1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 #include "opcode/mips.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_coff_flavour
:
124 case bfd_target_elf_flavour
:
126 /* This is traditional mips */
127 return (target_big_endian
128 ? "elf32-tradbigmips" : "elf32-tradlittlemips");
130 return (target_big_endian
131 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
132 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
140 /* The name of the readonly data section. */
141 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
143 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
145 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
147 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
151 /* This is the set of options which may be modified by the .set
152 pseudo-op. We use a struct so that .set push and .set pop are more
155 struct mips_set_options
157 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
158 if it has not been initialized. Changed by `.set mipsN', and the
159 -mipsN command line option, and the default CPU. */
161 /* Whether we are assembling for the mips16 processor. 0 if we are
162 not, 1 if we are, and -1 if the value has not been initialized.
163 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
164 -nomips16 command line options, and the default CPU. */
166 /* Non-zero if we should not reorder instructions. Changed by `.set
167 reorder' and `.set noreorder'. */
169 /* Non-zero if we should not permit the $at ($1) register to be used
170 in instructions. Changed by `.set at' and `.set noat'. */
172 /* Non-zero if we should warn when a macro instruction expands into
173 more than one machine instruction. Changed by `.set nomacro' and
175 int warn_about_macros
;
176 /* Non-zero if we should not move instructions. Changed by `.set
177 move', `.set volatile', `.set nomove', and `.set novolatile'. */
179 /* Non-zero if we should not optimize branches by moving the target
180 of the branch into the delay slot. Actually, we don't perform
181 this optimization anyhow. Changed by `.set bopt' and `.set
184 /* Non-zero if we should not autoextend mips16 instructions.
185 Changed by `.set autoextend' and `.set noautoextend'. */
189 /* This is the struct we use to hold the current set of options. Note
190 that we must set the isa and mips16 fields to -1 to indicate that
191 they have not been initialized. */
193 static struct mips_set_options mips_opts
= { -1, -1, 0, 0, 0, 0, 0, 0 };
195 /* These variables are filled in with the masks of registers used.
196 The object format code reads them and puts them in the appropriate
198 unsigned long mips_gprmask
;
199 unsigned long mips_cprmask
[4];
201 /* MIPS ISA we are using for this output file. */
202 static int file_mips_isa
;
204 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
205 static int mips_cpu
= -1;
207 /* The argument of the -mabi= flag. */
208 static char* mips_abi_string
= 0;
210 /* Wether we should mark the file EABI64 or EABI32. */
211 static int mips_eabi64
= 0;
213 /* If they asked for mips1 or mips2 and a cpu that is
214 mips3 or greater, then mark the object file 32BITMODE. */
215 static int mips_32bitmode
= 0;
217 /* True if -mgp32 was passed. */
218 static int mips_gp32
= 0;
220 /* Some ISA's have delay slots for instructions which read or write
221 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
222 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
223 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
224 delay slot in this ISA. The uses of this macro assume that any
225 ISA that has delay slots for one of these, has them for all. They
226 also assume that ISAs which don't have delays for these insns, don't
227 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
228 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
234 /* Return true if ISA supports 64 bit gp register instructions. */
235 #define ISA_HAS_64BIT_REGS(ISA) ( \
240 /* Whether the processor uses hardware interlocks to protect
241 reads from the HI and LO registers, and thus does not
242 require nops to be inserted.
244 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
245 -mcpu=FOO schedules for FOO, but still produces code that meets the
246 requirements of MIPS ISA I. For example, it won't generate any
247 FOO-specific instructions, and it will still assume that any
248 scheduling hazards described in MIPS ISA I are there, even if FOO
249 has interlocks. -mFOO gives GCC permission to generate code that
250 will only run on a FOO; it will generate FOO-specific instructions,
251 and assume interlocks provided by a FOO.
253 However, GAS currently doesn't make this distinction; before Jan 28
254 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
255 assumptions. The GCC driver passes these flags through to GAS, so
256 if GAS actually does anything that doesn't meet MIPS ISA I with
257 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
259 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
260 which seems senseless --- why generate code which will only run on
261 a FOO, but schedule for something else?
263 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
265 -- Jim Blandy <jimb@cygnus.com> */
267 #define hilo_interlocks (mips_cpu == CPU_R4010 \
270 /* Whether the processor uses hardware interlocks to protect reads
271 from the GPRs, and thus does not require nops to be inserted. */
272 #define gpr_interlocks \
273 (mips_opts.isa != 1 \
274 || mips_cpu == CPU_R3900)
276 /* As with other "interlocks" this is used by hardware that has FP
277 (co-processor) interlocks. */
278 /* Itbl support may require additional care here. */
279 #define cop_interlocks (mips_cpu == CPU_R4300 \
282 /* Is this a mfhi or mflo instruction? */
283 #define MF_HILO_INSN(PINFO) \
284 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
286 /* MIPS PIC level. */
290 /* Do not generate PIC code. */
293 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
294 not sure what it is supposed to do. */
297 /* Generate PIC code as in the SVR4 MIPS ABI. */
300 /* Generate PIC code without using a global offset table: the data
301 segment has a maximum size of 64K, all data references are off
302 the $gp register, and all text references are PC relative. This
303 is used on some embedded systems. */
307 static enum mips_pic_level mips_pic
;
309 /* 1 if we should generate 32 bit offsets from the GP register in
310 SVR4_PIC mode. Currently has no meaning in other modes. */
311 static int mips_big_got
;
313 /* 1 if trap instructions should used for overflow rather than break
315 static int mips_trap
;
317 /* 1 if double width floating point constants should not be constructed
318 by a assembling two single width halves into two single width floating
319 point registers which just happen to alias the double width destination
320 register. On some architectures this aliasing can be disabled by a bit
321 in the status register, and the setting of this bit cannot be determined
322 automatically at assemble time. */
323 static int mips_disable_float_construction
;
325 /* Non-zero if any .set noreorder directives were used. */
327 static int mips_any_noreorder
;
329 /* Non-zero if nops should be inserted when the register referenced in
330 an mfhi/mflo instruction is read in the next two instructions. */
331 static int mips_7000_hilo_fix
;
333 /* The size of the small data section. */
334 static unsigned int g_switch_value
= 8;
335 /* Whether the -G option was used. */
336 static int g_switch_seen
= 0;
341 /* If we can determine in advance that GP optimization won't be
342 possible, we can skip the relaxation stuff that tries to produce
343 GP-relative references. This makes delay slot optimization work
346 This function can only provide a guess, but it seems to work for
347 gcc output. It needs to guess right for gcc, otherwise gcc
348 will put what it thinks is a GP-relative instruction in a branch
351 I don't know if a fix is needed for the SVR4_PIC mode. I've only
352 fixed it for the non-PIC mode. KR 95/04/07 */
353 static int nopic_need_relax
PARAMS ((symbolS
*, int));
355 /* handle of the OPCODE hash table */
356 static struct hash_control
*op_hash
= NULL
;
358 /* The opcode hash table we use for the mips16. */
359 static struct hash_control
*mips16_op_hash
= NULL
;
361 /* This array holds the chars that always start a comment. If the
362 pre-processor is disabled, these aren't very useful */
363 const char comment_chars
[] = "#";
365 /* This array holds the chars that only start a comment at the beginning of
366 a line. If the line seems to have the form '# 123 filename'
367 .line and .file directives will appear in the pre-processed output */
368 /* Note that input_file.c hand checks for '#' at the beginning of the
369 first line of the input file. This is because the compiler outputs
370 #NO_APP at the beginning of its output. */
371 /* Also note that C style comments are always supported. */
372 const char line_comment_chars
[] = "#";
374 /* This array holds machine specific line separator characters. */
375 const char line_separator_chars
[] = ";";
377 /* Chars that can be used to separate mant from exp in floating point nums */
378 const char EXP_CHARS
[] = "eE";
380 /* Chars that mean this number is a floating point constant */
383 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
385 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
386 changed in read.c . Ideally it shouldn't have to know about it at all,
387 but nothing is ideal around here.
390 static char *insn_error
;
392 static int auto_align
= 1;
394 /* When outputting SVR4 PIC code, the assembler needs to know the
395 offset in the stack frame from which to restore the $gp register.
396 This is set by the .cprestore pseudo-op, and saved in this
398 static offsetT mips_cprestore_offset
= -1;
400 /* This is the register which holds the stack frame, as set by the
401 .frame pseudo-op. This is needed to implement .cprestore. */
402 static int mips_frame_reg
= SP
;
404 /* To output NOP instructions correctly, we need to keep information
405 about the previous two instructions. */
407 /* Whether we are optimizing. The default value of 2 means to remove
408 unneeded NOPs and swap branch instructions when possible. A value
409 of 1 means to not swap branches. A value of 0 means to always
411 static int mips_optimize
= 2;
413 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
414 equivalent to seeing no -g option at all. */
415 static int mips_debug
= 0;
417 /* The previous instruction. */
418 static struct mips_cl_insn prev_insn
;
420 /* The instruction before prev_insn. */
421 static struct mips_cl_insn prev_prev_insn
;
423 /* If we don't want information for prev_insn or prev_prev_insn, we
424 point the insn_mo field at this dummy integer. */
425 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
427 /* Non-zero if prev_insn is valid. */
428 static int prev_insn_valid
;
430 /* The frag for the previous instruction. */
431 static struct frag
*prev_insn_frag
;
433 /* The offset into prev_insn_frag for the previous instruction. */
434 static long prev_insn_where
;
436 /* The reloc type for the previous instruction, if any. */
437 static bfd_reloc_code_real_type prev_insn_reloc_type
;
439 /* The reloc for the previous instruction, if any. */
440 static fixS
*prev_insn_fixp
;
442 /* Non-zero if the previous instruction was in a delay slot. */
443 static int prev_insn_is_delay_slot
;
445 /* Non-zero if the previous instruction was in a .set noreorder. */
446 static int prev_insn_unreordered
;
448 /* Non-zero if the previous instruction uses an extend opcode (if
450 static int prev_insn_extended
;
452 /* Non-zero if the previous previous instruction was in a .set
454 static int prev_prev_insn_unreordered
;
456 /* If this is set, it points to a frag holding nop instructions which
457 were inserted before the start of a noreorder section. If those
458 nops turn out to be unnecessary, the size of the frag can be
460 static fragS
*prev_nop_frag
;
462 /* The number of nop instructions we created in prev_nop_frag. */
463 static int prev_nop_frag_holds
;
465 /* The number of nop instructions that we know we need in
467 static int prev_nop_frag_required
;
469 /* The number of instructions we've seen since prev_nop_frag. */
470 static int prev_nop_frag_since
;
472 /* For ECOFF and ELF, relocations against symbols are done in two
473 parts, with a HI relocation and a LO relocation. Each relocation
474 has only 16 bits of space to store an addend. This means that in
475 order for the linker to handle carries correctly, it must be able
476 to locate both the HI and the LO relocation. This means that the
477 relocations must appear in order in the relocation table.
479 In order to implement this, we keep track of each unmatched HI
480 relocation. We then sort them so that they immediately precede the
481 corresponding LO relocation. */
486 struct mips_hi_fixup
*next
;
489 /* The section this fixup is in. */
493 /* The list of unmatched HI relocs. */
495 static struct mips_hi_fixup
*mips_hi_fixup_list
;
497 /* Map normal MIPS register numbers to mips16 register numbers. */
499 #define X ILLEGAL_REG
500 static const int mips32_to_16_reg_map
[] =
502 X
, X
, 2, 3, 4, 5, 6, 7,
503 X
, X
, X
, X
, X
, X
, X
, X
,
504 0, 1, X
, X
, X
, X
, X
, X
,
505 X
, X
, X
, X
, X
, X
, X
, X
509 /* Map mips16 register numbers to normal MIPS register numbers. */
511 static const unsigned int mips16_to_32_reg_map
[] =
513 16, 17, 2, 3, 4, 5, 6, 7
516 /* Since the MIPS does not have multiple forms of PC relative
517 instructions, we do not have to do relaxing as is done on other
518 platforms. However, we do have to handle GP relative addressing
519 correctly, which turns out to be a similar problem.
521 Every macro that refers to a symbol can occur in (at least) two
522 forms, one with GP relative addressing and one without. For
523 example, loading a global variable into a register generally uses
524 a macro instruction like this:
526 If i can be addressed off the GP register (this is true if it is in
527 the .sbss or .sdata section, or if it is known to be smaller than
528 the -G argument) this will generate the following instruction:
530 This instruction will use a GPREL reloc. If i can not be addressed
531 off the GP register, the following instruction sequence will be used:
534 In this case the first instruction will have a HI16 reloc, and the
535 second reloc will have a LO16 reloc. Both relocs will be against
538 The issue here is that we may not know whether i is GP addressable
539 until after we see the instruction that uses it. Therefore, we
540 want to be able to choose the final instruction sequence only at
541 the end of the assembly. This is similar to the way other
542 platforms choose the size of a PC relative instruction only at the
545 When generating position independent code we do not use GP
546 addressing in quite the same way, but the issue still arises as
547 external symbols and local symbols must be handled differently.
549 We handle these issues by actually generating both possible
550 instruction sequences. The longer one is put in a frag_var with
551 type rs_machine_dependent. We encode what to do with the frag in
552 the subtype field. We encode (1) the number of existing bytes to
553 replace, (2) the number of new bytes to use, (3) the offset from
554 the start of the existing bytes to the first reloc we must generate
555 (that is, the offset is applied from the start of the existing
556 bytes after they are replaced by the new bytes, if any), (4) the
557 offset from the start of the existing bytes to the second reloc,
558 (5) whether a third reloc is needed (the third reloc is always four
559 bytes after the second reloc), and (6) whether to warn if this
560 variant is used (this is sometimes needed if .set nomacro or .set
561 noat is in effect). All these numbers are reasonably small.
563 Generating two instruction sequences must be handled carefully to
564 ensure that delay slots are handled correctly. Fortunately, there
565 are a limited number of cases. When the second instruction
566 sequence is generated, append_insn is directed to maintain the
567 existing delay slot information, so it continues to apply to any
568 code after the second instruction sequence. This means that the
569 second instruction sequence must not impose any requirements not
570 required by the first instruction sequence.
572 These variant frags are then handled in functions called by the
573 machine independent code. md_estimate_size_before_relax returns
574 the final size of the frag. md_convert_frag sets up the final form
575 of the frag. tc_gen_reloc adjust the first reloc and adds a second
577 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
581 | (((reloc1) + 64) << 9) \
582 | (((reloc2) + 64) << 2) \
583 | ((reloc3) ? (1 << 1) : 0) \
585 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
586 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
587 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
588 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
589 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
590 #define RELAX_WARN(i) ((i) & 1)
592 /* For mips16 code, we use an entirely different form of relaxation.
593 mips16 supports two versions of most instructions which take
594 immediate values: a small one which takes some small value, and a
595 larger one which takes a 16 bit value. Since branches also follow
596 this pattern, relaxing these values is required.
598 We can assemble both mips16 and normal MIPS code in a single
599 object. Therefore, we need to support this type of relaxation at
600 the same time that we support the relaxation described above. We
601 use the high bit of the subtype field to distinguish these cases.
603 The information we store for this type of relaxation is the
604 argument code found in the opcode file for this relocation, whether
605 the user explicitly requested a small or extended form, and whether
606 the relocation is in a jump or jal delay slot. That tells us the
607 size of the value, and how it should be stored. We also store
608 whether the fragment is considered to be extended or not. We also
609 store whether this is known to be a branch to a different section,
610 whether we have tried to relax this frag yet, and whether we have
611 ever extended a PC relative fragment because of a shift count. */
612 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
615 | ((small) ? 0x100 : 0) \
616 | ((ext) ? 0x200 : 0) \
617 | ((dslot) ? 0x400 : 0) \
618 | ((jal_dslot) ? 0x800 : 0))
619 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
620 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
621 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
622 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
623 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
624 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
625 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
626 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
627 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
628 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
629 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
630 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
632 /* Prototypes for static functions. */
635 #define internalError() \
636 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
638 #define internalError() as_fatal (_("MIPS internal Error"));
641 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
643 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
644 unsigned int reg
, enum mips_regclass
class));
645 static int reg_needs_delay
PARAMS ((unsigned int));
646 static void mips16_mark_labels
PARAMS ((void));
647 static void append_insn
PARAMS ((char *place
,
648 struct mips_cl_insn
* ip
,
650 bfd_reloc_code_real_type r
,
652 static void mips_no_prev_insn
PARAMS ((int));
653 static void mips_emit_delays
PARAMS ((boolean
));
655 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
656 const char *name
, const char *fmt
,
659 static void macro_build ();
661 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
662 const char *, const char *,
664 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
665 expressionS
* ep
, int regnum
));
666 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
667 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
669 static void load_register
PARAMS ((int *, int, expressionS
*, int));
670 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
671 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
672 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
673 #ifdef LOSING_COMPILER
674 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
676 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
677 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
678 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
679 boolean
, boolean
, unsigned long *,
680 boolean
*, unsigned short *));
681 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
682 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
683 static symbolS
*get_symbol
PARAMS ((void));
684 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
685 static void s_align
PARAMS ((int));
686 static void s_change_sec
PARAMS ((int));
687 static void s_cons
PARAMS ((int));
688 static void s_float_cons
PARAMS ((int));
689 static void s_mips_globl
PARAMS ((int));
690 static void s_option
PARAMS ((int));
691 static void s_mipsset
PARAMS ((int));
692 static void s_abicalls
PARAMS ((int));
693 static void s_cpload
PARAMS ((int));
694 static void s_cprestore
PARAMS ((int));
695 static void s_gpword
PARAMS ((int));
696 static void s_cpadd
PARAMS ((int));
697 static void s_insn
PARAMS ((int));
698 static void md_obj_begin
PARAMS ((void));
699 static void md_obj_end
PARAMS ((void));
700 static long get_number
PARAMS ((void));
701 static void s_mips_ent
PARAMS ((int));
702 static void s_mips_end
PARAMS ((int));
703 static void s_mips_frame
PARAMS ((int));
704 static void s_mips_mask
PARAMS ((int));
705 static void s_mips_stab
PARAMS ((int));
706 static void s_mips_weakext
PARAMS ((int));
707 static void s_file
PARAMS ((int));
708 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
709 static char *mips_cpu_to_str
PARAMS ((int));
711 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
715 The following pseudo-ops from the Kane and Heinrich MIPS book
716 should be defined here, but are currently unsupported: .alias,
717 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
719 The following pseudo-ops from the Kane and Heinrich MIPS book are
720 specific to the type of debugging information being generated, and
721 should be defined by the object format: .aent, .begin, .bend,
722 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
725 The following pseudo-ops from the Kane and Heinrich MIPS book are
726 not MIPS CPU specific, but are also not specific to the object file
727 format. This file is probably the best place to define them, but
728 they are not currently supported: .asm0, .endr, .lab, .repeat,
731 static const pseudo_typeS mips_pseudo_table
[] =
733 /* MIPS specific pseudo-ops. */
734 {"option", s_option
, 0},
735 {"set", s_mipsset
, 0},
736 {"rdata", s_change_sec
, 'r'},
737 {"sdata", s_change_sec
, 's'},
738 {"livereg", s_ignore
, 0},
739 {"abicalls", s_abicalls
, 0},
740 {"cpload", s_cpload
, 0},
741 {"cprestore", s_cprestore
, 0},
742 {"gpword", s_gpword
, 0},
743 {"cpadd", s_cpadd
, 0},
746 /* Relatively generic pseudo-ops that happen to be used on MIPS
748 {"asciiz", stringer
, 1},
749 {"bss", s_change_sec
, 'b'},
752 {"dword", s_cons
, 3},
753 {"weakext", s_mips_weakext
, 0},
755 /* These pseudo-ops are defined in read.c, but must be overridden
756 here for one reason or another. */
757 {"align", s_align
, 0},
759 {"data", s_change_sec
, 'd'},
760 {"double", s_float_cons
, 'd'},
761 {"float", s_float_cons
, 'f'},
762 {"globl", s_mips_globl
, 0},
763 {"global", s_mips_globl
, 0},
764 {"hword", s_cons
, 1},
769 {"short", s_cons
, 1},
770 {"single", s_float_cons
, 'f'},
771 {"stabn", s_mips_stab
, 'n'},
772 {"text", s_change_sec
, 't'},
777 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
778 /* These pseudo-ops should be defined by the object file format.
779 However, a.out doesn't support them, so we have versions here. */
780 {"aent", s_mips_ent
, 1},
781 {"bgnb", s_ignore
, 0},
782 {"end", s_mips_end
, 0},
783 {"endb", s_ignore
, 0},
784 {"ent", s_mips_ent
, 0},
786 {"fmask", s_mips_mask
, 'F'},
787 {"frame", s_mips_frame
, 0},
788 {"loc", s_ignore
, 0},
789 {"mask", s_mips_mask
, 'R'},
790 {"verstamp", s_ignore
, 0},
794 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
799 pop_insert (mips_pseudo_table
);
800 if (! ECOFF_DEBUGGING
)
801 pop_insert (mips_nonecoff_pseudo_table
);
804 /* Symbols labelling the current insn. */
806 struct insn_label_list
808 struct insn_label_list
*next
;
812 static struct insn_label_list
*insn_labels
;
813 static struct insn_label_list
*free_insn_labels
;
815 static void mips_clear_insn_labels
PARAMS ((void));
818 mips_clear_insn_labels ()
820 register struct insn_label_list
**pl
;
822 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
828 static char *expr_end
;
830 /* Expressions which appear in instructions. These are set by
833 static expressionS imm_expr
;
834 static expressionS offset_expr
;
836 /* Relocs associated with imm_expr and offset_expr. */
838 static bfd_reloc_code_real_type imm_reloc
;
839 static bfd_reloc_code_real_type offset_reloc
;
841 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
843 static boolean imm_unmatched_hi
;
845 /* These are set by mips16_ip if an explicit extension is used. */
847 static boolean mips16_small
, mips16_ext
;
849 #ifdef MIPS_STABS_ELF
850 /* The pdr segment for per procedure frame/regmask info */
856 mips_cpu_to_str (cpu
)
862 case CPU_R2000
: return "R2000";
863 case CPU_R3000
: return "R3000";
864 case CPU_R3900
: return "R3900";
865 case CPU_R4000
: return "R4000";
866 case CPU_R4010
: return "R4010";
867 case CPU_VR4100
: return "VR4100";
868 case CPU_R4111
: return "R4111";
869 case CPU_R4300
: return "R4300";
870 case CPU_R4400
: return "R4400";
871 case CPU_R4600
: return "R4600";
872 case CPU_R4650
: return "R4650";
873 case CPU_R5000
: return "R5000";
874 case CPU_R6000
: return "R6000";
875 case CPU_R8000
: return "R8000";
876 case CPU_R10000
: return "R10000";
877 case CPU_4K
: return "4K";
879 sprintf (s
, "%d", cpu
);
884 /* This function is called once, at assembler startup time. It should
885 set up all the tables, etc. that the MD part of the assembler will need. */
891 register const char *retval
= NULL
;
896 int mips_isa_from_cpu
;
898 /* GP relative stuff not working for PE */
899 if (strncmp (TARGET_OS
, "pe", 2) == 0
900 && g_switch_value
!= 0)
903 as_bad (_("-G not supported in this configuration."));
908 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
910 a
= xmalloc (sizeof TARGET_CPU
);
911 strcpy (a
, TARGET_CPU
);
912 a
[(sizeof TARGET_CPU
) - 3] = '\0';
918 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
919 just the generic 'mips', in which case set mips_cpu based
920 on the given ISA, if any. */
922 if (strcmp (cpu
, "mips") == 0)
924 if (mips_opts
.isa
< 0)
925 mips_cpu
= CPU_R3000
;
927 else if (mips_opts
.isa
== 2)
928 mips_cpu
= CPU_R6000
;
930 else if (mips_opts
.isa
== 3)
931 mips_cpu
= CPU_R4000
;
933 else if (mips_opts
.isa
== 4)
934 mips_cpu
= CPU_R8000
;
937 mips_cpu
= CPU_R3000
;
940 else if (strcmp (cpu
, "r3900") == 0
941 || strcmp (cpu
, "mipstx39") == 0
943 mips_cpu
= CPU_R3900
;
945 else if (strcmp (cpu
, "r6000") == 0
946 || strcmp (cpu
, "mips2") == 0)
947 mips_cpu
= CPU_R6000
;
949 else if (strcmp (cpu
, "mips64") == 0
950 || strcmp (cpu
, "r4000") == 0
951 || strcmp (cpu
, "mips3") == 0)
952 mips_cpu
= CPU_R4000
;
954 else if (strcmp (cpu
, "r4400") == 0)
955 mips_cpu
= CPU_R4400
;
957 else if (strcmp (cpu
, "mips64orion") == 0
958 || strcmp (cpu
, "r4600") == 0)
959 mips_cpu
= CPU_R4600
;
961 else if (strcmp (cpu
, "r4650") == 0)
962 mips_cpu
= CPU_R4650
;
964 else if (strcmp (cpu
, "mips64vr4300") == 0)
965 mips_cpu
= CPU_R4300
;
967 else if (strcmp (cpu
, "mips64vr4111") == 0)
968 mips_cpu
= CPU_R4111
;
970 else if (strcmp (cpu
, "mips64vr4100") == 0)
971 mips_cpu
= CPU_VR4100
;
973 else if (strcmp (cpu
, "r4010") == 0)
974 mips_cpu
= CPU_R4010
;
976 else if (strcmp (cpu
, "4Kc") == 0
977 || strcmp (cpu
, "4Kp") == 0
978 || strcmp (cpu
, "4Km") == 0)
981 else if (strcmp (cpu
, "r5000") == 0
982 || strcmp (cpu
, "mips64vr5000") == 0)
983 mips_cpu
= CPU_R5000
;
985 else if (strcmp (cpu
, "r8000") == 0
986 || strcmp (cpu
, "mips4") == 0)
987 mips_cpu
= CPU_R8000
;
989 else if (strcmp (cpu
, "r10000") == 0)
990 mips_cpu
= CPU_R10000
;
992 else if (strcmp (cpu
, "mips16") == 0)
993 mips_cpu
= 0; /* FIXME */
996 mips_cpu
= CPU_R3000
;
999 if (mips_cpu
== CPU_R3000
1000 || mips_cpu
== CPU_R3900
)
1001 mips_isa_from_cpu
= 1;
1003 else if (mips_cpu
== CPU_R6000
1004 || mips_cpu
== CPU_R4010
)
1005 mips_isa_from_cpu
= 2;
1007 else if (mips_cpu
== CPU_R4000
1008 || mips_cpu
== CPU_VR4100
1009 || mips_cpu
== CPU_R4111
1010 || mips_cpu
== CPU_R4400
1011 || mips_cpu
== CPU_R4300
1012 || mips_cpu
== CPU_R4600
1013 || mips_cpu
== CPU_R4650
)
1014 mips_isa_from_cpu
= 3;
1016 else if (mips_cpu
== CPU_R5000
1017 || mips_cpu
== CPU_R8000
1018 || mips_cpu
== CPU_R10000
)
1019 mips_isa_from_cpu
= 4;
1022 mips_isa_from_cpu
= -1;
1024 if (mips_opts
.isa
== -1)
1026 if (mips_isa_from_cpu
!= -1)
1027 mips_opts
.isa
= mips_isa_from_cpu
;
1032 if (mips_opts
.mips16
< 0)
1034 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
1035 mips_opts
.mips16
= 1;
1037 mips_opts
.mips16
= 0;
1040 /* End of TARGET_CPU processing, get rid of malloced memory
1049 if (mips_opts
.isa
== 1 && mips_trap
)
1050 as_bad (_("trap exception not supported at ISA 1"));
1052 /* Set the EABI kind based on the ISA before the user gets
1053 to change the ISA with directives. This isn't really
1054 the best, but then neither is basing the abi on the isa. */
1055 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1057 && 0 == strcmp (mips_abi_string
,"eabi"))
1060 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1062 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1064 /* If they asked for mips1 or mips2 and a cpu that is
1065 mips3 or greater, then mark the object file 32BITMODE. */
1066 if (mips_isa_from_cpu
!= -1
1067 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1068 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1073 switch (mips_opts
.isa
)
1076 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, CPU_R3000
);
1079 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, CPU_R6000
);
1082 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, CPU_R4000
);
1085 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, CPU_R8000
);
1091 as_warn (_("Could not set architecture and machine"));
1093 file_mips_isa
= mips_opts
.isa
;
1095 op_hash
= hash_new ();
1097 for (i
= 0; i
< NUMOPCODES
;)
1099 const char *name
= mips_opcodes
[i
].name
;
1101 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1104 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1105 mips_opcodes
[i
].name
, retval
);
1106 /* Probably a memory allocation problem? Give up now. */
1107 as_fatal (_("Broken assembler. No assembly attempted."));
1111 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1113 if (!validate_mips_insn (&mips_opcodes
[i
]))
1118 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1121 mips16_op_hash
= hash_new ();
1124 while (i
< bfd_mips16_num_opcodes
)
1126 const char *name
= mips16_opcodes
[i
].name
;
1128 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1130 as_fatal (_("internal: can't hash `%s': %s"),
1131 mips16_opcodes
[i
].name
, retval
);
1134 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1135 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1136 != mips16_opcodes
[i
].match
))
1138 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1139 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1144 while (i
< bfd_mips16_num_opcodes
1145 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1149 as_fatal (_("Broken assembler. No assembly attempted."));
1151 /* We add all the general register names to the symbol table. This
1152 helps us detect invalid uses of them. */
1153 for (i
= 0; i
< 32; i
++)
1157 sprintf (buf
, "$%d", i
);
1158 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1159 &zero_address_frag
));
1161 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1162 &zero_address_frag
));
1163 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1164 &zero_address_frag
));
1165 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1166 &zero_address_frag
));
1167 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1168 &zero_address_frag
));
1169 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1170 &zero_address_frag
));
1171 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1172 &zero_address_frag
));
1173 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1174 &zero_address_frag
));
1176 mips_no_prev_insn (false);
1179 mips_cprmask
[0] = 0;
1180 mips_cprmask
[1] = 0;
1181 mips_cprmask
[2] = 0;
1182 mips_cprmask
[3] = 0;
1184 /* set the default alignment for the text section (2**2) */
1185 record_alignment (text_section
, 2);
1187 if (USE_GLOBAL_POINTER_OPT
)
1188 bfd_set_gp_size (stdoutput
, g_switch_value
);
1190 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1192 /* On a native system, sections must be aligned to 16 byte
1193 boundaries. When configured for an embedded ELF target, we
1195 if (strcmp (TARGET_OS
, "elf") != 0)
1197 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1198 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1199 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1202 /* Create a .reginfo section for register masks and a .mdebug
1203 section for debugging information. */
1211 subseg
= now_subseg
;
1213 /* The ABI says this section should be loaded so that the
1214 running program can access it. However, we don't load it
1215 if we are configured for an embedded target */
1216 flags
= SEC_READONLY
| SEC_DATA
;
1217 if (strcmp (TARGET_OS
, "elf") != 0)
1218 flags
|= SEC_ALLOC
| SEC_LOAD
;
1222 sec
= subseg_new (".reginfo", (subsegT
) 0);
1224 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1225 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1228 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1233 /* The 64-bit ABI uses a .MIPS.options section rather than
1234 .reginfo section. */
1235 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1236 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1237 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1240 /* Set up the option header. */
1242 Elf_Internal_Options opthdr
;
1245 opthdr
.kind
= ODK_REGINFO
;
1246 opthdr
.size
= (sizeof (Elf_External_Options
)
1247 + sizeof (Elf64_External_RegInfo
));
1250 f
= frag_more (sizeof (Elf_External_Options
));
1251 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1252 (Elf_External_Options
*) f
);
1254 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1259 if (ECOFF_DEBUGGING
)
1261 sec
= subseg_new (".mdebug", (subsegT
) 0);
1262 (void) bfd_set_section_flags (stdoutput
, sec
,
1263 SEC_HAS_CONTENTS
| SEC_READONLY
);
1264 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1267 #ifdef MIPS_STABS_ELF
1268 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1269 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1270 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1271 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1274 subseg_set (seg
, subseg
);
1278 if (! ECOFF_DEBUGGING
)
1285 if (! ECOFF_DEBUGGING
)
1293 struct mips_cl_insn insn
;
1295 imm_expr
.X_op
= O_absent
;
1296 imm_reloc
= BFD_RELOC_UNUSED
;
1297 imm_unmatched_hi
= false;
1298 offset_expr
.X_op
= O_absent
;
1299 offset_reloc
= BFD_RELOC_UNUSED
;
1301 if (mips_opts
.mips16
)
1302 mips16_ip (str
, &insn
);
1305 mips_ip (str
, &insn
);
1306 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1307 str
, insn
.insn_opcode
));
1312 as_bad ("%s `%s'", insn_error
, str
);
1316 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1318 if (mips_opts
.mips16
)
1319 mips16_macro (&insn
);
1325 if (imm_expr
.X_op
!= O_absent
)
1326 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1328 else if (offset_expr
.X_op
!= O_absent
)
1329 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1331 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1335 /* See whether instruction IP reads register REG. CLASS is the type
1339 insn_uses_reg (ip
, reg
, class)
1340 struct mips_cl_insn
*ip
;
1342 enum mips_regclass
class;
1344 if (class == MIPS16_REG
)
1346 assert (mips_opts
.mips16
);
1347 reg
= mips16_to_32_reg_map
[reg
];
1348 class = MIPS_GR_REG
;
1351 /* Don't report on general register 0, since it never changes. */
1352 if (class == MIPS_GR_REG
&& reg
== 0)
1355 if (class == MIPS_FP_REG
)
1357 assert (! mips_opts
.mips16
);
1358 /* If we are called with either $f0 or $f1, we must check $f0.
1359 This is not optimal, because it will introduce an unnecessary
1360 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1361 need to distinguish reading both $f0 and $f1 or just one of
1362 them. Note that we don't have to check the other way,
1363 because there is no instruction that sets both $f0 and $f1
1364 and requires a delay. */
1365 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1366 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1367 == (reg
&~ (unsigned) 1)))
1369 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1370 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1371 == (reg
&~ (unsigned) 1)))
1374 else if (! mips_opts
.mips16
)
1376 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1377 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1379 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1380 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1385 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1386 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1387 & MIPS16OP_MASK_RX
)]
1390 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1391 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1392 & MIPS16OP_MASK_RY
)]
1395 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1396 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1397 & MIPS16OP_MASK_MOVE32Z
)]
1400 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1402 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1404 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1406 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1407 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1408 & MIPS16OP_MASK_REGR32
) == reg
)
1415 /* This function returns true if modifying a register requires a
1419 reg_needs_delay (reg
)
1422 unsigned long prev_pinfo
;
1424 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1425 if (! mips_opts
.noreorder
1426 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1427 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1428 || (! gpr_interlocks
1429 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1431 /* A load from a coprocessor or from memory. All load
1432 delays delay the use of general register rt for one
1433 instruction on the r3000. The r6000 and r4000 use
1435 /* Itbl support may require additional care here. */
1436 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1437 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1444 /* Mark instruction labels in mips16 mode. This permits the linker to
1445 handle them specially, such as generating jalx instructions when
1446 needed. We also make them odd for the duration of the assembly, in
1447 order to generate the right sort of code. We will make them even
1448 in the adjust_symtab routine, while leaving them marked. This is
1449 convenient for the debugger and the disassembler. The linker knows
1450 to make them odd again. */
1453 mips16_mark_labels ()
1455 if (mips_opts
.mips16
)
1457 struct insn_label_list
*l
;
1459 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1462 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1463 S_SET_OTHER (l
->label
, STO_MIPS16
);
1465 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1466 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1471 /* Output an instruction. PLACE is where to put the instruction; if
1472 it is NULL, this uses frag_more to get room. IP is the instruction
1473 information. ADDRESS_EXPR is an operand of the instruction to be
1474 used with RELOC_TYPE. */
1477 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1479 struct mips_cl_insn
*ip
;
1480 expressionS
*address_expr
;
1481 bfd_reloc_code_real_type reloc_type
;
1482 boolean unmatched_hi
;
1484 register unsigned long prev_pinfo
, pinfo
;
1489 /* Mark instruction labels in mips16 mode. */
1490 if (mips_opts
.mips16
)
1491 mips16_mark_labels ();
1493 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1494 pinfo
= ip
->insn_mo
->pinfo
;
1496 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1500 /* If the previous insn required any delay slots, see if we need
1501 to insert a NOP or two. There are eight kinds of possible
1502 hazards, of which an instruction can have at most one type.
1503 (1) a load from memory delay
1504 (2) a load from a coprocessor delay
1505 (3) an unconditional branch delay
1506 (4) a conditional branch delay
1507 (5) a move to coprocessor register delay
1508 (6) a load coprocessor register from memory delay
1509 (7) a coprocessor condition code delay
1510 (8) a HI/LO special register delay
1512 There are a lot of optimizations we could do that we don't.
1513 In particular, we do not, in general, reorder instructions.
1514 If you use gcc with optimization, it will reorder
1515 instructions and generally do much more optimization then we
1516 do here; repeating all that work in the assembler would only
1517 benefit hand written assembly code, and does not seem worth
1520 /* This is how a NOP is emitted. */
1521 #define emit_nop() \
1523 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1524 : md_number_to_chars (frag_more (4), 0, 4))
1526 /* The previous insn might require a delay slot, depending upon
1527 the contents of the current insn. */
1528 if (! mips_opts
.mips16
1529 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1530 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1531 && ! cop_interlocks
)
1532 || (! gpr_interlocks
1533 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1535 /* A load from a coprocessor or from memory. All load
1536 delays delay the use of general register rt for one
1537 instruction on the r3000. The r6000 and r4000 use
1539 /* Itbl support may require additional care here. */
1540 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1541 if (mips_optimize
== 0
1542 || insn_uses_reg (ip
,
1543 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1548 else if (! mips_opts
.mips16
1549 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1550 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1551 && ! cop_interlocks
)
1552 || (mips_opts
.isa
== 1
1553 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1555 /* A generic coprocessor delay. The previous instruction
1556 modified a coprocessor general or control register. If
1557 it modified a control register, we need to avoid any
1558 coprocessor instruction (this is probably not always
1559 required, but it sometimes is). If it modified a general
1560 register, we avoid using that register.
1562 On the r6000 and r4000 loading a coprocessor register
1563 from memory is interlocked, and does not require a delay.
1565 This case is not handled very well. There is no special
1566 knowledge of CP0 handling, and the coprocessors other
1567 than the floating point unit are not distinguished at
1569 /* Itbl support may require additional care here. FIXME!
1570 Need to modify this to include knowledge about
1571 user specified delays! */
1572 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1574 if (mips_optimize
== 0
1575 || insn_uses_reg (ip
,
1576 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1581 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1583 if (mips_optimize
== 0
1584 || insn_uses_reg (ip
,
1585 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1592 /* We don't know exactly what the previous instruction
1593 does. If the current instruction uses a coprocessor
1594 register, we must insert a NOP. If previous
1595 instruction may set the condition codes, and the
1596 current instruction uses them, we must insert two
1598 /* Itbl support may require additional care here. */
1599 if (mips_optimize
== 0
1600 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1601 && (pinfo
& INSN_READ_COND_CODE
)))
1603 else if (pinfo
& INSN_COP
)
1607 else if (! mips_opts
.mips16
1608 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1609 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1610 && ! cop_interlocks
)
1612 /* The previous instruction sets the coprocessor condition
1613 codes, but does not require a general coprocessor delay
1614 (this means it is a floating point comparison
1615 instruction). If this instruction uses the condition
1616 codes, we need to insert a single NOP. */
1617 /* Itbl support may require additional care here. */
1618 if (mips_optimize
== 0
1619 || (pinfo
& INSN_READ_COND_CODE
))
1623 /* If we're fixing up mfhi/mflo for the r7000 and the
1624 previous insn was an mfhi/mflo and the current insn
1625 reads the register that the mfhi/mflo wrote to, then
1628 else if (mips_7000_hilo_fix
1629 && MF_HILO_INSN (prev_pinfo
)
1630 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1638 /* If we're fixing up mfhi/mflo for the r7000 and the
1639 2nd previous insn was an mfhi/mflo and the current insn
1640 reads the register that the mfhi/mflo wrote to, then
1643 else if (mips_7000_hilo_fix
1644 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1645 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1653 else if (prev_pinfo
& INSN_READ_LO
)
1655 /* The previous instruction reads the LO register; if the
1656 current instruction writes to the LO register, we must
1657 insert two NOPS. Some newer processors have interlocks.
1658 Also the tx39's multiply instructions can be exectuted
1659 immediatly after a read from HI/LO (without the delay),
1660 though the tx39's divide insns still do require the
1662 if (! (hilo_interlocks
1663 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1664 && (mips_optimize
== 0
1665 || (pinfo
& INSN_WRITE_LO
)))
1667 /* Most mips16 branch insns don't have a delay slot.
1668 If a read from LO is immediately followed by a branch
1669 to a write to LO we have a read followed by a write
1670 less than 2 insns away. We assume the target of
1671 a branch might be a write to LO, and insert a nop
1672 between a read and an immediately following branch. */
1673 else if (mips_opts
.mips16
1674 && (mips_optimize
== 0
1675 || (pinfo
& MIPS16_INSN_BRANCH
)))
1678 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1680 /* The previous instruction reads the HI register; if the
1681 current instruction writes to the HI register, we must
1682 insert a NOP. Some newer processors have interlocks.
1683 Also the note tx39's multiply above. */
1684 if (! (hilo_interlocks
1685 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1686 && (mips_optimize
== 0
1687 || (pinfo
& INSN_WRITE_HI
)))
1689 /* Most mips16 branch insns don't have a delay slot.
1690 If a read from HI is immediately followed by a branch
1691 to a write to HI we have a read followed by a write
1692 less than 2 insns away. We assume the target of
1693 a branch might be a write to HI, and insert a nop
1694 between a read and an immediately following branch. */
1695 else if (mips_opts
.mips16
1696 && (mips_optimize
== 0
1697 || (pinfo
& MIPS16_INSN_BRANCH
)))
1701 /* If the previous instruction was in a noreorder section, then
1702 we don't want to insert the nop after all. */
1703 /* Itbl support may require additional care here. */
1704 if (prev_insn_unreordered
)
1707 /* There are two cases which require two intervening
1708 instructions: 1) setting the condition codes using a move to
1709 coprocessor instruction which requires a general coprocessor
1710 delay and then reading the condition codes 2) reading the HI
1711 or LO register and then writing to it (except on processors
1712 which have interlocks). If we are not already emitting a NOP
1713 instruction, we must check for these cases compared to the
1714 instruction previous to the previous instruction. */
1715 if ((! mips_opts
.mips16
1716 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1717 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1718 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1719 && (pinfo
& INSN_READ_COND_CODE
)
1720 && ! cop_interlocks
)
1721 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1722 && (pinfo
& INSN_WRITE_LO
)
1723 && ! (hilo_interlocks
1724 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1725 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1726 && (pinfo
& INSN_WRITE_HI
)
1727 && ! (hilo_interlocks
1728 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1733 if (prev_prev_insn_unreordered
)
1736 if (prev_prev_nop
&& nops
== 0)
1739 /* If we are being given a nop instruction, don't bother with
1740 one of the nops we would otherwise output. This will only
1741 happen when a nop instruction is used with mips_optimize set
1744 && ! mips_opts
.noreorder
1745 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1748 /* Now emit the right number of NOP instructions. */
1749 if (nops
> 0 && ! mips_opts
.noreorder
)
1752 unsigned long old_frag_offset
;
1754 struct insn_label_list
*l
;
1756 old_frag
= frag_now
;
1757 old_frag_offset
= frag_now_fix ();
1759 for (i
= 0; i
< nops
; i
++)
1764 listing_prev_line ();
1765 /* We may be at the start of a variant frag. In case we
1766 are, make sure there is enough space for the frag
1767 after the frags created by listing_prev_line. The
1768 argument to frag_grow here must be at least as large
1769 as the argument to all other calls to frag_grow in
1770 this file. We don't have to worry about being in the
1771 middle of a variant frag, because the variants insert
1772 all needed nop instructions themselves. */
1776 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1778 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1779 symbol_set_frag (l
->label
, frag_now
);
1780 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1781 /* mips16 text labels are stored as odd. */
1782 if (mips_opts
.mips16
)
1783 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1786 #ifndef NO_ECOFF_DEBUGGING
1787 if (ECOFF_DEBUGGING
)
1788 ecoff_fix_loc (old_frag
, old_frag_offset
);
1791 else if (prev_nop_frag
!= NULL
)
1793 /* We have a frag holding nops we may be able to remove. If
1794 we don't need any nops, we can decrease the size of
1795 prev_nop_frag by the size of one instruction. If we do
1796 need some nops, we count them in prev_nops_required. */
1797 if (prev_nop_frag_since
== 0)
1801 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1802 --prev_nop_frag_holds
;
1805 prev_nop_frag_required
+= nops
;
1809 if (prev_prev_nop
== 0)
1811 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1812 --prev_nop_frag_holds
;
1815 ++prev_nop_frag_required
;
1818 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1819 prev_nop_frag
= NULL
;
1821 ++prev_nop_frag_since
;
1823 /* Sanity check: by the time we reach the second instruction
1824 after prev_nop_frag, we should have used up all the nops
1825 one way or another. */
1826 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1830 if (reloc_type
> BFD_RELOC_UNUSED
)
1832 /* We need to set up a variant frag. */
1833 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1834 f
= frag_var (rs_machine_dependent
, 4, 0,
1835 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1836 mips16_small
, mips16_ext
,
1838 & INSN_UNCOND_BRANCH_DELAY
),
1839 (prev_insn_reloc_type
1840 == BFD_RELOC_MIPS16_JMP
)),
1841 make_expr_symbol (address_expr
), (offsetT
) 0,
1844 else if (place
!= NULL
)
1846 else if (mips_opts
.mips16
1848 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1850 /* Make sure there is enough room to swap this instruction with
1851 a following jump instruction. */
1857 if (mips_opts
.mips16
1858 && mips_opts
.noreorder
1859 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1860 as_warn (_("extended instruction in delay slot"));
1866 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1868 if (address_expr
->X_op
== O_constant
)
1873 ip
->insn_opcode
|= address_expr
->X_add_number
;
1876 case BFD_RELOC_LO16
:
1877 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1880 case BFD_RELOC_MIPS_JMP
:
1881 if ((address_expr
->X_add_number
& 3) != 0)
1882 as_bad (_("jump to misaligned address (0x%lx)"),
1883 (unsigned long) address_expr
->X_add_number
);
1884 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1887 case BFD_RELOC_MIPS16_JMP
:
1888 if ((address_expr
->X_add_number
& 3) != 0)
1889 as_bad (_("jump to misaligned address (0x%lx)"),
1890 (unsigned long) address_expr
->X_add_number
);
1892 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1893 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1894 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1897 case BFD_RELOC_16_PCREL_S2
:
1907 /* Don't generate a reloc if we are writing into a variant
1911 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1913 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1917 struct mips_hi_fixup
*hi_fixup
;
1919 assert (reloc_type
== BFD_RELOC_HI16_S
);
1920 hi_fixup
= ((struct mips_hi_fixup
*)
1921 xmalloc (sizeof (struct mips_hi_fixup
)));
1922 hi_fixup
->fixp
= fixp
;
1923 hi_fixup
->seg
= now_seg
;
1924 hi_fixup
->next
= mips_hi_fixup_list
;
1925 mips_hi_fixup_list
= hi_fixup
;
1931 if (! mips_opts
.mips16
)
1932 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1933 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1935 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1936 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1942 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1945 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1948 /* Update the register mask information. */
1949 if (! mips_opts
.mips16
)
1951 if (pinfo
& INSN_WRITE_GPR_D
)
1952 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1953 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1954 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1955 if (pinfo
& INSN_READ_GPR_S
)
1956 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1957 if (pinfo
& INSN_WRITE_GPR_31
)
1958 mips_gprmask
|= 1 << 31;
1959 if (pinfo
& INSN_WRITE_FPR_D
)
1960 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1961 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1962 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1963 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1964 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1965 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1966 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1967 if (pinfo
& INSN_COP
)
1969 /* We don't keep enough information to sort these cases out.
1970 The itbl support does keep this information however, although
1971 we currently don't support itbl fprmats as part of the cop
1972 instruction. May want to add this support in the future. */
1974 /* Never set the bit for $0, which is always zero. */
1975 mips_gprmask
&=~ 1 << 0;
1979 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1980 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1981 & MIPS16OP_MASK_RX
);
1982 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1983 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1984 & MIPS16OP_MASK_RY
);
1985 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1986 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1987 & MIPS16OP_MASK_RZ
);
1988 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1989 mips_gprmask
|= 1 << TREG
;
1990 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1991 mips_gprmask
|= 1 << SP
;
1992 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1993 mips_gprmask
|= 1 << RA
;
1994 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1995 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1996 if (pinfo
& MIPS16_INSN_READ_Z
)
1997 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1998 & MIPS16OP_MASK_MOVE32Z
);
1999 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2000 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2001 & MIPS16OP_MASK_REGR32
);
2004 if (place
== NULL
&& ! mips_opts
.noreorder
)
2006 /* Filling the branch delay slot is more complex. We try to
2007 switch the branch with the previous instruction, which we can
2008 do if the previous instruction does not set up a condition
2009 that the branch tests and if the branch is not itself the
2010 target of any branch. */
2011 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2012 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2014 if (mips_optimize
< 2
2015 /* If we have seen .set volatile or .set nomove, don't
2017 || mips_opts
.nomove
!= 0
2018 /* If we had to emit any NOP instructions, then we
2019 already know we can not swap. */
2021 /* If we don't even know the previous insn, we can not
2023 || ! prev_insn_valid
2024 /* If the previous insn is already in a branch delay
2025 slot, then we can not swap. */
2026 || prev_insn_is_delay_slot
2027 /* If the previous previous insn was in a .set
2028 noreorder, we can't swap. Actually, the MIPS
2029 assembler will swap in this situation. However, gcc
2030 configured -with-gnu-as will generate code like
2036 in which we can not swap the bne and INSN. If gcc is
2037 not configured -with-gnu-as, it does not output the
2038 .set pseudo-ops. We don't have to check
2039 prev_insn_unreordered, because prev_insn_valid will
2040 be 0 in that case. We don't want to use
2041 prev_prev_insn_valid, because we do want to be able
2042 to swap at the start of a function. */
2043 || prev_prev_insn_unreordered
2044 /* If the branch is itself the target of a branch, we
2045 can not swap. We cheat on this; all we check for is
2046 whether there is a label on this instruction. If
2047 there are any branches to anything other than a
2048 label, users must use .set noreorder. */
2049 || insn_labels
!= NULL
2050 /* If the previous instruction is in a variant frag, we
2051 can not do the swap. This does not apply to the
2052 mips16, which uses variant frags for different
2054 || (! mips_opts
.mips16
2055 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2056 /* If the branch reads the condition codes, we don't
2057 even try to swap, because in the sequence
2062 we can not swap, and I don't feel like handling that
2064 || (! mips_opts
.mips16
2065 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2066 && (pinfo
& INSN_READ_COND_CODE
))
2067 /* We can not swap with an instruction that requires a
2068 delay slot, becase the target of the branch might
2069 interfere with that instruction. */
2070 || (! mips_opts
.mips16
2071 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2073 /* Itbl support may require additional care here. */
2074 & (INSN_LOAD_COPROC_DELAY
2075 | INSN_COPROC_MOVE_DELAY
2076 | INSN_WRITE_COND_CODE
)))
2077 || (! (hilo_interlocks
2078 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2082 || (! mips_opts
.mips16
2084 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2085 || (! mips_opts
.mips16
2086 && mips_opts
.isa
== 1
2087 /* Itbl support may require additional care here. */
2088 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2089 /* We can not swap with a branch instruction. */
2091 & (INSN_UNCOND_BRANCH_DELAY
2092 | INSN_COND_BRANCH_DELAY
2093 | INSN_COND_BRANCH_LIKELY
))
2094 /* We do not swap with a trap instruction, since it
2095 complicates trap handlers to have the trap
2096 instruction be in a delay slot. */
2097 || (prev_pinfo
& INSN_TRAP
)
2098 /* If the branch reads a register that the previous
2099 instruction sets, we can not swap. */
2100 || (! mips_opts
.mips16
2101 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2102 && insn_uses_reg (ip
,
2103 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2106 || (! mips_opts
.mips16
2107 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2108 && insn_uses_reg (ip
,
2109 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2112 || (mips_opts
.mips16
2113 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2114 && insn_uses_reg (ip
,
2115 ((prev_insn
.insn_opcode
2117 & MIPS16OP_MASK_RX
),
2119 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2120 && insn_uses_reg (ip
,
2121 ((prev_insn
.insn_opcode
2123 & MIPS16OP_MASK_RY
),
2125 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2126 && insn_uses_reg (ip
,
2127 ((prev_insn
.insn_opcode
2129 & MIPS16OP_MASK_RZ
),
2131 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2132 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2133 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2134 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2135 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2136 && insn_uses_reg (ip
,
2137 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2140 /* If the branch writes a register that the previous
2141 instruction sets, we can not swap (we know that
2142 branches write only to RD or to $31). */
2143 || (! mips_opts
.mips16
2144 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2145 && (((pinfo
& INSN_WRITE_GPR_D
)
2146 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2147 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2148 || ((pinfo
& INSN_WRITE_GPR_31
)
2149 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2152 || (! mips_opts
.mips16
2153 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2154 && (((pinfo
& INSN_WRITE_GPR_D
)
2155 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2156 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2157 || ((pinfo
& INSN_WRITE_GPR_31
)
2158 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2161 || (mips_opts
.mips16
2162 && (pinfo
& MIPS16_INSN_WRITE_31
)
2163 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2164 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2165 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2167 /* If the branch writes a register that the previous
2168 instruction reads, we can not swap (we know that
2169 branches only write to RD or to $31). */
2170 || (! mips_opts
.mips16
2171 && (pinfo
& INSN_WRITE_GPR_D
)
2172 && insn_uses_reg (&prev_insn
,
2173 ((ip
->insn_opcode
>> OP_SH_RD
)
2176 || (! mips_opts
.mips16
2177 && (pinfo
& INSN_WRITE_GPR_31
)
2178 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2179 || (mips_opts
.mips16
2180 && (pinfo
& MIPS16_INSN_WRITE_31
)
2181 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2182 /* If we are generating embedded PIC code, the branch
2183 might be expanded into a sequence which uses $at, so
2184 we can't swap with an instruction which reads it. */
2185 || (mips_pic
== EMBEDDED_PIC
2186 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2187 /* If the previous previous instruction has a load
2188 delay, and sets a register that the branch reads, we
2190 || (! mips_opts
.mips16
2191 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2192 /* Itbl support may require additional care here. */
2193 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2194 || (! gpr_interlocks
2195 && (prev_prev_insn
.insn_mo
->pinfo
2196 & INSN_LOAD_MEMORY_DELAY
)))
2197 && insn_uses_reg (ip
,
2198 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2201 /* If one instruction sets a condition code and the
2202 other one uses a condition code, we can not swap. */
2203 || ((pinfo
& INSN_READ_COND_CODE
)
2204 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2205 || ((pinfo
& INSN_WRITE_COND_CODE
)
2206 && (prev_pinfo
& INSN_READ_COND_CODE
))
2207 /* If the previous instruction uses the PC, we can not
2209 || (mips_opts
.mips16
2210 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2211 /* If the previous instruction was extended, we can not
2213 || (mips_opts
.mips16
&& prev_insn_extended
)
2214 /* If the previous instruction had a fixup in mips16
2215 mode, we can not swap. This normally means that the
2216 previous instruction was a 4 byte branch anyhow. */
2217 || (mips_opts
.mips16
&& prev_insn_fixp
)
2218 /* If the previous instruction is a sync, sync.l, or
2219 sync.p, we can not swap. */
2220 || (prev_pinfo
& INSN_SYNC
))
2222 /* We could do even better for unconditional branches to
2223 portions of this object file; we could pick up the
2224 instruction at the destination, put it in the delay
2225 slot, and bump the destination address. */
2227 /* Update the previous insn information. */
2228 prev_prev_insn
= *ip
;
2229 prev_insn
.insn_mo
= &dummy_opcode
;
2233 /* It looks like we can actually do the swap. */
2234 if (! mips_opts
.mips16
)
2239 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2240 memcpy (temp
, prev_f
, 4);
2241 memcpy (prev_f
, f
, 4);
2242 memcpy (f
, temp
, 4);
2245 prev_insn_fixp
->fx_frag
= frag_now
;
2246 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2250 fixp
->fx_frag
= prev_insn_frag
;
2251 fixp
->fx_where
= prev_insn_where
;
2259 assert (prev_insn_fixp
== NULL
);
2260 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2261 memcpy (temp
, prev_f
, 2);
2262 memcpy (prev_f
, f
, 2);
2263 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2265 assert (reloc_type
== BFD_RELOC_UNUSED
);
2266 memcpy (f
, temp
, 2);
2270 memcpy (f
, f
+ 2, 2);
2271 memcpy (f
+ 2, temp
, 2);
2275 fixp
->fx_frag
= prev_insn_frag
;
2276 fixp
->fx_where
= prev_insn_where
;
2280 /* Update the previous insn information; leave prev_insn
2282 prev_prev_insn
= *ip
;
2284 prev_insn_is_delay_slot
= 1;
2286 /* If that was an unconditional branch, forget the previous
2287 insn information. */
2288 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2290 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2291 prev_insn
.insn_mo
= &dummy_opcode
;
2294 prev_insn_fixp
= NULL
;
2295 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2296 prev_insn_extended
= 0;
2298 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2300 /* We don't yet optimize a branch likely. What we should do
2301 is look at the target, copy the instruction found there
2302 into the delay slot, and increment the branch to jump to
2303 the next instruction. */
2305 /* Update the previous insn information. */
2306 prev_prev_insn
= *ip
;
2307 prev_insn
.insn_mo
= &dummy_opcode
;
2308 prev_insn_fixp
= NULL
;
2309 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2310 prev_insn_extended
= 0;
2314 /* Update the previous insn information. */
2316 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2318 prev_prev_insn
= prev_insn
;
2321 /* Any time we see a branch, we always fill the delay slot
2322 immediately; since this insn is not a branch, we know it
2323 is not in a delay slot. */
2324 prev_insn_is_delay_slot
= 0;
2326 prev_insn_fixp
= fixp
;
2327 prev_insn_reloc_type
= reloc_type
;
2328 if (mips_opts
.mips16
)
2329 prev_insn_extended
= (ip
->use_extend
2330 || reloc_type
> BFD_RELOC_UNUSED
);
2333 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2334 prev_insn_unreordered
= 0;
2335 prev_insn_frag
= frag_now
;
2336 prev_insn_where
= f
- frag_now
->fr_literal
;
2337 prev_insn_valid
= 1;
2339 else if (place
== NULL
)
2341 /* We need to record a bit of information even when we are not
2342 reordering, in order to determine the base address for mips16
2343 PC relative relocs. */
2344 prev_prev_insn
= prev_insn
;
2346 prev_insn_reloc_type
= reloc_type
;
2347 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2348 prev_insn_unreordered
= 1;
2351 /* We just output an insn, so the next one doesn't have a label. */
2352 mips_clear_insn_labels ();
2354 /* We must ensure that a fixup associated with an unmatched %hi
2355 reloc does not become a variant frag. Otherwise, the
2356 rearrangement of %hi relocs in frob_file may confuse
2360 frag_wane (frag_now
);
2365 /* This function forgets that there was any previous instruction or
2366 label. If PRESERVE is non-zero, it remembers enough information to
2367 know whether nops are needed before a noreorder section. */
2370 mips_no_prev_insn (preserve
)
2375 prev_insn
.insn_mo
= &dummy_opcode
;
2376 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2377 prev_nop_frag
= NULL
;
2378 prev_nop_frag_holds
= 0;
2379 prev_nop_frag_required
= 0;
2380 prev_nop_frag_since
= 0;
2382 prev_insn_valid
= 0;
2383 prev_insn_is_delay_slot
= 0;
2384 prev_insn_unreordered
= 0;
2385 prev_insn_extended
= 0;
2386 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2387 prev_prev_insn_unreordered
= 0;
2388 mips_clear_insn_labels ();
2391 /* This function must be called whenever we turn on noreorder or emit
2392 something other than instructions. It inserts any NOPS which might
2393 be needed by the previous instruction, and clears the information
2394 kept for the previous instructions. The INSNS parameter is true if
2395 instructions are to follow. */
2398 mips_emit_delays (insns
)
2401 if (! mips_opts
.noreorder
)
2406 if ((! mips_opts
.mips16
2407 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2408 && (! cop_interlocks
2409 && (prev_insn
.insn_mo
->pinfo
2410 & (INSN_LOAD_COPROC_DELAY
2411 | INSN_COPROC_MOVE_DELAY
2412 | INSN_WRITE_COND_CODE
))))
2413 || (! hilo_interlocks
2414 && (prev_insn
.insn_mo
->pinfo
2417 || (! mips_opts
.mips16
2419 && (prev_insn
.insn_mo
->pinfo
2420 & INSN_LOAD_MEMORY_DELAY
))
2421 || (! mips_opts
.mips16
2422 && mips_opts
.isa
== 1
2423 && (prev_insn
.insn_mo
->pinfo
2424 & INSN_COPROC_MEMORY_DELAY
)))
2426 /* Itbl support may require additional care here. */
2428 if ((! mips_opts
.mips16
2429 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2430 && (! cop_interlocks
2431 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2432 || (! hilo_interlocks
2433 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2434 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2437 if (prev_insn_unreordered
)
2440 else if ((! mips_opts
.mips16
2441 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2442 && (! cop_interlocks
2443 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2444 || (! hilo_interlocks
2445 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2446 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2448 /* Itbl support may require additional care here. */
2449 if (! prev_prev_insn_unreordered
)
2455 struct insn_label_list
*l
;
2459 /* Record the frag which holds the nop instructions, so
2460 that we can remove them if we don't need them. */
2461 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2462 prev_nop_frag
= frag_now
;
2463 prev_nop_frag_holds
= nops
;
2464 prev_nop_frag_required
= 0;
2465 prev_nop_frag_since
= 0;
2468 for (; nops
> 0; --nops
)
2473 /* Move on to a new frag, so that it is safe to simply
2474 decrease the size of prev_nop_frag. */
2475 frag_wane (frag_now
);
2479 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2481 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2482 symbol_set_frag (l
->label
, frag_now
);
2483 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2484 /* mips16 text labels are stored as odd. */
2485 if (mips_opts
.mips16
)
2486 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2491 /* Mark instruction labels in mips16 mode. */
2492 if (mips_opts
.mips16
&& insns
)
2493 mips16_mark_labels ();
2495 mips_no_prev_insn (insns
);
2498 /* Build an instruction created by a macro expansion. This is passed
2499 a pointer to the count of instructions created so far, an
2500 expression, the name of the instruction to build, an operand format
2501 string, and corresponding arguments. */
2505 macro_build (char *place
,
2513 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2522 struct mips_cl_insn insn
;
2523 bfd_reloc_code_real_type r
;
2527 va_start (args
, fmt
);
2533 * If the macro is about to expand into a second instruction,
2534 * print a warning if needed. We need to pass ip as a parameter
2535 * to generate a better warning message here...
2537 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2538 as_warn (_("Macro instruction expanded into multiple instructions"));
2541 *counter
+= 1; /* bump instruction counter */
2543 if (mips_opts
.mips16
)
2545 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2550 r
= BFD_RELOC_UNUSED
;
2551 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2552 assert (insn
.insn_mo
);
2553 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2555 /* Search until we get a match for NAME. */
2558 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2559 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2560 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2562 && (mips_cpu
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2566 assert (insn
.insn_mo
->name
);
2567 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2570 insn
.insn_opcode
= insn
.insn_mo
->match
;
2586 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2592 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2597 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2602 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2609 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2613 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2617 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2621 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2628 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2634 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2635 assert (r
== BFD_RELOC_MIPS_GPREL
2636 || r
== BFD_RELOC_MIPS_LITERAL
2637 || r
== BFD_RELOC_LO16
2638 || r
== BFD_RELOC_MIPS_GOT16
2639 || r
== BFD_RELOC_MIPS_CALL16
2640 || r
== BFD_RELOC_MIPS_GOT_LO16
2641 || r
== BFD_RELOC_MIPS_CALL_LO16
2642 || (ep
->X_op
== O_subtract
2643 && r
== BFD_RELOC_PCREL_LO16
));
2647 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2649 && (ep
->X_op
== O_constant
2650 || (ep
->X_op
== O_symbol
2651 && (r
== BFD_RELOC_HI16_S
2652 || r
== BFD_RELOC_HI16
2653 || r
== BFD_RELOC_MIPS_GOT_HI16
2654 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2655 || (ep
->X_op
== O_subtract
2656 && r
== BFD_RELOC_PCREL_HI16_S
)));
2657 if (ep
->X_op
== O_constant
)
2659 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2661 r
= BFD_RELOC_UNUSED
;
2666 assert (ep
!= NULL
);
2668 * This allows macro() to pass an immediate expression for
2669 * creating short branches without creating a symbol.
2670 * Note that the expression still might come from the assembly
2671 * input, in which case the value is not checked for range nor
2672 * is a relocation entry generated (yuck).
2674 if (ep
->X_op
== O_constant
)
2676 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2680 r
= BFD_RELOC_16_PCREL_S2
;
2684 assert (ep
!= NULL
);
2685 r
= BFD_RELOC_MIPS_JMP
;
2689 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2698 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2700 append_insn (place
, &insn
, ep
, r
, false);
2704 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2706 int *counter ATTRIBUTE_UNUSED
;
2712 struct mips_cl_insn insn
;
2713 bfd_reloc_code_real_type r
;
2715 r
= BFD_RELOC_UNUSED
;
2716 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2717 assert (insn
.insn_mo
);
2718 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2720 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2721 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2724 assert (insn
.insn_mo
->name
);
2725 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2728 insn
.insn_opcode
= insn
.insn_mo
->match
;
2729 insn
.use_extend
= false;
2748 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2753 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2757 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2761 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2771 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2778 regno
= va_arg (args
, int);
2779 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2780 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2801 assert (ep
!= NULL
);
2803 if (ep
->X_op
!= O_constant
)
2804 r
= BFD_RELOC_UNUSED
+ c
;
2807 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2808 false, false, &insn
.insn_opcode
,
2809 &insn
.use_extend
, &insn
.extend
);
2811 r
= BFD_RELOC_UNUSED
;
2817 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2824 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2826 append_insn (place
, &insn
, ep
, r
, false);
2830 * Generate a "lui" instruction.
2833 macro_build_lui (place
, counter
, ep
, regnum
)
2839 expressionS high_expr
;
2840 struct mips_cl_insn insn
;
2841 bfd_reloc_code_real_type r
;
2842 CONST
char *name
= "lui";
2843 CONST
char *fmt
= "t,u";
2845 assert (! mips_opts
.mips16
);
2851 high_expr
.X_op
= O_constant
;
2852 high_expr
.X_add_number
= ep
->X_add_number
;
2855 if (high_expr
.X_op
== O_constant
)
2857 /* we can compute the instruction now without a relocation entry */
2858 if (high_expr
.X_add_number
& 0x8000)
2859 high_expr
.X_add_number
+= 0x10000;
2860 high_expr
.X_add_number
=
2861 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2862 r
= BFD_RELOC_UNUSED
;
2866 assert (ep
->X_op
== O_symbol
);
2867 /* _gp_disp is a special case, used from s_cpload. */
2868 assert (mips_pic
== NO_PIC
2869 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2870 r
= BFD_RELOC_HI16_S
;
2874 * If the macro is about to expand into a second instruction,
2875 * print a warning if needed. We need to pass ip as a parameter
2876 * to generate a better warning message here...
2878 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2879 as_warn (_("Macro instruction expanded into multiple instructions"));
2882 *counter
+= 1; /* bump instruction counter */
2884 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2885 assert (insn
.insn_mo
);
2886 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2887 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2889 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2890 if (r
== BFD_RELOC_UNUSED
)
2892 insn
.insn_opcode
|= high_expr
.X_add_number
;
2893 append_insn (place
, &insn
, NULL
, r
, false);
2896 append_insn (place
, &insn
, &high_expr
, r
, false);
2900 * Generates code to set the $at register to true (one)
2901 * if reg is less than the immediate expression.
2904 set_at (counter
, reg
, unsignedp
)
2909 if (imm_expr
.X_op
== O_constant
2910 && imm_expr
.X_add_number
>= -0x8000
2911 && imm_expr
.X_add_number
< 0x8000)
2912 macro_build ((char *) NULL
, counter
, &imm_expr
,
2913 unsignedp
? "sltiu" : "slti",
2914 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2917 load_register (counter
, AT
, &imm_expr
, 0);
2918 macro_build ((char *) NULL
, counter
, NULL
,
2919 unsignedp
? "sltu" : "slt",
2920 "d,v,t", AT
, reg
, AT
);
2924 /* Warn if an expression is not a constant. */
2927 check_absolute_expr (ip
, ex
)
2928 struct mips_cl_insn
*ip
;
2931 if (ex
->X_op
== O_big
)
2932 as_bad (_("unsupported large constant"));
2933 else if (ex
->X_op
!= O_constant
)
2934 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2937 /* Count the leading zeroes by performing a binary chop. This is a
2938 bulky bit of source, but performance is a LOT better for the
2939 majority of values than a simple loop to count the bits:
2940 for (lcnt = 0; (lcnt < 32); lcnt++)
2941 if ((v) & (1 << (31 - lcnt)))
2943 However it is not code size friendly, and the gain will drop a bit
2944 on certain cached systems.
2946 #define COUNT_TOP_ZEROES(v) \
2947 (((v) & ~0xffff) == 0 \
2948 ? ((v) & ~0xff) == 0 \
2949 ? ((v) & ~0xf) == 0 \
2950 ? ((v) & ~0x3) == 0 \
2951 ? ((v) & ~0x1) == 0 \
2956 : ((v) & ~0x7) == 0 \
2959 : ((v) & ~0x3f) == 0 \
2960 ? ((v) & ~0x1f) == 0 \
2963 : ((v) & ~0x7f) == 0 \
2966 : ((v) & ~0xfff) == 0 \
2967 ? ((v) & ~0x3ff) == 0 \
2968 ? ((v) & ~0x1ff) == 0 \
2971 : ((v) & ~0x7ff) == 0 \
2974 : ((v) & ~0x3fff) == 0 \
2975 ? ((v) & ~0x1fff) == 0 \
2978 : ((v) & ~0x7fff) == 0 \
2981 : ((v) & ~0xffffff) == 0 \
2982 ? ((v) & ~0xfffff) == 0 \
2983 ? ((v) & ~0x3ffff) == 0 \
2984 ? ((v) & ~0x1ffff) == 0 \
2987 : ((v) & ~0x7ffff) == 0 \
2990 : ((v) & ~0x3fffff) == 0 \
2991 ? ((v) & ~0x1fffff) == 0 \
2994 : ((v) & ~0x7fffff) == 0 \
2997 : ((v) & ~0xfffffff) == 0 \
2998 ? ((v) & ~0x3ffffff) == 0 \
2999 ? ((v) & ~0x1ffffff) == 0 \
3002 : ((v) & ~0x7ffffff) == 0 \
3005 : ((v) & ~0x3fffffff) == 0 \
3006 ? ((v) & ~0x1fffffff) == 0 \
3009 : ((v) & ~0x7fffffff) == 0 \
3014 * This routine generates the least number of instructions neccessary to load
3015 * an absolute expression value into a register.
3018 load_register (counter
, reg
, ep
, dbl
)
3025 expressionS hi32
, lo32
;
3027 if (ep
->X_op
!= O_big
)
3029 assert (ep
->X_op
== O_constant
);
3030 if (ep
->X_add_number
< 0x8000
3031 && (ep
->X_add_number
>= 0
3032 || (ep
->X_add_number
>= -0x8000
3035 || sizeof (ep
->X_add_number
) > 4))))
3037 /* We can handle 16 bit signed values with an addiu to
3038 $zero. No need to ever use daddiu here, since $zero and
3039 the result are always correct in 32 bit mode. */
3040 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3041 (int) BFD_RELOC_LO16
);
3044 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3046 /* We can handle 16 bit unsigned values with an ori to
3048 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3049 (int) BFD_RELOC_LO16
);
3052 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3053 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3054 == ~ (offsetT
) 0x7fffffff))
3057 || sizeof (ep
->X_add_number
) > 4
3058 || (ep
->X_add_number
& 0x80000000) == 0))
3059 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
3060 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3061 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3063 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3064 == ~ (offsetT
) 0xffffffff)))
3066 /* 32 bit values require an lui. */
3067 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3068 (int) BFD_RELOC_HI16
);
3069 if ((ep
->X_add_number
& 0xffff) != 0)
3070 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3071 (int) BFD_RELOC_LO16
);
3076 /* The value is larger than 32 bits. */
3078 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3080 as_bad (_("Number larger than 32 bits"));
3081 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3082 (int) BFD_RELOC_LO16
);
3086 if (ep
->X_op
!= O_big
)
3089 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3090 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3091 hi32
.X_add_number
&= 0xffffffff;
3093 lo32
.X_add_number
&= 0xffffffff;
3097 assert (ep
->X_add_number
> 2);
3098 if (ep
->X_add_number
== 3)
3099 generic_bignum
[3] = 0;
3100 else if (ep
->X_add_number
> 4)
3101 as_bad (_("Number larger than 64 bits"));
3102 lo32
.X_op
= O_constant
;
3103 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3104 hi32
.X_op
= O_constant
;
3105 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3108 if (hi32
.X_add_number
== 0)
3113 unsigned long hi
, lo
;
3115 if (hi32
.X_add_number
== 0xffffffff)
3117 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3119 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3120 reg
, 0, (int) BFD_RELOC_LO16
);
3123 if (lo32
.X_add_number
& 0x80000000)
3125 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3126 (int) BFD_RELOC_HI16
);
3127 if (lo32
.X_add_number
& 0xffff)
3128 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3129 reg
, reg
, (int) BFD_RELOC_LO16
);
3134 /* Check for 16bit shifted constant. We know that hi32 is
3135 non-zero, so start the mask on the first bit of the hi32
3140 unsigned long himask
, lomask
;
3144 himask
= 0xffff >> (32 - shift
);
3145 lomask
= (0xffff << shift
) & 0xffffffff;
3149 himask
= 0xffff << (shift
- 32);
3152 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3153 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3157 tmp
.X_op
= O_constant
;
3159 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3160 | (lo32
.X_add_number
>> shift
));
3162 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3163 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3164 (int) BFD_RELOC_LO16
);
3165 macro_build ((char *) NULL
, counter
, NULL
,
3166 (shift
>= 32) ? "dsll32" : "dsll",
3168 (shift
>= 32) ? shift
- 32 : shift
);
3172 } while (shift
<= (64 - 16));
3174 /* Find the bit number of the lowest one bit, and store the
3175 shifted value in hi/lo. */
3176 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3177 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3181 while ((lo
& 1) == 0)
3186 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3192 while ((hi
& 1) == 0)
3201 /* Optimize if the shifted value is a (power of 2) - 1. */
3202 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3203 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3205 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3210 /* This instruction will set the register to be all
3212 tmp
.X_op
= O_constant
;
3213 tmp
.X_add_number
= (offsetT
) -1;
3214 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3215 reg
, 0, (int) BFD_RELOC_LO16
);
3219 macro_build ((char *) NULL
, counter
, NULL
,
3220 (bit
>= 32) ? "dsll32" : "dsll",
3222 (bit
>= 32) ? bit
- 32 : bit
);
3224 macro_build ((char *) NULL
, counter
, NULL
,
3225 (shift
>= 32) ? "dsrl32" : "dsrl",
3227 (shift
>= 32) ? shift
- 32 : shift
);
3232 /* Sign extend hi32 before calling load_register, because we can
3233 generally get better code when we load a sign extended value. */
3234 if ((hi32
.X_add_number
& 0x80000000) != 0)
3235 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3236 load_register (counter
, reg
, &hi32
, 0);
3239 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3243 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3252 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3254 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3255 (int) BFD_RELOC_HI16
);
3256 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3263 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3268 mid16
.X_add_number
>>= 16;
3269 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3270 freg
, (int) BFD_RELOC_LO16
);
3271 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3275 if ((lo32
.X_add_number
& 0xffff) != 0)
3276 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3277 (int) BFD_RELOC_LO16
);
3280 /* Load an address into a register. */
3283 load_address (counter
, reg
, ep
)
3290 if (ep
->X_op
!= O_constant
3291 && ep
->X_op
!= O_symbol
)
3293 as_bad (_("expression too complex"));
3294 ep
->X_op
= O_constant
;
3297 if (ep
->X_op
== O_constant
)
3299 load_register (counter
, reg
, ep
, 0);
3303 if (mips_pic
== NO_PIC
)
3305 /* If this is a reference to a GP relative symbol, we want
3306 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3308 lui $reg,<sym> (BFD_RELOC_HI16_S)
3309 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3310 If we have an addend, we always use the latter form. */
3311 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3312 || nopic_need_relax (ep
->X_add_symbol
, 1))
3317 macro_build ((char *) NULL
, counter
, ep
,
3318 ((bfd_arch_bits_per_address (stdoutput
) == 32
3319 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3320 ? "addiu" : "daddiu"),
3321 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3322 p
= frag_var (rs_machine_dependent
, 8, 0,
3323 RELAX_ENCODE (4, 8, 0, 4, 0,
3324 mips_opts
.warn_about_macros
),
3325 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3327 macro_build_lui (p
, counter
, ep
, reg
);
3330 macro_build (p
, counter
, ep
,
3331 ((bfd_arch_bits_per_address (stdoutput
) == 32
3332 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3333 ? "addiu" : "daddiu"),
3334 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3336 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3340 /* If this is a reference to an external symbol, we want
3341 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3343 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3345 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3346 If there is a constant, it must be added in after. */
3347 ex
.X_add_number
= ep
->X_add_number
;
3348 ep
->X_add_number
= 0;
3350 macro_build ((char *) NULL
, counter
, ep
,
3351 ((bfd_arch_bits_per_address (stdoutput
) == 32
3352 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3354 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3355 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3356 p
= frag_var (rs_machine_dependent
, 4, 0,
3357 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3358 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3359 macro_build (p
, counter
, ep
,
3360 ((bfd_arch_bits_per_address (stdoutput
) == 32
3361 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3362 ? "addiu" : "daddiu"),
3363 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3364 if (ex
.X_add_number
!= 0)
3366 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3367 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3368 ex
.X_op
= O_constant
;
3369 macro_build ((char *) NULL
, counter
, &ex
,
3370 ((bfd_arch_bits_per_address (stdoutput
) == 32
3371 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3372 ? "addiu" : "daddiu"),
3373 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3376 else if (mips_pic
== SVR4_PIC
)
3381 /* This is the large GOT case. If this is a reference to an
3382 external symbol, we want
3383 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3385 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3386 Otherwise, for a reference to a local symbol, we want
3387 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3389 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3390 If there is a constant, it must be added in after. */
3391 ex
.X_add_number
= ep
->X_add_number
;
3392 ep
->X_add_number
= 0;
3393 if (reg_needs_delay (GP
))
3398 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3399 (int) BFD_RELOC_MIPS_GOT_HI16
);
3400 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3401 ((bfd_arch_bits_per_address (stdoutput
) == 32
3402 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3403 ? "addu" : "daddu"),
3404 "d,v,t", reg
, reg
, GP
);
3405 macro_build ((char *) NULL
, counter
, ep
,
3406 ((bfd_arch_bits_per_address (stdoutput
) == 32
3407 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3409 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3410 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3411 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3412 mips_opts
.warn_about_macros
),
3413 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3416 /* We need a nop before loading from $gp. This special
3417 check is required because the lui which starts the main
3418 instruction stream does not refer to $gp, and so will not
3419 insert the nop which may be required. */
3420 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3423 macro_build (p
, counter
, ep
,
3424 ((bfd_arch_bits_per_address (stdoutput
) == 32
3425 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3427 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3429 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3431 macro_build (p
, counter
, ep
,
3432 ((bfd_arch_bits_per_address (stdoutput
) == 32
3433 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3434 ? "addiu" : "daddiu"),
3435 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3436 if (ex
.X_add_number
!= 0)
3438 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3439 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3440 ex
.X_op
= O_constant
;
3441 macro_build ((char *) NULL
, counter
, &ex
,
3442 ((bfd_arch_bits_per_address (stdoutput
) == 32
3443 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3444 ? "addiu" : "daddiu"),
3445 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3448 else if (mips_pic
== EMBEDDED_PIC
)
3451 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3453 macro_build ((char *) NULL
, counter
, ep
,
3454 ((bfd_arch_bits_per_address (stdoutput
) == 32
3455 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3456 ? "addiu" : "daddiu"),
3457 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3465 * This routine implements the seemingly endless macro or synthesized
3466 * instructions and addressing modes in the mips assembly language. Many
3467 * of these macros are simple and are similar to each other. These could
3468 * probably be handled by some kind of table or grammer aproach instead of
3469 * this verbose method. Others are not simple macros but are more like
3470 * optimizing code generation.
3471 * One interesting optimization is when several store macros appear
3472 * consecutivly that would load AT with the upper half of the same address.
3473 * The ensuing load upper instructions are ommited. This implies some kind
3474 * of global optimization. We currently only optimize within a single macro.
3475 * For many of the load and store macros if the address is specified as a
3476 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3477 * first load register 'at' with zero and use it as the base register. The
3478 * mips assembler simply uses register $zero. Just one tiny optimization
3483 struct mips_cl_insn
*ip
;
3485 register int treg
, sreg
, dreg
, breg
;
3501 bfd_reloc_code_real_type r
;
3503 int hold_mips_optimize
;
3505 assert (! mips_opts
.mips16
);
3507 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3508 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3509 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3510 mask
= ip
->insn_mo
->mask
;
3512 expr1
.X_op
= O_constant
;
3513 expr1
.X_op_symbol
= NULL
;
3514 expr1
.X_add_symbol
= NULL
;
3515 expr1
.X_add_number
= 1;
3527 mips_emit_delays (true);
3528 ++mips_opts
.noreorder
;
3529 mips_any_noreorder
= 1;
3531 expr1
.X_add_number
= 8;
3532 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3534 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3536 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3537 macro_build ((char *) NULL
, &icnt
, NULL
,
3538 dbl
? "dsub" : "sub",
3539 "d,v,t", dreg
, 0, sreg
);
3541 --mips_opts
.noreorder
;
3562 if (imm_expr
.X_op
== O_constant
3563 && imm_expr
.X_add_number
>= -0x8000
3564 && imm_expr
.X_add_number
< 0x8000)
3566 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3567 (int) BFD_RELOC_LO16
);
3570 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3571 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3590 if (imm_expr
.X_op
== O_constant
3591 && imm_expr
.X_add_number
>= 0
3592 && imm_expr
.X_add_number
< 0x10000)
3594 if (mask
!= M_NOR_I
)
3595 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3596 sreg
, (int) BFD_RELOC_LO16
);
3599 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3600 treg
, sreg
, (int) BFD_RELOC_LO16
);
3601 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3607 load_register (&icnt
, AT
, &imm_expr
, 0);
3608 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3625 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3627 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3631 load_register (&icnt
, AT
, &imm_expr
, 0);
3632 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3640 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3641 likely
? "bgezl" : "bgez",
3647 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3648 likely
? "blezl" : "blez",
3652 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3653 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3654 likely
? "beql" : "beq",
3661 /* check for > max integer */
3662 maxnum
= 0x7fffffff;
3663 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3670 if (imm_expr
.X_op
== O_constant
3671 && imm_expr
.X_add_number
>= maxnum
3672 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3675 /* result is always false */
3678 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3679 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3683 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3684 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3689 if (imm_expr
.X_op
!= O_constant
)
3690 as_bad (_("Unsupported large constant"));
3691 imm_expr
.X_add_number
++;
3695 if (mask
== M_BGEL_I
)
3697 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3699 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3700 likely
? "bgezl" : "bgez",
3704 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3706 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3707 likely
? "bgtzl" : "bgtz",
3711 maxnum
= 0x7fffffff;
3712 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3719 maxnum
= - maxnum
- 1;
3720 if (imm_expr
.X_op
== O_constant
3721 && imm_expr
.X_add_number
<= maxnum
3722 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3725 /* result is always true */
3726 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3727 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3730 set_at (&icnt
, sreg
, 0);
3731 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3732 likely
? "beql" : "beq",
3743 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3744 likely
? "beql" : "beq",
3748 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3751 likely
? "beql" : "beq",
3759 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3760 && imm_expr
.X_op
== O_constant
3761 && imm_expr
.X_add_number
== 0xffffffff))
3763 if (imm_expr
.X_op
!= O_constant
)
3764 as_bad (_("Unsupported large constant"));
3765 imm_expr
.X_add_number
++;
3769 if (mask
== M_BGEUL_I
)
3771 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3773 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3775 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3776 likely
? "bnel" : "bne",
3780 set_at (&icnt
, sreg
, 1);
3781 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3782 likely
? "beql" : "beq",
3791 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3792 likely
? "bgtzl" : "bgtz",
3798 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3799 likely
? "bltzl" : "bltz",
3803 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3804 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3805 likely
? "bnel" : "bne",
3814 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3815 likely
? "bnel" : "bne",
3821 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3823 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3824 likely
? "bnel" : "bne",
3833 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3834 likely
? "blezl" : "blez",
3840 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3841 likely
? "bgezl" : "bgez",
3845 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3846 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3847 likely
? "beql" : "beq",
3854 maxnum
= 0x7fffffff;
3855 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3862 if (imm_expr
.X_op
== O_constant
3863 && imm_expr
.X_add_number
>= maxnum
3864 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3866 if (imm_expr
.X_op
!= O_constant
)
3867 as_bad (_("Unsupported large constant"));
3868 imm_expr
.X_add_number
++;
3872 if (mask
== M_BLTL_I
)
3874 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3876 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3877 likely
? "bltzl" : "bltz",
3881 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3883 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3884 likely
? "blezl" : "blez",
3888 set_at (&icnt
, sreg
, 0);
3889 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3890 likely
? "bnel" : "bne",
3899 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3900 likely
? "beql" : "beq",
3906 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3908 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3909 likely
? "beql" : "beq",
3917 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3918 && imm_expr
.X_op
== O_constant
3919 && imm_expr
.X_add_number
== 0xffffffff))
3921 if (imm_expr
.X_op
!= O_constant
)
3922 as_bad (_("Unsupported large constant"));
3923 imm_expr
.X_add_number
++;
3927 if (mask
== M_BLTUL_I
)
3929 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3931 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3933 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3934 likely
? "beql" : "beq",
3938 set_at (&icnt
, sreg
, 1);
3939 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3940 likely
? "bnel" : "bne",
3949 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3950 likely
? "bltzl" : "bltz",
3956 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3957 likely
? "bgtzl" : "bgtz",
3961 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3962 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3963 likely
? "bnel" : "bne",
3974 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3975 likely
? "bnel" : "bne",
3979 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3981 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3982 likely
? "bnel" : "bne",
3998 as_warn (_("Divide by zero."));
4000 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4002 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4006 mips_emit_delays (true);
4007 ++mips_opts
.noreorder
;
4008 mips_any_noreorder
= 1;
4011 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4012 macro_build ((char *) NULL
, &icnt
, NULL
,
4013 dbl
? "ddiv" : "div",
4014 "z,s,t", sreg
, treg
);
4018 expr1
.X_add_number
= 8;
4019 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4020 macro_build ((char *) NULL
, &icnt
, NULL
,
4021 dbl
? "ddiv" : "div",
4022 "z,s,t", sreg
, treg
);
4023 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4025 expr1
.X_add_number
= -1;
4026 macro_build ((char *) NULL
, &icnt
, &expr1
,
4027 dbl
? "daddiu" : "addiu",
4028 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4029 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4030 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4033 expr1
.X_add_number
= 1;
4034 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4035 (int) BFD_RELOC_LO16
);
4036 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4041 expr1
.X_add_number
= 0x80000000;
4042 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4043 (int) BFD_RELOC_HI16
);
4047 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4048 /* We want to close the noreorder block as soon as possible, so
4049 that later insns are available for delay slot filling. */
4050 --mips_opts
.noreorder
;
4054 expr1
.X_add_number
= 8;
4055 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4056 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4058 /* We want to close the noreorder block as soon as possible, so
4059 that later insns are available for delay slot filling. */
4060 --mips_opts
.noreorder
;
4062 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4064 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4103 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4105 as_warn (_("Divide by zero."));
4107 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4109 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4112 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4114 if (strcmp (s2
, "mflo") == 0)
4115 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4118 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4121 if (imm_expr
.X_op
== O_constant
4122 && imm_expr
.X_add_number
== -1
4123 && s
[strlen (s
) - 1] != 'u')
4125 if (strcmp (s2
, "mflo") == 0)
4128 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4131 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4135 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4139 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4140 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4141 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4160 mips_emit_delays (true);
4161 ++mips_opts
.noreorder
;
4162 mips_any_noreorder
= 1;
4165 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4166 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4167 /* We want to close the noreorder block as soon as possible, so
4168 that later insns are available for delay slot filling. */
4169 --mips_opts
.noreorder
;
4173 expr1
.X_add_number
= 8;
4174 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4175 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4177 /* We want to close the noreorder block as soon as possible, so
4178 that later insns are available for delay slot filling. */
4179 --mips_opts
.noreorder
;
4180 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4182 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4188 /* Load the address of a symbol into a register. If breg is not
4189 zero, we then add a base register to it. */
4191 /* When generating embedded PIC code, we permit expressions of
4194 where bar is an address in the current section. These are used
4195 when getting the addresses of functions. We don't permit
4196 X_add_number to be non-zero, because if the symbol is
4197 external the relaxing code needs to know that any addend is
4198 purely the offset to X_op_symbol. */
4199 if (mips_pic
== EMBEDDED_PIC
4200 && offset_expr
.X_op
== O_subtract
4201 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4202 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4203 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4205 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4209 && (offset_expr
.X_add_number
== 0
4210 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4212 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4213 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4214 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4215 ((bfd_arch_bits_per_address (stdoutput
) == 32
4216 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4217 ? "addiu" : "daddiu"),
4218 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4222 if (offset_expr
.X_op
!= O_symbol
4223 && offset_expr
.X_op
!= O_constant
)
4225 as_bad (_("expression too complex"));
4226 offset_expr
.X_op
= O_constant
;
4240 if (offset_expr
.X_op
== O_constant
)
4241 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4242 else if (mips_pic
== NO_PIC
)
4244 /* If this is a reference to an GP relative symbol, we want
4245 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4247 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4248 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4249 If we have a constant, we need two instructions anyhow,
4250 so we may as well always use the latter form. */
4251 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4252 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4257 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4258 ((bfd_arch_bits_per_address (stdoutput
) == 32
4259 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4260 ? "addiu" : "daddiu"),
4261 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4262 p
= frag_var (rs_machine_dependent
, 8, 0,
4263 RELAX_ENCODE (4, 8, 0, 4, 0,
4264 mips_opts
.warn_about_macros
),
4265 offset_expr
.X_add_symbol
, (offsetT
) 0,
4268 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4271 macro_build (p
, &icnt
, &offset_expr
,
4272 ((bfd_arch_bits_per_address (stdoutput
) == 32
4273 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4274 ? "addiu" : "daddiu"),
4275 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4277 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4279 /* If this is a reference to an external symbol, and there
4280 is no constant, we want
4281 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4282 For a local symbol, we want
4283 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4285 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4287 If we have a small constant, and this is a reference to
4288 an external symbol, we want
4289 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4291 addiu $tempreg,$tempreg,<constant>
4292 For a local symbol, we want the same instruction
4293 sequence, but we output a BFD_RELOC_LO16 reloc on the
4296 If we have a large constant, and this is a reference to
4297 an external symbol, we want
4298 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4299 lui $at,<hiconstant>
4300 addiu $at,$at,<loconstant>
4301 addu $tempreg,$tempreg,$at
4302 For a local symbol, we want the same instruction
4303 sequence, but we output a BFD_RELOC_LO16 reloc on the
4304 addiu instruction. */
4305 expr1
.X_add_number
= offset_expr
.X_add_number
;
4306 offset_expr
.X_add_number
= 0;
4308 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4310 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4311 if (expr1
.X_add_number
== 0)
4319 /* We're going to put in an addu instruction using
4320 tempreg, so we may as well insert the nop right
4322 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4326 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4327 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4329 ? mips_opts
.warn_about_macros
4331 offset_expr
.X_add_symbol
, (offsetT
) 0,
4335 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4338 macro_build (p
, &icnt
, &expr1
,
4339 ((bfd_arch_bits_per_address (stdoutput
) == 32
4340 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4341 ? "addiu" : "daddiu"),
4342 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4343 /* FIXME: If breg == 0, and the next instruction uses
4344 $tempreg, then if this variant case is used an extra
4345 nop will be generated. */
4347 else if (expr1
.X_add_number
>= -0x8000
4348 && expr1
.X_add_number
< 0x8000)
4350 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4352 macro_build ((char *) NULL
, &icnt
, &expr1
,
4353 ((bfd_arch_bits_per_address (stdoutput
) == 32
4354 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4355 ? "addiu" : "daddiu"),
4356 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4357 (void) frag_var (rs_machine_dependent
, 0, 0,
4358 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4359 offset_expr
.X_add_symbol
, (offsetT
) 0,
4366 /* If we are going to add in a base register, and the
4367 target register and the base register are the same,
4368 then we are using AT as a temporary register. Since
4369 we want to load the constant into AT, we add our
4370 current AT (from the global offset table) and the
4371 register into the register now, and pretend we were
4372 not using a base register. */
4377 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4380 ((bfd_arch_bits_per_address (stdoutput
) == 32
4381 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4382 ? "addu" : "daddu"),
4383 "d,v,t", treg
, AT
, breg
);
4389 /* Set mips_optimize around the lui instruction to avoid
4390 inserting an unnecessary nop after the lw. */
4391 hold_mips_optimize
= mips_optimize
;
4393 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4394 mips_optimize
= hold_mips_optimize
;
4396 macro_build ((char *) NULL
, &icnt
, &expr1
,
4397 ((bfd_arch_bits_per_address (stdoutput
) == 32
4398 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4399 ? "addiu" : "daddiu"),
4400 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4401 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4402 ((bfd_arch_bits_per_address (stdoutput
) == 32
4403 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4404 ? "addu" : "daddu"),
4405 "d,v,t", tempreg
, tempreg
, AT
);
4406 (void) frag_var (rs_machine_dependent
, 0, 0,
4407 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4408 offset_expr
.X_add_symbol
, (offsetT
) 0,
4413 else if (mips_pic
== SVR4_PIC
)
4417 /* This is the large GOT case. If this is a reference to an
4418 external symbol, and there is no constant, we want
4419 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4420 addu $tempreg,$tempreg,$gp
4421 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4422 For a local symbol, we want
4423 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4425 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4427 If we have a small constant, and this is a reference to
4428 an external symbol, we want
4429 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4430 addu $tempreg,$tempreg,$gp
4431 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4433 addiu $tempreg,$tempreg,<constant>
4434 For a local symbol, we want
4435 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4437 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4439 If we have a large constant, and this is a reference to
4440 an external symbol, we want
4441 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4442 addu $tempreg,$tempreg,$gp
4443 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4444 lui $at,<hiconstant>
4445 addiu $at,$at,<loconstant>
4446 addu $tempreg,$tempreg,$at
4447 For a local symbol, we want
4448 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4449 lui $at,<hiconstant>
4450 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4451 addu $tempreg,$tempreg,$at
4453 expr1
.X_add_number
= offset_expr
.X_add_number
;
4454 offset_expr
.X_add_number
= 0;
4456 if (reg_needs_delay (GP
))
4460 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4461 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4463 ((bfd_arch_bits_per_address (stdoutput
) == 32
4464 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4465 ? "addu" : "daddu"),
4466 "d,v,t", tempreg
, tempreg
, GP
);
4467 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4469 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4471 if (expr1
.X_add_number
== 0)
4479 /* We're going to put in an addu instruction using
4480 tempreg, so we may as well insert the nop right
4482 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4487 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4488 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4491 ? mips_opts
.warn_about_macros
4493 offset_expr
.X_add_symbol
, (offsetT
) 0,
4496 else if (expr1
.X_add_number
>= -0x8000
4497 && expr1
.X_add_number
< 0x8000)
4499 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4501 macro_build ((char *) NULL
, &icnt
, &expr1
,
4502 ((bfd_arch_bits_per_address (stdoutput
) == 32
4503 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4504 ? "addiu" : "daddiu"),
4505 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4507 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4508 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4510 ? mips_opts
.warn_about_macros
4512 offset_expr
.X_add_symbol
, (offsetT
) 0,
4519 /* If we are going to add in a base register, and the
4520 target register and the base register are the same,
4521 then we are using AT as a temporary register. Since
4522 we want to load the constant into AT, we add our
4523 current AT (from the global offset table) and the
4524 register into the register now, and pretend we were
4525 not using a base register. */
4533 assert (tempreg
== AT
);
4534 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4536 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4537 ((bfd_arch_bits_per_address (stdoutput
) == 32
4538 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4539 ? "addu" : "daddu"),
4540 "d,v,t", treg
, AT
, breg
);
4545 /* Set mips_optimize around the lui instruction to avoid
4546 inserting an unnecessary nop after the lw. */
4547 hold_mips_optimize
= mips_optimize
;
4549 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4550 mips_optimize
= hold_mips_optimize
;
4552 macro_build ((char *) NULL
, &icnt
, &expr1
,
4553 ((bfd_arch_bits_per_address (stdoutput
) == 32
4554 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4555 ? "addiu" : "daddiu"),
4556 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4557 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4558 ((bfd_arch_bits_per_address (stdoutput
) == 32
4559 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4560 ? "addu" : "daddu"),
4561 "d,v,t", dreg
, dreg
, AT
);
4563 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4564 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4567 ? mips_opts
.warn_about_macros
4569 offset_expr
.X_add_symbol
, (offsetT
) 0,
4577 /* This is needed because this instruction uses $gp, but
4578 the first instruction on the main stream does not. */
4579 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4582 macro_build (p
, &icnt
, &offset_expr
,
4584 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4586 if (expr1
.X_add_number
>= -0x8000
4587 && expr1
.X_add_number
< 0x8000)
4589 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4591 macro_build (p
, &icnt
, &expr1
,
4592 ((bfd_arch_bits_per_address (stdoutput
) == 32
4593 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4594 ? "addiu" : "daddiu"),
4595 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4596 /* FIXME: If add_number is 0, and there was no base
4597 register, the external symbol case ended with a load,
4598 so if the symbol turns out to not be external, and
4599 the next instruction uses tempreg, an unnecessary nop
4600 will be inserted. */
4606 /* We must add in the base register now, as in the
4607 external symbol case. */
4608 assert (tempreg
== AT
);
4609 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4611 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4612 ((bfd_arch_bits_per_address (stdoutput
) == 32
4613 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4614 ? "addu" : "daddu"),
4615 "d,v,t", treg
, AT
, breg
);
4618 /* We set breg to 0 because we have arranged to add
4619 it in in both cases. */
4623 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4625 macro_build (p
, &icnt
, &expr1
,
4626 ((bfd_arch_bits_per_address (stdoutput
) == 32
4627 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4628 ? "addiu" : "daddiu"),
4629 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4631 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4632 ((bfd_arch_bits_per_address (stdoutput
) == 32
4633 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4634 ? "addu" : "daddu"),
4635 "d,v,t", tempreg
, tempreg
, AT
);
4639 else if (mips_pic
== EMBEDDED_PIC
)
4642 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4644 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4645 ((bfd_arch_bits_per_address (stdoutput
) == 32
4646 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4647 ? "addiu" : "daddiu"),
4648 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4654 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4655 ((bfd_arch_bits_per_address (stdoutput
) == 32
4656 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4657 ? "addu" : "daddu"),
4658 "d,v,t", treg
, tempreg
, breg
);
4666 /* The j instruction may not be used in PIC code, since it
4667 requires an absolute address. We convert it to a b
4669 if (mips_pic
== NO_PIC
)
4670 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4672 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4675 /* The jal instructions must be handled as macros because when
4676 generating PIC code they expand to multi-instruction
4677 sequences. Normally they are simple instructions. */
4682 if (mips_pic
== NO_PIC
4683 || mips_pic
== EMBEDDED_PIC
)
4684 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4686 else if (mips_pic
== SVR4_PIC
)
4688 if (sreg
!= PIC_CALL_REG
)
4689 as_warn (_("MIPS PIC call to register other than $25"));
4691 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4693 if (mips_cprestore_offset
< 0)
4694 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4697 expr1
.X_add_number
= mips_cprestore_offset
;
4698 macro_build ((char *) NULL
, &icnt
, &expr1
,
4699 ((bfd_arch_bits_per_address (stdoutput
) == 32
4700 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4702 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4711 if (mips_pic
== NO_PIC
)
4712 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4713 else if (mips_pic
== SVR4_PIC
)
4715 /* If this is a reference to an external symbol, and we are
4716 using a small GOT, we want
4717 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4721 lw $gp,cprestore($sp)
4722 The cprestore value is set using the .cprestore
4723 pseudo-op. If we are using a big GOT, we want
4724 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4726 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4730 lw $gp,cprestore($sp)
4731 If the symbol is not external, we want
4732 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4734 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4737 lw $gp,cprestore($sp) */
4741 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4742 ((bfd_arch_bits_per_address (stdoutput
) == 32
4743 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4745 "t,o(b)", PIC_CALL_REG
,
4746 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4747 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4749 p
= frag_var (rs_machine_dependent
, 4, 0,
4750 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4751 offset_expr
.X_add_symbol
, (offsetT
) 0,
4758 if (reg_needs_delay (GP
))
4762 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4763 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4765 ((bfd_arch_bits_per_address (stdoutput
) == 32
4766 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4767 ? "addu" : "daddu"),
4768 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4769 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4770 ((bfd_arch_bits_per_address (stdoutput
) == 32
4771 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4773 "t,o(b)", PIC_CALL_REG
,
4774 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4775 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4777 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4778 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4780 offset_expr
.X_add_symbol
, (offsetT
) 0,
4784 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4787 macro_build (p
, &icnt
, &offset_expr
,
4788 ((bfd_arch_bits_per_address (stdoutput
) == 32
4789 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4791 "t,o(b)", PIC_CALL_REG
,
4792 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4794 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4797 macro_build (p
, &icnt
, &offset_expr
,
4798 ((bfd_arch_bits_per_address (stdoutput
) == 32
4799 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4800 ? "addiu" : "daddiu"),
4801 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4802 (int) BFD_RELOC_LO16
);
4803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4804 "jalr", "s", PIC_CALL_REG
);
4805 if (mips_cprestore_offset
< 0)
4806 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4809 if (mips_opts
.noreorder
)
4810 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4812 expr1
.X_add_number
= mips_cprestore_offset
;
4813 macro_build ((char *) NULL
, &icnt
, &expr1
,
4814 ((bfd_arch_bits_per_address (stdoutput
) == 32
4815 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4817 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4821 else if (mips_pic
== EMBEDDED_PIC
)
4823 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4824 /* The linker may expand the call to a longer sequence which
4825 uses $at, so we must break rather than return. */
4850 /* Itbl support may require additional care here. */
4855 /* Itbl support may require additional care here. */
4860 /* Itbl support may require additional care here. */
4865 /* Itbl support may require additional care here. */
4877 if (mips_cpu
== CPU_R4650
)
4879 as_bad (_("opcode not supported on this processor"));
4883 /* Itbl support may require additional care here. */
4888 /* Itbl support may require additional care here. */
4893 /* Itbl support may require additional care here. */
4913 if (breg
== treg
|| coproc
|| lr
)
4935 /* Itbl support may require additional care here. */
4940 /* Itbl support may require additional care here. */
4945 /* Itbl support may require additional care here. */
4950 /* Itbl support may require additional care here. */
4966 if (mips_cpu
== CPU_R4650
)
4968 as_bad (_("opcode not supported on this processor"));
4973 /* Itbl support may require additional care here. */
4977 /* Itbl support may require additional care here. */
4982 /* Itbl support may require additional care here. */
4994 /* Itbl support may require additional care here. */
4995 if (mask
== M_LWC1_AB
4996 || mask
== M_SWC1_AB
4997 || mask
== M_LDC1_AB
4998 || mask
== M_SDC1_AB
5007 if (offset_expr
.X_op
!= O_constant
5008 && offset_expr
.X_op
!= O_symbol
)
5010 as_bad (_("expression too complex"));
5011 offset_expr
.X_op
= O_constant
;
5014 /* A constant expression in PIC code can be handled just as it
5015 is in non PIC code. */
5016 if (mips_pic
== NO_PIC
5017 || offset_expr
.X_op
== O_constant
)
5019 /* If this is a reference to a GP relative symbol, and there
5020 is no base register, we want
5021 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5022 Otherwise, if there is no base register, we want
5023 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5024 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5025 If we have a constant, we need two instructions anyhow,
5026 so we always use the latter form.
5028 If we have a base register, and this is a reference to a
5029 GP relative symbol, we want
5030 addu $tempreg,$breg,$gp
5031 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5033 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5034 addu $tempreg,$tempreg,$breg
5035 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5036 With a constant we always use the latter case. */
5039 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5040 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5045 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5046 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5047 p
= frag_var (rs_machine_dependent
, 8, 0,
5048 RELAX_ENCODE (4, 8, 0, 4, 0,
5049 (mips_opts
.warn_about_macros
5051 && mips_opts
.noat
))),
5052 offset_expr
.X_add_symbol
, (offsetT
) 0,
5056 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5059 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5060 (int) BFD_RELOC_LO16
, tempreg
);
5064 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5065 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5071 ((bfd_arch_bits_per_address (stdoutput
) == 32
5072 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5073 ? "addu" : "daddu"),
5074 "d,v,t", tempreg
, breg
, GP
);
5075 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5076 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5077 p
= frag_var (rs_machine_dependent
, 12, 0,
5078 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5079 offset_expr
.X_add_symbol
, (offsetT
) 0,
5082 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5085 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5086 ((bfd_arch_bits_per_address (stdoutput
) == 32
5087 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5088 ? "addu" : "daddu"),
5089 "d,v,t", tempreg
, tempreg
, breg
);
5092 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5093 (int) BFD_RELOC_LO16
, tempreg
);
5096 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5098 /* If this is a reference to an external symbol, we want
5099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5101 <op> $treg,0($tempreg)
5103 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5105 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5106 <op> $treg,0($tempreg)
5107 If there is a base register, we add it to $tempreg before
5108 the <op>. If there is a constant, we stick it in the
5109 <op> instruction. We don't handle constants larger than
5110 16 bits, because we have no way to load the upper 16 bits
5111 (actually, we could handle them for the subset of cases
5112 in which we are not using $at). */
5113 assert (offset_expr
.X_op
== O_symbol
);
5114 expr1
.X_add_number
= offset_expr
.X_add_number
;
5115 offset_expr
.X_add_number
= 0;
5116 if (expr1
.X_add_number
< -0x8000
5117 || expr1
.X_add_number
>= 0x8000)
5118 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5120 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5121 ((bfd_arch_bits_per_address (stdoutput
) == 32
5122 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5124 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5125 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5126 p
= frag_var (rs_machine_dependent
, 4, 0,
5127 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5128 offset_expr
.X_add_symbol
, (offsetT
) 0,
5130 macro_build (p
, &icnt
, &offset_expr
,
5131 ((bfd_arch_bits_per_address (stdoutput
) == 32
5132 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5133 ? "addiu" : "daddiu"),
5134 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5136 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5137 ((bfd_arch_bits_per_address (stdoutput
) == 32
5138 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5139 ? "addu" : "daddu"),
5140 "d,v,t", tempreg
, tempreg
, breg
);
5141 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5142 (int) BFD_RELOC_LO16
, tempreg
);
5144 else if (mips_pic
== SVR4_PIC
)
5148 /* If this is a reference to an external symbol, we want
5149 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5150 addu $tempreg,$tempreg,$gp
5151 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5152 <op> $treg,0($tempreg)
5154 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5156 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5157 <op> $treg,0($tempreg)
5158 If there is a base register, we add it to $tempreg before
5159 the <op>. If there is a constant, we stick it in the
5160 <op> instruction. We don't handle constants larger than
5161 16 bits, because we have no way to load the upper 16 bits
5162 (actually, we could handle them for the subset of cases
5163 in which we are not using $at). */
5164 assert (offset_expr
.X_op
== O_symbol
);
5165 expr1
.X_add_number
= offset_expr
.X_add_number
;
5166 offset_expr
.X_add_number
= 0;
5167 if (expr1
.X_add_number
< -0x8000
5168 || expr1
.X_add_number
>= 0x8000)
5169 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5170 if (reg_needs_delay (GP
))
5175 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5176 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5177 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5178 ((bfd_arch_bits_per_address (stdoutput
) == 32
5179 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5180 ? "addu" : "daddu"),
5181 "d,v,t", tempreg
, tempreg
, GP
);
5182 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5183 ((bfd_arch_bits_per_address (stdoutput
) == 32
5184 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5186 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5188 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5189 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5190 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5193 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5196 macro_build (p
, &icnt
, &offset_expr
,
5197 ((bfd_arch_bits_per_address (stdoutput
) == 32
5198 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5200 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5202 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5204 macro_build (p
, &icnt
, &offset_expr
,
5205 ((bfd_arch_bits_per_address (stdoutput
) == 32
5206 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5207 ? "addiu" : "daddiu"),
5208 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5210 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5211 ((bfd_arch_bits_per_address (stdoutput
) == 32
5212 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5213 ? "addu" : "daddu"),
5214 "d,v,t", tempreg
, tempreg
, breg
);
5215 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5216 (int) BFD_RELOC_LO16
, tempreg
);
5218 else if (mips_pic
== EMBEDDED_PIC
)
5220 /* If there is no base register, we want
5221 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5222 If there is a base register, we want
5223 addu $tempreg,$breg,$gp
5224 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5226 assert (offset_expr
.X_op
== O_symbol
);
5229 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5230 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5235 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5236 ((bfd_arch_bits_per_address (stdoutput
) == 32
5237 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5238 ? "addu" : "daddu"),
5239 "d,v,t", tempreg
, breg
, GP
);
5240 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5241 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5254 load_register (&icnt
, treg
, &imm_expr
, 0);
5258 load_register (&icnt
, treg
, &imm_expr
, 1);
5262 if (imm_expr
.X_op
== O_constant
)
5264 load_register (&icnt
, AT
, &imm_expr
, 0);
5265 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5266 "mtc1", "t,G", AT
, treg
);
5271 assert (offset_expr
.X_op
== O_symbol
5272 && strcmp (segment_name (S_GET_SEGMENT
5273 (offset_expr
.X_add_symbol
)),
5275 && offset_expr
.X_add_number
== 0);
5276 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5277 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5282 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5283 the entire value, and in mips1 mode it is the high order 32
5284 bits of the value and the low order 32 bits are either zero
5285 or in offset_expr. */
5286 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5288 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5289 load_register (&icnt
, treg
, &imm_expr
, 1);
5294 if (target_big_endian
)
5306 load_register (&icnt
, hreg
, &imm_expr
, 0);
5309 if (offset_expr
.X_op
== O_absent
)
5310 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5314 assert (offset_expr
.X_op
== O_constant
);
5315 load_register (&icnt
, lreg
, &offset_expr
, 0);
5322 /* We know that sym is in the .rdata section. First we get the
5323 upper 16 bits of the address. */
5324 if (mips_pic
== NO_PIC
)
5326 /* FIXME: This won't work for a 64 bit address. */
5327 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5329 else if (mips_pic
== SVR4_PIC
)
5331 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5332 ((bfd_arch_bits_per_address (stdoutput
) == 32
5333 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5335 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5337 else if (mips_pic
== EMBEDDED_PIC
)
5339 /* For embedded PIC we pick up the entire address off $gp in
5340 a single instruction. */
5341 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5342 ((bfd_arch_bits_per_address (stdoutput
) == 32
5343 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5344 ? "addiu" : "daddiu"),
5345 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5346 offset_expr
.X_op
= O_constant
;
5347 offset_expr
.X_add_number
= 0;
5352 /* Now we load the register(s). */
5353 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5354 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5355 treg
, (int) BFD_RELOC_LO16
, AT
);
5358 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5359 treg
, (int) BFD_RELOC_LO16
, AT
);
5362 /* FIXME: How in the world do we deal with the possible
5364 offset_expr
.X_add_number
+= 4;
5365 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5366 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5370 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5371 does not become a variant frag. */
5372 frag_wane (frag_now
);
5378 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5379 the entire value, and in mips1 mode it is the high order 32
5380 bits of the value and the low order 32 bits are either zero
5381 or in offset_expr. */
5382 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5384 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5385 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5386 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5387 "dmtc1", "t,S", AT
, treg
);
5390 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5391 "mtc1", "t,G", AT
, treg
+ 1);
5392 if (offset_expr
.X_op
== O_absent
)
5393 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5394 "mtc1", "t,G", 0, treg
);
5397 assert (offset_expr
.X_op
== O_constant
);
5398 load_register (&icnt
, AT
, &offset_expr
, 0);
5399 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5400 "mtc1", "t,G", AT
, treg
);
5406 assert (offset_expr
.X_op
== O_symbol
5407 && offset_expr
.X_add_number
== 0);
5408 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5409 if (strcmp (s
, ".lit8") == 0)
5411 if (mips_opts
.isa
!= 1)
5413 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5414 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5418 r
= BFD_RELOC_MIPS_LITERAL
;
5423 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5424 if (mips_pic
== SVR4_PIC
)
5425 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5426 ((bfd_arch_bits_per_address (stdoutput
) == 32
5427 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5429 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5432 /* FIXME: This won't work for a 64 bit address. */
5433 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5436 if (mips_opts
.isa
!= 1)
5438 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5439 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5441 /* To avoid confusion in tc_gen_reloc, we must ensure
5442 that this does not become a variant frag. */
5443 frag_wane (frag_now
);
5454 if (mips_cpu
== CPU_R4650
)
5456 as_bad (_("opcode not supported on this processor"));
5459 /* Even on a big endian machine $fn comes before $fn+1. We have
5460 to adjust when loading from memory. */
5463 assert (mips_opts
.isa
== 1);
5464 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5465 target_big_endian
? treg
+ 1 : treg
,
5467 /* FIXME: A possible overflow which I don't know how to deal
5469 offset_expr
.X_add_number
+= 4;
5470 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5471 target_big_endian
? treg
: treg
+ 1,
5474 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5475 does not become a variant frag. */
5476 frag_wane (frag_now
);
5485 * The MIPS assembler seems to check for X_add_number not
5486 * being double aligned and generating:
5489 * addiu at,at,%lo(foo+1)
5492 * But, the resulting address is the same after relocation so why
5493 * generate the extra instruction?
5495 if (mips_cpu
== CPU_R4650
)
5497 as_bad (_("opcode not supported on this processor"));
5500 /* Itbl support may require additional care here. */
5502 if (mips_opts
.isa
!= 1)
5513 if (mips_cpu
== CPU_R4650
)
5515 as_bad (_("opcode not supported on this processor"));
5519 if (mips_opts
.isa
!= 1)
5527 /* Itbl support may require additional care here. */
5532 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5543 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5553 if (offset_expr
.X_op
!= O_symbol
5554 && offset_expr
.X_op
!= O_constant
)
5556 as_bad (_("expression too complex"));
5557 offset_expr
.X_op
= O_constant
;
5560 /* Even on a big endian machine $fn comes before $fn+1. We have
5561 to adjust when loading from memory. We set coproc if we must
5562 load $fn+1 first. */
5563 /* Itbl support may require additional care here. */
5564 if (! target_big_endian
)
5567 if (mips_pic
== NO_PIC
5568 || offset_expr
.X_op
== O_constant
)
5570 /* If this is a reference to a GP relative symbol, we want
5571 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5572 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5573 If we have a base register, we use this
5575 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5576 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5577 If this is not a GP relative symbol, we want
5578 lui $at,<sym> (BFD_RELOC_HI16_S)
5579 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5580 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5581 If there is a base register, we add it to $at after the
5582 lui instruction. If there is a constant, we always use
5584 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5585 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5604 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5605 ((bfd_arch_bits_per_address (stdoutput
) == 32
5606 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5607 ? "addu" : "daddu"),
5608 "d,v,t", AT
, breg
, GP
);
5614 /* Itbl support may require additional care here. */
5615 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5616 coproc
? treg
+ 1 : treg
,
5617 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5618 offset_expr
.X_add_number
+= 4;
5620 /* Set mips_optimize to 2 to avoid inserting an
5622 hold_mips_optimize
= mips_optimize
;
5624 /* Itbl support may require additional care here. */
5625 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5626 coproc
? treg
: treg
+ 1,
5627 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5628 mips_optimize
= hold_mips_optimize
;
5630 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5631 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5632 used_at
&& mips_opts
.noat
),
5633 offset_expr
.X_add_symbol
, (offsetT
) 0,
5636 /* We just generated two relocs. When tc_gen_reloc
5637 handles this case, it will skip the first reloc and
5638 handle the second. The second reloc already has an
5639 extra addend of 4, which we added above. We must
5640 subtract it out, and then subtract another 4 to make
5641 the first reloc come out right. The second reloc
5642 will come out right because we are going to add 4 to
5643 offset_expr when we build its instruction below.
5645 If we have a symbol, then we don't want to include
5646 the offset, because it will wind up being included
5647 when we generate the reloc. */
5649 if (offset_expr
.X_op
== O_constant
)
5650 offset_expr
.X_add_number
-= 8;
5653 offset_expr
.X_add_number
= -4;
5654 offset_expr
.X_op
= O_constant
;
5657 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5662 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5663 ((bfd_arch_bits_per_address (stdoutput
) == 32
5664 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5665 ? "addu" : "daddu"),
5666 "d,v,t", AT
, breg
, AT
);
5670 /* Itbl support may require additional care here. */
5671 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5672 coproc
? treg
+ 1 : treg
,
5673 (int) BFD_RELOC_LO16
, AT
);
5676 /* FIXME: How do we handle overflow here? */
5677 offset_expr
.X_add_number
+= 4;
5678 /* Itbl support may require additional care here. */
5679 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5680 coproc
? treg
: treg
+ 1,
5681 (int) BFD_RELOC_LO16
, AT
);
5683 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5687 /* If this is a reference to an external symbol, we want
5688 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5693 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5695 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5696 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5697 If there is a base register we add it to $at before the
5698 lwc1 instructions. If there is a constant we include it
5699 in the lwc1 instructions. */
5701 expr1
.X_add_number
= offset_expr
.X_add_number
;
5702 offset_expr
.X_add_number
= 0;
5703 if (expr1
.X_add_number
< -0x8000
5704 || expr1
.X_add_number
>= 0x8000 - 4)
5705 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5710 frag_grow (24 + off
);
5711 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5712 ((bfd_arch_bits_per_address (stdoutput
) == 32
5713 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5715 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5716 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5718 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5719 ((bfd_arch_bits_per_address (stdoutput
) == 32
5720 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5721 ? "addu" : "daddu"),
5722 "d,v,t", AT
, breg
, AT
);
5723 /* Itbl support may require additional care here. */
5724 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5725 coproc
? treg
+ 1 : treg
,
5726 (int) BFD_RELOC_LO16
, AT
);
5727 expr1
.X_add_number
+= 4;
5729 /* Set mips_optimize to 2 to avoid inserting an undesired
5731 hold_mips_optimize
= mips_optimize
;
5733 /* Itbl support may require additional care here. */
5734 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5735 coproc
? treg
: treg
+ 1,
5736 (int) BFD_RELOC_LO16
, AT
);
5737 mips_optimize
= hold_mips_optimize
;
5739 (void) frag_var (rs_machine_dependent
, 0, 0,
5740 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5741 offset_expr
.X_add_symbol
, (offsetT
) 0,
5744 else if (mips_pic
== SVR4_PIC
)
5748 /* If this is a reference to an external symbol, we want
5749 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5751 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5756 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5758 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5759 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5760 If there is a base register we add it to $at before the
5761 lwc1 instructions. If there is a constant we include it
5762 in the lwc1 instructions. */
5764 expr1
.X_add_number
= offset_expr
.X_add_number
;
5765 offset_expr
.X_add_number
= 0;
5766 if (expr1
.X_add_number
< -0x8000
5767 || expr1
.X_add_number
>= 0x8000 - 4)
5768 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5769 if (reg_needs_delay (GP
))
5778 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5779 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5780 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5781 ((bfd_arch_bits_per_address (stdoutput
) == 32
5782 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5783 ? "addu" : "daddu"),
5784 "d,v,t", AT
, AT
, GP
);
5785 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5786 ((bfd_arch_bits_per_address (stdoutput
) == 32
5787 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5789 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5790 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5792 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5793 ((bfd_arch_bits_per_address (stdoutput
) == 32
5794 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5795 ? "addu" : "daddu"),
5796 "d,v,t", AT
, breg
, AT
);
5797 /* Itbl support may require additional care here. */
5798 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5799 coproc
? treg
+ 1 : treg
,
5800 (int) BFD_RELOC_LO16
, AT
);
5801 expr1
.X_add_number
+= 4;
5803 /* Set mips_optimize to 2 to avoid inserting an undesired
5805 hold_mips_optimize
= mips_optimize
;
5807 /* Itbl support may require additional care here. */
5808 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5809 coproc
? treg
: treg
+ 1,
5810 (int) BFD_RELOC_LO16
, AT
);
5811 mips_optimize
= hold_mips_optimize
;
5812 expr1
.X_add_number
-= 4;
5814 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5815 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5816 8 + gpdel
+ off
, 1, 0),
5817 offset_expr
.X_add_symbol
, (offsetT
) 0,
5821 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5824 macro_build (p
, &icnt
, &offset_expr
,
5825 ((bfd_arch_bits_per_address (stdoutput
) == 32
5826 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5828 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5830 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5834 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5835 ((bfd_arch_bits_per_address (stdoutput
) == 32
5836 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5837 ? "addu" : "daddu"),
5838 "d,v,t", AT
, breg
, AT
);
5841 /* Itbl support may require additional care here. */
5842 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5843 coproc
? treg
+ 1 : treg
,
5844 (int) BFD_RELOC_LO16
, AT
);
5846 expr1
.X_add_number
+= 4;
5848 /* Set mips_optimize to 2 to avoid inserting an undesired
5850 hold_mips_optimize
= mips_optimize
;
5852 /* Itbl support may require additional care here. */
5853 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5854 coproc
? treg
: treg
+ 1,
5855 (int) BFD_RELOC_LO16
, AT
);
5856 mips_optimize
= hold_mips_optimize
;
5858 else if (mips_pic
== EMBEDDED_PIC
)
5860 /* If there is no base register, we use
5861 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5862 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5863 If we have a base register, we use
5865 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5866 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5875 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5876 ((bfd_arch_bits_per_address (stdoutput
) == 32
5877 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5878 ? "addu" : "daddu"),
5879 "d,v,t", AT
, breg
, GP
);
5884 /* Itbl support may require additional care here. */
5885 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5886 coproc
? treg
+ 1 : treg
,
5887 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5888 offset_expr
.X_add_number
+= 4;
5889 /* Itbl support may require additional care here. */
5890 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5891 coproc
? treg
: treg
+ 1,
5892 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5908 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5909 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5910 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5911 (int) BFD_RELOC_LO16
, breg
);
5912 offset_expr
.X_add_number
+= 4;
5913 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5914 (int) BFD_RELOC_LO16
, breg
);
5917 /* New code added to support COPZ instructions.
5918 This code builds table entries out of the macros in mip_opcodes.
5919 R4000 uses interlocks to handle coproc delays.
5920 Other chips (like the R3000) require nops to be inserted for delays.
5922 FIXME: Currently, we require that the user handle delays.
5923 In order to fill delay slots for non-interlocked chips,
5924 we must have a way to specify delays based on the coprocessor.
5925 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5926 What are the side-effects of the cop instruction?
5927 What cache support might we have and what are its effects?
5928 Both coprocessor & memory require delays. how long???
5929 What registers are read/set/modified?
5931 If an itbl is provided to interpret cop instructions,
5932 this knowledge can be encoded in the itbl spec. */
5946 /* For now we just do C (same as Cz). The parameter will be
5947 stored in insn_opcode by mips_ip. */
5948 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5952 #ifdef LOSING_COMPILER
5954 /* Try and see if this is a new itbl instruction.
5955 This code builds table entries out of the macros in mip_opcodes.
5956 FIXME: For now we just assemble the expression and pass it's
5957 value along as a 32-bit immediate.
5958 We may want to have the assembler assemble this value,
5959 so that we gain the assembler's knowledge of delay slots,
5961 Would it be more efficient to use mask (id) here? */
5962 if (itbl_have_entries
5963 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5965 s
= ip
->insn_mo
->name
;
5967 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5968 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5975 as_warn (_("Macro used $at after \".set noat\""));
5980 struct mips_cl_insn
*ip
;
5982 register int treg
, sreg
, dreg
, breg
;
5998 bfd_reloc_code_real_type r
;
6001 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6002 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6003 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6004 mask
= ip
->insn_mo
->mask
;
6006 expr1
.X_op
= O_constant
;
6007 expr1
.X_op_symbol
= NULL
;
6008 expr1
.X_add_symbol
= NULL
;
6009 expr1
.X_add_number
= 1;
6013 #endif /* LOSING_COMPILER */
6018 macro_build ((char *) NULL
, &icnt
, NULL
,
6019 dbl
? "dmultu" : "multu",
6021 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6027 /* The MIPS assembler some times generates shifts and adds. I'm
6028 not trying to be that fancy. GCC should do this for us
6030 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6031 macro_build ((char *) NULL
, &icnt
, NULL
,
6032 dbl
? "dmult" : "mult",
6034 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6047 mips_emit_delays (true);
6048 ++mips_opts
.noreorder
;
6049 mips_any_noreorder
= 1;
6051 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6052 macro_build ((char *) NULL
, &icnt
, NULL
,
6053 dbl
? "dmult" : "mult",
6054 "s,t", sreg
, imm
? AT
: treg
);
6055 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6056 macro_build ((char *) NULL
, &icnt
, NULL
,
6057 dbl
? "dsra32" : "sra",
6058 "d,w,<", dreg
, dreg
, 31);
6059 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6061 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6064 expr1
.X_add_number
= 8;
6065 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6066 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6067 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6069 --mips_opts
.noreorder
;
6070 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6083 mips_emit_delays (true);
6084 ++mips_opts
.noreorder
;
6085 mips_any_noreorder
= 1;
6087 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6088 macro_build ((char *) NULL
, &icnt
, NULL
,
6089 dbl
? "dmultu" : "multu",
6090 "s,t", sreg
, imm
? AT
: treg
);
6091 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6092 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6094 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6097 expr1
.X_add_number
= 8;
6098 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6099 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6100 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6102 --mips_opts
.noreorder
;
6106 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6107 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6108 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6110 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6114 if (imm_expr
.X_op
!= O_constant
)
6115 as_bad (_("rotate count too large"));
6116 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6117 (int) (imm_expr
.X_add_number
& 0x1f));
6118 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6119 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6120 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6124 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6125 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6126 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6128 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6132 if (imm_expr
.X_op
!= O_constant
)
6133 as_bad (_("rotate count too large"));
6134 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6135 (int) (imm_expr
.X_add_number
& 0x1f));
6136 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6137 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6138 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6142 if (mips_cpu
== CPU_R4650
)
6144 as_bad (_("opcode not supported on this processor"));
6147 assert (mips_opts
.isa
== 1);
6148 /* Even on a big endian machine $fn comes before $fn+1. We have
6149 to adjust when storing to memory. */
6150 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6151 target_big_endian
? treg
+ 1 : treg
,
6152 (int) BFD_RELOC_LO16
, breg
);
6153 offset_expr
.X_add_number
+= 4;
6154 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6155 target_big_endian
? treg
: treg
+ 1,
6156 (int) BFD_RELOC_LO16
, breg
);
6161 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6162 treg
, (int) BFD_RELOC_LO16
);
6164 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6165 sreg
, (int) BFD_RELOC_LO16
);
6168 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6170 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6171 dreg
, (int) BFD_RELOC_LO16
);
6176 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6178 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6179 sreg
, (int) BFD_RELOC_LO16
);
6184 as_warn (_("Instruction %s: result is always false"),
6186 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6189 if (imm_expr
.X_op
== O_constant
6190 && imm_expr
.X_add_number
>= 0
6191 && imm_expr
.X_add_number
< 0x10000)
6193 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6194 sreg
, (int) BFD_RELOC_LO16
);
6197 else if (imm_expr
.X_op
== O_constant
6198 && imm_expr
.X_add_number
> -0x8000
6199 && imm_expr
.X_add_number
< 0)
6201 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6202 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6203 ((bfd_arch_bits_per_address (stdoutput
) == 32
6204 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6205 ? "addiu" : "daddiu"),
6206 "t,r,j", dreg
, sreg
,
6207 (int) BFD_RELOC_LO16
);
6212 load_register (&icnt
, AT
, &imm_expr
, 0);
6213 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6217 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6218 (int) BFD_RELOC_LO16
);
6223 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6229 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6230 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6231 (int) BFD_RELOC_LO16
);
6234 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6236 if (imm_expr
.X_op
== O_constant
6237 && imm_expr
.X_add_number
>= -0x8000
6238 && imm_expr
.X_add_number
< 0x8000)
6240 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6241 mask
== M_SGE_I
? "slti" : "sltiu",
6242 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6247 load_register (&icnt
, AT
, &imm_expr
, 0);
6248 macro_build ((char *) NULL
, &icnt
, NULL
,
6249 mask
== M_SGE_I
? "slt" : "sltu",
6250 "d,v,t", dreg
, sreg
, AT
);
6253 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6254 (int) BFD_RELOC_LO16
);
6259 case M_SGT
: /* sreg > treg <==> treg < sreg */
6265 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6268 case M_SGT_I
: /* sreg > I <==> I < sreg */
6274 load_register (&icnt
, AT
, &imm_expr
, 0);
6275 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6278 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6284 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6285 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6286 (int) BFD_RELOC_LO16
);
6289 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6295 load_register (&icnt
, AT
, &imm_expr
, 0);
6296 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6297 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6298 (int) BFD_RELOC_LO16
);
6302 if (imm_expr
.X_op
== O_constant
6303 && imm_expr
.X_add_number
>= -0x8000
6304 && imm_expr
.X_add_number
< 0x8000)
6306 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6307 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6310 load_register (&icnt
, AT
, &imm_expr
, 0);
6311 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6315 if (imm_expr
.X_op
== O_constant
6316 && imm_expr
.X_add_number
>= -0x8000
6317 && imm_expr
.X_add_number
< 0x8000)
6319 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6320 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6323 load_register (&icnt
, AT
, &imm_expr
, 0);
6324 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6330 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6333 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6337 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6339 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6345 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6347 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6353 as_warn (_("Instruction %s: result is always true"),
6355 macro_build ((char *) NULL
, &icnt
, &expr1
,
6356 ((bfd_arch_bits_per_address (stdoutput
) == 32
6357 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6358 ? "addiu" : "daddiu"),
6359 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6362 if (imm_expr
.X_op
== O_constant
6363 && imm_expr
.X_add_number
>= 0
6364 && imm_expr
.X_add_number
< 0x10000)
6366 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6367 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6370 else if (imm_expr
.X_op
== O_constant
6371 && imm_expr
.X_add_number
> -0x8000
6372 && imm_expr
.X_add_number
< 0)
6374 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6375 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6376 ((bfd_arch_bits_per_address (stdoutput
) == 32
6377 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6378 ? "addiu" : "daddiu"),
6379 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6384 load_register (&icnt
, AT
, &imm_expr
, 0);
6385 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6389 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6397 if (imm_expr
.X_op
== O_constant
6398 && imm_expr
.X_add_number
> -0x8000
6399 && imm_expr
.X_add_number
<= 0x8000)
6401 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6402 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6403 dbl
? "daddi" : "addi",
6404 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6407 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6408 macro_build ((char *) NULL
, &icnt
, NULL
,
6409 dbl
? "dsub" : "sub",
6410 "d,v,t", dreg
, sreg
, AT
);
6416 if (imm_expr
.X_op
== O_constant
6417 && imm_expr
.X_add_number
> -0x8000
6418 && imm_expr
.X_add_number
<= 0x8000)
6420 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6421 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6422 dbl
? "daddiu" : "addiu",
6423 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6426 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6427 macro_build ((char *) NULL
, &icnt
, NULL
,
6428 dbl
? "dsubu" : "subu",
6429 "d,v,t", dreg
, sreg
, AT
);
6450 load_register (&icnt
, AT
, &imm_expr
, 0);
6451 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6456 assert (mips_opts
.isa
== 1);
6457 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6458 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6461 * Is the double cfc1 instruction a bug in the mips assembler;
6462 * or is there a reason for it?
6464 mips_emit_delays (true);
6465 ++mips_opts
.noreorder
;
6466 mips_any_noreorder
= 1;
6467 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6468 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6469 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6470 expr1
.X_add_number
= 3;
6471 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6472 (int) BFD_RELOC_LO16
);
6473 expr1
.X_add_number
= 2;
6474 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6475 (int) BFD_RELOC_LO16
);
6476 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6477 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6478 macro_build ((char *) NULL
, &icnt
, NULL
,
6479 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6480 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6481 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6482 --mips_opts
.noreorder
;
6491 if (offset_expr
.X_add_number
>= 0x7fff)
6492 as_bad (_("operand overflow"));
6493 /* avoid load delay */
6494 if (! target_big_endian
)
6495 offset_expr
.X_add_number
+= 1;
6496 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6497 (int) BFD_RELOC_LO16
, breg
);
6498 if (! target_big_endian
)
6499 offset_expr
.X_add_number
-= 1;
6501 offset_expr
.X_add_number
+= 1;
6502 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6503 (int) BFD_RELOC_LO16
, breg
);
6504 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6505 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6518 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6519 as_bad (_("operand overflow"));
6520 if (! target_big_endian
)
6521 offset_expr
.X_add_number
+= off
;
6522 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6523 (int) BFD_RELOC_LO16
, breg
);
6524 if (! target_big_endian
)
6525 offset_expr
.X_add_number
-= off
;
6527 offset_expr
.X_add_number
+= off
;
6528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6529 (int) BFD_RELOC_LO16
, breg
);
6542 load_address (&icnt
, AT
, &offset_expr
);
6544 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6545 ((bfd_arch_bits_per_address (stdoutput
) == 32
6546 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6547 ? "addu" : "daddu"),
6548 "d,v,t", AT
, AT
, breg
);
6549 if (! target_big_endian
)
6550 expr1
.X_add_number
= off
;
6552 expr1
.X_add_number
= 0;
6553 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6554 (int) BFD_RELOC_LO16
, AT
);
6555 if (! target_big_endian
)
6556 expr1
.X_add_number
= 0;
6558 expr1
.X_add_number
= off
;
6559 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6560 (int) BFD_RELOC_LO16
, AT
);
6565 load_address (&icnt
, AT
, &offset_expr
);
6567 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6568 ((bfd_arch_bits_per_address (stdoutput
) == 32
6569 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6570 ? "addu" : "daddu"),
6571 "d,v,t", AT
, AT
, breg
);
6572 if (target_big_endian
)
6573 expr1
.X_add_number
= 0;
6574 macro_build ((char *) NULL
, &icnt
, &expr1
,
6575 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6576 (int) BFD_RELOC_LO16
, AT
);
6577 if (target_big_endian
)
6578 expr1
.X_add_number
= 1;
6580 expr1
.X_add_number
= 0;
6581 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6582 (int) BFD_RELOC_LO16
, AT
);
6583 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6585 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6590 if (offset_expr
.X_add_number
>= 0x7fff)
6591 as_bad (_("operand overflow"));
6592 if (target_big_endian
)
6593 offset_expr
.X_add_number
+= 1;
6594 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6595 (int) BFD_RELOC_LO16
, breg
);
6596 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6597 if (target_big_endian
)
6598 offset_expr
.X_add_number
-= 1;
6600 offset_expr
.X_add_number
+= 1;
6601 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6602 (int) BFD_RELOC_LO16
, breg
);
6615 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6616 as_bad (_("operand overflow"));
6617 if (! target_big_endian
)
6618 offset_expr
.X_add_number
+= off
;
6619 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6620 (int) BFD_RELOC_LO16
, breg
);
6621 if (! target_big_endian
)
6622 offset_expr
.X_add_number
-= off
;
6624 offset_expr
.X_add_number
+= off
;
6625 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6626 (int) BFD_RELOC_LO16
, breg
);
6639 load_address (&icnt
, AT
, &offset_expr
);
6641 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6642 ((bfd_arch_bits_per_address (stdoutput
) == 32
6643 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6644 ? "addu" : "daddu"),
6645 "d,v,t", AT
, AT
, breg
);
6646 if (! target_big_endian
)
6647 expr1
.X_add_number
= off
;
6649 expr1
.X_add_number
= 0;
6650 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6651 (int) BFD_RELOC_LO16
, AT
);
6652 if (! target_big_endian
)
6653 expr1
.X_add_number
= 0;
6655 expr1
.X_add_number
= off
;
6656 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6657 (int) BFD_RELOC_LO16
, AT
);
6661 load_address (&icnt
, AT
, &offset_expr
);
6663 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6664 ((bfd_arch_bits_per_address (stdoutput
) == 32
6665 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6666 ? "addu" : "daddu"),
6667 "d,v,t", AT
, AT
, breg
);
6668 if (! target_big_endian
)
6669 expr1
.X_add_number
= 0;
6670 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6671 (int) BFD_RELOC_LO16
, AT
);
6672 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6674 if (! target_big_endian
)
6675 expr1
.X_add_number
= 1;
6677 expr1
.X_add_number
= 0;
6678 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6679 (int) BFD_RELOC_LO16
, AT
);
6680 if (! target_big_endian
)
6681 expr1
.X_add_number
= 0;
6683 expr1
.X_add_number
= 1;
6684 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6685 (int) BFD_RELOC_LO16
, AT
);
6686 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6688 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6693 /* FIXME: Check if this is one of the itbl macros, since they
6694 are added dynamically. */
6695 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6699 as_warn (_("Macro used $at after \".set noat\""));
6702 /* Implement macros in mips16 mode. */
6706 struct mips_cl_insn
*ip
;
6709 int xreg
, yreg
, zreg
, tmp
;
6713 const char *s
, *s2
, *s3
;
6715 mask
= ip
->insn_mo
->mask
;
6717 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6718 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6719 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6723 expr1
.X_op
= O_constant
;
6724 expr1
.X_op_symbol
= NULL
;
6725 expr1
.X_add_symbol
= NULL
;
6726 expr1
.X_add_number
= 1;
6745 mips_emit_delays (true);
6746 ++mips_opts
.noreorder
;
6747 mips_any_noreorder
= 1;
6748 macro_build ((char *) NULL
, &icnt
, NULL
,
6749 dbl
? "ddiv" : "div",
6750 "0,x,y", xreg
, yreg
);
6751 expr1
.X_add_number
= 2;
6752 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6753 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6755 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6756 since that causes an overflow. We should do that as well,
6757 but I don't see how to do the comparisons without a temporary
6759 --mips_opts
.noreorder
;
6760 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6779 mips_emit_delays (true);
6780 ++mips_opts
.noreorder
;
6781 mips_any_noreorder
= 1;
6782 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6783 expr1
.X_add_number
= 2;
6784 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6785 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6786 --mips_opts
.noreorder
;
6787 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6793 macro_build ((char *) NULL
, &icnt
, NULL
,
6794 dbl
? "dmultu" : "multu",
6796 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6804 if (imm_expr
.X_op
!= O_constant
)
6805 as_bad (_("Unsupported large constant"));
6806 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6807 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6808 dbl
? "daddiu" : "addiu",
6809 "y,x,4", yreg
, xreg
);
6813 if (imm_expr
.X_op
!= O_constant
)
6814 as_bad (_("Unsupported large constant"));
6815 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6816 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6821 if (imm_expr
.X_op
!= O_constant
)
6822 as_bad (_("Unsupported large constant"));
6823 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6824 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6847 goto do_reverse_branch
;
6851 goto do_reverse_branch
;
6863 goto do_reverse_branch
;
6874 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6876 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6903 goto do_addone_branch_i
;
6908 goto do_addone_branch_i
;
6923 goto do_addone_branch_i
;
6930 if (imm_expr
.X_op
!= O_constant
)
6931 as_bad (_("Unsupported large constant"));
6932 ++imm_expr
.X_add_number
;
6935 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6936 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6940 expr1
.X_add_number
= 0;
6941 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6943 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6944 "move", "y,X", xreg
, yreg
);
6945 expr1
.X_add_number
= 2;
6946 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6947 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6948 "neg", "x,w", xreg
, xreg
);
6952 /* For consistency checking, verify that all bits are specified either
6953 by the match/mask part of the instruction definition, or by the
6956 validate_mips_insn (opc
)
6957 const struct mips_opcode
*opc
;
6959 const char *p
= opc
->args
;
6961 unsigned long used_bits
= opc
->mask
;
6963 if ((used_bits
& opc
->match
) != opc
->match
)
6965 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6966 opc
->name
, opc
->args
);
6969 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6976 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6977 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6979 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6980 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6981 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6982 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6984 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6985 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
6988 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6989 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6990 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6991 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6992 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6993 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6994 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6995 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6996 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6997 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6998 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7000 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7001 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7002 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7003 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7005 case 'm': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7006 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7007 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7008 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7009 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7010 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7011 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7012 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7013 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7014 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7017 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7019 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7020 c
, opc
->name
, opc
->args
);
7024 if (used_bits
!= 0xffffffff)
7026 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7027 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7033 /* This routine assembles an instruction into its binary format. As a
7034 side effect, it sets one of the global variables imm_reloc or
7035 offset_reloc to the type of relocation to do if one of the operands
7036 is an address expression. */
7041 struct mips_cl_insn
*ip
;
7046 struct mips_opcode
*insn
;
7049 unsigned int lastregno
= 0;
7052 int full_opcode_match
= 1;
7056 /* If the instruction contains a '.', we first try to match an instruction
7057 including the '.'. Then we try again without the '.'. */
7059 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
7062 /* If we stopped on whitespace, then replace the whitespace with null for
7063 the call to hash_find. Save the character we replaced just in case we
7064 have to re-parse the instruction. */
7065 if (isspace ((unsigned char) *s
))
7071 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7073 /* If we didn't find the instruction in the opcode table, try again, but
7074 this time with just the instruction up to, but not including the
7078 /* Restore the character we overwrite above (if any). */
7082 /* Scan up to the first '.' or whitespace. */
7083 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7086 /* If we did not find a '.', then we can quit now. */
7089 insn_error
= "unrecognized opcode";
7093 /* Lookup the instruction in the hash table. */
7095 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7097 insn_error
= "unrecognized opcode";
7101 full_opcode_match
= 0;
7109 assert (strcmp (insn
->name
, str
) == 0);
7111 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7116 if (insn
->pinfo
!= INSN_MACRO
)
7118 if (mips_cpu
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7124 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7125 && strcmp (insn
->name
, insn
[1].name
) == 0)
7132 static char buf
[100];
7134 _("opcode not supported on this processor: %s (MIPS%d)"),
7135 mips_cpu_to_str (mips_cpu
), mips_opts
.isa
);
7143 ip
->insn_opcode
= insn
->match
;
7144 for (args
= insn
->args
;; ++args
)
7150 case '\0': /* end of args */
7163 ip
->insn_opcode
|= lastregno
<< 21;
7168 ip
->insn_opcode
|= lastregno
<< 16;
7172 ip
->insn_opcode
|= lastregno
<< 11;
7178 /* Handle optional base register.
7179 Either the base register is omitted or
7180 we must have a left paren. */
7181 /* This is dependent on the next operand specifier
7182 is a base register specification. */
7183 assert (args
[1] == 'b' || args
[1] == '5'
7184 || args
[1] == '-' || args
[1] == '4');
7188 case ')': /* these must match exactly */
7193 case '<': /* must be at least one digit */
7195 * According to the manual, if the shift amount is greater
7196 * than 31 or less than 0 the the shift amount should be
7197 * mod 32. In reality the mips assembler issues an error.
7198 * We issue a warning and mask out all but the low 5 bits.
7200 my_getExpression (&imm_expr
, s
);
7201 check_absolute_expr (ip
, &imm_expr
);
7202 if ((unsigned long) imm_expr
.X_add_number
> 31)
7204 as_warn (_("Improper shift amount (%ld)"),
7205 (long) imm_expr
.X_add_number
);
7206 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7208 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7209 imm_expr
.X_op
= O_absent
;
7213 case '>': /* shift amount minus 32 */
7214 my_getExpression (&imm_expr
, s
);
7215 check_absolute_expr (ip
, &imm_expr
);
7216 if ((unsigned long) imm_expr
.X_add_number
< 32
7217 || (unsigned long) imm_expr
.X_add_number
> 63)
7219 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7220 imm_expr
.X_op
= O_absent
;
7224 case 'k': /* cache code */
7225 case 'h': /* prefx code */
7226 my_getExpression (&imm_expr
, s
);
7227 check_absolute_expr (ip
, &imm_expr
);
7228 if ((unsigned long) imm_expr
.X_add_number
> 31)
7230 as_warn (_("Invalid value for `%s' (%lu)"),
7232 (unsigned long) imm_expr
.X_add_number
);
7233 imm_expr
.X_add_number
&= 0x1f;
7236 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7238 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7239 imm_expr
.X_op
= O_absent
;
7243 case 'c': /* break code */
7244 my_getExpression (&imm_expr
, s
);
7245 check_absolute_expr (ip
, &imm_expr
);
7246 if ((unsigned) imm_expr
.X_add_number
> 1023)
7248 as_warn (_("Illegal break code (%ld)"),
7249 (long) imm_expr
.X_add_number
);
7250 imm_expr
.X_add_number
&= 0x3ff;
7252 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7253 imm_expr
.X_op
= O_absent
;
7257 case 'q': /* lower break code */
7258 my_getExpression (&imm_expr
, s
);
7259 check_absolute_expr (ip
, &imm_expr
);
7260 if ((unsigned) imm_expr
.X_add_number
> 1023)
7262 as_warn (_("Illegal lower break code (%ld)"),
7263 (long) imm_expr
.X_add_number
);
7264 imm_expr
.X_add_number
&= 0x3ff;
7266 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7267 imm_expr
.X_op
= O_absent
;
7271 case 'm': /* Full 20 bit break code. */
7272 my_getExpression (&imm_expr
, s
);
7274 check_absolute_expr (ip
, &imm_expr
);
7276 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7278 as_warn (_("Illegal break code (%ld)"),
7279 (long) imm_expr
.X_add_number
);
7280 imm_expr
.X_add_number
&= 0xfffff;
7283 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7284 imm_expr
.X_op
= O_absent
;
7289 case 'B': /* syscall code */
7290 my_getExpression (&imm_expr
, s
);
7291 check_absolute_expr (ip
, &imm_expr
);
7292 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7293 as_warn (_("Illegal syscall code (%ld)"),
7294 (long) imm_expr
.X_add_number
);
7295 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7296 imm_expr
.X_op
= O_absent
;
7300 case 'C': /* Coprocessor code */
7301 my_getExpression (&imm_expr
, s
);
7302 check_absolute_expr (ip
, &imm_expr
);
7303 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7305 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7306 (long) imm_expr
.X_add_number
);
7307 imm_expr
.X_add_number
&= ((1<<25) - 1);
7309 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7310 imm_expr
.X_op
= O_absent
;
7314 case 'P': /* Performance register */
7315 my_getExpression (&imm_expr
, s
);
7316 check_absolute_expr (ip
, &imm_expr
);
7317 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7319 as_warn (_("Invalidate performance regster (%ld)"),
7320 (long) imm_expr
.X_add_number
);
7321 imm_expr
.X_add_number
&= 1;
7323 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7324 imm_expr
.X_op
= O_absent
;
7328 case 'b': /* base register */
7329 case 'd': /* destination register */
7330 case 's': /* source register */
7331 case 't': /* target register */
7332 case 'r': /* both target and source */
7333 case 'v': /* both dest and source */
7334 case 'w': /* both dest and target */
7335 case 'E': /* coprocessor target register */
7336 case 'G': /* coprocessor destination register */
7337 case 'x': /* ignore register name */
7338 case 'z': /* must be zero register */
7343 if (isdigit ((unsigned char) s
[1]))
7353 while (isdigit ((unsigned char) *s
));
7355 as_bad (_("Invalid register number (%d)"), regno
);
7357 else if (*args
== 'E' || *args
== 'G')
7361 if (s
[1] == 'f' && s
[2] == 'p')
7366 else if (s
[1] == 's' && s
[2] == 'p')
7371 else if (s
[1] == 'g' && s
[2] == 'p')
7376 else if (s
[1] == 'a' && s
[2] == 't')
7381 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7386 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7391 else if (itbl_have_entries
)
7396 p
= s
+ 1; /* advance past '$' */
7397 n
= itbl_get_field (&p
); /* n is name */
7399 /* See if this is a register defined in an
7401 if (itbl_get_reg_val (n
, &r
))
7403 /* Get_field advances to the start of
7404 the next field, so we need to back
7405 rack to the end of the last field. */
7409 s
= strchr (s
, '\0');
7422 as_warn (_("Used $at without \".set noat\""));
7428 if (c
== 'r' || c
== 'v' || c
== 'w')
7435 /* 'z' only matches $0. */
7436 if (c
== 'z' && regno
!= 0)
7439 /* Now that we have assembled one operand, we use the args string
7440 * to figure out where it goes in the instruction. */
7447 ip
->insn_opcode
|= regno
<< 21;
7451 ip
->insn_opcode
|= regno
<< 11;
7456 ip
->insn_opcode
|= regno
<< 16;
7459 /* This case exists because on the r3000 trunc
7460 expands into a macro which requires a gp
7461 register. On the r6000 or r4000 it is
7462 assembled into a single instruction which
7463 ignores the register. Thus the insn version
7464 is MIPS_ISA2 and uses 'x', and the macro
7465 version is MIPS_ISA1 and uses 't'. */
7468 /* This case is for the div instruction, which
7469 acts differently if the destination argument
7470 is $0. This only matches $0, and is checked
7471 outside the switch. */
7474 /* Itbl operand; not yet implemented. FIXME ?? */
7476 /* What about all other operands like 'i', which
7477 can be specified in the opcode table? */
7487 ip
->insn_opcode
|= lastregno
<< 21;
7490 ip
->insn_opcode
|= lastregno
<< 16;
7495 case 'D': /* floating point destination register */
7496 case 'S': /* floating point source register */
7497 case 'T': /* floating point target register */
7498 case 'R': /* floating point source register */
7502 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7512 while (isdigit ((unsigned char) *s
));
7515 as_bad (_("Invalid float register number (%d)"), regno
);
7517 if ((regno
& 1) != 0
7518 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7519 && ! (strcmp (str
, "mtc1") == 0
7520 || strcmp (str
, "mfc1") == 0
7521 || strcmp (str
, "lwc1") == 0
7522 || strcmp (str
, "swc1") == 0
7523 || strcmp (str
, "l.s") == 0
7524 || strcmp (str
, "s.s") == 0))
7525 as_warn (_("Float register should be even, was %d"),
7533 if (c
== 'V' || c
== 'W')
7543 ip
->insn_opcode
|= regno
<< 6;
7547 ip
->insn_opcode
|= regno
<< 11;
7551 ip
->insn_opcode
|= regno
<< 16;
7554 ip
->insn_opcode
|= regno
<< 21;
7564 ip
->insn_opcode
|= lastregno
<< 11;
7567 ip
->insn_opcode
|= lastregno
<< 16;
7573 my_getExpression (&imm_expr
, s
);
7574 if (imm_expr
.X_op
!= O_big
7575 && imm_expr
.X_op
!= O_constant
)
7576 insn_error
= _("absolute expression required");
7581 my_getExpression (&offset_expr
, s
);
7582 imm_reloc
= BFD_RELOC_32
;
7594 unsigned char temp
[8];
7596 unsigned int length
;
7601 /* These only appear as the last operand in an
7602 instruction, and every instruction that accepts
7603 them in any variant accepts them in all variants.
7604 This means we don't have to worry about backing out
7605 any changes if the instruction does not match.
7607 The difference between them is the size of the
7608 floating point constant and where it goes. For 'F'
7609 and 'L' the constant is 64 bits; for 'f' and 'l' it
7610 is 32 bits. Where the constant is placed is based
7611 on how the MIPS assembler does things:
7614 f -- immediate value
7617 The .lit4 and .lit8 sections are only used if
7618 permitted by the -G argument.
7620 When generating embedded PIC code, we use the
7621 .lit8 section but not the .lit4 section (we can do
7622 .lit4 inline easily; we need to put .lit8
7623 somewhere in the data segment, and using .lit8
7624 permits the linker to eventually combine identical
7627 f64
= *args
== 'F' || *args
== 'L';
7629 save_in
= input_line_pointer
;
7630 input_line_pointer
= s
;
7631 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7633 s
= input_line_pointer
;
7634 input_line_pointer
= save_in
;
7635 if (err
!= NULL
&& *err
!= '\0')
7637 as_bad (_("Bad floating point constant: %s"), err
);
7638 memset (temp
, '\0', sizeof temp
);
7639 length
= f64
? 8 : 4;
7642 assert (length
== (unsigned) (f64
? 8 : 4));
7646 && (! USE_GLOBAL_POINTER_OPT
7647 || mips_pic
== EMBEDDED_PIC
7648 || g_switch_value
< 4
7649 || (temp
[0] == 0 && temp
[1] == 0)
7650 || (temp
[2] == 0 && temp
[3] == 0))))
7652 imm_expr
.X_op
= O_constant
;
7653 if (! target_big_endian
)
7654 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7656 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7659 && ! mips_disable_float_construction
7660 && ((temp
[0] == 0 && temp
[1] == 0)
7661 || (temp
[2] == 0 && temp
[3] == 0))
7662 && ((temp
[4] == 0 && temp
[5] == 0)
7663 || (temp
[6] == 0 && temp
[7] == 0)))
7665 /* The value is simple enough to load with a
7666 couple of instructions. In mips1 mode, set
7667 imm_expr to the high order 32 bits and
7668 offset_expr to the low order 32 bits.
7669 Otherwise, set imm_expr to the entire 64 bit
7671 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7673 imm_expr
.X_op
= O_constant
;
7674 offset_expr
.X_op
= O_constant
;
7675 if (! target_big_endian
)
7677 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7678 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7682 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7683 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7685 if (offset_expr
.X_add_number
== 0)
7686 offset_expr
.X_op
= O_absent
;
7688 else if (sizeof (imm_expr
.X_add_number
) > 4)
7690 imm_expr
.X_op
= O_constant
;
7691 if (! target_big_endian
)
7692 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7694 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7698 imm_expr
.X_op
= O_big
;
7699 imm_expr
.X_add_number
= 4;
7700 if (! target_big_endian
)
7702 generic_bignum
[0] = bfd_getl16 (temp
);
7703 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7704 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7705 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7709 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7710 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7711 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7712 generic_bignum
[3] = bfd_getb16 (temp
);
7718 const char *newname
;
7721 /* Switch to the right section. */
7723 subseg
= now_subseg
;
7726 default: /* unused default case avoids warnings. */
7728 newname
= RDATA_SECTION_NAME
;
7729 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7730 || mips_pic
== EMBEDDED_PIC
)
7734 if (mips_pic
== EMBEDDED_PIC
)
7737 newname
= RDATA_SECTION_NAME
;
7740 assert (!USE_GLOBAL_POINTER_OPT
7741 || g_switch_value
>= 4);
7745 new_seg
= subseg_new (newname
, (subsegT
) 0);
7746 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7747 bfd_set_section_flags (stdoutput
, new_seg
,
7752 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7753 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7754 && strcmp (TARGET_OS
, "elf") != 0)
7755 record_alignment (new_seg
, 4);
7757 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7759 as_bad (_("Can't use floating point insn in this section"));
7761 /* Set the argument to the current address in the
7763 offset_expr
.X_op
= O_symbol
;
7764 offset_expr
.X_add_symbol
=
7765 symbol_new ("L0\001", now_seg
,
7766 (valueT
) frag_now_fix (), frag_now
);
7767 offset_expr
.X_add_number
= 0;
7769 /* Put the floating point number into the section. */
7770 p
= frag_more ((int) length
);
7771 memcpy (p
, temp
, length
);
7773 /* Switch back to the original section. */
7774 subseg_set (seg
, subseg
);
7779 case 'i': /* 16 bit unsigned immediate */
7780 case 'j': /* 16 bit signed immediate */
7781 imm_reloc
= BFD_RELOC_LO16
;
7782 c
= my_getSmallExpression (&imm_expr
, s
);
7787 if (imm_expr
.X_op
== O_constant
)
7788 imm_expr
.X_add_number
=
7789 (imm_expr
.X_add_number
>> 16) & 0xffff;
7792 imm_reloc
= BFD_RELOC_HI16_S
;
7793 imm_unmatched_hi
= true;
7796 imm_reloc
= BFD_RELOC_HI16
;
7798 else if (imm_expr
.X_op
== O_constant
)
7799 imm_expr
.X_add_number
&= 0xffff;
7803 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7804 || ((imm_expr
.X_add_number
< 0
7805 || imm_expr
.X_add_number
>= 0x10000)
7806 && imm_expr
.X_op
== O_constant
))
7808 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7809 !strcmp (insn
->name
, insn
[1].name
))
7811 if (imm_expr
.X_op
== O_constant
7812 || imm_expr
.X_op
== O_big
)
7813 as_bad (_("16 bit expression not in range 0..65535"));
7821 /* The upper bound should be 0x8000, but
7822 unfortunately the MIPS assembler accepts numbers
7823 from 0x8000 to 0xffff and sign extends them, and
7824 we want to be compatible. We only permit this
7825 extended range for an instruction which does not
7826 provide any further alternates, since those
7827 alternates may handle other cases. People should
7828 use the numbers they mean, rather than relying on
7829 a mysterious sign extension. */
7830 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7831 strcmp (insn
->name
, insn
[1].name
) == 0);
7836 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7837 || ((imm_expr
.X_add_number
< -0x8000
7838 || imm_expr
.X_add_number
>= max
)
7839 && imm_expr
.X_op
== O_constant
)
7841 && imm_expr
.X_add_number
< 0
7842 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7843 && imm_expr
.X_unsigned
7844 && sizeof (imm_expr
.X_add_number
) <= 4))
7848 if (imm_expr
.X_op
== O_constant
7849 || imm_expr
.X_op
== O_big
)
7850 as_bad (_("16 bit expression not in range -32768..32767"));
7856 case 'o': /* 16 bit offset */
7857 c
= my_getSmallExpression (&offset_expr
, s
);
7859 /* If this value won't fit into a 16 bit offset, then go
7860 find a macro that will generate the 32 bit offset
7861 code pattern. As a special hack, we accept the
7862 difference of two local symbols as a constant. This
7863 is required to suppose embedded PIC switches, which
7864 use an instruction which looks like
7865 lw $4,$L12-$LS12($4)
7866 The problem with handling this in a more general
7867 fashion is that the macro function doesn't expect to
7868 see anything which can be handled in a single
7869 constant instruction. */
7871 && (offset_expr
.X_op
!= O_constant
7872 || offset_expr
.X_add_number
>= 0x8000
7873 || offset_expr
.X_add_number
< -0x8000)
7874 && (mips_pic
!= EMBEDDED_PIC
7875 || offset_expr
.X_op
!= O_subtract
7876 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7880 if (c
== 'h' || c
== 'H')
7882 if (offset_expr
.X_op
!= O_constant
)
7884 offset_expr
.X_add_number
=
7885 (offset_expr
.X_add_number
>> 16) & 0xffff;
7887 offset_reloc
= BFD_RELOC_LO16
;
7891 case 'p': /* pc relative offset */
7892 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7893 my_getExpression (&offset_expr
, s
);
7897 case 'u': /* upper 16 bits */
7898 c
= my_getSmallExpression (&imm_expr
, s
);
7899 imm_reloc
= BFD_RELOC_LO16
;
7904 if (imm_expr
.X_op
== O_constant
)
7905 imm_expr
.X_add_number
=
7906 (imm_expr
.X_add_number
>> 16) & 0xffff;
7909 imm_reloc
= BFD_RELOC_HI16_S
;
7910 imm_unmatched_hi
= true;
7913 imm_reloc
= BFD_RELOC_HI16
;
7915 else if (imm_expr
.X_op
== O_constant
)
7916 imm_expr
.X_add_number
&= 0xffff;
7918 if (imm_expr
.X_op
== O_constant
7919 && (imm_expr
.X_add_number
< 0
7920 || imm_expr
.X_add_number
>= 0x10000))
7921 as_bad (_("lui expression not in range 0..65535"));
7925 case 'a': /* 26 bit address */
7926 my_getExpression (&offset_expr
, s
);
7928 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7931 case 'N': /* 3 bit branch condition code */
7932 case 'M': /* 3 bit compare condition code */
7933 if (strncmp (s
, "$fcc", 4) != 0)
7943 while (isdigit ((unsigned char) *s
));
7945 as_bad (_("invalid condition code register $fcc%d"), regno
);
7947 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7949 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7953 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
7955 if (isdigit ((unsigned char) *s
))
7964 while (isdigit ((unsigned char) *s
));
7967 c
= 8; /* Invalid sel value. */
7970 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
7971 ip
->insn_opcode
|= c
;
7975 as_bad (_("bad char = '%c'\n"), *args
);
7980 /* Args don't match. */
7981 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7982 !strcmp (insn
->name
, insn
[1].name
))
7988 insn_error
= _("illegal operands");
7993 /* This routine assembles an instruction into its binary format when
7994 assembling for the mips16. As a side effect, it sets one of the
7995 global variables imm_reloc or offset_reloc to the type of
7996 relocation to do if one of the operands is an address expression.
7997 It also sets mips16_small and mips16_ext if the user explicitly
7998 requested a small or extended instruction. */
8003 struct mips_cl_insn
*ip
;
8007 struct mips_opcode
*insn
;
8010 unsigned int lastregno
= 0;
8015 mips16_small
= false;
8018 for (s
= str
; islower ((unsigned char) *s
); ++s
)
8030 if (s
[1] == 't' && s
[2] == ' ')
8033 mips16_small
= true;
8037 else if (s
[1] == 'e' && s
[2] == ' ')
8046 insn_error
= _("unknown opcode");
8050 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8051 mips16_small
= true;
8053 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8055 insn_error
= _("unrecognized opcode");
8062 assert (strcmp (insn
->name
, str
) == 0);
8065 ip
->insn_opcode
= insn
->match
;
8066 ip
->use_extend
= false;
8067 imm_expr
.X_op
= O_absent
;
8068 imm_reloc
= BFD_RELOC_UNUSED
;
8069 offset_expr
.X_op
= O_absent
;
8070 offset_reloc
= BFD_RELOC_UNUSED
;
8071 for (args
= insn
->args
; 1; ++args
)
8078 /* In this switch statement we call break if we did not find
8079 a match, continue if we did find a match, or return if we
8088 /* Stuff the immediate value in now, if we can. */
8089 if (imm_expr
.X_op
== O_constant
8090 && imm_reloc
> BFD_RELOC_UNUSED
8091 && insn
->pinfo
!= INSN_MACRO
)
8093 mips16_immed ((char *) NULL
, 0,
8094 imm_reloc
- BFD_RELOC_UNUSED
,
8095 imm_expr
.X_add_number
, true, mips16_small
,
8096 mips16_ext
, &ip
->insn_opcode
,
8097 &ip
->use_extend
, &ip
->extend
);
8098 imm_expr
.X_op
= O_absent
;
8099 imm_reloc
= BFD_RELOC_UNUSED
;
8113 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8116 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8132 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8134 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8151 if (isdigit ((unsigned char) s
[1]))
8161 while (isdigit ((unsigned char) *s
));
8164 as_bad (_("invalid register number (%d)"), regno
);
8170 if (s
[1] == 'f' && s
[2] == 'p')
8175 else if (s
[1] == 's' && s
[2] == 'p')
8180 else if (s
[1] == 'g' && s
[2] == 'p')
8185 else if (s
[1] == 'a' && s
[2] == 't')
8190 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8195 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8208 if (c
== 'v' || c
== 'w')
8210 regno
= mips16_to_32_reg_map
[lastregno
];
8224 regno
= mips32_to_16_reg_map
[regno
];
8229 regno
= ILLEGAL_REG
;
8234 regno
= ILLEGAL_REG
;
8239 regno
= ILLEGAL_REG
;
8244 if (regno
== AT
&& ! mips_opts
.noat
)
8245 as_warn (_("used $at without \".set noat\""));
8252 if (regno
== ILLEGAL_REG
)
8259 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8263 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8266 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8269 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8275 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8278 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8279 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8289 if (strncmp (s
, "$pc", 3) == 0)
8313 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8315 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8316 and generate the appropriate reloc. If the text
8317 inside %gprel is not a symbol name with an
8318 optional offset, then we generate a normal reloc
8319 and will probably fail later. */
8320 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8321 if (imm_expr
.X_op
== O_symbol
)
8324 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8326 ip
->use_extend
= true;
8333 /* Just pick up a normal expression. */
8334 my_getExpression (&imm_expr
, s
);
8337 if (imm_expr
.X_op
== O_register
)
8339 /* What we thought was an expression turned out to
8342 if (s
[0] == '(' && args
[1] == '(')
8344 /* It looks like the expression was omitted
8345 before a register indirection, which means
8346 that the expression is implicitly zero. We
8347 still set up imm_expr, so that we handle
8348 explicit extensions correctly. */
8349 imm_expr
.X_op
= O_constant
;
8350 imm_expr
.X_add_number
= 0;
8351 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8358 /* We need to relax this instruction. */
8359 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8368 /* We use offset_reloc rather than imm_reloc for the PC
8369 relative operands. This lets macros with both
8370 immediate and address operands work correctly. */
8371 my_getExpression (&offset_expr
, s
);
8373 if (offset_expr
.X_op
== O_register
)
8376 /* We need to relax this instruction. */
8377 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8381 case '6': /* break code */
8382 my_getExpression (&imm_expr
, s
);
8383 check_absolute_expr (ip
, &imm_expr
);
8384 if ((unsigned long) imm_expr
.X_add_number
> 63)
8386 as_warn (_("Invalid value for `%s' (%lu)"),
8388 (unsigned long) imm_expr
.X_add_number
);
8389 imm_expr
.X_add_number
&= 0x3f;
8391 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8392 imm_expr
.X_op
= O_absent
;
8396 case 'a': /* 26 bit address */
8397 my_getExpression (&offset_expr
, s
);
8399 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8400 ip
->insn_opcode
<<= 16;
8403 case 'l': /* register list for entry macro */
8404 case 'L': /* register list for exit macro */
8414 int freg
, reg1
, reg2
;
8416 while (*s
== ' ' || *s
== ',')
8420 as_bad (_("can't parse register list"));
8432 while (isdigit ((unsigned char) *s
))
8454 as_bad (_("invalid register list"));
8459 while (isdigit ((unsigned char) *s
))
8466 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8471 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8476 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8477 mask
|= (reg2
- 3) << 3;
8478 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8479 mask
|= (reg2
- 15) << 1;
8480 else if (reg1
== 31 && reg2
== 31)
8484 as_bad (_("invalid register list"));
8488 /* The mask is filled in in the opcode table for the
8489 benefit of the disassembler. We remove it before
8490 applying the actual mask. */
8491 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8492 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8496 case 'e': /* extend code */
8497 my_getExpression (&imm_expr
, s
);
8498 check_absolute_expr (ip
, &imm_expr
);
8499 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8501 as_warn (_("Invalid value for `%s' (%lu)"),
8503 (unsigned long) imm_expr
.X_add_number
);
8504 imm_expr
.X_add_number
&= 0x7ff;
8506 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8507 imm_expr
.X_op
= O_absent
;
8517 /* Args don't match. */
8518 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8519 strcmp (insn
->name
, insn
[1].name
) == 0)
8526 insn_error
= _("illegal operands");
8532 /* This structure holds information we know about a mips16 immediate
8535 struct mips16_immed_operand
8537 /* The type code used in the argument string in the opcode table. */
8539 /* The number of bits in the short form of the opcode. */
8541 /* The number of bits in the extended form of the opcode. */
8543 /* The amount by which the short form is shifted when it is used;
8544 for example, the sw instruction has a shift count of 2. */
8546 /* The amount by which the short form is shifted when it is stored
8547 into the instruction code. */
8549 /* Non-zero if the short form is unsigned. */
8551 /* Non-zero if the extended form is unsigned. */
8553 /* Non-zero if the value is PC relative. */
8557 /* The mips16 immediate operand types. */
8559 static const struct mips16_immed_operand mips16_immed_operands
[] =
8561 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8562 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8563 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8564 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8565 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8566 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8567 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8568 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8569 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8570 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8571 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8572 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8573 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8574 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8575 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8576 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8577 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8578 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8579 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8580 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8581 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8584 #define MIPS16_NUM_IMMED \
8585 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8587 /* Handle a mips16 instruction with an immediate value. This or's the
8588 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8589 whether an extended value is needed; if one is needed, it sets
8590 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8591 If SMALL is true, an unextended opcode was explicitly requested.
8592 If EXT is true, an extended opcode was explicitly requested. If
8593 WARN is true, warn if EXT does not match reality. */
8596 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8605 unsigned long *insn
;
8606 boolean
*use_extend
;
8607 unsigned short *extend
;
8609 register const struct mips16_immed_operand
*op
;
8610 int mintiny
, maxtiny
;
8613 op
= mips16_immed_operands
;
8614 while (op
->type
!= type
)
8617 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8622 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8625 maxtiny
= 1 << op
->nbits
;
8630 maxtiny
= (1 << op
->nbits
) - 1;
8635 mintiny
= - (1 << (op
->nbits
- 1));
8636 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8639 /* Branch offsets have an implicit 0 in the lowest bit. */
8640 if (type
== 'p' || type
== 'q')
8643 if ((val
& ((1 << op
->shift
) - 1)) != 0
8644 || val
< (mintiny
<< op
->shift
)
8645 || val
> (maxtiny
<< op
->shift
))
8650 if (warn
&& ext
&& ! needext
)
8651 as_warn_where (file
, line
, _("extended operand requested but not required"));
8652 if (small
&& needext
)
8653 as_bad_where (file
, line
, _("invalid unextended operand value"));
8655 if (small
|| (! ext
&& ! needext
))
8659 *use_extend
= false;
8660 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8661 insnval
<<= op
->op_shift
;
8666 long minext
, maxext
;
8672 maxext
= (1 << op
->extbits
) - 1;
8676 minext
= - (1 << (op
->extbits
- 1));
8677 maxext
= (1 << (op
->extbits
- 1)) - 1;
8679 if (val
< minext
|| val
> maxext
)
8680 as_bad_where (file
, line
,
8681 _("operand value out of range for instruction"));
8684 if (op
->extbits
== 16)
8686 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8689 else if (op
->extbits
== 15)
8691 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8696 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8700 *extend
= (unsigned short) extval
;
8709 my_getSmallExpression (ep
, str
)
8720 ((str
[1] == 'h' && str
[2] == 'i')
8721 || (str
[1] == 'H' && str
[2] == 'I')
8722 || (str
[1] == 'l' && str
[2] == 'o'))
8734 * A small expression may be followed by a base register.
8735 * Scan to the end of this operand, and then back over a possible
8736 * base register. Then scan the small expression up to that
8737 * point. (Based on code in sparc.c...)
8739 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8741 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8743 if (isdigit ((unsigned char) sp
[-2]))
8745 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8747 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8753 else if (sp
- 5 >= str
8756 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8757 || (sp
[-3] == 's' && sp
[-2] == 'p')
8758 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8759 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8765 /* no expression means zero offset */
8768 /* %xx(reg) is an error */
8769 ep
->X_op
= O_absent
;
8774 ep
->X_op
= O_constant
;
8777 ep
->X_add_symbol
= NULL
;
8778 ep
->X_op_symbol
= NULL
;
8779 ep
->X_add_number
= 0;
8784 my_getExpression (ep
, str
);
8791 my_getExpression (ep
, str
);
8792 return c
; /* => %hi or %lo encountered */
8796 my_getExpression (ep
, str
)
8802 save_in
= input_line_pointer
;
8803 input_line_pointer
= str
;
8805 expr_end
= input_line_pointer
;
8806 input_line_pointer
= save_in
;
8808 /* If we are in mips16 mode, and this is an expression based on `.',
8809 then we bump the value of the symbol by 1 since that is how other
8810 text symbols are handled. We don't bother to handle complex
8811 expressions, just `.' plus or minus a constant. */
8812 if (mips_opts
.mips16
8813 && ep
->X_op
== O_symbol
8814 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8815 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8816 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8817 && symbol_constant_p (ep
->X_add_symbol
)
8818 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8819 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8822 /* Turn a string in input_line_pointer into a floating point constant
8823 of type TYPE, and store the appropriate bytes in *LITP. The number
8824 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8825 returned, or NULL on OK. */
8828 md_atof (type
, litP
, sizeP
)
8834 LITTLENUM_TYPE words
[4];
8850 return _("bad call to md_atof");
8853 t
= atof_ieee (input_line_pointer
, type
, words
);
8855 input_line_pointer
= t
;
8859 if (! target_big_endian
)
8861 for (i
= prec
- 1; i
>= 0; i
--)
8863 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8869 for (i
= 0; i
< prec
; i
++)
8871 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8880 md_number_to_chars (buf
, val
, n
)
8885 if (target_big_endian
)
8886 number_to_chars_bigendian (buf
, val
, n
);
8888 number_to_chars_littleendian (buf
, val
, n
);
8891 CONST
char *md_shortopts
= "O::g::G:";
8893 struct option md_longopts
[] =
8895 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8896 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8897 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8898 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8899 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8900 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8901 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8902 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8903 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8904 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8905 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8906 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8907 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8908 #define OPTION_TRAP (OPTION_MD_BASE + 7)
8909 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8910 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8911 #define OPTION_BREAK (OPTION_MD_BASE + 8)
8912 {"break", no_argument
, NULL
, OPTION_BREAK
},
8913 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8914 #define OPTION_EB (OPTION_MD_BASE + 9)
8915 {"EB", no_argument
, NULL
, OPTION_EB
},
8916 #define OPTION_EL (OPTION_MD_BASE + 10)
8917 {"EL", no_argument
, NULL
, OPTION_EL
},
8918 #define OPTION_M4650 (OPTION_MD_BASE + 11)
8919 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8920 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
8921 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8922 #define OPTION_M4010 (OPTION_MD_BASE + 13)
8923 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8924 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
8925 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8926 #define OPTION_M4100 (OPTION_MD_BASE + 15)
8927 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8928 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
8929 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8930 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
8931 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8932 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
8933 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8934 #define OPTION_M3900 (OPTION_MD_BASE + 19)
8935 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8936 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
8937 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8938 #define OPTION_MABI (OPTION_MD_BASE + 21)
8939 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8940 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
8941 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8942 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
8943 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8944 #define OPTION_GP32 (OPTION_MD_BASE + 24)
8945 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8946 #define OPTION_GP64 (OPTION_MD_BASE + 25)
8947 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8948 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
8949 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
8950 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
8951 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
8952 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
8953 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
8954 #define OPTION_NO_MIPS32 (OPTION_MD_BASE + 29)
8955 {"no-mips32", no_argument
, NULL
, OPTION_NO_MIPS32
},
8958 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
8959 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
8960 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
8961 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
8962 #define OPTION_32 (OPTION_ELF_BASE + 3)
8963 #define OPTION_64 (OPTION_ELF_BASE + 4)
8964 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8965 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8966 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8967 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8968 {"32", no_argument
, NULL
, OPTION_32
},
8969 {"64", no_argument
, NULL
, OPTION_64
},
8972 {NULL
, no_argument
, NULL
, 0}
8974 size_t md_longopts_size
= sizeof (md_longopts
);
8977 md_parse_option (c
, arg
)
8983 case OPTION_CONSTRUCT_FLOATS
:
8984 mips_disable_float_construction
= 0;
8987 case OPTION_NO_CONSTRUCT_FLOATS
:
8988 mips_disable_float_construction
= 1;
9000 target_big_endian
= 1;
9004 target_big_endian
= 0;
9008 if (arg
&& arg
[1] == '0')
9018 mips_debug
= atoi (arg
);
9019 /* When the MIPS assembler sees -g or -g2, it does not do
9020 optimizations which limit full symbolic debugging. We take
9021 that to be equivalent to -O0. */
9022 if (mips_debug
== 2)
9046 /* Identify the processor type */
9048 if (strcmp (p
, "default") == 0
9049 || strcmp (p
, "DEFAULT") == 0)
9055 /* We need to cope with the various "vr" prefixes for the 4300
9057 if (*p
== 'v' || *p
== 'V')
9063 if (*p
== 'r' || *p
== 'R')
9070 if (strcmp (p
, "10000") == 0
9071 || strcmp (p
, "10k") == 0
9072 || strcmp (p
, "10K") == 0)
9073 mips_cpu
= CPU_R10000
;
9077 if (strcmp (p
, "2000") == 0
9078 || strcmp (p
, "2k") == 0
9079 || strcmp (p
, "2K") == 0)
9080 mips_cpu
= CPU_R2000
;
9084 if (strcmp (p
, "3000") == 0
9085 || strcmp (p
, "3k") == 0
9086 || strcmp (p
, "3K") == 0)
9087 mips_cpu
= CPU_R3000
;
9088 else if (strcmp (p
, "3900") == 0)
9089 mips_cpu
= CPU_R3900
;
9093 if (strcmp (p
, "4000") == 0
9094 || strcmp (p
, "4k") == 0
9095 || strcmp (p
, "4K") == 0)
9096 mips_cpu
= CPU_R4000
;
9097 else if (strcmp (p
, "4100") == 0)
9098 mips_cpu
= CPU_VR4100
;
9099 else if (strcmp (p
, "4111") == 0)
9100 mips_cpu
= CPU_R4111
;
9101 else if (strcmp (p
, "4300") == 0)
9102 mips_cpu
= CPU_R4300
;
9103 else if (strcmp (p
, "4400") == 0)
9104 mips_cpu
= CPU_R4400
;
9105 else if (strcmp (p
, "4600") == 0)
9106 mips_cpu
= CPU_R4600
;
9107 else if (strcmp (p
, "4650") == 0)
9108 mips_cpu
= CPU_R4650
;
9109 else if (strcmp (p
, "4010") == 0)
9110 mips_cpu
= CPU_R4010
;
9111 else if (strcmp (p
, "4Kc") == 0
9112 || strcmp (p
, "4Kp") == 0
9113 || strcmp (p
, "4Km") == 0)
9114 mips_cpu
= CPU_MIPS32
;
9118 if (strcmp (p
, "5000") == 0
9119 || strcmp (p
, "5k") == 0
9120 || strcmp (p
, "5K") == 0)
9121 mips_cpu
= CPU_R5000
;
9125 if (strcmp (p
, "6000") == 0
9126 || strcmp (p
, "6k") == 0
9127 || strcmp (p
, "6K") == 0)
9128 mips_cpu
= CPU_R6000
;
9132 if (strcmp (p
, "8000") == 0
9133 || strcmp (p
, "8k") == 0
9134 || strcmp (p
, "8K") == 0)
9135 mips_cpu
= CPU_R8000
;
9139 if (strcmp (p
, "orion") == 0)
9140 mips_cpu
= CPU_R4600
;
9145 switch (atoi (p
+ 1))
9153 mips_cpu
= CPU_R5000
;
9161 && (mips_cpu
!= CPU_R4300
9162 && mips_cpu
!= CPU_VR4100
9163 && mips_cpu
!= CPU_R4111
9164 && mips_cpu
!= CPU_R5000
))
9166 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9172 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9180 mips_cpu
= CPU_R4650
;
9183 case OPTION_NO_M4650
:
9187 mips_cpu
= CPU_R4010
;
9190 case OPTION_NO_M4010
:
9194 mips_cpu
= CPU_VR4100
;
9197 case OPTION_NO_M4100
:
9201 mips_cpu
= CPU_MIPS32
;
9204 case OPTION_NO_MIPS32
:
9208 mips_cpu
= CPU_R3900
;
9211 case OPTION_NO_M3900
:
9215 mips_opts
.mips16
= 1;
9216 mips_no_prev_insn (false);
9219 case OPTION_NO_MIPS16
:
9220 mips_opts
.mips16
= 0;
9221 mips_no_prev_insn (false);
9224 case OPTION_MEMBEDDED_PIC
:
9225 mips_pic
= EMBEDDED_PIC
;
9226 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9228 as_bad (_("-G may not be used with embedded PIC code"));
9231 g_switch_value
= 0x7fffffff;
9234 /* When generating ELF code, we permit -KPIC and -call_shared to
9235 select SVR4_PIC, and -non_shared to select no PIC. This is
9236 intended to be compatible with Irix 5. */
9237 case OPTION_CALL_SHARED
:
9238 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9240 as_bad (_("-call_shared is supported only for ELF format"));
9243 mips_pic
= SVR4_PIC
;
9244 if (g_switch_seen
&& g_switch_value
!= 0)
9246 as_bad (_("-G may not be used with SVR4 PIC code"));
9252 case OPTION_NON_SHARED
:
9253 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9255 as_bad (_("-non_shared is supported only for ELF format"));
9261 /* The -xgot option tells the assembler to use 32 offsets when
9262 accessing the got in SVR4_PIC mode. It is for Irix
9269 if (! USE_GLOBAL_POINTER_OPT
)
9271 as_bad (_("-G is not supported for this configuration"));
9274 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9276 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9280 g_switch_value
= atoi (arg
);
9284 /* The -32 and -64 options tell the assembler to output the 32
9285 bit or the 64 bit MIPS ELF format. */
9292 const char **list
, **l
;
9294 list
= bfd_target_list ();
9295 for (l
= list
; *l
!= NULL
; l
++)
9296 if (strcmp (*l
, "elf64-bigmips") == 0
9297 || strcmp (*l
, "elf64-littlemips") == 0)
9300 as_fatal (_("No compiled in support for 64 bit object file format"));
9310 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9311 flag in object files because to do so would make it
9312 impossible to link with libraries compiled without "-gp32".
9313 This is unnecessarily restrictive.
9315 We could solve this problem by adding "-gp32" multilibs to
9316 gcc, but to set this flag before gcc is built with such
9317 multilibs will break too many systems. */
9319 /* mips_32bitmode = 1; */
9325 /* mips_32bitmode = 0; */
9329 if (strcmp (arg
,"32") == 0
9330 || strcmp (arg
,"n32") == 0
9331 || strcmp (arg
,"64") == 0
9332 || strcmp (arg
,"o64") == 0
9333 || strcmp (arg
,"eabi") == 0)
9334 mips_abi_string
= arg
;
9337 case OPTION_M7000_HILO_FIX
:
9338 mips_7000_hilo_fix
= true;
9341 case OPTION_NO_M7000_HILO_FIX
:
9342 mips_7000_hilo_fix
= false;
9353 show (stream
, string
, col_p
, first_p
)
9361 fprintf (stream
, "%24s", "");
9366 fprintf (stream
, ", ");
9370 if (*col_p
+ strlen (string
) > 72)
9372 fprintf (stream
, "\n%24s", "");
9376 fprintf (stream
, "%s", string
);
9377 *col_p
+= strlen (string
);
9383 md_show_usage (stream
)
9388 fprintf(stream
, _("\
9390 -membedded-pic generate embedded position independent code\n\
9391 -EB generate big endian output\n\
9392 -EL generate little endian output\n\
9393 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9394 -G NUM allow referencing objects up to NUM bytes\n\
9395 implicitly with the gp register [default 8]\n"));
9396 fprintf(stream
, _("\
9397 -mips1 generate MIPS ISA I instructions\n\
9398 -mips2 generate MIPS ISA II instructions\n\
9399 -mips3 generate MIPS ISA III instructions\n\
9400 -mips4 generate MIPS ISA IV instructions\n\
9401 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9405 show (stream
, "2000", &column
, &first
);
9406 show (stream
, "3000", &column
, &first
);
9407 show (stream
, "3900", &column
, &first
);
9408 show (stream
, "4000", &column
, &first
);
9409 show (stream
, "4010", &column
, &first
);
9410 show (stream
, "4100", &column
, &first
);
9411 show (stream
, "4111", &column
, &first
);
9412 show (stream
, "4300", &column
, &first
);
9413 show (stream
, "4400", &column
, &first
);
9414 show (stream
, "4600", &column
, &first
);
9415 show (stream
, "4650", &column
, &first
);
9416 show (stream
, "5000", &column
, &first
);
9417 show (stream
, "6000", &column
, &first
);
9418 show (stream
, "8000", &column
, &first
);
9419 show (stream
, "10000", &column
, &first
);
9420 show (stream
, "4Kc", &column
, &first
);
9421 show (stream
, "4Kp", &column
, &first
);
9422 show (stream
, "4Km", &column
, &first
);
9423 fputc ('\n', stream
);
9425 fprintf (stream
, _("\
9426 -mCPU equivalent to -mcpu=CPU.\n\
9427 -no-mCPU don't generate code specific to CPU.\n\
9428 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9432 show (stream
, "3900", &column
, &first
);
9433 show (stream
, "4010", &column
, &first
);
9434 show (stream
, "4100", &column
, &first
);
9435 show (stream
, "4650", &column
, &first
);
9436 fputc ('\n', stream
);
9438 fprintf (stream
, _("\
9439 -mips32 generate MIPS32 instructions\n"));
9441 fprintf(stream
, _("\
9442 -mips16 generate mips16 instructions\n\
9443 -no-mips16 do not generate mips16 instructions\n"));
9444 fprintf(stream
, _("\
9445 -O0 remove unneeded NOPs, do not swap branches\n\
9446 -O remove unneeded NOPs and swap branches\n\
9447 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9448 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9449 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9451 fprintf(stream
, _("\
9452 -KPIC, -call_shared generate SVR4 position independent code\n\
9453 -non_shared do not generate position independent code\n\
9454 -xgot assume a 32 bit GOT\n\
9455 -32 create 32 bit object file (default)\n\
9456 -64 create 64 bit object file\n"));
9461 mips_init_after_args ()
9463 /* initialize opcodes */
9464 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9465 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9469 md_pcrel_from (fixP
)
9472 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9473 && fixP
->fx_addsy
!= (symbolS
*) NULL
9474 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9476 /* This makes a branch to an undefined symbol be a branch to the
9477 current location. */
9481 /* return the address of the delay slot */
9482 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9485 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9486 reloc for a cons. We could use the definition there, except that
9487 we want to handle 64 bit relocs specially. */
9490 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9491 fragS
*frag ATTRIBUTE_UNUSED
;
9493 unsigned int nbytes
;
9497 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9499 if (nbytes
== 8 && ! mips_64
)
9501 if (target_big_endian
)
9507 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9508 as_bad (_("Unsupported reloc size %d"), nbytes
);
9510 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9513 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9516 /* This is called before the symbol table is processed. In order to
9517 work with gcc when using mips-tfile, we must keep all local labels.
9518 However, in other cases, we want to discard them. If we were
9519 called with -g, but we didn't see any debugging information, it may
9520 mean that gcc is smuggling debugging information through to
9521 mips-tfile, in which case we must generate all local labels. */
9524 mips_frob_file_before_adjust ()
9526 #ifndef NO_ECOFF_DEBUGGING
9529 && ! ecoff_debugging_seen
)
9530 flag_keep_locals
= 1;
9534 /* Sort any unmatched HI16_S relocs so that they immediately precede
9535 the corresponding LO reloc. This is called before md_apply_fix and
9536 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9537 explicit use of the %hi modifier. */
9542 struct mips_hi_fixup
*l
;
9544 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9546 segment_info_type
*seginfo
;
9549 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9551 /* Check quickly whether the next fixup happens to be a matching
9553 if (l
->fixp
->fx_next
!= NULL
9554 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9555 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9556 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9559 /* Look through the fixups for this segment for a matching %lo.
9560 When we find one, move the %hi just in front of it. We do
9561 this in two passes. In the first pass, we try to find a
9562 unique %lo. In the second pass, we permit multiple %hi
9563 relocs for a single %lo (this is a GNU extension). */
9564 seginfo
= seg_info (l
->seg
);
9565 for (pass
= 0; pass
< 2; pass
++)
9570 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9572 /* Check whether this is a %lo fixup which matches l->fixp. */
9573 if (f
->fx_r_type
== BFD_RELOC_LO16
9574 && f
->fx_addsy
== l
->fixp
->fx_addsy
9575 && f
->fx_offset
== l
->fixp
->fx_offset
9578 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9579 || prev
->fx_addsy
!= f
->fx_addsy
9580 || prev
->fx_offset
!= f
->fx_offset
))
9584 /* Move l->fixp before f. */
9585 for (pf
= &seginfo
->fix_root
;
9587 pf
= &(*pf
)->fx_next
)
9588 assert (*pf
!= NULL
);
9590 *pf
= l
->fixp
->fx_next
;
9592 l
->fixp
->fx_next
= f
;
9594 seginfo
->fix_root
= l
->fixp
;
9596 prev
->fx_next
= l
->fixp
;
9607 #if 0 /* GCC code motion plus incomplete dead code elimination
9608 can leave a %hi without a %lo. */
9610 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9611 _("Unmatched %%hi reloc"));
9617 /* When generating embedded PIC code we need to use a special
9618 relocation to represent the difference of two symbols in the .text
9619 section (switch tables use a difference of this sort). See
9620 include/coff/mips.h for details. This macro checks whether this
9621 fixup requires the special reloc. */
9622 #define SWITCH_TABLE(fixp) \
9623 ((fixp)->fx_r_type == BFD_RELOC_32 \
9624 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9625 && (fixp)->fx_addsy != NULL \
9626 && (fixp)->fx_subsy != NULL \
9627 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9628 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9630 /* When generating embedded PIC code we must keep all PC relative
9631 relocations, in case the linker has to relax a call. We also need
9632 to keep relocations for switch table entries. */
9636 mips_force_relocation (fixp
)
9639 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9640 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9643 return (mips_pic
== EMBEDDED_PIC
9645 || SWITCH_TABLE (fixp
)
9646 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9647 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9650 /* Apply a fixup to the object file. */
9653 md_apply_fix (fixP
, valueP
)
9660 assert (fixP
->fx_size
== 4
9661 || fixP
->fx_r_type
== BFD_RELOC_16
9662 || fixP
->fx_r_type
== BFD_RELOC_64
9663 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9664 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9668 /* If we aren't adjusting this fixup to be against the section
9669 symbol, we need to adjust the value. */
9671 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9673 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9674 || S_IS_WEAK (fixP
->fx_addsy
)
9675 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9676 && (((bfd_get_section_flags (stdoutput
,
9677 S_GET_SEGMENT (fixP
->fx_addsy
))
9678 & SEC_LINK_ONCE
) != 0)
9679 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9681 sizeof (".gnu.linkonce") - 1))))
9684 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9685 if (value
!= 0 && ! fixP
->fx_pcrel
)
9687 /* In this case, the bfd_install_relocation routine will
9688 incorrectly add the symbol value back in. We just want
9689 the addend to appear in the object file.
9690 FIXME: If this makes VALUE zero, we're toast. */
9691 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9695 /* This code was generated using trial and error and so is
9696 fragile and not trustworthy. If you change it, you should
9697 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9699 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9701 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9703 /* BFD's REL handling, for MIPS, is _very_ weird.
9704 This gives the right results, but it can't possibly
9705 be the way things are supposed to work. */
9706 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9707 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9708 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9713 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9715 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9718 switch (fixP
->fx_r_type
)
9720 case BFD_RELOC_MIPS_JMP
:
9721 case BFD_RELOC_HI16
:
9722 case BFD_RELOC_HI16_S
:
9723 case BFD_RELOC_MIPS_GPREL
:
9724 case BFD_RELOC_MIPS_LITERAL
:
9725 case BFD_RELOC_MIPS_CALL16
:
9726 case BFD_RELOC_MIPS_GOT16
:
9727 case BFD_RELOC_MIPS_GPREL32
:
9728 case BFD_RELOC_MIPS_GOT_HI16
:
9729 case BFD_RELOC_MIPS_GOT_LO16
:
9730 case BFD_RELOC_MIPS_CALL_HI16
:
9731 case BFD_RELOC_MIPS_CALL_LO16
:
9732 case BFD_RELOC_MIPS16_GPREL
:
9734 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9735 _("Invalid PC relative reloc"));
9736 /* Nothing needed to do. The value comes from the reloc entry */
9739 case BFD_RELOC_MIPS16_JMP
:
9740 /* We currently always generate a reloc against a symbol, which
9741 means that we don't want an addend even if the symbol is
9743 fixP
->fx_addnumber
= 0;
9746 case BFD_RELOC_PCREL_HI16_S
:
9747 /* The addend for this is tricky if it is internal, so we just
9748 do everything here rather than in bfd_install_relocation. */
9749 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9754 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9756 /* For an external symbol adjust by the address to make it
9757 pcrel_offset. We use the address of the RELLO reloc
9758 which follows this one. */
9759 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9760 + fixP
->fx_next
->fx_where
);
9765 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9766 if (target_big_endian
)
9768 md_number_to_chars (buf
, value
, 2);
9771 case BFD_RELOC_PCREL_LO16
:
9772 /* The addend for this is tricky if it is internal, so we just
9773 do everything here rather than in bfd_install_relocation. */
9774 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9779 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9780 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9781 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9782 if (target_big_endian
)
9784 md_number_to_chars (buf
, value
, 2);
9788 /* This is handled like BFD_RELOC_32, but we output a sign
9789 extended value if we are only 32 bits. */
9791 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9793 if (8 <= sizeof (valueT
))
9794 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9801 w1
= w2
= fixP
->fx_where
;
9802 if (target_big_endian
)
9806 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9807 if ((value
& 0x80000000) != 0)
9811 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9818 /* If we are deleting this reloc entry, we must fill in the
9819 value now. This can happen if we have a .word which is not
9820 resolved when it appears but is later defined. We also need
9821 to fill in the value if this is an embedded PIC switch table
9824 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9825 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9830 /* If we are deleting this reloc entry, we must fill in the
9832 assert (fixP
->fx_size
== 2);
9834 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9838 case BFD_RELOC_LO16
:
9839 /* When handling an embedded PIC switch statement, we can wind
9840 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9843 if (value
< -0x8000 || value
> 0x7fff)
9844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9845 _("relocation overflow"));
9846 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9847 if (target_big_endian
)
9849 md_number_to_chars (buf
, value
, 2);
9853 case BFD_RELOC_16_PCREL_S2
:
9855 * We need to save the bits in the instruction since fixup_segment()
9856 * might be deleting the relocation entry (i.e., a branch within
9857 * the current segment).
9859 if ((value
& 0x3) != 0)
9860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9861 _("Branch to odd address (%lx)"), value
);
9863 if (!fixP
->fx_done
&& value
!= 0)
9865 /* If 'value' is zero, the remaining reloc code won't actually
9866 do the store, so it must be done here. This is probably
9869 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9873 /* update old instruction data */
9874 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9875 if (target_big_endian
)
9876 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9878 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9880 if (value
>= -0x8000 && value
< 0x8000)
9881 insn
|= value
& 0xffff;
9884 /* The branch offset is too large. If this is an
9885 unconditional branch, and we are not generating PIC code,
9886 we can convert it to an absolute jump instruction. */
9887 if (mips_pic
== NO_PIC
9889 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9890 && (fixP
->fx_frag
->fr_address
9891 < text_section
->vma
+ text_section
->_raw_size
)
9892 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9893 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9894 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9896 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9897 insn
= 0x0c000000; /* jal */
9899 insn
= 0x08000000; /* j */
9900 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9902 fixP
->fx_addsy
= section_symbol (text_section
);
9903 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9907 /* FIXME. It would be possible in principle to handle
9908 conditional branches which overflow. They could be
9909 transformed into a branch around a jump. This would
9910 require setting up variant frags for each different
9911 branch type. The native MIPS assembler attempts to
9912 handle these cases, but it appears to do it
9914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9915 _("Branch out of range"));
9919 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9922 case BFD_RELOC_VTABLE_INHERIT
:
9925 && !S_IS_DEFINED (fixP
->fx_addsy
)
9926 && !S_IS_WEAK (fixP
->fx_addsy
))
9927 S_SET_WEAK (fixP
->fx_addsy
);
9930 case BFD_RELOC_VTABLE_ENTRY
:
9946 const struct mips_opcode
*p
;
9947 int treg
, sreg
, dreg
, shamt
;
9952 for (i
= 0; i
< NUMOPCODES
; ++i
)
9954 p
= &mips_opcodes
[i
];
9955 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9957 printf ("%08lx %s\t", oc
, p
->name
);
9958 treg
= (oc
>> 16) & 0x1f;
9959 sreg
= (oc
>> 21) & 0x1f;
9960 dreg
= (oc
>> 11) & 0x1f;
9961 shamt
= (oc
>> 6) & 0x1f;
9963 for (args
= p
->args
;; ++args
)
9974 printf ("%c", *args
);
9978 assert (treg
== sreg
);
9979 printf ("$%d,$%d", treg
, sreg
);
9984 printf ("$%d", dreg
);
9989 printf ("$%d", treg
);
9993 printf ("0x%x", treg
);
9998 printf ("$%d", sreg
);
10002 printf ("0x%08lx", oc
& 0x1ffffff);
10009 printf ("%d", imm
);
10014 printf ("$%d", shamt
);
10025 printf (_("%08lx UNDEFINED\n"), oc
);
10036 name
= input_line_pointer
;
10037 c
= get_symbol_end ();
10038 p
= (symbolS
*) symbol_find_or_make (name
);
10039 *input_line_pointer
= c
;
10043 /* Align the current frag to a given power of two. The MIPS assembler
10044 also automatically adjusts any preceding label. */
10047 mips_align (to
, fill
, label
)
10052 mips_emit_delays (false);
10053 frag_align (to
, fill
, 0);
10054 record_alignment (now_seg
, to
);
10057 assert (S_GET_SEGMENT (label
) == now_seg
);
10058 symbol_set_frag (label
, frag_now
);
10059 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10063 /* Align to a given power of two. .align 0 turns off the automatic
10064 alignment used by the data creating pseudo-ops. */
10068 int x ATTRIBUTE_UNUSED
;
10071 register long temp_fill
;
10072 long max_alignment
= 15;
10076 o Note that the assembler pulls down any immediately preceeding label
10077 to the aligned address.
10078 o It's not documented but auto alignment is reinstated by
10079 a .align pseudo instruction.
10080 o Note also that after auto alignment is turned off the mips assembler
10081 issues an error on attempt to assemble an improperly aligned data item.
10086 temp
= get_absolute_expression ();
10087 if (temp
> max_alignment
)
10088 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10091 as_warn (_("Alignment negative: 0 assumed."));
10094 if (*input_line_pointer
== ',')
10096 input_line_pointer
++;
10097 temp_fill
= get_absolute_expression ();
10104 mips_align (temp
, (int) temp_fill
,
10105 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10112 demand_empty_rest_of_line ();
10116 mips_flush_pending_output ()
10118 mips_emit_delays (false);
10119 mips_clear_insn_labels ();
10128 /* When generating embedded PIC code, we only use the .text, .lit8,
10129 .sdata and .sbss sections. We change the .data and .rdata
10130 pseudo-ops to use .sdata. */
10131 if (mips_pic
== EMBEDDED_PIC
10132 && (sec
== 'd' || sec
== 'r'))
10136 /* The ELF backend needs to know that we are changing sections, so
10137 that .previous works correctly. We could do something like check
10138 for a obj_section_change_hook macro, but that might be confusing
10139 as it would not be appropriate to use it in the section changing
10140 functions in read.c, since obj-elf.c intercepts those. FIXME:
10141 This should be cleaner, somehow. */
10142 obj_elf_section_change_hook ();
10145 mips_emit_delays (false);
10155 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10156 demand_empty_rest_of_line ();
10160 if (USE_GLOBAL_POINTER_OPT
)
10162 seg
= subseg_new (RDATA_SECTION_NAME
,
10163 (subsegT
) get_absolute_expression ());
10164 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10166 bfd_set_section_flags (stdoutput
, seg
,
10172 if (strcmp (TARGET_OS
, "elf") != 0)
10173 record_alignment (seg
, 4);
10175 demand_empty_rest_of_line ();
10179 as_bad (_("No read only data section in this object file format"));
10180 demand_empty_rest_of_line ();
10186 if (USE_GLOBAL_POINTER_OPT
)
10188 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10189 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10191 bfd_set_section_flags (stdoutput
, seg
,
10192 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10194 if (strcmp (TARGET_OS
, "elf") != 0)
10195 record_alignment (seg
, 4);
10197 demand_empty_rest_of_line ();
10202 as_bad (_("Global pointers not supported; recompile -G 0"));
10203 demand_empty_rest_of_line ();
10212 mips_enable_auto_align ()
10223 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10224 mips_emit_delays (false);
10225 if (log_size
> 0 && auto_align
)
10226 mips_align (log_size
, 0, label
);
10227 mips_clear_insn_labels ();
10228 cons (1 << log_size
);
10232 s_float_cons (type
)
10237 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10239 mips_emit_delays (false);
10244 mips_align (3, 0, label
);
10246 mips_align (2, 0, label
);
10249 mips_clear_insn_labels ();
10254 /* Handle .globl. We need to override it because on Irix 5 you are
10257 where foo is an undefined symbol, to mean that foo should be
10258 considered to be the address of a function. */
10262 int x ATTRIBUTE_UNUSED
;
10269 name
= input_line_pointer
;
10270 c
= get_symbol_end ();
10271 symbolP
= symbol_find_or_make (name
);
10272 *input_line_pointer
= c
;
10273 SKIP_WHITESPACE ();
10275 /* On Irix 5, every global symbol that is not explicitly labelled as
10276 being a function is apparently labelled as being an object. */
10279 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10284 secname
= input_line_pointer
;
10285 c
= get_symbol_end ();
10286 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10288 as_bad (_("%s: no such section"), secname
);
10289 *input_line_pointer
= c
;
10291 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10292 flag
= BSF_FUNCTION
;
10295 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10297 S_SET_EXTERNAL (symbolP
);
10298 demand_empty_rest_of_line ();
10303 int x ATTRIBUTE_UNUSED
;
10308 opt
= input_line_pointer
;
10309 c
= get_symbol_end ();
10313 /* FIXME: What does this mean? */
10315 else if (strncmp (opt
, "pic", 3) == 0)
10319 i
= atoi (opt
+ 3);
10323 mips_pic
= SVR4_PIC
;
10325 as_bad (_(".option pic%d not supported"), i
);
10327 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10329 if (g_switch_seen
&& g_switch_value
!= 0)
10330 as_warn (_("-G may not be used with SVR4 PIC code"));
10331 g_switch_value
= 0;
10332 bfd_set_gp_size (stdoutput
, 0);
10336 as_warn (_("Unrecognized option \"%s\""), opt
);
10338 *input_line_pointer
= c
;
10339 demand_empty_rest_of_line ();
10342 /* This structure is used to hold a stack of .set values. */
10344 struct mips_option_stack
10346 struct mips_option_stack
*next
;
10347 struct mips_set_options options
;
10350 static struct mips_option_stack
*mips_opts_stack
;
10352 /* Handle the .set pseudo-op. */
10356 int x ATTRIBUTE_UNUSED
;
10358 char *name
= input_line_pointer
, ch
;
10360 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10361 input_line_pointer
++;
10362 ch
= *input_line_pointer
;
10363 *input_line_pointer
= '\0';
10365 if (strcmp (name
, "reorder") == 0)
10367 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10369 /* If we still have pending nops, we can discard them. The
10370 usual nop handling will insert any that are still
10372 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10373 * (mips_opts
.mips16
? 2 : 4));
10374 prev_nop_frag
= NULL
;
10376 mips_opts
.noreorder
= 0;
10378 else if (strcmp (name
, "noreorder") == 0)
10380 mips_emit_delays (true);
10381 mips_opts
.noreorder
= 1;
10382 mips_any_noreorder
= 1;
10384 else if (strcmp (name
, "at") == 0)
10386 mips_opts
.noat
= 0;
10388 else if (strcmp (name
, "noat") == 0)
10390 mips_opts
.noat
= 1;
10392 else if (strcmp (name
, "macro") == 0)
10394 mips_opts
.warn_about_macros
= 0;
10396 else if (strcmp (name
, "nomacro") == 0)
10398 if (mips_opts
.noreorder
== 0)
10399 as_bad (_("`noreorder' must be set before `nomacro'"));
10400 mips_opts
.warn_about_macros
= 1;
10402 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10404 mips_opts
.nomove
= 0;
10406 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10408 mips_opts
.nomove
= 1;
10410 else if (strcmp (name
, "bopt") == 0)
10412 mips_opts
.nobopt
= 0;
10414 else if (strcmp (name
, "nobopt") == 0)
10416 mips_opts
.nobopt
= 1;
10418 else if (strcmp (name
, "mips16") == 0
10419 || strcmp (name
, "MIPS-16") == 0)
10420 mips_opts
.mips16
= 1;
10421 else if (strcmp (name
, "nomips16") == 0
10422 || strcmp (name
, "noMIPS-16") == 0)
10423 mips_opts
.mips16
= 0;
10424 else if (strncmp (name
, "mips", 4) == 0)
10428 /* Permit the user to change the ISA on the fly. Needless to
10429 say, misuse can cause serious problems. */
10430 isa
= atoi (name
+ 4);
10432 mips_opts
.isa
= file_mips_isa
;
10433 else if (isa
< 1 || isa
> 4)
10434 as_bad (_("unknown ISA level"));
10436 mips_opts
.isa
= isa
;
10438 else if (strcmp (name
, "autoextend") == 0)
10439 mips_opts
.noautoextend
= 0;
10440 else if (strcmp (name
, "noautoextend") == 0)
10441 mips_opts
.noautoextend
= 1;
10442 else if (strcmp (name
, "push") == 0)
10444 struct mips_option_stack
*s
;
10446 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10447 s
->next
= mips_opts_stack
;
10448 s
->options
= mips_opts
;
10449 mips_opts_stack
= s
;
10451 else if (strcmp (name
, "pop") == 0)
10453 struct mips_option_stack
*s
;
10455 s
= mips_opts_stack
;
10457 as_bad (_(".set pop with no .set push"));
10460 /* If we're changing the reorder mode we need to handle
10461 delay slots correctly. */
10462 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10463 mips_emit_delays (true);
10464 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10466 if (prev_nop_frag
!= NULL
)
10468 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10469 * (mips_opts
.mips16
? 2 : 4));
10470 prev_nop_frag
= NULL
;
10474 mips_opts
= s
->options
;
10475 mips_opts_stack
= s
->next
;
10481 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10483 *input_line_pointer
= ch
;
10484 demand_empty_rest_of_line ();
10487 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10488 .option pic2. It means to generate SVR4 PIC calls. */
10491 s_abicalls (ignore
)
10492 int ignore ATTRIBUTE_UNUSED
;
10494 mips_pic
= SVR4_PIC
;
10495 if (USE_GLOBAL_POINTER_OPT
)
10497 if (g_switch_seen
&& g_switch_value
!= 0)
10498 as_warn (_("-G may not be used with SVR4 PIC code"));
10499 g_switch_value
= 0;
10501 bfd_set_gp_size (stdoutput
, 0);
10502 demand_empty_rest_of_line ();
10505 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10506 PIC code. It sets the $gp register for the function based on the
10507 function address, which is in the register named in the argument.
10508 This uses a relocation against _gp_disp, which is handled specially
10509 by the linker. The result is:
10510 lui $gp,%hi(_gp_disp)
10511 addiu $gp,$gp,%lo(_gp_disp)
10512 addu $gp,$gp,.cpload argument
10513 The .cpload argument is normally $25 == $t9. */
10517 int ignore ATTRIBUTE_UNUSED
;
10522 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10523 if (mips_pic
!= SVR4_PIC
)
10529 /* .cpload should be a in .set noreorder section. */
10530 if (mips_opts
.noreorder
== 0)
10531 as_warn (_(".cpload not in noreorder section"));
10533 ex
.X_op
= O_symbol
;
10534 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10535 ex
.X_op_symbol
= NULL
;
10536 ex
.X_add_number
= 0;
10538 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10539 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10541 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10542 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10543 (int) BFD_RELOC_LO16
);
10545 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10546 GP
, GP
, tc_get_register (0));
10548 demand_empty_rest_of_line ();
10551 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10552 offset from $sp. The offset is remembered, and after making a PIC
10553 call $gp is restored from that location. */
10556 s_cprestore (ignore
)
10557 int ignore ATTRIBUTE_UNUSED
;
10562 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10563 if (mips_pic
!= SVR4_PIC
)
10569 mips_cprestore_offset
= get_absolute_expression ();
10571 ex
.X_op
= O_constant
;
10572 ex
.X_add_symbol
= NULL
;
10573 ex
.X_op_symbol
= NULL
;
10574 ex
.X_add_number
= mips_cprestore_offset
;
10576 macro_build ((char *) NULL
, &icnt
, &ex
,
10577 ((bfd_arch_bits_per_address (stdoutput
) == 32
10578 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10580 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10582 demand_empty_rest_of_line ();
10585 /* Handle the .gpword pseudo-op. This is used when generating PIC
10586 code. It generates a 32 bit GP relative reloc. */
10590 int ignore ATTRIBUTE_UNUSED
;
10596 /* When not generating PIC code, this is treated as .word. */
10597 if (mips_pic
!= SVR4_PIC
)
10603 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10604 mips_emit_delays (true);
10606 mips_align (2, 0, label
);
10607 mips_clear_insn_labels ();
10611 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10613 as_bad (_("Unsupported use of .gpword"));
10614 ignore_rest_of_line ();
10618 md_number_to_chars (p
, (valueT
) 0, 4);
10619 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10620 BFD_RELOC_MIPS_GPREL32
);
10622 demand_empty_rest_of_line ();
10625 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10626 tables in SVR4 PIC code. */
10630 int ignore ATTRIBUTE_UNUSED
;
10635 /* This is ignored when not generating SVR4 PIC code. */
10636 if (mips_pic
!= SVR4_PIC
)
10642 /* Add $gp to the register named as an argument. */
10643 reg
= tc_get_register (0);
10644 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10645 ((bfd_arch_bits_per_address (stdoutput
) == 32
10646 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10647 ? "addu" : "daddu"),
10648 "d,v,t", reg
, reg
, GP
);
10650 demand_empty_rest_of_line ();
10653 /* Handle the .insn pseudo-op. This marks instruction labels in
10654 mips16 mode. This permits the linker to handle them specially,
10655 such as generating jalx instructions when needed. We also make
10656 them odd for the duration of the assembly, in order to generate the
10657 right sort of code. We will make them even in the adjust_symtab
10658 routine, while leaving them marked. This is convenient for the
10659 debugger and the disassembler. The linker knows to make them odd
10664 int ignore ATTRIBUTE_UNUSED
;
10666 if (mips_opts
.mips16
)
10667 mips16_mark_labels ();
10669 demand_empty_rest_of_line ();
10672 /* Handle a .stabn directive. We need these in order to mark a label
10673 as being a mips16 text label correctly. Sometimes the compiler
10674 will emit a label, followed by a .stabn, and then switch sections.
10675 If the label and .stabn are in mips16 mode, then the label is
10676 really a mips16 text label. */
10682 if (type
== 'n' && mips_opts
.mips16
)
10683 mips16_mark_labels ();
10688 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10692 s_mips_weakext (ignore
)
10693 int ignore ATTRIBUTE_UNUSED
;
10700 name
= input_line_pointer
;
10701 c
= get_symbol_end ();
10702 symbolP
= symbol_find_or_make (name
);
10703 S_SET_WEAK (symbolP
);
10704 *input_line_pointer
= c
;
10706 SKIP_WHITESPACE ();
10708 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10710 if (S_IS_DEFINED (symbolP
))
10712 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10713 S_GET_NAME (symbolP
));
10714 ignore_rest_of_line ();
10718 if (*input_line_pointer
== ',')
10720 ++input_line_pointer
;
10721 SKIP_WHITESPACE ();
10725 if (exp
.X_op
!= O_symbol
)
10727 as_bad ("bad .weakext directive");
10728 ignore_rest_of_line();
10731 symbol_set_value_expression (symbolP
, &exp
);
10734 demand_empty_rest_of_line ();
10737 /* Parse a register string into a number. Called from the ECOFF code
10738 to parse .frame. The argument is non-zero if this is the frame
10739 register, so that we can record it in mips_frame_reg. */
10742 tc_get_register (frame
)
10747 SKIP_WHITESPACE ();
10748 if (*input_line_pointer
++ != '$')
10750 as_warn (_("expected `$'"));
10753 else if (isdigit ((unsigned char) *input_line_pointer
))
10755 reg
= get_absolute_expression ();
10756 if (reg
< 0 || reg
>= 32)
10758 as_warn (_("Bad register number"));
10764 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10766 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10768 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10770 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10774 as_warn (_("Unrecognized register name"));
10777 input_line_pointer
+= 2;
10780 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10785 md_section_align (seg
, addr
)
10789 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10792 /* We don't need to align ELF sections to the full alignment.
10793 However, Irix 5 may prefer that we align them at least to a 16
10794 byte boundary. We don't bother to align the sections if we are
10795 targeted for an embedded system. */
10796 if (strcmp (TARGET_OS
, "elf") == 0)
10802 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10805 /* Utility routine, called from above as well. If called while the
10806 input file is still being read, it's only an approximation. (For
10807 example, a symbol may later become defined which appeared to be
10808 undefined earlier.) */
10811 nopic_need_relax (sym
, before_relaxing
)
10813 int before_relaxing
;
10818 if (USE_GLOBAL_POINTER_OPT
)
10820 const char *symname
;
10823 /* Find out whether this symbol can be referenced off the GP
10824 register. It can be if it is smaller than the -G size or if
10825 it is in the .sdata or .sbss section. Certain symbols can
10826 not be referenced off the GP, although it appears as though
10828 symname
= S_GET_NAME (sym
);
10829 if (symname
!= (const char *) NULL
10830 && (strcmp (symname
, "eprol") == 0
10831 || strcmp (symname
, "etext") == 0
10832 || strcmp (symname
, "_gp") == 0
10833 || strcmp (symname
, "edata") == 0
10834 || strcmp (symname
, "_fbss") == 0
10835 || strcmp (symname
, "_fdata") == 0
10836 || strcmp (symname
, "_ftext") == 0
10837 || strcmp (symname
, "end") == 0
10838 || strcmp (symname
, "_gp_disp") == 0))
10840 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10842 #ifndef NO_ECOFF_DEBUGGING
10843 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10844 && (symbol_get_obj (sym
)->ecoff_extern_size
10845 <= g_switch_value
))
10847 /* We must defer this decision until after the whole
10848 file has been read, since there might be a .extern
10849 after the first use of this symbol. */
10850 || (before_relaxing
10851 #ifndef NO_ECOFF_DEBUGGING
10852 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10854 && S_GET_VALUE (sym
) == 0)
10855 || (S_GET_VALUE (sym
) != 0
10856 && S_GET_VALUE (sym
) <= g_switch_value
)))
10860 const char *segname
;
10862 segname
= segment_name (S_GET_SEGMENT (sym
));
10863 assert (strcmp (segname
, ".lit8") != 0
10864 && strcmp (segname
, ".lit4") != 0);
10865 change
= (strcmp (segname
, ".sdata") != 0
10866 && strcmp (segname
, ".sbss") != 0
10867 && strncmp (segname
, ".sdata.", 7) != 0
10868 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10873 /* We are not optimizing for the GP register. */
10877 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10878 extended opcode. SEC is the section the frag is in. */
10881 mips16_extended_frag (fragp
, sec
, stretch
)
10887 register const struct mips16_immed_operand
*op
;
10889 int mintiny
, maxtiny
;
10892 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10894 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10897 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10898 op
= mips16_immed_operands
;
10899 while (op
->type
!= type
)
10902 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10907 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10910 maxtiny
= 1 << op
->nbits
;
10915 maxtiny
= (1 << op
->nbits
) - 1;
10920 mintiny
= - (1 << (op
->nbits
- 1));
10921 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10924 /* We can't always call S_GET_VALUE here, because we don't want to
10925 lock in a particular frag address. */
10926 if (symbol_constant_p (fragp
->fr_symbol
))
10928 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10929 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10930 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10932 else if (symbol_equated_p (fragp
->fr_symbol
)
10933 && (symbol_constant_p
10934 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10938 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10939 val
= (S_GET_VALUE (eqsym
)
10940 + symbol_get_frag (eqsym
)->fr_address
10941 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10942 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10943 symsec
= S_GET_SEGMENT (eqsym
);
10952 /* We won't have the section when we are called from
10953 mips_relax_frag. However, we will always have been called
10954 from md_estimate_size_before_relax first. If this is a
10955 branch to a different section, we mark it as such. If SEC is
10956 NULL, and the frag is not marked, then it must be a branch to
10957 the same section. */
10960 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10967 fragp
->fr_subtype
=
10968 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10970 /* FIXME: We should support this, and let the linker
10971 catch branches and loads that are out of range. */
10972 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10973 _("unsupported PC relative reference to different section"));
10979 /* In this case, we know for sure that the symbol fragment is in
10980 the same section. If the fr_address of the symbol fragment
10981 is greater then the address of this fragment we want to add
10982 in STRETCH in order to get a better estimate of the address.
10983 This particularly matters because of the shift bits. */
10985 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10986 >= fragp
->fr_address
))
10990 /* Adjust stretch for any alignment frag. Note that if have
10991 been expanding the earlier code, the symbol may be
10992 defined in what appears to be an earlier frag. FIXME:
10993 This doesn't handle the fr_subtype field, which specifies
10994 a maximum number of bytes to skip when doing an
10997 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
11000 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11003 stretch
= - ((- stretch
)
11004 & ~ ((1 << (int) f
->fr_offset
) - 1));
11006 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11015 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11017 /* The base address rules are complicated. The base address of
11018 a branch is the following instruction. The base address of a
11019 PC relative load or add is the instruction itself, but if it
11020 is in a delay slot (in which case it can not be extended) use
11021 the address of the instruction whose delay slot it is in. */
11022 if (type
== 'p' || type
== 'q')
11026 /* If we are currently assuming that this frag should be
11027 extended, then, the current address is two bytes
11029 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11032 /* Ignore the low bit in the target, since it will be set
11033 for a text label. */
11034 if ((val
& 1) != 0)
11037 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11039 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11042 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11044 /* Branch offsets have an implicit 0 in the lowest bit. */
11045 if (type
== 'p' || type
== 'q')
11048 /* If any of the shifted bits are set, we must use an extended
11049 opcode. If the address depends on the size of this
11050 instruction, this can lead to a loop, so we arrange to always
11051 use an extended opcode. We only check this when we are in
11052 the main relaxation loop, when SEC is NULL. */
11053 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11055 fragp
->fr_subtype
=
11056 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11060 /* If we are about to mark a frag as extended because the value
11061 is precisely maxtiny + 1, then there is a chance of an
11062 infinite loop as in the following code:
11067 In this case when the la is extended, foo is 0x3fc bytes
11068 away, so the la can be shrunk, but then foo is 0x400 away, so
11069 the la must be extended. To avoid this loop, we mark the
11070 frag as extended if it was small, and is about to become
11071 extended with a value of maxtiny + 1. */
11072 if (val
== ((maxtiny
+ 1) << op
->shift
)
11073 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11076 fragp
->fr_subtype
=
11077 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11081 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11082 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11084 if ((val
& ((1 << op
->shift
) - 1)) != 0
11085 || val
< (mintiny
<< op
->shift
)
11086 || val
> (maxtiny
<< op
->shift
))
11092 /* Estimate the size of a frag before relaxing. Unless this is the
11093 mips16, we are not really relaxing here, and the final size is
11094 encoded in the subtype information. For the mips16, we have to
11095 decide whether we are using an extended opcode or not. */
11099 md_estimate_size_before_relax (fragp
, segtype
)
11104 boolean linkonce
= false;
11106 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11108 if (mips16_extended_frag (fragp
, segtype
, 0))
11110 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11115 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11120 if (mips_pic
== NO_PIC
)
11122 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11124 else if (mips_pic
== SVR4_PIC
)
11129 sym
= fragp
->fr_symbol
;
11131 /* Handle the case of a symbol equated to another symbol. */
11132 while (symbol_equated_p (sym
)
11133 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11137 /* It's possible to get a loop here in a badly written
11139 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11145 symsec
= S_GET_SEGMENT (sym
);
11147 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11148 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11150 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11154 /* The GNU toolchain uses an extension for ELF: a section
11155 beginning with the magic string .gnu.linkonce is a linkonce
11157 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11158 sizeof ".gnu.linkonce" - 1) == 0)
11162 /* This must duplicate the test in adjust_reloc_syms. */
11163 change
= (symsec
!= &bfd_und_section
11164 && symsec
!= &bfd_abs_section
11165 && ! bfd_is_com_section (symsec
)
11168 /* A weak symbol is treated as external. */
11169 && ! S_IS_WEAK (sym
)
11178 /* Record the offset to the first reloc in the fr_opcode field.
11179 This lets md_convert_frag and tc_gen_reloc know that the code
11180 must be expanded. */
11181 fragp
->fr_opcode
= (fragp
->fr_literal
11183 - RELAX_OLD (fragp
->fr_subtype
)
11184 + RELAX_RELOC1 (fragp
->fr_subtype
));
11185 /* FIXME: This really needs as_warn_where. */
11186 if (RELAX_WARN (fragp
->fr_subtype
))
11187 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11193 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11196 /* This is called to see whether a reloc against a defined symbol
11197 should be converted into a reloc against a section. Don't adjust
11198 MIPS16 jump relocations, so we don't have to worry about the format
11199 of the offset in the .o file. Don't adjust relocations against
11200 mips16 symbols, so that the linker can find them if it needs to set
11204 mips_fix_adjustable (fixp
)
11207 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11209 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11210 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11212 if (fixp
->fx_addsy
== NULL
)
11215 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11216 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11217 && fixp
->fx_subsy
== NULL
)
11223 /* Translate internal representation of relocation info to BFD target
11227 tc_gen_reloc (section
, fixp
)
11228 asection
*section ATTRIBUTE_UNUSED
;
11231 static arelent
*retval
[4];
11233 bfd_reloc_code_real_type code
;
11235 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11238 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11239 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11240 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11242 if (mips_pic
== EMBEDDED_PIC
11243 && SWITCH_TABLE (fixp
))
11245 /* For a switch table entry we use a special reloc. The addend
11246 is actually the difference between the reloc address and the
11248 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11249 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11250 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11251 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11253 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11254 reloc
->addend
= fixp
->fx_addnumber
;
11255 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11257 /* We use a special addend for an internal RELLO reloc. */
11258 if (symbol_section_p (fixp
->fx_addsy
))
11259 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11261 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11263 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11265 assert (fixp
->fx_next
!= NULL
11266 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11267 /* We use a special addend for an internal RELHI reloc. The
11268 reloc is relative to the RELLO; adjust the addend
11270 if (symbol_section_p (fixp
->fx_addsy
))
11271 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11272 + fixp
->fx_next
->fx_where
11273 - S_GET_VALUE (fixp
->fx_subsy
));
11275 reloc
->addend
= (fixp
->fx_addnumber
11276 + fixp
->fx_next
->fx_frag
->fr_address
11277 + fixp
->fx_next
->fx_where
);
11281 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11282 /* A gruesome hack which is a result of the gruesome gas reloc
11284 reloc
->addend
= reloc
->address
;
11286 reloc
->addend
= -reloc
->address
;
11289 /* If this is a variant frag, we may need to adjust the existing
11290 reloc and generate a new one. */
11291 if (fixp
->fx_frag
->fr_opcode
!= NULL
11292 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11293 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11294 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11295 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11296 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11297 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11298 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11302 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11304 /* If this is not the last reloc in this frag, then we have two
11305 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11306 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11307 the second one handle all of them. */
11308 if (fixp
->fx_next
!= NULL
11309 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11311 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11312 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11313 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11314 && (fixp
->fx_next
->fx_r_type
11315 == BFD_RELOC_MIPS_GOT_LO16
))
11316 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11317 && (fixp
->fx_next
->fx_r_type
11318 == BFD_RELOC_MIPS_CALL_LO16
)));
11323 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11324 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11325 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11327 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11328 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11329 reloc2
->address
= (reloc
->address
11330 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11331 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11332 reloc2
->addend
= fixp
->fx_addnumber
;
11333 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11334 assert (reloc2
->howto
!= NULL
);
11336 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11340 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11343 reloc3
->address
+= 4;
11346 if (mips_pic
== NO_PIC
)
11348 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11349 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11351 else if (mips_pic
== SVR4_PIC
)
11353 switch (fixp
->fx_r_type
)
11357 case BFD_RELOC_MIPS_GOT16
:
11359 case BFD_RELOC_MIPS_CALL16
:
11360 case BFD_RELOC_MIPS_GOT_LO16
:
11361 case BFD_RELOC_MIPS_CALL_LO16
:
11362 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11370 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11371 to be used in the relocation's section offset. */
11372 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11374 reloc
->address
= reloc
->addend
;
11378 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11379 fixup_segment converted a non-PC relative reloc into a PC
11380 relative reloc. In such a case, we need to convert the reloc
11382 code
= fixp
->fx_r_type
;
11383 if (fixp
->fx_pcrel
)
11388 code
= BFD_RELOC_8_PCREL
;
11391 code
= BFD_RELOC_16_PCREL
;
11394 code
= BFD_RELOC_32_PCREL
;
11397 code
= BFD_RELOC_64_PCREL
;
11399 case BFD_RELOC_8_PCREL
:
11400 case BFD_RELOC_16_PCREL
:
11401 case BFD_RELOC_32_PCREL
:
11402 case BFD_RELOC_64_PCREL
:
11403 case BFD_RELOC_16_PCREL_S2
:
11404 case BFD_RELOC_PCREL_HI16_S
:
11405 case BFD_RELOC_PCREL_LO16
:
11408 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11409 _("Cannot make %s relocation PC relative"),
11410 bfd_get_reloc_code_name (code
));
11414 /* To support a PC relative reloc when generating embedded PIC code
11415 for ECOFF, we use a Cygnus extension. We check for that here to
11416 make sure that we don't let such a reloc escape normally. */
11417 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11418 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11419 && code
== BFD_RELOC_16_PCREL_S2
11420 && mips_pic
!= EMBEDDED_PIC
)
11421 reloc
->howto
= NULL
;
11423 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11425 if (reloc
->howto
== NULL
)
11427 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11428 _("Can not represent %s relocation in this object file format"),
11429 bfd_get_reloc_code_name (code
));
11436 /* Relax a machine dependent frag. This returns the amount by which
11437 the current size of the frag should change. */
11440 mips_relax_frag (fragp
, stretch
)
11444 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11447 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11449 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11451 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11456 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11458 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11465 /* Convert a machine dependent frag. */
11468 md_convert_frag (abfd
, asec
, fragp
)
11469 bfd
*abfd ATTRIBUTE_UNUSED
;
11476 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11479 register const struct mips16_immed_operand
*op
;
11480 boolean small
, ext
;
11483 unsigned long insn
;
11484 boolean use_extend
;
11485 unsigned short extend
;
11487 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11488 op
= mips16_immed_operands
;
11489 while (op
->type
!= type
)
11492 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11503 resolve_symbol_value (fragp
->fr_symbol
, 1);
11504 val
= S_GET_VALUE (fragp
->fr_symbol
);
11509 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11511 /* The rules for the base address of a PC relative reloc are
11512 complicated; see mips16_extended_frag. */
11513 if (type
== 'p' || type
== 'q')
11518 /* Ignore the low bit in the target, since it will be
11519 set for a text label. */
11520 if ((val
& 1) != 0)
11523 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11525 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11528 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11531 /* Make sure the section winds up with the alignment we have
11534 record_alignment (asec
, op
->shift
);
11538 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11539 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11540 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11541 _("extended instruction in delay slot"));
11543 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11545 if (target_big_endian
)
11546 insn
= bfd_getb16 (buf
);
11548 insn
= bfd_getl16 (buf
);
11550 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11551 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11552 small
, ext
, &insn
, &use_extend
, &extend
);
11556 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11557 fragp
->fr_fix
+= 2;
11561 md_number_to_chars (buf
, insn
, 2);
11562 fragp
->fr_fix
+= 2;
11567 if (fragp
->fr_opcode
== NULL
)
11570 old
= RELAX_OLD (fragp
->fr_subtype
);
11571 new = RELAX_NEW (fragp
->fr_subtype
);
11572 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11575 memcpy (fixptr
- old
, fixptr
, new);
11577 fragp
->fr_fix
+= new - old
;
11583 /* This function is called after the relocs have been generated.
11584 We've been storing mips16 text labels as odd. Here we convert them
11585 back to even for the convenience of the debugger. */
11588 mips_frob_file_after_relocs ()
11591 unsigned int count
, i
;
11593 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11596 syms
= bfd_get_outsymbols (stdoutput
);
11597 count
= bfd_get_symcount (stdoutput
);
11598 for (i
= 0; i
< count
; i
++, syms
++)
11600 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11601 && ((*syms
)->value
& 1) != 0)
11603 (*syms
)->value
&= ~1;
11604 /* If the symbol has an odd size, it was probably computed
11605 incorrectly, so adjust that as well. */
11606 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11607 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11614 /* This function is called whenever a label is defined. It is used
11615 when handling branch delays; if a branch has a label, we assume we
11616 can not move it. */
11619 mips_define_label (sym
)
11622 struct insn_label_list
*l
;
11624 if (free_insn_labels
== NULL
)
11625 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11628 l
= free_insn_labels
;
11629 free_insn_labels
= l
->next
;
11633 l
->next
= insn_labels
;
11637 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11639 /* Some special processing for a MIPS ELF file. */
11642 mips_elf_final_processing ()
11644 /* Write out the register information. */
11649 s
.ri_gprmask
= mips_gprmask
;
11650 s
.ri_cprmask
[0] = mips_cprmask
[0];
11651 s
.ri_cprmask
[1] = mips_cprmask
[1];
11652 s
.ri_cprmask
[2] = mips_cprmask
[2];
11653 s
.ri_cprmask
[3] = mips_cprmask
[3];
11654 /* The gp_value field is set by the MIPS ELF backend. */
11656 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11657 ((Elf32_External_RegInfo
*)
11658 mips_regmask_frag
));
11662 Elf64_Internal_RegInfo s
;
11664 s
.ri_gprmask
= mips_gprmask
;
11666 s
.ri_cprmask
[0] = mips_cprmask
[0];
11667 s
.ri_cprmask
[1] = mips_cprmask
[1];
11668 s
.ri_cprmask
[2] = mips_cprmask
[2];
11669 s
.ri_cprmask
[3] = mips_cprmask
[3];
11670 /* The gp_value field is set by the MIPS ELF backend. */
11672 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11673 ((Elf64_External_RegInfo
*)
11674 mips_regmask_frag
));
11677 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11678 sort of BFD interface for this. */
11679 if (mips_any_noreorder
)
11680 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11681 if (mips_pic
!= NO_PIC
)
11682 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11684 /* Set the MIPS ELF ABI flags. */
11685 if (mips_abi_string
== 0)
11687 else if (strcmp (mips_abi_string
,"32") == 0)
11688 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11689 else if (strcmp (mips_abi_string
,"o64") == 0)
11690 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11691 else if (strcmp (mips_abi_string
,"eabi") == 0)
11694 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11696 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11699 if (mips_32bitmode
)
11700 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11703 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11705 typedef struct proc
11708 unsigned long reg_mask
;
11709 unsigned long reg_offset
;
11710 unsigned long fpreg_mask
;
11711 unsigned long fpreg_offset
;
11712 unsigned long frame_offset
;
11713 unsigned long frame_reg
;
11714 unsigned long pc_reg
;
11718 static procS cur_proc
;
11719 static procS
*cur_proc_ptr
;
11720 static int numprocs
;
11722 /* When we align code in the .text section of mips16, use the correct two
11723 byte nop pattern of 0x6500 (move $0,$0) */
11726 mips_do_align (n
, fill
, len
, max
)
11729 int len ATTRIBUTE_UNUSED
;
11733 && subseg_text_p (now_seg
)
11735 && mips_opts
.mips16
)
11737 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11738 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11740 frag_align (1, 0, 0);
11742 if (target_big_endian
)
11743 frag_align_pattern (n
, be_nop
, 2, max
);
11745 frag_align_pattern (n
, le_nop
, 2, max
);
11760 /* check for premature end, nesting errors, etc */
11762 as_warn (_("missing `.end' at end of assembly"));
11771 if (*input_line_pointer
== '-')
11773 ++input_line_pointer
;
11776 if (!isdigit ((unsigned char) *input_line_pointer
))
11777 as_bad (_("Expected simple number."));
11778 if (input_line_pointer
[0] == '0')
11780 if (input_line_pointer
[1] == 'x')
11782 input_line_pointer
+= 2;
11783 while (isxdigit ((unsigned char) *input_line_pointer
))
11786 val
|= hex_value (*input_line_pointer
++);
11788 return negative
? -val
: val
;
11792 ++input_line_pointer
;
11793 while (isdigit ((unsigned char) *input_line_pointer
))
11796 val
|= *input_line_pointer
++ - '0';
11798 return negative
? -val
: val
;
11801 if (!isdigit ((unsigned char) *input_line_pointer
))
11803 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11804 *input_line_pointer
, *input_line_pointer
);
11805 as_warn (_("Invalid number"));
11808 while (isdigit ((unsigned char) *input_line_pointer
))
11811 val
+= *input_line_pointer
++ - '0';
11813 return negative
? -val
: val
;
11816 /* The .file directive; just like the usual .file directive, but there
11817 is an initial number which is the ECOFF file index. */
11821 int x ATTRIBUTE_UNUSED
;
11825 line
= get_number ();
11829 /* The .end directive. */
11833 int x ATTRIBUTE_UNUSED
;
11838 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11841 demand_empty_rest_of_line ();
11846 #ifdef BFD_ASSEMBLER
11847 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11852 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11859 as_warn (_(".end not in text section"));
11863 as_warn (_(".end directive without a preceding .ent directive."));
11864 demand_empty_rest_of_line ();
11870 assert (S_GET_NAME (p
));
11871 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11872 as_warn (_(".end symbol does not match .ent symbol."));
11875 as_warn (_(".end directive missing or unknown symbol"));
11877 #ifdef MIPS_STABS_ELF
11879 segT saved_seg
= now_seg
;
11880 subsegT saved_subseg
= now_subseg
;
11881 fragS
*saved_frag
= frag_now
;
11887 dot
= frag_now_fix ();
11889 #ifdef md_flush_pending_output
11890 md_flush_pending_output ();
11894 subseg_set (pdr_seg
, 0);
11896 /* Write the symbol */
11897 exp
.X_op
= O_symbol
;
11898 exp
.X_add_symbol
= p
;
11899 exp
.X_add_number
= 0;
11900 emit_expr (&exp
, 4);
11902 fragp
= frag_more (7*4);
11904 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11905 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11906 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11907 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11908 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11909 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11910 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11912 subseg_set (saved_seg
, saved_subseg
);
11916 cur_proc_ptr
= NULL
;
11919 /* The .aent and .ent directives. */
11929 symbolP
= get_symbol ();
11930 if (*input_line_pointer
== ',')
11931 input_line_pointer
++;
11932 SKIP_WHITESPACE ();
11933 if (isdigit ((unsigned char) *input_line_pointer
)
11934 || *input_line_pointer
== '-')
11935 number
= get_number ();
11937 #ifdef BFD_ASSEMBLER
11938 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11943 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11950 as_warn (_(".ent or .aent not in text section."));
11952 if (!aent
&& cur_proc_ptr
)
11953 as_warn (_("missing `.end'"));
11957 cur_proc_ptr
= &cur_proc
;
11958 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11960 cur_proc_ptr
->isym
= symbolP
;
11962 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11967 demand_empty_rest_of_line ();
11970 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11971 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11972 s_mips_frame is used so that we can set the PDR information correctly.
11973 We can't use the ecoff routines because they make reference to the ecoff
11974 symbol table (in the mdebug section). */
11977 s_mips_frame (ignore
)
11980 #ifdef MIPS_STABS_ELF
11984 if (cur_proc_ptr
== (procS
*) NULL
)
11986 as_warn (_(".frame outside of .ent"));
11987 demand_empty_rest_of_line ();
11991 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11993 SKIP_WHITESPACE ();
11994 if (*input_line_pointer
++ != ','
11995 || get_absolute_expression_and_terminator (&val
) != ',')
11997 as_warn (_("Bad .frame directive"));
11998 --input_line_pointer
;
11999 demand_empty_rest_of_line ();
12003 cur_proc_ptr
->frame_offset
= val
;
12004 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12006 demand_empty_rest_of_line ();
12009 #endif /* MIPS_STABS_ELF */
12012 /* The .fmask and .mask directives. If the mdebug section is present
12013 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12014 embedded targets, s_mips_mask is used so that we can set the PDR
12015 information correctly. We can't use the ecoff routines because they
12016 make reference to the ecoff symbol table (in the mdebug section). */
12019 s_mips_mask (reg_type
)
12022 #ifdef MIPS_STABS_ELF
12025 if (cur_proc_ptr
== (procS
*) NULL
)
12027 as_warn (_(".mask/.fmask outside of .ent"));
12028 demand_empty_rest_of_line ();
12032 if (get_absolute_expression_and_terminator (&mask
) != ',')
12034 as_warn (_("Bad .mask/.fmask directive"));
12035 --input_line_pointer
;
12036 demand_empty_rest_of_line ();
12040 off
= get_absolute_expression ();
12042 if (reg_type
== 'F')
12044 cur_proc_ptr
->fpreg_mask
= mask
;
12045 cur_proc_ptr
->fpreg_offset
= off
;
12049 cur_proc_ptr
->reg_mask
= mask
;
12050 cur_proc_ptr
->reg_offset
= off
;
12053 demand_empty_rest_of_line ();
12055 s_ignore (reg_type
);
12056 #endif /* MIPS_STABS_ELF */
12059 /* The .loc directive. */
12070 assert (now_seg
== text_section
);
12072 lineno
= get_number ();
12073 addroff
= frag_now_fix ();
12075 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12076 S_SET_TYPE (symbolP
, N_SLINE
);
12077 S_SET_OTHER (symbolP
, 0);
12078 S_SET_DESC (symbolP
, lineno
);
12079 symbolP
->sy_segment
= now_seg
;