1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
27 #include "libiberty.h"
42 #endif /* NO_VARARGS */
43 #endif /* NO_STDARG */
45 #include "opcode/mips.h"
50 static char *mips_regmask_frag
;
54 #define PIC_CALL_REG 25
62 /* Decide whether to do GP reference optimizations based on the object
72 /* The default target format to use. */
74 #ifdef TARGET_BYTES_BIG_ENDIAN
75 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
77 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
81 #ifdef TARGET_BYTES_BIG_ENDIAN
82 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
84 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
86 #endif /* OBJ_ECOFF */
88 #ifdef TARGET_BYTES_BIG_ENDIAN
89 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
91 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
95 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
97 /* The name of the readonly data section. */
99 #define RDATA_SECTION_NAME ".data"
102 #define RDATA_SECTION_NAME ".rdata"
105 #define RDATA_SECTION_NAME ".rodata"
108 /* These variables are filled in with the masks of registers used.
109 The object format code reads them and puts them in the appropriate
111 unsigned long mips_gprmask
;
112 unsigned long mips_cprmask
[4];
114 /* MIPS ISA (Instruction Set Architecture) level (may be changed
115 temporarily using .set mipsN). */
116 static int mips_isa
= -1;
118 /* MIPS ISA we are using for this output file. */
119 static int file_mips_isa
;
121 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
122 static int mips_cpu
= -1;
124 /* Whether the 4650 instructions (mad/madu) are permitted. */
125 static int mips_4650
= -1;
127 /* MIPS PIC level. */
131 /* Do not generate PIC code. */
134 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
135 not sure what it is supposed to do. */
138 /* Generate PIC code as in the SVR4 MIPS ABI. */
141 /* Generate PIC code without using a global offset table: the data
142 segment has a maximum size of 64K, all data references are off
143 the $gp register, and all text references are PC relative. This
144 is used on some embedded systems. */
148 static enum mips_pic_level mips_pic
;
150 /* 1 if trap instructions should used for overflow rather than break
152 static int mips_trap
;
154 static int mips_warn_about_macros
;
155 static int mips_noreorder
;
156 static int mips_any_noreorder
;
157 static int mips_nomove
;
158 static int mips_noat
;
159 static int mips_nobopt
;
162 /* The size of the small data section. */
163 static int g_switch_value
= 8;
164 /* Whether the -G option was used. */
165 static int g_switch_seen
= 0;
171 /* handle of the OPCODE hash table */
172 static struct hash_control
*op_hash
= NULL
;
174 /* This array holds the chars that always start a comment. If the
175 pre-processor is disabled, these aren't very useful */
176 const char comment_chars
[] = "#";
178 /* This array holds the chars that only start a comment at the beginning of
179 a line. If the line seems to have the form '# 123 filename'
180 .line and .file directives will appear in the pre-processed output */
181 /* Note that input_file.c hand checks for '#' at the beginning of the
182 first line of the input file. This is because the compiler outputs
183 #NO_APP at the beginning of its output. */
184 /* Also note that C style comments are always supported. */
185 const char line_comment_chars
[] = "#";
187 /* This array holds machine specific line separator characters. */
188 const char line_separator_chars
[] = "";
190 /* Chars that can be used to separate mant from exp in floating point nums */
191 const char EXP_CHARS
[] = "eE";
193 /* Chars that mean this number is a floating point constant */
196 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c . Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here.
203 static char *insn_error
;
205 static int byte_order
= BYTE_ORDER
;
207 static int auto_align
= 1;
209 /* Symbol labelling the current insn. */
210 static symbolS
*insn_label
;
212 /* When outputting SVR4 PIC code, the assembler needs to know the
213 offset in the stack frame from which to restore the $gp register.
214 This is set by the .cprestore pseudo-op, and saved in this
216 static offsetT mips_cprestore_offset
= -1;
218 /* This is the register which holds the stack frame, as set by the
219 .frame pseudo-op. This is needed to implement .cprestore. */
220 static int mips_frame_reg
= SP
;
222 /* To output NOP instructions correctly, we need to keep information
223 about the previous two instructions. */
225 /* Whether we are optimizing. The default value of 2 means to remove
226 unneeded NOPs and swap branch instructions when possible. A value
227 of 1 means to not swap branches. A value of 0 means to always
229 static int mips_optimize
= 2;
231 /* The previous instruction. */
232 static struct mips_cl_insn prev_insn
;
234 /* The instruction before prev_insn. */
235 static struct mips_cl_insn prev_prev_insn
;
237 /* If we don't want information for prev_insn or prev_prev_insn, we
238 point the insn_mo field at this dummy integer. */
239 static const struct mips_opcode dummy_opcode
= { 0 };
241 /* Non-zero if prev_insn is valid. */
242 static int prev_insn_valid
;
244 /* The frag for the previous instruction. */
245 static struct frag
*prev_insn_frag
;
247 /* The offset into prev_insn_frag for the previous instruction. */
248 static long prev_insn_where
;
250 /* The reloc for the previous instruction, if any. */
251 static fixS
*prev_insn_fixp
;
253 /* Non-zero if the previous instruction was in a delay slot. */
254 static int prev_insn_is_delay_slot
;
256 /* Non-zero if the previous instruction was in a .set noreorder. */
257 static int prev_insn_unreordered
;
259 /* Non-zero if the previous previous instruction was in a .set
261 static int prev_prev_insn_unreordered
;
263 /* Since the MIPS does not have multiple forms of PC relative
264 instructions, we do not have to do relaxing as is done on other
265 platforms. However, we do have to handle GP relative addressing
266 correctly, which turns out to be a similar problem.
268 Every macro that refers to a symbol can occur in (at least) two
269 forms, one with GP relative addressing and one without. For
270 example, loading a global variable into a register generally uses
271 a macro instruction like this:
273 If i can be addressed off the GP register (this is true if it is in
274 the .sbss or .sdata section, or if it is known to be smaller than
275 the -G argument) this will generate the following instruction:
277 This instruction will use a GPREL reloc. If i can not be addressed
278 off the GP register, the following instruction sequence will be used:
281 In this case the first instruction will have a HI16 reloc, and the
282 second reloc will have a LO16 reloc. Both relocs will be against
285 The issue here is that we may not know whether i is GP addressable
286 until after we see the instruction that uses it. Therefore, we
287 want to be able to choose the final instruction sequence only at
288 the end of the assembly. This is similar to the way other
289 platforms choose the size of a PC relative instruction only at the
292 When generating position independent code we do not use GP
293 addressing in quite the same way, but the issue still arises as
294 external symbols and local symbols must be handled differently.
296 We handle these issues by actually generating both possible
297 instruction sequences. The longer one is put in a frag_var with
298 type rs_machine_dependent. We encode what to do with the frag in
299 the subtype field. We encode (1) the number of existing bytes to
300 replace, (2) the number of new bytes to use, (3) the offset from
301 the start of the existing bytes to the first reloc we must generate
302 (that is, the offset is applied from the start of the existing
303 bytes after they are replaced by the new bytes, if any), (4) the
304 offset from the start of the existing bytes to the second reloc,
305 (5) whether a third reloc is needed (the third reloc is always four
306 bytes after the second reloc), and (6) whether to warn if this
307 variant is used (this is sometimes needed if .set nomacro or .set
308 noat is in effect). All these numbers are reasonably small.
310 Generating two instruction sequences must be handled carefully to
311 ensure that delay slots are handled correctly. Fortunately, there
312 are a limited number of cases. When the second instruction
313 sequence is generated, append_insn is directed to maintain the
314 existing delay slot information, so it continues to apply to any
315 code after the second instruction sequence. This means that the
316 second instruction sequence must not impose any requirements not
317 required by the first instruction sequence.
319 These variant frags are then handled in functions called by the
320 machine independent code. md_estimate_size_before_relax returns
321 the final size of the frag. md_convert_frag sets up the final form
322 of the frag. tc_gen_reloc adjust the first reloc and adds a second
324 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
328 | (((reloc1) + 64) << 9) \
329 | (((reloc2) + 64) << 2) \
330 | ((reloc3) ? (1 << 1) : 0) \
332 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
333 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
334 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
335 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
336 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
337 #define RELAX_WARN(i) ((i) & 1)
339 /* Prototypes for static functions. */
342 #define internalError() \
343 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
345 #define internalError() as_fatal ("MIPS internal Error");
348 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
349 unsigned int reg
, int fpr
));
350 static void append_insn
PARAMS ((char *place
,
351 struct mips_cl_insn
* ip
,
353 bfd_reloc_code_real_type r
));
354 static void mips_no_prev_insn
PARAMS ((void));
355 static void mips_emit_delays
PARAMS ((void));
356 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
357 const char *name
, const char *fmt
,
359 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
360 expressionS
* ep
, int regnum
));
361 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
362 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
364 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
365 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
366 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
367 #ifdef LOSING_COMPILER
368 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
370 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
371 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
372 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
373 static symbolS
*get_symbol
PARAMS ((void));
374 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
375 static void s_align
PARAMS ((int));
376 static void s_stringer
PARAMS ((int));
377 static void s_change_sec
PARAMS ((int));
378 static void s_cons
PARAMS ((int));
379 static void s_err
PARAMS ((int));
380 static void s_extern
PARAMS ((int));
381 static void s_float_cons
PARAMS ((int));
382 static void s_mips_globl
PARAMS ((int));
383 static void s_option
PARAMS ((int));
384 static void s_mipsset
PARAMS ((int));
385 static void s_mips_space
PARAMS ((int));
386 static void s_abicalls
PARAMS ((int));
387 static void s_cpload
PARAMS ((int));
388 static void s_cprestore
PARAMS ((int));
389 static void s_gpword
PARAMS ((int));
390 static void s_cpadd
PARAMS ((int));
391 #ifndef ECOFF_DEBUGGING
392 static void md_obj_begin
PARAMS ((void));
393 static void md_obj_end
PARAMS ((void));
394 static long get_number
PARAMS ((void));
395 static void s_ent
PARAMS ((int));
396 static void s_mipsend
PARAMS ((int));
397 static void s_file
PARAMS ((int));
399 static void s_frame
PARAMS ((int));
400 static void s_loc
PARAMS ((int));
401 static void s_mask
PARAMS ((char));
405 static void s_elf_section
PARAMS ((int));
410 The following pseudo-ops from the Kane and Heinrich MIPS book
411 should be defined here, but are currently unsupported: .alias,
412 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
414 The following pseudo-ops from the Kane and Heinrich MIPS book are
415 specific to the type of debugging information being generated, and
416 should be defined by the object format: .aent, .begin, .bend,
417 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
420 The following pseudo-ops from the Kane and Heinrich MIPS book are
421 not MIPS CPU specific, but are also not specific to the object file
422 format. This file is probably the best place to define them, but
423 they are not currently supported: .asm0, .endr, .lab, .repeat,
424 .struct, .weakext. */
426 const pseudo_typeS md_pseudo_table
[] =
428 /* MIPS specific pseudo-ops. */
429 {"option", s_option
, 0},
430 {"set", s_mipsset
, 0},
431 {"rdata", s_change_sec
, 'r'},
432 {"sdata", s_change_sec
, 's'},
433 {"livereg", s_ignore
, 0},
434 { "abicalls", s_abicalls
, 0},
435 { "cpload", s_cpload
, 0},
436 { "cprestore", s_cprestore
, 0},
437 { "gpword", s_gpword
, 0},
438 { "cpadd", s_cpadd
, 0},
440 /* Relatively generic pseudo-ops that happen to be used on MIPS
442 {"asciiz", s_stringer
, 1},
443 {"bss", s_change_sec
, 'b'},
446 {"dword", s_cons
, 3},
448 /* These pseudo-ops are defined in read.c, but must be overridden
449 here for one reason or another. */
450 {"align", s_align
, 0},
451 {"ascii", s_stringer
, 0},
452 {"asciz", s_stringer
, 1},
454 {"data", s_change_sec
, 'd'},
455 {"double", s_float_cons
, 'd'},
456 {"extern", s_extern
, 0},
457 {"float", s_float_cons
, 'f'},
458 {"globl", s_mips_globl
, 0},
459 {"global", s_mips_globl
, 0},
460 {"hword", s_cons
, 1},
465 {"short", s_cons
, 1},
466 {"single", s_float_cons
, 'f'},
467 {"space", s_mips_space
, 0},
468 {"text", s_change_sec
, 't'},
471 #ifndef ECOFF_DEBUGGING
472 /* These pseudo-ops should be defined by the object file format.
473 However, a.out doesn't support them, so we have versions here. */
475 {"bgnb", s_ignore
, 0},
476 {"end", s_mipsend
, 0},
477 {"endb", s_ignore
, 0},
480 {"fmask", s_ignore
, 'F'},
481 {"frame", s_ignore
, 0},
482 {"loc", s_ignore
, 0},
483 {"mask", s_ignore
, 'R'},
484 {"verstamp", s_ignore
, 0},
488 /* We need to tweak the ELF ".section" pseudo-op a bit. */
489 {"section", s_elf_section
, 0},
496 const relax_typeS md_relax_table
[] =
501 static char *expr_end
;
503 static expressionS imm_expr
;
504 static expressionS offset_expr
;
505 static bfd_reloc_code_real_type imm_reloc
;
506 static bfd_reloc_code_real_type offset_reloc
;
508 /* FIXME: This should be handled in a different way. */
509 extern int target_big_endian
;
512 * This function is called once, at assembler startup time. It should
513 * set up all the tables, etc. that the MD part of the assembler will need.
519 register const char *retval
= NULL
;
520 register unsigned int i
= 0;
528 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
530 a
= xmalloc (sizeof TARGET_CPU
);
531 strcpy (a
, TARGET_CPU
);
532 a
[(sizeof TARGET_CPU
) - 3] = '\0';
536 if (strcmp (cpu
, "mips") == 0)
542 else if (strcmp (cpu
, "r6000") == 0
543 || strcmp (cpu
, "mips2") == 0)
549 else if (strcmp (cpu
, "mips64") == 0
550 || strcmp (cpu
, "r4000") == 0
551 || strcmp (cpu
, "mips3") == 0)
557 else if (strcmp (cpu
, "r4400") == 0)
563 else if (strcmp (cpu
, "mips64orion") == 0
564 || strcmp (cpu
, "r4600") == 0)
570 else if (strcmp (cpu
, "r4650") == 0)
592 if (mips_isa
< 2 && mips_trap
)
593 as_bad ("trap exception not supported at ISA 1");
598 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
601 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
604 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
608 as_warn ("Could not set architecture and machine");
610 file_mips_isa
= mips_isa
;
612 op_hash
= hash_new ();
614 for (i
= 0; i
< NUMOPCODES
;)
616 const char *name
= mips_opcodes
[i
].name
;
618 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
621 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
622 mips_opcodes
[i
].name
, retval
);
623 as_fatal ("Broken assembler. No assembly attempted.");
627 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
628 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
629 != mips_opcodes
[i
].match
))
631 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
632 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
633 as_fatal ("Broken assembler. No assembly attempted.");
637 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
640 mips_no_prev_insn ();
648 /* set the default alignment for the text section (2**2) */
649 record_alignment (text_section
, 2);
651 /* FIXME: This should be handled in a different way. */
652 target_big_endian
= byte_order
== BIG_ENDIAN
;
655 bfd_set_gp_size (stdoutput
, g_switch_value
);
659 /* Sections must be aligned to 16 byte boundaries. */
660 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
661 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
662 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
664 /* Create a .reginfo section for register masks and a .mdebug
665 section for debugging information. */
673 sec
= subseg_new (".reginfo", (subsegT
) 0);
675 /* The ABI says this section should be loaded so that the running
676 program can access it. */
677 (void) bfd_set_section_flags (stdoutput
, sec
,
678 (SEC_ALLOC
| SEC_LOAD
679 | SEC_READONLY
| SEC_DATA
));
680 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
682 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
684 #ifdef ECOFF_DEBUGGING
685 sec
= subseg_new (".mdebug", (subsegT
) 0);
686 (void) bfd_set_section_flags (stdoutput
, sec
,
687 SEC_HAS_CONTENTS
| SEC_READONLY
);
688 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
691 subseg_set (seg
, subseg
);
695 #ifndef ECOFF_DEBUGGING
703 #ifndef ECOFF_DEBUGGING
712 struct mips_cl_insn insn
;
714 imm_expr
.X_op
= O_absent
;
715 offset_expr
.X_op
= O_absent
;
717 mips_ip (str
, &insn
);
720 as_bad ("%s `%s'", insn_error
, str
);
723 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
729 if (imm_expr
.X_op
!= O_absent
)
730 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
731 else if (offset_expr
.X_op
!= O_absent
)
732 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
734 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
738 /* See whether instruction IP reads register REG. If FPR is non-zero,
739 REG is a floating point register. */
742 insn_uses_reg (ip
, reg
, fpr
)
743 struct mips_cl_insn
*ip
;
747 /* Don't report on general register 0, since it never changes. */
748 if (! fpr
&& reg
== 0)
753 /* If we are called with either $f0 or $f1, we must check $f0.
754 This is not optimal, because it will introduce an unnecessary
755 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
756 need to distinguish reading both $f0 and $f1 or just one of
757 them. Note that we don't have to check the other way,
758 because there is no instruction that sets both $f0 and $f1
759 and requires a delay. */
760 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
761 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
762 == (reg
&~ (unsigned) 1)))
764 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
765 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
766 == (reg
&~ (unsigned) 1)))
771 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
772 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
774 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
775 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
782 /* Output an instruction. PLACE is where to put the instruction; if
783 it is NULL, this uses frag_more to get room. IP is the instruction
784 information. ADDRESS_EXPR is an operand of the instruction to be
785 used with RELOC_TYPE. */
788 append_insn (place
, ip
, address_expr
, reloc_type
)
790 struct mips_cl_insn
*ip
;
791 expressionS
*address_expr
;
792 bfd_reloc_code_real_type reloc_type
;
794 register unsigned long prev_pinfo
, pinfo
;
799 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
800 pinfo
= ip
->insn_mo
->pinfo
;
802 if (place
== NULL
&& ! mips_noreorder
)
804 /* If the previous insn required any delay slots, see if we need
805 to insert a NOP or two. There are eight kinds of possible
806 hazards, of which an instruction can have at most one type.
807 (1) a load from memory delay
808 (2) a load from a coprocessor delay
809 (3) an unconditional branch delay
810 (4) a conditional branch delay
811 (5) a move to coprocessor register delay
812 (6) a load coprocessor register from memory delay
813 (7) a coprocessor condition code delay
814 (8) a HI/LO special register delay
816 There are a lot of optimizations we could do that we don't.
817 In particular, we do not, in general, reorder instructions.
818 If you use gcc with optimization, it will reorder
819 instructions and generally do much more optimization then we
820 do here; repeating all that work in the assembler would only
821 benefit hand written assembly code, and does not seem worth
824 /* This is how a NOP is emitted. */
825 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
827 /* The previous insn might require a delay slot, depending upon
828 the contents of the current insn. */
829 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
831 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
833 /* A load from a coprocessor or from memory. All load
834 delays delay the use of general register rt for one
835 instruction on the r3000. The r6000 and r4000 use
837 know (prev_pinfo
& INSN_WRITE_GPR_T
);
838 if (mips_optimize
== 0
839 || insn_uses_reg (ip
,
840 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
845 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
847 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
849 /* A generic coprocessor delay. The previous instruction
850 modified a coprocessor general or control register. If
851 it modified a control register, we need to avoid any
852 coprocessor instruction (this is probably not always
853 required, but it sometimes is). If it modified a general
854 register, we avoid using that register.
856 On the r6000 and r4000 loading a coprocessor register
857 from memory is interlocked, and does not require a delay.
859 This case is not handled very well. There is no special
860 knowledge of CP0 handling, and the coprocessors other
861 than the floating point unit are not distinguished at
863 if (prev_pinfo
& INSN_WRITE_FPR_T
)
865 if (mips_optimize
== 0
866 || insn_uses_reg (ip
,
867 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
872 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
874 if (mips_optimize
== 0
875 || insn_uses_reg (ip
,
876 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
883 /* We don't know exactly what the previous instruction
884 does. If the current instruction uses a coprocessor
885 register, we must insert a NOP. If previous
886 instruction may set the condition codes, and the
887 current instruction uses them, we must insert two
889 if (mips_optimize
== 0
890 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
891 && (pinfo
& INSN_READ_COND_CODE
)))
893 else if (pinfo
& INSN_COP
)
897 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
899 /* The previous instruction sets the coprocessor condition
900 codes, but does not require a general coprocessor delay
901 (this means it is a floating point comparison
902 instruction). If this instruction uses the condition
903 codes, we need to insert a single NOP. */
904 if (mips_optimize
== 0
905 || (pinfo
& INSN_READ_COND_CODE
))
908 else if (prev_pinfo
& INSN_READ_LO
)
910 /* The previous instruction reads the LO register; if the
911 current instruction writes to the LO register, we must
912 insert two NOPS. The R4650 has interlocks. */
914 && (mips_optimize
== 0
915 || (pinfo
& INSN_WRITE_LO
)))
918 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
920 /* The previous instruction reads the HI register; if the
921 current instruction writes to the HI register, we must
922 insert a NOP. The R4650 has interlocks. */
924 && (mips_optimize
== 0
925 || (pinfo
& INSN_WRITE_HI
)))
929 /* There are two cases which require two intervening
930 instructions: 1) setting the condition codes using a move to
931 coprocessor instruction which requires a general coprocessor
932 delay and then reading the condition codes 2) reading the HI
933 or LO register and then writing to it (except on the R4650,
934 which has interlocks). If we are not already emitting a NOP
935 instruction, we must check for these cases compared to the
936 instruction previous to the previous instruction. */
938 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
939 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
940 && (pinfo
& INSN_READ_COND_CODE
))
941 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
942 && (pinfo
& INSN_WRITE_LO
)
944 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
945 && (pinfo
& INSN_WRITE_HI
)
949 /* If we are being given a nop instruction, don't bother with
950 one of the nops we would otherwise output. This will only
951 happen when a nop instruction is used with mips_optimize set
953 if (nops
> 0 && ip
->insn_opcode
== 0)
956 /* Now emit the right number of NOP instructions. */
961 for (i
= 0; i
< nops
; i
++)
964 listing_prev_line ();
965 if (insn_label
!= NULL
)
967 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
968 insn_label
->sy_frag
= frag_now
;
969 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
979 if (address_expr
!= NULL
)
981 if (address_expr
->X_op
== O_constant
)
986 ip
->insn_opcode
|= address_expr
->X_add_number
;
990 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
993 case BFD_RELOC_MIPS_JMP
:
994 case BFD_RELOC_16_PCREL_S2
:
1003 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1005 /* Don't generate a reloc if we are writing into a variant
1008 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1010 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1015 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1017 /* Update the register mask information. */
1018 if (pinfo
& INSN_WRITE_GPR_D
)
1019 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1020 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1021 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1022 if (pinfo
& INSN_READ_GPR_S
)
1023 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1024 if (pinfo
& INSN_WRITE_GPR_31
)
1025 mips_gprmask
|= 1 << 31;
1026 if (pinfo
& INSN_WRITE_FPR_D
)
1027 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1028 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1029 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1030 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1031 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1032 if (pinfo
& INSN_COP
)
1034 /* We don't keep enough information to sort these cases out. */
1036 /* Never set the bit for $0, which is always zero. */
1037 mips_gprmask
&=~ 1 << 0;
1039 if (place
== NULL
&& ! mips_noreorder
)
1041 /* Filling the branch delay slot is more complex. We try to
1042 switch the branch with the previous instruction, which we can
1043 do if the previous instruction does not set up a condition
1044 that the branch tests and if the branch is not itself the
1045 target of any branch. */
1046 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1047 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1049 if (mips_optimize
< 2
1050 /* If we have seen .set volatile or .set nomove, don't
1053 /* If we had to emit any NOP instructions, then we
1054 already know we can not swap. */
1056 /* If we don't even know the previous insn, we can not
1058 || ! prev_insn_valid
1059 /* If the previous insn is already in a branch delay
1060 slot, then we can not swap. */
1061 || prev_insn_is_delay_slot
1062 /* If the previous previous insn was in a .set
1063 noreorder, we can't swap. Actually, the MIPS
1064 assembler will swap in this situation. However, gcc
1065 configured -with-gnu-as will generate code like
1071 in which we can not swap the bne and INSN. If gcc is
1072 not configured -with-gnu-as, it does not output the
1073 .set pseudo-ops. We don't have to check
1074 prev_insn_unreordered, because prev_insn_valid will
1075 be 0 in that case. We don't want to use
1076 prev_prev_insn_valid, because we do want to be able
1077 to swap at the start of a function. */
1078 || prev_prev_insn_unreordered
1079 /* If the branch is itself the target of a branch, we
1080 can not swap. We cheat on this; all we check for is
1081 whether there is a label on this instruction. If
1082 there are any branches to anything other than a
1083 label, users must use .set noreorder. */
1084 || insn_label
!= NULL
1085 /* If the previous instruction is in a variant frag, we
1086 can not do the swap. */
1087 || prev_insn_frag
->fr_type
== rs_machine_dependent
1088 /* If the branch reads the condition codes, we don't
1089 even try to swap, because in the sequence
1094 we can not swap, and I don't feel like handling that
1096 || (pinfo
& INSN_READ_COND_CODE
)
1097 /* We can not swap with an instruction that requires a
1098 delay slot, becase the target of the branch might
1099 interfere with that instruction. */
1101 & (INSN_LOAD_COPROC_DELAY
1102 | INSN_COPROC_MOVE_DELAY
1103 | INSN_WRITE_COND_CODE
))
1110 & (INSN_LOAD_MEMORY_DELAY
1111 | INSN_COPROC_MEMORY_DELAY
)))
1112 /* We can not swap with a branch instruction. */
1114 & (INSN_UNCOND_BRANCH_DELAY
1115 | INSN_COND_BRANCH_DELAY
1116 | INSN_COND_BRANCH_LIKELY
))
1117 /* We do not swap with a trap instruction, since it
1118 complicates trap handlers to have the trap
1119 instruction be in a delay slot. */
1120 || (prev_pinfo
& INSN_TRAP
)
1121 /* If the branch reads a register that the previous
1122 instruction sets, we can not swap. */
1123 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1124 && insn_uses_reg (ip
,
1125 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1128 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1129 && insn_uses_reg (ip
,
1130 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1133 /* If the branch writes a register that the previous
1134 instruction sets, we can not swap (we know that
1135 branches write only to RD or to $31). */
1136 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1137 && (((pinfo
& INSN_WRITE_GPR_D
)
1138 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1139 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1140 || ((pinfo
& INSN_WRITE_GPR_31
)
1141 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1144 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1145 && (((pinfo
& INSN_WRITE_GPR_D
)
1146 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1147 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1148 || ((pinfo
& INSN_WRITE_GPR_31
)
1149 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1152 /* If the branch writes a register that the previous
1153 instruction reads, we can not swap (we know that
1154 branches only write to RD or to $31). */
1155 || ((pinfo
& INSN_WRITE_GPR_D
)
1156 && insn_uses_reg (&prev_insn
,
1157 ((ip
->insn_opcode
>> OP_SH_RD
)
1160 || ((pinfo
& INSN_WRITE_GPR_31
)
1161 && insn_uses_reg (&prev_insn
, 31, 0))
1162 /* If we are generating embedded PIC code, the branch
1163 might be expanded into a sequence which uses $at, so
1164 we can't swap with an instruction which reads it. */
1165 || (mips_pic
== EMBEDDED_PIC
1166 && insn_uses_reg (&prev_insn
, AT
, 0))
1167 /* If the previous previous instruction has a load
1168 delay, and sets a register that the branch reads, we
1170 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1172 && (prev_prev_insn
.insn_mo
->pinfo
1173 & INSN_LOAD_MEMORY_DELAY
)))
1174 && insn_uses_reg (ip
,
1175 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1179 /* We could do even better for unconditional branches to
1180 portions of this object file; we could pick up the
1181 instruction at the destination, put it in the delay
1182 slot, and bump the destination address. */
1184 /* Update the previous insn information. */
1185 prev_prev_insn
= *ip
;
1186 prev_insn
.insn_mo
= &dummy_opcode
;
1193 /* It looks like we can actually do the swap. */
1194 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1195 memcpy (temp
, prev_f
, 4);
1196 memcpy (prev_f
, f
, 4);
1197 memcpy (f
, temp
, 4);
1200 prev_insn_fixp
->fx_frag
= frag_now
;
1201 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1205 fixp
->fx_frag
= prev_insn_frag
;
1206 fixp
->fx_where
= prev_insn_where
;
1208 /* Update the previous insn information; leave prev_insn
1210 prev_prev_insn
= *ip
;
1212 prev_insn_is_delay_slot
= 1;
1214 /* If that was an unconditional branch, forget the previous
1215 insn information. */
1216 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1218 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1219 prev_insn
.insn_mo
= &dummy_opcode
;
1222 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1224 /* We don't yet optimize a branch likely. What we should do
1225 is look at the target, copy the instruction found there
1226 into the delay slot, and increment the branch to jump to
1227 the next instruction. */
1229 /* Update the previous insn information. */
1230 prev_prev_insn
= *ip
;
1231 prev_insn
.insn_mo
= &dummy_opcode
;
1235 /* Update the previous insn information. */
1237 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1239 prev_prev_insn
= prev_insn
;
1242 /* Any time we see a branch, we always fill the delay slot
1243 immediately; since this insn is not a branch, we know it
1244 is not in a delay slot. */
1245 prev_insn_is_delay_slot
= 0;
1248 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1249 prev_insn_unreordered
= 0;
1250 prev_insn_frag
= frag_now
;
1251 prev_insn_where
= f
- frag_now
->fr_literal
;
1252 prev_insn_fixp
= fixp
;
1253 prev_insn_valid
= 1;
1256 /* We just output an insn, so the next one doesn't have a label. */
1260 /* This function forgets that there was any previous instruction or
1264 mips_no_prev_insn ()
1266 prev_insn
.insn_mo
= &dummy_opcode
;
1267 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1268 prev_insn_valid
= 0;
1269 prev_insn_is_delay_slot
= 0;
1270 prev_insn_unreordered
= 0;
1271 prev_prev_insn_unreordered
= 0;
1275 /* This function must be called whenever we turn on noreorder or emit
1276 something other than instructions. It inserts any NOPS which might
1277 be needed by the previous instruction, and clears the information
1278 kept for the previous instructions. */
1283 if (! mips_noreorder
)
1288 if ((prev_insn
.insn_mo
->pinfo
1289 & (INSN_LOAD_COPROC_DELAY
1290 | INSN_COPROC_MOVE_DELAY
1291 | INSN_WRITE_COND_CODE
))
1293 && (prev_insn
.insn_mo
->pinfo
1297 && (prev_insn
.insn_mo
->pinfo
1298 & (INSN_LOAD_MEMORY_DELAY
1299 | INSN_COPROC_MEMORY_DELAY
))))
1302 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1304 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1305 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1308 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1310 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1311 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1316 if (insn_label
!= NULL
)
1318 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1319 insn_label
->sy_frag
= frag_now
;
1320 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1325 mips_no_prev_insn ();
1328 /* Build an instruction created by a macro expansion. This is passed
1329 a pointer to the count of instructions created so far, an
1330 expression, the name of the instruction to build, an operand format
1331 string, and corresponding arguments. */
1335 macro_build (char *place
,
1341 #else /* ! defined (NO_STDARG) */
1343 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1350 #endif /* ! defined (NO_STDARG) */
1352 struct mips_cl_insn insn
;
1353 bfd_reloc_code_real_type r
;
1357 va_start (args
, fmt
);
1363 * If the macro is about to expand into a second instruction,
1364 * print a warning if needed. We need to pass ip as a parameter
1365 * to generate a better warning message here...
1367 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1368 as_warn ("Macro instruction expanded into multiple instructions");
1371 *counter
+= 1; /* bump instruction counter */
1373 r
= BFD_RELOC_UNUSED
;
1374 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1375 assert (insn
.insn_mo
);
1376 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1378 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1379 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1382 assert (insn
.insn_mo
->name
);
1383 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1385 insn
.insn_opcode
= insn
.insn_mo
->match
;
1401 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1407 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1412 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1417 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1424 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1428 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1432 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1439 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1445 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1446 assert (r
== BFD_RELOC_MIPS_GPREL
1447 || r
== BFD_RELOC_MIPS_LITERAL
1448 || r
== BFD_RELOC_LO16
1449 || r
== BFD_RELOC_MIPS_GOT16
1450 || r
== BFD_RELOC_MIPS_CALL16
1451 || (ep
->X_op
== O_subtract
1452 && now_seg
== text_section
1453 && r
== BFD_RELOC_PCREL_LO16
));
1457 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1459 && (ep
->X_op
== O_constant
1460 || (ep
->X_op
== O_symbol
1461 && (r
== BFD_RELOC_HI16_S
1462 || r
== BFD_RELOC_HI16
))
1463 || (ep
->X_op
== O_subtract
1464 && now_seg
== text_section
1465 && r
== BFD_RELOC_PCREL_HI16_S
)));
1466 if (ep
->X_op
== O_constant
)
1468 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1470 r
= BFD_RELOC_UNUSED
;
1475 assert (ep
!= NULL
);
1477 * This allows macro() to pass an immediate expression for
1478 * creating short branches without creating a symbol.
1479 * Note that the expression still might come from the assembly
1480 * input, in which case the value is not checked for range nor
1481 * is a relocation entry generated (yuck).
1483 if (ep
->X_op
== O_constant
)
1485 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1489 r
= BFD_RELOC_16_PCREL_S2
;
1493 assert (ep
!= NULL
);
1494 r
= BFD_RELOC_MIPS_JMP
;
1503 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1505 append_insn (place
, &insn
, ep
, r
);
1509 * Generate a "lui" instruction.
1512 macro_build_lui (place
, counter
, ep
, regnum
)
1518 expressionS high_expr
;
1519 struct mips_cl_insn insn
;
1520 bfd_reloc_code_real_type r
;
1521 CONST
char *name
= "lui";
1522 CONST
char *fmt
= "t,u";
1528 high_expr
.X_op
= O_constant
;
1529 high_expr
.X_add_number
= 0;
1532 if (high_expr
.X_op
== O_constant
)
1534 /* we can compute the instruction now without a relocation entry */
1535 if (high_expr
.X_add_number
& 0x8000)
1536 high_expr
.X_add_number
+= 0x10000;
1537 high_expr
.X_add_number
=
1538 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1539 r
= BFD_RELOC_UNUSED
;
1543 assert (ep
->X_op
== O_symbol
);
1544 /* _gp_disp is a special case, used from s_cpload. */
1545 assert (mips_pic
== NO_PIC
1546 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1547 r
= BFD_RELOC_HI16_S
;
1551 * If the macro is about to expand into a second instruction,
1552 * print a warning if needed. We need to pass ip as a parameter
1553 * to generate a better warning message here...
1555 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1556 as_warn ("Macro instruction expanded into multiple instructions");
1559 *counter
+= 1; /* bump instruction counter */
1561 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1562 assert (insn
.insn_mo
);
1563 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1564 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1566 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1567 if (r
== BFD_RELOC_UNUSED
)
1569 insn
.insn_opcode
|= high_expr
.X_add_number
;
1570 append_insn (place
, &insn
, NULL
, r
);
1573 append_insn (place
, &insn
, &high_expr
, r
);
1577 * Generates code to set the $at register to true (one)
1578 * if reg is less than the immediate expression.
1581 set_at (counter
, reg
, unsignedp
)
1586 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1587 macro_build ((char *) NULL
, counter
, &imm_expr
,
1588 unsignedp
? "sltiu" : "slti",
1589 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1592 load_register (counter
, AT
, &imm_expr
);
1593 macro_build ((char *) NULL
, counter
, NULL
,
1594 unsignedp
? "sltu" : "slt",
1595 "d,v,t", AT
, reg
, AT
);
1599 /* Warn if an expression is not a constant. */
1602 check_absolute_expr (ip
, ex
)
1603 struct mips_cl_insn
*ip
;
1606 if (ex
->X_op
!= O_constant
)
1607 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1611 * This routine generates the least number of instructions neccessary to load
1612 * an absolute expression value into a register.
1615 load_register (counter
, reg
, ep
)
1621 expressionS hi32
, lo32
;
1623 if (ep
->X_op
!= O_big
)
1625 assert (ep
->X_op
== O_constant
);
1626 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1628 /* We can handle 16 bit signed values with an addiu to
1629 $zero. No need to ever use daddiu here, since $zero and
1630 the result are always correct in 32 bit mode. */
1631 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1632 (int) BFD_RELOC_LO16
);
1635 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1637 /* We can handle 16 bit unsigned values with an ori to
1639 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1640 (int) BFD_RELOC_LO16
);
1643 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1644 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1645 == ~ (offsetT
) 0x7fffffff))
1647 /* 32 bit values require an lui. */
1648 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1649 (int) BFD_RELOC_HI16
);
1650 if ((ep
->X_add_number
& 0xffff) != 0)
1651 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1652 (int) BFD_RELOC_LO16
);
1657 /* The value is larger than 32 bits. */
1661 as_bad ("Number larger than 32 bits");
1662 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1663 (int) BFD_RELOC_LO16
);
1667 if (ep
->X_op
!= O_big
)
1671 hi32
.X_add_number
>>= shift
;
1672 hi32
.X_add_number
&= 0xffffffff;
1673 if ((hi32
.X_add_number
& 0x80000000) != 0)
1674 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1676 lo32
.X_add_number
&= 0xffffffff;
1680 assert (ep
->X_add_number
> 2);
1681 if (ep
->X_add_number
== 3)
1682 generic_bignum
[3] = 0;
1683 else if (ep
->X_add_number
> 4)
1684 as_bad ("Number larger than 64 bits");
1685 lo32
.X_op
= O_constant
;
1686 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1687 hi32
.X_op
= O_constant
;
1688 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1691 load_register (counter
, reg
, &hi32
);
1692 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1693 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1699 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1702 mid16
.X_add_number
>>= 16;
1703 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1704 reg
, (int) BFD_RELOC_LO16
);
1705 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1708 if ((lo32
.X_add_number
& 0xffff) != 0)
1709 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1710 (int) BFD_RELOC_LO16
);
1713 /* Load an address into a register. */
1716 load_address (counter
, reg
, ep
)
1723 if (ep
->X_op
!= O_constant
1724 && ep
->X_op
!= O_symbol
)
1726 as_bad ("expression too complex");
1727 ep
->X_op
= O_constant
;
1730 if (ep
->X_op
== O_constant
)
1732 load_register (counter
, reg
, ep
);
1736 if (mips_pic
== NO_PIC
)
1738 /* If this is a reference to a GP relative symbol, we want
1739 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1741 lui $reg,<sym> (BFD_RELOC_HI16_S)
1742 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1743 If we have an addend, we always use the latter form. */
1744 if (ep
->X_add_number
!= 0)
1749 macro_build ((char *) NULL
, counter
, ep
,
1750 mips_isa
< 3 ? "addiu" : "daddiu",
1751 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1752 p
= frag_var (rs_machine_dependent
, 8, 0,
1753 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
1754 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1756 macro_build_lui (p
, counter
, ep
, reg
);
1759 macro_build (p
, counter
, ep
,
1760 mips_isa
< 3 ? "addiu" : "daddiu",
1761 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1763 else if (mips_pic
== SVR4_PIC
)
1767 /* If this is a reference to an external symbol, we want
1768 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1770 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1772 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1773 If there is a constant, it must be added in after. */
1774 ex
.X_add_number
= ep
->X_add_number
;
1775 ep
->X_add_number
= 0;
1777 macro_build ((char *) NULL
, counter
, ep
,
1778 mips_isa
< 3 ? "lw" : "ld",
1779 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1780 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1781 p
= frag_var (rs_machine_dependent
, 4, 0,
1782 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1783 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1784 macro_build (p
, counter
, ep
,
1785 mips_isa
< 3 ? "addiu" : "daddiu",
1786 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1787 if (ex
.X_add_number
!= 0)
1789 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1790 as_bad ("PIC code offset overflow (max 16 signed bits)");
1791 ex
.X_op
= O_constant
;
1792 macro_build (p
, counter
, &ex
,
1793 mips_isa
< 3 ? "addiu" : "daddiu",
1794 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1797 else if (mips_pic
== EMBEDDED_PIC
)
1800 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1802 macro_build ((char *) NULL
, counter
, ep
,
1803 mips_isa
< 3 ? "addiu" : "daddiu",
1804 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1812 * This routine implements the seemingly endless macro or synthesized
1813 * instructions and addressing modes in the mips assembly language. Many
1814 * of these macros are simple and are similar to each other. These could
1815 * probably be handled by some kind of table or grammer aproach instead of
1816 * this verbose method. Others are not simple macros but are more like
1817 * optimizing code generation.
1818 * One interesting optimization is when several store macros appear
1819 * consecutivly that would load AT with the upper half of the same address.
1820 * The ensuing load upper instructions are ommited. This implies some kind
1821 * of global optimization. We currently only optimize within a single macro.
1822 * For many of the load and store macros if the address is specified as a
1823 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1824 * first load register 'at' with zero and use it as the base register. The
1825 * mips assembler simply uses register $zero. Just one tiny optimization
1830 struct mips_cl_insn
*ip
;
1832 register int treg
, sreg
, dreg
, breg
;
1847 bfd_reloc_code_real_type r
;
1849 int hold_mips_optimize
;
1851 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1852 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1853 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1854 mask
= ip
->insn_mo
->mask
;
1856 expr1
.X_op
= O_constant
;
1857 expr1
.X_op_symbol
= NULL
;
1858 expr1
.X_add_symbol
= NULL
;
1859 expr1
.X_add_number
= 1;
1871 mips_emit_delays ();
1873 mips_any_noreorder
= 1;
1875 expr1
.X_add_number
= 8;
1876 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1878 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1880 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1881 macro_build ((char *) NULL
, &icnt
, NULL
,
1882 dbl
? "dsub" : "sub",
1883 "d,v,t", dreg
, 0, sreg
);
1906 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1908 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1909 (int) BFD_RELOC_LO16
);
1912 load_register (&icnt
, AT
, &imm_expr
);
1913 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1932 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1934 if (mask
!= M_NOR_I
)
1935 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1936 sreg
, (int) BFD_RELOC_LO16
);
1939 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1940 treg
, sreg
, (int) BFD_RELOC_LO16
);
1941 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1947 load_register (&icnt
, AT
, &imm_expr
);
1948 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1965 if (imm_expr
.X_add_number
== 0)
1967 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1971 load_register (&icnt
, AT
, &imm_expr
);
1972 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1980 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1981 likely
? "bgezl" : "bgez",
1987 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1988 likely
? "blezl" : "blez",
1992 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1993 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1994 likely
? "beql" : "beq",
2001 /* check for > max integer */
2002 maxnum
= 0x7fffffff;
2010 if (imm_expr
.X_add_number
>= maxnum
2011 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2014 /* result is always false */
2017 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2018 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2022 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2023 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2028 imm_expr
.X_add_number
++;
2032 if (mask
== M_BGEL_I
)
2034 if (imm_expr
.X_add_number
== 0)
2036 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2037 likely
? "bgezl" : "bgez",
2041 if (imm_expr
.X_add_number
== 1)
2043 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2044 likely
? "bgtzl" : "bgtz",
2048 maxnum
= 0x7fffffff;
2056 maxnum
= - maxnum
- 1;
2057 if (imm_expr
.X_add_number
<= maxnum
2058 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2061 /* result is always true */
2062 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2063 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2066 set_at (&icnt
, sreg
, 0);
2067 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2068 likely
? "beql" : "beq",
2079 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2080 likely
? "beql" : "beq",
2084 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2086 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2087 likely
? "beql" : "beq",
2094 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2096 imm_expr
.X_add_number
++;
2100 if (mask
== M_BGEUL_I
)
2102 if (imm_expr
.X_add_number
== 0)
2104 if (imm_expr
.X_add_number
== 1)
2106 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2107 likely
? "bnel" : "bne",
2111 set_at (&icnt
, sreg
, 1);
2112 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2113 likely
? "beql" : "beq",
2122 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2123 likely
? "bgtzl" : "bgtz",
2129 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2130 likely
? "bltzl" : "bltz",
2134 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2135 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2136 likely
? "bnel" : "bne",
2145 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2146 likely
? "bnel" : "bne",
2152 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2154 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2155 likely
? "bnel" : "bne",
2164 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2165 likely
? "blezl" : "blez",
2171 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2172 likely
? "bgezl" : "bgez",
2176 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2177 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2178 likely
? "beql" : "beq",
2185 maxnum
= 0x7fffffff;
2193 if (imm_expr
.X_add_number
>= maxnum
2194 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2196 imm_expr
.X_add_number
++;
2200 if (mask
== M_BLTL_I
)
2202 if (imm_expr
.X_add_number
== 0)
2204 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2205 likely
? "bltzl" : "bltz",
2209 if (imm_expr
.X_add_number
== 1)
2211 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2212 likely
? "blezl" : "blez",
2216 set_at (&icnt
, sreg
, 0);
2217 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2218 likely
? "bnel" : "bne",
2227 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2228 likely
? "beql" : "beq",
2234 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2236 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2237 likely
? "beql" : "beq",
2244 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2246 imm_expr
.X_add_number
++;
2250 if (mask
== M_BLTUL_I
)
2252 if (imm_expr
.X_add_number
== 0)
2254 if (imm_expr
.X_add_number
== 1)
2256 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2257 likely
? "beql" : "beq",
2261 set_at (&icnt
, sreg
, 1);
2262 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2263 likely
? "bnel" : "bne",
2272 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2273 likely
? "bltzl" : "bltz",
2279 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2280 likely
? "bgtzl" : "bgtz",
2284 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2285 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2286 likely
? "bnel" : "bne",
2297 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2298 likely
? "bnel" : "bne",
2302 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2304 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2305 likely
? "bnel" : "bne",
2321 as_warn ("Divide by zero.");
2323 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2325 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2329 mips_emit_delays ();
2331 mips_any_noreorder
= 1;
2332 macro_build ((char *) NULL
, &icnt
, NULL
,
2333 dbl
? "ddiv" : "div",
2334 "z,s,t", sreg
, treg
);
2336 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2339 expr1
.X_add_number
= 8;
2340 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2341 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2342 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2344 expr1
.X_add_number
= -1;
2345 macro_build ((char *) NULL
, &icnt
, &expr1
,
2346 dbl
? "daddiu" : "addiu",
2347 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2348 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2349 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2352 expr1
.X_add_number
= 1;
2353 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2354 (int) BFD_RELOC_LO16
);
2355 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2360 expr1
.X_add_number
= 0x80000000;
2361 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2362 (int) BFD_RELOC_HI16
);
2365 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2368 expr1
.X_add_number
= 8;
2369 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2370 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2371 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2374 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2413 if (imm_expr
.X_add_number
== 0)
2415 as_warn ("Divide by zero.");
2417 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2419 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2422 if (imm_expr
.X_add_number
== 1)
2424 if (strcmp (s2
, "mflo") == 0)
2425 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2428 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2431 if (imm_expr
.X_add_number
== -1
2432 && s
[strlen (s
) - 1] != 'u')
2434 if (strcmp (s2
, "mflo") == 0)
2437 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2440 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2444 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2448 load_register (&icnt
, AT
, &imm_expr
);
2449 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2450 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2469 mips_emit_delays ();
2471 mips_any_noreorder
= 1;
2472 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2474 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2477 expr1
.X_add_number
= 8;
2478 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2479 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2480 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2483 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2487 /* Load the address of a symbol into a register. If breg is not
2488 zero, we then add a base register to it. */
2490 /* When generating embedded PIC code, we permit expressions of
2493 where bar is an address in the .text section. These are used
2494 when getting the addresses of functions. We don't permit
2495 X_add_number to be non-zero, because if the symbol is
2496 external the relaxing code needs to know that any addend is
2497 purely the offset to X_op_symbol. */
2498 if (mips_pic
== EMBEDDED_PIC
2499 && offset_expr
.X_op
== O_subtract
2500 && now_seg
== text_section
2501 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2502 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2503 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2504 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2505 ->sy_value
.X_add_symbol
)
2508 && offset_expr
.X_add_number
== 0)
2510 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2511 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2512 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2513 mips_isa
< 3 ? "addiu" : "daddiu",
2514 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2518 if (offset_expr
.X_op
!= O_symbol
2519 && offset_expr
.X_op
!= O_constant
)
2521 as_bad ("expression too complex");
2522 offset_expr
.X_op
= O_constant
;
2536 if (offset_expr
.X_op
== O_constant
)
2537 load_register (&icnt
, tempreg
, &offset_expr
);
2538 else if (mips_pic
== NO_PIC
)
2540 /* If this is a reference to an GP relative symbol, we want
2541 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2543 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2544 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2545 If we have a constant, we need two instructions anyhow,
2546 so we may as well always use the latter form. */
2547 if (offset_expr
.X_add_number
!= 0)
2552 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2553 mips_isa
< 3 ? "addiu" : "daddiu",
2554 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2555 p
= frag_var (rs_machine_dependent
, 8, 0,
2556 RELAX_ENCODE (4, 8, 0, 4, 0,
2557 mips_warn_about_macros
),
2558 offset_expr
.X_add_symbol
, (long) 0,
2561 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2564 macro_build (p
, &icnt
, &offset_expr
,
2565 mips_isa
< 3 ? "addiu" : "daddiu",
2566 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2568 else if (mips_pic
== SVR4_PIC
)
2570 /* If this is a reference to an external symbol, and there
2571 is no constant, we want
2572 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2573 For a local symbol, we want
2574 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2576 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2578 If we have a small constant, and this is a reference to
2579 an external symbol, we want
2580 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2582 addiu $tempreg,$tempreg,<constant>
2583 For a local symbol, we want the same instruction
2584 sequence, but we output a BFD_RELOC_LO16 reloc on the
2587 If we have a large constant, and this is a reference to
2588 an external symbol, we want
2589 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2590 lui $at,<hiconstant>
2591 addiu $at,$at,<loconstant>
2592 addu $tempreg,$tempreg,$at
2593 For a local symbol, we want the same instruction
2594 sequence, but we output a BFD_RELOC_LO16 reloc on the
2595 addiu instruction. */
2596 expr1
.X_add_number
= offset_expr
.X_add_number
;
2597 offset_expr
.X_add_number
= 0;
2599 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2600 mips_isa
< 3 ? "lw" : "ld",
2601 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2602 if (expr1
.X_add_number
== 0)
2610 /* We're going to put in an addu instruction using
2611 tempreg, so we may as well insert the nop right
2613 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2617 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2618 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2620 ? mips_warn_about_macros
2622 offset_expr
.X_add_symbol
, (long) 0,
2626 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2629 macro_build (p
, &icnt
, &expr1
,
2630 mips_isa
< 3 ? "addiu" : "daddiu",
2631 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2632 /* FIXME: If breg == 0, and the next instruction uses
2633 $tempreg, then if this variant case is used an extra
2634 nop will be generated. */
2636 else if (expr1
.X_add_number
>= -0x8000
2637 && expr1
.X_add_number
< 0x8000)
2639 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2641 macro_build ((char *) NULL
, &icnt
, &expr1
,
2642 mips_isa
< 3 ? "addiu" : "daddiu",
2643 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2644 (void) frag_var (rs_machine_dependent
, 0, 0,
2645 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2646 offset_expr
.X_add_symbol
, (long) 0,
2653 /* If we are going to add in a base register, and the
2654 target register and the base register are the same,
2655 then we are using AT as a temporary register. Since
2656 we want to load the constant into AT, we add our
2657 current AT (from the global offset table) and the
2658 register into the register now, and pretend we were
2659 not using a base register. */
2664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2666 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2667 mips_isa
< 3 ? "addu" : "daddu",
2668 "d,v,t", treg
, AT
, breg
);
2674 /* Set mips_optimize around the lui instruction to avoid
2675 inserting an unnecessary nop after the lw. */
2676 hold_mips_optimize
= mips_optimize
;
2678 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2679 mips_optimize
= hold_mips_optimize
;
2681 macro_build ((char *) NULL
, &icnt
, &expr1
,
2682 mips_isa
< 3 ? "addiu" : "daddiu",
2683 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2684 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2685 mips_isa
< 3 ? "addu" : "daddu",
2686 "d,v,t", tempreg
, tempreg
, AT
);
2687 (void) frag_var (rs_machine_dependent
, 0, 0,
2688 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2689 offset_expr
.X_add_symbol
, (long) 0,
2694 else if (mips_pic
== EMBEDDED_PIC
)
2697 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2699 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2700 mips_isa
< 3 ? "addiu" : "daddiu",
2701 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2708 mips_isa
< 3 ? "addu" : "daddu",
2709 "d,v,t", treg
, tempreg
, breg
);
2717 /* The j instruction may not be used in PIC code, since it
2718 requires an absolute address. We convert it to a b
2720 if (mips_pic
== NO_PIC
)
2721 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2723 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2726 /* The jal instructions must be handled as macros because when
2727 generating PIC code they expand to multi-instruction
2728 sequences. Normally they are simple instructions. */
2733 if (mips_pic
== NO_PIC
2734 || mips_pic
== EMBEDDED_PIC
)
2735 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2737 else if (mips_pic
== SVR4_PIC
)
2739 if (sreg
!= PIC_CALL_REG
)
2740 as_warn ("MIPS PIC call to register other than $25");
2742 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2744 if (mips_cprestore_offset
< 0)
2745 as_warn ("No .cprestore pseudo-op used in PIC code");
2748 expr1
.X_add_number
= mips_cprestore_offset
;
2749 macro_build ((char *) NULL
, &icnt
, &expr1
,
2750 mips_isa
< 3 ? "lw" : "ld",
2751 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2760 if (mips_pic
== NO_PIC
)
2761 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2762 else if (mips_pic
== SVR4_PIC
)
2764 /* If this is a reference to an external symbol, we want
2765 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2769 lw $gp,cprestore($sp)
2770 The cprestore value is set using the .cprestore
2771 pseudo-op. If the symbol is not external, we want
2772 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2774 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2777 lw $gp,cprestore($sp)
2780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2781 mips_isa
< 3 ? "lw" : "ld",
2782 "t,o(b)", PIC_CALL_REG
,
2783 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2785 p
= frag_var (rs_machine_dependent
, 4, 0,
2786 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2787 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2788 macro_build (p
, &icnt
, &offset_expr
,
2789 mips_isa
< 3 ? "addiu" : "daddiu",
2790 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2791 (int) BFD_RELOC_LO16
);
2792 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2793 "jalr", "s", PIC_CALL_REG
);
2794 if (mips_cprestore_offset
< 0)
2795 as_warn ("No .cprestore pseudo-op used in PIC code");
2799 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2801 expr1
.X_add_number
= mips_cprestore_offset
;
2802 macro_build ((char *) NULL
, &icnt
, &expr1
,
2803 mips_isa
< 3 ? "lw" : "ld",
2804 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2808 else if (mips_pic
== EMBEDDED_PIC
)
2810 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2811 /* The linker may expand the call to a longer sequence which
2812 uses $at, so we must break rather than return. */
2888 if (breg
== treg
|| coproc
|| lr
)
2957 if (mask
== M_LWC1_AB
2958 || mask
== M_SWC1_AB
2959 || mask
== M_LDC1_AB
2960 || mask
== M_SDC1_AB
2969 if (offset_expr
.X_op
!= O_constant
2970 && offset_expr
.X_op
!= O_symbol
)
2972 as_bad ("expression too complex");
2973 offset_expr
.X_op
= O_constant
;
2976 /* A constant expression in PIC code can be handled just as it
2977 is in non PIC code. */
2978 if (mips_pic
== NO_PIC
2979 || offset_expr
.X_op
== O_constant
)
2981 /* If this is a reference to a GP relative symbol, and there
2982 is no base register, we want
2983 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2984 Otherwise, if there is no base register, we want
2985 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2986 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2987 If we have a constant, we need two instructions anyhow,
2988 so we always use the latter form.
2990 If we have a base register, and this is a reference to a
2991 GP relative symbol, we want
2992 addu $tempreg,$breg,$gp
2993 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2995 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2996 addu $tempreg,$tempreg,$breg
2997 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2998 With a constant we always use the latter case. */
3001 if (offset_expr
.X_add_number
!= 0)
3006 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3007 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3008 p
= frag_var (rs_machine_dependent
, 8, 0,
3009 RELAX_ENCODE (4, 8, 0, 4, 0,
3010 (mips_warn_about_macros
3011 || (used_at
&& mips_noat
))),
3012 offset_expr
.X_add_symbol
, (long) 0,
3016 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3019 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3020 (int) BFD_RELOC_LO16
, tempreg
);
3024 if (offset_expr
.X_add_number
!= 0)
3029 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3030 mips_isa
< 3 ? "addu" : "daddu",
3031 "d,v,t", tempreg
, breg
, GP
);
3032 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3033 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3034 p
= frag_var (rs_machine_dependent
, 12, 0,
3035 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3036 offset_expr
.X_add_symbol
, (long) 0,
3039 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3042 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3043 mips_isa
< 3 ? "addu" : "daddu",
3044 "d,v,t", tempreg
, tempreg
, breg
);
3047 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3048 (int) BFD_RELOC_LO16
, tempreg
);
3051 else if (mips_pic
== SVR4_PIC
)
3053 /* If this is a reference to an external symbol, we want
3054 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3056 <op> $treg,0($tempreg)
3058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3060 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3061 <op> $treg,0($tempreg)
3062 If there is a base register, we add it to $tempreg before
3063 the <op>. If there is a constant, we stick it in the
3064 <op> instruction. We don't handle constants larger than
3065 16 bits, because we have no way to load the upper 16 bits
3066 (actually, we could handle them for the subset of cases
3067 in which we are not using $at). */
3068 assert (offset_expr
.X_op
== O_symbol
);
3069 expr1
.X_add_number
= offset_expr
.X_add_number
;
3070 offset_expr
.X_add_number
= 0;
3071 if (expr1
.X_add_number
< -0x8000
3072 || expr1
.X_add_number
>= 0x8000)
3073 as_bad ("PIC code offset overflow (max 16 signed bits)");
3075 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3076 mips_isa
< 3 ? "lw" : "ld",
3077 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3079 p
= frag_var (rs_machine_dependent
, 4, 0,
3080 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3081 offset_expr
.X_add_symbol
, (long) 0,
3083 macro_build (p
, &icnt
, &offset_expr
,
3084 mips_isa
< 3 ? "addiu" : "daddiu",
3085 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3087 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3088 mips_isa
< 3 ? "addu" : "daddu",
3089 "d,v,t", tempreg
, tempreg
, breg
);
3090 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3091 (int) BFD_RELOC_LO16
, tempreg
);
3093 else if (mips_pic
== EMBEDDED_PIC
)
3095 /* If there is no base register, we want
3096 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3097 If there is a base register, we want
3098 addu $tempreg,$breg,$gp
3099 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3101 assert (offset_expr
.X_op
== O_symbol
);
3104 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3105 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3110 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3111 mips_isa
< 3 ? "addu" : "daddu",
3112 "d,v,t", tempreg
, breg
, GP
);
3113 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3114 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3127 load_register (&icnt
, treg
, &imm_expr
);
3131 if (imm_expr
.X_op
== O_constant
)
3133 load_register (&icnt
, AT
, &imm_expr
);
3134 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3135 "mtc1", "t,G", AT
, treg
);
3140 assert (offset_expr
.X_op
== O_symbol
3141 && strcmp (segment_name (S_GET_SEGMENT
3142 (offset_expr
.X_add_symbol
)),
3144 && offset_expr
.X_add_number
== 0);
3145 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3146 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3151 /* We know that sym is in the .rdata section. First we get the
3152 upper 16 bits of the address. */
3153 if (mips_pic
== NO_PIC
)
3155 /* FIXME: This won't work for a 64 bit address. */
3156 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3158 else if (mips_pic
== SVR4_PIC
)
3160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3161 mips_isa
< 3 ? "lw" : "ld",
3162 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3164 else if (mips_pic
== EMBEDDED_PIC
)
3166 /* For embedded PIC we pick up the entire address off $gp in
3167 a single instruction. */
3168 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3169 mips_isa
< 3 ? "addiu" : "daddiu",
3170 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3171 offset_expr
.X_op
= O_constant
;
3172 offset_expr
.X_add_number
= 0;
3177 /* Now we load the register(s). */
3179 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3180 treg
, (int) BFD_RELOC_LO16
, AT
);
3183 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3184 treg
, (int) BFD_RELOC_LO16
, AT
);
3187 /* FIXME: How in the world do we deal with the possible
3189 offset_expr
.X_add_number
+= 4;
3190 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3191 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3195 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3196 does not become a variant frag. */
3197 frag_wane (frag_now
);
3203 assert (offset_expr
.X_op
== O_symbol
3204 && offset_expr
.X_add_number
== 0);
3205 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3206 if (strcmp (s
, ".lit8") == 0)
3210 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3211 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3215 r
= BFD_RELOC_MIPS_LITERAL
;
3220 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3221 if (mips_pic
== SVR4_PIC
)
3222 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3223 mips_isa
< 3 ? "lw" : "ld",
3224 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3227 /* FIXME: This won't work for a 64 bit address. */
3228 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3233 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3234 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3236 /* To avoid confusion in tc_gen_reloc, we must ensure
3237 that this does not become a variant frag. */
3238 frag_wane (frag_now
);
3249 /* Even on a big endian machine $fn comes before $fn+1. We have
3250 to adjust when loading from memory. */
3253 assert (mips_isa
< 2);
3254 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3255 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3257 /* FIXME: A possible overflow which I don't know how to deal
3259 offset_expr
.X_add_number
+= 4;
3260 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3261 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3264 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3265 does not become a variant frag. */
3266 frag_wane (frag_now
);
3275 * The MIPS assembler seems to check for X_add_number not
3276 * being double aligned and generating:
3279 * addiu at,at,%lo(foo+1)
3282 * But, the resulting address is the same after relocation so why
3283 * generate the extra instruction?
3330 if (offset_expr
.X_op
!= O_symbol
3331 && offset_expr
.X_op
!= O_constant
)
3333 as_bad ("expression too complex");
3334 offset_expr
.X_op
= O_constant
;
3337 /* Even on a big endian machine $fn comes before $fn+1. We have
3338 to adjust when loading from memory. We set coproc if we must
3339 load $fn+1 first. */
3340 if (byte_order
== LITTLE_ENDIAN
)
3343 if (mips_pic
== NO_PIC
3344 || offset_expr
.X_op
== O_constant
)
3346 /* If this is a reference to a GP relative symbol, we want
3347 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3348 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3349 If we have a base register, we use this
3351 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3352 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3353 If this is not a GP relative symbol, we want
3354 lui $at,<sym> (BFD_RELOC_HI16_S)
3355 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3356 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3357 If there is a base register, we add it to $at after the
3358 lui instruction. If there is a constant, we always use
3360 if (offset_expr
.X_add_number
!= 0)
3379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3380 mips_isa
< 3 ? "addu" : "daddu",
3381 "d,v,t", AT
, breg
, GP
);
3387 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3388 coproc
? treg
+ 1 : treg
,
3389 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3390 offset_expr
.X_add_number
+= 4;
3392 /* Set mips_optimize to 2 to avoid inserting an
3394 hold_mips_optimize
= mips_optimize
;
3396 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3397 coproc
? treg
: treg
+ 1,
3398 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3399 mips_optimize
= hold_mips_optimize
;
3401 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3402 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3403 used_at
&& mips_noat
),
3404 offset_expr
.X_add_symbol
, (long) 0,
3407 /* We just generated two relocs. When tc_gen_reloc
3408 handles this case, it will skip the first reloc and
3409 handle the second. The second reloc already has an
3410 extra addend of 4, which we added above. We must
3411 subtract it out, and then subtract another 4 to make
3412 the first reloc come out right. The second reloc
3413 will come out right because we are going to add 4 to
3414 offset_expr when we build its instruction below. */
3415 offset_expr
.X_add_number
-= 8;
3416 offset_expr
.X_op
= O_constant
;
3418 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3423 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3424 mips_isa
< 3 ? "addu" : "daddu",
3425 "d,v,t", AT
, breg
, AT
);
3429 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3430 coproc
? treg
+ 1 : treg
,
3431 (int) BFD_RELOC_LO16
, AT
);
3434 /* FIXME: How do we handle overflow here? */
3435 offset_expr
.X_add_number
+= 4;
3436 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3437 coproc
? treg
: treg
+ 1,
3438 (int) BFD_RELOC_LO16
, AT
);
3440 else if (mips_pic
== SVR4_PIC
)
3444 /* If this is a reference to an external symbol, we want
3445 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3450 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3452 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3453 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3454 If there is a base register we add it to $at before the
3455 lwc1 instructions. If there is a constant we include it
3456 in the lwc1 instructions. */
3458 expr1
.X_add_number
= offset_expr
.X_add_number
;
3459 offset_expr
.X_add_number
= 0;
3460 if (expr1
.X_add_number
< -0x8000
3461 || expr1
.X_add_number
>= 0x8000 - 4)
3462 as_bad ("PIC code offset overflow (max 16 signed bits)");
3467 frag_grow (24 + off
);
3468 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3469 mips_isa
< 3 ? "lw" : "ld",
3470 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3471 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3473 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3474 mips_isa
< 3 ? "addu" : "daddu",
3475 "d,v,t", AT
, breg
, AT
);
3476 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3477 coproc
? treg
+ 1 : treg
,
3478 (int) BFD_RELOC_LO16
, AT
);
3479 expr1
.X_add_number
+= 4;
3481 /* Set mips_optimize to 2 to avoid inserting an undesired
3483 hold_mips_optimize
= mips_optimize
;
3485 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3486 coproc
? treg
: treg
+ 1,
3487 (int) BFD_RELOC_LO16
, AT
);
3488 mips_optimize
= hold_mips_optimize
;
3490 (void) frag_var (rs_machine_dependent
, 0, 0,
3491 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3492 offset_expr
.X_add_symbol
, (long) 0,
3495 else if (mips_pic
== EMBEDDED_PIC
)
3497 /* If there is no base register, we use
3498 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3499 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3500 If we have a base register, we use
3502 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3503 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3512 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3513 mips_isa
< 3 ? "addu" : "daddu",
3514 "d,v,t", AT
, breg
, GP
);
3519 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3520 coproc
? treg
+ 1 : treg
,
3521 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3522 offset_expr
.X_add_number
+= 4;
3523 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3524 coproc
? treg
: treg
+ 1,
3525 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3541 assert (mips_isa
< 3);
3542 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3543 (int) BFD_RELOC_LO16
, breg
);
3544 offset_expr
.X_add_number
+= 4;
3545 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3546 (int) BFD_RELOC_LO16
, breg
);
3548 #ifdef LOSING_COMPILER
3554 as_warn ("Macro used $at after \".set noat\"");
3559 struct mips_cl_insn
*ip
;
3561 register int treg
, sreg
, dreg
, breg
;
3576 bfd_reloc_code_real_type r
;
3579 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3580 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3581 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3582 mask
= ip
->insn_mo
->mask
;
3584 expr1
.X_op
= O_constant
;
3585 expr1
.X_op_symbol
= NULL
;
3586 expr1
.X_add_symbol
= NULL
;
3587 expr1
.X_add_number
= 1;
3591 #endif /* LOSING_COMPILER */
3596 macro_build ((char *) NULL
, &icnt
, NULL
,
3597 dbl
? "dmultu" : "multu",
3599 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3605 /* The MIPS assembler some times generates shifts and adds. I'm
3606 not trying to be that fancy. GCC should do this for us
3608 load_register (&icnt
, AT
, &imm_expr
);
3609 macro_build ((char *) NULL
, &icnt
, NULL
,
3610 dbl
? "dmult" : "mult",
3612 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3618 mips_emit_delays ();
3620 mips_any_noreorder
= 1;
3621 macro_build ((char *) NULL
, &icnt
, NULL
,
3622 dbl
? "dmult" : "mult",
3624 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3625 macro_build ((char *) NULL
, &icnt
, NULL
,
3626 dbl
? "dsra32" : "sra",
3627 "d,w,<", dreg
, dreg
, 31);
3628 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3630 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3633 expr1
.X_add_number
= 8;
3634 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3635 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3636 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3639 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3645 mips_emit_delays ();
3647 mips_any_noreorder
= 1;
3648 macro_build ((char *) NULL
, &icnt
, NULL
,
3649 dbl
? "dmultu" : "multu",
3651 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3652 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3654 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3657 expr1
.X_add_number
= 8;
3658 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3659 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3660 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3666 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3667 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3668 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3670 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3674 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3675 imm_expr
.X_add_number
& 0x1f);
3676 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3677 (0 - imm_expr
.X_add_number
) & 0x1f);
3678 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3682 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3683 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3684 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3686 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3690 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3691 imm_expr
.X_add_number
& 0x1f);
3692 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3693 (0 - imm_expr
.X_add_number
) & 0x1f);
3694 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3698 assert (mips_isa
< 2);
3699 /* Even on a big endian machine $fn comes before $fn+1. We have
3700 to adjust when storing to memory. */
3701 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3702 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3703 (int) BFD_RELOC_LO16
, breg
);
3704 offset_expr
.X_add_number
+= 4;
3705 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3706 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3707 (int) BFD_RELOC_LO16
, breg
);
3712 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3713 treg
, (int) BFD_RELOC_LO16
);
3715 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3716 sreg
, (int) BFD_RELOC_LO16
);
3719 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3721 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3722 dreg
, (int) BFD_RELOC_LO16
);
3727 if (imm_expr
.X_add_number
== 0)
3729 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3730 sreg
, (int) BFD_RELOC_LO16
);
3735 as_warn ("Instruction %s: result is always false",
3737 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3740 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3742 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3743 sreg
, (int) BFD_RELOC_LO16
);
3746 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3748 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3749 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3750 mips_isa
< 3 ? "addiu" : "daddiu",
3751 "t,r,j", dreg
, sreg
,
3752 (int) BFD_RELOC_LO16
);
3757 load_register (&icnt
, AT
, &imm_expr
);
3758 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3762 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3763 (int) BFD_RELOC_LO16
);
3768 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3774 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3775 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3776 (int) BFD_RELOC_LO16
);
3779 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3781 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3783 macro_build ((char *) NULL
, &icnt
, &expr1
,
3784 mask
== M_SGE_I
? "slti" : "sltiu",
3785 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3790 load_register (&icnt
, AT
, &imm_expr
);
3791 macro_build ((char *) NULL
, &icnt
, NULL
,
3792 mask
== M_SGE_I
? "slt" : "sltu",
3793 "d,v,t", dreg
, sreg
, AT
);
3796 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3797 (int) BFD_RELOC_LO16
);
3802 case M_SGT
: /* sreg > treg <==> treg < sreg */
3808 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3811 case M_SGT_I
: /* sreg > I <==> I < sreg */
3817 load_register (&icnt
, AT
, &imm_expr
);
3818 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3821 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3827 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3828 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3829 (int) BFD_RELOC_LO16
);
3832 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3838 load_register (&icnt
, AT
, &imm_expr
);
3839 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3840 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3841 (int) BFD_RELOC_LO16
);
3845 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3847 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3848 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3851 load_register (&icnt
, AT
, &imm_expr
);
3852 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3856 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3858 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3859 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3862 load_register (&icnt
, AT
, &imm_expr
);
3863 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3869 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3872 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3876 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3878 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3884 if (imm_expr
.X_add_number
== 0)
3886 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3892 as_warn ("Instruction %s: result is always true",
3894 macro_build ((char *) NULL
, &icnt
, &expr1
,
3895 mips_isa
< 3 ? "addiu" : "daddiu",
3896 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3899 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3901 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3902 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3905 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3907 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3908 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3909 mips_isa
< 3 ? "addiu" : "daddiu",
3910 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3915 load_register (&icnt
, AT
, &imm_expr
);
3916 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3920 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3928 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3930 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3931 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3932 dbl
? "daddi" : "addi",
3933 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3936 load_register (&icnt
, AT
, &imm_expr
);
3937 macro_build ((char *) NULL
, &icnt
, NULL
,
3938 dbl
? "dsub" : "sub",
3939 "d,v,t", dreg
, sreg
, AT
);
3945 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3947 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3948 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3949 dbl
? "daddiu" : "addiu",
3950 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3953 load_register (&icnt
, AT
, &imm_expr
);
3954 macro_build ((char *) NULL
, &icnt
, NULL
,
3955 dbl
? "dsubu" : "subu",
3956 "d,v,t", dreg
, sreg
, AT
);
3977 load_register (&icnt
, AT
, &imm_expr
);
3978 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3983 assert (mips_isa
< 2);
3984 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3985 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3988 * Is the double cfc1 instruction a bug in the mips assembler;
3989 * or is there a reason for it?
3991 mips_emit_delays ();
3993 mips_any_noreorder
= 1;
3994 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3995 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3996 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3997 expr1
.X_add_number
= 3;
3998 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3999 (int) BFD_RELOC_LO16
);
4000 expr1
.X_add_number
= 2;
4001 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4002 (int) BFD_RELOC_LO16
);
4003 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4004 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4005 macro_build ((char *) NULL
, &icnt
, NULL
,
4006 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4007 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4008 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4018 if (offset_expr
.X_add_number
>= 0x7fff)
4019 as_bad ("operand overflow");
4020 /* avoid load delay */
4021 if (byte_order
== LITTLE_ENDIAN
)
4022 offset_expr
.X_add_number
+= 1;
4023 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4024 (int) BFD_RELOC_LO16
, breg
);
4025 if (byte_order
== LITTLE_ENDIAN
)
4026 offset_expr
.X_add_number
-= 1;
4028 offset_expr
.X_add_number
+= 1;
4029 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4030 (int) BFD_RELOC_LO16
, breg
);
4031 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4032 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4045 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4046 as_bad ("operand overflow");
4047 if (byte_order
== LITTLE_ENDIAN
)
4048 offset_expr
.X_add_number
+= off
;
4049 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4050 (int) BFD_RELOC_LO16
, breg
);
4051 if (byte_order
== LITTLE_ENDIAN
)
4052 offset_expr
.X_add_number
-= off
;
4054 offset_expr
.X_add_number
+= off
;
4055 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4056 (int) BFD_RELOC_LO16
, breg
);
4069 load_address (&icnt
, AT
, &offset_expr
);
4070 if (byte_order
== LITTLE_ENDIAN
)
4071 expr1
.X_add_number
= off
;
4073 expr1
.X_add_number
= 0;
4074 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4075 (int) BFD_RELOC_LO16
, AT
);
4076 if (byte_order
== LITTLE_ENDIAN
)
4077 expr1
.X_add_number
= 0;
4079 expr1
.X_add_number
= off
;
4080 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4081 (int) BFD_RELOC_LO16
, AT
);
4086 load_address (&icnt
, AT
, &offset_expr
);
4087 if (byte_order
== BIG_ENDIAN
)
4088 expr1
.X_add_number
= 0;
4089 macro_build ((char *) NULL
, &icnt
, &expr1
,
4090 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4091 (int) BFD_RELOC_LO16
, AT
);
4092 if (byte_order
== BIG_ENDIAN
)
4093 expr1
.X_add_number
= 1;
4095 expr1
.X_add_number
= 0;
4096 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4097 (int) BFD_RELOC_LO16
, AT
);
4098 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4100 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4105 if (offset_expr
.X_add_number
>= 0x7fff)
4106 as_bad ("operand overflow");
4107 if (byte_order
== BIG_ENDIAN
)
4108 offset_expr
.X_add_number
+= 1;
4109 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4110 (int) BFD_RELOC_LO16
, breg
);
4111 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4112 if (byte_order
== BIG_ENDIAN
)
4113 offset_expr
.X_add_number
-= 1;
4115 offset_expr
.X_add_number
+= 1;
4116 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4117 (int) BFD_RELOC_LO16
, breg
);
4130 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4131 as_bad ("operand overflow");
4132 if (byte_order
== LITTLE_ENDIAN
)
4133 offset_expr
.X_add_number
+= off
;
4134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4135 (int) BFD_RELOC_LO16
, breg
);
4136 if (byte_order
== LITTLE_ENDIAN
)
4137 offset_expr
.X_add_number
-= off
;
4139 offset_expr
.X_add_number
+= off
;
4140 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4141 (int) BFD_RELOC_LO16
, breg
);
4154 load_address (&icnt
, AT
, &offset_expr
);
4155 if (byte_order
== LITTLE_ENDIAN
)
4156 expr1
.X_add_number
= off
;
4158 expr1
.X_add_number
= 0;
4159 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4160 (int) BFD_RELOC_LO16
, AT
);
4161 if (byte_order
== LITTLE_ENDIAN
)
4162 expr1
.X_add_number
= 0;
4164 expr1
.X_add_number
= off
;
4165 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4166 (int) BFD_RELOC_LO16
, AT
);
4170 load_address (&icnt
, AT
, &offset_expr
);
4171 if (byte_order
== LITTLE_ENDIAN
)
4172 expr1
.X_add_number
= 0;
4173 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4174 (int) BFD_RELOC_LO16
, AT
);
4175 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4177 if (byte_order
== LITTLE_ENDIAN
)
4178 expr1
.X_add_number
= 1;
4180 expr1
.X_add_number
= 0;
4181 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4182 (int) BFD_RELOC_LO16
, AT
);
4183 if (byte_order
== LITTLE_ENDIAN
)
4184 expr1
.X_add_number
= 0;
4186 expr1
.X_add_number
= 1;
4187 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4188 (int) BFD_RELOC_LO16
, AT
);
4189 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4191 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4196 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4200 as_warn ("Macro used $at after \".set noat\"");
4205 This routine assembles an instruction into its binary format. As a side
4206 effect it sets one of the global variables imm_reloc or offset_reloc to the
4207 type of relocation to do if one of the operands is an address expression.
4212 struct mips_cl_insn
*ip
;
4217 struct mips_opcode
*insn
;
4220 unsigned int lastregno
= 0;
4225 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4237 as_fatal ("Unknown opcode: `%s'", str
);
4239 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4241 as_warn ("`%s' not in hash table.", str
);
4242 insn_error
= "ERROR: Unrecognized opcode";
4250 assert (strcmp (insn
->name
, str
) == 0);
4252 if (insn
->pinfo
== INSN_MACRO
)
4253 insn_isa
= insn
->match
;
4254 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
4256 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
4261 if (insn_isa
> mips_isa
4262 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
4265 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4266 && strcmp (insn
->name
, insn
[1].name
) == 0)
4271 as_warn ("Instruction not supported on this processor");
4275 ip
->insn_opcode
= insn
->match
;
4276 for (args
= insn
->args
;; ++args
)
4282 case '\0': /* end of args */
4295 ip
->insn_opcode
|= lastregno
<< 21;
4300 ip
->insn_opcode
|= lastregno
<< 16;
4304 ip
->insn_opcode
|= lastregno
<< 11;
4310 /* handle optional base register.
4311 Either the base register is omitted or
4312 we must have a left paren. */
4313 /* this is dependent on the next operand specifier
4314 is a 'b' for base register */
4315 assert (args
[1] == 'b');
4319 case ')': /* these must match exactly */
4324 case '<': /* must be at least one digit */
4326 * According to the manual, if the shift amount is greater
4327 * than 31 or less than 0 the the shift amount should be
4328 * mod 32. In reality the mips assembler issues an error.
4329 * We issue a warning and mask out all but the low 5 bits.
4331 my_getExpression (&imm_expr
, s
);
4332 check_absolute_expr (ip
, &imm_expr
);
4333 if ((unsigned long) imm_expr
.X_add_number
> 31)
4335 as_warn ("Improper shift amount (%ld)",
4336 (long) imm_expr
.X_add_number
);
4337 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4339 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4340 imm_expr
.X_op
= O_absent
;
4344 case '>': /* shift amount minus 32 */
4345 my_getExpression (&imm_expr
, s
);
4346 check_absolute_expr (ip
, &imm_expr
);
4347 if ((unsigned long) imm_expr
.X_add_number
< 32
4348 || (unsigned long) imm_expr
.X_add_number
> 63)
4350 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4351 imm_expr
.X_op
= O_absent
;
4355 case 'k': /* cache code */
4356 my_getExpression (&imm_expr
, s
);
4357 check_absolute_expr (ip
, &imm_expr
);
4358 if ((unsigned long) imm_expr
.X_add_number
> 31)
4360 as_warn ("Invalid cahce opcode (%lu)",
4361 (unsigned long) imm_expr
.X_add_number
);
4362 imm_expr
.X_add_number
&= 0x1f;
4364 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4365 imm_expr
.X_op
= O_absent
;
4369 case 'c': /* break code */
4370 my_getExpression (&imm_expr
, s
);
4371 check_absolute_expr (ip
, &imm_expr
);
4372 if ((unsigned) imm_expr
.X_add_number
> 1023)
4373 as_warn ("Illegal break code (%ld)",
4374 (long) imm_expr
.X_add_number
);
4375 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4376 imm_expr
.X_op
= O_absent
;
4380 case 'B': /* syscall code */
4381 my_getExpression (&imm_expr
, s
);
4382 check_absolute_expr (ip
, &imm_expr
);
4383 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4384 as_warn ("Illegal syscall code (%ld)",
4385 (long) imm_expr
.X_add_number
);
4386 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4387 imm_expr
.X_op
= O_absent
;
4391 case 'C': /* Coprocessor code */
4392 my_getExpression (&imm_expr
, s
);
4393 check_absolute_expr (ip
, &imm_expr
);
4394 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4396 as_warn ("Coproccesor code > 25 bits (%ld)",
4397 (long) imm_expr
.X_add_number
);
4398 imm_expr
.X_add_number
&= ((1<<25) - 1);
4400 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4401 imm_expr
.X_op
= O_absent
;
4405 case 'b': /* base register */
4406 case 'd': /* destination register */
4407 case 's': /* source register */
4408 case 't': /* target register */
4409 case 'r': /* both target and source */
4410 case 'v': /* both dest and source */
4411 case 'w': /* both dest and target */
4412 case 'E': /* coprocessor target register */
4413 case 'G': /* coprocessor destination register */
4414 case 'x': /* ignore register name */
4415 case 'z': /* must be zero register */
4429 while (isdigit (*s
));
4431 as_bad ("Invalid register number (%d)", regno
);
4433 else if (*args
== 'E' || *args
== 'G')
4437 if (s
[1] == 'f' && s
[2] == 'p')
4442 else if (s
[1] == 's' && s
[2] == 'p')
4447 else if (s
[1] == 'g' && s
[2] == 'p')
4452 else if (s
[1] == 'a' && s
[2] == 't')
4457 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
4462 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
4470 if (regno
== AT
&& ! mips_noat
)
4471 as_warn ("Used $at without \".set noat\"");
4477 if (c
== 'r' || c
== 'v' || c
== 'w')
4484 /* 'z' only matches $0. */
4485 if (c
== 'z' && regno
!= 0)
4493 ip
->insn_opcode
|= regno
<< 21;
4497 ip
->insn_opcode
|= regno
<< 11;
4502 ip
->insn_opcode
|= regno
<< 16;
4505 /* This case exists because on the r3000 trunc
4506 expands into a macro which requires a gp
4507 register. On the r6000 or r4000 it is
4508 assembled into a single instruction which
4509 ignores the register. Thus the insn version
4510 is MIPS_ISA2 and uses 'x', and the macro
4511 version is MIPS_ISA1 and uses 't'. */
4514 /* This case is for the div instruction, which
4515 acts differently if the destination argument
4516 is $0. This only matches $0, and is checked
4517 outside the switch. */
4528 ip
->insn_opcode
|= lastregno
<< 21;
4531 ip
->insn_opcode
|= lastregno
<< 16;
4536 case 'D': /* floating point destination register */
4537 case 'S': /* floating point source register */
4538 case 'T': /* floating point target register */
4542 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4552 while (isdigit (*s
));
4555 as_bad ("Invalid float register number (%d)", regno
);
4557 if ((regno
& 1) != 0
4559 && ! (strcmp (str
, "mtc1") == 0 ||
4560 strcmp (str
, "mfc1") == 0 ||
4561 strcmp (str
, "lwc1") == 0 ||
4562 strcmp (str
, "swc1") == 0))
4563 as_warn ("Float register should be even, was %d",
4571 if (c
== 'V' || c
== 'W')
4581 ip
->insn_opcode
|= regno
<< 6;
4585 ip
->insn_opcode
|= regno
<< 11;
4589 ip
->insn_opcode
|= regno
<< 16;
4597 ip
->insn_opcode
|= lastregno
<< 11;
4600 ip
->insn_opcode
|= lastregno
<< 16;
4606 my_getExpression (&imm_expr
, s
);
4607 if (imm_expr
.X_op
!= O_big
)
4608 check_absolute_expr (ip
, &imm_expr
);
4613 my_getExpression (&offset_expr
, s
);
4614 imm_reloc
= BFD_RELOC_32
;
4626 unsigned char temp
[8];
4628 unsigned int length
;
4633 /* These only appear as the last operand in an
4634 instruction, and every instruction that accepts
4635 them in any variant accepts them in all variants.
4636 This means we don't have to worry about backing out
4637 any changes if the instruction does not match.
4639 The difference between them is the size of the
4640 floating point constant and where it goes. For 'F'
4641 and 'L' the constant is 64 bits; for 'f' and 'l' it
4642 is 32 bits. Where the constant is placed is based
4643 on how the MIPS assembler does things:
4646 f -- immediate value
4649 The .lit4 and .lit8 sections are only used if
4650 permitted by the -G argument.
4652 When generating embedded PIC code, we use the
4653 .lit8 section but not the .lit4 section (we can do
4654 .lit4 inline easily; we need to put .lit8
4655 somewhere in the data segment, and using .lit8
4656 permits the linker to eventually combine identical
4659 f64
= *args
== 'F' || *args
== 'L';
4661 save_in
= input_line_pointer
;
4662 input_line_pointer
= s
;
4663 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4665 s
= input_line_pointer
;
4666 input_line_pointer
= save_in
;
4667 if (err
!= NULL
&& *err
!= '\0')
4669 as_bad ("Bad floating point constant: %s", err
);
4670 memset (temp
, '\0', sizeof temp
);
4671 length
= f64
? 8 : 4;
4674 assert (length
== (f64
? 8 : 4));
4679 && (mips_pic
== EMBEDDED_PIC
4680 || g_switch_value
< 4)
4684 imm_expr
.X_op
= O_constant
;
4685 if (byte_order
== LITTLE_ENDIAN
)
4686 imm_expr
.X_add_number
=
4687 (((((((int) temp
[3] << 8)
4692 imm_expr
.X_add_number
=
4693 (((((((int) temp
[0] << 8)
4700 const char *newname
;
4703 /* Switch to the right section. */
4705 subseg
= now_subseg
;
4708 default: /* unused default case avoids warnings. */
4710 newname
= RDATA_SECTION_NAME
;
4712 if (g_switch_value
>= 8)
4717 newname
= RDATA_SECTION_NAME
;
4721 assert (g_switch_value
>= 4);
4726 new_seg
= subseg_new (newname
, (subsegT
) 0);
4727 frag_align (*args
== 'l' ? 2 : 3, 0);
4729 record_alignment (new_seg
, 4);
4731 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4734 as_bad ("Can't use floating point insn in this section");
4736 /* Set the argument to the current address in the
4738 offset_expr
.X_op
= O_symbol
;
4739 offset_expr
.X_add_symbol
=
4740 symbol_new ("L0\001", now_seg
,
4741 (valueT
) frag_now_fix (), frag_now
);
4742 offset_expr
.X_add_number
= 0;
4744 /* Put the floating point number into the section. */
4745 p
= frag_more ((int) length
);
4746 memcpy (p
, temp
, length
);
4748 /* Switch back to the original section. */
4749 subseg_set (seg
, subseg
);
4754 case 'i': /* 16 bit unsigned immediate */
4755 case 'j': /* 16 bit signed immediate */
4756 imm_reloc
= BFD_RELOC_LO16
;
4757 c
= my_getSmallExpression (&imm_expr
, s
);
4762 if (imm_expr
.X_op
== O_constant
)
4763 imm_expr
.X_add_number
=
4764 (imm_expr
.X_add_number
>> 16) & 0xffff;
4766 imm_reloc
= BFD_RELOC_HI16_S
;
4768 imm_reloc
= BFD_RELOC_HI16
;
4771 else if (imm_expr
.X_op
!= O_big
)
4772 check_absolute_expr (ip
, &imm_expr
);
4775 if (imm_expr
.X_op
== O_big
4776 || imm_expr
.X_add_number
< 0
4777 || imm_expr
.X_add_number
>= 0x10000)
4779 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4780 !strcmp (insn
->name
, insn
[1].name
))
4782 as_bad ("16 bit expression not in range 0..65535");
4790 /* The upper bound should be 0x8000, but
4791 unfortunately the MIPS assembler accepts numbers
4792 from 0x8000 to 0xffff and sign extends them, and
4793 we want to be compatible. We only permit this
4794 extended range for an instruction which does not
4795 provide any further alternates, since those
4796 alternates may handle other cases. People should
4797 use the numbers they mean, rather than relying on
4798 a mysterious sign extension. */
4799 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4800 strcmp (insn
->name
, insn
[1].name
) == 0);
4805 if (imm_expr
.X_op
== O_big
4806 || imm_expr
.X_add_number
< -0x8000
4807 || imm_expr
.X_add_number
>= max
)
4811 as_bad ("16 bit expression not in range -32768..32767");
4817 case 'o': /* 16 bit offset */
4818 c
= my_getSmallExpression (&offset_expr
, s
);
4820 /* If this value won't fit into a 16 bit offset, then go
4821 find a macro that will generate the 32 bit offset
4822 code pattern. As a special hack, we accept the
4823 difference of two local symbols as a constant. This
4824 is required to suppose embedded PIC switches, which
4825 use an instruction which looks like
4826 lw $4,$L12-$LS12($4)
4827 The problem with handling this in a more general
4828 fashion is that the macro function doesn't expect to
4829 see anything which can be handled in a single
4830 constant instruction. */
4832 && (offset_expr
.X_op
!= O_constant
4833 || offset_expr
.X_add_number
>= 0x8000
4834 || offset_expr
.X_add_number
< -0x8000)
4835 && (mips_pic
!= EMBEDDED_PIC
4836 || offset_expr
.X_op
!= O_subtract
4837 || now_seg
!= text_section
4838 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
4842 offset_reloc
= BFD_RELOC_LO16
;
4843 if (c
== 'h' || c
== 'H')
4845 assert (offset_expr
.X_op
== O_constant
);
4846 offset_expr
.X_add_number
=
4847 (offset_expr
.X_add_number
>> 16) & 0xffff;
4852 case 'p': /* pc relative offset */
4853 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4854 my_getExpression (&offset_expr
, s
);
4858 case 'u': /* upper 16 bits */
4859 c
= my_getSmallExpression (&imm_expr
, s
);
4860 if (imm_expr
.X_op
== O_constant
4861 && (imm_expr
.X_add_number
< 0
4862 || imm_expr
.X_add_number
>= 0x10000))
4863 as_bad ("lui expression not in range 0..65535");
4864 imm_reloc
= BFD_RELOC_LO16
;
4869 if (imm_expr
.X_op
== O_constant
)
4870 imm_expr
.X_add_number
=
4871 (imm_expr
.X_add_number
>> 16) & 0xffff;
4873 imm_reloc
= BFD_RELOC_HI16_S
;
4875 imm_reloc
= BFD_RELOC_HI16
;
4881 case 'a': /* 26 bit address */
4882 my_getExpression (&offset_expr
, s
);
4884 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4888 fprintf (stderr
, "bad char = '%c'\n", *args
);
4893 /* Args don't match. */
4894 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4895 !strcmp (insn
->name
, insn
[1].name
))
4901 insn_error
= "ERROR: Illegal operands";
4910 my_getSmallExpression (ep
, str
)
4921 ((str
[1] == 'h' && str
[2] == 'i')
4922 || (str
[1] == 'H' && str
[2] == 'I')
4923 || (str
[1] == 'l' && str
[2] == 'o'))
4935 * A small expression may be followed by a base register.
4936 * Scan to the end of this operand, and then back over a possible
4937 * base register. Then scan the small expression up to that
4938 * point. (Based on code in sparc.c...)
4940 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4942 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4944 if (isdigit (sp
[-2]))
4946 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4948 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4954 else if (sp
- 5 >= str
4957 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4958 || (sp
[-3] == 's' && sp
[-2] == 'p')
4959 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4960 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4966 /* no expression means zero offset */
4969 /* %xx(reg) is an error */
4970 ep
->X_op
= O_absent
;
4975 ep
->X_op
= O_constant
;
4978 ep
->X_add_symbol
= NULL
;
4979 ep
->X_op_symbol
= NULL
;
4980 ep
->X_add_number
= 0;
4985 my_getExpression (ep
, str
);
4992 my_getExpression (ep
, str
);
4993 return c
; /* => %hi or %lo encountered */
4997 my_getExpression (ep
, str
)
5003 save_in
= input_line_pointer
;
5004 input_line_pointer
= str
;
5006 expr_end
= input_line_pointer
;
5007 input_line_pointer
= save_in
;
5010 /* Turn a string in input_line_pointer into a floating point constant
5011 of type type, and store the appropriate bytes in *litP. The number
5012 of LITTLENUMS emitted is stored in *sizeP . An error message is
5013 returned, or NULL on OK. */
5016 md_atof (type
, litP
, sizeP
)
5022 LITTLENUM_TYPE words
[4];
5038 return "bad call to md_atof";
5041 t
= atof_ieee (input_line_pointer
, type
, words
);
5043 input_line_pointer
= t
;
5047 if (byte_order
== LITTLE_ENDIAN
)
5049 for (i
= prec
- 1; i
>= 0; i
--)
5051 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5057 for (i
= 0; i
< prec
; i
++)
5059 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5068 md_number_to_chars (buf
, val
, n
)
5076 number_to_chars_littleendian (buf
, val
, n
);
5080 number_to_chars_bigendian (buf
, val
, n
);
5089 CONST
char *md_shortopts
= "O::g::G:";
5091 CONST
char *md_shortopts
= "O::g::";
5093 struct option md_longopts
[] = {
5094 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5095 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5096 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5097 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5098 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5099 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5100 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5101 #define OPTION_MCPU (OPTION_MD_BASE + 4)
5102 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5103 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
5104 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5105 #define OPTION_TRAP (OPTION_MD_BASE + 8)
5106 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5107 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5108 #define OPTION_BREAK (OPTION_MD_BASE + 9)
5109 {"break", no_argument
, NULL
, OPTION_BREAK
},
5110 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5111 #define OPTION_EB (OPTION_MD_BASE + 10)
5112 {"EB", no_argument
, NULL
, OPTION_EB
},
5113 #define OPTION_EL (OPTION_MD_BASE + 11)
5114 {"EL", no_argument
, NULL
, OPTION_EL
},
5115 #define OPTION_M4650 (OPTION_MD_BASE + 12)
5116 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5117 #define OPTION_NO_M4650 (OPTION_MD_BASE + 13)
5118 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5121 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
5122 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5123 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5124 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
5125 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5128 {NULL
, no_argument
, NULL
, 0}
5130 size_t md_longopts_size
= sizeof(md_longopts
);
5133 md_parse_option (c
, arg
)
5148 byte_order
= BIG_ENDIAN
;
5150 mips_target_format
= "a.out-mips-big";
5153 mips_target_format
= "ecoff-bigmips";
5156 mips_target_format
= "elf32-bigmips";
5161 byte_order
= LITTLE_ENDIAN
;
5163 mips_target_format
= "a.out-mips-little";
5166 mips_target_format
= "ecoff-littlemips";
5169 mips_target_format
= "elf32-littlemips";
5174 if (arg
&& arg
[1] == '0')
5181 if (arg
== NULL
|| arg
[1] == '2')
5207 /* Identify the processor type */
5209 if (strcmp (p
, "default") == 0
5210 || strcmp (p
, "DEFAULT") == 0)
5214 if (*p
== 'r' || *p
== 'R')
5221 if (strcmp (p
, "2000") == 0
5222 || strcmp (p
, "2k") == 0
5223 || strcmp (p
, "2K") == 0)
5228 if (strcmp (p
, "3000") == 0
5229 || strcmp (p
, "3k") == 0
5230 || strcmp (p
, "3K") == 0)
5235 if (strcmp (p
, "4000") == 0
5236 || strcmp (p
, "4k") == 0
5237 || strcmp (p
, "4K") == 0)
5239 else if (strcmp (p
, "4400") == 0)
5241 else if (strcmp (p
, "4600") == 0)
5243 else if (strcmp (p
, "4650") == 0)
5252 if (strcmp (p
, "6000") == 0
5253 || strcmp (p
, "6k") == 0
5254 || strcmp (p
, "6K") == 0)
5259 if (strcmp (p
, "orion") == 0)
5266 as_bad ("invalid architecture -mcpu=%s", arg
);
5277 case OPTION_NO_M4650
:
5281 case OPTION_MEMBEDDED_PIC
:
5282 mips_pic
= EMBEDDED_PIC
;
5286 as_bad ("-G may not be used with embedded PIC code");
5289 g_switch_value
= 0x7fffffff;
5294 /* When generating ELF code, we permit -KPIC and -call_shared to
5295 select SVR4_PIC, and -non_shared to select no PIC. This is
5296 intended to be compatible with Irix 5. */
5297 case OPTION_CALL_SHARED
:
5298 mips_pic
= SVR4_PIC
;
5299 if (g_switch_seen
&& g_switch_value
!= 0)
5301 as_bad ("-G may not be used with SVR4 PIC code");
5307 case OPTION_NON_SHARED
:
5310 #endif /* OBJ_ELF */
5314 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5316 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5320 g_switch_value
= atoi (arg
);
5333 md_show_usage (stream
)
5338 -membedded-pic generate embedded position independent code\n\
5339 -EB generate big endian output\n\
5340 -EL generate little endian output\n\
5341 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5342 -G NUM allow referencing objects up to NUM bytes\n\
5343 implicitly with the gp register [default 8]\n");
5345 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5346 -mips2, -mcpu=r6000 generate code for r6000\n\
5347 -mips3, -mcpu=r4000 generate code for r4000\n\
5348 -O0 remove unneeded NOPs, do not swap branches\n\
5349 -O remove unneeded NOPs and swap branches\n\
5350 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5351 --break, --no-trap break exception on div by 0 and mult overflow\n");
5354 -KPIC, -call_shared generate SVR4 position independent code\n\
5355 -non_shared do not generate position independent code\n");
5360 md_pcrel_from (fixP
)
5364 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5365 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5367 /* This makes a branch to an undefined symbol be a branch to the
5368 current location. */
5373 /* return the address of the delay slot */
5374 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5377 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5378 reloc for a cons. We could use the definition there, except that
5379 we want to handle 64 bit relocs specially. */
5382 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5385 unsigned int nbytes
;
5388 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5390 FIXME: There is no way to select anything but 32 bit mode right
5394 if (byte_order
== BIG_ENDIAN
)
5399 if (nbytes
!= 2 && nbytes
!= 4)
5400 as_bad ("Unsupported reloc size %d", nbytes
);
5402 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5403 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5406 /* When generating embedded PIC code we need to use a special
5407 relocation to represent the difference of two symbols in the .text
5408 section (switch tables use a difference of this sort). See
5409 include/coff/mips.h for details. This macro checks whether this
5410 fixup requires the special reloc. */
5411 #define SWITCH_TABLE(fixp) \
5412 ((fixp)->fx_r_type == BFD_RELOC_32 \
5413 && (fixp)->fx_addsy != NULL \
5414 && (fixp)->fx_subsy != NULL \
5415 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5416 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5418 /* When generating embedded PIC code we must keep all PC relative
5419 relocations, in case the linker has to relax a call. We also need
5420 to keep relocations for switch table entries. */
5424 mips_force_relocation (fixp
)
5427 return (mips_pic
== EMBEDDED_PIC
5429 || SWITCH_TABLE (fixp
)
5430 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5431 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5434 /* Apply a fixup to the object file. */
5437 md_apply_fix (fixP
, valueP
)
5444 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
5447 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5449 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5452 switch (fixP
->fx_r_type
)
5454 case BFD_RELOC_MIPS_JMP
:
5455 case BFD_RELOC_HI16
:
5456 case BFD_RELOC_HI16_S
:
5457 case BFD_RELOC_MIPS_GPREL
:
5458 case BFD_RELOC_MIPS_LITERAL
:
5459 case BFD_RELOC_MIPS_CALL16
:
5460 case BFD_RELOC_MIPS_GOT16
:
5461 case BFD_RELOC_MIPS_GPREL32
:
5463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5464 "Invalid PC relative reloc");
5465 /* Nothing needed to do. The value comes from the reloc entry */
5468 case BFD_RELOC_PCREL_HI16_S
:
5469 /* The addend for this is tricky if it is internal, so we just
5470 do everything here rather than in bfd_perform_relocation. */
5471 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5473 /* For an external symbol adjust by the address to make it
5474 pcrel_offset. We use the address of the RELLO reloc
5475 which follows this one. */
5476 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5477 + fixP
->fx_next
->fx_where
);
5482 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5483 if (byte_order
== BIG_ENDIAN
)
5485 md_number_to_chars (buf
, value
, 2);
5488 case BFD_RELOC_PCREL_LO16
:
5489 /* The addend for this is tricky if it is internal, so we just
5490 do everything here rather than in bfd_perform_relocation. */
5491 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5492 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5493 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5494 if (byte_order
== BIG_ENDIAN
)
5496 md_number_to_chars (buf
, value
, 2);
5500 /* If we are deleting this reloc entry, we must fill in the
5501 value now. This can happen if we have a .word which is not
5502 resolved when it appears but is later defined. We also need
5503 to fill in the value if this is an embedded PIC switch table
5506 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5507 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5512 /* If we are deleting this reloc entry, we must fill in the
5514 assert (fixP
->fx_size
== 2);
5516 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5520 case BFD_RELOC_LO16
:
5521 /* When handling an embedded PIC switch statement, we can wind
5522 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5525 if (value
< -0x8000 || value
> 0x7fff)
5526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5527 "relocation overflow");
5528 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5529 if (byte_order
== BIG_ENDIAN
)
5531 md_number_to_chars (buf
, value
, 2);
5535 case BFD_RELOC_16_PCREL_S2
:
5537 * We need to save the bits in the instruction since fixup_segment()
5538 * might be deleting the relocation entry (i.e., a branch within
5539 * the current segment).
5542 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5543 "Branch to odd address (%lx)", value
);
5546 /* update old instruction data */
5547 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5551 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5555 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5563 if (value
>= -0x8000 && value
< 0x8000)
5564 insn
|= value
& 0xffff;
5567 /* The branch offset is too large. If this is an
5568 unconditional branch, and we are not generating PIC code,
5569 we can convert it to an absolute jump instruction. */
5570 if (mips_pic
== NO_PIC
5572 && fixP
->fx_frag
->fr_address
>= text_section
->vma
5573 && (fixP
->fx_frag
->fr_address
5574 < text_section
->vma
+ text_section
->_raw_size
)
5575 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5576 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
5577 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5579 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
5580 insn
= 0x0c000000; /* jal */
5582 insn
= 0x08000000; /* j */
5583 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
5585 fixP
->fx_addsy
= section_symbol (text_section
);
5586 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
5590 /* FIXME. It would be possible in principle to handle
5591 conditional branches which overflow. They could be
5592 transformed into a branch around a jump. This would
5593 require setting up variant frags for each different
5594 branch type. The native MIPS assembler attempts to
5595 handle these cases, but it appears to do it
5597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5598 "Relocation overflow");
5602 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5617 const struct mips_opcode
*p
;
5618 int treg
, sreg
, dreg
, shamt
;
5623 for (i
= 0; i
< NUMOPCODES
; ++i
)
5625 p
= &mips_opcodes
[i
];
5626 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5628 printf ("%08lx %s\t", oc
, p
->name
);
5629 treg
= (oc
>> 16) & 0x1f;
5630 sreg
= (oc
>> 21) & 0x1f;
5631 dreg
= (oc
>> 11) & 0x1f;
5632 shamt
= (oc
>> 6) & 0x1f;
5634 for (args
= p
->args
;; ++args
)
5645 printf ("%c", *args
);
5649 assert (treg
== sreg
);
5650 printf ("$%d,$%d", treg
, sreg
);
5655 printf ("$%d", dreg
);
5660 printf ("$%d", treg
);
5664 printf ("0x%x", treg
);
5669 printf ("$%d", sreg
);
5673 printf ("0x%08lx", oc
& 0x1ffffff);
5685 printf ("$%d", shamt
);
5696 printf ("%08lx UNDEFINED\n", oc
);
5707 name
= input_line_pointer
;
5708 c
= get_symbol_end ();
5709 p
= (symbolS
*) symbol_find_or_make (name
);
5710 *input_line_pointer
= c
;
5714 /* Align the current frag to a given power of two. The MIPS assembler
5715 also automatically adjusts any preceding label. */
5718 mips_align (to
, fill
, label
)
5723 mips_emit_delays ();
5724 frag_align (to
, fill
);
5725 record_alignment (now_seg
, to
);
5728 assert (S_GET_SEGMENT (label
) == now_seg
);
5729 label
->sy_frag
= frag_now
;
5730 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5734 /* Align to a given power of two. .align 0 turns off the automatic
5735 alignment used by the data creating pseudo-ops. */
5742 register long temp_fill
;
5743 long max_alignment
= 15;
5747 o Note that the assembler pulls down any immediately preceeding label
5748 to the aligned address.
5749 o It's not documented but auto alignment is reinstated by
5750 a .align pseudo instruction.
5751 o Note also that after auto alignment is turned off the mips assembler
5752 issues an error on attempt to assemble an improperly aligned data item.
5757 temp
= get_absolute_expression ();
5758 if (temp
> max_alignment
)
5759 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5762 as_warn ("Alignment negative: 0 assumed.");
5765 if (*input_line_pointer
== ',')
5767 input_line_pointer
++;
5768 temp_fill
= get_absolute_expression ();
5775 mips_align (temp
, (int) temp_fill
, insn_label
);
5782 demand_empty_rest_of_line ();
5785 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5786 that there was a previous instruction. */
5789 s_stringer (append_zero
)
5792 mips_emit_delays ();
5794 stringer (append_zero
);
5805 /* When generating embedded PIC code, we only use the .text, .lit8,
5806 .sdata and .sbss sections. We change the .data and .rdata
5807 pseudo-ops to use .sdata. */
5808 if (mips_pic
== EMBEDDED_PIC
5809 && (sec
== 'd' || sec
== 'r'))
5812 mips_emit_delays ();
5822 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5823 demand_empty_rest_of_line ();
5828 seg
= subseg_new (RDATA_SECTION_NAME
,
5829 (subsegT
) get_absolute_expression ());
5831 bfd_set_section_flags (stdoutput
, seg
,
5837 bfd_set_section_alignment (stdoutput
, seg
, 4);
5839 demand_empty_rest_of_line ();
5840 #else /* ! defined (GPOPT) */
5841 as_bad ("No read only data section in this object file format");
5842 demand_empty_rest_of_line ();
5844 #endif /* ! defined (GPOPT) */
5849 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5851 bfd_set_section_flags (stdoutput
, seg
,
5852 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5853 bfd_set_section_alignment (stdoutput
, seg
, 4);
5855 demand_empty_rest_of_line ();
5857 #else /* ! defined (GPOPT) */
5858 as_bad ("Global pointers not supported; recompile -G 0");
5859 demand_empty_rest_of_line ();
5861 #endif /* ! defined (GPOPT) */
5869 /* Handle the ELF .section pseudo-op. This is a wrapper around
5876 mips_emit_delays ();
5877 obj_elf_section (x
);
5881 #endif /* OBJ_ELF */
5890 mips_emit_delays ();
5891 if (log_size
> 0 && auto_align
)
5892 mips_align (log_size
, 0, label
);
5894 cons (1 << log_size
);
5901 as_fatal ("Encountered `.err', aborting assembly");
5911 symbolP
= get_symbol ();
5912 if (*input_line_pointer
== ',')
5913 input_line_pointer
++;
5914 size
= get_absolute_expression ();
5915 S_SET_EXTERNAL (symbolP
);
5917 #ifdef ECOFF_DEBUGGING
5918 symbolP
->ecoff_extern_size
= size
;
5930 mips_emit_delays ();
5934 mips_align (3, 0, label
);
5936 mips_align (2, 0, label
);
5943 /* Handle .globl. We need to override it because on Irix 5 you are
5946 where foo is an undefined symbol, to mean that foo should be
5947 considered to be the address of a function. */
5957 name
= input_line_pointer
;
5958 c
= get_symbol_end ();
5959 symbolP
= symbol_find_or_make (name
);
5960 *input_line_pointer
= c
;
5962 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5967 secname
= input_line_pointer
;
5968 c
= get_symbol_end ();
5969 sec
= bfd_get_section_by_name (stdoutput
, secname
);
5971 as_bad ("%s: no such section", secname
);
5972 *input_line_pointer
= c
;
5974 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
5975 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
5978 S_SET_EXTERNAL (symbolP
);
5979 demand_empty_rest_of_line ();
5989 opt
= input_line_pointer
;
5990 c
= get_symbol_end ();
5994 /* FIXME: What does this mean? */
5996 else if (strncmp (opt
, "pic", 3) == 0)
6004 mips_pic
= SVR4_PIC
;
6006 as_bad (".option pic%d not supported", i
);
6009 if (mips_pic
== SVR4_PIC
)
6011 if (g_switch_seen
&& g_switch_value
!= 0)
6012 as_warn ("-G may not be used with SVR4 PIC code");
6014 bfd_set_gp_size (stdoutput
, 0);
6019 as_warn ("Unrecognized option \"%s\"", opt
);
6021 *input_line_pointer
= c
;
6022 demand_empty_rest_of_line ();
6029 char *name
= input_line_pointer
, ch
;
6031 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6032 input_line_pointer
++;
6033 ch
= *input_line_pointer
;
6034 *input_line_pointer
= '\0';
6036 if (strcmp (name
, "reorder") == 0)
6040 prev_insn_unreordered
= 1;
6041 prev_prev_insn_unreordered
= 1;
6045 else if (strcmp (name
, "noreorder") == 0)
6047 mips_emit_delays ();
6049 mips_any_noreorder
= 1;
6051 else if (strcmp (name
, "at") == 0)
6055 else if (strcmp (name
, "noat") == 0)
6059 else if (strcmp (name
, "macro") == 0)
6061 mips_warn_about_macros
= 0;
6063 else if (strcmp (name
, "nomacro") == 0)
6065 if (mips_noreorder
== 0)
6066 as_bad ("`noreorder' must be set before `nomacro'");
6067 mips_warn_about_macros
= 1;
6069 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
6073 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
6077 else if (strcmp (name
, "bopt") == 0)
6081 else if (strcmp (name
, "nobopt") == 0)
6085 else if (strncmp (name
, "mips", 4) == 0)
6089 /* Permit the user to change the ISA on the fly. Needless to
6090 say, misuse can cause serious problems. */
6091 isa
= atoi (name
+ 4);
6093 mips_isa
= file_mips_isa
;
6094 else if (isa
< 1 || isa
> 3)
6095 as_bad ("unknown ISA level");
6101 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
6103 *input_line_pointer
= ch
;
6104 demand_empty_rest_of_line ();
6107 /* The same as the usual .space directive, except that we have to
6108 forget about any previous instruction. */
6111 s_mips_space (param
)
6114 mips_emit_delays ();
6119 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
6120 .option pic2. It means to generate SVR4 PIC calls. */
6126 mips_pic
= SVR4_PIC
;
6128 if (g_switch_seen
&& g_switch_value
!= 0)
6129 as_warn ("-G may not be used with SVR4 PIC code");
6132 bfd_set_gp_size (stdoutput
, 0);
6133 demand_empty_rest_of_line ();
6136 /* Handle the .cpload pseudo-op. This is used when generating SVR4
6137 PIC code. It sets the $gp register for the function based on the
6138 function address, which is in the register named in the argument.
6139 This uses a relocation against _gp_disp, which is handled specially
6140 by the linker. The result is:
6141 lui $gp,%hi(_gp_disp)
6142 addiu $gp,$gp,%lo(_gp_disp)
6143 addu $gp,$gp,.cpload argument
6144 The .cpload argument is normally $25 == $t9. */
6153 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6154 if (mips_pic
!= SVR4_PIC
)
6160 /* .cpload should be a in .set noreorder section. */
6161 if (mips_noreorder
== 0)
6162 as_warn (".cpload not in noreorder section");
6165 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6166 ex
.X_op_symbol
= NULL
;
6167 ex
.X_add_number
= 0;
6169 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6170 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6171 (int) BFD_RELOC_LO16
);
6173 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6174 GP
, GP
, tc_get_register (0));
6176 demand_empty_rest_of_line ();
6179 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6180 offset from $sp. The offset is remembered, and after making a PIC
6181 call $gp is restored from that location. */
6184 s_cprestore (ignore
)
6190 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6191 if (mips_pic
!= SVR4_PIC
)
6197 mips_cprestore_offset
= get_absolute_expression ();
6199 ex
.X_op
= O_constant
;
6200 ex
.X_add_symbol
= NULL
;
6201 ex
.X_op_symbol
= NULL
;
6202 ex
.X_add_number
= mips_cprestore_offset
;
6204 macro_build ((char *) NULL
, &icnt
, &ex
,
6205 mips_isa
< 3 ? "sw" : "sd",
6206 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6208 demand_empty_rest_of_line ();
6211 /* Handle the .gpword pseudo-op. This is used when generating PIC
6212 code. It generates a 32 bit GP relative reloc. */
6222 /* When not generating PIC code, this is treated as .word. */
6223 if (mips_pic
!= SVR4_PIC
)
6230 mips_emit_delays ();
6232 mips_align (2, 0, label
);
6237 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6239 as_bad ("Unsupported use of .gpword");
6240 ignore_rest_of_line ();
6244 md_number_to_chars (p
, (valueT
) 0, 4);
6245 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6246 BFD_RELOC_MIPS_GPREL32
);
6248 demand_empty_rest_of_line ();
6251 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6252 tables in SVR4 PIC code. */
6261 /* This is ignored when not generating SVR4 PIC code. */
6262 if (mips_pic
!= SVR4_PIC
)
6268 /* Add $gp to the register named as an argument. */
6269 reg
= tc_get_register (0);
6270 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6271 mips_isa
< 3 ? "addu" : "daddu",
6272 "d,v,t", reg
, reg
, GP
);
6274 demand_empty_rest_of_line ();
6277 /* Parse a register string into a number. Called from the ECOFF code
6278 to parse .frame. The argument is non-zero if this is the frame
6279 register, so that we can record it in mips_frame_reg. */
6282 tc_get_register (frame
)
6288 if (*input_line_pointer
++ != '$')
6290 as_warn ("expected `$'");
6293 else if (isdigit ((unsigned char) *input_line_pointer
))
6295 reg
= get_absolute_expression ();
6296 if (reg
< 0 || reg
>= 32)
6298 as_warn ("Bad register number");
6304 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6306 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6308 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6310 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6314 as_warn ("Unrecognized register name");
6317 input_line_pointer
+= 2;
6320 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6325 md_section_align (seg
, addr
)
6329 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6331 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6334 /* Estimate the size of a frag before relaxing. We are not really
6335 relaxing here, and the final size is encoded in the subtype
6340 md_estimate_size_before_relax (fragp
, segtype
)
6346 if (mips_pic
== NO_PIC
)
6349 const char *symname
;
6351 /* Find out whether this symbol can be referenced off the GP
6352 register. It can be if it is smaller than the -G size or if
6353 it is in the .sdata or .sbss section. Certain symbols can
6354 not be referenced off the GP, although it appears as though
6356 symname
= S_GET_NAME (fragp
->fr_symbol
);
6357 if (symname
!= (const char *) NULL
6358 && (strcmp (symname
, "eprol") == 0
6359 || strcmp (symname
, "etext") == 0
6360 || strcmp (symname
, "_gp") == 0
6361 || strcmp (symname
, "edata") == 0
6362 || strcmp (symname
, "_fbss") == 0
6363 || strcmp (symname
, "_fdata") == 0
6364 || strcmp (symname
, "_ftext") == 0
6365 || strcmp (symname
, "end") == 0
6366 || strcmp (symname
, "_gp_disp") == 0))
6368 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6369 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6370 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6371 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6372 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6376 const char *segname
;
6378 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6379 assert (strcmp (segname
, ".lit8") != 0
6380 && strcmp (segname
, ".lit4") != 0);
6381 change
= (strcmp (segname
, ".sdata") != 0
6382 && strcmp (segname
, ".sbss") != 0);
6384 #else /* ! defined (GPOPT) */
6385 /* We are not optimizing for the GP register. */
6387 #endif /* ! defined (GPOPT) */
6389 else if (mips_pic
== SVR4_PIC
)
6391 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6393 /* This must duplicate the test in adjust_reloc_syms. */
6394 change
= (symsec
!= &bfd_und_section
6395 && symsec
!= &bfd_abs_section
6396 && ! bfd_is_com_section (symsec
));
6403 /* Record the offset to the first reloc in the fr_opcode field.
6404 This lets md_convert_frag and tc_gen_reloc know that the code
6405 must be expanded. */
6406 fragp
->fr_opcode
= (fragp
->fr_literal
6408 - RELAX_OLD (fragp
->fr_subtype
)
6409 + RELAX_RELOC1 (fragp
->fr_subtype
));
6410 /* FIXME: This really needs as_warn_where. */
6411 if (RELAX_WARN (fragp
->fr_subtype
))
6412 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6418 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6421 /* Translate internal representation of relocation info to BFD target
6425 tc_gen_reloc (section
, fixp
)
6429 static arelent
*retval
[4];
6432 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6435 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6436 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6438 if (mips_pic
== EMBEDDED_PIC
6439 && SWITCH_TABLE (fixp
))
6441 /* For a switch table entry we use a special reloc. The addend
6442 is actually the difference between the reloc address and the
6444 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6446 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6448 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6450 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6452 /* We use a special addend for an internal RELLO reloc. */
6453 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6454 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6456 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6458 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6460 assert (fixp
->fx_next
!= NULL
6461 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6462 /* We use a special addend for an internal RELHI reloc. The
6463 reloc is relative to the RELLO; adjust the addend
6465 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6466 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6467 + fixp
->fx_next
->fx_where
6468 - S_GET_VALUE (fixp
->fx_subsy
));
6470 reloc
->addend
= (fixp
->fx_addnumber
6471 + fixp
->fx_next
->fx_frag
->fr_address
6472 + fixp
->fx_next
->fx_where
);
6474 else if (fixp
->fx_pcrel
== 0)
6475 reloc
->addend
= fixp
->fx_addnumber
;
6479 /* A gruesome hack which is a result of the gruesome gas reloc
6481 reloc
->addend
= reloc
->address
;
6483 reloc
->addend
= -reloc
->address
;
6487 /* If this is a variant frag, we may need to adjust the existing
6488 reloc and generate a new one. */
6489 if (fixp
->fx_frag
->fr_opcode
!= NULL
6490 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6491 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6492 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6496 /* If this is not the last reloc in this frag, then we have two
6497 GPREL relocs, both of which are being replaced. Let the
6498 second one handle all of them. */
6499 if (fixp
->fx_next
!= NULL
6500 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6502 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6503 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6508 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6509 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6510 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6512 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6513 reloc2
->address
= (reloc
->address
6514 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6515 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6516 reloc2
->addend
= fixp
->fx_addnumber
;
6517 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6518 assert (reloc2
->howto
!= NULL
);
6520 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6524 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6527 reloc3
->address
+= 4;
6530 if (mips_pic
== NO_PIC
)
6532 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6533 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6535 else if (mips_pic
== SVR4_PIC
)
6537 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6539 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6540 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6547 /* To support a PC relative reloc when generating embedded PIC code
6548 for ECOFF, we use a Cygnus extension. We check for that here to
6549 make sure that we don't let such a reloc escape normally. */
6551 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6552 && mips_pic
!= EMBEDDED_PIC
)
6553 reloc
->howto
= NULL
;
6556 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6558 if (reloc
->howto
== NULL
)
6560 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6561 "Can not represent relocation in this object file format");
6568 /* Convert a machine dependent frag. */
6571 md_convert_frag (abfd
, asec
, fragp
)
6579 if (fragp
->fr_opcode
== NULL
)
6582 old
= RELAX_OLD (fragp
->fr_subtype
);
6583 new = RELAX_NEW (fragp
->fr_subtype
);
6584 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6587 memcpy (fixptr
- old
, fixptr
, new);
6589 fragp
->fr_fix
+= new - old
;
6592 /* This function is called whenever a label is defined. It is used
6593 when handling branch delays; if a branch has a label, we assume we
6597 mips_define_label (sym
)
6605 /* Some special processing for a MIPS ELF file. */
6608 mips_elf_final_processing ()
6612 /* Write out the .reginfo section. */
6613 s
.ri_gprmask
= mips_gprmask
;
6614 s
.ri_cprmask
[0] = mips_cprmask
[0];
6615 s
.ri_cprmask
[1] = mips_cprmask
[1];
6616 s
.ri_cprmask
[2] = mips_cprmask
[2];
6617 s
.ri_cprmask
[3] = mips_cprmask
[3];
6618 /* The gp_value field is set by the MIPS ELF backend. */
6620 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6621 ((Elf32_External_RegInfo
*)
6622 mips_regmask_frag
));
6624 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6625 sort of BFD interface for this. */
6626 if (mips_any_noreorder
)
6627 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6628 if (mips_pic
!= NO_PIC
)
6629 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6632 #endif /* OBJ_ELF */
6634 #ifndef ECOFF_DEBUGGING
6636 /* These functions should really be defined by the object file format,
6637 since they are related to debugging information. However, this
6638 code has to work for the a.out format, which does not define them,
6639 so we provide simple versions here. These don't actually generate
6640 any debugging information, but they do simple checking and someday
6641 somebody may make them useful. */
6645 struct loc
*loc_next
;
6646 unsigned long loc_fileno
;
6647 unsigned long loc_lineno
;
6648 unsigned long loc_offset
;
6649 unsigned short loc_delta
;
6650 unsigned short loc_count
;
6659 struct proc
*proc_next
;
6660 struct symbol
*proc_isym
;
6661 struct symbol
*proc_end
;
6662 unsigned long proc_reg_mask
;
6663 unsigned long proc_reg_offset
;
6664 unsigned long proc_fpreg_mask
;
6665 unsigned long proc_fpreg_offset
;
6666 unsigned long proc_frameoffset
;
6667 unsigned long proc_framereg
;
6668 unsigned long proc_pcreg
;
6670 struct file
*proc_file
;
6677 struct file
*file_next
;
6678 unsigned long file_fileno
;
6679 struct symbol
*file_symbol
;
6680 struct symbol
*file_end
;
6681 struct proc
*file_proc
;
6686 static struct obstack proc_frags
;
6687 static procS
*proc_lastP
;
6688 static procS
*proc_rootP
;
6689 static int numprocs
;
6694 obstack_begin (&proc_frags
, 0x2000);
6700 /* check for premature end, nesting errors, etc */
6701 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6702 as_warn ("missing `.end' at end of assembly");
6711 if (*input_line_pointer
== '-')
6713 ++input_line_pointer
;
6716 if (!isdigit (*input_line_pointer
))
6717 as_bad ("Expected simple number.");
6718 if (input_line_pointer
[0] == '0')
6720 if (input_line_pointer
[1] == 'x')
6722 input_line_pointer
+= 2;
6723 while (isxdigit (*input_line_pointer
))
6726 val
|= hex_value (*input_line_pointer
++);
6728 return negative
? -val
: val
;
6732 ++input_line_pointer
;
6733 while (isdigit (*input_line_pointer
))
6736 val
|= *input_line_pointer
++ - '0';
6738 return negative
? -val
: val
;
6741 if (!isdigit (*input_line_pointer
))
6743 printf (" *input_line_pointer == '%c' 0x%02x\n",
6744 *input_line_pointer
, *input_line_pointer
);
6745 as_warn ("Invalid number");
6748 while (isdigit (*input_line_pointer
))
6751 val
+= *input_line_pointer
++ - '0';
6753 return negative
? -val
: val
;
6756 /* The .file directive; just like the usual .file directive, but there
6757 is an initial number which is the ECOFF file index. */
6765 line
= get_number ();
6770 /* The .end directive. */
6778 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6781 demand_empty_rest_of_line ();
6785 if (now_seg
!= text_section
)
6786 as_warn (".end not in text section");
6789 as_warn (".end and no .ent seen yet.");
6795 assert (S_GET_NAME (p
));
6796 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6797 as_warn (".end symbol does not match .ent symbol.");
6800 proc_lastP
->proc_end
= (symbolS
*) 1;
6803 /* The .aent and .ent directives. */
6813 symbolP
= get_symbol ();
6814 if (*input_line_pointer
== ',')
6815 input_line_pointer
++;
6817 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6818 number
= get_number ();
6819 if (now_seg
!= text_section
)
6820 as_warn (".ent or .aent not in text section.");
6822 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6823 as_warn ("missing `.end'");
6827 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6828 procP
->proc_isym
= symbolP
;
6829 procP
->proc_reg_mask
= 0;
6830 procP
->proc_reg_offset
= 0;
6831 procP
->proc_fpreg_mask
= 0;
6832 procP
->proc_fpreg_offset
= 0;
6833 procP
->proc_frameoffset
= 0;
6834 procP
->proc_framereg
= 0;
6835 procP
->proc_pcreg
= 0;
6836 procP
->proc_end
= NULL
;
6837 procP
->proc_next
= NULL
;
6839 proc_lastP
->proc_next
= procP
;
6845 demand_empty_rest_of_line ();
6848 /* The .frame directive. */
6861 frame_reg
= tc_get_register (1);
6862 if (*input_line_pointer
== ',')
6863 input_line_pointer
++;
6864 frame_off
= get_absolute_expression ();
6865 if (*input_line_pointer
== ',')
6866 input_line_pointer
++;
6867 pcreg
= tc_get_register (0);
6870 assert (proc_rootP
);
6871 proc_rootP
->proc_framereg
= frame_reg
;
6872 proc_rootP
->proc_frameoffset
= frame_off
;
6873 proc_rootP
->proc_pcreg
= pcreg
;
6874 /* bob macho .frame */
6876 /* We don't have to write out a frame stab for unoptimized code. */
6877 if (!(frame_reg
== FP
&& frame_off
== 0))
6880 as_warn ("No .ent for .frame to use.");
6881 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6882 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6883 S_SET_TYPE (symP
, N_RMASK
);
6884 S_SET_OTHER (symP
, 0);
6885 S_SET_DESC (symP
, 0);
6886 symP
->sy_forward
= proc_lastP
->proc_isym
;
6887 /* bob perhaps I should have used pseudo set */
6889 demand_empty_rest_of_line ();
6893 /* The .fmask and .mask directives. */
6900 char str
[100], *strP
;
6906 mask
= get_number ();
6907 if (*input_line_pointer
== ',')
6908 input_line_pointer
++;
6909 off
= get_absolute_expression ();
6911 /* bob only for coff */
6912 assert (proc_rootP
);
6913 if (reg_type
== 'F')
6915 proc_rootP
->proc_fpreg_mask
= mask
;
6916 proc_rootP
->proc_fpreg_offset
= off
;
6920 proc_rootP
->proc_reg_mask
= mask
;
6921 proc_rootP
->proc_reg_offset
= off
;
6924 /* bob macho .mask + .fmask */
6926 /* We don't have to write out a mask stab if no saved regs. */
6930 as_warn ("No .ent for .mask to use.");
6932 for (i
= 0; i
< 32; i
++)
6936 sprintf (strP
, "%c%d,", reg_type
, i
);
6937 strP
+= strlen (strP
);
6941 sprintf (strP
, ";%d,", off
);
6942 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6943 S_SET_TYPE (symP
, N_RMASK
);
6944 S_SET_OTHER (symP
, 0);
6945 S_SET_DESC (symP
, 0);
6946 symP
->sy_forward
= proc_lastP
->proc_isym
;
6947 /* bob perhaps I should have used pseudo set */
6952 /* The .loc directive. */
6963 assert (now_seg
== text_section
);
6965 lineno
= get_number ();
6966 addroff
= frag_now_fix ();
6968 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6969 S_SET_TYPE (symbolP
, N_SLINE
);
6970 S_SET_OTHER (symbolP
, 0);
6971 S_SET_DESC (symbolP
, lineno
);
6972 symbolP
->sy_segment
= now_seg
;
6976 #endif /* ! defined (ECOFF_DEBUGGING) */