1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Whether we are assembling for the mips16 processor. 0 if we are
152 not, 1 if we are, and -1 if the value has not been initialized.
153 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
154 -nomips16 command line options, and the default CPU. */
156 /* Non-zero if we should not reorder instructions. Changed by `.set
157 reorder' and `.set noreorder'. */
159 /* Non-zero if we should not permit the $at ($1) register to be used
160 in instructions. Changed by `.set at' and `.set noat'. */
162 /* Non-zero if we should warn when a macro instruction expands into
163 more than one machine instruction. Changed by `.set nomacro' and
165 int warn_about_macros
;
166 /* Non-zero if we should not move instructions. Changed by `.set
167 move', `.set volatile', `.set nomove', and `.set novolatile'. */
169 /* Non-zero if we should not optimize branches by moving the target
170 of the branch into the delay slot. Actually, we don't perform
171 this optimization anyhow. Changed by `.set bopt' and `.set
174 /* Non-zero if we should not autoextend mips16 instructions.
175 Changed by `.set autoextend' and `.set noautoextend'. */
179 /* This is the struct we use to hold the current set of options. Note
180 that we must set the isa and mips16 fields to -1 to indicate that
181 they have not been initialized. */
183 static struct mips_set_options mips_opts
= { -1, -1 };
185 /* These variables are filled in with the masks of registers used.
186 The object format code reads them and puts them in the appropriate
188 unsigned long mips_gprmask
;
189 unsigned long mips_cprmask
[4];
191 /* MIPS ISA we are using for this output file. */
192 static int file_mips_isa
;
194 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
195 static int mips_cpu
= -1;
197 /* Whether the 4650 instructions (mad/madu) are permitted. */
198 static int mips_4650
= -1;
200 /* Whether the 4010 instructions are permitted. */
201 static int mips_4010
= -1;
203 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
204 static int mips_4100
= -1;
206 /* start-sanitize-vr5400 */
207 /* Whether NEC vr5400 instructions are permitted. */
208 static int mips_5400
= -1;
210 /* end-sanitize-vr5400 */
211 /* start-sanitize-r5900 */
212 /* Whether Toshiba r5900 instructions are permitted. */
213 static int mips_5900
= -1;
215 /* end-sanitize-r5900 */
216 /* Whether Toshiba r3900 instructions are permitted. */
217 static int mips_3900
= -1;
219 /* start-sanitize-tx49 */
220 /* Whether Toshiba r4900 instructions are permitted. */
221 static int mips_4900
= -1;
223 /* end-sanitize-tx49 */
224 /* start-sanitize-tx19 */
225 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
226 The tx19 related options and configuration bits are handled by
228 /* end-sanitize-tx19 */
230 /* Whether the processor uses hardware interlocks to protect
231 reads from the HI and LO registers, and thus does not
232 require nops to be inserted. */
233 #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900 \
234 /* start-sanitize-tx49 */ \
235 || mips_cpu == 4900 || mips_4900 \
236 /* end-sanitize-tx49 */ \
237 /* start-sanitize-vr5400 */ \
238 || mips_cpu == 5400 \
239 /* end-sanitize-vr5400 */ \
242 /* Whether the processor uses hardware interlocks to protect reads
243 from the GPRs, and thus does not require nops to be inserted. */
244 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900)
245 /* start-sanitize-vr5400 */
246 #undef gpr_interlocks
247 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400)
248 /* end-sanitize-vr5400 */
251 /* As with other "interlocks" this is used by hardware that has FP
252 (co-processor) interlocks. */
253 /* Itbl support may require additional care here. */
254 #define cop_interlocks (mips_cpu == 4300)
255 /* start-sanitize-vr5400 */
256 #undef cop_interlocks
257 #define cop_interlocks (mips_cpu == 4300 || mips_cpu == 5400)
258 /* end-sanitize-vr5400 */
260 /* MIPS PIC level. */
264 /* Do not generate PIC code. */
267 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
268 not sure what it is supposed to do. */
271 /* Generate PIC code as in the SVR4 MIPS ABI. */
274 /* Generate PIC code without using a global offset table: the data
275 segment has a maximum size of 64K, all data references are off
276 the $gp register, and all text references are PC relative. This
277 is used on some embedded systems. */
281 static enum mips_pic_level mips_pic
;
283 /* 1 if we should generate 32 bit offsets from the GP register in
284 SVR4_PIC mode. Currently has no meaning in other modes. */
285 static int mips_big_got
;
287 /* 1 if trap instructions should used for overflow rather than break
289 static int mips_trap
;
291 /* Non-zero if any .set noreorder directives were used. */
293 static int mips_any_noreorder
;
295 /* The size of the small data section. */
296 static int g_switch_value
= 8;
297 /* Whether the -G option was used. */
298 static int g_switch_seen
= 0;
303 /* If we can determine in advance that GP optimization won't be
304 possible, we can skip the relaxation stuff that tries to produce
305 GP-relative references. This makes delay slot optimization work
308 This function can only provide a guess, but it seems to work for
309 gcc output. If it guesses wrong, the only loss should be in
310 efficiency; it shouldn't introduce any bugs.
312 I don't know if a fix is needed for the SVR4_PIC mode. I've only
313 fixed it for the non-PIC mode. KR 95/04/07 */
314 static int nopic_need_relax
PARAMS ((symbolS
*, int));
316 /* handle of the OPCODE hash table */
317 static struct hash_control
*op_hash
= NULL
;
319 /* The opcode hash table we use for the mips16. */
320 static struct hash_control
*mips16_op_hash
= NULL
;
322 /* This array holds the chars that always start a comment. If the
323 pre-processor is disabled, these aren't very useful */
324 const char comment_chars
[] = "#";
326 /* This array holds the chars that only start a comment at the beginning of
327 a line. If the line seems to have the form '# 123 filename'
328 .line and .file directives will appear in the pre-processed output */
329 /* Note that input_file.c hand checks for '#' at the beginning of the
330 first line of the input file. This is because the compiler outputs
331 #NO_APP at the beginning of its output. */
332 /* Also note that C style comments are always supported. */
333 const char line_comment_chars
[] = "#";
335 /* This array holds machine specific line separator characters. */
336 const char line_separator_chars
[] = "";
338 /* Chars that can be used to separate mant from exp in floating point nums */
339 const char EXP_CHARS
[] = "eE";
341 /* Chars that mean this number is a floating point constant */
344 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
346 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
347 changed in read.c . Ideally it shouldn't have to know about it at all,
348 but nothing is ideal around here.
351 static char *insn_error
;
353 static int auto_align
= 1;
355 /* When outputting SVR4 PIC code, the assembler needs to know the
356 offset in the stack frame from which to restore the $gp register.
357 This is set by the .cprestore pseudo-op, and saved in this
359 static offsetT mips_cprestore_offset
= -1;
361 /* This is the register which holds the stack frame, as set by the
362 .frame pseudo-op. This is needed to implement .cprestore. */
363 static int mips_frame_reg
= SP
;
365 /* To output NOP instructions correctly, we need to keep information
366 about the previous two instructions. */
368 /* Whether we are optimizing. The default value of 2 means to remove
369 unneeded NOPs and swap branch instructions when possible. A value
370 of 1 means to not swap branches. A value of 0 means to always
372 static int mips_optimize
= 2;
374 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
375 equivalent to seeing no -g option at all. */
376 static int mips_debug
= 0;
378 /* The previous instruction. */
379 static struct mips_cl_insn prev_insn
;
381 /* The instruction before prev_insn. */
382 static struct mips_cl_insn prev_prev_insn
;
384 /* If we don't want information for prev_insn or prev_prev_insn, we
385 point the insn_mo field at this dummy integer. */
386 static const struct mips_opcode dummy_opcode
= { 0 };
388 /* Non-zero if prev_insn is valid. */
389 static int prev_insn_valid
;
391 /* The frag for the previous instruction. */
392 static struct frag
*prev_insn_frag
;
394 /* The offset into prev_insn_frag for the previous instruction. */
395 static long prev_insn_where
;
397 /* The reloc type for the previous instruction, if any. */
398 static bfd_reloc_code_real_type prev_insn_reloc_type
;
400 /* The reloc for the previous instruction, if any. */
401 static fixS
*prev_insn_fixp
;
403 /* Non-zero if the previous instruction was in a delay slot. */
404 static int prev_insn_is_delay_slot
;
406 /* Non-zero if the previous instruction was in a .set noreorder. */
407 static int prev_insn_unreordered
;
409 /* Non-zero if the previous instruction uses an extend opcode (if
411 static int prev_insn_extended
;
413 /* Non-zero if the previous previous instruction was in a .set
415 static int prev_prev_insn_unreordered
;
417 /* If this is set, it points to a frag holding nop instructions which
418 were inserted before the start of a noreorder section. If those
419 nops turn out to be unnecessary, the size of the frag can be
421 static fragS
*prev_nop_frag
;
423 /* The number of nop instructions we created in prev_nop_frag. */
424 static int prev_nop_frag_holds
;
426 /* The number of nop instructions that we know we need in
428 static int prev_nop_frag_required
;
430 /* The number of instructions we've seen since prev_nop_frag. */
431 static int prev_nop_frag_since
;
433 /* For ECOFF and ELF, relocations against symbols are done in two
434 parts, with a HI relocation and a LO relocation. Each relocation
435 has only 16 bits of space to store an addend. This means that in
436 order for the linker to handle carries correctly, it must be able
437 to locate both the HI and the LO relocation. This means that the
438 relocations must appear in order in the relocation table.
440 In order to implement this, we keep track of each unmatched HI
441 relocation. We then sort them so that they immediately precede the
442 corresponding LO relocation. */
447 struct mips_hi_fixup
*next
;
450 /* The section this fixup is in. */
454 /* The list of unmatched HI relocs. */
456 static struct mips_hi_fixup
*mips_hi_fixup_list
;
458 /* Map normal MIPS register numbers to mips16 register numbers. */
460 #define X ILLEGAL_REG
461 static const int mips32_to_16_reg_map
[] =
463 X
, X
, 2, 3, 4, 5, 6, 7,
464 X
, X
, X
, X
, X
, X
, X
, X
,
465 0, 1, X
, X
, X
, X
, X
, X
,
466 X
, X
, X
, X
, X
, X
, X
, X
470 /* Map mips16 register numbers to normal MIPS register numbers. */
472 static const int mips16_to_32_reg_map
[] =
474 16, 17, 2, 3, 4, 5, 6, 7
477 /* Since the MIPS does not have multiple forms of PC relative
478 instructions, we do not have to do relaxing as is done on other
479 platforms. However, we do have to handle GP relative addressing
480 correctly, which turns out to be a similar problem.
482 Every macro that refers to a symbol can occur in (at least) two
483 forms, one with GP relative addressing and one without. For
484 example, loading a global variable into a register generally uses
485 a macro instruction like this:
487 If i can be addressed off the GP register (this is true if it is in
488 the .sbss or .sdata section, or if it is known to be smaller than
489 the -G argument) this will generate the following instruction:
491 This instruction will use a GPREL reloc. If i can not be addressed
492 off the GP register, the following instruction sequence will be used:
495 In this case the first instruction will have a HI16 reloc, and the
496 second reloc will have a LO16 reloc. Both relocs will be against
499 The issue here is that we may not know whether i is GP addressable
500 until after we see the instruction that uses it. Therefore, we
501 want to be able to choose the final instruction sequence only at
502 the end of the assembly. This is similar to the way other
503 platforms choose the size of a PC relative instruction only at the
506 When generating position independent code we do not use GP
507 addressing in quite the same way, but the issue still arises as
508 external symbols and local symbols must be handled differently.
510 We handle these issues by actually generating both possible
511 instruction sequences. The longer one is put in a frag_var with
512 type rs_machine_dependent. We encode what to do with the frag in
513 the subtype field. We encode (1) the number of existing bytes to
514 replace, (2) the number of new bytes to use, (3) the offset from
515 the start of the existing bytes to the first reloc we must generate
516 (that is, the offset is applied from the start of the existing
517 bytes after they are replaced by the new bytes, if any), (4) the
518 offset from the start of the existing bytes to the second reloc,
519 (5) whether a third reloc is needed (the third reloc is always four
520 bytes after the second reloc), and (6) whether to warn if this
521 variant is used (this is sometimes needed if .set nomacro or .set
522 noat is in effect). All these numbers are reasonably small.
524 Generating two instruction sequences must be handled carefully to
525 ensure that delay slots are handled correctly. Fortunately, there
526 are a limited number of cases. When the second instruction
527 sequence is generated, append_insn is directed to maintain the
528 existing delay slot information, so it continues to apply to any
529 code after the second instruction sequence. This means that the
530 second instruction sequence must not impose any requirements not
531 required by the first instruction sequence.
533 These variant frags are then handled in functions called by the
534 machine independent code. md_estimate_size_before_relax returns
535 the final size of the frag. md_convert_frag sets up the final form
536 of the frag. tc_gen_reloc adjust the first reloc and adds a second
538 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
542 | (((reloc1) + 64) << 9) \
543 | (((reloc2) + 64) << 2) \
544 | ((reloc3) ? (1 << 1) : 0) \
546 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
547 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
548 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
549 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
550 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
551 #define RELAX_WARN(i) ((i) & 1)
553 /* For mips16 code, we use an entirely different form of relaxation.
554 mips16 supports two versions of most instructions which take
555 immediate values: a small one which takes some small value, and a
556 larger one which takes a 16 bit value. Since branches also follow
557 this pattern, relaxing these values is required.
559 We can assemble both mips16 and normal MIPS code in a single
560 object. Therefore, we need to support this type of relaxation at
561 the same time that we support the relaxation described above. We
562 use the high bit of the subtype field to distinguish these cases.
564 The information we store for this type of relaxation is the
565 argument code found in the opcode file for this relocation, whether
566 the user explicitly requested a small or extended form, and whether
567 the relocation is in a jump or jal delay slot. That tells us the
568 size of the value, and how it should be stored. We also store
569 whether the fragment is considered to be extended or not. We also
570 store whether this is known to be a branch to a different section,
571 whether we have tried to relax this frag yet, and whether we have
572 ever extended a PC relative fragment because of a shift count. */
573 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
576 | ((small) ? 0x100 : 0) \
577 | ((ext) ? 0x200 : 0) \
578 | ((dslot) ? 0x400 : 0) \
579 | ((jal_dslot) ? 0x800 : 0))
580 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
581 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
582 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
583 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
584 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
585 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
586 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
587 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
588 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
589 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
590 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
591 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
593 /* Prototypes for static functions. */
596 #define internalError() \
597 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
599 #define internalError() as_fatal ("MIPS internal Error");
602 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
604 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
605 unsigned int reg
, enum mips_regclass
class));
606 static int reg_needs_delay
PARAMS ((int));
607 static void mips16_mark_labels
PARAMS ((void));
608 static void append_insn
PARAMS ((char *place
,
609 struct mips_cl_insn
* ip
,
611 bfd_reloc_code_real_type r
,
613 static void mips_no_prev_insn
PARAMS ((int));
614 static void mips_emit_delays
PARAMS ((boolean
));
616 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
617 const char *name
, const char *fmt
,
620 static void macro_build ();
622 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
623 const char *, const char *,
625 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
626 expressionS
* ep
, int regnum
));
627 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
628 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
630 static void load_register
PARAMS ((int *, int, expressionS
*, int));
631 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
632 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
633 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
634 #ifdef LOSING_COMPILER
635 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
637 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
638 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
639 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
640 boolean
, boolean
, unsigned long *,
641 boolean
*, unsigned short *));
642 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
643 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
644 static symbolS
*get_symbol
PARAMS ((void));
645 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
646 static void s_align
PARAMS ((int));
647 static void s_change_sec
PARAMS ((int));
648 static void s_cons
PARAMS ((int));
649 static void s_float_cons
PARAMS ((int));
650 static void s_mips_globl
PARAMS ((int));
651 static void s_option
PARAMS ((int));
652 static void s_mipsset
PARAMS ((int));
653 static void s_abicalls
PARAMS ((int));
654 static void s_cpload
PARAMS ((int));
655 static void s_cprestore
PARAMS ((int));
656 static void s_gpword
PARAMS ((int));
657 static void s_cpadd
PARAMS ((int));
658 static void s_insn
PARAMS ((int));
659 static void md_obj_begin
PARAMS ((void));
660 static void md_obj_end
PARAMS ((void));
661 static long get_number
PARAMS ((void));
662 static void s_ent
PARAMS ((int));
663 static void s_mipsend
PARAMS ((int));
664 static void s_file
PARAMS ((int));
665 static void s_mips_stab
PARAMS ((int));
666 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
668 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
672 The following pseudo-ops from the Kane and Heinrich MIPS book
673 should be defined here, but are currently unsupported: .alias,
674 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
676 The following pseudo-ops from the Kane and Heinrich MIPS book are
677 specific to the type of debugging information being generated, and
678 should be defined by the object format: .aent, .begin, .bend,
679 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
682 The following pseudo-ops from the Kane and Heinrich MIPS book are
683 not MIPS CPU specific, but are also not specific to the object file
684 format. This file is probably the best place to define them, but
685 they are not currently supported: .asm0, .endr, .lab, .repeat,
686 .struct, .weakext. */
688 static const pseudo_typeS mips_pseudo_table
[] =
690 /* MIPS specific pseudo-ops. */
691 {"option", s_option
, 0},
692 {"set", s_mipsset
, 0},
693 {"rdata", s_change_sec
, 'r'},
694 {"sdata", s_change_sec
, 's'},
695 {"livereg", s_ignore
, 0},
696 {"abicalls", s_abicalls
, 0},
697 {"cpload", s_cpload
, 0},
698 {"cprestore", s_cprestore
, 0},
699 {"gpword", s_gpword
, 0},
700 {"cpadd", s_cpadd
, 0},
703 /* Relatively generic pseudo-ops that happen to be used on MIPS
705 {"asciiz", stringer
, 1},
706 {"bss", s_change_sec
, 'b'},
709 {"dword", s_cons
, 3},
711 /* These pseudo-ops are defined in read.c, but must be overridden
712 here for one reason or another. */
713 {"align", s_align
, 0},
715 {"data", s_change_sec
, 'd'},
716 {"double", s_float_cons
, 'd'},
717 {"float", s_float_cons
, 'f'},
718 {"globl", s_mips_globl
, 0},
719 {"global", s_mips_globl
, 0},
720 {"hword", s_cons
, 1},
725 {"short", s_cons
, 1},
726 {"single", s_float_cons
, 'f'},
727 {"stabn", s_mips_stab
, 'n'},
728 {"text", s_change_sec
, 't'},
733 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
734 /* These pseudo-ops should be defined by the object file format.
735 However, a.out doesn't support them, so we have versions here. */
737 {"bgnb", s_ignore
, 0},
738 {"end", s_mipsend
, 0},
739 {"endb", s_ignore
, 0},
742 {"fmask", s_ignore
, 'F'},
743 {"frame", s_ignore
, 0},
744 {"loc", s_ignore
, 0},
745 {"mask", s_ignore
, 'R'},
746 {"verstamp", s_ignore
, 0},
750 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
755 pop_insert (mips_pseudo_table
);
756 if (! ECOFF_DEBUGGING
)
757 pop_insert (mips_nonecoff_pseudo_table
);
760 /* Symbols labelling the current insn. */
762 struct insn_label_list
764 struct insn_label_list
*next
;
768 static struct insn_label_list
*insn_labels
;
769 static struct insn_label_list
*free_insn_labels
;
771 static void mips_clear_insn_labels
PARAMS ((void));
774 mips_clear_insn_labels ()
776 register struct insn_label_list
**pl
;
778 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
784 static char *expr_end
;
786 /* Expressions which appear in instructions. These are set by
789 static expressionS imm_expr
;
790 static expressionS offset_expr
;
792 /* Relocs associated with imm_expr and offset_expr. */
794 static bfd_reloc_code_real_type imm_reloc
;
795 static bfd_reloc_code_real_type offset_reloc
;
797 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
799 static boolean imm_unmatched_hi
;
801 /* These are set by mips16_ip if an explicit extension is used. */
803 static boolean mips16_small
, mips16_ext
;
806 * This function is called once, at assembler startup time. It should
807 * set up all the tables, etc. that the MD part of the assembler will need.
813 register const char *retval
= NULL
;
814 register unsigned int i
= 0;
820 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
822 a
= xmalloc (sizeof TARGET_CPU
);
823 strcpy (a
, TARGET_CPU
);
824 a
[(sizeof TARGET_CPU
) - 3] = '\0';
830 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
831 just the generic 'mips', in which case set mips_cpu based
832 on the given ISA, if any. */
834 if (strcmp (cpu
, "mips") == 0)
836 if (mips_opts
.isa
< 0)
839 else if (mips_opts
.isa
== 2)
842 else if (mips_opts
.isa
== 3)
845 else if (mips_opts
.isa
== 4)
852 else if (strcmp (cpu
, "r3900") == 0
853 || strcmp (cpu
, "mipstx39") == 0
854 /* start-sanitize-tx19 */
855 || strcmp (cpu
, "r1900") == 0
856 || strcmp (cpu
, "mipstx19") == 0
857 /* end-sanitize-tx19 */
861 else if (strcmp (cpu
, "r6000") == 0
862 || strcmp (cpu
, "mips2") == 0)
865 else if (strcmp (cpu
, "mips64") == 0
866 || strcmp (cpu
, "r4000") == 0
867 || strcmp (cpu
, "mips3") == 0)
870 else if (strcmp (cpu
, "r4400") == 0)
873 else if (strcmp (cpu
, "mips64orion") == 0
874 || strcmp (cpu
, "r4600") == 0)
877 else if (strcmp (cpu
, "r4650") == 0)
880 else if (strcmp (cpu
, "mips64vr4300") == 0)
883 else if (strcmp (cpu
, "mips64vr4100") == 0)
886 else if (strcmp (cpu
, "r4010") == 0)
889 /* start-sanitize-tx49 */
890 else if (strcmp (cpu
, "mips64tx49") == 0)
892 /* end-sanitize-tx49 */
894 else if (strcmp (cpu
, "r5000") == 0
895 || strcmp (cpu
, "mips64vr5000") == 0)
898 /* start-sanitize-vr5400 */
899 else if (strcmp (cpu
, "r5400") == 0
900 || strcmp (cpu
, "mips64vr5400") == 0)
902 /* end-sanitize-vr5400 */
904 /* start-sanitize-r5900 */
905 else if (strcmp (cpu
, "r5900") == 0
906 || strcmp (cpu
, "mips64r5900") == 0)
908 /* end-sanitize-r5900 */
910 else if (strcmp (cpu
, "r8000") == 0
911 || strcmp (cpu
, "mips4") == 0)
914 else if (strcmp (cpu
, "r10000") == 0)
917 else if (strcmp (cpu
, "mips16") == 0)
918 mips_cpu
= 0; /* FIXME */
924 if (mips_opts
.isa
== -1)
930 else if (mips_cpu
== 6000
934 else if (mips_cpu
== 4000
939 /* start-sanitize-tx49 */
941 /* end-sanitize-tx49 */
942 /* start-sanitize-r5900 */
944 /* end-sanitize-r5900 */
948 else if (mips_cpu
== 5000
949 /* start-sanitize-vr5400 */
951 /* end-sanitize-vr5400 */
953 || mips_cpu
== 10000)
960 if (mips_opts
.mips16
< 0)
962 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
963 mips_opts
.mips16
= 1;
965 mips_opts
.mips16
= 0;
969 mips_4650
= (mips_cpu
== 4650);
972 mips_4010
= (mips_cpu
== 4010);
975 mips_4100
= (mips_cpu
== 4100);
977 /* start-sanitize-vr5400 */
979 mips_5400
= (mips_cpu
== 5400);
980 /* end-sanitize-vr5400 */
982 /* start-sanitize-r5900 */
984 mips_5900
= (mips_cpu
== 5900);
985 /* end-sanitize-r5900 */
988 mips_3900
= (mips_cpu
== 3900);
990 /* start-sanitize-tx49 */
992 mips_4900
= (mips_cpu
== 4900);
994 /* end-sanitize-tx49 */
996 /* End of TARGET_CPU processing, get rid of malloced memory
1005 if (mips_opts
.isa
< 2 && mips_trap
)
1006 as_bad ("trap exception not supported at ISA 1");
1008 switch (mips_opts
.isa
)
1011 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1014 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1017 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1020 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1024 as_warn ("Could not set architecture and machine");
1026 file_mips_isa
= mips_opts
.isa
;
1028 op_hash
= hash_new ();
1030 for (i
= 0; i
< NUMOPCODES
;)
1032 const char *name
= mips_opcodes
[i
].name
;
1034 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1037 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
1038 mips_opcodes
[i
].name
, retval
);
1039 /* Probably a memory allocation problem? Give up now. */
1040 as_fatal ("Broken assembler. No assembly attempted.");
1044 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1046 if (!validate_mips_insn (&mips_opcodes
[i
]))
1051 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1054 mips16_op_hash
= hash_new ();
1057 while (i
< bfd_mips16_num_opcodes
)
1059 const char *name
= mips16_opcodes
[i
].name
;
1061 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1063 as_fatal ("internal: can't hash `%s': %s",
1064 mips16_opcodes
[i
].name
, retval
);
1067 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1068 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1069 != mips16_opcodes
[i
].match
))
1071 fprintf (stderr
, "internal error: bad mips16 opcode: %s %s\n",
1072 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1077 while (i
< bfd_mips16_num_opcodes
1078 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1082 as_fatal ("Broken assembler. No assembly attempted.");
1084 /* We add all the general register names to the symbol table. This
1085 helps us detect invalid uses of them. */
1086 for (i
= 0; i
< 32; i
++)
1090 sprintf (buf
, "$%d", i
);
1091 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1092 &zero_address_frag
));
1094 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1095 &zero_address_frag
));
1096 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1097 &zero_address_frag
));
1098 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1099 &zero_address_frag
));
1100 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1101 &zero_address_frag
));
1102 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1103 &zero_address_frag
));
1104 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1105 &zero_address_frag
));
1106 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1107 &zero_address_frag
));
1109 mips_no_prev_insn (false);
1112 mips_cprmask
[0] = 0;
1113 mips_cprmask
[1] = 0;
1114 mips_cprmask
[2] = 0;
1115 mips_cprmask
[3] = 0;
1117 /* set the default alignment for the text section (2**2) */
1118 record_alignment (text_section
, 2);
1120 if (USE_GLOBAL_POINTER_OPT
)
1121 bfd_set_gp_size (stdoutput
, g_switch_value
);
1123 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1125 /* On a native system, sections must be aligned to 16 byte
1126 boundaries. When configured for an embedded ELF target, we
1128 if (strcmp (TARGET_OS
, "elf") != 0)
1130 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1131 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1132 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1135 /* Create a .reginfo section for register masks and a .mdebug
1136 section for debugging information. */
1144 subseg
= now_subseg
;
1146 /* The ABI says this section should be loaded so that the
1147 running program can access it. However, we don't load it
1148 if we are configured for an embedded target */
1149 flags
= SEC_READONLY
| SEC_DATA
;
1150 if (strcmp (TARGET_OS
, "elf") != 0)
1151 flags
|= SEC_ALLOC
| SEC_LOAD
;
1155 sec
= subseg_new (".reginfo", (subsegT
) 0);
1158 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1159 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1162 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1167 /* The 64-bit ABI uses a .MIPS.options section rather than
1168 .reginfo section. */
1169 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1170 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1171 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1174 /* Set up the option header. */
1176 Elf_Internal_Options opthdr
;
1179 opthdr
.kind
= ODK_REGINFO
;
1180 opthdr
.size
= (sizeof (Elf_External_Options
)
1181 + sizeof (Elf64_External_RegInfo
));
1184 f
= frag_more (sizeof (Elf_External_Options
));
1185 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1186 (Elf_External_Options
*) f
);
1188 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1193 if (ECOFF_DEBUGGING
)
1195 sec
= subseg_new (".mdebug", (subsegT
) 0);
1196 (void) bfd_set_section_flags (stdoutput
, sec
,
1197 SEC_HAS_CONTENTS
| SEC_READONLY
);
1198 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1201 subseg_set (seg
, subseg
);
1205 if (! ECOFF_DEBUGGING
)
1212 if (! ECOFF_DEBUGGING
)
1220 struct mips_cl_insn insn
;
1222 imm_expr
.X_op
= O_absent
;
1223 imm_reloc
= BFD_RELOC_UNUSED
;
1224 imm_unmatched_hi
= false;
1225 offset_expr
.X_op
= O_absent
;
1226 offset_reloc
= BFD_RELOC_UNUSED
;
1228 if (mips_opts
.mips16
)
1229 mips16_ip (str
, &insn
);
1232 mips_ip (str
, &insn
);
1233 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1234 str
, insn
.insn_opcode
));
1239 as_bad ("%s `%s'", insn_error
, str
);
1243 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1245 if (mips_opts
.mips16
)
1246 mips16_macro (&insn
);
1252 if (imm_expr
.X_op
!= O_absent
)
1253 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1255 else if (offset_expr
.X_op
!= O_absent
)
1256 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1258 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1262 /* See whether instruction IP reads register REG. CLASS is the type
1266 insn_uses_reg (ip
, reg
, class)
1267 struct mips_cl_insn
*ip
;
1269 enum mips_regclass
class;
1271 if (class == MIPS16_REG
)
1273 assert (mips_opts
.mips16
);
1274 reg
= mips16_to_32_reg_map
[reg
];
1275 class = MIPS_GR_REG
;
1278 /* Don't report on general register 0, since it never changes. */
1279 if (class == MIPS_GR_REG
&& reg
== 0)
1282 if (class == MIPS_FP_REG
)
1284 assert (! mips_opts
.mips16
);
1285 /* If we are called with either $f0 or $f1, we must check $f0.
1286 This is not optimal, because it will introduce an unnecessary
1287 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1288 need to distinguish reading both $f0 and $f1 or just one of
1289 them. Note that we don't have to check the other way,
1290 because there is no instruction that sets both $f0 and $f1
1291 and requires a delay. */
1292 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1293 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1294 == (reg
&~ (unsigned) 1)))
1296 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1297 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1298 == (reg
&~ (unsigned) 1)))
1301 else if (! mips_opts
.mips16
)
1303 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1304 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1306 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1307 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1312 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1313 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1314 & MIPS16OP_MASK_RX
)]
1317 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1318 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1319 & MIPS16OP_MASK_RY
)]
1322 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1323 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1324 & MIPS16OP_MASK_MOVE32Z
)]
1327 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1329 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1331 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1333 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1334 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1335 & MIPS16OP_MASK_REGR32
) == reg
)
1342 /* This function returns true if modifying a register requires a
1346 reg_needs_delay (reg
)
1349 unsigned long prev_pinfo
;
1351 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1352 if (! mips_opts
.noreorder
1353 && mips_opts
.isa
< 4
1354 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1355 || (! gpr_interlocks
1356 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1358 /* A load from a coprocessor or from memory. All load
1359 delays delay the use of general register rt for one
1360 instruction on the r3000. The r6000 and r4000 use
1362 /* Itbl support may require additional care here. */
1363 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1364 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1371 /* Mark instruction labels in mips16 mode. This permits the linker to
1372 handle them specially, such as generating jalx instructions when
1373 needed. We also make them odd for the duration of the assembly, in
1374 order to generate the right sort of code. We will make them even
1375 in the adjust_symtab routine, while leaving them marked. This is
1376 convenient for the debugger and the disassembler. The linker knows
1377 to make them odd again. */
1380 mips16_mark_labels ()
1382 if (mips_opts
.mips16
)
1384 struct insn_label_list
*l
;
1386 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1389 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1390 S_SET_OTHER (l
->label
, STO_MIPS16
);
1392 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1393 ++l
->label
->sy_value
.X_add_number
;
1398 /* Output an instruction. PLACE is where to put the instruction; if
1399 it is NULL, this uses frag_more to get room. IP is the instruction
1400 information. ADDRESS_EXPR is an operand of the instruction to be
1401 used with RELOC_TYPE. */
1404 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1406 struct mips_cl_insn
*ip
;
1407 expressionS
*address_expr
;
1408 bfd_reloc_code_real_type reloc_type
;
1409 boolean unmatched_hi
;
1411 register unsigned long prev_pinfo
, pinfo
;
1416 /* Mark instruction labels in mips16 mode. */
1417 if (mips_opts
.mips16
)
1418 mips16_mark_labels ();
1420 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1421 pinfo
= ip
->insn_mo
->pinfo
;
1423 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1427 /* If the previous insn required any delay slots, see if we need
1428 to insert a NOP or two. There are eight kinds of possible
1429 hazards, of which an instruction can have at most one type.
1430 (1) a load from memory delay
1431 (2) a load from a coprocessor delay
1432 (3) an unconditional branch delay
1433 (4) a conditional branch delay
1434 (5) a move to coprocessor register delay
1435 (6) a load coprocessor register from memory delay
1436 (7) a coprocessor condition code delay
1437 (8) a HI/LO special register delay
1439 There are a lot of optimizations we could do that we don't.
1440 In particular, we do not, in general, reorder instructions.
1441 If you use gcc with optimization, it will reorder
1442 instructions and generally do much more optimization then we
1443 do here; repeating all that work in the assembler would only
1444 benefit hand written assembly code, and does not seem worth
1447 /* This is how a NOP is emitted. */
1448 #define emit_nop() \
1450 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1451 : md_number_to_chars (frag_more (4), 0, 4))
1453 /* The previous insn might require a delay slot, depending upon
1454 the contents of the current insn. */
1455 if (! mips_opts
.mips16
1456 && mips_opts
.isa
< 4
1457 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1458 && ! cop_interlocks
)
1459 || (! gpr_interlocks
1460 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1462 /* A load from a coprocessor or from memory. All load
1463 delays delay the use of general register rt for one
1464 instruction on the r3000. The r6000 and r4000 use
1466 /* Itbl support may require additional care here. */
1467 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1468 if (mips_optimize
== 0
1469 || insn_uses_reg (ip
,
1470 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1475 else if (! mips_opts
.mips16
1476 && mips_opts
.isa
< 4
1477 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1478 && ! cop_interlocks
)
1479 || (mips_opts
.isa
< 2
1480 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1482 /* A generic coprocessor delay. The previous instruction
1483 modified a coprocessor general or control register. If
1484 it modified a control register, we need to avoid any
1485 coprocessor instruction (this is probably not always
1486 required, but it sometimes is). If it modified a general
1487 register, we avoid using that register.
1489 On the r6000 and r4000 loading a coprocessor register
1490 from memory is interlocked, and does not require a delay.
1492 This case is not handled very well. There is no special
1493 knowledge of CP0 handling, and the coprocessors other
1494 than the floating point unit are not distinguished at
1496 /* Itbl support may require additional care here. FIXME!
1497 Need to modify this to include knowledge about
1498 user specified delays! */
1499 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1501 if (mips_optimize
== 0
1502 || insn_uses_reg (ip
,
1503 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1508 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1510 if (mips_optimize
== 0
1511 || insn_uses_reg (ip
,
1512 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1519 /* We don't know exactly what the previous instruction
1520 does. If the current instruction uses a coprocessor
1521 register, we must insert a NOP. If previous
1522 instruction may set the condition codes, and the
1523 current instruction uses them, we must insert two
1525 /* Itbl support may require additional care here. */
1526 if (mips_optimize
== 0
1527 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1528 && (pinfo
& INSN_READ_COND_CODE
)))
1530 else if (pinfo
& INSN_COP
)
1534 else if (! mips_opts
.mips16
1535 && mips_opts
.isa
< 4
1536 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1537 && ! cop_interlocks
)
1539 /* The previous instruction sets the coprocessor condition
1540 codes, but does not require a general coprocessor delay
1541 (this means it is a floating point comparison
1542 instruction). If this instruction uses the condition
1543 codes, we need to insert a single NOP. */
1544 /* Itbl support may require additional care here. */
1545 if (mips_optimize
== 0
1546 || (pinfo
& INSN_READ_COND_CODE
))
1549 else if (prev_pinfo
& INSN_READ_LO
)
1551 /* The previous instruction reads the LO register; if the
1552 current instruction writes to the LO register, we must
1553 insert two NOPS. Some newer processors have interlocks. */
1554 if (! hilo_interlocks
1555 && (mips_optimize
== 0
1556 || (pinfo
& INSN_WRITE_LO
)))
1559 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1561 /* The previous instruction reads the HI register; if the
1562 current instruction writes to the HI register, we must
1563 insert a NOP. Some newer processors have interlocks. */
1564 if (! hilo_interlocks
1565 && (mips_optimize
== 0
1566 || (pinfo
& INSN_WRITE_HI
)))
1570 /* If the previous instruction was in a noreorder section, then
1571 we don't want to insert the nop after all. */
1572 /* Itbl support may require additional care here. */
1573 if (prev_insn_unreordered
)
1576 /* There are two cases which require two intervening
1577 instructions: 1) setting the condition codes using a move to
1578 coprocessor instruction which requires a general coprocessor
1579 delay and then reading the condition codes 2) reading the HI
1580 or LO register and then writing to it (except on processors
1581 which have interlocks). If we are not already emitting a NOP
1582 instruction, we must check for these cases compared to the
1583 instruction previous to the previous instruction. */
1584 if ((! mips_opts
.mips16
1585 && mips_opts
.isa
< 4
1586 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1587 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1588 && (pinfo
& INSN_READ_COND_CODE
)
1589 && ! cop_interlocks
)
1590 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1591 && (pinfo
& INSN_WRITE_LO
)
1592 && ! hilo_interlocks
)
1593 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1594 && (pinfo
& INSN_WRITE_HI
)
1595 && ! hilo_interlocks
))
1600 if (prev_prev_insn_unreordered
)
1603 if (prev_prev_nop
&& nops
== 0)
1606 /* If we are being given a nop instruction, don't bother with
1607 one of the nops we would otherwise output. This will only
1608 happen when a nop instruction is used with mips_optimize set
1611 && ! mips_opts
.noreorder
1612 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1615 /* Now emit the right number of NOP instructions. */
1616 if (nops
> 0 && ! mips_opts
.noreorder
)
1619 unsigned long old_frag_offset
;
1621 struct insn_label_list
*l
;
1623 old_frag
= frag_now
;
1624 old_frag_offset
= frag_now_fix ();
1626 for (i
= 0; i
< nops
; i
++)
1631 listing_prev_line ();
1632 /* We may be at the start of a variant frag. In case we
1633 are, make sure there is enough space for the frag
1634 after the frags created by listing_prev_line. The
1635 argument to frag_grow here must be at least as large
1636 as the argument to all other calls to frag_grow in
1637 this file. We don't have to worry about being in the
1638 middle of a variant frag, because the variants insert
1639 all needed nop instructions themselves. */
1643 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1645 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1646 l
->label
->sy_frag
= frag_now
;
1647 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1648 /* mips16 text labels are stored as odd. */
1649 if (mips_opts
.mips16
)
1650 ++l
->label
->sy_value
.X_add_number
;
1653 #ifndef NO_ECOFF_DEBUGGING
1654 if (ECOFF_DEBUGGING
)
1655 ecoff_fix_loc (old_frag
, old_frag_offset
);
1658 else if (prev_nop_frag
!= NULL
)
1660 /* We have a frag holding nops we may be able to remove. If
1661 we don't need any nops, we can decrease the size of
1662 prev_nop_frag by the size of one instruction. If we do
1663 need some nops, we count them in prev_nops_required. */
1664 if (prev_nop_frag_since
== 0)
1668 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1669 --prev_nop_frag_holds
;
1672 prev_nop_frag_required
+= nops
;
1676 if (prev_prev_nop
== 0)
1678 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1679 --prev_nop_frag_holds
;
1682 ++prev_nop_frag_required
;
1685 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1686 prev_nop_frag
= NULL
;
1688 ++prev_nop_frag_since
;
1690 /* Sanity check: by the time we reach the second instruction
1691 after prev_nop_frag, we should have used up all the nops
1692 one way or another. */
1693 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1697 if (reloc_type
> BFD_RELOC_UNUSED
)
1699 /* We need to set up a variant frag. */
1700 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1701 f
= frag_var (rs_machine_dependent
, 4, 0,
1702 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1703 mips16_small
, mips16_ext
,
1705 & INSN_UNCOND_BRANCH_DELAY
),
1706 (prev_insn_reloc_type
1707 == BFD_RELOC_MIPS16_JMP
)),
1708 make_expr_symbol (address_expr
), (offsetT
) 0,
1711 else if (place
!= NULL
)
1713 else if (mips_opts
.mips16
1715 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1717 /* Make sure there is enough room to swap this instruction with
1718 a following jump instruction. */
1724 if (mips_opts
.mips16
1725 && mips_opts
.noreorder
1726 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1727 as_warn ("extended instruction in delay slot");
1733 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1735 if (address_expr
->X_op
== O_constant
)
1740 ip
->insn_opcode
|= address_expr
->X_add_number
;
1743 case BFD_RELOC_LO16
:
1744 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1747 case BFD_RELOC_MIPS_JMP
:
1748 if ((address_expr
->X_add_number
& 3) != 0)
1749 as_bad ("jump to misaligned address (0x%lx)",
1750 (unsigned long) address_expr
->X_add_number
);
1751 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1754 case BFD_RELOC_MIPS16_JMP
:
1755 if ((address_expr
->X_add_number
& 3) != 0)
1756 as_bad ("jump to misaligned address (0x%lx)",
1757 (unsigned long) address_expr
->X_add_number
);
1759 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1760 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1761 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1764 case BFD_RELOC_16_PCREL_S2
:
1774 /* Don't generate a reloc if we are writing into a variant
1778 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1780 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1784 struct mips_hi_fixup
*hi_fixup
;
1786 assert (reloc_type
== BFD_RELOC_HI16_S
);
1787 hi_fixup
= ((struct mips_hi_fixup
*)
1788 xmalloc (sizeof (struct mips_hi_fixup
)));
1789 hi_fixup
->fixp
= fixp
;
1790 hi_fixup
->seg
= now_seg
;
1791 hi_fixup
->next
= mips_hi_fixup_list
;
1792 mips_hi_fixup_list
= hi_fixup
;
1798 if (! mips_opts
.mips16
)
1799 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1800 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1802 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1803 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1809 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1812 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1815 /* Update the register mask information. */
1816 if (! mips_opts
.mips16
)
1818 if (pinfo
& INSN_WRITE_GPR_D
)
1819 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1820 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1821 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1822 if (pinfo
& INSN_READ_GPR_S
)
1823 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1824 if (pinfo
& INSN_WRITE_GPR_31
)
1825 mips_gprmask
|= 1 << 31;
1826 if (pinfo
& INSN_WRITE_FPR_D
)
1827 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1828 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1829 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1830 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1831 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1832 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1833 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1834 if (pinfo
& INSN_COP
)
1836 /* We don't keep enough information to sort these cases out.
1837 The itbl support does keep this information however, although
1838 we currently don't support itbl fprmats as part of the cop
1839 instruction. May want to add this support in the future. */
1841 /* Never set the bit for $0, which is always zero. */
1842 mips_gprmask
&=~ 1 << 0;
1846 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1847 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1848 & MIPS16OP_MASK_RX
);
1849 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1850 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1851 & MIPS16OP_MASK_RY
);
1852 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1853 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1854 & MIPS16OP_MASK_RZ
);
1855 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1856 mips_gprmask
|= 1 << TREG
;
1857 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1858 mips_gprmask
|= 1 << SP
;
1859 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1860 mips_gprmask
|= 1 << RA
;
1861 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1862 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1863 if (pinfo
& MIPS16_INSN_READ_Z
)
1864 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1865 & MIPS16OP_MASK_MOVE32Z
);
1866 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1867 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1868 & MIPS16OP_MASK_REGR32
);
1871 if (place
== NULL
&& ! mips_opts
.noreorder
)
1873 /* Filling the branch delay slot is more complex. We try to
1874 switch the branch with the previous instruction, which we can
1875 do if the previous instruction does not set up a condition
1876 that the branch tests and if the branch is not itself the
1877 target of any branch. */
1878 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1879 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1881 if (mips_optimize
< 2
1882 /* If we have seen .set volatile or .set nomove, don't
1884 || mips_opts
.nomove
!= 0
1885 /* If we had to emit any NOP instructions, then we
1886 already know we can not swap. */
1888 /* If we don't even know the previous insn, we can not
1890 || ! prev_insn_valid
1891 /* If the previous insn is already in a branch delay
1892 slot, then we can not swap. */
1893 || prev_insn_is_delay_slot
1894 /* If the previous previous insn was in a .set
1895 noreorder, we can't swap. Actually, the MIPS
1896 assembler will swap in this situation. However, gcc
1897 configured -with-gnu-as will generate code like
1903 in which we can not swap the bne and INSN. If gcc is
1904 not configured -with-gnu-as, it does not output the
1905 .set pseudo-ops. We don't have to check
1906 prev_insn_unreordered, because prev_insn_valid will
1907 be 0 in that case. We don't want to use
1908 prev_prev_insn_valid, because we do want to be able
1909 to swap at the start of a function. */
1910 || prev_prev_insn_unreordered
1911 /* If the branch is itself the target of a branch, we
1912 can not swap. We cheat on this; all we check for is
1913 whether there is a label on this instruction. If
1914 there are any branches to anything other than a
1915 label, users must use .set noreorder. */
1916 || insn_labels
!= NULL
1917 /* If the previous instruction is in a variant frag, we
1918 can not do the swap. This does not apply to the
1919 mips16, which uses variant frags for different
1921 || (! mips_opts
.mips16
1922 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1923 /* If the branch reads the condition codes, we don't
1924 even try to swap, because in the sequence
1929 we can not swap, and I don't feel like handling that
1931 || (! mips_opts
.mips16
1932 && mips_opts
.isa
< 4
1933 && (pinfo
& INSN_READ_COND_CODE
))
1934 /* We can not swap with an instruction that requires a
1935 delay slot, becase the target of the branch might
1936 interfere with that instruction. */
1937 || (! mips_opts
.mips16
1938 && mips_opts
.isa
< 4
1940 /* Itbl support may require additional care here. */
1941 & (INSN_LOAD_COPROC_DELAY
1942 | INSN_COPROC_MOVE_DELAY
1943 | INSN_WRITE_COND_CODE
)))
1944 || (! hilo_interlocks
1948 || (! mips_opts
.mips16
1950 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1951 || (! mips_opts
.mips16
1952 && mips_opts
.isa
< 2
1953 /* Itbl support may require additional care here. */
1954 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1955 /* We can not swap with a branch instruction. */
1957 & (INSN_UNCOND_BRANCH_DELAY
1958 | INSN_COND_BRANCH_DELAY
1959 | INSN_COND_BRANCH_LIKELY
))
1960 /* We do not swap with a trap instruction, since it
1961 complicates trap handlers to have the trap
1962 instruction be in a delay slot. */
1963 || (prev_pinfo
& INSN_TRAP
)
1964 /* If the branch reads a register that the previous
1965 instruction sets, we can not swap. */
1966 || (! mips_opts
.mips16
1967 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1968 && insn_uses_reg (ip
,
1969 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1972 || (! mips_opts
.mips16
1973 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1974 && insn_uses_reg (ip
,
1975 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1978 || (mips_opts
.mips16
1979 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1980 && insn_uses_reg (ip
,
1981 ((prev_insn
.insn_opcode
1983 & MIPS16OP_MASK_RX
),
1985 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1986 && insn_uses_reg (ip
,
1987 ((prev_insn
.insn_opcode
1989 & MIPS16OP_MASK_RY
),
1991 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1992 && insn_uses_reg (ip
,
1993 ((prev_insn
.insn_opcode
1995 & MIPS16OP_MASK_RZ
),
1997 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1998 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1999 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2000 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2001 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2002 && insn_uses_reg (ip
,
2003 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2006 /* If the branch writes a register that the previous
2007 instruction sets, we can not swap (we know that
2008 branches write only to RD or to $31). */
2009 || (! mips_opts
.mips16
2010 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2011 && (((pinfo
& INSN_WRITE_GPR_D
)
2012 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2013 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2014 || ((pinfo
& INSN_WRITE_GPR_31
)
2015 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2018 || (! mips_opts
.mips16
2019 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2020 && (((pinfo
& INSN_WRITE_GPR_D
)
2021 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2022 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2023 || ((pinfo
& INSN_WRITE_GPR_31
)
2024 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2027 || (mips_opts
.mips16
2028 && (pinfo
& MIPS16_INSN_WRITE_31
)
2029 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2030 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2031 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2033 /* If the branch writes a register that the previous
2034 instruction reads, we can not swap (we know that
2035 branches only write to RD or to $31). */
2036 || (! mips_opts
.mips16
2037 && (pinfo
& INSN_WRITE_GPR_D
)
2038 && insn_uses_reg (&prev_insn
,
2039 ((ip
->insn_opcode
>> OP_SH_RD
)
2042 || (! mips_opts
.mips16
2043 && (pinfo
& INSN_WRITE_GPR_31
)
2044 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2045 || (mips_opts
.mips16
2046 && (pinfo
& MIPS16_INSN_WRITE_31
)
2047 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2048 /* If we are generating embedded PIC code, the branch
2049 might be expanded into a sequence which uses $at, so
2050 we can't swap with an instruction which reads it. */
2051 || (mips_pic
== EMBEDDED_PIC
2052 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2053 /* If the previous previous instruction has a load
2054 delay, and sets a register that the branch reads, we
2056 || (! mips_opts
.mips16
2057 && mips_opts
.isa
< 4
2058 /* Itbl support may require additional care here. */
2059 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2060 || (! gpr_interlocks
2061 && (prev_prev_insn
.insn_mo
->pinfo
2062 & INSN_LOAD_MEMORY_DELAY
)))
2063 && insn_uses_reg (ip
,
2064 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2067 /* If one instruction sets a condition code and the
2068 other one uses a condition code, we can not swap. */
2069 || ((pinfo
& INSN_READ_COND_CODE
)
2070 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2071 || ((pinfo
& INSN_WRITE_COND_CODE
)
2072 && (prev_pinfo
& INSN_READ_COND_CODE
))
2073 /* If the previous instruction uses the PC, we can not
2075 || (mips_opts
.mips16
2076 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2077 /* If the previous instruction was extended, we can not
2079 || (mips_opts
.mips16
&& prev_insn_extended
)
2080 /* If the previous instruction had a fixup in mips16
2081 mode, we can not swap. This normally means that the
2082 previous instruction was a 4 byte branch anyhow. */
2083 || (mips_opts
.mips16
&& prev_insn_fixp
))
2085 /* We could do even better for unconditional branches to
2086 portions of this object file; we could pick up the
2087 instruction at the destination, put it in the delay
2088 slot, and bump the destination address. */
2090 /* Update the previous insn information. */
2091 prev_prev_insn
= *ip
;
2092 prev_insn
.insn_mo
= &dummy_opcode
;
2096 /* It looks like we can actually do the swap. */
2097 if (! mips_opts
.mips16
)
2102 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2103 memcpy (temp
, prev_f
, 4);
2104 memcpy (prev_f
, f
, 4);
2105 memcpy (f
, temp
, 4);
2108 prev_insn_fixp
->fx_frag
= frag_now
;
2109 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2113 fixp
->fx_frag
= prev_insn_frag
;
2114 fixp
->fx_where
= prev_insn_where
;
2122 assert (prev_insn_fixp
== NULL
);
2123 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2124 memcpy (temp
, prev_f
, 2);
2125 memcpy (prev_f
, f
, 2);
2126 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2128 assert (reloc_type
== BFD_RELOC_UNUSED
);
2129 memcpy (f
, temp
, 2);
2133 memcpy (f
, f
+ 2, 2);
2134 memcpy (f
+ 2, temp
, 2);
2138 fixp
->fx_frag
= prev_insn_frag
;
2139 fixp
->fx_where
= prev_insn_where
;
2143 /* Update the previous insn information; leave prev_insn
2145 prev_prev_insn
= *ip
;
2147 prev_insn_is_delay_slot
= 1;
2149 /* If that was an unconditional branch, forget the previous
2150 insn information. */
2151 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2153 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2154 prev_insn
.insn_mo
= &dummy_opcode
;
2157 prev_insn_fixp
= NULL
;
2158 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2159 prev_insn_extended
= 0;
2161 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2163 /* We don't yet optimize a branch likely. What we should do
2164 is look at the target, copy the instruction found there
2165 into the delay slot, and increment the branch to jump to
2166 the next instruction. */
2168 /* Update the previous insn information. */
2169 prev_prev_insn
= *ip
;
2170 prev_insn
.insn_mo
= &dummy_opcode
;
2171 prev_insn_fixp
= NULL
;
2172 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2173 prev_insn_extended
= 0;
2177 /* Update the previous insn information. */
2179 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2181 prev_prev_insn
= prev_insn
;
2184 /* Any time we see a branch, we always fill the delay slot
2185 immediately; since this insn is not a branch, we know it
2186 is not in a delay slot. */
2187 prev_insn_is_delay_slot
= 0;
2189 prev_insn_fixp
= fixp
;
2190 prev_insn_reloc_type
= reloc_type
;
2191 if (mips_opts
.mips16
)
2192 prev_insn_extended
= (ip
->use_extend
2193 || reloc_type
> BFD_RELOC_UNUSED
);
2196 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2197 prev_insn_unreordered
= 0;
2198 prev_insn_frag
= frag_now
;
2199 prev_insn_where
= f
- frag_now
->fr_literal
;
2200 prev_insn_valid
= 1;
2202 else if (place
== NULL
)
2204 /* We need to record a bit of information even when we are not
2205 reordering, in order to determine the base address for mips16
2206 PC relative relocs. */
2207 prev_prev_insn
= prev_insn
;
2209 prev_insn_reloc_type
= reloc_type
;
2210 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2211 prev_insn_unreordered
= 1;
2214 /* We just output an insn, so the next one doesn't have a label. */
2215 mips_clear_insn_labels ();
2218 /* This function forgets that there was any previous instruction or
2219 label. If PRESERVE is non-zero, it remembers enough information to
2220 know whether nops are needed before a noreorder section. */
2223 mips_no_prev_insn (preserve
)
2228 prev_insn
.insn_mo
= &dummy_opcode
;
2229 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2230 prev_nop_frag
= NULL
;
2231 prev_nop_frag_holds
= 0;
2232 prev_nop_frag_required
= 0;
2233 prev_nop_frag_since
= 0;
2235 prev_insn_valid
= 0;
2236 prev_insn_is_delay_slot
= 0;
2237 prev_insn_unreordered
= 0;
2238 prev_insn_extended
= 0;
2239 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2240 prev_prev_insn_unreordered
= 0;
2241 mips_clear_insn_labels ();
2244 /* This function must be called whenever we turn on noreorder or emit
2245 something other than instructions. It inserts any NOPS which might
2246 be needed by the previous instruction, and clears the information
2247 kept for the previous instructions. The INSNS parameter is true if
2248 instructions are to follow. */
2251 mips_emit_delays (insns
)
2254 if (! mips_opts
.noreorder
)
2259 if ((! mips_opts
.mips16
2260 && mips_opts
.isa
< 4
2261 && (! cop_interlocks
2262 && (prev_insn
.insn_mo
->pinfo
2263 & (INSN_LOAD_COPROC_DELAY
2264 | INSN_COPROC_MOVE_DELAY
2265 | INSN_WRITE_COND_CODE
))))
2266 || (! hilo_interlocks
2267 && (prev_insn
.insn_mo
->pinfo
2270 || (! mips_opts
.mips16
2272 && (prev_insn
.insn_mo
->pinfo
2273 & INSN_LOAD_MEMORY_DELAY
))
2274 || (! mips_opts
.mips16
2275 && mips_opts
.isa
< 2
2276 && (prev_insn
.insn_mo
->pinfo
2277 & INSN_COPROC_MEMORY_DELAY
)))
2279 /* Itbl support may require additional care here. */
2281 if ((! mips_opts
.mips16
2282 && mips_opts
.isa
< 4
2283 && (! cop_interlocks
2284 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2285 || (! hilo_interlocks
2286 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2287 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2290 if (prev_insn_unreordered
)
2293 else if ((! mips_opts
.mips16
2294 && mips_opts
.isa
< 4
2295 && (! cop_interlocks
2296 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2297 || (! hilo_interlocks
2298 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2299 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2301 /* Itbl support may require additional care here. */
2302 if (! prev_prev_insn_unreordered
)
2308 struct insn_label_list
*l
;
2312 /* Record the frag which holds the nop instructions, so
2313 that we can remove them if we don't need them. */
2314 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2315 prev_nop_frag
= frag_now
;
2316 prev_nop_frag_holds
= nops
;
2317 prev_nop_frag_required
= 0;
2318 prev_nop_frag_since
= 0;
2321 for (; nops
> 0; --nops
)
2326 /* Move on to a new frag, so that it is safe to simply
2327 decrease the size of prev_nop_frag. */
2328 frag_wane (frag_now
);
2332 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2334 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2335 l
->label
->sy_frag
= frag_now
;
2336 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2337 /* mips16 text labels are stored as odd. */
2338 if (mips_opts
.mips16
)
2339 ++l
->label
->sy_value
.X_add_number
;
2344 /* Mark instruction labels in mips16 mode. */
2345 if (mips_opts
.mips16
&& insns
)
2346 mips16_mark_labels ();
2348 mips_no_prev_insn (insns
);
2351 /* Build an instruction created by a macro expansion. This is passed
2352 a pointer to the count of instructions created so far, an
2353 expression, the name of the instruction to build, an operand format
2354 string, and corresponding arguments. */
2358 macro_build (char *place
,
2366 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2375 struct mips_cl_insn insn
;
2376 bfd_reloc_code_real_type r
;
2381 va_start (args
, fmt
);
2387 * If the macro is about to expand into a second instruction,
2388 * print a warning if needed. We need to pass ip as a parameter
2389 * to generate a better warning message here...
2391 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2392 as_warn ("Macro instruction expanded into multiple instructions");
2395 *counter
+= 1; /* bump instruction counter */
2397 if (mips_opts
.mips16
)
2399 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2404 r
= BFD_RELOC_UNUSED
;
2405 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2406 assert (insn
.insn_mo
);
2407 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2409 /* Search until we get a match for NAME. */
2412 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2414 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2416 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2418 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2423 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2424 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2425 && (insn_isa
<= mips_opts
.isa
2427 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2429 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2431 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2432 /* start-sanitize-tx49 */
2434 && (insn
.insn_mo
->membership
& INSN_4900
) != 0)
2435 /* end-sanitize-tx49 */
2436 /* start-sanitize-r5900 */
2438 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2439 /* end-sanitize-r5900 */
2440 /* start-sanitize-vr5400 */
2442 && (insn
.insn_mo
->membership
& INSN_5400
) != 0)
2443 /* end-sanitize-vr5400 */
2445 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2446 /* start-sanitize-r5900 */
2447 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2448 /* end-sanitize-r5900 */
2449 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2453 assert (insn
.insn_mo
->name
);
2454 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2457 insn
.insn_opcode
= insn
.insn_mo
->match
;
2473 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2479 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2484 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2489 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2496 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2500 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2504 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2511 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2517 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2518 assert (r
== BFD_RELOC_MIPS_GPREL
2519 || r
== BFD_RELOC_MIPS_LITERAL
2520 || r
== BFD_RELOC_LO16
2521 || r
== BFD_RELOC_MIPS_GOT16
2522 || r
== BFD_RELOC_MIPS_CALL16
2523 || r
== BFD_RELOC_MIPS_GOT_LO16
2524 || r
== BFD_RELOC_MIPS_CALL_LO16
2525 || (ep
->X_op
== O_subtract
2526 && now_seg
== text_section
2527 && r
== BFD_RELOC_PCREL_LO16
));
2531 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2533 && (ep
->X_op
== O_constant
2534 || (ep
->X_op
== O_symbol
2535 && (r
== BFD_RELOC_HI16_S
2536 || r
== BFD_RELOC_HI16
2537 || r
== BFD_RELOC_MIPS_GOT_HI16
2538 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2539 || (ep
->X_op
== O_subtract
2540 && now_seg
== text_section
2541 && r
== BFD_RELOC_PCREL_HI16_S
)));
2542 if (ep
->X_op
== O_constant
)
2544 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2546 r
= BFD_RELOC_UNUSED
;
2551 assert (ep
!= NULL
);
2553 * This allows macro() to pass an immediate expression for
2554 * creating short branches without creating a symbol.
2555 * Note that the expression still might come from the assembly
2556 * input, in which case the value is not checked for range nor
2557 * is a relocation entry generated (yuck).
2559 if (ep
->X_op
== O_constant
)
2561 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2565 r
= BFD_RELOC_16_PCREL_S2
;
2569 assert (ep
!= NULL
);
2570 r
= BFD_RELOC_MIPS_JMP
;
2579 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2581 append_insn (place
, &insn
, ep
, r
, false);
2585 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2593 struct mips_cl_insn insn
;
2594 bfd_reloc_code_real_type r
;
2596 r
= BFD_RELOC_UNUSED
;
2597 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2598 assert (insn
.insn_mo
);
2599 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2601 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2602 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2605 assert (insn
.insn_mo
->name
);
2606 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2609 insn
.insn_opcode
= insn
.insn_mo
->match
;
2610 insn
.use_extend
= false;
2629 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2634 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2638 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2642 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2652 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2659 regno
= va_arg (args
, int);
2660 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2661 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2682 assert (ep
!= NULL
);
2684 if (ep
->X_op
!= O_constant
)
2685 r
= BFD_RELOC_UNUSED
+ c
;
2688 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2689 false, false, &insn
.insn_opcode
,
2690 &insn
.use_extend
, &insn
.extend
);
2692 r
= BFD_RELOC_UNUSED
;
2698 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2705 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2707 append_insn (place
, &insn
, ep
, r
, false);
2711 * Generate a "lui" instruction.
2714 macro_build_lui (place
, counter
, ep
, regnum
)
2720 expressionS high_expr
;
2721 struct mips_cl_insn insn
;
2722 bfd_reloc_code_real_type r
;
2723 CONST
char *name
= "lui";
2724 CONST
char *fmt
= "t,u";
2726 assert (! mips_opts
.mips16
);
2732 high_expr
.X_op
= O_constant
;
2733 high_expr
.X_add_number
= ep
->X_add_number
;
2736 if (high_expr
.X_op
== O_constant
)
2738 /* we can compute the instruction now without a relocation entry */
2739 if (high_expr
.X_add_number
& 0x8000)
2740 high_expr
.X_add_number
+= 0x10000;
2741 high_expr
.X_add_number
=
2742 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2743 r
= BFD_RELOC_UNUSED
;
2747 assert (ep
->X_op
== O_symbol
);
2748 /* _gp_disp is a special case, used from s_cpload. */
2749 assert (mips_pic
== NO_PIC
2750 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2751 r
= BFD_RELOC_HI16_S
;
2755 * If the macro is about to expand into a second instruction,
2756 * print a warning if needed. We need to pass ip as a parameter
2757 * to generate a better warning message here...
2759 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2760 as_warn ("Macro instruction expanded into multiple instructions");
2763 *counter
+= 1; /* bump instruction counter */
2765 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2766 assert (insn
.insn_mo
);
2767 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2768 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2770 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2771 if (r
== BFD_RELOC_UNUSED
)
2773 insn
.insn_opcode
|= high_expr
.X_add_number
;
2774 append_insn (place
, &insn
, NULL
, r
, false);
2777 append_insn (place
, &insn
, &high_expr
, r
, false);
2781 * Generates code to set the $at register to true (one)
2782 * if reg is less than the immediate expression.
2785 set_at (counter
, reg
, unsignedp
)
2790 if (imm_expr
.X_op
== O_constant
2791 && imm_expr
.X_add_number
>= -0x8000
2792 && imm_expr
.X_add_number
< 0x8000)
2793 macro_build ((char *) NULL
, counter
, &imm_expr
,
2794 unsignedp
? "sltiu" : "slti",
2795 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2798 load_register (counter
, AT
, &imm_expr
, 0);
2799 macro_build ((char *) NULL
, counter
, NULL
,
2800 unsignedp
? "sltu" : "slt",
2801 "d,v,t", AT
, reg
, AT
);
2805 /* Warn if an expression is not a constant. */
2808 check_absolute_expr (ip
, ex
)
2809 struct mips_cl_insn
*ip
;
2812 if (ex
->X_op
== O_big
)
2813 as_bad ("unsupported large constant");
2814 else if (ex
->X_op
!= O_constant
)
2815 as_bad ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2818 /* Count the leading zeroes by performing a binary chop. This is a
2819 bulky bit of source, but performance is a LOT better for the
2820 majority of values than a simple loop to count the bits:
2821 for (lcnt = 0; (lcnt < 32); lcnt++)
2822 if ((v) & (1 << (31 - lcnt)))
2824 However it is not code size friendly, and the gain will drop a bit
2825 on certain cached systems.
2827 #define COUNT_TOP_ZEROES(v) \
2828 (((v) & ~0xffff) == 0 \
2829 ? ((v) & ~0xff) == 0 \
2830 ? ((v) & ~0xf) == 0 \
2831 ? ((v) & ~0x3) == 0 \
2832 ? ((v) & ~0x1) == 0 \
2837 : ((v) & ~0x7) == 0 \
2840 : ((v) & ~0x3f) == 0 \
2841 ? ((v) & ~0x1f) == 0 \
2844 : ((v) & ~0x7f) == 0 \
2847 : ((v) & ~0xfff) == 0 \
2848 ? ((v) & ~0x3ff) == 0 \
2849 ? ((v) & ~0x1ff) == 0 \
2852 : ((v) & ~0x7ff) == 0 \
2855 : ((v) & ~0x3fff) == 0 \
2856 ? ((v) & ~0x1fff) == 0 \
2859 : ((v) & ~0x7fff) == 0 \
2862 : ((v) & ~0xffffff) == 0 \
2863 ? ((v) & ~0xfffff) == 0 \
2864 ? ((v) & ~0x3ffff) == 0 \
2865 ? ((v) & ~0x1ffff) == 0 \
2868 : ((v) & ~0x7ffff) == 0 \
2871 : ((v) & ~0x3fffff) == 0 \
2872 ? ((v) & ~0x1fffff) == 0 \
2875 : ((v) & ~0x7fffff) == 0 \
2878 : ((v) & ~0xfffffff) == 0 \
2879 ? ((v) & ~0x3ffffff) == 0 \
2880 ? ((v) & ~0x1ffffff) == 0 \
2883 : ((v) & ~0x7ffffff) == 0 \
2886 : ((v) & ~0x3fffffff) == 0 \
2887 ? ((v) & ~0x1fffffff) == 0 \
2890 : ((v) & ~0x7fffffff) == 0 \
2895 * This routine generates the least number of instructions neccessary to load
2896 * an absolute expression value into a register.
2899 load_register (counter
, reg
, ep
, dbl
)
2906 expressionS hi32
, lo32
;
2908 if (ep
->X_op
!= O_big
)
2910 assert (ep
->X_op
== O_constant
);
2911 if (ep
->X_add_number
< 0x8000
2912 && (ep
->X_add_number
>= 0
2913 || (ep
->X_add_number
>= -0x8000
2916 || sizeof (ep
->X_add_number
) > 4))))
2918 /* We can handle 16 bit signed values with an addiu to
2919 $zero. No need to ever use daddiu here, since $zero and
2920 the result are always correct in 32 bit mode. */
2921 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2922 (int) BFD_RELOC_LO16
);
2925 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2927 /* We can handle 16 bit unsigned values with an ori to
2929 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2930 (int) BFD_RELOC_LO16
);
2933 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2934 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2935 == ~ (offsetT
) 0x7fffffff))
2938 || sizeof (ep
->X_add_number
) > 4
2939 || (ep
->X_add_number
& 0x80000000) == 0))
2940 || ((mips_opts
.isa
< 3 || ! dbl
)
2941 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2942 || (mips_opts
.isa
< 3
2944 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2945 == ~ (offsetT
) 0xffffffff)))
2947 /* 32 bit values require an lui. */
2948 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2949 (int) BFD_RELOC_HI16
);
2950 if ((ep
->X_add_number
& 0xffff) != 0)
2951 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2952 (int) BFD_RELOC_LO16
);
2957 /* The value is larger than 32 bits. */
2959 if (mips_opts
.isa
< 3)
2961 as_bad ("Number larger than 32 bits");
2962 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2963 (int) BFD_RELOC_LO16
);
2967 if (ep
->X_op
!= O_big
)
2970 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2971 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2972 hi32
.X_add_number
&= 0xffffffff;
2974 lo32
.X_add_number
&= 0xffffffff;
2978 assert (ep
->X_add_number
> 2);
2979 if (ep
->X_add_number
== 3)
2980 generic_bignum
[3] = 0;
2981 else if (ep
->X_add_number
> 4)
2982 as_bad ("Number larger than 64 bits");
2983 lo32
.X_op
= O_constant
;
2984 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2985 hi32
.X_op
= O_constant
;
2986 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2989 if (hi32
.X_add_number
== 0)
2994 unsigned long hi
, lo
;
2996 if (hi32
.X_add_number
== 0xffffffff)
2998 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3000 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3001 reg
, 0, (int) BFD_RELOC_LO16
);
3004 if (lo32
.X_add_number
& 0x80000000)
3006 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3007 (int) BFD_RELOC_HI16
);
3008 if (lo32
.X_add_number
& 0xffff)
3009 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3010 reg
, reg
, (int) BFD_RELOC_LO16
);
3015 /* Check for 16bit shifted constant. We know that hi32 is
3016 non-zero, so start the mask on the first bit of the hi32
3021 unsigned long himask
, lomask
;
3025 himask
= 0xffff >> (32 - shift
);
3026 lomask
= (0xffff << shift
) & 0xffffffff;
3030 himask
= 0xffff << (shift
- 32);
3033 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3034 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3038 tmp
.X_op
= O_constant
;
3040 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3041 | (lo32
.X_add_number
>> shift
));
3043 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3044 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3045 (int) BFD_RELOC_LO16
);
3046 macro_build ((char *) NULL
, counter
, NULL
,
3047 (shift
>= 32) ? "dsll32" : "dsll",
3049 (shift
>= 32) ? shift
- 32 : shift
);
3053 } while (shift
<= (64 - 16));
3055 /* Find the bit number of the lowest one bit, and store the
3056 shifted value in hi/lo. */
3057 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3058 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3062 while ((lo
& 1) == 0)
3067 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3073 while ((hi
& 1) == 0)
3082 /* Optimize if the shifted value is a (power of 2) - 1. */
3083 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3084 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3086 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3091 /* This instruction will set the register to be all
3093 tmp
.X_op
= O_constant
;
3094 tmp
.X_add_number
= (offsetT
) -1;
3095 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3096 reg
, 0, (int) BFD_RELOC_LO16
);
3100 macro_build ((char *) NULL
, counter
, NULL
,
3101 (bit
>= 32) ? "dsll32" : "dsll",
3103 (bit
>= 32) ? bit
- 32 : bit
);
3105 macro_build ((char *) NULL
, counter
, NULL
,
3106 (shift
>= 32) ? "dsrl32" : "dsrl",
3108 (shift
>= 32) ? shift
- 32 : shift
);
3113 /* Sign extend hi32 before calling load_register, because we can
3114 generally get better code when we load a sign extended value. */
3115 if ((hi32
.X_add_number
& 0x80000000) != 0)
3116 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3117 load_register (counter
, reg
, &hi32
, 0);
3120 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3124 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3133 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3135 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3136 (int) BFD_RELOC_HI16
);
3137 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3144 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3149 mid16
.X_add_number
>>= 16;
3150 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3151 freg
, (int) BFD_RELOC_LO16
);
3152 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3156 if ((lo32
.X_add_number
& 0xffff) != 0)
3157 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3158 (int) BFD_RELOC_LO16
);
3161 /* Load an address into a register. */
3164 load_address (counter
, reg
, ep
)
3171 if (ep
->X_op
!= O_constant
3172 && ep
->X_op
!= O_symbol
)
3174 as_bad ("expression too complex");
3175 ep
->X_op
= O_constant
;
3178 if (ep
->X_op
== O_constant
)
3180 load_register (counter
, reg
, ep
, 0);
3184 if (mips_pic
== NO_PIC
)
3186 /* If this is a reference to a GP relative symbol, we want
3187 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3189 lui $reg,<sym> (BFD_RELOC_HI16_S)
3190 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3191 If we have an addend, we always use the latter form. */
3192 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3193 || nopic_need_relax (ep
->X_add_symbol
, 1))
3198 macro_build ((char *) NULL
, counter
, ep
,
3199 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3200 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3201 p
= frag_var (rs_machine_dependent
, 8, 0,
3202 RELAX_ENCODE (4, 8, 0, 4, 0,
3203 mips_opts
.warn_about_macros
),
3204 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3206 macro_build_lui (p
, counter
, ep
, reg
);
3209 macro_build (p
, counter
, ep
,
3210 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3211 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3213 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3217 /* If this is a reference to an external symbol, we want
3218 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3220 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3222 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3223 If there is a constant, it must be added in after. */
3224 ex
.X_add_number
= ep
->X_add_number
;
3225 ep
->X_add_number
= 0;
3227 macro_build ((char *) NULL
, counter
, ep
,
3228 mips_opts
.isa
< 3 ? "lw" : "ld",
3229 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3230 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3231 p
= frag_var (rs_machine_dependent
, 4, 0,
3232 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3233 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3234 macro_build (p
, counter
, ep
,
3235 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3236 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3237 if (ex
.X_add_number
!= 0)
3239 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3240 as_bad ("PIC code offset overflow (max 16 signed bits)");
3241 ex
.X_op
= O_constant
;
3242 macro_build ((char *) NULL
, counter
, &ex
,
3243 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3244 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3247 else if (mips_pic
== SVR4_PIC
)
3252 /* This is the large GOT case. If this is a reference to an
3253 external symbol, we want
3254 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3256 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3257 Otherwise, for a reference to a local symbol, we want
3258 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3260 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3261 If there is a constant, it must be added in after. */
3262 ex
.X_add_number
= ep
->X_add_number
;
3263 ep
->X_add_number
= 0;
3264 if (reg_needs_delay (GP
))
3269 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3270 (int) BFD_RELOC_MIPS_GOT_HI16
);
3271 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3272 mips_opts
.isa
< 3 ? "addu" : "daddu",
3273 "d,v,t", reg
, reg
, GP
);
3274 macro_build ((char *) NULL
, counter
, ep
,
3275 mips_opts
.isa
< 3 ? "lw" : "ld",
3276 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3277 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3278 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3279 mips_opts
.warn_about_macros
),
3280 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3283 /* We need a nop before loading from $gp. This special
3284 check is required because the lui which starts the main
3285 instruction stream does not refer to $gp, and so will not
3286 insert the nop which may be required. */
3287 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3290 macro_build (p
, counter
, ep
,
3291 mips_opts
.isa
< 3 ? "lw" : "ld",
3292 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3294 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3296 macro_build (p
, counter
, ep
,
3297 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3298 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3299 if (ex
.X_add_number
!= 0)
3301 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3302 as_bad ("PIC code offset overflow (max 16 signed bits)");
3303 ex
.X_op
= O_constant
;
3304 macro_build ((char *) NULL
, counter
, &ex
,
3305 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3306 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3309 else if (mips_pic
== EMBEDDED_PIC
)
3312 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3314 macro_build ((char *) NULL
, counter
, ep
,
3315 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3316 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3324 * This routine implements the seemingly endless macro or synthesized
3325 * instructions and addressing modes in the mips assembly language. Many
3326 * of these macros are simple and are similar to each other. These could
3327 * probably be handled by some kind of table or grammer aproach instead of
3328 * this verbose method. Others are not simple macros but are more like
3329 * optimizing code generation.
3330 * One interesting optimization is when several store macros appear
3331 * consecutivly that would load AT with the upper half of the same address.
3332 * The ensuing load upper instructions are ommited. This implies some kind
3333 * of global optimization. We currently only optimize within a single macro.
3334 * For many of the load and store macros if the address is specified as a
3335 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3336 * first load register 'at' with zero and use it as the base register. The
3337 * mips assembler simply uses register $zero. Just one tiny optimization
3342 struct mips_cl_insn
*ip
;
3344 register int treg
, sreg
, dreg
, breg
;
3359 bfd_reloc_code_real_type r
;
3361 int hold_mips_optimize
;
3363 assert (! mips_opts
.mips16
);
3365 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3366 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3367 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3368 mask
= ip
->insn_mo
->mask
;
3370 expr1
.X_op
= O_constant
;
3371 expr1
.X_op_symbol
= NULL
;
3372 expr1
.X_add_symbol
= NULL
;
3373 expr1
.X_add_number
= 1;
3385 mips_emit_delays (true);
3386 ++mips_opts
.noreorder
;
3387 mips_any_noreorder
= 1;
3389 expr1
.X_add_number
= 8;
3390 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3392 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3394 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3395 macro_build ((char *) NULL
, &icnt
, NULL
,
3396 dbl
? "dsub" : "sub",
3397 "d,v,t", dreg
, 0, sreg
);
3399 --mips_opts
.noreorder
;
3420 if (imm_expr
.X_op
== O_constant
3421 && imm_expr
.X_add_number
>= -0x8000
3422 && imm_expr
.X_add_number
< 0x8000)
3424 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3425 (int) BFD_RELOC_LO16
);
3428 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3429 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3448 if (imm_expr
.X_op
== O_constant
3449 && imm_expr
.X_add_number
>= 0
3450 && imm_expr
.X_add_number
< 0x10000)
3452 if (mask
!= M_NOR_I
)
3453 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3454 sreg
, (int) BFD_RELOC_LO16
);
3457 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3458 treg
, sreg
, (int) BFD_RELOC_LO16
);
3459 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3465 load_register (&icnt
, AT
, &imm_expr
, 0);
3466 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3483 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3485 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3489 load_register (&icnt
, AT
, &imm_expr
, 0);
3490 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3498 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3499 likely
? "bgezl" : "bgez",
3505 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3506 likely
? "blezl" : "blez",
3510 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3511 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3512 likely
? "beql" : "beq",
3519 /* check for > max integer */
3520 maxnum
= 0x7fffffff;
3521 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3528 if (imm_expr
.X_op
== O_constant
3529 && imm_expr
.X_add_number
>= maxnum
3530 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3533 /* result is always false */
3536 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3537 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3541 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3542 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3547 if (imm_expr
.X_op
!= O_constant
)
3548 as_bad ("Unsupported large constant");
3549 imm_expr
.X_add_number
++;
3553 if (mask
== M_BGEL_I
)
3555 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3557 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3558 likely
? "bgezl" : "bgez",
3562 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3564 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3565 likely
? "bgtzl" : "bgtz",
3569 maxnum
= 0x7fffffff;
3570 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3577 maxnum
= - maxnum
- 1;
3578 if (imm_expr
.X_op
== O_constant
3579 && imm_expr
.X_add_number
<= maxnum
3580 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3583 /* result is always true */
3584 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3585 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3588 set_at (&icnt
, sreg
, 0);
3589 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3590 likely
? "beql" : "beq",
3601 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3602 likely
? "beql" : "beq",
3606 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3608 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3609 likely
? "beql" : "beq",
3617 || (mips_opts
.isa
< 3
3618 && imm_expr
.X_op
== O_constant
3619 && imm_expr
.X_add_number
== 0xffffffff))
3621 if (imm_expr
.X_op
!= O_constant
)
3622 as_bad ("Unsupported large constant");
3623 imm_expr
.X_add_number
++;
3627 if (mask
== M_BGEUL_I
)
3629 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3631 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3633 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3634 likely
? "bnel" : "bne",
3638 set_at (&icnt
, sreg
, 1);
3639 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3640 likely
? "beql" : "beq",
3649 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3650 likely
? "bgtzl" : "bgtz",
3656 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3657 likely
? "bltzl" : "bltz",
3661 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3662 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3663 likely
? "bnel" : "bne",
3672 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3673 likely
? "bnel" : "bne",
3679 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3681 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3682 likely
? "bnel" : "bne",
3691 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3692 likely
? "blezl" : "blez",
3698 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3699 likely
? "bgezl" : "bgez",
3703 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3704 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3705 likely
? "beql" : "beq",
3712 maxnum
= 0x7fffffff;
3713 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3720 if (imm_expr
.X_op
== O_constant
3721 && imm_expr
.X_add_number
>= maxnum
3722 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3724 if (imm_expr
.X_op
!= O_constant
)
3725 as_bad ("Unsupported large constant");
3726 imm_expr
.X_add_number
++;
3730 if (mask
== M_BLTL_I
)
3732 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3734 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3735 likely
? "bltzl" : "bltz",
3739 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3741 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3742 likely
? "blezl" : "blez",
3746 set_at (&icnt
, sreg
, 0);
3747 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3748 likely
? "bnel" : "bne",
3757 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3758 likely
? "beql" : "beq",
3764 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3766 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3767 likely
? "beql" : "beq",
3775 || (mips_opts
.isa
< 3
3776 && imm_expr
.X_op
== O_constant
3777 && imm_expr
.X_add_number
== 0xffffffff))
3779 if (imm_expr
.X_op
!= O_constant
)
3780 as_bad ("Unsupported large constant");
3781 imm_expr
.X_add_number
++;
3785 if (mask
== M_BLTUL_I
)
3787 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3789 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3791 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3792 likely
? "beql" : "beq",
3796 set_at (&icnt
, sreg
, 1);
3797 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3798 likely
? "bnel" : "bne",
3807 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3808 likely
? "bltzl" : "bltz",
3814 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3815 likely
? "bgtzl" : "bgtz",
3819 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3820 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3821 likely
? "bnel" : "bne",
3832 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3833 likely
? "bnel" : "bne",
3837 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3839 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3840 likely
? "bnel" : "bne",
3856 as_warn ("Divide by zero.");
3858 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3860 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3864 mips_emit_delays (true);
3865 ++mips_opts
.noreorder
;
3866 mips_any_noreorder
= 1;
3869 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3870 macro_build ((char *) NULL
, &icnt
, NULL
,
3871 dbl
? "ddiv" : "div",
3872 "z,s,t", sreg
, treg
);
3876 expr1
.X_add_number
= 8;
3877 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3878 macro_build ((char *) NULL
, &icnt
, NULL
,
3879 dbl
? "ddiv" : "div",
3880 "z,s,t", sreg
, treg
);
3881 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3883 expr1
.X_add_number
= -1;
3884 macro_build ((char *) NULL
, &icnt
, &expr1
,
3885 dbl
? "daddiu" : "addiu",
3886 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3887 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3888 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3891 expr1
.X_add_number
= 1;
3892 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3893 (int) BFD_RELOC_LO16
);
3894 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3899 expr1
.X_add_number
= 0x80000000;
3900 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3901 (int) BFD_RELOC_HI16
);
3904 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3907 expr1
.X_add_number
= 8;
3908 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3909 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3910 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3912 --mips_opts
.noreorder
;
3913 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3952 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3954 as_warn ("Divide by zero.");
3956 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3958 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3961 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3963 if (strcmp (s2
, "mflo") == 0)
3964 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3967 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3970 if (imm_expr
.X_op
== O_constant
3971 && imm_expr
.X_add_number
== -1
3972 && s
[strlen (s
) - 1] != 'u')
3974 if (strcmp (s2
, "mflo") == 0)
3977 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3980 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3984 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3988 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3989 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3990 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4009 mips_emit_delays (true);
4010 ++mips_opts
.noreorder
;
4011 mips_any_noreorder
= 1;
4014 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4015 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4019 expr1
.X_add_number
= 8;
4020 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4021 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4022 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4024 --mips_opts
.noreorder
;
4025 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4031 /* Load the address of a symbol into a register. If breg is not
4032 zero, we then add a base register to it. */
4034 /* When generating embedded PIC code, we permit expressions of
4037 where bar is an address in the .text section. These are used
4038 when getting the addresses of functions. We don't permit
4039 X_add_number to be non-zero, because if the symbol is
4040 external the relaxing code needs to know that any addend is
4041 purely the offset to X_op_symbol. */
4042 if (mips_pic
== EMBEDDED_PIC
4043 && offset_expr
.X_op
== O_subtract
4044 && now_seg
== text_section
4045 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4046 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4047 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4048 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4049 ->sy_value
.X_add_symbol
)
4052 && offset_expr
.X_add_number
== 0)
4054 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4055 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4056 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4057 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4058 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4062 if (offset_expr
.X_op
!= O_symbol
4063 && offset_expr
.X_op
!= O_constant
)
4065 as_bad ("expression too complex");
4066 offset_expr
.X_op
= O_constant
;
4080 if (offset_expr
.X_op
== O_constant
)
4081 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4082 else if (mips_pic
== NO_PIC
)
4084 /* If this is a reference to an GP relative symbol, we want
4085 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4087 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4088 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4089 If we have a constant, we need two instructions anyhow,
4090 so we may as well always use the latter form. */
4091 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4092 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4097 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4098 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4099 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4100 p
= frag_var (rs_machine_dependent
, 8, 0,
4101 RELAX_ENCODE (4, 8, 0, 4, 0,
4102 mips_opts
.warn_about_macros
),
4103 offset_expr
.X_add_symbol
, (offsetT
) 0,
4106 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4109 macro_build (p
, &icnt
, &offset_expr
,
4110 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4111 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4113 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4115 /* If this is a reference to an external symbol, and there
4116 is no constant, we want
4117 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4118 For a local symbol, we want
4119 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4121 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4123 If we have a small constant, and this is a reference to
4124 an external symbol, we want
4125 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4127 addiu $tempreg,$tempreg,<constant>
4128 For a local symbol, we want the same instruction
4129 sequence, but we output a BFD_RELOC_LO16 reloc on the
4132 If we have a large constant, and this is a reference to
4133 an external symbol, we want
4134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4135 lui $at,<hiconstant>
4136 addiu $at,$at,<loconstant>
4137 addu $tempreg,$tempreg,$at
4138 For a local symbol, we want the same instruction
4139 sequence, but we output a BFD_RELOC_LO16 reloc on the
4140 addiu instruction. */
4141 expr1
.X_add_number
= offset_expr
.X_add_number
;
4142 offset_expr
.X_add_number
= 0;
4144 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4146 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4147 if (expr1
.X_add_number
== 0)
4155 /* We're going to put in an addu instruction using
4156 tempreg, so we may as well insert the nop right
4158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4162 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4163 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4165 ? mips_opts
.warn_about_macros
4167 offset_expr
.X_add_symbol
, (offsetT
) 0,
4171 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4174 macro_build (p
, &icnt
, &expr1
,
4175 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4176 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4177 /* FIXME: If breg == 0, and the next instruction uses
4178 $tempreg, then if this variant case is used an extra
4179 nop will be generated. */
4181 else if (expr1
.X_add_number
>= -0x8000
4182 && expr1
.X_add_number
< 0x8000)
4184 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4186 macro_build ((char *) NULL
, &icnt
, &expr1
,
4187 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4188 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4189 (void) frag_var (rs_machine_dependent
, 0, 0,
4190 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4191 offset_expr
.X_add_symbol
, (offsetT
) 0,
4198 /* If we are going to add in a base register, and the
4199 target register and the base register are the same,
4200 then we are using AT as a temporary register. Since
4201 we want to load the constant into AT, we add our
4202 current AT (from the global offset table) and the
4203 register into the register now, and pretend we were
4204 not using a base register. */
4209 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4211 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4212 mips_opts
.isa
< 3 ? "addu" : "daddu",
4213 "d,v,t", treg
, AT
, breg
);
4219 /* Set mips_optimize around the lui instruction to avoid
4220 inserting an unnecessary nop after the lw. */
4221 hold_mips_optimize
= mips_optimize
;
4223 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4224 mips_optimize
= hold_mips_optimize
;
4226 macro_build ((char *) NULL
, &icnt
, &expr1
,
4227 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4228 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4229 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4230 mips_opts
.isa
< 3 ? "addu" : "daddu",
4231 "d,v,t", tempreg
, tempreg
, AT
);
4232 (void) frag_var (rs_machine_dependent
, 0, 0,
4233 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4234 offset_expr
.X_add_symbol
, (offsetT
) 0,
4239 else if (mips_pic
== SVR4_PIC
)
4243 /* This is the large GOT case. If this is a reference to an
4244 external symbol, and there is no constant, we want
4245 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4246 addu $tempreg,$tempreg,$gp
4247 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4248 For a local symbol, we want
4249 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4251 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4253 If we have a small constant, and this is a reference to
4254 an external symbol, we want
4255 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4256 addu $tempreg,$tempreg,$gp
4257 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4259 addiu $tempreg,$tempreg,<constant>
4260 For a local symbol, we want
4261 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4263 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4265 If we have a large constant, and this is a reference to
4266 an external symbol, we want
4267 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4268 addu $tempreg,$tempreg,$gp
4269 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4270 lui $at,<hiconstant>
4271 addiu $at,$at,<loconstant>
4272 addu $tempreg,$tempreg,$at
4273 For a local symbol, we want
4274 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4275 lui $at,<hiconstant>
4276 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4277 addu $tempreg,$tempreg,$at
4279 expr1
.X_add_number
= offset_expr
.X_add_number
;
4280 offset_expr
.X_add_number
= 0;
4282 if (reg_needs_delay (GP
))
4286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4287 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4288 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4289 mips_opts
.isa
< 3 ? "addu" : "daddu",
4290 "d,v,t", tempreg
, tempreg
, GP
);
4291 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4293 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4295 if (expr1
.X_add_number
== 0)
4303 /* We're going to put in an addu instruction using
4304 tempreg, so we may as well insert the nop right
4306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4311 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4312 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4315 ? mips_opts
.warn_about_macros
4317 offset_expr
.X_add_symbol
, (offsetT
) 0,
4320 else if (expr1
.X_add_number
>= -0x8000
4321 && expr1
.X_add_number
< 0x8000)
4323 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4325 macro_build ((char *) NULL
, &icnt
, &expr1
,
4326 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4327 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4329 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4330 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4332 ? mips_opts
.warn_about_macros
4334 offset_expr
.X_add_symbol
, (offsetT
) 0,
4341 /* If we are going to add in a base register, and the
4342 target register and the base register are the same,
4343 then we are using AT as a temporary register. Since
4344 we want to load the constant into AT, we add our
4345 current AT (from the global offset table) and the
4346 register into the register now, and pretend we were
4347 not using a base register. */
4355 assert (tempreg
== AT
);
4356 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4358 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4359 mips_opts
.isa
< 3 ? "addu" : "daddu",
4360 "d,v,t", treg
, AT
, breg
);
4365 /* Set mips_optimize around the lui instruction to avoid
4366 inserting an unnecessary nop after the lw. */
4367 hold_mips_optimize
= mips_optimize
;
4369 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4370 mips_optimize
= hold_mips_optimize
;
4372 macro_build ((char *) NULL
, &icnt
, &expr1
,
4373 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4374 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4375 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4376 mips_opts
.isa
< 3 ? "addu" : "daddu",
4377 "d,v,t", dreg
, dreg
, AT
);
4379 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4380 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4383 ? mips_opts
.warn_about_macros
4385 offset_expr
.X_add_symbol
, (offsetT
) 0,
4393 /* This is needed because this instruction uses $gp, but
4394 the first instruction on the main stream does not. */
4395 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4398 macro_build (p
, &icnt
, &offset_expr
,
4400 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4402 if (expr1
.X_add_number
>= -0x8000
4403 && expr1
.X_add_number
< 0x8000)
4405 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4407 macro_build (p
, &icnt
, &expr1
,
4408 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4409 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4410 /* FIXME: If add_number is 0, and there was no base
4411 register, the external symbol case ended with a load,
4412 so if the symbol turns out to not be external, and
4413 the next instruction uses tempreg, an unnecessary nop
4414 will be inserted. */
4420 /* We must add in the base register now, as in the
4421 external symbol case. */
4422 assert (tempreg
== AT
);
4423 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4425 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4426 mips_opts
.isa
< 3 ? "addu" : "daddu",
4427 "d,v,t", treg
, AT
, breg
);
4430 /* We set breg to 0 because we have arranged to add
4431 it in in both cases. */
4435 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4437 macro_build (p
, &icnt
, &expr1
,
4438 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4439 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4441 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4442 mips_opts
.isa
< 3 ? "addu" : "daddu",
4443 "d,v,t", tempreg
, tempreg
, AT
);
4447 else if (mips_pic
== EMBEDDED_PIC
)
4450 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4452 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4453 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4454 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4460 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4461 mips_opts
.isa
< 3 ? "addu" : "daddu",
4462 "d,v,t", treg
, tempreg
, breg
);
4470 /* The j instruction may not be used in PIC code, since it
4471 requires an absolute address. We convert it to a b
4473 if (mips_pic
== NO_PIC
)
4474 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4476 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4479 /* The jal instructions must be handled as macros because when
4480 generating PIC code they expand to multi-instruction
4481 sequences. Normally they are simple instructions. */
4486 if (mips_pic
== NO_PIC
4487 || mips_pic
== EMBEDDED_PIC
)
4488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4490 else if (mips_pic
== SVR4_PIC
)
4492 if (sreg
!= PIC_CALL_REG
)
4493 as_warn ("MIPS PIC call to register other than $25");
4495 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4497 if (mips_cprestore_offset
< 0)
4498 as_warn ("No .cprestore pseudo-op used in PIC code");
4501 expr1
.X_add_number
= mips_cprestore_offset
;
4502 macro_build ((char *) NULL
, &icnt
, &expr1
,
4503 mips_opts
.isa
< 3 ? "lw" : "ld",
4504 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4513 if (mips_pic
== NO_PIC
)
4514 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4515 else if (mips_pic
== SVR4_PIC
)
4517 /* If this is a reference to an external symbol, and we are
4518 using a small GOT, we want
4519 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4523 lw $gp,cprestore($sp)
4524 The cprestore value is set using the .cprestore
4525 pseudo-op. If we are using a big GOT, we want
4526 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4528 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4532 lw $gp,cprestore($sp)
4533 If the symbol is not external, we want
4534 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4536 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4539 lw $gp,cprestore($sp) */
4543 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4544 mips_opts
.isa
< 3 ? "lw" : "ld",
4545 "t,o(b)", PIC_CALL_REG
,
4546 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4547 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4549 p
= frag_var (rs_machine_dependent
, 4, 0,
4550 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4551 offset_expr
.X_add_symbol
, (offsetT
) 0,
4558 if (reg_needs_delay (GP
))
4562 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4563 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4564 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4565 mips_opts
.isa
< 3 ? "addu" : "daddu",
4566 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4567 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4568 mips_opts
.isa
< 3 ? "lw" : "ld",
4569 "t,o(b)", PIC_CALL_REG
,
4570 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4571 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4573 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4574 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4576 offset_expr
.X_add_symbol
, (offsetT
) 0,
4580 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4583 macro_build (p
, &icnt
, &offset_expr
,
4584 mips_opts
.isa
< 3 ? "lw" : "ld",
4585 "t,o(b)", PIC_CALL_REG
,
4586 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4588 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4591 macro_build (p
, &icnt
, &offset_expr
,
4592 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4593 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4594 (int) BFD_RELOC_LO16
);
4595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4596 "jalr", "s", PIC_CALL_REG
);
4597 if (mips_cprestore_offset
< 0)
4598 as_warn ("No .cprestore pseudo-op used in PIC code");
4601 if (mips_opts
.noreorder
)
4602 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4604 expr1
.X_add_number
= mips_cprestore_offset
;
4605 macro_build ((char *) NULL
, &icnt
, &expr1
,
4606 mips_opts
.isa
< 3 ? "lw" : "ld",
4607 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4611 else if (mips_pic
== EMBEDDED_PIC
)
4613 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4614 /* The linker may expand the call to a longer sequence which
4615 uses $at, so we must break rather than return. */
4640 /* Itbl support may require additional care here. */
4645 /* Itbl support may require additional care here. */
4650 /* Itbl support may require additional care here. */
4655 /* Itbl support may require additional care here. */
4669 as_bad ("opcode not supported on this processor");
4673 /* Itbl support may require additional care here. */
4678 /* Itbl support may require additional care here. */
4683 /* Itbl support may require additional care here. */
4703 if (breg
== treg
|| coproc
|| lr
)
4725 /* Itbl support may require additional care here. */
4730 /* Itbl support may require additional care here. */
4735 /* Itbl support may require additional care here. */
4740 /* Itbl support may require additional care here. */
4758 as_bad ("opcode not supported on this processor");
4763 /* Itbl support may require additional care here. */
4767 /* Itbl support may require additional care here. */
4772 /* Itbl support may require additional care here. */
4784 /* Itbl support may require additional care here. */
4785 if (mask
== M_LWC1_AB
4786 || mask
== M_SWC1_AB
4787 || mask
== M_LDC1_AB
4788 || mask
== M_SDC1_AB
4797 if (offset_expr
.X_op
!= O_constant
4798 && offset_expr
.X_op
!= O_symbol
)
4800 as_bad ("expression too complex");
4801 offset_expr
.X_op
= O_constant
;
4804 /* A constant expression in PIC code can be handled just as it
4805 is in non PIC code. */
4806 if (mips_pic
== NO_PIC
4807 || offset_expr
.X_op
== O_constant
)
4809 /* If this is a reference to a GP relative symbol, and there
4810 is no base register, we want
4811 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4812 Otherwise, if there is no base register, we want
4813 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4814 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4815 If we have a constant, we need two instructions anyhow,
4816 so we always use the latter form.
4818 If we have a base register, and this is a reference to a
4819 GP relative symbol, we want
4820 addu $tempreg,$breg,$gp
4821 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4823 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4824 addu $tempreg,$tempreg,$breg
4825 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4826 With a constant we always use the latter case. */
4829 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4830 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4835 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4836 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4837 p
= frag_var (rs_machine_dependent
, 8, 0,
4838 RELAX_ENCODE (4, 8, 0, 4, 0,
4839 (mips_opts
.warn_about_macros
4841 && mips_opts
.noat
))),
4842 offset_expr
.X_add_symbol
, (offsetT
) 0,
4846 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4849 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4850 (int) BFD_RELOC_LO16
, tempreg
);
4854 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4855 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4860 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4861 mips_opts
.isa
< 3 ? "addu" : "daddu",
4862 "d,v,t", tempreg
, breg
, GP
);
4863 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4864 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4865 p
= frag_var (rs_machine_dependent
, 12, 0,
4866 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4867 offset_expr
.X_add_symbol
, (offsetT
) 0,
4870 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4873 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4874 mips_opts
.isa
< 3 ? "addu" : "daddu",
4875 "d,v,t", tempreg
, tempreg
, breg
);
4878 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4879 (int) BFD_RELOC_LO16
, tempreg
);
4882 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4884 /* If this is a reference to an external symbol, we want
4885 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4887 <op> $treg,0($tempreg)
4889 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4891 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4892 <op> $treg,0($tempreg)
4893 If there is a base register, we add it to $tempreg before
4894 the <op>. If there is a constant, we stick it in the
4895 <op> instruction. We don't handle constants larger than
4896 16 bits, because we have no way to load the upper 16 bits
4897 (actually, we could handle them for the subset of cases
4898 in which we are not using $at). */
4899 assert (offset_expr
.X_op
== O_symbol
);
4900 expr1
.X_add_number
= offset_expr
.X_add_number
;
4901 offset_expr
.X_add_number
= 0;
4902 if (expr1
.X_add_number
< -0x8000
4903 || expr1
.X_add_number
>= 0x8000)
4904 as_bad ("PIC code offset overflow (max 16 signed bits)");
4906 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4907 mips_opts
.isa
< 3 ? "lw" : "ld",
4908 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4909 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4910 p
= frag_var (rs_machine_dependent
, 4, 0,
4911 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4912 offset_expr
.X_add_symbol
, (offsetT
) 0,
4914 macro_build (p
, &icnt
, &offset_expr
,
4915 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4916 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4918 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4919 mips_opts
.isa
< 3 ? "addu" : "daddu",
4920 "d,v,t", tempreg
, tempreg
, breg
);
4921 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4922 (int) BFD_RELOC_LO16
, tempreg
);
4924 else if (mips_pic
== SVR4_PIC
)
4928 /* If this is a reference to an external symbol, we want
4929 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4930 addu $tempreg,$tempreg,$gp
4931 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4932 <op> $treg,0($tempreg)
4934 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4936 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4937 <op> $treg,0($tempreg)
4938 If there is a base register, we add it to $tempreg before
4939 the <op>. If there is a constant, we stick it in the
4940 <op> instruction. We don't handle constants larger than
4941 16 bits, because we have no way to load the upper 16 bits
4942 (actually, we could handle them for the subset of cases
4943 in which we are not using $at). */
4944 assert (offset_expr
.X_op
== O_symbol
);
4945 expr1
.X_add_number
= offset_expr
.X_add_number
;
4946 offset_expr
.X_add_number
= 0;
4947 if (expr1
.X_add_number
< -0x8000
4948 || expr1
.X_add_number
>= 0x8000)
4949 as_bad ("PIC code offset overflow (max 16 signed bits)");
4950 if (reg_needs_delay (GP
))
4955 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4956 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4957 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4958 mips_opts
.isa
< 3 ? "addu" : "daddu",
4959 "d,v,t", tempreg
, tempreg
, GP
);
4960 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4961 mips_opts
.isa
< 3 ? "lw" : "ld",
4962 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4964 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4965 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4966 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
4969 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4972 macro_build (p
, &icnt
, &offset_expr
,
4973 mips_opts
.isa
< 3 ? "lw" : "ld",
4974 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4976 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4978 macro_build (p
, &icnt
, &offset_expr
,
4979 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4980 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4982 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4983 mips_opts
.isa
< 3 ? "addu" : "daddu",
4984 "d,v,t", tempreg
, tempreg
, breg
);
4985 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4986 (int) BFD_RELOC_LO16
, tempreg
);
4988 else if (mips_pic
== EMBEDDED_PIC
)
4990 /* If there is no base register, we want
4991 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4992 If there is a base register, we want
4993 addu $tempreg,$breg,$gp
4994 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4996 assert (offset_expr
.X_op
== O_symbol
);
4999 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5000 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5005 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5006 mips_opts
.isa
< 3 ? "addu" : "daddu",
5007 "d,v,t", tempreg
, breg
, GP
);
5008 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5009 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5022 load_register (&icnt
, treg
, &imm_expr
, 0);
5026 load_register (&icnt
, treg
, &imm_expr
, 1);
5030 if (imm_expr
.X_op
== O_constant
)
5032 load_register (&icnt
, AT
, &imm_expr
, 0);
5033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5034 "mtc1", "t,G", AT
, treg
);
5039 assert (offset_expr
.X_op
== O_symbol
5040 && strcmp (segment_name (S_GET_SEGMENT
5041 (offset_expr
.X_add_symbol
)),
5043 && offset_expr
.X_add_number
== 0);
5044 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5045 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5050 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5051 the entire value, and in mips1 mode it is the high order 32
5052 bits of the value and the low order 32 bits are either zero
5053 or in offset_expr. */
5054 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5056 if (mips_opts
.isa
>= 3)
5057 load_register (&icnt
, treg
, &imm_expr
, 1);
5062 if (target_big_endian
)
5074 load_register (&icnt
, hreg
, &imm_expr
, 0);
5077 if (offset_expr
.X_op
== O_absent
)
5078 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5082 assert (offset_expr
.X_op
== O_constant
);
5083 load_register (&icnt
, lreg
, &offset_expr
, 0);
5090 /* We know that sym is in the .rdata section. First we get the
5091 upper 16 bits of the address. */
5092 if (mips_pic
== NO_PIC
)
5094 /* FIXME: This won't work for a 64 bit address. */
5095 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5097 else if (mips_pic
== SVR4_PIC
)
5099 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5100 mips_opts
.isa
< 3 ? "lw" : "ld",
5101 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5103 else if (mips_pic
== EMBEDDED_PIC
)
5105 /* For embedded PIC we pick up the entire address off $gp in
5106 a single instruction. */
5107 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5108 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5109 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5110 offset_expr
.X_op
= O_constant
;
5111 offset_expr
.X_add_number
= 0;
5116 /* Now we load the register(s). */
5117 if (mips_opts
.isa
>= 3)
5118 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5119 treg
, (int) BFD_RELOC_LO16
, AT
);
5122 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5123 treg
, (int) BFD_RELOC_LO16
, AT
);
5126 /* FIXME: How in the world do we deal with the possible
5128 offset_expr
.X_add_number
+= 4;
5129 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5130 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5134 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5135 does not become a variant frag. */
5136 frag_wane (frag_now
);
5142 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5143 the entire value, and in mips1 mode it is the high order 32
5144 bits of the value and the low order 32 bits are either zero
5145 or in offset_expr. */
5146 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5148 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5149 if (mips_opts
.isa
>= 3)
5150 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5151 "dmtc1", "t,S", AT
, treg
);
5154 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5155 "mtc1", "t,G", AT
, treg
+ 1);
5156 if (offset_expr
.X_op
== O_absent
)
5157 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5158 "mtc1", "t,G", 0, treg
);
5161 assert (offset_expr
.X_op
== O_constant
);
5162 load_register (&icnt
, AT
, &offset_expr
, 0);
5163 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5164 "mtc1", "t,G", AT
, treg
);
5170 assert (offset_expr
.X_op
== O_symbol
5171 && offset_expr
.X_add_number
== 0);
5172 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5173 if (strcmp (s
, ".lit8") == 0)
5175 if (mips_opts
.isa
>= 2)
5177 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5178 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5182 r
= BFD_RELOC_MIPS_LITERAL
;
5187 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5188 if (mips_pic
== SVR4_PIC
)
5189 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5190 mips_opts
.isa
< 3 ? "lw" : "ld",
5191 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5194 /* FIXME: This won't work for a 64 bit address. */
5195 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5198 if (mips_opts
.isa
>= 2)
5200 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5201 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5203 /* To avoid confusion in tc_gen_reloc, we must ensure
5204 that this does not become a variant frag. */
5205 frag_wane (frag_now
);
5218 as_bad ("opcode not supported on this processor");
5221 /* Even on a big endian machine $fn comes before $fn+1. We have
5222 to adjust when loading from memory. */
5225 assert (mips_opts
.isa
< 2);
5226 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5227 target_big_endian
? treg
+ 1 : treg
,
5229 /* FIXME: A possible overflow which I don't know how to deal
5231 offset_expr
.X_add_number
+= 4;
5232 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5233 target_big_endian
? treg
: treg
+ 1,
5236 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5237 does not become a variant frag. */
5238 frag_wane (frag_now
);
5247 * The MIPS assembler seems to check for X_add_number not
5248 * being double aligned and generating:
5251 * addiu at,at,%lo(foo+1)
5254 * But, the resulting address is the same after relocation so why
5255 * generate the extra instruction?
5259 as_bad ("opcode not supported on this processor");
5262 /* Itbl support may require additional care here. */
5264 if (mips_opts
.isa
>= 2)
5277 as_bad ("opcode not supported on this processor");
5281 if (mips_opts
.isa
>= 2)
5289 /* Itbl support may require additional care here. */
5294 if (mips_opts
.isa
>= 3)
5305 if (mips_opts
.isa
>= 3)
5315 if (offset_expr
.X_op
!= O_symbol
5316 && offset_expr
.X_op
!= O_constant
)
5318 as_bad ("expression too complex");
5319 offset_expr
.X_op
= O_constant
;
5322 /* Even on a big endian machine $fn comes before $fn+1. We have
5323 to adjust when loading from memory. We set coproc if we must
5324 load $fn+1 first. */
5325 /* Itbl support may require additional care here. */
5326 if (! target_big_endian
)
5329 if (mips_pic
== NO_PIC
5330 || offset_expr
.X_op
== O_constant
)
5332 /* If this is a reference to a GP relative symbol, we want
5333 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5334 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5335 If we have a base register, we use this
5337 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5338 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5339 If this is not a GP relative symbol, we want
5340 lui $at,<sym> (BFD_RELOC_HI16_S)
5341 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5342 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5343 If there is a base register, we add it to $at after the
5344 lui instruction. If there is a constant, we always use
5346 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5347 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5366 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5367 mips_opts
.isa
< 3 ? "addu" : "daddu",
5368 "d,v,t", AT
, breg
, GP
);
5374 /* Itbl support may require additional care here. */
5375 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5376 coproc
? treg
+ 1 : treg
,
5377 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5378 offset_expr
.X_add_number
+= 4;
5380 /* Set mips_optimize to 2 to avoid inserting an
5382 hold_mips_optimize
= mips_optimize
;
5384 /* Itbl support may require additional care here. */
5385 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5386 coproc
? treg
: treg
+ 1,
5387 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5388 mips_optimize
= hold_mips_optimize
;
5390 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5391 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5392 used_at
&& mips_opts
.noat
),
5393 offset_expr
.X_add_symbol
, (offsetT
) 0,
5396 /* We just generated two relocs. When tc_gen_reloc
5397 handles this case, it will skip the first reloc and
5398 handle the second. The second reloc already has an
5399 extra addend of 4, which we added above. We must
5400 subtract it out, and then subtract another 4 to make
5401 the first reloc come out right. The second reloc
5402 will come out right because we are going to add 4 to
5403 offset_expr when we build its instruction below.
5405 If we have a symbol, then we don't want to include
5406 the offset, because it will wind up being included
5407 when we generate the reloc. */
5409 if (offset_expr
.X_op
== O_constant
)
5410 offset_expr
.X_add_number
-= 8;
5413 offset_expr
.X_add_number
= -4;
5414 offset_expr
.X_op
= O_constant
;
5417 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5422 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5423 mips_opts
.isa
< 3 ? "addu" : "daddu",
5424 "d,v,t", AT
, breg
, AT
);
5428 /* Itbl support may require additional care here. */
5429 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5430 coproc
? treg
+ 1 : treg
,
5431 (int) BFD_RELOC_LO16
, AT
);
5434 /* FIXME: How do we handle overflow here? */
5435 offset_expr
.X_add_number
+= 4;
5436 /* Itbl support may require additional care here. */
5437 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5438 coproc
? treg
: treg
+ 1,
5439 (int) BFD_RELOC_LO16
, AT
);
5441 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5445 /* If this is a reference to an external symbol, we want
5446 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5451 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5453 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5454 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5455 If there is a base register we add it to $at before the
5456 lwc1 instructions. If there is a constant we include it
5457 in the lwc1 instructions. */
5459 expr1
.X_add_number
= offset_expr
.X_add_number
;
5460 offset_expr
.X_add_number
= 0;
5461 if (expr1
.X_add_number
< -0x8000
5462 || expr1
.X_add_number
>= 0x8000 - 4)
5463 as_bad ("PIC code offset overflow (max 16 signed bits)");
5468 frag_grow (24 + off
);
5469 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5470 mips_opts
.isa
< 3 ? "lw" : "ld",
5471 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5472 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5474 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5475 mips_opts
.isa
< 3 ? "addu" : "daddu",
5476 "d,v,t", AT
, breg
, AT
);
5477 /* Itbl support may require additional care here. */
5478 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5479 coproc
? treg
+ 1 : treg
,
5480 (int) BFD_RELOC_LO16
, AT
);
5481 expr1
.X_add_number
+= 4;
5483 /* Set mips_optimize to 2 to avoid inserting an undesired
5485 hold_mips_optimize
= mips_optimize
;
5487 /* Itbl support may require additional care here. */
5488 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5489 coproc
? treg
: treg
+ 1,
5490 (int) BFD_RELOC_LO16
, AT
);
5491 mips_optimize
= hold_mips_optimize
;
5493 (void) frag_var (rs_machine_dependent
, 0, 0,
5494 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5495 offset_expr
.X_add_symbol
, (offsetT
) 0,
5498 else if (mips_pic
== SVR4_PIC
)
5502 /* If this is a reference to an external symbol, we want
5503 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5505 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5510 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5512 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5513 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5514 If there is a base register we add it to $at before the
5515 lwc1 instructions. If there is a constant we include it
5516 in the lwc1 instructions. */
5518 expr1
.X_add_number
= offset_expr
.X_add_number
;
5519 offset_expr
.X_add_number
= 0;
5520 if (expr1
.X_add_number
< -0x8000
5521 || expr1
.X_add_number
>= 0x8000 - 4)
5522 as_bad ("PIC code offset overflow (max 16 signed bits)");
5523 if (reg_needs_delay (GP
))
5532 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5533 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5534 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5535 mips_opts
.isa
< 3 ? "addu" : "daddu",
5536 "d,v,t", AT
, AT
, GP
);
5537 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5538 mips_opts
.isa
< 3 ? "lw" : "ld",
5539 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5540 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5543 mips_opts
.isa
< 3 ? "addu" : "daddu",
5544 "d,v,t", AT
, breg
, AT
);
5545 /* Itbl support may require additional care here. */
5546 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5547 coproc
? treg
+ 1 : treg
,
5548 (int) BFD_RELOC_LO16
, AT
);
5549 expr1
.X_add_number
+= 4;
5551 /* Set mips_optimize to 2 to avoid inserting an undesired
5553 hold_mips_optimize
= mips_optimize
;
5555 /* Itbl support may require additional care here. */
5556 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5557 coproc
? treg
: treg
+ 1,
5558 (int) BFD_RELOC_LO16
, AT
);
5559 mips_optimize
= hold_mips_optimize
;
5560 expr1
.X_add_number
-= 4;
5562 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5563 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5564 8 + gpdel
+ off
, 1, 0),
5565 offset_expr
.X_add_symbol
, (offsetT
) 0,
5569 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5572 macro_build (p
, &icnt
, &offset_expr
,
5573 mips_opts
.isa
< 3 ? "lw" : "ld",
5574 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5576 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5580 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5581 mips_opts
.isa
< 3 ? "addu" : "daddu",
5582 "d,v,t", AT
, breg
, AT
);
5585 /* Itbl support may require additional care here. */
5586 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5587 coproc
? treg
+ 1 : treg
,
5588 (int) BFD_RELOC_LO16
, AT
);
5590 expr1
.X_add_number
+= 4;
5592 /* Set mips_optimize to 2 to avoid inserting an undesired
5594 hold_mips_optimize
= mips_optimize
;
5596 /* Itbl support may require additional care here. */
5597 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5598 coproc
? treg
: treg
+ 1,
5599 (int) BFD_RELOC_LO16
, AT
);
5600 mips_optimize
= hold_mips_optimize
;
5602 else if (mips_pic
== EMBEDDED_PIC
)
5604 /* If there is no base register, we use
5605 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5606 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5607 If we have a base register, we use
5609 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5610 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5619 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5620 mips_opts
.isa
< 3 ? "addu" : "daddu",
5621 "d,v,t", AT
, breg
, GP
);
5626 /* Itbl support may require additional care here. */
5627 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5628 coproc
? treg
+ 1 : treg
,
5629 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5630 offset_expr
.X_add_number
+= 4;
5631 /* Itbl support may require additional care here. */
5632 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5633 coproc
? treg
: treg
+ 1,
5634 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5650 assert (mips_opts
.isa
< 3);
5651 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5652 (int) BFD_RELOC_LO16
, breg
);
5653 offset_expr
.X_add_number
+= 4;
5654 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5655 (int) BFD_RELOC_LO16
, breg
);
5658 /* New code added to support COPZ instructions.
5659 This code builds table entries out of the macros in mip_opcodes.
5660 R4000 uses interlocks to handle coproc delays.
5661 Other chips (like the R3000) require nops to be inserted for delays.
5663 FIXME: Currently, we require that the user handle delays.
5664 In order to fill delay slots for non-interlocked chips,
5665 we must have a way to specify delays based on the coprocessor.
5666 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5667 What are the side-effects of the cop instruction?
5668 What cache support might we have and what are its effects?
5669 Both coprocessor & memory require delays. how long???
5670 What registers are read/set/modified?
5672 If an itbl is provided to interpret cop instructions,
5673 this knowledge can be encoded in the itbl spec. */
5687 /* For now we just do C (same as Cz). */
5688 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "C");
5691 #ifdef LOSING_COMPILER
5693 /* Try and see if this is a new itbl instruction.
5694 This code builds table entries out of the macros in mip_opcodes.
5695 FIXME: For now we just assemble the expression and pass it's
5696 value along as a 32-bit immediate.
5697 We may want to have the assembler assemble this value,
5698 so that we gain the assembler's knowledge of delay slots,
5700 Would it be more efficient to use mask (id) here? */
5701 if (itbl_have_entries
5702 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5704 s
= ip
->insn_mo
->name
;
5706 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5707 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5714 as_warn ("Macro used $at after \".set noat\"");
5719 struct mips_cl_insn
*ip
;
5721 register int treg
, sreg
, dreg
, breg
;
5736 bfd_reloc_code_real_type r
;
5739 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5740 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5741 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5742 mask
= ip
->insn_mo
->mask
;
5744 expr1
.X_op
= O_constant
;
5745 expr1
.X_op_symbol
= NULL
;
5746 expr1
.X_add_symbol
= NULL
;
5747 expr1
.X_add_number
= 1;
5751 #endif /* LOSING_COMPILER */
5756 macro_build ((char *) NULL
, &icnt
, NULL
,
5757 dbl
? "dmultu" : "multu",
5759 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5765 /* The MIPS assembler some times generates shifts and adds. I'm
5766 not trying to be that fancy. GCC should do this for us
5768 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5769 macro_build ((char *) NULL
, &icnt
, NULL
,
5770 dbl
? "dmult" : "mult",
5772 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5778 mips_emit_delays (true);
5779 ++mips_opts
.noreorder
;
5780 mips_any_noreorder
= 1;
5781 macro_build ((char *) NULL
, &icnt
, NULL
,
5782 dbl
? "dmult" : "mult",
5784 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5785 macro_build ((char *) NULL
, &icnt
, NULL
,
5786 dbl
? "dsra32" : "sra",
5787 "d,w,<", dreg
, dreg
, 31);
5788 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5790 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5793 expr1
.X_add_number
= 8;
5794 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5795 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5796 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5798 --mips_opts
.noreorder
;
5799 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5805 mips_emit_delays (true);
5806 ++mips_opts
.noreorder
;
5807 mips_any_noreorder
= 1;
5808 macro_build ((char *) NULL
, &icnt
, NULL
,
5809 dbl
? "dmultu" : "multu",
5811 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5812 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5814 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5817 expr1
.X_add_number
= 8;
5818 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5819 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5820 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5822 --mips_opts
.noreorder
;
5826 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5827 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5828 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5830 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5834 if (imm_expr
.X_op
!= O_constant
)
5835 as_bad ("rotate count too large");
5836 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5837 (int) (imm_expr
.X_add_number
& 0x1f));
5838 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5839 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5840 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5844 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5845 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5846 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5848 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5852 if (imm_expr
.X_op
!= O_constant
)
5853 as_bad ("rotate count too large");
5854 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5855 (int) (imm_expr
.X_add_number
& 0x1f));
5856 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5857 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5858 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5864 as_bad ("opcode not supported on this processor");
5867 assert (mips_opts
.isa
< 2);
5868 /* Even on a big endian machine $fn comes before $fn+1. We have
5869 to adjust when storing to memory. */
5870 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5871 target_big_endian
? treg
+ 1 : treg
,
5872 (int) BFD_RELOC_LO16
, breg
);
5873 offset_expr
.X_add_number
+= 4;
5874 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5875 target_big_endian
? treg
: treg
+ 1,
5876 (int) BFD_RELOC_LO16
, breg
);
5881 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5882 treg
, (int) BFD_RELOC_LO16
);
5884 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5885 sreg
, (int) BFD_RELOC_LO16
);
5888 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5890 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5891 dreg
, (int) BFD_RELOC_LO16
);
5896 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5898 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5899 sreg
, (int) BFD_RELOC_LO16
);
5904 as_warn ("Instruction %s: result is always false",
5906 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5909 if (imm_expr
.X_op
== O_constant
5910 && imm_expr
.X_add_number
>= 0
5911 && imm_expr
.X_add_number
< 0x10000)
5913 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5914 sreg
, (int) BFD_RELOC_LO16
);
5917 else if (imm_expr
.X_op
== O_constant
5918 && imm_expr
.X_add_number
> -0x8000
5919 && imm_expr
.X_add_number
< 0)
5921 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5922 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5923 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5924 "t,r,j", dreg
, sreg
,
5925 (int) BFD_RELOC_LO16
);
5930 load_register (&icnt
, AT
, &imm_expr
, 0);
5931 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5935 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5936 (int) BFD_RELOC_LO16
);
5941 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5947 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5948 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5949 (int) BFD_RELOC_LO16
);
5952 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5954 if (imm_expr
.X_op
== O_constant
5955 && imm_expr
.X_add_number
>= -0x8000
5956 && imm_expr
.X_add_number
< 0x8000)
5958 macro_build ((char *) NULL
, &icnt
, &expr1
,
5959 mask
== M_SGE_I
? "slti" : "sltiu",
5960 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5965 load_register (&icnt
, AT
, &imm_expr
, 0);
5966 macro_build ((char *) NULL
, &icnt
, NULL
,
5967 mask
== M_SGE_I
? "slt" : "sltu",
5968 "d,v,t", dreg
, sreg
, AT
);
5971 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5972 (int) BFD_RELOC_LO16
);
5977 case M_SGT
: /* sreg > treg <==> treg < sreg */
5983 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5986 case M_SGT_I
: /* sreg > I <==> I < sreg */
5992 load_register (&icnt
, AT
, &imm_expr
, 0);
5993 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5996 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6002 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6003 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6004 (int) BFD_RELOC_LO16
);
6007 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6013 load_register (&icnt
, AT
, &imm_expr
, 0);
6014 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6015 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6016 (int) BFD_RELOC_LO16
);
6020 if (imm_expr
.X_op
== O_constant
6021 && imm_expr
.X_add_number
>= -0x8000
6022 && imm_expr
.X_add_number
< 0x8000)
6024 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6025 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6028 load_register (&icnt
, AT
, &imm_expr
, 0);
6029 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6033 if (imm_expr
.X_op
== O_constant
6034 && imm_expr
.X_add_number
>= -0x8000
6035 && imm_expr
.X_add_number
< 0x8000)
6037 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6038 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6041 load_register (&icnt
, AT
, &imm_expr
, 0);
6042 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6048 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6051 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6055 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6057 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6063 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6065 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6071 as_warn ("Instruction %s: result is always true",
6073 macro_build ((char *) NULL
, &icnt
, &expr1
,
6074 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
6075 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6078 if (imm_expr
.X_op
== O_constant
6079 && imm_expr
.X_add_number
>= 0
6080 && imm_expr
.X_add_number
< 0x10000)
6082 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6083 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6086 else if (imm_expr
.X_op
== O_constant
6087 && imm_expr
.X_add_number
> -0x8000
6088 && imm_expr
.X_add_number
< 0)
6090 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6091 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6092 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
6093 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6098 load_register (&icnt
, AT
, &imm_expr
, 0);
6099 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6103 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6111 if (imm_expr
.X_op
== O_constant
6112 && imm_expr
.X_add_number
> -0x8000
6113 && imm_expr
.X_add_number
<= 0x8000)
6115 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6116 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6117 dbl
? "daddi" : "addi",
6118 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6121 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6122 macro_build ((char *) NULL
, &icnt
, NULL
,
6123 dbl
? "dsub" : "sub",
6124 "d,v,t", dreg
, sreg
, AT
);
6130 if (imm_expr
.X_op
== O_constant
6131 && imm_expr
.X_add_number
> -0x8000
6132 && imm_expr
.X_add_number
<= 0x8000)
6134 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6135 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6136 dbl
? "daddiu" : "addiu",
6137 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6140 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6141 macro_build ((char *) NULL
, &icnt
, NULL
,
6142 dbl
? "dsubu" : "subu",
6143 "d,v,t", dreg
, sreg
, AT
);
6164 load_register (&icnt
, AT
, &imm_expr
, 0);
6165 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6170 assert (mips_opts
.isa
< 2);
6171 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6172 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6175 * Is the double cfc1 instruction a bug in the mips assembler;
6176 * or is there a reason for it?
6178 mips_emit_delays (true);
6179 ++mips_opts
.noreorder
;
6180 mips_any_noreorder
= 1;
6181 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6182 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6183 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6184 expr1
.X_add_number
= 3;
6185 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6186 (int) BFD_RELOC_LO16
);
6187 expr1
.X_add_number
= 2;
6188 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6189 (int) BFD_RELOC_LO16
);
6190 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6191 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6192 macro_build ((char *) NULL
, &icnt
, NULL
,
6193 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6194 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6195 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6196 --mips_opts
.noreorder
;
6205 if (offset_expr
.X_add_number
>= 0x7fff)
6206 as_bad ("operand overflow");
6207 /* avoid load delay */
6208 if (! target_big_endian
)
6209 offset_expr
.X_add_number
+= 1;
6210 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6211 (int) BFD_RELOC_LO16
, breg
);
6212 if (! target_big_endian
)
6213 offset_expr
.X_add_number
-= 1;
6215 offset_expr
.X_add_number
+= 1;
6216 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6217 (int) BFD_RELOC_LO16
, breg
);
6218 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6219 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6232 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6233 as_bad ("operand overflow");
6234 if (! target_big_endian
)
6235 offset_expr
.X_add_number
+= off
;
6236 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6237 (int) BFD_RELOC_LO16
, breg
);
6238 if (! target_big_endian
)
6239 offset_expr
.X_add_number
-= off
;
6241 offset_expr
.X_add_number
+= off
;
6242 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6243 (int) BFD_RELOC_LO16
, breg
);
6256 load_address (&icnt
, AT
, &offset_expr
);
6258 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6259 mips_opts
.isa
< 3 ? "addu" : "daddu",
6260 "d,v,t", AT
, AT
, breg
);
6261 if (! target_big_endian
)
6262 expr1
.X_add_number
= off
;
6264 expr1
.X_add_number
= 0;
6265 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6266 (int) BFD_RELOC_LO16
, AT
);
6267 if (! target_big_endian
)
6268 expr1
.X_add_number
= 0;
6270 expr1
.X_add_number
= off
;
6271 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6272 (int) BFD_RELOC_LO16
, AT
);
6277 load_address (&icnt
, AT
, &offset_expr
);
6279 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6280 mips_opts
.isa
< 3 ? "addu" : "daddu",
6281 "d,v,t", AT
, AT
, breg
);
6282 if (target_big_endian
)
6283 expr1
.X_add_number
= 0;
6284 macro_build ((char *) NULL
, &icnt
, &expr1
,
6285 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6286 (int) BFD_RELOC_LO16
, AT
);
6287 if (target_big_endian
)
6288 expr1
.X_add_number
= 1;
6290 expr1
.X_add_number
= 0;
6291 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6292 (int) BFD_RELOC_LO16
, AT
);
6293 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6295 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6300 if (offset_expr
.X_add_number
>= 0x7fff)
6301 as_bad ("operand overflow");
6302 if (target_big_endian
)
6303 offset_expr
.X_add_number
+= 1;
6304 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6305 (int) BFD_RELOC_LO16
, breg
);
6306 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6307 if (target_big_endian
)
6308 offset_expr
.X_add_number
-= 1;
6310 offset_expr
.X_add_number
+= 1;
6311 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6312 (int) BFD_RELOC_LO16
, breg
);
6325 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6326 as_bad ("operand overflow");
6327 if (! target_big_endian
)
6328 offset_expr
.X_add_number
+= off
;
6329 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6330 (int) BFD_RELOC_LO16
, breg
);
6331 if (! target_big_endian
)
6332 offset_expr
.X_add_number
-= off
;
6334 offset_expr
.X_add_number
+= off
;
6335 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6336 (int) BFD_RELOC_LO16
, breg
);
6349 load_address (&icnt
, AT
, &offset_expr
);
6351 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6352 mips_opts
.isa
< 3 ? "addu" : "daddu",
6353 "d,v,t", AT
, AT
, breg
);
6354 if (! target_big_endian
)
6355 expr1
.X_add_number
= off
;
6357 expr1
.X_add_number
= 0;
6358 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6359 (int) BFD_RELOC_LO16
, AT
);
6360 if (! target_big_endian
)
6361 expr1
.X_add_number
= 0;
6363 expr1
.X_add_number
= off
;
6364 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6365 (int) BFD_RELOC_LO16
, AT
);
6369 load_address (&icnt
, AT
, &offset_expr
);
6371 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6372 mips_opts
.isa
< 3 ? "addu" : "daddu",
6373 "d,v,t", AT
, AT
, breg
);
6374 if (! target_big_endian
)
6375 expr1
.X_add_number
= 0;
6376 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6377 (int) BFD_RELOC_LO16
, AT
);
6378 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6380 if (! target_big_endian
)
6381 expr1
.X_add_number
= 1;
6383 expr1
.X_add_number
= 0;
6384 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6385 (int) BFD_RELOC_LO16
, AT
);
6386 if (! target_big_endian
)
6387 expr1
.X_add_number
= 0;
6389 expr1
.X_add_number
= 1;
6390 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6391 (int) BFD_RELOC_LO16
, AT
);
6392 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6394 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6399 /* FIXME: Check if this is one of the itbl macros, since they
6400 are added dynamically. */
6401 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6405 as_warn ("Macro used $at after \".set noat\"");
6408 /* Implement macros in mips16 mode. */
6412 struct mips_cl_insn
*ip
;
6415 int xreg
, yreg
, zreg
, tmp
;
6419 const char *s
, *s2
, *s3
;
6421 mask
= ip
->insn_mo
->mask
;
6423 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6424 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6425 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6429 expr1
.X_op
= O_constant
;
6430 expr1
.X_op_symbol
= NULL
;
6431 expr1
.X_add_symbol
= NULL
;
6432 expr1
.X_add_number
= 1;
6451 mips_emit_delays (true);
6452 ++mips_opts
.noreorder
;
6453 mips_any_noreorder
= 1;
6454 macro_build ((char *) NULL
, &icnt
, NULL
,
6455 dbl
? "ddiv" : "div",
6456 "0,x,y", xreg
, yreg
);
6457 expr1
.X_add_number
= 2;
6458 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6459 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6460 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6461 since that causes an overflow. We should do that as well,
6462 but I don't see how to do the comparisons without a temporary
6464 --mips_opts
.noreorder
;
6465 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6484 mips_emit_delays (true);
6485 ++mips_opts
.noreorder
;
6486 mips_any_noreorder
= 1;
6487 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6488 expr1
.X_add_number
= 2;
6489 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6490 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6491 --mips_opts
.noreorder
;
6492 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6498 macro_build ((char *) NULL
, &icnt
, NULL
,
6499 dbl
? "dmultu" : "multu",
6501 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6509 if (imm_expr
.X_op
!= O_constant
)
6510 as_bad ("Unsupported large constant");
6511 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6512 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6513 dbl
? "daddiu" : "addiu",
6514 "y,x,4", yreg
, xreg
);
6518 if (imm_expr
.X_op
!= O_constant
)
6519 as_bad ("Unsupported large constant");
6520 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6521 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6526 if (imm_expr
.X_op
!= O_constant
)
6527 as_bad ("Unsupported large constant");
6528 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6529 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6552 goto do_reverse_branch
;
6556 goto do_reverse_branch
;
6568 goto do_reverse_branch
;
6579 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6581 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6608 goto do_addone_branch_i
;
6613 goto do_addone_branch_i
;
6628 goto do_addone_branch_i
;
6635 if (imm_expr
.X_op
!= O_constant
)
6636 as_bad ("Unsupported large constant");
6637 ++imm_expr
.X_add_number
;
6640 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6641 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6645 expr1
.X_add_number
= 0;
6646 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6648 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6649 "move", "y,X", xreg
, yreg
);
6650 expr1
.X_add_number
= 2;
6651 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6652 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6653 "neg", "x,w", xreg
, xreg
);
6657 /* For consistency checking, verify that all bits are specified either
6658 by the match/mask part of the instruction definition, or by the
6661 validate_mips_insn (opc
)
6662 const struct mips_opcode
*opc
;
6664 const char *p
= opc
->args
;
6666 unsigned long used_bits
= opc
->mask
;
6668 if ((used_bits
& opc
->match
) != opc
->match
)
6670 as_bad ("internal: bad mips opcode (mask error): %s %s",
6671 opc
->name
, opc
->args
);
6674 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6681 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6682 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6684 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6685 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6686 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6687 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6689 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6692 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6693 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6694 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6695 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6696 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6697 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6698 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6699 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6700 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6701 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6702 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6704 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6705 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6706 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6707 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6709 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6710 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6711 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6712 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6713 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6714 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6715 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6716 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6719 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6720 /* start-sanitize-vr5400 */
6721 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
6722 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
6725 /* end-sanitize-vr5400 */
6727 as_bad ("internal: bad mips opcode (unknown operand type `%c'): %s %s",
6728 c
, opc
->name
, opc
->args
);
6732 /* Some of the trapping instructions (break, t*, sdbbp) have "code"
6733 fields that cannot currently be set by assembly code. Ignore them
6735 if (opc
->pinfo
& INSN_TRAP
)
6737 static const char *const trap_insns
[] = {
6739 "teq", "tge", "tgeu", "tlt", "tltu", "tne",
6742 for (i
= sizeof(trap_insns
)/sizeof(trap_insns
[0]) - 1; i
>= 0; i
--)
6743 if (!strcmp (trap_insns
[i
], opc
->name
))
6745 used_bits
|= 0xffc0;
6749 if (used_bits
!= 0xffffffff)
6751 as_bad ("internal: bad mips opcode (bits 0x%lx undefined): %s %s",
6752 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6758 /* This routine assembles an instruction into its binary format. As a
6759 side effect, it sets one of the global variables imm_reloc or
6760 offset_reloc to the type of relocation to do if one of the operands
6761 is an address expression. */
6766 struct mips_cl_insn
*ip
;
6771 struct mips_opcode
*insn
;
6774 unsigned int lastregno
= 0;
6779 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6784 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6786 insn_error
= "unrecognized opcode";
6795 assert (strcmp (insn
->name
, str
) == 0);
6797 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
6799 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
6801 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
6803 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
6808 if (insn_isa
<= mips_opts
.isa
)
6810 else if (insn
->pinfo
== INSN_MACRO
)
6812 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
6813 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
6814 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
6815 /* start-sanitize-tx49 */
6816 || (mips_4900
&& (insn
->membership
& INSN_4900
) != 0)
6817 /* end-sanitize-tx49 */
6818 /* start-sanitize-r5900 */
6819 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
6820 /* end-sanitize-r5900 */
6821 /* start-sanitize-vr5400 */
6822 || (mips_5400
&& (insn
->membership
& INSN_5400
) != 0)
6823 /* end-sanitize-vr5400 */
6824 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
6829 if (insn
->pinfo
!= INSN_MACRO
)
6831 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
6833 /* start-sanitize-r5900 */
6834 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
6836 /* end-sanitize-r5900 */
6841 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6842 && strcmp (insn
->name
, insn
[1].name
) == 0)
6848 || insn_isa
<= mips_opts
.isa
)
6849 insn_error
= "opcode not supported on this processor";
6852 static char buf
[100];
6854 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6861 ip
->insn_opcode
= insn
->match
;
6862 for (args
= insn
->args
;; ++args
)
6868 case '\0': /* end of args */
6881 ip
->insn_opcode
|= lastregno
<< 21;
6886 ip
->insn_opcode
|= lastregno
<< 16;
6890 ip
->insn_opcode
|= lastregno
<< 11;
6896 /* handle optional base register.
6897 Either the base register is omitted or
6898 we must have a left paren. */
6899 /* this is dependent on the next operand specifier
6900 is a 'b' for base register */
6901 assert (args
[1] == 'b');
6905 case ')': /* these must match exactly */
6906 /* start-sanitize-vr5400 */
6909 /* end-sanitize-vr5400 */
6914 case '<': /* must be at least one digit */
6916 * According to the manual, if the shift amount is greater
6917 * than 31 or less than 0 the the shift amount should be
6918 * mod 32. In reality the mips assembler issues an error.
6919 * We issue a warning and mask out all but the low 5 bits.
6921 my_getExpression (&imm_expr
, s
);
6922 check_absolute_expr (ip
, &imm_expr
);
6923 if ((unsigned long) imm_expr
.X_add_number
> 31)
6925 as_warn ("Improper shift amount (%ld)",
6926 (long) imm_expr
.X_add_number
);
6927 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6929 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6930 imm_expr
.X_op
= O_absent
;
6934 case '>': /* shift amount minus 32 */
6935 my_getExpression (&imm_expr
, s
);
6936 check_absolute_expr (ip
, &imm_expr
);
6937 if ((unsigned long) imm_expr
.X_add_number
< 32
6938 || (unsigned long) imm_expr
.X_add_number
> 63)
6940 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6941 imm_expr
.X_op
= O_absent
;
6945 case 'k': /* cache code */
6946 case 'h': /* prefx code */
6947 my_getExpression (&imm_expr
, s
);
6948 check_absolute_expr (ip
, &imm_expr
);
6949 if ((unsigned long) imm_expr
.X_add_number
> 31)
6951 as_warn ("Invalid value for `%s' (%lu)",
6953 (unsigned long) imm_expr
.X_add_number
);
6954 imm_expr
.X_add_number
&= 0x1f;
6957 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6959 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6960 imm_expr
.X_op
= O_absent
;
6964 case 'c': /* break code */
6965 my_getExpression (&imm_expr
, s
);
6966 check_absolute_expr (ip
, &imm_expr
);
6967 if ((unsigned) imm_expr
.X_add_number
> 1023)
6968 as_warn ("Illegal break code (%ld)",
6969 (long) imm_expr
.X_add_number
);
6970 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6971 imm_expr
.X_op
= O_absent
;
6975 case 'B': /* syscall code */
6976 my_getExpression (&imm_expr
, s
);
6977 check_absolute_expr (ip
, &imm_expr
);
6978 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6979 as_warn ("Illegal syscall code (%ld)",
6980 (long) imm_expr
.X_add_number
);
6981 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6982 imm_expr
.X_op
= O_absent
;
6986 case 'C': /* Coprocessor code */
6987 my_getExpression (&imm_expr
, s
);
6988 check_absolute_expr (ip
, &imm_expr
);
6989 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6991 as_warn ("Coproccesor code > 25 bits (%ld)",
6992 (long) imm_expr
.X_add_number
);
6993 imm_expr
.X_add_number
&= ((1<<25) - 1);
6995 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6996 imm_expr
.X_op
= O_absent
;
7000 case 'b': /* base register */
7001 case 'd': /* destination register */
7002 case 's': /* source register */
7003 case 't': /* target register */
7004 case 'r': /* both target and source */
7005 case 'v': /* both dest and source */
7006 case 'w': /* both dest and target */
7007 case 'E': /* coprocessor target register */
7008 case 'G': /* coprocessor destination register */
7009 case 'x': /* ignore register name */
7010 case 'z': /* must be zero register */
7011 case 'P': /* performance register */
7025 while (isdigit (*s
));
7027 as_bad ("Invalid register number (%d)", regno
);
7029 else if (*args
== 'E' || *args
== 'G')
7033 if (s
[1] == 'f' && s
[2] == 'p')
7038 else if (s
[1] == 's' && s
[2] == 'p')
7043 else if (s
[1] == 'g' && s
[2] == 'p')
7048 else if (s
[1] == 'a' && s
[2] == 't')
7053 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7058 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7063 else if (itbl_have_entries
)
7068 p
= s
+1; /* advance past '$' */
7069 n
= itbl_get_field (&p
); /* n is name */
7071 /* See if this is a register defined in an
7073 r
= itbl_get_reg_val (n
);
7076 /* Get_field advances to the start of
7077 the next field, so we need to back
7078 rack to the end of the last field. */
7082 s
= strchr (s
,'\0');
7096 as_warn ("Used $at without \".set noat\"");
7102 if (c
== 'r' || c
== 'v' || c
== 'w')
7109 /* 'z' only matches $0. */
7110 if (c
== 'z' && regno
!= 0)
7113 /* Now that we have assembled one operand, we use the args string
7114 * to figure out where it goes in the instruction. */
7121 ip
->insn_opcode
|= regno
<< 21;
7125 ip
->insn_opcode
|= regno
<< 11;
7130 ip
->insn_opcode
|= regno
<< 16;
7133 /* This case exists because on the r3000 trunc
7134 expands into a macro which requires a gp
7135 register. On the r6000 or r4000 it is
7136 assembled into a single instruction which
7137 ignores the register. Thus the insn version
7138 is MIPS_ISA2 and uses 'x', and the macro
7139 version is MIPS_ISA1 and uses 't'. */
7142 /* This case is for the div instruction, which
7143 acts differently if the destination argument
7144 is $0. This only matches $0, and is checked
7145 outside the switch. */
7148 /* Itbl operand; not yet implemented. FIXME ?? */
7151 ip
->insn_opcode
|= regno
<< 1;
7153 /* What about all other operands like 'i', which
7154 can be specified in the opcode table? */
7164 ip
->insn_opcode
|= lastregno
<< 21;
7167 ip
->insn_opcode
|= lastregno
<< 16;
7172 case 'D': /* floating point destination register */
7173 case 'S': /* floating point source register */
7174 case 'T': /* floating point target register */
7175 case 'R': /* floating point source register */
7179 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7189 while (isdigit (*s
));
7192 as_bad ("Invalid float register number (%d)", regno
);
7194 if ((regno
& 1) != 0
7195 && mips_opts
.isa
< 3
7196 && ! (strcmp (str
, "mtc1") == 0
7197 || strcmp (str
, "mfc1") == 0
7198 || strcmp (str
, "lwc1") == 0
7199 || strcmp (str
, "swc1") == 0
7200 || strcmp (str
, "l.s") == 0
7201 || strcmp (str
, "s.s") == 0))
7202 as_warn ("Float register should be even, was %d",
7210 if (c
== 'V' || c
== 'W')
7220 ip
->insn_opcode
|= regno
<< 6;
7224 ip
->insn_opcode
|= regno
<< 11;
7228 ip
->insn_opcode
|= regno
<< 16;
7231 ip
->insn_opcode
|= regno
<< 21;
7240 ip
->insn_opcode
|= lastregno
<< 11;
7243 ip
->insn_opcode
|= lastregno
<< 16;
7249 my_getExpression (&imm_expr
, s
);
7250 if (imm_expr
.X_op
!= O_big
7251 && imm_expr
.X_op
!= O_constant
)
7252 insn_error
= "absolute expression required";
7257 my_getExpression (&offset_expr
, s
);
7258 imm_reloc
= BFD_RELOC_32
;
7270 unsigned char temp
[8];
7272 unsigned int length
;
7277 /* These only appear as the last operand in an
7278 instruction, and every instruction that accepts
7279 them in any variant accepts them in all variants.
7280 This means we don't have to worry about backing out
7281 any changes if the instruction does not match.
7283 The difference between them is the size of the
7284 floating point constant and where it goes. For 'F'
7285 and 'L' the constant is 64 bits; for 'f' and 'l' it
7286 is 32 bits. Where the constant is placed is based
7287 on how the MIPS assembler does things:
7290 f -- immediate value
7293 The .lit4 and .lit8 sections are only used if
7294 permitted by the -G argument.
7296 When generating embedded PIC code, we use the
7297 .lit8 section but not the .lit4 section (we can do
7298 .lit4 inline easily; we need to put .lit8
7299 somewhere in the data segment, and using .lit8
7300 permits the linker to eventually combine identical
7303 f64
= *args
== 'F' || *args
== 'L';
7305 save_in
= input_line_pointer
;
7306 input_line_pointer
= s
;
7307 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7309 s
= input_line_pointer
;
7310 input_line_pointer
= save_in
;
7311 if (err
!= NULL
&& *err
!= '\0')
7313 as_bad ("Bad floating point constant: %s", err
);
7314 memset (temp
, '\0', sizeof temp
);
7315 length
= f64
? 8 : 4;
7318 assert (length
== (f64
? 8 : 4));
7322 && (! USE_GLOBAL_POINTER_OPT
7323 || mips_pic
== EMBEDDED_PIC
7324 || g_switch_value
< 4
7325 || (temp
[0] == 0 && temp
[1] == 0)
7326 || (temp
[2] == 0 && temp
[3] == 0))))
7328 imm_expr
.X_op
= O_constant
;
7329 if (! target_big_endian
)
7330 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7332 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7335 && ((temp
[0] == 0 && temp
[1] == 0)
7336 || (temp
[2] == 0 && temp
[3] == 0))
7337 && ((temp
[4] == 0 && temp
[5] == 0)
7338 || (temp
[6] == 0 && temp
[7] == 0)))
7340 /* The value is simple enough to load with a
7341 couple of instructions. In mips1 mode, set
7342 imm_expr to the high order 32 bits and
7343 offset_expr to the low order 32 bits.
7344 Otherwise, set imm_expr to the entire 64 bit
7346 if (mips_opts
.isa
< 3)
7348 imm_expr
.X_op
= O_constant
;
7349 offset_expr
.X_op
= O_constant
;
7350 if (! target_big_endian
)
7352 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7353 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7357 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7358 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7360 if (offset_expr
.X_add_number
== 0)
7361 offset_expr
.X_op
= O_absent
;
7363 else if (sizeof (imm_expr
.X_add_number
) > 4)
7365 imm_expr
.X_op
= O_constant
;
7366 if (! target_big_endian
)
7367 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7369 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7373 imm_expr
.X_op
= O_big
;
7374 imm_expr
.X_add_number
= 4;
7375 if (! target_big_endian
)
7377 generic_bignum
[0] = bfd_getl16 (temp
);
7378 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7379 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7380 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7384 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7385 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7386 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7387 generic_bignum
[3] = bfd_getb16 (temp
);
7393 const char *newname
;
7396 /* Switch to the right section. */
7398 subseg
= now_subseg
;
7401 default: /* unused default case avoids warnings. */
7403 newname
= RDATA_SECTION_NAME
;
7404 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7408 newname
= RDATA_SECTION_NAME
;
7411 assert (!USE_GLOBAL_POINTER_OPT
7412 || g_switch_value
>= 4);
7416 new_seg
= subseg_new (newname
, (subsegT
) 0);
7417 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7418 bfd_set_section_flags (stdoutput
, new_seg
,
7423 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7424 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7425 && strcmp (TARGET_OS
, "elf") != 0)
7426 record_alignment (new_seg
, 4);
7428 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7430 as_bad ("Can't use floating point insn in this section");
7432 /* Set the argument to the current address in the
7434 offset_expr
.X_op
= O_symbol
;
7435 offset_expr
.X_add_symbol
=
7436 symbol_new ("L0\001", now_seg
,
7437 (valueT
) frag_now_fix (), frag_now
);
7438 offset_expr
.X_add_number
= 0;
7440 /* Put the floating point number into the section. */
7441 p
= frag_more ((int) length
);
7442 memcpy (p
, temp
, length
);
7444 /* Switch back to the original section. */
7445 subseg_set (seg
, subseg
);
7450 case 'i': /* 16 bit unsigned immediate */
7451 case 'j': /* 16 bit signed immediate */
7452 imm_reloc
= BFD_RELOC_LO16
;
7453 c
= my_getSmallExpression (&imm_expr
, s
);
7458 if (imm_expr
.X_op
== O_constant
)
7459 imm_expr
.X_add_number
=
7460 (imm_expr
.X_add_number
>> 16) & 0xffff;
7463 imm_reloc
= BFD_RELOC_HI16_S
;
7464 imm_unmatched_hi
= true;
7467 imm_reloc
= BFD_RELOC_HI16
;
7472 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7473 || ((imm_expr
.X_add_number
< 0
7474 || imm_expr
.X_add_number
>= 0x10000)
7475 && imm_expr
.X_op
== O_constant
))
7477 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7478 !strcmp (insn
->name
, insn
[1].name
))
7480 if (imm_expr
.X_op
!= O_constant
7481 && imm_expr
.X_op
!= O_big
)
7482 insn_error
= "absolute expression required";
7484 as_bad ("16 bit expression not in range 0..65535");
7492 /* The upper bound should be 0x8000, but
7493 unfortunately the MIPS assembler accepts numbers
7494 from 0x8000 to 0xffff and sign extends them, and
7495 we want to be compatible. We only permit this
7496 extended range for an instruction which does not
7497 provide any further alternates, since those
7498 alternates may handle other cases. People should
7499 use the numbers they mean, rather than relying on
7500 a mysterious sign extension. */
7501 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7502 strcmp (insn
->name
, insn
[1].name
) == 0);
7507 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7508 || ((imm_expr
.X_add_number
< -0x8000
7509 || imm_expr
.X_add_number
>= max
)
7510 && imm_expr
.X_op
== O_constant
)
7512 && imm_expr
.X_add_number
< 0
7513 && mips_opts
.isa
>= 3
7514 && imm_expr
.X_unsigned
7515 && sizeof (imm_expr
.X_add_number
) <= 4))
7519 if (imm_expr
.X_op
!= O_constant
7520 && imm_expr
.X_op
!= O_big
)
7521 insn_error
= "absolute expression required";
7523 as_bad ("16 bit expression not in range -32768..32767");
7529 case 'o': /* 16 bit offset */
7530 c
= my_getSmallExpression (&offset_expr
, s
);
7532 /* If this value won't fit into a 16 bit offset, then go
7533 find a macro that will generate the 32 bit offset
7534 code pattern. As a special hack, we accept the
7535 difference of two local symbols as a constant. This
7536 is required to suppose embedded PIC switches, which
7537 use an instruction which looks like
7538 lw $4,$L12-$LS12($4)
7539 The problem with handling this in a more general
7540 fashion is that the macro function doesn't expect to
7541 see anything which can be handled in a single
7542 constant instruction. */
7544 && (offset_expr
.X_op
!= O_constant
7545 || offset_expr
.X_add_number
>= 0x8000
7546 || offset_expr
.X_add_number
< -0x8000)
7547 && (mips_pic
!= EMBEDDED_PIC
7548 || offset_expr
.X_op
!= O_subtract
7549 || now_seg
!= text_section
7550 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7554 offset_reloc
= BFD_RELOC_LO16
;
7555 if (c
== 'h' || c
== 'H')
7557 assert (offset_expr
.X_op
== O_constant
);
7558 offset_expr
.X_add_number
=
7559 (offset_expr
.X_add_number
>> 16) & 0xffff;
7564 case 'p': /* pc relative offset */
7565 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7566 my_getExpression (&offset_expr
, s
);
7570 case 'u': /* upper 16 bits */
7571 c
= my_getSmallExpression (&imm_expr
, s
);
7572 if (imm_expr
.X_op
== O_constant
7573 && (imm_expr
.X_add_number
< 0
7574 || imm_expr
.X_add_number
>= 0x10000))
7575 as_bad ("lui expression not in range 0..65535");
7576 imm_reloc
= BFD_RELOC_LO16
;
7581 if (imm_expr
.X_op
== O_constant
)
7582 imm_expr
.X_add_number
=
7583 (imm_expr
.X_add_number
>> 16) & 0xffff;
7586 imm_reloc
= BFD_RELOC_HI16_S
;
7587 imm_unmatched_hi
= true;
7590 imm_reloc
= BFD_RELOC_HI16
;
7596 case 'a': /* 26 bit address */
7597 my_getExpression (&offset_expr
, s
);
7599 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7602 case 'N': /* 3 bit branch condition code */
7603 case 'M': /* 3 bit compare condition code */
7604 if (strncmp (s
, "$fcc", 4) != 0)
7614 while (isdigit (*s
));
7616 as_bad ("invalid condition code register $fcc%d", regno
);
7618 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7620 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7623 /* start-sanitize-vr5400 */
7624 case 'e': /* must be at least one digit */
7625 my_getExpression (&imm_expr
, s
);
7626 check_absolute_expr (ip
, &imm_expr
);
7627 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECBYTE
)
7629 as_bad ("bad byte vector index (%ld)",
7630 (long) imm_expr
.X_add_number
);
7631 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
7633 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
7634 imm_expr
.X_op
= O_absent
;
7639 my_getExpression (&imm_expr
, s
);
7640 check_absolute_expr (ip
, &imm_expr
);
7641 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECALIGN
)
7643 as_bad ("bad byte vector index (%ld)",
7644 (long) imm_expr
.X_add_number
);
7645 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
7647 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
7648 imm_expr
.X_op
= O_absent
;
7652 /* end-sanitize-vr5400 */
7654 as_bad ("bad char = '%c'\n", *args
);
7659 /* Args don't match. */
7660 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7661 !strcmp (insn
->name
, insn
[1].name
))
7667 insn_error
= "illegal operands";
7672 /* This routine assembles an instruction into its binary format when
7673 assembling for the mips16. As a side effect, it sets one of the
7674 global variables imm_reloc or offset_reloc to the type of
7675 relocation to do if one of the operands is an address expression.
7676 It also sets mips16_small and mips16_ext if the user explicitly
7677 requested a small or extended instruction. */
7682 struct mips_cl_insn
*ip
;
7686 struct mips_opcode
*insn
;
7689 unsigned int lastregno
= 0;
7694 mips16_small
= false;
7697 for (s
= str
; islower (*s
); ++s
)
7709 if (s
[1] == 't' && s
[2] == ' ')
7712 mips16_small
= true;
7716 else if (s
[1] == 'e' && s
[2] == ' ')
7725 insn_error
= "unknown opcode";
7729 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7730 mips16_small
= true;
7732 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7734 insn_error
= "unrecognized opcode";
7741 assert (strcmp (insn
->name
, str
) == 0);
7744 ip
->insn_opcode
= insn
->match
;
7745 ip
->use_extend
= false;
7746 imm_expr
.X_op
= O_absent
;
7747 imm_reloc
= BFD_RELOC_UNUSED
;
7748 offset_expr
.X_op
= O_absent
;
7749 offset_reloc
= BFD_RELOC_UNUSED
;
7750 for (args
= insn
->args
; 1; ++args
)
7757 /* In this switch statement we call break if we did not find
7758 a match, continue if we did find a match, or return if we
7767 /* Stuff the immediate value in now, if we can. */
7768 if (imm_expr
.X_op
== O_constant
7769 && imm_reloc
> BFD_RELOC_UNUSED
7770 && insn
->pinfo
!= INSN_MACRO
)
7772 mips16_immed ((char *) NULL
, 0,
7773 imm_reloc
- BFD_RELOC_UNUSED
,
7774 imm_expr
.X_add_number
, true, mips16_small
,
7775 mips16_ext
, &ip
->insn_opcode
,
7776 &ip
->use_extend
, &ip
->extend
);
7777 imm_expr
.X_op
= O_absent
;
7778 imm_reloc
= BFD_RELOC_UNUSED
;
7792 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7795 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7811 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7813 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7840 while (isdigit (*s
));
7843 as_bad ("invalid register number (%d)", regno
);
7849 if (s
[1] == 'f' && s
[2] == 'p')
7854 else if (s
[1] == 's' && s
[2] == 'p')
7859 else if (s
[1] == 'g' && s
[2] == 'p')
7864 else if (s
[1] == 'a' && s
[2] == 't')
7869 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7874 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7887 if (c
== 'v' || c
== 'w')
7889 regno
= mips16_to_32_reg_map
[lastregno
];
7903 regno
= mips32_to_16_reg_map
[regno
];
7908 regno
= ILLEGAL_REG
;
7913 regno
= ILLEGAL_REG
;
7918 regno
= ILLEGAL_REG
;
7923 if (regno
== AT
&& ! mips_opts
.noat
)
7924 as_warn ("used $at without \".set noat\"");
7931 if (regno
== ILLEGAL_REG
)
7938 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7942 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7945 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7948 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7954 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7957 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7958 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7968 if (strncmp (s
, "$pc", 3) == 0)
7992 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7994 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7995 and generate the appropriate reloc. If the text
7996 inside %gprel is not a symbol name with an
7997 optional offset, then we generate a normal reloc
7998 and will probably fail later. */
7999 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8000 if (imm_expr
.X_op
== O_symbol
)
8003 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8005 ip
->use_extend
= true;
8012 /* Just pick up a normal expression. */
8013 my_getExpression (&imm_expr
, s
);
8016 if (imm_expr
.X_op
== O_register
)
8018 /* What we thought was an expression turned out to
8021 if (s
[0] == '(' && args
[1] == '(')
8023 /* It looks like the expression was omitted
8024 before a register indirection, which means
8025 that the expression is implicitly zero. We
8026 still set up imm_expr, so that we handle
8027 explicit extensions correctly. */
8028 imm_expr
.X_op
= O_constant
;
8029 imm_expr
.X_add_number
= 0;
8030 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8037 /* We need to relax this instruction. */
8038 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8047 /* We use offset_reloc rather than imm_reloc for the PC
8048 relative operands. This lets macros with both
8049 immediate and address operands work correctly. */
8050 my_getExpression (&offset_expr
, s
);
8052 if (offset_expr
.X_op
== O_register
)
8055 /* We need to relax this instruction. */
8056 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8060 case '6': /* break code */
8061 my_getExpression (&imm_expr
, s
);
8062 check_absolute_expr (ip
, &imm_expr
);
8063 if ((unsigned long) imm_expr
.X_add_number
> 63)
8065 as_warn ("Invalid value for `%s' (%lu)",
8067 (unsigned long) imm_expr
.X_add_number
);
8068 imm_expr
.X_add_number
&= 0x3f;
8070 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8071 imm_expr
.X_op
= O_absent
;
8075 case 'a': /* 26 bit address */
8076 my_getExpression (&offset_expr
, s
);
8078 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8079 ip
->insn_opcode
<<= 16;
8082 case 'l': /* register list for entry macro */
8083 case 'L': /* register list for exit macro */
8093 int freg
, reg1
, reg2
;
8095 while (*s
== ' ' || *s
== ',')
8099 as_bad ("can't parse register list");
8111 while (isdigit (*s
))
8133 as_bad ("invalid register list");
8138 while (isdigit (*s
))
8145 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8150 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8155 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8156 mask
|= (reg2
- 3) << 3;
8157 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8158 mask
|= (reg2
- 15) << 1;
8159 else if (reg1
== 31 && reg2
== 31)
8163 as_bad ("invalid register list");
8167 /* The mask is filled in in the opcode table for the
8168 benefit of the disassembler. We remove it before
8169 applying the actual mask. */
8170 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8171 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8175 case 'e': /* extend code */
8176 my_getExpression (&imm_expr
, s
);
8177 check_absolute_expr (ip
, &imm_expr
);
8178 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8180 as_warn ("Invalid value for `%s' (%lu)",
8182 (unsigned long) imm_expr
.X_add_number
);
8183 imm_expr
.X_add_number
&= 0x7ff;
8185 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8186 imm_expr
.X_op
= O_absent
;
8196 /* Args don't match. */
8197 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8198 strcmp (insn
->name
, insn
[1].name
) == 0)
8205 insn_error
= "illegal operands";
8211 /* This structure holds information we know about a mips16 immediate
8214 struct mips16_immed_operand
8216 /* The type code used in the argument string in the opcode table. */
8218 /* The number of bits in the short form of the opcode. */
8220 /* The number of bits in the extended form of the opcode. */
8222 /* The amount by which the short form is shifted when it is used;
8223 for example, the sw instruction has a shift count of 2. */
8225 /* The amount by which the short form is shifted when it is stored
8226 into the instruction code. */
8228 /* Non-zero if the short form is unsigned. */
8230 /* Non-zero if the extended form is unsigned. */
8232 /* Non-zero if the value is PC relative. */
8236 /* The mips16 immediate operand types. */
8238 static const struct mips16_immed_operand mips16_immed_operands
[] =
8240 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8241 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8242 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8243 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8244 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8245 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8246 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8247 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8248 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8249 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8250 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8251 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8252 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8253 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8254 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8255 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8256 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8257 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8258 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8259 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8260 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8263 #define MIPS16_NUM_IMMED \
8264 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8266 /* Handle a mips16 instruction with an immediate value. This or's the
8267 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8268 whether an extended value is needed; if one is needed, it sets
8269 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8270 If SMALL is true, an unextended opcode was explicitly requested.
8271 If EXT is true, an extended opcode was explicitly requested. If
8272 WARN is true, warn if EXT does not match reality. */
8275 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8284 unsigned long *insn
;
8285 boolean
*use_extend
;
8286 unsigned short *extend
;
8288 register const struct mips16_immed_operand
*op
;
8289 int mintiny
, maxtiny
;
8292 op
= mips16_immed_operands
;
8293 while (op
->type
!= type
)
8296 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8301 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8304 maxtiny
= 1 << op
->nbits
;
8309 maxtiny
= (1 << op
->nbits
) - 1;
8314 mintiny
= - (1 << (op
->nbits
- 1));
8315 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8318 /* Branch offsets have an implicit 0 in the lowest bit. */
8319 if (type
== 'p' || type
== 'q')
8322 if ((val
& ((1 << op
->shift
) - 1)) != 0
8323 || val
< (mintiny
<< op
->shift
)
8324 || val
> (maxtiny
<< op
->shift
))
8329 if (warn
&& ext
&& ! needext
)
8330 as_warn_where (file
, line
, "extended operand requested but not required");
8331 if (small
&& needext
)
8332 as_bad_where (file
, line
, "invalid unextended operand value");
8334 if (small
|| (! ext
&& ! needext
))
8338 *use_extend
= false;
8339 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8340 insnval
<<= op
->op_shift
;
8345 long minext
, maxext
;
8351 maxext
= (1 << op
->extbits
) - 1;
8355 minext
= - (1 << (op
->extbits
- 1));
8356 maxext
= (1 << (op
->extbits
- 1)) - 1;
8358 if (val
< minext
|| val
> maxext
)
8359 as_bad_where (file
, line
,
8360 "operand value out of range for instruction");
8363 if (op
->extbits
== 16)
8365 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8368 else if (op
->extbits
== 15)
8370 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8375 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8379 *extend
= (unsigned short) extval
;
8388 my_getSmallExpression (ep
, str
)
8399 ((str
[1] == 'h' && str
[2] == 'i')
8400 || (str
[1] == 'H' && str
[2] == 'I')
8401 || (str
[1] == 'l' && str
[2] == 'o'))
8413 * A small expression may be followed by a base register.
8414 * Scan to the end of this operand, and then back over a possible
8415 * base register. Then scan the small expression up to that
8416 * point. (Based on code in sparc.c...)
8418 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8420 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8422 if (isdigit (sp
[-2]))
8424 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8426 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8432 else if (sp
- 5 >= str
8435 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8436 || (sp
[-3] == 's' && sp
[-2] == 'p')
8437 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8438 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8444 /* no expression means zero offset */
8447 /* %xx(reg) is an error */
8448 ep
->X_op
= O_absent
;
8453 ep
->X_op
= O_constant
;
8456 ep
->X_add_symbol
= NULL
;
8457 ep
->X_op_symbol
= NULL
;
8458 ep
->X_add_number
= 0;
8463 my_getExpression (ep
, str
);
8470 my_getExpression (ep
, str
);
8471 return c
; /* => %hi or %lo encountered */
8475 my_getExpression (ep
, str
)
8481 save_in
= input_line_pointer
;
8482 input_line_pointer
= str
;
8484 expr_end
= input_line_pointer
;
8485 input_line_pointer
= save_in
;
8487 /* If we are in mips16 mode, and this is an expression based on `.',
8488 then we bump the value of the symbol by 1 since that is how other
8489 text symbols are handled. We don't bother to handle complex
8490 expressions, just `.' plus or minus a constant. */
8491 if (mips_opts
.mips16
8492 && ep
->X_op
== O_symbol
8493 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8494 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8495 && ep
->X_add_symbol
->sy_frag
== frag_now
8496 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
8497 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
8498 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8501 /* Turn a string in input_line_pointer into a floating point constant
8502 of type type, and store the appropriate bytes in *litP. The number
8503 of LITTLENUMS emitted is stored in *sizeP . An error message is
8504 returned, or NULL on OK. */
8507 md_atof (type
, litP
, sizeP
)
8513 LITTLENUM_TYPE words
[4];
8529 return "bad call to md_atof";
8532 t
= atof_ieee (input_line_pointer
, type
, words
);
8534 input_line_pointer
= t
;
8538 if (! target_big_endian
)
8540 for (i
= prec
- 1; i
>= 0; i
--)
8542 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8548 for (i
= 0; i
< prec
; i
++)
8550 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8559 md_number_to_chars (buf
, val
, n
)
8564 if (target_big_endian
)
8565 number_to_chars_bigendian (buf
, val
, n
);
8567 number_to_chars_littleendian (buf
, val
, n
);
8570 CONST
char *md_shortopts
= "O::g::G:";
8572 struct option md_longopts
[] = {
8573 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8574 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8575 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8576 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8577 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8578 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8579 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8580 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8581 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8582 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8583 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8584 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8585 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8586 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8587 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8588 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8589 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8590 {"break", no_argument
, NULL
, OPTION_BREAK
},
8591 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8592 #define OPTION_EB (OPTION_MD_BASE + 11)
8593 {"EB", no_argument
, NULL
, OPTION_EB
},
8594 #define OPTION_EL (OPTION_MD_BASE + 12)
8595 {"EL", no_argument
, NULL
, OPTION_EL
},
8596 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8597 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8598 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8599 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8600 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8601 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8602 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8603 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8604 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8605 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8606 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8607 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8608 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8609 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8610 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8611 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8612 /* start-sanitize-r5900 */
8613 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8614 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8615 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8616 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8617 /* end-sanitize-r5900 */
8618 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8619 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8620 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8621 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8623 /* start-sanitize-tx19 */
8624 {"m1900", no_argument
, NULL
, OPTION_M3900
},
8625 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
8626 /* end-sanitize-tx19 */
8628 /* start-sanitize-vr5400 */
8629 #define OPTION_M5400 (OPTION_MD_BASE + 28)
8630 {"m5400", no_argument
, NULL
, OPTION_M5400
},
8631 #define OPTION_NO_M5400 (OPTION_MD_BASE + 29)
8632 {"no-m5400", no_argument
, NULL
, OPTION_NO_M5400
},
8634 /* end-sanitize-vr5400 */
8635 /* start-sanitize-tx49 */
8636 #define OPTION_M4900 (OPTION_MD_BASE + 30)
8637 {"m4900", no_argument
, NULL
, OPTION_M4900
},
8638 #define OPTION_NO_M4900 (OPTION_MD_BASE + 31)
8639 {"no-m4900", no_argument
, NULL
, OPTION_NO_M4900
},
8641 /* end-sanitize-tx49 */
8642 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8643 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8644 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8645 #define OPTION_32 (OPTION_MD_BASE + 20)
8646 #define OPTION_64 (OPTION_MD_BASE + 21)
8648 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8649 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8650 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8651 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8652 {"32", no_argument
, NULL
, OPTION_32
},
8653 {"64", no_argument
, NULL
, OPTION_64
},
8656 {NULL
, no_argument
, NULL
, 0}
8658 size_t md_longopts_size
= sizeof(md_longopts
);
8661 md_parse_option (c
, arg
)
8676 target_big_endian
= 1;
8680 target_big_endian
= 0;
8684 if (arg
&& arg
[1] == '0')
8694 mips_debug
= atoi (arg
);
8695 /* When the MIPS assembler sees -g or -g2, it does not do
8696 optimizations which limit full symbolic debugging. We take
8697 that to be equivalent to -O0. */
8698 if (mips_debug
== 2)
8722 /* Identify the processor type */
8724 if (strcmp (p
, "default") == 0
8725 || strcmp (p
, "DEFAULT") == 0)
8731 /* We need to cope with the various "vr" prefixes for the 4300
8733 if (*p
== 'v' || *p
== 'V')
8739 if (*p
== 'r' || *p
== 'R')
8746 if (strcmp (p
, "10000") == 0
8747 || strcmp (p
, "10k") == 0
8748 || strcmp (p
, "10K") == 0)
8750 /* start-sanitize-tx19 */
8751 else if (strcmp (p
, "1900") == 0)
8753 /* end-sanitize-tx19 */
8757 if (strcmp (p
, "2000") == 0
8758 || strcmp (p
, "2k") == 0
8759 || strcmp (p
, "2K") == 0)
8764 if (strcmp (p
, "3000") == 0
8765 || strcmp (p
, "3k") == 0
8766 || strcmp (p
, "3K") == 0)
8768 else if (strcmp (p
, "3900") == 0)
8773 if (strcmp (p
, "4000") == 0
8774 || strcmp (p
, "4k") == 0
8775 || strcmp (p
, "4K") == 0)
8777 else if (strcmp (p
, "4100") == 0)
8779 else if (strcmp (p
, "4300") == 0)
8781 else if (strcmp (p
, "4400") == 0)
8783 else if (strcmp (p
, "4600") == 0)
8785 else if (strcmp (p
, "4650") == 0)
8787 /* start-sanitize-tx49 */
8788 else if (strcmp (p
, "4900") == 0)
8790 /* end-sanitize-tx49 */
8791 else if (strcmp (p
, "4010") == 0)
8796 if (strcmp (p
, "5000") == 0
8797 || strcmp (p
, "5k") == 0
8798 || strcmp (p
, "5K") == 0)
8800 /* start-sanitize-vr5400 */
8801 else if (strcmp (p
, "5400") == 0)
8803 /* end-sanitize-vr5400 */
8804 /* start-sanitize-r5900 */
8805 else if (strcmp (p
, "5900") == 0)
8807 /* end-sanitize-r5900 */
8811 if (strcmp (p
, "6000") == 0
8812 || strcmp (p
, "6k") == 0
8813 || strcmp (p
, "6K") == 0)
8818 if (strcmp (p
, "8000") == 0
8819 || strcmp (p
, "8k") == 0
8820 || strcmp (p
, "8K") == 0)
8825 if (strcmp (p
, "orion") == 0)
8831 && (mips_cpu
!= 4300
8833 /* start-sanitize-vr5400 */
8835 /* end-sanitize-vr5400 */
8836 && mips_cpu
!= 5000))
8838 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8844 as_bad ("invalid architecture -mcpu=%s", arg
);
8855 case OPTION_NO_M4650
:
8863 case OPTION_NO_M4010
:
8871 case OPTION_NO_M4100
:
8875 /* start-sanitize-r5900 */
8880 case OPTION_NO_M5900
:
8883 /* end-sanitize-r5900 */
8885 /* start-sanitize-vr5400 */
8890 case OPTION_NO_M5400
:
8894 /* end-sanitize-vr5400 */
8899 case OPTION_NO_M3900
:
8903 /* start-sanitize-tx49 */
8908 case OPTION_NO_M4900
:
8912 /* end-sanitize-tx49 */
8914 mips_opts
.mips16
= 1;
8915 mips_no_prev_insn (false);
8918 case OPTION_NO_MIPS16
:
8919 mips_opts
.mips16
= 0;
8920 mips_no_prev_insn (false);
8923 case OPTION_MEMBEDDED_PIC
:
8924 mips_pic
= EMBEDDED_PIC
;
8925 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8927 as_bad ("-G may not be used with embedded PIC code");
8930 g_switch_value
= 0x7fffffff;
8933 /* When generating ELF code, we permit -KPIC and -call_shared to
8934 select SVR4_PIC, and -non_shared to select no PIC. This is
8935 intended to be compatible with Irix 5. */
8936 case OPTION_CALL_SHARED
:
8937 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8939 as_bad ("-call_shared is supported only for ELF format");
8942 mips_pic
= SVR4_PIC
;
8943 if (g_switch_seen
&& g_switch_value
!= 0)
8945 as_bad ("-G may not be used with SVR4 PIC code");
8951 case OPTION_NON_SHARED
:
8952 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8954 as_bad ("-non_shared is supported only for ELF format");
8960 /* The -xgot option tells the assembler to use 32 offsets when
8961 accessing the got in SVR4_PIC mode. It is for Irix
8968 if (! USE_GLOBAL_POINTER_OPT
)
8970 as_bad ("-G is not supported for this configuration");
8973 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8975 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8979 g_switch_value
= atoi (arg
);
8983 /* The -32 and -64 options tell the assembler to output the 32
8984 bit or the 64 bit MIPS ELF format. */
8991 const char **list
, **l
;
8993 list
= bfd_target_list ();
8994 for (l
= list
; *l
!= NULL
; l
++)
8995 if (strcmp (*l
, "elf64-bigmips") == 0
8996 || strcmp (*l
, "elf64-littlemips") == 0)
8999 as_fatal ("No compiled in support for 64 bit object file format");
9013 md_show_usage (stream
)
9018 -membedded-pic generate embedded position independent code\n\
9019 -EB generate big endian output\n\
9020 -EL generate little endian output\n\
9021 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9022 -G NUM allow referencing objects up to NUM bytes\n\
9023 implicitly with the gp register [default 8]\n");
9025 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
9026 -mips2, -mcpu=r6000 generate code for r6000\n\
9027 -mips3, -mcpu=r4000 generate code for r4000\n\
9028 -mips4, -mcpu=r8000 generate code for r8000\n\
9029 -mcpu=vr4300 generate code for vr4300\n\
9030 -mcpu=vr4100 generate code for vr4100\n\
9031 -m4650 permit R4650 instructions\n\
9032 -no-m4650 do not permit R4650 instructions\n\
9033 -m4010 permit R4010 instructions\n\
9034 -no-m4010 do not permit R4010 instructions\n\
9035 -m4100 permit VR4100 instructions\n\
9036 -no-m4100 do not permit VR4100 instructions\n");
9038 -mips16 generate mips16 instructions\n\
9039 -no-mips16 do not generate mips16 instructions\n");
9041 -O0 remove unneeded NOPs, do not swap branches\n\
9042 -O remove unneeded NOPs and swap branches\n\
9043 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9044 --break, --no-trap break exception on div by 0 and mult overflow\n");
9047 -KPIC, -call_shared generate SVR4 position independent code\n\
9048 -non_shared do not generate position independent code\n\
9049 -xgot assume a 32 bit GOT\n\
9050 -32 create 32 bit object file (default)\n\
9051 -64 create 64 bit object file\n");
9056 mips_init_after_args ()
9058 /* initialize opcodes */
9059 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9060 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9064 md_pcrel_from (fixP
)
9067 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9068 && fixP
->fx_addsy
!= (symbolS
*) NULL
9069 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9071 /* This makes a branch to an undefined symbol be a branch to the
9072 current location. */
9076 /* return the address of the delay slot */
9077 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9080 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9081 reloc for a cons. We could use the definition there, except that
9082 we want to handle 64 bit relocs specially. */
9085 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9088 unsigned int nbytes
;
9092 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9094 if (nbytes
== 8 && ! mips_64
)
9096 if (target_big_endian
)
9102 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9103 as_bad ("Unsupported reloc size %d", nbytes
);
9105 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9108 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9111 /* This is called before the symbol table is processed. In order to
9112 work with gcc when using mips-tfile, we must keep all local labels.
9113 However, in other cases, we want to discard them. If we were
9114 called with -g, but we didn't see any debugging information, it may
9115 mean that gcc is smuggling debugging information through to
9116 mips-tfile, in which case we must generate all local labels. */
9119 mips_frob_file_before_adjust ()
9121 #ifndef NO_ECOFF_DEBUGGING
9124 && ! ecoff_debugging_seen
)
9125 flag_keep_locals
= 1;
9129 /* Sort any unmatched HI16_S relocs so that they immediately precede
9130 the corresponding LO reloc. This is called before md_apply_fix and
9131 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9132 explicit use of the %hi modifier. */
9137 struct mips_hi_fixup
*l
;
9139 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9141 segment_info_type
*seginfo
;
9144 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9146 /* Check quickly whether the next fixup happens to be a matching
9148 if (l
->fixp
->fx_next
!= NULL
9149 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9150 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9151 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9154 /* Look through the fixups for this segment for a matching %lo.
9155 When we find one, move the %hi just in front of it. We do
9156 this in two passes. In the first pass, we try to find a
9157 unique %lo. In the second pass, we permit multiple %hi
9158 relocs for a single %lo (this is a GNU extension). */
9159 seginfo
= seg_info (l
->seg
);
9160 for (pass
= 0; pass
< 2; pass
++)
9165 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9167 /* Check whether this is a %lo fixup which matches l->fixp. */
9168 if (f
->fx_r_type
== BFD_RELOC_LO16
9169 && f
->fx_addsy
== l
->fixp
->fx_addsy
9170 && f
->fx_offset
== l
->fixp
->fx_offset
9173 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9174 || prev
->fx_addsy
!= f
->fx_addsy
9175 || prev
->fx_offset
!= f
->fx_offset
))
9179 /* Move l->fixp before f. */
9180 for (pf
= &seginfo
->fix_root
;
9182 pf
= &(*pf
)->fx_next
)
9183 assert (*pf
!= NULL
);
9185 *pf
= l
->fixp
->fx_next
;
9187 l
->fixp
->fx_next
= f
;
9189 seginfo
->fix_root
= l
->fixp
;
9191 prev
->fx_next
= l
->fixp
;
9203 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9204 "Unmatched %%hi reloc");
9209 /* When generating embedded PIC code we need to use a special
9210 relocation to represent the difference of two symbols in the .text
9211 section (switch tables use a difference of this sort). See
9212 include/coff/mips.h for details. This macro checks whether this
9213 fixup requires the special reloc. */
9214 #define SWITCH_TABLE(fixp) \
9215 ((fixp)->fx_r_type == BFD_RELOC_32 \
9216 && (fixp)->fx_addsy != NULL \
9217 && (fixp)->fx_subsy != NULL \
9218 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9219 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9221 /* When generating embedded PIC code we must keep all PC relative
9222 relocations, in case the linker has to relax a call. We also need
9223 to keep relocations for switch table entries. */
9227 mips_force_relocation (fixp
)
9230 return (mips_pic
== EMBEDDED_PIC
9232 || SWITCH_TABLE (fixp
)
9233 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9234 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9237 /* Apply a fixup to the object file. */
9240 md_apply_fix (fixP
, valueP
)
9247 assert (fixP
->fx_size
== 4
9248 || fixP
->fx_r_type
== BFD_RELOC_16
9249 || fixP
->fx_r_type
== BFD_RELOC_64
);
9253 /* If we aren't adjusting this fixup to be against the section
9254 symbol, we need to adjust the value. */
9256 if (fixP
->fx_addsy
!= NULL
9257 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
9258 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
9260 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9261 if (value
!= 0 && ! fixP
->fx_pcrel
)
9263 /* In this case, the bfd_install_relocation routine will
9264 incorrectly add the symbol value back in. We just want
9265 the addend to appear in the object file. */
9266 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9271 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9273 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9276 switch (fixP
->fx_r_type
)
9278 case BFD_RELOC_MIPS_JMP
:
9279 case BFD_RELOC_HI16
:
9280 case BFD_RELOC_HI16_S
:
9281 case BFD_RELOC_MIPS_GPREL
:
9282 case BFD_RELOC_MIPS_LITERAL
:
9283 case BFD_RELOC_MIPS_CALL16
:
9284 case BFD_RELOC_MIPS_GOT16
:
9285 case BFD_RELOC_MIPS_GPREL32
:
9286 case BFD_RELOC_MIPS_GOT_HI16
:
9287 case BFD_RELOC_MIPS_GOT_LO16
:
9288 case BFD_RELOC_MIPS_CALL_HI16
:
9289 case BFD_RELOC_MIPS_CALL_LO16
:
9290 case BFD_RELOC_MIPS16_GPREL
:
9292 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9293 "Invalid PC relative reloc");
9294 /* Nothing needed to do. The value comes from the reloc entry */
9297 case BFD_RELOC_MIPS16_JMP
:
9298 /* We currently always generate a reloc against a symbol, which
9299 means that we don't want an addend even if the symbol is
9301 fixP
->fx_addnumber
= 0;
9304 case BFD_RELOC_PCREL_HI16_S
:
9305 /* The addend for this is tricky if it is internal, so we just
9306 do everything here rather than in bfd_install_relocation. */
9307 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9309 /* For an external symbol adjust by the address to make it
9310 pcrel_offset. We use the address of the RELLO reloc
9311 which follows this one. */
9312 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9313 + fixP
->fx_next
->fx_where
);
9318 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9319 if (target_big_endian
)
9321 md_number_to_chars (buf
, value
, 2);
9324 case BFD_RELOC_PCREL_LO16
:
9325 /* The addend for this is tricky if it is internal, so we just
9326 do everything here rather than in bfd_install_relocation. */
9327 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9328 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9329 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9330 if (target_big_endian
)
9332 md_number_to_chars (buf
, value
, 2);
9336 /* This is handled like BFD_RELOC_32, but we output a sign
9337 extended value if we are only 32 bits. */
9339 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9341 if (8 <= sizeof (valueT
))
9342 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9349 w1
= w2
= fixP
->fx_where
;
9350 if (target_big_endian
)
9354 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9355 if ((value
& 0x80000000) != 0)
9359 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9365 /* If we are deleting this reloc entry, we must fill in the
9366 value now. This can happen if we have a .word which is not
9367 resolved when it appears but is later defined. We also need
9368 to fill in the value if this is an embedded PIC switch table
9371 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9372 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9377 /* If we are deleting this reloc entry, we must fill in the
9379 assert (fixP
->fx_size
== 2);
9381 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9385 case BFD_RELOC_LO16
:
9386 /* When handling an embedded PIC switch statement, we can wind
9387 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9390 if (value
< -0x8000 || value
> 0x7fff)
9391 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9392 "relocation overflow");
9393 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9394 if (target_big_endian
)
9396 md_number_to_chars (buf
, value
, 2);
9400 case BFD_RELOC_16_PCREL_S2
:
9402 * We need to save the bits in the instruction since fixup_segment()
9403 * might be deleting the relocation entry (i.e., a branch within
9404 * the current segment).
9406 if ((value
& 0x3) != 0)
9407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9408 "Branch to odd address (%lx)", value
);
9411 /* update old instruction data */
9412 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9413 if (target_big_endian
)
9414 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9416 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9418 if (value
>= -0x8000 && value
< 0x8000)
9419 insn
|= value
& 0xffff;
9422 /* The branch offset is too large. If this is an
9423 unconditional branch, and we are not generating PIC code,
9424 we can convert it to an absolute jump instruction. */
9425 if (mips_pic
== NO_PIC
9427 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9428 && (fixP
->fx_frag
->fr_address
9429 < text_section
->vma
+ text_section
->_raw_size
)
9430 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9431 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9432 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9434 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9435 insn
= 0x0c000000; /* jal */
9437 insn
= 0x08000000; /* j */
9438 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9440 fixP
->fx_addsy
= section_symbol (text_section
);
9441 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9445 /* FIXME. It would be possible in principle to handle
9446 conditional branches which overflow. They could be
9447 transformed into a branch around a jump. This would
9448 require setting up variant frags for each different
9449 branch type. The native MIPS assembler attempts to
9450 handle these cases, but it appears to do it
9452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9453 "Branch out of range");
9457 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9472 const struct mips_opcode
*p
;
9473 int treg
, sreg
, dreg
, shamt
;
9478 for (i
= 0; i
< NUMOPCODES
; ++i
)
9480 p
= &mips_opcodes
[i
];
9481 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9483 printf ("%08lx %s\t", oc
, p
->name
);
9484 treg
= (oc
>> 16) & 0x1f;
9485 sreg
= (oc
>> 21) & 0x1f;
9486 dreg
= (oc
>> 11) & 0x1f;
9487 shamt
= (oc
>> 6) & 0x1f;
9489 for (args
= p
->args
;; ++args
)
9500 printf ("%c", *args
);
9504 assert (treg
== sreg
);
9505 printf ("$%d,$%d", treg
, sreg
);
9510 printf ("$%d", dreg
);
9515 printf ("$%d", treg
);
9519 printf ("0x%x", treg
);
9524 printf ("$%d", sreg
);
9528 printf ("0x%08lx", oc
& 0x1ffffff);
9540 printf ("$%d", shamt
);
9551 printf ("%08lx UNDEFINED\n", oc
);
9562 name
= input_line_pointer
;
9563 c
= get_symbol_end ();
9564 p
= (symbolS
*) symbol_find_or_make (name
);
9565 *input_line_pointer
= c
;
9569 /* Align the current frag to a given power of two. The MIPS assembler
9570 also automatically adjusts any preceding label. */
9573 mips_align (to
, fill
, label
)
9578 mips_emit_delays (false);
9579 frag_align (to
, fill
, 0);
9580 record_alignment (now_seg
, to
);
9583 assert (S_GET_SEGMENT (label
) == now_seg
);
9584 label
->sy_frag
= frag_now
;
9585 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9589 /* Align to a given power of two. .align 0 turns off the automatic
9590 alignment used by the data creating pseudo-ops. */
9597 register long temp_fill
;
9598 long max_alignment
= 15;
9602 o Note that the assembler pulls down any immediately preceeding label
9603 to the aligned address.
9604 o It's not documented but auto alignment is reinstated by
9605 a .align pseudo instruction.
9606 o Note also that after auto alignment is turned off the mips assembler
9607 issues an error on attempt to assemble an improperly aligned data item.
9612 temp
= get_absolute_expression ();
9613 if (temp
> max_alignment
)
9614 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9617 as_warn ("Alignment negative: 0 assumed.");
9620 if (*input_line_pointer
== ',')
9622 input_line_pointer
++;
9623 temp_fill
= get_absolute_expression ();
9630 mips_align (temp
, (int) temp_fill
,
9631 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9638 demand_empty_rest_of_line ();
9642 mips_flush_pending_output ()
9644 mips_emit_delays (false);
9645 mips_clear_insn_labels ();
9654 /* When generating embedded PIC code, we only use the .text, .lit8,
9655 .sdata and .sbss sections. We change the .data and .rdata
9656 pseudo-ops to use .sdata. */
9657 if (mips_pic
== EMBEDDED_PIC
9658 && (sec
== 'd' || sec
== 'r'))
9662 /* The ELF backend needs to know that we are changing sections, so
9663 that .previous works correctly. We could do something like check
9664 for a obj_section_change_hook macro, but that might be confusing
9665 as it would not be appropriate to use it in the section changing
9666 functions in read.c, since obj-elf.c intercepts those. FIXME:
9667 This should be cleaner, somehow. */
9668 obj_elf_section_change_hook ();
9671 mips_emit_delays (false);
9681 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9682 demand_empty_rest_of_line ();
9686 if (USE_GLOBAL_POINTER_OPT
)
9688 seg
= subseg_new (RDATA_SECTION_NAME
,
9689 (subsegT
) get_absolute_expression ());
9690 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9692 bfd_set_section_flags (stdoutput
, seg
,
9698 if (strcmp (TARGET_OS
, "elf") != 0)
9699 bfd_set_section_alignment (stdoutput
, seg
, 4);
9701 demand_empty_rest_of_line ();
9705 as_bad ("No read only data section in this object file format");
9706 demand_empty_rest_of_line ();
9712 if (USE_GLOBAL_POINTER_OPT
)
9714 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9715 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9717 bfd_set_section_flags (stdoutput
, seg
,
9718 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9720 if (strcmp (TARGET_OS
, "elf") != 0)
9721 bfd_set_section_alignment (stdoutput
, seg
, 4);
9723 demand_empty_rest_of_line ();
9728 as_bad ("Global pointers not supported; recompile -G 0");
9729 demand_empty_rest_of_line ();
9738 mips_enable_auto_align ()
9749 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9750 mips_emit_delays (false);
9751 if (log_size
> 0 && auto_align
)
9752 mips_align (log_size
, 0, label
);
9753 mips_clear_insn_labels ();
9754 cons (1 << log_size
);
9763 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9765 mips_emit_delays (false);
9769 mips_align (3, 0, label
);
9771 mips_align (2, 0, label
);
9773 mips_clear_insn_labels ();
9778 /* Handle .globl. We need to override it because on Irix 5 you are
9781 where foo is an undefined symbol, to mean that foo should be
9782 considered to be the address of a function. */
9793 name
= input_line_pointer
;
9794 c
= get_symbol_end ();
9795 symbolP
= symbol_find_or_make (name
);
9796 *input_line_pointer
= c
;
9799 /* On Irix 5, every global symbol that is not explicitly labelled as
9800 being a function is apparently labelled as being an object. */
9803 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9808 secname
= input_line_pointer
;
9809 c
= get_symbol_end ();
9810 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9812 as_bad ("%s: no such section", secname
);
9813 *input_line_pointer
= c
;
9815 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9816 flag
= BSF_FUNCTION
;
9819 symbolP
->bsym
->flags
|= flag
;
9821 S_SET_EXTERNAL (symbolP
);
9822 demand_empty_rest_of_line ();
9832 opt
= input_line_pointer
;
9833 c
= get_symbol_end ();
9837 /* FIXME: What does this mean? */
9839 else if (strncmp (opt
, "pic", 3) == 0)
9847 mips_pic
= SVR4_PIC
;
9849 as_bad (".option pic%d not supported", i
);
9851 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9853 if (g_switch_seen
&& g_switch_value
!= 0)
9854 as_warn ("-G may not be used with SVR4 PIC code");
9856 bfd_set_gp_size (stdoutput
, 0);
9860 as_warn ("Unrecognized option \"%s\"", opt
);
9862 *input_line_pointer
= c
;
9863 demand_empty_rest_of_line ();
9866 /* This structure is used to hold a stack of .set values. */
9868 struct mips_option_stack
9870 struct mips_option_stack
*next
;
9871 struct mips_set_options options
;
9874 static struct mips_option_stack
*mips_opts_stack
;
9876 /* Handle the .set pseudo-op. */
9882 char *name
= input_line_pointer
, ch
;
9884 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9885 input_line_pointer
++;
9886 ch
= *input_line_pointer
;
9887 *input_line_pointer
= '\0';
9889 if (strcmp (name
, "reorder") == 0)
9891 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
9893 /* If we still have pending nops, we can discard them. The
9894 usual nop handling will insert any that are still
9896 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9897 * (mips_opts
.mips16
? 2 : 4));
9898 prev_nop_frag
= NULL
;
9900 mips_opts
.noreorder
= 0;
9902 else if (strcmp (name
, "noreorder") == 0)
9904 mips_emit_delays (true);
9905 mips_opts
.noreorder
= 1;
9906 mips_any_noreorder
= 1;
9908 else if (strcmp (name
, "at") == 0)
9912 else if (strcmp (name
, "noat") == 0)
9916 else if (strcmp (name
, "macro") == 0)
9918 mips_opts
.warn_about_macros
= 0;
9920 else if (strcmp (name
, "nomacro") == 0)
9922 if (mips_opts
.noreorder
== 0)
9923 as_bad ("`noreorder' must be set before `nomacro'");
9924 mips_opts
.warn_about_macros
= 1;
9926 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9928 mips_opts
.nomove
= 0;
9930 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9932 mips_opts
.nomove
= 1;
9934 else if (strcmp (name
, "bopt") == 0)
9936 mips_opts
.nobopt
= 0;
9938 else if (strcmp (name
, "nobopt") == 0)
9940 mips_opts
.nobopt
= 1;
9942 else if (strcmp (name
, "mips16") == 0
9943 || strcmp (name
, "MIPS-16") == 0)
9944 mips_opts
.mips16
= 1;
9945 else if (strcmp (name
, "nomips16") == 0
9946 || strcmp (name
, "noMIPS-16") == 0)
9947 mips_opts
.mips16
= 0;
9948 else if (strncmp (name
, "mips", 4) == 0)
9952 /* Permit the user to change the ISA on the fly. Needless to
9953 say, misuse can cause serious problems. */
9954 isa
= atoi (name
+ 4);
9956 mips_opts
.isa
= file_mips_isa
;
9957 else if (isa
< 1 || isa
> 4)
9958 as_bad ("unknown ISA level");
9960 mips_opts
.isa
= isa
;
9962 else if (strcmp (name
, "autoextend") == 0)
9963 mips_opts
.noautoextend
= 0;
9964 else if (strcmp (name
, "noautoextend") == 0)
9965 mips_opts
.noautoextend
= 1;
9966 else if (strcmp (name
, "push") == 0)
9968 struct mips_option_stack
*s
;
9970 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
9971 s
->next
= mips_opts_stack
;
9972 s
->options
= mips_opts
;
9973 mips_opts_stack
= s
;
9975 else if (strcmp (name
, "pop") == 0)
9977 struct mips_option_stack
*s
;
9979 s
= mips_opts_stack
;
9981 as_bad (".set pop with no .set push");
9984 /* If we're changing the reorder mode we need to handle
9985 delay slots correctly. */
9986 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
9987 mips_emit_delays (true);
9988 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
9990 if (prev_nop_frag
!= NULL
)
9992 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9993 * (mips_opts
.mips16
? 2 : 4));
9994 prev_nop_frag
= NULL
;
9998 mips_opts
= s
->options
;
9999 mips_opts_stack
= s
->next
;
10005 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
10007 *input_line_pointer
= ch
;
10008 demand_empty_rest_of_line ();
10011 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10012 .option pic2. It means to generate SVR4 PIC calls. */
10015 s_abicalls (ignore
)
10018 mips_pic
= SVR4_PIC
;
10019 if (USE_GLOBAL_POINTER_OPT
)
10021 if (g_switch_seen
&& g_switch_value
!= 0)
10022 as_warn ("-G may not be used with SVR4 PIC code");
10023 g_switch_value
= 0;
10025 bfd_set_gp_size (stdoutput
, 0);
10026 demand_empty_rest_of_line ();
10029 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10030 PIC code. It sets the $gp register for the function based on the
10031 function address, which is in the register named in the argument.
10032 This uses a relocation against _gp_disp, which is handled specially
10033 by the linker. The result is:
10034 lui $gp,%hi(_gp_disp)
10035 addiu $gp,$gp,%lo(_gp_disp)
10036 addu $gp,$gp,.cpload argument
10037 The .cpload argument is normally $25 == $t9. */
10046 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10047 if (mips_pic
!= SVR4_PIC
)
10053 /* .cpload should be a in .set noreorder section. */
10054 if (mips_opts
.noreorder
== 0)
10055 as_warn (".cpload not in noreorder section");
10057 ex
.X_op
= O_symbol
;
10058 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10059 ex
.X_op_symbol
= NULL
;
10060 ex
.X_add_number
= 0;
10062 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10063 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
10065 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10066 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10067 (int) BFD_RELOC_LO16
);
10069 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10070 GP
, GP
, tc_get_register (0));
10072 demand_empty_rest_of_line ();
10075 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10076 offset from $sp. The offset is remembered, and after making a PIC
10077 call $gp is restored from that location. */
10080 s_cprestore (ignore
)
10086 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10087 if (mips_pic
!= SVR4_PIC
)
10093 mips_cprestore_offset
= get_absolute_expression ();
10095 ex
.X_op
= O_constant
;
10096 ex
.X_add_symbol
= NULL
;
10097 ex
.X_op_symbol
= NULL
;
10098 ex
.X_add_number
= mips_cprestore_offset
;
10100 macro_build ((char *) NULL
, &icnt
, &ex
,
10101 mips_opts
.isa
< 3 ? "sw" : "sd",
10102 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10104 demand_empty_rest_of_line ();
10107 /* Handle the .gpword pseudo-op. This is used when generating PIC
10108 code. It generates a 32 bit GP relative reloc. */
10118 /* When not generating PIC code, this is treated as .word. */
10119 if (mips_pic
!= SVR4_PIC
)
10125 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10126 mips_emit_delays (true);
10128 mips_align (2, 0, label
);
10129 mips_clear_insn_labels ();
10133 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10135 as_bad ("Unsupported use of .gpword");
10136 ignore_rest_of_line ();
10140 md_number_to_chars (p
, (valueT
) 0, 4);
10141 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10142 BFD_RELOC_MIPS_GPREL32
);
10144 demand_empty_rest_of_line ();
10147 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10148 tables in SVR4 PIC code. */
10157 /* This is ignored when not generating SVR4 PIC code. */
10158 if (mips_pic
!= SVR4_PIC
)
10164 /* Add $gp to the register named as an argument. */
10165 reg
= tc_get_register (0);
10166 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10167 mips_opts
.isa
< 3 ? "addu" : "daddu",
10168 "d,v,t", reg
, reg
, GP
);
10170 demand_empty_rest_of_line ();
10173 /* Handle the .insn pseudo-op. This marks instruction labels in
10174 mips16 mode. This permits the linker to handle them specially,
10175 such as generating jalx instructions when needed. We also make
10176 them odd for the duration of the assembly, in order to generate the
10177 right sort of code. We will make them even in the adjust_symtab
10178 routine, while leaving them marked. This is convenient for the
10179 debugger and the disassembler. The linker knows to make them odd
10186 if (mips_opts
.mips16
)
10187 mips16_mark_labels ();
10189 demand_empty_rest_of_line ();
10192 /* Handle a .stabn directive. We need these in order to mark a label
10193 as being a mips16 text label correctly. Sometimes the compiler
10194 will emit a label, followed by a .stabn, and then switch sections.
10195 If the label and .stabn are in mips16 mode, then the label is
10196 really a mips16 text label. */
10202 if (type
== 'n' && mips_opts
.mips16
)
10203 mips16_mark_labels ();
10208 /* Parse a register string into a number. Called from the ECOFF code
10209 to parse .frame. The argument is non-zero if this is the frame
10210 register, so that we can record it in mips_frame_reg. */
10213 tc_get_register (frame
)
10218 SKIP_WHITESPACE ();
10219 if (*input_line_pointer
++ != '$')
10221 as_warn ("expected `$'");
10224 else if (isdigit ((unsigned char) *input_line_pointer
))
10226 reg
= get_absolute_expression ();
10227 if (reg
< 0 || reg
>= 32)
10229 as_warn ("Bad register number");
10235 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10237 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10239 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10241 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10245 as_warn ("Unrecognized register name");
10248 input_line_pointer
+= 2;
10251 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10256 md_section_align (seg
, addr
)
10260 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10263 /* We don't need to align ELF sections to the full alignment.
10264 However, Irix 5 may prefer that we align them at least to a 16
10265 byte boundary. We don't bother to align the sections if we are
10266 targeted for an embedded system. */
10267 if (strcmp (TARGET_OS
, "elf") == 0)
10273 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10276 /* Utility routine, called from above as well. If called while the
10277 input file is still being read, it's only an approximation. (For
10278 example, a symbol may later become defined which appeared to be
10279 undefined earlier.) */
10282 nopic_need_relax (sym
, before_relaxing
)
10284 int before_relaxing
;
10289 if (USE_GLOBAL_POINTER_OPT
)
10291 const char *symname
;
10294 /* Find out whether this symbol can be referenced off the GP
10295 register. It can be if it is smaller than the -G size or if
10296 it is in the .sdata or .sbss section. Certain symbols can
10297 not be referenced off the GP, although it appears as though
10299 symname
= S_GET_NAME (sym
);
10300 if (symname
!= (const char *) NULL
10301 && (strcmp (symname
, "eprol") == 0
10302 || strcmp (symname
, "etext") == 0
10303 || strcmp (symname
, "_gp") == 0
10304 || strcmp (symname
, "edata") == 0
10305 || strcmp (symname
, "_fbss") == 0
10306 || strcmp (symname
, "_fdata") == 0
10307 || strcmp (symname
, "_ftext") == 0
10308 || strcmp (symname
, "end") == 0
10309 || strcmp (symname
, "_gp_disp") == 0))
10311 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10313 #ifndef NO_ECOFF_DEBUGGING
10314 || (sym
->ecoff_extern_size
!= 0
10315 && sym
->ecoff_extern_size
<= g_switch_value
)
10317 /* We must defer this decision until after the whole
10318 file has been read, since there might be a .extern
10319 after the first use of this symbol. */
10320 || (before_relaxing
10321 #ifndef NO_ECOFF_DEBUGGING
10322 && sym
->ecoff_extern_size
== 0
10324 && S_GET_VALUE (sym
) == 0)
10325 || (S_GET_VALUE (sym
) != 0
10326 && S_GET_VALUE (sym
) <= g_switch_value
)))
10330 const char *segname
;
10332 segname
= segment_name (S_GET_SEGMENT (sym
));
10333 assert (strcmp (segname
, ".lit8") != 0
10334 && strcmp (segname
, ".lit4") != 0);
10335 change
= (strcmp (segname
, ".sdata") != 0
10336 && strcmp (segname
, ".sbss") != 0);
10341 /* We are not optimizing for the GP register. */
10345 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10346 extended opcode. SEC is the section the frag is in. */
10349 mips16_extended_frag (fragp
, sec
, stretch
)
10355 register const struct mips16_immed_operand
*op
;
10357 int mintiny
, maxtiny
;
10360 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10362 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10365 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10366 op
= mips16_immed_operands
;
10367 while (op
->type
!= type
)
10370 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10375 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10378 maxtiny
= 1 << op
->nbits
;
10383 maxtiny
= (1 << op
->nbits
) - 1;
10388 mintiny
= - (1 << (op
->nbits
- 1));
10389 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10392 /* We can't call S_GET_VALUE here, because we don't want to lock in
10393 a particular frag address. */
10394 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10396 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10397 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10398 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10400 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
10401 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
10404 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
10405 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
10406 + fragp
->fr_symbol
->sy_value
.X_add_number
10407 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10408 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
10417 /* We won't have the section when we are called from
10418 mips_relax_frag. However, we will always have been called
10419 from md_estimate_size_before_relax first. If this is a
10420 branch to a different section, we mark it as such. If SEC is
10421 NULL, and the frag is not marked, then it must be a branch to
10422 the same section. */
10425 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10432 fragp
->fr_subtype
=
10433 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10435 /* FIXME: We should support this, and let the linker
10436 catch branches and loads that are out of range. */
10437 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10438 "unsupported PC relative reference to different section");
10444 /* In this case, we know for sure that the symbol fragment is in
10445 the same section. If the fr_address of the symbol fragment
10446 is greater then the address of this fragment we want to add
10447 in STRETCH in order to get a better estimate of the address.
10448 This particularly matters because of the shift bits. */
10450 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
10454 /* Adjust stretch for any alignment frag. Note that if have
10455 been expanding the earlier code, the symbol may be
10456 defined in what appears to be an earlier frag. FIXME:
10457 This doesn't handle the fr_subtype field, which specifies
10458 a maximum number of bytes to skip when doing an
10461 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
10464 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10467 stretch
= - ((- stretch
)
10468 & ~ ((1 << (int) f
->fr_offset
) - 1));
10470 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10479 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10481 /* The base address rules are complicated. The base address of
10482 a branch is the following instruction. The base address of a
10483 PC relative load or add is the instruction itself, but if it
10484 is in a delay slot (in which case it can not be extended) use
10485 the address of the instruction whose delay slot it is in. */
10486 if (type
== 'p' || type
== 'q')
10490 /* If we are currently assuming that this frag should be
10491 extended, then, the current address is two bytes
10493 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10496 /* Ignore the low bit in the target, since it will be set
10497 for a text label. */
10498 if ((val
& 1) != 0)
10501 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10503 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10506 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10508 /* Branch offsets have an implicit 0 in the lowest bit. */
10509 if (type
== 'p' || type
== 'q')
10512 /* If any of the shifted bits are set, we must use an extended
10513 opcode. If the address depends on the size of this
10514 instruction, this can lead to a loop, so we arrange to always
10515 use an extended opcode. We only check this when we are in
10516 the main relaxation loop, when SEC is NULL. */
10517 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10519 fragp
->fr_subtype
=
10520 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10524 /* If we are about to mark a frag as extended because the value
10525 is precisely maxtiny + 1, then there is a chance of an
10526 infinite loop as in the following code:
10531 In this case when the la is extended, foo is 0x3fc bytes
10532 away, so the la can be shrunk, but then foo is 0x400 away, so
10533 the la must be extended. To avoid this loop, we mark the
10534 frag as extended if it was small, and is about to become
10535 extended with a value of maxtiny + 1. */
10536 if (val
== ((maxtiny
+ 1) << op
->shift
)
10537 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10540 fragp
->fr_subtype
=
10541 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10545 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10546 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
10548 if ((val
& ((1 << op
->shift
) - 1)) != 0
10549 || val
< (mintiny
<< op
->shift
)
10550 || val
> (maxtiny
<< op
->shift
))
10556 /* Estimate the size of a frag before relaxing. Unless this is the
10557 mips16, we are not really relaxing here, and the final size is
10558 encoded in the subtype information. For the mips16, we have to
10559 decide whether we are using an extended opcode or not. */
10563 md_estimate_size_before_relax (fragp
, segtype
)
10569 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10571 if (mips16_extended_frag (fragp
, segtype
, 0))
10573 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10578 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10583 if (mips_pic
== NO_PIC
)
10585 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10587 else if (mips_pic
== SVR4_PIC
)
10592 sym
= fragp
->fr_symbol
;
10594 /* Handle the case of a symbol equated to another symbol. */
10595 while (sym
->sy_value
.X_op
== O_symbol
10596 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10600 /* It's possible to get a loop here in a badly written
10602 n
= sym
->sy_value
.X_add_symbol
;
10608 symsec
= S_GET_SEGMENT (sym
);
10610 /* This must duplicate the test in adjust_reloc_syms. */
10611 change
= (symsec
!= &bfd_und_section
10612 && symsec
!= &bfd_abs_section
10613 && ! bfd_is_com_section (symsec
));
10620 /* Record the offset to the first reloc in the fr_opcode field.
10621 This lets md_convert_frag and tc_gen_reloc know that the code
10622 must be expanded. */
10623 fragp
->fr_opcode
= (fragp
->fr_literal
10625 - RELAX_OLD (fragp
->fr_subtype
)
10626 + RELAX_RELOC1 (fragp
->fr_subtype
));
10627 /* FIXME: This really needs as_warn_where. */
10628 if (RELAX_WARN (fragp
->fr_subtype
))
10629 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
10635 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10638 /* This is called to see whether a reloc against a defined symbol
10639 should be converted into a reloc against a section. Don't adjust
10640 MIPS16 jump relocations, so we don't have to worry about the format
10641 of the offset in the .o file. Don't adjust relocations against
10642 mips16 symbols, so that the linker can find them if it needs to set
10646 mips_fix_adjustable (fixp
)
10649 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10651 if (fixp
->fx_addsy
== NULL
)
10654 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10655 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10656 && fixp
->fx_subsy
== NULL
)
10662 /* Translate internal representation of relocation info to BFD target
10666 tc_gen_reloc (section
, fixp
)
10670 static arelent
*retval
[4];
10672 bfd_reloc_code_real_type code
;
10674 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10677 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10678 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10680 if (mips_pic
== EMBEDDED_PIC
10681 && SWITCH_TABLE (fixp
))
10683 /* For a switch table entry we use a special reloc. The addend
10684 is actually the difference between the reloc address and the
10686 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10687 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10688 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
10689 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10691 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10693 /* We use a special addend for an internal RELLO reloc. */
10694 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10695 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10697 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10699 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10701 assert (fixp
->fx_next
!= NULL
10702 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10703 /* We use a special addend for an internal RELHI reloc. The
10704 reloc is relative to the RELLO; adjust the addend
10706 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10707 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10708 + fixp
->fx_next
->fx_where
10709 - S_GET_VALUE (fixp
->fx_subsy
));
10711 reloc
->addend
= (fixp
->fx_addnumber
10712 + fixp
->fx_next
->fx_frag
->fr_address
10713 + fixp
->fx_next
->fx_where
);
10715 else if (fixp
->fx_pcrel
== 0)
10716 reloc
->addend
= fixp
->fx_addnumber
;
10719 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10720 /* A gruesome hack which is a result of the gruesome gas reloc
10722 reloc
->addend
= reloc
->address
;
10724 reloc
->addend
= -reloc
->address
;
10727 /* If this is a variant frag, we may need to adjust the existing
10728 reloc and generate a new one. */
10729 if (fixp
->fx_frag
->fr_opcode
!= NULL
10730 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10731 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10732 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10733 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10734 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10735 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10736 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10740 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10742 /* If this is not the last reloc in this frag, then we have two
10743 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10744 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10745 the second one handle all of them. */
10746 if (fixp
->fx_next
!= NULL
10747 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10749 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10750 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10751 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10752 && (fixp
->fx_next
->fx_r_type
10753 == BFD_RELOC_MIPS_GOT_LO16
))
10754 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10755 && (fixp
->fx_next
->fx_r_type
10756 == BFD_RELOC_MIPS_CALL_LO16
)));
10761 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10762 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10763 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10765 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10766 reloc2
->address
= (reloc
->address
10767 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
10768 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
10769 reloc2
->addend
= fixp
->fx_addnumber
;
10770 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
10771 assert (reloc2
->howto
!= NULL
);
10773 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
10777 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
10780 reloc3
->address
+= 4;
10783 if (mips_pic
== NO_PIC
)
10785 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
10786 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
10788 else if (mips_pic
== SVR4_PIC
)
10790 switch (fixp
->fx_r_type
)
10794 case BFD_RELOC_MIPS_GOT16
:
10796 case BFD_RELOC_MIPS_CALL16
:
10797 case BFD_RELOC_MIPS_GOT_LO16
:
10798 case BFD_RELOC_MIPS_CALL_LO16
:
10799 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
10807 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
10808 fixup_segment converted a non-PC relative reloc into a PC
10809 relative reloc. In such a case, we need to convert the reloc
10811 code
= fixp
->fx_r_type
;
10812 if (fixp
->fx_pcrel
)
10817 code
= BFD_RELOC_8_PCREL
;
10820 code
= BFD_RELOC_16_PCREL
;
10823 code
= BFD_RELOC_32_PCREL
;
10826 code
= BFD_RELOC_64_PCREL
;
10828 case BFD_RELOC_8_PCREL
:
10829 case BFD_RELOC_16_PCREL
:
10830 case BFD_RELOC_32_PCREL
:
10831 case BFD_RELOC_64_PCREL
:
10832 case BFD_RELOC_16_PCREL_S2
:
10833 case BFD_RELOC_PCREL_HI16_S
:
10834 case BFD_RELOC_PCREL_LO16
:
10837 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10838 "Cannot make %s relocation PC relative",
10839 bfd_get_reloc_code_name (code
));
10843 /* To support a PC relative reloc when generating embedded PIC code
10844 for ECOFF, we use a Cygnus extension. We check for that here to
10845 make sure that we don't let such a reloc escape normally. */
10846 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10847 && code
== BFD_RELOC_16_PCREL_S2
10848 && mips_pic
!= EMBEDDED_PIC
)
10849 reloc
->howto
= NULL
;
10851 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10853 if (reloc
->howto
== NULL
)
10855 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10856 "Can not represent %s relocation in this object file format",
10857 bfd_get_reloc_code_name (code
));
10864 /* Relax a machine dependent frag. This returns the amount by which
10865 the current size of the frag should change. */
10868 mips_relax_frag (fragp
, stretch
)
10872 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10875 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10877 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10879 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10884 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10886 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10893 /* Convert a machine dependent frag. */
10896 md_convert_frag (abfd
, asec
, fragp
)
10904 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10907 register const struct mips16_immed_operand
*op
;
10908 boolean small
, ext
;
10911 unsigned long insn
;
10912 boolean use_extend
;
10913 unsigned short extend
;
10915 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10916 op
= mips16_immed_operands
;
10917 while (op
->type
!= type
)
10920 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10931 resolve_symbol_value (fragp
->fr_symbol
, 1);
10932 val
= S_GET_VALUE (fragp
->fr_symbol
);
10937 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10939 /* The rules for the base address of a PC relative reloc are
10940 complicated; see mips16_extended_frag. */
10941 if (type
== 'p' || type
== 'q')
10946 /* Ignore the low bit in the target, since it will be
10947 set for a text label. */
10948 if ((val
& 1) != 0)
10951 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10953 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10956 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10959 /* Make sure the section winds up with the alignment we have
10962 record_alignment (asec
, op
->shift
);
10966 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10967 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10968 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10969 "extended instruction in delay slot");
10971 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10973 if (target_big_endian
)
10974 insn
= bfd_getb16 (buf
);
10976 insn
= bfd_getl16 (buf
);
10978 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10979 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10980 small
, ext
, &insn
, &use_extend
, &extend
);
10984 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10985 fragp
->fr_fix
+= 2;
10989 md_number_to_chars (buf
, insn
, 2);
10990 fragp
->fr_fix
+= 2;
10995 if (fragp
->fr_opcode
== NULL
)
10998 old
= RELAX_OLD (fragp
->fr_subtype
);
10999 new = RELAX_NEW (fragp
->fr_subtype
);
11000 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11003 memcpy (fixptr
- old
, fixptr
, new);
11005 fragp
->fr_fix
+= new - old
;
11011 /* This function is called after the relocs have been generated.
11012 We've been storing mips16 text labels as odd. Here we convert them
11013 back to even for the convenience of the debugger. */
11016 mips_frob_file_after_relocs ()
11019 unsigned int count
, i
;
11021 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11024 syms
= bfd_get_outsymbols (stdoutput
);
11025 count
= bfd_get_symcount (stdoutput
);
11026 for (i
= 0; i
< count
; i
++, syms
++)
11028 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11029 && ((*syms
)->value
& 1) != 0)
11031 (*syms
)->value
&= ~1;
11032 /* If the symbol has an odd size, it was probably computed
11033 incorrectly, so adjust that as well. */
11034 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11035 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11042 /* This function is called whenever a label is defined. It is used
11043 when handling branch delays; if a branch has a label, we assume we
11044 can not move it. */
11047 mips_define_label (sym
)
11050 struct insn_label_list
*l
;
11052 if (free_insn_labels
== NULL
)
11053 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11056 l
= free_insn_labels
;
11057 free_insn_labels
= l
->next
;
11061 l
->next
= insn_labels
;
11065 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11067 /* Some special processing for a MIPS ELF file. */
11070 mips_elf_final_processing ()
11072 /* Write out the register information. */
11077 s
.ri_gprmask
= mips_gprmask
;
11078 s
.ri_cprmask
[0] = mips_cprmask
[0];
11079 s
.ri_cprmask
[1] = mips_cprmask
[1];
11080 s
.ri_cprmask
[2] = mips_cprmask
[2];
11081 s
.ri_cprmask
[3] = mips_cprmask
[3];
11082 /* The gp_value field is set by the MIPS ELF backend. */
11084 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11085 ((Elf32_External_RegInfo
*)
11086 mips_regmask_frag
));
11090 Elf64_Internal_RegInfo s
;
11092 s
.ri_gprmask
= mips_gprmask
;
11094 s
.ri_cprmask
[0] = mips_cprmask
[0];
11095 s
.ri_cprmask
[1] = mips_cprmask
[1];
11096 s
.ri_cprmask
[2] = mips_cprmask
[2];
11097 s
.ri_cprmask
[3] = mips_cprmask
[3];
11098 /* The gp_value field is set by the MIPS ELF backend. */
11100 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11101 ((Elf64_External_RegInfo
*)
11102 mips_regmask_frag
));
11105 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11106 sort of BFD interface for this. */
11107 if (mips_any_noreorder
)
11108 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11109 if (mips_pic
!= NO_PIC
)
11110 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11113 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11115 /* These functions should really be defined by the object file format,
11116 since they are related to debugging information. However, this
11117 code has to work for the a.out format, which does not define them,
11118 so we provide simple versions here. These don't actually generate
11119 any debugging information, but they do simple checking and someday
11120 somebody may make them useful. */
11124 struct loc
*loc_next
;
11125 unsigned long loc_fileno
;
11126 unsigned long loc_lineno
;
11127 unsigned long loc_offset
;
11128 unsigned short loc_delta
;
11129 unsigned short loc_count
;
11136 typedef struct proc
11138 struct proc
*proc_next
;
11139 struct symbol
*proc_isym
;
11140 struct symbol
*proc_end
;
11141 unsigned long proc_reg_mask
;
11142 unsigned long proc_reg_offset
;
11143 unsigned long proc_fpreg_mask
;
11144 unsigned long proc_fpreg_offset
;
11145 unsigned long proc_frameoffset
;
11146 unsigned long proc_framereg
;
11147 unsigned long proc_pcreg
;
11149 struct file
*proc_file
;
11154 typedef struct file
11156 struct file
*file_next
;
11157 unsigned long file_fileno
;
11158 struct symbol
*file_symbol
;
11159 struct symbol
*file_end
;
11160 struct proc
*file_proc
;
11165 static struct obstack proc_frags
;
11166 static procS
*proc_lastP
;
11167 static procS
*proc_rootP
;
11168 static int numprocs
;
11173 obstack_begin (&proc_frags
, 0x2000);
11179 /* check for premature end, nesting errors, etc */
11180 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11181 as_warn ("missing `.end' at end of assembly");
11190 if (*input_line_pointer
== '-')
11192 ++input_line_pointer
;
11195 if (!isdigit (*input_line_pointer
))
11196 as_bad ("Expected simple number.");
11197 if (input_line_pointer
[0] == '0')
11199 if (input_line_pointer
[1] == 'x')
11201 input_line_pointer
+= 2;
11202 while (isxdigit (*input_line_pointer
))
11205 val
|= hex_value (*input_line_pointer
++);
11207 return negative
? -val
: val
;
11211 ++input_line_pointer
;
11212 while (isdigit (*input_line_pointer
))
11215 val
|= *input_line_pointer
++ - '0';
11217 return negative
? -val
: val
;
11220 if (!isdigit (*input_line_pointer
))
11222 printf (" *input_line_pointer == '%c' 0x%02x\n",
11223 *input_line_pointer
, *input_line_pointer
);
11224 as_warn ("Invalid number");
11227 while (isdigit (*input_line_pointer
))
11230 val
+= *input_line_pointer
++ - '0';
11232 return negative
? -val
: val
;
11235 /* The .file directive; just like the usual .file directive, but there
11236 is an initial number which is the ECOFF file index. */
11244 line
= get_number ();
11249 /* The .end directive. */
11257 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11260 demand_empty_rest_of_line ();
11264 if (now_seg
!= text_section
)
11265 as_warn (".end not in text section");
11268 as_warn (".end and no .ent seen yet.");
11274 assert (S_GET_NAME (p
));
11275 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
11276 as_warn (".end symbol does not match .ent symbol.");
11279 proc_lastP
->proc_end
= (symbolS
*) 1;
11282 /* The .aent and .ent directives. */
11292 symbolP
= get_symbol ();
11293 if (*input_line_pointer
== ',')
11294 input_line_pointer
++;
11295 SKIP_WHITESPACE ();
11296 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
11297 number
= get_number ();
11298 if (now_seg
!= text_section
)
11299 as_warn (".ent or .aent not in text section.");
11301 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11302 as_warn ("missing `.end'");
11306 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
11307 procP
->proc_isym
= symbolP
;
11308 procP
->proc_reg_mask
= 0;
11309 procP
->proc_reg_offset
= 0;
11310 procP
->proc_fpreg_mask
= 0;
11311 procP
->proc_fpreg_offset
= 0;
11312 procP
->proc_frameoffset
= 0;
11313 procP
->proc_framereg
= 0;
11314 procP
->proc_pcreg
= 0;
11315 procP
->proc_end
= NULL
;
11316 procP
->proc_next
= NULL
;
11318 proc_lastP
->proc_next
= procP
;
11320 proc_rootP
= procP
;
11321 proc_lastP
= procP
;
11324 demand_empty_rest_of_line ();
11327 /* The .frame directive. */
11340 frame_reg
= tc_get_register (1);
11341 if (*input_line_pointer
== ',')
11342 input_line_pointer
++;
11343 frame_off
= get_absolute_expression ();
11344 if (*input_line_pointer
== ',')
11345 input_line_pointer
++;
11346 pcreg
= tc_get_register (0);
11348 /* bob third eye */
11349 assert (proc_rootP
);
11350 proc_rootP
->proc_framereg
= frame_reg
;
11351 proc_rootP
->proc_frameoffset
= frame_off
;
11352 proc_rootP
->proc_pcreg
= pcreg
;
11353 /* bob macho .frame */
11355 /* We don't have to write out a frame stab for unoptimized code. */
11356 if (!(frame_reg
== FP
&& frame_off
== 0))
11359 as_warn ("No .ent for .frame to use.");
11360 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
11361 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
11362 S_SET_TYPE (symP
, N_RMASK
);
11363 S_SET_OTHER (symP
, 0);
11364 S_SET_DESC (symP
, 0);
11365 symP
->sy_forward
= proc_lastP
->proc_isym
;
11366 /* bob perhaps I should have used pseudo set */
11368 demand_empty_rest_of_line ();
11372 /* The .fmask and .mask directives. */
11379 char str
[100], *strP
;
11385 mask
= get_number ();
11386 if (*input_line_pointer
== ',')
11387 input_line_pointer
++;
11388 off
= get_absolute_expression ();
11390 /* bob only for coff */
11391 assert (proc_rootP
);
11392 if (reg_type
== 'F')
11394 proc_rootP
->proc_fpreg_mask
= mask
;
11395 proc_rootP
->proc_fpreg_offset
= off
;
11399 proc_rootP
->proc_reg_mask
= mask
;
11400 proc_rootP
->proc_reg_offset
= off
;
11403 /* bob macho .mask + .fmask */
11405 /* We don't have to write out a mask stab if no saved regs. */
11409 as_warn ("No .ent for .mask to use.");
11411 for (i
= 0; i
< 32; i
++)
11415 sprintf (strP
, "%c%d,", reg_type
, i
);
11416 strP
+= strlen (strP
);
11420 sprintf (strP
, ";%d,", off
);
11421 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
11422 S_SET_TYPE (symP
, N_RMASK
);
11423 S_SET_OTHER (symP
, 0);
11424 S_SET_DESC (symP
, 0);
11425 symP
->sy_forward
= proc_lastP
->proc_isym
;
11426 /* bob perhaps I should have used pseudo set */
11431 /* The .loc directive. */
11442 assert (now_seg
== text_section
);
11444 lineno
= get_number ();
11445 addroff
= frag_now_fix ();
11447 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11448 S_SET_TYPE (symbolP
, N_SLINE
);
11449 S_SET_OTHER (symbolP
, 0);
11450 S_SET_DESC (symbolP
, lineno
);
11451 symbolP
->sy_segment
= now_seg
;