1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
78 #define PIC_CALL_REG 25
86 extern int target_big_endian
;
88 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
89 32 bit ABI. This has no meaning for ECOFF. */
92 /* The default target format to use. */
96 switch (OUTPUT_FLAVOR
)
98 case bfd_target_aout_flavour
:
99 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
100 case bfd_target_ecoff_flavour
:
101 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
102 case bfd_target_elf_flavour
:
103 return (target_big_endian
104 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
105 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
111 /* The name of the readonly data section. */
112 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
114 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* These variables are filled in with the masks of registers used.
121 The object format code reads them and puts them in the appropriate
123 unsigned long mips_gprmask
;
124 unsigned long mips_cprmask
[4];
126 /* MIPS ISA (Instruction Set Architecture) level (may be changed
127 temporarily using .set mipsN). */
128 static int mips_isa
= -1;
130 /* MIPS ISA we are using for this output file. */
131 static int file_mips_isa
;
133 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
134 static int mips_cpu
= -1;
136 /* Whether the 4650 instructions (mad/madu) are permitted. */
137 static int mips_4650
= -1;
139 /* Whether the 4010 instructions are permitted. */
140 static int mips_4010
= -1;
142 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
143 static int mips_4100
= -1;
145 /* Whether the processor uses hardware interlocks, and thus does not
146 require nops to be inserted. */
147 static int interlocks
= -1;
149 /* As with "interlocks" this is used by hardware that has FP
150 (co-processor) interlocks. */
151 static int cop_interlocks
= -1;
153 /* MIPS PIC level. */
157 /* Do not generate PIC code. */
160 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
161 not sure what it is supposed to do. */
164 /* Generate PIC code as in the SVR4 MIPS ABI. */
167 /* Generate PIC code without using a global offset table: the data
168 segment has a maximum size of 64K, all data references are off
169 the $gp register, and all text references are PC relative. This
170 is used on some embedded systems. */
174 static enum mips_pic_level mips_pic
;
176 /* 1 if we should generate 32 bit offsets from the GP register in
177 SVR4_PIC mode. Currently has no meaning in other modes. */
178 static int mips_big_got
;
180 /* 1 if trap instructions should used for overflow rather than break
182 static int mips_trap
;
184 static int mips_warn_about_macros
;
185 static int mips_noreorder
;
186 static int mips_any_noreorder
;
187 static int mips_nomove
;
188 static int mips_noat
;
189 static int mips_nobopt
;
191 /* The size of the small data section. */
192 static int g_switch_value
= 8;
193 /* Whether the -G option was used. */
194 static int g_switch_seen
= 0;
199 /* If we can determine in advance that GP optimization won't be
200 possible, we can skip the relaxation stuff that tries to produce
201 GP-relative references. This makes delay slot optimization work
204 This function can only provide a guess, but it seems to work for
205 gcc output. If it guesses wrong, the only loss should be in
206 efficiency; it shouldn't introduce any bugs.
208 I don't know if a fix is needed for the SVR4_PIC mode. I've only
209 fixed it for the non-PIC mode. KR 95/04/07 */
210 static int nopic_need_relax
PARAMS ((symbolS
*));
212 /* handle of the OPCODE hash table */
213 static struct hash_control
*op_hash
= NULL
;
215 /* This array holds the chars that always start a comment. If the
216 pre-processor is disabled, these aren't very useful */
217 const char comment_chars
[] = "#";
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output */
222 /* Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output. */
225 /* Also note that C style comments are always supported. */
226 const char line_comment_chars
[] = "#";
228 /* This array holds machine specific line separator characters. */
229 const char line_separator_chars
[] = "";
231 /* Chars that can be used to separate mant from exp in floating point nums */
232 const char EXP_CHARS
[] = "eE";
234 /* Chars that mean this number is a floating point constant */
237 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
239 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
240 changed in read.c . Ideally it shouldn't have to know about it at all,
241 but nothing is ideal around here.
244 static char *insn_error
;
246 static int byte_order
;
248 static int auto_align
= 1;
250 /* Symbol labelling the current insn. */
251 static symbolS
*insn_label
;
253 /* When outputting SVR4 PIC code, the assembler needs to know the
254 offset in the stack frame from which to restore the $gp register.
255 This is set by the .cprestore pseudo-op, and saved in this
257 static offsetT mips_cprestore_offset
= -1;
259 /* This is the register which holds the stack frame, as set by the
260 .frame pseudo-op. This is needed to implement .cprestore. */
261 static int mips_frame_reg
= SP
;
263 /* To output NOP instructions correctly, we need to keep information
264 about the previous two instructions. */
266 /* Whether we are optimizing. The default value of 2 means to remove
267 unneeded NOPs and swap branch instructions when possible. A value
268 of 1 means to not swap branches. A value of 0 means to always
270 static int mips_optimize
= 2;
272 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
273 equivalent to seeing no -g option at all. */
274 static int mips_debug
= 0;
276 /* The previous instruction. */
277 static struct mips_cl_insn prev_insn
;
279 /* The instruction before prev_insn. */
280 static struct mips_cl_insn prev_prev_insn
;
282 /* If we don't want information for prev_insn or prev_prev_insn, we
283 point the insn_mo field at this dummy integer. */
284 static const struct mips_opcode dummy_opcode
= { 0 };
286 /* Non-zero if prev_insn is valid. */
287 static int prev_insn_valid
;
289 /* The frag for the previous instruction. */
290 static struct frag
*prev_insn_frag
;
292 /* The offset into prev_insn_frag for the previous instruction. */
293 static long prev_insn_where
;
295 /* The reloc for the previous instruction, if any. */
296 static fixS
*prev_insn_fixp
;
298 /* Non-zero if the previous instruction was in a delay slot. */
299 static int prev_insn_is_delay_slot
;
301 /* Non-zero if the previous instruction was in a .set noreorder. */
302 static int prev_insn_unreordered
;
304 /* Non-zero if the previous previous instruction was in a .set
306 static int prev_prev_insn_unreordered
;
308 /* For ECOFF and ELF, relocations against symbols are done in two
309 parts, with a HI relocation and a LO relocation. Each relocation
310 has only 16 bits of space to store an addend. This means that in
311 order for the linker to handle carries correctly, it must be able
312 to locate both the HI and the LO relocation. This means that the
313 relocations must appear in order in the relocation table.
315 In order to implement this, we keep track of each unmatched HI
316 relocation. We then sort them so that they immediately precede the
317 corresponding LO relocation. */
322 struct mips_hi_fixup
*next
;
325 /* The section this fixup is in. */
329 /* The list of unmatched HI relocs. */
331 static struct mips_hi_fixup
*mips_hi_fixup_list
;
333 /* Since the MIPS does not have multiple forms of PC relative
334 instructions, we do not have to do relaxing as is done on other
335 platforms. However, we do have to handle GP relative addressing
336 correctly, which turns out to be a similar problem.
338 Every macro that refers to a symbol can occur in (at least) two
339 forms, one with GP relative addressing and one without. For
340 example, loading a global variable into a register generally uses
341 a macro instruction like this:
343 If i can be addressed off the GP register (this is true if it is in
344 the .sbss or .sdata section, or if it is known to be smaller than
345 the -G argument) this will generate the following instruction:
347 This instruction will use a GPREL reloc. If i can not be addressed
348 off the GP register, the following instruction sequence will be used:
351 In this case the first instruction will have a HI16 reloc, and the
352 second reloc will have a LO16 reloc. Both relocs will be against
355 The issue here is that we may not know whether i is GP addressable
356 until after we see the instruction that uses it. Therefore, we
357 want to be able to choose the final instruction sequence only at
358 the end of the assembly. This is similar to the way other
359 platforms choose the size of a PC relative instruction only at the
362 When generating position independent code we do not use GP
363 addressing in quite the same way, but the issue still arises as
364 external symbols and local symbols must be handled differently.
366 We handle these issues by actually generating both possible
367 instruction sequences. The longer one is put in a frag_var with
368 type rs_machine_dependent. We encode what to do with the frag in
369 the subtype field. We encode (1) the number of existing bytes to
370 replace, (2) the number of new bytes to use, (3) the offset from
371 the start of the existing bytes to the first reloc we must generate
372 (that is, the offset is applied from the start of the existing
373 bytes after they are replaced by the new bytes, if any), (4) the
374 offset from the start of the existing bytes to the second reloc,
375 (5) whether a third reloc is needed (the third reloc is always four
376 bytes after the second reloc), and (6) whether to warn if this
377 variant is used (this is sometimes needed if .set nomacro or .set
378 noat is in effect). All these numbers are reasonably small.
380 Generating two instruction sequences must be handled carefully to
381 ensure that delay slots are handled correctly. Fortunately, there
382 are a limited number of cases. When the second instruction
383 sequence is generated, append_insn is directed to maintain the
384 existing delay slot information, so it continues to apply to any
385 code after the second instruction sequence. This means that the
386 second instruction sequence must not impose any requirements not
387 required by the first instruction sequence.
389 These variant frags are then handled in functions called by the
390 machine independent code. md_estimate_size_before_relax returns
391 the final size of the frag. md_convert_frag sets up the final form
392 of the frag. tc_gen_reloc adjust the first reloc and adds a second
394 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
398 | (((reloc1) + 64) << 9) \
399 | (((reloc2) + 64) << 2) \
400 | ((reloc3) ? (1 << 1) : 0) \
402 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
403 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
404 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
405 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
406 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
407 #define RELAX_WARN(i) ((i) & 1)
409 /* Prototypes for static functions. */
412 #define internalError() \
413 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
415 #define internalError() as_fatal ("MIPS internal Error");
418 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
419 unsigned int reg
, int fpr
));
420 static int reg_needs_delay
PARAMS ((int));
421 static void append_insn
PARAMS ((char *place
,
422 struct mips_cl_insn
* ip
,
424 bfd_reloc_code_real_type r
,
426 static void mips_no_prev_insn
PARAMS ((void));
427 static void mips_emit_delays
PARAMS ((void));
429 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
430 const char *name
, const char *fmt
,
433 static void macro_build ();
435 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
436 expressionS
* ep
, int regnum
));
437 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
438 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
440 static void load_register
PARAMS ((int *, int, expressionS
*, int));
441 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
442 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
443 #ifdef LOSING_COMPILER
444 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
446 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
447 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
448 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
449 static symbolS
*get_symbol
PARAMS ((void));
450 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
451 static void s_align
PARAMS ((int));
452 static void s_change_sec
PARAMS ((int));
453 static void s_cons
PARAMS ((int));
454 static void s_float_cons
PARAMS ((int));
455 static void s_mips_globl
PARAMS ((int));
456 static void s_option
PARAMS ((int));
457 static void s_mipsset
PARAMS ((int));
458 static void s_abicalls
PARAMS ((int));
459 static void s_cpload
PARAMS ((int));
460 static void s_cprestore
PARAMS ((int));
461 static void s_gpword
PARAMS ((int));
462 static void s_cpadd
PARAMS ((int));
463 static void md_obj_begin
PARAMS ((void));
464 static void md_obj_end
PARAMS ((void));
465 static long get_number
PARAMS ((void));
466 static void s_ent
PARAMS ((int));
467 static void s_mipsend
PARAMS ((int));
468 static void s_file
PARAMS ((int));
472 The following pseudo-ops from the Kane and Heinrich MIPS book
473 should be defined here, but are currently unsupported: .alias,
474 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
476 The following pseudo-ops from the Kane and Heinrich MIPS book are
477 specific to the type of debugging information being generated, and
478 should be defined by the object format: .aent, .begin, .bend,
479 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
482 The following pseudo-ops from the Kane and Heinrich MIPS book are
483 not MIPS CPU specific, but are also not specific to the object file
484 format. This file is probably the best place to define them, but
485 they are not currently supported: .asm0, .endr, .lab, .repeat,
486 .struct, .weakext. */
488 static const pseudo_typeS mips_pseudo_table
[] =
490 /* MIPS specific pseudo-ops. */
491 {"option", s_option
, 0},
492 {"set", s_mipsset
, 0},
493 {"rdata", s_change_sec
, 'r'},
494 {"sdata", s_change_sec
, 's'},
495 {"livereg", s_ignore
, 0},
496 {"abicalls", s_abicalls
, 0},
497 {"cpload", s_cpload
, 0},
498 {"cprestore", s_cprestore
, 0},
499 {"gpword", s_gpword
, 0},
500 {"cpadd", s_cpadd
, 0},
502 /* Relatively generic pseudo-ops that happen to be used on MIPS
504 {"asciiz", stringer
, 1},
505 {"bss", s_change_sec
, 'b'},
508 {"dword", s_cons
, 3},
510 /* These pseudo-ops are defined in read.c, but must be overridden
511 here for one reason or another. */
512 {"align", s_align
, 0},
514 {"data", s_change_sec
, 'd'},
515 {"double", s_float_cons
, 'd'},
516 {"float", s_float_cons
, 'f'},
517 {"globl", s_mips_globl
, 0},
518 {"global", s_mips_globl
, 0},
519 {"hword", s_cons
, 1},
524 {"short", s_cons
, 1},
525 {"single", s_float_cons
, 'f'},
526 {"text", s_change_sec
, 't'},
531 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
532 /* These pseudo-ops should be defined by the object file format.
533 However, a.out doesn't support them, so we have versions here. */
535 {"bgnb", s_ignore
, 0},
536 {"end", s_mipsend
, 0},
537 {"endb", s_ignore
, 0},
540 {"fmask", s_ignore
, 'F'},
541 {"frame", s_ignore
, 0},
542 {"loc", s_ignore
, 0},
543 {"mask", s_ignore
, 'R'},
544 {"verstamp", s_ignore
, 0},
548 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
553 pop_insert (mips_pseudo_table
);
554 if (! ECOFF_DEBUGGING
)
555 pop_insert (mips_nonecoff_pseudo_table
);
558 static char *expr_end
;
560 /* Expressions which appear in instructions. These are set by
563 static expressionS imm_expr
;
564 static expressionS offset_expr
;
566 /* Relocs associated with imm_expr and offset_expr. */
568 static bfd_reloc_code_real_type imm_reloc
;
569 static bfd_reloc_code_real_type offset_reloc
;
571 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
573 static boolean imm_unmatched_hi
;
576 * This function is called once, at assembler startup time. It should
577 * set up all the tables, etc. that the MD part of the assembler will need.
583 register const char *retval
= NULL
;
584 register unsigned int i
= 0;
592 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
594 a
= xmalloc (sizeof TARGET_CPU
);
595 strcpy (a
, TARGET_CPU
);
596 a
[(sizeof TARGET_CPU
) - 3] = '\0';
600 if (strcmp (cpu
, "mips") == 0)
606 else if (strcmp (cpu
, "r6000") == 0
607 || strcmp (cpu
, "mips2") == 0)
613 else if (strcmp (cpu
, "mips64") == 0
614 || strcmp (cpu
, "r4000") == 0
615 || strcmp (cpu
, "mips3") == 0)
621 else if (strcmp (cpu
, "r4400") == 0)
627 else if (strcmp (cpu
, "mips64orion") == 0
628 || strcmp (cpu
, "r4600") == 0)
634 else if (strcmp (cpu
, "r4650") == 0)
642 else if (strcmp (cpu
, "mips64vr4300") == 0)
648 else if (strcmp (cpu
, "mips64vr4100") == 0)
656 else if (strcmp (cpu
, "r4010") == 0)
664 else if (strcmp (cpu
, "r8000") == 0
665 || strcmp (cpu
, "mips4") == 0)
671 else if (strcmp (cpu
, "r10000") == 0)
697 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
702 if (mips_cpu
== 4300)
707 if (mips_isa
< 2 && mips_trap
)
708 as_bad ("trap exception not supported at ISA 1");
713 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
716 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
719 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
722 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
726 as_warn ("Could not set architecture and machine");
728 file_mips_isa
= mips_isa
;
730 op_hash
= hash_new ();
732 for (i
= 0; i
< NUMOPCODES
;)
734 const char *name
= mips_opcodes
[i
].name
;
736 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
739 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
740 mips_opcodes
[i
].name
, retval
);
741 as_fatal ("Broken assembler. No assembly attempted.");
745 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
746 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
747 != mips_opcodes
[i
].match
))
749 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
750 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
751 as_fatal ("Broken assembler. No assembly attempted.");
755 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
758 mips_no_prev_insn ();
766 /* set the default alignment for the text section (2**2) */
767 record_alignment (text_section
, 2);
769 if (USE_GLOBAL_POINTER_OPT
)
770 bfd_set_gp_size (stdoutput
, g_switch_value
);
772 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
774 /* Sections must be aligned to 16 byte boundaries. */
775 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
776 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
777 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
779 /* Create a .reginfo section for register masks and a .mdebug
780 section for debugging information. */
791 sec
= subseg_new (".reginfo", (subsegT
) 0);
793 /* The ABI says this section should be loaded so that the
794 running program can access it. */
795 (void) bfd_set_section_flags (stdoutput
, sec
,
796 (SEC_ALLOC
| SEC_LOAD
797 | SEC_READONLY
| SEC_DATA
));
798 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
801 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
806 /* The 64-bit ABI uses a .MIPS.options section rather than
808 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
809 (void) bfd_set_section_flags (stdoutput
, sec
,
810 (SEC_ALLOC
| SEC_LOAD
811 | SEC_READONLY
| SEC_DATA
));
812 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
815 /* Set up the option header. */
817 Elf_Internal_Options opthdr
;
820 opthdr
.kind
= ODK_REGINFO
;
821 opthdr
.size
= (sizeof (Elf_External_Options
)
822 + sizeof (Elf64_External_RegInfo
));
825 f
= frag_more (sizeof (Elf_External_Options
));
826 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
827 (Elf_External_Options
*) f
);
829 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
836 sec
= subseg_new (".mdebug", (subsegT
) 0);
837 (void) bfd_set_section_flags (stdoutput
, sec
,
838 SEC_HAS_CONTENTS
| SEC_READONLY
);
839 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
842 subseg_set (seg
, subseg
);
846 if (! ECOFF_DEBUGGING
)
853 if (! ECOFF_DEBUGGING
)
861 struct mips_cl_insn insn
;
863 imm_expr
.X_op
= O_absent
;
864 imm_reloc
= BFD_RELOC_UNUSED
;
865 imm_unmatched_hi
= false;
866 offset_expr
.X_op
= O_absent
;
867 offset_reloc
= BFD_RELOC_UNUSED
;
869 mips_ip (str
, &insn
);
872 as_bad ("%s `%s'", insn_error
, str
);
875 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
881 if (imm_expr
.X_op
!= O_absent
)
882 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
884 else if (offset_expr
.X_op
!= O_absent
)
885 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
887 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
891 /* See whether instruction IP reads register REG. If FPR is non-zero,
892 REG is a floating point register. */
895 insn_uses_reg (ip
, reg
, fpr
)
896 struct mips_cl_insn
*ip
;
900 /* Don't report on general register 0, since it never changes. */
901 if (! fpr
&& reg
== 0)
906 /* If we are called with either $f0 or $f1, we must check $f0.
907 This is not optimal, because it will introduce an unnecessary
908 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
909 need to distinguish reading both $f0 and $f1 or just one of
910 them. Note that we don't have to check the other way,
911 because there is no instruction that sets both $f0 and $f1
912 and requires a delay. */
913 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
914 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
915 == (reg
&~ (unsigned) 1)))
917 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
918 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
919 == (reg
&~ (unsigned) 1)))
924 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
925 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
927 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
928 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
935 /* This function returns true if modifying a register requires a
939 reg_needs_delay (reg
)
942 unsigned long prev_pinfo
;
944 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
947 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
949 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
951 /* A load from a coprocessor or from memory. All load
952 delays delay the use of general register rt for one
953 instruction on the r3000. The r6000 and r4000 use
955 know (prev_pinfo
& INSN_WRITE_GPR_T
);
956 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
963 /* Output an instruction. PLACE is where to put the instruction; if
964 it is NULL, this uses frag_more to get room. IP is the instruction
965 information. ADDRESS_EXPR is an operand of the instruction to be
966 used with RELOC_TYPE. */
969 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
971 struct mips_cl_insn
*ip
;
972 expressionS
*address_expr
;
973 bfd_reloc_code_real_type reloc_type
;
974 boolean unmatched_hi
;
976 register unsigned long prev_pinfo
, pinfo
;
981 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
982 pinfo
= ip
->insn_mo
->pinfo
;
984 if (place
== NULL
&& ! mips_noreorder
)
986 /* If the previous insn required any delay slots, see if we need
987 to insert a NOP or two. There are eight kinds of possible
988 hazards, of which an instruction can have at most one type.
989 (1) a load from memory delay
990 (2) a load from a coprocessor delay
991 (3) an unconditional branch delay
992 (4) a conditional branch delay
993 (5) a move to coprocessor register delay
994 (6) a load coprocessor register from memory delay
995 (7) a coprocessor condition code delay
996 (8) a HI/LO special register delay
998 There are a lot of optimizations we could do that we don't.
999 In particular, we do not, in general, reorder instructions.
1000 If you use gcc with optimization, it will reorder
1001 instructions and generally do much more optimization then we
1002 do here; repeating all that work in the assembler would only
1003 benefit hand written assembly code, and does not seem worth
1006 /* This is how a NOP is emitted. */
1007 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
1009 /* The previous insn might require a delay slot, depending upon
1010 the contents of the current insn. */
1012 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1013 && ! cop_interlocks
)
1015 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1017 /* A load from a coprocessor or from memory. All load
1018 delays delay the use of general register rt for one
1019 instruction on the r3000. The r6000 and r4000 use
1021 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1022 if (mips_optimize
== 0
1023 || insn_uses_reg (ip
,
1024 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1029 else if (mips_isa
< 4
1030 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1031 && ! cop_interlocks
)
1033 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1035 /* A generic coprocessor delay. The previous instruction
1036 modified a coprocessor general or control register. If
1037 it modified a control register, we need to avoid any
1038 coprocessor instruction (this is probably not always
1039 required, but it sometimes is). If it modified a general
1040 register, we avoid using that register.
1042 On the r6000 and r4000 loading a coprocessor register
1043 from memory is interlocked, and does not require a delay.
1045 This case is not handled very well. There is no special
1046 knowledge of CP0 handling, and the coprocessors other
1047 than the floating point unit are not distinguished at
1049 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1051 if (mips_optimize
== 0
1052 || insn_uses_reg (ip
,
1053 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1058 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1060 if (mips_optimize
== 0
1061 || insn_uses_reg (ip
,
1062 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1069 /* We don't know exactly what the previous instruction
1070 does. If the current instruction uses a coprocessor
1071 register, we must insert a NOP. If previous
1072 instruction may set the condition codes, and the
1073 current instruction uses them, we must insert two
1075 if (mips_optimize
== 0
1076 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1077 && (pinfo
& INSN_READ_COND_CODE
)))
1079 else if (pinfo
& INSN_COP
)
1083 else if (mips_isa
< 4
1084 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1085 && ! cop_interlocks
)
1087 /* The previous instruction sets the coprocessor condition
1088 codes, but does not require a general coprocessor delay
1089 (this means it is a floating point comparison
1090 instruction). If this instruction uses the condition
1091 codes, we need to insert a single NOP. */
1092 if (mips_optimize
== 0
1093 || (pinfo
& INSN_READ_COND_CODE
))
1096 else if (prev_pinfo
& INSN_READ_LO
)
1098 /* The previous instruction reads the LO register; if the
1099 current instruction writes to the LO register, we must
1100 insert two NOPS. The R4650, VR4100 and VR4300 have
1103 && (mips_optimize
== 0
1104 || (pinfo
& INSN_WRITE_LO
)))
1107 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1109 /* The previous instruction reads the HI register; if the
1110 current instruction writes to the HI register, we must
1111 insert a NOP. The R4650, VR4100 and VR4300 have
1114 && (mips_optimize
== 0
1115 || (pinfo
& INSN_WRITE_HI
)))
1119 /* There are two cases which require two intervening
1120 instructions: 1) setting the condition codes using a move to
1121 coprocessor instruction which requires a general coprocessor
1122 delay and then reading the condition codes 2) reading the HI
1123 or LO register and then writing to it (except on the R4650,
1124 VR4100, and VR4300 which have interlocks). If we are not
1125 already emitting a NOP instruction, we must check for these
1126 cases compared to the instruction previous to the previous
1130 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1131 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1132 && (pinfo
& INSN_READ_COND_CODE
)
1133 && ! cop_interlocks
)
1134 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1135 && (pinfo
& INSN_WRITE_LO
)
1137 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1138 && (pinfo
& INSN_WRITE_HI
)
1142 /* If we are being given a nop instruction, don't bother with
1143 one of the nops we would otherwise output. This will only
1144 happen when a nop instruction is used with mips_optimize set
1146 if (nops
> 0 && ip
->insn_opcode
== 0)
1149 /* Now emit the right number of NOP instructions. */
1153 unsigned long old_frag_offset
;
1156 old_frag
= frag_now
;
1157 old_frag_offset
= frag_now_fix ();
1159 for (i
= 0; i
< nops
; i
++)
1164 listing_prev_line ();
1165 /* We may be at the start of a variant frag. In case we
1166 are, make sure there is enough space for the frag
1167 after the frags created by listing_prev_line. The
1168 argument to frag_grow here must be at least as large
1169 as the argument to all other calls to frag_grow in
1170 this file. We don't have to worry about being in the
1171 middle of a variant frag, because the variants insert
1172 all needed nop instructions themselves. */
1176 if (insn_label
!= NULL
)
1178 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1179 insn_label
->sy_frag
= frag_now
;
1180 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1183 #ifndef NO_ECOFF_DEBUGGING
1184 if (ECOFF_DEBUGGING
)
1185 ecoff_fix_loc (old_frag
, old_frag_offset
);
1195 if (address_expr
!= NULL
)
1197 if (address_expr
->X_op
== O_constant
)
1202 ip
->insn_opcode
|= address_expr
->X_add_number
;
1205 case BFD_RELOC_LO16
:
1206 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1209 case BFD_RELOC_MIPS_JMP
:
1210 case BFD_RELOC_16_PCREL_S2
:
1219 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1221 /* Don't generate a reloc if we are writing into a variant
1225 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1227 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1231 struct mips_hi_fixup
*hi_fixup
;
1233 assert (reloc_type
== BFD_RELOC_HI16_S
);
1234 hi_fixup
= ((struct mips_hi_fixup
*)
1235 xmalloc (sizeof (struct mips_hi_fixup
)));
1236 hi_fixup
->fixp
= fixp
;
1237 hi_fixup
->seg
= now_seg
;
1238 hi_fixup
->next
= mips_hi_fixup_list
;
1239 mips_hi_fixup_list
= hi_fixup
;
1245 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1247 /* Update the register mask information. */
1248 if (pinfo
& INSN_WRITE_GPR_D
)
1249 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1250 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1251 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1252 if (pinfo
& INSN_READ_GPR_S
)
1253 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1254 if (pinfo
& INSN_WRITE_GPR_31
)
1255 mips_gprmask
|= 1 << 31;
1256 if (pinfo
& INSN_WRITE_FPR_D
)
1257 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1258 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1259 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1260 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1261 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1262 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1263 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1264 if (pinfo
& INSN_COP
)
1266 /* We don't keep enough information to sort these cases out. */
1268 /* Never set the bit for $0, which is always zero. */
1269 mips_gprmask
&=~ 1 << 0;
1271 if (place
== NULL
&& ! mips_noreorder
)
1273 /* Filling the branch delay slot is more complex. We try to
1274 switch the branch with the previous instruction, which we can
1275 do if the previous instruction does not set up a condition
1276 that the branch tests and if the branch is not itself the
1277 target of any branch. */
1278 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1279 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1281 if (mips_optimize
< 2
1282 /* If we have seen .set volatile or .set nomove, don't
1285 /* If we had to emit any NOP instructions, then we
1286 already know we can not swap. */
1288 /* If we don't even know the previous insn, we can not
1290 || ! prev_insn_valid
1291 /* If the previous insn is already in a branch delay
1292 slot, then we can not swap. */
1293 || prev_insn_is_delay_slot
1294 /* If the previous previous insn was in a .set
1295 noreorder, we can't swap. Actually, the MIPS
1296 assembler will swap in this situation. However, gcc
1297 configured -with-gnu-as will generate code like
1303 in which we can not swap the bne and INSN. If gcc is
1304 not configured -with-gnu-as, it does not output the
1305 .set pseudo-ops. We don't have to check
1306 prev_insn_unreordered, because prev_insn_valid will
1307 be 0 in that case. We don't want to use
1308 prev_prev_insn_valid, because we do want to be able
1309 to swap at the start of a function. */
1310 || prev_prev_insn_unreordered
1311 /* If the branch is itself the target of a branch, we
1312 can not swap. We cheat on this; all we check for is
1313 whether there is a label on this instruction. If
1314 there are any branches to anything other than a
1315 label, users must use .set noreorder. */
1316 || insn_label
!= NULL
1317 /* If the previous instruction is in a variant frag, we
1318 can not do the swap. */
1319 || prev_insn_frag
->fr_type
== rs_machine_dependent
1320 /* If the branch reads the condition codes, we don't
1321 even try to swap, because in the sequence
1326 we can not swap, and I don't feel like handling that
1329 && (pinfo
& INSN_READ_COND_CODE
))
1330 /* We can not swap with an instruction that requires a
1331 delay slot, becase the target of the branch might
1332 interfere with that instruction. */
1335 & (INSN_LOAD_COPROC_DELAY
1336 | INSN_COPROC_MOVE_DELAY
1337 | INSN_WRITE_COND_CODE
)))
1344 & (INSN_LOAD_MEMORY_DELAY
1345 | INSN_COPROC_MEMORY_DELAY
)))
1346 /* We can not swap with a branch instruction. */
1348 & (INSN_UNCOND_BRANCH_DELAY
1349 | INSN_COND_BRANCH_DELAY
1350 | INSN_COND_BRANCH_LIKELY
))
1351 /* We do not swap with a trap instruction, since it
1352 complicates trap handlers to have the trap
1353 instruction be in a delay slot. */
1354 || (prev_pinfo
& INSN_TRAP
)
1355 /* If the branch reads a register that the previous
1356 instruction sets, we can not swap. */
1357 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1358 && insn_uses_reg (ip
,
1359 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1362 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1363 && insn_uses_reg (ip
,
1364 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1367 /* If the branch writes a register that the previous
1368 instruction sets, we can not swap (we know that
1369 branches write only to RD or to $31). */
1370 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1371 && (((pinfo
& INSN_WRITE_GPR_D
)
1372 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1373 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1374 || ((pinfo
& INSN_WRITE_GPR_31
)
1375 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1378 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1379 && (((pinfo
& INSN_WRITE_GPR_D
)
1380 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1381 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1382 || ((pinfo
& INSN_WRITE_GPR_31
)
1383 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1386 /* If the branch writes a register that the previous
1387 instruction reads, we can not swap (we know that
1388 branches only write to RD or to $31). */
1389 || ((pinfo
& INSN_WRITE_GPR_D
)
1390 && insn_uses_reg (&prev_insn
,
1391 ((ip
->insn_opcode
>> OP_SH_RD
)
1394 || ((pinfo
& INSN_WRITE_GPR_31
)
1395 && insn_uses_reg (&prev_insn
, 31, 0))
1396 /* If we are generating embedded PIC code, the branch
1397 might be expanded into a sequence which uses $at, so
1398 we can't swap with an instruction which reads it. */
1399 || (mips_pic
== EMBEDDED_PIC
1400 && insn_uses_reg (&prev_insn
, AT
, 0))
1401 /* If the previous previous instruction has a load
1402 delay, and sets a register that the branch reads, we
1405 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1407 && (prev_prev_insn
.insn_mo
->pinfo
1408 & INSN_LOAD_MEMORY_DELAY
)))
1409 && insn_uses_reg (ip
,
1410 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1414 /* We could do even better for unconditional branches to
1415 portions of this object file; we could pick up the
1416 instruction at the destination, put it in the delay
1417 slot, and bump the destination address. */
1419 /* Update the previous insn information. */
1420 prev_prev_insn
= *ip
;
1421 prev_insn
.insn_mo
= &dummy_opcode
;
1428 /* It looks like we can actually do the swap. */
1429 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1430 memcpy (temp
, prev_f
, 4);
1431 memcpy (prev_f
, f
, 4);
1432 memcpy (f
, temp
, 4);
1435 prev_insn_fixp
->fx_frag
= frag_now
;
1436 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1440 fixp
->fx_frag
= prev_insn_frag
;
1441 fixp
->fx_where
= prev_insn_where
;
1443 /* Update the previous insn information; leave prev_insn
1445 prev_prev_insn
= *ip
;
1447 prev_insn_is_delay_slot
= 1;
1449 /* If that was an unconditional branch, forget the previous
1450 insn information. */
1451 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1453 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1454 prev_insn
.insn_mo
= &dummy_opcode
;
1457 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1459 /* We don't yet optimize a branch likely. What we should do
1460 is look at the target, copy the instruction found there
1461 into the delay slot, and increment the branch to jump to
1462 the next instruction. */
1464 /* Update the previous insn information. */
1465 prev_prev_insn
= *ip
;
1466 prev_insn
.insn_mo
= &dummy_opcode
;
1470 /* Update the previous insn information. */
1472 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1474 prev_prev_insn
= prev_insn
;
1477 /* Any time we see a branch, we always fill the delay slot
1478 immediately; since this insn is not a branch, we know it
1479 is not in a delay slot. */
1480 prev_insn_is_delay_slot
= 0;
1483 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1484 prev_insn_unreordered
= 0;
1485 prev_insn_frag
= frag_now
;
1486 prev_insn_where
= f
- frag_now
->fr_literal
;
1487 prev_insn_fixp
= fixp
;
1488 prev_insn_valid
= 1;
1491 /* We just output an insn, so the next one doesn't have a label. */
1495 /* This function forgets that there was any previous instruction or
1499 mips_no_prev_insn ()
1501 prev_insn
.insn_mo
= &dummy_opcode
;
1502 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1503 prev_insn_valid
= 0;
1504 prev_insn_is_delay_slot
= 0;
1505 prev_insn_unreordered
= 0;
1506 prev_prev_insn_unreordered
= 0;
1510 /* This function must be called whenever we turn on noreorder or emit
1511 something other than instructions. It inserts any NOPS which might
1512 be needed by the previous instruction, and clears the information
1513 kept for the previous instructions. */
1518 if (! mips_noreorder
)
1524 && (! cop_interlocks
1525 && (prev_insn
.insn_mo
->pinfo
1526 & (INSN_LOAD_COPROC_DELAY
1527 | INSN_COPROC_MOVE_DELAY
1528 | INSN_WRITE_COND_CODE
))))
1530 && (prev_insn
.insn_mo
->pinfo
1534 && (prev_insn
.insn_mo
->pinfo
1535 & (INSN_LOAD_MEMORY_DELAY
1536 | INSN_COPROC_MEMORY_DELAY
))))
1540 && (! cop_interlocks
1541 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1543 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1544 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1547 else if ((mips_isa
< 4
1548 && (! cop_interlocks
1549 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1551 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1552 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1557 if (insn_label
!= NULL
)
1559 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1560 insn_label
->sy_frag
= frag_now
;
1561 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1566 mips_no_prev_insn ();
1569 /* Build an instruction created by a macro expansion. This is passed
1570 a pointer to the count of instructions created so far, an
1571 expression, the name of the instruction to build, an operand format
1572 string, and corresponding arguments. */
1576 macro_build (char *place
,
1584 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1593 struct mips_cl_insn insn
;
1594 bfd_reloc_code_real_type r
;
1598 va_start (args
, fmt
);
1604 * If the macro is about to expand into a second instruction,
1605 * print a warning if needed. We need to pass ip as a parameter
1606 * to generate a better warning message here...
1608 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1609 as_warn ("Macro instruction expanded into multiple instructions");
1612 *counter
+= 1; /* bump instruction counter */
1614 r
= BFD_RELOC_UNUSED
;
1615 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1616 assert (insn
.insn_mo
);
1617 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1619 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1620 || insn
.insn_mo
->pinfo
== INSN_MACRO
1621 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1623 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1625 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1627 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1629 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1631 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1635 assert (insn
.insn_mo
->name
);
1636 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1638 insn
.insn_opcode
= insn
.insn_mo
->match
;
1654 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1660 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1665 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1670 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1677 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1681 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1685 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1692 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1698 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1699 assert (r
== BFD_RELOC_MIPS_GPREL
1700 || r
== BFD_RELOC_MIPS_LITERAL
1701 || r
== BFD_RELOC_LO16
1702 || r
== BFD_RELOC_MIPS_GOT16
1703 || r
== BFD_RELOC_MIPS_CALL16
1704 || r
== BFD_RELOC_MIPS_GOT_LO16
1705 || r
== BFD_RELOC_MIPS_CALL_LO16
1706 || (ep
->X_op
== O_subtract
1707 && now_seg
== text_section
1708 && r
== BFD_RELOC_PCREL_LO16
));
1712 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1714 && (ep
->X_op
== O_constant
1715 || (ep
->X_op
== O_symbol
1716 && (r
== BFD_RELOC_HI16_S
1717 || r
== BFD_RELOC_HI16
1718 || r
== BFD_RELOC_MIPS_GOT_HI16
1719 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1720 || (ep
->X_op
== O_subtract
1721 && now_seg
== text_section
1722 && r
== BFD_RELOC_PCREL_HI16_S
)));
1723 if (ep
->X_op
== O_constant
)
1725 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1727 r
= BFD_RELOC_UNUSED
;
1732 assert (ep
!= NULL
);
1734 * This allows macro() to pass an immediate expression for
1735 * creating short branches without creating a symbol.
1736 * Note that the expression still might come from the assembly
1737 * input, in which case the value is not checked for range nor
1738 * is a relocation entry generated (yuck).
1740 if (ep
->X_op
== O_constant
)
1742 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1746 r
= BFD_RELOC_16_PCREL_S2
;
1750 assert (ep
!= NULL
);
1751 r
= BFD_RELOC_MIPS_JMP
;
1760 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1762 append_insn (place
, &insn
, ep
, r
, false);
1766 * Generate a "lui" instruction.
1769 macro_build_lui (place
, counter
, ep
, regnum
)
1775 expressionS high_expr
;
1776 struct mips_cl_insn insn
;
1777 bfd_reloc_code_real_type r
;
1778 CONST
char *name
= "lui";
1779 CONST
char *fmt
= "t,u";
1785 high_expr
.X_op
= O_constant
;
1786 high_expr
.X_add_number
= ep
->X_add_number
;
1789 if (high_expr
.X_op
== O_constant
)
1791 /* we can compute the instruction now without a relocation entry */
1792 if (high_expr
.X_add_number
& 0x8000)
1793 high_expr
.X_add_number
+= 0x10000;
1794 high_expr
.X_add_number
=
1795 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1796 r
= BFD_RELOC_UNUSED
;
1800 assert (ep
->X_op
== O_symbol
);
1801 /* _gp_disp is a special case, used from s_cpload. */
1802 assert (mips_pic
== NO_PIC
1803 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1804 r
= BFD_RELOC_HI16_S
;
1808 * If the macro is about to expand into a second instruction,
1809 * print a warning if needed. We need to pass ip as a parameter
1810 * to generate a better warning message here...
1812 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1813 as_warn ("Macro instruction expanded into multiple instructions");
1816 *counter
+= 1; /* bump instruction counter */
1818 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1819 assert (insn
.insn_mo
);
1820 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1821 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1823 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1824 if (r
== BFD_RELOC_UNUSED
)
1826 insn
.insn_opcode
|= high_expr
.X_add_number
;
1827 append_insn (place
, &insn
, NULL
, r
, false);
1830 append_insn (place
, &insn
, &high_expr
, r
, false);
1834 * Generates code to set the $at register to true (one)
1835 * if reg is less than the immediate expression.
1838 set_at (counter
, reg
, unsignedp
)
1843 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1844 macro_build ((char *) NULL
, counter
, &imm_expr
,
1845 unsignedp
? "sltiu" : "slti",
1846 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1849 load_register (counter
, AT
, &imm_expr
, 0);
1850 macro_build ((char *) NULL
, counter
, NULL
,
1851 unsignedp
? "sltu" : "slt",
1852 "d,v,t", AT
, reg
, AT
);
1856 /* Warn if an expression is not a constant. */
1859 check_absolute_expr (ip
, ex
)
1860 struct mips_cl_insn
*ip
;
1863 if (ex
->X_op
!= O_constant
)
1864 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1868 * This routine generates the least number of instructions neccessary to load
1869 * an absolute expression value into a register.
1872 load_register (counter
, reg
, ep
, dbl
)
1879 expressionS hi32
, lo32
;
1881 if (ep
->X_op
!= O_big
)
1883 assert (ep
->X_op
== O_constant
);
1884 if (ep
->X_add_number
< 0x8000
1885 && (ep
->X_add_number
>= 0
1886 || (ep
->X_add_number
>= -0x8000
1889 || sizeof (ep
->X_add_number
) > 4))))
1891 /* We can handle 16 bit signed values with an addiu to
1892 $zero. No need to ever use daddiu here, since $zero and
1893 the result are always correct in 32 bit mode. */
1894 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1895 (int) BFD_RELOC_LO16
);
1898 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1900 /* We can handle 16 bit unsigned values with an ori to
1902 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1903 (int) BFD_RELOC_LO16
);
1906 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1907 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1908 == ~ (offsetT
) 0x7fffffff))
1911 || sizeof (ep
->X_add_number
) > 4
1912 || (ep
->X_add_number
& 0x80000000) == 0))
1914 && (ep
->X_add_number
&~ 0xffffffff) == 0))
1916 /* 32 bit values require an lui. */
1917 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1918 (int) BFD_RELOC_HI16
);
1919 if ((ep
->X_add_number
& 0xffff) != 0)
1920 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1921 (int) BFD_RELOC_LO16
);
1926 /* The value is larger than 32 bits. */
1930 as_bad ("Number larger than 32 bits");
1931 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1932 (int) BFD_RELOC_LO16
);
1936 if (ep
->X_op
!= O_big
)
1940 hi32
.X_add_number
>>= shift
;
1941 hi32
.X_add_number
&= 0xffffffff;
1942 if ((hi32
.X_add_number
& 0x80000000) != 0)
1943 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1945 lo32
.X_add_number
&= 0xffffffff;
1949 assert (ep
->X_add_number
> 2);
1950 if (ep
->X_add_number
== 3)
1951 generic_bignum
[3] = 0;
1952 else if (ep
->X_add_number
> 4)
1953 as_bad ("Number larger than 64 bits");
1954 lo32
.X_op
= O_constant
;
1955 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1956 hi32
.X_op
= O_constant
;
1957 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1960 if (hi32
.X_add_number
== 0)
1964 if (hi32
.X_add_number
== 0xffffffff)
1966 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
1968 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
1969 (int) BFD_RELOC_LO16
);
1972 if (lo32
.X_add_number
& 0x80000000)
1974 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1975 (int) BFD_RELOC_HI16
);
1976 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1977 (int) BFD_RELOC_LO16
);
1981 load_register (counter
, reg
, &hi32
, 0);
1984 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1988 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1997 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
1999 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2000 (int) BFD_RELOC_HI16
);
2001 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2008 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2013 mid16
.X_add_number
>>= 16;
2014 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2015 freg
, (int) BFD_RELOC_LO16
);
2016 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2020 if ((lo32
.X_add_number
& 0xffff) != 0)
2021 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2022 (int) BFD_RELOC_LO16
);
2025 /* Load an address into a register. */
2028 load_address (counter
, reg
, ep
)
2035 if (ep
->X_op
!= O_constant
2036 && ep
->X_op
!= O_symbol
)
2038 as_bad ("expression too complex");
2039 ep
->X_op
= O_constant
;
2042 if (ep
->X_op
== O_constant
)
2044 load_register (counter
, reg
, ep
, 0);
2048 if (mips_pic
== NO_PIC
)
2050 /* If this is a reference to a GP relative symbol, we want
2051 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2053 lui $reg,<sym> (BFD_RELOC_HI16_S)
2054 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2055 If we have an addend, we always use the latter form. */
2056 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2057 || nopic_need_relax (ep
->X_add_symbol
))
2062 macro_build ((char *) NULL
, counter
, ep
,
2063 mips_isa
< 3 ? "addiu" : "daddiu",
2064 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2065 p
= frag_var (rs_machine_dependent
, 8, 0,
2066 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2067 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2069 macro_build_lui (p
, counter
, ep
, reg
);
2072 macro_build (p
, counter
, ep
,
2073 mips_isa
< 3 ? "addiu" : "daddiu",
2074 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2076 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2080 /* If this is a reference to an external symbol, we want
2081 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2083 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2085 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2086 If there is a constant, it must be added in after. */
2087 ex
.X_add_number
= ep
->X_add_number
;
2088 ep
->X_add_number
= 0;
2090 macro_build ((char *) NULL
, counter
, ep
,
2091 mips_isa
< 3 ? "lw" : "ld",
2092 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2093 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2094 p
= frag_var (rs_machine_dependent
, 4, 0,
2095 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2096 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2097 macro_build (p
, counter
, ep
,
2098 mips_isa
< 3 ? "addiu" : "daddiu",
2099 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2100 if (ex
.X_add_number
!= 0)
2102 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2103 as_bad ("PIC code offset overflow (max 16 signed bits)");
2104 ex
.X_op
= O_constant
;
2105 macro_build ((char *) NULL
, counter
, &ex
,
2106 mips_isa
< 3 ? "addiu" : "daddiu",
2107 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2110 else if (mips_pic
== SVR4_PIC
)
2115 /* This is the large GOT case. If this is a reference to an
2116 external symbol, we want
2117 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2119 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2120 Otherwise, for a reference to a local symbol, we want
2121 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2123 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2124 If there is a constant, it must be added in after. */
2125 ex
.X_add_number
= ep
->X_add_number
;
2126 ep
->X_add_number
= 0;
2127 if (reg_needs_delay (GP
))
2132 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2133 (int) BFD_RELOC_MIPS_GOT_HI16
);
2134 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2135 mips_isa
< 3 ? "addu" : "daddu",
2136 "d,v,t", reg
, reg
, GP
);
2137 macro_build ((char *) NULL
, counter
, ep
,
2138 mips_isa
< 3 ? "lw" : "ld",
2139 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2140 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2141 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2142 mips_warn_about_macros
),
2143 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2146 /* We need a nop before loading from $gp. This special
2147 check is required because the lui which starts the main
2148 instruction stream does not refer to $gp, and so will not
2149 insert the nop which may be required. */
2150 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2153 macro_build (p
, counter
, ep
,
2154 mips_isa
< 3 ? "lw" : "ld",
2155 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2157 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2159 macro_build (p
, counter
, ep
,
2160 mips_isa
< 3 ? "addiu" : "daddiu",
2161 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2162 if (ex
.X_add_number
!= 0)
2164 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2165 as_bad ("PIC code offset overflow (max 16 signed bits)");
2166 ex
.X_op
= O_constant
;
2167 macro_build ((char *) NULL
, counter
, &ex
,
2168 mips_isa
< 3 ? "addiu" : "daddiu",
2169 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2172 else if (mips_pic
== EMBEDDED_PIC
)
2175 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2177 macro_build ((char *) NULL
, counter
, ep
,
2178 mips_isa
< 3 ? "addiu" : "daddiu",
2179 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2187 * This routine implements the seemingly endless macro or synthesized
2188 * instructions and addressing modes in the mips assembly language. Many
2189 * of these macros are simple and are similar to each other. These could
2190 * probably be handled by some kind of table or grammer aproach instead of
2191 * this verbose method. Others are not simple macros but are more like
2192 * optimizing code generation.
2193 * One interesting optimization is when several store macros appear
2194 * consecutivly that would load AT with the upper half of the same address.
2195 * The ensuing load upper instructions are ommited. This implies some kind
2196 * of global optimization. We currently only optimize within a single macro.
2197 * For many of the load and store macros if the address is specified as a
2198 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2199 * first load register 'at' with zero and use it as the base register. The
2200 * mips assembler simply uses register $zero. Just one tiny optimization
2205 struct mips_cl_insn
*ip
;
2207 register int treg
, sreg
, dreg
, breg
;
2222 bfd_reloc_code_real_type r
;
2224 int hold_mips_optimize
;
2226 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2227 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2228 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2229 mask
= ip
->insn_mo
->mask
;
2231 expr1
.X_op
= O_constant
;
2232 expr1
.X_op_symbol
= NULL
;
2233 expr1
.X_add_symbol
= NULL
;
2234 expr1
.X_add_number
= 1;
2246 mips_emit_delays ();
2248 mips_any_noreorder
= 1;
2250 expr1
.X_add_number
= 8;
2251 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2253 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2255 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2256 macro_build ((char *) NULL
, &icnt
, NULL
,
2257 dbl
? "dsub" : "sub",
2258 "d,v,t", dreg
, 0, sreg
);
2281 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2283 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2284 (int) BFD_RELOC_LO16
);
2287 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2288 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2307 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2309 if (mask
!= M_NOR_I
)
2310 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2311 sreg
, (int) BFD_RELOC_LO16
);
2314 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2315 treg
, sreg
, (int) BFD_RELOC_LO16
);
2316 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2322 load_register (&icnt
, AT
, &imm_expr
, 0);
2323 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2340 if (imm_expr
.X_add_number
== 0)
2342 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2346 load_register (&icnt
, AT
, &imm_expr
, 0);
2347 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2355 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2356 likely
? "bgezl" : "bgez",
2362 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2363 likely
? "blezl" : "blez",
2367 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2368 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2369 likely
? "beql" : "beq",
2376 /* check for > max integer */
2377 maxnum
= 0x7fffffff;
2385 if (imm_expr
.X_add_number
>= maxnum
2386 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2389 /* result is always false */
2392 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2393 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2397 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2398 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2403 imm_expr
.X_add_number
++;
2407 if (mask
== M_BGEL_I
)
2409 if (imm_expr
.X_add_number
== 0)
2411 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2412 likely
? "bgezl" : "bgez",
2416 if (imm_expr
.X_add_number
== 1)
2418 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2419 likely
? "bgtzl" : "bgtz",
2423 maxnum
= 0x7fffffff;
2431 maxnum
= - maxnum
- 1;
2432 if (imm_expr
.X_add_number
<= maxnum
2433 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2436 /* result is always true */
2437 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2438 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2441 set_at (&icnt
, sreg
, 0);
2442 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2443 likely
? "beql" : "beq",
2454 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2455 likely
? "beql" : "beq",
2459 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2461 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2462 likely
? "beql" : "beq",
2469 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2471 imm_expr
.X_add_number
++;
2475 if (mask
== M_BGEUL_I
)
2477 if (imm_expr
.X_add_number
== 0)
2479 if (imm_expr
.X_add_number
== 1)
2481 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2482 likely
? "bnel" : "bne",
2486 set_at (&icnt
, sreg
, 1);
2487 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2488 likely
? "beql" : "beq",
2497 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2498 likely
? "bgtzl" : "bgtz",
2504 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2505 likely
? "bltzl" : "bltz",
2509 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2510 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2511 likely
? "bnel" : "bne",
2520 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2521 likely
? "bnel" : "bne",
2527 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2529 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2530 likely
? "bnel" : "bne",
2539 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2540 likely
? "blezl" : "blez",
2546 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2547 likely
? "bgezl" : "bgez",
2551 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2552 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2553 likely
? "beql" : "beq",
2560 maxnum
= 0x7fffffff;
2568 if (imm_expr
.X_add_number
>= maxnum
2569 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2571 imm_expr
.X_add_number
++;
2575 if (mask
== M_BLTL_I
)
2577 if (imm_expr
.X_add_number
== 0)
2579 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2580 likely
? "bltzl" : "bltz",
2584 if (imm_expr
.X_add_number
== 1)
2586 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2587 likely
? "blezl" : "blez",
2591 set_at (&icnt
, sreg
, 0);
2592 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2593 likely
? "bnel" : "bne",
2602 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2603 likely
? "beql" : "beq",
2609 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2611 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2612 likely
? "beql" : "beq",
2619 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2621 imm_expr
.X_add_number
++;
2625 if (mask
== M_BLTUL_I
)
2627 if (imm_expr
.X_add_number
== 0)
2629 if (imm_expr
.X_add_number
== 1)
2631 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2632 likely
? "beql" : "beq",
2636 set_at (&icnt
, sreg
, 1);
2637 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2638 likely
? "bnel" : "bne",
2647 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2648 likely
? "bltzl" : "bltz",
2654 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2655 likely
? "bgtzl" : "bgtz",
2659 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2660 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2661 likely
? "bnel" : "bne",
2672 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2673 likely
? "bnel" : "bne",
2677 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2679 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2680 likely
? "bnel" : "bne",
2696 as_warn ("Divide by zero.");
2698 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2700 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2704 mips_emit_delays ();
2706 mips_any_noreorder
= 1;
2707 macro_build ((char *) NULL
, &icnt
, NULL
,
2708 dbl
? "ddiv" : "div",
2709 "z,s,t", sreg
, treg
);
2711 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2714 expr1
.X_add_number
= 8;
2715 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2716 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2717 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2719 expr1
.X_add_number
= -1;
2720 macro_build ((char *) NULL
, &icnt
, &expr1
,
2721 dbl
? "daddiu" : "addiu",
2722 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2723 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2724 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2727 expr1
.X_add_number
= 1;
2728 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2729 (int) BFD_RELOC_LO16
);
2730 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2735 expr1
.X_add_number
= 0x80000000;
2736 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2737 (int) BFD_RELOC_HI16
);
2740 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2743 expr1
.X_add_number
= 8;
2744 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2745 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2746 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2749 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2788 if (imm_expr
.X_add_number
== 0)
2790 as_warn ("Divide by zero.");
2792 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2794 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2797 if (imm_expr
.X_add_number
== 1)
2799 if (strcmp (s2
, "mflo") == 0)
2800 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2803 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2806 if (imm_expr
.X_add_number
== -1
2807 && s
[strlen (s
) - 1] != 'u')
2809 if (strcmp (s2
, "mflo") == 0)
2812 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2815 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2819 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2823 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2824 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2825 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2844 mips_emit_delays ();
2846 mips_any_noreorder
= 1;
2847 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2849 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2852 expr1
.X_add_number
= 8;
2853 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2854 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2855 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2858 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2864 /* Load the address of a symbol into a register. If breg is not
2865 zero, we then add a base register to it. */
2867 /* When generating embedded PIC code, we permit expressions of
2870 where bar is an address in the .text section. These are used
2871 when getting the addresses of functions. We don't permit
2872 X_add_number to be non-zero, because if the symbol is
2873 external the relaxing code needs to know that any addend is
2874 purely the offset to X_op_symbol. */
2875 if (mips_pic
== EMBEDDED_PIC
2876 && offset_expr
.X_op
== O_subtract
2877 && now_seg
== text_section
2878 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2879 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2880 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2881 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2882 ->sy_value
.X_add_symbol
)
2885 && offset_expr
.X_add_number
== 0)
2887 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2888 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2889 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2890 mips_isa
< 3 ? "addiu" : "daddiu",
2891 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2895 if (offset_expr
.X_op
!= O_symbol
2896 && offset_expr
.X_op
!= O_constant
)
2898 as_bad ("expression too complex");
2899 offset_expr
.X_op
= O_constant
;
2913 if (offset_expr
.X_op
== O_constant
)
2914 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2915 else if (mips_pic
== NO_PIC
)
2917 /* If this is a reference to an GP relative symbol, we want
2918 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2920 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2921 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2922 If we have a constant, we need two instructions anyhow,
2923 so we may as well always use the latter form. */
2924 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
2925 || nopic_need_relax (offset_expr
.X_add_symbol
))
2930 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2931 mips_isa
< 3 ? "addiu" : "daddiu",
2932 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2933 p
= frag_var (rs_machine_dependent
, 8, 0,
2934 RELAX_ENCODE (4, 8, 0, 4, 0,
2935 mips_warn_about_macros
),
2936 offset_expr
.X_add_symbol
, (long) 0,
2939 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2942 macro_build (p
, &icnt
, &offset_expr
,
2943 mips_isa
< 3 ? "addiu" : "daddiu",
2944 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2946 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2948 /* If this is a reference to an external symbol, and there
2949 is no constant, we want
2950 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2951 For a local symbol, we want
2952 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2954 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2956 If we have a small constant, and this is a reference to
2957 an external symbol, we want
2958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2960 addiu $tempreg,$tempreg,<constant>
2961 For a local symbol, we want the same instruction
2962 sequence, but we output a BFD_RELOC_LO16 reloc on the
2965 If we have a large constant, and this is a reference to
2966 an external symbol, we want
2967 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2968 lui $at,<hiconstant>
2969 addiu $at,$at,<loconstant>
2970 addu $tempreg,$tempreg,$at
2971 For a local symbol, we want the same instruction
2972 sequence, but we output a BFD_RELOC_LO16 reloc on the
2973 addiu instruction. */
2974 expr1
.X_add_number
= offset_expr
.X_add_number
;
2975 offset_expr
.X_add_number
= 0;
2977 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2979 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2980 if (expr1
.X_add_number
== 0)
2988 /* We're going to put in an addu instruction using
2989 tempreg, so we may as well insert the nop right
2991 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2995 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2996 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2998 ? mips_warn_about_macros
3000 offset_expr
.X_add_symbol
, (long) 0,
3004 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3007 macro_build (p
, &icnt
, &expr1
,
3008 mips_isa
< 3 ? "addiu" : "daddiu",
3009 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3010 /* FIXME: If breg == 0, and the next instruction uses
3011 $tempreg, then if this variant case is used an extra
3012 nop will be generated. */
3014 else if (expr1
.X_add_number
>= -0x8000
3015 && expr1
.X_add_number
< 0x8000)
3017 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3019 macro_build ((char *) NULL
, &icnt
, &expr1
,
3020 mips_isa
< 3 ? "addiu" : "daddiu",
3021 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3022 (void) frag_var (rs_machine_dependent
, 0, 0,
3023 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3024 offset_expr
.X_add_symbol
, (long) 0,
3031 /* If we are going to add in a base register, and the
3032 target register and the base register are the same,
3033 then we are using AT as a temporary register. Since
3034 we want to load the constant into AT, we add our
3035 current AT (from the global offset table) and the
3036 register into the register now, and pretend we were
3037 not using a base register. */
3042 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3045 mips_isa
< 3 ? "addu" : "daddu",
3046 "d,v,t", treg
, AT
, breg
);
3052 /* Set mips_optimize around the lui instruction to avoid
3053 inserting an unnecessary nop after the lw. */
3054 hold_mips_optimize
= mips_optimize
;
3056 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3057 mips_optimize
= hold_mips_optimize
;
3059 macro_build ((char *) NULL
, &icnt
, &expr1
,
3060 mips_isa
< 3 ? "addiu" : "daddiu",
3061 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3062 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3063 mips_isa
< 3 ? "addu" : "daddu",
3064 "d,v,t", tempreg
, tempreg
, AT
);
3065 (void) frag_var (rs_machine_dependent
, 0, 0,
3066 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3067 offset_expr
.X_add_symbol
, (long) 0,
3072 else if (mips_pic
== SVR4_PIC
)
3076 /* This is the large GOT case. If this is a reference to an
3077 external symbol, and there is no constant, we want
3078 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3079 addu $tempreg,$tempreg,$gp
3080 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3081 For a local symbol, we want
3082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3084 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3086 If we have a small constant, and this is a reference to
3087 an external symbol, we want
3088 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3089 addu $tempreg,$tempreg,$gp
3090 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3092 addiu $tempreg,$tempreg,<constant>
3093 For a local symbol, we want
3094 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3096 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3098 If we have a large constant, and this is a reference to
3099 an external symbol, we want
3100 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3101 addu $tempreg,$tempreg,$gp
3102 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3103 lui $at,<hiconstant>
3104 addiu $at,$at,<loconstant>
3105 addu $tempreg,$tempreg,$at
3106 For a local symbol, we want
3107 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3108 lui $at,<hiconstant>
3109 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3110 addu $tempreg,$tempreg,$at
3112 expr1
.X_add_number
= offset_expr
.X_add_number
;
3113 offset_expr
.X_add_number
= 0;
3115 if (reg_needs_delay (GP
))
3119 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3120 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3121 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3122 mips_isa
< 3 ? "addu" : "daddu",
3123 "d,v,t", tempreg
, tempreg
, GP
);
3124 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3126 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3128 if (expr1
.X_add_number
== 0)
3136 /* We're going to put in an addu instruction using
3137 tempreg, so we may as well insert the nop right
3139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3144 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3145 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3148 ? mips_warn_about_macros
3150 offset_expr
.X_add_symbol
, (long) 0,
3153 else if (expr1
.X_add_number
>= -0x8000
3154 && expr1
.X_add_number
< 0x8000)
3156 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3158 macro_build ((char *) NULL
, &icnt
, &expr1
,
3159 mips_isa
< 3 ? "addiu" : "daddiu",
3160 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3162 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3163 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3165 ? mips_warn_about_macros
3167 offset_expr
.X_add_symbol
, (long) 0,
3174 /* If we are going to add in a base register, and the
3175 target register and the base register are the same,
3176 then we are using AT as a temporary register. Since
3177 we want to load the constant into AT, we add our
3178 current AT (from the global offset table) and the
3179 register into the register now, and pretend we were
3180 not using a base register. */
3188 assert (tempreg
== AT
);
3189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3191 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3192 mips_isa
< 3 ? "addu" : "daddu",
3193 "d,v,t", treg
, AT
, breg
);
3198 /* Set mips_optimize around the lui instruction to avoid
3199 inserting an unnecessary nop after the lw. */
3200 hold_mips_optimize
= mips_optimize
;
3202 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3203 mips_optimize
= hold_mips_optimize
;
3205 macro_build ((char *) NULL
, &icnt
, &expr1
,
3206 mips_isa
< 3 ? "addiu" : "daddiu",
3207 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3208 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3209 mips_isa
< 3 ? "addu" : "daddu",
3210 "d,v,t", dreg
, dreg
, AT
);
3212 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3213 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3216 ? mips_warn_about_macros
3218 offset_expr
.X_add_symbol
, (long) 0,
3226 /* This is needed because this instruction uses $gp, but
3227 the first instruction on the main stream does not. */
3228 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3231 macro_build (p
, &icnt
, &offset_expr
,
3233 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3235 if (expr1
.X_add_number
>= -0x8000
3236 && expr1
.X_add_number
< 0x8000)
3238 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3240 macro_build (p
, &icnt
, &expr1
,
3241 mips_isa
< 3 ? "addiu" : "daddiu",
3242 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3243 /* FIXME: If add_number is 0, and there was no base
3244 register, the external symbol case ended with a load,
3245 so if the symbol turns out to not be external, and
3246 the next instruction uses tempreg, an unnecessary nop
3247 will be inserted. */
3253 /* We must add in the base register now, as in the
3254 external symbol case. */
3255 assert (tempreg
== AT
);
3256 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3258 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3259 mips_isa
< 3 ? "addu" : "daddu",
3260 "d,v,t", treg
, AT
, breg
);
3263 /* We set breg to 0 because we have arranged to add
3264 it in in both cases. */
3268 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3270 macro_build (p
, &icnt
, &expr1
,
3271 mips_isa
< 3 ? "addiu" : "daddiu",
3272 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3274 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3275 mips_isa
< 3 ? "addu" : "daddu",
3276 "d,v,t", tempreg
, tempreg
, AT
);
3280 else if (mips_pic
== EMBEDDED_PIC
)
3283 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3285 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3286 mips_isa
< 3 ? "addiu" : "daddiu",
3287 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3293 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3294 mips_isa
< 3 ? "addu" : "daddu",
3295 "d,v,t", treg
, tempreg
, breg
);
3303 /* The j instruction may not be used in PIC code, since it
3304 requires an absolute address. We convert it to a b
3306 if (mips_pic
== NO_PIC
)
3307 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3309 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3312 /* The jal instructions must be handled as macros because when
3313 generating PIC code they expand to multi-instruction
3314 sequences. Normally they are simple instructions. */
3319 if (mips_pic
== NO_PIC
3320 || mips_pic
== EMBEDDED_PIC
)
3321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3323 else if (mips_pic
== SVR4_PIC
)
3325 if (sreg
!= PIC_CALL_REG
)
3326 as_warn ("MIPS PIC call to register other than $25");
3328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3330 if (mips_cprestore_offset
< 0)
3331 as_warn ("No .cprestore pseudo-op used in PIC code");
3334 expr1
.X_add_number
= mips_cprestore_offset
;
3335 macro_build ((char *) NULL
, &icnt
, &expr1
,
3336 mips_isa
< 3 ? "lw" : "ld",
3337 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3346 if (mips_pic
== NO_PIC
)
3347 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3348 else if (mips_pic
== SVR4_PIC
)
3350 /* If this is a reference to an external symbol, and we are
3351 using a small GOT, we want
3352 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3356 lw $gp,cprestore($sp)
3357 The cprestore value is set using the .cprestore
3358 pseudo-op. If we are using a big GOT, we want
3359 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3361 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3365 lw $gp,cprestore($sp)
3366 If the symbol is not external, we want
3367 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3369 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3372 lw $gp,cprestore($sp) */
3376 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3377 mips_isa
< 3 ? "lw" : "ld",
3378 "t,o(b)", PIC_CALL_REG
,
3379 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3380 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3382 p
= frag_var (rs_machine_dependent
, 4, 0,
3383 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3384 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3390 if (reg_needs_delay (GP
))
3394 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3395 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3396 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3397 mips_isa
< 3 ? "addu" : "daddu",
3398 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3399 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3400 mips_isa
< 3 ? "lw" : "ld",
3401 "t,o(b)", PIC_CALL_REG
,
3402 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3403 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3405 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3406 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3408 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3411 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3414 macro_build (p
, &icnt
, &offset_expr
,
3415 mips_isa
< 3 ? "lw" : "ld",
3416 "t,o(b)", PIC_CALL_REG
,
3417 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3419 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3422 macro_build (p
, &icnt
, &offset_expr
,
3423 mips_isa
< 3 ? "addiu" : "daddiu",
3424 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3425 (int) BFD_RELOC_LO16
);
3426 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3427 "jalr", "s", PIC_CALL_REG
);
3428 if (mips_cprestore_offset
< 0)
3429 as_warn ("No .cprestore pseudo-op used in PIC code");
3433 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3435 expr1
.X_add_number
= mips_cprestore_offset
;
3436 macro_build ((char *) NULL
, &icnt
, &expr1
,
3437 mips_isa
< 3 ? "lw" : "ld",
3438 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3442 else if (mips_pic
== EMBEDDED_PIC
)
3444 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3445 /* The linker may expand the call to a longer sequence which
3446 uses $at, so we must break rather than return. */
3522 if (breg
== treg
|| coproc
|| lr
)
3591 if (mask
== M_LWC1_AB
3592 || mask
== M_SWC1_AB
3593 || mask
== M_LDC1_AB
3594 || mask
== M_SDC1_AB
3603 if (offset_expr
.X_op
!= O_constant
3604 && offset_expr
.X_op
!= O_symbol
)
3606 as_bad ("expression too complex");
3607 offset_expr
.X_op
= O_constant
;
3610 /* A constant expression in PIC code can be handled just as it
3611 is in non PIC code. */
3612 if (mips_pic
== NO_PIC
3613 || offset_expr
.X_op
== O_constant
)
3615 /* If this is a reference to a GP relative symbol, and there
3616 is no base register, we want
3617 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3618 Otherwise, if there is no base register, we want
3619 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3620 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3621 If we have a constant, we need two instructions anyhow,
3622 so we always use the latter form.
3624 If we have a base register, and this is a reference to a
3625 GP relative symbol, we want
3626 addu $tempreg,$breg,$gp
3627 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3629 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3630 addu $tempreg,$tempreg,$breg
3631 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3632 With a constant we always use the latter case. */
3635 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3636 || nopic_need_relax (offset_expr
.X_add_symbol
))
3641 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3642 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3643 p
= frag_var (rs_machine_dependent
, 8, 0,
3644 RELAX_ENCODE (4, 8, 0, 4, 0,
3645 (mips_warn_about_macros
3646 || (used_at
&& mips_noat
))),
3647 offset_expr
.X_add_symbol
, (long) 0,
3651 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3654 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3655 (int) BFD_RELOC_LO16
, tempreg
);
3659 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3660 || nopic_need_relax (offset_expr
.X_add_symbol
))
3665 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3666 mips_isa
< 3 ? "addu" : "daddu",
3667 "d,v,t", tempreg
, breg
, GP
);
3668 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3669 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3670 p
= frag_var (rs_machine_dependent
, 12, 0,
3671 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3672 offset_expr
.X_add_symbol
, (long) 0,
3675 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3678 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3679 mips_isa
< 3 ? "addu" : "daddu",
3680 "d,v,t", tempreg
, tempreg
, breg
);
3683 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3684 (int) BFD_RELOC_LO16
, tempreg
);
3687 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3689 /* If this is a reference to an external symbol, we want
3690 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3692 <op> $treg,0($tempreg)
3694 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3696 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3697 <op> $treg,0($tempreg)
3698 If there is a base register, we add it to $tempreg before
3699 the <op>. If there is a constant, we stick it in the
3700 <op> instruction. We don't handle constants larger than
3701 16 bits, because we have no way to load the upper 16 bits
3702 (actually, we could handle them for the subset of cases
3703 in which we are not using $at). */
3704 assert (offset_expr
.X_op
== O_symbol
);
3705 expr1
.X_add_number
= offset_expr
.X_add_number
;
3706 offset_expr
.X_add_number
= 0;
3707 if (expr1
.X_add_number
< -0x8000
3708 || expr1
.X_add_number
>= 0x8000)
3709 as_bad ("PIC code offset overflow (max 16 signed bits)");
3711 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3712 mips_isa
< 3 ? "lw" : "ld",
3713 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3714 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3715 p
= frag_var (rs_machine_dependent
, 4, 0,
3716 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3717 offset_expr
.X_add_symbol
, (long) 0,
3719 macro_build (p
, &icnt
, &offset_expr
,
3720 mips_isa
< 3 ? "addiu" : "daddiu",
3721 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3723 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3724 mips_isa
< 3 ? "addu" : "daddu",
3725 "d,v,t", tempreg
, tempreg
, breg
);
3726 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3727 (int) BFD_RELOC_LO16
, tempreg
);
3729 else if (mips_pic
== SVR4_PIC
)
3733 /* If this is a reference to an external symbol, we want
3734 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3735 addu $tempreg,$tempreg,$gp
3736 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3737 <op> $treg,0($tempreg)
3739 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3741 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3742 <op> $treg,0($tempreg)
3743 If there is a base register, we add it to $tempreg before
3744 the <op>. If there is a constant, we stick it in the
3745 <op> instruction. We don't handle constants larger than
3746 16 bits, because we have no way to load the upper 16 bits
3747 (actually, we could handle them for the subset of cases
3748 in which we are not using $at). */
3749 assert (offset_expr
.X_op
== O_symbol
);
3750 expr1
.X_add_number
= offset_expr
.X_add_number
;
3751 offset_expr
.X_add_number
= 0;
3752 if (expr1
.X_add_number
< -0x8000
3753 || expr1
.X_add_number
>= 0x8000)
3754 as_bad ("PIC code offset overflow (max 16 signed bits)");
3755 if (reg_needs_delay (GP
))
3760 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3761 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3762 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3763 mips_isa
< 3 ? "addu" : "daddu",
3764 "d,v,t", tempreg
, tempreg
, GP
);
3765 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3766 mips_isa
< 3 ? "lw" : "ld",
3767 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3769 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3770 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3771 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3774 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3777 macro_build (p
, &icnt
, &offset_expr
,
3778 mips_isa
< 3 ? "lw" : "ld",
3779 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3781 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3783 macro_build (p
, &icnt
, &offset_expr
,
3784 mips_isa
< 3 ? "addiu" : "daddiu",
3785 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3787 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3788 mips_isa
< 3 ? "addu" : "daddu",
3789 "d,v,t", tempreg
, tempreg
, breg
);
3790 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3791 (int) BFD_RELOC_LO16
, tempreg
);
3793 else if (mips_pic
== EMBEDDED_PIC
)
3795 /* If there is no base register, we want
3796 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3797 If there is a base register, we want
3798 addu $tempreg,$breg,$gp
3799 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3801 assert (offset_expr
.X_op
== O_symbol
);
3804 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3805 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3810 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3811 mips_isa
< 3 ? "addu" : "daddu",
3812 "d,v,t", tempreg
, breg
, GP
);
3813 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3814 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3827 load_register (&icnt
, treg
, &imm_expr
, 0);
3831 load_register (&icnt
, treg
, &imm_expr
, 1);
3835 if (imm_expr
.X_op
== O_constant
)
3837 load_register (&icnt
, AT
, &imm_expr
, 0);
3838 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3839 "mtc1", "t,G", AT
, treg
);
3844 assert (offset_expr
.X_op
== O_symbol
3845 && strcmp (segment_name (S_GET_SEGMENT
3846 (offset_expr
.X_add_symbol
)),
3848 && offset_expr
.X_add_number
== 0);
3849 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3850 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3855 /* We know that sym is in the .rdata section. First we get the
3856 upper 16 bits of the address. */
3857 if (mips_pic
== NO_PIC
)
3859 /* FIXME: This won't work for a 64 bit address. */
3860 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3862 else if (mips_pic
== SVR4_PIC
)
3864 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3865 mips_isa
< 3 ? "lw" : "ld",
3866 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3868 else if (mips_pic
== EMBEDDED_PIC
)
3870 /* For embedded PIC we pick up the entire address off $gp in
3871 a single instruction. */
3872 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3873 mips_isa
< 3 ? "addiu" : "daddiu",
3874 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3875 offset_expr
.X_op
= O_constant
;
3876 offset_expr
.X_add_number
= 0;
3881 /* Now we load the register(s). */
3883 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3884 treg
, (int) BFD_RELOC_LO16
, AT
);
3887 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3888 treg
, (int) BFD_RELOC_LO16
, AT
);
3891 /* FIXME: How in the world do we deal with the possible
3893 offset_expr
.X_add_number
+= 4;
3894 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3895 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3899 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3900 does not become a variant frag. */
3901 frag_wane (frag_now
);
3907 assert (offset_expr
.X_op
== O_symbol
3908 && offset_expr
.X_add_number
== 0);
3909 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3910 if (strcmp (s
, ".lit8") == 0)
3914 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3915 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3919 r
= BFD_RELOC_MIPS_LITERAL
;
3924 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3925 if (mips_pic
== SVR4_PIC
)
3926 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3927 mips_isa
< 3 ? "lw" : "ld",
3928 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3931 /* FIXME: This won't work for a 64 bit address. */
3932 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3937 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3938 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3940 /* To avoid confusion in tc_gen_reloc, we must ensure
3941 that this does not become a variant frag. */
3942 frag_wane (frag_now
);
3953 /* Even on a big endian machine $fn comes before $fn+1. We have
3954 to adjust when loading from memory. */
3957 assert (mips_isa
< 2);
3958 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3959 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3961 /* FIXME: A possible overflow which I don't know how to deal
3963 offset_expr
.X_add_number
+= 4;
3964 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3965 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3968 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3969 does not become a variant frag. */
3970 frag_wane (frag_now
);
3979 * The MIPS assembler seems to check for X_add_number not
3980 * being double aligned and generating:
3983 * addiu at,at,%lo(foo+1)
3986 * But, the resulting address is the same after relocation so why
3987 * generate the extra instruction?
4034 if (offset_expr
.X_op
!= O_symbol
4035 && offset_expr
.X_op
!= O_constant
)
4037 as_bad ("expression too complex");
4038 offset_expr
.X_op
= O_constant
;
4041 /* Even on a big endian machine $fn comes before $fn+1. We have
4042 to adjust when loading from memory. We set coproc if we must
4043 load $fn+1 first. */
4044 if (byte_order
== LITTLE_ENDIAN
)
4047 if (mips_pic
== NO_PIC
4048 || offset_expr
.X_op
== O_constant
)
4050 /* If this is a reference to a GP relative symbol, we want
4051 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4052 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4053 If we have a base register, we use this
4055 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4056 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4057 If this is not a GP relative symbol, we want
4058 lui $at,<sym> (BFD_RELOC_HI16_S)
4059 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4060 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4061 If there is a base register, we add it to $at after the
4062 lui instruction. If there is a constant, we always use
4064 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4065 || nopic_need_relax (offset_expr
.X_add_symbol
))
4084 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4085 mips_isa
< 3 ? "addu" : "daddu",
4086 "d,v,t", AT
, breg
, GP
);
4092 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4093 coproc
? treg
+ 1 : treg
,
4094 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4095 offset_expr
.X_add_number
+= 4;
4097 /* Set mips_optimize to 2 to avoid inserting an
4099 hold_mips_optimize
= mips_optimize
;
4101 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4102 coproc
? treg
: treg
+ 1,
4103 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4104 mips_optimize
= hold_mips_optimize
;
4106 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4107 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4108 used_at
&& mips_noat
),
4109 offset_expr
.X_add_symbol
, (long) 0,
4112 /* We just generated two relocs. When tc_gen_reloc
4113 handles this case, it will skip the first reloc and
4114 handle the second. The second reloc already has an
4115 extra addend of 4, which we added above. We must
4116 subtract it out, and then subtract another 4 to make
4117 the first reloc come out right. The second reloc
4118 will come out right because we are going to add 4 to
4119 offset_expr when we build its instruction below. */
4120 offset_expr
.X_add_number
-= 8;
4121 offset_expr
.X_op
= O_constant
;
4123 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4128 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4129 mips_isa
< 3 ? "addu" : "daddu",
4130 "d,v,t", AT
, breg
, AT
);
4134 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4135 coproc
? treg
+ 1 : treg
,
4136 (int) BFD_RELOC_LO16
, AT
);
4139 /* FIXME: How do we handle overflow here? */
4140 offset_expr
.X_add_number
+= 4;
4141 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4142 coproc
? treg
: treg
+ 1,
4143 (int) BFD_RELOC_LO16
, AT
);
4145 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4149 /* If this is a reference to an external symbol, we want
4150 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4155 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4157 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4158 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4159 If there is a base register we add it to $at before the
4160 lwc1 instructions. If there is a constant we include it
4161 in the lwc1 instructions. */
4163 expr1
.X_add_number
= offset_expr
.X_add_number
;
4164 offset_expr
.X_add_number
= 0;
4165 if (expr1
.X_add_number
< -0x8000
4166 || expr1
.X_add_number
>= 0x8000 - 4)
4167 as_bad ("PIC code offset overflow (max 16 signed bits)");
4172 frag_grow (24 + off
);
4173 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4174 mips_isa
< 3 ? "lw" : "ld",
4175 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4176 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4178 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4179 mips_isa
< 3 ? "addu" : "daddu",
4180 "d,v,t", AT
, breg
, AT
);
4181 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4182 coproc
? treg
+ 1 : treg
,
4183 (int) BFD_RELOC_LO16
, AT
);
4184 expr1
.X_add_number
+= 4;
4186 /* Set mips_optimize to 2 to avoid inserting an undesired
4188 hold_mips_optimize
= mips_optimize
;
4190 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4191 coproc
? treg
: treg
+ 1,
4192 (int) BFD_RELOC_LO16
, AT
);
4193 mips_optimize
= hold_mips_optimize
;
4195 (void) frag_var (rs_machine_dependent
, 0, 0,
4196 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4197 offset_expr
.X_add_symbol
, (long) 0,
4200 else if (mips_pic
== SVR4_PIC
)
4204 /* If this is a reference to an external symbol, we want
4205 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4207 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4212 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4214 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4215 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4216 If there is a base register we add it to $at before the
4217 lwc1 instructions. If there is a constant we include it
4218 in the lwc1 instructions. */
4220 expr1
.X_add_number
= offset_expr
.X_add_number
;
4221 offset_expr
.X_add_number
= 0;
4222 if (expr1
.X_add_number
< -0x8000
4223 || expr1
.X_add_number
>= 0x8000 - 4)
4224 as_bad ("PIC code offset overflow (max 16 signed bits)");
4225 if (reg_needs_delay (GP
))
4234 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4235 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4236 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4237 mips_isa
< 3 ? "addu" : "daddu",
4238 "d,v,t", AT
, AT
, GP
);
4239 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4240 mips_isa
< 3 ? "lw" : "ld",
4241 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4242 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4244 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4245 mips_isa
< 3 ? "addu" : "daddu",
4246 "d,v,t", AT
, breg
, AT
);
4247 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4248 coproc
? treg
+ 1 : treg
,
4249 (int) BFD_RELOC_LO16
, AT
);
4250 expr1
.X_add_number
+= 4;
4252 /* Set mips_optimize to 2 to avoid inserting an undesired
4254 hold_mips_optimize
= mips_optimize
;
4256 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4257 coproc
? treg
: treg
+ 1,
4258 (int) BFD_RELOC_LO16
, AT
);
4259 mips_optimize
= hold_mips_optimize
;
4260 expr1
.X_add_number
-= 4;
4262 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4263 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4264 8 + gpdel
+ off
, 1, 0),
4265 offset_expr
.X_add_symbol
, (long) 0,
4269 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4272 macro_build (p
, &icnt
, &offset_expr
,
4273 mips_isa
< 3 ? "lw" : "ld",
4274 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4276 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4280 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4281 mips_isa
< 3 ? "addu" : "daddu",
4282 "d,v,t", AT
, breg
, AT
);
4285 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4286 coproc
? treg
+ 1 : treg
,
4287 (int) BFD_RELOC_LO16
, AT
);
4289 expr1
.X_add_number
+= 4;
4291 /* Set mips_optimize to 2 to avoid inserting an undesired
4293 hold_mips_optimize
= mips_optimize
;
4295 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4296 coproc
? treg
: treg
+ 1,
4297 (int) BFD_RELOC_LO16
, AT
);
4298 mips_optimize
= hold_mips_optimize
;
4300 else if (mips_pic
== EMBEDDED_PIC
)
4302 /* If there is no base register, we use
4303 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4304 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4305 If we have a base register, we use
4307 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4308 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4318 mips_isa
< 3 ? "addu" : "daddu",
4319 "d,v,t", AT
, breg
, GP
);
4324 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4325 coproc
? treg
+ 1 : treg
,
4326 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4327 offset_expr
.X_add_number
+= 4;
4328 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4329 coproc
? treg
: treg
+ 1,
4330 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4346 assert (mips_isa
< 3);
4347 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4348 (int) BFD_RELOC_LO16
, breg
);
4349 offset_expr
.X_add_number
+= 4;
4350 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4351 (int) BFD_RELOC_LO16
, breg
);
4353 #ifdef LOSING_COMPILER
4359 as_warn ("Macro used $at after \".set noat\"");
4364 struct mips_cl_insn
*ip
;
4366 register int treg
, sreg
, dreg
, breg
;
4381 bfd_reloc_code_real_type r
;
4384 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4385 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4386 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4387 mask
= ip
->insn_mo
->mask
;
4389 expr1
.X_op
= O_constant
;
4390 expr1
.X_op_symbol
= NULL
;
4391 expr1
.X_add_symbol
= NULL
;
4392 expr1
.X_add_number
= 1;
4396 #endif /* LOSING_COMPILER */
4401 macro_build ((char *) NULL
, &icnt
, NULL
,
4402 dbl
? "dmultu" : "multu",
4404 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4410 /* The MIPS assembler some times generates shifts and adds. I'm
4411 not trying to be that fancy. GCC should do this for us
4413 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4414 macro_build ((char *) NULL
, &icnt
, NULL
,
4415 dbl
? "dmult" : "mult",
4417 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4423 mips_emit_delays ();
4425 mips_any_noreorder
= 1;
4426 macro_build ((char *) NULL
, &icnt
, NULL
,
4427 dbl
? "dmult" : "mult",
4429 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4430 macro_build ((char *) NULL
, &icnt
, NULL
,
4431 dbl
? "dsra32" : "sra",
4432 "d,w,<", dreg
, dreg
, 31);
4433 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4435 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4438 expr1
.X_add_number
= 8;
4439 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4440 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4441 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4444 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4450 mips_emit_delays ();
4452 mips_any_noreorder
= 1;
4453 macro_build ((char *) NULL
, &icnt
, NULL
,
4454 dbl
? "dmultu" : "multu",
4456 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4457 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4459 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4462 expr1
.X_add_number
= 8;
4463 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4464 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4465 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4471 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4472 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4473 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4475 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4479 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4480 (int) (imm_expr
.X_add_number
& 0x1f));
4481 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4482 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4483 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4487 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4488 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4489 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4491 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4495 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4496 (int) (imm_expr
.X_add_number
& 0x1f));
4497 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4498 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4499 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4503 assert (mips_isa
< 2);
4504 /* Even on a big endian machine $fn comes before $fn+1. We have
4505 to adjust when storing to memory. */
4506 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4507 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4508 (int) BFD_RELOC_LO16
, breg
);
4509 offset_expr
.X_add_number
+= 4;
4510 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4511 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4512 (int) BFD_RELOC_LO16
, breg
);
4517 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4518 treg
, (int) BFD_RELOC_LO16
);
4520 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4521 sreg
, (int) BFD_RELOC_LO16
);
4524 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4526 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4527 dreg
, (int) BFD_RELOC_LO16
);
4532 if (imm_expr
.X_add_number
== 0)
4534 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4535 sreg
, (int) BFD_RELOC_LO16
);
4540 as_warn ("Instruction %s: result is always false",
4542 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4545 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4547 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4548 sreg
, (int) BFD_RELOC_LO16
);
4551 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4553 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4554 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4555 mips_isa
< 3 ? "addiu" : "daddiu",
4556 "t,r,j", dreg
, sreg
,
4557 (int) BFD_RELOC_LO16
);
4562 load_register (&icnt
, AT
, &imm_expr
, 0);
4563 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4567 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4568 (int) BFD_RELOC_LO16
);
4573 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4579 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4580 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4581 (int) BFD_RELOC_LO16
);
4584 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4586 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4588 macro_build ((char *) NULL
, &icnt
, &expr1
,
4589 mask
== M_SGE_I
? "slti" : "sltiu",
4590 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4595 load_register (&icnt
, AT
, &imm_expr
, 0);
4596 macro_build ((char *) NULL
, &icnt
, NULL
,
4597 mask
== M_SGE_I
? "slt" : "sltu",
4598 "d,v,t", dreg
, sreg
, AT
);
4601 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4602 (int) BFD_RELOC_LO16
);
4607 case M_SGT
: /* sreg > treg <==> treg < sreg */
4613 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4616 case M_SGT_I
: /* sreg > I <==> I < sreg */
4622 load_register (&icnt
, AT
, &imm_expr
, 0);
4623 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4626 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4632 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4633 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4634 (int) BFD_RELOC_LO16
);
4637 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4643 load_register (&icnt
, AT
, &imm_expr
, 0);
4644 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4645 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4646 (int) BFD_RELOC_LO16
);
4650 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4652 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4653 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4656 load_register (&icnt
, AT
, &imm_expr
, 0);
4657 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4661 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4663 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4664 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4667 load_register (&icnt
, AT
, &imm_expr
, 0);
4668 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4674 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4677 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4681 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4683 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4689 if (imm_expr
.X_add_number
== 0)
4691 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4697 as_warn ("Instruction %s: result is always true",
4699 macro_build ((char *) NULL
, &icnt
, &expr1
,
4700 mips_isa
< 3 ? "addiu" : "daddiu",
4701 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4704 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4706 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4707 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4710 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4712 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4713 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4714 mips_isa
< 3 ? "addiu" : "daddiu",
4715 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4720 load_register (&icnt
, AT
, &imm_expr
, 0);
4721 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4725 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4733 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4735 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4736 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4737 dbl
? "daddi" : "addi",
4738 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4741 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4742 macro_build ((char *) NULL
, &icnt
, NULL
,
4743 dbl
? "dsub" : "sub",
4744 "d,v,t", dreg
, sreg
, AT
);
4750 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4752 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4753 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4754 dbl
? "daddiu" : "addiu",
4755 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4758 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4759 macro_build ((char *) NULL
, &icnt
, NULL
,
4760 dbl
? "dsubu" : "subu",
4761 "d,v,t", dreg
, sreg
, AT
);
4782 load_register (&icnt
, AT
, &imm_expr
, 0);
4783 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4788 assert (mips_isa
< 2);
4789 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4790 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4793 * Is the double cfc1 instruction a bug in the mips assembler;
4794 * or is there a reason for it?
4796 mips_emit_delays ();
4798 mips_any_noreorder
= 1;
4799 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4800 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4801 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4802 expr1
.X_add_number
= 3;
4803 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4804 (int) BFD_RELOC_LO16
);
4805 expr1
.X_add_number
= 2;
4806 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4807 (int) BFD_RELOC_LO16
);
4808 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4809 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4810 macro_build ((char *) NULL
, &icnt
, NULL
,
4811 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4812 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4813 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4823 if (offset_expr
.X_add_number
>= 0x7fff)
4824 as_bad ("operand overflow");
4825 /* avoid load delay */
4826 if (byte_order
== LITTLE_ENDIAN
)
4827 offset_expr
.X_add_number
+= 1;
4828 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4829 (int) BFD_RELOC_LO16
, breg
);
4830 if (byte_order
== LITTLE_ENDIAN
)
4831 offset_expr
.X_add_number
-= 1;
4833 offset_expr
.X_add_number
+= 1;
4834 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4835 (int) BFD_RELOC_LO16
, breg
);
4836 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4837 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4850 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4851 as_bad ("operand overflow");
4852 if (byte_order
== LITTLE_ENDIAN
)
4853 offset_expr
.X_add_number
+= off
;
4854 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4855 (int) BFD_RELOC_LO16
, breg
);
4856 if (byte_order
== LITTLE_ENDIAN
)
4857 offset_expr
.X_add_number
-= off
;
4859 offset_expr
.X_add_number
+= off
;
4860 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4861 (int) BFD_RELOC_LO16
, breg
);
4874 load_address (&icnt
, AT
, &offset_expr
);
4876 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4877 mips_isa
< 3 ? "addu" : "daddu",
4878 "d,v,t", AT
, AT
, breg
);
4879 if (byte_order
== LITTLE_ENDIAN
)
4880 expr1
.X_add_number
= off
;
4882 expr1
.X_add_number
= 0;
4883 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4884 (int) BFD_RELOC_LO16
, AT
);
4885 if (byte_order
== LITTLE_ENDIAN
)
4886 expr1
.X_add_number
= 0;
4888 expr1
.X_add_number
= off
;
4889 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4890 (int) BFD_RELOC_LO16
, AT
);
4895 load_address (&icnt
, AT
, &offset_expr
);
4897 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4898 mips_isa
< 3 ? "addu" : "daddu",
4899 "d,v,t", AT
, AT
, breg
);
4900 if (byte_order
== BIG_ENDIAN
)
4901 expr1
.X_add_number
= 0;
4902 macro_build ((char *) NULL
, &icnt
, &expr1
,
4903 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4904 (int) BFD_RELOC_LO16
, AT
);
4905 if (byte_order
== BIG_ENDIAN
)
4906 expr1
.X_add_number
= 1;
4908 expr1
.X_add_number
= 0;
4909 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4910 (int) BFD_RELOC_LO16
, AT
);
4911 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4913 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4918 if (offset_expr
.X_add_number
>= 0x7fff)
4919 as_bad ("operand overflow");
4920 if (byte_order
== BIG_ENDIAN
)
4921 offset_expr
.X_add_number
+= 1;
4922 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4923 (int) BFD_RELOC_LO16
, breg
);
4924 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4925 if (byte_order
== BIG_ENDIAN
)
4926 offset_expr
.X_add_number
-= 1;
4928 offset_expr
.X_add_number
+= 1;
4929 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4930 (int) BFD_RELOC_LO16
, breg
);
4943 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4944 as_bad ("operand overflow");
4945 if (byte_order
== LITTLE_ENDIAN
)
4946 offset_expr
.X_add_number
+= off
;
4947 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4948 (int) BFD_RELOC_LO16
, breg
);
4949 if (byte_order
== LITTLE_ENDIAN
)
4950 offset_expr
.X_add_number
-= off
;
4952 offset_expr
.X_add_number
+= off
;
4953 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4954 (int) BFD_RELOC_LO16
, breg
);
4967 load_address (&icnt
, AT
, &offset_expr
);
4969 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4970 mips_isa
< 3 ? "addu" : "daddu",
4971 "d,v,t", AT
, AT
, breg
);
4972 if (byte_order
== LITTLE_ENDIAN
)
4973 expr1
.X_add_number
= off
;
4975 expr1
.X_add_number
= 0;
4976 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4977 (int) BFD_RELOC_LO16
, AT
);
4978 if (byte_order
== LITTLE_ENDIAN
)
4979 expr1
.X_add_number
= 0;
4981 expr1
.X_add_number
= off
;
4982 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4983 (int) BFD_RELOC_LO16
, AT
);
4987 load_address (&icnt
, AT
, &offset_expr
);
4989 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4990 mips_isa
< 3 ? "addu" : "daddu",
4991 "d,v,t", AT
, AT
, breg
);
4992 if (byte_order
== LITTLE_ENDIAN
)
4993 expr1
.X_add_number
= 0;
4994 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4995 (int) BFD_RELOC_LO16
, AT
);
4996 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4998 if (byte_order
== LITTLE_ENDIAN
)
4999 expr1
.X_add_number
= 1;
5001 expr1
.X_add_number
= 0;
5002 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5003 (int) BFD_RELOC_LO16
, AT
);
5004 if (byte_order
== LITTLE_ENDIAN
)
5005 expr1
.X_add_number
= 0;
5007 expr1
.X_add_number
= 1;
5008 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5009 (int) BFD_RELOC_LO16
, AT
);
5010 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5012 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5017 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5021 as_warn ("Macro used $at after \".set noat\"");
5024 /* This routine assembles an instruction into its binary format. As a
5025 side effect, it sets one of the global variables imm_reloc or
5026 offset_reloc to the type of relocation to do if one of the operands
5027 is an address expression. */
5032 struct mips_cl_insn
*ip
;
5037 struct mips_opcode
*insn
;
5040 unsigned int lastregno
= 0;
5045 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5057 as_fatal ("Unknown opcode: `%s'", str
);
5059 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5061 insn_error
= "unrecognized opcode";
5069 assert (strcmp (insn
->name
, str
) == 0);
5071 if (insn
->pinfo
== INSN_MACRO
)
5072 insn_isa
= insn
->match
;
5073 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5075 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5077 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5082 if (insn_isa
> mips_isa
5083 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5085 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5087 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5090 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5091 && strcmp (insn
->name
, insn
[1].name
) == 0)
5096 insn_error
= "opcode not supported on this processor";
5101 ip
->insn_opcode
= insn
->match
;
5102 for (args
= insn
->args
;; ++args
)
5108 case '\0': /* end of args */
5121 ip
->insn_opcode
|= lastregno
<< 21;
5126 ip
->insn_opcode
|= lastregno
<< 16;
5130 ip
->insn_opcode
|= lastregno
<< 11;
5136 /* handle optional base register.
5137 Either the base register is omitted or
5138 we must have a left paren. */
5139 /* this is dependent on the next operand specifier
5140 is a 'b' for base register */
5141 assert (args
[1] == 'b');
5145 case ')': /* these must match exactly */
5150 case '<': /* must be at least one digit */
5152 * According to the manual, if the shift amount is greater
5153 * than 31 or less than 0 the the shift amount should be
5154 * mod 32. In reality the mips assembler issues an error.
5155 * We issue a warning and mask out all but the low 5 bits.
5157 my_getExpression (&imm_expr
, s
);
5158 check_absolute_expr (ip
, &imm_expr
);
5159 if ((unsigned long) imm_expr
.X_add_number
> 31)
5161 as_warn ("Improper shift amount (%ld)",
5162 (long) imm_expr
.X_add_number
);
5163 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5165 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5166 imm_expr
.X_op
= O_absent
;
5170 case '>': /* shift amount minus 32 */
5171 my_getExpression (&imm_expr
, s
);
5172 check_absolute_expr (ip
, &imm_expr
);
5173 if ((unsigned long) imm_expr
.X_add_number
< 32
5174 || (unsigned long) imm_expr
.X_add_number
> 63)
5176 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5177 imm_expr
.X_op
= O_absent
;
5181 case 'k': /* cache code */
5182 case 'h': /* prefx code */
5183 my_getExpression (&imm_expr
, s
);
5184 check_absolute_expr (ip
, &imm_expr
);
5185 if ((unsigned long) imm_expr
.X_add_number
> 31)
5187 as_warn ("Invalid value for `%s' (%lu)",
5189 (unsigned long) imm_expr
.X_add_number
);
5190 imm_expr
.X_add_number
&= 0x1f;
5193 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5195 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5196 imm_expr
.X_op
= O_absent
;
5200 case 'c': /* break code */
5201 my_getExpression (&imm_expr
, s
);
5202 check_absolute_expr (ip
, &imm_expr
);
5203 if ((unsigned) imm_expr
.X_add_number
> 1023)
5204 as_warn ("Illegal break code (%ld)",
5205 (long) imm_expr
.X_add_number
);
5206 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5207 imm_expr
.X_op
= O_absent
;
5211 case 'B': /* syscall code */
5212 my_getExpression (&imm_expr
, s
);
5213 check_absolute_expr (ip
, &imm_expr
);
5214 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5215 as_warn ("Illegal syscall code (%ld)",
5216 (long) imm_expr
.X_add_number
);
5217 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5218 imm_expr
.X_op
= O_absent
;
5222 case 'C': /* Coprocessor code */
5223 my_getExpression (&imm_expr
, s
);
5224 check_absolute_expr (ip
, &imm_expr
);
5225 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5227 as_warn ("Coproccesor code > 25 bits (%ld)",
5228 (long) imm_expr
.X_add_number
);
5229 imm_expr
.X_add_number
&= ((1<<25) - 1);
5231 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5232 imm_expr
.X_op
= O_absent
;
5236 case 'b': /* base register */
5237 case 'd': /* destination register */
5238 case 's': /* source register */
5239 case 't': /* target register */
5240 case 'r': /* both target and source */
5241 case 'v': /* both dest and source */
5242 case 'w': /* both dest and target */
5243 case 'E': /* coprocessor target register */
5244 case 'G': /* coprocessor destination register */
5245 case 'x': /* ignore register name */
5246 case 'z': /* must be zero register */
5260 while (isdigit (*s
));
5262 as_bad ("Invalid register number (%d)", regno
);
5264 else if (*args
== 'E' || *args
== 'G')
5268 if (s
[1] == 'f' && s
[2] == 'p')
5273 else if (s
[1] == 's' && s
[2] == 'p')
5278 else if (s
[1] == 'g' && s
[2] == 'p')
5283 else if (s
[1] == 'a' && s
[2] == 't')
5288 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5293 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5305 as_warn ("Used $at without \".set noat\"");
5311 if (c
== 'r' || c
== 'v' || c
== 'w')
5318 /* 'z' only matches $0. */
5319 if (c
== 'z' && regno
!= 0)
5327 ip
->insn_opcode
|= regno
<< 21;
5331 ip
->insn_opcode
|= regno
<< 11;
5336 ip
->insn_opcode
|= regno
<< 16;
5339 /* This case exists because on the r3000 trunc
5340 expands into a macro which requires a gp
5341 register. On the r6000 or r4000 it is
5342 assembled into a single instruction which
5343 ignores the register. Thus the insn version
5344 is MIPS_ISA2 and uses 'x', and the macro
5345 version is MIPS_ISA1 and uses 't'. */
5348 /* This case is for the div instruction, which
5349 acts differently if the destination argument
5350 is $0. This only matches $0, and is checked
5351 outside the switch. */
5362 ip
->insn_opcode
|= lastregno
<< 21;
5365 ip
->insn_opcode
|= lastregno
<< 16;
5370 case 'D': /* floating point destination register */
5371 case 'S': /* floating point source register */
5372 case 'T': /* floating point target register */
5373 case 'R': /* floating point source register */
5377 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5387 while (isdigit (*s
));
5390 as_bad ("Invalid float register number (%d)", regno
);
5392 if ((regno
& 1) != 0
5394 && ! (strcmp (str
, "mtc1") == 0 ||
5395 strcmp (str
, "mfc1") == 0 ||
5396 strcmp (str
, "lwc1") == 0 ||
5397 strcmp (str
, "swc1") == 0))
5398 as_warn ("Float register should be even, was %d",
5406 if (c
== 'V' || c
== 'W')
5416 ip
->insn_opcode
|= regno
<< 6;
5420 ip
->insn_opcode
|= regno
<< 11;
5424 ip
->insn_opcode
|= regno
<< 16;
5427 ip
->insn_opcode
|= regno
<< 21;
5436 ip
->insn_opcode
|= lastregno
<< 11;
5439 ip
->insn_opcode
|= lastregno
<< 16;
5445 my_getExpression (&imm_expr
, s
);
5446 if (imm_expr
.X_op
!= O_big
5447 && imm_expr
.X_op
!= O_constant
)
5448 insn_error
= "absolute expression required";
5453 my_getExpression (&offset_expr
, s
);
5454 imm_reloc
= BFD_RELOC_32
;
5466 unsigned char temp
[8];
5468 unsigned int length
;
5473 /* These only appear as the last operand in an
5474 instruction, and every instruction that accepts
5475 them in any variant accepts them in all variants.
5476 This means we don't have to worry about backing out
5477 any changes if the instruction does not match.
5479 The difference between them is the size of the
5480 floating point constant and where it goes. For 'F'
5481 and 'L' the constant is 64 bits; for 'f' and 'l' it
5482 is 32 bits. Where the constant is placed is based
5483 on how the MIPS assembler does things:
5486 f -- immediate value
5489 The .lit4 and .lit8 sections are only used if
5490 permitted by the -G argument.
5492 When generating embedded PIC code, we use the
5493 .lit8 section but not the .lit4 section (we can do
5494 .lit4 inline easily; we need to put .lit8
5495 somewhere in the data segment, and using .lit8
5496 permits the linker to eventually combine identical
5499 f64
= *args
== 'F' || *args
== 'L';
5501 save_in
= input_line_pointer
;
5502 input_line_pointer
= s
;
5503 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5505 s
= input_line_pointer
;
5506 input_line_pointer
= save_in
;
5507 if (err
!= NULL
&& *err
!= '\0')
5509 as_bad ("Bad floating point constant: %s", err
);
5510 memset (temp
, '\0', sizeof temp
);
5511 length
= f64
? 8 : 4;
5514 assert (length
== (f64
? 8 : 4));
5518 && (! USE_GLOBAL_POINTER_OPT
5519 || mips_pic
== EMBEDDED_PIC
5520 || g_switch_value
< 4)
5523 imm_expr
.X_op
= O_constant
;
5524 if (byte_order
== LITTLE_ENDIAN
)
5525 imm_expr
.X_add_number
=
5526 (((((((int) temp
[3] << 8)
5531 imm_expr
.X_add_number
=
5532 (((((((int) temp
[0] << 8)
5539 const char *newname
;
5542 /* Switch to the right section. */
5544 subseg
= now_subseg
;
5547 default: /* unused default case avoids warnings. */
5549 newname
= RDATA_SECTION_NAME
;
5550 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5554 newname
= RDATA_SECTION_NAME
;
5557 assert (!USE_GLOBAL_POINTER_OPT
5558 || g_switch_value
>= 4);
5562 new_seg
= subseg_new (newname
, (subsegT
) 0);
5563 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5564 bfd_set_section_flags (stdoutput
, new_seg
,
5569 frag_align (*args
== 'l' ? 2 : 3, 0);
5570 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5571 record_alignment (new_seg
, 4);
5573 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5575 as_bad ("Can't use floating point insn in this section");
5577 /* Set the argument to the current address in the
5579 offset_expr
.X_op
= O_symbol
;
5580 offset_expr
.X_add_symbol
=
5581 symbol_new ("L0\001", now_seg
,
5582 (valueT
) frag_now_fix (), frag_now
);
5583 offset_expr
.X_add_number
= 0;
5585 /* Put the floating point number into the section. */
5586 p
= frag_more ((int) length
);
5587 memcpy (p
, temp
, length
);
5589 /* Switch back to the original section. */
5590 subseg_set (seg
, subseg
);
5595 case 'i': /* 16 bit unsigned immediate */
5596 case 'j': /* 16 bit signed immediate */
5597 imm_reloc
= BFD_RELOC_LO16
;
5598 c
= my_getSmallExpression (&imm_expr
, s
);
5603 if (imm_expr
.X_op
== O_constant
)
5604 imm_expr
.X_add_number
=
5605 (imm_expr
.X_add_number
>> 16) & 0xffff;
5608 imm_reloc
= BFD_RELOC_HI16_S
;
5609 imm_unmatched_hi
= true;
5612 imm_reloc
= BFD_RELOC_HI16
;
5617 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5618 || ((imm_expr
.X_add_number
< 0
5619 || imm_expr
.X_add_number
>= 0x10000)
5620 && imm_expr
.X_op
== O_constant
))
5622 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5623 !strcmp (insn
->name
, insn
[1].name
))
5625 if (imm_expr
.X_op
!= O_constant
5626 && imm_expr
.X_op
!= O_big
)
5627 insn_error
= "absolute expression required";
5629 as_bad ("16 bit expression not in range 0..65535");
5637 /* The upper bound should be 0x8000, but
5638 unfortunately the MIPS assembler accepts numbers
5639 from 0x8000 to 0xffff and sign extends them, and
5640 we want to be compatible. We only permit this
5641 extended range for an instruction which does not
5642 provide any further alternates, since those
5643 alternates may handle other cases. People should
5644 use the numbers they mean, rather than relying on
5645 a mysterious sign extension. */
5646 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5647 strcmp (insn
->name
, insn
[1].name
) == 0);
5652 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5653 || ((imm_expr
.X_add_number
< -0x8000
5654 || imm_expr
.X_add_number
>= max
)
5655 && imm_expr
.X_op
== O_constant
)
5657 && imm_expr
.X_add_number
< 0
5659 && imm_expr
.X_unsigned
5660 && sizeof (imm_expr
.X_add_number
) <= 4))
5664 if (imm_expr
.X_op
!= O_constant
5665 && imm_expr
.X_op
!= O_big
)
5666 insn_error
= "absolute expression required";
5668 as_bad ("16 bit expression not in range -32768..32767");
5674 case 'o': /* 16 bit offset */
5675 c
= my_getSmallExpression (&offset_expr
, s
);
5677 /* If this value won't fit into a 16 bit offset, then go
5678 find a macro that will generate the 32 bit offset
5679 code pattern. As a special hack, we accept the
5680 difference of two local symbols as a constant. This
5681 is required to suppose embedded PIC switches, which
5682 use an instruction which looks like
5683 lw $4,$L12-$LS12($4)
5684 The problem with handling this in a more general
5685 fashion is that the macro function doesn't expect to
5686 see anything which can be handled in a single
5687 constant instruction. */
5689 && (offset_expr
.X_op
!= O_constant
5690 || offset_expr
.X_add_number
>= 0x8000
5691 || offset_expr
.X_add_number
< -0x8000)
5692 && (mips_pic
!= EMBEDDED_PIC
5693 || offset_expr
.X_op
!= O_subtract
5694 || now_seg
!= text_section
5695 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5699 offset_reloc
= BFD_RELOC_LO16
;
5700 if (c
== 'h' || c
== 'H')
5702 assert (offset_expr
.X_op
== O_constant
);
5703 offset_expr
.X_add_number
=
5704 (offset_expr
.X_add_number
>> 16) & 0xffff;
5709 case 'p': /* pc relative offset */
5710 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5711 my_getExpression (&offset_expr
, s
);
5715 case 'u': /* upper 16 bits */
5716 c
= my_getSmallExpression (&imm_expr
, s
);
5717 if (imm_expr
.X_op
== O_constant
5718 && (imm_expr
.X_add_number
< 0
5719 || imm_expr
.X_add_number
>= 0x10000))
5720 as_bad ("lui expression not in range 0..65535");
5721 imm_reloc
= BFD_RELOC_LO16
;
5726 if (imm_expr
.X_op
== O_constant
)
5727 imm_expr
.X_add_number
=
5728 (imm_expr
.X_add_number
>> 16) & 0xffff;
5731 imm_reloc
= BFD_RELOC_HI16_S
;
5732 imm_unmatched_hi
= true;
5735 imm_reloc
= BFD_RELOC_HI16
;
5741 case 'a': /* 26 bit address */
5742 my_getExpression (&offset_expr
, s
);
5744 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5747 case 'N': /* 3 bit branch condition code */
5748 case 'M': /* 3 bit compare condition code */
5749 my_getExpression (&imm_expr
, s
);
5750 check_absolute_expr (ip
, &imm_expr
);
5751 if ((unsigned long) imm_expr
.X_add_number
> 7)
5753 as_warn ("Condition code > 7 (%ld)",
5754 (long) imm_expr
.X_add_number
);
5755 imm_expr
.X_add_number
&= 7;
5758 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5760 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5761 imm_expr
.X_op
= O_absent
;
5766 fprintf (stderr
, "bad char = '%c'\n", *args
);
5771 /* Args don't match. */
5772 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5773 !strcmp (insn
->name
, insn
[1].name
))
5779 insn_error
= "illegal operands";
5788 my_getSmallExpression (ep
, str
)
5799 ((str
[1] == 'h' && str
[2] == 'i')
5800 || (str
[1] == 'H' && str
[2] == 'I')
5801 || (str
[1] == 'l' && str
[2] == 'o'))
5813 * A small expression may be followed by a base register.
5814 * Scan to the end of this operand, and then back over a possible
5815 * base register. Then scan the small expression up to that
5816 * point. (Based on code in sparc.c...)
5818 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5820 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5822 if (isdigit (sp
[-2]))
5824 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5826 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5832 else if (sp
- 5 >= str
5835 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5836 || (sp
[-3] == 's' && sp
[-2] == 'p')
5837 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5838 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5844 /* no expression means zero offset */
5847 /* %xx(reg) is an error */
5848 ep
->X_op
= O_absent
;
5853 ep
->X_op
= O_constant
;
5856 ep
->X_add_symbol
= NULL
;
5857 ep
->X_op_symbol
= NULL
;
5858 ep
->X_add_number
= 0;
5863 my_getExpression (ep
, str
);
5870 my_getExpression (ep
, str
);
5871 return c
; /* => %hi or %lo encountered */
5875 my_getExpression (ep
, str
)
5881 save_in
= input_line_pointer
;
5882 input_line_pointer
= str
;
5884 expr_end
= input_line_pointer
;
5885 input_line_pointer
= save_in
;
5888 /* Turn a string in input_line_pointer into a floating point constant
5889 of type type, and store the appropriate bytes in *litP. The number
5890 of LITTLENUMS emitted is stored in *sizeP . An error message is
5891 returned, or NULL on OK. */
5894 md_atof (type
, litP
, sizeP
)
5900 LITTLENUM_TYPE words
[4];
5916 return "bad call to md_atof";
5919 t
= atof_ieee (input_line_pointer
, type
, words
);
5921 input_line_pointer
= t
;
5925 if (byte_order
== LITTLE_ENDIAN
)
5927 for (i
= prec
- 1; i
>= 0; i
--)
5929 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5935 for (i
= 0; i
< prec
; i
++)
5937 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5946 md_number_to_chars (buf
, val
, n
)
5954 number_to_chars_littleendian (buf
, val
, n
);
5958 number_to_chars_bigendian (buf
, val
, n
);
5966 CONST
char *md_shortopts
= "O::g::G:";
5968 struct option md_longopts
[] = {
5969 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5970 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5971 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5972 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5973 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5974 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5975 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5976 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5977 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5978 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5979 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5980 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5981 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5982 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5983 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5984 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5985 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5986 {"break", no_argument
, NULL
, OPTION_BREAK
},
5987 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5988 #define OPTION_EB (OPTION_MD_BASE + 11)
5989 {"EB", no_argument
, NULL
, OPTION_EB
},
5990 #define OPTION_EL (OPTION_MD_BASE + 12)
5991 {"EL", no_argument
, NULL
, OPTION_EL
},
5992 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5993 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5994 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5995 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5996 #define OPTION_M4010 (OPTION_MD_BASE + 15)
5997 {"m4010", no_argument
, NULL
, OPTION_M4010
},
5998 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
5999 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
6000 #define OPTION_M4100 (OPTION_MD_BASE + 17)
6001 {"m4100", no_argument
, NULL
, OPTION_M4100
},
6002 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
6003 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
6005 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
6006 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
6007 #define OPTION_XGOT (OPTION_MD_BASE + 19)
6008 #define OPTION_32 (OPTION_MD_BASE + 20)
6009 #define OPTION_64 (OPTION_MD_BASE + 21)
6011 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
6012 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
6013 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
6014 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
6015 {"32", no_argument
, NULL
, OPTION_32
},
6016 {"64", no_argument
, NULL
, OPTION_64
},
6019 {NULL
, no_argument
, NULL
, 0}
6021 size_t md_longopts_size
= sizeof(md_longopts
);
6024 md_parse_option (c
, arg
)
6039 target_big_endian
= 1;
6043 target_big_endian
= 0;
6047 if (arg
&& arg
[1] == '0')
6057 mips_debug
= atoi (arg
);
6058 /* When the MIPS assembler sees -g or -g2, it does not do
6059 optimizations which limit full symbolic debugging. We take
6060 that to be equivalent to -O0. */
6061 if (mips_debug
== 2)
6093 /* Identify the processor type */
6095 if (strcmp (p
, "default") == 0
6096 || strcmp (p
, "DEFAULT") == 0)
6102 /* We need to cope with the various "vr" prefixes for the 4300
6104 if (*p
== 'v' || *p
== 'V')
6110 if (*p
== 'r' || *p
== 'R')
6117 if (strcmp (p
, "10000") == 0
6118 || strcmp (p
, "10k") == 0
6119 || strcmp (p
, "10K") == 0)
6124 if (strcmp (p
, "2000") == 0
6125 || strcmp (p
, "2k") == 0
6126 || strcmp (p
, "2K") == 0)
6131 if (strcmp (p
, "3000") == 0
6132 || strcmp (p
, "3k") == 0
6133 || strcmp (p
, "3K") == 0)
6138 if (strcmp (p
, "4000") == 0
6139 || strcmp (p
, "4k") == 0
6140 || strcmp (p
, "4K") == 0)
6142 else if (strcmp (p
, "4100") == 0)
6148 else if (strcmp (p
, "4300") == 0)
6150 else if (strcmp (p
, "4400") == 0)
6152 else if (strcmp (p
, "4600") == 0)
6154 else if (strcmp (p
, "4650") == 0)
6160 else if (strcmp (p
, "4010") == 0)
6169 if (strcmp (p
, "6000") == 0
6170 || strcmp (p
, "6k") == 0
6171 || strcmp (p
, "6K") == 0)
6176 if (strcmp (p
, "8000") == 0
6177 || strcmp (p
, "8k") == 0
6178 || strcmp (p
, "8K") == 0)
6183 if (strcmp (p
, "orion") == 0)
6188 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6190 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6196 as_bad ("invalid architecture -mcpu=%s", arg
);
6207 case OPTION_NO_M4650
:
6215 case OPTION_NO_M4010
:
6223 case OPTION_NO_M4100
:
6227 case OPTION_MEMBEDDED_PIC
:
6228 mips_pic
= EMBEDDED_PIC
;
6229 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6231 as_bad ("-G may not be used with embedded PIC code");
6234 g_switch_value
= 0x7fffffff;
6237 /* When generating ELF code, we permit -KPIC and -call_shared to
6238 select SVR4_PIC, and -non_shared to select no PIC. This is
6239 intended to be compatible with Irix 5. */
6240 case OPTION_CALL_SHARED
:
6241 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6243 as_bad ("-call_shared is supported only for ELF format");
6246 mips_pic
= SVR4_PIC
;
6247 if (g_switch_seen
&& g_switch_value
!= 0)
6249 as_bad ("-G may not be used with SVR4 PIC code");
6255 case OPTION_NON_SHARED
:
6256 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6258 as_bad ("-non_shared is supported only for ELF format");
6264 /* The -xgot option tells the assembler to use 32 offsets when
6265 accessing the got in SVR4_PIC mode. It is for Irix
6272 if (! USE_GLOBAL_POINTER_OPT
)
6274 as_bad ("-G is not supported for this configuration");
6277 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6279 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6283 g_switch_value
= atoi (arg
);
6287 /* The -32 and -64 options tell the assembler to output the 32
6288 bit or the 64 bit MIPS ELF format. */
6295 const char **list
, **l
;
6297 list
= bfd_target_list ();
6298 for (l
= list
; *l
!= NULL
; l
++)
6299 if (strcmp (*l
, "elf64-bigmips") == 0
6300 || strcmp (*l
, "elf64-littlemips") == 0)
6303 as_fatal ("No compiled in support for 64 bit object file format");
6317 md_show_usage (stream
)
6322 -membedded-pic generate embedded position independent code\n\
6323 -EB generate big endian output\n\
6324 -EL generate little endian output\n\
6325 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6326 -G NUM allow referencing objects up to NUM bytes\n\
6327 implicitly with the gp register [default 8]\n");
6329 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6330 -mips2, -mcpu=r6000 generate code for r6000\n\
6331 -mips3, -mcpu=r4000 generate code for r4000\n\
6332 -mips4, -mcpu=r8000 generate code for r8000\n\
6333 -mcpu=vr4300 generate code for vr4300\n\
6334 -mcpu=vr4100 generate code for vr4100\n\
6335 -m4650 permit R4650 instructions\n\
6336 -no-m4650 do not permit R4650 instructions\n\
6337 -m4010 permit R4010 instructions\n\
6338 -no-m4010 do not permit R4010 instructions\n\
6339 -m4100 permit VR4100 instructions\n\
6340 -no-m4100 do not permit VR4100 instructions\n");
6342 -O0 remove unneeded NOPs, do not swap branches\n\
6343 -O remove unneeded NOPs and swap branches\n\
6344 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6345 --break, --no-trap break exception on div by 0 and mult overflow\n");
6348 -KPIC, -call_shared generate SVR4 position independent code\n\
6349 -non_shared do not generate position independent code\n\
6350 -xgot assume a 32 bit GOT\n\
6351 -32 create 32 bit object file (default)\n\
6352 -64 create 64 bit object file\n");
6357 mips_init_after_args ()
6359 if (target_big_endian
)
6360 byte_order
= BIG_ENDIAN
;
6362 byte_order
= LITTLE_ENDIAN
;
6366 md_pcrel_from (fixP
)
6369 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6370 && fixP
->fx_addsy
!= (symbolS
*) NULL
6371 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6373 /* This makes a branch to an undefined symbol be a branch to the
6374 current location. */
6378 /* return the address of the delay slot */
6379 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6382 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6383 reloc for a cons. We could use the definition there, except that
6384 we want to handle 64 bit relocs specially. */
6387 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6390 unsigned int nbytes
;
6393 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6395 if (nbytes
== 8 && ! mips_64
)
6397 if (byte_order
== BIG_ENDIAN
)
6402 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6403 as_bad ("Unsupported reloc size %d", nbytes
);
6405 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6408 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6411 /* Sort any unmatched HI16_S relocs so that they immediately precede
6412 the corresponding LO reloc. This is called before md_apply_fix and
6413 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6414 explicit use of the %hi modifier. */
6419 struct mips_hi_fixup
*l
;
6421 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6423 segment_info_type
*seginfo
;
6426 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6428 /* Check quickly whether the next fixup happens to be a matching
6430 if (l
->fixp
->fx_next
!= NULL
6431 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6432 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6433 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6436 /* Look through the fixups for this segment for a matching %lo.
6437 When we find one, move the %hi just in front of it. We do
6438 this in two passes. In the first pass, we try to find a
6439 unique %lo. In the second pass, we permit multiple %hi
6440 relocs for a single %lo (this is a GNU extension). */
6441 seginfo
= seg_info (l
->seg
);
6442 for (pass
= 0; pass
< 2; pass
++)
6447 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6449 /* Check whether this is a %lo fixup which matches l->fixp. */
6450 if (f
->fx_r_type
== BFD_RELOC_LO16
6451 && f
->fx_addsy
== l
->fixp
->fx_addsy
6452 && f
->fx_offset
== l
->fixp
->fx_offset
6455 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6456 || prev
->fx_addsy
!= f
->fx_addsy
6457 || prev
->fx_offset
!= f
->fx_offset
))
6461 /* Move l->fixp before f. */
6462 for (pf
= &seginfo
->fix_root
;
6464 pf
= &(*pf
)->fx_next
)
6465 assert (*pf
!= NULL
);
6467 *pf
= l
->fixp
->fx_next
;
6469 l
->fixp
->fx_next
= f
;
6471 seginfo
->fix_root
= l
->fixp
;
6473 prev
->fx_next
= l
->fixp
;
6485 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6486 "Unmatched %%hi reloc");
6491 /* When generating embedded PIC code we need to use a special
6492 relocation to represent the difference of two symbols in the .text
6493 section (switch tables use a difference of this sort). See
6494 include/coff/mips.h for details. This macro checks whether this
6495 fixup requires the special reloc. */
6496 #define SWITCH_TABLE(fixp) \
6497 ((fixp)->fx_r_type == BFD_RELOC_32 \
6498 && (fixp)->fx_addsy != NULL \
6499 && (fixp)->fx_subsy != NULL \
6500 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6501 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6503 /* When generating embedded PIC code we must keep all PC relative
6504 relocations, in case the linker has to relax a call. We also need
6505 to keep relocations for switch table entries. */
6509 mips_force_relocation (fixp
)
6512 return (mips_pic
== EMBEDDED_PIC
6514 || SWITCH_TABLE (fixp
)
6515 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6516 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6519 /* Apply a fixup to the object file. */
6522 md_apply_fix (fixP
, valueP
)
6529 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6532 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6534 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6537 switch (fixP
->fx_r_type
)
6539 case BFD_RELOC_MIPS_JMP
:
6540 case BFD_RELOC_HI16
:
6541 case BFD_RELOC_HI16_S
:
6542 case BFD_RELOC_MIPS_GPREL
:
6543 case BFD_RELOC_MIPS_LITERAL
:
6544 case BFD_RELOC_MIPS_CALL16
:
6545 case BFD_RELOC_MIPS_GOT16
:
6546 case BFD_RELOC_MIPS_GPREL32
:
6547 case BFD_RELOC_MIPS_GOT_HI16
:
6548 case BFD_RELOC_MIPS_GOT_LO16
:
6549 case BFD_RELOC_MIPS_CALL_HI16
:
6550 case BFD_RELOC_MIPS_CALL_LO16
:
6552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6553 "Invalid PC relative reloc");
6554 /* Nothing needed to do. The value comes from the reloc entry */
6557 case BFD_RELOC_PCREL_HI16_S
:
6558 /* The addend for this is tricky if it is internal, so we just
6559 do everything here rather than in bfd_perform_relocation. */
6560 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6562 /* For an external symbol adjust by the address to make it
6563 pcrel_offset. We use the address of the RELLO reloc
6564 which follows this one. */
6565 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6566 + fixP
->fx_next
->fx_where
);
6571 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6572 if (byte_order
== BIG_ENDIAN
)
6574 md_number_to_chars (buf
, value
, 2);
6577 case BFD_RELOC_PCREL_LO16
:
6578 /* The addend for this is tricky if it is internal, so we just
6579 do everything here rather than in bfd_perform_relocation. */
6580 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6581 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6582 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6583 if (byte_order
== BIG_ENDIAN
)
6585 md_number_to_chars (buf
, value
, 2);
6589 /* If we are deleting this reloc entry, we must fill in the
6590 value now. This can happen if we have a .word which is not
6591 resolved when it appears but is later defined. We also need
6592 to fill in the value if this is an embedded PIC switch table
6595 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6596 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6601 /* If we are deleting this reloc entry, we must fill in the
6603 assert (fixP
->fx_size
== 2);
6605 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6609 case BFD_RELOC_LO16
:
6610 /* When handling an embedded PIC switch statement, we can wind
6611 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6614 if (value
< -0x8000 || value
> 0x7fff)
6615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6616 "relocation overflow");
6617 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6618 if (byte_order
== BIG_ENDIAN
)
6620 md_number_to_chars (buf
, value
, 2);
6624 case BFD_RELOC_16_PCREL_S2
:
6626 * We need to save the bits in the instruction since fixup_segment()
6627 * might be deleting the relocation entry (i.e., a branch within
6628 * the current segment).
6631 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6632 "Branch to odd address (%lx)", value
);
6635 /* update old instruction data */
6636 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6640 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6644 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6652 if (value
>= -0x8000 && value
< 0x8000)
6653 insn
|= value
& 0xffff;
6656 /* The branch offset is too large. If this is an
6657 unconditional branch, and we are not generating PIC code,
6658 we can convert it to an absolute jump instruction. */
6659 if (mips_pic
== NO_PIC
6661 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6662 && (fixP
->fx_frag
->fr_address
6663 < text_section
->vma
+ text_section
->_raw_size
)
6664 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6665 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6666 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6668 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6669 insn
= 0x0c000000; /* jal */
6671 insn
= 0x08000000; /* j */
6672 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6674 fixP
->fx_addsy
= section_symbol (text_section
);
6675 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6679 /* FIXME. It would be possible in principle to handle
6680 conditional branches which overflow. They could be
6681 transformed into a branch around a jump. This would
6682 require setting up variant frags for each different
6683 branch type. The native MIPS assembler attempts to
6684 handle these cases, but it appears to do it
6686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6687 "Relocation overflow");
6691 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6706 const struct mips_opcode
*p
;
6707 int treg
, sreg
, dreg
, shamt
;
6712 for (i
= 0; i
< NUMOPCODES
; ++i
)
6714 p
= &mips_opcodes
[i
];
6715 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6717 printf ("%08lx %s\t", oc
, p
->name
);
6718 treg
= (oc
>> 16) & 0x1f;
6719 sreg
= (oc
>> 21) & 0x1f;
6720 dreg
= (oc
>> 11) & 0x1f;
6721 shamt
= (oc
>> 6) & 0x1f;
6723 for (args
= p
->args
;; ++args
)
6734 printf ("%c", *args
);
6738 assert (treg
== sreg
);
6739 printf ("$%d,$%d", treg
, sreg
);
6744 printf ("$%d", dreg
);
6749 printf ("$%d", treg
);
6753 printf ("0x%x", treg
);
6758 printf ("$%d", sreg
);
6762 printf ("0x%08lx", oc
& 0x1ffffff);
6774 printf ("$%d", shamt
);
6785 printf ("%08lx UNDEFINED\n", oc
);
6796 name
= input_line_pointer
;
6797 c
= get_symbol_end ();
6798 p
= (symbolS
*) symbol_find_or_make (name
);
6799 *input_line_pointer
= c
;
6803 /* Align the current frag to a given power of two. The MIPS assembler
6804 also automatically adjusts any preceding label. */
6807 mips_align (to
, fill
, label
)
6812 mips_emit_delays ();
6813 frag_align (to
, fill
);
6814 record_alignment (now_seg
, to
);
6817 assert (S_GET_SEGMENT (label
) == now_seg
);
6818 label
->sy_frag
= frag_now
;
6819 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6823 /* Align to a given power of two. .align 0 turns off the automatic
6824 alignment used by the data creating pseudo-ops. */
6831 register long temp_fill
;
6832 long max_alignment
= 15;
6836 o Note that the assembler pulls down any immediately preceeding label
6837 to the aligned address.
6838 o It's not documented but auto alignment is reinstated by
6839 a .align pseudo instruction.
6840 o Note also that after auto alignment is turned off the mips assembler
6841 issues an error on attempt to assemble an improperly aligned data item.
6846 temp
= get_absolute_expression ();
6847 if (temp
> max_alignment
)
6848 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6851 as_warn ("Alignment negative: 0 assumed.");
6854 if (*input_line_pointer
== ',')
6856 input_line_pointer
++;
6857 temp_fill
= get_absolute_expression ();
6864 mips_align (temp
, (int) temp_fill
, insn_label
);
6871 demand_empty_rest_of_line ();
6875 mips_flush_pending_output ()
6877 mips_emit_delays ();
6887 /* When generating embedded PIC code, we only use the .text, .lit8,
6888 .sdata and .sbss sections. We change the .data and .rdata
6889 pseudo-ops to use .sdata. */
6890 if (mips_pic
== EMBEDDED_PIC
6891 && (sec
== 'd' || sec
== 'r'))
6894 mips_emit_delays ();
6904 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6905 demand_empty_rest_of_line ();
6909 if (USE_GLOBAL_POINTER_OPT
)
6911 seg
= subseg_new (RDATA_SECTION_NAME
,
6912 (subsegT
) get_absolute_expression ());
6913 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6915 bfd_set_section_flags (stdoutput
, seg
,
6921 bfd_set_section_alignment (stdoutput
, seg
, 4);
6923 demand_empty_rest_of_line ();
6927 as_bad ("No read only data section in this object file format");
6928 demand_empty_rest_of_line ();
6934 if (USE_GLOBAL_POINTER_OPT
)
6936 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6937 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6939 bfd_set_section_flags (stdoutput
, seg
,
6940 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6942 bfd_set_section_alignment (stdoutput
, seg
, 4);
6944 demand_empty_rest_of_line ();
6949 as_bad ("Global pointers not supported; recompile -G 0");
6950 demand_empty_rest_of_line ();
6959 mips_enable_auto_align ()
6971 mips_emit_delays ();
6972 if (log_size
> 0 && auto_align
)
6973 mips_align (log_size
, 0, label
);
6975 cons (1 << log_size
);
6986 mips_emit_delays ();
6990 mips_align (3, 0, label
);
6992 mips_align (2, 0, label
);
6999 /* Handle .globl. We need to override it because on Irix 5 you are
7002 where foo is an undefined symbol, to mean that foo should be
7003 considered to be the address of a function. */
7014 name
= input_line_pointer
;
7015 c
= get_symbol_end ();
7016 symbolP
= symbol_find_or_make (name
);
7017 *input_line_pointer
= c
;
7020 /* On Irix 5, every global symbol that is not explicitly labelled as
7021 being a function is apparently labelled as being an object. */
7024 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7029 secname
= input_line_pointer
;
7030 c
= get_symbol_end ();
7031 sec
= bfd_get_section_by_name (stdoutput
, secname
);
7033 as_bad ("%s: no such section", secname
);
7034 *input_line_pointer
= c
;
7036 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
7037 flag
= BSF_FUNCTION
;
7040 symbolP
->bsym
->flags
|= flag
;
7042 S_SET_EXTERNAL (symbolP
);
7043 demand_empty_rest_of_line ();
7053 opt
= input_line_pointer
;
7054 c
= get_symbol_end ();
7058 /* FIXME: What does this mean? */
7060 else if (strncmp (opt
, "pic", 3) == 0)
7068 mips_pic
= SVR4_PIC
;
7070 as_bad (".option pic%d not supported", i
);
7072 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
7074 if (g_switch_seen
&& g_switch_value
!= 0)
7075 as_warn ("-G may not be used with SVR4 PIC code");
7077 bfd_set_gp_size (stdoutput
, 0);
7081 as_warn ("Unrecognized option \"%s\"", opt
);
7083 *input_line_pointer
= c
;
7084 demand_empty_rest_of_line ();
7091 char *name
= input_line_pointer
, ch
;
7093 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7094 input_line_pointer
++;
7095 ch
= *input_line_pointer
;
7096 *input_line_pointer
= '\0';
7098 if (strcmp (name
, "reorder") == 0)
7102 prev_insn_unreordered
= 1;
7103 prev_prev_insn_unreordered
= 1;
7107 else if (strcmp (name
, "noreorder") == 0)
7109 mips_emit_delays ();
7111 mips_any_noreorder
= 1;
7113 else if (strcmp (name
, "at") == 0)
7117 else if (strcmp (name
, "noat") == 0)
7121 else if (strcmp (name
, "macro") == 0)
7123 mips_warn_about_macros
= 0;
7125 else if (strcmp (name
, "nomacro") == 0)
7127 if (mips_noreorder
== 0)
7128 as_bad ("`noreorder' must be set before `nomacro'");
7129 mips_warn_about_macros
= 1;
7131 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7135 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7139 else if (strcmp (name
, "bopt") == 0)
7143 else if (strcmp (name
, "nobopt") == 0)
7147 else if (strncmp (name
, "mips", 4) == 0)
7151 /* Permit the user to change the ISA on the fly. Needless to
7152 say, misuse can cause serious problems. */
7153 isa
= atoi (name
+ 4);
7155 mips_isa
= file_mips_isa
;
7156 else if (isa
< 1 || isa
> 4)
7157 as_bad ("unknown ISA level");
7163 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7165 *input_line_pointer
= ch
;
7166 demand_empty_rest_of_line ();
7169 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7170 .option pic2. It means to generate SVR4 PIC calls. */
7176 mips_pic
= SVR4_PIC
;
7177 if (USE_GLOBAL_POINTER_OPT
)
7179 if (g_switch_seen
&& g_switch_value
!= 0)
7180 as_warn ("-G may not be used with SVR4 PIC code");
7183 bfd_set_gp_size (stdoutput
, 0);
7184 demand_empty_rest_of_line ();
7187 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7188 PIC code. It sets the $gp register for the function based on the
7189 function address, which is in the register named in the argument.
7190 This uses a relocation against _gp_disp, which is handled specially
7191 by the linker. The result is:
7192 lui $gp,%hi(_gp_disp)
7193 addiu $gp,$gp,%lo(_gp_disp)
7194 addu $gp,$gp,.cpload argument
7195 The .cpload argument is normally $25 == $t9. */
7204 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7205 if (mips_pic
!= SVR4_PIC
)
7211 /* .cpload should be a in .set noreorder section. */
7212 if (mips_noreorder
== 0)
7213 as_warn (".cpload not in noreorder section");
7216 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7217 ex
.X_op_symbol
= NULL
;
7218 ex
.X_add_number
= 0;
7220 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7221 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7223 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7224 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7225 (int) BFD_RELOC_LO16
);
7227 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7228 GP
, GP
, tc_get_register (0));
7230 demand_empty_rest_of_line ();
7233 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7234 offset from $sp. The offset is remembered, and after making a PIC
7235 call $gp is restored from that location. */
7238 s_cprestore (ignore
)
7244 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7245 if (mips_pic
!= SVR4_PIC
)
7251 mips_cprestore_offset
= get_absolute_expression ();
7253 ex
.X_op
= O_constant
;
7254 ex
.X_add_symbol
= NULL
;
7255 ex
.X_op_symbol
= NULL
;
7256 ex
.X_add_number
= mips_cprestore_offset
;
7258 macro_build ((char *) NULL
, &icnt
, &ex
,
7259 mips_isa
< 3 ? "sw" : "sd",
7260 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7262 demand_empty_rest_of_line ();
7265 /* Handle the .gpword pseudo-op. This is used when generating PIC
7266 code. It generates a 32 bit GP relative reloc. */
7276 /* When not generating PIC code, this is treated as .word. */
7277 if (mips_pic
!= SVR4_PIC
)
7284 mips_emit_delays ();
7286 mips_align (2, 0, label
);
7291 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7293 as_bad ("Unsupported use of .gpword");
7294 ignore_rest_of_line ();
7298 md_number_to_chars (p
, (valueT
) 0, 4);
7299 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7300 BFD_RELOC_MIPS_GPREL32
);
7302 demand_empty_rest_of_line ();
7305 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7306 tables in SVR4 PIC code. */
7315 /* This is ignored when not generating SVR4 PIC code. */
7316 if (mips_pic
!= SVR4_PIC
)
7322 /* Add $gp to the register named as an argument. */
7323 reg
= tc_get_register (0);
7324 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7325 mips_isa
< 3 ? "addu" : "daddu",
7326 "d,v,t", reg
, reg
, GP
);
7328 demand_empty_rest_of_line ();
7331 /* Parse a register string into a number. Called from the ECOFF code
7332 to parse .frame. The argument is non-zero if this is the frame
7333 register, so that we can record it in mips_frame_reg. */
7336 tc_get_register (frame
)
7342 if (*input_line_pointer
++ != '$')
7344 as_warn ("expected `$'");
7347 else if (isdigit ((unsigned char) *input_line_pointer
))
7349 reg
= get_absolute_expression ();
7350 if (reg
< 0 || reg
>= 32)
7352 as_warn ("Bad register number");
7358 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7360 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7362 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7364 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7368 as_warn ("Unrecognized register name");
7371 input_line_pointer
+= 2;
7374 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7379 md_section_align (seg
, addr
)
7383 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7386 /* We don't need to align ELF sections to the full alignment.
7387 However, Irix 5 may prefer that we align them at least to a 16
7393 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7396 /* Utility routine, called from above as well. If called while the
7397 input file is still being read, it's only an approximation. (For
7398 example, a symbol may later become defined which appeared to be
7399 undefined earlier.) */
7402 nopic_need_relax (sym
)
7408 if (USE_GLOBAL_POINTER_OPT
)
7410 const char *symname
;
7413 /* Find out whether this symbol can be referenced off the GP
7414 register. It can be if it is smaller than the -G size or if
7415 it is in the .sdata or .sbss section. Certain symbols can
7416 not be referenced off the GP, although it appears as though
7418 symname
= S_GET_NAME (sym
);
7419 if (symname
!= (const char *) NULL
7420 && (strcmp (symname
, "eprol") == 0
7421 || strcmp (symname
, "etext") == 0
7422 || strcmp (symname
, "_gp") == 0
7423 || strcmp (symname
, "edata") == 0
7424 || strcmp (symname
, "_fbss") == 0
7425 || strcmp (symname
, "_fdata") == 0
7426 || strcmp (symname
, "_ftext") == 0
7427 || strcmp (symname
, "end") == 0
7428 || strcmp (symname
, "_gp_disp") == 0))
7430 else if (! S_IS_DEFINED (sym
)
7432 #ifndef NO_ECOFF_DEBUGGING
7433 || (sym
->ecoff_extern_size
!= 0
7434 && sym
->ecoff_extern_size
<= g_switch_value
)
7436 || (S_GET_VALUE (sym
) != 0
7437 && S_GET_VALUE (sym
) <= g_switch_value
)))
7441 const char *segname
;
7443 segname
= segment_name (S_GET_SEGMENT (sym
));
7444 assert (strcmp (segname
, ".lit8") != 0
7445 && strcmp (segname
, ".lit4") != 0);
7446 change
= (strcmp (segname
, ".sdata") != 0
7447 && strcmp (segname
, ".sbss") != 0);
7452 /* We are not optimizing for the GP register. */
7456 /* Estimate the size of a frag before relaxing. We are not really
7457 relaxing here, and the final size is encoded in the subtype
7462 md_estimate_size_before_relax (fragp
, segtype
)
7468 if (mips_pic
== NO_PIC
)
7470 change
= nopic_need_relax (fragp
->fr_symbol
);
7472 else if (mips_pic
== SVR4_PIC
)
7474 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7476 /* This must duplicate the test in adjust_reloc_syms. */
7477 change
= (symsec
!= &bfd_und_section
7478 && symsec
!= &bfd_abs_section
7479 && ! bfd_is_com_section (symsec
));
7486 /* Record the offset to the first reloc in the fr_opcode field.
7487 This lets md_convert_frag and tc_gen_reloc know that the code
7488 must be expanded. */
7489 fragp
->fr_opcode
= (fragp
->fr_literal
7491 - RELAX_OLD (fragp
->fr_subtype
)
7492 + RELAX_RELOC1 (fragp
->fr_subtype
));
7493 /* FIXME: This really needs as_warn_where. */
7494 if (RELAX_WARN (fragp
->fr_subtype
))
7495 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7501 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7504 /* Translate internal representation of relocation info to BFD target
7508 tc_gen_reloc (section
, fixp
)
7512 static arelent
*retval
[4];
7514 bfd_reloc_code_real_type code
;
7516 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7519 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7520 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7522 if (mips_pic
== EMBEDDED_PIC
7523 && SWITCH_TABLE (fixp
))
7525 /* For a switch table entry we use a special reloc. The addend
7526 is actually the difference between the reloc address and the
7528 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7529 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7530 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7531 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7533 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7535 /* We use a special addend for an internal RELLO reloc. */
7536 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7537 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7539 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7541 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7543 assert (fixp
->fx_next
!= NULL
7544 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7545 /* We use a special addend for an internal RELHI reloc. The
7546 reloc is relative to the RELLO; adjust the addend
7548 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7549 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7550 + fixp
->fx_next
->fx_where
7551 - S_GET_VALUE (fixp
->fx_subsy
));
7553 reloc
->addend
= (fixp
->fx_addnumber
7554 + fixp
->fx_next
->fx_frag
->fr_address
7555 + fixp
->fx_next
->fx_where
);
7557 else if (fixp
->fx_pcrel
== 0)
7558 reloc
->addend
= fixp
->fx_addnumber
;
7561 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7562 /* A gruesome hack which is a result of the gruesome gas reloc
7564 reloc
->addend
= reloc
->address
;
7566 reloc
->addend
= -reloc
->address
;
7569 /* If this is a variant frag, we may need to adjust the existing
7570 reloc and generate a new one. */
7571 if (fixp
->fx_frag
->fr_opcode
!= NULL
7572 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7573 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7574 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7575 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7576 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7577 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7578 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7582 /* If this is not the last reloc in this frag, then we have two
7583 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7584 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7585 the second one handle all of them. */
7586 if (fixp
->fx_next
!= NULL
7587 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7589 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7590 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7591 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7592 && (fixp
->fx_next
->fx_r_type
7593 == BFD_RELOC_MIPS_GOT_LO16
))
7594 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7595 && (fixp
->fx_next
->fx_r_type
7596 == BFD_RELOC_MIPS_CALL_LO16
)));
7601 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7602 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7603 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7605 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7606 reloc2
->address
= (reloc
->address
7607 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7608 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7609 reloc2
->addend
= fixp
->fx_addnumber
;
7610 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7611 assert (reloc2
->howto
!= NULL
);
7613 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7617 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7620 reloc3
->address
+= 4;
7623 if (mips_pic
== NO_PIC
)
7625 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7626 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7628 else if (mips_pic
== SVR4_PIC
)
7630 switch (fixp
->fx_r_type
)
7634 case BFD_RELOC_MIPS_GOT16
:
7636 case BFD_RELOC_MIPS_CALL16
:
7637 case BFD_RELOC_MIPS_GOT_LO16
:
7638 case BFD_RELOC_MIPS_CALL_LO16
:
7639 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7647 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
7648 fixup_segment converted a non-PC relative reloc into a PC
7649 relative reloc. In such a case, we need to convert the reloc
7651 code
= fixp
->fx_r_type
;
7657 code
= BFD_RELOC_8_PCREL
;
7660 code
= BFD_RELOC_16_PCREL
;
7663 code
= BFD_RELOC_32_PCREL
;
7665 case BFD_RELOC_8_PCREL
:
7666 case BFD_RELOC_16_PCREL
:
7667 case BFD_RELOC_32_PCREL
:
7668 case BFD_RELOC_16_PCREL_S2
:
7669 case BFD_RELOC_PCREL_HI16_S
:
7670 case BFD_RELOC_PCREL_LO16
:
7673 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7674 "Cannot make %s relocation PC relative",
7675 bfd_get_reloc_code_name (code
));
7679 /* To support a PC relative reloc when generating embedded PIC code
7680 for ECOFF, we use a Cygnus extension. We check for that here to
7681 make sure that we don't let such a reloc escape normally. */
7682 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7683 && code
== BFD_RELOC_16_PCREL_S2
7684 && mips_pic
!= EMBEDDED_PIC
)
7685 reloc
->howto
= NULL
;
7687 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7689 if (reloc
->howto
== NULL
)
7691 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7692 "Can not represent %s relocation in this object file format",
7693 bfd_get_reloc_code_name (code
));
7700 /* Convert a machine dependent frag. */
7703 md_convert_frag (abfd
, asec
, fragp
)
7711 if (fragp
->fr_opcode
== NULL
)
7714 old
= RELAX_OLD (fragp
->fr_subtype
);
7715 new = RELAX_NEW (fragp
->fr_subtype
);
7716 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7719 memcpy (fixptr
- old
, fixptr
, new);
7721 fragp
->fr_fix
+= new - old
;
7724 /* This function is called whenever a label is defined. It is used
7725 when handling branch delays; if a branch has a label, we assume we
7729 mips_define_label (sym
)
7735 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7736 In order to work with gcc when using mips-tfile, we must keep all
7737 local labels. However, in other cases, we want to discard them,
7738 since they are useless. */
7741 mips_local_label (name
)
7744 #ifndef NO_ECOFF_DEBUGGING
7747 && ! ecoff_debugging_seen
)
7749 /* We were called with -g, but we didn't see any debugging
7750 information. That may mean that gcc is smuggling debugging
7751 information through to mips-tfile, in which case we must
7752 generate all local labels. */
7757 /* Here it's OK to discard local labels. */
7759 return name
[0] == '$';
7762 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7764 /* Some special processing for a MIPS ELF file. */
7767 mips_elf_final_processing ()
7769 /* Write out the register information. */
7774 s
.ri_gprmask
= mips_gprmask
;
7775 s
.ri_cprmask
[0] = mips_cprmask
[0];
7776 s
.ri_cprmask
[1] = mips_cprmask
[1];
7777 s
.ri_cprmask
[2] = mips_cprmask
[2];
7778 s
.ri_cprmask
[3] = mips_cprmask
[3];
7779 /* The gp_value field is set by the MIPS ELF backend. */
7781 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7782 ((Elf32_External_RegInfo
*)
7783 mips_regmask_frag
));
7787 Elf64_Internal_RegInfo s
;
7789 s
.ri_gprmask
= mips_gprmask
;
7791 s
.ri_cprmask
[0] = mips_cprmask
[0];
7792 s
.ri_cprmask
[1] = mips_cprmask
[1];
7793 s
.ri_cprmask
[2] = mips_cprmask
[2];
7794 s
.ri_cprmask
[3] = mips_cprmask
[3];
7795 /* The gp_value field is set by the MIPS ELF backend. */
7797 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
7798 ((Elf64_External_RegInfo
*)
7799 mips_regmask_frag
));
7802 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7803 sort of BFD interface for this. */
7804 if (mips_any_noreorder
)
7805 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7806 if (mips_pic
!= NO_PIC
)
7807 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7810 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7812 /* These functions should really be defined by the object file format,
7813 since they are related to debugging information. However, this
7814 code has to work for the a.out format, which does not define them,
7815 so we provide simple versions here. These don't actually generate
7816 any debugging information, but they do simple checking and someday
7817 somebody may make them useful. */
7821 struct loc
*loc_next
;
7822 unsigned long loc_fileno
;
7823 unsigned long loc_lineno
;
7824 unsigned long loc_offset
;
7825 unsigned short loc_delta
;
7826 unsigned short loc_count
;
7835 struct proc
*proc_next
;
7836 struct symbol
*proc_isym
;
7837 struct symbol
*proc_end
;
7838 unsigned long proc_reg_mask
;
7839 unsigned long proc_reg_offset
;
7840 unsigned long proc_fpreg_mask
;
7841 unsigned long proc_fpreg_offset
;
7842 unsigned long proc_frameoffset
;
7843 unsigned long proc_framereg
;
7844 unsigned long proc_pcreg
;
7846 struct file
*proc_file
;
7853 struct file
*file_next
;
7854 unsigned long file_fileno
;
7855 struct symbol
*file_symbol
;
7856 struct symbol
*file_end
;
7857 struct proc
*file_proc
;
7862 static struct obstack proc_frags
;
7863 static procS
*proc_lastP
;
7864 static procS
*proc_rootP
;
7865 static int numprocs
;
7870 obstack_begin (&proc_frags
, 0x2000);
7876 /* check for premature end, nesting errors, etc */
7877 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7878 as_warn ("missing `.end' at end of assembly");
7887 if (*input_line_pointer
== '-')
7889 ++input_line_pointer
;
7892 if (!isdigit (*input_line_pointer
))
7893 as_bad ("Expected simple number.");
7894 if (input_line_pointer
[0] == '0')
7896 if (input_line_pointer
[1] == 'x')
7898 input_line_pointer
+= 2;
7899 while (isxdigit (*input_line_pointer
))
7902 val
|= hex_value (*input_line_pointer
++);
7904 return negative
? -val
: val
;
7908 ++input_line_pointer
;
7909 while (isdigit (*input_line_pointer
))
7912 val
|= *input_line_pointer
++ - '0';
7914 return negative
? -val
: val
;
7917 if (!isdigit (*input_line_pointer
))
7919 printf (" *input_line_pointer == '%c' 0x%02x\n",
7920 *input_line_pointer
, *input_line_pointer
);
7921 as_warn ("Invalid number");
7924 while (isdigit (*input_line_pointer
))
7927 val
+= *input_line_pointer
++ - '0';
7929 return negative
? -val
: val
;
7932 /* The .file directive; just like the usual .file directive, but there
7933 is an initial number which is the ECOFF file index. */
7941 line
= get_number ();
7946 /* The .end directive. */
7954 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7957 demand_empty_rest_of_line ();
7961 if (now_seg
!= text_section
)
7962 as_warn (".end not in text section");
7965 as_warn (".end and no .ent seen yet.");
7971 assert (S_GET_NAME (p
));
7972 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7973 as_warn (".end symbol does not match .ent symbol.");
7976 proc_lastP
->proc_end
= (symbolS
*) 1;
7979 /* The .aent and .ent directives. */
7989 symbolP
= get_symbol ();
7990 if (*input_line_pointer
== ',')
7991 input_line_pointer
++;
7993 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7994 number
= get_number ();
7995 if (now_seg
!= text_section
)
7996 as_warn (".ent or .aent not in text section.");
7998 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7999 as_warn ("missing `.end'");
8003 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
8004 procP
->proc_isym
= symbolP
;
8005 procP
->proc_reg_mask
= 0;
8006 procP
->proc_reg_offset
= 0;
8007 procP
->proc_fpreg_mask
= 0;
8008 procP
->proc_fpreg_offset
= 0;
8009 procP
->proc_frameoffset
= 0;
8010 procP
->proc_framereg
= 0;
8011 procP
->proc_pcreg
= 0;
8012 procP
->proc_end
= NULL
;
8013 procP
->proc_next
= NULL
;
8015 proc_lastP
->proc_next
= procP
;
8021 demand_empty_rest_of_line ();
8024 /* The .frame directive. */
8037 frame_reg
= tc_get_register (1);
8038 if (*input_line_pointer
== ',')
8039 input_line_pointer
++;
8040 frame_off
= get_absolute_expression ();
8041 if (*input_line_pointer
== ',')
8042 input_line_pointer
++;
8043 pcreg
= tc_get_register (0);
8046 assert (proc_rootP
);
8047 proc_rootP
->proc_framereg
= frame_reg
;
8048 proc_rootP
->proc_frameoffset
= frame_off
;
8049 proc_rootP
->proc_pcreg
= pcreg
;
8050 /* bob macho .frame */
8052 /* We don't have to write out a frame stab for unoptimized code. */
8053 if (!(frame_reg
== FP
&& frame_off
== 0))
8056 as_warn ("No .ent for .frame to use.");
8057 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
8058 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
8059 S_SET_TYPE (symP
, N_RMASK
);
8060 S_SET_OTHER (symP
, 0);
8061 S_SET_DESC (symP
, 0);
8062 symP
->sy_forward
= proc_lastP
->proc_isym
;
8063 /* bob perhaps I should have used pseudo set */
8065 demand_empty_rest_of_line ();
8069 /* The .fmask and .mask directives. */
8076 char str
[100], *strP
;
8082 mask
= get_number ();
8083 if (*input_line_pointer
== ',')
8084 input_line_pointer
++;
8085 off
= get_absolute_expression ();
8087 /* bob only for coff */
8088 assert (proc_rootP
);
8089 if (reg_type
== 'F')
8091 proc_rootP
->proc_fpreg_mask
= mask
;
8092 proc_rootP
->proc_fpreg_offset
= off
;
8096 proc_rootP
->proc_reg_mask
= mask
;
8097 proc_rootP
->proc_reg_offset
= off
;
8100 /* bob macho .mask + .fmask */
8102 /* We don't have to write out a mask stab if no saved regs. */
8106 as_warn ("No .ent for .mask to use.");
8108 for (i
= 0; i
< 32; i
++)
8112 sprintf (strP
, "%c%d,", reg_type
, i
);
8113 strP
+= strlen (strP
);
8117 sprintf (strP
, ";%d,", off
);
8118 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
8119 S_SET_TYPE (symP
, N_RMASK
);
8120 S_SET_OTHER (symP
, 0);
8121 S_SET_DESC (symP
, 0);
8122 symP
->sy_forward
= proc_lastP
->proc_isym
;
8123 /* bob perhaps I should have used pseudo set */
8128 /* The .loc directive. */
8139 assert (now_seg
== text_section
);
8141 lineno
= get_number ();
8142 addroff
= frag_now_fix ();
8144 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8145 S_SET_TYPE (symbolP
, N_SLINE
);
8146 S_SET_OTHER (symbolP
, 0);
8147 S_SET_DESC (symbolP
, lineno
);
8148 symbolP
->sy_segment
= now_seg
;