1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
78 #define PIC_CALL_REG 25
86 extern int target_big_endian
;
88 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
89 32 bit ABI. This has no meaning for ECOFF. */
92 /* The default target format to use. */
96 switch (OUTPUT_FLAVOR
)
98 case bfd_target_aout_flavour
:
99 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
100 case bfd_target_ecoff_flavour
:
101 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
102 case bfd_target_elf_flavour
:
103 return (target_big_endian
104 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
105 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
111 /* The name of the readonly data section. */
112 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
114 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* These variables are filled in with the masks of registers used.
121 The object format code reads them and puts them in the appropriate
123 unsigned long mips_gprmask
;
124 unsigned long mips_cprmask
[4];
126 /* MIPS ISA (Instruction Set Architecture) level (may be changed
127 temporarily using .set mipsN). */
128 static int mips_isa
= -1;
130 /* MIPS ISA we are using for this output file. */
131 static int file_mips_isa
;
133 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
134 static int mips_cpu
= -1;
136 /* Whether the 4650 instructions (mad/madu) are permitted. */
137 static int mips_4650
= -1;
139 /* Whether the 4010 instructions are permitted. */
140 static int mips_4010
= -1;
142 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
143 static int mips_4100
= -1;
145 /* Whether the processor uses hardware interlocks, and thus does not
146 require nops to be inserted. */
147 static int interlocks
= -1;
149 /* As with "interlocks" this is used by hardware that has FP
150 (co-processor) interlocks. */
151 static int cop_interlocks
= -1;
153 /* MIPS PIC level. */
157 /* Do not generate PIC code. */
160 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
161 not sure what it is supposed to do. */
164 /* Generate PIC code as in the SVR4 MIPS ABI. */
167 /* Generate PIC code without using a global offset table: the data
168 segment has a maximum size of 64K, all data references are off
169 the $gp register, and all text references are PC relative. This
170 is used on some embedded systems. */
174 static enum mips_pic_level mips_pic
;
176 /* 1 if we should generate 32 bit offsets from the GP register in
177 SVR4_PIC mode. Currently has no meaning in other modes. */
178 static int mips_big_got
;
180 /* 1 if trap instructions should used for overflow rather than break
182 static int mips_trap
;
184 static int mips_warn_about_macros
;
185 static int mips_noreorder
;
186 static int mips_any_noreorder
;
187 static int mips_nomove
;
188 static int mips_noat
;
189 static int mips_nobopt
;
191 /* The size of the small data section. */
192 static int g_switch_value
= 8;
193 /* Whether the -G option was used. */
194 static int g_switch_seen
= 0;
199 /* If we can determine in advance that GP optimization won't be
200 possible, we can skip the relaxation stuff that tries to produce
201 GP-relative references. This makes delay slot optimization work
204 This function can only provide a guess, but it seems to work for
205 gcc output. If it guesses wrong, the only loss should be in
206 efficiency; it shouldn't introduce any bugs.
208 I don't know if a fix is needed for the SVR4_PIC mode. I've only
209 fixed it for the non-PIC mode. KR 95/04/07 */
210 static int nopic_need_relax
PARAMS ((symbolS
*));
212 /* handle of the OPCODE hash table */
213 static struct hash_control
*op_hash
= NULL
;
215 /* This array holds the chars that always start a comment. If the
216 pre-processor is disabled, these aren't very useful */
217 const char comment_chars
[] = "#";
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output */
222 /* Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output. */
225 /* Also note that C style comments are always supported. */
226 const char line_comment_chars
[] = "#";
228 /* This array holds machine specific line separator characters. */
229 const char line_separator_chars
[] = "";
231 /* Chars that can be used to separate mant from exp in floating point nums */
232 const char EXP_CHARS
[] = "eE";
234 /* Chars that mean this number is a floating point constant */
237 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
239 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
240 changed in read.c . Ideally it shouldn't have to know about it at all,
241 but nothing is ideal around here.
244 static char *insn_error
;
246 static int byte_order
;
248 static int auto_align
= 1;
250 /* Symbol labelling the current insn. */
251 static symbolS
*insn_label
;
253 /* When outputting SVR4 PIC code, the assembler needs to know the
254 offset in the stack frame from which to restore the $gp register.
255 This is set by the .cprestore pseudo-op, and saved in this
257 static offsetT mips_cprestore_offset
= -1;
259 /* This is the register which holds the stack frame, as set by the
260 .frame pseudo-op. This is needed to implement .cprestore. */
261 static int mips_frame_reg
= SP
;
263 /* To output NOP instructions correctly, we need to keep information
264 about the previous two instructions. */
266 /* Whether we are optimizing. The default value of 2 means to remove
267 unneeded NOPs and swap branch instructions when possible. A value
268 of 1 means to not swap branches. A value of 0 means to always
270 static int mips_optimize
= 2;
272 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
273 equivalent to seeing no -g option at all. */
274 static int mips_debug
= 0;
276 /* The previous instruction. */
277 static struct mips_cl_insn prev_insn
;
279 /* The instruction before prev_insn. */
280 static struct mips_cl_insn prev_prev_insn
;
282 /* If we don't want information for prev_insn or prev_prev_insn, we
283 point the insn_mo field at this dummy integer. */
284 static const struct mips_opcode dummy_opcode
= { 0 };
286 /* Non-zero if prev_insn is valid. */
287 static int prev_insn_valid
;
289 /* The frag for the previous instruction. */
290 static struct frag
*prev_insn_frag
;
292 /* The offset into prev_insn_frag for the previous instruction. */
293 static long prev_insn_where
;
295 /* The reloc for the previous instruction, if any. */
296 static fixS
*prev_insn_fixp
;
298 /* Non-zero if the previous instruction was in a delay slot. */
299 static int prev_insn_is_delay_slot
;
301 /* Non-zero if the previous instruction was in a .set noreorder. */
302 static int prev_insn_unreordered
;
304 /* Non-zero if the previous previous instruction was in a .set
306 static int prev_prev_insn_unreordered
;
308 /* For ECOFF and ELF, relocations against symbols are done in two
309 parts, with a HI relocation and a LO relocation. Each relocation
310 has only 16 bits of space to store an addend. This means that in
311 order for the linker to handle carries correctly, it must be able
312 to locate both the HI and the LO relocation. This means that the
313 relocations must appear in order in the relocation table.
315 In order to implement this, we keep track of each unmatched HI
316 relocation. We then sort them so that they immediately precede the
317 corresponding LO relocation. */
322 struct mips_hi_fixup
*next
;
325 /* The section this fixup is in. */
329 /* The list of unmatched HI relocs. */
331 static struct mips_hi_fixup
*mips_hi_fixup_list
;
333 /* Since the MIPS does not have multiple forms of PC relative
334 instructions, we do not have to do relaxing as is done on other
335 platforms. However, we do have to handle GP relative addressing
336 correctly, which turns out to be a similar problem.
338 Every macro that refers to a symbol can occur in (at least) two
339 forms, one with GP relative addressing and one without. For
340 example, loading a global variable into a register generally uses
341 a macro instruction like this:
343 If i can be addressed off the GP register (this is true if it is in
344 the .sbss or .sdata section, or if it is known to be smaller than
345 the -G argument) this will generate the following instruction:
347 This instruction will use a GPREL reloc. If i can not be addressed
348 off the GP register, the following instruction sequence will be used:
351 In this case the first instruction will have a HI16 reloc, and the
352 second reloc will have a LO16 reloc. Both relocs will be against
355 The issue here is that we may not know whether i is GP addressable
356 until after we see the instruction that uses it. Therefore, we
357 want to be able to choose the final instruction sequence only at
358 the end of the assembly. This is similar to the way other
359 platforms choose the size of a PC relative instruction only at the
362 When generating position independent code we do not use GP
363 addressing in quite the same way, but the issue still arises as
364 external symbols and local symbols must be handled differently.
366 We handle these issues by actually generating both possible
367 instruction sequences. The longer one is put in a frag_var with
368 type rs_machine_dependent. We encode what to do with the frag in
369 the subtype field. We encode (1) the number of existing bytes to
370 replace, (2) the number of new bytes to use, (3) the offset from
371 the start of the existing bytes to the first reloc we must generate
372 (that is, the offset is applied from the start of the existing
373 bytes after they are replaced by the new bytes, if any), (4) the
374 offset from the start of the existing bytes to the second reloc,
375 (5) whether a third reloc is needed (the third reloc is always four
376 bytes after the second reloc), and (6) whether to warn if this
377 variant is used (this is sometimes needed if .set nomacro or .set
378 noat is in effect). All these numbers are reasonably small.
380 Generating two instruction sequences must be handled carefully to
381 ensure that delay slots are handled correctly. Fortunately, there
382 are a limited number of cases. When the second instruction
383 sequence is generated, append_insn is directed to maintain the
384 existing delay slot information, so it continues to apply to any
385 code after the second instruction sequence. This means that the
386 second instruction sequence must not impose any requirements not
387 required by the first instruction sequence.
389 These variant frags are then handled in functions called by the
390 machine independent code. md_estimate_size_before_relax returns
391 the final size of the frag. md_convert_frag sets up the final form
392 of the frag. tc_gen_reloc adjust the first reloc and adds a second
394 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
398 | (((reloc1) + 64) << 9) \
399 | (((reloc2) + 64) << 2) \
400 | ((reloc3) ? (1 << 1) : 0) \
402 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
403 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
404 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
405 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
406 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
407 #define RELAX_WARN(i) ((i) & 1)
409 /* Prototypes for static functions. */
412 #define internalError() \
413 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
415 #define internalError() as_fatal ("MIPS internal Error");
418 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
419 unsigned int reg
, int fpr
));
420 static int reg_needs_delay
PARAMS ((int));
421 static void append_insn
PARAMS ((char *place
,
422 struct mips_cl_insn
* ip
,
424 bfd_reloc_code_real_type r
,
426 static void mips_no_prev_insn
PARAMS ((void));
427 static void mips_emit_delays
PARAMS ((void));
429 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
430 const char *name
, const char *fmt
,
433 static void macro_build ();
435 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
436 expressionS
* ep
, int regnum
));
437 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
438 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
440 static void load_register
PARAMS ((int *, int, expressionS
*, int));
441 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
442 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
443 #ifdef LOSING_COMPILER
444 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
446 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
447 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
448 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
449 static symbolS
*get_symbol
PARAMS ((void));
450 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
451 static void s_align
PARAMS ((int));
452 static void s_change_sec
PARAMS ((int));
453 static void s_cons
PARAMS ((int));
454 static void s_float_cons
PARAMS ((int));
455 static void s_mips_globl
PARAMS ((int));
456 static void s_option
PARAMS ((int));
457 static void s_mipsset
PARAMS ((int));
458 static void s_abicalls
PARAMS ((int));
459 static void s_cpload
PARAMS ((int));
460 static void s_cprestore
PARAMS ((int));
461 static void s_gpword
PARAMS ((int));
462 static void s_cpadd
PARAMS ((int));
463 static void md_obj_begin
PARAMS ((void));
464 static void md_obj_end
PARAMS ((void));
465 static long get_number
PARAMS ((void));
466 static void s_ent
PARAMS ((int));
467 static void s_mipsend
PARAMS ((int));
468 static void s_file
PARAMS ((int));
472 The following pseudo-ops from the Kane and Heinrich MIPS book
473 should be defined here, but are currently unsupported: .alias,
474 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
476 The following pseudo-ops from the Kane and Heinrich MIPS book are
477 specific to the type of debugging information being generated, and
478 should be defined by the object format: .aent, .begin, .bend,
479 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
482 The following pseudo-ops from the Kane and Heinrich MIPS book are
483 not MIPS CPU specific, but are also not specific to the object file
484 format. This file is probably the best place to define them, but
485 they are not currently supported: .asm0, .endr, .lab, .repeat,
486 .struct, .weakext. */
488 static const pseudo_typeS mips_pseudo_table
[] =
490 /* MIPS specific pseudo-ops. */
491 {"option", s_option
, 0},
492 {"set", s_mipsset
, 0},
493 {"rdata", s_change_sec
, 'r'},
494 {"sdata", s_change_sec
, 's'},
495 {"livereg", s_ignore
, 0},
496 {"abicalls", s_abicalls
, 0},
497 {"cpload", s_cpload
, 0},
498 {"cprestore", s_cprestore
, 0},
499 {"gpword", s_gpword
, 0},
500 {"cpadd", s_cpadd
, 0},
502 /* Relatively generic pseudo-ops that happen to be used on MIPS
504 {"asciiz", stringer
, 1},
505 {"bss", s_change_sec
, 'b'},
508 {"dword", s_cons
, 3},
510 /* These pseudo-ops are defined in read.c, but must be overridden
511 here for one reason or another. */
512 {"align", s_align
, 0},
514 {"data", s_change_sec
, 'd'},
515 {"double", s_float_cons
, 'd'},
516 {"float", s_float_cons
, 'f'},
517 {"globl", s_mips_globl
, 0},
518 {"global", s_mips_globl
, 0},
519 {"hword", s_cons
, 1},
524 {"short", s_cons
, 1},
525 {"single", s_float_cons
, 'f'},
526 {"text", s_change_sec
, 't'},
531 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
532 /* These pseudo-ops should be defined by the object file format.
533 However, a.out doesn't support them, so we have versions here. */
535 {"bgnb", s_ignore
, 0},
536 {"end", s_mipsend
, 0},
537 {"endb", s_ignore
, 0},
540 {"fmask", s_ignore
, 'F'},
541 {"frame", s_ignore
, 0},
542 {"loc", s_ignore
, 0},
543 {"mask", s_ignore
, 'R'},
544 {"verstamp", s_ignore
, 0},
548 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
553 pop_insert (mips_pseudo_table
);
554 if (! ECOFF_DEBUGGING
)
555 pop_insert (mips_nonecoff_pseudo_table
);
558 static char *expr_end
;
560 /* Expressions which appear in instructions. These are set by
563 static expressionS imm_expr
;
564 static expressionS offset_expr
;
566 /* Relocs associated with imm_expr and offset_expr. */
568 static bfd_reloc_code_real_type imm_reloc
;
569 static bfd_reloc_code_real_type offset_reloc
;
571 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
573 static boolean imm_unmatched_hi
;
576 * This function is called once, at assembler startup time. It should
577 * set up all the tables, etc. that the MD part of the assembler will need.
583 register const char *retval
= NULL
;
584 register unsigned int i
= 0;
592 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
594 a
= xmalloc (sizeof TARGET_CPU
);
595 strcpy (a
, TARGET_CPU
);
596 a
[(sizeof TARGET_CPU
) - 3] = '\0';
600 if (strcmp (cpu
, "mips") == 0)
606 else if (strcmp (cpu
, "r6000") == 0
607 || strcmp (cpu
, "mips2") == 0)
613 else if (strcmp (cpu
, "mips64") == 0
614 || strcmp (cpu
, "r4000") == 0
615 || strcmp (cpu
, "mips3") == 0)
621 else if (strcmp (cpu
, "r4400") == 0)
627 else if (strcmp (cpu
, "mips64orion") == 0
628 || strcmp (cpu
, "r4600") == 0)
634 else if (strcmp (cpu
, "r4650") == 0)
642 else if (strcmp (cpu
, "mips64vr4300") == 0)
648 else if (strcmp (cpu
, "mips64vr4100") == 0)
656 else if (strcmp (cpu
, "r4010") == 0)
664 else if (strcmp (cpu
, "r8000") == 0
665 || strcmp (cpu
, "mips4") == 0)
671 else if (strcmp (cpu
, "r10000") == 0)
697 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
702 if (mips_cpu
== 4300)
707 if (mips_isa
< 2 && mips_trap
)
708 as_bad ("trap exception not supported at ISA 1");
713 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
716 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
719 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
722 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
726 as_warn ("Could not set architecture and machine");
728 file_mips_isa
= mips_isa
;
730 op_hash
= hash_new ();
732 for (i
= 0; i
< NUMOPCODES
;)
734 const char *name
= mips_opcodes
[i
].name
;
736 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
739 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
740 mips_opcodes
[i
].name
, retval
);
741 as_fatal ("Broken assembler. No assembly attempted.");
745 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
746 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
747 != mips_opcodes
[i
].match
))
749 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
750 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
751 as_fatal ("Broken assembler. No assembly attempted.");
755 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
758 mips_no_prev_insn ();
766 /* set the default alignment for the text section (2**2) */
767 record_alignment (text_section
, 2);
769 if (USE_GLOBAL_POINTER_OPT
)
770 bfd_set_gp_size (stdoutput
, g_switch_value
);
772 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
774 /* Sections must be aligned to 16 byte boundaries. */
775 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
776 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
777 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
779 /* Create a .reginfo section for register masks and a .mdebug
780 section for debugging information. */
791 sec
= subseg_new (".reginfo", (subsegT
) 0);
793 /* The ABI says this section should be loaded so that the
794 running program can access it. */
795 (void) bfd_set_section_flags (stdoutput
, sec
,
796 (SEC_ALLOC
| SEC_LOAD
797 | SEC_READONLY
| SEC_DATA
));
798 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
801 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
806 /* The 64-bit ABI uses a .MIPS.options section rather than
808 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
809 (void) bfd_set_section_flags (stdoutput
, sec
,
810 (SEC_ALLOC
| SEC_LOAD
811 | SEC_READONLY
| SEC_DATA
));
812 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
815 /* Set up the option header. */
817 Elf_Internal_Options opthdr
;
820 opthdr
.kind
= ODK_REGINFO
;
821 opthdr
.size
= (sizeof (Elf_External_Options
)
822 + sizeof (Elf64_External_RegInfo
));
825 f
= frag_more (sizeof (Elf_External_Options
));
826 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
827 (Elf_External_Options
*) f
);
829 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
836 sec
= subseg_new (".mdebug", (subsegT
) 0);
837 (void) bfd_set_section_flags (stdoutput
, sec
,
838 SEC_HAS_CONTENTS
| SEC_READONLY
);
839 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
842 subseg_set (seg
, subseg
);
846 if (! ECOFF_DEBUGGING
)
853 if (! ECOFF_DEBUGGING
)
861 struct mips_cl_insn insn
;
863 imm_expr
.X_op
= O_absent
;
864 imm_reloc
= BFD_RELOC_UNUSED
;
865 imm_unmatched_hi
= false;
866 offset_expr
.X_op
= O_absent
;
867 offset_reloc
= BFD_RELOC_UNUSED
;
869 mips_ip (str
, &insn
);
872 as_bad ("%s `%s'", insn_error
, str
);
875 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
881 if (imm_expr
.X_op
!= O_absent
)
882 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
884 else if (offset_expr
.X_op
!= O_absent
)
885 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
887 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
891 /* See whether instruction IP reads register REG. If FPR is non-zero,
892 REG is a floating point register. */
895 insn_uses_reg (ip
, reg
, fpr
)
896 struct mips_cl_insn
*ip
;
900 /* Don't report on general register 0, since it never changes. */
901 if (! fpr
&& reg
== 0)
906 /* If we are called with either $f0 or $f1, we must check $f0.
907 This is not optimal, because it will introduce an unnecessary
908 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
909 need to distinguish reading both $f0 and $f1 or just one of
910 them. Note that we don't have to check the other way,
911 because there is no instruction that sets both $f0 and $f1
912 and requires a delay. */
913 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
914 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
915 == (reg
&~ (unsigned) 1)))
917 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
918 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
919 == (reg
&~ (unsigned) 1)))
924 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
925 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
927 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
928 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
935 /* This function returns true if modifying a register requires a
939 reg_needs_delay (reg
)
942 unsigned long prev_pinfo
;
944 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
947 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
949 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
951 /* A load from a coprocessor or from memory. All load
952 delays delay the use of general register rt for one
953 instruction on the r3000. The r6000 and r4000 use
955 know (prev_pinfo
& INSN_WRITE_GPR_T
);
956 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
963 /* Output an instruction. PLACE is where to put the instruction; if
964 it is NULL, this uses frag_more to get room. IP is the instruction
965 information. ADDRESS_EXPR is an operand of the instruction to be
966 used with RELOC_TYPE. */
969 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
971 struct mips_cl_insn
*ip
;
972 expressionS
*address_expr
;
973 bfd_reloc_code_real_type reloc_type
;
974 boolean unmatched_hi
;
976 register unsigned long prev_pinfo
, pinfo
;
981 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
982 pinfo
= ip
->insn_mo
->pinfo
;
984 if (place
== NULL
&& ! mips_noreorder
)
986 /* If the previous insn required any delay slots, see if we need
987 to insert a NOP or two. There are eight kinds of possible
988 hazards, of which an instruction can have at most one type.
989 (1) a load from memory delay
990 (2) a load from a coprocessor delay
991 (3) an unconditional branch delay
992 (4) a conditional branch delay
993 (5) a move to coprocessor register delay
994 (6) a load coprocessor register from memory delay
995 (7) a coprocessor condition code delay
996 (8) a HI/LO special register delay
998 There are a lot of optimizations we could do that we don't.
999 In particular, we do not, in general, reorder instructions.
1000 If you use gcc with optimization, it will reorder
1001 instructions and generally do much more optimization then we
1002 do here; repeating all that work in the assembler would only
1003 benefit hand written assembly code, and does not seem worth
1006 /* This is how a NOP is emitted. */
1007 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
1009 /* The previous insn might require a delay slot, depending upon
1010 the contents of the current insn. */
1012 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1013 && ! cop_interlocks
)
1015 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1017 /* A load from a coprocessor or from memory. All load
1018 delays delay the use of general register rt for one
1019 instruction on the r3000. The r6000 and r4000 use
1021 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1022 if (mips_optimize
== 0
1023 || insn_uses_reg (ip
,
1024 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1029 else if (mips_isa
< 4
1030 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1031 && ! cop_interlocks
)
1033 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1035 /* A generic coprocessor delay. The previous instruction
1036 modified a coprocessor general or control register. If
1037 it modified a control register, we need to avoid any
1038 coprocessor instruction (this is probably not always
1039 required, but it sometimes is). If it modified a general
1040 register, we avoid using that register.
1042 On the r6000 and r4000 loading a coprocessor register
1043 from memory is interlocked, and does not require a delay.
1045 This case is not handled very well. There is no special
1046 knowledge of CP0 handling, and the coprocessors other
1047 than the floating point unit are not distinguished at
1049 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1051 if (mips_optimize
== 0
1052 || insn_uses_reg (ip
,
1053 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1058 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1060 if (mips_optimize
== 0
1061 || insn_uses_reg (ip
,
1062 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1069 /* We don't know exactly what the previous instruction
1070 does. If the current instruction uses a coprocessor
1071 register, we must insert a NOP. If previous
1072 instruction may set the condition codes, and the
1073 current instruction uses them, we must insert two
1075 if (mips_optimize
== 0
1076 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1077 && (pinfo
& INSN_READ_COND_CODE
)))
1079 else if (pinfo
& INSN_COP
)
1083 else if (mips_isa
< 4
1084 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1085 && ! cop_interlocks
)
1087 /* The previous instruction sets the coprocessor condition
1088 codes, but does not require a general coprocessor delay
1089 (this means it is a floating point comparison
1090 instruction). If this instruction uses the condition
1091 codes, we need to insert a single NOP. */
1092 if (mips_optimize
== 0
1093 || (pinfo
& INSN_READ_COND_CODE
))
1096 else if (prev_pinfo
& INSN_READ_LO
)
1098 /* The previous instruction reads the LO register; if the
1099 current instruction writes to the LO register, we must
1100 insert two NOPS. The R4650, VR4100 and VR4300 have
1103 && (mips_optimize
== 0
1104 || (pinfo
& INSN_WRITE_LO
)))
1107 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1109 /* The previous instruction reads the HI register; if the
1110 current instruction writes to the HI register, we must
1111 insert a NOP. The R4650, VR4100 and VR4300 have
1114 && (mips_optimize
== 0
1115 || (pinfo
& INSN_WRITE_HI
)))
1119 /* There are two cases which require two intervening
1120 instructions: 1) setting the condition codes using a move to
1121 coprocessor instruction which requires a general coprocessor
1122 delay and then reading the condition codes 2) reading the HI
1123 or LO register and then writing to it (except on the R4650,
1124 VR4100, and VR4300 which have interlocks). If we are not
1125 already emitting a NOP instruction, we must check for these
1126 cases compared to the instruction previous to the previous
1130 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1131 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1132 && (pinfo
& INSN_READ_COND_CODE
)
1133 && ! cop_interlocks
)
1134 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1135 && (pinfo
& INSN_WRITE_LO
)
1137 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1138 && (pinfo
& INSN_WRITE_HI
)
1142 /* If we are being given a nop instruction, don't bother with
1143 one of the nops we would otherwise output. This will only
1144 happen when a nop instruction is used with mips_optimize set
1146 if (nops
> 0 && ip
->insn_opcode
== 0)
1149 /* Now emit the right number of NOP instructions. */
1153 unsigned long old_frag_offset
;
1156 old_frag
= frag_now
;
1157 old_frag_offset
= frag_now_fix ();
1159 for (i
= 0; i
< nops
; i
++)
1164 listing_prev_line ();
1165 /* We may be at the start of a variant frag. In case we
1166 are, make sure there is enough space for the frag
1167 after the frags created by listing_prev_line. The
1168 argument to frag_grow here must be at least as large
1169 as the argument to all other calls to frag_grow in
1170 this file. We don't have to worry about being in the
1171 middle of a variant frag, because the variants insert
1172 all needed nop instructions themselves. */
1176 if (insn_label
!= NULL
)
1178 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1179 insn_label
->sy_frag
= frag_now
;
1180 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1183 #ifndef NO_ECOFF_DEBUGGING
1184 if (ECOFF_DEBUGGING
)
1185 ecoff_fix_loc (old_frag
, old_frag_offset
);
1195 if (address_expr
!= NULL
)
1197 if (address_expr
->X_op
== O_constant
)
1202 ip
->insn_opcode
|= address_expr
->X_add_number
;
1205 case BFD_RELOC_LO16
:
1206 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1209 case BFD_RELOC_MIPS_JMP
:
1210 case BFD_RELOC_16_PCREL_S2
:
1219 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1221 /* Don't generate a reloc if we are writing into a variant
1225 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1227 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1231 struct mips_hi_fixup
*hi_fixup
;
1233 assert (reloc_type
== BFD_RELOC_HI16_S
);
1234 hi_fixup
= ((struct mips_hi_fixup
*)
1235 xmalloc (sizeof (struct mips_hi_fixup
)));
1236 hi_fixup
->fixp
= fixp
;
1237 hi_fixup
->seg
= now_seg
;
1238 hi_fixup
->next
= mips_hi_fixup_list
;
1239 mips_hi_fixup_list
= hi_fixup
;
1245 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1247 /* Update the register mask information. */
1248 if (pinfo
& INSN_WRITE_GPR_D
)
1249 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1250 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1251 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1252 if (pinfo
& INSN_READ_GPR_S
)
1253 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1254 if (pinfo
& INSN_WRITE_GPR_31
)
1255 mips_gprmask
|= 1 << 31;
1256 if (pinfo
& INSN_WRITE_FPR_D
)
1257 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1258 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1259 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1260 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1261 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1262 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1263 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1264 if (pinfo
& INSN_COP
)
1266 /* We don't keep enough information to sort these cases out. */
1268 /* Never set the bit for $0, which is always zero. */
1269 mips_gprmask
&=~ 1 << 0;
1271 if (place
== NULL
&& ! mips_noreorder
)
1273 /* Filling the branch delay slot is more complex. We try to
1274 switch the branch with the previous instruction, which we can
1275 do if the previous instruction does not set up a condition
1276 that the branch tests and if the branch is not itself the
1277 target of any branch. */
1278 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1279 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1281 if (mips_optimize
< 2
1282 /* If we have seen .set volatile or .set nomove, don't
1285 /* If we had to emit any NOP instructions, then we
1286 already know we can not swap. */
1288 /* If we don't even know the previous insn, we can not
1290 || ! prev_insn_valid
1291 /* If the previous insn is already in a branch delay
1292 slot, then we can not swap. */
1293 || prev_insn_is_delay_slot
1294 /* If the previous previous insn was in a .set
1295 noreorder, we can't swap. Actually, the MIPS
1296 assembler will swap in this situation. However, gcc
1297 configured -with-gnu-as will generate code like
1303 in which we can not swap the bne and INSN. If gcc is
1304 not configured -with-gnu-as, it does not output the
1305 .set pseudo-ops. We don't have to check
1306 prev_insn_unreordered, because prev_insn_valid will
1307 be 0 in that case. We don't want to use
1308 prev_prev_insn_valid, because we do want to be able
1309 to swap at the start of a function. */
1310 || prev_prev_insn_unreordered
1311 /* If the branch is itself the target of a branch, we
1312 can not swap. We cheat on this; all we check for is
1313 whether there is a label on this instruction. If
1314 there are any branches to anything other than a
1315 label, users must use .set noreorder. */
1316 || insn_label
!= NULL
1317 /* If the previous instruction is in a variant frag, we
1318 can not do the swap. */
1319 || prev_insn_frag
->fr_type
== rs_machine_dependent
1320 /* If the branch reads the condition codes, we don't
1321 even try to swap, because in the sequence
1326 we can not swap, and I don't feel like handling that
1329 && (pinfo
& INSN_READ_COND_CODE
))
1330 /* We can not swap with an instruction that requires a
1331 delay slot, becase the target of the branch might
1332 interfere with that instruction. */
1335 & (INSN_LOAD_COPROC_DELAY
1336 | INSN_COPROC_MOVE_DELAY
1337 | INSN_WRITE_COND_CODE
)))
1344 & (INSN_LOAD_MEMORY_DELAY
1345 | INSN_COPROC_MEMORY_DELAY
)))
1346 /* We can not swap with a branch instruction. */
1348 & (INSN_UNCOND_BRANCH_DELAY
1349 | INSN_COND_BRANCH_DELAY
1350 | INSN_COND_BRANCH_LIKELY
))
1351 /* We do not swap with a trap instruction, since it
1352 complicates trap handlers to have the trap
1353 instruction be in a delay slot. */
1354 || (prev_pinfo
& INSN_TRAP
)
1355 /* If the branch reads a register that the previous
1356 instruction sets, we can not swap. */
1357 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1358 && insn_uses_reg (ip
,
1359 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1362 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1363 && insn_uses_reg (ip
,
1364 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1367 /* If the branch writes a register that the previous
1368 instruction sets, we can not swap (we know that
1369 branches write only to RD or to $31). */
1370 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1371 && (((pinfo
& INSN_WRITE_GPR_D
)
1372 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1373 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1374 || ((pinfo
& INSN_WRITE_GPR_31
)
1375 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1378 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1379 && (((pinfo
& INSN_WRITE_GPR_D
)
1380 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1381 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1382 || ((pinfo
& INSN_WRITE_GPR_31
)
1383 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1386 /* If the branch writes a register that the previous
1387 instruction reads, we can not swap (we know that
1388 branches only write to RD or to $31). */
1389 || ((pinfo
& INSN_WRITE_GPR_D
)
1390 && insn_uses_reg (&prev_insn
,
1391 ((ip
->insn_opcode
>> OP_SH_RD
)
1394 || ((pinfo
& INSN_WRITE_GPR_31
)
1395 && insn_uses_reg (&prev_insn
, 31, 0))
1396 /* If we are generating embedded PIC code, the branch
1397 might be expanded into a sequence which uses $at, so
1398 we can't swap with an instruction which reads it. */
1399 || (mips_pic
== EMBEDDED_PIC
1400 && insn_uses_reg (&prev_insn
, AT
, 0))
1401 /* If the previous previous instruction has a load
1402 delay, and sets a register that the branch reads, we
1405 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1407 && (prev_prev_insn
.insn_mo
->pinfo
1408 & INSN_LOAD_MEMORY_DELAY
)))
1409 && insn_uses_reg (ip
,
1410 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1414 /* We could do even better for unconditional branches to
1415 portions of this object file; we could pick up the
1416 instruction at the destination, put it in the delay
1417 slot, and bump the destination address. */
1419 /* Update the previous insn information. */
1420 prev_prev_insn
= *ip
;
1421 prev_insn
.insn_mo
= &dummy_opcode
;
1428 /* It looks like we can actually do the swap. */
1429 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1430 memcpy (temp
, prev_f
, 4);
1431 memcpy (prev_f
, f
, 4);
1432 memcpy (f
, temp
, 4);
1435 prev_insn_fixp
->fx_frag
= frag_now
;
1436 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1440 fixp
->fx_frag
= prev_insn_frag
;
1441 fixp
->fx_where
= prev_insn_where
;
1443 /* Update the previous insn information; leave prev_insn
1445 prev_prev_insn
= *ip
;
1447 prev_insn_is_delay_slot
= 1;
1449 /* If that was an unconditional branch, forget the previous
1450 insn information. */
1451 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1453 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1454 prev_insn
.insn_mo
= &dummy_opcode
;
1457 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1459 /* We don't yet optimize a branch likely. What we should do
1460 is look at the target, copy the instruction found there
1461 into the delay slot, and increment the branch to jump to
1462 the next instruction. */
1464 /* Update the previous insn information. */
1465 prev_prev_insn
= *ip
;
1466 prev_insn
.insn_mo
= &dummy_opcode
;
1470 /* Update the previous insn information. */
1472 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1474 prev_prev_insn
= prev_insn
;
1477 /* Any time we see a branch, we always fill the delay slot
1478 immediately; since this insn is not a branch, we know it
1479 is not in a delay slot. */
1480 prev_insn_is_delay_slot
= 0;
1483 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1484 prev_insn_unreordered
= 0;
1485 prev_insn_frag
= frag_now
;
1486 prev_insn_where
= f
- frag_now
->fr_literal
;
1487 prev_insn_fixp
= fixp
;
1488 prev_insn_valid
= 1;
1491 /* We just output an insn, so the next one doesn't have a label. */
1495 /* This function forgets that there was any previous instruction or
1499 mips_no_prev_insn ()
1501 prev_insn
.insn_mo
= &dummy_opcode
;
1502 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1503 prev_insn_valid
= 0;
1504 prev_insn_is_delay_slot
= 0;
1505 prev_insn_unreordered
= 0;
1506 prev_prev_insn_unreordered
= 0;
1510 /* This function must be called whenever we turn on noreorder or emit
1511 something other than instructions. It inserts any NOPS which might
1512 be needed by the previous instruction, and clears the information
1513 kept for the previous instructions. */
1518 if (! mips_noreorder
)
1524 && (! cop_interlocks
1525 && (prev_insn
.insn_mo
->pinfo
1526 & (INSN_LOAD_COPROC_DELAY
1527 | INSN_COPROC_MOVE_DELAY
1528 | INSN_WRITE_COND_CODE
))))
1530 && (prev_insn
.insn_mo
->pinfo
1534 && (prev_insn
.insn_mo
->pinfo
1535 & (INSN_LOAD_MEMORY_DELAY
1536 | INSN_COPROC_MEMORY_DELAY
))))
1540 && (! cop_interlocks
1541 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1543 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1544 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1547 else if ((mips_isa
< 4
1548 && (! cop_interlocks
1549 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1551 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1552 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1557 if (insn_label
!= NULL
)
1559 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1560 insn_label
->sy_frag
= frag_now
;
1561 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1566 mips_no_prev_insn ();
1569 /* Build an instruction created by a macro expansion. This is passed
1570 a pointer to the count of instructions created so far, an
1571 expression, the name of the instruction to build, an operand format
1572 string, and corresponding arguments. */
1576 macro_build (char *place
,
1584 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1593 struct mips_cl_insn insn
;
1594 bfd_reloc_code_real_type r
;
1598 va_start (args
, fmt
);
1604 * If the macro is about to expand into a second instruction,
1605 * print a warning if needed. We need to pass ip as a parameter
1606 * to generate a better warning message here...
1608 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1609 as_warn ("Macro instruction expanded into multiple instructions");
1612 *counter
+= 1; /* bump instruction counter */
1614 r
= BFD_RELOC_UNUSED
;
1615 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1616 assert (insn
.insn_mo
);
1617 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1619 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1620 || insn
.insn_mo
->pinfo
== INSN_MACRO
1621 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1623 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1625 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1627 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1629 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1631 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1635 assert (insn
.insn_mo
->name
);
1636 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1638 insn
.insn_opcode
= insn
.insn_mo
->match
;
1654 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1660 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1665 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1670 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1677 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1681 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1685 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1692 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1698 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1699 assert (r
== BFD_RELOC_MIPS_GPREL
1700 || r
== BFD_RELOC_MIPS_LITERAL
1701 || r
== BFD_RELOC_LO16
1702 || r
== BFD_RELOC_MIPS_GOT16
1703 || r
== BFD_RELOC_MIPS_CALL16
1704 || r
== BFD_RELOC_MIPS_GOT_LO16
1705 || r
== BFD_RELOC_MIPS_CALL_LO16
1706 || (ep
->X_op
== O_subtract
1707 && now_seg
== text_section
1708 && r
== BFD_RELOC_PCREL_LO16
));
1712 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1714 && (ep
->X_op
== O_constant
1715 || (ep
->X_op
== O_symbol
1716 && (r
== BFD_RELOC_HI16_S
1717 || r
== BFD_RELOC_HI16
1718 || r
== BFD_RELOC_MIPS_GOT_HI16
1719 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1720 || (ep
->X_op
== O_subtract
1721 && now_seg
== text_section
1722 && r
== BFD_RELOC_PCREL_HI16_S
)));
1723 if (ep
->X_op
== O_constant
)
1725 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1727 r
= BFD_RELOC_UNUSED
;
1732 assert (ep
!= NULL
);
1734 * This allows macro() to pass an immediate expression for
1735 * creating short branches without creating a symbol.
1736 * Note that the expression still might come from the assembly
1737 * input, in which case the value is not checked for range nor
1738 * is a relocation entry generated (yuck).
1740 if (ep
->X_op
== O_constant
)
1742 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1746 r
= BFD_RELOC_16_PCREL_S2
;
1750 assert (ep
!= NULL
);
1751 r
= BFD_RELOC_MIPS_JMP
;
1760 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1762 append_insn (place
, &insn
, ep
, r
, false);
1766 * Generate a "lui" instruction.
1769 macro_build_lui (place
, counter
, ep
, regnum
)
1775 expressionS high_expr
;
1776 struct mips_cl_insn insn
;
1777 bfd_reloc_code_real_type r
;
1778 CONST
char *name
= "lui";
1779 CONST
char *fmt
= "t,u";
1785 high_expr
.X_op
= O_constant
;
1786 high_expr
.X_add_number
= ep
->X_add_number
;
1789 if (high_expr
.X_op
== O_constant
)
1791 /* we can compute the instruction now without a relocation entry */
1792 if (high_expr
.X_add_number
& 0x8000)
1793 high_expr
.X_add_number
+= 0x10000;
1794 high_expr
.X_add_number
=
1795 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1796 r
= BFD_RELOC_UNUSED
;
1800 assert (ep
->X_op
== O_symbol
);
1801 /* _gp_disp is a special case, used from s_cpload. */
1802 assert (mips_pic
== NO_PIC
1803 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1804 r
= BFD_RELOC_HI16_S
;
1808 * If the macro is about to expand into a second instruction,
1809 * print a warning if needed. We need to pass ip as a parameter
1810 * to generate a better warning message here...
1812 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1813 as_warn ("Macro instruction expanded into multiple instructions");
1816 *counter
+= 1; /* bump instruction counter */
1818 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1819 assert (insn
.insn_mo
);
1820 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1821 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1823 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1824 if (r
== BFD_RELOC_UNUSED
)
1826 insn
.insn_opcode
|= high_expr
.X_add_number
;
1827 append_insn (place
, &insn
, NULL
, r
, false);
1830 append_insn (place
, &insn
, &high_expr
, r
, false);
1834 * Generates code to set the $at register to true (one)
1835 * if reg is less than the immediate expression.
1838 set_at (counter
, reg
, unsignedp
)
1843 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1844 macro_build ((char *) NULL
, counter
, &imm_expr
,
1845 unsignedp
? "sltiu" : "slti",
1846 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1849 load_register (counter
, AT
, &imm_expr
, 0);
1850 macro_build ((char *) NULL
, counter
, NULL
,
1851 unsignedp
? "sltu" : "slt",
1852 "d,v,t", AT
, reg
, AT
);
1856 /* Warn if an expression is not a constant. */
1859 check_absolute_expr (ip
, ex
)
1860 struct mips_cl_insn
*ip
;
1863 if (ex
->X_op
!= O_constant
)
1864 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1868 * This routine generates the least number of instructions neccessary to load
1869 * an absolute expression value into a register.
1872 load_register (counter
, reg
, ep
, dbl
)
1879 expressionS hi32
, lo32
, tmp
;
1881 if (ep
->X_op
!= O_big
)
1883 assert (ep
->X_op
== O_constant
);
1884 if (ep
->X_add_number
< 0x8000
1885 && (ep
->X_add_number
>= 0
1886 || (ep
->X_add_number
>= -0x8000
1889 || sizeof (ep
->X_add_number
) > 4))))
1891 /* We can handle 16 bit signed values with an addiu to
1892 $zero. No need to ever use daddiu here, since $zero and
1893 the result are always correct in 32 bit mode. */
1894 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1895 (int) BFD_RELOC_LO16
);
1898 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1900 /* We can handle 16 bit unsigned values with an ori to
1902 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1903 (int) BFD_RELOC_LO16
);
1906 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1907 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1908 == ~ (offsetT
) 0x7fffffff))
1911 || sizeof (ep
->X_add_number
) > 4
1912 || (ep
->X_add_number
& 0x80000000) == 0))
1914 && (ep
->X_add_number
&~ 0xffffffff) == 0))
1916 /* 32 bit values require an lui. */
1917 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1918 (int) BFD_RELOC_HI16
);
1919 if ((ep
->X_add_number
& 0xffff) != 0)
1920 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1921 (int) BFD_RELOC_LO16
);
1926 /* 32 bit value with high bit set being loaded into a 64 bit
1927 register. We can't use lui, because that would
1928 incorrectly set the 32 high bits. */
1929 generic_bignum
[3] = 0;
1930 generic_bignum
[2] = 0;
1931 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1932 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1934 tmp
.X_add_number
= 4;
1939 /* The value is larger than 32 bits. */
1943 as_bad ("Number larger than 32 bits");
1944 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1945 (int) BFD_RELOC_LO16
);
1949 if (ep
->X_op
!= O_big
)
1953 hi32
.X_add_number
>>= shift
;
1954 hi32
.X_add_number
&= 0xffffffff;
1955 if ((hi32
.X_add_number
& 0x80000000) != 0)
1956 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1958 lo32
.X_add_number
&= 0xffffffff;
1962 assert (ep
->X_add_number
> 2);
1963 if (ep
->X_add_number
== 3)
1964 generic_bignum
[3] = 0;
1965 else if (ep
->X_add_number
> 4)
1966 as_bad ("Number larger than 64 bits");
1967 lo32
.X_op
= O_constant
;
1968 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1969 hi32
.X_op
= O_constant
;
1970 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1973 if (hi32
.X_add_number
== 0)
1977 if (hi32
.X_add_number
== 0xffffffff)
1979 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
1981 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
1982 (int) BFD_RELOC_LO16
);
1985 if (lo32
.X_add_number
& 0x80000000)
1987 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1988 (int) BFD_RELOC_HI16
);
1989 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1990 (int) BFD_RELOC_LO16
);
1994 load_register (counter
, reg
, &hi32
, 0);
1997 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2001 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2010 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2012 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2013 (int) BFD_RELOC_HI16
);
2014 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2021 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2026 mid16
.X_add_number
>>= 16;
2027 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2028 freg
, (int) BFD_RELOC_LO16
);
2029 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2033 if ((lo32
.X_add_number
& 0xffff) != 0)
2034 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2035 (int) BFD_RELOC_LO16
);
2038 /* Load an address into a register. */
2041 load_address (counter
, reg
, ep
)
2048 if (ep
->X_op
!= O_constant
2049 && ep
->X_op
!= O_symbol
)
2051 as_bad ("expression too complex");
2052 ep
->X_op
= O_constant
;
2055 if (ep
->X_op
== O_constant
)
2057 load_register (counter
, reg
, ep
, 0);
2061 if (mips_pic
== NO_PIC
)
2063 /* If this is a reference to a GP relative symbol, we want
2064 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2066 lui $reg,<sym> (BFD_RELOC_HI16_S)
2067 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2068 If we have an addend, we always use the latter form. */
2069 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2070 || nopic_need_relax (ep
->X_add_symbol
))
2075 macro_build ((char *) NULL
, counter
, ep
,
2076 mips_isa
< 3 ? "addiu" : "daddiu",
2077 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2078 p
= frag_var (rs_machine_dependent
, 8, 0,
2079 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2080 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2082 macro_build_lui (p
, counter
, ep
, reg
);
2085 macro_build (p
, counter
, ep
,
2086 mips_isa
< 3 ? "addiu" : "daddiu",
2087 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2089 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2093 /* If this is a reference to an external symbol, we want
2094 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2096 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2098 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2099 If there is a constant, it must be added in after. */
2100 ex
.X_add_number
= ep
->X_add_number
;
2101 ep
->X_add_number
= 0;
2103 macro_build ((char *) NULL
, counter
, ep
,
2104 mips_isa
< 3 ? "lw" : "ld",
2105 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2106 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2107 p
= frag_var (rs_machine_dependent
, 4, 0,
2108 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2109 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2110 macro_build (p
, counter
, ep
,
2111 mips_isa
< 3 ? "addiu" : "daddiu",
2112 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2113 if (ex
.X_add_number
!= 0)
2115 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2116 as_bad ("PIC code offset overflow (max 16 signed bits)");
2117 ex
.X_op
= O_constant
;
2118 macro_build ((char *) NULL
, counter
, &ex
,
2119 mips_isa
< 3 ? "addiu" : "daddiu",
2120 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2123 else if (mips_pic
== SVR4_PIC
)
2128 /* This is the large GOT case. If this is a reference to an
2129 external symbol, we want
2130 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2132 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2133 Otherwise, for a reference to a local symbol, we want
2134 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2136 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2137 If there is a constant, it must be added in after. */
2138 ex
.X_add_number
= ep
->X_add_number
;
2139 ep
->X_add_number
= 0;
2140 if (reg_needs_delay (GP
))
2145 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2146 (int) BFD_RELOC_MIPS_GOT_HI16
);
2147 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2148 mips_isa
< 3 ? "addu" : "daddu",
2149 "d,v,t", reg
, reg
, GP
);
2150 macro_build ((char *) NULL
, counter
, ep
,
2151 mips_isa
< 3 ? "lw" : "ld",
2152 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2153 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2154 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2155 mips_warn_about_macros
),
2156 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2159 /* We need a nop before loading from $gp. This special
2160 check is required because the lui which starts the main
2161 instruction stream does not refer to $gp, and so will not
2162 insert the nop which may be required. */
2163 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2166 macro_build (p
, counter
, ep
,
2167 mips_isa
< 3 ? "lw" : "ld",
2168 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2170 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2172 macro_build (p
, counter
, ep
,
2173 mips_isa
< 3 ? "addiu" : "daddiu",
2174 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2175 if (ex
.X_add_number
!= 0)
2177 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2178 as_bad ("PIC code offset overflow (max 16 signed bits)");
2179 ex
.X_op
= O_constant
;
2180 macro_build ((char *) NULL
, counter
, &ex
,
2181 mips_isa
< 3 ? "addiu" : "daddiu",
2182 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2185 else if (mips_pic
== EMBEDDED_PIC
)
2188 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2190 macro_build ((char *) NULL
, counter
, ep
,
2191 mips_isa
< 3 ? "addiu" : "daddiu",
2192 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2200 * This routine implements the seemingly endless macro or synthesized
2201 * instructions and addressing modes in the mips assembly language. Many
2202 * of these macros are simple and are similar to each other. These could
2203 * probably be handled by some kind of table or grammer aproach instead of
2204 * this verbose method. Others are not simple macros but are more like
2205 * optimizing code generation.
2206 * One interesting optimization is when several store macros appear
2207 * consecutivly that would load AT with the upper half of the same address.
2208 * The ensuing load upper instructions are ommited. This implies some kind
2209 * of global optimization. We currently only optimize within a single macro.
2210 * For many of the load and store macros if the address is specified as a
2211 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2212 * first load register 'at' with zero and use it as the base register. The
2213 * mips assembler simply uses register $zero. Just one tiny optimization
2218 struct mips_cl_insn
*ip
;
2220 register int treg
, sreg
, dreg
, breg
;
2235 bfd_reloc_code_real_type r
;
2237 int hold_mips_optimize
;
2239 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2240 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2241 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2242 mask
= ip
->insn_mo
->mask
;
2244 expr1
.X_op
= O_constant
;
2245 expr1
.X_op_symbol
= NULL
;
2246 expr1
.X_add_symbol
= NULL
;
2247 expr1
.X_add_number
= 1;
2259 mips_emit_delays ();
2261 mips_any_noreorder
= 1;
2263 expr1
.X_add_number
= 8;
2264 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2266 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2268 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2269 macro_build ((char *) NULL
, &icnt
, NULL
,
2270 dbl
? "dsub" : "sub",
2271 "d,v,t", dreg
, 0, sreg
);
2294 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2296 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2297 (int) BFD_RELOC_LO16
);
2300 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2301 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2320 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2322 if (mask
!= M_NOR_I
)
2323 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2324 sreg
, (int) BFD_RELOC_LO16
);
2327 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2328 treg
, sreg
, (int) BFD_RELOC_LO16
);
2329 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2335 load_register (&icnt
, AT
, &imm_expr
, 0);
2336 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2353 if (imm_expr
.X_add_number
== 0)
2355 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2359 load_register (&icnt
, AT
, &imm_expr
, 0);
2360 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2368 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2369 likely
? "bgezl" : "bgez",
2375 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2376 likely
? "blezl" : "blez",
2380 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2381 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2382 likely
? "beql" : "beq",
2389 /* check for > max integer */
2390 maxnum
= 0x7fffffff;
2398 if (imm_expr
.X_add_number
>= maxnum
2399 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2402 /* result is always false */
2405 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2406 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2410 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2411 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2416 imm_expr
.X_add_number
++;
2420 if (mask
== M_BGEL_I
)
2422 if (imm_expr
.X_add_number
== 0)
2424 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2425 likely
? "bgezl" : "bgez",
2429 if (imm_expr
.X_add_number
== 1)
2431 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2432 likely
? "bgtzl" : "bgtz",
2436 maxnum
= 0x7fffffff;
2444 maxnum
= - maxnum
- 1;
2445 if (imm_expr
.X_add_number
<= maxnum
2446 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2449 /* result is always true */
2450 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2451 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2454 set_at (&icnt
, sreg
, 0);
2455 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2456 likely
? "beql" : "beq",
2467 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2468 likely
? "beql" : "beq",
2472 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2474 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2475 likely
? "beql" : "beq",
2482 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2484 imm_expr
.X_add_number
++;
2488 if (mask
== M_BGEUL_I
)
2490 if (imm_expr
.X_add_number
== 0)
2492 if (imm_expr
.X_add_number
== 1)
2494 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2495 likely
? "bnel" : "bne",
2499 set_at (&icnt
, sreg
, 1);
2500 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2501 likely
? "beql" : "beq",
2510 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2511 likely
? "bgtzl" : "bgtz",
2517 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2518 likely
? "bltzl" : "bltz",
2522 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2523 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2524 likely
? "bnel" : "bne",
2533 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2534 likely
? "bnel" : "bne",
2540 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2542 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2543 likely
? "bnel" : "bne",
2552 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2553 likely
? "blezl" : "blez",
2559 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2560 likely
? "bgezl" : "bgez",
2564 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2565 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2566 likely
? "beql" : "beq",
2573 maxnum
= 0x7fffffff;
2581 if (imm_expr
.X_add_number
>= maxnum
2582 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2584 imm_expr
.X_add_number
++;
2588 if (mask
== M_BLTL_I
)
2590 if (imm_expr
.X_add_number
== 0)
2592 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2593 likely
? "bltzl" : "bltz",
2597 if (imm_expr
.X_add_number
== 1)
2599 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2600 likely
? "blezl" : "blez",
2604 set_at (&icnt
, sreg
, 0);
2605 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2606 likely
? "bnel" : "bne",
2615 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2616 likely
? "beql" : "beq",
2622 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2624 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2625 likely
? "beql" : "beq",
2632 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2634 imm_expr
.X_add_number
++;
2638 if (mask
== M_BLTUL_I
)
2640 if (imm_expr
.X_add_number
== 0)
2642 if (imm_expr
.X_add_number
== 1)
2644 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2645 likely
? "beql" : "beq",
2649 set_at (&icnt
, sreg
, 1);
2650 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2651 likely
? "bnel" : "bne",
2660 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2661 likely
? "bltzl" : "bltz",
2667 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2668 likely
? "bgtzl" : "bgtz",
2672 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2673 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2674 likely
? "bnel" : "bne",
2685 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2686 likely
? "bnel" : "bne",
2690 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2692 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2693 likely
? "bnel" : "bne",
2709 as_warn ("Divide by zero.");
2711 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2713 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2717 mips_emit_delays ();
2719 mips_any_noreorder
= 1;
2720 macro_build ((char *) NULL
, &icnt
, NULL
,
2721 dbl
? "ddiv" : "div",
2722 "z,s,t", sreg
, treg
);
2724 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2727 expr1
.X_add_number
= 8;
2728 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2729 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2730 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2732 expr1
.X_add_number
= -1;
2733 macro_build ((char *) NULL
, &icnt
, &expr1
,
2734 dbl
? "daddiu" : "addiu",
2735 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2736 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2737 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2740 expr1
.X_add_number
= 1;
2741 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2742 (int) BFD_RELOC_LO16
);
2743 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2748 expr1
.X_add_number
= 0x80000000;
2749 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2750 (int) BFD_RELOC_HI16
);
2753 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2756 expr1
.X_add_number
= 8;
2757 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2758 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2759 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2762 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2801 if (imm_expr
.X_add_number
== 0)
2803 as_warn ("Divide by zero.");
2805 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2807 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2810 if (imm_expr
.X_add_number
== 1)
2812 if (strcmp (s2
, "mflo") == 0)
2813 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2816 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2819 if (imm_expr
.X_add_number
== -1
2820 && s
[strlen (s
) - 1] != 'u')
2822 if (strcmp (s2
, "mflo") == 0)
2825 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2828 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2832 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2836 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2837 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2838 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2857 mips_emit_delays ();
2859 mips_any_noreorder
= 1;
2860 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2862 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2865 expr1
.X_add_number
= 8;
2866 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2867 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2868 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2871 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2877 /* Load the address of a symbol into a register. If breg is not
2878 zero, we then add a base register to it. */
2880 /* When generating embedded PIC code, we permit expressions of
2883 where bar is an address in the .text section. These are used
2884 when getting the addresses of functions. We don't permit
2885 X_add_number to be non-zero, because if the symbol is
2886 external the relaxing code needs to know that any addend is
2887 purely the offset to X_op_symbol. */
2888 if (mips_pic
== EMBEDDED_PIC
2889 && offset_expr
.X_op
== O_subtract
2890 && now_seg
== text_section
2891 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2892 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2893 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2894 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2895 ->sy_value
.X_add_symbol
)
2898 && offset_expr
.X_add_number
== 0)
2900 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2901 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2902 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2903 mips_isa
< 3 ? "addiu" : "daddiu",
2904 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2908 if (offset_expr
.X_op
!= O_symbol
2909 && offset_expr
.X_op
!= O_constant
)
2911 as_bad ("expression too complex");
2912 offset_expr
.X_op
= O_constant
;
2926 if (offset_expr
.X_op
== O_constant
)
2927 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2928 else if (mips_pic
== NO_PIC
)
2930 /* If this is a reference to an GP relative symbol, we want
2931 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2933 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2934 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2935 If we have a constant, we need two instructions anyhow,
2936 so we may as well always use the latter form. */
2937 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
2938 || nopic_need_relax (offset_expr
.X_add_symbol
))
2943 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2944 mips_isa
< 3 ? "addiu" : "daddiu",
2945 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2946 p
= frag_var (rs_machine_dependent
, 8, 0,
2947 RELAX_ENCODE (4, 8, 0, 4, 0,
2948 mips_warn_about_macros
),
2949 offset_expr
.X_add_symbol
, (long) 0,
2952 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2955 macro_build (p
, &icnt
, &offset_expr
,
2956 mips_isa
< 3 ? "addiu" : "daddiu",
2957 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2959 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2961 /* If this is a reference to an external symbol, and there
2962 is no constant, we want
2963 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2964 For a local symbol, we want
2965 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2967 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2969 If we have a small constant, and this is a reference to
2970 an external symbol, we want
2971 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2973 addiu $tempreg,$tempreg,<constant>
2974 For a local symbol, we want the same instruction
2975 sequence, but we output a BFD_RELOC_LO16 reloc on the
2978 If we have a large constant, and this is a reference to
2979 an external symbol, we want
2980 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2981 lui $at,<hiconstant>
2982 addiu $at,$at,<loconstant>
2983 addu $tempreg,$tempreg,$at
2984 For a local symbol, we want the same instruction
2985 sequence, but we output a BFD_RELOC_LO16 reloc on the
2986 addiu instruction. */
2987 expr1
.X_add_number
= offset_expr
.X_add_number
;
2988 offset_expr
.X_add_number
= 0;
2990 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2992 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2993 if (expr1
.X_add_number
== 0)
3001 /* We're going to put in an addu instruction using
3002 tempreg, so we may as well insert the nop right
3004 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3008 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3009 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3011 ? mips_warn_about_macros
3013 offset_expr
.X_add_symbol
, (long) 0,
3017 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3020 macro_build (p
, &icnt
, &expr1
,
3021 mips_isa
< 3 ? "addiu" : "daddiu",
3022 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3023 /* FIXME: If breg == 0, and the next instruction uses
3024 $tempreg, then if this variant case is used an extra
3025 nop will be generated. */
3027 else if (expr1
.X_add_number
>= -0x8000
3028 && expr1
.X_add_number
< 0x8000)
3030 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3032 macro_build ((char *) NULL
, &icnt
, &expr1
,
3033 mips_isa
< 3 ? "addiu" : "daddiu",
3034 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3035 (void) frag_var (rs_machine_dependent
, 0, 0,
3036 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3037 offset_expr
.X_add_symbol
, (long) 0,
3044 /* If we are going to add in a base register, and the
3045 target register and the base register are the same,
3046 then we are using AT as a temporary register. Since
3047 we want to load the constant into AT, we add our
3048 current AT (from the global offset table) and the
3049 register into the register now, and pretend we were
3050 not using a base register. */
3055 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3057 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3058 mips_isa
< 3 ? "addu" : "daddu",
3059 "d,v,t", treg
, AT
, breg
);
3065 /* Set mips_optimize around the lui instruction to avoid
3066 inserting an unnecessary nop after the lw. */
3067 hold_mips_optimize
= mips_optimize
;
3069 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3070 mips_optimize
= hold_mips_optimize
;
3072 macro_build ((char *) NULL
, &icnt
, &expr1
,
3073 mips_isa
< 3 ? "addiu" : "daddiu",
3074 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3075 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3076 mips_isa
< 3 ? "addu" : "daddu",
3077 "d,v,t", tempreg
, tempreg
, AT
);
3078 (void) frag_var (rs_machine_dependent
, 0, 0,
3079 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3080 offset_expr
.X_add_symbol
, (long) 0,
3085 else if (mips_pic
== SVR4_PIC
)
3089 /* This is the large GOT case. If this is a reference to an
3090 external symbol, and there is no constant, we want
3091 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3092 addu $tempreg,$tempreg,$gp
3093 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3094 For a local symbol, we want
3095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3097 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3099 If we have a small constant, and this is a reference to
3100 an external symbol, we want
3101 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3102 addu $tempreg,$tempreg,$gp
3103 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3105 addiu $tempreg,$tempreg,<constant>
3106 For a local symbol, we want
3107 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3109 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3111 If we have a large constant, and this is a reference to
3112 an external symbol, we want
3113 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3114 addu $tempreg,$tempreg,$gp
3115 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3116 lui $at,<hiconstant>
3117 addiu $at,$at,<loconstant>
3118 addu $tempreg,$tempreg,$at
3119 For a local symbol, we want
3120 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3121 lui $at,<hiconstant>
3122 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3123 addu $tempreg,$tempreg,$at
3125 expr1
.X_add_number
= offset_expr
.X_add_number
;
3126 offset_expr
.X_add_number
= 0;
3128 if (reg_needs_delay (GP
))
3132 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3133 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3134 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3135 mips_isa
< 3 ? "addu" : "daddu",
3136 "d,v,t", tempreg
, tempreg
, GP
);
3137 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3139 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3141 if (expr1
.X_add_number
== 0)
3149 /* We're going to put in an addu instruction using
3150 tempreg, so we may as well insert the nop right
3152 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3157 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3158 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3161 ? mips_warn_about_macros
3163 offset_expr
.X_add_symbol
, (long) 0,
3166 else if (expr1
.X_add_number
>= -0x8000
3167 && expr1
.X_add_number
< 0x8000)
3169 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3171 macro_build ((char *) NULL
, &icnt
, &expr1
,
3172 mips_isa
< 3 ? "addiu" : "daddiu",
3173 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3175 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3176 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3178 ? mips_warn_about_macros
3180 offset_expr
.X_add_symbol
, (long) 0,
3187 /* If we are going to add in a base register, and the
3188 target register and the base register are the same,
3189 then we are using AT as a temporary register. Since
3190 we want to load the constant into AT, we add our
3191 current AT (from the global offset table) and the
3192 register into the register now, and pretend we were
3193 not using a base register. */
3201 assert (tempreg
== AT
);
3202 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3204 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3205 mips_isa
< 3 ? "addu" : "daddu",
3206 "d,v,t", treg
, AT
, breg
);
3211 /* Set mips_optimize around the lui instruction to avoid
3212 inserting an unnecessary nop after the lw. */
3213 hold_mips_optimize
= mips_optimize
;
3215 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3216 mips_optimize
= hold_mips_optimize
;
3218 macro_build ((char *) NULL
, &icnt
, &expr1
,
3219 mips_isa
< 3 ? "addiu" : "daddiu",
3220 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3221 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3222 mips_isa
< 3 ? "addu" : "daddu",
3223 "d,v,t", dreg
, dreg
, AT
);
3225 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3226 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3229 ? mips_warn_about_macros
3231 offset_expr
.X_add_symbol
, (long) 0,
3239 /* This is needed because this instruction uses $gp, but
3240 the first instruction on the main stream does not. */
3241 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3244 macro_build (p
, &icnt
, &offset_expr
,
3246 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3248 if (expr1
.X_add_number
>= -0x8000
3249 && expr1
.X_add_number
< 0x8000)
3251 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3253 macro_build (p
, &icnt
, &expr1
,
3254 mips_isa
< 3 ? "addiu" : "daddiu",
3255 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3256 /* FIXME: If add_number is 0, and there was no base
3257 register, the external symbol case ended with a load,
3258 so if the symbol turns out to not be external, and
3259 the next instruction uses tempreg, an unnecessary nop
3260 will be inserted. */
3266 /* We must add in the base register now, as in the
3267 external symbol case. */
3268 assert (tempreg
== AT
);
3269 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3271 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3272 mips_isa
< 3 ? "addu" : "daddu",
3273 "d,v,t", treg
, AT
, breg
);
3276 /* We set breg to 0 because we have arranged to add
3277 it in in both cases. */
3281 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3283 macro_build (p
, &icnt
, &expr1
,
3284 mips_isa
< 3 ? "addiu" : "daddiu",
3285 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3287 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3288 mips_isa
< 3 ? "addu" : "daddu",
3289 "d,v,t", tempreg
, tempreg
, AT
);
3293 else if (mips_pic
== EMBEDDED_PIC
)
3296 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3298 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3299 mips_isa
< 3 ? "addiu" : "daddiu",
3300 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3307 mips_isa
< 3 ? "addu" : "daddu",
3308 "d,v,t", treg
, tempreg
, breg
);
3316 /* The j instruction may not be used in PIC code, since it
3317 requires an absolute address. We convert it to a b
3319 if (mips_pic
== NO_PIC
)
3320 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3322 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3325 /* The jal instructions must be handled as macros because when
3326 generating PIC code they expand to multi-instruction
3327 sequences. Normally they are simple instructions. */
3332 if (mips_pic
== NO_PIC
3333 || mips_pic
== EMBEDDED_PIC
)
3334 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3336 else if (mips_pic
== SVR4_PIC
)
3338 if (sreg
!= PIC_CALL_REG
)
3339 as_warn ("MIPS PIC call to register other than $25");
3341 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3343 if (mips_cprestore_offset
< 0)
3344 as_warn ("No .cprestore pseudo-op used in PIC code");
3347 expr1
.X_add_number
= mips_cprestore_offset
;
3348 macro_build ((char *) NULL
, &icnt
, &expr1
,
3349 mips_isa
< 3 ? "lw" : "ld",
3350 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3359 if (mips_pic
== NO_PIC
)
3360 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3361 else if (mips_pic
== SVR4_PIC
)
3363 /* If this is a reference to an external symbol, and we are
3364 using a small GOT, we want
3365 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3369 lw $gp,cprestore($sp)
3370 The cprestore value is set using the .cprestore
3371 pseudo-op. If we are using a big GOT, we want
3372 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3374 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3378 lw $gp,cprestore($sp)
3379 If the symbol is not external, we want
3380 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3382 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3385 lw $gp,cprestore($sp) */
3389 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3390 mips_isa
< 3 ? "lw" : "ld",
3391 "t,o(b)", PIC_CALL_REG
,
3392 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3393 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3395 p
= frag_var (rs_machine_dependent
, 4, 0,
3396 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3397 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3403 if (reg_needs_delay (GP
))
3407 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3408 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3409 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3410 mips_isa
< 3 ? "addu" : "daddu",
3411 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3412 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3413 mips_isa
< 3 ? "lw" : "ld",
3414 "t,o(b)", PIC_CALL_REG
,
3415 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3416 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3418 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3419 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3421 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3424 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3427 macro_build (p
, &icnt
, &offset_expr
,
3428 mips_isa
< 3 ? "lw" : "ld",
3429 "t,o(b)", PIC_CALL_REG
,
3430 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3432 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3435 macro_build (p
, &icnt
, &offset_expr
,
3436 mips_isa
< 3 ? "addiu" : "daddiu",
3437 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3438 (int) BFD_RELOC_LO16
);
3439 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3440 "jalr", "s", PIC_CALL_REG
);
3441 if (mips_cprestore_offset
< 0)
3442 as_warn ("No .cprestore pseudo-op used in PIC code");
3446 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3448 expr1
.X_add_number
= mips_cprestore_offset
;
3449 macro_build ((char *) NULL
, &icnt
, &expr1
,
3450 mips_isa
< 3 ? "lw" : "ld",
3451 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3455 else if (mips_pic
== EMBEDDED_PIC
)
3457 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3458 /* The linker may expand the call to a longer sequence which
3459 uses $at, so we must break rather than return. */
3535 if (breg
== treg
|| coproc
|| lr
)
3604 if (mask
== M_LWC1_AB
3605 || mask
== M_SWC1_AB
3606 || mask
== M_LDC1_AB
3607 || mask
== M_SDC1_AB
3616 if (offset_expr
.X_op
!= O_constant
3617 && offset_expr
.X_op
!= O_symbol
)
3619 as_bad ("expression too complex");
3620 offset_expr
.X_op
= O_constant
;
3623 /* A constant expression in PIC code can be handled just as it
3624 is in non PIC code. */
3625 if (mips_pic
== NO_PIC
3626 || offset_expr
.X_op
== O_constant
)
3628 /* If this is a reference to a GP relative symbol, and there
3629 is no base register, we want
3630 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3631 Otherwise, if there is no base register, we want
3632 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3633 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3634 If we have a constant, we need two instructions anyhow,
3635 so we always use the latter form.
3637 If we have a base register, and this is a reference to a
3638 GP relative symbol, we want
3639 addu $tempreg,$breg,$gp
3640 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3642 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3643 addu $tempreg,$tempreg,$breg
3644 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3645 With a constant we always use the latter case. */
3648 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3649 || nopic_need_relax (offset_expr
.X_add_symbol
))
3654 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3655 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3656 p
= frag_var (rs_machine_dependent
, 8, 0,
3657 RELAX_ENCODE (4, 8, 0, 4, 0,
3658 (mips_warn_about_macros
3659 || (used_at
&& mips_noat
))),
3660 offset_expr
.X_add_symbol
, (long) 0,
3664 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3667 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3668 (int) BFD_RELOC_LO16
, tempreg
);
3672 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3673 || nopic_need_relax (offset_expr
.X_add_symbol
))
3678 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3679 mips_isa
< 3 ? "addu" : "daddu",
3680 "d,v,t", tempreg
, breg
, GP
);
3681 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3682 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3683 p
= frag_var (rs_machine_dependent
, 12, 0,
3684 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3685 offset_expr
.X_add_symbol
, (long) 0,
3688 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3691 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3692 mips_isa
< 3 ? "addu" : "daddu",
3693 "d,v,t", tempreg
, tempreg
, breg
);
3696 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3697 (int) BFD_RELOC_LO16
, tempreg
);
3700 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3702 /* If this is a reference to an external symbol, we want
3703 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3705 <op> $treg,0($tempreg)
3707 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3709 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3710 <op> $treg,0($tempreg)
3711 If there is a base register, we add it to $tempreg before
3712 the <op>. If there is a constant, we stick it in the
3713 <op> instruction. We don't handle constants larger than
3714 16 bits, because we have no way to load the upper 16 bits
3715 (actually, we could handle them for the subset of cases
3716 in which we are not using $at). */
3717 assert (offset_expr
.X_op
== O_symbol
);
3718 expr1
.X_add_number
= offset_expr
.X_add_number
;
3719 offset_expr
.X_add_number
= 0;
3720 if (expr1
.X_add_number
< -0x8000
3721 || expr1
.X_add_number
>= 0x8000)
3722 as_bad ("PIC code offset overflow (max 16 signed bits)");
3724 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3725 mips_isa
< 3 ? "lw" : "ld",
3726 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3727 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3728 p
= frag_var (rs_machine_dependent
, 4, 0,
3729 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3730 offset_expr
.X_add_symbol
, (long) 0,
3732 macro_build (p
, &icnt
, &offset_expr
,
3733 mips_isa
< 3 ? "addiu" : "daddiu",
3734 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3736 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3737 mips_isa
< 3 ? "addu" : "daddu",
3738 "d,v,t", tempreg
, tempreg
, breg
);
3739 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3740 (int) BFD_RELOC_LO16
, tempreg
);
3742 else if (mips_pic
== SVR4_PIC
)
3746 /* If this is a reference to an external symbol, we want
3747 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3748 addu $tempreg,$tempreg,$gp
3749 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3750 <op> $treg,0($tempreg)
3752 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3754 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3755 <op> $treg,0($tempreg)
3756 If there is a base register, we add it to $tempreg before
3757 the <op>. If there is a constant, we stick it in the
3758 <op> instruction. We don't handle constants larger than
3759 16 bits, because we have no way to load the upper 16 bits
3760 (actually, we could handle them for the subset of cases
3761 in which we are not using $at). */
3762 assert (offset_expr
.X_op
== O_symbol
);
3763 expr1
.X_add_number
= offset_expr
.X_add_number
;
3764 offset_expr
.X_add_number
= 0;
3765 if (expr1
.X_add_number
< -0x8000
3766 || expr1
.X_add_number
>= 0x8000)
3767 as_bad ("PIC code offset overflow (max 16 signed bits)");
3768 if (reg_needs_delay (GP
))
3773 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3774 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3775 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3776 mips_isa
< 3 ? "addu" : "daddu",
3777 "d,v,t", tempreg
, tempreg
, GP
);
3778 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3779 mips_isa
< 3 ? "lw" : "ld",
3780 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3782 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3783 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3784 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3787 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3790 macro_build (p
, &icnt
, &offset_expr
,
3791 mips_isa
< 3 ? "lw" : "ld",
3792 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3794 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3796 macro_build (p
, &icnt
, &offset_expr
,
3797 mips_isa
< 3 ? "addiu" : "daddiu",
3798 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3800 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3801 mips_isa
< 3 ? "addu" : "daddu",
3802 "d,v,t", tempreg
, tempreg
, breg
);
3803 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3804 (int) BFD_RELOC_LO16
, tempreg
);
3806 else if (mips_pic
== EMBEDDED_PIC
)
3808 /* If there is no base register, we want
3809 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3810 If there is a base register, we want
3811 addu $tempreg,$breg,$gp
3812 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3814 assert (offset_expr
.X_op
== O_symbol
);
3817 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3818 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3824 mips_isa
< 3 ? "addu" : "daddu",
3825 "d,v,t", tempreg
, breg
, GP
);
3826 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3827 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3840 load_register (&icnt
, treg
, &imm_expr
, 0);
3844 load_register (&icnt
, treg
, &imm_expr
, 1);
3848 if (imm_expr
.X_op
== O_constant
)
3850 load_register (&icnt
, AT
, &imm_expr
, 0);
3851 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3852 "mtc1", "t,G", AT
, treg
);
3857 assert (offset_expr
.X_op
== O_symbol
3858 && strcmp (segment_name (S_GET_SEGMENT
3859 (offset_expr
.X_add_symbol
)),
3861 && offset_expr
.X_add_number
== 0);
3862 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3863 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3868 /* We know that sym is in the .rdata section. First we get the
3869 upper 16 bits of the address. */
3870 if (mips_pic
== NO_PIC
)
3872 /* FIXME: This won't work for a 64 bit address. */
3873 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3875 else if (mips_pic
== SVR4_PIC
)
3877 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3878 mips_isa
< 3 ? "lw" : "ld",
3879 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3881 else if (mips_pic
== EMBEDDED_PIC
)
3883 /* For embedded PIC we pick up the entire address off $gp in
3884 a single instruction. */
3885 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3886 mips_isa
< 3 ? "addiu" : "daddiu",
3887 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3888 offset_expr
.X_op
= O_constant
;
3889 offset_expr
.X_add_number
= 0;
3894 /* Now we load the register(s). */
3896 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3897 treg
, (int) BFD_RELOC_LO16
, AT
);
3900 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3901 treg
, (int) BFD_RELOC_LO16
, AT
);
3904 /* FIXME: How in the world do we deal with the possible
3906 offset_expr
.X_add_number
+= 4;
3907 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3908 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3912 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3913 does not become a variant frag. */
3914 frag_wane (frag_now
);
3920 assert (offset_expr
.X_op
== O_symbol
3921 && offset_expr
.X_add_number
== 0);
3922 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3923 if (strcmp (s
, ".lit8") == 0)
3927 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3928 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3932 r
= BFD_RELOC_MIPS_LITERAL
;
3937 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3938 if (mips_pic
== SVR4_PIC
)
3939 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3940 mips_isa
< 3 ? "lw" : "ld",
3941 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3944 /* FIXME: This won't work for a 64 bit address. */
3945 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3950 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3951 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3953 /* To avoid confusion in tc_gen_reloc, we must ensure
3954 that this does not become a variant frag. */
3955 frag_wane (frag_now
);
3966 /* Even on a big endian machine $fn comes before $fn+1. We have
3967 to adjust when loading from memory. */
3970 assert (mips_isa
< 2);
3971 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3972 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3974 /* FIXME: A possible overflow which I don't know how to deal
3976 offset_expr
.X_add_number
+= 4;
3977 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3978 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3981 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3982 does not become a variant frag. */
3983 frag_wane (frag_now
);
3992 * The MIPS assembler seems to check for X_add_number not
3993 * being double aligned and generating:
3996 * addiu at,at,%lo(foo+1)
3999 * But, the resulting address is the same after relocation so why
4000 * generate the extra instruction?
4047 if (offset_expr
.X_op
!= O_symbol
4048 && offset_expr
.X_op
!= O_constant
)
4050 as_bad ("expression too complex");
4051 offset_expr
.X_op
= O_constant
;
4054 /* Even on a big endian machine $fn comes before $fn+1. We have
4055 to adjust when loading from memory. We set coproc if we must
4056 load $fn+1 first. */
4057 if (byte_order
== LITTLE_ENDIAN
)
4060 if (mips_pic
== NO_PIC
4061 || offset_expr
.X_op
== O_constant
)
4063 /* If this is a reference to a GP relative symbol, we want
4064 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4065 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4066 If we have a base register, we use this
4068 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4069 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4070 If this is not a GP relative symbol, we want
4071 lui $at,<sym> (BFD_RELOC_HI16_S)
4072 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4073 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4074 If there is a base register, we add it to $at after the
4075 lui instruction. If there is a constant, we always use
4077 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4078 || nopic_need_relax (offset_expr
.X_add_symbol
))
4097 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4098 mips_isa
< 3 ? "addu" : "daddu",
4099 "d,v,t", AT
, breg
, GP
);
4105 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4106 coproc
? treg
+ 1 : treg
,
4107 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4108 offset_expr
.X_add_number
+= 4;
4110 /* Set mips_optimize to 2 to avoid inserting an
4112 hold_mips_optimize
= mips_optimize
;
4114 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4115 coproc
? treg
: treg
+ 1,
4116 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4117 mips_optimize
= hold_mips_optimize
;
4119 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4120 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4121 used_at
&& mips_noat
),
4122 offset_expr
.X_add_symbol
, (long) 0,
4125 /* We just generated two relocs. When tc_gen_reloc
4126 handles this case, it will skip the first reloc and
4127 handle the second. The second reloc already has an
4128 extra addend of 4, which we added above. We must
4129 subtract it out, and then subtract another 4 to make
4130 the first reloc come out right. The second reloc
4131 will come out right because we are going to add 4 to
4132 offset_expr when we build its instruction below. */
4133 offset_expr
.X_add_number
-= 8;
4134 offset_expr
.X_op
= O_constant
;
4136 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4141 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4142 mips_isa
< 3 ? "addu" : "daddu",
4143 "d,v,t", AT
, breg
, AT
);
4147 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4148 coproc
? treg
+ 1 : treg
,
4149 (int) BFD_RELOC_LO16
, AT
);
4152 /* FIXME: How do we handle overflow here? */
4153 offset_expr
.X_add_number
+= 4;
4154 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4155 coproc
? treg
: treg
+ 1,
4156 (int) BFD_RELOC_LO16
, AT
);
4158 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4162 /* If this is a reference to an external symbol, we want
4163 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4168 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4170 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4171 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4172 If there is a base register we add it to $at before the
4173 lwc1 instructions. If there is a constant we include it
4174 in the lwc1 instructions. */
4176 expr1
.X_add_number
= offset_expr
.X_add_number
;
4177 offset_expr
.X_add_number
= 0;
4178 if (expr1
.X_add_number
< -0x8000
4179 || expr1
.X_add_number
>= 0x8000 - 4)
4180 as_bad ("PIC code offset overflow (max 16 signed bits)");
4185 frag_grow (24 + off
);
4186 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4187 mips_isa
< 3 ? "lw" : "ld",
4188 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4191 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4192 mips_isa
< 3 ? "addu" : "daddu",
4193 "d,v,t", AT
, breg
, AT
);
4194 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4195 coproc
? treg
+ 1 : treg
,
4196 (int) BFD_RELOC_LO16
, AT
);
4197 expr1
.X_add_number
+= 4;
4199 /* Set mips_optimize to 2 to avoid inserting an undesired
4201 hold_mips_optimize
= mips_optimize
;
4203 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4204 coproc
? treg
: treg
+ 1,
4205 (int) BFD_RELOC_LO16
, AT
);
4206 mips_optimize
= hold_mips_optimize
;
4208 (void) frag_var (rs_machine_dependent
, 0, 0,
4209 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4210 offset_expr
.X_add_symbol
, (long) 0,
4213 else if (mips_pic
== SVR4_PIC
)
4217 /* If this is a reference to an external symbol, we want
4218 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4220 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4225 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4227 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4228 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4229 If there is a base register we add it to $at before the
4230 lwc1 instructions. If there is a constant we include it
4231 in the lwc1 instructions. */
4233 expr1
.X_add_number
= offset_expr
.X_add_number
;
4234 offset_expr
.X_add_number
= 0;
4235 if (expr1
.X_add_number
< -0x8000
4236 || expr1
.X_add_number
>= 0x8000 - 4)
4237 as_bad ("PIC code offset overflow (max 16 signed bits)");
4238 if (reg_needs_delay (GP
))
4247 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4248 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4249 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4250 mips_isa
< 3 ? "addu" : "daddu",
4251 "d,v,t", AT
, AT
, GP
);
4252 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4253 mips_isa
< 3 ? "lw" : "ld",
4254 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4255 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4257 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4258 mips_isa
< 3 ? "addu" : "daddu",
4259 "d,v,t", AT
, breg
, AT
);
4260 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4261 coproc
? treg
+ 1 : treg
,
4262 (int) BFD_RELOC_LO16
, AT
);
4263 expr1
.X_add_number
+= 4;
4265 /* Set mips_optimize to 2 to avoid inserting an undesired
4267 hold_mips_optimize
= mips_optimize
;
4269 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4270 coproc
? treg
: treg
+ 1,
4271 (int) BFD_RELOC_LO16
, AT
);
4272 mips_optimize
= hold_mips_optimize
;
4273 expr1
.X_add_number
-= 4;
4275 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4276 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4277 8 + gpdel
+ off
, 1, 0),
4278 offset_expr
.X_add_symbol
, (long) 0,
4282 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4285 macro_build (p
, &icnt
, &offset_expr
,
4286 mips_isa
< 3 ? "lw" : "ld",
4287 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4289 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4293 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4294 mips_isa
< 3 ? "addu" : "daddu",
4295 "d,v,t", AT
, breg
, AT
);
4298 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4299 coproc
? treg
+ 1 : treg
,
4300 (int) BFD_RELOC_LO16
, AT
);
4302 expr1
.X_add_number
+= 4;
4304 /* Set mips_optimize to 2 to avoid inserting an undesired
4306 hold_mips_optimize
= mips_optimize
;
4308 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4309 coproc
? treg
: treg
+ 1,
4310 (int) BFD_RELOC_LO16
, AT
);
4311 mips_optimize
= hold_mips_optimize
;
4313 else if (mips_pic
== EMBEDDED_PIC
)
4315 /* If there is no base register, we use
4316 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4317 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4318 If we have a base register, we use
4320 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4321 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4330 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4331 mips_isa
< 3 ? "addu" : "daddu",
4332 "d,v,t", AT
, breg
, GP
);
4337 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4338 coproc
? treg
+ 1 : treg
,
4339 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4340 offset_expr
.X_add_number
+= 4;
4341 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4342 coproc
? treg
: treg
+ 1,
4343 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4359 assert (mips_isa
< 3);
4360 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4361 (int) BFD_RELOC_LO16
, breg
);
4362 offset_expr
.X_add_number
+= 4;
4363 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4364 (int) BFD_RELOC_LO16
, breg
);
4366 #ifdef LOSING_COMPILER
4372 as_warn ("Macro used $at after \".set noat\"");
4377 struct mips_cl_insn
*ip
;
4379 register int treg
, sreg
, dreg
, breg
;
4394 bfd_reloc_code_real_type r
;
4397 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4398 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4399 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4400 mask
= ip
->insn_mo
->mask
;
4402 expr1
.X_op
= O_constant
;
4403 expr1
.X_op_symbol
= NULL
;
4404 expr1
.X_add_symbol
= NULL
;
4405 expr1
.X_add_number
= 1;
4409 #endif /* LOSING_COMPILER */
4414 macro_build ((char *) NULL
, &icnt
, NULL
,
4415 dbl
? "dmultu" : "multu",
4417 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4423 /* The MIPS assembler some times generates shifts and adds. I'm
4424 not trying to be that fancy. GCC should do this for us
4426 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4427 macro_build ((char *) NULL
, &icnt
, NULL
,
4428 dbl
? "dmult" : "mult",
4430 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4436 mips_emit_delays ();
4438 mips_any_noreorder
= 1;
4439 macro_build ((char *) NULL
, &icnt
, NULL
,
4440 dbl
? "dmult" : "mult",
4442 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4443 macro_build ((char *) NULL
, &icnt
, NULL
,
4444 dbl
? "dsra32" : "sra",
4445 "d,w,<", dreg
, dreg
, 31);
4446 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4448 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4451 expr1
.X_add_number
= 8;
4452 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4453 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4454 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4457 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4463 mips_emit_delays ();
4465 mips_any_noreorder
= 1;
4466 macro_build ((char *) NULL
, &icnt
, NULL
,
4467 dbl
? "dmultu" : "multu",
4469 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4470 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4472 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4475 expr1
.X_add_number
= 8;
4476 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4477 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4478 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4484 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4485 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4486 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4488 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4492 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4493 (int) (imm_expr
.X_add_number
& 0x1f));
4494 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4495 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4496 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4500 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4501 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4502 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4504 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4508 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4509 (int) (imm_expr
.X_add_number
& 0x1f));
4510 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4511 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4512 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4516 assert (mips_isa
< 2);
4517 /* Even on a big endian machine $fn comes before $fn+1. We have
4518 to adjust when storing to memory. */
4519 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4520 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4521 (int) BFD_RELOC_LO16
, breg
);
4522 offset_expr
.X_add_number
+= 4;
4523 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4524 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4525 (int) BFD_RELOC_LO16
, breg
);
4530 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4531 treg
, (int) BFD_RELOC_LO16
);
4533 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4534 sreg
, (int) BFD_RELOC_LO16
);
4537 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4539 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4540 dreg
, (int) BFD_RELOC_LO16
);
4545 if (imm_expr
.X_add_number
== 0)
4547 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4548 sreg
, (int) BFD_RELOC_LO16
);
4553 as_warn ("Instruction %s: result is always false",
4555 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4558 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4560 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4561 sreg
, (int) BFD_RELOC_LO16
);
4564 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4566 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4567 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4568 mips_isa
< 3 ? "addiu" : "daddiu",
4569 "t,r,j", dreg
, sreg
,
4570 (int) BFD_RELOC_LO16
);
4575 load_register (&icnt
, AT
, &imm_expr
, 0);
4576 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4580 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4581 (int) BFD_RELOC_LO16
);
4586 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4592 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4593 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4594 (int) BFD_RELOC_LO16
);
4597 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4599 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4601 macro_build ((char *) NULL
, &icnt
, &expr1
,
4602 mask
== M_SGE_I
? "slti" : "sltiu",
4603 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4608 load_register (&icnt
, AT
, &imm_expr
, 0);
4609 macro_build ((char *) NULL
, &icnt
, NULL
,
4610 mask
== M_SGE_I
? "slt" : "sltu",
4611 "d,v,t", dreg
, sreg
, AT
);
4614 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4615 (int) BFD_RELOC_LO16
);
4620 case M_SGT
: /* sreg > treg <==> treg < sreg */
4626 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4629 case M_SGT_I
: /* sreg > I <==> I < sreg */
4635 load_register (&icnt
, AT
, &imm_expr
, 0);
4636 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4639 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4645 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4646 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4647 (int) BFD_RELOC_LO16
);
4650 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4656 load_register (&icnt
, AT
, &imm_expr
, 0);
4657 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4658 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4659 (int) BFD_RELOC_LO16
);
4663 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4665 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4666 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4669 load_register (&icnt
, AT
, &imm_expr
, 0);
4670 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4674 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4676 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4677 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4680 load_register (&icnt
, AT
, &imm_expr
, 0);
4681 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4687 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4690 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4694 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4696 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4702 if (imm_expr
.X_add_number
== 0)
4704 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4710 as_warn ("Instruction %s: result is always true",
4712 macro_build ((char *) NULL
, &icnt
, &expr1
,
4713 mips_isa
< 3 ? "addiu" : "daddiu",
4714 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4717 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4719 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4720 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4723 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4725 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4726 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4727 mips_isa
< 3 ? "addiu" : "daddiu",
4728 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4733 load_register (&icnt
, AT
, &imm_expr
, 0);
4734 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4738 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4746 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4748 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4749 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4750 dbl
? "daddi" : "addi",
4751 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4754 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4755 macro_build ((char *) NULL
, &icnt
, NULL
,
4756 dbl
? "dsub" : "sub",
4757 "d,v,t", dreg
, sreg
, AT
);
4763 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4765 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4766 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4767 dbl
? "daddiu" : "addiu",
4768 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4771 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4772 macro_build ((char *) NULL
, &icnt
, NULL
,
4773 dbl
? "dsubu" : "subu",
4774 "d,v,t", dreg
, sreg
, AT
);
4795 load_register (&icnt
, AT
, &imm_expr
, 0);
4796 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4801 assert (mips_isa
< 2);
4802 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4803 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4806 * Is the double cfc1 instruction a bug in the mips assembler;
4807 * or is there a reason for it?
4809 mips_emit_delays ();
4811 mips_any_noreorder
= 1;
4812 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4813 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4814 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4815 expr1
.X_add_number
= 3;
4816 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4817 (int) BFD_RELOC_LO16
);
4818 expr1
.X_add_number
= 2;
4819 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4820 (int) BFD_RELOC_LO16
);
4821 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4822 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4823 macro_build ((char *) NULL
, &icnt
, NULL
,
4824 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4825 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4826 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4836 if (offset_expr
.X_add_number
>= 0x7fff)
4837 as_bad ("operand overflow");
4838 /* avoid load delay */
4839 if (byte_order
== LITTLE_ENDIAN
)
4840 offset_expr
.X_add_number
+= 1;
4841 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4842 (int) BFD_RELOC_LO16
, breg
);
4843 if (byte_order
== LITTLE_ENDIAN
)
4844 offset_expr
.X_add_number
-= 1;
4846 offset_expr
.X_add_number
+= 1;
4847 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4848 (int) BFD_RELOC_LO16
, breg
);
4849 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4850 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4863 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4864 as_bad ("operand overflow");
4865 if (byte_order
== LITTLE_ENDIAN
)
4866 offset_expr
.X_add_number
+= off
;
4867 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4868 (int) BFD_RELOC_LO16
, breg
);
4869 if (byte_order
== LITTLE_ENDIAN
)
4870 offset_expr
.X_add_number
-= off
;
4872 offset_expr
.X_add_number
+= off
;
4873 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4874 (int) BFD_RELOC_LO16
, breg
);
4887 load_address (&icnt
, AT
, &offset_expr
);
4889 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4890 mips_isa
< 3 ? "addu" : "daddu",
4891 "d,v,t", AT
, AT
, breg
);
4892 if (byte_order
== LITTLE_ENDIAN
)
4893 expr1
.X_add_number
= off
;
4895 expr1
.X_add_number
= 0;
4896 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4897 (int) BFD_RELOC_LO16
, AT
);
4898 if (byte_order
== LITTLE_ENDIAN
)
4899 expr1
.X_add_number
= 0;
4901 expr1
.X_add_number
= off
;
4902 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4903 (int) BFD_RELOC_LO16
, AT
);
4908 load_address (&icnt
, AT
, &offset_expr
);
4910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4911 mips_isa
< 3 ? "addu" : "daddu",
4912 "d,v,t", AT
, AT
, breg
);
4913 if (byte_order
== BIG_ENDIAN
)
4914 expr1
.X_add_number
= 0;
4915 macro_build ((char *) NULL
, &icnt
, &expr1
,
4916 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4917 (int) BFD_RELOC_LO16
, AT
);
4918 if (byte_order
== BIG_ENDIAN
)
4919 expr1
.X_add_number
= 1;
4921 expr1
.X_add_number
= 0;
4922 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4923 (int) BFD_RELOC_LO16
, AT
);
4924 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4926 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4931 if (offset_expr
.X_add_number
>= 0x7fff)
4932 as_bad ("operand overflow");
4933 if (byte_order
== BIG_ENDIAN
)
4934 offset_expr
.X_add_number
+= 1;
4935 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4936 (int) BFD_RELOC_LO16
, breg
);
4937 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4938 if (byte_order
== BIG_ENDIAN
)
4939 offset_expr
.X_add_number
-= 1;
4941 offset_expr
.X_add_number
+= 1;
4942 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4943 (int) BFD_RELOC_LO16
, breg
);
4956 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4957 as_bad ("operand overflow");
4958 if (byte_order
== LITTLE_ENDIAN
)
4959 offset_expr
.X_add_number
+= off
;
4960 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4961 (int) BFD_RELOC_LO16
, breg
);
4962 if (byte_order
== LITTLE_ENDIAN
)
4963 offset_expr
.X_add_number
-= off
;
4965 offset_expr
.X_add_number
+= off
;
4966 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4967 (int) BFD_RELOC_LO16
, breg
);
4980 load_address (&icnt
, AT
, &offset_expr
);
4982 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4983 mips_isa
< 3 ? "addu" : "daddu",
4984 "d,v,t", AT
, AT
, breg
);
4985 if (byte_order
== LITTLE_ENDIAN
)
4986 expr1
.X_add_number
= off
;
4988 expr1
.X_add_number
= 0;
4989 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4990 (int) BFD_RELOC_LO16
, AT
);
4991 if (byte_order
== LITTLE_ENDIAN
)
4992 expr1
.X_add_number
= 0;
4994 expr1
.X_add_number
= off
;
4995 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4996 (int) BFD_RELOC_LO16
, AT
);
5000 load_address (&icnt
, AT
, &offset_expr
);
5002 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5003 mips_isa
< 3 ? "addu" : "daddu",
5004 "d,v,t", AT
, AT
, breg
);
5005 if (byte_order
== LITTLE_ENDIAN
)
5006 expr1
.X_add_number
= 0;
5007 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5008 (int) BFD_RELOC_LO16
, AT
);
5009 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5011 if (byte_order
== LITTLE_ENDIAN
)
5012 expr1
.X_add_number
= 1;
5014 expr1
.X_add_number
= 0;
5015 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5016 (int) BFD_RELOC_LO16
, AT
);
5017 if (byte_order
== LITTLE_ENDIAN
)
5018 expr1
.X_add_number
= 0;
5020 expr1
.X_add_number
= 1;
5021 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5022 (int) BFD_RELOC_LO16
, AT
);
5023 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5025 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5030 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5034 as_warn ("Macro used $at after \".set noat\"");
5037 /* This routine assembles an instruction into its binary format. As a
5038 side effect, it sets one of the global variables imm_reloc or
5039 offset_reloc to the type of relocation to do if one of the operands
5040 is an address expression. */
5045 struct mips_cl_insn
*ip
;
5050 struct mips_opcode
*insn
;
5053 unsigned int lastregno
= 0;
5058 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5070 as_fatal ("Unknown opcode: `%s'", str
);
5072 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5074 insn_error
= "unrecognized opcode";
5082 assert (strcmp (insn
->name
, str
) == 0);
5084 if (insn
->pinfo
== INSN_MACRO
)
5085 insn_isa
= insn
->match
;
5086 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5088 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5090 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5095 if (insn_isa
> mips_isa
5096 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5098 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5100 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5103 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5104 && strcmp (insn
->name
, insn
[1].name
) == 0)
5109 insn_error
= "opcode not supported on this processor";
5114 ip
->insn_opcode
= insn
->match
;
5115 for (args
= insn
->args
;; ++args
)
5121 case '\0': /* end of args */
5134 ip
->insn_opcode
|= lastregno
<< 21;
5139 ip
->insn_opcode
|= lastregno
<< 16;
5143 ip
->insn_opcode
|= lastregno
<< 11;
5149 /* handle optional base register.
5150 Either the base register is omitted or
5151 we must have a left paren. */
5152 /* this is dependent on the next operand specifier
5153 is a 'b' for base register */
5154 assert (args
[1] == 'b');
5158 case ')': /* these must match exactly */
5163 case '<': /* must be at least one digit */
5165 * According to the manual, if the shift amount is greater
5166 * than 31 or less than 0 the the shift amount should be
5167 * mod 32. In reality the mips assembler issues an error.
5168 * We issue a warning and mask out all but the low 5 bits.
5170 my_getExpression (&imm_expr
, s
);
5171 check_absolute_expr (ip
, &imm_expr
);
5172 if ((unsigned long) imm_expr
.X_add_number
> 31)
5174 as_warn ("Improper shift amount (%ld)",
5175 (long) imm_expr
.X_add_number
);
5176 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5178 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5179 imm_expr
.X_op
= O_absent
;
5183 case '>': /* shift amount minus 32 */
5184 my_getExpression (&imm_expr
, s
);
5185 check_absolute_expr (ip
, &imm_expr
);
5186 if ((unsigned long) imm_expr
.X_add_number
< 32
5187 || (unsigned long) imm_expr
.X_add_number
> 63)
5189 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5190 imm_expr
.X_op
= O_absent
;
5194 case 'k': /* cache code */
5195 case 'h': /* prefx code */
5196 my_getExpression (&imm_expr
, s
);
5197 check_absolute_expr (ip
, &imm_expr
);
5198 if ((unsigned long) imm_expr
.X_add_number
> 31)
5200 as_warn ("Invalid value for `%s' (%lu)",
5202 (unsigned long) imm_expr
.X_add_number
);
5203 imm_expr
.X_add_number
&= 0x1f;
5206 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5208 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5209 imm_expr
.X_op
= O_absent
;
5213 case 'c': /* break code */
5214 my_getExpression (&imm_expr
, s
);
5215 check_absolute_expr (ip
, &imm_expr
);
5216 if ((unsigned) imm_expr
.X_add_number
> 1023)
5217 as_warn ("Illegal break code (%ld)",
5218 (long) imm_expr
.X_add_number
);
5219 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5220 imm_expr
.X_op
= O_absent
;
5224 case 'B': /* syscall code */
5225 my_getExpression (&imm_expr
, s
);
5226 check_absolute_expr (ip
, &imm_expr
);
5227 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5228 as_warn ("Illegal syscall code (%ld)",
5229 (long) imm_expr
.X_add_number
);
5230 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5231 imm_expr
.X_op
= O_absent
;
5235 case 'C': /* Coprocessor code */
5236 my_getExpression (&imm_expr
, s
);
5237 check_absolute_expr (ip
, &imm_expr
);
5238 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5240 as_warn ("Coproccesor code > 25 bits (%ld)",
5241 (long) imm_expr
.X_add_number
);
5242 imm_expr
.X_add_number
&= ((1<<25) - 1);
5244 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5245 imm_expr
.X_op
= O_absent
;
5249 case 'b': /* base register */
5250 case 'd': /* destination register */
5251 case 's': /* source register */
5252 case 't': /* target register */
5253 case 'r': /* both target and source */
5254 case 'v': /* both dest and source */
5255 case 'w': /* both dest and target */
5256 case 'E': /* coprocessor target register */
5257 case 'G': /* coprocessor destination register */
5258 case 'x': /* ignore register name */
5259 case 'z': /* must be zero register */
5273 while (isdigit (*s
));
5275 as_bad ("Invalid register number (%d)", regno
);
5277 else if (*args
== 'E' || *args
== 'G')
5281 if (s
[1] == 'f' && s
[2] == 'p')
5286 else if (s
[1] == 's' && s
[2] == 'p')
5291 else if (s
[1] == 'g' && s
[2] == 'p')
5296 else if (s
[1] == 'a' && s
[2] == 't')
5301 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5306 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5318 as_warn ("Used $at without \".set noat\"");
5324 if (c
== 'r' || c
== 'v' || c
== 'w')
5331 /* 'z' only matches $0. */
5332 if (c
== 'z' && regno
!= 0)
5340 ip
->insn_opcode
|= regno
<< 21;
5344 ip
->insn_opcode
|= regno
<< 11;
5349 ip
->insn_opcode
|= regno
<< 16;
5352 /* This case exists because on the r3000 trunc
5353 expands into a macro which requires a gp
5354 register. On the r6000 or r4000 it is
5355 assembled into a single instruction which
5356 ignores the register. Thus the insn version
5357 is MIPS_ISA2 and uses 'x', and the macro
5358 version is MIPS_ISA1 and uses 't'. */
5361 /* This case is for the div instruction, which
5362 acts differently if the destination argument
5363 is $0. This only matches $0, and is checked
5364 outside the switch. */
5375 ip
->insn_opcode
|= lastregno
<< 21;
5378 ip
->insn_opcode
|= lastregno
<< 16;
5383 case 'D': /* floating point destination register */
5384 case 'S': /* floating point source register */
5385 case 'T': /* floating point target register */
5386 case 'R': /* floating point source register */
5390 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5400 while (isdigit (*s
));
5403 as_bad ("Invalid float register number (%d)", regno
);
5405 if ((regno
& 1) != 0
5407 && ! (strcmp (str
, "mtc1") == 0 ||
5408 strcmp (str
, "mfc1") == 0 ||
5409 strcmp (str
, "lwc1") == 0 ||
5410 strcmp (str
, "swc1") == 0))
5411 as_warn ("Float register should be even, was %d",
5419 if (c
== 'V' || c
== 'W')
5429 ip
->insn_opcode
|= regno
<< 6;
5433 ip
->insn_opcode
|= regno
<< 11;
5437 ip
->insn_opcode
|= regno
<< 16;
5440 ip
->insn_opcode
|= regno
<< 21;
5449 ip
->insn_opcode
|= lastregno
<< 11;
5452 ip
->insn_opcode
|= lastregno
<< 16;
5458 my_getExpression (&imm_expr
, s
);
5459 if (imm_expr
.X_op
!= O_big
5460 && imm_expr
.X_op
!= O_constant
)
5461 insn_error
= "absolute expression required";
5466 my_getExpression (&offset_expr
, s
);
5467 imm_reloc
= BFD_RELOC_32
;
5479 unsigned char temp
[8];
5481 unsigned int length
;
5486 /* These only appear as the last operand in an
5487 instruction, and every instruction that accepts
5488 them in any variant accepts them in all variants.
5489 This means we don't have to worry about backing out
5490 any changes if the instruction does not match.
5492 The difference between them is the size of the
5493 floating point constant and where it goes. For 'F'
5494 and 'L' the constant is 64 bits; for 'f' and 'l' it
5495 is 32 bits. Where the constant is placed is based
5496 on how the MIPS assembler does things:
5499 f -- immediate value
5502 The .lit4 and .lit8 sections are only used if
5503 permitted by the -G argument.
5505 When generating embedded PIC code, we use the
5506 .lit8 section but not the .lit4 section (we can do
5507 .lit4 inline easily; we need to put .lit8
5508 somewhere in the data segment, and using .lit8
5509 permits the linker to eventually combine identical
5512 f64
= *args
== 'F' || *args
== 'L';
5514 save_in
= input_line_pointer
;
5515 input_line_pointer
= s
;
5516 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5518 s
= input_line_pointer
;
5519 input_line_pointer
= save_in
;
5520 if (err
!= NULL
&& *err
!= '\0')
5522 as_bad ("Bad floating point constant: %s", err
);
5523 memset (temp
, '\0', sizeof temp
);
5524 length
= f64
? 8 : 4;
5527 assert (length
== (f64
? 8 : 4));
5531 && (! USE_GLOBAL_POINTER_OPT
5532 || mips_pic
== EMBEDDED_PIC
5533 || g_switch_value
< 4)
5536 imm_expr
.X_op
= O_constant
;
5537 if (byte_order
== LITTLE_ENDIAN
)
5538 imm_expr
.X_add_number
=
5539 (((((((int) temp
[3] << 8)
5544 imm_expr
.X_add_number
=
5545 (((((((int) temp
[0] << 8)
5552 const char *newname
;
5555 /* Switch to the right section. */
5557 subseg
= now_subseg
;
5560 default: /* unused default case avoids warnings. */
5562 newname
= RDATA_SECTION_NAME
;
5563 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5567 newname
= RDATA_SECTION_NAME
;
5570 assert (!USE_GLOBAL_POINTER_OPT
5571 || g_switch_value
>= 4);
5575 new_seg
= subseg_new (newname
, (subsegT
) 0);
5576 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5577 bfd_set_section_flags (stdoutput
, new_seg
,
5582 frag_align (*args
== 'l' ? 2 : 3, 0);
5583 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5584 record_alignment (new_seg
, 4);
5586 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5588 as_bad ("Can't use floating point insn in this section");
5590 /* Set the argument to the current address in the
5592 offset_expr
.X_op
= O_symbol
;
5593 offset_expr
.X_add_symbol
=
5594 symbol_new ("L0\001", now_seg
,
5595 (valueT
) frag_now_fix (), frag_now
);
5596 offset_expr
.X_add_number
= 0;
5598 /* Put the floating point number into the section. */
5599 p
= frag_more ((int) length
);
5600 memcpy (p
, temp
, length
);
5602 /* Switch back to the original section. */
5603 subseg_set (seg
, subseg
);
5608 case 'i': /* 16 bit unsigned immediate */
5609 case 'j': /* 16 bit signed immediate */
5610 imm_reloc
= BFD_RELOC_LO16
;
5611 c
= my_getSmallExpression (&imm_expr
, s
);
5616 if (imm_expr
.X_op
== O_constant
)
5617 imm_expr
.X_add_number
=
5618 (imm_expr
.X_add_number
>> 16) & 0xffff;
5621 imm_reloc
= BFD_RELOC_HI16_S
;
5622 imm_unmatched_hi
= true;
5625 imm_reloc
= BFD_RELOC_HI16
;
5630 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5631 || ((imm_expr
.X_add_number
< 0
5632 || imm_expr
.X_add_number
>= 0x10000)
5633 && imm_expr
.X_op
== O_constant
))
5635 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5636 !strcmp (insn
->name
, insn
[1].name
))
5638 if (imm_expr
.X_op
!= O_constant
5639 && imm_expr
.X_op
!= O_big
)
5640 insn_error
= "absolute expression required";
5642 as_bad ("16 bit expression not in range 0..65535");
5650 /* The upper bound should be 0x8000, but
5651 unfortunately the MIPS assembler accepts numbers
5652 from 0x8000 to 0xffff and sign extends them, and
5653 we want to be compatible. We only permit this
5654 extended range for an instruction which does not
5655 provide any further alternates, since those
5656 alternates may handle other cases. People should
5657 use the numbers they mean, rather than relying on
5658 a mysterious sign extension. */
5659 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5660 strcmp (insn
->name
, insn
[1].name
) == 0);
5665 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5666 || ((imm_expr
.X_add_number
< -0x8000
5667 || imm_expr
.X_add_number
>= max
)
5668 && imm_expr
.X_op
== O_constant
)
5670 && imm_expr
.X_add_number
< 0
5672 && imm_expr
.X_unsigned
5673 && sizeof (imm_expr
.X_add_number
) <= 4))
5677 if (imm_expr
.X_op
!= O_constant
5678 && imm_expr
.X_op
!= O_big
)
5679 insn_error
= "absolute expression required";
5681 as_bad ("16 bit expression not in range -32768..32767");
5687 case 'o': /* 16 bit offset */
5688 c
= my_getSmallExpression (&offset_expr
, s
);
5690 /* If this value won't fit into a 16 bit offset, then go
5691 find a macro that will generate the 32 bit offset
5692 code pattern. As a special hack, we accept the
5693 difference of two local symbols as a constant. This
5694 is required to suppose embedded PIC switches, which
5695 use an instruction which looks like
5696 lw $4,$L12-$LS12($4)
5697 The problem with handling this in a more general
5698 fashion is that the macro function doesn't expect to
5699 see anything which can be handled in a single
5700 constant instruction. */
5702 && (offset_expr
.X_op
!= O_constant
5703 || offset_expr
.X_add_number
>= 0x8000
5704 || offset_expr
.X_add_number
< -0x8000)
5705 && (mips_pic
!= EMBEDDED_PIC
5706 || offset_expr
.X_op
!= O_subtract
5707 || now_seg
!= text_section
5708 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5712 offset_reloc
= BFD_RELOC_LO16
;
5713 if (c
== 'h' || c
== 'H')
5715 assert (offset_expr
.X_op
== O_constant
);
5716 offset_expr
.X_add_number
=
5717 (offset_expr
.X_add_number
>> 16) & 0xffff;
5722 case 'p': /* pc relative offset */
5723 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5724 my_getExpression (&offset_expr
, s
);
5728 case 'u': /* upper 16 bits */
5729 c
= my_getSmallExpression (&imm_expr
, s
);
5730 if (imm_expr
.X_op
== O_constant
5731 && (imm_expr
.X_add_number
< 0
5732 || imm_expr
.X_add_number
>= 0x10000))
5733 as_bad ("lui expression not in range 0..65535");
5734 imm_reloc
= BFD_RELOC_LO16
;
5739 if (imm_expr
.X_op
== O_constant
)
5740 imm_expr
.X_add_number
=
5741 (imm_expr
.X_add_number
>> 16) & 0xffff;
5744 imm_reloc
= BFD_RELOC_HI16_S
;
5745 imm_unmatched_hi
= true;
5748 imm_reloc
= BFD_RELOC_HI16
;
5754 case 'a': /* 26 bit address */
5755 my_getExpression (&offset_expr
, s
);
5757 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5760 case 'N': /* 3 bit branch condition code */
5761 case 'M': /* 3 bit compare condition code */
5762 my_getExpression (&imm_expr
, s
);
5763 check_absolute_expr (ip
, &imm_expr
);
5764 if ((unsigned long) imm_expr
.X_add_number
> 7)
5766 as_warn ("Condition code > 7 (%ld)",
5767 (long) imm_expr
.X_add_number
);
5768 imm_expr
.X_add_number
&= 7;
5771 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5773 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5774 imm_expr
.X_op
= O_absent
;
5779 fprintf (stderr
, "bad char = '%c'\n", *args
);
5784 /* Args don't match. */
5785 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5786 !strcmp (insn
->name
, insn
[1].name
))
5792 insn_error
= "illegal operands";
5801 my_getSmallExpression (ep
, str
)
5812 ((str
[1] == 'h' && str
[2] == 'i')
5813 || (str
[1] == 'H' && str
[2] == 'I')
5814 || (str
[1] == 'l' && str
[2] == 'o'))
5826 * A small expression may be followed by a base register.
5827 * Scan to the end of this operand, and then back over a possible
5828 * base register. Then scan the small expression up to that
5829 * point. (Based on code in sparc.c...)
5831 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5833 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5835 if (isdigit (sp
[-2]))
5837 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5839 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5845 else if (sp
- 5 >= str
5848 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5849 || (sp
[-3] == 's' && sp
[-2] == 'p')
5850 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5851 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5857 /* no expression means zero offset */
5860 /* %xx(reg) is an error */
5861 ep
->X_op
= O_absent
;
5866 ep
->X_op
= O_constant
;
5869 ep
->X_add_symbol
= NULL
;
5870 ep
->X_op_symbol
= NULL
;
5871 ep
->X_add_number
= 0;
5876 my_getExpression (ep
, str
);
5883 my_getExpression (ep
, str
);
5884 return c
; /* => %hi or %lo encountered */
5888 my_getExpression (ep
, str
)
5894 save_in
= input_line_pointer
;
5895 input_line_pointer
= str
;
5897 expr_end
= input_line_pointer
;
5898 input_line_pointer
= save_in
;
5901 /* Turn a string in input_line_pointer into a floating point constant
5902 of type type, and store the appropriate bytes in *litP. The number
5903 of LITTLENUMS emitted is stored in *sizeP . An error message is
5904 returned, or NULL on OK. */
5907 md_atof (type
, litP
, sizeP
)
5913 LITTLENUM_TYPE words
[4];
5929 return "bad call to md_atof";
5932 t
= atof_ieee (input_line_pointer
, type
, words
);
5934 input_line_pointer
= t
;
5938 if (byte_order
== LITTLE_ENDIAN
)
5940 for (i
= prec
- 1; i
>= 0; i
--)
5942 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5948 for (i
= 0; i
< prec
; i
++)
5950 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5959 md_number_to_chars (buf
, val
, n
)
5967 number_to_chars_littleendian (buf
, val
, n
);
5971 number_to_chars_bigendian (buf
, val
, n
);
5979 CONST
char *md_shortopts
= "O::g::G:";
5981 struct option md_longopts
[] = {
5982 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5983 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5984 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5985 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5986 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5987 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5988 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5989 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5990 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5991 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5992 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5993 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5994 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5995 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5996 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5997 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5998 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5999 {"break", no_argument
, NULL
, OPTION_BREAK
},
6000 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
6001 #define OPTION_EB (OPTION_MD_BASE + 11)
6002 {"EB", no_argument
, NULL
, OPTION_EB
},
6003 #define OPTION_EL (OPTION_MD_BASE + 12)
6004 {"EL", no_argument
, NULL
, OPTION_EL
},
6005 #define OPTION_M4650 (OPTION_MD_BASE + 13)
6006 {"m4650", no_argument
, NULL
, OPTION_M4650
},
6007 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
6008 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
6009 #define OPTION_M4010 (OPTION_MD_BASE + 15)
6010 {"m4010", no_argument
, NULL
, OPTION_M4010
},
6011 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
6012 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
6013 #define OPTION_M4100 (OPTION_MD_BASE + 17)
6014 {"m4100", no_argument
, NULL
, OPTION_M4100
},
6015 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
6016 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
6018 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
6019 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
6020 #define OPTION_XGOT (OPTION_MD_BASE + 19)
6021 #define OPTION_32 (OPTION_MD_BASE + 20)
6022 #define OPTION_64 (OPTION_MD_BASE + 21)
6024 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
6025 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
6026 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
6027 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
6028 {"32", no_argument
, NULL
, OPTION_32
},
6029 {"64", no_argument
, NULL
, OPTION_64
},
6032 {NULL
, no_argument
, NULL
, 0}
6034 size_t md_longopts_size
= sizeof(md_longopts
);
6037 md_parse_option (c
, arg
)
6052 target_big_endian
= 1;
6056 target_big_endian
= 0;
6060 if (arg
&& arg
[1] == '0')
6070 mips_debug
= atoi (arg
);
6071 /* When the MIPS assembler sees -g or -g2, it does not do
6072 optimizations which limit full symbolic debugging. We take
6073 that to be equivalent to -O0. */
6074 if (mips_debug
== 2)
6106 /* Identify the processor type */
6108 if (strcmp (p
, "default") == 0
6109 || strcmp (p
, "DEFAULT") == 0)
6115 /* We need to cope with the various "vr" prefixes for the 4300
6117 if (*p
== 'v' || *p
== 'V')
6123 if (*p
== 'r' || *p
== 'R')
6130 if (strcmp (p
, "10000") == 0
6131 || strcmp (p
, "10k") == 0
6132 || strcmp (p
, "10K") == 0)
6137 if (strcmp (p
, "2000") == 0
6138 || strcmp (p
, "2k") == 0
6139 || strcmp (p
, "2K") == 0)
6144 if (strcmp (p
, "3000") == 0
6145 || strcmp (p
, "3k") == 0
6146 || strcmp (p
, "3K") == 0)
6151 if (strcmp (p
, "4000") == 0
6152 || strcmp (p
, "4k") == 0
6153 || strcmp (p
, "4K") == 0)
6155 else if (strcmp (p
, "4100") == 0)
6161 else if (strcmp (p
, "4300") == 0)
6163 else if (strcmp (p
, "4400") == 0)
6165 else if (strcmp (p
, "4600") == 0)
6167 else if (strcmp (p
, "4650") == 0)
6173 else if (strcmp (p
, "4010") == 0)
6182 if (strcmp (p
, "6000") == 0
6183 || strcmp (p
, "6k") == 0
6184 || strcmp (p
, "6K") == 0)
6189 if (strcmp (p
, "8000") == 0
6190 || strcmp (p
, "8k") == 0
6191 || strcmp (p
, "8K") == 0)
6196 if (strcmp (p
, "orion") == 0)
6201 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6203 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6209 as_bad ("invalid architecture -mcpu=%s", arg
);
6220 case OPTION_NO_M4650
:
6228 case OPTION_NO_M4010
:
6236 case OPTION_NO_M4100
:
6240 case OPTION_MEMBEDDED_PIC
:
6241 mips_pic
= EMBEDDED_PIC
;
6242 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6244 as_bad ("-G may not be used with embedded PIC code");
6247 g_switch_value
= 0x7fffffff;
6250 /* When generating ELF code, we permit -KPIC and -call_shared to
6251 select SVR4_PIC, and -non_shared to select no PIC. This is
6252 intended to be compatible with Irix 5. */
6253 case OPTION_CALL_SHARED
:
6254 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6256 as_bad ("-call_shared is supported only for ELF format");
6259 mips_pic
= SVR4_PIC
;
6260 if (g_switch_seen
&& g_switch_value
!= 0)
6262 as_bad ("-G may not be used with SVR4 PIC code");
6268 case OPTION_NON_SHARED
:
6269 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6271 as_bad ("-non_shared is supported only for ELF format");
6277 /* The -xgot option tells the assembler to use 32 offsets when
6278 accessing the got in SVR4_PIC mode. It is for Irix
6285 if (! USE_GLOBAL_POINTER_OPT
)
6287 as_bad ("-G is not supported for this configuration");
6290 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6292 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6296 g_switch_value
= atoi (arg
);
6300 /* The -32 and -64 options tell the assembler to output the 32
6301 bit or the 64 bit MIPS ELF format. */
6308 const char **list
, **l
;
6310 list
= bfd_target_list ();
6311 for (l
= list
; *l
!= NULL
; l
++)
6312 if (strcmp (*l
, "elf64-bigmips") == 0
6313 || strcmp (*l
, "elf64-littlemips") == 0)
6316 as_fatal ("No compiled in support for 64 bit object file format");
6330 md_show_usage (stream
)
6335 -membedded-pic generate embedded position independent code\n\
6336 -EB generate big endian output\n\
6337 -EL generate little endian output\n\
6338 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6339 -G NUM allow referencing objects up to NUM bytes\n\
6340 implicitly with the gp register [default 8]\n");
6342 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6343 -mips2, -mcpu=r6000 generate code for r6000\n\
6344 -mips3, -mcpu=r4000 generate code for r4000\n\
6345 -mips4, -mcpu=r8000 generate code for r8000\n\
6346 -mcpu=vr4300 generate code for vr4300\n\
6347 -mcpu=vr4100 generate code for vr4100\n\
6348 -m4650 permit R4650 instructions\n\
6349 -no-m4650 do not permit R4650 instructions\n\
6350 -m4010 permit R4010 instructions\n\
6351 -no-m4010 do not permit R4010 instructions\n\
6352 -m4100 permit VR4100 instructions\n\
6353 -no-m4100 do not permit VR4100 instructions\n");
6355 -O0 remove unneeded NOPs, do not swap branches\n\
6356 -O remove unneeded NOPs and swap branches\n\
6357 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6358 --break, --no-trap break exception on div by 0 and mult overflow\n");
6361 -KPIC, -call_shared generate SVR4 position independent code\n\
6362 -non_shared do not generate position independent code\n\
6363 -xgot assume a 32 bit GOT\n\
6364 -32 create 32 bit object file (default)\n\
6365 -64 create 64 bit object file\n");
6370 mips_init_after_args ()
6372 if (target_big_endian
)
6373 byte_order
= BIG_ENDIAN
;
6375 byte_order
= LITTLE_ENDIAN
;
6379 md_pcrel_from (fixP
)
6382 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6383 && fixP
->fx_addsy
!= (symbolS
*) NULL
6384 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6386 /* This makes a branch to an undefined symbol be a branch to the
6387 current location. */
6391 /* return the address of the delay slot */
6392 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6395 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6396 reloc for a cons. We could use the definition there, except that
6397 we want to handle 64 bit relocs specially. */
6400 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6403 unsigned int nbytes
;
6406 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6408 if (nbytes
== 8 && ! mips_64
)
6410 if (byte_order
== BIG_ENDIAN
)
6415 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6416 as_bad ("Unsupported reloc size %d", nbytes
);
6418 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6421 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6424 /* Sort any unmatched HI16_S relocs so that they immediately precede
6425 the corresponding LO reloc. This is called before md_apply_fix and
6426 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6427 explicit use of the %hi modifier. */
6432 struct mips_hi_fixup
*l
;
6434 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6436 segment_info_type
*seginfo
;
6439 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6441 /* Check quickly whether the next fixup happens to be a matching
6443 if (l
->fixp
->fx_next
!= NULL
6444 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6445 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6446 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6449 /* Look through the fixups for this segment for a matching %lo.
6450 When we find one, move the %hi just in front of it. We do
6451 this in two passes. In the first pass, we try to find a
6452 unique %lo. In the second pass, we permit multiple %hi
6453 relocs for a single %lo (this is a GNU extension). */
6454 seginfo
= seg_info (l
->seg
);
6455 for (pass
= 0; pass
< 2; pass
++)
6460 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6462 /* Check whether this is a %lo fixup which matches l->fixp. */
6463 if (f
->fx_r_type
== BFD_RELOC_LO16
6464 && f
->fx_addsy
== l
->fixp
->fx_addsy
6465 && f
->fx_offset
== l
->fixp
->fx_offset
6468 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6469 || prev
->fx_addsy
!= f
->fx_addsy
6470 || prev
->fx_offset
!= f
->fx_offset
))
6474 /* Move l->fixp before f. */
6475 for (pf
= &seginfo
->fix_root
;
6477 pf
= &(*pf
)->fx_next
)
6478 assert (*pf
!= NULL
);
6480 *pf
= l
->fixp
->fx_next
;
6482 l
->fixp
->fx_next
= f
;
6484 seginfo
->fix_root
= l
->fixp
;
6486 prev
->fx_next
= l
->fixp
;
6498 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6499 "Unmatched %%hi reloc");
6504 /* When generating embedded PIC code we need to use a special
6505 relocation to represent the difference of two symbols in the .text
6506 section (switch tables use a difference of this sort). See
6507 include/coff/mips.h for details. This macro checks whether this
6508 fixup requires the special reloc. */
6509 #define SWITCH_TABLE(fixp) \
6510 ((fixp)->fx_r_type == BFD_RELOC_32 \
6511 && (fixp)->fx_addsy != NULL \
6512 && (fixp)->fx_subsy != NULL \
6513 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6514 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6516 /* When generating embedded PIC code we must keep all PC relative
6517 relocations, in case the linker has to relax a call. We also need
6518 to keep relocations for switch table entries. */
6522 mips_force_relocation (fixp
)
6525 return (mips_pic
== EMBEDDED_PIC
6527 || SWITCH_TABLE (fixp
)
6528 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6529 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6532 /* Apply a fixup to the object file. */
6535 md_apply_fix (fixP
, valueP
)
6542 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6545 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6547 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6550 switch (fixP
->fx_r_type
)
6552 case BFD_RELOC_MIPS_JMP
:
6553 case BFD_RELOC_HI16
:
6554 case BFD_RELOC_HI16_S
:
6555 case BFD_RELOC_MIPS_GPREL
:
6556 case BFD_RELOC_MIPS_LITERAL
:
6557 case BFD_RELOC_MIPS_CALL16
:
6558 case BFD_RELOC_MIPS_GOT16
:
6559 case BFD_RELOC_MIPS_GPREL32
:
6560 case BFD_RELOC_MIPS_GOT_HI16
:
6561 case BFD_RELOC_MIPS_GOT_LO16
:
6562 case BFD_RELOC_MIPS_CALL_HI16
:
6563 case BFD_RELOC_MIPS_CALL_LO16
:
6565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6566 "Invalid PC relative reloc");
6567 /* Nothing needed to do. The value comes from the reloc entry */
6570 case BFD_RELOC_PCREL_HI16_S
:
6571 /* The addend for this is tricky if it is internal, so we just
6572 do everything here rather than in bfd_perform_relocation. */
6573 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6575 /* For an external symbol adjust by the address to make it
6576 pcrel_offset. We use the address of the RELLO reloc
6577 which follows this one. */
6578 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6579 + fixP
->fx_next
->fx_where
);
6584 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6585 if (byte_order
== BIG_ENDIAN
)
6587 md_number_to_chars (buf
, value
, 2);
6590 case BFD_RELOC_PCREL_LO16
:
6591 /* The addend for this is tricky if it is internal, so we just
6592 do everything here rather than in bfd_perform_relocation. */
6593 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6594 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6595 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6596 if (byte_order
== BIG_ENDIAN
)
6598 md_number_to_chars (buf
, value
, 2);
6602 /* If we are deleting this reloc entry, we must fill in the
6603 value now. This can happen if we have a .word which is not
6604 resolved when it appears but is later defined. We also need
6605 to fill in the value if this is an embedded PIC switch table
6608 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6609 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6614 /* If we are deleting this reloc entry, we must fill in the
6616 assert (fixP
->fx_size
== 2);
6618 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6622 case BFD_RELOC_LO16
:
6623 /* When handling an embedded PIC switch statement, we can wind
6624 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6627 if (value
< -0x8000 || value
> 0x7fff)
6628 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6629 "relocation overflow");
6630 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6631 if (byte_order
== BIG_ENDIAN
)
6633 md_number_to_chars (buf
, value
, 2);
6637 case BFD_RELOC_16_PCREL_S2
:
6639 * We need to save the bits in the instruction since fixup_segment()
6640 * might be deleting the relocation entry (i.e., a branch within
6641 * the current segment).
6644 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6645 "Branch to odd address (%lx)", value
);
6648 /* update old instruction data */
6649 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6653 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6657 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6665 if (value
>= -0x8000 && value
< 0x8000)
6666 insn
|= value
& 0xffff;
6669 /* The branch offset is too large. If this is an
6670 unconditional branch, and we are not generating PIC code,
6671 we can convert it to an absolute jump instruction. */
6672 if (mips_pic
== NO_PIC
6674 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6675 && (fixP
->fx_frag
->fr_address
6676 < text_section
->vma
+ text_section
->_raw_size
)
6677 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6678 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6679 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6681 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6682 insn
= 0x0c000000; /* jal */
6684 insn
= 0x08000000; /* j */
6685 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6687 fixP
->fx_addsy
= section_symbol (text_section
);
6688 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6692 /* FIXME. It would be possible in principle to handle
6693 conditional branches which overflow. They could be
6694 transformed into a branch around a jump. This would
6695 require setting up variant frags for each different
6696 branch type. The native MIPS assembler attempts to
6697 handle these cases, but it appears to do it
6699 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6700 "Relocation overflow");
6704 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6719 const struct mips_opcode
*p
;
6720 int treg
, sreg
, dreg
, shamt
;
6725 for (i
= 0; i
< NUMOPCODES
; ++i
)
6727 p
= &mips_opcodes
[i
];
6728 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6730 printf ("%08lx %s\t", oc
, p
->name
);
6731 treg
= (oc
>> 16) & 0x1f;
6732 sreg
= (oc
>> 21) & 0x1f;
6733 dreg
= (oc
>> 11) & 0x1f;
6734 shamt
= (oc
>> 6) & 0x1f;
6736 for (args
= p
->args
;; ++args
)
6747 printf ("%c", *args
);
6751 assert (treg
== sreg
);
6752 printf ("$%d,$%d", treg
, sreg
);
6757 printf ("$%d", dreg
);
6762 printf ("$%d", treg
);
6766 printf ("0x%x", treg
);
6771 printf ("$%d", sreg
);
6775 printf ("0x%08lx", oc
& 0x1ffffff);
6787 printf ("$%d", shamt
);
6798 printf ("%08lx UNDEFINED\n", oc
);
6809 name
= input_line_pointer
;
6810 c
= get_symbol_end ();
6811 p
= (symbolS
*) symbol_find_or_make (name
);
6812 *input_line_pointer
= c
;
6816 /* Align the current frag to a given power of two. The MIPS assembler
6817 also automatically adjusts any preceding label. */
6820 mips_align (to
, fill
, label
)
6825 mips_emit_delays ();
6826 frag_align (to
, fill
);
6827 record_alignment (now_seg
, to
);
6830 assert (S_GET_SEGMENT (label
) == now_seg
);
6831 label
->sy_frag
= frag_now
;
6832 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6836 /* Align to a given power of two. .align 0 turns off the automatic
6837 alignment used by the data creating pseudo-ops. */
6844 register long temp_fill
;
6845 long max_alignment
= 15;
6849 o Note that the assembler pulls down any immediately preceeding label
6850 to the aligned address.
6851 o It's not documented but auto alignment is reinstated by
6852 a .align pseudo instruction.
6853 o Note also that after auto alignment is turned off the mips assembler
6854 issues an error on attempt to assemble an improperly aligned data item.
6859 temp
= get_absolute_expression ();
6860 if (temp
> max_alignment
)
6861 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6864 as_warn ("Alignment negative: 0 assumed.");
6867 if (*input_line_pointer
== ',')
6869 input_line_pointer
++;
6870 temp_fill
= get_absolute_expression ();
6877 mips_align (temp
, (int) temp_fill
, insn_label
);
6884 demand_empty_rest_of_line ();
6888 mips_flush_pending_output ()
6890 mips_emit_delays ();
6900 /* When generating embedded PIC code, we only use the .text, .lit8,
6901 .sdata and .sbss sections. We change the .data and .rdata
6902 pseudo-ops to use .sdata. */
6903 if (mips_pic
== EMBEDDED_PIC
6904 && (sec
== 'd' || sec
== 'r'))
6907 mips_emit_delays ();
6917 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6918 demand_empty_rest_of_line ();
6922 if (USE_GLOBAL_POINTER_OPT
)
6924 seg
= subseg_new (RDATA_SECTION_NAME
,
6925 (subsegT
) get_absolute_expression ());
6926 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6928 bfd_set_section_flags (stdoutput
, seg
,
6934 bfd_set_section_alignment (stdoutput
, seg
, 4);
6936 demand_empty_rest_of_line ();
6940 as_bad ("No read only data section in this object file format");
6941 demand_empty_rest_of_line ();
6947 if (USE_GLOBAL_POINTER_OPT
)
6949 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6950 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6952 bfd_set_section_flags (stdoutput
, seg
,
6953 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6955 bfd_set_section_alignment (stdoutput
, seg
, 4);
6957 demand_empty_rest_of_line ();
6962 as_bad ("Global pointers not supported; recompile -G 0");
6963 demand_empty_rest_of_line ();
6972 mips_enable_auto_align ()
6984 mips_emit_delays ();
6985 if (log_size
> 0 && auto_align
)
6986 mips_align (log_size
, 0, label
);
6988 cons (1 << log_size
);
6999 mips_emit_delays ();
7003 mips_align (3, 0, label
);
7005 mips_align (2, 0, label
);
7012 /* Handle .globl. We need to override it because on Irix 5 you are
7015 where foo is an undefined symbol, to mean that foo should be
7016 considered to be the address of a function. */
7027 name
= input_line_pointer
;
7028 c
= get_symbol_end ();
7029 symbolP
= symbol_find_or_make (name
);
7030 *input_line_pointer
= c
;
7033 /* On Irix 5, every global symbol that is not explicitly labelled as
7034 being a function is apparently labelled as being an object. */
7037 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7042 secname
= input_line_pointer
;
7043 c
= get_symbol_end ();
7044 sec
= bfd_get_section_by_name (stdoutput
, secname
);
7046 as_bad ("%s: no such section", secname
);
7047 *input_line_pointer
= c
;
7049 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
7050 flag
= BSF_FUNCTION
;
7053 symbolP
->bsym
->flags
|= flag
;
7055 S_SET_EXTERNAL (symbolP
);
7056 demand_empty_rest_of_line ();
7066 opt
= input_line_pointer
;
7067 c
= get_symbol_end ();
7071 /* FIXME: What does this mean? */
7073 else if (strncmp (opt
, "pic", 3) == 0)
7081 mips_pic
= SVR4_PIC
;
7083 as_bad (".option pic%d not supported", i
);
7085 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
7087 if (g_switch_seen
&& g_switch_value
!= 0)
7088 as_warn ("-G may not be used with SVR4 PIC code");
7090 bfd_set_gp_size (stdoutput
, 0);
7094 as_warn ("Unrecognized option \"%s\"", opt
);
7096 *input_line_pointer
= c
;
7097 demand_empty_rest_of_line ();
7104 char *name
= input_line_pointer
, ch
;
7106 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7107 input_line_pointer
++;
7108 ch
= *input_line_pointer
;
7109 *input_line_pointer
= '\0';
7111 if (strcmp (name
, "reorder") == 0)
7115 prev_insn_unreordered
= 1;
7116 prev_prev_insn_unreordered
= 1;
7120 else if (strcmp (name
, "noreorder") == 0)
7122 mips_emit_delays ();
7124 mips_any_noreorder
= 1;
7126 else if (strcmp (name
, "at") == 0)
7130 else if (strcmp (name
, "noat") == 0)
7134 else if (strcmp (name
, "macro") == 0)
7136 mips_warn_about_macros
= 0;
7138 else if (strcmp (name
, "nomacro") == 0)
7140 if (mips_noreorder
== 0)
7141 as_bad ("`noreorder' must be set before `nomacro'");
7142 mips_warn_about_macros
= 1;
7144 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7148 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7152 else if (strcmp (name
, "bopt") == 0)
7156 else if (strcmp (name
, "nobopt") == 0)
7160 else if (strncmp (name
, "mips", 4) == 0)
7164 /* Permit the user to change the ISA on the fly. Needless to
7165 say, misuse can cause serious problems. */
7166 isa
= atoi (name
+ 4);
7168 mips_isa
= file_mips_isa
;
7169 else if (isa
< 1 || isa
> 4)
7170 as_bad ("unknown ISA level");
7176 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7178 *input_line_pointer
= ch
;
7179 demand_empty_rest_of_line ();
7182 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7183 .option pic2. It means to generate SVR4 PIC calls. */
7189 mips_pic
= SVR4_PIC
;
7190 if (USE_GLOBAL_POINTER_OPT
)
7192 if (g_switch_seen
&& g_switch_value
!= 0)
7193 as_warn ("-G may not be used with SVR4 PIC code");
7196 bfd_set_gp_size (stdoutput
, 0);
7197 demand_empty_rest_of_line ();
7200 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7201 PIC code. It sets the $gp register for the function based on the
7202 function address, which is in the register named in the argument.
7203 This uses a relocation against _gp_disp, which is handled specially
7204 by the linker. The result is:
7205 lui $gp,%hi(_gp_disp)
7206 addiu $gp,$gp,%lo(_gp_disp)
7207 addu $gp,$gp,.cpload argument
7208 The .cpload argument is normally $25 == $t9. */
7217 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7218 if (mips_pic
!= SVR4_PIC
)
7224 /* .cpload should be a in .set noreorder section. */
7225 if (mips_noreorder
== 0)
7226 as_warn (".cpload not in noreorder section");
7229 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7230 ex
.X_op_symbol
= NULL
;
7231 ex
.X_add_number
= 0;
7233 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7234 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7236 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7237 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7238 (int) BFD_RELOC_LO16
);
7240 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7241 GP
, GP
, tc_get_register (0));
7243 demand_empty_rest_of_line ();
7246 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7247 offset from $sp. The offset is remembered, and after making a PIC
7248 call $gp is restored from that location. */
7251 s_cprestore (ignore
)
7257 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7258 if (mips_pic
!= SVR4_PIC
)
7264 mips_cprestore_offset
= get_absolute_expression ();
7266 ex
.X_op
= O_constant
;
7267 ex
.X_add_symbol
= NULL
;
7268 ex
.X_op_symbol
= NULL
;
7269 ex
.X_add_number
= mips_cprestore_offset
;
7271 macro_build ((char *) NULL
, &icnt
, &ex
,
7272 mips_isa
< 3 ? "sw" : "sd",
7273 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7275 demand_empty_rest_of_line ();
7278 /* Handle the .gpword pseudo-op. This is used when generating PIC
7279 code. It generates a 32 bit GP relative reloc. */
7289 /* When not generating PIC code, this is treated as .word. */
7290 if (mips_pic
!= SVR4_PIC
)
7297 mips_emit_delays ();
7299 mips_align (2, 0, label
);
7304 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7306 as_bad ("Unsupported use of .gpword");
7307 ignore_rest_of_line ();
7311 md_number_to_chars (p
, (valueT
) 0, 4);
7312 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7313 BFD_RELOC_MIPS_GPREL32
);
7315 demand_empty_rest_of_line ();
7318 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7319 tables in SVR4 PIC code. */
7328 /* This is ignored when not generating SVR4 PIC code. */
7329 if (mips_pic
!= SVR4_PIC
)
7335 /* Add $gp to the register named as an argument. */
7336 reg
= tc_get_register (0);
7337 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7338 mips_isa
< 3 ? "addu" : "daddu",
7339 "d,v,t", reg
, reg
, GP
);
7341 demand_empty_rest_of_line ();
7344 /* Parse a register string into a number. Called from the ECOFF code
7345 to parse .frame. The argument is non-zero if this is the frame
7346 register, so that we can record it in mips_frame_reg. */
7349 tc_get_register (frame
)
7355 if (*input_line_pointer
++ != '$')
7357 as_warn ("expected `$'");
7360 else if (isdigit ((unsigned char) *input_line_pointer
))
7362 reg
= get_absolute_expression ();
7363 if (reg
< 0 || reg
>= 32)
7365 as_warn ("Bad register number");
7371 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7373 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7375 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7377 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7381 as_warn ("Unrecognized register name");
7384 input_line_pointer
+= 2;
7387 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7392 md_section_align (seg
, addr
)
7396 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7399 /* We don't need to align ELF sections to the full alignment.
7400 However, Irix 5 may prefer that we align them at least to a 16
7406 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7409 /* Utility routine, called from above as well. If called while the
7410 input file is still being read, it's only an approximation. (For
7411 example, a symbol may later become defined which appeared to be
7412 undefined earlier.) */
7415 nopic_need_relax (sym
)
7421 if (USE_GLOBAL_POINTER_OPT
)
7423 const char *symname
;
7426 /* Find out whether this symbol can be referenced off the GP
7427 register. It can be if it is smaller than the -G size or if
7428 it is in the .sdata or .sbss section. Certain symbols can
7429 not be referenced off the GP, although it appears as though
7431 symname
= S_GET_NAME (sym
);
7432 if (symname
!= (const char *) NULL
7433 && (strcmp (symname
, "eprol") == 0
7434 || strcmp (symname
, "etext") == 0
7435 || strcmp (symname
, "_gp") == 0
7436 || strcmp (symname
, "edata") == 0
7437 || strcmp (symname
, "_fbss") == 0
7438 || strcmp (symname
, "_fdata") == 0
7439 || strcmp (symname
, "_ftext") == 0
7440 || strcmp (symname
, "end") == 0
7441 || strcmp (symname
, "_gp_disp") == 0))
7443 else if (! S_IS_DEFINED (sym
)
7445 #ifndef NO_ECOFF_DEBUGGING
7446 || (sym
->ecoff_extern_size
!= 0
7447 && sym
->ecoff_extern_size
<= g_switch_value
)
7449 || (S_GET_VALUE (sym
) != 0
7450 && S_GET_VALUE (sym
) <= g_switch_value
)))
7454 const char *segname
;
7456 segname
= segment_name (S_GET_SEGMENT (sym
));
7457 assert (strcmp (segname
, ".lit8") != 0
7458 && strcmp (segname
, ".lit4") != 0);
7459 change
= (strcmp (segname
, ".sdata") != 0
7460 && strcmp (segname
, ".sbss") != 0);
7465 /* We are not optimizing for the GP register. */
7469 /* Estimate the size of a frag before relaxing. We are not really
7470 relaxing here, and the final size is encoded in the subtype
7475 md_estimate_size_before_relax (fragp
, segtype
)
7481 if (mips_pic
== NO_PIC
)
7483 change
= nopic_need_relax (fragp
->fr_symbol
);
7485 else if (mips_pic
== SVR4_PIC
)
7487 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7489 /* This must duplicate the test in adjust_reloc_syms. */
7490 change
= (symsec
!= &bfd_und_section
7491 && symsec
!= &bfd_abs_section
7492 && ! bfd_is_com_section (symsec
));
7499 /* Record the offset to the first reloc in the fr_opcode field.
7500 This lets md_convert_frag and tc_gen_reloc know that the code
7501 must be expanded. */
7502 fragp
->fr_opcode
= (fragp
->fr_literal
7504 - RELAX_OLD (fragp
->fr_subtype
)
7505 + RELAX_RELOC1 (fragp
->fr_subtype
));
7506 /* FIXME: This really needs as_warn_where. */
7507 if (RELAX_WARN (fragp
->fr_subtype
))
7508 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7514 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7517 /* Translate internal representation of relocation info to BFD target
7521 tc_gen_reloc (section
, fixp
)
7525 static arelent
*retval
[4];
7527 bfd_reloc_code_real_type code
;
7529 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7532 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7533 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7535 if (mips_pic
== EMBEDDED_PIC
7536 && SWITCH_TABLE (fixp
))
7538 /* For a switch table entry we use a special reloc. The addend
7539 is actually the difference between the reloc address and the
7541 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7542 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7543 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7544 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7546 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7548 /* We use a special addend for an internal RELLO reloc. */
7549 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7550 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7552 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7554 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7556 assert (fixp
->fx_next
!= NULL
7557 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7558 /* We use a special addend for an internal RELHI reloc. The
7559 reloc is relative to the RELLO; adjust the addend
7561 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7562 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7563 + fixp
->fx_next
->fx_where
7564 - S_GET_VALUE (fixp
->fx_subsy
));
7566 reloc
->addend
= (fixp
->fx_addnumber
7567 + fixp
->fx_next
->fx_frag
->fr_address
7568 + fixp
->fx_next
->fx_where
);
7570 else if (fixp
->fx_pcrel
== 0)
7571 reloc
->addend
= fixp
->fx_addnumber
;
7574 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7575 /* A gruesome hack which is a result of the gruesome gas reloc
7577 reloc
->addend
= reloc
->address
;
7579 reloc
->addend
= -reloc
->address
;
7582 /* If this is a variant frag, we may need to adjust the existing
7583 reloc and generate a new one. */
7584 if (fixp
->fx_frag
->fr_opcode
!= NULL
7585 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7586 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7587 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7588 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7589 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7590 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7591 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7595 /* If this is not the last reloc in this frag, then we have two
7596 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7597 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7598 the second one handle all of them. */
7599 if (fixp
->fx_next
!= NULL
7600 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7602 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7603 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7604 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7605 && (fixp
->fx_next
->fx_r_type
7606 == BFD_RELOC_MIPS_GOT_LO16
))
7607 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7608 && (fixp
->fx_next
->fx_r_type
7609 == BFD_RELOC_MIPS_CALL_LO16
)));
7614 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7615 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7616 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7618 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7619 reloc2
->address
= (reloc
->address
7620 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7621 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7622 reloc2
->addend
= fixp
->fx_addnumber
;
7623 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7624 assert (reloc2
->howto
!= NULL
);
7626 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7630 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7633 reloc3
->address
+= 4;
7636 if (mips_pic
== NO_PIC
)
7638 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7639 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7641 else if (mips_pic
== SVR4_PIC
)
7643 switch (fixp
->fx_r_type
)
7647 case BFD_RELOC_MIPS_GOT16
:
7649 case BFD_RELOC_MIPS_CALL16
:
7650 case BFD_RELOC_MIPS_GOT_LO16
:
7651 case BFD_RELOC_MIPS_CALL_LO16
:
7652 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7660 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
7661 fixup_segment converted a non-PC relative reloc into a PC
7662 relative reloc. In such a case, we need to convert the reloc
7664 code
= fixp
->fx_r_type
;
7670 code
= BFD_RELOC_8_PCREL
;
7673 code
= BFD_RELOC_16_PCREL
;
7676 code
= BFD_RELOC_32_PCREL
;
7678 case BFD_RELOC_8_PCREL
:
7679 case BFD_RELOC_16_PCREL
:
7680 case BFD_RELOC_32_PCREL
:
7681 case BFD_RELOC_16_PCREL_S2
:
7682 case BFD_RELOC_PCREL_HI16_S
:
7683 case BFD_RELOC_PCREL_LO16
:
7686 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7687 "Cannot make %s relocation PC relative",
7688 bfd_get_reloc_code_name (code
));
7692 /* To support a PC relative reloc when generating embedded PIC code
7693 for ECOFF, we use a Cygnus extension. We check for that here to
7694 make sure that we don't let such a reloc escape normally. */
7695 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7696 && code
== BFD_RELOC_16_PCREL_S2
7697 && mips_pic
!= EMBEDDED_PIC
)
7698 reloc
->howto
= NULL
;
7700 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7702 if (reloc
->howto
== NULL
)
7704 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7705 "Can not represent %s relocation in this object file format",
7706 bfd_get_reloc_code_name (code
));
7713 /* Convert a machine dependent frag. */
7716 md_convert_frag (abfd
, asec
, fragp
)
7724 if (fragp
->fr_opcode
== NULL
)
7727 old
= RELAX_OLD (fragp
->fr_subtype
);
7728 new = RELAX_NEW (fragp
->fr_subtype
);
7729 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7732 memcpy (fixptr
- old
, fixptr
, new);
7734 fragp
->fr_fix
+= new - old
;
7737 /* This function is called whenever a label is defined. It is used
7738 when handling branch delays; if a branch has a label, we assume we
7742 mips_define_label (sym
)
7748 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7749 In order to work with gcc when using mips-tfile, we must keep all
7750 local labels. However, in other cases, we want to discard them,
7751 since they are useless. */
7754 mips_local_label (name
)
7757 #ifndef NO_ECOFF_DEBUGGING
7760 && ! ecoff_debugging_seen
)
7762 /* We were called with -g, but we didn't see any debugging
7763 information. That may mean that gcc is smuggling debugging
7764 information through to mips-tfile, in which case we must
7765 generate all local labels. */
7770 /* Here it's OK to discard local labels. */
7772 return name
[0] == '$';
7775 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7777 /* Some special processing for a MIPS ELF file. */
7780 mips_elf_final_processing ()
7782 /* Write out the register information. */
7787 s
.ri_gprmask
= mips_gprmask
;
7788 s
.ri_cprmask
[0] = mips_cprmask
[0];
7789 s
.ri_cprmask
[1] = mips_cprmask
[1];
7790 s
.ri_cprmask
[2] = mips_cprmask
[2];
7791 s
.ri_cprmask
[3] = mips_cprmask
[3];
7792 /* The gp_value field is set by the MIPS ELF backend. */
7794 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7795 ((Elf32_External_RegInfo
*)
7796 mips_regmask_frag
));
7800 Elf64_Internal_RegInfo s
;
7802 s
.ri_gprmask
= mips_gprmask
;
7804 s
.ri_cprmask
[0] = mips_cprmask
[0];
7805 s
.ri_cprmask
[1] = mips_cprmask
[1];
7806 s
.ri_cprmask
[2] = mips_cprmask
[2];
7807 s
.ri_cprmask
[3] = mips_cprmask
[3];
7808 /* The gp_value field is set by the MIPS ELF backend. */
7810 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
7811 ((Elf64_External_RegInfo
*)
7812 mips_regmask_frag
));
7815 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7816 sort of BFD interface for this. */
7817 if (mips_any_noreorder
)
7818 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7819 if (mips_pic
!= NO_PIC
)
7820 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7823 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7825 /* These functions should really be defined by the object file format,
7826 since they are related to debugging information. However, this
7827 code has to work for the a.out format, which does not define them,
7828 so we provide simple versions here. These don't actually generate
7829 any debugging information, but they do simple checking and someday
7830 somebody may make them useful. */
7834 struct loc
*loc_next
;
7835 unsigned long loc_fileno
;
7836 unsigned long loc_lineno
;
7837 unsigned long loc_offset
;
7838 unsigned short loc_delta
;
7839 unsigned short loc_count
;
7848 struct proc
*proc_next
;
7849 struct symbol
*proc_isym
;
7850 struct symbol
*proc_end
;
7851 unsigned long proc_reg_mask
;
7852 unsigned long proc_reg_offset
;
7853 unsigned long proc_fpreg_mask
;
7854 unsigned long proc_fpreg_offset
;
7855 unsigned long proc_frameoffset
;
7856 unsigned long proc_framereg
;
7857 unsigned long proc_pcreg
;
7859 struct file
*proc_file
;
7866 struct file
*file_next
;
7867 unsigned long file_fileno
;
7868 struct symbol
*file_symbol
;
7869 struct symbol
*file_end
;
7870 struct proc
*file_proc
;
7875 static struct obstack proc_frags
;
7876 static procS
*proc_lastP
;
7877 static procS
*proc_rootP
;
7878 static int numprocs
;
7883 obstack_begin (&proc_frags
, 0x2000);
7889 /* check for premature end, nesting errors, etc */
7890 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7891 as_warn ("missing `.end' at end of assembly");
7900 if (*input_line_pointer
== '-')
7902 ++input_line_pointer
;
7905 if (!isdigit (*input_line_pointer
))
7906 as_bad ("Expected simple number.");
7907 if (input_line_pointer
[0] == '0')
7909 if (input_line_pointer
[1] == 'x')
7911 input_line_pointer
+= 2;
7912 while (isxdigit (*input_line_pointer
))
7915 val
|= hex_value (*input_line_pointer
++);
7917 return negative
? -val
: val
;
7921 ++input_line_pointer
;
7922 while (isdigit (*input_line_pointer
))
7925 val
|= *input_line_pointer
++ - '0';
7927 return negative
? -val
: val
;
7930 if (!isdigit (*input_line_pointer
))
7932 printf (" *input_line_pointer == '%c' 0x%02x\n",
7933 *input_line_pointer
, *input_line_pointer
);
7934 as_warn ("Invalid number");
7937 while (isdigit (*input_line_pointer
))
7940 val
+= *input_line_pointer
++ - '0';
7942 return negative
? -val
: val
;
7945 /* The .file directive; just like the usual .file directive, but there
7946 is an initial number which is the ECOFF file index. */
7954 line
= get_number ();
7959 /* The .end directive. */
7967 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7970 demand_empty_rest_of_line ();
7974 if (now_seg
!= text_section
)
7975 as_warn (".end not in text section");
7978 as_warn (".end and no .ent seen yet.");
7984 assert (S_GET_NAME (p
));
7985 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7986 as_warn (".end symbol does not match .ent symbol.");
7989 proc_lastP
->proc_end
= (symbolS
*) 1;
7992 /* The .aent and .ent directives. */
8002 symbolP
= get_symbol ();
8003 if (*input_line_pointer
== ',')
8004 input_line_pointer
++;
8006 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
8007 number
= get_number ();
8008 if (now_seg
!= text_section
)
8009 as_warn (".ent or .aent not in text section.");
8011 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8012 as_warn ("missing `.end'");
8016 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
8017 procP
->proc_isym
= symbolP
;
8018 procP
->proc_reg_mask
= 0;
8019 procP
->proc_reg_offset
= 0;
8020 procP
->proc_fpreg_mask
= 0;
8021 procP
->proc_fpreg_offset
= 0;
8022 procP
->proc_frameoffset
= 0;
8023 procP
->proc_framereg
= 0;
8024 procP
->proc_pcreg
= 0;
8025 procP
->proc_end
= NULL
;
8026 procP
->proc_next
= NULL
;
8028 proc_lastP
->proc_next
= procP
;
8034 demand_empty_rest_of_line ();
8037 /* The .frame directive. */
8050 frame_reg
= tc_get_register (1);
8051 if (*input_line_pointer
== ',')
8052 input_line_pointer
++;
8053 frame_off
= get_absolute_expression ();
8054 if (*input_line_pointer
== ',')
8055 input_line_pointer
++;
8056 pcreg
= tc_get_register (0);
8059 assert (proc_rootP
);
8060 proc_rootP
->proc_framereg
= frame_reg
;
8061 proc_rootP
->proc_frameoffset
= frame_off
;
8062 proc_rootP
->proc_pcreg
= pcreg
;
8063 /* bob macho .frame */
8065 /* We don't have to write out a frame stab for unoptimized code. */
8066 if (!(frame_reg
== FP
&& frame_off
== 0))
8069 as_warn ("No .ent for .frame to use.");
8070 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
8071 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
8072 S_SET_TYPE (symP
, N_RMASK
);
8073 S_SET_OTHER (symP
, 0);
8074 S_SET_DESC (symP
, 0);
8075 symP
->sy_forward
= proc_lastP
->proc_isym
;
8076 /* bob perhaps I should have used pseudo set */
8078 demand_empty_rest_of_line ();
8082 /* The .fmask and .mask directives. */
8089 char str
[100], *strP
;
8095 mask
= get_number ();
8096 if (*input_line_pointer
== ',')
8097 input_line_pointer
++;
8098 off
= get_absolute_expression ();
8100 /* bob only for coff */
8101 assert (proc_rootP
);
8102 if (reg_type
== 'F')
8104 proc_rootP
->proc_fpreg_mask
= mask
;
8105 proc_rootP
->proc_fpreg_offset
= off
;
8109 proc_rootP
->proc_reg_mask
= mask
;
8110 proc_rootP
->proc_reg_offset
= off
;
8113 /* bob macho .mask + .fmask */
8115 /* We don't have to write out a mask stab if no saved regs. */
8119 as_warn ("No .ent for .mask to use.");
8121 for (i
= 0; i
< 32; i
++)
8125 sprintf (strP
, "%c%d,", reg_type
, i
);
8126 strP
+= strlen (strP
);
8130 sprintf (strP
, ";%d,", off
);
8131 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
8132 S_SET_TYPE (symP
, N_RMASK
);
8133 S_SET_OTHER (symP
, 0);
8134 S_SET_DESC (symP
, 0);
8135 symP
->sy_forward
= proc_lastP
->proc_isym
;
8136 /* bob perhaps I should have used pseudo set */
8141 /* The .loc directive. */
8152 assert (now_seg
== text_section
);
8154 lineno
= get_number ();
8155 addroff
= frag_now_fix ();
8157 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8158 S_SET_TYPE (symbolP
, N_SLINE
);
8159 S_SET_OTHER (symbolP
, 0);
8160 S_SET_DESC (symbolP
, lineno
);
8161 symbolP
->sy_segment
= now_seg
;