1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa
;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, pic, sym32, nomacro, \
1138 | ((pic) ? 0x100 : 0) \
1139 | ((sym32) ? 0x200 : 0) \
1140 | ((nomacro) ? 0x400 : 0) \
1141 | ((small) ? 0x800 : 0) \
1142 | ((ext) ? 0x1000 : 0) \
1143 | ((dslot) ? 0x2000 : 0) \
1144 | ((jal_dslot) ? 0x4000 : 0))
1146 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1147 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1148 #define RELAX_MIPS16_PIC(i) (((i) & 0x100) != 0)
1149 #define RELAX_MIPS16_SYM32(i) (((i) & 0x200) != 0)
1150 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x400) != 0)
1151 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x800) != 0)
1152 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x1000) != 0)
1153 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x2000) != 0)
1154 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x8000) != 0)
1157 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x8000)
1158 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x8000)
1159 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x10000) != 0)
1160 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x10000)
1161 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x10000)
1162 #define RELAX_MIPS16_MACRO(i) (((i) & 0x20000) != 0)
1163 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x20000)
1164 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x20000)
1166 /* For microMIPS code, we use relaxation similar to one we use for
1167 MIPS16 code. Some instructions that take immediate values support
1168 two encodings: a small one which takes some small value, and a
1169 larger one which takes a 16 bit value. As some branches also follow
1170 this pattern, relaxing these values is required.
1172 We can assemble both microMIPS and normal MIPS code in a single
1173 object. Therefore, we need to support this type of relaxation at
1174 the same time that we support the relaxation described above. We
1175 use one of the high bits of the subtype field to distinguish these
1178 The information we store for this type of relaxation is the argument
1179 code found in the opcode file for this relocation, the register
1180 selected as the assembler temporary, whether in the 32-bit
1181 instruction mode, whether the branch is unconditional, whether it is
1182 compact, whether there is no delay-slot instruction available to fill
1183 in, whether it stores the link address implicitly in $ra, whether
1184 relaxation of out-of-range 32-bit branches to a sequence of
1185 instructions is enabled, and whether the displacement of a branch is
1186 too large to fit as an immediate argument of a 16-bit and a 32-bit
1187 branch, respectively. */
1188 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1189 uncond, compact, link, nods, \
1190 relax32, toofar16, toofar32) \
1193 | (((at) & 0x1f) << 8) \
1194 | ((insn32) ? 0x2000 : 0) \
1195 | ((pic) ? 0x4000 : 0) \
1196 | ((uncond) ? 0x8000 : 0) \
1197 | ((compact) ? 0x10000 : 0) \
1198 | ((link) ? 0x20000 : 0) \
1199 | ((nods) ? 0x40000 : 0) \
1200 | ((relax32) ? 0x80000 : 0) \
1201 | ((toofar16) ? 0x100000 : 0) \
1202 | ((toofar32) ? 0x200000 : 0))
1203 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1204 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1205 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1206 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1207 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1208 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1209 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1210 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1211 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1212 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1214 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1215 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1216 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1217 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1218 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1219 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1221 /* Sign-extend 16-bit value X. */
1222 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1224 /* Is the given value a sign-extended 32-bit value? */
1225 #define IS_SEXT_32BIT_NUM(x) \
1226 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1227 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1229 /* Is the given value a sign-extended 16-bit value? */
1230 #define IS_SEXT_16BIT_NUM(x) \
1231 (((x) &~ (offsetT) 0x7fff) == 0 \
1232 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1234 /* Is the given value a sign-extended 12-bit value? */
1235 #define IS_SEXT_12BIT_NUM(x) \
1236 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1238 /* Is the given value a sign-extended 9-bit value? */
1239 #define IS_SEXT_9BIT_NUM(x) \
1240 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1242 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1243 #define IS_ZEXT_32BIT_NUM(x) \
1244 (((x) &~ (offsetT) 0xffffffff) == 0 \
1245 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1247 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1249 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1250 (((STRUCT) >> (SHIFT)) & (MASK))
1252 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1253 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1255 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1256 : EXTRACT_BITS ((INSN).insn_opcode, \
1257 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1258 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1259 EXTRACT_BITS ((INSN).insn_opcode, \
1260 MIPS16OP_MASK_##FIELD, \
1261 MIPS16OP_SH_##FIELD)
1263 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1264 #define MIPS16_EXTEND (0xf000U << 16)
1266 /* Whether or not we are emitting a branch-likely macro. */
1267 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1269 /* Global variables used when generating relaxable macros. See the
1270 comment above RELAX_ENCODE for more details about how relaxation
1273 /* 0 if we're not emitting a relaxable macro.
1274 1 if we're emitting the first of the two relaxation alternatives.
1275 2 if we're emitting the second alternative. */
1278 /* The first relaxable fixup in the current frag. (In other words,
1279 the first fixup that refers to relaxable code.) */
1282 /* sizes[0] says how many bytes of the first alternative are stored in
1283 the current frag. Likewise sizes[1] for the second alternative. */
1284 unsigned int sizes
[2];
1286 /* The symbol on which the choice of sequence depends. */
1290 /* Global variables used to decide whether a macro needs a warning. */
1292 /* True if the macro is in a branch delay slot. */
1293 bfd_boolean delay_slot_p
;
1295 /* Set to the length in bytes required if the macro is in a delay slot
1296 that requires a specific length of instruction, otherwise zero. */
1297 unsigned int delay_slot_length
;
1299 /* For relaxable macros, sizes[0] is the length of the first alternative
1300 in bytes and sizes[1] is the length of the second alternative.
1301 For non-relaxable macros, both elements give the length of the
1303 unsigned int sizes
[2];
1305 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1306 instruction of the first alternative in bytes and first_insn_sizes[1]
1307 is the length of the first instruction of the second alternative.
1308 For non-relaxable macros, both elements give the length of the first
1309 instruction in bytes.
1311 Set to zero if we haven't yet seen the first instruction. */
1312 unsigned int first_insn_sizes
[2];
1314 /* For relaxable macros, insns[0] is the number of instructions for the
1315 first alternative and insns[1] is the number of instructions for the
1318 For non-relaxable macros, both elements give the number of
1319 instructions for the macro. */
1320 unsigned int insns
[2];
1322 /* The first variant frag for this macro. */
1324 } mips_macro_warning
;
1326 /* Prototypes for static functions. */
1328 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1330 static void append_insn
1331 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1332 bfd_boolean expansionp
);
1333 static void mips_no_prev_insn (void);
1334 static void macro_build (expressionS
*, const char *, const char *, ...);
1335 static void mips16_macro_build
1336 (expressionS
*, const char *, const char *, va_list *);
1337 static void load_register (int, expressionS
*, int);
1338 static void macro_start (void);
1339 static void macro_end (void);
1340 static void macro (struct mips_cl_insn
*ip
, char *str
);
1341 static void mips16_macro (struct mips_cl_insn
* ip
);
1342 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1343 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1344 static void mips16_immed
1345 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1346 unsigned int, unsigned long *);
1347 static size_t my_getSmallExpression
1348 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1349 static void my_getExpression (expressionS
*, char *);
1350 static void s_align (int);
1351 static void s_change_sec (int);
1352 static void s_change_section (int);
1353 static void s_cons (int);
1354 static void s_float_cons (int);
1355 static void s_mips_globl (int);
1356 static void s_option (int);
1357 static void s_mipsset (int);
1358 static void s_abicalls (int);
1359 static void s_cpload (int);
1360 static void s_cpsetup (int);
1361 static void s_cplocal (int);
1362 static void s_cprestore (int);
1363 static void s_cpreturn (int);
1364 static void s_dtprelword (int);
1365 static void s_dtpreldword (int);
1366 static void s_tprelword (int);
1367 static void s_tpreldword (int);
1368 static void s_gpvalue (int);
1369 static void s_gpword (int);
1370 static void s_gpdword (int);
1371 static void s_ehword (int);
1372 static void s_cpadd (int);
1373 static void s_insn (int);
1374 static void s_nan (int);
1375 static void s_module (int);
1376 static void s_mips_ent (int);
1377 static void s_mips_end (int);
1378 static void s_mips_frame (int);
1379 static void s_mips_mask (int reg_type
);
1380 static void s_mips_stab (int);
1381 static void s_mips_weakext (int);
1382 static void s_mips_file (int);
1383 static void s_mips_loc (int);
1384 static bfd_boolean
pic_need_relax (symbolS
*);
1385 static int relaxed_branch_length (fragS
*, asection
*, int);
1386 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1387 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1388 static void file_mips_check_options (void);
1390 /* Table and functions used to map between CPU/ISA names, and
1391 ISA levels, and CPU numbers. */
1393 struct mips_cpu_info
1395 const char *name
; /* CPU or ISA name. */
1396 int flags
; /* MIPS_CPU_* flags. */
1397 int ase
; /* Set of ASEs implemented by the CPU. */
1398 int isa
; /* ISA level. */
1399 int cpu
; /* CPU number (default CPU if ISA). */
1402 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1404 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1405 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1406 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1408 /* Command-line options. */
1409 const char *md_shortopts
= "O::g::G:";
1413 OPTION_MARCH
= OPTION_MD_BASE
,
1445 OPTION_NO_SMARTMIPS
,
1455 OPTION_NO_MICROMIPS
,
1458 OPTION_COMPAT_ARCH_BASE
,
1467 OPTION_M7000_HILO_FIX
,
1468 OPTION_MNO_7000_HILO_FIX
,
1472 OPTION_NO_FIX_RM7000
,
1473 OPTION_FIX_LOONGSON2F_JUMP
,
1474 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1475 OPTION_FIX_LOONGSON2F_NOP
,
1476 OPTION_NO_FIX_LOONGSON2F_NOP
,
1478 OPTION_NO_FIX_VR4120
,
1480 OPTION_NO_FIX_VR4130
,
1481 OPTION_FIX_CN63XXP1
,
1482 OPTION_NO_FIX_CN63XXP1
,
1489 OPTION_CONSTRUCT_FLOATS
,
1490 OPTION_NO_CONSTRUCT_FLOATS
,
1494 OPTION_RELAX_BRANCH
,
1495 OPTION_NO_RELAX_BRANCH
,
1496 OPTION_IGNORE_BRANCH_ISA
,
1497 OPTION_NO_IGNORE_BRANCH_ISA
,
1506 OPTION_SINGLE_FLOAT
,
1507 OPTION_DOUBLE_FLOAT
,
1520 OPTION_MVXWORKS_PIC
,
1523 OPTION_NO_ODD_SPREG
,
1527 struct option md_longopts
[] =
1529 /* Options which specify architecture. */
1530 {"march", required_argument
, NULL
, OPTION_MARCH
},
1531 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1532 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1533 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1534 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1535 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1536 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1537 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1538 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1539 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1540 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1541 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1542 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1543 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1544 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1545 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1546 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1547 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1549 /* Options which specify Application Specific Extensions (ASEs). */
1550 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1551 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1552 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1553 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1554 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1555 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1556 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1557 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1558 {"mmt", no_argument
, NULL
, OPTION_MT
},
1559 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1560 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1561 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1562 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1563 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1564 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1565 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1566 {"meva", no_argument
, NULL
, OPTION_EVA
},
1567 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1568 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1569 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1570 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1571 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1572 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1573 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1574 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1575 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1576 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1577 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1579 /* Old-style architecture options. Don't add more of these. */
1580 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1581 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1582 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1583 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1584 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1585 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1586 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1587 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1589 /* Options which enable bug fixes. */
1590 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1591 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1592 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1593 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1594 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1595 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1596 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1597 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1598 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1599 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1600 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1601 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1602 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1603 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1604 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1605 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1606 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1608 /* Miscellaneous options. */
1609 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1610 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1611 {"break", no_argument
, NULL
, OPTION_BREAK
},
1612 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1613 {"EB", no_argument
, NULL
, OPTION_EB
},
1614 {"EL", no_argument
, NULL
, OPTION_EL
},
1615 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1616 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1617 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1618 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1619 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1620 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1621 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1622 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1623 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1624 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1625 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1626 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1627 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1628 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1629 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1630 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1631 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1632 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1633 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1634 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1635 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1636 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1637 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1639 /* Strictly speaking this next option is ELF specific,
1640 but we allow it for other ports as well in order to
1641 make testing easier. */
1642 {"32", no_argument
, NULL
, OPTION_32
},
1644 /* ELF-specific options. */
1645 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1646 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1647 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1648 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1649 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1650 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1651 {"n32", no_argument
, NULL
, OPTION_N32
},
1652 {"64", no_argument
, NULL
, OPTION_64
},
1653 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1654 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1655 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1656 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1657 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1658 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1660 {NULL
, no_argument
, NULL
, 0}
1662 size_t md_longopts_size
= sizeof (md_longopts
);
1664 /* Information about either an Application Specific Extension or an
1665 optional architecture feature that, for simplicity, we treat in the
1666 same way as an ASE. */
1669 /* The name of the ASE, used in both the command-line and .set options. */
1672 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1673 and 64-bit architectures, the flags here refer to the subset that
1674 is available on both. */
1677 /* The ASE_* flag used for instructions that are available on 64-bit
1678 architectures but that are not included in FLAGS. */
1679 unsigned int flags64
;
1681 /* The command-line options that turn the ASE on and off. */
1685 /* The minimum required architecture revisions for MIPS32, MIPS64,
1686 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1689 int micromips32_rev
;
1690 int micromips64_rev
;
1692 /* The architecture where the ASE was removed or -1 if the extension has not
1697 /* A table of all supported ASEs. */
1698 static const struct mips_ase mips_ases
[] = {
1699 { "dsp", ASE_DSP
, ASE_DSP64
,
1700 OPTION_DSP
, OPTION_NO_DSP
,
1704 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1705 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1709 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1710 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1714 { "eva", ASE_EVA
, 0,
1715 OPTION_EVA
, OPTION_NO_EVA
,
1719 { "mcu", ASE_MCU
, 0,
1720 OPTION_MCU
, OPTION_NO_MCU
,
1724 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1725 { "mdmx", ASE_MDMX
, 0,
1726 OPTION_MDMX
, OPTION_NO_MDMX
,
1730 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1731 { "mips3d", ASE_MIPS3D
, 0,
1732 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1737 OPTION_MT
, OPTION_NO_MT
,
1741 { "smartmips", ASE_SMARTMIPS
, 0,
1742 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1746 { "virt", ASE_VIRT
, ASE_VIRT64
,
1747 OPTION_VIRT
, OPTION_NO_VIRT
,
1751 { "msa", ASE_MSA
, ASE_MSA64
,
1752 OPTION_MSA
, OPTION_NO_MSA
,
1756 { "xpa", ASE_XPA
, 0,
1757 OPTION_XPA
, OPTION_NO_XPA
,
1762 /* The set of ASEs that require -mfp64. */
1763 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1765 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1766 static const unsigned int mips_ase_groups
[] = {
1767 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
1772 The following pseudo-ops from the Kane and Heinrich MIPS book
1773 should be defined here, but are currently unsupported: .alias,
1774 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1776 The following pseudo-ops from the Kane and Heinrich MIPS book are
1777 specific to the type of debugging information being generated, and
1778 should be defined by the object format: .aent, .begin, .bend,
1779 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1782 The following pseudo-ops from the Kane and Heinrich MIPS book are
1783 not MIPS CPU specific, but are also not specific to the object file
1784 format. This file is probably the best place to define them, but
1785 they are not currently supported: .asm0, .endr, .lab, .struct. */
1787 static const pseudo_typeS mips_pseudo_table
[] =
1789 /* MIPS specific pseudo-ops. */
1790 {"option", s_option
, 0},
1791 {"set", s_mipsset
, 0},
1792 {"rdata", s_change_sec
, 'r'},
1793 {"sdata", s_change_sec
, 's'},
1794 {"livereg", s_ignore
, 0},
1795 {"abicalls", s_abicalls
, 0},
1796 {"cpload", s_cpload
, 0},
1797 {"cpsetup", s_cpsetup
, 0},
1798 {"cplocal", s_cplocal
, 0},
1799 {"cprestore", s_cprestore
, 0},
1800 {"cpreturn", s_cpreturn
, 0},
1801 {"dtprelword", s_dtprelword
, 0},
1802 {"dtpreldword", s_dtpreldword
, 0},
1803 {"tprelword", s_tprelword
, 0},
1804 {"tpreldword", s_tpreldword
, 0},
1805 {"gpvalue", s_gpvalue
, 0},
1806 {"gpword", s_gpword
, 0},
1807 {"gpdword", s_gpdword
, 0},
1808 {"ehword", s_ehword
, 0},
1809 {"cpadd", s_cpadd
, 0},
1810 {"insn", s_insn
, 0},
1812 {"module", s_module
, 0},
1814 /* Relatively generic pseudo-ops that happen to be used on MIPS
1816 {"asciiz", stringer
, 8 + 1},
1817 {"bss", s_change_sec
, 'b'},
1819 {"half", s_cons
, 1},
1820 {"dword", s_cons
, 3},
1821 {"weakext", s_mips_weakext
, 0},
1822 {"origin", s_org
, 0},
1823 {"repeat", s_rept
, 0},
1825 /* For MIPS this is non-standard, but we define it for consistency. */
1826 {"sbss", s_change_sec
, 'B'},
1828 /* These pseudo-ops are defined in read.c, but must be overridden
1829 here for one reason or another. */
1830 {"align", s_align
, 0},
1831 {"byte", s_cons
, 0},
1832 {"data", s_change_sec
, 'd'},
1833 {"double", s_float_cons
, 'd'},
1834 {"float", s_float_cons
, 'f'},
1835 {"globl", s_mips_globl
, 0},
1836 {"global", s_mips_globl
, 0},
1837 {"hword", s_cons
, 1},
1839 {"long", s_cons
, 2},
1840 {"octa", s_cons
, 4},
1841 {"quad", s_cons
, 3},
1842 {"section", s_change_section
, 0},
1843 {"short", s_cons
, 1},
1844 {"single", s_float_cons
, 'f'},
1845 {"stabd", s_mips_stab
, 'd'},
1846 {"stabn", s_mips_stab
, 'n'},
1847 {"stabs", s_mips_stab
, 's'},
1848 {"text", s_change_sec
, 't'},
1849 {"word", s_cons
, 2},
1851 { "extern", ecoff_directive_extern
, 0},
1856 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1858 /* These pseudo-ops should be defined by the object file format.
1859 However, a.out doesn't support them, so we have versions here. */
1860 {"aent", s_mips_ent
, 1},
1861 {"bgnb", s_ignore
, 0},
1862 {"end", s_mips_end
, 0},
1863 {"endb", s_ignore
, 0},
1864 {"ent", s_mips_ent
, 0},
1865 {"file", s_mips_file
, 0},
1866 {"fmask", s_mips_mask
, 'F'},
1867 {"frame", s_mips_frame
, 0},
1868 {"loc", s_mips_loc
, 0},
1869 {"mask", s_mips_mask
, 'R'},
1870 {"verstamp", s_ignore
, 0},
1874 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1875 purpose of the `.dc.a' internal pseudo-op. */
1878 mips_address_bytes (void)
1880 file_mips_check_options ();
1881 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1884 extern void pop_insert (const pseudo_typeS
*);
1887 mips_pop_insert (void)
1889 pop_insert (mips_pseudo_table
);
1890 if (! ECOFF_DEBUGGING
)
1891 pop_insert (mips_nonecoff_pseudo_table
);
1894 /* Symbols labelling the current insn. */
1896 struct insn_label_list
1898 struct insn_label_list
*next
;
1902 static struct insn_label_list
*free_insn_labels
;
1903 #define label_list tc_segment_info_data.labels
1905 static void mips_clear_insn_labels (void);
1906 static void mips_mark_labels (void);
1907 static void mips_compressed_mark_labels (void);
1910 mips_clear_insn_labels (void)
1912 struct insn_label_list
**pl
;
1913 segment_info_type
*si
;
1917 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1920 si
= seg_info (now_seg
);
1921 *pl
= si
->label_list
;
1922 si
->label_list
= NULL
;
1926 /* Mark instruction labels in MIPS16/microMIPS mode. */
1929 mips_mark_labels (void)
1931 if (HAVE_CODE_COMPRESSION
)
1932 mips_compressed_mark_labels ();
1935 static char *expr_end
;
1937 /* An expression in a macro instruction. This is set by mips_ip and
1938 mips16_ip and when populated is always an O_constant. */
1940 static expressionS imm_expr
;
1942 /* The relocatable field in an instruction and the relocs associated
1943 with it. These variables are used for instructions like LUI and
1944 JAL as well as true offsets. They are also used for address
1945 operands in macros. */
1947 static expressionS offset_expr
;
1948 static bfd_reloc_code_real_type offset_reloc
[3]
1949 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1951 /* This is set to the resulting size of the instruction to be produced
1952 by mips16_ip if an explicit extension is used or by mips_ip if an
1953 explicit size is supplied. */
1955 static unsigned int forced_insn_length
;
1957 /* True if we are assembling an instruction. All dot symbols defined during
1958 this time should be treated as code labels. */
1960 static bfd_boolean mips_assembling_insn
;
1962 /* The pdr segment for per procedure frame/regmask info. Not used for
1965 static segT pdr_seg
;
1967 /* The default target format to use. */
1969 #if defined (TE_FreeBSD)
1970 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1971 #elif defined (TE_TMIPS)
1972 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1974 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1978 mips_target_format (void)
1980 switch (OUTPUT_FLAVOR
)
1982 case bfd_target_elf_flavour
:
1984 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1985 return (target_big_endian
1986 ? "elf32-bigmips-vxworks"
1987 : "elf32-littlemips-vxworks");
1989 return (target_big_endian
1990 ? (HAVE_64BIT_OBJECTS
1991 ? ELF_TARGET ("elf64-", "big")
1993 ? ELF_TARGET ("elf32-n", "big")
1994 : ELF_TARGET ("elf32-", "big")))
1995 : (HAVE_64BIT_OBJECTS
1996 ? ELF_TARGET ("elf64-", "little")
1998 ? ELF_TARGET ("elf32-n", "little")
1999 : ELF_TARGET ("elf32-", "little"))));
2006 /* Return the ISA revision that is currently in use, or 0 if we are
2007 generating code for MIPS V or below. */
2012 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2015 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2018 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2021 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2024 /* microMIPS implies revision 2 or above. */
2025 if (mips_opts
.micromips
)
2028 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2034 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2037 mips_ase_mask (unsigned int flags
)
2041 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2042 if (flags
& mips_ase_groups
[i
])
2043 flags
|= mips_ase_groups
[i
];
2047 /* Check whether the current ISA supports ASE. Issue a warning if
2051 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2055 static unsigned int warned_isa
;
2056 static unsigned int warned_fp32
;
2058 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2059 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2061 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2062 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2063 && (warned_isa
& ase
->flags
) != ase
->flags
)
2065 warned_isa
|= ase
->flags
;
2066 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2067 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2069 as_warn (_("the %d-bit %s architecture does not support the"
2070 " `%s' extension"), size
, base
, ase
->name
);
2072 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2073 ase
->name
, base
, size
, min_rev
);
2075 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2076 && (warned_isa
& ase
->flags
) != ase
->flags
)
2078 warned_isa
|= ase
->flags
;
2079 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2080 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2081 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2082 ase
->name
, base
, size
, ase
->rem_rev
);
2085 if ((ase
->flags
& FP64_ASES
)
2086 && mips_opts
.fp
!= 64
2087 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2089 warned_fp32
|= ase
->flags
;
2090 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2094 /* Check all enabled ASEs to see whether they are supported by the
2095 chosen architecture. */
2098 mips_check_isa_supports_ases (void)
2100 unsigned int i
, mask
;
2102 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2104 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2105 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2106 mips_check_isa_supports_ase (&mips_ases
[i
]);
2110 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2111 that were affected. */
2114 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2115 bfd_boolean enabled_p
)
2119 mask
= mips_ase_mask (ase
->flags
);
2122 opts
->ase
|= ase
->flags
;
2126 /* Return the ASE called NAME, or null if none. */
2128 static const struct mips_ase
*
2129 mips_lookup_ase (const char *name
)
2133 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2134 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2135 return &mips_ases
[i
];
2139 /* Return the length of a microMIPS instruction in bytes. If bits of
2140 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2141 otherwise it is a 32-bit instruction. */
2143 static inline unsigned int
2144 micromips_insn_length (const struct mips_opcode
*mo
)
2146 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2149 /* Return the length of MIPS16 instruction OPCODE. */
2151 static inline unsigned int
2152 mips16_opcode_length (unsigned long opcode
)
2154 return (opcode
>> 16) == 0 ? 2 : 4;
2157 /* Return the length of instruction INSN. */
2159 static inline unsigned int
2160 insn_length (const struct mips_cl_insn
*insn
)
2162 if (mips_opts
.micromips
)
2163 return micromips_insn_length (insn
->insn_mo
);
2164 else if (mips_opts
.mips16
)
2165 return mips16_opcode_length (insn
->insn_opcode
);
2170 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2173 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2178 insn
->insn_opcode
= mo
->match
;
2181 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2182 insn
->fixp
[i
] = NULL
;
2183 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2184 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2185 insn
->mips16_absolute_jump_p
= 0;
2186 insn
->complete_p
= 0;
2187 insn
->cleared_p
= 0;
2190 /* Get a list of all the operands in INSN. */
2192 static const struct mips_operand_array
*
2193 insn_operands (const struct mips_cl_insn
*insn
)
2195 if (insn
->insn_mo
>= &mips_opcodes
[0]
2196 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2197 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2199 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2200 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2201 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2203 if (insn
->insn_mo
>= µmips_opcodes
[0]
2204 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2205 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2210 /* Get a description of operand OPNO of INSN. */
2212 static const struct mips_operand
*
2213 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2215 const struct mips_operand_array
*operands
;
2217 operands
= insn_operands (insn
);
2218 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2220 return operands
->operand
[opno
];
2223 /* Install UVAL as the value of OPERAND in INSN. */
2226 insn_insert_operand (struct mips_cl_insn
*insn
,
2227 const struct mips_operand
*operand
, unsigned int uval
)
2229 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2232 /* Extract the value of OPERAND from INSN. */
2234 static inline unsigned
2235 insn_extract_operand (const struct mips_cl_insn
*insn
,
2236 const struct mips_operand
*operand
)
2238 return mips_extract_operand (operand
, insn
->insn_opcode
);
2241 /* Record the current MIPS16/microMIPS mode in now_seg. */
2244 mips_record_compressed_mode (void)
2246 segment_info_type
*si
;
2248 si
= seg_info (now_seg
);
2249 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2250 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2251 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2252 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2255 /* Read a standard MIPS instruction from BUF. */
2257 static unsigned long
2258 read_insn (char *buf
)
2260 if (target_big_endian
)
2261 return bfd_getb32 ((bfd_byte
*) buf
);
2263 return bfd_getl32 ((bfd_byte
*) buf
);
2266 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2270 write_insn (char *buf
, unsigned int insn
)
2272 md_number_to_chars (buf
, insn
, 4);
2276 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2277 has length LENGTH. */
2279 static unsigned long
2280 read_compressed_insn (char *buf
, unsigned int length
)
2286 for (i
= 0; i
< length
; i
+= 2)
2289 if (target_big_endian
)
2290 insn
|= bfd_getb16 ((char *) buf
);
2292 insn
|= bfd_getl16 ((char *) buf
);
2298 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2299 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2302 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2306 for (i
= 0; i
< length
; i
+= 2)
2307 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2308 return buf
+ length
;
2311 /* Install INSN at the location specified by its "frag" and "where" fields. */
2314 install_insn (const struct mips_cl_insn
*insn
)
2316 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2317 if (HAVE_CODE_COMPRESSION
)
2318 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2320 write_insn (f
, insn
->insn_opcode
);
2321 mips_record_compressed_mode ();
2324 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2325 and install the opcode in the new location. */
2328 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2333 insn
->where
= where
;
2334 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2335 if (insn
->fixp
[i
] != NULL
)
2337 insn
->fixp
[i
]->fx_frag
= frag
;
2338 insn
->fixp
[i
]->fx_where
= where
;
2340 install_insn (insn
);
2343 /* Add INSN to the end of the output. */
2346 add_fixed_insn (struct mips_cl_insn
*insn
)
2348 char *f
= frag_more (insn_length (insn
));
2349 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2352 /* Start a variant frag and move INSN to the start of the variant part,
2353 marking it as fixed. The other arguments are as for frag_var. */
2356 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2357 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2359 frag_grow (max_chars
);
2360 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2362 frag_var (rs_machine_dependent
, max_chars
, var
,
2363 subtype
, symbol
, offset
, NULL
);
2366 /* Insert N copies of INSN into the history buffer, starting at
2367 position FIRST. Neither FIRST nor N need to be clipped. */
2370 insert_into_history (unsigned int first
, unsigned int n
,
2371 const struct mips_cl_insn
*insn
)
2373 if (mips_relax
.sequence
!= 2)
2377 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2379 history
[i
] = history
[i
- n
];
2385 /* Clear the error in insn_error. */
2388 clear_insn_error (void)
2390 memset (&insn_error
, 0, sizeof (insn_error
));
2393 /* Possibly record error message MSG for the current instruction.
2394 If the error is about a particular argument, ARGNUM is the 1-based
2395 number of that argument, otherwise it is 0. FORMAT is the format
2396 of MSG. Return true if MSG was used, false if the current message
2400 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2405 /* Give priority to errors against specific arguments, and to
2406 the first whole-instruction message. */
2412 /* Keep insn_error if it is against a later argument. */
2413 if (argnum
< insn_error
.min_argnum
)
2416 /* If both errors are against the same argument but are different,
2417 give up on reporting a specific error for this argument.
2418 See the comment about mips_insn_error for details. */
2419 if (argnum
== insn_error
.min_argnum
2421 && strcmp (insn_error
.msg
, msg
) != 0)
2424 insn_error
.min_argnum
+= 1;
2428 insn_error
.min_argnum
= argnum
;
2429 insn_error
.format
= format
;
2430 insn_error
.msg
= msg
;
2434 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2435 as for set_insn_error_format. */
2438 set_insn_error (int argnum
, const char *msg
)
2440 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2443 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2444 as for set_insn_error_format. */
2447 set_insn_error_i (int argnum
, const char *msg
, int i
)
2449 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2453 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2454 are as for set_insn_error_format. */
2457 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2459 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2461 insn_error
.u
.ss
[0] = s1
;
2462 insn_error
.u
.ss
[1] = s2
;
2466 /* Report the error in insn_error, which is against assembly code STR. */
2469 report_insn_error (const char *str
)
2471 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2473 switch (insn_error
.format
)
2480 as_bad (msg
, insn_error
.u
.i
, str
);
2484 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2488 free ((char *) msg
);
2491 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2492 the idea is to make it obvious at a glance that each errata is
2496 init_vr4120_conflicts (void)
2498 #define CONFLICT(FIRST, SECOND) \
2499 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2501 /* Errata 21 - [D]DIV[U] after [D]MACC */
2502 CONFLICT (MACC
, DIV
);
2503 CONFLICT (DMACC
, DIV
);
2505 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2506 CONFLICT (DMULT
, DMULT
);
2507 CONFLICT (DMULT
, DMACC
);
2508 CONFLICT (DMACC
, DMULT
);
2509 CONFLICT (DMACC
, DMACC
);
2511 /* Errata 24 - MT{LO,HI} after [D]MACC */
2512 CONFLICT (MACC
, MTHILO
);
2513 CONFLICT (DMACC
, MTHILO
);
2515 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2516 instruction is executed immediately after a MACC or DMACC
2517 instruction, the result of [either instruction] is incorrect." */
2518 CONFLICT (MACC
, MULT
);
2519 CONFLICT (MACC
, DMULT
);
2520 CONFLICT (DMACC
, MULT
);
2521 CONFLICT (DMACC
, DMULT
);
2523 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2524 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2525 DDIV or DDIVU instruction, the result of the MACC or
2526 DMACC instruction is incorrect.". */
2527 CONFLICT (DMULT
, MACC
);
2528 CONFLICT (DMULT
, DMACC
);
2529 CONFLICT (DIV
, MACC
);
2530 CONFLICT (DIV
, DMACC
);
2540 #define RNUM_MASK 0x00000ff
2541 #define RTYPE_MASK 0x0ffff00
2542 #define RTYPE_NUM 0x0000100
2543 #define RTYPE_FPU 0x0000200
2544 #define RTYPE_FCC 0x0000400
2545 #define RTYPE_VEC 0x0000800
2546 #define RTYPE_GP 0x0001000
2547 #define RTYPE_CP0 0x0002000
2548 #define RTYPE_PC 0x0004000
2549 #define RTYPE_ACC 0x0008000
2550 #define RTYPE_CCC 0x0010000
2551 #define RTYPE_VI 0x0020000
2552 #define RTYPE_VF 0x0040000
2553 #define RTYPE_R5900_I 0x0080000
2554 #define RTYPE_R5900_Q 0x0100000
2555 #define RTYPE_R5900_R 0x0200000
2556 #define RTYPE_R5900_ACC 0x0400000
2557 #define RTYPE_MSA 0x0800000
2558 #define RWARN 0x8000000
2560 #define GENERIC_REGISTER_NUMBERS \
2561 {"$0", RTYPE_NUM | 0}, \
2562 {"$1", RTYPE_NUM | 1}, \
2563 {"$2", RTYPE_NUM | 2}, \
2564 {"$3", RTYPE_NUM | 3}, \
2565 {"$4", RTYPE_NUM | 4}, \
2566 {"$5", RTYPE_NUM | 5}, \
2567 {"$6", RTYPE_NUM | 6}, \
2568 {"$7", RTYPE_NUM | 7}, \
2569 {"$8", RTYPE_NUM | 8}, \
2570 {"$9", RTYPE_NUM | 9}, \
2571 {"$10", RTYPE_NUM | 10}, \
2572 {"$11", RTYPE_NUM | 11}, \
2573 {"$12", RTYPE_NUM | 12}, \
2574 {"$13", RTYPE_NUM | 13}, \
2575 {"$14", RTYPE_NUM | 14}, \
2576 {"$15", RTYPE_NUM | 15}, \
2577 {"$16", RTYPE_NUM | 16}, \
2578 {"$17", RTYPE_NUM | 17}, \
2579 {"$18", RTYPE_NUM | 18}, \
2580 {"$19", RTYPE_NUM | 19}, \
2581 {"$20", RTYPE_NUM | 20}, \
2582 {"$21", RTYPE_NUM | 21}, \
2583 {"$22", RTYPE_NUM | 22}, \
2584 {"$23", RTYPE_NUM | 23}, \
2585 {"$24", RTYPE_NUM | 24}, \
2586 {"$25", RTYPE_NUM | 25}, \
2587 {"$26", RTYPE_NUM | 26}, \
2588 {"$27", RTYPE_NUM | 27}, \
2589 {"$28", RTYPE_NUM | 28}, \
2590 {"$29", RTYPE_NUM | 29}, \
2591 {"$30", RTYPE_NUM | 30}, \
2592 {"$31", RTYPE_NUM | 31}
2594 #define FPU_REGISTER_NAMES \
2595 {"$f0", RTYPE_FPU | 0}, \
2596 {"$f1", RTYPE_FPU | 1}, \
2597 {"$f2", RTYPE_FPU | 2}, \
2598 {"$f3", RTYPE_FPU | 3}, \
2599 {"$f4", RTYPE_FPU | 4}, \
2600 {"$f5", RTYPE_FPU | 5}, \
2601 {"$f6", RTYPE_FPU | 6}, \
2602 {"$f7", RTYPE_FPU | 7}, \
2603 {"$f8", RTYPE_FPU | 8}, \
2604 {"$f9", RTYPE_FPU | 9}, \
2605 {"$f10", RTYPE_FPU | 10}, \
2606 {"$f11", RTYPE_FPU | 11}, \
2607 {"$f12", RTYPE_FPU | 12}, \
2608 {"$f13", RTYPE_FPU | 13}, \
2609 {"$f14", RTYPE_FPU | 14}, \
2610 {"$f15", RTYPE_FPU | 15}, \
2611 {"$f16", RTYPE_FPU | 16}, \
2612 {"$f17", RTYPE_FPU | 17}, \
2613 {"$f18", RTYPE_FPU | 18}, \
2614 {"$f19", RTYPE_FPU | 19}, \
2615 {"$f20", RTYPE_FPU | 20}, \
2616 {"$f21", RTYPE_FPU | 21}, \
2617 {"$f22", RTYPE_FPU | 22}, \
2618 {"$f23", RTYPE_FPU | 23}, \
2619 {"$f24", RTYPE_FPU | 24}, \
2620 {"$f25", RTYPE_FPU | 25}, \
2621 {"$f26", RTYPE_FPU | 26}, \
2622 {"$f27", RTYPE_FPU | 27}, \
2623 {"$f28", RTYPE_FPU | 28}, \
2624 {"$f29", RTYPE_FPU | 29}, \
2625 {"$f30", RTYPE_FPU | 30}, \
2626 {"$f31", RTYPE_FPU | 31}
2628 #define FPU_CONDITION_CODE_NAMES \
2629 {"$fcc0", RTYPE_FCC | 0}, \
2630 {"$fcc1", RTYPE_FCC | 1}, \
2631 {"$fcc2", RTYPE_FCC | 2}, \
2632 {"$fcc3", RTYPE_FCC | 3}, \
2633 {"$fcc4", RTYPE_FCC | 4}, \
2634 {"$fcc5", RTYPE_FCC | 5}, \
2635 {"$fcc6", RTYPE_FCC | 6}, \
2636 {"$fcc7", RTYPE_FCC | 7}
2638 #define COPROC_CONDITION_CODE_NAMES \
2639 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2640 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2641 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2642 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2643 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2644 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2645 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2646 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2648 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2649 {"$a4", RTYPE_GP | 8}, \
2650 {"$a5", RTYPE_GP | 9}, \
2651 {"$a6", RTYPE_GP | 10}, \
2652 {"$a7", RTYPE_GP | 11}, \
2653 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2654 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2655 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2656 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2657 {"$t0", RTYPE_GP | 12}, \
2658 {"$t1", RTYPE_GP | 13}, \
2659 {"$t2", RTYPE_GP | 14}, \
2660 {"$t3", RTYPE_GP | 15}
2662 #define O32_SYMBOLIC_REGISTER_NAMES \
2663 {"$t0", RTYPE_GP | 8}, \
2664 {"$t1", RTYPE_GP | 9}, \
2665 {"$t2", RTYPE_GP | 10}, \
2666 {"$t3", RTYPE_GP | 11}, \
2667 {"$t4", RTYPE_GP | 12}, \
2668 {"$t5", RTYPE_GP | 13}, \
2669 {"$t6", RTYPE_GP | 14}, \
2670 {"$t7", RTYPE_GP | 15}, \
2671 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2672 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2673 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2674 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2676 /* Remaining symbolic register names */
2677 #define SYMBOLIC_REGISTER_NAMES \
2678 {"$zero", RTYPE_GP | 0}, \
2679 {"$at", RTYPE_GP | 1}, \
2680 {"$AT", RTYPE_GP | 1}, \
2681 {"$v0", RTYPE_GP | 2}, \
2682 {"$v1", RTYPE_GP | 3}, \
2683 {"$a0", RTYPE_GP | 4}, \
2684 {"$a1", RTYPE_GP | 5}, \
2685 {"$a2", RTYPE_GP | 6}, \
2686 {"$a3", RTYPE_GP | 7}, \
2687 {"$s0", RTYPE_GP | 16}, \
2688 {"$s1", RTYPE_GP | 17}, \
2689 {"$s2", RTYPE_GP | 18}, \
2690 {"$s3", RTYPE_GP | 19}, \
2691 {"$s4", RTYPE_GP | 20}, \
2692 {"$s5", RTYPE_GP | 21}, \
2693 {"$s6", RTYPE_GP | 22}, \
2694 {"$s7", RTYPE_GP | 23}, \
2695 {"$t8", RTYPE_GP | 24}, \
2696 {"$t9", RTYPE_GP | 25}, \
2697 {"$k0", RTYPE_GP | 26}, \
2698 {"$kt0", RTYPE_GP | 26}, \
2699 {"$k1", RTYPE_GP | 27}, \
2700 {"$kt1", RTYPE_GP | 27}, \
2701 {"$gp", RTYPE_GP | 28}, \
2702 {"$sp", RTYPE_GP | 29}, \
2703 {"$s8", RTYPE_GP | 30}, \
2704 {"$fp", RTYPE_GP | 30}, \
2705 {"$ra", RTYPE_GP | 31}
2707 #define MIPS16_SPECIAL_REGISTER_NAMES \
2708 {"$pc", RTYPE_PC | 0}
2710 #define MDMX_VECTOR_REGISTER_NAMES \
2711 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2712 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2713 {"$v2", RTYPE_VEC | 2}, \
2714 {"$v3", RTYPE_VEC | 3}, \
2715 {"$v4", RTYPE_VEC | 4}, \
2716 {"$v5", RTYPE_VEC | 5}, \
2717 {"$v6", RTYPE_VEC | 6}, \
2718 {"$v7", RTYPE_VEC | 7}, \
2719 {"$v8", RTYPE_VEC | 8}, \
2720 {"$v9", RTYPE_VEC | 9}, \
2721 {"$v10", RTYPE_VEC | 10}, \
2722 {"$v11", RTYPE_VEC | 11}, \
2723 {"$v12", RTYPE_VEC | 12}, \
2724 {"$v13", RTYPE_VEC | 13}, \
2725 {"$v14", RTYPE_VEC | 14}, \
2726 {"$v15", RTYPE_VEC | 15}, \
2727 {"$v16", RTYPE_VEC | 16}, \
2728 {"$v17", RTYPE_VEC | 17}, \
2729 {"$v18", RTYPE_VEC | 18}, \
2730 {"$v19", RTYPE_VEC | 19}, \
2731 {"$v20", RTYPE_VEC | 20}, \
2732 {"$v21", RTYPE_VEC | 21}, \
2733 {"$v22", RTYPE_VEC | 22}, \
2734 {"$v23", RTYPE_VEC | 23}, \
2735 {"$v24", RTYPE_VEC | 24}, \
2736 {"$v25", RTYPE_VEC | 25}, \
2737 {"$v26", RTYPE_VEC | 26}, \
2738 {"$v27", RTYPE_VEC | 27}, \
2739 {"$v28", RTYPE_VEC | 28}, \
2740 {"$v29", RTYPE_VEC | 29}, \
2741 {"$v30", RTYPE_VEC | 30}, \
2742 {"$v31", RTYPE_VEC | 31}
2744 #define R5900_I_NAMES \
2745 {"$I", RTYPE_R5900_I | 0}
2747 #define R5900_Q_NAMES \
2748 {"$Q", RTYPE_R5900_Q | 0}
2750 #define R5900_R_NAMES \
2751 {"$R", RTYPE_R5900_R | 0}
2753 #define R5900_ACC_NAMES \
2754 {"$ACC", RTYPE_R5900_ACC | 0 }
2756 #define MIPS_DSP_ACCUMULATOR_NAMES \
2757 {"$ac0", RTYPE_ACC | 0}, \
2758 {"$ac1", RTYPE_ACC | 1}, \
2759 {"$ac2", RTYPE_ACC | 2}, \
2760 {"$ac3", RTYPE_ACC | 3}
2762 static const struct regname reg_names
[] = {
2763 GENERIC_REGISTER_NUMBERS
,
2765 FPU_CONDITION_CODE_NAMES
,
2766 COPROC_CONDITION_CODE_NAMES
,
2768 /* The $txx registers depends on the abi,
2769 these will be added later into the symbol table from
2770 one of the tables below once mips_abi is set after
2771 parsing of arguments from the command line. */
2772 SYMBOLIC_REGISTER_NAMES
,
2774 MIPS16_SPECIAL_REGISTER_NAMES
,
2775 MDMX_VECTOR_REGISTER_NAMES
,
2780 MIPS_DSP_ACCUMULATOR_NAMES
,
2784 static const struct regname reg_names_o32
[] = {
2785 O32_SYMBOLIC_REGISTER_NAMES
,
2789 static const struct regname reg_names_n32n64
[] = {
2790 N32N64_SYMBOLIC_REGISTER_NAMES
,
2794 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2795 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2796 of these register symbols, return the associated vector register,
2797 otherwise return SYMVAL itself. */
2800 mips_prefer_vec_regno (unsigned int symval
)
2802 if ((symval
& -2) == (RTYPE_GP
| 2))
2803 return RTYPE_VEC
| (symval
& 1);
2807 /* Return true if string [S, E) is a valid register name, storing its
2808 symbol value in *SYMVAL_PTR if so. */
2811 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2816 /* Terminate name. */
2820 /* Look up the name. */
2821 symbol
= symbol_find (s
);
2824 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2827 *symval_ptr
= S_GET_VALUE (symbol
);
2831 /* Return true if the string at *SPTR is a valid register name. Allow it
2832 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2835 When returning true, move *SPTR past the register, store the
2836 register's symbol value in *SYMVAL_PTR and the channel mask in
2837 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2838 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2839 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2842 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2843 unsigned int *channels_ptr
)
2847 unsigned int channels
, symval
, bit
;
2849 /* Find end of name. */
2851 if (is_name_beginner (*e
))
2853 while (is_part_of_name (*e
))
2857 if (!mips_parse_register_1 (s
, e
, &symval
))
2862 /* Eat characters from the end of the string that are valid
2863 channel suffixes. The preceding register must be $ACC or
2864 end with a digit, so there is no ambiguity. */
2867 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2868 if (m
> s
&& m
[-1] == *q
)
2875 || !mips_parse_register_1 (s
, m
, &symval
)
2876 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2881 *symval_ptr
= symval
;
2883 *channels_ptr
= channels
;
2887 /* Check if SPTR points at a valid register specifier according to TYPES.
2888 If so, then return 1, advance S to consume the specifier and store
2889 the register's number in REGNOP, otherwise return 0. */
2892 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2896 if (mips_parse_register (s
, ®no
, NULL
))
2898 if (types
& RTYPE_VEC
)
2899 regno
= mips_prefer_vec_regno (regno
);
2908 as_warn (_("unrecognized register name `%s'"), *s
);
2913 return regno
<= RNUM_MASK
;
2916 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2917 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2920 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2925 for (i
= 0; i
< 4; i
++)
2926 if (*s
== "xyzw"[i
])
2928 *channels
|= 1 << (3 - i
);
2934 /* Token types for parsed operand lists. */
2935 enum mips_operand_token_type
{
2936 /* A plain register, e.g. $f2. */
2939 /* A 4-bit XYZW channel mask. */
2942 /* A constant vector index, e.g. [1]. */
2945 /* A register vector index, e.g. [$2]. */
2948 /* A continuous range of registers, e.g. $s0-$s4. */
2951 /* A (possibly relocated) expression. */
2954 /* A floating-point value. */
2957 /* A single character. This can be '(', ')' or ',', but '(' only appears
2961 /* A doubled character, either "--" or "++". */
2964 /* The end of the operand list. */
2968 /* A parsed operand token. */
2969 struct mips_operand_token
2971 /* The type of token. */
2972 enum mips_operand_token_type type
;
2975 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2978 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2979 unsigned int channels
;
2981 /* The integer value of an OT_INTEGER_INDEX. */
2984 /* The two register symbol values involved in an OT_REG_RANGE. */
2986 unsigned int regno1
;
2987 unsigned int regno2
;
2990 /* The value of an OT_INTEGER. The value is represented as an
2991 expression and the relocation operators that were applied to
2992 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2993 relocation operators were used. */
2996 bfd_reloc_code_real_type relocs
[3];
2999 /* The binary data for an OT_FLOAT constant, and the number of bytes
3002 unsigned char data
[8];
3006 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3011 /* An obstack used to construct lists of mips_operand_tokens. */
3012 static struct obstack mips_operand_tokens
;
3014 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3017 mips_add_token (struct mips_operand_token
*token
,
3018 enum mips_operand_token_type type
)
3021 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3024 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3025 and OT_REG tokens for them if so, and return a pointer to the first
3026 unconsumed character. Return null otherwise. */
3029 mips_parse_base_start (char *s
)
3031 struct mips_operand_token token
;
3032 unsigned int regno
, channels
;
3033 bfd_boolean decrement_p
;
3039 SKIP_SPACE_TABS (s
);
3041 /* Only match "--" as part of a base expression. In other contexts "--X"
3042 is a double negative. */
3043 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3047 SKIP_SPACE_TABS (s
);
3050 /* Allow a channel specifier because that leads to better error messages
3051 than treating something like "$vf0x++" as an expression. */
3052 if (!mips_parse_register (&s
, ®no
, &channels
))
3056 mips_add_token (&token
, OT_CHAR
);
3061 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3064 token
.u
.regno
= regno
;
3065 mips_add_token (&token
, OT_REG
);
3069 token
.u
.channels
= channels
;
3070 mips_add_token (&token
, OT_CHANNELS
);
3073 /* For consistency, only match "++" as part of base expressions too. */
3074 SKIP_SPACE_TABS (s
);
3075 if (s
[0] == '+' && s
[1] == '+')
3079 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3085 /* Parse one or more tokens from S. Return a pointer to the first
3086 unconsumed character on success. Return null if an error was found
3087 and store the error text in insn_error. FLOAT_FORMAT is as for
3088 mips_parse_arguments. */
3091 mips_parse_argument_token (char *s
, char float_format
)
3093 char *end
, *save_in
;
3095 unsigned int regno1
, regno2
, channels
;
3096 struct mips_operand_token token
;
3098 /* First look for "($reg", since we want to treat that as an
3099 OT_CHAR and OT_REG rather than an expression. */
3100 end
= mips_parse_base_start (s
);
3104 /* Handle other characters that end up as OT_CHARs. */
3105 if (*s
== ')' || *s
== ',')
3108 mips_add_token (&token
, OT_CHAR
);
3113 /* Handle tokens that start with a register. */
3114 if (mips_parse_register (&s
, ®no1
, &channels
))
3118 /* A register and a VU0 channel suffix. */
3119 token
.u
.regno
= regno1
;
3120 mips_add_token (&token
, OT_REG
);
3122 token
.u
.channels
= channels
;
3123 mips_add_token (&token
, OT_CHANNELS
);
3127 SKIP_SPACE_TABS (s
);
3130 /* A register range. */
3132 SKIP_SPACE_TABS (s
);
3133 if (!mips_parse_register (&s
, ®no2
, NULL
))
3135 set_insn_error (0, _("invalid register range"));
3139 token
.u
.reg_range
.regno1
= regno1
;
3140 token
.u
.reg_range
.regno2
= regno2
;
3141 mips_add_token (&token
, OT_REG_RANGE
);
3145 /* Add the register itself. */
3146 token
.u
.regno
= regno1
;
3147 mips_add_token (&token
, OT_REG
);
3149 /* Check for a vector index. */
3153 SKIP_SPACE_TABS (s
);
3154 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3155 mips_add_token (&token
, OT_REG_INDEX
);
3158 expressionS element
;
3160 my_getExpression (&element
, s
);
3161 if (element
.X_op
!= O_constant
)
3163 set_insn_error (0, _("vector element must be constant"));
3167 token
.u
.index
= element
.X_add_number
;
3168 mips_add_token (&token
, OT_INTEGER_INDEX
);
3170 SKIP_SPACE_TABS (s
);
3173 set_insn_error (0, _("missing `]'"));
3183 /* First try to treat expressions as floats. */
3184 save_in
= input_line_pointer
;
3185 input_line_pointer
= s
;
3186 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3187 &token
.u
.flt
.length
);
3188 end
= input_line_pointer
;
3189 input_line_pointer
= save_in
;
3192 set_insn_error (0, err
);
3197 mips_add_token (&token
, OT_FLOAT
);
3202 /* Treat everything else as an integer expression. */
3203 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3204 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3205 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3206 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3208 mips_add_token (&token
, OT_INTEGER
);
3212 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3213 if expressions should be treated as 32-bit floating-point constants,
3214 'd' if they should be treated as 64-bit floating-point constants,
3215 or 0 if they should be treated as integer expressions (the usual case).
3217 Return a list of tokens on success, otherwise return 0. The caller
3218 must obstack_free the list after use. */
3220 static struct mips_operand_token
*
3221 mips_parse_arguments (char *s
, char float_format
)
3223 struct mips_operand_token token
;
3225 SKIP_SPACE_TABS (s
);
3228 s
= mips_parse_argument_token (s
, float_format
);
3231 obstack_free (&mips_operand_tokens
,
3232 obstack_finish (&mips_operand_tokens
));
3235 SKIP_SPACE_TABS (s
);
3237 mips_add_token (&token
, OT_END
);
3238 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3241 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3242 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3245 is_opcode_valid (const struct mips_opcode
*mo
)
3247 int isa
= mips_opts
.isa
;
3248 int ase
= mips_opts
.ase
;
3252 if (ISA_HAS_64BIT_REGS (isa
))
3253 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3254 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3255 ase
|= mips_ases
[i
].flags64
;
3257 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3260 /* Check whether the instruction or macro requires single-precision or
3261 double-precision floating-point support. Note that this information is
3262 stored differently in the opcode table for insns and macros. */
3263 if (mo
->pinfo
== INSN_MACRO
)
3265 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3266 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3270 fp_s
= mo
->pinfo
& FP_S
;
3271 fp_d
= mo
->pinfo
& FP_D
;
3274 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3277 if (fp_s
&& mips_opts
.soft_float
)
3283 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3284 selected ISA and architecture. */
3287 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3289 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3292 /* Return TRUE if the size of the microMIPS opcode MO matches one
3293 explicitly requested. Always TRUE in the standard MIPS mode.
3294 Use is_size_valid_16 for MIPS16 opcodes. */
3297 is_size_valid (const struct mips_opcode
*mo
)
3299 if (!mips_opts
.micromips
)
3302 if (mips_opts
.insn32
)
3304 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3306 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3309 if (!forced_insn_length
)
3311 if (mo
->pinfo
== INSN_MACRO
)
3313 return forced_insn_length
== micromips_insn_length (mo
);
3316 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3317 explicitly requested. */
3320 is_size_valid_16 (const struct mips_opcode
*mo
)
3322 if (!forced_insn_length
)
3324 if (mo
->pinfo
== INSN_MACRO
)
3326 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3328 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3333 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3334 of the preceding instruction. Always TRUE in the standard MIPS mode.
3336 We don't accept macros in 16-bit delay slots to avoid a case where
3337 a macro expansion fails because it relies on a preceding 32-bit real
3338 instruction to have matched and does not handle the operands correctly.
3339 The only macros that may expand to 16-bit instructions are JAL that
3340 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3341 and BGT (that likewise cannot be placed in a delay slot) that decay to
3342 a NOP. In all these cases the macros precede any corresponding real
3343 instruction definitions in the opcode table, so they will match in the
3344 second pass where the size of the delay slot is ignored and therefore
3345 produce correct code. */
3348 is_delay_slot_valid (const struct mips_opcode
*mo
)
3350 if (!mips_opts
.micromips
)
3353 if (mo
->pinfo
== INSN_MACRO
)
3354 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3355 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3356 && micromips_insn_length (mo
) != 4)
3358 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3359 && micromips_insn_length (mo
) != 2)
3365 /* For consistency checking, verify that all bits of OPCODE are specified
3366 either by the match/mask part of the instruction definition, or by the
3367 operand list. Also build up a list of operands in OPERANDS.
3369 INSN_BITS says which bits of the instruction are significant.
3370 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3371 provides the mips_operand description of each operand. DECODE_OPERAND
3372 is null for MIPS16 instructions. */
3375 validate_mips_insn (const struct mips_opcode
*opcode
,
3376 unsigned long insn_bits
,
3377 const struct mips_operand
*(*decode_operand
) (const char *),
3378 struct mips_operand_array
*operands
)
3381 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3382 const struct mips_operand
*operand
;
3384 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3385 if ((mask
& opcode
->match
) != opcode
->match
)
3387 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3388 opcode
->name
, opcode
->args
);
3393 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3394 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3395 for (s
= opcode
->args
; *s
; ++s
)
3408 if (!decode_operand
)
3409 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3411 operand
= decode_operand (s
);
3412 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3414 as_bad (_("internal: unknown operand type: %s %s"),
3415 opcode
->name
, opcode
->args
);
3418 gas_assert (opno
< MAX_OPERANDS
);
3419 operands
->operand
[opno
] = operand
;
3420 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3422 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3423 if (operand
->type
== OP_MDMX_IMM_REG
)
3424 /* Bit 5 is the format selector (OB vs QH). The opcode table
3425 has separate entries for each format. */
3426 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3427 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3428 used_bits
&= ~(mask
& 0x700);
3430 /* Skip prefix characters. */
3431 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3436 doubled
= used_bits
& mask
& insn_bits
;
3439 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3440 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3444 undefined
= ~used_bits
& insn_bits
;
3445 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3447 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3448 undefined
, opcode
->name
, opcode
->args
);
3451 used_bits
&= ~insn_bits
;
3454 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3455 used_bits
, opcode
->name
, opcode
->args
);
3461 /* The MIPS16 version of validate_mips_insn. */
3464 validate_mips16_insn (const struct mips_opcode
*opcode
,
3465 struct mips_operand_array
*operands
)
3467 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3469 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3472 /* The microMIPS version of validate_mips_insn. */
3475 validate_micromips_insn (const struct mips_opcode
*opc
,
3476 struct mips_operand_array
*operands
)
3478 unsigned long insn_bits
;
3479 unsigned long major
;
3480 unsigned int length
;
3482 if (opc
->pinfo
== INSN_MACRO
)
3483 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3486 length
= micromips_insn_length (opc
);
3487 if (length
!= 2 && length
!= 4)
3489 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3490 "%s %s"), length
, opc
->name
, opc
->args
);
3493 major
= opc
->match
>> (10 + 8 * (length
- 2));
3494 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3495 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3497 as_bad (_("internal error: bad microMIPS opcode "
3498 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3502 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3503 insn_bits
= 1 << 4 * length
;
3504 insn_bits
<<= 4 * length
;
3506 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3510 /* This function is called once, at assembler startup time. It should set up
3511 all the tables, etc. that the MD part of the assembler will need. */
3516 const char *retval
= NULL
;
3520 if (mips_pic
!= NO_PIC
)
3522 if (g_switch_seen
&& g_switch_value
!= 0)
3523 as_bad (_("-G may not be used in position-independent code"));
3526 else if (mips_abicalls
)
3528 if (g_switch_seen
&& g_switch_value
!= 0)
3529 as_bad (_("-G may not be used with abicalls"));
3533 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3534 as_warn (_("could not set architecture and machine"));
3536 op_hash
= hash_new ();
3538 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3539 for (i
= 0; i
< NUMOPCODES
;)
3541 const char *name
= mips_opcodes
[i
].name
;
3543 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3546 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3547 mips_opcodes
[i
].name
, retval
);
3548 /* Probably a memory allocation problem? Give up now. */
3549 as_fatal (_("broken assembler, no assembly attempted"));
3553 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3554 decode_mips_operand
, &mips_operands
[i
]))
3556 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3558 create_insn (&nop_insn
, mips_opcodes
+ i
);
3559 if (mips_fix_loongson2f_nop
)
3560 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3561 nop_insn
.fixed_p
= 1;
3565 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3568 mips16_op_hash
= hash_new ();
3569 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3570 bfd_mips16_num_opcodes
);
3573 while (i
< bfd_mips16_num_opcodes
)
3575 const char *name
= mips16_opcodes
[i
].name
;
3577 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3579 as_fatal (_("internal: can't hash `%s': %s"),
3580 mips16_opcodes
[i
].name
, retval
);
3583 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3585 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3587 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3588 mips16_nop_insn
.fixed_p
= 1;
3592 while (i
< bfd_mips16_num_opcodes
3593 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3596 micromips_op_hash
= hash_new ();
3597 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3598 bfd_micromips_num_opcodes
);
3601 while (i
< bfd_micromips_num_opcodes
)
3603 const char *name
= micromips_opcodes
[i
].name
;
3605 retval
= hash_insert (micromips_op_hash
, name
,
3606 (void *) µmips_opcodes
[i
]);
3608 as_fatal (_("internal: can't hash `%s': %s"),
3609 micromips_opcodes
[i
].name
, retval
);
3612 struct mips_cl_insn
*micromips_nop_insn
;
3614 if (!validate_micromips_insn (µmips_opcodes
[i
],
3615 µmips_operands
[i
]))
3618 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3620 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3621 micromips_nop_insn
= µmips_nop16_insn
;
3622 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3623 micromips_nop_insn
= µmips_nop32_insn
;
3627 if (micromips_nop_insn
->insn_mo
== NULL
3628 && strcmp (name
, "nop") == 0)
3630 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3631 micromips_nop_insn
->fixed_p
= 1;
3635 while (++i
< bfd_micromips_num_opcodes
3636 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3640 as_fatal (_("broken assembler, no assembly attempted"));
3642 /* We add all the general register names to the symbol table. This
3643 helps us detect invalid uses of them. */
3644 for (i
= 0; reg_names
[i
].name
; i
++)
3645 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3646 reg_names
[i
].num
, /* & RNUM_MASK, */
3647 &zero_address_frag
));
3649 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3650 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3651 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3652 &zero_address_frag
));
3654 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3655 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3656 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3657 &zero_address_frag
));
3659 for (i
= 0; i
< 32; i
++)
3663 /* R5900 VU0 floating-point register. */
3664 sprintf (regname
, "$vf%d", i
);
3665 symbol_table_insert (symbol_new (regname
, reg_section
,
3666 RTYPE_VF
| i
, &zero_address_frag
));
3668 /* R5900 VU0 integer register. */
3669 sprintf (regname
, "$vi%d", i
);
3670 symbol_table_insert (symbol_new (regname
, reg_section
,
3671 RTYPE_VI
| i
, &zero_address_frag
));
3674 sprintf (regname
, "$w%d", i
);
3675 symbol_table_insert (symbol_new (regname
, reg_section
,
3676 RTYPE_MSA
| i
, &zero_address_frag
));
3679 obstack_init (&mips_operand_tokens
);
3681 mips_no_prev_insn ();
3684 mips_cprmask
[0] = 0;
3685 mips_cprmask
[1] = 0;
3686 mips_cprmask
[2] = 0;
3687 mips_cprmask
[3] = 0;
3689 /* set the default alignment for the text section (2**2) */
3690 record_alignment (text_section
, 2);
3692 bfd_set_gp_size (stdoutput
, g_switch_value
);
3694 /* On a native system other than VxWorks, sections must be aligned
3695 to 16 byte boundaries. When configured for an embedded ELF
3696 target, we don't bother. */
3697 if (strncmp (TARGET_OS
, "elf", 3) != 0
3698 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3700 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3701 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3702 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3705 /* Create a .reginfo section for register masks and a .mdebug
3706 section for debugging information. */
3714 subseg
= now_subseg
;
3716 /* The ABI says this section should be loaded so that the
3717 running program can access it. However, we don't load it
3718 if we are configured for an embedded target */
3719 flags
= SEC_READONLY
| SEC_DATA
;
3720 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3721 flags
|= SEC_ALLOC
| SEC_LOAD
;
3723 if (mips_abi
!= N64_ABI
)
3725 sec
= subseg_new (".reginfo", (subsegT
) 0);
3727 bfd_set_section_flags (stdoutput
, sec
, flags
);
3728 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3730 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3734 /* The 64-bit ABI uses a .MIPS.options section rather than
3735 .reginfo section. */
3736 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3737 bfd_set_section_flags (stdoutput
, sec
, flags
);
3738 bfd_set_section_alignment (stdoutput
, sec
, 3);
3740 /* Set up the option header. */
3742 Elf_Internal_Options opthdr
;
3745 opthdr
.kind
= ODK_REGINFO
;
3746 opthdr
.size
= (sizeof (Elf_External_Options
)
3747 + sizeof (Elf64_External_RegInfo
));
3750 f
= frag_more (sizeof (Elf_External_Options
));
3751 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3752 (Elf_External_Options
*) f
);
3754 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3758 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3759 bfd_set_section_flags (stdoutput
, sec
,
3760 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3761 bfd_set_section_alignment (stdoutput
, sec
, 3);
3762 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3764 if (ECOFF_DEBUGGING
)
3766 sec
= subseg_new (".mdebug", (subsegT
) 0);
3767 (void) bfd_set_section_flags (stdoutput
, sec
,
3768 SEC_HAS_CONTENTS
| SEC_READONLY
);
3769 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3771 else if (mips_flag_pdr
)
3773 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3774 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3775 SEC_READONLY
| SEC_RELOC
3777 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3780 subseg_set (seg
, subseg
);
3783 if (mips_fix_vr4120
)
3784 init_vr4120_conflicts ();
3788 fpabi_incompatible_with (int fpabi
, const char *what
)
3790 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3791 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3795 fpabi_requires (int fpabi
, const char *what
)
3797 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3798 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3801 /* Check -mabi and register sizes against the specified FP ABI. */
3803 check_fpabi (int fpabi
)
3807 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3808 if (file_mips_opts
.soft_float
)
3809 fpabi_incompatible_with (fpabi
, "softfloat");
3810 else if (file_mips_opts
.single_float
)
3811 fpabi_incompatible_with (fpabi
, "singlefloat");
3812 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3813 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3814 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3815 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3818 case Val_GNU_MIPS_ABI_FP_XX
:
3819 if (mips_abi
!= O32_ABI
)
3820 fpabi_requires (fpabi
, "-mabi=32");
3821 else if (file_mips_opts
.soft_float
)
3822 fpabi_incompatible_with (fpabi
, "softfloat");
3823 else if (file_mips_opts
.single_float
)
3824 fpabi_incompatible_with (fpabi
, "singlefloat");
3825 else if (file_mips_opts
.fp
!= 0)
3826 fpabi_requires (fpabi
, "fp=xx");
3829 case Val_GNU_MIPS_ABI_FP_64A
:
3830 case Val_GNU_MIPS_ABI_FP_64
:
3831 if (mips_abi
!= O32_ABI
)
3832 fpabi_requires (fpabi
, "-mabi=32");
3833 else if (file_mips_opts
.soft_float
)
3834 fpabi_incompatible_with (fpabi
, "softfloat");
3835 else if (file_mips_opts
.single_float
)
3836 fpabi_incompatible_with (fpabi
, "singlefloat");
3837 else if (file_mips_opts
.fp
!= 64)
3838 fpabi_requires (fpabi
, "fp=64");
3839 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3840 fpabi_incompatible_with (fpabi
, "nooddspreg");
3841 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3842 fpabi_requires (fpabi
, "nooddspreg");
3845 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3846 if (file_mips_opts
.soft_float
)
3847 fpabi_incompatible_with (fpabi
, "softfloat");
3848 else if (!file_mips_opts
.single_float
)
3849 fpabi_requires (fpabi
, "singlefloat");
3852 case Val_GNU_MIPS_ABI_FP_SOFT
:
3853 if (!file_mips_opts
.soft_float
)
3854 fpabi_requires (fpabi
, "softfloat");
3857 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3858 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3859 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3862 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3863 /* Silently ignore compatibility value. */
3867 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3868 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3873 /* Perform consistency checks on the current options. */
3876 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3878 /* Check the size of integer registers agrees with the ABI and ISA. */
3879 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3880 as_bad (_("`gp=64' used with a 32-bit processor"));
3882 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3883 as_bad (_("`gp=32' used with a 64-bit ABI"));
3885 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3886 as_bad (_("`gp=64' used with a 32-bit ABI"));
3888 /* Check the size of the float registers agrees with the ABI and ISA. */
3892 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3893 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3894 else if (opts
->single_float
== 1)
3895 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3898 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3899 as_bad (_("`fp=64' used with a 32-bit fpu"));
3901 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3902 && !ISA_HAS_MXHC1 (opts
->isa
))
3903 as_warn (_("`fp=64' used with a 32-bit ABI"));
3907 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3908 as_warn (_("`fp=32' used with a 64-bit ABI"));
3909 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
3910 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3913 as_bad (_("Unknown size of floating point registers"));
3917 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3918 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3920 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3921 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3922 else if (ISA_IS_R6 (opts
->isa
)
3923 && (opts
->micromips
== 1
3924 || opts
->mips16
== 1))
3925 as_fatal (_("`%s' cannot be used with `%s'"),
3926 opts
->micromips
? "micromips" : "mips16",
3927 mips_cpu_info_from_isa (opts
->isa
)->name
);
3929 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3930 as_fatal (_("branch relaxation is not supported in `%s'"),
3931 mips_cpu_info_from_isa (opts
->isa
)->name
);
3934 /* Perform consistency checks on the module level options exactly once.
3935 This is a deferred check that happens:
3936 at the first .set directive
3937 or, at the first pseudo op that generates code (inc .dc.a)
3938 or, at the first instruction
3942 file_mips_check_options (void)
3944 const struct mips_cpu_info
*arch_info
= 0;
3946 if (file_mips_opts_checked
)
3949 /* The following code determines the register size.
3950 Similar code was added to GCC 3.3 (see override_options() in
3951 config/mips/mips.c). The GAS and GCC code should be kept in sync
3952 as much as possible. */
3954 if (file_mips_opts
.gp
< 0)
3956 /* Infer the integer register size from the ABI and processor.
3957 Restrict ourselves to 32-bit registers if that's all the
3958 processor has, or if the ABI cannot handle 64-bit registers. */
3959 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
3960 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
3964 if (file_mips_opts
.fp
< 0)
3966 /* No user specified float register size.
3967 ??? GAS treats single-float processors as though they had 64-bit
3968 float registers (although it complains when double-precision
3969 instructions are used). As things stand, saying they have 32-bit
3970 registers would lead to spurious "register must be even" messages.
3971 So here we assume float registers are never smaller than the
3973 if (file_mips_opts
.gp
== 64)
3974 /* 64-bit integer registers implies 64-bit float registers. */
3975 file_mips_opts
.fp
= 64;
3976 else if ((file_mips_opts
.ase
& FP64_ASES
)
3977 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
3978 /* Handle ASEs that require 64-bit float registers, if possible. */
3979 file_mips_opts
.fp
= 64;
3980 else if (ISA_IS_R6 (mips_opts
.isa
))
3981 /* R6 implies 64-bit float registers. */
3982 file_mips_opts
.fp
= 64;
3984 /* 32-bit float registers. */
3985 file_mips_opts
.fp
= 32;
3988 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
3990 /* Disable operations on odd-numbered floating-point registers by default
3991 when using the FPXX ABI. */
3992 if (file_mips_opts
.oddspreg
< 0)
3994 if (file_mips_opts
.fp
== 0)
3995 file_mips_opts
.oddspreg
= 0;
3997 file_mips_opts
.oddspreg
= 1;
4000 /* End of GCC-shared inference code. */
4002 /* This flag is set when we have a 64-bit capable CPU but use only
4003 32-bit wide registers. Note that EABI does not use it. */
4004 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4005 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4006 || mips_abi
== O32_ABI
))
4009 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4010 as_bad (_("trap exception not supported at ISA 1"));
4012 /* If the selected architecture includes support for ASEs, enable
4013 generation of code for them. */
4014 if (file_mips_opts
.mips16
== -1)
4015 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4016 if (file_mips_opts
.micromips
== -1)
4017 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4020 if (mips_nan2008
== -1)
4021 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4022 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4023 as_fatal (_("`%s' does not support legacy NaN"),
4024 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4026 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4027 being selected implicitly. */
4028 if (file_mips_opts
.fp
!= 64)
4029 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4031 /* If the user didn't explicitly select or deselect a particular ASE,
4032 use the default setting for the CPU. */
4033 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4035 /* Set up the current options. These may change throughout assembly. */
4036 mips_opts
= file_mips_opts
;
4038 mips_check_isa_supports_ases ();
4039 mips_check_options (&file_mips_opts
, TRUE
);
4040 file_mips_opts_checked
= TRUE
;
4042 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4043 as_warn (_("could not set architecture and machine"));
4047 md_assemble (char *str
)
4049 struct mips_cl_insn insn
;
4050 bfd_reloc_code_real_type unused_reloc
[3]
4051 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4053 file_mips_check_options ();
4055 imm_expr
.X_op
= O_absent
;
4056 offset_expr
.X_op
= O_absent
;
4057 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4058 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4059 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4061 mips_mark_labels ();
4062 mips_assembling_insn
= TRUE
;
4063 clear_insn_error ();
4065 if (mips_opts
.mips16
)
4066 mips16_ip (str
, &insn
);
4069 mips_ip (str
, &insn
);
4070 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4071 str
, insn
.insn_opcode
));
4075 report_insn_error (str
);
4076 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4079 if (mips_opts
.mips16
)
4080 mips16_macro (&insn
);
4087 if (offset_expr
.X_op
!= O_absent
)
4088 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4090 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4093 mips_assembling_insn
= FALSE
;
4096 /* Convenience functions for abstracting away the differences between
4097 MIPS16 and non-MIPS16 relocations. */
4099 static inline bfd_boolean
4100 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4104 case BFD_RELOC_MIPS16_JMP
:
4105 case BFD_RELOC_MIPS16_GPREL
:
4106 case BFD_RELOC_MIPS16_GOT16
:
4107 case BFD_RELOC_MIPS16_CALL16
:
4108 case BFD_RELOC_MIPS16_HI16_S
:
4109 case BFD_RELOC_MIPS16_HI16
:
4110 case BFD_RELOC_MIPS16_LO16
:
4111 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4119 static inline bfd_boolean
4120 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4124 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4125 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4126 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4127 case BFD_RELOC_MICROMIPS_GPREL16
:
4128 case BFD_RELOC_MICROMIPS_JMP
:
4129 case BFD_RELOC_MICROMIPS_HI16
:
4130 case BFD_RELOC_MICROMIPS_HI16_S
:
4131 case BFD_RELOC_MICROMIPS_LO16
:
4132 case BFD_RELOC_MICROMIPS_LITERAL
:
4133 case BFD_RELOC_MICROMIPS_GOT16
:
4134 case BFD_RELOC_MICROMIPS_CALL16
:
4135 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4136 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4137 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4138 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4139 case BFD_RELOC_MICROMIPS_SUB
:
4140 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4141 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4142 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4143 case BFD_RELOC_MICROMIPS_HIGHEST
:
4144 case BFD_RELOC_MICROMIPS_HIGHER
:
4145 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4146 case BFD_RELOC_MICROMIPS_JALR
:
4154 static inline bfd_boolean
4155 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4157 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4160 static inline bfd_boolean
4161 b_reloc_p (bfd_reloc_code_real_type reloc
)
4163 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4164 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4165 || reloc
== BFD_RELOC_16_PCREL_S2
4166 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4167 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4168 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4169 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4172 static inline bfd_boolean
4173 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4175 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4176 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4179 static inline bfd_boolean
4180 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4182 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4183 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4186 static inline bfd_boolean
4187 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4189 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4190 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4193 static inline bfd_boolean
4194 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4196 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4199 static inline bfd_boolean
4200 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4202 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4203 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4206 /* Return true if RELOC is a PC-relative relocation that does not have
4207 full address range. */
4209 static inline bfd_boolean
4210 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4214 case BFD_RELOC_16_PCREL_S2
:
4215 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4216 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4217 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4218 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4219 case BFD_RELOC_MIPS_21_PCREL_S2
:
4220 case BFD_RELOC_MIPS_26_PCREL_S2
:
4221 case BFD_RELOC_MIPS_18_PCREL_S3
:
4222 case BFD_RELOC_MIPS_19_PCREL_S2
:
4225 case BFD_RELOC_32_PCREL
:
4226 case BFD_RELOC_HI16_S_PCREL
:
4227 case BFD_RELOC_LO16_PCREL
:
4228 return HAVE_64BIT_ADDRESSES
;
4235 /* Return true if the given relocation might need a matching %lo().
4236 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4237 need a matching %lo() when applied to local symbols. */
4239 static inline bfd_boolean
4240 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4242 return (HAVE_IN_PLACE_ADDENDS
4243 && (hi16_reloc_p (reloc
)
4244 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4245 all GOT16 relocations evaluate to "G". */
4246 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4249 /* Return the type of %lo() reloc needed by RELOC, given that
4250 reloc_needs_lo_p. */
4252 static inline bfd_reloc_code_real_type
4253 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4255 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4256 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4260 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4263 static inline bfd_boolean
4264 fixup_has_matching_lo_p (fixS
*fixp
)
4266 return (fixp
->fx_next
!= NULL
4267 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4268 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4269 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4272 /* Move all labels in LABELS to the current insertion point. TEXT_P
4273 says whether the labels refer to text or data. */
4276 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4278 struct insn_label_list
*l
;
4281 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4283 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4284 symbol_set_frag (l
->label
, frag_now
);
4285 val
= (valueT
) frag_now_fix ();
4286 /* MIPS16/microMIPS text labels are stored as odd. */
4287 if (text_p
&& HAVE_CODE_COMPRESSION
)
4289 S_SET_VALUE (l
->label
, val
);
4293 /* Move all labels in insn_labels to the current insertion point
4294 and treat them as text labels. */
4297 mips_move_text_labels (void)
4299 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4302 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4305 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4307 bfd_boolean linkonce
= FALSE
;
4308 segT symseg
= S_GET_SEGMENT (sym
);
4310 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4312 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4314 /* The GNU toolchain uses an extension for ELF: a section
4315 beginning with the magic string .gnu.linkonce is a
4316 linkonce section. */
4317 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4318 sizeof ".gnu.linkonce" - 1) == 0)
4324 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4325 linker to handle them specially, such as generating jalx instructions
4326 when needed. We also make them odd for the duration of the assembly,
4327 in order to generate the right sort of code. We will make them even
4328 in the adjust_symtab routine, while leaving them marked. This is
4329 convenient for the debugger and the disassembler. The linker knows
4330 to make them odd again. */
4333 mips_compressed_mark_label (symbolS
*label
)
4335 gas_assert (HAVE_CODE_COMPRESSION
);
4337 if (mips_opts
.mips16
)
4338 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4340 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4341 if ((S_GET_VALUE (label
) & 1) == 0
4342 /* Don't adjust the address if the label is global or weak, or
4343 in a link-once section, since we'll be emitting symbol reloc
4344 references to it which will be patched up by the linker, and
4345 the final value of the symbol may or may not be MIPS16/microMIPS. */
4346 && !S_IS_WEAK (label
)
4347 && !S_IS_EXTERNAL (label
)
4348 && !s_is_linkonce (label
, now_seg
))
4349 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4352 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4355 mips_compressed_mark_labels (void)
4357 struct insn_label_list
*l
;
4359 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4360 mips_compressed_mark_label (l
->label
);
4363 /* End the current frag. Make it a variant frag and record the
4367 relax_close_frag (void)
4369 mips_macro_warning
.first_frag
= frag_now
;
4370 frag_var (rs_machine_dependent
, 0, 0,
4371 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4372 mips_pic
!= NO_PIC
),
4373 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4375 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4376 mips_relax
.first_fixup
= 0;
4379 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4380 See the comment above RELAX_ENCODE for more details. */
4383 relax_start (symbolS
*symbol
)
4385 gas_assert (mips_relax
.sequence
== 0);
4386 mips_relax
.sequence
= 1;
4387 mips_relax
.symbol
= symbol
;
4390 /* Start generating the second version of a relaxable sequence.
4391 See the comment above RELAX_ENCODE for more details. */
4396 gas_assert (mips_relax
.sequence
== 1);
4397 mips_relax
.sequence
= 2;
4400 /* End the current relaxable sequence. */
4405 gas_assert (mips_relax
.sequence
== 2);
4406 relax_close_frag ();
4407 mips_relax
.sequence
= 0;
4410 /* Return true if IP is a delayed branch or jump. */
4412 static inline bfd_boolean
4413 delayed_branch_p (const struct mips_cl_insn
*ip
)
4415 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4416 | INSN_COND_BRANCH_DELAY
4417 | INSN_COND_BRANCH_LIKELY
)) != 0;
4420 /* Return true if IP is a compact branch or jump. */
4422 static inline bfd_boolean
4423 compact_branch_p (const struct mips_cl_insn
*ip
)
4425 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4426 | INSN2_COND_BRANCH
)) != 0;
4429 /* Return true if IP is an unconditional branch or jump. */
4431 static inline bfd_boolean
4432 uncond_branch_p (const struct mips_cl_insn
*ip
)
4434 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4435 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4438 /* Return true if IP is a branch-likely instruction. */
4440 static inline bfd_boolean
4441 branch_likely_p (const struct mips_cl_insn
*ip
)
4443 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4446 /* Return the type of nop that should be used to fill the delay slot
4447 of delayed branch IP. */
4449 static struct mips_cl_insn
*
4450 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4452 if (mips_opts
.micromips
4453 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4454 return µmips_nop32_insn
;
4458 /* Return a mask that has bit N set if OPCODE reads the register(s)
4462 insn_read_mask (const struct mips_opcode
*opcode
)
4464 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4467 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4471 insn_write_mask (const struct mips_opcode
*opcode
)
4473 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4476 /* Return a mask of the registers specified by operand OPERAND of INSN.
4477 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4481 operand_reg_mask (const struct mips_cl_insn
*insn
,
4482 const struct mips_operand
*operand
,
4483 unsigned int type_mask
)
4485 unsigned int uval
, vsel
;
4487 switch (operand
->type
)
4494 case OP_ADDIUSP_INT
:
4495 case OP_ENTRY_EXIT_LIST
:
4496 case OP_REPEAT_DEST_REG
:
4497 case OP_REPEAT_PREV_REG
:
4500 case OP_VU0_MATCH_SUFFIX
:
4505 case OP_OPTIONAL_REG
:
4507 const struct mips_reg_operand
*reg_op
;
4509 reg_op
= (const struct mips_reg_operand
*) operand
;
4510 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4512 uval
= insn_extract_operand (insn
, operand
);
4513 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4518 const struct mips_reg_pair_operand
*pair_op
;
4520 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4521 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4523 uval
= insn_extract_operand (insn
, operand
);
4524 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4527 case OP_CLO_CLZ_DEST
:
4528 if (!(type_mask
& (1 << OP_REG_GP
)))
4530 uval
= insn_extract_operand (insn
, operand
);
4531 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4534 if (!(type_mask
& (1 << OP_REG_GP
)))
4536 uval
= insn_extract_operand (insn
, operand
);
4537 gas_assert ((uval
& 31) == (uval
>> 5));
4538 return 1 << (uval
& 31);
4541 case OP_NON_ZERO_REG
:
4542 if (!(type_mask
& (1 << OP_REG_GP
)))
4544 uval
= insn_extract_operand (insn
, operand
);
4545 return 1 << (uval
& 31);
4547 case OP_LWM_SWM_LIST
:
4550 case OP_SAVE_RESTORE_LIST
:
4553 case OP_MDMX_IMM_REG
:
4554 if (!(type_mask
& (1 << OP_REG_VEC
)))
4556 uval
= insn_extract_operand (insn
, operand
);
4558 if ((vsel
& 0x18) == 0x18)
4560 return 1 << (uval
& 31);
4563 if (!(type_mask
& (1 << OP_REG_GP
)))
4565 return 1 << insn_extract_operand (insn
, operand
);
4570 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4571 where bit N of OPNO_MASK is set if operand N should be included.
4572 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4576 insn_reg_mask (const struct mips_cl_insn
*insn
,
4577 unsigned int type_mask
, unsigned int opno_mask
)
4579 unsigned int opno
, reg_mask
;
4583 while (opno_mask
!= 0)
4586 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4593 /* Return the mask of core registers that IP reads. */
4596 gpr_read_mask (const struct mips_cl_insn
*ip
)
4598 unsigned long pinfo
, pinfo2
;
4601 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4602 pinfo
= ip
->insn_mo
->pinfo
;
4603 pinfo2
= ip
->insn_mo
->pinfo2
;
4604 if (pinfo
& INSN_UDI
)
4606 /* UDI instructions have traditionally been assumed to read RS
4608 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4609 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4611 if (pinfo
& INSN_READ_GPR_24
)
4613 if (pinfo2
& INSN2_READ_GPR_16
)
4615 if (pinfo2
& INSN2_READ_SP
)
4617 if (pinfo2
& INSN2_READ_GPR_31
)
4619 /* Don't include register 0. */
4623 /* Return the mask of core registers that IP writes. */
4626 gpr_write_mask (const struct mips_cl_insn
*ip
)
4628 unsigned long pinfo
, pinfo2
;
4631 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4632 pinfo
= ip
->insn_mo
->pinfo
;
4633 pinfo2
= ip
->insn_mo
->pinfo2
;
4634 if (pinfo
& INSN_WRITE_GPR_24
)
4636 if (pinfo
& INSN_WRITE_GPR_31
)
4638 if (pinfo
& INSN_UDI
)
4639 /* UDI instructions have traditionally been assumed to write to RD. */
4640 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4641 if (pinfo2
& INSN2_WRITE_SP
)
4643 /* Don't include register 0. */
4647 /* Return the mask of floating-point registers that IP reads. */
4650 fpr_read_mask (const struct mips_cl_insn
*ip
)
4652 unsigned long pinfo
;
4655 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4656 | (1 << OP_REG_MSA
)),
4657 insn_read_mask (ip
->insn_mo
));
4658 pinfo
= ip
->insn_mo
->pinfo
;
4659 /* Conservatively treat all operands to an FP_D instruction are doubles.
4660 (This is overly pessimistic for things like cvt.d.s.) */
4661 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4666 /* Return the mask of floating-point registers that IP writes. */
4669 fpr_write_mask (const struct mips_cl_insn
*ip
)
4671 unsigned long pinfo
;
4674 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4675 | (1 << OP_REG_MSA
)),
4676 insn_write_mask (ip
->insn_mo
));
4677 pinfo
= ip
->insn_mo
->pinfo
;
4678 /* Conservatively treat all operands to an FP_D instruction are doubles.
4679 (This is overly pessimistic for things like cvt.s.d.) */
4680 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4685 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4686 Check whether that is allowed. */
4689 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4691 const char *s
= insn
->name
;
4692 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4694 && mips_opts
.oddspreg
;
4696 if (insn
->pinfo
== INSN_MACRO
)
4697 /* Let a macro pass, we'll catch it later when it is expanded. */
4700 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4701 otherwise it depends on oddspreg. */
4702 if ((insn
->pinfo
& FP_S
)
4703 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4704 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4705 return FPR_SIZE
== 32 || oddspreg
;
4707 /* Allow odd registers for single-precision ops and double-precision if the
4708 floating-point registers are 64-bit wide. */
4709 switch (insn
->pinfo
& (FP_S
| FP_D
))
4715 return FPR_SIZE
== 64;
4720 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4721 s
= strchr (insn
->name
, '.');
4722 if (s
!= NULL
&& opnum
== 2)
4723 s
= strchr (s
+ 1, '.');
4724 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4727 return FPR_SIZE
== 64;
4730 /* Information about an instruction argument that we're trying to match. */
4731 struct mips_arg_info
4733 /* The instruction so far. */
4734 struct mips_cl_insn
*insn
;
4736 /* The first unconsumed operand token. */
4737 struct mips_operand_token
*token
;
4739 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4742 /* The 1-based argument number, for error reporting. This does not
4743 count elided optional registers, etc.. */
4746 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4747 unsigned int last_regno
;
4749 /* If the first operand was an OP_REG, this is the register that it
4750 specified, otherwise it is ILLEGAL_REG. */
4751 unsigned int dest_regno
;
4753 /* The value of the last OP_INT operand. Only used for OP_MSB,
4754 where it gives the lsb position. */
4755 unsigned int last_op_int
;
4757 /* If true, match routines should assume that no later instruction
4758 alternative matches and should therefore be as accommodating as
4759 possible. Match routines should not report errors if something
4760 is only invalid for !LAX_MATCH. */
4761 bfd_boolean lax_match
;
4763 /* True if a reference to the current AT register was seen. */
4764 bfd_boolean seen_at
;
4767 /* Record that the argument is out of range. */
4770 match_out_of_range (struct mips_arg_info
*arg
)
4772 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4775 /* Record that the argument isn't constant but needs to be. */
4778 match_not_constant (struct mips_arg_info
*arg
)
4780 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4784 /* Try to match an OT_CHAR token for character CH. Consume the token
4785 and return true on success, otherwise return false. */
4788 match_char (struct mips_arg_info
*arg
, char ch
)
4790 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4800 /* Try to get an expression from the next tokens in ARG. Consume the
4801 tokens and return true on success, storing the expression value in
4802 VALUE and relocation types in R. */
4805 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4806 bfd_reloc_code_real_type
*r
)
4808 /* If the next token is a '(' that was parsed as being part of a base
4809 expression, assume we have an elided offset. The later match will fail
4810 if this turns out to be wrong. */
4811 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4813 value
->X_op
= O_constant
;
4814 value
->X_add_number
= 0;
4815 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4819 /* Reject register-based expressions such as "0+$2" and "(($2))".
4820 For plain registers the default error seems more appropriate. */
4821 if (arg
->token
->type
== OT_INTEGER
4822 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4824 set_insn_error (arg
->argnum
, _("register value used as expression"));
4828 if (arg
->token
->type
== OT_INTEGER
)
4830 *value
= arg
->token
->u
.integer
.value
;
4831 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4837 (arg
->argnum
, _("operand %d must be an immediate expression"),
4842 /* Try to get a constant expression from the next tokens in ARG. Consume
4843 the tokens and return return true on success, storing the constant value
4847 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4850 bfd_reloc_code_real_type r
[3];
4852 if (!match_expression (arg
, &ex
, r
))
4855 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4856 *value
= ex
.X_add_number
;
4859 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
4860 match_out_of_range (arg
);
4862 match_not_constant (arg
);
4868 /* Return the RTYPE_* flags for a register operand of type TYPE that
4869 appears in instruction OPCODE. */
4872 convert_reg_type (const struct mips_opcode
*opcode
,
4873 enum mips_reg_operand_type type
)
4878 return RTYPE_NUM
| RTYPE_GP
;
4881 /* Allow vector register names for MDMX if the instruction is a 64-bit
4882 FPR load, store or move (including moves to and from GPRs). */
4883 if ((mips_opts
.ase
& ASE_MDMX
)
4884 && (opcode
->pinfo
& FP_D
)
4885 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4886 | INSN_COPROC_MEMORY_DELAY
4889 | INSN_STORE_MEMORY
)))
4890 return RTYPE_FPU
| RTYPE_VEC
;
4894 if (opcode
->pinfo
& (FP_D
| FP_S
))
4895 return RTYPE_CCC
| RTYPE_FCC
;
4899 if (opcode
->membership
& INSN_5400
)
4901 return RTYPE_FPU
| RTYPE_VEC
;
4907 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4908 return RTYPE_NUM
| RTYPE_CP0
;
4915 return RTYPE_NUM
| RTYPE_VI
;
4918 return RTYPE_NUM
| RTYPE_VF
;
4920 case OP_REG_R5900_I
:
4921 return RTYPE_R5900_I
;
4923 case OP_REG_R5900_Q
:
4924 return RTYPE_R5900_Q
;
4926 case OP_REG_R5900_R
:
4927 return RTYPE_R5900_R
;
4929 case OP_REG_R5900_ACC
:
4930 return RTYPE_R5900_ACC
;
4935 case OP_REG_MSA_CTRL
:
4941 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4944 check_regno (struct mips_arg_info
*arg
,
4945 enum mips_reg_operand_type type
, unsigned int regno
)
4947 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4948 arg
->seen_at
= TRUE
;
4950 if (type
== OP_REG_FP
4952 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4954 /* This was a warning prior to introducing O32 FPXX and FP64 support
4955 so maintain a warning for FP32 but raise an error for the new
4958 as_warn (_("float register should be even, was %d"), regno
);
4960 as_bad (_("float register should be even, was %d"), regno
);
4963 if (type
== OP_REG_CCC
)
4968 name
= arg
->insn
->insn_mo
->name
;
4969 length
= strlen (name
);
4970 if ((regno
& 1) != 0
4971 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4972 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4973 as_warn (_("condition code register should be even for %s, was %d"),
4976 if ((regno
& 3) != 0
4977 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4978 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4983 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4984 a register of type TYPE. Return true on success, storing the register
4985 number in *REGNO and warning about any dubious uses. */
4988 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4989 unsigned int symval
, unsigned int *regno
)
4991 if (type
== OP_REG_VEC
)
4992 symval
= mips_prefer_vec_regno (symval
);
4993 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4996 *regno
= symval
& RNUM_MASK
;
4997 check_regno (arg
, type
, *regno
);
5001 /* Try to interpret the next token in ARG as a register of type TYPE.
5002 Consume the token and return true on success, storing the register
5003 number in *REGNO. Return false on failure. */
5006 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5007 unsigned int *regno
)
5009 if (arg
->token
->type
== OT_REG
5010 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5018 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5019 Consume the token and return true on success, storing the register numbers
5020 in *REGNO1 and *REGNO2. Return false on failure. */
5023 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5024 unsigned int *regno1
, unsigned int *regno2
)
5026 if (match_reg (arg
, type
, regno1
))
5031 if (arg
->token
->type
== OT_REG_RANGE
5032 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5033 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5034 && *regno1
<= *regno2
)
5042 /* OP_INT matcher. */
5045 match_int_operand (struct mips_arg_info
*arg
,
5046 const struct mips_operand
*operand_base
)
5048 const struct mips_int_operand
*operand
;
5050 int min_val
, max_val
, factor
;
5053 operand
= (const struct mips_int_operand
*) operand_base
;
5054 factor
= 1 << operand
->shift
;
5055 min_val
= mips_int_operand_min (operand
);
5056 max_val
= mips_int_operand_max (operand
);
5058 if (operand_base
->lsb
== 0
5059 && operand_base
->size
== 16
5060 && operand
->shift
== 0
5061 && operand
->bias
== 0
5062 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5064 /* The operand can be relocated. */
5065 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5068 if (offset_expr
.X_op
== O_big
)
5070 match_out_of_range (arg
);
5074 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5075 /* Relocation operators were used. Accept the argument and
5076 leave the relocation value in offset_expr and offset_relocs
5077 for the caller to process. */
5080 if (offset_expr
.X_op
!= O_constant
)
5082 /* Accept non-constant operands if no later alternative matches,
5083 leaving it for the caller to process. */
5084 if (!arg
->lax_match
)
5086 match_not_constant (arg
);
5089 offset_reloc
[0] = BFD_RELOC_LO16
;
5093 /* Clear the global state; we're going to install the operand
5095 sval
= offset_expr
.X_add_number
;
5096 offset_expr
.X_op
= O_absent
;
5098 /* For compatibility with older assemblers, we accept
5099 0x8000-0xffff as signed 16-bit numbers when only
5100 signed numbers are allowed. */
5103 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5104 if (!arg
->lax_match
&& sval
<= max_val
)
5110 if (!match_const_int (arg
, &sval
))
5114 arg
->last_op_int
= sval
;
5116 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5118 match_out_of_range (arg
);
5122 uval
= (unsigned int) sval
>> operand
->shift
;
5123 uval
-= operand
->bias
;
5125 /* Handle -mfix-cn63xxp1. */
5127 && mips_fix_cn63xxp1
5128 && !mips_opts
.micromips
5129 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5144 /* The rest must be changed to 28. */
5149 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5153 /* OP_MAPPED_INT matcher. */
5156 match_mapped_int_operand (struct mips_arg_info
*arg
,
5157 const struct mips_operand
*operand_base
)
5159 const struct mips_mapped_int_operand
*operand
;
5160 unsigned int uval
, num_vals
;
5163 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5164 if (!match_const_int (arg
, &sval
))
5167 num_vals
= 1 << operand_base
->size
;
5168 for (uval
= 0; uval
< num_vals
; uval
++)
5169 if (operand
->int_map
[uval
] == sval
)
5171 if (uval
== num_vals
)
5173 match_out_of_range (arg
);
5177 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5181 /* OP_MSB matcher. */
5184 match_msb_operand (struct mips_arg_info
*arg
,
5185 const struct mips_operand
*operand_base
)
5187 const struct mips_msb_operand
*operand
;
5188 int min_val
, max_val
, max_high
;
5189 offsetT size
, sval
, high
;
5191 operand
= (const struct mips_msb_operand
*) operand_base
;
5192 min_val
= operand
->bias
;
5193 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5194 max_high
= operand
->opsize
;
5196 if (!match_const_int (arg
, &size
))
5199 high
= size
+ arg
->last_op_int
;
5200 sval
= operand
->add_lsb
? high
: size
;
5202 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5204 match_out_of_range (arg
);
5207 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5211 /* OP_REG matcher. */
5214 match_reg_operand (struct mips_arg_info
*arg
,
5215 const struct mips_operand
*operand_base
)
5217 const struct mips_reg_operand
*operand
;
5218 unsigned int regno
, uval
, num_vals
;
5220 operand
= (const struct mips_reg_operand
*) operand_base
;
5221 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5224 if (operand
->reg_map
)
5226 num_vals
= 1 << operand
->root
.size
;
5227 for (uval
= 0; uval
< num_vals
; uval
++)
5228 if (operand
->reg_map
[uval
] == regno
)
5230 if (num_vals
== uval
)
5236 arg
->last_regno
= regno
;
5237 if (arg
->opnum
== 1)
5238 arg
->dest_regno
= regno
;
5239 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5243 /* OP_REG_PAIR matcher. */
5246 match_reg_pair_operand (struct mips_arg_info
*arg
,
5247 const struct mips_operand
*operand_base
)
5249 const struct mips_reg_pair_operand
*operand
;
5250 unsigned int regno1
, regno2
, uval
, num_vals
;
5252 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5253 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5254 || !match_char (arg
, ',')
5255 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5258 num_vals
= 1 << operand_base
->size
;
5259 for (uval
= 0; uval
< num_vals
; uval
++)
5260 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5262 if (uval
== num_vals
)
5265 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5269 /* OP_PCREL matcher. The caller chooses the relocation type. */
5272 match_pcrel_operand (struct mips_arg_info
*arg
)
5274 bfd_reloc_code_real_type r
[3];
5276 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5279 /* OP_PERF_REG matcher. */
5282 match_perf_reg_operand (struct mips_arg_info
*arg
,
5283 const struct mips_operand
*operand
)
5287 if (!match_const_int (arg
, &sval
))
5292 || (mips_opts
.arch
== CPU_R5900
5293 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5294 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5296 set_insn_error (arg
->argnum
, _("invalid performance register"));
5300 insn_insert_operand (arg
->insn
, operand
, sval
);
5304 /* OP_ADDIUSP matcher. */
5307 match_addiusp_operand (struct mips_arg_info
*arg
,
5308 const struct mips_operand
*operand
)
5313 if (!match_const_int (arg
, &sval
))
5318 match_out_of_range (arg
);
5323 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5325 match_out_of_range (arg
);
5329 uval
= (unsigned int) sval
;
5330 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5331 insn_insert_operand (arg
->insn
, operand
, uval
);
5335 /* OP_CLO_CLZ_DEST matcher. */
5338 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5339 const struct mips_operand
*operand
)
5343 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5346 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5350 /* OP_CHECK_PREV matcher. */
5353 match_check_prev_operand (struct mips_arg_info
*arg
,
5354 const struct mips_operand
*operand_base
)
5356 const struct mips_check_prev_operand
*operand
;
5359 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5361 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5364 if (!operand
->zero_ok
&& regno
== 0)
5367 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5368 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5369 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5371 arg
->last_regno
= regno
;
5372 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5379 /* OP_SAME_RS_RT matcher. */
5382 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5383 const struct mips_operand
*operand
)
5387 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5392 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5396 arg
->last_regno
= regno
;
5398 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5402 /* OP_LWM_SWM_LIST matcher. */
5405 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5406 const struct mips_operand
*operand
)
5408 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5409 struct mips_arg_info reset
;
5412 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5416 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5421 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5424 while (match_char (arg
, ',')
5425 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5428 if (operand
->size
== 2)
5430 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5436 and any permutations of these. */
5437 if ((reglist
& 0xfff1ffff) != 0x80010000)
5440 sregs
= (reglist
>> 17) & 7;
5445 /* The list must include at least one of ra and s0-sN,
5446 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5447 which are $23 and $30 respectively.) E.g.:
5455 and any permutations of these. */
5456 if ((reglist
& 0x3f00ffff) != 0)
5459 ra
= (reglist
>> 27) & 0x10;
5460 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5463 if ((sregs
& -sregs
) != sregs
)
5466 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5470 /* OP_ENTRY_EXIT_LIST matcher. */
5473 match_entry_exit_operand (struct mips_arg_info
*arg
,
5474 const struct mips_operand
*operand
)
5477 bfd_boolean is_exit
;
5479 /* The format is the same for both ENTRY and EXIT, but the constraints
5481 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5482 mask
= (is_exit
? 7 << 3 : 0);
5485 unsigned int regno1
, regno2
;
5486 bfd_boolean is_freg
;
5488 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5490 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5495 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5498 mask
|= (5 + regno2
) << 3;
5500 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5501 mask
|= (regno2
- 3) << 3;
5502 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5503 mask
|= (regno2
- 15) << 1;
5504 else if (regno1
== RA
&& regno2
== RA
)
5509 while (match_char (arg
, ','));
5511 insn_insert_operand (arg
->insn
, operand
, mask
);
5515 /* OP_SAVE_RESTORE_LIST matcher. */
5518 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5520 unsigned int opcode
, args
, statics
, sregs
;
5521 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5524 opcode
= arg
->insn
->insn_opcode
;
5526 num_frame_sizes
= 0;
5532 unsigned int regno1
, regno2
;
5534 if (arg
->token
->type
== OT_INTEGER
)
5536 /* Handle the frame size. */
5537 if (!match_const_int (arg
, &frame_size
))
5539 num_frame_sizes
+= 1;
5543 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5546 while (regno1
<= regno2
)
5548 if (regno1
>= 4 && regno1
<= 7)
5550 if (num_frame_sizes
== 0)
5552 args
|= 1 << (regno1
- 4);
5554 /* statics $a0-$a3 */
5555 statics
|= 1 << (regno1
- 4);
5557 else if (regno1
>= 16 && regno1
<= 23)
5559 sregs
|= 1 << (regno1
- 16);
5560 else if (regno1
== 30)
5563 else if (regno1
== 31)
5564 /* Add $ra to insn. */
5574 while (match_char (arg
, ','));
5576 /* Encode args/statics combination. */
5579 else if (args
== 0xf)
5580 /* All $a0-$a3 are args. */
5581 opcode
|= MIPS16_ALL_ARGS
<< 16;
5582 else if (statics
== 0xf)
5583 /* All $a0-$a3 are statics. */
5584 opcode
|= MIPS16_ALL_STATICS
<< 16;
5587 /* Count arg registers. */
5597 /* Count static registers. */
5599 while (statics
& 0x8)
5601 statics
= (statics
<< 1) & 0xf;
5607 /* Encode args/statics. */
5608 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5611 /* Encode $s0/$s1. */
5612 if (sregs
& (1 << 0)) /* $s0 */
5614 if (sregs
& (1 << 1)) /* $s1 */
5618 /* Encode $s2-$s8. */
5627 opcode
|= num_sregs
<< 24;
5629 /* Encode frame size. */
5630 if (num_frame_sizes
== 0)
5632 set_insn_error (arg
->argnum
, _("missing frame size"));
5635 if (num_frame_sizes
> 1)
5637 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5640 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5642 set_insn_error (arg
->argnum
, _("invalid frame size"));
5645 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5648 opcode
|= (((frame_size
& 0xf0) << 16)
5649 | (frame_size
& 0x0f));
5652 /* Finally build the instruction. */
5653 if ((opcode
>> 16) != 0 || frame_size
== 0)
5654 opcode
|= MIPS16_EXTEND
;
5655 arg
->insn
->insn_opcode
= opcode
;
5659 /* OP_MDMX_IMM_REG matcher. */
5662 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5663 const struct mips_operand
*operand
)
5665 unsigned int regno
, uval
;
5667 const struct mips_opcode
*opcode
;
5669 /* The mips_opcode records whether this is an octobyte or quadhalf
5670 instruction. Start out with that bit in place. */
5671 opcode
= arg
->insn
->insn_mo
;
5672 uval
= mips_extract_operand (operand
, opcode
->match
);
5673 is_qh
= (uval
!= 0);
5675 if (arg
->token
->type
== OT_REG
)
5677 if ((opcode
->membership
& INSN_5400
)
5678 && strcmp (opcode
->name
, "rzu.ob") == 0)
5680 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5685 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5689 /* Check whether this is a vector register or a broadcast of
5690 a single element. */
5691 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5693 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5695 set_insn_error (arg
->argnum
, _("invalid element selector"));
5698 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5703 /* A full vector. */
5704 if ((opcode
->membership
& INSN_5400
)
5705 && (strcmp (opcode
->name
, "sll.ob") == 0
5706 || strcmp (opcode
->name
, "srl.ob") == 0))
5708 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5714 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5716 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5724 if (!match_const_int (arg
, &sval
))
5726 if (sval
< 0 || sval
> 31)
5728 match_out_of_range (arg
);
5731 uval
|= (sval
& 31);
5733 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5735 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5737 insn_insert_operand (arg
->insn
, operand
, uval
);
5741 /* OP_IMM_INDEX matcher. */
5744 match_imm_index_operand (struct mips_arg_info
*arg
,
5745 const struct mips_operand
*operand
)
5747 unsigned int max_val
;
5749 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5752 max_val
= (1 << operand
->size
) - 1;
5753 if (arg
->token
->u
.index
> max_val
)
5755 match_out_of_range (arg
);
5758 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5763 /* OP_REG_INDEX matcher. */
5766 match_reg_index_operand (struct mips_arg_info
*arg
,
5767 const struct mips_operand
*operand
)
5771 if (arg
->token
->type
!= OT_REG_INDEX
)
5774 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5777 insn_insert_operand (arg
->insn
, operand
, regno
);
5782 /* OP_PC matcher. */
5785 match_pc_operand (struct mips_arg_info
*arg
)
5787 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5795 /* OP_NON_ZERO_REG matcher. */
5798 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5799 const struct mips_operand
*operand
)
5803 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5809 arg
->last_regno
= regno
;
5810 insn_insert_operand (arg
->insn
, operand
, regno
);
5814 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5815 register that we need to match. */
5818 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5822 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5825 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5826 the length of the value in bytes (4 for float, 8 for double) and
5827 USING_GPRS says whether the destination is a GPR rather than an FPR.
5829 Return the constant in IMM and OFFSET as follows:
5831 - If the constant should be loaded via memory, set IMM to O_absent and
5832 OFFSET to the memory address.
5834 - Otherwise, if the constant should be loaded into two 32-bit registers,
5835 set IMM to the O_constant to load into the high register and OFFSET
5836 to the corresponding value for the low register.
5838 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5840 These constants only appear as the last operand in an instruction,
5841 and every instruction that accepts them in any variant accepts them
5842 in all variants. This means we don't have to worry about backing out
5843 any changes if the instruction does not match. We just match
5844 unconditionally and report an error if the constant is invalid. */
5847 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5848 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5853 const char *newname
;
5854 unsigned char *data
;
5856 /* Where the constant is placed is based on how the MIPS assembler
5859 length == 4 && using_gprs -- immediate value only
5860 length == 8 && using_gprs -- .rdata or immediate value
5861 length == 4 && !using_gprs -- .lit4 or immediate value
5862 length == 8 && !using_gprs -- .lit8 or immediate value
5864 The .lit4 and .lit8 sections are only used if permitted by the
5866 if (arg
->token
->type
!= OT_FLOAT
)
5868 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5872 gas_assert (arg
->token
->u
.flt
.length
== length
);
5873 data
= arg
->token
->u
.flt
.data
;
5876 /* Handle 32-bit constants for which an immediate value is best. */
5879 || g_switch_value
< 4
5880 || (data
[0] == 0 && data
[1] == 0)
5881 || (data
[2] == 0 && data
[3] == 0)))
5883 imm
->X_op
= O_constant
;
5884 if (!target_big_endian
)
5885 imm
->X_add_number
= bfd_getl32 (data
);
5887 imm
->X_add_number
= bfd_getb32 (data
);
5888 offset
->X_op
= O_absent
;
5892 /* Handle 64-bit constants for which an immediate value is best. */
5894 && !mips_disable_float_construction
5895 /* Constants can only be constructed in GPRs and copied to FPRs if the
5896 GPRs are at least as wide as the FPRs or MTHC1 is available.
5897 Unlike most tests for 32-bit floating-point registers this check
5898 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5899 permit 64-bit moves without MXHC1.
5900 Force the constant into memory otherwise. */
5903 || ISA_HAS_MXHC1 (mips_opts
.isa
)
5905 && ((data
[0] == 0 && data
[1] == 0)
5906 || (data
[2] == 0 && data
[3] == 0))
5907 && ((data
[4] == 0 && data
[5] == 0)
5908 || (data
[6] == 0 && data
[7] == 0)))
5910 /* The value is simple enough to load with a couple of instructions.
5911 If using 32-bit registers, set IMM to the high order 32 bits and
5912 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5914 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
5916 imm
->X_op
= O_constant
;
5917 offset
->X_op
= O_constant
;
5918 if (!target_big_endian
)
5920 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5921 offset
->X_add_number
= bfd_getl32 (data
);
5925 imm
->X_add_number
= bfd_getb32 (data
);
5926 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5928 if (offset
->X_add_number
== 0)
5929 offset
->X_op
= O_absent
;
5933 imm
->X_op
= O_constant
;
5934 if (!target_big_endian
)
5935 imm
->X_add_number
= bfd_getl64 (data
);
5937 imm
->X_add_number
= bfd_getb64 (data
);
5938 offset
->X_op
= O_absent
;
5943 /* Switch to the right section. */
5945 subseg
= now_subseg
;
5948 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5953 if (using_gprs
|| g_switch_value
< 8)
5954 newname
= RDATA_SECTION_NAME
;
5959 new_seg
= subseg_new (newname
, (subsegT
) 0);
5960 bfd_set_section_flags (stdoutput
, new_seg
,
5961 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5962 frag_align (length
== 4 ? 2 : 3, 0, 0);
5963 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5964 record_alignment (new_seg
, 4);
5966 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5968 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5970 /* Set the argument to the current address in the section. */
5971 imm
->X_op
= O_absent
;
5972 offset
->X_op
= O_symbol
;
5973 offset
->X_add_symbol
= symbol_temp_new_now ();
5974 offset
->X_add_number
= 0;
5976 /* Put the floating point number into the section. */
5977 p
= frag_more (length
);
5978 memcpy (p
, data
, length
);
5980 /* Switch back to the original section. */
5981 subseg_set (seg
, subseg
);
5985 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5989 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5990 const struct mips_operand
*operand
,
5991 bfd_boolean match_p
)
5995 /* The operand can be an XYZW mask or a single 2-bit channel index
5996 (with X being 0). */
5997 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5999 /* The suffix can be omitted when it is already part of the opcode. */
6000 if (arg
->token
->type
!= OT_CHANNELS
)
6003 uval
= arg
->token
->u
.channels
;
6004 if (operand
->size
== 2)
6006 /* Check that a single bit is set and convert it into a 2-bit index. */
6007 if ((uval
& -uval
) != uval
)
6009 uval
= 4 - ffs (uval
);
6012 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6017 insn_insert_operand (arg
->insn
, operand
, uval
);
6021 /* S is the text seen for ARG. Match it against OPERAND. Return the end
6022 of the argument text if the match is successful, otherwise return null. */
6025 match_operand (struct mips_arg_info
*arg
,
6026 const struct mips_operand
*operand
)
6028 switch (operand
->type
)
6031 return match_int_operand (arg
, operand
);
6034 return match_mapped_int_operand (arg
, operand
);
6037 return match_msb_operand (arg
, operand
);
6040 case OP_OPTIONAL_REG
:
6041 return match_reg_operand (arg
, operand
);
6044 return match_reg_pair_operand (arg
, operand
);
6047 return match_pcrel_operand (arg
);
6050 return match_perf_reg_operand (arg
, operand
);
6052 case OP_ADDIUSP_INT
:
6053 return match_addiusp_operand (arg
, operand
);
6055 case OP_CLO_CLZ_DEST
:
6056 return match_clo_clz_dest_operand (arg
, operand
);
6058 case OP_LWM_SWM_LIST
:
6059 return match_lwm_swm_list_operand (arg
, operand
);
6061 case OP_ENTRY_EXIT_LIST
:
6062 return match_entry_exit_operand (arg
, operand
);
6064 case OP_SAVE_RESTORE_LIST
:
6065 return match_save_restore_list_operand (arg
);
6067 case OP_MDMX_IMM_REG
:
6068 return match_mdmx_imm_reg_operand (arg
, operand
);
6070 case OP_REPEAT_DEST_REG
:
6071 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6073 case OP_REPEAT_PREV_REG
:
6074 return match_tied_reg_operand (arg
, arg
->last_regno
);
6077 return match_pc_operand (arg
);
6080 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6082 case OP_VU0_MATCH_SUFFIX
:
6083 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6086 return match_imm_index_operand (arg
, operand
);
6089 return match_reg_index_operand (arg
, operand
);
6092 return match_same_rs_rt_operand (arg
, operand
);
6095 return match_check_prev_operand (arg
, operand
);
6097 case OP_NON_ZERO_REG
:
6098 return match_non_zero_reg_operand (arg
, operand
);
6103 /* ARG is the state after successfully matching an instruction.
6104 Issue any queued-up warnings. */
6107 check_completed_insn (struct mips_arg_info
*arg
)
6112 as_warn (_("used $at without \".set noat\""));
6114 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6118 /* Return true if modifying general-purpose register REG needs a delay. */
6121 reg_needs_delay (unsigned int reg
)
6123 unsigned long prev_pinfo
;
6125 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6126 if (!mips_opts
.noreorder
6127 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6128 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6129 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6135 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6136 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6137 by VR4120 errata. */
6140 classify_vr4120_insn (const char *name
)
6142 if (strncmp (name
, "macc", 4) == 0)
6143 return FIX_VR4120_MACC
;
6144 if (strncmp (name
, "dmacc", 5) == 0)
6145 return FIX_VR4120_DMACC
;
6146 if (strncmp (name
, "mult", 4) == 0)
6147 return FIX_VR4120_MULT
;
6148 if (strncmp (name
, "dmult", 5) == 0)
6149 return FIX_VR4120_DMULT
;
6150 if (strstr (name
, "div"))
6151 return FIX_VR4120_DIV
;
6152 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6153 return FIX_VR4120_MTHILO
;
6154 return NUM_FIX_VR4120_CLASSES
;
6157 #define INSN_ERET 0x42000018
6158 #define INSN_DERET 0x4200001f
6159 #define INSN_DMULT 0x1c
6160 #define INSN_DMULTU 0x1d
6162 /* Return the number of instructions that must separate INSN1 and INSN2,
6163 where INSN1 is the earlier instruction. Return the worst-case value
6164 for any INSN2 if INSN2 is null. */
6167 insns_between (const struct mips_cl_insn
*insn1
,
6168 const struct mips_cl_insn
*insn2
)
6170 unsigned long pinfo1
, pinfo2
;
6173 /* If INFO2 is null, pessimistically assume that all flags are set for
6174 the second instruction. */
6175 pinfo1
= insn1
->insn_mo
->pinfo
;
6176 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6178 /* For most targets, write-after-read dependencies on the HI and LO
6179 registers must be separated by at least two instructions. */
6180 if (!hilo_interlocks
)
6182 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6184 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6188 /* If we're working around r7000 errata, there must be two instructions
6189 between an mfhi or mflo and any instruction that uses the result. */
6190 if (mips_7000_hilo_fix
6191 && !mips_opts
.micromips
6192 && MF_HILO_INSN (pinfo1
)
6193 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6196 /* If we're working around 24K errata, one instruction is required
6197 if an ERET or DERET is followed by a branch instruction. */
6198 if (mips_fix_24k
&& !mips_opts
.micromips
)
6200 if (insn1
->insn_opcode
== INSN_ERET
6201 || insn1
->insn_opcode
== INSN_DERET
)
6204 || insn2
->insn_opcode
== INSN_ERET
6205 || insn2
->insn_opcode
== INSN_DERET
6206 || delayed_branch_p (insn2
))
6211 /* If we're working around PMC RM7000 errata, there must be three
6212 nops between a dmult and a load instruction. */
6213 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6215 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6216 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6218 if (pinfo2
& INSN_LOAD_MEMORY
)
6223 /* If working around VR4120 errata, check for combinations that need
6224 a single intervening instruction. */
6225 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6227 unsigned int class1
, class2
;
6229 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6230 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6234 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6235 if (vr4120_conflicts
[class1
] & (1 << class2
))
6240 if (!HAVE_CODE_COMPRESSION
)
6242 /* Check for GPR or coprocessor load delays. All such delays
6243 are on the RT register. */
6244 /* Itbl support may require additional care here. */
6245 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6246 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6248 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6252 /* Check for generic coprocessor hazards.
6254 This case is not handled very well. There is no special
6255 knowledge of CP0 handling, and the coprocessors other than
6256 the floating point unit are not distinguished at all. */
6257 /* Itbl support may require additional care here. FIXME!
6258 Need to modify this to include knowledge about
6259 user specified delays! */
6260 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6261 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6263 /* Handle cases where INSN1 writes to a known general coprocessor
6264 register. There must be a one instruction delay before INSN2
6265 if INSN2 reads that register, otherwise no delay is needed. */
6266 mask
= fpr_write_mask (insn1
);
6269 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6274 /* Read-after-write dependencies on the control registers
6275 require a two-instruction gap. */
6276 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6277 && (pinfo2
& INSN_READ_COND_CODE
))
6280 /* We don't know exactly what INSN1 does. If INSN2 is
6281 also a coprocessor instruction, assume there must be
6282 a one instruction gap. */
6283 if (pinfo2
& INSN_COP
)
6288 /* Check for read-after-write dependencies on the coprocessor
6289 control registers in cases where INSN1 does not need a general
6290 coprocessor delay. This means that INSN1 is a floating point
6291 comparison instruction. */
6292 /* Itbl support may require additional care here. */
6293 else if (!cop_interlocks
6294 && (pinfo1
& INSN_WRITE_COND_CODE
)
6295 && (pinfo2
& INSN_READ_COND_CODE
))
6299 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6300 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6302 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6303 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6304 || (insn2
&& delayed_branch_p (insn2
))))
6310 /* Return the number of nops that would be needed to work around the
6311 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6312 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6313 that are contained within the first IGNORE instructions of HIST. */
6316 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6317 const struct mips_cl_insn
*insn
)
6322 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6323 are not affected by the errata. */
6325 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6326 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6327 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6330 /* Search for the first MFLO or MFHI. */
6331 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6332 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6334 /* Extract the destination register. */
6335 mask
= gpr_write_mask (&hist
[i
]);
6337 /* No nops are needed if INSN reads that register. */
6338 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6341 /* ...or if any of the intervening instructions do. */
6342 for (j
= 0; j
< i
; j
++)
6343 if (gpr_read_mask (&hist
[j
]) & mask
)
6347 return MAX_VR4130_NOPS
- i
;
6352 #define BASE_REG_EQ(INSN1, INSN2) \
6353 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6354 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6356 /* Return the minimum alignment for this store instruction. */
6359 fix_24k_align_to (const struct mips_opcode
*mo
)
6361 if (strcmp (mo
->name
, "sh") == 0)
6364 if (strcmp (mo
->name
, "swc1") == 0
6365 || strcmp (mo
->name
, "swc2") == 0
6366 || strcmp (mo
->name
, "sw") == 0
6367 || strcmp (mo
->name
, "sc") == 0
6368 || strcmp (mo
->name
, "s.s") == 0)
6371 if (strcmp (mo
->name
, "sdc1") == 0
6372 || strcmp (mo
->name
, "sdc2") == 0
6373 || strcmp (mo
->name
, "s.d") == 0)
6380 struct fix_24k_store_info
6382 /* Immediate offset, if any, for this store instruction. */
6384 /* Alignment required by this store instruction. */
6386 /* True for register offsets. */
6387 int register_offset
;
6390 /* Comparison function used by qsort. */
6393 fix_24k_sort (const void *a
, const void *b
)
6395 const struct fix_24k_store_info
*pos1
= a
;
6396 const struct fix_24k_store_info
*pos2
= b
;
6398 return (pos1
->off
- pos2
->off
);
6401 /* INSN is a store instruction. Try to record the store information
6402 in STINFO. Return false if the information isn't known. */
6405 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6406 const struct mips_cl_insn
*insn
)
6408 /* The instruction must have a known offset. */
6409 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6412 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6413 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6417 /* Return the number of nops that would be needed to work around the 24k
6418 "lost data on stores during refill" errata if instruction INSN
6419 immediately followed the 2 instructions described by HIST.
6420 Ignore hazards that are contained within the first IGNORE
6421 instructions of HIST.
6423 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6424 for the data cache refills and store data. The following describes
6425 the scenario where the store data could be lost.
6427 * A data cache miss, due to either a load or a store, causing fill
6428 data to be supplied by the memory subsystem
6429 * The first three doublewords of fill data are returned and written
6431 * A sequence of four stores occurs in consecutive cycles around the
6432 final doubleword of the fill:
6436 * Zero, One or more instructions
6439 The four stores A-D must be to different doublewords of the line that
6440 is being filled. The fourth instruction in the sequence above permits
6441 the fill of the final doubleword to be transferred from the FSB into
6442 the cache. In the sequence above, the stores may be either integer
6443 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6444 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6445 different doublewords on the line. If the floating point unit is
6446 running in 1:2 mode, it is not possible to create the sequence above
6447 using only floating point store instructions.
6449 In this case, the cache line being filled is incorrectly marked
6450 invalid, thereby losing the data from any store to the line that
6451 occurs between the original miss and the completion of the five
6452 cycle sequence shown above.
6454 The workarounds are:
6456 * Run the data cache in write-through mode.
6457 * Insert a non-store instruction between
6458 Store A and Store B or Store B and Store C. */
6461 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6462 const struct mips_cl_insn
*insn
)
6464 struct fix_24k_store_info pos
[3];
6465 int align
, i
, base_offset
;
6470 /* If the previous instruction wasn't a store, there's nothing to
6472 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6475 /* If the instructions after the previous one are unknown, we have
6476 to assume the worst. */
6480 /* Check whether we are dealing with three consecutive stores. */
6481 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6482 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6485 /* If we don't know the relationship between the store addresses,
6486 assume the worst. */
6487 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6488 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6491 if (!fix_24k_record_store_info (&pos
[0], insn
)
6492 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6493 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6496 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6498 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6499 X bytes and such that the base register + X is known to be aligned
6502 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6506 align
= pos
[0].align_to
;
6507 base_offset
= pos
[0].off
;
6508 for (i
= 1; i
< 3; i
++)
6509 if (align
< pos
[i
].align_to
)
6511 align
= pos
[i
].align_to
;
6512 base_offset
= pos
[i
].off
;
6514 for (i
= 0; i
< 3; i
++)
6515 pos
[i
].off
-= base_offset
;
6518 pos
[0].off
&= ~align
+ 1;
6519 pos
[1].off
&= ~align
+ 1;
6520 pos
[2].off
&= ~align
+ 1;
6522 /* If any two stores write to the same chunk, they also write to the
6523 same doubleword. The offsets are still sorted at this point. */
6524 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6527 /* A range of at least 9 bytes is needed for the stores to be in
6528 non-overlapping doublewords. */
6529 if (pos
[2].off
- pos
[0].off
<= 8)
6532 if (pos
[2].off
- pos
[1].off
>= 24
6533 || pos
[1].off
- pos
[0].off
>= 24
6534 || pos
[2].off
- pos
[0].off
>= 32)
6540 /* Return the number of nops that would be needed if instruction INSN
6541 immediately followed the MAX_NOPS instructions given by HIST,
6542 where HIST[0] is the most recent instruction. Ignore hazards
6543 between INSN and the first IGNORE instructions in HIST.
6545 If INSN is null, return the worse-case number of nops for any
6549 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6550 const struct mips_cl_insn
*insn
)
6552 int i
, nops
, tmp_nops
;
6555 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6557 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6558 if (tmp_nops
> nops
)
6562 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6564 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6565 if (tmp_nops
> nops
)
6569 if (mips_fix_24k
&& !mips_opts
.micromips
)
6571 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6572 if (tmp_nops
> nops
)
6579 /* The variable arguments provide NUM_INSNS extra instructions that
6580 might be added to HIST. Return the largest number of nops that
6581 would be needed after the extended sequence, ignoring hazards
6582 in the first IGNORE instructions. */
6585 nops_for_sequence (int num_insns
, int ignore
,
6586 const struct mips_cl_insn
*hist
, ...)
6589 struct mips_cl_insn buffer
[MAX_NOPS
];
6590 struct mips_cl_insn
*cursor
;
6593 va_start (args
, hist
);
6594 cursor
= buffer
+ num_insns
;
6595 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6596 while (cursor
> buffer
)
6597 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6599 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6604 /* Like nops_for_insn, but if INSN is a branch, take into account the
6605 worst-case delay for the branch target. */
6608 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6609 const struct mips_cl_insn
*insn
)
6613 nops
= nops_for_insn (ignore
, hist
, insn
);
6614 if (delayed_branch_p (insn
))
6616 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6617 hist
, insn
, get_delay_slot_nop (insn
));
6618 if (tmp_nops
> nops
)
6621 else if (compact_branch_p (insn
))
6623 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6624 if (tmp_nops
> nops
)
6630 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6633 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6635 gas_assert (!HAVE_CODE_COMPRESSION
);
6636 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6637 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6640 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6641 jr target pc &= 'hffff_ffff_cfff_ffff. */
6644 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6646 gas_assert (!HAVE_CODE_COMPRESSION
);
6647 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6648 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6649 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6657 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6658 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6661 ep
.X_op
= O_constant
;
6662 ep
.X_add_number
= 0xcfff0000;
6663 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6664 ep
.X_add_number
= 0xffff;
6665 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6666 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6671 fix_loongson2f (struct mips_cl_insn
* ip
)
6673 if (mips_fix_loongson2f_nop
)
6674 fix_loongson2f_nop (ip
);
6676 if (mips_fix_loongson2f_jump
)
6677 fix_loongson2f_jump (ip
);
6680 /* IP is a branch that has a delay slot, and we need to fill it
6681 automatically. Return true if we can do that by swapping IP
6682 with the previous instruction.
6683 ADDRESS_EXPR is an operand of the instruction to be used with
6687 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6688 bfd_reloc_code_real_type
*reloc_type
)
6690 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6691 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6692 unsigned int fpr_read
, prev_fpr_write
;
6694 /* -O2 and above is required for this optimization. */
6695 if (mips_optimize
< 2)
6698 /* If we have seen .set volatile or .set nomove, don't optimize. */
6699 if (mips_opts
.nomove
)
6702 /* We can't swap if the previous instruction's position is fixed. */
6703 if (history
[0].fixed_p
)
6706 /* If the previous previous insn was in a .set noreorder, we can't
6707 swap. Actually, the MIPS assembler will swap in this situation.
6708 However, gcc configured -with-gnu-as will generate code like
6716 in which we can not swap the bne and INSN. If gcc is not configured
6717 -with-gnu-as, it does not output the .set pseudo-ops. */
6718 if (history
[1].noreorder_p
)
6721 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6722 This means that the previous instruction was a 4-byte one anyhow. */
6723 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6726 /* If the branch is itself the target of a branch, we can not swap.
6727 We cheat on this; all we check for is whether there is a label on
6728 this instruction. If there are any branches to anything other than
6729 a label, users must use .set noreorder. */
6730 if (seg_info (now_seg
)->label_list
)
6733 /* If the previous instruction is in a variant frag other than this
6734 branch's one, we cannot do the swap. This does not apply to
6735 MIPS16 code, which uses variant frags for different purposes. */
6736 if (!mips_opts
.mips16
6738 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6741 /* We do not swap with instructions that cannot architecturally
6742 be placed in a branch delay slot, such as SYNC or ERET. We
6743 also refrain from swapping with a trap instruction, since it
6744 complicates trap handlers to have the trap instruction be in
6746 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6747 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6750 /* Check for conflicts between the branch and the instructions
6751 before the candidate delay slot. */
6752 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6755 /* Check for conflicts between the swapped sequence and the
6756 target of the branch. */
6757 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6760 /* If the branch reads a register that the previous
6761 instruction sets, we can not swap. */
6762 gpr_read
= gpr_read_mask (ip
);
6763 prev_gpr_write
= gpr_write_mask (&history
[0]);
6764 if (gpr_read
& prev_gpr_write
)
6767 fpr_read
= fpr_read_mask (ip
);
6768 prev_fpr_write
= fpr_write_mask (&history
[0]);
6769 if (fpr_read
& prev_fpr_write
)
6772 /* If the branch writes a register that the previous
6773 instruction sets, we can not swap. */
6774 gpr_write
= gpr_write_mask (ip
);
6775 if (gpr_write
& prev_gpr_write
)
6778 /* If the branch writes a register that the previous
6779 instruction reads, we can not swap. */
6780 prev_gpr_read
= gpr_read_mask (&history
[0]);
6781 if (gpr_write
& prev_gpr_read
)
6784 /* If one instruction sets a condition code and the
6785 other one uses a condition code, we can not swap. */
6786 pinfo
= ip
->insn_mo
->pinfo
;
6787 if ((pinfo
& INSN_READ_COND_CODE
)
6788 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6790 if ((pinfo
& INSN_WRITE_COND_CODE
)
6791 && (prev_pinfo
& INSN_READ_COND_CODE
))
6794 /* If the previous instruction uses the PC, we can not swap. */
6795 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6796 if (prev_pinfo2
& INSN2_READ_PC
)
6799 /* If the previous instruction has an incorrect size for a fixed
6800 branch delay slot in microMIPS mode, we cannot swap. */
6801 pinfo2
= ip
->insn_mo
->pinfo2
;
6802 if (mips_opts
.micromips
6803 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6804 && insn_length (history
) != 2)
6806 if (mips_opts
.micromips
6807 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6808 && insn_length (history
) != 4)
6811 /* On R5900 short loops need to be fixed by inserting a nop in
6812 the branch delay slots.
6813 A short loop can be terminated too early. */
6814 if (mips_opts
.arch
== CPU_R5900
6815 /* Check if instruction has a parameter, ignore "j $31". */
6816 && (address_expr
!= NULL
)
6817 /* Parameter must be 16 bit. */
6818 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6819 /* Branch to same segment. */
6820 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
6821 /* Branch to same code fragment. */
6822 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
6823 /* Can only calculate branch offset if value is known. */
6824 && symbol_constant_p (address_expr
->X_add_symbol
)
6825 /* Check if branch is really conditional. */
6826 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6827 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6828 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6831 /* Check if loop is shorter than 6 instructions including
6832 branch and delay slot. */
6833 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
6840 /* When the loop includes branches or jumps,
6841 it is not a short loop. */
6842 for (i
= 0; i
< (distance
/ 4); i
++)
6844 if ((history
[i
].cleared_p
)
6845 || delayed_branch_p (&history
[i
]))
6853 /* Insert nop after branch to fix short loop. */
6862 /* Decide how we should add IP to the instruction stream.
6863 ADDRESS_EXPR is an operand of the instruction to be used with
6866 static enum append_method
6867 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6868 bfd_reloc_code_real_type
*reloc_type
)
6870 /* The relaxed version of a macro sequence must be inherently
6872 if (mips_relax
.sequence
== 2)
6875 /* We must not dabble with instructions in a ".set noreorder" block. */
6876 if (mips_opts
.noreorder
)
6879 /* Otherwise, it's our responsibility to fill branch delay slots. */
6880 if (delayed_branch_p (ip
))
6882 if (!branch_likely_p (ip
)
6883 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6886 if (mips_opts
.mips16
6887 && ISA_SUPPORTS_MIPS16E
6888 && gpr_read_mask (ip
) != 0)
6889 return APPEND_ADD_COMPACT
;
6891 if (mips_opts
.micromips
6892 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
6893 || (!forced_insn_length
6894 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
6895 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
6896 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
6897 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
6898 return APPEND_ADD_COMPACT
;
6900 return APPEND_ADD_WITH_NOP
;
6906 /* IP is an instruction whose opcode we have just changed, END points
6907 to the end of the opcode table processed. Point IP->insn_mo to the
6908 new opcode's definition. */
6911 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
6913 const struct mips_opcode
*mo
;
6915 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6916 if (mo
->pinfo
!= INSN_MACRO
6917 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6925 /* IP is a MIPS16 instruction whose opcode we have just changed.
6926 Point IP->insn_mo to the new opcode's definition. */
6929 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6931 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
6934 /* IP is a microMIPS instruction whose opcode we have just changed.
6935 Point IP->insn_mo to the new opcode's definition. */
6938 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
6940 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
6943 /* For microMIPS macros, we need to generate a local number label
6944 as the target of branches. */
6945 #define MICROMIPS_LABEL_CHAR '\037'
6946 static unsigned long micromips_target_label
;
6947 static char micromips_target_name
[32];
6950 micromips_label_name (void)
6952 char *p
= micromips_target_name
;
6953 char symbol_name_temporary
[24];
6961 l
= micromips_target_label
;
6962 #ifdef LOCAL_LABEL_PREFIX
6963 *p
++ = LOCAL_LABEL_PREFIX
;
6966 *p
++ = MICROMIPS_LABEL_CHAR
;
6969 symbol_name_temporary
[i
++] = l
% 10 + '0';
6974 *p
++ = symbol_name_temporary
[--i
];
6977 return micromips_target_name
;
6981 micromips_label_expr (expressionS
*label_expr
)
6983 label_expr
->X_op
= O_symbol
;
6984 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6985 label_expr
->X_add_number
= 0;
6989 micromips_label_inc (void)
6991 micromips_target_label
++;
6992 *micromips_target_name
= '\0';
6996 micromips_add_label (void)
7000 s
= colon (micromips_label_name ());
7001 micromips_label_inc ();
7002 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7005 /* If assembling microMIPS code, then return the microMIPS reloc
7006 corresponding to the requested one if any. Otherwise return
7007 the reloc unchanged. */
7009 static bfd_reloc_code_real_type
7010 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7012 static const bfd_reloc_code_real_type relocs
[][2] =
7014 /* Keep sorted incrementally by the left-hand key. */
7015 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7016 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7017 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7018 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7019 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7020 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7021 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7022 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7023 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7024 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7025 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7026 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7027 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7028 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7029 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7030 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7031 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7032 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7033 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7034 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7035 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7036 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7037 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7038 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7039 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7040 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7041 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7043 bfd_reloc_code_real_type r
;
7046 if (!mips_opts
.micromips
)
7048 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7054 return relocs
[i
][1];
7059 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7060 Return true on success, storing the resolved value in RESULT. */
7063 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7068 case BFD_RELOC_MIPS_HIGHEST
:
7069 case BFD_RELOC_MICROMIPS_HIGHEST
:
7070 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7073 case BFD_RELOC_MIPS_HIGHER
:
7074 case BFD_RELOC_MICROMIPS_HIGHER
:
7075 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7078 case BFD_RELOC_HI16_S
:
7079 case BFD_RELOC_HI16_S_PCREL
:
7080 case BFD_RELOC_MICROMIPS_HI16_S
:
7081 case BFD_RELOC_MIPS16_HI16_S
:
7082 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7085 case BFD_RELOC_HI16
:
7086 case BFD_RELOC_MICROMIPS_HI16
:
7087 case BFD_RELOC_MIPS16_HI16
:
7088 *result
= (operand
>> 16) & 0xffff;
7091 case BFD_RELOC_LO16
:
7092 case BFD_RELOC_LO16_PCREL
:
7093 case BFD_RELOC_MICROMIPS_LO16
:
7094 case BFD_RELOC_MIPS16_LO16
:
7095 *result
= operand
& 0xffff;
7098 case BFD_RELOC_UNUSED
:
7107 /* Output an instruction. IP is the instruction information.
7108 ADDRESS_EXPR is an operand of the instruction to be used with
7109 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7110 a macro expansion. */
7113 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7114 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7116 unsigned long prev_pinfo2
, pinfo
;
7117 bfd_boolean relaxed_branch
= FALSE
;
7118 enum append_method method
;
7119 bfd_boolean relax32
;
7122 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7123 fix_loongson2f (ip
);
7125 file_ase_mips16
|= mips_opts
.mips16
;
7126 file_ase_micromips
|= mips_opts
.micromips
;
7128 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7129 pinfo
= ip
->insn_mo
->pinfo
;
7131 /* Don't raise alarm about `nods' frags as they'll fill in the right
7132 kind of nop in relaxation if required. */
7133 if (mips_opts
.micromips
7135 && !(history
[0].frag
7136 && history
[0].frag
->fr_type
== rs_machine_dependent
7137 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7138 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7139 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7140 && micromips_insn_length (ip
->insn_mo
) != 2)
7141 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7142 && micromips_insn_length (ip
->insn_mo
) != 4)))
7143 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7144 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7146 if (address_expr
== NULL
)
7148 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7149 && reloc_type
[1] == BFD_RELOC_UNUSED
7150 && reloc_type
[2] == BFD_RELOC_UNUSED
7151 && address_expr
->X_op
== O_constant
)
7153 switch (*reloc_type
)
7155 case BFD_RELOC_MIPS_JMP
:
7159 /* Shift is 2, unusually, for microMIPS JALX. */
7160 shift
= (mips_opts
.micromips
7161 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7162 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7163 as_bad (_("jump to misaligned address (0x%lx)"),
7164 (unsigned long) address_expr
->X_add_number
);
7165 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7171 case BFD_RELOC_MIPS16_JMP
:
7172 if ((address_expr
->X_add_number
& 3) != 0)
7173 as_bad (_("jump to misaligned address (0x%lx)"),
7174 (unsigned long) address_expr
->X_add_number
);
7176 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7177 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7178 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7182 case BFD_RELOC_16_PCREL_S2
:
7186 shift
= mips_opts
.micromips
? 1 : 2;
7187 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7188 as_bad (_("branch to misaligned address (0x%lx)"),
7189 (unsigned long) address_expr
->X_add_number
);
7190 if (!mips_relax_branch
)
7192 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7193 & ~((1 << (shift
+ 16)) - 1))
7194 as_bad (_("branch address range overflow (0x%lx)"),
7195 (unsigned long) address_expr
->X_add_number
);
7196 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7202 case BFD_RELOC_MIPS_21_PCREL_S2
:
7207 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7208 as_bad (_("branch to misaligned address (0x%lx)"),
7209 (unsigned long) address_expr
->X_add_number
);
7210 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7211 & ~((1 << (shift
+ 21)) - 1))
7212 as_bad (_("branch address range overflow (0x%lx)"),
7213 (unsigned long) address_expr
->X_add_number
);
7214 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7219 case BFD_RELOC_MIPS_26_PCREL_S2
:
7224 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7225 as_bad (_("branch to misaligned address (0x%lx)"),
7226 (unsigned long) address_expr
->X_add_number
);
7227 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7228 & ~((1 << (shift
+ 26)) - 1))
7229 as_bad (_("branch address range overflow (0x%lx)"),
7230 (unsigned long) address_expr
->X_add_number
);
7231 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7240 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7243 ip
->insn_opcode
|= value
& 0xffff;
7251 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7253 /* There are a lot of optimizations we could do that we don't.
7254 In particular, we do not, in general, reorder instructions.
7255 If you use gcc with optimization, it will reorder
7256 instructions and generally do much more optimization then we
7257 do here; repeating all that work in the assembler would only
7258 benefit hand written assembly code, and does not seem worth
7260 int nops
= (mips_optimize
== 0
7261 ? nops_for_insn (0, history
, NULL
)
7262 : nops_for_insn_or_target (0, history
, ip
));
7266 unsigned long old_frag_offset
;
7269 old_frag
= frag_now
;
7270 old_frag_offset
= frag_now_fix ();
7272 for (i
= 0; i
< nops
; i
++)
7273 add_fixed_insn (NOP_INSN
);
7274 insert_into_history (0, nops
, NOP_INSN
);
7278 listing_prev_line ();
7279 /* We may be at the start of a variant frag. In case we
7280 are, make sure there is enough space for the frag
7281 after the frags created by listing_prev_line. The
7282 argument to frag_grow here must be at least as large
7283 as the argument to all other calls to frag_grow in
7284 this file. We don't have to worry about being in the
7285 middle of a variant frag, because the variants insert
7286 all needed nop instructions themselves. */
7290 mips_move_text_labels ();
7292 #ifndef NO_ECOFF_DEBUGGING
7293 if (ECOFF_DEBUGGING
)
7294 ecoff_fix_loc (old_frag
, old_frag_offset
);
7298 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7302 /* Work out how many nops in prev_nop_frag are needed by IP,
7303 ignoring hazards generated by the first prev_nop_frag_since
7305 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7306 gas_assert (nops
<= prev_nop_frag_holds
);
7308 /* Enforce NOPS as a minimum. */
7309 if (nops
> prev_nop_frag_required
)
7310 prev_nop_frag_required
= nops
;
7312 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7314 /* Settle for the current number of nops. Update the history
7315 accordingly (for the benefit of any future .set reorder code). */
7316 prev_nop_frag
= NULL
;
7317 insert_into_history (prev_nop_frag_since
,
7318 prev_nop_frag_holds
, NOP_INSN
);
7322 /* Allow this instruction to replace one of the nops that was
7323 tentatively added to prev_nop_frag. */
7324 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7325 prev_nop_frag_holds
--;
7326 prev_nop_frag_since
++;
7330 method
= get_append_method (ip
, address_expr
, reloc_type
);
7331 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7333 dwarf2_emit_insn (0);
7334 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7335 so "move" the instruction address accordingly.
7337 Also, it doesn't seem appropriate for the assembler to reorder .loc
7338 entries. If this instruction is a branch that we are going to swap
7339 with the previous instruction, the two instructions should be
7340 treated as a unit, and the debug information for both instructions
7341 should refer to the start of the branch sequence. Using the
7342 current position is certainly wrong when swapping a 32-bit branch
7343 and a 16-bit delay slot, since the current position would then be
7344 in the middle of a branch. */
7345 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7347 relax32
= (mips_relax_branch
7348 /* Don't try branch relaxation within .set nomacro, or within
7349 .set noat if we use $at for PIC computations. If it turns
7350 out that the branch was out-of-range, we'll get an error. */
7351 && !mips_opts
.warn_about_macros
7352 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7353 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7354 as they have no complementing branches. */
7355 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7357 if (!HAVE_CODE_COMPRESSION
7360 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7361 && delayed_branch_p (ip
))
7363 relaxed_branch
= TRUE
;
7364 add_relaxed_insn (ip
, (relaxed_branch_length
7366 uncond_branch_p (ip
) ? -1
7367 : branch_likely_p (ip
) ? 1
7370 (AT
, mips_pic
!= NO_PIC
,
7371 uncond_branch_p (ip
),
7372 branch_likely_p (ip
),
7373 pinfo
& INSN_WRITE_GPR_31
,
7375 address_expr
->X_add_symbol
,
7376 address_expr
->X_add_number
);
7377 *reloc_type
= BFD_RELOC_UNUSED
;
7379 else if (mips_opts
.micromips
7381 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7382 || *reloc_type
> BFD_RELOC_UNUSED
)
7383 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7384 /* Don't try branch relaxation when users specify
7385 16-bit/32-bit instructions. */
7386 && !forced_insn_length
)
7388 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7389 && *reloc_type
> BFD_RELOC_UNUSED
);
7390 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7391 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7392 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7393 int nods
= method
== APPEND_ADD_WITH_NOP
;
7394 int al
= pinfo
& INSN_WRITE_GPR_31
;
7395 int length32
= nods
? 8 : 4;
7397 gas_assert (address_expr
!= NULL
);
7398 gas_assert (!mips_relax
.sequence
);
7400 relaxed_branch
= TRUE
;
7402 method
= APPEND_ADD
;
7404 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7405 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7406 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7408 uncond
, compact
, al
, nods
,
7410 address_expr
->X_add_symbol
,
7411 address_expr
->X_add_number
);
7412 *reloc_type
= BFD_RELOC_UNUSED
;
7414 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7416 bfd_boolean require_unextended
;
7417 bfd_boolean require_extended
;
7421 if (forced_insn_length
!= 0)
7423 require_unextended
= forced_insn_length
== 2;
7424 require_extended
= forced_insn_length
== 4;
7428 require_unextended
= (mips_opts
.noautoextend
7429 && !mips_opcode_32bit_p (ip
->insn_mo
));
7430 require_extended
= 0;
7433 /* We need to set up a variant frag. */
7434 gas_assert (address_expr
!= NULL
);
7435 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7436 symbol created by `make_expr_symbol' may not get a necessary
7437 external relocation produced. */
7438 if (address_expr
->X_op
== O_symbol
)
7440 symbol
= address_expr
->X_add_symbol
;
7441 offset
= address_expr
->X_add_number
;
7445 symbol
= make_expr_symbol (address_expr
);
7446 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7449 add_relaxed_insn (ip
, 12, 0,
7451 (*reloc_type
- BFD_RELOC_UNUSED
,
7454 mips_opts
.warn_about_macros
,
7455 require_unextended
, require_extended
,
7456 delayed_branch_p (&history
[0]),
7457 history
[0].mips16_absolute_jump_p
),
7460 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7462 if (!delayed_branch_p (ip
))
7463 /* Make sure there is enough room to swap this instruction with
7464 a following jump instruction. */
7466 add_fixed_insn (ip
);
7470 if (mips_opts
.mips16
7471 && mips_opts
.noreorder
7472 && delayed_branch_p (&history
[0]))
7473 as_warn (_("extended instruction in delay slot"));
7475 if (mips_relax
.sequence
)
7477 /* If we've reached the end of this frag, turn it into a variant
7478 frag and record the information for the instructions we've
7480 if (frag_room () < 4)
7481 relax_close_frag ();
7482 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7485 if (mips_relax
.sequence
!= 2)
7487 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7488 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7489 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7490 mips_macro_warning
.insns
[0]++;
7492 if (mips_relax
.sequence
!= 1)
7494 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7495 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7496 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7497 mips_macro_warning
.insns
[1]++;
7500 if (mips_opts
.mips16
)
7503 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7505 add_fixed_insn (ip
);
7508 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7510 bfd_reloc_code_real_type final_type
[3];
7511 reloc_howto_type
*howto0
;
7512 reloc_howto_type
*howto
;
7515 /* Perform any necessary conversion to microMIPS relocations
7516 and find out how many relocations there actually are. */
7517 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7518 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7520 /* In a compound relocation, it is the final (outermost)
7521 operator that determines the relocated field. */
7522 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7527 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7528 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7529 bfd_get_reloc_size (howto
),
7531 howto0
&& howto0
->pc_relative
,
7533 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7534 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7536 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7537 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7538 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7540 /* These relocations can have an addend that won't fit in
7541 4 octets for 64bit assembly. */
7543 && ! howto
->partial_inplace
7544 && (reloc_type
[0] == BFD_RELOC_16
7545 || reloc_type
[0] == BFD_RELOC_32
7546 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7547 || reloc_type
[0] == BFD_RELOC_GPREL16
7548 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7549 || reloc_type
[0] == BFD_RELOC_GPREL32
7550 || reloc_type
[0] == BFD_RELOC_64
7551 || reloc_type
[0] == BFD_RELOC_CTOR
7552 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7553 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7554 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7555 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7556 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7557 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7558 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7559 || hi16_reloc_p (reloc_type
[0])
7560 || lo16_reloc_p (reloc_type
[0])))
7561 ip
->fixp
[0]->fx_no_overflow
= 1;
7563 /* These relocations can have an addend that won't fit in 2 octets. */
7564 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7565 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7566 ip
->fixp
[0]->fx_no_overflow
= 1;
7568 if (mips_relax
.sequence
)
7570 if (mips_relax
.first_fixup
== 0)
7571 mips_relax
.first_fixup
= ip
->fixp
[0];
7573 else if (reloc_needs_lo_p (*reloc_type
))
7575 struct mips_hi_fixup
*hi_fixup
;
7577 /* Reuse the last entry if it already has a matching %lo. */
7578 hi_fixup
= mips_hi_fixup_list
;
7580 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7582 hi_fixup
= XNEW (struct mips_hi_fixup
);
7583 hi_fixup
->next
= mips_hi_fixup_list
;
7584 mips_hi_fixup_list
= hi_fixup
;
7586 hi_fixup
->fixp
= ip
->fixp
[0];
7587 hi_fixup
->seg
= now_seg
;
7590 /* Add fixups for the second and third relocations, if given.
7591 Note that the ABI allows the second relocation to be
7592 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7593 moment we only use RSS_UNDEF, but we could add support
7594 for the others if it ever becomes necessary. */
7595 for (i
= 1; i
< 3; i
++)
7596 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7598 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7599 ip
->fixp
[0]->fx_size
, NULL
, 0,
7600 FALSE
, final_type
[i
]);
7602 /* Use fx_tcbit to mark compound relocs. */
7603 ip
->fixp
[0]->fx_tcbit
= 1;
7604 ip
->fixp
[i
]->fx_tcbit
= 1;
7608 /* Update the register mask information. */
7609 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7610 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7615 insert_into_history (0, 1, ip
);
7618 case APPEND_ADD_WITH_NOP
:
7620 struct mips_cl_insn
*nop
;
7622 insert_into_history (0, 1, ip
);
7623 nop
= get_delay_slot_nop (ip
);
7624 add_fixed_insn (nop
);
7625 insert_into_history (0, 1, nop
);
7626 if (mips_relax
.sequence
)
7627 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7631 case APPEND_ADD_COMPACT
:
7632 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7633 if (mips_opts
.mips16
)
7635 ip
->insn_opcode
|= 0x0080;
7636 find_altered_mips16_opcode (ip
);
7638 /* Convert microMIPS instructions. */
7639 else if (mips_opts
.micromips
)
7642 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7643 ip
->insn_opcode
|= 0x0020;
7645 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7646 ip
->insn_opcode
= 0x40e00000;
7647 /* beqz16->beqzc, bnez16->bnezc */
7648 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7650 unsigned long regno
;
7652 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7653 regno
&= MICROMIPSOP_MASK_MD
;
7654 regno
= micromips_to_32_reg_d_map
[regno
];
7655 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7656 | (regno
<< MICROMIPSOP_SH_RS
)
7657 | 0x40a00000) ^ 0x00400000;
7659 /* beqz->beqzc, bnez->bnezc */
7660 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7661 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7662 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7663 | 0x40a00000) ^ 0x00400000;
7664 /* beq $0->beqzc, bne $0->bnezc */
7665 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7666 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7667 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7668 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7669 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7670 | 0x40a00000) ^ 0x00400000;
7673 find_altered_micromips_opcode (ip
);
7678 insert_into_history (0, 1, ip
);
7683 struct mips_cl_insn delay
= history
[0];
7685 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7687 /* Add the delay slot instruction to the end of the
7688 current frag and shrink the fixed part of the
7689 original frag. If the branch occupies the tail of
7690 the latter, move it backwards to cover the gap. */
7691 delay
.frag
->fr_fix
-= branch_disp
;
7692 if (delay
.frag
== ip
->frag
)
7693 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7694 add_fixed_insn (&delay
);
7698 /* If this is not a relaxed branch and we are in the
7699 same frag, then just swap the instructions. */
7700 move_insn (ip
, delay
.frag
, delay
.where
);
7701 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7705 insert_into_history (0, 1, &delay
);
7710 /* If we have just completed an unconditional branch, clear the history. */
7711 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7712 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7716 mips_no_prev_insn ();
7718 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7719 history
[i
].cleared_p
= 1;
7722 /* We need to emit a label at the end of branch-likely macros. */
7723 if (emit_branch_likely_macro
)
7725 emit_branch_likely_macro
= FALSE
;
7726 micromips_add_label ();
7729 /* We just output an insn, so the next one doesn't have a label. */
7730 mips_clear_insn_labels ();
7733 /* Forget that there was any previous instruction or label.
7734 When BRANCH is true, the branch history is also flushed. */
7737 mips_no_prev_insn (void)
7739 prev_nop_frag
= NULL
;
7740 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7741 mips_clear_insn_labels ();
7744 /* This function must be called before we emit something other than
7745 instructions. It is like mips_no_prev_insn except that it inserts
7746 any NOPS that might be needed by previous instructions. */
7749 mips_emit_delays (void)
7751 if (! mips_opts
.noreorder
)
7753 int nops
= nops_for_insn (0, history
, NULL
);
7757 add_fixed_insn (NOP_INSN
);
7758 mips_move_text_labels ();
7761 mips_no_prev_insn ();
7764 /* Start a (possibly nested) noreorder block. */
7767 start_noreorder (void)
7769 if (mips_opts
.noreorder
== 0)
7774 /* None of the instructions before the .set noreorder can be moved. */
7775 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7776 history
[i
].fixed_p
= 1;
7778 /* Insert any nops that might be needed between the .set noreorder
7779 block and the previous instructions. We will later remove any
7780 nops that turn out not to be needed. */
7781 nops
= nops_for_insn (0, history
, NULL
);
7784 if (mips_optimize
!= 0)
7786 /* Record the frag which holds the nop instructions, so
7787 that we can remove them if we don't need them. */
7788 frag_grow (nops
* NOP_INSN_SIZE
);
7789 prev_nop_frag
= frag_now
;
7790 prev_nop_frag_holds
= nops
;
7791 prev_nop_frag_required
= 0;
7792 prev_nop_frag_since
= 0;
7795 for (; nops
> 0; --nops
)
7796 add_fixed_insn (NOP_INSN
);
7798 /* Move on to a new frag, so that it is safe to simply
7799 decrease the size of prev_nop_frag. */
7800 frag_wane (frag_now
);
7802 mips_move_text_labels ();
7804 mips_mark_labels ();
7805 mips_clear_insn_labels ();
7807 mips_opts
.noreorder
++;
7808 mips_any_noreorder
= 1;
7811 /* End a nested noreorder block. */
7814 end_noreorder (void)
7816 mips_opts
.noreorder
--;
7817 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7819 /* Commit to inserting prev_nop_frag_required nops and go back to
7820 handling nop insertion the .set reorder way. */
7821 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7823 insert_into_history (prev_nop_frag_since
,
7824 prev_nop_frag_required
, NOP_INSN
);
7825 prev_nop_frag
= NULL
;
7829 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7830 higher bits unset. */
7833 normalize_constant_expr (expressionS
*ex
)
7835 if (ex
->X_op
== O_constant
7836 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7837 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7841 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7842 all higher bits unset. */
7845 normalize_address_expr (expressionS
*ex
)
7847 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7848 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7849 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7850 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7854 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7855 Return true if the match was successful.
7857 OPCODE_EXTRA is a value that should be ORed into the opcode
7858 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7859 there are more alternatives after OPCODE and SOFT_MATCH is
7860 as for mips_arg_info. */
7863 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7864 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7865 bfd_boolean lax_match
, bfd_boolean complete_p
)
7868 struct mips_arg_info arg
;
7869 const struct mips_operand
*operand
;
7872 imm_expr
.X_op
= O_absent
;
7873 offset_expr
.X_op
= O_absent
;
7874 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7875 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7876 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7878 create_insn (insn
, opcode
);
7879 /* When no opcode suffix is specified, assume ".xyzw". */
7880 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7881 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7883 insn
->insn_opcode
|= opcode_extra
;
7884 memset (&arg
, 0, sizeof (arg
));
7888 arg
.last_regno
= ILLEGAL_REG
;
7889 arg
.dest_regno
= ILLEGAL_REG
;
7890 arg
.lax_match
= lax_match
;
7891 for (args
= opcode
->args
;; ++args
)
7893 if (arg
.token
->type
== OT_END
)
7895 /* Handle unary instructions in which only one operand is given.
7896 The source is then the same as the destination. */
7897 if (arg
.opnum
== 1 && *args
== ',')
7899 operand
= (mips_opts
.micromips
7900 ? decode_micromips_operand (args
+ 1)
7901 : decode_mips_operand (args
+ 1));
7902 if (operand
&& mips_optional_operand_p (operand
))
7910 /* Treat elided base registers as $0. */
7911 if (strcmp (args
, "(b)") == 0)
7919 /* The register suffix is optional. */
7924 /* Fail the match if there were too few operands. */
7928 /* Successful match. */
7931 clear_insn_error ();
7932 if (arg
.dest_regno
== arg
.last_regno
7933 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7937 (0, _("source and destination must be different"));
7938 else if (arg
.last_regno
== 31)
7940 (0, _("a destination register must be supplied"));
7942 else if (arg
.last_regno
== 31
7943 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7944 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7945 set_insn_error (0, _("the source register must not be $31"));
7946 check_completed_insn (&arg
);
7950 /* Fail the match if the line has too many operands. */
7954 /* Handle characters that need to match exactly. */
7955 if (*args
== '(' || *args
== ')' || *args
== ',')
7957 if (match_char (&arg
, *args
))
7964 if (arg
.token
->type
== OT_DOUBLE_CHAR
7965 && arg
.token
->u
.ch
== *args
)
7973 /* Handle special macro operands. Work out the properties of
7982 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
7986 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
7995 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7999 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8003 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8009 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8011 imm_expr
.X_op
= O_constant
;
8013 normalize_constant_expr (&imm_expr
);
8017 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8019 /* Assume that the offset has been elided and that what
8020 we saw was a base register. The match will fail later
8021 if that assumption turns out to be wrong. */
8022 offset_expr
.X_op
= O_constant
;
8023 offset_expr
.X_add_number
= 0;
8027 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8029 normalize_address_expr (&offset_expr
);
8034 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8040 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8046 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8052 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8058 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8062 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8066 gas_assert (mips_opts
.micromips
);
8072 if (!forced_insn_length
)
8073 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8075 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8077 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8083 operand
= (mips_opts
.micromips
8084 ? decode_micromips_operand (args
)
8085 : decode_mips_operand (args
));
8089 /* Skip prefixes. */
8090 if (*args
== '+' || *args
== 'm' || *args
== '-')
8093 if (mips_optional_operand_p (operand
)
8095 && (arg
.token
[0].type
!= OT_REG
8096 || arg
.token
[1].type
== OT_END
))
8098 /* Assume that the register has been elided and is the
8099 same as the first operand. */
8104 if (!match_operand (&arg
, operand
))
8109 /* Like match_insn, but for MIPS16. */
8112 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8113 struct mips_operand_token
*tokens
)
8116 const struct mips_operand
*operand
;
8117 const struct mips_operand
*ext_operand
;
8118 bfd_boolean pcrel
= FALSE
;
8119 int required_insn_length
;
8120 struct mips_arg_info arg
;
8123 if (forced_insn_length
)
8124 required_insn_length
= forced_insn_length
;
8125 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8126 required_insn_length
= 2;
8128 required_insn_length
= 0;
8130 create_insn (insn
, opcode
);
8131 imm_expr
.X_op
= O_absent
;
8132 offset_expr
.X_op
= O_absent
;
8133 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8134 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8135 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8138 memset (&arg
, 0, sizeof (arg
));
8142 arg
.last_regno
= ILLEGAL_REG
;
8143 arg
.dest_regno
= ILLEGAL_REG
;
8145 for (args
= opcode
->args
;; ++args
)
8149 if (arg
.token
->type
== OT_END
)
8153 /* Handle unary instructions in which only one operand is given.
8154 The source is then the same as the destination. */
8155 if (arg
.opnum
== 1 && *args
== ',')
8157 operand
= decode_mips16_operand (args
[1], FALSE
);
8158 if (operand
&& mips_optional_operand_p (operand
))
8166 /* Fail the match if there were too few operands. */
8170 /* Successful match. Stuff the immediate value in now, if
8172 clear_insn_error ();
8173 if (opcode
->pinfo
== INSN_MACRO
)
8175 gas_assert (relax_char
== 0 || relax_char
== 'p');
8176 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8179 && offset_expr
.X_op
== O_constant
8181 && calculate_reloc (*offset_reloc
,
8182 offset_expr
.X_add_number
,
8185 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8186 required_insn_length
, &insn
->insn_opcode
);
8187 offset_expr
.X_op
= O_absent
;
8188 *offset_reloc
= BFD_RELOC_UNUSED
;
8190 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8192 if (required_insn_length
== 2)
8193 set_insn_error (0, _("invalid unextended operand value"));
8196 forced_insn_length
= 4;
8197 insn
->insn_opcode
|= MIPS16_EXTEND
;
8200 else if (relax_char
)
8201 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8203 check_completed_insn (&arg
);
8207 /* Fail the match if the line has too many operands. */
8211 /* Handle characters that need to match exactly. */
8212 if (*args
== '(' || *args
== ')' || *args
== ',')
8214 if (match_char (&arg
, *args
))
8232 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8234 imm_expr
.X_op
= O_constant
;
8236 normalize_constant_expr (&imm_expr
);
8241 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8245 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8249 if (operand
->type
== OP_PCREL
)
8253 ext_operand
= decode_mips16_operand (c
, TRUE
);
8254 if (operand
!= ext_operand
)
8256 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8258 offset_expr
.X_op
= O_constant
;
8259 offset_expr
.X_add_number
= 0;
8264 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8267 /* '8' is used for SLTI(U) and has traditionally not
8268 been allowed to take relocation operators. */
8269 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8270 && (ext_operand
->size
!= 16 || c
== '8'))
8272 match_not_constant (&arg
);
8276 if (offset_expr
.X_op
== O_big
)
8278 match_out_of_range (&arg
);
8287 if (mips_optional_operand_p (operand
)
8289 && (arg
.token
[0].type
!= OT_REG
8290 || arg
.token
[1].type
== OT_END
))
8292 /* Assume that the register has been elided and is the
8293 same as the first operand. */
8298 if (!match_operand (&arg
, operand
))
8303 /* Record that the current instruction is invalid for the current ISA. */
8306 match_invalid_for_isa (void)
8309 (0, _("opcode not supported on this processor: %s (%s)"),
8310 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8311 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8314 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8315 Return true if a definite match or failure was found, storing any match
8316 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8317 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8318 tried and failed to match under normal conditions and now want to try a
8319 more relaxed match. */
8322 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8323 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8324 int opcode_extra
, bfd_boolean lax_match
)
8326 const struct mips_opcode
*opcode
;
8327 const struct mips_opcode
*invalid_delay_slot
;
8328 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8330 /* Search for a match, ignoring alternatives that don't satisfy the
8331 current ISA or forced_length. */
8332 invalid_delay_slot
= 0;
8333 seen_valid_for_isa
= FALSE
;
8334 seen_valid_for_size
= FALSE
;
8338 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8339 if (is_opcode_valid (opcode
))
8341 seen_valid_for_isa
= TRUE
;
8342 if (is_size_valid (opcode
))
8344 bfd_boolean delay_slot_ok
;
8346 seen_valid_for_size
= TRUE
;
8347 delay_slot_ok
= is_delay_slot_valid (opcode
);
8348 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8349 lax_match
, delay_slot_ok
))
8353 if (!invalid_delay_slot
)
8354 invalid_delay_slot
= opcode
;
8363 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8365 /* If the only matches we found had the wrong length for the delay slot,
8366 pick the first such match. We'll issue an appropriate warning later. */
8367 if (invalid_delay_slot
)
8369 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8375 /* Handle the case where we didn't try to match an instruction because
8376 all the alternatives were incompatible with the current ISA. */
8377 if (!seen_valid_for_isa
)
8379 match_invalid_for_isa ();
8383 /* Handle the case where we didn't try to match an instruction because
8384 all the alternatives were of the wrong size. */
8385 if (!seen_valid_for_size
)
8387 if (mips_opts
.insn32
)
8388 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8391 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8392 8 * forced_insn_length
);
8399 /* Like match_insns, but for MIPS16. */
8402 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8403 struct mips_operand_token
*tokens
)
8405 const struct mips_opcode
*opcode
;
8406 bfd_boolean seen_valid_for_isa
;
8407 bfd_boolean seen_valid_for_size
;
8409 /* Search for a match, ignoring alternatives that don't satisfy the
8410 current ISA. There are no separate entries for extended forms so
8411 we deal with forced_length later. */
8412 seen_valid_for_isa
= FALSE
;
8413 seen_valid_for_size
= FALSE
;
8417 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8418 if (is_opcode_valid_16 (opcode
))
8420 seen_valid_for_isa
= TRUE
;
8421 if (is_size_valid_16 (opcode
))
8423 seen_valid_for_size
= TRUE
;
8424 if (match_mips16_insn (insn
, opcode
, tokens
))
8430 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8431 && strcmp (opcode
->name
, first
->name
) == 0);
8433 /* Handle the case where we didn't try to match an instruction because
8434 all the alternatives were incompatible with the current ISA. */
8435 if (!seen_valid_for_isa
)
8437 match_invalid_for_isa ();
8441 /* Handle the case where we didn't try to match an instruction because
8442 all the alternatives were of the wrong size. */
8443 if (!seen_valid_for_size
)
8445 if (forced_insn_length
== 2)
8447 (0, _("unrecognized unextended version of MIPS16 opcode"));
8450 (0, _("unrecognized extended version of MIPS16 opcode"));
8457 /* Set up global variables for the start of a new macro. */
8462 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8463 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8464 sizeof (mips_macro_warning
.first_insn_sizes
));
8465 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8466 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8467 && delayed_branch_p (&history
[0]));
8469 && history
[0].frag
->fr_type
== rs_machine_dependent
8470 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8471 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8472 mips_macro_warning
.delay_slot_length
= 0;
8474 switch (history
[0].insn_mo
->pinfo2
8475 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8477 case INSN2_BRANCH_DELAY_32BIT
:
8478 mips_macro_warning
.delay_slot_length
= 4;
8480 case INSN2_BRANCH_DELAY_16BIT
:
8481 mips_macro_warning
.delay_slot_length
= 2;
8484 mips_macro_warning
.delay_slot_length
= 0;
8487 mips_macro_warning
.first_frag
= NULL
;
8490 /* Given that a macro is longer than one instruction or of the wrong size,
8491 return the appropriate warning for it. Return null if no warning is
8492 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8493 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8494 and RELAX_NOMACRO. */
8497 macro_warning (relax_substateT subtype
)
8499 if (subtype
& RELAX_DELAY_SLOT
)
8500 return _("macro instruction expanded into multiple instructions"
8501 " in a branch delay slot");
8502 else if (subtype
& RELAX_NOMACRO
)
8503 return _("macro instruction expanded into multiple instructions");
8504 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8505 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8506 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8507 ? _("macro instruction expanded into a wrong size instruction"
8508 " in a 16-bit branch delay slot")
8509 : _("macro instruction expanded into a wrong size instruction"
8510 " in a 32-bit branch delay slot"));
8515 /* Finish up a macro. Emit warnings as appropriate. */
8520 /* Relaxation warning flags. */
8521 relax_substateT subtype
= 0;
8523 /* Check delay slot size requirements. */
8524 if (mips_macro_warning
.delay_slot_length
== 2)
8525 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8526 if (mips_macro_warning
.delay_slot_length
!= 0)
8528 if (mips_macro_warning
.delay_slot_length
8529 != mips_macro_warning
.first_insn_sizes
[0])
8530 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8531 if (mips_macro_warning
.delay_slot_length
8532 != mips_macro_warning
.first_insn_sizes
[1])
8533 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8536 /* Check instruction count requirements. */
8537 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8539 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8540 subtype
|= RELAX_SECOND_LONGER
;
8541 if (mips_opts
.warn_about_macros
)
8542 subtype
|= RELAX_NOMACRO
;
8543 if (mips_macro_warning
.delay_slot_p
)
8544 subtype
|= RELAX_DELAY_SLOT
;
8547 /* If both alternatives fail to fill a delay slot correctly,
8548 emit the warning now. */
8549 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8550 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8555 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8556 | RELAX_DELAY_SLOT_SIZE_FIRST
8557 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8558 msg
= macro_warning (s
);
8560 as_warn ("%s", msg
);
8564 /* If both implementations are longer than 1 instruction, then emit the
8566 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8571 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8572 msg
= macro_warning (s
);
8574 as_warn ("%s", msg
);
8578 /* If any flags still set, then one implementation might need a warning
8579 and the other either will need one of a different kind or none at all.
8580 Pass any remaining flags over to relaxation. */
8581 if (mips_macro_warning
.first_frag
!= NULL
)
8582 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8585 /* Instruction operand formats used in macros that vary between
8586 standard MIPS and microMIPS code. */
8588 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8589 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8590 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8591 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8592 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8593 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8594 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8595 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8597 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8598 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8599 : cop12_fmt[mips_opts.micromips])
8600 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8601 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8602 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8603 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8604 : mem12_fmt[mips_opts.micromips])
8605 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8606 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8607 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8609 /* Read a macro's relocation codes from *ARGS and store them in *R.
8610 The first argument in *ARGS will be either the code for a single
8611 relocation or -1 followed by the three codes that make up a
8612 composite relocation. */
8615 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8619 next
= va_arg (*args
, int);
8621 r
[0] = (bfd_reloc_code_real_type
) next
;
8624 for (i
= 0; i
< 3; i
++)
8625 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8626 /* This function is only used for 16-bit relocation fields.
8627 To make the macro code simpler, treat an unrelocated value
8628 in the same way as BFD_RELOC_LO16. */
8629 if (r
[0] == BFD_RELOC_UNUSED
)
8630 r
[0] = BFD_RELOC_LO16
;
8634 /* Build an instruction created by a macro expansion. This is passed
8635 a pointer to the count of instructions created so far, an
8636 expression, the name of the instruction to build, an operand format
8637 string, and corresponding arguments. */
8640 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8642 const struct mips_opcode
*mo
= NULL
;
8643 bfd_reloc_code_real_type r
[3];
8644 const struct mips_opcode
*amo
;
8645 const struct mips_operand
*operand
;
8646 struct hash_control
*hash
;
8647 struct mips_cl_insn insn
;
8651 va_start (args
, fmt
);
8653 if (mips_opts
.mips16
)
8655 mips16_macro_build (ep
, name
, fmt
, &args
);
8660 r
[0] = BFD_RELOC_UNUSED
;
8661 r
[1] = BFD_RELOC_UNUSED
;
8662 r
[2] = BFD_RELOC_UNUSED
;
8663 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8664 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8666 gas_assert (strcmp (name
, amo
->name
) == 0);
8670 /* Search until we get a match for NAME. It is assumed here that
8671 macros will never generate MDMX, MIPS-3D, or MT instructions.
8672 We try to match an instruction that fulfills the branch delay
8673 slot instruction length requirement (if any) of the previous
8674 instruction. While doing this we record the first instruction
8675 seen that matches all the other conditions and use it anyway
8676 if the requirement cannot be met; we will issue an appropriate
8677 warning later on. */
8678 if (strcmp (fmt
, amo
->args
) == 0
8679 && amo
->pinfo
!= INSN_MACRO
8680 && is_opcode_valid (amo
)
8681 && is_size_valid (amo
))
8683 if (is_delay_slot_valid (amo
))
8693 gas_assert (amo
->name
);
8695 while (strcmp (name
, amo
->name
) == 0);
8698 create_insn (&insn
, mo
);
8711 macro_read_relocs (&args
, r
);
8712 gas_assert (*r
== BFD_RELOC_GPREL16
8713 || *r
== BFD_RELOC_MIPS_HIGHER
8714 || *r
== BFD_RELOC_HI16_S
8715 || *r
== BFD_RELOC_LO16
8716 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8720 macro_read_relocs (&args
, r
);
8724 macro_read_relocs (&args
, r
);
8725 gas_assert (ep
!= NULL
8726 && (ep
->X_op
== O_constant
8727 || (ep
->X_op
== O_symbol
8728 && (*r
== BFD_RELOC_MIPS_HIGHEST
8729 || *r
== BFD_RELOC_HI16_S
8730 || *r
== BFD_RELOC_HI16
8731 || *r
== BFD_RELOC_GPREL16
8732 || *r
== BFD_RELOC_MIPS_GOT_HI16
8733 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8737 gas_assert (ep
!= NULL
);
8740 * This allows macro() to pass an immediate expression for
8741 * creating short branches without creating a symbol.
8743 * We don't allow branch relaxation for these branches, as
8744 * they should only appear in ".set nomacro" anyway.
8746 if (ep
->X_op
== O_constant
)
8748 /* For microMIPS we always use relocations for branches.
8749 So we should not resolve immediate values. */
8750 gas_assert (!mips_opts
.micromips
);
8752 if ((ep
->X_add_number
& 3) != 0)
8753 as_bad (_("branch to misaligned address (0x%lx)"),
8754 (unsigned long) ep
->X_add_number
);
8755 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8756 as_bad (_("branch address range overflow (0x%lx)"),
8757 (unsigned long) ep
->X_add_number
);
8758 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8762 *r
= BFD_RELOC_16_PCREL_S2
;
8766 gas_assert (ep
!= NULL
);
8767 *r
= BFD_RELOC_MIPS_JMP
;
8771 operand
= (mips_opts
.micromips
8772 ? decode_micromips_operand (fmt
)
8773 : decode_mips_operand (fmt
));
8777 uval
= va_arg (args
, int);
8778 if (operand
->type
== OP_CLO_CLZ_DEST
)
8779 uval
|= (uval
<< 5);
8780 insn_insert_operand (&insn
, operand
, uval
);
8782 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8788 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8790 append_insn (&insn
, ep
, r
, TRUE
);
8794 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8797 struct mips_opcode
*mo
;
8798 struct mips_cl_insn insn
;
8799 const struct mips_operand
*operand
;
8800 bfd_reloc_code_real_type r
[3]
8801 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8803 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8805 gas_assert (strcmp (name
, mo
->name
) == 0);
8807 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8810 gas_assert (mo
->name
);
8811 gas_assert (strcmp (name
, mo
->name
) == 0);
8814 create_insn (&insn
, mo
);
8851 gas_assert (ep
!= NULL
);
8853 if (ep
->X_op
!= O_constant
)
8854 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8855 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8857 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8859 *r
= BFD_RELOC_UNUSED
;
8865 operand
= decode_mips16_operand (c
, FALSE
);
8869 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8874 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8876 append_insn (&insn
, ep
, r
, TRUE
);
8880 * Generate a "jalr" instruction with a relocation hint to the called
8881 * function. This occurs in NewABI PIC code.
8884 macro_build_jalr (expressionS
*ep
, int cprestore
)
8886 static const bfd_reloc_code_real_type jalr_relocs
[2]
8887 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8888 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8892 if (MIPS_JALR_HINT_P (ep
))
8897 if (mips_opts
.micromips
)
8899 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8900 ? "jalr" : "jalrs");
8901 if (MIPS_JALR_HINT_P (ep
)
8903 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8904 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8906 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8909 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8910 if (MIPS_JALR_HINT_P (ep
))
8911 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8915 * Generate a "lui" instruction.
8918 macro_build_lui (expressionS
*ep
, int regnum
)
8920 gas_assert (! mips_opts
.mips16
);
8922 if (ep
->X_op
!= O_constant
)
8924 gas_assert (ep
->X_op
== O_symbol
);
8925 /* _gp_disp is a special case, used from s_cpload.
8926 __gnu_local_gp is used if mips_no_shared. */
8927 gas_assert (mips_pic
== NO_PIC
8929 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8930 || (! mips_in_shared
8931 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8932 "__gnu_local_gp") == 0));
8935 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8938 /* Generate a sequence of instructions to do a load or store from a constant
8939 offset off of a base register (breg) into/from a target register (treg),
8940 using AT if necessary. */
8942 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8943 int treg
, int breg
, int dbl
)
8945 gas_assert (ep
->X_op
== O_constant
);
8947 /* Sign-extending 32-bit constants makes their handling easier. */
8949 normalize_constant_expr (ep
);
8951 /* Right now, this routine can only handle signed 32-bit constants. */
8952 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8953 as_warn (_("operand overflow"));
8955 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8957 /* Signed 16-bit offset will fit in the op. Easy! */
8958 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8962 /* 32-bit offset, need multiple instructions and AT, like:
8963 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8964 addu $tempreg,$tempreg,$breg
8965 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8966 to handle the complete offset. */
8967 macro_build_lui (ep
, AT
);
8968 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8969 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8972 as_bad (_("macro used $at after \".set noat\""));
8977 * Generates code to set the $at register to true (one)
8978 * if reg is less than the immediate expression.
8981 set_at (int reg
, int unsignedp
)
8983 if (imm_expr
.X_add_number
>= -0x8000
8984 && imm_expr
.X_add_number
< 0x8000)
8985 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8986 AT
, reg
, BFD_RELOC_LO16
);
8989 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
8990 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8994 /* Count the leading zeroes by performing a binary chop. This is a
8995 bulky bit of source, but performance is a LOT better for the
8996 majority of values than a simple loop to count the bits:
8997 for (lcnt = 0; (lcnt < 32); lcnt++)
8998 if ((v) & (1 << (31 - lcnt)))
9000 However it is not code size friendly, and the gain will drop a bit
9001 on certain cached systems.
9003 #define COUNT_TOP_ZEROES(v) \
9004 (((v) & ~0xffff) == 0 \
9005 ? ((v) & ~0xff) == 0 \
9006 ? ((v) & ~0xf) == 0 \
9007 ? ((v) & ~0x3) == 0 \
9008 ? ((v) & ~0x1) == 0 \
9013 : ((v) & ~0x7) == 0 \
9016 : ((v) & ~0x3f) == 0 \
9017 ? ((v) & ~0x1f) == 0 \
9020 : ((v) & ~0x7f) == 0 \
9023 : ((v) & ~0xfff) == 0 \
9024 ? ((v) & ~0x3ff) == 0 \
9025 ? ((v) & ~0x1ff) == 0 \
9028 : ((v) & ~0x7ff) == 0 \
9031 : ((v) & ~0x3fff) == 0 \
9032 ? ((v) & ~0x1fff) == 0 \
9035 : ((v) & ~0x7fff) == 0 \
9038 : ((v) & ~0xffffff) == 0 \
9039 ? ((v) & ~0xfffff) == 0 \
9040 ? ((v) & ~0x3ffff) == 0 \
9041 ? ((v) & ~0x1ffff) == 0 \
9044 : ((v) & ~0x7ffff) == 0 \
9047 : ((v) & ~0x3fffff) == 0 \
9048 ? ((v) & ~0x1fffff) == 0 \
9051 : ((v) & ~0x7fffff) == 0 \
9054 : ((v) & ~0xfffffff) == 0 \
9055 ? ((v) & ~0x3ffffff) == 0 \
9056 ? ((v) & ~0x1ffffff) == 0 \
9059 : ((v) & ~0x7ffffff) == 0 \
9062 : ((v) & ~0x3fffffff) == 0 \
9063 ? ((v) & ~0x1fffffff) == 0 \
9066 : ((v) & ~0x7fffffff) == 0 \
9071 * This routine generates the least number of instructions necessary to load
9072 * an absolute expression value into a register.
9075 load_register (int reg
, expressionS
*ep
, int dbl
)
9078 expressionS hi32
, lo32
;
9080 if (ep
->X_op
!= O_big
)
9082 gas_assert (ep
->X_op
== O_constant
);
9084 /* Sign-extending 32-bit constants makes their handling easier. */
9086 normalize_constant_expr (ep
);
9088 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9090 /* We can handle 16 bit signed values with an addiu to
9091 $zero. No need to ever use daddiu here, since $zero and
9092 the result are always correct in 32 bit mode. */
9093 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9096 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9098 /* We can handle 16 bit unsigned values with an ori to
9100 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9103 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9105 /* 32 bit values require an lui. */
9106 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9107 if ((ep
->X_add_number
& 0xffff) != 0)
9108 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9113 /* The value is larger than 32 bits. */
9115 if (!dbl
|| GPR_SIZE
== 32)
9119 sprintf_vma (value
, ep
->X_add_number
);
9120 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9121 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9125 if (ep
->X_op
!= O_big
)
9128 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9129 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9130 hi32
.X_add_number
&= 0xffffffff;
9132 lo32
.X_add_number
&= 0xffffffff;
9136 gas_assert (ep
->X_add_number
> 2);
9137 if (ep
->X_add_number
== 3)
9138 generic_bignum
[3] = 0;
9139 else if (ep
->X_add_number
> 4)
9140 as_bad (_("number larger than 64 bits"));
9141 lo32
.X_op
= O_constant
;
9142 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9143 hi32
.X_op
= O_constant
;
9144 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9147 if (hi32
.X_add_number
== 0)
9152 unsigned long hi
, lo
;
9154 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9156 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9158 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9161 if (lo32
.X_add_number
& 0x80000000)
9163 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9164 if (lo32
.X_add_number
& 0xffff)
9165 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9170 /* Check for 16bit shifted constant. We know that hi32 is
9171 non-zero, so start the mask on the first bit of the hi32
9176 unsigned long himask
, lomask
;
9180 himask
= 0xffff >> (32 - shift
);
9181 lomask
= (0xffff << shift
) & 0xffffffff;
9185 himask
= 0xffff << (shift
- 32);
9188 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9189 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9193 tmp
.X_op
= O_constant
;
9195 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9196 | (lo32
.X_add_number
>> shift
));
9198 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9199 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9200 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9201 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9206 while (shift
<= (64 - 16));
9208 /* Find the bit number of the lowest one bit, and store the
9209 shifted value in hi/lo. */
9210 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9211 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9215 while ((lo
& 1) == 0)
9220 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9226 while ((hi
& 1) == 0)
9235 /* Optimize if the shifted value is a (power of 2) - 1. */
9236 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9237 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9239 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9244 /* This instruction will set the register to be all
9246 tmp
.X_op
= O_constant
;
9247 tmp
.X_add_number
= (offsetT
) -1;
9248 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9252 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9253 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9255 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9256 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9261 /* Sign extend hi32 before calling load_register, because we can
9262 generally get better code when we load a sign extended value. */
9263 if ((hi32
.X_add_number
& 0x80000000) != 0)
9264 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9265 load_register (reg
, &hi32
, 0);
9268 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9272 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9280 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9282 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9283 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9289 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9293 mid16
.X_add_number
>>= 16;
9294 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9295 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9298 if ((lo32
.X_add_number
& 0xffff) != 0)
9299 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9303 load_delay_nop (void)
9305 if (!gpr_interlocks
)
9306 macro_build (NULL
, "nop", "");
9309 /* Load an address into a register. */
9312 load_address (int reg
, expressionS
*ep
, int *used_at
)
9314 if (ep
->X_op
!= O_constant
9315 && ep
->X_op
!= O_symbol
)
9317 as_bad (_("expression too complex"));
9318 ep
->X_op
= O_constant
;
9321 if (ep
->X_op
== O_constant
)
9323 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9327 if (mips_pic
== NO_PIC
)
9329 /* If this is a reference to a GP relative symbol, we want
9330 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9332 lui $reg,<sym> (BFD_RELOC_HI16_S)
9333 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9334 If we have an addend, we always use the latter form.
9336 With 64bit address space and a usable $at we want
9337 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9338 lui $at,<sym> (BFD_RELOC_HI16_S)
9339 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9340 daddiu $at,<sym> (BFD_RELOC_LO16)
9344 If $at is already in use, we use a path which is suboptimal
9345 on superscalar processors.
9346 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9347 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9349 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9351 daddiu $reg,<sym> (BFD_RELOC_LO16)
9353 For GP relative symbols in 64bit address space we can use
9354 the same sequence as in 32bit address space. */
9355 if (HAVE_64BIT_SYMBOLS
)
9357 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9358 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9360 relax_start (ep
->X_add_symbol
);
9361 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9362 mips_gp_register
, BFD_RELOC_GPREL16
);
9366 if (*used_at
== 0 && mips_opts
.at
)
9368 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9369 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9370 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9371 BFD_RELOC_MIPS_HIGHER
);
9372 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9373 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9374 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9379 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9380 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9381 BFD_RELOC_MIPS_HIGHER
);
9382 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9383 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9384 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9385 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9388 if (mips_relax
.sequence
)
9393 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9394 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9396 relax_start (ep
->X_add_symbol
);
9397 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9398 mips_gp_register
, BFD_RELOC_GPREL16
);
9401 macro_build_lui (ep
, reg
);
9402 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9403 reg
, reg
, BFD_RELOC_LO16
);
9404 if (mips_relax
.sequence
)
9408 else if (!mips_big_got
)
9412 /* If this is a reference to an external symbol, we want
9413 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9415 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9417 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9418 If there is a constant, it must be added in after.
9420 If we have NewABI, we want
9421 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9422 unless we're referencing a global symbol with a non-zero
9423 offset, in which case cst must be added separately. */
9426 if (ep
->X_add_number
)
9428 ex
.X_add_number
= ep
->X_add_number
;
9429 ep
->X_add_number
= 0;
9430 relax_start (ep
->X_add_symbol
);
9431 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9432 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9433 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9434 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9435 ex
.X_op
= O_constant
;
9436 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9437 reg
, reg
, BFD_RELOC_LO16
);
9438 ep
->X_add_number
= ex
.X_add_number
;
9441 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9442 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9443 if (mips_relax
.sequence
)
9448 ex
.X_add_number
= ep
->X_add_number
;
9449 ep
->X_add_number
= 0;
9450 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9451 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9453 relax_start (ep
->X_add_symbol
);
9455 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9459 if (ex
.X_add_number
!= 0)
9461 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9462 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9463 ex
.X_op
= O_constant
;
9464 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9465 reg
, reg
, BFD_RELOC_LO16
);
9469 else if (mips_big_got
)
9473 /* This is the large GOT case. If this is a reference to an
9474 external symbol, we want
9475 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9477 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9479 Otherwise, for a reference to a local symbol in old ABI, we want
9480 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9482 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9483 If there is a constant, it must be added in after.
9485 In the NewABI, for local symbols, with or without offsets, we want:
9486 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9487 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9491 ex
.X_add_number
= ep
->X_add_number
;
9492 ep
->X_add_number
= 0;
9493 relax_start (ep
->X_add_symbol
);
9494 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9495 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9496 reg
, reg
, mips_gp_register
);
9497 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9498 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9499 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9500 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9501 else if (ex
.X_add_number
)
9503 ex
.X_op
= O_constant
;
9504 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9508 ep
->X_add_number
= ex
.X_add_number
;
9510 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9511 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9512 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9513 BFD_RELOC_MIPS_GOT_OFST
);
9518 ex
.X_add_number
= ep
->X_add_number
;
9519 ep
->X_add_number
= 0;
9520 relax_start (ep
->X_add_symbol
);
9521 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9522 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9523 reg
, reg
, mips_gp_register
);
9524 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9525 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9527 if (reg_needs_delay (mips_gp_register
))
9529 /* We need a nop before loading from $gp. This special
9530 check is required because the lui which starts the main
9531 instruction stream does not refer to $gp, and so will not
9532 insert the nop which may be required. */
9533 macro_build (NULL
, "nop", "");
9535 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9536 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9538 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9542 if (ex
.X_add_number
!= 0)
9544 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9545 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9546 ex
.X_op
= O_constant
;
9547 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9555 if (!mips_opts
.at
&& *used_at
== 1)
9556 as_bad (_("macro used $at after \".set noat\""));
9559 /* Move the contents of register SOURCE into register DEST. */
9562 move_register (int dest
, int source
)
9564 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9565 instruction specifically requires a 32-bit one. */
9566 if (mips_opts
.micromips
9567 && !mips_opts
.insn32
9568 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9569 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9571 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9574 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9575 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9576 The two alternatives are:
9578 Global symbol Local symbol
9579 ------------- ------------
9580 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9582 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9584 load_got_offset emits the first instruction and add_got_offset
9585 emits the second for a 16-bit offset or add_got_offset_hilo emits
9586 a sequence to add a 32-bit offset using a scratch register. */
9589 load_got_offset (int dest
, expressionS
*local
)
9594 global
.X_add_number
= 0;
9596 relax_start (local
->X_add_symbol
);
9597 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9598 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9600 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9601 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9606 add_got_offset (int dest
, expressionS
*local
)
9610 global
.X_op
= O_constant
;
9611 global
.X_op_symbol
= NULL
;
9612 global
.X_add_symbol
= NULL
;
9613 global
.X_add_number
= local
->X_add_number
;
9615 relax_start (local
->X_add_symbol
);
9616 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9617 dest
, dest
, BFD_RELOC_LO16
);
9619 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9624 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9627 int hold_mips_optimize
;
9629 global
.X_op
= O_constant
;
9630 global
.X_op_symbol
= NULL
;
9631 global
.X_add_symbol
= NULL
;
9632 global
.X_add_number
= local
->X_add_number
;
9634 relax_start (local
->X_add_symbol
);
9635 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9637 /* Set mips_optimize around the lui instruction to avoid
9638 inserting an unnecessary nop after the lw. */
9639 hold_mips_optimize
= mips_optimize
;
9641 macro_build_lui (&global
, tmp
);
9642 mips_optimize
= hold_mips_optimize
;
9643 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9646 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9649 /* Emit a sequence of instructions to emulate a branch likely operation.
9650 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9651 is its complementing branch with the original condition negated.
9652 CALL is set if the original branch specified the link operation.
9653 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9655 Code like this is produced in the noreorder mode:
9660 delay slot (executed only if branch taken)
9668 delay slot (executed only if branch taken)
9671 In the reorder mode the delay slot would be filled with a nop anyway,
9672 so code produced is simply:
9677 This function is used when producing code for the microMIPS ASE that
9678 does not implement branch likely instructions in hardware. */
9681 macro_build_branch_likely (const char *br
, const char *brneg
,
9682 int call
, expressionS
*ep
, const char *fmt
,
9683 unsigned int sreg
, unsigned int treg
)
9685 int noreorder
= mips_opts
.noreorder
;
9688 gas_assert (mips_opts
.micromips
);
9692 micromips_label_expr (&expr1
);
9693 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9694 macro_build (NULL
, "nop", "");
9695 macro_build (ep
, call
? "bal" : "b", "p");
9697 /* Set to true so that append_insn adds a label. */
9698 emit_branch_likely_macro
= TRUE
;
9702 macro_build (ep
, br
, fmt
, sreg
, treg
);
9703 macro_build (NULL
, "nop", "");
9708 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9709 the condition code tested. EP specifies the branch target. */
9712 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9739 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9742 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9743 the register tested. EP specifies the branch target. */
9746 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9748 const char *brneg
= NULL
;
9758 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9762 gas_assert (mips_opts
.micromips
);
9763 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9771 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9778 br
= mips_opts
.micromips
? "blez" : "blezl";
9785 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9789 gas_assert (mips_opts
.micromips
);
9790 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9797 if (mips_opts
.micromips
&& brneg
)
9798 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9800 macro_build (ep
, br
, "s,p", sreg
);
9803 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9804 TREG as the registers tested. EP specifies the branch target. */
9807 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9808 unsigned int sreg
, unsigned int treg
)
9810 const char *brneg
= NULL
;
9822 br
= mips_opts
.micromips
? "beq" : "beql";
9831 br
= mips_opts
.micromips
? "bne" : "bnel";
9837 if (mips_opts
.micromips
&& brneg
)
9838 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9840 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9843 /* Return the high part that should be loaded in order to make the low
9844 part of VALUE accessible using an offset of OFFBITS bits. */
9847 offset_high_part (offsetT value
, unsigned int offbits
)
9854 bias
= 1 << (offbits
- 1);
9855 low_mask
= bias
* 2 - 1;
9856 return (value
+ bias
) & ~low_mask
;
9859 /* Return true if the value stored in offset_expr and offset_reloc
9860 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9861 amount that the caller wants to add without inducing overflow
9862 and ALIGN is the known alignment of the value in bytes. */
9865 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9869 /* Accept any relocation operator if overflow isn't a concern. */
9870 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9873 /* These relocations are guaranteed not to overflow in correct links. */
9874 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9875 || gprel16_reloc_p (*offset_reloc
))
9878 if (offset_expr
.X_op
== O_constant
9879 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9880 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9887 * This routine implements the seemingly endless macro or synthesized
9888 * instructions and addressing modes in the mips assembly language. Many
9889 * of these macros are simple and are similar to each other. These could
9890 * probably be handled by some kind of table or grammar approach instead of
9891 * this verbose method. Others are not simple macros but are more like
9892 * optimizing code generation.
9893 * One interesting optimization is when several store macros appear
9894 * consecutively that would load AT with the upper half of the same address.
9895 * The ensuing load upper instructions are omitted. This implies some kind
9896 * of global optimization. We currently only optimize within a single macro.
9897 * For many of the load and store macros if the address is specified as a
9898 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9899 * first load register 'at' with zero and use it as the base register. The
9900 * mips assembler simply uses register $zero. Just one tiny optimization
9904 macro (struct mips_cl_insn
*ip
, char *str
)
9906 const struct mips_operand_array
*operands
;
9907 unsigned int breg
, i
;
9908 unsigned int tempreg
;
9911 expressionS label_expr
;
9926 bfd_boolean large_offset
;
9928 int hold_mips_optimize
;
9930 unsigned int op
[MAX_OPERANDS
];
9932 gas_assert (! mips_opts
.mips16
);
9934 operands
= insn_operands (ip
);
9935 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9936 if (operands
->operand
[i
])
9937 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9941 mask
= ip
->insn_mo
->mask
;
9943 label_expr
.X_op
= O_constant
;
9944 label_expr
.X_op_symbol
= NULL
;
9945 label_expr
.X_add_symbol
= NULL
;
9946 label_expr
.X_add_number
= 0;
9948 expr1
.X_op
= O_constant
;
9949 expr1
.X_op_symbol
= NULL
;
9950 expr1
.X_add_symbol
= NULL
;
9951 expr1
.X_add_number
= 1;
9968 if (mips_opts
.micromips
)
9969 micromips_label_expr (&label_expr
);
9971 label_expr
.X_add_number
= 8;
9972 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9974 macro_build (NULL
, "nop", "");
9976 move_register (op
[0], op
[1]);
9977 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9978 if (mips_opts
.micromips
)
9979 micromips_add_label ();
9996 if (!mips_opts
.micromips
)
9998 if (imm_expr
.X_add_number
>= -0x200
9999 && imm_expr
.X_add_number
< 0x200)
10001 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10002 (int) imm_expr
.X_add_number
);
10011 if (imm_expr
.X_add_number
>= -0x8000
10012 && imm_expr
.X_add_number
< 0x8000)
10014 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10019 load_register (AT
, &imm_expr
, dbl
);
10020 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10039 if (imm_expr
.X_add_number
>= 0
10040 && imm_expr
.X_add_number
< 0x10000)
10042 if (mask
!= M_NOR_I
)
10043 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10046 macro_build (&imm_expr
, "ori", "t,r,i",
10047 op
[0], op
[1], BFD_RELOC_LO16
);
10048 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10054 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10055 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10059 switch (imm_expr
.X_add_number
)
10062 macro_build (NULL
, "nop", "");
10065 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10069 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10070 (int) imm_expr
.X_add_number
);
10073 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10074 (unsigned long) imm_expr
.X_add_number
);
10083 gas_assert (mips_opts
.micromips
);
10084 macro_build_branch_ccl (mask
, &offset_expr
,
10085 EXTRACT_OPERAND (1, BCC
, *ip
));
10092 if (imm_expr
.X_add_number
== 0)
10098 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10100 /* Fall through. */
10103 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10108 /* Fall through. */
10111 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10112 else if (op
[0] == 0)
10113 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10117 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10118 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10119 &offset_expr
, AT
, ZERO
);
10129 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10134 /* Fall through. */
10136 /* Check for > max integer. */
10137 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10140 /* Result is always false. */
10142 macro_build (NULL
, "nop", "");
10144 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10147 ++imm_expr
.X_add_number
;
10151 if (mask
== M_BGEL_I
)
10153 if (imm_expr
.X_add_number
== 0)
10155 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10156 &offset_expr
, op
[0]);
10159 if (imm_expr
.X_add_number
== 1)
10161 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10162 &offset_expr
, op
[0]);
10165 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10168 /* result is always true */
10169 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10170 macro_build (&offset_expr
, "b", "p");
10175 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10176 &offset_expr
, AT
, ZERO
);
10181 /* Fall through. */
10185 else if (op
[0] == 0)
10186 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10187 &offset_expr
, ZERO
, op
[1]);
10191 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10192 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10193 &offset_expr
, AT
, ZERO
);
10199 /* Fall through. */
10203 && imm_expr
.X_add_number
== -1))
10205 ++imm_expr
.X_add_number
;
10209 if (mask
== M_BGEUL_I
)
10211 if (imm_expr
.X_add_number
== 0)
10213 else if (imm_expr
.X_add_number
== 1)
10214 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10215 &offset_expr
, op
[0], ZERO
);
10220 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10221 &offset_expr
, AT
, ZERO
);
10227 /* Fall through. */
10230 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10231 else if (op
[0] == 0)
10232 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10236 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10237 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10238 &offset_expr
, AT
, ZERO
);
10244 /* Fall through. */
10247 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10248 &offset_expr
, op
[0], ZERO
);
10249 else if (op
[0] == 0)
10254 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10255 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10256 &offset_expr
, AT
, ZERO
);
10262 /* Fall through. */
10265 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10266 else if (op
[0] == 0)
10267 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10271 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10272 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10273 &offset_expr
, AT
, ZERO
);
10279 /* Fall through. */
10281 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10283 ++imm_expr
.X_add_number
;
10287 if (mask
== M_BLTL_I
)
10289 if (imm_expr
.X_add_number
== 0)
10290 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10291 else if (imm_expr
.X_add_number
== 1)
10292 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10297 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10298 &offset_expr
, AT
, ZERO
);
10304 /* Fall through. */
10307 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10308 &offset_expr
, op
[0], ZERO
);
10309 else if (op
[0] == 0)
10314 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10315 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10316 &offset_expr
, AT
, ZERO
);
10322 /* Fall through. */
10326 && imm_expr
.X_add_number
== -1))
10328 ++imm_expr
.X_add_number
;
10332 if (mask
== M_BLTUL_I
)
10334 if (imm_expr
.X_add_number
== 0)
10336 else if (imm_expr
.X_add_number
== 1)
10337 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10338 &offset_expr
, op
[0], ZERO
);
10343 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10344 &offset_expr
, AT
, ZERO
);
10350 /* Fall through. */
10353 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10354 else if (op
[0] == 0)
10355 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10359 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10360 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10361 &offset_expr
, AT
, ZERO
);
10367 /* Fall through. */
10371 else if (op
[0] == 0)
10372 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10373 &offset_expr
, ZERO
, op
[1]);
10377 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10378 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10379 &offset_expr
, AT
, ZERO
);
10385 /* Fall through. */
10391 /* Fall through. */
10397 as_warn (_("divide by zero"));
10399 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10401 macro_build (NULL
, "break", BRK_FMT
, 7);
10405 start_noreorder ();
10408 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10409 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10413 if (mips_opts
.micromips
)
10414 micromips_label_expr (&label_expr
);
10416 label_expr
.X_add_number
= 8;
10417 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10418 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10419 macro_build (NULL
, "break", BRK_FMT
, 7);
10420 if (mips_opts
.micromips
)
10421 micromips_add_label ();
10423 expr1
.X_add_number
= -1;
10425 load_register (AT
, &expr1
, dbl
);
10426 if (mips_opts
.micromips
)
10427 micromips_label_expr (&label_expr
);
10429 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10430 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10433 expr1
.X_add_number
= 1;
10434 load_register (AT
, &expr1
, dbl
);
10435 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10439 expr1
.X_add_number
= 0x80000000;
10440 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10444 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10445 /* We want to close the noreorder block as soon as possible, so
10446 that later insns are available for delay slot filling. */
10451 if (mips_opts
.micromips
)
10452 micromips_label_expr (&label_expr
);
10454 label_expr
.X_add_number
= 8;
10455 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10456 macro_build (NULL
, "nop", "");
10458 /* We want to close the noreorder block as soon as possible, so
10459 that later insns are available for delay slot filling. */
10462 macro_build (NULL
, "break", BRK_FMT
, 6);
10464 if (mips_opts
.micromips
)
10465 micromips_add_label ();
10466 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10505 if (imm_expr
.X_add_number
== 0)
10507 as_warn (_("divide by zero"));
10509 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10511 macro_build (NULL
, "break", BRK_FMT
, 7);
10514 if (imm_expr
.X_add_number
== 1)
10516 if (strcmp (s2
, "mflo") == 0)
10517 move_register (op
[0], op
[1]);
10519 move_register (op
[0], ZERO
);
10522 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10524 if (strcmp (s2
, "mflo") == 0)
10525 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10527 move_register (op
[0], ZERO
);
10532 load_register (AT
, &imm_expr
, dbl
);
10533 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10534 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10553 start_noreorder ();
10556 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10557 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10558 /* We want to close the noreorder block as soon as possible, so
10559 that later insns are available for delay slot filling. */
10564 if (mips_opts
.micromips
)
10565 micromips_label_expr (&label_expr
);
10567 label_expr
.X_add_number
= 8;
10568 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10569 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10571 /* We want to close the noreorder block as soon as possible, so
10572 that later insns are available for delay slot filling. */
10574 macro_build (NULL
, "break", BRK_FMT
, 7);
10575 if (mips_opts
.micromips
)
10576 micromips_add_label ();
10578 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10583 /* Fall through. */
10589 /* Fall through. */
10592 /* Load the address of a symbol into a register. If breg is not
10593 zero, we then add a base register to it. */
10596 if (dbl
&& GPR_SIZE
== 32)
10597 as_warn (_("dla used to load 32-bit register; recommend using la "
10600 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10601 as_warn (_("la used to load 64-bit address; recommend using dla "
10604 if (small_offset_p (0, align
, 16))
10606 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10607 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10611 if (mips_opts
.at
&& (op
[0] == breg
))
10619 if (offset_expr
.X_op
!= O_symbol
10620 && offset_expr
.X_op
!= O_constant
)
10622 as_bad (_("expression too complex"));
10623 offset_expr
.X_op
= O_constant
;
10626 if (offset_expr
.X_op
== O_constant
)
10627 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10628 else if (mips_pic
== NO_PIC
)
10630 /* If this is a reference to a GP relative symbol, we want
10631 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10633 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10634 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10635 If we have a constant, we need two instructions anyhow,
10636 so we may as well always use the latter form.
10638 With 64bit address space and a usable $at we want
10639 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10640 lui $at,<sym> (BFD_RELOC_HI16_S)
10641 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10642 daddiu $at,<sym> (BFD_RELOC_LO16)
10644 daddu $tempreg,$tempreg,$at
10646 If $at is already in use, we use a path which is suboptimal
10647 on superscalar processors.
10648 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10649 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10651 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10653 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10655 For GP relative symbols in 64bit address space we can use
10656 the same sequence as in 32bit address space. */
10657 if (HAVE_64BIT_SYMBOLS
)
10659 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10660 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10662 relax_start (offset_expr
.X_add_symbol
);
10663 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10664 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10668 if (used_at
== 0 && mips_opts
.at
)
10670 macro_build (&offset_expr
, "lui", LUI_FMT
,
10671 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10672 macro_build (&offset_expr
, "lui", LUI_FMT
,
10673 AT
, BFD_RELOC_HI16_S
);
10674 macro_build (&offset_expr
, "daddiu", "t,r,j",
10675 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10676 macro_build (&offset_expr
, "daddiu", "t,r,j",
10677 AT
, AT
, BFD_RELOC_LO16
);
10678 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10679 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10684 macro_build (&offset_expr
, "lui", LUI_FMT
,
10685 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10686 macro_build (&offset_expr
, "daddiu", "t,r,j",
10687 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10688 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10689 macro_build (&offset_expr
, "daddiu", "t,r,j",
10690 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10691 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10692 macro_build (&offset_expr
, "daddiu", "t,r,j",
10693 tempreg
, tempreg
, BFD_RELOC_LO16
);
10696 if (mips_relax
.sequence
)
10701 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10702 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10704 relax_start (offset_expr
.X_add_symbol
);
10705 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10706 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10709 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10710 as_bad (_("offset too large"));
10711 macro_build_lui (&offset_expr
, tempreg
);
10712 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10713 tempreg
, tempreg
, BFD_RELOC_LO16
);
10714 if (mips_relax
.sequence
)
10718 else if (!mips_big_got
&& !HAVE_NEWABI
)
10720 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10722 /* If this is a reference to an external symbol, and there
10723 is no constant, we want
10724 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10725 or for lca or if tempreg is PIC_CALL_REG
10726 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10727 For a local symbol, we want
10728 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10730 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10732 If we have a small constant, and this is a reference to
10733 an external symbol, we want
10734 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10736 addiu $tempreg,$tempreg,<constant>
10737 For a local symbol, we want the same instruction
10738 sequence, but we output a BFD_RELOC_LO16 reloc on the
10741 If we have a large constant, and this is a reference to
10742 an external symbol, we want
10743 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10744 lui $at,<hiconstant>
10745 addiu $at,$at,<loconstant>
10746 addu $tempreg,$tempreg,$at
10747 For a local symbol, we want the same instruction
10748 sequence, but we output a BFD_RELOC_LO16 reloc on the
10752 if (offset_expr
.X_add_number
== 0)
10754 if (mips_pic
== SVR4_PIC
10756 && (call
|| tempreg
== PIC_CALL_REG
))
10757 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10759 relax_start (offset_expr
.X_add_symbol
);
10760 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10761 lw_reloc_type
, mips_gp_register
);
10764 /* We're going to put in an addu instruction using
10765 tempreg, so we may as well insert the nop right
10770 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10771 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10773 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10774 tempreg
, tempreg
, BFD_RELOC_LO16
);
10776 /* FIXME: If breg == 0, and the next instruction uses
10777 $tempreg, then if this variant case is used an extra
10778 nop will be generated. */
10780 else if (offset_expr
.X_add_number
>= -0x8000
10781 && offset_expr
.X_add_number
< 0x8000)
10783 load_got_offset (tempreg
, &offset_expr
);
10785 add_got_offset (tempreg
, &offset_expr
);
10789 expr1
.X_add_number
= offset_expr
.X_add_number
;
10790 offset_expr
.X_add_number
=
10791 SEXT_16BIT (offset_expr
.X_add_number
);
10792 load_got_offset (tempreg
, &offset_expr
);
10793 offset_expr
.X_add_number
= expr1
.X_add_number
;
10794 /* If we are going to add in a base register, and the
10795 target register and the base register are the same,
10796 then we are using AT as a temporary register. Since
10797 we want to load the constant into AT, we add our
10798 current AT (from the global offset table) and the
10799 register into the register now, and pretend we were
10800 not using a base register. */
10804 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10809 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10813 else if (!mips_big_got
&& HAVE_NEWABI
)
10815 int add_breg_early
= 0;
10817 /* If this is a reference to an external, and there is no
10818 constant, or local symbol (*), with or without a
10820 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10821 or for lca or if tempreg is PIC_CALL_REG
10822 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10824 If we have a small constant, and this is a reference to
10825 an external symbol, we want
10826 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10827 addiu $tempreg,$tempreg,<constant>
10829 If we have a large constant, and this is a reference to
10830 an external symbol, we want
10831 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10832 lui $at,<hiconstant>
10833 addiu $at,$at,<loconstant>
10834 addu $tempreg,$tempreg,$at
10836 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10837 local symbols, even though it introduces an additional
10840 if (offset_expr
.X_add_number
)
10842 expr1
.X_add_number
= offset_expr
.X_add_number
;
10843 offset_expr
.X_add_number
= 0;
10845 relax_start (offset_expr
.X_add_symbol
);
10846 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10847 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10849 if (expr1
.X_add_number
>= -0x8000
10850 && expr1
.X_add_number
< 0x8000)
10852 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10853 tempreg
, tempreg
, BFD_RELOC_LO16
);
10855 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10859 /* If we are going to add in a base register, and the
10860 target register and the base register are the same,
10861 then we are using AT as a temporary register. Since
10862 we want to load the constant into AT, we add our
10863 current AT (from the global offset table) and the
10864 register into the register now, and pretend we were
10865 not using a base register. */
10870 gas_assert (tempreg
== AT
);
10871 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10874 add_breg_early
= 1;
10877 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10878 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10884 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10887 offset_expr
.X_add_number
= expr1
.X_add_number
;
10889 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10890 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10891 if (add_breg_early
)
10893 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10894 op
[0], tempreg
, breg
);
10900 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10902 relax_start (offset_expr
.X_add_symbol
);
10903 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10904 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10906 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10907 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10912 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10913 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10916 else if (mips_big_got
&& !HAVE_NEWABI
)
10919 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10920 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10921 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10923 /* This is the large GOT case. If this is a reference to an
10924 external symbol, and there is no constant, we want
10925 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10926 addu $tempreg,$tempreg,$gp
10927 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10928 or for lca or if tempreg is PIC_CALL_REG
10929 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10930 addu $tempreg,$tempreg,$gp
10931 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10932 For a local symbol, we want
10933 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10935 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10937 If we have a small constant, and this is a reference to
10938 an external symbol, we want
10939 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10940 addu $tempreg,$tempreg,$gp
10941 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10943 addiu $tempreg,$tempreg,<constant>
10944 For a local symbol, we want
10945 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10947 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10949 If we have a large constant, and this is a reference to
10950 an external symbol, we want
10951 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10952 addu $tempreg,$tempreg,$gp
10953 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10954 lui $at,<hiconstant>
10955 addiu $at,$at,<loconstant>
10956 addu $tempreg,$tempreg,$at
10957 For a local symbol, we want
10958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10959 lui $at,<hiconstant>
10960 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10961 addu $tempreg,$tempreg,$at
10964 expr1
.X_add_number
= offset_expr
.X_add_number
;
10965 offset_expr
.X_add_number
= 0;
10966 relax_start (offset_expr
.X_add_symbol
);
10967 gpdelay
= reg_needs_delay (mips_gp_register
);
10968 if (expr1
.X_add_number
== 0 && breg
== 0
10969 && (call
|| tempreg
== PIC_CALL_REG
))
10971 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10972 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10974 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10975 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10976 tempreg
, tempreg
, mips_gp_register
);
10977 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10978 tempreg
, lw_reloc_type
, tempreg
);
10979 if (expr1
.X_add_number
== 0)
10983 /* We're going to put in an addu instruction using
10984 tempreg, so we may as well insert the nop right
10989 else if (expr1
.X_add_number
>= -0x8000
10990 && expr1
.X_add_number
< 0x8000)
10993 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10994 tempreg
, tempreg
, BFD_RELOC_LO16
);
11000 /* If we are going to add in a base register, and the
11001 target register and the base register are the same,
11002 then we are using AT as a temporary register. Since
11003 we want to load the constant into AT, we add our
11004 current AT (from the global offset table) and the
11005 register into the register now, and pretend we were
11006 not using a base register. */
11011 gas_assert (tempreg
== AT
);
11013 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11018 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11019 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11023 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11028 /* This is needed because this instruction uses $gp, but
11029 the first instruction on the main stream does not. */
11030 macro_build (NULL
, "nop", "");
11033 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11034 local_reloc_type
, mips_gp_register
);
11035 if (expr1
.X_add_number
>= -0x8000
11036 && expr1
.X_add_number
< 0x8000)
11039 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11040 tempreg
, tempreg
, BFD_RELOC_LO16
);
11041 /* FIXME: If add_number is 0, and there was no base
11042 register, the external symbol case ended with a load,
11043 so if the symbol turns out to not be external, and
11044 the next instruction uses tempreg, an unnecessary nop
11045 will be inserted. */
11051 /* We must add in the base register now, as in the
11052 external symbol case. */
11053 gas_assert (tempreg
== AT
);
11055 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11058 /* We set breg to 0 because we have arranged to add
11059 it in in both cases. */
11063 macro_build_lui (&expr1
, AT
);
11064 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11065 AT
, AT
, BFD_RELOC_LO16
);
11066 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11067 tempreg
, tempreg
, AT
);
11072 else if (mips_big_got
&& HAVE_NEWABI
)
11074 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11075 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11076 int add_breg_early
= 0;
11078 /* This is the large GOT case. If this is a reference to an
11079 external symbol, and there is no constant, we want
11080 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11081 add $tempreg,$tempreg,$gp
11082 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11083 or for lca or if tempreg is PIC_CALL_REG
11084 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11085 add $tempreg,$tempreg,$gp
11086 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11088 If we have a small constant, and this is a reference to
11089 an external symbol, we want
11090 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11091 add $tempreg,$tempreg,$gp
11092 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11093 addi $tempreg,$tempreg,<constant>
11095 If we have a large constant, and this is a reference to
11096 an external symbol, we want
11097 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11098 addu $tempreg,$tempreg,$gp
11099 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11100 lui $at,<hiconstant>
11101 addi $at,$at,<loconstant>
11102 add $tempreg,$tempreg,$at
11104 If we have NewABI, and we know it's a local symbol, we want
11105 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11106 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11107 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11109 relax_start (offset_expr
.X_add_symbol
);
11111 expr1
.X_add_number
= offset_expr
.X_add_number
;
11112 offset_expr
.X_add_number
= 0;
11114 if (expr1
.X_add_number
== 0 && breg
== 0
11115 && (call
|| tempreg
== PIC_CALL_REG
))
11117 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11118 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11120 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11121 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11122 tempreg
, tempreg
, mips_gp_register
);
11123 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11124 tempreg
, lw_reloc_type
, tempreg
);
11126 if (expr1
.X_add_number
== 0)
11128 else if (expr1
.X_add_number
>= -0x8000
11129 && expr1
.X_add_number
< 0x8000)
11131 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11132 tempreg
, tempreg
, BFD_RELOC_LO16
);
11134 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11138 /* If we are going to add in a base register, and the
11139 target register and the base register are the same,
11140 then we are using AT as a temporary register. Since
11141 we want to load the constant into AT, we add our
11142 current AT (from the global offset table) and the
11143 register into the register now, and pretend we were
11144 not using a base register. */
11149 gas_assert (tempreg
== AT
);
11150 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11153 add_breg_early
= 1;
11156 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11157 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11162 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11165 offset_expr
.X_add_number
= expr1
.X_add_number
;
11166 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11167 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11168 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11169 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11170 if (add_breg_early
)
11172 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11173 op
[0], tempreg
, breg
);
11183 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11187 gas_assert (!mips_opts
.micromips
);
11188 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11192 gas_assert (!mips_opts
.micromips
);
11193 macro_build (NULL
, "c2", "C", 0x02);
11197 gas_assert (!mips_opts
.micromips
);
11198 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11202 gas_assert (!mips_opts
.micromips
);
11203 macro_build (NULL
, "c2", "C", 3);
11207 gas_assert (!mips_opts
.micromips
);
11208 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11212 /* The j instruction may not be used in PIC code, since it
11213 requires an absolute address. We convert it to a b
11215 if (mips_pic
== NO_PIC
)
11216 macro_build (&offset_expr
, "j", "a");
11218 macro_build (&offset_expr
, "b", "p");
11221 /* The jal instructions must be handled as macros because when
11222 generating PIC code they expand to multi-instruction
11223 sequences. Normally they are simple instructions. */
11227 /* Fall through. */
11229 gas_assert (mips_opts
.micromips
);
11230 if (mips_opts
.insn32
)
11232 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11240 /* Fall through. */
11243 if (mips_pic
== NO_PIC
)
11245 s
= jals
? "jalrs" : "jalr";
11246 if (mips_opts
.micromips
11247 && !mips_opts
.insn32
11249 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11250 macro_build (NULL
, s
, "mj", op
[1]);
11252 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11256 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11257 && mips_cprestore_offset
>= 0);
11259 if (op
[1] != PIC_CALL_REG
)
11260 as_warn (_("MIPS PIC call to register other than $25"));
11262 s
= ((mips_opts
.micromips
11263 && !mips_opts
.insn32
11264 && (!mips_opts
.noreorder
|| cprestore
))
11265 ? "jalrs" : "jalr");
11266 if (mips_opts
.micromips
11267 && !mips_opts
.insn32
11269 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11270 macro_build (NULL
, s
, "mj", op
[1]);
11272 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11273 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11275 if (mips_cprestore_offset
< 0)
11276 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11279 if (!mips_frame_reg_valid
)
11281 as_warn (_("no .frame pseudo-op used in PIC code"));
11282 /* Quiet this warning. */
11283 mips_frame_reg_valid
= 1;
11285 if (!mips_cprestore_valid
)
11287 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11288 /* Quiet this warning. */
11289 mips_cprestore_valid
= 1;
11291 if (mips_opts
.noreorder
)
11292 macro_build (NULL
, "nop", "");
11293 expr1
.X_add_number
= mips_cprestore_offset
;
11294 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11297 HAVE_64BIT_ADDRESSES
);
11305 gas_assert (mips_opts
.micromips
);
11306 if (mips_opts
.insn32
)
11308 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11312 /* Fall through. */
11314 if (mips_pic
== NO_PIC
)
11315 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11316 else if (mips_pic
== SVR4_PIC
)
11318 /* If this is a reference to an external symbol, and we are
11319 using a small GOT, we want
11320 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11324 lw $gp,cprestore($sp)
11325 The cprestore value is set using the .cprestore
11326 pseudo-op. If we are using a big GOT, we want
11327 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11329 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11333 lw $gp,cprestore($sp)
11334 If the symbol is not external, we want
11335 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11337 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11340 lw $gp,cprestore($sp)
11342 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11343 sequences above, minus nops, unless the symbol is local,
11344 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11350 relax_start (offset_expr
.X_add_symbol
);
11351 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11352 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11355 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11356 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11362 relax_start (offset_expr
.X_add_symbol
);
11363 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11364 BFD_RELOC_MIPS_CALL_HI16
);
11365 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11366 PIC_CALL_REG
, mips_gp_register
);
11367 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11368 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11371 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11372 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11374 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11375 PIC_CALL_REG
, PIC_CALL_REG
,
11376 BFD_RELOC_MIPS_GOT_OFST
);
11380 macro_build_jalr (&offset_expr
, 0);
11384 relax_start (offset_expr
.X_add_symbol
);
11387 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11388 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11397 gpdelay
= reg_needs_delay (mips_gp_register
);
11398 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11399 BFD_RELOC_MIPS_CALL_HI16
);
11400 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11401 PIC_CALL_REG
, mips_gp_register
);
11402 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11403 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11408 macro_build (NULL
, "nop", "");
11410 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11411 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11414 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11415 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11417 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11419 if (mips_cprestore_offset
< 0)
11420 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11423 if (!mips_frame_reg_valid
)
11425 as_warn (_("no .frame pseudo-op used in PIC code"));
11426 /* Quiet this warning. */
11427 mips_frame_reg_valid
= 1;
11429 if (!mips_cprestore_valid
)
11431 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11432 /* Quiet this warning. */
11433 mips_cprestore_valid
= 1;
11435 if (mips_opts
.noreorder
)
11436 macro_build (NULL
, "nop", "");
11437 expr1
.X_add_number
= mips_cprestore_offset
;
11438 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11441 HAVE_64BIT_ADDRESSES
);
11445 else if (mips_pic
== VXWORKS_PIC
)
11446 as_bad (_("non-PIC jump used in PIC library"));
11553 gas_assert (!mips_opts
.micromips
);
11556 /* Itbl support may require additional care here. */
11562 /* Itbl support may require additional care here. */
11568 offbits
= (mips_opts
.micromips
? 12
11569 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11571 /* Itbl support may require additional care here. */
11575 gas_assert (!mips_opts
.micromips
);
11578 /* Itbl support may require additional care here. */
11584 offbits
= (mips_opts
.micromips
? 12 : 16);
11589 offbits
= (mips_opts
.micromips
? 12 : 16);
11594 /* Itbl support may require additional care here. */
11600 offbits
= (mips_opts
.micromips
? 12
11601 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11603 /* Itbl support may require additional care here. */
11609 /* Itbl support may require additional care here. */
11615 /* Itbl support may require additional care here. */
11621 offbits
= (mips_opts
.micromips
? 12 : 16);
11626 offbits
= (mips_opts
.micromips
? 12 : 16);
11631 offbits
= (mips_opts
.micromips
? 12
11632 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11638 offbits
= (mips_opts
.micromips
? 12
11639 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11645 offbits
= (mips_opts
.micromips
? 12 : 16);
11648 gas_assert (mips_opts
.micromips
);
11655 gas_assert (mips_opts
.micromips
);
11662 gas_assert (mips_opts
.micromips
);
11668 gas_assert (mips_opts
.micromips
);
11675 /* We don't want to use $0 as tempreg. */
11676 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11679 tempreg
= op
[0] + lp
;
11695 gas_assert (!mips_opts
.micromips
);
11698 /* Itbl support may require additional care here. */
11704 /* Itbl support may require additional care here. */
11710 offbits
= (mips_opts
.micromips
? 12
11711 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11713 /* Itbl support may require additional care here. */
11717 gas_assert (!mips_opts
.micromips
);
11720 /* Itbl support may require additional care here. */
11726 offbits
= (mips_opts
.micromips
? 12 : 16);
11731 offbits
= (mips_opts
.micromips
? 12 : 16);
11736 offbits
= (mips_opts
.micromips
? 12
11737 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11743 offbits
= (mips_opts
.micromips
? 12
11744 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11749 fmt
= (mips_opts
.micromips
? "k,~(b)"
11750 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11752 offbits
= (mips_opts
.micromips
? 12
11753 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11763 fmt
= (mips_opts
.micromips
? "k,~(b)"
11764 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11766 offbits
= (mips_opts
.micromips
? 12
11767 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11779 /* Itbl support may require additional care here. */
11784 offbits
= (mips_opts
.micromips
? 12
11785 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11787 /* Itbl support may require additional care here. */
11793 /* Itbl support may require additional care here. */
11797 gas_assert (!mips_opts
.micromips
);
11800 /* Itbl support may require additional care here. */
11806 offbits
= (mips_opts
.micromips
? 12 : 16);
11811 offbits
= (mips_opts
.micromips
? 12 : 16);
11814 gas_assert (mips_opts
.micromips
);
11820 gas_assert (mips_opts
.micromips
);
11826 gas_assert (mips_opts
.micromips
);
11832 gas_assert (mips_opts
.micromips
);
11841 if (small_offset_p (0, align
, 16))
11843 /* The first case exists for M_LD_AB and M_SD_AB, which are
11844 macros for o32 but which should act like normal instructions
11847 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11848 offset_reloc
[1], offset_reloc
[2], breg
);
11849 else if (small_offset_p (0, align
, offbits
))
11852 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11854 macro_build (NULL
, s
, fmt
, op
[0],
11855 (int) offset_expr
.X_add_number
, breg
);
11861 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11862 tempreg
, breg
, -1, offset_reloc
[0],
11863 offset_reloc
[1], offset_reloc
[2]);
11865 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11867 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11875 if (offset_expr
.X_op
!= O_constant
11876 && offset_expr
.X_op
!= O_symbol
)
11878 as_bad (_("expression too complex"));
11879 offset_expr
.X_op
= O_constant
;
11882 if (HAVE_32BIT_ADDRESSES
11883 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11887 sprintf_vma (value
, offset_expr
.X_add_number
);
11888 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11891 /* A constant expression in PIC code can be handled just as it
11892 is in non PIC code. */
11893 if (offset_expr
.X_op
== O_constant
)
11895 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11896 offbits
== 0 ? 16 : offbits
);
11897 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11899 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11901 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11902 tempreg
, tempreg
, breg
);
11905 if (offset_expr
.X_add_number
!= 0)
11906 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11907 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11908 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11910 else if (offbits
== 16)
11911 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11913 macro_build (NULL
, s
, fmt
, op
[0],
11914 (int) offset_expr
.X_add_number
, tempreg
);
11916 else if (offbits
!= 16)
11918 /* The offset field is too narrow to be used for a low-part
11919 relocation, so load the whole address into the auxiliary
11921 load_address (tempreg
, &offset_expr
, &used_at
);
11923 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11924 tempreg
, tempreg
, breg
);
11926 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11928 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11930 else if (mips_pic
== NO_PIC
)
11932 /* If this is a reference to a GP relative symbol, and there
11933 is no base register, we want
11934 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11935 Otherwise, if there is no base register, we want
11936 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11937 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11938 If we have a constant, we need two instructions anyhow,
11939 so we always use the latter form.
11941 If we have a base register, and this is a reference to a
11942 GP relative symbol, we want
11943 addu $tempreg,$breg,$gp
11944 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11946 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11947 addu $tempreg,$tempreg,$breg
11948 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11949 With a constant we always use the latter case.
11951 With 64bit address space and no base register and $at usable,
11953 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11954 lui $at,<sym> (BFD_RELOC_HI16_S)
11955 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11958 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11959 If we have a base register, we want
11960 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11961 lui $at,<sym> (BFD_RELOC_HI16_S)
11962 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11966 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11968 Without $at we can't generate the optimal path for superscalar
11969 processors here since this would require two temporary registers.
11970 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11971 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11973 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11975 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11976 If we have a base register, we want
11977 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11978 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11980 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11982 daddu $tempreg,$tempreg,$breg
11983 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11985 For GP relative symbols in 64bit address space we can use
11986 the same sequence as in 32bit address space. */
11987 if (HAVE_64BIT_SYMBOLS
)
11989 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11990 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11992 relax_start (offset_expr
.X_add_symbol
);
11995 macro_build (&offset_expr
, s
, fmt
, op
[0],
11996 BFD_RELOC_GPREL16
, mips_gp_register
);
12000 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12001 tempreg
, breg
, mips_gp_register
);
12002 macro_build (&offset_expr
, s
, fmt
, op
[0],
12003 BFD_RELOC_GPREL16
, tempreg
);
12008 if (used_at
== 0 && mips_opts
.at
)
12010 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12011 BFD_RELOC_MIPS_HIGHEST
);
12012 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12014 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12015 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12017 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12018 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12019 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12020 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12026 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12027 BFD_RELOC_MIPS_HIGHEST
);
12028 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12029 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12030 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12031 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12032 tempreg
, BFD_RELOC_HI16_S
);
12033 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12035 macro_build (NULL
, "daddu", "d,v,t",
12036 tempreg
, tempreg
, breg
);
12037 macro_build (&offset_expr
, s
, fmt
, op
[0],
12038 BFD_RELOC_LO16
, tempreg
);
12041 if (mips_relax
.sequence
)
12048 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12049 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12051 relax_start (offset_expr
.X_add_symbol
);
12052 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12056 macro_build_lui (&offset_expr
, tempreg
);
12057 macro_build (&offset_expr
, s
, fmt
, op
[0],
12058 BFD_RELOC_LO16
, tempreg
);
12059 if (mips_relax
.sequence
)
12064 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12065 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12067 relax_start (offset_expr
.X_add_symbol
);
12068 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12069 tempreg
, breg
, mips_gp_register
);
12070 macro_build (&offset_expr
, s
, fmt
, op
[0],
12071 BFD_RELOC_GPREL16
, tempreg
);
12074 macro_build_lui (&offset_expr
, tempreg
);
12075 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12076 tempreg
, tempreg
, breg
);
12077 macro_build (&offset_expr
, s
, fmt
, op
[0],
12078 BFD_RELOC_LO16
, tempreg
);
12079 if (mips_relax
.sequence
)
12083 else if (!mips_big_got
)
12085 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12087 /* If this is a reference to an external symbol, we want
12088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12090 <op> op[0],0($tempreg)
12092 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12094 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12095 <op> op[0],0($tempreg)
12097 For NewABI, we want
12098 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12099 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12101 If there is a base register, we add it to $tempreg before
12102 the <op>. If there is a constant, we stick it in the
12103 <op> instruction. We don't handle constants larger than
12104 16 bits, because we have no way to load the upper 16 bits
12105 (actually, we could handle them for the subset of cases
12106 in which we are not using $at). */
12107 gas_assert (offset_expr
.X_op
== O_symbol
);
12110 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12111 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12113 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12114 tempreg
, tempreg
, breg
);
12115 macro_build (&offset_expr
, s
, fmt
, op
[0],
12116 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12119 expr1
.X_add_number
= offset_expr
.X_add_number
;
12120 offset_expr
.X_add_number
= 0;
12121 if (expr1
.X_add_number
< -0x8000
12122 || expr1
.X_add_number
>= 0x8000)
12123 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12124 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12125 lw_reloc_type
, mips_gp_register
);
12127 relax_start (offset_expr
.X_add_symbol
);
12129 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12130 tempreg
, BFD_RELOC_LO16
);
12133 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12134 tempreg
, tempreg
, breg
);
12135 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12137 else if (mips_big_got
&& !HAVE_NEWABI
)
12141 /* If this is a reference to an external symbol, we want
12142 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12143 addu $tempreg,$tempreg,$gp
12144 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12145 <op> op[0],0($tempreg)
12147 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12149 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12150 <op> op[0],0($tempreg)
12151 If there is a base register, we add it to $tempreg before
12152 the <op>. If there is a constant, we stick it in the
12153 <op> instruction. We don't handle constants larger than
12154 16 bits, because we have no way to load the upper 16 bits
12155 (actually, we could handle them for the subset of cases
12156 in which we are not using $at). */
12157 gas_assert (offset_expr
.X_op
== O_symbol
);
12158 expr1
.X_add_number
= offset_expr
.X_add_number
;
12159 offset_expr
.X_add_number
= 0;
12160 if (expr1
.X_add_number
< -0x8000
12161 || expr1
.X_add_number
>= 0x8000)
12162 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12163 gpdelay
= reg_needs_delay (mips_gp_register
);
12164 relax_start (offset_expr
.X_add_symbol
);
12165 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12166 BFD_RELOC_MIPS_GOT_HI16
);
12167 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12169 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12170 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12173 macro_build (NULL
, "nop", "");
12174 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12175 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12177 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12178 tempreg
, BFD_RELOC_LO16
);
12182 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12183 tempreg
, tempreg
, breg
);
12184 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12186 else if (mips_big_got
&& HAVE_NEWABI
)
12188 /* If this is a reference to an external symbol, we want
12189 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12190 add $tempreg,$tempreg,$gp
12191 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12192 <op> op[0],<ofst>($tempreg)
12193 Otherwise, for local symbols, we want:
12194 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12195 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12196 gas_assert (offset_expr
.X_op
== O_symbol
);
12197 expr1
.X_add_number
= offset_expr
.X_add_number
;
12198 offset_expr
.X_add_number
= 0;
12199 if (expr1
.X_add_number
< -0x8000
12200 || expr1
.X_add_number
>= 0x8000)
12201 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12202 relax_start (offset_expr
.X_add_symbol
);
12203 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12204 BFD_RELOC_MIPS_GOT_HI16
);
12205 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12207 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12208 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12210 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12211 tempreg
, tempreg
, breg
);
12212 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12215 offset_expr
.X_add_number
= expr1
.X_add_number
;
12216 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12217 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12219 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12220 tempreg
, tempreg
, breg
);
12221 macro_build (&offset_expr
, s
, fmt
, op
[0],
12222 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12231 gas_assert (mips_opts
.micromips
);
12232 gas_assert (mips_opts
.insn32
);
12233 start_noreorder ();
12234 macro_build (NULL
, "jr", "s", RA
);
12235 expr1
.X_add_number
= op
[0] << 2;
12236 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12241 gas_assert (mips_opts
.micromips
);
12242 gas_assert (mips_opts
.insn32
);
12243 macro_build (NULL
, "jr", "s", op
[0]);
12244 if (mips_opts
.noreorder
)
12245 macro_build (NULL
, "nop", "");
12250 load_register (op
[0], &imm_expr
, 0);
12254 load_register (op
[0], &imm_expr
, 1);
12258 if (imm_expr
.X_op
== O_constant
)
12261 load_register (AT
, &imm_expr
, 0);
12262 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12267 gas_assert (imm_expr
.X_op
== O_absent
12268 && offset_expr
.X_op
== O_symbol
12269 && strcmp (segment_name (S_GET_SEGMENT
12270 (offset_expr
.X_add_symbol
)),
12272 && offset_expr
.X_add_number
== 0);
12273 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12274 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12279 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12280 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12281 order 32 bits of the value and the low order 32 bits are either
12282 zero or in OFFSET_EXPR. */
12283 if (imm_expr
.X_op
== O_constant
)
12285 if (GPR_SIZE
== 64)
12286 load_register (op
[0], &imm_expr
, 1);
12291 if (target_big_endian
)
12303 load_register (hreg
, &imm_expr
, 0);
12306 if (offset_expr
.X_op
== O_absent
)
12307 move_register (lreg
, 0);
12310 gas_assert (offset_expr
.X_op
== O_constant
);
12311 load_register (lreg
, &offset_expr
, 0);
12317 gas_assert (imm_expr
.X_op
== O_absent
);
12319 /* We know that sym is in the .rdata section. First we get the
12320 upper 16 bits of the address. */
12321 if (mips_pic
== NO_PIC
)
12323 macro_build_lui (&offset_expr
, AT
);
12328 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12329 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12333 /* Now we load the register(s). */
12334 if (GPR_SIZE
== 64)
12337 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12338 BFD_RELOC_LO16
, AT
);
12343 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12344 BFD_RELOC_LO16
, AT
);
12347 /* FIXME: How in the world do we deal with the possible
12349 offset_expr
.X_add_number
+= 4;
12350 macro_build (&offset_expr
, "lw", "t,o(b)",
12351 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12357 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12358 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12359 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12360 the value and the low order 32 bits are either zero or in
12362 if (imm_expr
.X_op
== O_constant
)
12365 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12366 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12367 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12370 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12371 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12372 else if (FPR_SIZE
!= 32)
12373 as_bad (_("Unable to generate `%s' compliant code "
12375 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12377 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12378 if (offset_expr
.X_op
== O_absent
)
12379 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12382 gas_assert (offset_expr
.X_op
== O_constant
);
12383 load_register (AT
, &offset_expr
, 0);
12384 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12390 gas_assert (imm_expr
.X_op
== O_absent
12391 && offset_expr
.X_op
== O_symbol
12392 && offset_expr
.X_add_number
== 0);
12393 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12394 if (strcmp (s
, ".lit8") == 0)
12396 op
[2] = mips_gp_register
;
12397 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12398 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12399 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12403 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12405 if (mips_pic
!= NO_PIC
)
12406 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12407 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12410 /* FIXME: This won't work for a 64 bit address. */
12411 macro_build_lui (&offset_expr
, AT
);
12415 offset_reloc
[0] = BFD_RELOC_LO16
;
12416 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12417 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12424 * The MIPS assembler seems to check for X_add_number not
12425 * being double aligned and generating:
12426 * lui at,%hi(foo+1)
12428 * addiu at,at,%lo(foo+1)
12431 * But, the resulting address is the same after relocation so why
12432 * generate the extra instruction?
12434 /* Itbl support may require additional care here. */
12437 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12446 gas_assert (!mips_opts
.micromips
);
12447 /* Itbl support may require additional care here. */
12450 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12470 if (GPR_SIZE
== 64)
12480 if (GPR_SIZE
== 64)
12488 /* Even on a big endian machine $fn comes before $fn+1. We have
12489 to adjust when loading from memory. We set coproc if we must
12490 load $fn+1 first. */
12491 /* Itbl support may require additional care here. */
12492 if (!target_big_endian
)
12496 if (small_offset_p (0, align
, 16))
12499 if (!small_offset_p (4, align
, 16))
12501 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12502 -1, offset_reloc
[0], offset_reloc
[1],
12504 expr1
.X_add_number
= 0;
12508 offset_reloc
[0] = BFD_RELOC_LO16
;
12509 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12510 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12512 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12514 ep
->X_add_number
+= 4;
12515 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12516 offset_reloc
[1], offset_reloc
[2], breg
);
12517 ep
->X_add_number
-= 4;
12518 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12519 offset_reloc
[1], offset_reloc
[2], breg
);
12523 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12524 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12526 ep
->X_add_number
+= 4;
12527 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12528 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12534 if (offset_expr
.X_op
!= O_symbol
12535 && offset_expr
.X_op
!= O_constant
)
12537 as_bad (_("expression too complex"));
12538 offset_expr
.X_op
= O_constant
;
12541 if (HAVE_32BIT_ADDRESSES
12542 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12546 sprintf_vma (value
, offset_expr
.X_add_number
);
12547 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12550 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12552 /* If this is a reference to a GP relative symbol, we want
12553 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12554 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12555 If we have a base register, we use this
12557 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12558 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12559 If this is not a GP relative symbol, we want
12560 lui $at,<sym> (BFD_RELOC_HI16_S)
12561 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12562 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12563 If there is a base register, we add it to $at after the
12564 lui instruction. If there is a constant, we always use
12566 if (offset_expr
.X_op
== O_symbol
12567 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12568 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12570 relax_start (offset_expr
.X_add_symbol
);
12573 tempreg
= mips_gp_register
;
12577 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12578 AT
, breg
, mips_gp_register
);
12583 /* Itbl support may require additional care here. */
12584 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12585 BFD_RELOC_GPREL16
, tempreg
);
12586 offset_expr
.X_add_number
+= 4;
12588 /* Set mips_optimize to 2 to avoid inserting an
12590 hold_mips_optimize
= mips_optimize
;
12592 /* Itbl support may require additional care here. */
12593 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12594 BFD_RELOC_GPREL16
, tempreg
);
12595 mips_optimize
= hold_mips_optimize
;
12599 offset_expr
.X_add_number
-= 4;
12602 if (offset_high_part (offset_expr
.X_add_number
, 16)
12603 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12605 load_address (AT
, &offset_expr
, &used_at
);
12606 offset_expr
.X_op
= O_constant
;
12607 offset_expr
.X_add_number
= 0;
12610 macro_build_lui (&offset_expr
, AT
);
12612 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12613 /* Itbl support may require additional care here. */
12614 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12615 BFD_RELOC_LO16
, AT
);
12616 /* FIXME: How do we handle overflow here? */
12617 offset_expr
.X_add_number
+= 4;
12618 /* Itbl support may require additional care here. */
12619 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12620 BFD_RELOC_LO16
, AT
);
12621 if (mips_relax
.sequence
)
12624 else if (!mips_big_got
)
12626 /* If this is a reference to an external symbol, we want
12627 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12630 <op> op[0]+1,4($at)
12632 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12634 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12635 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12636 If there is a base register we add it to $at before the
12637 lwc1 instructions. If there is a constant we include it
12638 in the lwc1 instructions. */
12640 expr1
.X_add_number
= offset_expr
.X_add_number
;
12641 if (expr1
.X_add_number
< -0x8000
12642 || expr1
.X_add_number
>= 0x8000 - 4)
12643 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12644 load_got_offset (AT
, &offset_expr
);
12647 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12649 /* Set mips_optimize to 2 to avoid inserting an undesired
12651 hold_mips_optimize
= mips_optimize
;
12654 /* Itbl support may require additional care here. */
12655 relax_start (offset_expr
.X_add_symbol
);
12656 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12657 BFD_RELOC_LO16
, AT
);
12658 expr1
.X_add_number
+= 4;
12659 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12660 BFD_RELOC_LO16
, AT
);
12662 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12663 BFD_RELOC_LO16
, AT
);
12664 offset_expr
.X_add_number
+= 4;
12665 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12666 BFD_RELOC_LO16
, AT
);
12669 mips_optimize
= hold_mips_optimize
;
12671 else if (mips_big_got
)
12675 /* If this is a reference to an external symbol, we want
12676 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12678 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12681 <op> op[0]+1,4($at)
12683 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12685 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12686 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12687 If there is a base register we add it to $at before the
12688 lwc1 instructions. If there is a constant we include it
12689 in the lwc1 instructions. */
12691 expr1
.X_add_number
= offset_expr
.X_add_number
;
12692 offset_expr
.X_add_number
= 0;
12693 if (expr1
.X_add_number
< -0x8000
12694 || expr1
.X_add_number
>= 0x8000 - 4)
12695 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12696 gpdelay
= reg_needs_delay (mips_gp_register
);
12697 relax_start (offset_expr
.X_add_symbol
);
12698 macro_build (&offset_expr
, "lui", LUI_FMT
,
12699 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12700 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12701 AT
, AT
, mips_gp_register
);
12702 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12703 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12706 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12707 /* Itbl support may require additional care here. */
12708 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12709 BFD_RELOC_LO16
, AT
);
12710 expr1
.X_add_number
+= 4;
12712 /* Set mips_optimize to 2 to avoid inserting an undesired
12714 hold_mips_optimize
= mips_optimize
;
12716 /* Itbl support may require additional care here. */
12717 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12718 BFD_RELOC_LO16
, AT
);
12719 mips_optimize
= hold_mips_optimize
;
12720 expr1
.X_add_number
-= 4;
12723 offset_expr
.X_add_number
= expr1
.X_add_number
;
12725 macro_build (NULL
, "nop", "");
12726 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12727 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12730 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12731 /* Itbl support may require additional care here. */
12732 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12733 BFD_RELOC_LO16
, AT
);
12734 offset_expr
.X_add_number
+= 4;
12736 /* Set mips_optimize to 2 to avoid inserting an undesired
12738 hold_mips_optimize
= mips_optimize
;
12740 /* Itbl support may require additional care here. */
12741 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12742 BFD_RELOC_LO16
, AT
);
12743 mips_optimize
= hold_mips_optimize
;
12757 gas_assert (!mips_opts
.micromips
);
12762 /* New code added to support COPZ instructions.
12763 This code builds table entries out of the macros in mip_opcodes.
12764 R4000 uses interlocks to handle coproc delays.
12765 Other chips (like the R3000) require nops to be inserted for delays.
12767 FIXME: Currently, we require that the user handle delays.
12768 In order to fill delay slots for non-interlocked chips,
12769 we must have a way to specify delays based on the coprocessor.
12770 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12771 What are the side-effects of the cop instruction?
12772 What cache support might we have and what are its effects?
12773 Both coprocessor & memory require delays. how long???
12774 What registers are read/set/modified?
12776 If an itbl is provided to interpret cop instructions,
12777 this knowledge can be encoded in the itbl spec. */
12791 gas_assert (!mips_opts
.micromips
);
12792 /* For now we just do C (same as Cz). The parameter will be
12793 stored in insn_opcode by mips_ip. */
12794 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12798 move_register (op
[0], op
[1]);
12802 gas_assert (mips_opts
.micromips
);
12803 gas_assert (mips_opts
.insn32
);
12804 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12805 micromips_to_32_reg_m_map
[op
[1]]);
12806 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12807 micromips_to_32_reg_n_map
[op
[2]]);
12812 /* Fall through. */
12814 if (mips_opts
.arch
== CPU_R5900
)
12815 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12819 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12820 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12826 /* Fall through. */
12828 /* The MIPS assembler some times generates shifts and adds. I'm
12829 not trying to be that fancy. GCC should do this for us
12832 load_register (AT
, &imm_expr
, dbl
);
12833 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12834 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12839 /* Fall through. */
12846 /* Fall through. */
12849 start_noreorder ();
12852 load_register (AT
, &imm_expr
, dbl
);
12853 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12854 op
[1], imm
? AT
: op
[2]);
12855 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12856 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12857 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12859 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12862 if (mips_opts
.micromips
)
12863 micromips_label_expr (&label_expr
);
12865 label_expr
.X_add_number
= 8;
12866 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12867 macro_build (NULL
, "nop", "");
12868 macro_build (NULL
, "break", BRK_FMT
, 6);
12869 if (mips_opts
.micromips
)
12870 micromips_add_label ();
12873 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12878 /* Fall through. */
12885 /* Fall through. */
12888 start_noreorder ();
12891 load_register (AT
, &imm_expr
, dbl
);
12892 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12893 op
[1], imm
? AT
: op
[2]);
12894 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12895 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12897 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12900 if (mips_opts
.micromips
)
12901 micromips_label_expr (&label_expr
);
12903 label_expr
.X_add_number
= 8;
12904 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12905 macro_build (NULL
, "nop", "");
12906 macro_build (NULL
, "break", BRK_FMT
, 6);
12907 if (mips_opts
.micromips
)
12908 micromips_add_label ();
12914 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12916 if (op
[0] == op
[1])
12923 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12924 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12928 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12929 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12930 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12931 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12935 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12937 if (op
[0] == op
[1])
12944 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12945 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12949 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12950 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12951 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12952 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12961 rot
= imm_expr
.X_add_number
& 0x3f;
12962 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12964 rot
= (64 - rot
) & 0x3f;
12966 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12968 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12973 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12976 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12977 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12980 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12981 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12982 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12990 rot
= imm_expr
.X_add_number
& 0x1f;
12991 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12993 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12994 (32 - rot
) & 0x1f);
12999 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13003 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13004 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13005 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13010 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13012 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13016 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13017 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13018 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13019 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13023 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13025 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13029 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13030 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13031 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13032 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13041 rot
= imm_expr
.X_add_number
& 0x3f;
13042 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13045 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13047 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13052 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13055 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13056 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13059 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13060 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13061 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13069 rot
= imm_expr
.X_add_number
& 0x1f;
13070 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13072 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13077 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13081 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13082 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13083 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13089 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13090 else if (op
[2] == 0)
13091 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13094 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13095 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13100 if (imm_expr
.X_add_number
== 0)
13102 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13107 as_warn (_("instruction %s: result is always false"),
13108 ip
->insn_mo
->name
);
13109 move_register (op
[0], 0);
13112 if (CPU_HAS_SEQ (mips_opts
.arch
)
13113 && -512 <= imm_expr
.X_add_number
13114 && imm_expr
.X_add_number
< 512)
13116 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13117 (int) imm_expr
.X_add_number
);
13120 if (imm_expr
.X_add_number
>= 0
13121 && imm_expr
.X_add_number
< 0x10000)
13122 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13123 else if (imm_expr
.X_add_number
> -0x8000
13124 && imm_expr
.X_add_number
< 0)
13126 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13127 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13128 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13130 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13133 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13134 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13139 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13140 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13143 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13146 case M_SGE
: /* X >= Y <==> not (X < Y) */
13152 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13153 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13156 case M_SGE_I
: /* X >= I <==> not (X < I) */
13158 if (imm_expr
.X_add_number
>= -0x8000
13159 && imm_expr
.X_add_number
< 0x8000)
13160 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13161 op
[0], op
[1], BFD_RELOC_LO16
);
13164 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13165 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13169 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13172 case M_SGT
: /* X > Y <==> Y < X */
13178 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13181 case M_SGT_I
: /* X > I <==> I < X */
13188 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13189 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13192 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13198 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13199 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13202 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13209 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13210 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13211 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13215 if (imm_expr
.X_add_number
>= -0x8000
13216 && imm_expr
.X_add_number
< 0x8000)
13218 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13223 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13224 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13228 if (imm_expr
.X_add_number
>= -0x8000
13229 && imm_expr
.X_add_number
< 0x8000)
13231 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13236 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13237 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13242 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13243 else if (op
[2] == 0)
13244 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13247 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13248 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13253 if (imm_expr
.X_add_number
== 0)
13255 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13260 as_warn (_("instruction %s: result is always true"),
13261 ip
->insn_mo
->name
);
13262 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13263 op
[0], 0, BFD_RELOC_LO16
);
13266 if (CPU_HAS_SEQ (mips_opts
.arch
)
13267 && -512 <= imm_expr
.X_add_number
13268 && imm_expr
.X_add_number
< 512)
13270 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13271 (int) imm_expr
.X_add_number
);
13274 if (imm_expr
.X_add_number
>= 0
13275 && imm_expr
.X_add_number
< 0x10000)
13277 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13280 else if (imm_expr
.X_add_number
> -0x8000
13281 && imm_expr
.X_add_number
< 0)
13283 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13284 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13285 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13287 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13290 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13291 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13296 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13297 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13300 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13315 if (!mips_opts
.micromips
)
13317 if (imm_expr
.X_add_number
> -0x200
13318 && imm_expr
.X_add_number
<= 0x200)
13320 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13321 (int) -imm_expr
.X_add_number
);
13330 if (imm_expr
.X_add_number
> -0x8000
13331 && imm_expr
.X_add_number
<= 0x8000)
13333 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13334 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13339 load_register (AT
, &imm_expr
, dbl
);
13340 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13362 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13363 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13368 gas_assert (!mips_opts
.micromips
);
13369 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13373 * Is the double cfc1 instruction a bug in the mips assembler;
13374 * or is there a reason for it?
13376 start_noreorder ();
13377 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13378 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13379 macro_build (NULL
, "nop", "");
13380 expr1
.X_add_number
= 3;
13381 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13382 expr1
.X_add_number
= 2;
13383 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13384 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13385 macro_build (NULL
, "nop", "");
13386 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13388 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13389 macro_build (NULL
, "nop", "");
13406 offbits
= (mips_opts
.micromips
? 12 : 16);
13412 offbits
= (mips_opts
.micromips
? 12 : 16);
13424 offbits
= (mips_opts
.micromips
? 12 : 16);
13431 offbits
= (mips_opts
.micromips
? 12 : 16);
13437 large_offset
= !small_offset_p (off
, align
, offbits
);
13439 expr1
.X_add_number
= 0;
13444 if (small_offset_p (0, align
, 16))
13445 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13446 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13449 load_address (tempreg
, ep
, &used_at
);
13451 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13452 tempreg
, tempreg
, breg
);
13454 offset_reloc
[0] = BFD_RELOC_LO16
;
13455 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13456 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13461 else if (!ust
&& op
[0] == breg
)
13472 if (!target_big_endian
)
13473 ep
->X_add_number
+= off
;
13475 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13477 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13478 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13480 if (!target_big_endian
)
13481 ep
->X_add_number
-= off
;
13483 ep
->X_add_number
+= off
;
13485 macro_build (NULL
, s2
, "t,~(b)",
13486 tempreg
, (int) ep
->X_add_number
, breg
);
13488 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13489 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13491 /* If necessary, move the result in tempreg to the final destination. */
13492 if (!ust
&& op
[0] != tempreg
)
13494 /* Protect second load's delay slot. */
13496 move_register (op
[0], tempreg
);
13502 if (target_big_endian
== ust
)
13503 ep
->X_add_number
+= off
;
13504 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13505 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13506 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13508 /* For halfword transfers we need a temporary register to shuffle
13509 bytes. Unfortunately for M_USH_A we have none available before
13510 the next store as AT holds the base address. We deal with this
13511 case by clobbering TREG and then restoring it as with ULH. */
13512 tempreg
= ust
== large_offset
? op
[0] : AT
;
13514 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13516 if (target_big_endian
== ust
)
13517 ep
->X_add_number
-= off
;
13519 ep
->X_add_number
+= off
;
13520 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13521 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13523 /* For M_USH_A re-retrieve the LSB. */
13524 if (ust
&& large_offset
)
13526 if (target_big_endian
)
13527 ep
->X_add_number
+= off
;
13529 ep
->X_add_number
-= off
;
13530 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13531 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13533 /* For ULH and M_USH_A OR the LSB in. */
13534 if (!ust
|| large_offset
)
13536 tempreg
= !large_offset
? AT
: op
[0];
13537 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13538 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13543 /* FIXME: Check if this is one of the itbl macros, since they
13544 are added dynamically. */
13545 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13548 if (!mips_opts
.at
&& used_at
)
13549 as_bad (_("macro used $at after \".set noat\""));
13552 /* Implement macros in mips16 mode. */
13555 mips16_macro (struct mips_cl_insn
*ip
)
13557 const struct mips_operand_array
*operands
;
13562 const char *s
, *s2
, *s3
;
13563 unsigned int op
[MAX_OPERANDS
];
13566 mask
= ip
->insn_mo
->mask
;
13568 operands
= insn_operands (ip
);
13569 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13570 if (operands
->operand
[i
])
13571 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13575 expr1
.X_op
= O_constant
;
13576 expr1
.X_op_symbol
= NULL
;
13577 expr1
.X_add_symbol
= NULL
;
13578 expr1
.X_add_number
= 1;
13589 /* Fall through. */
13595 /* Fall through. */
13599 start_noreorder ();
13600 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13601 expr1
.X_add_number
= 2;
13602 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13603 macro_build (NULL
, "break", "6", 7);
13605 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13606 since that causes an overflow. We should do that as well,
13607 but I don't see how to do the comparisons without a temporary
13610 macro_build (NULL
, s
, "x", op
[0]);
13629 start_noreorder ();
13630 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13631 expr1
.X_add_number
= 2;
13632 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13633 macro_build (NULL
, "break", "6", 7);
13635 macro_build (NULL
, s2
, "x", op
[0]);
13640 /* Fall through. */
13642 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13643 macro_build (NULL
, "mflo", "x", op
[0]);
13651 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13652 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13656 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13657 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13661 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13662 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13684 goto do_reverse_branch
;
13688 goto do_reverse_branch
;
13700 goto do_reverse_branch
;
13711 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13712 macro_build (&offset_expr
, s2
, "p");
13739 goto do_addone_branch_i
;
13744 goto do_addone_branch_i
;
13759 goto do_addone_branch_i
;
13765 do_addone_branch_i
:
13766 ++imm_expr
.X_add_number
;
13769 macro_build (&imm_expr
, s
, s3
, op
[0]);
13770 macro_build (&offset_expr
, s2
, "p");
13774 expr1
.X_add_number
= 0;
13775 macro_build (&expr1
, "slti", "x,8", op
[1]);
13776 if (op
[0] != op
[1])
13777 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13778 expr1
.X_add_number
= 2;
13779 macro_build (&expr1
, "bteqz", "p");
13780 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13785 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13786 opcode bits in *OPCODE_EXTRA. */
13788 static struct mips_opcode
*
13789 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13790 ssize_t length
, unsigned int *opcode_extra
)
13792 char *name
, *dot
, *p
;
13793 unsigned int mask
, suffix
;
13795 struct mips_opcode
*insn
;
13797 /* Make a copy of the instruction so that we can fiddle with it. */
13798 name
= xstrndup (start
, length
);
13800 /* Look up the instruction as-is. */
13801 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13805 dot
= strchr (name
, '.');
13808 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13809 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13810 if (*p
== 0 && mask
!= 0)
13813 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13815 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13817 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13823 if (mips_opts
.micromips
)
13825 /* See if there's an instruction size override suffix,
13826 either `16' or `32', at the end of the mnemonic proper,
13827 that defines the operation, i.e. before the first `.'
13828 character if any. Strip it and retry. */
13829 opend
= dot
!= NULL
? dot
- name
: length
;
13830 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13832 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13838 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13839 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13842 forced_insn_length
= suffix
;
13854 /* Assemble an instruction into its binary format. If the instruction
13855 is a macro, set imm_expr and offset_expr to the values associated
13856 with "I" and "A" operands respectively. Otherwise store the value
13857 of the relocatable field (if any) in offset_expr. In both cases
13858 set offset_reloc to the relocation operators applied to offset_expr. */
13861 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13863 const struct mips_opcode
*first
, *past
;
13864 struct hash_control
*hash
;
13867 struct mips_operand_token
*tokens
;
13868 unsigned int opcode_extra
;
13870 if (mips_opts
.micromips
)
13872 hash
= micromips_op_hash
;
13873 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13878 past
= &mips_opcodes
[NUMOPCODES
];
13880 forced_insn_length
= 0;
13883 /* We first try to match an instruction up to a space or to the end. */
13884 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13887 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13890 set_insn_error (0, _("unrecognized opcode"));
13894 if (strcmp (first
->name
, "li.s") == 0)
13896 else if (strcmp (first
->name
, "li.d") == 0)
13900 tokens
= mips_parse_arguments (str
+ end
, format
);
13904 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13905 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13906 set_insn_error (0, _("invalid operands"));
13908 obstack_free (&mips_operand_tokens
, tokens
);
13911 /* As for mips_ip, but used when assembling MIPS16 code.
13912 Also set forced_insn_length to the resulting instruction size in
13913 bytes if the user explicitly requested a small or extended instruction. */
13916 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13919 struct mips_opcode
*first
;
13920 struct mips_operand_token
*tokens
;
13923 for (s
= str
; ISLOWER (*s
); ++s
)
13945 else if (*s
== 'e')
13952 else if (*s
++ == ' ')
13954 /* Fall through. */
13956 set_insn_error (0, _("unrecognized opcode"));
13959 forced_insn_length
= l
;
13962 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13967 set_insn_error (0, _("unrecognized opcode"));
13971 tokens
= mips_parse_arguments (s
, 0);
13975 if (!match_mips16_insns (insn
, first
, tokens
))
13976 set_insn_error (0, _("invalid operands"));
13978 obstack_free (&mips_operand_tokens
, tokens
);
13981 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13982 NBITS is the number of significant bits in VAL. */
13984 static unsigned long
13985 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13990 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13993 else if (nbits
== 15)
13995 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14000 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14003 return (extval
<< 16) | val
;
14006 /* Like decode_mips16_operand, but require the operand to be defined and
14007 require it to be an integer. */
14009 static const struct mips_int_operand
*
14010 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14012 const struct mips_operand
*operand
;
14014 operand
= decode_mips16_operand (type
, extended_p
);
14015 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14017 return (const struct mips_int_operand
*) operand
;
14020 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14023 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14024 bfd_reloc_code_real_type reloc
, offsetT sval
)
14026 int min_val
, max_val
;
14028 min_val
= mips_int_operand_min (operand
);
14029 max_val
= mips_int_operand_max (operand
);
14030 if (reloc
!= BFD_RELOC_UNUSED
)
14033 sval
= SEXT_16BIT (sval
);
14038 return (sval
>= min_val
14040 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14043 /* Install immediate value VAL into MIPS16 instruction *INSN,
14044 extending it if necessary. The instruction in *INSN may
14045 already be extended.
14047 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14048 if none. In the former case, VAL is a 16-bit number with no
14049 defined signedness.
14051 TYPE is the type of the immediate field. USER_INSN_LENGTH
14052 is the length that the user requested, or 0 if none. */
14055 mips16_immed (const char *file
, unsigned int line
, int type
,
14056 bfd_reloc_code_real_type reloc
, offsetT val
,
14057 unsigned int user_insn_length
, unsigned long *insn
)
14059 const struct mips_int_operand
*operand
;
14060 unsigned int uval
, length
;
14062 operand
= mips16_immed_operand (type
, FALSE
);
14063 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14065 /* We need an extended instruction. */
14066 if (user_insn_length
== 2)
14067 as_bad_where (file
, line
, _("invalid unextended operand value"));
14069 *insn
|= MIPS16_EXTEND
;
14071 else if (user_insn_length
== 4)
14073 /* The operand doesn't force an unextended instruction to be extended.
14074 Warn if the user wanted an extended instruction anyway. */
14075 *insn
|= MIPS16_EXTEND
;
14076 as_warn_where (file
, line
,
14077 _("extended operand requested but not required"));
14080 length
= mips16_opcode_length (*insn
);
14083 operand
= mips16_immed_operand (type
, TRUE
);
14084 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14085 as_bad_where (file
, line
,
14086 _("operand value out of range for instruction"));
14088 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14089 if (length
== 2 || operand
->root
.lsb
!= 0)
14090 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14092 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14095 struct percent_op_match
14098 bfd_reloc_code_real_type reloc
;
14101 static const struct percent_op_match mips_percent_op
[] =
14103 {"%lo", BFD_RELOC_LO16
},
14104 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14105 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14106 {"%call16", BFD_RELOC_MIPS_CALL16
},
14107 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14108 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14109 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14110 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14111 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14112 {"%got", BFD_RELOC_MIPS_GOT16
},
14113 {"%gp_rel", BFD_RELOC_GPREL16
},
14114 {"%gprel", BFD_RELOC_GPREL16
},
14115 {"%half", BFD_RELOC_16
},
14116 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14117 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14118 {"%neg", BFD_RELOC_MIPS_SUB
},
14119 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14120 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14121 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14122 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14123 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14124 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14125 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14126 {"%hi", BFD_RELOC_HI16_S
},
14127 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14128 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14131 static const struct percent_op_match mips16_percent_op
[] =
14133 {"%lo", BFD_RELOC_MIPS16_LO16
},
14134 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14135 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14136 {"%got", BFD_RELOC_MIPS16_GOT16
},
14137 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14138 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14139 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14140 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14141 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14142 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14143 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14144 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14145 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14149 /* Return true if *STR points to a relocation operator. When returning true,
14150 move *STR over the operator and store its relocation code in *RELOC.
14151 Leave both *STR and *RELOC alone when returning false. */
14154 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14156 const struct percent_op_match
*percent_op
;
14159 if (mips_opts
.mips16
)
14161 percent_op
= mips16_percent_op
;
14162 limit
= ARRAY_SIZE (mips16_percent_op
);
14166 percent_op
= mips_percent_op
;
14167 limit
= ARRAY_SIZE (mips_percent_op
);
14170 for (i
= 0; i
< limit
; i
++)
14171 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14173 int len
= strlen (percent_op
[i
].str
);
14175 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14178 *str
+= strlen (percent_op
[i
].str
);
14179 *reloc
= percent_op
[i
].reloc
;
14181 /* Check whether the output BFD supports this relocation.
14182 If not, issue an error and fall back on something safe. */
14183 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14185 as_bad (_("relocation %s isn't supported by the current ABI"),
14186 percent_op
[i
].str
);
14187 *reloc
= BFD_RELOC_UNUSED
;
14195 /* Parse string STR as a 16-bit relocatable operand. Store the
14196 expression in *EP and the relocations in the array starting
14197 at RELOC. Return the number of relocation operators used.
14199 On exit, EXPR_END points to the first character after the expression. */
14202 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14205 bfd_reloc_code_real_type reversed_reloc
[3];
14206 size_t reloc_index
, i
;
14207 int crux_depth
, str_depth
;
14210 /* Search for the start of the main expression, recoding relocations
14211 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14212 of the main expression and with CRUX_DEPTH containing the number
14213 of open brackets at that point. */
14220 crux_depth
= str_depth
;
14222 /* Skip over whitespace and brackets, keeping count of the number
14224 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14229 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14230 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14232 my_getExpression (ep
, crux
);
14235 /* Match every open bracket. */
14236 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14240 if (crux_depth
> 0)
14241 as_bad (_("unclosed '('"));
14245 if (reloc_index
!= 0)
14247 prev_reloc_op_frag
= frag_now
;
14248 for (i
= 0; i
< reloc_index
; i
++)
14249 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14252 return reloc_index
;
14256 my_getExpression (expressionS
*ep
, char *str
)
14260 save_in
= input_line_pointer
;
14261 input_line_pointer
= str
;
14263 expr_end
= input_line_pointer
;
14264 input_line_pointer
= save_in
;
14268 md_atof (int type
, char *litP
, int *sizeP
)
14270 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14274 md_number_to_chars (char *buf
, valueT val
, int n
)
14276 if (target_big_endian
)
14277 number_to_chars_bigendian (buf
, val
, n
);
14279 number_to_chars_littleendian (buf
, val
, n
);
14282 static int support_64bit_objects(void)
14284 const char **list
, **l
;
14287 list
= bfd_target_list ();
14288 for (l
= list
; *l
!= NULL
; l
++)
14289 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14290 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14292 yes
= (*l
!= NULL
);
14297 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14298 NEW_VALUE. Warn if another value was already specified. Note:
14299 we have to defer parsing the -march and -mtune arguments in order
14300 to handle 'from-abi' correctly, since the ABI might be specified
14301 in a later argument. */
14304 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14306 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14307 as_warn (_("a different %s was already specified, is now %s"),
14308 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14311 *string_ptr
= new_value
;
14315 md_parse_option (int c
, const char *arg
)
14319 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14320 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14322 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14323 c
== mips_ases
[i
].option_on
);
14329 case OPTION_CONSTRUCT_FLOATS
:
14330 mips_disable_float_construction
= 0;
14333 case OPTION_NO_CONSTRUCT_FLOATS
:
14334 mips_disable_float_construction
= 1;
14346 target_big_endian
= 1;
14350 target_big_endian
= 0;
14356 else if (arg
[0] == '0')
14358 else if (arg
[0] == '1')
14368 mips_debug
= atoi (arg
);
14372 file_mips_opts
.isa
= ISA_MIPS1
;
14376 file_mips_opts
.isa
= ISA_MIPS2
;
14380 file_mips_opts
.isa
= ISA_MIPS3
;
14384 file_mips_opts
.isa
= ISA_MIPS4
;
14388 file_mips_opts
.isa
= ISA_MIPS5
;
14391 case OPTION_MIPS32
:
14392 file_mips_opts
.isa
= ISA_MIPS32
;
14395 case OPTION_MIPS32R2
:
14396 file_mips_opts
.isa
= ISA_MIPS32R2
;
14399 case OPTION_MIPS32R3
:
14400 file_mips_opts
.isa
= ISA_MIPS32R3
;
14403 case OPTION_MIPS32R5
:
14404 file_mips_opts
.isa
= ISA_MIPS32R5
;
14407 case OPTION_MIPS32R6
:
14408 file_mips_opts
.isa
= ISA_MIPS32R6
;
14411 case OPTION_MIPS64R2
:
14412 file_mips_opts
.isa
= ISA_MIPS64R2
;
14415 case OPTION_MIPS64R3
:
14416 file_mips_opts
.isa
= ISA_MIPS64R3
;
14419 case OPTION_MIPS64R5
:
14420 file_mips_opts
.isa
= ISA_MIPS64R5
;
14423 case OPTION_MIPS64R6
:
14424 file_mips_opts
.isa
= ISA_MIPS64R6
;
14427 case OPTION_MIPS64
:
14428 file_mips_opts
.isa
= ISA_MIPS64
;
14432 mips_set_option_string (&mips_tune_string
, arg
);
14436 mips_set_option_string (&mips_arch_string
, arg
);
14440 mips_set_option_string (&mips_arch_string
, "4650");
14441 mips_set_option_string (&mips_tune_string
, "4650");
14444 case OPTION_NO_M4650
:
14448 mips_set_option_string (&mips_arch_string
, "4010");
14449 mips_set_option_string (&mips_tune_string
, "4010");
14452 case OPTION_NO_M4010
:
14456 mips_set_option_string (&mips_arch_string
, "4100");
14457 mips_set_option_string (&mips_tune_string
, "4100");
14460 case OPTION_NO_M4100
:
14464 mips_set_option_string (&mips_arch_string
, "3900");
14465 mips_set_option_string (&mips_tune_string
, "3900");
14468 case OPTION_NO_M3900
:
14471 case OPTION_MICROMIPS
:
14472 if (file_mips_opts
.mips16
== 1)
14474 as_bad (_("-mmicromips cannot be used with -mips16"));
14477 file_mips_opts
.micromips
= 1;
14478 mips_no_prev_insn ();
14481 case OPTION_NO_MICROMIPS
:
14482 file_mips_opts
.micromips
= 0;
14483 mips_no_prev_insn ();
14486 case OPTION_MIPS16
:
14487 if (file_mips_opts
.micromips
== 1)
14489 as_bad (_("-mips16 cannot be used with -micromips"));
14492 file_mips_opts
.mips16
= 1;
14493 mips_no_prev_insn ();
14496 case OPTION_NO_MIPS16
:
14497 file_mips_opts
.mips16
= 0;
14498 mips_no_prev_insn ();
14501 case OPTION_FIX_24K
:
14505 case OPTION_NO_FIX_24K
:
14509 case OPTION_FIX_RM7000
:
14510 mips_fix_rm7000
= 1;
14513 case OPTION_NO_FIX_RM7000
:
14514 mips_fix_rm7000
= 0;
14517 case OPTION_FIX_LOONGSON2F_JUMP
:
14518 mips_fix_loongson2f_jump
= TRUE
;
14521 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14522 mips_fix_loongson2f_jump
= FALSE
;
14525 case OPTION_FIX_LOONGSON2F_NOP
:
14526 mips_fix_loongson2f_nop
= TRUE
;
14529 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14530 mips_fix_loongson2f_nop
= FALSE
;
14533 case OPTION_FIX_VR4120
:
14534 mips_fix_vr4120
= 1;
14537 case OPTION_NO_FIX_VR4120
:
14538 mips_fix_vr4120
= 0;
14541 case OPTION_FIX_VR4130
:
14542 mips_fix_vr4130
= 1;
14545 case OPTION_NO_FIX_VR4130
:
14546 mips_fix_vr4130
= 0;
14549 case OPTION_FIX_CN63XXP1
:
14550 mips_fix_cn63xxp1
= TRUE
;
14553 case OPTION_NO_FIX_CN63XXP1
:
14554 mips_fix_cn63xxp1
= FALSE
;
14557 case OPTION_RELAX_BRANCH
:
14558 mips_relax_branch
= 1;
14561 case OPTION_NO_RELAX_BRANCH
:
14562 mips_relax_branch
= 0;
14565 case OPTION_IGNORE_BRANCH_ISA
:
14566 mips_ignore_branch_isa
= TRUE
;
14569 case OPTION_NO_IGNORE_BRANCH_ISA
:
14570 mips_ignore_branch_isa
= FALSE
;
14573 case OPTION_INSN32
:
14574 file_mips_opts
.insn32
= TRUE
;
14577 case OPTION_NO_INSN32
:
14578 file_mips_opts
.insn32
= FALSE
;
14581 case OPTION_MSHARED
:
14582 mips_in_shared
= TRUE
;
14585 case OPTION_MNO_SHARED
:
14586 mips_in_shared
= FALSE
;
14589 case OPTION_MSYM32
:
14590 file_mips_opts
.sym32
= TRUE
;
14593 case OPTION_MNO_SYM32
:
14594 file_mips_opts
.sym32
= FALSE
;
14597 /* When generating ELF code, we permit -KPIC and -call_shared to
14598 select SVR4_PIC, and -non_shared to select no PIC. This is
14599 intended to be compatible with Irix 5. */
14600 case OPTION_CALL_SHARED
:
14601 mips_pic
= SVR4_PIC
;
14602 mips_abicalls
= TRUE
;
14605 case OPTION_CALL_NONPIC
:
14607 mips_abicalls
= TRUE
;
14610 case OPTION_NON_SHARED
:
14612 mips_abicalls
= FALSE
;
14615 /* The -xgot option tells the assembler to use 32 bit offsets
14616 when accessing the got in SVR4_PIC mode. It is for Irix
14623 g_switch_value
= atoi (arg
);
14627 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14630 mips_abi
= O32_ABI
;
14634 mips_abi
= N32_ABI
;
14638 mips_abi
= N64_ABI
;
14639 if (!support_64bit_objects())
14640 as_fatal (_("no compiled in support for 64 bit object file format"));
14644 file_mips_opts
.gp
= 32;
14648 file_mips_opts
.gp
= 64;
14652 file_mips_opts
.fp
= 32;
14656 file_mips_opts
.fp
= 0;
14660 file_mips_opts
.fp
= 64;
14663 case OPTION_ODD_SPREG
:
14664 file_mips_opts
.oddspreg
= 1;
14667 case OPTION_NO_ODD_SPREG
:
14668 file_mips_opts
.oddspreg
= 0;
14671 case OPTION_SINGLE_FLOAT
:
14672 file_mips_opts
.single_float
= 1;
14675 case OPTION_DOUBLE_FLOAT
:
14676 file_mips_opts
.single_float
= 0;
14679 case OPTION_SOFT_FLOAT
:
14680 file_mips_opts
.soft_float
= 1;
14683 case OPTION_HARD_FLOAT
:
14684 file_mips_opts
.soft_float
= 0;
14688 if (strcmp (arg
, "32") == 0)
14689 mips_abi
= O32_ABI
;
14690 else if (strcmp (arg
, "o64") == 0)
14691 mips_abi
= O64_ABI
;
14692 else if (strcmp (arg
, "n32") == 0)
14693 mips_abi
= N32_ABI
;
14694 else if (strcmp (arg
, "64") == 0)
14696 mips_abi
= N64_ABI
;
14697 if (! support_64bit_objects())
14698 as_fatal (_("no compiled in support for 64 bit object file "
14701 else if (strcmp (arg
, "eabi") == 0)
14702 mips_abi
= EABI_ABI
;
14705 as_fatal (_("invalid abi -mabi=%s"), arg
);
14710 case OPTION_M7000_HILO_FIX
:
14711 mips_7000_hilo_fix
= TRUE
;
14714 case OPTION_MNO_7000_HILO_FIX
:
14715 mips_7000_hilo_fix
= FALSE
;
14718 case OPTION_MDEBUG
:
14719 mips_flag_mdebug
= TRUE
;
14722 case OPTION_NO_MDEBUG
:
14723 mips_flag_mdebug
= FALSE
;
14727 mips_flag_pdr
= TRUE
;
14730 case OPTION_NO_PDR
:
14731 mips_flag_pdr
= FALSE
;
14734 case OPTION_MVXWORKS_PIC
:
14735 mips_pic
= VXWORKS_PIC
;
14739 if (strcmp (arg
, "2008") == 0)
14741 else if (strcmp (arg
, "legacy") == 0)
14745 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14754 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14759 /* Set up globals to tune for the ISA or processor described by INFO. */
14762 mips_set_tune (const struct mips_cpu_info
*info
)
14765 mips_tune
= info
->cpu
;
14770 mips_after_parse_args (void)
14772 const struct mips_cpu_info
*arch_info
= 0;
14773 const struct mips_cpu_info
*tune_info
= 0;
14775 /* GP relative stuff not working for PE */
14776 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14778 if (g_switch_seen
&& g_switch_value
!= 0)
14779 as_bad (_("-G not supported in this configuration"));
14780 g_switch_value
= 0;
14783 if (mips_abi
== NO_ABI
)
14784 mips_abi
= MIPS_DEFAULT_ABI
;
14786 /* The following code determines the architecture.
14787 Similar code was added to GCC 3.3 (see override_options() in
14788 config/mips/mips.c). The GAS and GCC code should be kept in sync
14789 as much as possible. */
14791 if (mips_arch_string
!= 0)
14792 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14794 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14796 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14797 ISA level specified by -mipsN, while arch_info->isa contains
14798 the -march selection (if any). */
14799 if (arch_info
!= 0)
14801 /* -march takes precedence over -mipsN, since it is more descriptive.
14802 There's no harm in specifying both as long as the ISA levels
14804 if (file_mips_opts
.isa
!= arch_info
->isa
)
14805 as_bad (_("-%s conflicts with the other architecture options,"
14806 " which imply -%s"),
14807 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14808 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14811 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14814 if (arch_info
== 0)
14816 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14817 gas_assert (arch_info
);
14820 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14821 as_bad (_("-march=%s is not compatible with the selected ABI"),
14824 file_mips_opts
.arch
= arch_info
->cpu
;
14825 file_mips_opts
.isa
= arch_info
->isa
;
14827 /* Set up initial mips_opts state. */
14828 mips_opts
= file_mips_opts
;
14830 /* The register size inference code is now placed in
14831 file_mips_check_options. */
14833 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14835 if (mips_tune_string
!= 0)
14836 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14838 if (tune_info
== 0)
14839 mips_set_tune (arch_info
);
14841 mips_set_tune (tune_info
);
14843 if (mips_flag_mdebug
< 0)
14844 mips_flag_mdebug
= 0;
14848 mips_init_after_args (void)
14850 /* initialize opcodes */
14851 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14852 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14856 md_pcrel_from (fixS
*fixP
)
14858 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14859 switch (fixP
->fx_r_type
)
14861 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14862 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14863 /* Return the address of the delay slot. */
14866 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14867 case BFD_RELOC_MICROMIPS_JMP
:
14868 case BFD_RELOC_MIPS16_16_PCREL_S1
:
14869 case BFD_RELOC_16_PCREL_S2
:
14870 case BFD_RELOC_MIPS_21_PCREL_S2
:
14871 case BFD_RELOC_MIPS_26_PCREL_S2
:
14872 case BFD_RELOC_MIPS_JMP
:
14873 /* Return the address of the delay slot. */
14876 case BFD_RELOC_MIPS_18_PCREL_S3
:
14877 /* Return the aligned address of the doubleword containing
14878 the instruction. */
14886 /* This is called before the symbol table is processed. In order to
14887 work with gcc when using mips-tfile, we must keep all local labels.
14888 However, in other cases, we want to discard them. If we were
14889 called with -g, but we didn't see any debugging information, it may
14890 mean that gcc is smuggling debugging information through to
14891 mips-tfile, in which case we must generate all local labels. */
14894 mips_frob_file_before_adjust (void)
14896 #ifndef NO_ECOFF_DEBUGGING
14897 if (ECOFF_DEBUGGING
14899 && ! ecoff_debugging_seen
)
14900 flag_keep_locals
= 1;
14904 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14905 the corresponding LO16 reloc. This is called before md_apply_fix and
14906 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14907 relocation operators.
14909 For our purposes, a %lo() expression matches a %got() or %hi()
14912 (a) it refers to the same symbol; and
14913 (b) the offset applied in the %lo() expression is no lower than
14914 the offset applied in the %got() or %hi().
14916 (b) allows us to cope with code like:
14919 lh $4,%lo(foo+2)($4)
14921 ...which is legal on RELA targets, and has a well-defined behaviour
14922 if the user knows that adding 2 to "foo" will not induce a carry to
14925 When several %lo()s match a particular %got() or %hi(), we use the
14926 following rules to distinguish them:
14928 (1) %lo()s with smaller offsets are a better match than %lo()s with
14931 (2) %lo()s with no matching %got() or %hi() are better than those
14932 that already have a matching %got() or %hi().
14934 (3) later %lo()s are better than earlier %lo()s.
14936 These rules are applied in order.
14938 (1) means, among other things, that %lo()s with identical offsets are
14939 chosen if they exist.
14941 (2) means that we won't associate several high-part relocations with
14942 the same low-part relocation unless there's no alternative. Having
14943 several high parts for the same low part is a GNU extension; this rule
14944 allows careful users to avoid it.
14946 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14947 with the last high-part relocation being at the front of the list.
14948 It therefore makes sense to choose the last matching low-part
14949 relocation, all other things being equal. It's also easier
14950 to code that way. */
14953 mips_frob_file (void)
14955 struct mips_hi_fixup
*l
;
14956 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14958 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14960 segment_info_type
*seginfo
;
14961 bfd_boolean matched_lo_p
;
14962 fixS
**hi_pos
, **lo_pos
, **pos
;
14964 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14966 /* If a GOT16 relocation turns out to be against a global symbol,
14967 there isn't supposed to be a matching LO. Ignore %gots against
14968 constants; we'll report an error for those later. */
14969 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14970 && !(l
->fixp
->fx_addsy
14971 && pic_need_relax (l
->fixp
->fx_addsy
)))
14974 /* Check quickly whether the next fixup happens to be a matching %lo. */
14975 if (fixup_has_matching_lo_p (l
->fixp
))
14978 seginfo
= seg_info (l
->seg
);
14980 /* Set HI_POS to the position of this relocation in the chain.
14981 Set LO_POS to the position of the chosen low-part relocation.
14982 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14983 relocation that matches an immediately-preceding high-part
14987 matched_lo_p
= FALSE
;
14988 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14990 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14992 if (*pos
== l
->fixp
)
14995 if ((*pos
)->fx_r_type
== looking_for_rtype
14996 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14997 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14999 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15001 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15004 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15005 && fixup_has_matching_lo_p (*pos
));
15008 /* If we found a match, remove the high-part relocation from its
15009 current position and insert it before the low-part relocation.
15010 Make the offsets match so that fixup_has_matching_lo_p()
15013 We don't warn about unmatched high-part relocations since some
15014 versions of gcc have been known to emit dead "lui ...%hi(...)"
15016 if (lo_pos
!= NULL
)
15018 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15019 if (l
->fixp
->fx_next
!= *lo_pos
)
15021 *hi_pos
= l
->fixp
->fx_next
;
15022 l
->fixp
->fx_next
= *lo_pos
;
15030 mips_force_relocation (fixS
*fixp
)
15032 if (generic_force_reloc (fixp
))
15035 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15036 so that the linker relaxation can update targets. */
15037 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15038 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15039 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15042 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15043 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15044 microMIPS symbols so that we can do cross-mode branch diagnostics
15045 and BAL to JALX conversion by the linker. */
15046 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15047 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15048 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15050 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15053 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15054 if (ISA_IS_R6 (file_mips_opts
.isa
)
15055 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15056 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15057 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15058 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15059 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15060 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15061 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15067 /* Implement TC_FORCE_RELOCATION_ABS. */
15070 mips_force_relocation_abs (fixS
*fixp
)
15072 if (generic_force_reloc (fixp
))
15075 /* These relocations do not have enough bits in the in-place addend
15076 to hold an arbitrary absolute section's offset. */
15077 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15083 /* Read the instruction associated with RELOC from BUF. */
15085 static unsigned int
15086 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15088 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15089 return read_compressed_insn (buf
, 4);
15091 return read_insn (buf
);
15094 /* Write instruction INSN to BUF, given that it has been relocated
15098 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15099 unsigned long insn
)
15101 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15102 write_compressed_insn (buf
, insn
, 4);
15104 write_insn (buf
, insn
);
15107 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15108 to a symbol in another ISA mode, which cannot be converted to JALX. */
15111 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15113 unsigned long opcode
;
15117 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15120 other
= S_GET_OTHER (fixP
->fx_addsy
);
15121 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15122 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15123 switch (fixP
->fx_r_type
)
15125 case BFD_RELOC_MIPS_JMP
:
15126 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15127 case BFD_RELOC_MICROMIPS_JMP
:
15128 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15134 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15135 jump to a symbol in the same ISA mode. */
15138 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15140 unsigned long opcode
;
15144 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15147 other
= S_GET_OTHER (fixP
->fx_addsy
);
15148 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15149 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15150 switch (fixP
->fx_r_type
)
15152 case BFD_RELOC_MIPS_JMP
:
15153 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15154 case BFD_RELOC_MIPS16_JMP
:
15155 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15156 case BFD_RELOC_MICROMIPS_JMP
:
15157 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15163 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15164 to a symbol whose value plus addend is not aligned according to the
15165 ultimate (after linker relaxation) jump instruction's immediate field
15166 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15167 regular MIPS code, to (1 << 2). */
15170 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15172 bfd_boolean micro_to_mips_p
;
15176 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15179 other
= S_GET_OTHER (fixP
->fx_addsy
);
15180 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15181 val
+= fixP
->fx_offset
;
15182 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15183 && !ELF_ST_IS_MICROMIPS (other
));
15184 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15185 != ELF_ST_IS_COMPRESSED (other
));
15188 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15189 to a symbol whose annotation indicates another ISA mode. For absolute
15190 symbols check the ISA bit instead.
15192 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15193 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15194 MIPS symbols and associated with BAL instructions as these instructions
15195 may be be converted to JALX by the linker. */
15198 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15200 bfd_boolean absolute_p
;
15201 unsigned long opcode
;
15207 if (mips_ignore_branch_isa
)
15210 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15213 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15214 absolute_p
= bfd_is_abs_section (symsec
);
15216 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15217 other
= S_GET_OTHER (fixP
->fx_addsy
);
15219 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15220 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15221 switch (fixP
->fx_r_type
)
15223 case BFD_RELOC_16_PCREL_S2
:
15224 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15225 && opcode
!= 0x0411);
15226 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15227 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15228 && opcode
!= 0x4060);
15229 case BFD_RELOC_MIPS_21_PCREL_S2
:
15230 case BFD_RELOC_MIPS_26_PCREL_S2
:
15231 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15232 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15233 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15234 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15235 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15236 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15242 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15243 branch instruction pointed to by FIXP is not aligned according to the
15244 branch instruction's immediate field requirement. We need the addend
15245 to preserve the ISA bit and also the sum must not have bit 2 set. We
15246 must explicitly OR in the ISA bit from symbol annotation as the bit
15247 won't be set in the symbol's value then. */
15250 fix_bad_misaligned_branch_p (fixS
*fixP
)
15252 bfd_boolean absolute_p
;
15259 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15262 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15263 absolute_p
= bfd_is_abs_section (symsec
);
15265 val
= S_GET_VALUE (fixP
->fx_addsy
);
15266 other
= S_GET_OTHER (fixP
->fx_addsy
);
15267 off
= fixP
->fx_offset
;
15269 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15270 val
|= ELF_ST_IS_COMPRESSED (other
);
15272 return (val
& 0x3) != isa_bit
;
15275 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15276 and its calculated value VAL. */
15279 fix_validate_branch (fixS
*fixP
, valueT val
)
15281 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15283 _("branch to misaligned address (0x%lx)"),
15284 (long) (val
+ md_pcrel_from (fixP
)));
15285 else if (fix_bad_cross_mode_branch_p (fixP
))
15286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15287 _("branch to a symbol in another ISA mode"));
15288 else if (fix_bad_misaligned_branch_p (fixP
))
15289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15290 _("branch to misaligned address (0x%lx)"),
15291 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15292 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15293 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15294 _("cannot encode misaligned addend "
15295 "in the relocatable field (0x%lx)"),
15296 (long) fixP
->fx_offset
);
15299 /* Apply a fixup to the object file. */
15302 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15305 unsigned long insn
;
15306 reloc_howto_type
*howto
;
15308 if (fixP
->fx_pcrel
)
15309 switch (fixP
->fx_r_type
)
15311 case BFD_RELOC_16_PCREL_S2
:
15312 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15313 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15314 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15315 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15316 case BFD_RELOC_32_PCREL
:
15317 case BFD_RELOC_MIPS_21_PCREL_S2
:
15318 case BFD_RELOC_MIPS_26_PCREL_S2
:
15319 case BFD_RELOC_MIPS_18_PCREL_S3
:
15320 case BFD_RELOC_MIPS_19_PCREL_S2
:
15321 case BFD_RELOC_HI16_S_PCREL
:
15322 case BFD_RELOC_LO16_PCREL
:
15326 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15331 _("PC-relative reference to a different section"));
15335 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15336 that have no MIPS ELF equivalent. */
15337 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15339 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15344 gas_assert (fixP
->fx_size
== 2
15345 || fixP
->fx_size
== 4
15346 || fixP
->fx_r_type
== BFD_RELOC_8
15347 || fixP
->fx_r_type
== BFD_RELOC_16
15348 || fixP
->fx_r_type
== BFD_RELOC_64
15349 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15350 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15351 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15352 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15353 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15354 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15355 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15357 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15359 /* Don't treat parts of a composite relocation as done. There are two
15362 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15363 should nevertheless be emitted if the first part is.
15365 (2) In normal usage, composite relocations are never assembly-time
15366 constants. The easiest way of dealing with the pathological
15367 exceptions is to generate a relocation against STN_UNDEF and
15368 leave everything up to the linker. */
15369 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15372 switch (fixP
->fx_r_type
)
15374 case BFD_RELOC_MIPS_TLS_GD
:
15375 case BFD_RELOC_MIPS_TLS_LDM
:
15376 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15377 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15378 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15379 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15380 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15381 case BFD_RELOC_MIPS_TLS_TPREL32
:
15382 case BFD_RELOC_MIPS_TLS_TPREL64
:
15383 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15384 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15385 case BFD_RELOC_MICROMIPS_TLS_GD
:
15386 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15387 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15388 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15389 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15390 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15391 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15392 case BFD_RELOC_MIPS16_TLS_GD
:
15393 case BFD_RELOC_MIPS16_TLS_LDM
:
15394 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15395 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15396 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15397 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15398 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15399 if (fixP
->fx_addsy
)
15400 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15403 _("TLS relocation against a constant"));
15406 case BFD_RELOC_MIPS_JMP
:
15407 case BFD_RELOC_MIPS16_JMP
:
15408 case BFD_RELOC_MICROMIPS_JMP
:
15412 gas_assert (!fixP
->fx_done
);
15414 /* Shift is 2, unusually, for microMIPS JALX. */
15415 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15416 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15421 if (fix_bad_cross_mode_jump_p (fixP
))
15422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15423 _("jump to a symbol in another ISA mode"));
15424 else if (fix_bad_same_mode_jalx_p (fixP
))
15425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15426 _("JALX to a symbol in the same ISA mode"));
15427 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15429 _("jump to misaligned address (0x%lx)"),
15430 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15431 + fixP
->fx_offset
));
15432 else if (HAVE_IN_PLACE_ADDENDS
15433 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15434 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15435 _("cannot encode misaligned addend "
15436 "in the relocatable field (0x%lx)"),
15437 (long) fixP
->fx_offset
);
15439 /* Fall through. */
15441 case BFD_RELOC_MIPS_SHIFT5
:
15442 case BFD_RELOC_MIPS_SHIFT6
:
15443 case BFD_RELOC_MIPS_GOT_DISP
:
15444 case BFD_RELOC_MIPS_GOT_PAGE
:
15445 case BFD_RELOC_MIPS_GOT_OFST
:
15446 case BFD_RELOC_MIPS_SUB
:
15447 case BFD_RELOC_MIPS_INSERT_A
:
15448 case BFD_RELOC_MIPS_INSERT_B
:
15449 case BFD_RELOC_MIPS_DELETE
:
15450 case BFD_RELOC_MIPS_HIGHEST
:
15451 case BFD_RELOC_MIPS_HIGHER
:
15452 case BFD_RELOC_MIPS_SCN_DISP
:
15453 case BFD_RELOC_MIPS_REL16
:
15454 case BFD_RELOC_MIPS_RELGOT
:
15455 case BFD_RELOC_MIPS_JALR
:
15456 case BFD_RELOC_HI16
:
15457 case BFD_RELOC_HI16_S
:
15458 case BFD_RELOC_LO16
:
15459 case BFD_RELOC_GPREL16
:
15460 case BFD_RELOC_MIPS_LITERAL
:
15461 case BFD_RELOC_MIPS_CALL16
:
15462 case BFD_RELOC_MIPS_GOT16
:
15463 case BFD_RELOC_GPREL32
:
15464 case BFD_RELOC_MIPS_GOT_HI16
:
15465 case BFD_RELOC_MIPS_GOT_LO16
:
15466 case BFD_RELOC_MIPS_CALL_HI16
:
15467 case BFD_RELOC_MIPS_CALL_LO16
:
15468 case BFD_RELOC_HI16_S_PCREL
:
15469 case BFD_RELOC_LO16_PCREL
:
15470 case BFD_RELOC_MIPS16_GPREL
:
15471 case BFD_RELOC_MIPS16_GOT16
:
15472 case BFD_RELOC_MIPS16_CALL16
:
15473 case BFD_RELOC_MIPS16_HI16
:
15474 case BFD_RELOC_MIPS16_HI16_S
:
15475 case BFD_RELOC_MIPS16_LO16
:
15476 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15477 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15478 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15479 case BFD_RELOC_MICROMIPS_SUB
:
15480 case BFD_RELOC_MICROMIPS_HIGHEST
:
15481 case BFD_RELOC_MICROMIPS_HIGHER
:
15482 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15483 case BFD_RELOC_MICROMIPS_JALR
:
15484 case BFD_RELOC_MICROMIPS_HI16
:
15485 case BFD_RELOC_MICROMIPS_HI16_S
:
15486 case BFD_RELOC_MICROMIPS_LO16
:
15487 case BFD_RELOC_MICROMIPS_GPREL16
:
15488 case BFD_RELOC_MICROMIPS_LITERAL
:
15489 case BFD_RELOC_MICROMIPS_CALL16
:
15490 case BFD_RELOC_MICROMIPS_GOT16
:
15491 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15492 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15493 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15494 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15495 case BFD_RELOC_MIPS_EH
:
15500 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15502 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15503 if (mips16_reloc_p (fixP
->fx_r_type
))
15504 insn
|= mips16_immed_extend (value
, 16);
15506 insn
|= (value
& 0xffff);
15507 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15511 _("unsupported constant in relocation"));
15516 /* This is handled like BFD_RELOC_32, but we output a sign
15517 extended value if we are only 32 bits. */
15520 if (8 <= sizeof (valueT
))
15521 md_number_to_chars (buf
, *valP
, 8);
15526 if ((*valP
& 0x80000000) != 0)
15530 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15531 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15536 case BFD_RELOC_RVA
:
15538 case BFD_RELOC_32_PCREL
:
15541 /* If we are deleting this reloc entry, we must fill in the
15542 value now. This can happen if we have a .word which is not
15543 resolved when it appears but is later defined. */
15545 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15548 case BFD_RELOC_MIPS_21_PCREL_S2
:
15549 fix_validate_branch (fixP
, *valP
);
15550 if (!fixP
->fx_done
)
15553 if (*valP
+ 0x400000 <= 0x7fffff)
15555 insn
= read_insn (buf
);
15556 insn
|= (*valP
>> 2) & 0x1fffff;
15557 write_insn (buf
, insn
);
15560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15561 _("branch out of range"));
15564 case BFD_RELOC_MIPS_26_PCREL_S2
:
15565 fix_validate_branch (fixP
, *valP
);
15566 if (!fixP
->fx_done
)
15569 if (*valP
+ 0x8000000 <= 0xfffffff)
15571 insn
= read_insn (buf
);
15572 insn
|= (*valP
>> 2) & 0x3ffffff;
15573 write_insn (buf
, insn
);
15576 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15577 _("branch out of range"));
15580 case BFD_RELOC_MIPS_18_PCREL_S3
:
15581 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15583 _("PC-relative access using misaligned symbol (%lx)"),
15584 (long) S_GET_VALUE (fixP
->fx_addsy
));
15585 if ((fixP
->fx_offset
& 0x7) != 0)
15586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15587 _("PC-relative access using misaligned offset (%lx)"),
15588 (long) fixP
->fx_offset
);
15589 if (!fixP
->fx_done
)
15592 if (*valP
+ 0x100000 <= 0x1fffff)
15594 insn
= read_insn (buf
);
15595 insn
|= (*valP
>> 3) & 0x3ffff;
15596 write_insn (buf
, insn
);
15599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15600 _("PC-relative access out of range"));
15603 case BFD_RELOC_MIPS_19_PCREL_S2
:
15604 if ((*valP
& 0x3) != 0)
15605 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15606 _("PC-relative access to misaligned address (%lx)"),
15608 if (!fixP
->fx_done
)
15611 if (*valP
+ 0x100000 <= 0x1fffff)
15613 insn
= read_insn (buf
);
15614 insn
|= (*valP
>> 2) & 0x7ffff;
15615 write_insn (buf
, insn
);
15618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15619 _("PC-relative access out of range"));
15622 case BFD_RELOC_16_PCREL_S2
:
15623 fix_validate_branch (fixP
, *valP
);
15625 /* We need to save the bits in the instruction since fixup_segment()
15626 might be deleting the relocation entry (i.e., a branch within
15627 the current segment). */
15628 if (! fixP
->fx_done
)
15631 /* Update old instruction data. */
15632 insn
= read_insn (buf
);
15634 if (*valP
+ 0x20000 <= 0x3ffff)
15636 insn
|= (*valP
>> 2) & 0xffff;
15637 write_insn (buf
, insn
);
15639 else if (fixP
->fx_tcbit2
15641 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15642 && (fixP
->fx_frag
->fr_address
15643 < text_section
->vma
+ bfd_get_section_size (text_section
))
15644 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15645 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15646 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15648 /* The branch offset is too large. If this is an
15649 unconditional branch, and we are not generating PIC code,
15650 we can convert it to an absolute jump instruction. */
15651 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15652 insn
= 0x0c000000; /* jal */
15654 insn
= 0x08000000; /* j */
15655 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15657 fixP
->fx_addsy
= section_symbol (text_section
);
15658 *valP
+= md_pcrel_from (fixP
);
15659 write_insn (buf
, insn
);
15663 /* If we got here, we have branch-relaxation disabled,
15664 and there's nothing we can do to fix this instruction
15665 without turning it into a longer sequence. */
15666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15667 _("branch out of range"));
15671 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15672 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15673 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15674 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15675 gas_assert (!fixP
->fx_done
);
15676 if (fix_bad_cross_mode_branch_p (fixP
))
15677 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15678 _("branch to a symbol in another ISA mode"));
15679 else if (fixP
->fx_addsy
15680 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15681 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15682 && (fixP
->fx_offset
& 0x1) != 0)
15683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15684 _("branch to misaligned address (0x%lx)"),
15685 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15686 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15688 _("cannot encode misaligned addend "
15689 "in the relocatable field (0x%lx)"),
15690 (long) fixP
->fx_offset
);
15693 case BFD_RELOC_VTABLE_INHERIT
:
15696 && !S_IS_DEFINED (fixP
->fx_addsy
)
15697 && !S_IS_WEAK (fixP
->fx_addsy
))
15698 S_SET_WEAK (fixP
->fx_addsy
);
15701 case BFD_RELOC_NONE
:
15702 case BFD_RELOC_VTABLE_ENTRY
:
15710 /* Remember value for tc_gen_reloc. */
15711 fixP
->fx_addnumber
= *valP
;
15721 c
= get_symbol_name (&name
);
15722 p
= (symbolS
*) symbol_find_or_make (name
);
15723 (void) restore_line_pointer (c
);
15727 /* Align the current frag to a given power of two. If a particular
15728 fill byte should be used, FILL points to an integer that contains
15729 that byte, otherwise FILL is null.
15731 This function used to have the comment:
15733 The MIPS assembler also automatically adjusts any preceding label.
15735 The implementation therefore applied the adjustment to a maximum of
15736 one label. However, other label adjustments are applied to batches
15737 of labels, and adjusting just one caused problems when new labels
15738 were added for the sake of debugging or unwind information.
15739 We therefore adjust all preceding labels (given as LABELS) instead. */
15742 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15744 mips_emit_delays ();
15745 mips_record_compressed_mode ();
15746 if (fill
== NULL
&& subseg_text_p (now_seg
))
15747 frag_align_code (to
, 0);
15749 frag_align (to
, fill
? *fill
: 0, 0);
15750 record_alignment (now_seg
, to
);
15751 mips_move_labels (labels
, FALSE
);
15754 /* Align to a given power of two. .align 0 turns off the automatic
15755 alignment used by the data creating pseudo-ops. */
15758 s_align (int x ATTRIBUTE_UNUSED
)
15760 int temp
, fill_value
, *fill_ptr
;
15761 long max_alignment
= 28;
15763 /* o Note that the assembler pulls down any immediately preceding label
15764 to the aligned address.
15765 o It's not documented but auto alignment is reinstated by
15766 a .align pseudo instruction.
15767 o Note also that after auto alignment is turned off the mips assembler
15768 issues an error on attempt to assemble an improperly aligned data item.
15771 temp
= get_absolute_expression ();
15772 if (temp
> max_alignment
)
15773 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15776 as_warn (_("alignment negative, 0 assumed"));
15779 if (*input_line_pointer
== ',')
15781 ++input_line_pointer
;
15782 fill_value
= get_absolute_expression ();
15783 fill_ptr
= &fill_value
;
15789 segment_info_type
*si
= seg_info (now_seg
);
15790 struct insn_label_list
*l
= si
->label_list
;
15791 /* Auto alignment should be switched on by next section change. */
15793 mips_align (temp
, fill_ptr
, l
);
15800 demand_empty_rest_of_line ();
15804 s_change_sec (int sec
)
15808 /* The ELF backend needs to know that we are changing sections, so
15809 that .previous works correctly. We could do something like check
15810 for an obj_section_change_hook macro, but that might be confusing
15811 as it would not be appropriate to use it in the section changing
15812 functions in read.c, since obj-elf.c intercepts those. FIXME:
15813 This should be cleaner, somehow. */
15814 obj_elf_section_change_hook ();
15816 mips_emit_delays ();
15827 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15828 demand_empty_rest_of_line ();
15832 seg
= subseg_new (RDATA_SECTION_NAME
,
15833 (subsegT
) get_absolute_expression ());
15834 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15835 | SEC_READONLY
| SEC_RELOC
15837 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15838 record_alignment (seg
, 4);
15839 demand_empty_rest_of_line ();
15843 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15844 bfd_set_section_flags (stdoutput
, seg
,
15845 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15846 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15847 record_alignment (seg
, 4);
15848 demand_empty_rest_of_line ();
15852 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15853 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15854 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15855 record_alignment (seg
, 4);
15856 demand_empty_rest_of_line ();
15864 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15867 char *section_name
;
15872 int section_entry_size
;
15873 int section_alignment
;
15875 saved_ilp
= input_line_pointer
;
15876 endc
= get_symbol_name (§ion_name
);
15877 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
15879 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
15881 /* Do we have .section Name<,"flags">? */
15882 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15884 /* Just after name is now '\0'. */
15885 (void) restore_line_pointer (endc
);
15886 input_line_pointer
= saved_ilp
;
15887 obj_elf_section (ignore
);
15891 section_name
= xstrdup (section_name
);
15892 c
= restore_line_pointer (endc
);
15894 input_line_pointer
++;
15896 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15898 section_type
= get_absolute_expression ();
15902 if (*input_line_pointer
++ == ',')
15903 section_flag
= get_absolute_expression ();
15907 if (*input_line_pointer
++ == ',')
15908 section_entry_size
= get_absolute_expression ();
15910 section_entry_size
= 0;
15912 if (*input_line_pointer
++ == ',')
15913 section_alignment
= get_absolute_expression ();
15915 section_alignment
= 0;
15917 /* FIXME: really ignore? */
15918 (void) section_alignment
;
15920 /* When using the generic form of .section (as implemented by obj-elf.c),
15921 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15922 traditionally had to fall back on the more common @progbits instead.
15924 There's nothing really harmful in this, since bfd will correct
15925 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15926 means that, for backwards compatibility, the special_section entries
15927 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15929 Even so, we shouldn't force users of the MIPS .section syntax to
15930 incorrectly label the sections as SHT_PROGBITS. The best compromise
15931 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15932 generic type-checking code. */
15933 if (section_type
== SHT_MIPS_DWARF
)
15934 section_type
= SHT_PROGBITS
;
15936 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
15937 section_entry_size
, 0, 0, 0);
15939 if (now_seg
->name
!= section_name
)
15940 free (section_name
);
15944 mips_enable_auto_align (void)
15950 s_cons (int log_size
)
15952 segment_info_type
*si
= seg_info (now_seg
);
15953 struct insn_label_list
*l
= si
->label_list
;
15955 mips_emit_delays ();
15956 if (log_size
> 0 && auto_align
)
15957 mips_align (log_size
, 0, l
);
15958 cons (1 << log_size
);
15959 mips_clear_insn_labels ();
15963 s_float_cons (int type
)
15965 segment_info_type
*si
= seg_info (now_seg
);
15966 struct insn_label_list
*l
= si
->label_list
;
15968 mips_emit_delays ();
15973 mips_align (3, 0, l
);
15975 mips_align (2, 0, l
);
15979 mips_clear_insn_labels ();
15982 /* Handle .globl. We need to override it because on Irix 5 you are
15985 where foo is an undefined symbol, to mean that foo should be
15986 considered to be the address of a function. */
15989 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15998 c
= get_symbol_name (&name
);
15999 symbolP
= symbol_find_or_make (name
);
16000 S_SET_EXTERNAL (symbolP
);
16002 *input_line_pointer
= c
;
16003 SKIP_WHITESPACE_AFTER_NAME ();
16005 /* On Irix 5, every global symbol that is not explicitly labelled as
16006 being a function is apparently labelled as being an object. */
16009 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16010 && (*input_line_pointer
!= ','))
16015 c
= get_symbol_name (&secname
);
16016 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16018 as_bad (_("%s: no such section"), secname
);
16019 (void) restore_line_pointer (c
);
16021 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16022 flag
= BSF_FUNCTION
;
16025 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16027 c
= *input_line_pointer
;
16030 input_line_pointer
++;
16031 SKIP_WHITESPACE ();
16032 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16038 demand_empty_rest_of_line ();
16042 s_option (int x ATTRIBUTE_UNUSED
)
16047 c
= get_symbol_name (&opt
);
16051 /* FIXME: What does this mean? */
16053 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16057 i
= atoi (opt
+ 3);
16058 if (i
!= 0 && i
!= 2)
16059 as_bad (_(".option pic%d not supported"), i
);
16060 else if (mips_pic
== VXWORKS_PIC
)
16061 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16066 mips_pic
= SVR4_PIC
;
16067 mips_abicalls
= TRUE
;
16070 if (mips_pic
== SVR4_PIC
)
16072 if (g_switch_seen
&& g_switch_value
!= 0)
16073 as_warn (_("-G may not be used with SVR4 PIC code"));
16074 g_switch_value
= 0;
16075 bfd_set_gp_size (stdoutput
, 0);
16079 as_warn (_("unrecognized option \"%s\""), opt
);
16081 (void) restore_line_pointer (c
);
16082 demand_empty_rest_of_line ();
16085 /* This structure is used to hold a stack of .set values. */
16087 struct mips_option_stack
16089 struct mips_option_stack
*next
;
16090 struct mips_set_options options
;
16093 static struct mips_option_stack
*mips_opts_stack
;
16095 /* Return status for .set/.module option handling. */
16097 enum code_option_type
16099 /* Unrecognized option. */
16100 OPTION_TYPE_BAD
= -1,
16102 /* Ordinary option. */
16103 OPTION_TYPE_NORMAL
,
16105 /* ISA changing option. */
16109 /* Handle common .set/.module options. Return status indicating option
16112 static enum code_option_type
16113 parse_code_option (char * name
)
16115 bfd_boolean isa_set
= FALSE
;
16116 const struct mips_ase
*ase
;
16118 if (strncmp (name
, "at=", 3) == 0)
16120 char *s
= name
+ 3;
16122 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16123 as_bad (_("unrecognized register name `%s'"), s
);
16125 else if (strcmp (name
, "at") == 0)
16126 mips_opts
.at
= ATREG
;
16127 else if (strcmp (name
, "noat") == 0)
16128 mips_opts
.at
= ZERO
;
16129 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16130 mips_opts
.nomove
= 0;
16131 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16132 mips_opts
.nomove
= 1;
16133 else if (strcmp (name
, "bopt") == 0)
16134 mips_opts
.nobopt
= 0;
16135 else if (strcmp (name
, "nobopt") == 0)
16136 mips_opts
.nobopt
= 1;
16137 else if (strcmp (name
, "gp=32") == 0)
16139 else if (strcmp (name
, "gp=64") == 0)
16141 else if (strcmp (name
, "fp=32") == 0)
16143 else if (strcmp (name
, "fp=xx") == 0)
16145 else if (strcmp (name
, "fp=64") == 0)
16147 else if (strcmp (name
, "softfloat") == 0)
16148 mips_opts
.soft_float
= 1;
16149 else if (strcmp (name
, "hardfloat") == 0)
16150 mips_opts
.soft_float
= 0;
16151 else if (strcmp (name
, "singlefloat") == 0)
16152 mips_opts
.single_float
= 1;
16153 else if (strcmp (name
, "doublefloat") == 0)
16154 mips_opts
.single_float
= 0;
16155 else if (strcmp (name
, "nooddspreg") == 0)
16156 mips_opts
.oddspreg
= 0;
16157 else if (strcmp (name
, "oddspreg") == 0)
16158 mips_opts
.oddspreg
= 1;
16159 else if (strcmp (name
, "mips16") == 0
16160 || strcmp (name
, "MIPS-16") == 0)
16161 mips_opts
.mips16
= 1;
16162 else if (strcmp (name
, "nomips16") == 0
16163 || strcmp (name
, "noMIPS-16") == 0)
16164 mips_opts
.mips16
= 0;
16165 else if (strcmp (name
, "micromips") == 0)
16166 mips_opts
.micromips
= 1;
16167 else if (strcmp (name
, "nomicromips") == 0)
16168 mips_opts
.micromips
= 0;
16169 else if (name
[0] == 'n'
16171 && (ase
= mips_lookup_ase (name
+ 2)))
16172 mips_set_ase (ase
, &mips_opts
, FALSE
);
16173 else if ((ase
= mips_lookup_ase (name
)))
16174 mips_set_ase (ase
, &mips_opts
, TRUE
);
16175 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16177 /* Permit the user to change the ISA and architecture on the fly.
16178 Needless to say, misuse can cause serious problems. */
16179 if (strncmp (name
, "arch=", 5) == 0)
16181 const struct mips_cpu_info
*p
;
16183 p
= mips_parse_cpu ("internal use", name
+ 5);
16185 as_bad (_("unknown architecture %s"), name
+ 5);
16188 mips_opts
.arch
= p
->cpu
;
16189 mips_opts
.isa
= p
->isa
;
16193 else if (strncmp (name
, "mips", 4) == 0)
16195 const struct mips_cpu_info
*p
;
16197 p
= mips_parse_cpu ("internal use", name
);
16199 as_bad (_("unknown ISA level %s"), name
+ 4);
16202 mips_opts
.arch
= p
->cpu
;
16203 mips_opts
.isa
= p
->isa
;
16208 as_bad (_("unknown ISA or architecture %s"), name
);
16210 else if (strcmp (name
, "autoextend") == 0)
16211 mips_opts
.noautoextend
= 0;
16212 else if (strcmp (name
, "noautoextend") == 0)
16213 mips_opts
.noautoextend
= 1;
16214 else if (strcmp (name
, "insn32") == 0)
16215 mips_opts
.insn32
= TRUE
;
16216 else if (strcmp (name
, "noinsn32") == 0)
16217 mips_opts
.insn32
= FALSE
;
16218 else if (strcmp (name
, "sym32") == 0)
16219 mips_opts
.sym32
= TRUE
;
16220 else if (strcmp (name
, "nosym32") == 0)
16221 mips_opts
.sym32
= FALSE
;
16223 return OPTION_TYPE_BAD
;
16225 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16228 /* Handle the .set pseudo-op. */
16231 s_mipsset (int x ATTRIBUTE_UNUSED
)
16233 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16234 char *name
= input_line_pointer
, ch
;
16236 file_mips_check_options ();
16238 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16239 ++input_line_pointer
;
16240 ch
= *input_line_pointer
;
16241 *input_line_pointer
= '\0';
16243 if (strchr (name
, ','))
16245 /* Generic ".set" directive; use the generic handler. */
16246 *input_line_pointer
= ch
;
16247 input_line_pointer
= name
;
16252 if (strcmp (name
, "reorder") == 0)
16254 if (mips_opts
.noreorder
)
16257 else if (strcmp (name
, "noreorder") == 0)
16259 if (!mips_opts
.noreorder
)
16260 start_noreorder ();
16262 else if (strcmp (name
, "macro") == 0)
16263 mips_opts
.warn_about_macros
= 0;
16264 else if (strcmp (name
, "nomacro") == 0)
16266 if (mips_opts
.noreorder
== 0)
16267 as_bad (_("`noreorder' must be set before `nomacro'"));
16268 mips_opts
.warn_about_macros
= 1;
16270 else if (strcmp (name
, "gp=default") == 0)
16271 mips_opts
.gp
= file_mips_opts
.gp
;
16272 else if (strcmp (name
, "fp=default") == 0)
16273 mips_opts
.fp
= file_mips_opts
.fp
;
16274 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16276 mips_opts
.isa
= file_mips_opts
.isa
;
16277 mips_opts
.arch
= file_mips_opts
.arch
;
16278 mips_opts
.gp
= file_mips_opts
.gp
;
16279 mips_opts
.fp
= file_mips_opts
.fp
;
16281 else if (strcmp (name
, "push") == 0)
16283 struct mips_option_stack
*s
;
16285 s
= XNEW (struct mips_option_stack
);
16286 s
->next
= mips_opts_stack
;
16287 s
->options
= mips_opts
;
16288 mips_opts_stack
= s
;
16290 else if (strcmp (name
, "pop") == 0)
16292 struct mips_option_stack
*s
;
16294 s
= mips_opts_stack
;
16296 as_bad (_(".set pop with no .set push"));
16299 /* If we're changing the reorder mode we need to handle
16300 delay slots correctly. */
16301 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16302 start_noreorder ();
16303 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16306 mips_opts
= s
->options
;
16307 mips_opts_stack
= s
->next
;
16313 type
= parse_code_option (name
);
16314 if (type
== OPTION_TYPE_BAD
)
16315 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16318 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16319 registers based on what is supported by the arch/cpu. */
16320 if (type
== OPTION_TYPE_ISA
)
16322 switch (mips_opts
.isa
)
16327 /* MIPS I cannot support FPXX. */
16329 /* fall-through. */
16336 if (mips_opts
.fp
!= 0)
16352 if (mips_opts
.fp
!= 0)
16354 if (mips_opts
.arch
== CPU_R5900
)
16361 as_bad (_("unknown ISA level %s"), name
+ 4);
16366 mips_check_options (&mips_opts
, FALSE
);
16368 mips_check_isa_supports_ases ();
16369 *input_line_pointer
= ch
;
16370 demand_empty_rest_of_line ();
16373 /* Handle the .module pseudo-op. */
16376 s_module (int ignore ATTRIBUTE_UNUSED
)
16378 char *name
= input_line_pointer
, ch
;
16380 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16381 ++input_line_pointer
;
16382 ch
= *input_line_pointer
;
16383 *input_line_pointer
= '\0';
16385 if (!file_mips_opts_checked
)
16387 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16388 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16390 /* Update module level settings from mips_opts. */
16391 file_mips_opts
= mips_opts
;
16394 as_bad (_(".module is not permitted after generating code"));
16396 *input_line_pointer
= ch
;
16397 demand_empty_rest_of_line ();
16400 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16401 .option pic2. It means to generate SVR4 PIC calls. */
16404 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16406 mips_pic
= SVR4_PIC
;
16407 mips_abicalls
= TRUE
;
16409 if (g_switch_seen
&& g_switch_value
!= 0)
16410 as_warn (_("-G may not be used with SVR4 PIC code"));
16411 g_switch_value
= 0;
16413 bfd_set_gp_size (stdoutput
, 0);
16414 demand_empty_rest_of_line ();
16417 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16418 PIC code. It sets the $gp register for the function based on the
16419 function address, which is in the register named in the argument.
16420 This uses a relocation against _gp_disp, which is handled specially
16421 by the linker. The result is:
16422 lui $gp,%hi(_gp_disp)
16423 addiu $gp,$gp,%lo(_gp_disp)
16424 addu $gp,$gp,.cpload argument
16425 The .cpload argument is normally $25 == $t9.
16427 The -mno-shared option changes this to:
16428 lui $gp,%hi(__gnu_local_gp)
16429 addiu $gp,$gp,%lo(__gnu_local_gp)
16430 and the argument is ignored. This saves an instruction, but the
16431 resulting code is not position independent; it uses an absolute
16432 address for __gnu_local_gp. Thus code assembled with -mno-shared
16433 can go into an ordinary executable, but not into a shared library. */
16436 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16442 file_mips_check_options ();
16444 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16445 .cpload is ignored. */
16446 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16452 if (mips_opts
.mips16
)
16454 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16455 ignore_rest_of_line ();
16459 /* .cpload should be in a .set noreorder section. */
16460 if (mips_opts
.noreorder
== 0)
16461 as_warn (_(".cpload not in noreorder section"));
16463 reg
= tc_get_register (0);
16465 /* If we need to produce a 64-bit address, we are better off using
16466 the default instruction sequence. */
16467 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16469 ex
.X_op
= O_symbol
;
16470 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16472 ex
.X_op_symbol
= NULL
;
16473 ex
.X_add_number
= 0;
16475 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16476 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16478 mips_mark_labels ();
16479 mips_assembling_insn
= TRUE
;
16482 macro_build_lui (&ex
, mips_gp_register
);
16483 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16484 mips_gp_register
, BFD_RELOC_LO16
);
16486 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16487 mips_gp_register
, reg
);
16490 mips_assembling_insn
= FALSE
;
16491 demand_empty_rest_of_line ();
16494 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16495 .cpsetup $reg1, offset|$reg2, label
16497 If offset is given, this results in:
16498 sd $gp, offset($sp)
16499 lui $gp, %hi(%neg(%gp_rel(label)))
16500 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16501 daddu $gp, $gp, $reg1
16503 If $reg2 is given, this results in:
16505 lui $gp, %hi(%neg(%gp_rel(label)))
16506 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16507 daddu $gp, $gp, $reg1
16508 $reg1 is normally $25 == $t9.
16510 The -mno-shared option replaces the last three instructions with
16512 addiu $gp,$gp,%lo(_gp) */
16515 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16517 expressionS ex_off
;
16518 expressionS ex_sym
;
16521 file_mips_check_options ();
16523 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16524 We also need NewABI support. */
16525 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16531 if (mips_opts
.mips16
)
16533 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16534 ignore_rest_of_line ();
16538 reg1
= tc_get_register (0);
16539 SKIP_WHITESPACE ();
16540 if (*input_line_pointer
!= ',')
16542 as_bad (_("missing argument separator ',' for .cpsetup"));
16546 ++input_line_pointer
;
16547 SKIP_WHITESPACE ();
16548 if (*input_line_pointer
== '$')
16550 mips_cpreturn_register
= tc_get_register (0);
16551 mips_cpreturn_offset
= -1;
16555 mips_cpreturn_offset
= get_absolute_expression ();
16556 mips_cpreturn_register
= -1;
16558 SKIP_WHITESPACE ();
16559 if (*input_line_pointer
!= ',')
16561 as_bad (_("missing argument separator ',' for .cpsetup"));
16565 ++input_line_pointer
;
16566 SKIP_WHITESPACE ();
16567 expression (&ex_sym
);
16569 mips_mark_labels ();
16570 mips_assembling_insn
= TRUE
;
16573 if (mips_cpreturn_register
== -1)
16575 ex_off
.X_op
= O_constant
;
16576 ex_off
.X_add_symbol
= NULL
;
16577 ex_off
.X_op_symbol
= NULL
;
16578 ex_off
.X_add_number
= mips_cpreturn_offset
;
16580 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16581 BFD_RELOC_LO16
, SP
);
16584 move_register (mips_cpreturn_register
, mips_gp_register
);
16586 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16588 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16589 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16592 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16593 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16594 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16596 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16597 mips_gp_register
, reg1
);
16603 ex
.X_op
= O_symbol
;
16604 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16605 ex
.X_op_symbol
= NULL
;
16606 ex
.X_add_number
= 0;
16608 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16609 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16611 macro_build_lui (&ex
, mips_gp_register
);
16612 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16613 mips_gp_register
, BFD_RELOC_LO16
);
16618 mips_assembling_insn
= FALSE
;
16619 demand_empty_rest_of_line ();
16623 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16625 file_mips_check_options ();
16627 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16628 .cplocal is ignored. */
16629 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16635 if (mips_opts
.mips16
)
16637 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16638 ignore_rest_of_line ();
16642 mips_gp_register
= tc_get_register (0);
16643 demand_empty_rest_of_line ();
16646 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16647 offset from $sp. The offset is remembered, and after making a PIC
16648 call $gp is restored from that location. */
16651 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16655 file_mips_check_options ();
16657 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16658 .cprestore is ignored. */
16659 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16665 if (mips_opts
.mips16
)
16667 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16668 ignore_rest_of_line ();
16672 mips_cprestore_offset
= get_absolute_expression ();
16673 mips_cprestore_valid
= 1;
16675 ex
.X_op
= O_constant
;
16676 ex
.X_add_symbol
= NULL
;
16677 ex
.X_op_symbol
= NULL
;
16678 ex
.X_add_number
= mips_cprestore_offset
;
16680 mips_mark_labels ();
16681 mips_assembling_insn
= TRUE
;
16684 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16685 SP
, HAVE_64BIT_ADDRESSES
);
16688 mips_assembling_insn
= FALSE
;
16689 demand_empty_rest_of_line ();
16692 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16693 was given in the preceding .cpsetup, it results in:
16694 ld $gp, offset($sp)
16696 If a register $reg2 was given there, it results in:
16697 or $gp, $reg2, $0 */
16700 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16704 file_mips_check_options ();
16706 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16707 We also need NewABI support. */
16708 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16714 if (mips_opts
.mips16
)
16716 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16717 ignore_rest_of_line ();
16721 mips_mark_labels ();
16722 mips_assembling_insn
= TRUE
;
16725 if (mips_cpreturn_register
== -1)
16727 ex
.X_op
= O_constant
;
16728 ex
.X_add_symbol
= NULL
;
16729 ex
.X_op_symbol
= NULL
;
16730 ex
.X_add_number
= mips_cpreturn_offset
;
16732 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16735 move_register (mips_gp_register
, mips_cpreturn_register
);
16739 mips_assembling_insn
= FALSE
;
16740 demand_empty_rest_of_line ();
16743 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16744 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16745 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16746 debug information or MIPS16 TLS. */
16749 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16750 bfd_reloc_code_real_type rtype
)
16757 if (ex
.X_op
!= O_symbol
)
16759 as_bad (_("unsupported use of %s"), dirstr
);
16760 ignore_rest_of_line ();
16763 p
= frag_more (bytes
);
16764 md_number_to_chars (p
, 0, bytes
);
16765 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16766 demand_empty_rest_of_line ();
16767 mips_clear_insn_labels ();
16770 /* Handle .dtprelword. */
16773 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16775 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16778 /* Handle .dtpreldword. */
16781 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16783 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16786 /* Handle .tprelword. */
16789 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16791 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16794 /* Handle .tpreldword. */
16797 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16799 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16802 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16803 code. It sets the offset to use in gp_rel relocations. */
16806 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16808 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16809 We also need NewABI support. */
16810 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16816 mips_gprel_offset
= get_absolute_expression ();
16818 demand_empty_rest_of_line ();
16821 /* Handle the .gpword pseudo-op. This is used when generating PIC
16822 code. It generates a 32 bit GP relative reloc. */
16825 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16827 segment_info_type
*si
;
16828 struct insn_label_list
*l
;
16832 /* When not generating PIC code, this is treated as .word. */
16833 if (mips_pic
!= SVR4_PIC
)
16839 si
= seg_info (now_seg
);
16840 l
= si
->label_list
;
16841 mips_emit_delays ();
16843 mips_align (2, 0, l
);
16846 mips_clear_insn_labels ();
16848 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16850 as_bad (_("unsupported use of .gpword"));
16851 ignore_rest_of_line ();
16855 md_number_to_chars (p
, 0, 4);
16856 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16857 BFD_RELOC_GPREL32
);
16859 demand_empty_rest_of_line ();
16863 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16865 segment_info_type
*si
;
16866 struct insn_label_list
*l
;
16870 /* When not generating PIC code, this is treated as .dword. */
16871 if (mips_pic
!= SVR4_PIC
)
16877 si
= seg_info (now_seg
);
16878 l
= si
->label_list
;
16879 mips_emit_delays ();
16881 mips_align (3, 0, l
);
16884 mips_clear_insn_labels ();
16886 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16888 as_bad (_("unsupported use of .gpdword"));
16889 ignore_rest_of_line ();
16893 md_number_to_chars (p
, 0, 8);
16894 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16895 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16897 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16898 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16899 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16901 demand_empty_rest_of_line ();
16904 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16905 tables. It generates a R_MIPS_EH reloc. */
16908 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16913 mips_emit_delays ();
16916 mips_clear_insn_labels ();
16918 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16920 as_bad (_("unsupported use of .ehword"));
16921 ignore_rest_of_line ();
16925 md_number_to_chars (p
, 0, 4);
16926 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16927 BFD_RELOC_32_PCREL
);
16929 demand_empty_rest_of_line ();
16932 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16933 tables in SVR4 PIC code. */
16936 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16940 file_mips_check_options ();
16942 /* This is ignored when not generating SVR4 PIC code. */
16943 if (mips_pic
!= SVR4_PIC
)
16949 mips_mark_labels ();
16950 mips_assembling_insn
= TRUE
;
16952 /* Add $gp to the register named as an argument. */
16954 reg
= tc_get_register (0);
16955 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16958 mips_assembling_insn
= FALSE
;
16959 demand_empty_rest_of_line ();
16962 /* Handle the .insn pseudo-op. This marks instruction labels in
16963 mips16/micromips mode. This permits the linker to handle them specially,
16964 such as generating jalx instructions when needed. We also make
16965 them odd for the duration of the assembly, in order to generate the
16966 right sort of code. We will make them even in the adjust_symtab
16967 routine, while leaving them marked. This is convenient for the
16968 debugger and the disassembler. The linker knows to make them odd
16972 s_insn (int ignore ATTRIBUTE_UNUSED
)
16974 file_mips_check_options ();
16975 file_ase_mips16
|= mips_opts
.mips16
;
16976 file_ase_micromips
|= mips_opts
.micromips
;
16978 mips_mark_labels ();
16980 demand_empty_rest_of_line ();
16983 /* Handle the .nan pseudo-op. */
16986 s_nan (int ignore ATTRIBUTE_UNUSED
)
16988 static const char str_legacy
[] = "legacy";
16989 static const char str_2008
[] = "2008";
16992 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16994 if (i
== sizeof (str_2008
) - 1
16995 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
16997 else if (i
== sizeof (str_legacy
) - 1
16998 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17000 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17003 as_bad (_("`%s' does not support legacy NaN"),
17004 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17007 as_bad (_("bad .nan directive"));
17009 input_line_pointer
+= i
;
17010 demand_empty_rest_of_line ();
17013 /* Handle a .stab[snd] directive. Ideally these directives would be
17014 implemented in a transparent way, so that removing them would not
17015 have any effect on the generated instructions. However, s_stab
17016 internally changes the section, so in practice we need to decide
17017 now whether the preceding label marks compressed code. We do not
17018 support changing the compression mode of a label after a .stab*
17019 directive, such as in:
17025 so the current mode wins. */
17028 s_mips_stab (int type
)
17030 mips_mark_labels ();
17034 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17037 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17044 c
= get_symbol_name (&name
);
17045 symbolP
= symbol_find_or_make (name
);
17046 S_SET_WEAK (symbolP
);
17047 *input_line_pointer
= c
;
17049 SKIP_WHITESPACE_AFTER_NAME ();
17051 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17053 if (S_IS_DEFINED (symbolP
))
17055 as_bad (_("ignoring attempt to redefine symbol %s"),
17056 S_GET_NAME (symbolP
));
17057 ignore_rest_of_line ();
17061 if (*input_line_pointer
== ',')
17063 ++input_line_pointer
;
17064 SKIP_WHITESPACE ();
17068 if (exp
.X_op
!= O_symbol
)
17070 as_bad (_("bad .weakext directive"));
17071 ignore_rest_of_line ();
17074 symbol_set_value_expression (symbolP
, &exp
);
17077 demand_empty_rest_of_line ();
17080 /* Parse a register string into a number. Called from the ECOFF code
17081 to parse .frame. The argument is non-zero if this is the frame
17082 register, so that we can record it in mips_frame_reg. */
17085 tc_get_register (int frame
)
17089 SKIP_WHITESPACE ();
17090 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17094 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17095 mips_frame_reg_valid
= 1;
17096 mips_cprestore_valid
= 0;
17102 md_section_align (asection
*seg
, valueT addr
)
17104 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17106 /* We don't need to align ELF sections to the full alignment.
17107 However, Irix 5 may prefer that we align them at least to a 16
17108 byte boundary. We don't bother to align the sections if we
17109 are targeted for an embedded system. */
17110 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17115 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17118 /* Utility routine, called from above as well. If called while the
17119 input file is still being read, it's only an approximation. (For
17120 example, a symbol may later become defined which appeared to be
17121 undefined earlier.) */
17124 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17129 if (g_switch_value
> 0)
17131 const char *symname
;
17134 /* Find out whether this symbol can be referenced off the $gp
17135 register. It can be if it is smaller than the -G size or if
17136 it is in the .sdata or .sbss section. Certain symbols can
17137 not be referenced off the $gp, although it appears as though
17139 symname
= S_GET_NAME (sym
);
17140 if (symname
!= (const char *) NULL
17141 && (strcmp (symname
, "eprol") == 0
17142 || strcmp (symname
, "etext") == 0
17143 || strcmp (symname
, "_gp") == 0
17144 || strcmp (symname
, "edata") == 0
17145 || strcmp (symname
, "_fbss") == 0
17146 || strcmp (symname
, "_fdata") == 0
17147 || strcmp (symname
, "_ftext") == 0
17148 || strcmp (symname
, "end") == 0
17149 || strcmp (symname
, "_gp_disp") == 0))
17151 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17153 #ifndef NO_ECOFF_DEBUGGING
17154 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17155 && (symbol_get_obj (sym
)->ecoff_extern_size
17156 <= g_switch_value
))
17158 /* We must defer this decision until after the whole
17159 file has been read, since there might be a .extern
17160 after the first use of this symbol. */
17161 || (before_relaxing
17162 #ifndef NO_ECOFF_DEBUGGING
17163 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17165 && S_GET_VALUE (sym
) == 0)
17166 || (S_GET_VALUE (sym
) != 0
17167 && S_GET_VALUE (sym
) <= g_switch_value
)))
17171 const char *segname
;
17173 segname
= segment_name (S_GET_SEGMENT (sym
));
17174 gas_assert (strcmp (segname
, ".lit8") != 0
17175 && strcmp (segname
, ".lit4") != 0);
17176 change
= (strcmp (segname
, ".sdata") != 0
17177 && strcmp (segname
, ".sbss") != 0
17178 && strncmp (segname
, ".sdata.", 7) != 0
17179 && strncmp (segname
, ".sbss.", 6) != 0
17180 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17181 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17186 /* We are not optimizing for the $gp register. */
17191 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17194 pic_need_relax (symbolS
*sym
)
17198 /* Handle the case of a symbol equated to another symbol. */
17199 while (symbol_equated_reloc_p (sym
))
17203 /* It's possible to get a loop here in a badly written program. */
17204 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17210 if (symbol_section_p (sym
))
17213 symsec
= S_GET_SEGMENT (sym
);
17215 /* This must duplicate the test in adjust_reloc_syms. */
17216 return (!bfd_is_und_section (symsec
)
17217 && !bfd_is_abs_section (symsec
)
17218 && !bfd_is_com_section (symsec
)
17219 /* A global or weak symbol is treated as external. */
17220 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17223 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17224 convert a section-relative value VAL to the equivalent PC-relative
17228 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17229 offsetT val
, long stretch
)
17234 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17236 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17238 /* If the relax_marker of the symbol fragment differs from the
17239 relax_marker of this fragment, we have not yet adjusted the
17240 symbol fragment fr_address. We want to add in STRETCH in
17241 order to get a better estimate of the address. This
17242 particularly matters because of the shift bits. */
17243 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17247 /* Adjust stretch for any alignment frag. Note that if have
17248 been expanding the earlier code, the symbol may be
17249 defined in what appears to be an earlier frag. FIXME:
17250 This doesn't handle the fr_subtype field, which specifies
17251 a maximum number of bytes to skip when doing an
17253 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17255 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17258 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17260 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17269 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17271 /* The base address rules are complicated. The base address of
17272 a branch is the following instruction. The base address of a
17273 PC relative load or add is the instruction itself, but if it
17274 is in a delay slot (in which case it can not be extended) use
17275 the address of the instruction whose delay slot it is in. */
17276 if (pcrel_op
->include_isa_bit
)
17280 /* If we are currently assuming that this frag should be
17281 extended, then the current address is two bytes higher. */
17282 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17285 /* Ignore the low bit in the target, since it will be set
17286 for a text label. */
17289 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17291 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17294 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17299 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17300 extended opcode. SEC is the section the frag is in. */
17303 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17305 const struct mips_int_operand
*operand
;
17310 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17312 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17315 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17316 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17317 operand
= mips16_immed_operand (type
, FALSE
);
17318 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17319 || (operand
->root
.type
== OP_PCREL
17321 : !bfd_is_abs_section (symsec
)))
17324 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17326 if (operand
->root
.type
== OP_PCREL
)
17328 const struct mips_pcrel_operand
*pcrel_op
;
17331 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17334 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17335 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17337 /* If any of the shifted bits are set, we must use an extended
17338 opcode. If the address depends on the size of this
17339 instruction, this can lead to a loop, so we arrange to always
17340 use an extended opcode. */
17341 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17343 fragp
->fr_subtype
=
17344 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17348 /* If we are about to mark a frag as extended because the value
17349 is precisely the next value above maxtiny, then there is a
17350 chance of an infinite loop as in the following code:
17355 In this case when the la is extended, foo is 0x3fc bytes
17356 away, so the la can be shrunk, but then foo is 0x400 away, so
17357 the la must be extended. To avoid this loop, we mark the
17358 frag as extended if it was small, and is about to become
17359 extended with the next value above maxtiny. */
17360 maxtiny
= mips_int_operand_max (operand
);
17361 if (val
== maxtiny
+ (1 << operand
->shift
)
17362 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17364 fragp
->fr_subtype
=
17365 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17370 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17373 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17374 macro expansion. SEC is the section the frag is in. We only
17375 support PC-relative instructions (LA, DLA, LW, LD) here, in
17376 non-PIC code using 32-bit addressing. */
17379 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17381 const struct mips_pcrel_operand
*pcrel_op
;
17382 const struct mips_int_operand
*operand
;
17387 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17389 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17391 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17394 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17400 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17401 if (bfd_is_abs_section (symsec
))
17403 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17405 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17408 operand
= mips16_immed_operand (type
, TRUE
);
17409 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17410 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17411 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17413 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17420 /* Compute the length of a branch sequence, and adjust the
17421 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17422 worst-case length is computed, with UPDATE being used to indicate
17423 whether an unconditional (-1), branch-likely (+1) or regular (0)
17424 branch is to be computed. */
17426 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17428 bfd_boolean toofar
;
17432 && S_IS_DEFINED (fragp
->fr_symbol
)
17433 && !S_IS_WEAK (fragp
->fr_symbol
)
17434 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17439 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17441 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17445 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17448 /* If the symbol is not defined or it's in a different segment,
17449 we emit the long sequence. */
17452 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17454 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17455 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17456 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17457 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17458 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17464 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17467 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17469 /* Additional space for PIC loading of target address. */
17471 if (mips_opts
.isa
== ISA_MIPS1
)
17472 /* Additional space for $at-stabilizing nop. */
17476 /* If branch is conditional. */
17477 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17484 /* Get a FRAG's branch instruction delay slot size, either from the
17485 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17486 or SHORT_INSN_SIZE otherwise. */
17489 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17491 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17494 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17496 return short_insn_size
;
17499 /* Compute the length of a branch sequence, and adjust the
17500 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17501 worst-case length is computed, with UPDATE being used to indicate
17502 whether an unconditional (-1), or regular (0) branch is to be
17506 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17508 bfd_boolean insn32
= TRUE
;
17509 bfd_boolean nods
= TRUE
;
17510 bfd_boolean pic
= TRUE
;
17511 bfd_boolean al
= TRUE
;
17512 int short_insn_size
;
17513 bfd_boolean toofar
;
17518 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17519 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17520 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17521 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17523 short_insn_size
= insn32
? 4 : 2;
17526 && S_IS_DEFINED (fragp
->fr_symbol
)
17527 && !S_IS_WEAK (fragp
->fr_symbol
)
17528 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17533 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17534 /* Ignore the low bit in the target, since it will be set
17535 for a text label. */
17536 if ((val
& 1) != 0)
17539 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17543 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17546 /* If the symbol is not defined or it's in a different segment,
17547 we emit the long sequence. */
17550 if (fragp
&& update
17551 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17552 fragp
->fr_subtype
= (toofar
17553 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17554 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17559 bfd_boolean compact_known
= fragp
!= NULL
;
17560 bfd_boolean compact
= FALSE
;
17561 bfd_boolean uncond
;
17565 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17566 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17569 uncond
= update
< 0;
17571 /* If label is out of range, we turn branch <br>:
17573 <br> label # 4 bytes
17580 # compact && (!PIC || insn32)
17583 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17584 length
+= short_insn_size
;
17586 /* If assembling PIC code, we further turn:
17592 lw/ld at, %got(label)(gp) # 4 bytes
17593 d/addiu at, %lo(label) # 4 bytes
17594 jr/c at # 2/4 bytes
17597 length
+= 4 + short_insn_size
;
17599 /* Add an extra nop if the jump has no compact form and we need
17600 to fill the delay slot. */
17601 if ((!pic
|| al
) && nods
)
17603 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17604 : short_insn_size
);
17606 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17608 <brneg> 0f # 4 bytes
17609 nop # 2/4 bytes if !compact
17612 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17616 /* Add an extra nop to fill the delay slot. */
17617 gas_assert (fragp
);
17618 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17624 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17625 bit accordingly. */
17628 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17630 bfd_boolean toofar
;
17633 && S_IS_DEFINED (fragp
->fr_symbol
)
17634 && !S_IS_WEAK (fragp
->fr_symbol
)
17635 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17641 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17642 /* Ignore the low bit in the target, since it will be set
17643 for a text label. */
17644 if ((val
& 1) != 0)
17647 /* Assume this is a 2-byte branch. */
17648 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17650 /* We try to avoid the infinite loop by not adding 2 more bytes for
17655 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17657 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17658 else if (type
== 'E')
17659 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17664 /* If the symbol is not defined or it's in a different segment,
17665 we emit a normal 32-bit branch. */
17668 if (fragp
&& update
17669 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17671 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17672 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17680 /* Estimate the size of a frag before relaxing. Unless this is the
17681 mips16, we are not really relaxing here, and the final size is
17682 encoded in the subtype information. For the mips16, we have to
17683 decide whether we are using an extended opcode or not. */
17686 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17690 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17693 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17695 return fragp
->fr_var
;
17698 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17700 /* We don't want to modify the EXTENDED bit here; it might get us
17701 into infinite loops. We change it only in mips_relax_frag(). */
17702 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17705 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
17708 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17712 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17713 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17714 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17715 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17716 fragp
->fr_var
= length
;
17721 if (mips_pic
== VXWORKS_PIC
)
17722 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17724 else if (RELAX_PIC (fragp
->fr_subtype
))
17725 change
= pic_need_relax (fragp
->fr_symbol
);
17727 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17731 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17732 return -RELAX_FIRST (fragp
->fr_subtype
);
17735 return -RELAX_SECOND (fragp
->fr_subtype
);
17738 /* This is called to see whether a reloc against a defined symbol
17739 should be converted into a reloc against a section. */
17742 mips_fix_adjustable (fixS
*fixp
)
17744 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17745 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17748 if (fixp
->fx_addsy
== NULL
)
17751 /* Allow relocs used for EH tables. */
17752 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17755 /* If symbol SYM is in a mergeable section, relocations of the form
17756 SYM + 0 can usually be made section-relative. The mergeable data
17757 is then identified by the section offset rather than by the symbol.
17759 However, if we're generating REL LO16 relocations, the offset is split
17760 between the LO16 and partnering high part relocation. The linker will
17761 need to recalculate the complete offset in order to correctly identify
17764 The linker has traditionally not looked for the partnering high part
17765 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17766 placed anywhere. Rather than break backwards compatibility by changing
17767 this, it seems better not to force the issue, and instead keep the
17768 original symbol. This will work with either linker behavior. */
17769 if ((lo16_reloc_p (fixp
->fx_r_type
)
17770 || reloc_needs_lo_p (fixp
->fx_r_type
))
17771 && HAVE_IN_PLACE_ADDENDS
17772 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17775 /* There is no place to store an in-place offset for JALR relocations. */
17776 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17779 /* Likewise an in-range offset of limited PC-relative relocations may
17780 overflow the in-place relocatable field if recalculated against the
17781 start address of the symbol's containing section.
17783 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17784 section relative to allow linker relaxations to be performed later on. */
17785 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17786 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17789 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17790 to a floating-point stub. The same is true for non-R_MIPS16_26
17791 relocations against MIPS16 functions; in this case, the stub becomes
17792 the function's canonical address.
17794 Floating-point stubs are stored in unique .mips16.call.* or
17795 .mips16.fn.* sections. If a stub T for function F is in section S,
17796 the first relocation in section S must be against F; this is how the
17797 linker determines the target function. All relocations that might
17798 resolve to T must also be against F. We therefore have the following
17799 restrictions, which are given in an intentionally-redundant way:
17801 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17804 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17805 if that stub might be used.
17807 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17810 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17811 that stub might be used.
17813 There is a further restriction:
17815 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17816 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17817 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17818 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17819 against MIPS16 or microMIPS symbols because we need to keep the
17820 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17821 detection and JAL or BAL to JALX instruction conversion in the
17824 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17825 against a MIPS16 symbol. We deal with (5) by additionally leaving
17826 alone any jump and branch relocations against a microMIPS symbol.
17828 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17829 relocation against some symbol R, no relocation against R may be
17830 reduced. (Note that this deals with (2) as well as (1) because
17831 relocations against global symbols will never be reduced on ELF
17832 targets.) This approach is a little simpler than trying to detect
17833 stub sections, and gives the "all or nothing" per-symbol consistency
17834 that we have for MIPS16 symbols. */
17835 if (fixp
->fx_subsy
== NULL
17836 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17837 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17838 && (jmp_reloc_p (fixp
->fx_r_type
)
17839 || b_reloc_p (fixp
->fx_r_type
)))
17840 || *symbol_get_tc (fixp
->fx_addsy
)))
17846 /* Translate internal representation of relocation info to BFD target
17850 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17852 static arelent
*retval
[4];
17854 bfd_reloc_code_real_type code
;
17856 memset (retval
, 0, sizeof(retval
));
17857 reloc
= retval
[0] = XCNEW (arelent
);
17858 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
17859 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17860 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17862 if (fixp
->fx_pcrel
)
17864 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17865 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
17866 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17867 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17868 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17869 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17870 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17871 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17872 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17873 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17874 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17875 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17877 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17878 Relocations want only the symbol offset. */
17879 switch (fixp
->fx_r_type
)
17881 case BFD_RELOC_MIPS_18_PCREL_S3
:
17882 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
17885 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17889 else if (HAVE_IN_PLACE_ADDENDS
17890 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
17891 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
17892 + fixp
->fx_where
, 4) >> 26) == 0x3c)
17894 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17895 addend accordingly. */
17896 reloc
->addend
= fixp
->fx_addnumber
>> 1;
17899 reloc
->addend
= fixp
->fx_addnumber
;
17901 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17902 entry to be used in the relocation's section offset. */
17903 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17905 reloc
->address
= reloc
->addend
;
17909 code
= fixp
->fx_r_type
;
17911 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17912 if (reloc
->howto
== NULL
)
17914 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17915 _("cannot represent %s relocation in this object file"
17917 bfd_get_reloc_code_name (code
));
17924 /* Relax a machine dependent frag. This returns the amount by which
17925 the current size of the frag should change. */
17928 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17930 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17932 offsetT old_var
= fragp
->fr_var
;
17934 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17936 return fragp
->fr_var
- old_var
;
17939 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17941 offsetT old_var
= fragp
->fr_var
;
17942 offsetT new_var
= 4;
17944 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17945 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17946 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17947 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17948 fragp
->fr_var
= new_var
;
17950 return new_var
- old_var
;
17953 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17956 if (!mips16_extended_frag (fragp
, sec
, stretch
))
17958 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17960 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
17963 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17965 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17971 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
17973 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17975 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
17976 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17979 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17981 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17989 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17991 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17993 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17994 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
17999 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18007 /* Convert a machine dependent frag. */
18010 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18012 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18015 unsigned long insn
;
18019 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18020 insn
= read_insn (buf
);
18022 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18024 /* We generate a fixup instead of applying it right now
18025 because, if there are linker relaxations, we're going to
18026 need the relocations. */
18027 exp
.X_op
= O_symbol
;
18028 exp
.X_add_symbol
= fragp
->fr_symbol
;
18029 exp
.X_add_number
= fragp
->fr_offset
;
18031 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18032 BFD_RELOC_16_PCREL_S2
);
18033 fixp
->fx_file
= fragp
->fr_file
;
18034 fixp
->fx_line
= fragp
->fr_line
;
18036 buf
= write_insn (buf
, insn
);
18042 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18043 _("relaxed out-of-range branch into a jump"));
18045 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18048 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18050 /* Reverse the branch. */
18051 switch ((insn
>> 28) & 0xf)
18054 if ((insn
& 0xff000000) == 0x47000000
18055 || (insn
& 0xff600000) == 0x45600000)
18057 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18058 reversed by tweaking bit 23. */
18059 insn
^= 0x00800000;
18063 /* bc[0-3][tf]l? instructions can have the condition
18064 reversed by tweaking a single TF bit, and their
18065 opcodes all have 0x4???????. */
18066 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18067 insn
^= 0x00010000;
18072 /* bltz 0x04000000 bgez 0x04010000
18073 bltzal 0x04100000 bgezal 0x04110000 */
18074 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18075 insn
^= 0x00010000;
18079 /* beq 0x10000000 bne 0x14000000
18080 blez 0x18000000 bgtz 0x1c000000 */
18081 insn
^= 0x04000000;
18089 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18091 /* Clear the and-link bit. */
18092 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18094 /* bltzal 0x04100000 bgezal 0x04110000
18095 bltzall 0x04120000 bgezall 0x04130000 */
18096 insn
&= ~0x00100000;
18099 /* Branch over the branch (if the branch was likely) or the
18100 full jump (not likely case). Compute the offset from the
18101 current instruction to branch to. */
18102 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18106 /* How many bytes in instructions we've already emitted? */
18107 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18108 /* How many bytes in instructions from here to the end? */
18109 i
= fragp
->fr_var
- i
;
18111 /* Convert to instruction count. */
18113 /* Branch counts from the next instruction. */
18116 /* Branch over the jump. */
18117 buf
= write_insn (buf
, insn
);
18120 buf
= write_insn (buf
, 0);
18122 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18124 /* beql $0, $0, 2f */
18126 /* Compute the PC offset from the current instruction to
18127 the end of the variable frag. */
18128 /* How many bytes in instructions we've already emitted? */
18129 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18130 /* How many bytes in instructions from here to the end? */
18131 i
= fragp
->fr_var
- i
;
18132 /* Convert to instruction count. */
18134 /* Don't decrement i, because we want to branch over the
18138 buf
= write_insn (buf
, insn
);
18139 buf
= write_insn (buf
, 0);
18143 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18146 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18147 ? 0x0c000000 : 0x08000000);
18148 exp
.X_op
= O_symbol
;
18149 exp
.X_add_symbol
= fragp
->fr_symbol
;
18150 exp
.X_add_number
= fragp
->fr_offset
;
18152 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18153 FALSE
, BFD_RELOC_MIPS_JMP
);
18154 fixp
->fx_file
= fragp
->fr_file
;
18155 fixp
->fx_line
= fragp
->fr_line
;
18157 buf
= write_insn (buf
, insn
);
18161 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18163 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18164 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18165 insn
|= at
<< OP_SH_RT
;
18166 exp
.X_op
= O_symbol
;
18167 exp
.X_add_symbol
= fragp
->fr_symbol
;
18168 exp
.X_add_number
= fragp
->fr_offset
;
18170 if (fragp
->fr_offset
)
18172 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18173 exp
.X_add_number
= 0;
18176 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18177 FALSE
, BFD_RELOC_MIPS_GOT16
);
18178 fixp
->fx_file
= fragp
->fr_file
;
18179 fixp
->fx_line
= fragp
->fr_line
;
18181 buf
= write_insn (buf
, insn
);
18183 if (mips_opts
.isa
== ISA_MIPS1
)
18185 buf
= write_insn (buf
, 0);
18187 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18188 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18189 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18191 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18192 FALSE
, BFD_RELOC_LO16
);
18193 fixp
->fx_file
= fragp
->fr_file
;
18194 fixp
->fx_line
= fragp
->fr_line
;
18196 buf
= write_insn (buf
, insn
);
18199 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18203 insn
|= at
<< OP_SH_RS
;
18205 buf
= write_insn (buf
, insn
);
18209 fragp
->fr_fix
+= fragp
->fr_var
;
18210 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18214 /* Relax microMIPS branches. */
18215 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18217 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18218 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18219 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18220 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18221 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18222 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18223 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18224 bfd_boolean short_ds
;
18225 unsigned long insn
;
18229 exp
.X_op
= O_symbol
;
18230 exp
.X_add_symbol
= fragp
->fr_symbol
;
18231 exp
.X_add_number
= fragp
->fr_offset
;
18233 fragp
->fr_fix
+= fragp
->fr_var
;
18235 /* Handle 16-bit branches that fit or are forced to fit. */
18236 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18238 /* We generate a fixup instead of applying it right now,
18239 because if there is linker relaxation, we're going to
18240 need the relocations. */
18242 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18243 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18244 else if (type
== 'E')
18245 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18246 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18250 fixp
->fx_file
= fragp
->fr_file
;
18251 fixp
->fx_line
= fragp
->fr_line
;
18253 /* These relocations can have an addend that won't fit in
18255 fixp
->fx_no_overflow
= 1;
18260 /* Handle 32-bit branches that fit or are forced to fit. */
18261 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18262 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18264 /* We generate a fixup instead of applying it right now,
18265 because if there is linker relaxation, we're going to
18266 need the relocations. */
18267 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18268 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18269 fixp
->fx_file
= fragp
->fr_file
;
18270 fixp
->fx_line
= fragp
->fr_line
;
18274 insn
= read_compressed_insn (buf
, 4);
18279 /* Check the short-delay-slot bit. */
18280 if (!al
|| (insn
& 0x02000000) != 0)
18281 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18283 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18286 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18291 /* Relax 16-bit branches to 32-bit branches. */
18294 insn
= read_compressed_insn (buf
, 2);
18296 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18297 insn
= 0x94000000; /* beq */
18298 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18300 unsigned long regno
;
18302 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18303 regno
= micromips_to_32_reg_d_map
[regno
];
18304 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18305 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18310 /* Nothing else to do, just write it out. */
18311 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18312 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18314 buf
= write_compressed_insn (buf
, insn
, 4);
18316 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18317 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18322 insn
= read_compressed_insn (buf
, 4);
18324 /* Relax 32-bit branches to a sequence of instructions. */
18325 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18326 _("relaxed out-of-range branch into a jump"));
18328 /* Set the short-delay-slot bit. */
18329 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18331 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18335 /* Reverse the branch. */
18336 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18337 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18338 insn
^= 0x20000000;
18339 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18340 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18341 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18342 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18343 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18344 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18345 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18346 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18347 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18348 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18349 insn
^= 0x00400000;
18350 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18351 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18352 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18353 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18354 insn
^= 0x00200000;
18355 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18357 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18359 insn
^= 0x00800000;
18365 /* Clear the and-link and short-delay-slot bits. */
18366 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18368 /* bltzal 0x40200000 bgezal 0x40600000 */
18369 /* bltzals 0x42200000 bgezals 0x42600000 */
18370 insn
&= ~0x02200000;
18373 /* Make a label at the end for use with the branch. */
18374 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18375 micromips_label_inc ();
18376 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18379 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18380 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18381 fixp
->fx_file
= fragp
->fr_file
;
18382 fixp
->fx_line
= fragp
->fr_line
;
18384 /* Branch over the jump. */
18385 buf
= write_compressed_insn (buf
, insn
, 4);
18391 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18393 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18399 unsigned long jal
= (short_ds
|| nods
18400 ? 0x74000000 : 0xf4000000); /* jal/s */
18402 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18403 insn
= al
? jal
: 0xd4000000;
18405 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18406 BFD_RELOC_MICROMIPS_JMP
);
18407 fixp
->fx_file
= fragp
->fr_file
;
18408 fixp
->fx_line
= fragp
->fr_line
;
18410 buf
= write_compressed_insn (buf
, insn
, 4);
18412 if (compact
|| nods
)
18416 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18418 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18423 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18425 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18426 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18427 insn
|= at
<< MICROMIPSOP_SH_RT
;
18429 if (exp
.X_add_number
)
18431 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18432 exp
.X_add_number
= 0;
18435 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18436 BFD_RELOC_MICROMIPS_GOT16
);
18437 fixp
->fx_file
= fragp
->fr_file
;
18438 fixp
->fx_line
= fragp
->fr_line
;
18440 buf
= write_compressed_insn (buf
, insn
, 4);
18442 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18443 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18444 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18446 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18447 BFD_RELOC_MICROMIPS_LO16
);
18448 fixp
->fx_file
= fragp
->fr_file
;
18449 fixp
->fx_line
= fragp
->fr_line
;
18451 buf
= write_compressed_insn (buf
, insn
, 4);
18456 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18457 insn
|= at
<< MICROMIPSOP_SH_RS
;
18459 buf
= write_compressed_insn (buf
, insn
, 4);
18461 if (compact
|| nods
)
18463 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18467 /* jr/jrc/jalr/jalrs $at */
18468 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18469 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18471 insn
= al
? jalr
: jr
;
18472 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18474 buf
= write_compressed_insn (buf
, insn
, 2);
18479 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18481 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18486 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18490 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18493 const struct mips_int_operand
*operand
;
18496 unsigned int user_length
;
18497 bfd_boolean need_reloc
;
18498 unsigned long insn
;
18503 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18504 operand
= mips16_immed_operand (type
, FALSE
);
18506 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18507 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18508 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18510 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18511 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18512 || (operand
->root
.type
== OP_PCREL
&& !mac
18514 : !bfd_is_abs_section (symsec
)));
18516 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18518 const struct mips_pcrel_operand
*pcrel_op
;
18520 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18522 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18524 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18525 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18526 _("branch to a symbol in another ISA mode"));
18527 else if ((fragp
->fr_offset
& 0x1) != 0)
18528 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18529 _("branch to misaligned address (0x%lx)"),
18533 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18535 /* Make sure the section winds up with the alignment we have
18537 if (operand
->shift
> 0)
18538 record_alignment (asec
, operand
->shift
);
18541 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18542 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18545 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18546 _("macro instruction expanded into multiple "
18547 "instructions in a branch delay slot"));
18549 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18550 _("extended instruction in a branch delay slot"));
18552 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18553 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18554 _("macro instruction expanded into multiple "
18557 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18559 insn
= read_compressed_insn (buf
, 2);
18561 insn
|= MIPS16_EXTEND
;
18563 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18565 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18576 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18577 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18583 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18585 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18586 fragp
->fr_symbol
, fragp
->fr_offset
,
18587 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18588 fixp
->fx_file
= fragp
->fr_file
;
18589 fixp
->fx_line
= fragp
->fr_line
;
18591 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ 8, 4,
18592 fragp
->fr_symbol
, fragp
->fr_offset
,
18593 FALSE
, BFD_RELOC_MIPS16_LO16
);
18594 fixp
->fx_file
= fragp
->fr_file
;
18595 fixp
->fx_line
= fragp
->fr_line
;
18600 switch (insn
& 0xf800)
18602 case 0x0800: /* ADDIU */
18603 reg
= (insn
>> 8) & 0x7;
18604 op
= 0xf0004800 | (reg
<< 8);
18606 case 0xb000: /* LW */
18607 reg
= (insn
>> 8) & 0x7;
18608 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18610 case 0xf800: /* I64 */
18611 reg
= (insn
>> 5) & 0x7;
18612 switch (insn
& 0x0700)
18614 case 0x0400: /* LD */
18615 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18617 case 0x0600: /* DADDIU */
18618 op
= 0xf000fd00 | (reg
<< 5);
18628 new = 0xf0006800 | (reg
<< 8); /* LI */
18629 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18630 buf
= write_compressed_insn (buf
, new, 4);
18631 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18632 buf
= write_compressed_insn (buf
, new, 4);
18633 op
|= mips16_immed_extend (val
, 16);
18634 buf
= write_compressed_insn (buf
, op
, 4);
18636 fragp
->fr_fix
+= 12;
18640 unsigned int length
= ext
? 4 : 2;
18644 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18652 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18657 if (mac
|| reloc
== BFD_RELOC_NONE
)
18658 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18659 _("unsupported relocation"));
18662 exp
.X_op
= O_symbol
;
18663 exp
.X_add_symbol
= fragp
->fr_symbol
;
18664 exp
.X_add_number
= fragp
->fr_offset
;
18666 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18669 fixp
->fx_file
= fragp
->fr_file
;
18670 fixp
->fx_line
= fragp
->fr_line
;
18673 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18674 _("invalid unextended operand value"));
18677 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18678 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18680 gas_assert (mips16_opcode_length (insn
) == length
);
18681 write_compressed_insn (buf
, insn
, length
);
18682 fragp
->fr_fix
+= length
;
18687 relax_substateT subtype
= fragp
->fr_subtype
;
18688 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18689 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18693 first
= RELAX_FIRST (subtype
);
18694 second
= RELAX_SECOND (subtype
);
18695 fixp
= (fixS
*) fragp
->fr_opcode
;
18697 /* If the delay slot chosen does not match the size of the instruction,
18698 then emit a warning. */
18699 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18700 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18705 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18706 | RELAX_DELAY_SLOT_SIZE_FIRST
18707 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18708 msg
= macro_warning (s
);
18710 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18714 /* Possibly emit a warning if we've chosen the longer option. */
18715 if (use_second
== second_longer
)
18721 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18722 msg
= macro_warning (s
);
18724 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18728 /* Go through all the fixups for the first sequence. Disable them
18729 (by marking them as done) if we're going to use the second
18730 sequence instead. */
18732 && fixp
->fx_frag
== fragp
18733 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18735 if (subtype
& RELAX_USE_SECOND
)
18737 fixp
= fixp
->fx_next
;
18740 /* Go through the fixups for the second sequence. Disable them if
18741 we're going to use the first sequence, otherwise adjust their
18742 addresses to account for the relaxation. */
18743 while (fixp
&& fixp
->fx_frag
== fragp
)
18745 if (subtype
& RELAX_USE_SECOND
)
18746 fixp
->fx_where
-= first
;
18749 fixp
= fixp
->fx_next
;
18752 /* Now modify the frag contents. */
18753 if (subtype
& RELAX_USE_SECOND
)
18757 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18758 memmove (start
, start
+ first
, second
);
18759 fragp
->fr_fix
-= first
;
18762 fragp
->fr_fix
-= second
;
18766 /* This function is called after the relocs have been generated.
18767 We've been storing mips16 text labels as odd. Here we convert them
18768 back to even for the convenience of the debugger. */
18771 mips_frob_file_after_relocs (void)
18774 unsigned int count
, i
;
18776 syms
= bfd_get_outsymbols (stdoutput
);
18777 count
= bfd_get_symcount (stdoutput
);
18778 for (i
= 0; i
< count
; i
++, syms
++)
18779 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18780 && ((*syms
)->value
& 1) != 0)
18782 (*syms
)->value
&= ~1;
18783 /* If the symbol has an odd size, it was probably computed
18784 incorrectly, so adjust that as well. */
18785 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18786 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18790 /* This function is called whenever a label is defined, including fake
18791 labels instantiated off the dot special symbol. It is used when
18792 handling branch delays; if a branch has a label, we assume we cannot
18793 move it. This also bumps the value of the symbol by 1 in compressed
18797 mips_record_label (symbolS
*sym
)
18799 segment_info_type
*si
= seg_info (now_seg
);
18800 struct insn_label_list
*l
;
18802 if (free_insn_labels
== NULL
)
18803 l
= XNEW (struct insn_label_list
);
18806 l
= free_insn_labels
;
18807 free_insn_labels
= l
->next
;
18811 l
->next
= si
->label_list
;
18812 si
->label_list
= l
;
18815 /* This function is called as tc_frob_label() whenever a label is defined
18816 and adds a DWARF-2 record we only want for true labels. */
18819 mips_define_label (symbolS
*sym
)
18821 mips_record_label (sym
);
18822 dwarf2_emit_label (sym
);
18825 /* This function is called by tc_new_dot_label whenever a new dot symbol
18829 mips_add_dot_label (symbolS
*sym
)
18831 mips_record_label (sym
);
18832 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18833 mips_compressed_mark_label (sym
);
18836 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18837 static unsigned int
18838 mips_convert_ase_flags (int ase
)
18840 unsigned int ext_ases
= 0;
18843 ext_ases
|= AFL_ASE_DSP
;
18844 if (ase
& ASE_DSPR2
)
18845 ext_ases
|= AFL_ASE_DSPR2
;
18846 if (ase
& ASE_DSPR3
)
18847 ext_ases
|= AFL_ASE_DSPR3
;
18849 ext_ases
|= AFL_ASE_EVA
;
18851 ext_ases
|= AFL_ASE_MCU
;
18852 if (ase
& ASE_MDMX
)
18853 ext_ases
|= AFL_ASE_MDMX
;
18854 if (ase
& ASE_MIPS3D
)
18855 ext_ases
|= AFL_ASE_MIPS3D
;
18857 ext_ases
|= AFL_ASE_MT
;
18858 if (ase
& ASE_SMARTMIPS
)
18859 ext_ases
|= AFL_ASE_SMARTMIPS
;
18860 if (ase
& ASE_VIRT
)
18861 ext_ases
|= AFL_ASE_VIRT
;
18863 ext_ases
|= AFL_ASE_MSA
;
18865 ext_ases
|= AFL_ASE_XPA
;
18869 /* Some special processing for a MIPS ELF file. */
18872 mips_elf_final_processing (void)
18875 Elf_Internal_ABIFlags_v0 flags
;
18879 switch (file_mips_opts
.isa
)
18882 flags
.isa_level
= 1;
18885 flags
.isa_level
= 2;
18888 flags
.isa_level
= 3;
18891 flags
.isa_level
= 4;
18894 flags
.isa_level
= 5;
18897 flags
.isa_level
= 32;
18901 flags
.isa_level
= 32;
18905 flags
.isa_level
= 32;
18909 flags
.isa_level
= 32;
18913 flags
.isa_level
= 32;
18917 flags
.isa_level
= 64;
18921 flags
.isa_level
= 64;
18925 flags
.isa_level
= 64;
18929 flags
.isa_level
= 64;
18933 flags
.isa_level
= 64;
18938 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
18939 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
18940 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
18941 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
18943 flags
.cpr2_size
= AFL_REG_NONE
;
18944 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18945 Tag_GNU_MIPS_ABI_FP
);
18946 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
18947 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
18948 if (file_ase_mips16
)
18949 flags
.ases
|= AFL_ASE_MIPS16
;
18950 if (file_ase_micromips
)
18951 flags
.ases
|= AFL_ASE_MICROMIPS
;
18953 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
18954 || file_mips_opts
.fp
== 64)
18955 && file_mips_opts
.oddspreg
)
18956 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
18959 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
18960 ((Elf_External_ABIFlags_v0
*)
18963 /* Write out the register information. */
18964 if (mips_abi
!= N64_ABI
)
18968 s
.ri_gprmask
= mips_gprmask
;
18969 s
.ri_cprmask
[0] = mips_cprmask
[0];
18970 s
.ri_cprmask
[1] = mips_cprmask
[1];
18971 s
.ri_cprmask
[2] = mips_cprmask
[2];
18972 s
.ri_cprmask
[3] = mips_cprmask
[3];
18973 /* The gp_value field is set by the MIPS ELF backend. */
18975 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18976 ((Elf32_External_RegInfo
*)
18977 mips_regmask_frag
));
18981 Elf64_Internal_RegInfo s
;
18983 s
.ri_gprmask
= mips_gprmask
;
18985 s
.ri_cprmask
[0] = mips_cprmask
[0];
18986 s
.ri_cprmask
[1] = mips_cprmask
[1];
18987 s
.ri_cprmask
[2] = mips_cprmask
[2];
18988 s
.ri_cprmask
[3] = mips_cprmask
[3];
18989 /* The gp_value field is set by the MIPS ELF backend. */
18991 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18992 ((Elf64_External_RegInfo
*)
18993 mips_regmask_frag
));
18996 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18997 sort of BFD interface for this. */
18998 if (mips_any_noreorder
)
18999 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19000 if (mips_pic
!= NO_PIC
)
19002 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19003 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19006 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19008 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19009 defined at present; this might need to change in future. */
19010 if (file_ase_mips16
)
19011 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19012 if (file_ase_micromips
)
19013 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19014 if (file_mips_opts
.ase
& ASE_MDMX
)
19015 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19017 /* Set the MIPS ELF ABI flags. */
19018 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19019 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19020 else if (mips_abi
== O64_ABI
)
19021 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19022 else if (mips_abi
== EABI_ABI
)
19024 if (file_mips_opts
.gp
== 64)
19025 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19027 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19029 else if (mips_abi
== N32_ABI
)
19030 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
19032 /* Nothing to do for N64_ABI. */
19034 if (mips_32bitmode
)
19035 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19037 if (mips_nan2008
== 1)
19038 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19040 /* 32 bit code with 64 bit FP registers. */
19041 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19042 Tag_GNU_MIPS_ABI_FP
);
19043 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19044 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19047 typedef struct proc
{
19049 symbolS
*func_end_sym
;
19050 unsigned long reg_mask
;
19051 unsigned long reg_offset
;
19052 unsigned long fpreg_mask
;
19053 unsigned long fpreg_offset
;
19054 unsigned long frame_offset
;
19055 unsigned long frame_reg
;
19056 unsigned long pc_reg
;
19059 static procS cur_proc
;
19060 static procS
*cur_proc_ptr
;
19061 static int numprocs
;
19063 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19064 as "2", and a normal nop as "0". */
19066 #define NOP_OPCODE_MIPS 0
19067 #define NOP_OPCODE_MIPS16 1
19068 #define NOP_OPCODE_MICROMIPS 2
19071 mips_nop_opcode (void)
19073 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19074 return NOP_OPCODE_MICROMIPS
;
19075 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19076 return NOP_OPCODE_MIPS16
;
19078 return NOP_OPCODE_MIPS
;
19081 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19082 32-bit microMIPS NOPs here (if applicable). */
19085 mips_handle_align (fragS
*fragp
)
19089 int bytes
, size
, excess
;
19092 if (fragp
->fr_type
!= rs_align_code
)
19095 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19097 switch (nop_opcode
)
19099 case NOP_OPCODE_MICROMIPS
:
19100 opcode
= micromips_nop32_insn
.insn_opcode
;
19103 case NOP_OPCODE_MIPS16
:
19104 opcode
= mips16_nop_insn
.insn_opcode
;
19107 case NOP_OPCODE_MIPS
:
19109 opcode
= nop_insn
.insn_opcode
;
19114 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19115 excess
= bytes
% size
;
19117 /* Handle the leading part if we're not inserting a whole number of
19118 instructions, and make it the end of the fixed part of the frag.
19119 Try to fit in a short microMIPS NOP if applicable and possible,
19120 and use zeroes otherwise. */
19121 gas_assert (excess
< 4);
19122 fragp
->fr_fix
+= excess
;
19127 /* Fall through. */
19129 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19131 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19135 /* Fall through. */
19138 /* Fall through. */
19143 md_number_to_chars (p
, opcode
, size
);
19144 fragp
->fr_var
= size
;
19153 if (*input_line_pointer
== '-')
19155 ++input_line_pointer
;
19158 if (!ISDIGIT (*input_line_pointer
))
19159 as_bad (_("expected simple number"));
19160 if (input_line_pointer
[0] == '0')
19162 if (input_line_pointer
[1] == 'x')
19164 input_line_pointer
+= 2;
19165 while (ISXDIGIT (*input_line_pointer
))
19168 val
|= hex_value (*input_line_pointer
++);
19170 return negative
? -val
: val
;
19174 ++input_line_pointer
;
19175 while (ISDIGIT (*input_line_pointer
))
19178 val
|= *input_line_pointer
++ - '0';
19180 return negative
? -val
: val
;
19183 if (!ISDIGIT (*input_line_pointer
))
19185 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19186 *input_line_pointer
, *input_line_pointer
);
19187 as_warn (_("invalid number"));
19190 while (ISDIGIT (*input_line_pointer
))
19193 val
+= *input_line_pointer
++ - '0';
19195 return negative
? -val
: val
;
19198 /* The .file directive; just like the usual .file directive, but there
19199 is an initial number which is the ECOFF file index. In the non-ECOFF
19200 case .file implies DWARF-2. */
19203 s_mips_file (int x ATTRIBUTE_UNUSED
)
19205 static int first_file_directive
= 0;
19207 if (ECOFF_DEBUGGING
)
19216 filename
= dwarf2_directive_file (0);
19218 /* Versions of GCC up to 3.1 start files with a ".file"
19219 directive even for stabs output. Make sure that this
19220 ".file" is handled. Note that you need a version of GCC
19221 after 3.1 in order to support DWARF-2 on MIPS. */
19222 if (filename
!= NULL
&& ! first_file_directive
)
19224 (void) new_logical_line (filename
, -1);
19225 s_app_file_string (filename
, 0);
19227 first_file_directive
= 1;
19231 /* The .loc directive, implying DWARF-2. */
19234 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19236 if (!ECOFF_DEBUGGING
)
19237 dwarf2_directive_loc (0);
19240 /* The .end directive. */
19243 s_mips_end (int x ATTRIBUTE_UNUSED
)
19247 /* Following functions need their own .frame and .cprestore directives. */
19248 mips_frame_reg_valid
= 0;
19249 mips_cprestore_valid
= 0;
19251 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19254 demand_empty_rest_of_line ();
19259 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19260 as_warn (_(".end not in text section"));
19264 as_warn (_(".end directive without a preceding .ent directive"));
19265 demand_empty_rest_of_line ();
19271 gas_assert (S_GET_NAME (p
));
19272 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19273 as_warn (_(".end symbol does not match .ent symbol"));
19275 if (debug_type
== DEBUG_STABS
)
19276 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19280 as_warn (_(".end directive missing or unknown symbol"));
19282 /* Create an expression to calculate the size of the function. */
19283 if (p
&& cur_proc_ptr
)
19285 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19286 expressionS
*exp
= XNEW (expressionS
);
19289 exp
->X_op
= O_subtract
;
19290 exp
->X_add_symbol
= symbol_temp_new_now ();
19291 exp
->X_op_symbol
= p
;
19292 exp
->X_add_number
= 0;
19294 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19297 #ifdef md_flush_pending_output
19298 md_flush_pending_output ();
19301 /* Generate a .pdr section. */
19302 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19304 segT saved_seg
= now_seg
;
19305 subsegT saved_subseg
= now_subseg
;
19309 gas_assert (pdr_seg
);
19310 subseg_set (pdr_seg
, 0);
19312 /* Write the symbol. */
19313 exp
.X_op
= O_symbol
;
19314 exp
.X_add_symbol
= p
;
19315 exp
.X_add_number
= 0;
19316 emit_expr (&exp
, 4);
19318 fragp
= frag_more (7 * 4);
19320 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19321 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19322 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19323 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19324 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19325 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19326 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19328 subseg_set (saved_seg
, saved_subseg
);
19331 cur_proc_ptr
= NULL
;
19334 /* The .aent and .ent directives. */
19337 s_mips_ent (int aent
)
19341 symbolP
= get_symbol ();
19342 if (*input_line_pointer
== ',')
19343 ++input_line_pointer
;
19344 SKIP_WHITESPACE ();
19345 if (ISDIGIT (*input_line_pointer
)
19346 || *input_line_pointer
== '-')
19349 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19350 as_warn (_(".ent or .aent not in text section"));
19352 if (!aent
&& cur_proc_ptr
)
19353 as_warn (_("missing .end"));
19357 /* This function needs its own .frame and .cprestore directives. */
19358 mips_frame_reg_valid
= 0;
19359 mips_cprestore_valid
= 0;
19361 cur_proc_ptr
= &cur_proc
;
19362 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19364 cur_proc_ptr
->func_sym
= symbolP
;
19368 if (debug_type
== DEBUG_STABS
)
19369 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19370 S_GET_NAME (symbolP
));
19373 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19375 demand_empty_rest_of_line ();
19378 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19379 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19380 s_mips_frame is used so that we can set the PDR information correctly.
19381 We can't use the ecoff routines because they make reference to the ecoff
19382 symbol table (in the mdebug section). */
19385 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19387 if (ECOFF_DEBUGGING
)
19393 if (cur_proc_ptr
== (procS
*) NULL
)
19395 as_warn (_(".frame outside of .ent"));
19396 demand_empty_rest_of_line ();
19400 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19402 SKIP_WHITESPACE ();
19403 if (*input_line_pointer
++ != ','
19404 || get_absolute_expression_and_terminator (&val
) != ',')
19406 as_warn (_("bad .frame directive"));
19407 --input_line_pointer
;
19408 demand_empty_rest_of_line ();
19412 cur_proc_ptr
->frame_offset
= val
;
19413 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19415 demand_empty_rest_of_line ();
19419 /* The .fmask and .mask directives. If the mdebug section is present
19420 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19421 embedded targets, s_mips_mask is used so that we can set the PDR
19422 information correctly. We can't use the ecoff routines because they
19423 make reference to the ecoff symbol table (in the mdebug section). */
19426 s_mips_mask (int reg_type
)
19428 if (ECOFF_DEBUGGING
)
19429 s_ignore (reg_type
);
19434 if (cur_proc_ptr
== (procS
*) NULL
)
19436 as_warn (_(".mask/.fmask outside of .ent"));
19437 demand_empty_rest_of_line ();
19441 if (get_absolute_expression_and_terminator (&mask
) != ',')
19443 as_warn (_("bad .mask/.fmask directive"));
19444 --input_line_pointer
;
19445 demand_empty_rest_of_line ();
19449 off
= get_absolute_expression ();
19451 if (reg_type
== 'F')
19453 cur_proc_ptr
->fpreg_mask
= mask
;
19454 cur_proc_ptr
->fpreg_offset
= off
;
19458 cur_proc_ptr
->reg_mask
= mask
;
19459 cur_proc_ptr
->reg_offset
= off
;
19462 demand_empty_rest_of_line ();
19466 /* A table describing all the processors gas knows about. Names are
19467 matched in the order listed.
19469 To ease comparison, please keep this table in the same order as
19470 gcc's mips_cpu_info_table[]. */
19471 static const struct mips_cpu_info mips_cpu_info_table
[] =
19473 /* Entries for generic ISAs */
19474 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19475 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19476 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19477 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19478 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19479 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19480 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19481 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19482 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19483 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19484 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19485 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19486 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19487 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19488 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19491 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19492 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19493 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19496 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19499 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19500 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19501 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19502 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19503 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19504 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19505 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19506 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19507 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19508 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19509 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19510 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19511 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19512 /* ST Microelectronics Loongson 2E and 2F cores */
19513 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19514 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19517 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19518 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19519 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19520 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19521 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19522 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19523 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19524 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19525 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19526 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19527 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19528 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19529 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19530 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19531 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19534 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19535 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19536 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19537 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19539 /* MIPS 32 Release 2 */
19540 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19541 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19542 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19543 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19544 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19545 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19546 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19547 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19548 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19549 ISA_MIPS32R2
, CPU_MIPS32R2
},
19550 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19551 ISA_MIPS32R2
, CPU_MIPS32R2
},
19552 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19553 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19554 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19555 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19556 /* Deprecated forms of the above. */
19557 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19558 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19559 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19560 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19561 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19562 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19563 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19564 /* Deprecated forms of the above. */
19565 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19566 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19567 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19568 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19569 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19570 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19571 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19572 /* Deprecated forms of the above. */
19573 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19574 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19575 /* 34Kn is a 34kc without DSP. */
19576 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19577 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19578 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19579 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19580 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19581 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19582 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19583 /* Deprecated forms of the above. */
19584 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19585 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19586 /* 1004K cores are multiprocessor versions of the 34K. */
19587 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19588 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19589 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19590 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19591 /* interaptiv is the new name for 1004kf */
19592 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19594 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19595 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19596 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19597 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19600 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19601 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19602 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19603 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19605 /* Broadcom SB-1 CPU core */
19606 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19607 /* Broadcom SB-1A CPU core */
19608 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19610 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
19612 /* MIPS 64 Release 2 */
19614 /* Cavium Networks Octeon CPU core */
19615 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19616 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19617 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19618 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19621 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19624 XLP is mostly like XLR, with the prominent exception that it is
19625 MIPS64R2 rather than MIPS64. */
19626 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19628 /* MIPS 64 Release 6 */
19629 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19630 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19633 { NULL
, 0, 0, 0, 0 }
19637 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19638 with a final "000" replaced by "k". Ignore case.
19640 Note: this function is shared between GCC and GAS. */
19643 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19645 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19646 given
++, canonical
++;
19648 return ((*given
== 0 && *canonical
== 0)
19649 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19653 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19654 CPU name. We've traditionally allowed a lot of variation here.
19656 Note: this function is shared between GCC and GAS. */
19659 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19661 /* First see if the name matches exactly, or with a final "000"
19662 turned into "k". */
19663 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19666 /* If not, try comparing based on numerical designation alone.
19667 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19668 if (TOLOWER (*given
) == 'r')
19670 if (!ISDIGIT (*given
))
19673 /* Skip over some well-known prefixes in the canonical name,
19674 hoping to find a number there too. */
19675 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19677 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19679 else if (TOLOWER (canonical
[0]) == 'r')
19682 return mips_strict_matching_cpu_name_p (canonical
, given
);
19686 /* Parse an option that takes the name of a processor as its argument.
19687 OPTION is the name of the option and CPU_STRING is the argument.
19688 Return the corresponding processor enumeration if the CPU_STRING is
19689 recognized, otherwise report an error and return null.
19691 A similar function exists in GCC. */
19693 static const struct mips_cpu_info
*
19694 mips_parse_cpu (const char *option
, const char *cpu_string
)
19696 const struct mips_cpu_info
*p
;
19698 /* 'from-abi' selects the most compatible architecture for the given
19699 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19700 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19701 version. Look first at the -mgp options, if given, otherwise base
19702 the choice on MIPS_DEFAULT_64BIT.
19704 Treat NO_ABI like the EABIs. One reason to do this is that the
19705 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19706 architecture. This code picks MIPS I for 'mips' and MIPS III for
19707 'mips64', just as we did in the days before 'from-abi'. */
19708 if (strcasecmp (cpu_string
, "from-abi") == 0)
19710 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19711 return mips_cpu_info_from_isa (ISA_MIPS1
);
19713 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19714 return mips_cpu_info_from_isa (ISA_MIPS3
);
19716 if (file_mips_opts
.gp
>= 0)
19717 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19718 ? ISA_MIPS1
: ISA_MIPS3
);
19720 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19725 /* 'default' has traditionally been a no-op. Probably not very useful. */
19726 if (strcasecmp (cpu_string
, "default") == 0)
19729 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19730 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19733 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19737 /* Return the canonical processor information for ISA (a member of the
19738 ISA_MIPS* enumeration). */
19740 static const struct mips_cpu_info
*
19741 mips_cpu_info_from_isa (int isa
)
19745 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19746 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19747 && isa
== mips_cpu_info_table
[i
].isa
)
19748 return (&mips_cpu_info_table
[i
]);
19753 static const struct mips_cpu_info
*
19754 mips_cpu_info_from_arch (int arch
)
19758 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19759 if (arch
== mips_cpu_info_table
[i
].cpu
)
19760 return (&mips_cpu_info_table
[i
]);
19766 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19770 fprintf (stream
, "%24s", "");
19775 fprintf (stream
, ", ");
19779 if (*col_p
+ strlen (string
) > 72)
19781 fprintf (stream
, "\n%24s", "");
19785 fprintf (stream
, "%s", string
);
19786 *col_p
+= strlen (string
);
19792 md_show_usage (FILE *stream
)
19797 fprintf (stream
, _("\
19799 -EB generate big endian output\n\
19800 -EL generate little endian output\n\
19801 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19802 -G NUM allow referencing objects up to NUM bytes\n\
19803 implicitly with the gp register [default 8]\n"));
19804 fprintf (stream
, _("\
19805 -mips1 generate MIPS ISA I instructions\n\
19806 -mips2 generate MIPS ISA II instructions\n\
19807 -mips3 generate MIPS ISA III instructions\n\
19808 -mips4 generate MIPS ISA IV instructions\n\
19809 -mips5 generate MIPS ISA V instructions\n\
19810 -mips32 generate MIPS32 ISA instructions\n\
19811 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19812 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19813 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19814 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19815 -mips64 generate MIPS64 ISA instructions\n\
19816 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19817 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19818 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19819 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19820 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19824 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19825 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19826 show (stream
, "from-abi", &column
, &first
);
19827 fputc ('\n', stream
);
19829 fprintf (stream
, _("\
19830 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19831 -no-mCPU don't generate code specific to CPU.\n\
19832 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19836 show (stream
, "3900", &column
, &first
);
19837 show (stream
, "4010", &column
, &first
);
19838 show (stream
, "4100", &column
, &first
);
19839 show (stream
, "4650", &column
, &first
);
19840 fputc ('\n', stream
);
19842 fprintf (stream
, _("\
19843 -mips16 generate mips16 instructions\n\
19844 -no-mips16 do not generate mips16 instructions\n"));
19845 fprintf (stream
, _("\
19846 -mmicromips generate microMIPS instructions\n\
19847 -mno-micromips do not generate microMIPS instructions\n"));
19848 fprintf (stream
, _("\
19849 -msmartmips generate smartmips instructions\n\
19850 -mno-smartmips do not generate smartmips instructions\n"));
19851 fprintf (stream
, _("\
19852 -mdsp generate DSP instructions\n\
19853 -mno-dsp do not generate DSP instructions\n"));
19854 fprintf (stream
, _("\
19855 -mdspr2 generate DSP R2 instructions\n\
19856 -mno-dspr2 do not generate DSP R2 instructions\n"));
19857 fprintf (stream
, _("\
19858 -mdspr3 generate DSP R3 instructions\n\
19859 -mno-dspr3 do not generate DSP R3 instructions\n"));
19860 fprintf (stream
, _("\
19861 -mmt generate MT instructions\n\
19862 -mno-mt do not generate MT instructions\n"));
19863 fprintf (stream
, _("\
19864 -mmcu generate MCU instructions\n\
19865 -mno-mcu do not generate MCU instructions\n"));
19866 fprintf (stream
, _("\
19867 -mmsa generate MSA instructions\n\
19868 -mno-msa do not generate MSA instructions\n"));
19869 fprintf (stream
, _("\
19870 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19871 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19872 fprintf (stream
, _("\
19873 -mvirt generate Virtualization instructions\n\
19874 -mno-virt do not generate Virtualization instructions\n"));
19875 fprintf (stream
, _("\
19876 -minsn32 only generate 32-bit microMIPS instructions\n\
19877 -mno-insn32 generate all microMIPS instructions\n"));
19878 fprintf (stream
, _("\
19879 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19880 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19881 -mfix-vr4120 work around certain VR4120 errata\n\
19882 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19883 -mfix-24k insert a nop after ERET and DERET instructions\n\
19884 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19885 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19886 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19887 -msym32 assume all symbols have 32-bit values\n\
19888 -O0 remove unneeded NOPs, do not swap branches\n\
19889 -O remove unneeded NOPs and swap branches\n\
19890 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19891 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19892 fprintf (stream
, _("\
19893 -mhard-float allow floating-point instructions\n\
19894 -msoft-float do not allow floating-point instructions\n\
19895 -msingle-float only allow 32-bit floating-point operations\n\
19896 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19897 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19898 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19899 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
19900 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
19901 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19905 show (stream
, "legacy", &column
, &first
);
19906 show (stream
, "2008", &column
, &first
);
19908 fputc ('\n', stream
);
19910 fprintf (stream
, _("\
19911 -KPIC, -call_shared generate SVR4 position independent code\n\
19912 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19913 -mvxworks-pic generate VxWorks position independent code\n\
19914 -non_shared do not generate code that can operate with DSOs\n\
19915 -xgot assume a 32 bit GOT\n\
19916 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19917 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19918 position dependent (non shared) code\n\
19919 -mabi=ABI create ABI conformant object file for:\n"));
19923 show (stream
, "32", &column
, &first
);
19924 show (stream
, "o64", &column
, &first
);
19925 show (stream
, "n32", &column
, &first
);
19926 show (stream
, "64", &column
, &first
);
19927 show (stream
, "eabi", &column
, &first
);
19929 fputc ('\n', stream
);
19931 fprintf (stream
, _("\
19932 -32 create o32 ABI object file (default)\n\
19933 -n32 create n32 ABI object file\n\
19934 -64 create 64 ABI object file\n"));
19939 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19941 if (HAVE_64BIT_SYMBOLS
)
19942 return dwarf2_format_64bit_irix
;
19944 return dwarf2_format_32bit
;
19949 mips_dwarf2_addr_size (void)
19951 if (HAVE_64BIT_OBJECTS
)
19957 /* Standard calling conventions leave the CFA at SP on entry. */
19959 mips_cfi_frame_initial_instructions (void)
19961 cfi_add_CFA_def_cfa_register (SP
);
19965 tc_mips_regname_to_dw2regnum (char *regname
)
19967 unsigned int regnum
= -1;
19970 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
19976 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19977 Given a symbolic attribute NAME, return the proper integer value.
19978 Returns -1 if the attribute is not known. */
19981 mips_convert_symbolic_attribute (const char *name
)
19983 static const struct
19988 attribute_table
[] =
19990 #define T(tag) {#tag, tag}
19991 T (Tag_GNU_MIPS_ABI_FP
),
19992 T (Tag_GNU_MIPS_ABI_MSA
),
20000 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20001 if (streq (name
, attribute_table
[i
].name
))
20002 return attribute_table
[i
].tag
;
20010 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20012 mips_emit_delays ();
20014 as_warn (_("missing .end at end of assembly"));
20016 /* Just in case no code was emitted, do the consistency check. */
20017 file_mips_check_options ();
20019 /* Set a floating-point ABI if the user did not. */
20020 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20022 /* Perform consistency checks on the floating-point ABI. */
20023 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20024 Tag_GNU_MIPS_ABI_FP
);
20025 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20026 check_fpabi (fpabi
);
20030 /* Soft-float gets precedence over single-float, the two options should
20031 not be used together so this should not matter. */
20032 if (file_mips_opts
.soft_float
== 1)
20033 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20034 /* Single-float gets precedence over all double_float cases. */
20035 else if (file_mips_opts
.single_float
== 1)
20036 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20039 switch (file_mips_opts
.fp
)
20042 if (file_mips_opts
.gp
== 32)
20043 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20046 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20049 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20050 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20051 else if (file_mips_opts
.gp
== 32)
20052 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20054 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20059 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20060 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20064 /* Returns the relocation type required for a particular CFI encoding. */
20066 bfd_reloc_code_real_type
20067 mips_cfi_reloc_for_encoding (int encoding
)
20069 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20070 return BFD_RELOC_32_PCREL
;
20071 else return BFD_RELOC_NONE
;