1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF.
107 Note that the default is always 32 bit, even if "configured" for
108 64 bit [e.g. --target=mips64-elf]. */
111 /* The default target format to use. */
113 mips_target_format ()
115 switch (OUTPUT_FLAVOR
)
117 case bfd_target_aout_flavour
:
118 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
119 case bfd_target_ecoff_flavour
:
120 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
121 case bfd_target_elf_flavour
:
122 return (target_big_endian
123 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
124 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
131 /* The name of the readonly data section. */
132 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
134 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
136 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
140 /* This is the set of options which may be modified by the .set
141 pseudo-op. We use a struct so that .set push and .set pop are more
144 struct mips_set_options
146 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
147 if it has not been initialized. Changed by `.set mipsN', and the
148 -mipsN command line option, and the default CPU. */
150 /* Whether we are assembling for the mips16 processor. 0 if we are
151 not, 1 if we are, and -1 if the value has not been initialized.
152 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
153 -nomips16 command line options, and the default CPU. */
155 /* Non-zero if we should not reorder instructions. Changed by `.set
156 reorder' and `.set noreorder'. */
158 /* Non-zero if we should not permit the $at ($1) register to be used
159 in instructions. Changed by `.set at' and `.set noat'. */
161 /* Non-zero if we should warn when a macro instruction expands into
162 more than one machine instruction. Changed by `.set nomacro' and
164 int warn_about_macros
;
165 /* Non-zero if we should not move instructions. Changed by `.set
166 move', `.set volatile', `.set nomove', and `.set novolatile'. */
168 /* Non-zero if we should not optimize branches by moving the target
169 of the branch into the delay slot. Actually, we don't perform
170 this optimization anyhow. Changed by `.set bopt' and `.set
173 /* Non-zero if we should not autoextend mips16 instructions.
174 Changed by `.set autoextend' and `.set noautoextend'. */
178 /* This is the struct we use to hold the current set of options. Note
179 that we must set the isa and mips16 fields to -1 to indicate that
180 they have not been initialized. */
182 static struct mips_set_options mips_opts
= { -1, -1 };
184 /* These variables are filled in with the masks of registers used.
185 The object format code reads them and puts them in the appropriate
187 unsigned long mips_gprmask
;
188 unsigned long mips_cprmask
[4];
190 /* MIPS ISA we are using for this output file. */
191 static int file_mips_isa
;
193 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
194 static int mips_cpu
= -1;
196 /* The argument of the -mabi= flag. */
197 static char* mips_abi_string
= 0;
199 /* Wether we should mark the file EABI64 or EABI32. */
200 static int mips_eabi64
= 0;
202 /* If they asked for mips1 or mips2 and a cpu that is
203 mips3 or greater, then mark the object file 32BITMODE. */
204 static int mips_32bitmode
= 0;
206 /* Whether the processor uses hardware interlocks to protect
207 reads from the HI and LO registers, and thus does not
208 require nops to be inserted.
210 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
211 -mcpu=FOO schedules for FOO, but still produces code that meets the
212 requirements of MIPS ISA I. For example, it won't generate any
213 FOO-specific instructions, and it will still assume that any
214 scheduling hazards described in MIPS ISA I are there, even if FOO
215 has interlocks. -mFOO gives GCC permission to generate code that
216 will only run on a FOO; it will generate FOO-specific instructions,
217 and assume interlocks provided by a FOO.
219 However, GAS currently doesn't make this distinction; before Jan 28
220 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
221 assumptions. The GCC driver passes these flags through to GAS, so
222 if GAS actually does anything that doesn't meet MIPS ISA I with
223 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
225 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
226 which seems senseless --- why generate code which will only run on
227 a FOO, but schedule for something else?
229 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
231 -- Jim Blandy <jimb@cygnus.com> */
233 #define hilo_interlocks (mips_cpu == 4010 \
236 /* Whether the processor uses hardware interlocks to protect reads
237 from the GPRs, and thus does not require nops to be inserted. */
238 #define gpr_interlocks \
239 (mips_opts.isa >= 2 \
242 /* As with other "interlocks" this is used by hardware that has FP
243 (co-processor) interlocks. */
244 /* Itbl support may require additional care here. */
245 #define cop_interlocks (mips_cpu == 4300 \
248 /* MIPS PIC level. */
252 /* Do not generate PIC code. */
255 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
256 not sure what it is supposed to do. */
259 /* Generate PIC code as in the SVR4 MIPS ABI. */
262 /* Generate PIC code without using a global offset table: the data
263 segment has a maximum size of 64K, all data references are off
264 the $gp register, and all text references are PC relative. This
265 is used on some embedded systems. */
269 static enum mips_pic_level mips_pic
;
271 /* 1 if we should generate 32 bit offsets from the GP register in
272 SVR4_PIC mode. Currently has no meaning in other modes. */
273 static int mips_big_got
;
275 /* 1 if trap instructions should used for overflow rather than break
277 static int mips_trap
;
279 /* Non-zero if any .set noreorder directives were used. */
281 static int mips_any_noreorder
;
283 /* The size of the small data section. */
284 static int g_switch_value
= 8;
285 /* Whether the -G option was used. */
286 static int g_switch_seen
= 0;
291 /* If we can determine in advance that GP optimization won't be
292 possible, we can skip the relaxation stuff that tries to produce
293 GP-relative references. This makes delay slot optimization work
296 This function can only provide a guess, but it seems to work for
297 gcc output. If it guesses wrong, the only loss should be in
298 efficiency; it shouldn't introduce any bugs.
300 I don't know if a fix is needed for the SVR4_PIC mode. I've only
301 fixed it for the non-PIC mode. KR 95/04/07 */
302 static int nopic_need_relax
PARAMS ((symbolS
*, int));
304 /* handle of the OPCODE hash table */
305 static struct hash_control
*op_hash
= NULL
;
307 /* The opcode hash table we use for the mips16. */
308 static struct hash_control
*mips16_op_hash
= NULL
;
310 /* This array holds the chars that always start a comment. If the
311 pre-processor is disabled, these aren't very useful */
312 const char comment_chars
[] = "#";
314 /* This array holds the chars that only start a comment at the beginning of
315 a line. If the line seems to have the form '# 123 filename'
316 .line and .file directives will appear in the pre-processed output */
317 /* Note that input_file.c hand checks for '#' at the beginning of the
318 first line of the input file. This is because the compiler outputs
319 #NO_APP at the beginning of its output. */
320 /* Also note that C style comments are always supported. */
321 const char line_comment_chars
[] = "#";
323 /* This array holds machine specific line separator characters. */
324 const char line_separator_chars
[] = "";
326 /* Chars that can be used to separate mant from exp in floating point nums */
327 const char EXP_CHARS
[] = "eE";
329 /* Chars that mean this number is a floating point constant */
332 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
334 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
335 changed in read.c . Ideally it shouldn't have to know about it at all,
336 but nothing is ideal around here.
339 static char *insn_error
;
341 static int auto_align
= 1;
343 /* When outputting SVR4 PIC code, the assembler needs to know the
344 offset in the stack frame from which to restore the $gp register.
345 This is set by the .cprestore pseudo-op, and saved in this
347 static offsetT mips_cprestore_offset
= -1;
349 /* This is the register which holds the stack frame, as set by the
350 .frame pseudo-op. This is needed to implement .cprestore. */
351 static int mips_frame_reg
= SP
;
353 /* To output NOP instructions correctly, we need to keep information
354 about the previous two instructions. */
356 /* Whether we are optimizing. The default value of 2 means to remove
357 unneeded NOPs and swap branch instructions when possible. A value
358 of 1 means to not swap branches. A value of 0 means to always
360 static int mips_optimize
= 2;
362 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
363 equivalent to seeing no -g option at all. */
364 static int mips_debug
= 0;
366 /* The previous instruction. */
367 static struct mips_cl_insn prev_insn
;
369 /* The instruction before prev_insn. */
370 static struct mips_cl_insn prev_prev_insn
;
372 /* If we don't want information for prev_insn or prev_prev_insn, we
373 point the insn_mo field at this dummy integer. */
374 static const struct mips_opcode dummy_opcode
= { 0 };
376 /* Non-zero if prev_insn is valid. */
377 static int prev_insn_valid
;
379 /* The frag for the previous instruction. */
380 static struct frag
*prev_insn_frag
;
382 /* The offset into prev_insn_frag for the previous instruction. */
383 static long prev_insn_where
;
385 /* The reloc type for the previous instruction, if any. */
386 static bfd_reloc_code_real_type prev_insn_reloc_type
;
388 /* The reloc for the previous instruction, if any. */
389 static fixS
*prev_insn_fixp
;
391 /* Non-zero if the previous instruction was in a delay slot. */
392 static int prev_insn_is_delay_slot
;
394 /* Non-zero if the previous instruction was in a .set noreorder. */
395 static int prev_insn_unreordered
;
397 /* Non-zero if the previous instruction uses an extend opcode (if
399 static int prev_insn_extended
;
401 /* Non-zero if the previous previous instruction was in a .set
403 static int prev_prev_insn_unreordered
;
405 /* If this is set, it points to a frag holding nop instructions which
406 were inserted before the start of a noreorder section. If those
407 nops turn out to be unnecessary, the size of the frag can be
409 static fragS
*prev_nop_frag
;
411 /* The number of nop instructions we created in prev_nop_frag. */
412 static int prev_nop_frag_holds
;
414 /* The number of nop instructions that we know we need in
416 static int prev_nop_frag_required
;
418 /* The number of instructions we've seen since prev_nop_frag. */
419 static int prev_nop_frag_since
;
421 /* For ECOFF and ELF, relocations against symbols are done in two
422 parts, with a HI relocation and a LO relocation. Each relocation
423 has only 16 bits of space to store an addend. This means that in
424 order for the linker to handle carries correctly, it must be able
425 to locate both the HI and the LO relocation. This means that the
426 relocations must appear in order in the relocation table.
428 In order to implement this, we keep track of each unmatched HI
429 relocation. We then sort them so that they immediately precede the
430 corresponding LO relocation. */
435 struct mips_hi_fixup
*next
;
438 /* The section this fixup is in. */
442 /* The list of unmatched HI relocs. */
444 static struct mips_hi_fixup
*mips_hi_fixup_list
;
446 /* Map normal MIPS register numbers to mips16 register numbers. */
448 #define X ILLEGAL_REG
449 static const int mips32_to_16_reg_map
[] =
451 X
, X
, 2, 3, 4, 5, 6, 7,
452 X
, X
, X
, X
, X
, X
, X
, X
,
453 0, 1, X
, X
, X
, X
, X
, X
,
454 X
, X
, X
, X
, X
, X
, X
, X
458 /* Map mips16 register numbers to normal MIPS register numbers. */
460 static const int mips16_to_32_reg_map
[] =
462 16, 17, 2, 3, 4, 5, 6, 7
465 /* Since the MIPS does not have multiple forms of PC relative
466 instructions, we do not have to do relaxing as is done on other
467 platforms. However, we do have to handle GP relative addressing
468 correctly, which turns out to be a similar problem.
470 Every macro that refers to a symbol can occur in (at least) two
471 forms, one with GP relative addressing and one without. For
472 example, loading a global variable into a register generally uses
473 a macro instruction like this:
475 If i can be addressed off the GP register (this is true if it is in
476 the .sbss or .sdata section, or if it is known to be smaller than
477 the -G argument) this will generate the following instruction:
479 This instruction will use a GPREL reloc. If i can not be addressed
480 off the GP register, the following instruction sequence will be used:
483 In this case the first instruction will have a HI16 reloc, and the
484 second reloc will have a LO16 reloc. Both relocs will be against
487 The issue here is that we may not know whether i is GP addressable
488 until after we see the instruction that uses it. Therefore, we
489 want to be able to choose the final instruction sequence only at
490 the end of the assembly. This is similar to the way other
491 platforms choose the size of a PC relative instruction only at the
494 When generating position independent code we do not use GP
495 addressing in quite the same way, but the issue still arises as
496 external symbols and local symbols must be handled differently.
498 We handle these issues by actually generating both possible
499 instruction sequences. The longer one is put in a frag_var with
500 type rs_machine_dependent. We encode what to do with the frag in
501 the subtype field. We encode (1) the number of existing bytes to
502 replace, (2) the number of new bytes to use, (3) the offset from
503 the start of the existing bytes to the first reloc we must generate
504 (that is, the offset is applied from the start of the existing
505 bytes after they are replaced by the new bytes, if any), (4) the
506 offset from the start of the existing bytes to the second reloc,
507 (5) whether a third reloc is needed (the third reloc is always four
508 bytes after the second reloc), and (6) whether to warn if this
509 variant is used (this is sometimes needed if .set nomacro or .set
510 noat is in effect). All these numbers are reasonably small.
512 Generating two instruction sequences must be handled carefully to
513 ensure that delay slots are handled correctly. Fortunately, there
514 are a limited number of cases. When the second instruction
515 sequence is generated, append_insn is directed to maintain the
516 existing delay slot information, so it continues to apply to any
517 code after the second instruction sequence. This means that the
518 second instruction sequence must not impose any requirements not
519 required by the first instruction sequence.
521 These variant frags are then handled in functions called by the
522 machine independent code. md_estimate_size_before_relax returns
523 the final size of the frag. md_convert_frag sets up the final form
524 of the frag. tc_gen_reloc adjust the first reloc and adds a second
526 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
530 | (((reloc1) + 64) << 9) \
531 | (((reloc2) + 64) << 2) \
532 | ((reloc3) ? (1 << 1) : 0) \
534 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
535 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
536 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
537 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
538 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
539 #define RELAX_WARN(i) ((i) & 1)
541 /* For mips16 code, we use an entirely different form of relaxation.
542 mips16 supports two versions of most instructions which take
543 immediate values: a small one which takes some small value, and a
544 larger one which takes a 16 bit value. Since branches also follow
545 this pattern, relaxing these values is required.
547 We can assemble both mips16 and normal MIPS code in a single
548 object. Therefore, we need to support this type of relaxation at
549 the same time that we support the relaxation described above. We
550 use the high bit of the subtype field to distinguish these cases.
552 The information we store for this type of relaxation is the
553 argument code found in the opcode file for this relocation, whether
554 the user explicitly requested a small or extended form, and whether
555 the relocation is in a jump or jal delay slot. That tells us the
556 size of the value, and how it should be stored. We also store
557 whether the fragment is considered to be extended or not. We also
558 store whether this is known to be a branch to a different section,
559 whether we have tried to relax this frag yet, and whether we have
560 ever extended a PC relative fragment because of a shift count. */
561 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
564 | ((small) ? 0x100 : 0) \
565 | ((ext) ? 0x200 : 0) \
566 | ((dslot) ? 0x400 : 0) \
567 | ((jal_dslot) ? 0x800 : 0))
568 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
569 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
570 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
571 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
572 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
573 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
574 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
575 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
576 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
577 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
578 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
579 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
581 /* Prototypes for static functions. */
584 #define internalError() \
585 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
587 #define internalError() as_fatal (_("MIPS internal Error"));
590 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
592 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
593 unsigned int reg
, enum mips_regclass
class));
594 static int reg_needs_delay
PARAMS ((int));
595 static void mips16_mark_labels
PARAMS ((void));
596 static void append_insn
PARAMS ((char *place
,
597 struct mips_cl_insn
* ip
,
599 bfd_reloc_code_real_type r
,
601 static void mips_no_prev_insn
PARAMS ((int));
602 static void mips_emit_delays
PARAMS ((boolean
));
604 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
605 const char *name
, const char *fmt
,
608 static void macro_build ();
610 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
611 const char *, const char *,
613 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
614 expressionS
* ep
, int regnum
));
615 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
616 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
618 static void load_register
PARAMS ((int *, int, expressionS
*, int));
619 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
620 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
621 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
622 #ifdef LOSING_COMPILER
623 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
625 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
626 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
627 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
628 boolean
, boolean
, unsigned long *,
629 boolean
*, unsigned short *));
630 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
631 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
632 static symbolS
*get_symbol
PARAMS ((void));
633 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
634 static void s_align
PARAMS ((int));
635 static void s_change_sec
PARAMS ((int));
636 static void s_cons
PARAMS ((int));
637 static void s_float_cons
PARAMS ((int));
638 static void s_mips_globl
PARAMS ((int));
639 static void s_option
PARAMS ((int));
640 static void s_mipsset
PARAMS ((int));
641 static void s_abicalls
PARAMS ((int));
642 static void s_cpload
PARAMS ((int));
643 static void s_cprestore
PARAMS ((int));
644 static void s_gpword
PARAMS ((int));
645 static void s_cpadd
PARAMS ((int));
646 static void s_insn
PARAMS ((int));
647 static void md_obj_begin
PARAMS ((void));
648 static void md_obj_end
PARAMS ((void));
649 static long get_number
PARAMS ((void));
650 static void s_mips_ent
PARAMS ((int));
651 static void s_mips_end
PARAMS ((int));
652 static void s_mips_frame
PARAMS ((int));
653 static void s_mips_mask
PARAMS ((int));
654 static void s_mips_stab
PARAMS ((int));
655 static void s_mips_weakext
PARAMS ((int));
656 static void s_file
PARAMS ((int));
657 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
660 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
664 The following pseudo-ops from the Kane and Heinrich MIPS book
665 should be defined here, but are currently unsupported: .alias,
666 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
668 The following pseudo-ops from the Kane and Heinrich MIPS book are
669 specific to the type of debugging information being generated, and
670 should be defined by the object format: .aent, .begin, .bend,
671 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
674 The following pseudo-ops from the Kane and Heinrich MIPS book are
675 not MIPS CPU specific, but are also not specific to the object file
676 format. This file is probably the best place to define them, but
677 they are not currently supported: .asm0, .endr, .lab, .repeat,
680 static const pseudo_typeS mips_pseudo_table
[] =
682 /* MIPS specific pseudo-ops. */
683 {"option", s_option
, 0},
684 {"set", s_mipsset
, 0},
685 {"rdata", s_change_sec
, 'r'},
686 {"sdata", s_change_sec
, 's'},
687 {"livereg", s_ignore
, 0},
688 {"abicalls", s_abicalls
, 0},
689 {"cpload", s_cpload
, 0},
690 {"cprestore", s_cprestore
, 0},
691 {"gpword", s_gpword
, 0},
692 {"cpadd", s_cpadd
, 0},
695 /* Relatively generic pseudo-ops that happen to be used on MIPS
697 {"asciiz", stringer
, 1},
698 {"bss", s_change_sec
, 'b'},
701 {"dword", s_cons
, 3},
702 {"weakext", s_mips_weakext
, 0},
704 /* These pseudo-ops are defined in read.c, but must be overridden
705 here for one reason or another. */
706 {"align", s_align
, 0},
708 {"data", s_change_sec
, 'd'},
709 {"double", s_float_cons
, 'd'},
710 {"float", s_float_cons
, 'f'},
711 {"globl", s_mips_globl
, 0},
712 {"global", s_mips_globl
, 0},
713 {"hword", s_cons
, 1},
718 {"short", s_cons
, 1},
719 {"single", s_float_cons
, 'f'},
720 {"stabn", s_mips_stab
, 'n'},
721 {"text", s_change_sec
, 't'},
726 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
727 /* These pseudo-ops should be defined by the object file format.
728 However, a.out doesn't support them, so we have versions here. */
729 {"aent", s_mips_ent
, 1},
730 {"bgnb", s_ignore
, 0},
731 {"end", s_mips_end
, 0},
732 {"endb", s_ignore
, 0},
733 {"ent", s_mips_ent
, 0},
735 {"fmask", s_mips_mask
, 'F'},
736 {"frame", s_mips_frame
, 0},
737 {"loc", s_ignore
, 0},
738 {"mask", s_mips_mask
, 'R'},
739 {"verstamp", s_ignore
, 0},
743 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
748 pop_insert (mips_pseudo_table
);
749 if (! ECOFF_DEBUGGING
)
750 pop_insert (mips_nonecoff_pseudo_table
);
753 /* Symbols labelling the current insn. */
755 struct insn_label_list
757 struct insn_label_list
*next
;
761 static struct insn_label_list
*insn_labels
;
762 static struct insn_label_list
*free_insn_labels
;
764 static void mips_clear_insn_labels
PARAMS ((void));
767 mips_clear_insn_labels ()
769 register struct insn_label_list
**pl
;
771 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
777 static char *expr_end
;
779 /* Expressions which appear in instructions. These are set by
782 static expressionS imm_expr
;
783 static expressionS offset_expr
;
785 /* Relocs associated with imm_expr and offset_expr. */
787 static bfd_reloc_code_real_type imm_reloc
;
788 static bfd_reloc_code_real_type offset_reloc
;
790 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
792 static boolean imm_unmatched_hi
;
794 /* These are set by mips16_ip if an explicit extension is used. */
796 static boolean mips16_small
, mips16_ext
;
798 #ifdef MIPS_STABS_ELF
799 /* The pdr segment for per procedure frame/regmask info */
805 * This function is called once, at assembler startup time. It should
806 * set up all the tables, etc. that the MD part of the assembler will need.
812 register const char *retval
= NULL
;
813 register unsigned int i
= 0;
817 int mips_isa_from_cpu
;
820 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
822 a
= xmalloc (sizeof TARGET_CPU
);
823 strcpy (a
, TARGET_CPU
);
824 a
[(sizeof TARGET_CPU
) - 3] = '\0';
830 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
831 just the generic 'mips', in which case set mips_cpu based
832 on the given ISA, if any. */
834 if (strcmp (cpu
, "mips") == 0)
836 if (mips_opts
.isa
< 0)
839 else if (mips_opts
.isa
== 2)
842 else if (mips_opts
.isa
== 3)
845 else if (mips_opts
.isa
== 4)
852 else if (strcmp (cpu
, "r3900") == 0
853 || strcmp (cpu
, "mipstx39") == 0
857 else if (strcmp (cpu
, "r6000") == 0
858 || strcmp (cpu
, "mips2") == 0)
861 else if (strcmp (cpu
, "mips64") == 0
862 || strcmp (cpu
, "r4000") == 0
863 || strcmp (cpu
, "mips3") == 0)
866 else if (strcmp (cpu
, "r4400") == 0)
869 else if (strcmp (cpu
, "mips64orion") == 0
870 || strcmp (cpu
, "r4600") == 0)
873 else if (strcmp (cpu
, "r4650") == 0)
876 else if (strcmp (cpu
, "mips64vr4300") == 0)
879 else if (strcmp (cpu
, "mips64vr4111") == 0)
882 else if (strcmp (cpu
, "mips64vr4100") == 0)
885 else if (strcmp (cpu
, "r4010") == 0)
889 else if (strcmp (cpu
, "r5000") == 0
890 || strcmp (cpu
, "mips64vr5000") == 0)
895 else if (strcmp (cpu
, "r8000") == 0
896 || strcmp (cpu
, "mips4") == 0)
899 else if (strcmp (cpu
, "r10000") == 0)
902 else if (strcmp (cpu
, "mips16") == 0)
903 mips_cpu
= 0; /* FIXME */
911 mips_isa_from_cpu
= 1;
913 else if (mips_cpu
== 6000
915 mips_isa_from_cpu
= 2;
917 else if (mips_cpu
== 4000
924 mips_isa_from_cpu
= 3;
926 else if (mips_cpu
== 5000
928 || mips_cpu
== 10000)
929 mips_isa_from_cpu
= 4;
932 mips_isa_from_cpu
= -1;
934 if (mips_opts
.isa
== -1)
936 if (mips_isa_from_cpu
!= -1)
937 mips_opts
.isa
= mips_isa_from_cpu
;
942 if (mips_opts
.mips16
< 0)
944 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
945 mips_opts
.mips16
= 1;
947 mips_opts
.mips16
= 0;
950 /* End of TARGET_CPU processing, get rid of malloced memory
959 if (mips_opts
.isa
< 2 && mips_trap
)
960 as_bad (_("trap exception not supported at ISA 1"));
962 /* Set the EABI kind based on the ISA before the user gets
963 to change the ISA with directives. This isn't really
964 the best, but then neither is basing the abi on the isa. */
965 if (mips_opts
.isa
> 2
967 && 0 == strcmp (mips_abi_string
,"eabi"))
970 if (mips_cpu
!= 0 && mips_cpu
!= -1)
972 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
974 /* If they asked for mips1 or mips2 and a cpu that is
975 mips3 or greater, then mark the object file 32BITMODE. */
976 if (mips_isa_from_cpu
!= -1
977 && mips_opts
.isa
<= 2 && mips_isa_from_cpu
> 2)
982 switch (mips_opts
.isa
)
985 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
988 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
991 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
994 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1000 as_warn (_("Could not set architecture and machine"));
1002 file_mips_isa
= mips_opts
.isa
;
1004 op_hash
= hash_new ();
1006 for (i
= 0; i
< NUMOPCODES
;)
1008 const char *name
= mips_opcodes
[i
].name
;
1010 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1013 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1014 mips_opcodes
[i
].name
, retval
);
1015 /* Probably a memory allocation problem? Give up now. */
1016 as_fatal (_("Broken assembler. No assembly attempted."));
1020 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1022 if (!validate_mips_insn (&mips_opcodes
[i
]))
1027 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1030 mips16_op_hash
= hash_new ();
1033 while (i
< bfd_mips16_num_opcodes
)
1035 const char *name
= mips16_opcodes
[i
].name
;
1037 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1039 as_fatal (_("internal: can't hash `%s': %s"),
1040 mips16_opcodes
[i
].name
, retval
);
1043 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1044 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1045 != mips16_opcodes
[i
].match
))
1047 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1048 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1053 while (i
< bfd_mips16_num_opcodes
1054 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1058 as_fatal (_("Broken assembler. No assembly attempted."));
1060 /* We add all the general register names to the symbol table. This
1061 helps us detect invalid uses of them. */
1062 for (i
= 0; i
< 32; i
++)
1066 sprintf (buf
, "$%d", i
);
1067 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1068 &zero_address_frag
));
1070 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1071 &zero_address_frag
));
1072 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1073 &zero_address_frag
));
1074 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1075 &zero_address_frag
));
1076 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1077 &zero_address_frag
));
1078 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1079 &zero_address_frag
));
1080 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1081 &zero_address_frag
));
1082 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1083 &zero_address_frag
));
1085 mips_no_prev_insn (false);
1088 mips_cprmask
[0] = 0;
1089 mips_cprmask
[1] = 0;
1090 mips_cprmask
[2] = 0;
1091 mips_cprmask
[3] = 0;
1093 /* set the default alignment for the text section (2**2) */
1094 record_alignment (text_section
, 2);
1096 if (USE_GLOBAL_POINTER_OPT
)
1097 bfd_set_gp_size (stdoutput
, g_switch_value
);
1099 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1101 /* On a native system, sections must be aligned to 16 byte
1102 boundaries. When configured for an embedded ELF target, we
1104 if (strcmp (TARGET_OS
, "elf") != 0)
1106 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1107 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1108 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1111 /* Create a .reginfo section for register masks and a .mdebug
1112 section for debugging information. */
1120 subseg
= now_subseg
;
1122 /* The ABI says this section should be loaded so that the
1123 running program can access it. However, we don't load it
1124 if we are configured for an embedded target */
1125 flags
= SEC_READONLY
| SEC_DATA
;
1126 if (strcmp (TARGET_OS
, "elf") != 0)
1127 flags
|= SEC_ALLOC
| SEC_LOAD
;
1131 sec
= subseg_new (".reginfo", (subsegT
) 0);
1134 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1135 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1138 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1143 /* The 64-bit ABI uses a .MIPS.options section rather than
1144 .reginfo section. */
1145 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1146 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1147 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1150 /* Set up the option header. */
1152 Elf_Internal_Options opthdr
;
1155 opthdr
.kind
= ODK_REGINFO
;
1156 opthdr
.size
= (sizeof (Elf_External_Options
)
1157 + sizeof (Elf64_External_RegInfo
));
1160 f
= frag_more (sizeof (Elf_External_Options
));
1161 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1162 (Elf_External_Options
*) f
);
1164 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1169 if (ECOFF_DEBUGGING
)
1171 sec
= subseg_new (".mdebug", (subsegT
) 0);
1172 (void) bfd_set_section_flags (stdoutput
, sec
,
1173 SEC_HAS_CONTENTS
| SEC_READONLY
);
1174 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1177 #ifdef MIPS_STABS_ELF
1178 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1179 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1180 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1181 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1184 subseg_set (seg
, subseg
);
1188 if (! ECOFF_DEBUGGING
)
1195 if (! ECOFF_DEBUGGING
)
1203 struct mips_cl_insn insn
;
1205 imm_expr
.X_op
= O_absent
;
1206 imm_reloc
= BFD_RELOC_UNUSED
;
1207 imm_unmatched_hi
= false;
1208 offset_expr
.X_op
= O_absent
;
1209 offset_reloc
= BFD_RELOC_UNUSED
;
1211 if (mips_opts
.mips16
)
1212 mips16_ip (str
, &insn
);
1215 mips_ip (str
, &insn
);
1216 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1217 str
, insn
.insn_opcode
));
1222 as_bad ("%s `%s'", insn_error
, str
);
1226 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1228 if (mips_opts
.mips16
)
1229 mips16_macro (&insn
);
1235 if (imm_expr
.X_op
!= O_absent
)
1236 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1238 else if (offset_expr
.X_op
!= O_absent
)
1239 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1241 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1245 /* See whether instruction IP reads register REG. CLASS is the type
1249 insn_uses_reg (ip
, reg
, class)
1250 struct mips_cl_insn
*ip
;
1252 enum mips_regclass
class;
1254 if (class == MIPS16_REG
)
1256 assert (mips_opts
.mips16
);
1257 reg
= mips16_to_32_reg_map
[reg
];
1258 class = MIPS_GR_REG
;
1261 /* Don't report on general register 0, since it never changes. */
1262 if (class == MIPS_GR_REG
&& reg
== 0)
1265 if (class == MIPS_FP_REG
)
1267 assert (! mips_opts
.mips16
);
1268 /* If we are called with either $f0 or $f1, we must check $f0.
1269 This is not optimal, because it will introduce an unnecessary
1270 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1271 need to distinguish reading both $f0 and $f1 or just one of
1272 them. Note that we don't have to check the other way,
1273 because there is no instruction that sets both $f0 and $f1
1274 and requires a delay. */
1275 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1276 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1277 == (reg
&~ (unsigned) 1)))
1279 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1280 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1281 == (reg
&~ (unsigned) 1)))
1284 else if (! mips_opts
.mips16
)
1286 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1287 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1289 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1290 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1295 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1296 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1297 & MIPS16OP_MASK_RX
)]
1300 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1301 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1302 & MIPS16OP_MASK_RY
)]
1305 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1306 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1307 & MIPS16OP_MASK_MOVE32Z
)]
1310 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1312 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1314 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1316 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1317 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1318 & MIPS16OP_MASK_REGR32
) == reg
)
1325 /* This function returns true if modifying a register requires a
1329 reg_needs_delay (reg
)
1332 unsigned long prev_pinfo
;
1334 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1335 if (! mips_opts
.noreorder
1336 && mips_opts
.isa
< 4
1337 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1338 || (! gpr_interlocks
1339 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1341 /* A load from a coprocessor or from memory. All load
1342 delays delay the use of general register rt for one
1343 instruction on the r3000. The r6000 and r4000 use
1345 /* Itbl support may require additional care here. */
1346 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1347 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1354 /* Mark instruction labels in mips16 mode. This permits the linker to
1355 handle them specially, such as generating jalx instructions when
1356 needed. We also make them odd for the duration of the assembly, in
1357 order to generate the right sort of code. We will make them even
1358 in the adjust_symtab routine, while leaving them marked. This is
1359 convenient for the debugger and the disassembler. The linker knows
1360 to make them odd again. */
1363 mips16_mark_labels ()
1365 if (mips_opts
.mips16
)
1367 struct insn_label_list
*l
;
1369 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1372 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1373 S_SET_OTHER (l
->label
, STO_MIPS16
);
1375 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1376 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1381 /* Output an instruction. PLACE is where to put the instruction; if
1382 it is NULL, this uses frag_more to get room. IP is the instruction
1383 information. ADDRESS_EXPR is an operand of the instruction to be
1384 used with RELOC_TYPE. */
1387 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1389 struct mips_cl_insn
*ip
;
1390 expressionS
*address_expr
;
1391 bfd_reloc_code_real_type reloc_type
;
1392 boolean unmatched_hi
;
1394 register unsigned long prev_pinfo
, pinfo
;
1399 /* Mark instruction labels in mips16 mode. */
1400 if (mips_opts
.mips16
)
1401 mips16_mark_labels ();
1403 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1404 pinfo
= ip
->insn_mo
->pinfo
;
1406 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1410 /* If the previous insn required any delay slots, see if we need
1411 to insert a NOP or two. There are eight kinds of possible
1412 hazards, of which an instruction can have at most one type.
1413 (1) a load from memory delay
1414 (2) a load from a coprocessor delay
1415 (3) an unconditional branch delay
1416 (4) a conditional branch delay
1417 (5) a move to coprocessor register delay
1418 (6) a load coprocessor register from memory delay
1419 (7) a coprocessor condition code delay
1420 (8) a HI/LO special register delay
1422 There are a lot of optimizations we could do that we don't.
1423 In particular, we do not, in general, reorder instructions.
1424 If you use gcc with optimization, it will reorder
1425 instructions and generally do much more optimization then we
1426 do here; repeating all that work in the assembler would only
1427 benefit hand written assembly code, and does not seem worth
1430 /* This is how a NOP is emitted. */
1431 #define emit_nop() \
1433 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1434 : md_number_to_chars (frag_more (4), 0, 4))
1436 /* The previous insn might require a delay slot, depending upon
1437 the contents of the current insn. */
1438 if (! mips_opts
.mips16
1439 && mips_opts
.isa
< 4
1440 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1441 && ! cop_interlocks
)
1442 || (! gpr_interlocks
1443 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1445 /* A load from a coprocessor or from memory. All load
1446 delays delay the use of general register rt for one
1447 instruction on the r3000. The r6000 and r4000 use
1449 /* Itbl support may require additional care here. */
1450 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1451 if (mips_optimize
== 0
1452 || insn_uses_reg (ip
,
1453 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1458 else if (! mips_opts
.mips16
1459 && mips_opts
.isa
< 4
1460 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1461 && ! cop_interlocks
)
1462 || (mips_opts
.isa
< 2
1463 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1465 /* A generic coprocessor delay. The previous instruction
1466 modified a coprocessor general or control register. If
1467 it modified a control register, we need to avoid any
1468 coprocessor instruction (this is probably not always
1469 required, but it sometimes is). If it modified a general
1470 register, we avoid using that register.
1472 On the r6000 and r4000 loading a coprocessor register
1473 from memory is interlocked, and does not require a delay.
1475 This case is not handled very well. There is no special
1476 knowledge of CP0 handling, and the coprocessors other
1477 than the floating point unit are not distinguished at
1479 /* Itbl support may require additional care here. FIXME!
1480 Need to modify this to include knowledge about
1481 user specified delays! */
1482 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1484 if (mips_optimize
== 0
1485 || insn_uses_reg (ip
,
1486 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1491 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1493 if (mips_optimize
== 0
1494 || insn_uses_reg (ip
,
1495 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1502 /* We don't know exactly what the previous instruction
1503 does. If the current instruction uses a coprocessor
1504 register, we must insert a NOP. If previous
1505 instruction may set the condition codes, and the
1506 current instruction uses them, we must insert two
1508 /* Itbl support may require additional care here. */
1509 if (mips_optimize
== 0
1510 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1511 && (pinfo
& INSN_READ_COND_CODE
)))
1513 else if (pinfo
& INSN_COP
)
1517 else if (! mips_opts
.mips16
1518 && mips_opts
.isa
< 4
1519 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1520 && ! cop_interlocks
)
1522 /* The previous instruction sets the coprocessor condition
1523 codes, but does not require a general coprocessor delay
1524 (this means it is a floating point comparison
1525 instruction). If this instruction uses the condition
1526 codes, we need to insert a single NOP. */
1527 /* Itbl support may require additional care here. */
1528 if (mips_optimize
== 0
1529 || (pinfo
& INSN_READ_COND_CODE
))
1532 else if (prev_pinfo
& INSN_READ_LO
)
1534 /* The previous instruction reads the LO register; if the
1535 current instruction writes to the LO register, we must
1536 insert two NOPS. Some newer processors have interlocks.
1537 Also the tx39's multiply instructions can be exectuted
1538 immediatly after a read from HI/LO (without the delay),
1539 though the tx39's divide insns still do require the
1541 if (! (hilo_interlocks
1542 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1543 && (mips_optimize
== 0
1544 || (pinfo
& INSN_WRITE_LO
)))
1546 /* Most mips16 branch insns don't have a delay slot.
1547 If a read from LO is immediately followed by a branch
1548 to a write to LO we have a read followed by a write
1549 less than 2 insns away. We assume the target of
1550 a branch might be a write to LO, and insert a nop
1551 between a read and an immediately following branch. */
1552 else if (mips_opts
.mips16
1553 && (mips_optimize
== 0
1554 || (pinfo
& MIPS16_INSN_BRANCH
)))
1557 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1559 /* The previous instruction reads the HI register; if the
1560 current instruction writes to the HI register, we must
1561 insert a NOP. Some newer processors have interlocks.
1562 Also the note tx39's multiply above. */
1563 if (! (hilo_interlocks
1564 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1565 && (mips_optimize
== 0
1566 || (pinfo
& INSN_WRITE_HI
)))
1568 /* Most mips16 branch insns don't have a delay slot.
1569 If a read from HI is immediately followed by a branch
1570 to a write to HI we have a read followed by a write
1571 less than 2 insns away. We assume the target of
1572 a branch might be a write to HI, and insert a nop
1573 between a read and an immediately following branch. */
1574 else if (mips_opts
.mips16
1575 && (mips_optimize
== 0
1576 || (pinfo
& MIPS16_INSN_BRANCH
)))
1580 /* If the previous instruction was in a noreorder section, then
1581 we don't want to insert the nop after all. */
1582 /* Itbl support may require additional care here. */
1583 if (prev_insn_unreordered
)
1586 /* There are two cases which require two intervening
1587 instructions: 1) setting the condition codes using a move to
1588 coprocessor instruction which requires a general coprocessor
1589 delay and then reading the condition codes 2) reading the HI
1590 or LO register and then writing to it (except on processors
1591 which have interlocks). If we are not already emitting a NOP
1592 instruction, we must check for these cases compared to the
1593 instruction previous to the previous instruction. */
1594 if ((! mips_opts
.mips16
1595 && mips_opts
.isa
< 4
1596 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1597 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1598 && (pinfo
& INSN_READ_COND_CODE
)
1599 && ! cop_interlocks
)
1600 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1601 && (pinfo
& INSN_WRITE_LO
)
1602 && ! (hilo_interlocks
1603 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
))))
1604 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1605 && (pinfo
& INSN_WRITE_HI
)
1606 && ! (hilo_interlocks
1607 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))))
1612 if (prev_prev_insn_unreordered
)
1615 if (prev_prev_nop
&& nops
== 0)
1618 /* If we are being given a nop instruction, don't bother with
1619 one of the nops we would otherwise output. This will only
1620 happen when a nop instruction is used with mips_optimize set
1623 && ! mips_opts
.noreorder
1624 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1627 /* Now emit the right number of NOP instructions. */
1628 if (nops
> 0 && ! mips_opts
.noreorder
)
1631 unsigned long old_frag_offset
;
1633 struct insn_label_list
*l
;
1635 old_frag
= frag_now
;
1636 old_frag_offset
= frag_now_fix ();
1638 for (i
= 0; i
< nops
; i
++)
1643 listing_prev_line ();
1644 /* We may be at the start of a variant frag. In case we
1645 are, make sure there is enough space for the frag
1646 after the frags created by listing_prev_line. The
1647 argument to frag_grow here must be at least as large
1648 as the argument to all other calls to frag_grow in
1649 this file. We don't have to worry about being in the
1650 middle of a variant frag, because the variants insert
1651 all needed nop instructions themselves. */
1655 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1657 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1658 symbol_set_frag (l
->label
, frag_now
);
1659 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1660 /* mips16 text labels are stored as odd. */
1661 if (mips_opts
.mips16
)
1662 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1665 #ifndef NO_ECOFF_DEBUGGING
1666 if (ECOFF_DEBUGGING
)
1667 ecoff_fix_loc (old_frag
, old_frag_offset
);
1670 else if (prev_nop_frag
!= NULL
)
1672 /* We have a frag holding nops we may be able to remove. If
1673 we don't need any nops, we can decrease the size of
1674 prev_nop_frag by the size of one instruction. If we do
1675 need some nops, we count them in prev_nops_required. */
1676 if (prev_nop_frag_since
== 0)
1680 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1681 --prev_nop_frag_holds
;
1684 prev_nop_frag_required
+= nops
;
1688 if (prev_prev_nop
== 0)
1690 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1691 --prev_nop_frag_holds
;
1694 ++prev_nop_frag_required
;
1697 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1698 prev_nop_frag
= NULL
;
1700 ++prev_nop_frag_since
;
1702 /* Sanity check: by the time we reach the second instruction
1703 after prev_nop_frag, we should have used up all the nops
1704 one way or another. */
1705 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1709 if (reloc_type
> BFD_RELOC_UNUSED
)
1711 /* We need to set up a variant frag. */
1712 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1713 f
= frag_var (rs_machine_dependent
, 4, 0,
1714 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1715 mips16_small
, mips16_ext
,
1717 & INSN_UNCOND_BRANCH_DELAY
),
1718 (prev_insn_reloc_type
1719 == BFD_RELOC_MIPS16_JMP
)),
1720 make_expr_symbol (address_expr
), (offsetT
) 0,
1723 else if (place
!= NULL
)
1725 else if (mips_opts
.mips16
1727 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1729 /* Make sure there is enough room to swap this instruction with
1730 a following jump instruction. */
1736 if (mips_opts
.mips16
1737 && mips_opts
.noreorder
1738 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1739 as_warn (_("extended instruction in delay slot"));
1745 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1747 if (address_expr
->X_op
== O_constant
)
1752 ip
->insn_opcode
|= address_expr
->X_add_number
;
1755 case BFD_RELOC_LO16
:
1756 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1759 case BFD_RELOC_MIPS_JMP
:
1760 if ((address_expr
->X_add_number
& 3) != 0)
1761 as_bad (_("jump to misaligned address (0x%lx)"),
1762 (unsigned long) address_expr
->X_add_number
);
1763 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1766 case BFD_RELOC_MIPS16_JMP
:
1767 if ((address_expr
->X_add_number
& 3) != 0)
1768 as_bad (_("jump to misaligned address (0x%lx)"),
1769 (unsigned long) address_expr
->X_add_number
);
1771 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1772 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1773 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1777 case BFD_RELOC_16_PCREL_S2
:
1787 /* Don't generate a reloc if we are writing into a variant
1791 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1793 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1797 struct mips_hi_fixup
*hi_fixup
;
1799 assert (reloc_type
== BFD_RELOC_HI16_S
);
1800 hi_fixup
= ((struct mips_hi_fixup
*)
1801 xmalloc (sizeof (struct mips_hi_fixup
)));
1802 hi_fixup
->fixp
= fixp
;
1803 hi_fixup
->seg
= now_seg
;
1804 hi_fixup
->next
= mips_hi_fixup_list
;
1805 mips_hi_fixup_list
= hi_fixup
;
1811 if (! mips_opts
.mips16
)
1812 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1813 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1815 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1816 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1822 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1825 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1828 /* Update the register mask information. */
1829 if (! mips_opts
.mips16
)
1831 if (pinfo
& INSN_WRITE_GPR_D
)
1832 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1833 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1834 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1835 if (pinfo
& INSN_READ_GPR_S
)
1836 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1837 if (pinfo
& INSN_WRITE_GPR_31
)
1838 mips_gprmask
|= 1 << 31;
1839 if (pinfo
& INSN_WRITE_FPR_D
)
1840 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1841 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1842 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1843 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1844 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1845 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1846 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1847 if (pinfo
& INSN_COP
)
1849 /* We don't keep enough information to sort these cases out.
1850 The itbl support does keep this information however, although
1851 we currently don't support itbl fprmats as part of the cop
1852 instruction. May want to add this support in the future. */
1854 /* Never set the bit for $0, which is always zero. */
1855 mips_gprmask
&=~ 1 << 0;
1859 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1860 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1861 & MIPS16OP_MASK_RX
);
1862 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1863 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1864 & MIPS16OP_MASK_RY
);
1865 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1866 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1867 & MIPS16OP_MASK_RZ
);
1868 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1869 mips_gprmask
|= 1 << TREG
;
1870 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1871 mips_gprmask
|= 1 << SP
;
1872 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1873 mips_gprmask
|= 1 << RA
;
1874 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1875 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1876 if (pinfo
& MIPS16_INSN_READ_Z
)
1877 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1878 & MIPS16OP_MASK_MOVE32Z
);
1879 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1880 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1881 & MIPS16OP_MASK_REGR32
);
1884 if (place
== NULL
&& ! mips_opts
.noreorder
)
1886 /* Filling the branch delay slot is more complex. We try to
1887 switch the branch with the previous instruction, which we can
1888 do if the previous instruction does not set up a condition
1889 that the branch tests and if the branch is not itself the
1890 target of any branch. */
1891 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1892 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1894 if (mips_optimize
< 2
1895 /* If we have seen .set volatile or .set nomove, don't
1897 || mips_opts
.nomove
!= 0
1898 /* If we had to emit any NOP instructions, then we
1899 already know we can not swap. */
1901 /* If we don't even know the previous insn, we can not
1903 || ! prev_insn_valid
1904 /* If the previous insn is already in a branch delay
1905 slot, then we can not swap. */
1906 || prev_insn_is_delay_slot
1907 /* If the previous previous insn was in a .set
1908 noreorder, we can't swap. Actually, the MIPS
1909 assembler will swap in this situation. However, gcc
1910 configured -with-gnu-as will generate code like
1916 in which we can not swap the bne and INSN. If gcc is
1917 not configured -with-gnu-as, it does not output the
1918 .set pseudo-ops. We don't have to check
1919 prev_insn_unreordered, because prev_insn_valid will
1920 be 0 in that case. We don't want to use
1921 prev_prev_insn_valid, because we do want to be able
1922 to swap at the start of a function. */
1923 || prev_prev_insn_unreordered
1924 /* If the branch is itself the target of a branch, we
1925 can not swap. We cheat on this; all we check for is
1926 whether there is a label on this instruction. If
1927 there are any branches to anything other than a
1928 label, users must use .set noreorder. */
1929 || insn_labels
!= NULL
1930 /* If the previous instruction is in a variant frag, we
1931 can not do the swap. This does not apply to the
1932 mips16, which uses variant frags for different
1934 || (! mips_opts
.mips16
1935 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1936 /* If the branch reads the condition codes, we don't
1937 even try to swap, because in the sequence
1942 we can not swap, and I don't feel like handling that
1944 || (! mips_opts
.mips16
1945 && mips_opts
.isa
< 4
1946 && (pinfo
& INSN_READ_COND_CODE
))
1947 /* We can not swap with an instruction that requires a
1948 delay slot, becase the target of the branch might
1949 interfere with that instruction. */
1950 || (! mips_opts
.mips16
1951 && mips_opts
.isa
< 4
1953 /* Itbl support may require additional care here. */
1954 & (INSN_LOAD_COPROC_DELAY
1955 | INSN_COPROC_MOVE_DELAY
1956 | INSN_WRITE_COND_CODE
)))
1957 || (! (hilo_interlocks
1958 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1962 || (! mips_opts
.mips16
1964 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1965 || (! mips_opts
.mips16
1966 && mips_opts
.isa
< 2
1967 /* Itbl support may require additional care here. */
1968 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1969 /* We can not swap with a branch instruction. */
1971 & (INSN_UNCOND_BRANCH_DELAY
1972 | INSN_COND_BRANCH_DELAY
1973 | INSN_COND_BRANCH_LIKELY
))
1974 /* We do not swap with a trap instruction, since it
1975 complicates trap handlers to have the trap
1976 instruction be in a delay slot. */
1977 || (prev_pinfo
& INSN_TRAP
)
1978 /* If the branch reads a register that the previous
1979 instruction sets, we can not swap. */
1980 || (! mips_opts
.mips16
1981 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1982 && insn_uses_reg (ip
,
1983 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1986 || (! mips_opts
.mips16
1987 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1988 && insn_uses_reg (ip
,
1989 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1992 || (mips_opts
.mips16
1993 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1994 && insn_uses_reg (ip
,
1995 ((prev_insn
.insn_opcode
1997 & MIPS16OP_MASK_RX
),
1999 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2000 && insn_uses_reg (ip
,
2001 ((prev_insn
.insn_opcode
2003 & MIPS16OP_MASK_RY
),
2005 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2006 && insn_uses_reg (ip
,
2007 ((prev_insn
.insn_opcode
2009 & MIPS16OP_MASK_RZ
),
2011 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2012 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2013 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2014 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2015 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2016 && insn_uses_reg (ip
,
2017 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2020 /* If the branch writes a register that the previous
2021 instruction sets, we can not swap (we know that
2022 branches write only to RD or to $31). */
2023 || (! mips_opts
.mips16
2024 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2025 && (((pinfo
& INSN_WRITE_GPR_D
)
2026 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2027 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2028 || ((pinfo
& INSN_WRITE_GPR_31
)
2029 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2032 || (! mips_opts
.mips16
2033 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2034 && (((pinfo
& INSN_WRITE_GPR_D
)
2035 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2036 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2037 || ((pinfo
& INSN_WRITE_GPR_31
)
2038 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2041 || (mips_opts
.mips16
2042 && (pinfo
& MIPS16_INSN_WRITE_31
)
2043 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2044 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2045 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2047 /* If the branch writes a register that the previous
2048 instruction reads, we can not swap (we know that
2049 branches only write to RD or to $31). */
2050 || (! mips_opts
.mips16
2051 && (pinfo
& INSN_WRITE_GPR_D
)
2052 && insn_uses_reg (&prev_insn
,
2053 ((ip
->insn_opcode
>> OP_SH_RD
)
2056 || (! mips_opts
.mips16
2057 && (pinfo
& INSN_WRITE_GPR_31
)
2058 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2059 || (mips_opts
.mips16
2060 && (pinfo
& MIPS16_INSN_WRITE_31
)
2061 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2062 /* If we are generating embedded PIC code, the branch
2063 might be expanded into a sequence which uses $at, so
2064 we can't swap with an instruction which reads it. */
2065 || (mips_pic
== EMBEDDED_PIC
2066 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2067 /* If the previous previous instruction has a load
2068 delay, and sets a register that the branch reads, we
2070 || (! mips_opts
.mips16
2071 && mips_opts
.isa
< 4
2072 /* Itbl support may require additional care here. */
2073 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2074 || (! gpr_interlocks
2075 && (prev_prev_insn
.insn_mo
->pinfo
2076 & INSN_LOAD_MEMORY_DELAY
)))
2077 && insn_uses_reg (ip
,
2078 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2081 /* If one instruction sets a condition code and the
2082 other one uses a condition code, we can not swap. */
2083 || ((pinfo
& INSN_READ_COND_CODE
)
2084 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2085 || ((pinfo
& INSN_WRITE_COND_CODE
)
2086 && (prev_pinfo
& INSN_READ_COND_CODE
))
2087 /* If the previous instruction uses the PC, we can not
2089 || (mips_opts
.mips16
2090 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2091 /* If the previous instruction was extended, we can not
2093 || (mips_opts
.mips16
&& prev_insn_extended
)
2094 /* If the previous instruction had a fixup in mips16
2095 mode, we can not swap. This normally means that the
2096 previous instruction was a 4 byte branch anyhow. */
2097 || (mips_opts
.mips16
&& prev_insn_fixp
)
2098 /* If the previous instruction is a sync, sync.l, or
2099 sync.p, we can not swap. */
2100 || (prev_pinfo
& INSN_SYNC
))
2102 /* We could do even better for unconditional branches to
2103 portions of this object file; we could pick up the
2104 instruction at the destination, put it in the delay
2105 slot, and bump the destination address. */
2107 /* Update the previous insn information. */
2108 prev_prev_insn
= *ip
;
2109 prev_insn
.insn_mo
= &dummy_opcode
;
2113 /* It looks like we can actually do the swap. */
2114 if (! mips_opts
.mips16
)
2119 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2120 memcpy (temp
, prev_f
, 4);
2121 memcpy (prev_f
, f
, 4);
2122 memcpy (f
, temp
, 4);
2125 prev_insn_fixp
->fx_frag
= frag_now
;
2126 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2130 fixp
->fx_frag
= prev_insn_frag
;
2131 fixp
->fx_where
= prev_insn_where
;
2139 assert (prev_insn_fixp
== NULL
);
2140 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2141 memcpy (temp
, prev_f
, 2);
2142 memcpy (prev_f
, f
, 2);
2143 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2145 assert (reloc_type
== BFD_RELOC_UNUSED
);
2146 memcpy (f
, temp
, 2);
2150 memcpy (f
, f
+ 2, 2);
2151 memcpy (f
+ 2, temp
, 2);
2155 fixp
->fx_frag
= prev_insn_frag
;
2156 fixp
->fx_where
= prev_insn_where
;
2160 /* Update the previous insn information; leave prev_insn
2162 prev_prev_insn
= *ip
;
2164 prev_insn_is_delay_slot
= 1;
2166 /* If that was an unconditional branch, forget the previous
2167 insn information. */
2168 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2170 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2171 prev_insn
.insn_mo
= &dummy_opcode
;
2174 prev_insn_fixp
= NULL
;
2175 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2176 prev_insn_extended
= 0;
2178 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2180 /* We don't yet optimize a branch likely. What we should do
2181 is look at the target, copy the instruction found there
2182 into the delay slot, and increment the branch to jump to
2183 the next instruction. */
2185 /* Update the previous insn information. */
2186 prev_prev_insn
= *ip
;
2187 prev_insn
.insn_mo
= &dummy_opcode
;
2188 prev_insn_fixp
= NULL
;
2189 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2190 prev_insn_extended
= 0;
2194 /* Update the previous insn information. */
2196 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2198 prev_prev_insn
= prev_insn
;
2201 /* Any time we see a branch, we always fill the delay slot
2202 immediately; since this insn is not a branch, we know it
2203 is not in a delay slot. */
2204 prev_insn_is_delay_slot
= 0;
2206 prev_insn_fixp
= fixp
;
2207 prev_insn_reloc_type
= reloc_type
;
2208 if (mips_opts
.mips16
)
2209 prev_insn_extended
= (ip
->use_extend
2210 || reloc_type
> BFD_RELOC_UNUSED
);
2213 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2214 prev_insn_unreordered
= 0;
2215 prev_insn_frag
= frag_now
;
2216 prev_insn_where
= f
- frag_now
->fr_literal
;
2217 prev_insn_valid
= 1;
2219 else if (place
== NULL
)
2221 /* We need to record a bit of information even when we are not
2222 reordering, in order to determine the base address for mips16
2223 PC relative relocs. */
2224 prev_prev_insn
= prev_insn
;
2226 prev_insn_reloc_type
= reloc_type
;
2227 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2228 prev_insn_unreordered
= 1;
2231 /* We just output an insn, so the next one doesn't have a label. */
2232 mips_clear_insn_labels ();
2234 /* We must ensure that a fixup associated with an unmatched %hi
2235 reloc does not become a variant frag. Otherwise, the
2236 rearrangement of %hi relocs in frob_file may confuse
2240 frag_wane (frag_now
);
2245 /* This function forgets that there was any previous instruction or
2246 label. If PRESERVE is non-zero, it remembers enough information to
2247 know whether nops are needed before a noreorder section. */
2250 mips_no_prev_insn (preserve
)
2255 prev_insn
.insn_mo
= &dummy_opcode
;
2256 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2257 prev_nop_frag
= NULL
;
2258 prev_nop_frag_holds
= 0;
2259 prev_nop_frag_required
= 0;
2260 prev_nop_frag_since
= 0;
2262 prev_insn_valid
= 0;
2263 prev_insn_is_delay_slot
= 0;
2264 prev_insn_unreordered
= 0;
2265 prev_insn_extended
= 0;
2266 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2267 prev_prev_insn_unreordered
= 0;
2268 mips_clear_insn_labels ();
2271 /* This function must be called whenever we turn on noreorder or emit
2272 something other than instructions. It inserts any NOPS which might
2273 be needed by the previous instruction, and clears the information
2274 kept for the previous instructions. The INSNS parameter is true if
2275 instructions are to follow. */
2278 mips_emit_delays (insns
)
2281 if (! mips_opts
.noreorder
)
2286 if ((! mips_opts
.mips16
2287 && mips_opts
.isa
< 4
2288 && (! cop_interlocks
2289 && (prev_insn
.insn_mo
->pinfo
2290 & (INSN_LOAD_COPROC_DELAY
2291 | INSN_COPROC_MOVE_DELAY
2292 | INSN_WRITE_COND_CODE
))))
2293 || (! hilo_interlocks
2294 && (prev_insn
.insn_mo
->pinfo
2297 || (! mips_opts
.mips16
2299 && (prev_insn
.insn_mo
->pinfo
2300 & INSN_LOAD_MEMORY_DELAY
))
2301 || (! mips_opts
.mips16
2302 && mips_opts
.isa
< 2
2303 && (prev_insn
.insn_mo
->pinfo
2304 & INSN_COPROC_MEMORY_DELAY
)))
2306 /* Itbl support may require additional care here. */
2308 if ((! mips_opts
.mips16
2309 && mips_opts
.isa
< 4
2310 && (! cop_interlocks
2311 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2312 || (! hilo_interlocks
2313 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2314 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2317 if (prev_insn_unreordered
)
2320 else if ((! mips_opts
.mips16
2321 && mips_opts
.isa
< 4
2322 && (! cop_interlocks
2323 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2324 || (! hilo_interlocks
2325 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2326 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2328 /* Itbl support may require additional care here. */
2329 if (! prev_prev_insn_unreordered
)
2335 struct insn_label_list
*l
;
2339 /* Record the frag which holds the nop instructions, so
2340 that we can remove them if we don't need them. */
2341 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2342 prev_nop_frag
= frag_now
;
2343 prev_nop_frag_holds
= nops
;
2344 prev_nop_frag_required
= 0;
2345 prev_nop_frag_since
= 0;
2348 for (; nops
> 0; --nops
)
2353 /* Move on to a new frag, so that it is safe to simply
2354 decrease the size of prev_nop_frag. */
2355 frag_wane (frag_now
);
2359 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2361 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2362 symbol_set_frag (l
->label
, frag_now
);
2363 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2364 /* mips16 text labels are stored as odd. */
2365 if (mips_opts
.mips16
)
2366 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2371 /* Mark instruction labels in mips16 mode. */
2372 if (mips_opts
.mips16
&& insns
)
2373 mips16_mark_labels ();
2375 mips_no_prev_insn (insns
);
2378 /* Build an instruction created by a macro expansion. This is passed
2379 a pointer to the count of instructions created so far, an
2380 expression, the name of the instruction to build, an operand format
2381 string, and corresponding arguments. */
2385 macro_build (char *place
,
2393 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2402 struct mips_cl_insn insn
;
2403 bfd_reloc_code_real_type r
;
2408 va_start (args
, fmt
);
2414 * If the macro is about to expand into a second instruction,
2415 * print a warning if needed. We need to pass ip as a parameter
2416 * to generate a better warning message here...
2418 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2419 as_warn (_("Macro instruction expanded into multiple instructions"));
2422 *counter
+= 1; /* bump instruction counter */
2424 if (mips_opts
.mips16
)
2426 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2431 r
= BFD_RELOC_UNUSED
;
2432 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2433 assert (insn
.insn_mo
);
2434 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2436 /* Search until we get a match for NAME. */
2439 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2441 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2443 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2445 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2450 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2451 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2452 && (insn_isa
<= mips_opts
.isa
2453 || (mips_cpu
== 4650
2454 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2455 || (mips_cpu
== 4010
2456 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2457 || ((mips_cpu
== 4100
2460 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2461 || (mips_cpu
== 3900
2462 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2463 && (mips_cpu
!= 4650 || (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2467 assert (insn
.insn_mo
->name
);
2468 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2471 insn
.insn_opcode
= insn
.insn_mo
->match
;
2487 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2493 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2498 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2503 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2510 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2514 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2518 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2522 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2529 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2535 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2536 assert (r
== BFD_RELOC_MIPS_GPREL
2537 || r
== BFD_RELOC_MIPS_LITERAL
2538 || r
== BFD_RELOC_LO16
2539 || r
== BFD_RELOC_MIPS_GOT16
2540 || r
== BFD_RELOC_MIPS_CALL16
2541 || r
== BFD_RELOC_MIPS_GOT_LO16
2542 || r
== BFD_RELOC_MIPS_CALL_LO16
2543 || (ep
->X_op
== O_subtract
2544 && now_seg
== text_section
2545 && r
== BFD_RELOC_PCREL_LO16
));
2549 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2551 && (ep
->X_op
== O_constant
2552 || (ep
->X_op
== O_symbol
2553 && (r
== BFD_RELOC_HI16_S
2554 || r
== BFD_RELOC_HI16
2555 || r
== BFD_RELOC_MIPS_GOT_HI16
2556 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2557 || (ep
->X_op
== O_subtract
2558 && now_seg
== text_section
2559 && r
== BFD_RELOC_PCREL_HI16_S
)));
2560 if (ep
->X_op
== O_constant
)
2562 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2564 r
= BFD_RELOC_UNUSED
;
2569 assert (ep
!= NULL
);
2571 * This allows macro() to pass an immediate expression for
2572 * creating short branches without creating a symbol.
2573 * Note that the expression still might come from the assembly
2574 * input, in which case the value is not checked for range nor
2575 * is a relocation entry generated (yuck).
2577 if (ep
->X_op
== O_constant
)
2579 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2583 r
= BFD_RELOC_16_PCREL_S2
;
2587 assert (ep
!= NULL
);
2588 r
= BFD_RELOC_MIPS_JMP
;
2592 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2601 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2603 append_insn (place
, &insn
, ep
, r
, false);
2607 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2615 struct mips_cl_insn insn
;
2616 bfd_reloc_code_real_type r
;
2618 r
= BFD_RELOC_UNUSED
;
2619 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2620 assert (insn
.insn_mo
);
2621 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2623 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2624 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2627 assert (insn
.insn_mo
->name
);
2628 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2631 insn
.insn_opcode
= insn
.insn_mo
->match
;
2632 insn
.use_extend
= false;
2651 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2656 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2660 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2664 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2674 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2681 regno
= va_arg (args
, int);
2682 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2683 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2704 assert (ep
!= NULL
);
2706 if (ep
->X_op
!= O_constant
)
2707 r
= BFD_RELOC_UNUSED
+ c
;
2710 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2711 false, false, &insn
.insn_opcode
,
2712 &insn
.use_extend
, &insn
.extend
);
2714 r
= BFD_RELOC_UNUSED
;
2720 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2727 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2729 append_insn (place
, &insn
, ep
, r
, false);
2733 * Generate a "lui" instruction.
2736 macro_build_lui (place
, counter
, ep
, regnum
)
2742 expressionS high_expr
;
2743 struct mips_cl_insn insn
;
2744 bfd_reloc_code_real_type r
;
2745 CONST
char *name
= "lui";
2746 CONST
char *fmt
= "t,u";
2748 assert (! mips_opts
.mips16
);
2754 high_expr
.X_op
= O_constant
;
2755 high_expr
.X_add_number
= ep
->X_add_number
;
2758 if (high_expr
.X_op
== O_constant
)
2760 /* we can compute the instruction now without a relocation entry */
2761 if (high_expr
.X_add_number
& 0x8000)
2762 high_expr
.X_add_number
+= 0x10000;
2763 high_expr
.X_add_number
=
2764 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2765 r
= BFD_RELOC_UNUSED
;
2769 assert (ep
->X_op
== O_symbol
);
2770 /* _gp_disp is a special case, used from s_cpload. */
2771 assert (mips_pic
== NO_PIC
2772 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2773 r
= BFD_RELOC_HI16_S
;
2777 * If the macro is about to expand into a second instruction,
2778 * print a warning if needed. We need to pass ip as a parameter
2779 * to generate a better warning message here...
2781 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2782 as_warn (_("Macro instruction expanded into multiple instructions"));
2785 *counter
+= 1; /* bump instruction counter */
2787 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2788 assert (insn
.insn_mo
);
2789 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2790 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2792 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2793 if (r
== BFD_RELOC_UNUSED
)
2795 insn
.insn_opcode
|= high_expr
.X_add_number
;
2796 append_insn (place
, &insn
, NULL
, r
, false);
2799 append_insn (place
, &insn
, &high_expr
, r
, false);
2803 * Generates code to set the $at register to true (one)
2804 * if reg is less than the immediate expression.
2807 set_at (counter
, reg
, unsignedp
)
2812 if (imm_expr
.X_op
== O_constant
2813 && imm_expr
.X_add_number
>= -0x8000
2814 && imm_expr
.X_add_number
< 0x8000)
2815 macro_build ((char *) NULL
, counter
, &imm_expr
,
2816 unsignedp
? "sltiu" : "slti",
2817 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2820 load_register (counter
, AT
, &imm_expr
, 0);
2821 macro_build ((char *) NULL
, counter
, NULL
,
2822 unsignedp
? "sltu" : "slt",
2823 "d,v,t", AT
, reg
, AT
);
2827 /* Warn if an expression is not a constant. */
2830 check_absolute_expr (ip
, ex
)
2831 struct mips_cl_insn
*ip
;
2834 if (ex
->X_op
== O_big
)
2835 as_bad (_("unsupported large constant"));
2836 else if (ex
->X_op
!= O_constant
)
2837 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2840 /* Count the leading zeroes by performing a binary chop. This is a
2841 bulky bit of source, but performance is a LOT better for the
2842 majority of values than a simple loop to count the bits:
2843 for (lcnt = 0; (lcnt < 32); lcnt++)
2844 if ((v) & (1 << (31 - lcnt)))
2846 However it is not code size friendly, and the gain will drop a bit
2847 on certain cached systems.
2849 #define COUNT_TOP_ZEROES(v) \
2850 (((v) & ~0xffff) == 0 \
2851 ? ((v) & ~0xff) == 0 \
2852 ? ((v) & ~0xf) == 0 \
2853 ? ((v) & ~0x3) == 0 \
2854 ? ((v) & ~0x1) == 0 \
2859 : ((v) & ~0x7) == 0 \
2862 : ((v) & ~0x3f) == 0 \
2863 ? ((v) & ~0x1f) == 0 \
2866 : ((v) & ~0x7f) == 0 \
2869 : ((v) & ~0xfff) == 0 \
2870 ? ((v) & ~0x3ff) == 0 \
2871 ? ((v) & ~0x1ff) == 0 \
2874 : ((v) & ~0x7ff) == 0 \
2877 : ((v) & ~0x3fff) == 0 \
2878 ? ((v) & ~0x1fff) == 0 \
2881 : ((v) & ~0x7fff) == 0 \
2884 : ((v) & ~0xffffff) == 0 \
2885 ? ((v) & ~0xfffff) == 0 \
2886 ? ((v) & ~0x3ffff) == 0 \
2887 ? ((v) & ~0x1ffff) == 0 \
2890 : ((v) & ~0x7ffff) == 0 \
2893 : ((v) & ~0x3fffff) == 0 \
2894 ? ((v) & ~0x1fffff) == 0 \
2897 : ((v) & ~0x7fffff) == 0 \
2900 : ((v) & ~0xfffffff) == 0 \
2901 ? ((v) & ~0x3ffffff) == 0 \
2902 ? ((v) & ~0x1ffffff) == 0 \
2905 : ((v) & ~0x7ffffff) == 0 \
2908 : ((v) & ~0x3fffffff) == 0 \
2909 ? ((v) & ~0x1fffffff) == 0 \
2912 : ((v) & ~0x7fffffff) == 0 \
2917 * This routine generates the least number of instructions neccessary to load
2918 * an absolute expression value into a register.
2921 load_register (counter
, reg
, ep
, dbl
)
2928 expressionS hi32
, lo32
;
2930 if (ep
->X_op
!= O_big
)
2932 assert (ep
->X_op
== O_constant
);
2933 if (ep
->X_add_number
< 0x8000
2934 && (ep
->X_add_number
>= 0
2935 || (ep
->X_add_number
>= -0x8000
2938 || sizeof (ep
->X_add_number
) > 4))))
2940 /* We can handle 16 bit signed values with an addiu to
2941 $zero. No need to ever use daddiu here, since $zero and
2942 the result are always correct in 32 bit mode. */
2943 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2944 (int) BFD_RELOC_LO16
);
2947 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2949 /* We can handle 16 bit unsigned values with an ori to
2951 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2952 (int) BFD_RELOC_LO16
);
2955 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2956 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2957 == ~ (offsetT
) 0x7fffffff))
2960 || sizeof (ep
->X_add_number
) > 4
2961 || (ep
->X_add_number
& 0x80000000) == 0))
2962 || ((mips_opts
.isa
< 3 || ! dbl
)
2963 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2964 || (mips_opts
.isa
< 3
2966 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2967 == ~ (offsetT
) 0xffffffff)))
2969 /* 32 bit values require an lui. */
2970 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2971 (int) BFD_RELOC_HI16
);
2972 if ((ep
->X_add_number
& 0xffff) != 0)
2973 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2974 (int) BFD_RELOC_LO16
);
2979 /* The value is larger than 32 bits. */
2981 if (mips_opts
.isa
< 3)
2983 as_bad (_("Number larger than 32 bits"));
2984 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2985 (int) BFD_RELOC_LO16
);
2989 if (ep
->X_op
!= O_big
)
2992 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2993 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2994 hi32
.X_add_number
&= 0xffffffff;
2996 lo32
.X_add_number
&= 0xffffffff;
3000 assert (ep
->X_add_number
> 2);
3001 if (ep
->X_add_number
== 3)
3002 generic_bignum
[3] = 0;
3003 else if (ep
->X_add_number
> 4)
3004 as_bad (_("Number larger than 64 bits"));
3005 lo32
.X_op
= O_constant
;
3006 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3007 hi32
.X_op
= O_constant
;
3008 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3011 if (hi32
.X_add_number
== 0)
3016 unsigned long hi
, lo
;
3018 if (hi32
.X_add_number
== 0xffffffff)
3020 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3022 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3023 reg
, 0, (int) BFD_RELOC_LO16
);
3026 if (lo32
.X_add_number
& 0x80000000)
3028 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3029 (int) BFD_RELOC_HI16
);
3030 if (lo32
.X_add_number
& 0xffff)
3031 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3032 reg
, reg
, (int) BFD_RELOC_LO16
);
3037 /* Check for 16bit shifted constant. We know that hi32 is
3038 non-zero, so start the mask on the first bit of the hi32
3043 unsigned long himask
, lomask
;
3047 himask
= 0xffff >> (32 - shift
);
3048 lomask
= (0xffff << shift
) & 0xffffffff;
3052 himask
= 0xffff << (shift
- 32);
3055 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3056 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3060 tmp
.X_op
= O_constant
;
3062 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3063 | (lo32
.X_add_number
>> shift
));
3065 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3066 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3067 (int) BFD_RELOC_LO16
);
3068 macro_build ((char *) NULL
, counter
, NULL
,
3069 (shift
>= 32) ? "dsll32" : "dsll",
3071 (shift
>= 32) ? shift
- 32 : shift
);
3075 } while (shift
<= (64 - 16));
3077 /* Find the bit number of the lowest one bit, and store the
3078 shifted value in hi/lo. */
3079 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3080 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3084 while ((lo
& 1) == 0)
3089 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3095 while ((hi
& 1) == 0)
3104 /* Optimize if the shifted value is a (power of 2) - 1. */
3105 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3106 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3108 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3113 /* This instruction will set the register to be all
3115 tmp
.X_op
= O_constant
;
3116 tmp
.X_add_number
= (offsetT
) -1;
3117 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3118 reg
, 0, (int) BFD_RELOC_LO16
);
3122 macro_build ((char *) NULL
, counter
, NULL
,
3123 (bit
>= 32) ? "dsll32" : "dsll",
3125 (bit
>= 32) ? bit
- 32 : bit
);
3127 macro_build ((char *) NULL
, counter
, NULL
,
3128 (shift
>= 32) ? "dsrl32" : "dsrl",
3130 (shift
>= 32) ? shift
- 32 : shift
);
3135 /* Sign extend hi32 before calling load_register, because we can
3136 generally get better code when we load a sign extended value. */
3137 if ((hi32
.X_add_number
& 0x80000000) != 0)
3138 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3139 load_register (counter
, reg
, &hi32
, 0);
3142 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3146 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3155 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3157 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3158 (int) BFD_RELOC_HI16
);
3159 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3166 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3171 mid16
.X_add_number
>>= 16;
3172 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3173 freg
, (int) BFD_RELOC_LO16
);
3174 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3178 if ((lo32
.X_add_number
& 0xffff) != 0)
3179 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3180 (int) BFD_RELOC_LO16
);
3183 /* Load an address into a register. */
3186 load_address (counter
, reg
, ep
)
3193 if (ep
->X_op
!= O_constant
3194 && ep
->X_op
!= O_symbol
)
3196 as_bad (_("expression too complex"));
3197 ep
->X_op
= O_constant
;
3200 if (ep
->X_op
== O_constant
)
3202 load_register (counter
, reg
, ep
, 0);
3206 if (mips_pic
== NO_PIC
)
3208 /* If this is a reference to a GP relative symbol, we want
3209 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3211 lui $reg,<sym> (BFD_RELOC_HI16_S)
3212 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3213 If we have an addend, we always use the latter form. */
3214 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3215 || nopic_need_relax (ep
->X_add_symbol
, 1))
3220 macro_build ((char *) NULL
, counter
, ep
,
3221 ((bfd_arch_bits_per_address (stdoutput
) == 32
3222 || mips_opts
.isa
< 3)
3223 ? "addiu" : "daddiu"),
3224 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3225 p
= frag_var (rs_machine_dependent
, 8, 0,
3226 RELAX_ENCODE (4, 8, 0, 4, 0,
3227 mips_opts
.warn_about_macros
),
3228 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3230 macro_build_lui (p
, counter
, ep
, reg
);
3233 macro_build (p
, counter
, ep
,
3234 ((bfd_arch_bits_per_address (stdoutput
) == 32
3235 || mips_opts
.isa
< 3)
3236 ? "addiu" : "daddiu"),
3237 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3239 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3243 /* If this is a reference to an external symbol, we want
3244 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3246 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3248 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3249 If there is a constant, it must be added in after. */
3250 ex
.X_add_number
= ep
->X_add_number
;
3251 ep
->X_add_number
= 0;
3253 macro_build ((char *) NULL
, counter
, ep
,
3254 ((bfd_arch_bits_per_address (stdoutput
) == 32
3255 || mips_opts
.isa
< 3)
3257 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3258 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3259 p
= frag_var (rs_machine_dependent
, 4, 0,
3260 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3261 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3262 macro_build (p
, counter
, ep
,
3263 ((bfd_arch_bits_per_address (stdoutput
) == 32
3264 || mips_opts
.isa
< 3)
3265 ? "addiu" : "daddiu"),
3266 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3267 if (ex
.X_add_number
!= 0)
3269 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3270 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3271 ex
.X_op
= O_constant
;
3272 macro_build ((char *) NULL
, counter
, &ex
,
3273 ((bfd_arch_bits_per_address (stdoutput
) == 32
3274 || mips_opts
.isa
< 3)
3275 ? "addiu" : "daddiu"),
3276 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3279 else if (mips_pic
== SVR4_PIC
)
3284 /* This is the large GOT case. If this is a reference to an
3285 external symbol, we want
3286 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3288 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3289 Otherwise, for a reference to a local symbol, we want
3290 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3292 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3293 If there is a constant, it must be added in after. */
3294 ex
.X_add_number
= ep
->X_add_number
;
3295 ep
->X_add_number
= 0;
3296 if (reg_needs_delay (GP
))
3301 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3302 (int) BFD_RELOC_MIPS_GOT_HI16
);
3303 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3304 ((bfd_arch_bits_per_address (stdoutput
) == 32
3305 || mips_opts
.isa
< 3)
3306 ? "addu" : "daddu"),
3307 "d,v,t", reg
, reg
, GP
);
3308 macro_build ((char *) NULL
, counter
, ep
,
3309 ((bfd_arch_bits_per_address (stdoutput
) == 32
3310 || mips_opts
.isa
< 3)
3312 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3313 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3314 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3315 mips_opts
.warn_about_macros
),
3316 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3319 /* We need a nop before loading from $gp. This special
3320 check is required because the lui which starts the main
3321 instruction stream does not refer to $gp, and so will not
3322 insert the nop which may be required. */
3323 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3326 macro_build (p
, counter
, ep
,
3327 ((bfd_arch_bits_per_address (stdoutput
) == 32
3328 || mips_opts
.isa
< 3)
3330 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3332 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3334 macro_build (p
, counter
, ep
,
3335 ((bfd_arch_bits_per_address (stdoutput
) == 32
3336 || mips_opts
.isa
< 3)
3337 ? "addiu" : "daddiu"),
3338 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3339 if (ex
.X_add_number
!= 0)
3341 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3342 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3343 ex
.X_op
= O_constant
;
3344 macro_build ((char *) NULL
, counter
, &ex
,
3345 ((bfd_arch_bits_per_address (stdoutput
) == 32
3346 || mips_opts
.isa
< 3)
3347 ? "addiu" : "daddiu"),
3348 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3351 else if (mips_pic
== EMBEDDED_PIC
)
3354 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3356 macro_build ((char *) NULL
, counter
, ep
,
3357 ((bfd_arch_bits_per_address (stdoutput
) == 32
3358 || mips_opts
.isa
< 3)
3359 ? "addiu" : "daddiu"),
3360 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3368 * This routine implements the seemingly endless macro or synthesized
3369 * instructions and addressing modes in the mips assembly language. Many
3370 * of these macros are simple and are similar to each other. These could
3371 * probably be handled by some kind of table or grammer aproach instead of
3372 * this verbose method. Others are not simple macros but are more like
3373 * optimizing code generation.
3374 * One interesting optimization is when several store macros appear
3375 * consecutivly that would load AT with the upper half of the same address.
3376 * The ensuing load upper instructions are ommited. This implies some kind
3377 * of global optimization. We currently only optimize within a single macro.
3378 * For many of the load and store macros if the address is specified as a
3379 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3380 * first load register 'at' with zero and use it as the base register. The
3381 * mips assembler simply uses register $zero. Just one tiny optimization
3386 struct mips_cl_insn
*ip
;
3388 register int treg
, sreg
, dreg
, breg
;
3404 bfd_reloc_code_real_type r
;
3406 int hold_mips_optimize
;
3408 assert (! mips_opts
.mips16
);
3410 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3411 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3412 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3413 mask
= ip
->insn_mo
->mask
;
3415 expr1
.X_op
= O_constant
;
3416 expr1
.X_op_symbol
= NULL
;
3417 expr1
.X_add_symbol
= NULL
;
3418 expr1
.X_add_number
= 1;
3430 mips_emit_delays (true);
3431 ++mips_opts
.noreorder
;
3432 mips_any_noreorder
= 1;
3434 expr1
.X_add_number
= 8;
3435 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3437 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3439 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3440 macro_build ((char *) NULL
, &icnt
, NULL
,
3441 dbl
? "dsub" : "sub",
3442 "d,v,t", dreg
, 0, sreg
);
3444 --mips_opts
.noreorder
;
3465 if (imm_expr
.X_op
== O_constant
3466 && imm_expr
.X_add_number
>= -0x8000
3467 && imm_expr
.X_add_number
< 0x8000)
3469 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3470 (int) BFD_RELOC_LO16
);
3473 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3474 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3493 if (imm_expr
.X_op
== O_constant
3494 && imm_expr
.X_add_number
>= 0
3495 && imm_expr
.X_add_number
< 0x10000)
3497 if (mask
!= M_NOR_I
)
3498 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3499 sreg
, (int) BFD_RELOC_LO16
);
3502 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3503 treg
, sreg
, (int) BFD_RELOC_LO16
);
3504 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3510 load_register (&icnt
, AT
, &imm_expr
, 0);
3511 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3528 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3530 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3534 load_register (&icnt
, AT
, &imm_expr
, 0);
3535 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3543 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3544 likely
? "bgezl" : "bgez",
3550 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3551 likely
? "blezl" : "blez",
3555 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3556 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3557 likely
? "beql" : "beq",
3564 /* check for > max integer */
3565 maxnum
= 0x7fffffff;
3566 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3573 if (imm_expr
.X_op
== O_constant
3574 && imm_expr
.X_add_number
>= maxnum
3575 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3578 /* result is always false */
3581 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3582 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3586 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3587 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3592 if (imm_expr
.X_op
!= O_constant
)
3593 as_bad (_("Unsupported large constant"));
3594 imm_expr
.X_add_number
++;
3598 if (mask
== M_BGEL_I
)
3600 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3602 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3603 likely
? "bgezl" : "bgez",
3607 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3609 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3610 likely
? "bgtzl" : "bgtz",
3614 maxnum
= 0x7fffffff;
3615 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3622 maxnum
= - maxnum
- 1;
3623 if (imm_expr
.X_op
== O_constant
3624 && imm_expr
.X_add_number
<= maxnum
3625 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3628 /* result is always true */
3629 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3630 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3633 set_at (&icnt
, sreg
, 0);
3634 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3635 likely
? "beql" : "beq",
3646 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3647 likely
? "beql" : "beq",
3651 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3653 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3654 likely
? "beql" : "beq",
3662 || (mips_opts
.isa
< 3
3663 && imm_expr
.X_op
== O_constant
3664 && imm_expr
.X_add_number
== 0xffffffff))
3666 if (imm_expr
.X_op
!= O_constant
)
3667 as_bad (_("Unsupported large constant"));
3668 imm_expr
.X_add_number
++;
3672 if (mask
== M_BGEUL_I
)
3674 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3676 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3678 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3679 likely
? "bnel" : "bne",
3683 set_at (&icnt
, sreg
, 1);
3684 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3685 likely
? "beql" : "beq",
3694 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3695 likely
? "bgtzl" : "bgtz",
3701 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3702 likely
? "bltzl" : "bltz",
3706 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3707 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3708 likely
? "bnel" : "bne",
3717 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3718 likely
? "bnel" : "bne",
3724 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3726 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3727 likely
? "bnel" : "bne",
3736 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3737 likely
? "blezl" : "blez",
3743 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3744 likely
? "bgezl" : "bgez",
3748 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3749 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3750 likely
? "beql" : "beq",
3757 maxnum
= 0x7fffffff;
3758 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3765 if (imm_expr
.X_op
== O_constant
3766 && imm_expr
.X_add_number
>= maxnum
3767 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3769 if (imm_expr
.X_op
!= O_constant
)
3770 as_bad (_("Unsupported large constant"));
3771 imm_expr
.X_add_number
++;
3775 if (mask
== M_BLTL_I
)
3777 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3779 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3780 likely
? "bltzl" : "bltz",
3784 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3786 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3787 likely
? "blezl" : "blez",
3791 set_at (&icnt
, sreg
, 0);
3792 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3793 likely
? "bnel" : "bne",
3802 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3803 likely
? "beql" : "beq",
3809 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3811 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3812 likely
? "beql" : "beq",
3820 || (mips_opts
.isa
< 3
3821 && imm_expr
.X_op
== O_constant
3822 && imm_expr
.X_add_number
== 0xffffffff))
3824 if (imm_expr
.X_op
!= O_constant
)
3825 as_bad (_("Unsupported large constant"));
3826 imm_expr
.X_add_number
++;
3830 if (mask
== M_BLTUL_I
)
3832 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3834 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3836 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3837 likely
? "beql" : "beq",
3841 set_at (&icnt
, sreg
, 1);
3842 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3843 likely
? "bnel" : "bne",
3852 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3853 likely
? "bltzl" : "bltz",
3859 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3860 likely
? "bgtzl" : "bgtz",
3864 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3865 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3866 likely
? "bnel" : "bne",
3877 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3878 likely
? "bnel" : "bne",
3882 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3884 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3885 likely
? "bnel" : "bne",
3901 as_warn (_("Divide by zero."));
3903 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3905 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3909 mips_emit_delays (true);
3910 ++mips_opts
.noreorder
;
3911 mips_any_noreorder
= 1;
3914 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3915 macro_build ((char *) NULL
, &icnt
, NULL
,
3916 dbl
? "ddiv" : "div",
3917 "z,s,t", sreg
, treg
);
3921 expr1
.X_add_number
= 8;
3922 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3923 macro_build ((char *) NULL
, &icnt
, NULL
,
3924 dbl
? "ddiv" : "div",
3925 "z,s,t", sreg
, treg
);
3926 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3928 expr1
.X_add_number
= -1;
3929 macro_build ((char *) NULL
, &icnt
, &expr1
,
3930 dbl
? "daddiu" : "addiu",
3931 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3932 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3933 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3936 expr1
.X_add_number
= 1;
3937 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3938 (int) BFD_RELOC_LO16
);
3939 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3944 expr1
.X_add_number
= 0x80000000;
3945 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3946 (int) BFD_RELOC_HI16
);
3950 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3951 /* We want to close the noreorder block as soon as possible, so
3952 that later insns are available for delay slot filling. */
3953 --mips_opts
.noreorder
;
3957 expr1
.X_add_number
= 8;
3958 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3959 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3961 /* We want to close the noreorder block as soon as possible, so
3962 that later insns are available for delay slot filling. */
3963 --mips_opts
.noreorder
;
3965 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3967 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4006 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4008 as_warn (_("Divide by zero."));
4010 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4012 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4015 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4017 if (strcmp (s2
, "mflo") == 0)
4018 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4021 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4024 if (imm_expr
.X_op
== O_constant
4025 && imm_expr
.X_add_number
== -1
4026 && s
[strlen (s
) - 1] != 'u')
4028 if (strcmp (s2
, "mflo") == 0)
4031 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4034 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4038 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4042 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4043 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4044 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4063 mips_emit_delays (true);
4064 ++mips_opts
.noreorder
;
4065 mips_any_noreorder
= 1;
4068 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4069 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4070 /* We want to close the noreorder block as soon as possible, so
4071 that later insns are available for delay slot filling. */
4072 --mips_opts
.noreorder
;
4076 expr1
.X_add_number
= 8;
4077 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4078 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4080 /* We want to close the noreorder block as soon as possible, so
4081 that later insns are available for delay slot filling. */
4082 --mips_opts
.noreorder
;
4083 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4085 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4091 /* Load the address of a symbol into a register. If breg is not
4092 zero, we then add a base register to it. */
4094 /* When generating embedded PIC code, we permit expressions of
4097 where bar is an address in the .text section. These are used
4098 when getting the addresses of functions. We don't permit
4099 X_add_number to be non-zero, because if the symbol is
4100 external the relaxing code needs to know that any addend is
4101 purely the offset to X_op_symbol. */
4102 if (mips_pic
== EMBEDDED_PIC
4103 && offset_expr
.X_op
== O_subtract
4104 && now_seg
== text_section
4105 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4106 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4107 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4109 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4113 && offset_expr
.X_add_number
== 0)
4115 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4116 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4117 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4118 ((bfd_arch_bits_per_address (stdoutput
) == 32
4119 || mips_opts
.isa
< 3)
4120 ? "addiu" : "daddiu"),
4121 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4125 if (offset_expr
.X_op
!= O_symbol
4126 && offset_expr
.X_op
!= O_constant
)
4128 as_bad (_("expression too complex"));
4129 offset_expr
.X_op
= O_constant
;
4143 if (offset_expr
.X_op
== O_constant
)
4144 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4145 else if (mips_pic
== NO_PIC
)
4147 /* If this is a reference to an GP relative symbol, we want
4148 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4150 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4151 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4152 If we have a constant, we need two instructions anyhow,
4153 so we may as well always use the latter form. */
4154 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4155 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4161 ((bfd_arch_bits_per_address (stdoutput
) == 32
4162 || mips_opts
.isa
< 3)
4163 ? "addiu" : "daddiu"),
4164 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4165 p
= frag_var (rs_machine_dependent
, 8, 0,
4166 RELAX_ENCODE (4, 8, 0, 4, 0,
4167 mips_opts
.warn_about_macros
),
4168 offset_expr
.X_add_symbol
, (offsetT
) 0,
4171 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4174 macro_build (p
, &icnt
, &offset_expr
,
4175 ((bfd_arch_bits_per_address (stdoutput
) == 32
4176 || mips_opts
.isa
< 3)
4177 ? "addiu" : "daddiu"),
4178 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4180 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4182 /* If this is a reference to an external symbol, and there
4183 is no constant, we want
4184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4185 For a local symbol, we want
4186 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4188 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4190 If we have a small constant, and this is a reference to
4191 an external symbol, we want
4192 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4194 addiu $tempreg,$tempreg,<constant>
4195 For a local symbol, we want the same instruction
4196 sequence, but we output a BFD_RELOC_LO16 reloc on the
4199 If we have a large constant, and this is a reference to
4200 an external symbol, we want
4201 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4202 lui $at,<hiconstant>
4203 addiu $at,$at,<loconstant>
4204 addu $tempreg,$tempreg,$at
4205 For a local symbol, we want the same instruction
4206 sequence, but we output a BFD_RELOC_LO16 reloc on the
4207 addiu instruction. */
4208 expr1
.X_add_number
= offset_expr
.X_add_number
;
4209 offset_expr
.X_add_number
= 0;
4211 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4213 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4214 if (expr1
.X_add_number
== 0)
4222 /* We're going to put in an addu instruction using
4223 tempreg, so we may as well insert the nop right
4225 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4229 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4230 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4232 ? mips_opts
.warn_about_macros
4234 offset_expr
.X_add_symbol
, (offsetT
) 0,
4238 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4241 macro_build (p
, &icnt
, &expr1
,
4242 ((bfd_arch_bits_per_address (stdoutput
) == 32
4243 || mips_opts
.isa
< 3)
4244 ? "addiu" : "daddiu"),
4245 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4246 /* FIXME: If breg == 0, and the next instruction uses
4247 $tempreg, then if this variant case is used an extra
4248 nop will be generated. */
4250 else if (expr1
.X_add_number
>= -0x8000
4251 && expr1
.X_add_number
< 0x8000)
4253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4255 macro_build ((char *) NULL
, &icnt
, &expr1
,
4256 ((bfd_arch_bits_per_address (stdoutput
) == 32
4257 || mips_opts
.isa
< 3)
4258 ? "addiu" : "daddiu"),
4259 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4260 (void) frag_var (rs_machine_dependent
, 0, 0,
4261 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4262 offset_expr
.X_add_symbol
, (offsetT
) 0,
4269 /* If we are going to add in a base register, and the
4270 target register and the base register are the same,
4271 then we are using AT as a temporary register. Since
4272 we want to load the constant into AT, we add our
4273 current AT (from the global offset table) and the
4274 register into the register now, and pretend we were
4275 not using a base register. */
4280 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4282 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4283 ((bfd_arch_bits_per_address (stdoutput
) == 32
4284 || mips_opts
.isa
< 3)
4285 ? "addu" : "daddu"),
4286 "d,v,t", treg
, AT
, breg
);
4292 /* Set mips_optimize around the lui instruction to avoid
4293 inserting an unnecessary nop after the lw. */
4294 hold_mips_optimize
= mips_optimize
;
4296 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4297 mips_optimize
= hold_mips_optimize
;
4299 macro_build ((char *) NULL
, &icnt
, &expr1
,
4300 ((bfd_arch_bits_per_address (stdoutput
) == 32
4301 || mips_opts
.isa
< 3)
4302 ? "addiu" : "daddiu"),
4303 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4305 ((bfd_arch_bits_per_address (stdoutput
) == 32
4306 || mips_opts
.isa
< 3)
4307 ? "addu" : "daddu"),
4308 "d,v,t", tempreg
, tempreg
, AT
);
4309 (void) frag_var (rs_machine_dependent
, 0, 0,
4310 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4311 offset_expr
.X_add_symbol
, (offsetT
) 0,
4316 else if (mips_pic
== SVR4_PIC
)
4320 /* This is the large GOT case. If this is a reference to an
4321 external symbol, and there is no constant, we want
4322 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4323 addu $tempreg,$tempreg,$gp
4324 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4325 For a local symbol, we want
4326 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4328 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4330 If we have a small constant, and this is a reference to
4331 an external symbol, we want
4332 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4333 addu $tempreg,$tempreg,$gp
4334 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4336 addiu $tempreg,$tempreg,<constant>
4337 For a local symbol, we want
4338 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4340 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4342 If we have a large constant, and this is a reference to
4343 an external symbol, we want
4344 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4345 addu $tempreg,$tempreg,$gp
4346 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4347 lui $at,<hiconstant>
4348 addiu $at,$at,<loconstant>
4349 addu $tempreg,$tempreg,$at
4350 For a local symbol, we want
4351 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4352 lui $at,<hiconstant>
4353 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4354 addu $tempreg,$tempreg,$at
4356 expr1
.X_add_number
= offset_expr
.X_add_number
;
4357 offset_expr
.X_add_number
= 0;
4359 if (reg_needs_delay (GP
))
4363 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4364 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4365 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4366 ((bfd_arch_bits_per_address (stdoutput
) == 32
4367 || mips_opts
.isa
< 3)
4368 ? "addu" : "daddu"),
4369 "d,v,t", tempreg
, tempreg
, GP
);
4370 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4372 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4374 if (expr1
.X_add_number
== 0)
4382 /* We're going to put in an addu instruction using
4383 tempreg, so we may as well insert the nop right
4385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4390 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4391 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4394 ? mips_opts
.warn_about_macros
4396 offset_expr
.X_add_symbol
, (offsetT
) 0,
4399 else if (expr1
.X_add_number
>= -0x8000
4400 && expr1
.X_add_number
< 0x8000)
4402 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4404 macro_build ((char *) NULL
, &icnt
, &expr1
,
4405 ((bfd_arch_bits_per_address (stdoutput
) == 32
4406 || mips_opts
.isa
< 3)
4407 ? "addiu" : "daddiu"),
4408 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4410 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4411 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4413 ? mips_opts
.warn_about_macros
4415 offset_expr
.X_add_symbol
, (offsetT
) 0,
4422 /* If we are going to add in a base register, and the
4423 target register and the base register are the same,
4424 then we are using AT as a temporary register. Since
4425 we want to load the constant into AT, we add our
4426 current AT (from the global offset table) and the
4427 register into the register now, and pretend we were
4428 not using a base register. */
4436 assert (tempreg
== AT
);
4437 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4439 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4440 ((bfd_arch_bits_per_address (stdoutput
) == 32
4441 || mips_opts
.isa
< 3)
4442 ? "addu" : "daddu"),
4443 "d,v,t", treg
, AT
, breg
);
4448 /* Set mips_optimize around the lui instruction to avoid
4449 inserting an unnecessary nop after the lw. */
4450 hold_mips_optimize
= mips_optimize
;
4452 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4453 mips_optimize
= hold_mips_optimize
;
4455 macro_build ((char *) NULL
, &icnt
, &expr1
,
4456 ((bfd_arch_bits_per_address (stdoutput
) == 32
4457 || mips_opts
.isa
< 3)
4458 ? "addiu" : "daddiu"),
4459 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4460 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4461 ((bfd_arch_bits_per_address (stdoutput
) == 32
4462 || mips_opts
.isa
< 3)
4463 ? "addu" : "daddu"),
4464 "d,v,t", dreg
, dreg
, AT
);
4466 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4467 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4470 ? mips_opts
.warn_about_macros
4472 offset_expr
.X_add_symbol
, (offsetT
) 0,
4480 /* This is needed because this instruction uses $gp, but
4481 the first instruction on the main stream does not. */
4482 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4485 macro_build (p
, &icnt
, &offset_expr
,
4487 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4489 if (expr1
.X_add_number
>= -0x8000
4490 && expr1
.X_add_number
< 0x8000)
4492 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4494 macro_build (p
, &icnt
, &expr1
,
4495 ((bfd_arch_bits_per_address (stdoutput
) == 32
4496 || mips_opts
.isa
< 3)
4497 ? "addiu" : "daddiu"),
4498 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4499 /* FIXME: If add_number is 0, and there was no base
4500 register, the external symbol case ended with a load,
4501 so if the symbol turns out to not be external, and
4502 the next instruction uses tempreg, an unnecessary nop
4503 will be inserted. */
4509 /* We must add in the base register now, as in the
4510 external symbol case. */
4511 assert (tempreg
== AT
);
4512 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4514 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4515 ((bfd_arch_bits_per_address (stdoutput
) == 32
4516 || mips_opts
.isa
< 3)
4517 ? "addu" : "daddu"),
4518 "d,v,t", treg
, AT
, breg
);
4521 /* We set breg to 0 because we have arranged to add
4522 it in in both cases. */
4526 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4528 macro_build (p
, &icnt
, &expr1
,
4529 ((bfd_arch_bits_per_address (stdoutput
) == 32
4530 || mips_opts
.isa
< 3)
4531 ? "addiu" : "daddiu"),
4532 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4534 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4535 ((bfd_arch_bits_per_address (stdoutput
) == 32
4536 || mips_opts
.isa
< 3)
4537 ? "addu" : "daddu"),
4538 "d,v,t", tempreg
, tempreg
, AT
);
4542 else if (mips_pic
== EMBEDDED_PIC
)
4545 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4547 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4548 ((bfd_arch_bits_per_address (stdoutput
) == 32
4549 || mips_opts
.isa
< 3)
4550 ? "addiu" : "daddiu"),
4551 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4557 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4558 ((bfd_arch_bits_per_address (stdoutput
) == 32
4559 || mips_opts
.isa
< 3)
4560 ? "addu" : "daddu"),
4561 "d,v,t", treg
, tempreg
, breg
);
4569 /* The j instruction may not be used in PIC code, since it
4570 requires an absolute address. We convert it to a b
4572 if (mips_pic
== NO_PIC
)
4573 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4575 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4578 /* The jal instructions must be handled as macros because when
4579 generating PIC code they expand to multi-instruction
4580 sequences. Normally they are simple instructions. */
4585 if (mips_pic
== NO_PIC
4586 || mips_pic
== EMBEDDED_PIC
)
4587 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4589 else if (mips_pic
== SVR4_PIC
)
4591 if (sreg
!= PIC_CALL_REG
)
4592 as_warn (_("MIPS PIC call to register other than $25"));
4594 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4596 if (mips_cprestore_offset
< 0)
4597 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4600 expr1
.X_add_number
= mips_cprestore_offset
;
4601 macro_build ((char *) NULL
, &icnt
, &expr1
,
4602 ((bfd_arch_bits_per_address (stdoutput
) == 32
4603 || mips_opts
.isa
< 3)
4605 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4614 if (mips_pic
== NO_PIC
)
4615 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4616 else if (mips_pic
== SVR4_PIC
)
4618 /* If this is a reference to an external symbol, and we are
4619 using a small GOT, we want
4620 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4624 lw $gp,cprestore($sp)
4625 The cprestore value is set using the .cprestore
4626 pseudo-op. If we are using a big GOT, we want
4627 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4629 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4633 lw $gp,cprestore($sp)
4634 If the symbol is not external, we want
4635 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4637 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4640 lw $gp,cprestore($sp) */
4644 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4645 ((bfd_arch_bits_per_address (stdoutput
) == 32
4646 || mips_opts
.isa
< 3)
4648 "t,o(b)", PIC_CALL_REG
,
4649 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4652 p
= frag_var (rs_machine_dependent
, 4, 0,
4653 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4654 offset_expr
.X_add_symbol
, (offsetT
) 0,
4661 if (reg_needs_delay (GP
))
4665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4666 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4667 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4668 ((bfd_arch_bits_per_address (stdoutput
) == 32
4669 || mips_opts
.isa
< 3)
4670 ? "addu" : "daddu"),
4671 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4672 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4673 ((bfd_arch_bits_per_address (stdoutput
) == 32
4674 || mips_opts
.isa
< 3)
4676 "t,o(b)", PIC_CALL_REG
,
4677 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4678 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4680 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4681 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4683 offset_expr
.X_add_symbol
, (offsetT
) 0,
4687 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4690 macro_build (p
, &icnt
, &offset_expr
,
4691 ((bfd_arch_bits_per_address (stdoutput
) == 32
4692 || mips_opts
.isa
< 3)
4694 "t,o(b)", PIC_CALL_REG
,
4695 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4697 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4700 macro_build (p
, &icnt
, &offset_expr
,
4701 ((bfd_arch_bits_per_address (stdoutput
) == 32
4702 || mips_opts
.isa
< 3)
4703 ? "addiu" : "daddiu"),
4704 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4705 (int) BFD_RELOC_LO16
);
4706 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4707 "jalr", "s", PIC_CALL_REG
);
4708 if (mips_cprestore_offset
< 0)
4709 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4712 if (mips_opts
.noreorder
)
4713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4715 expr1
.X_add_number
= mips_cprestore_offset
;
4716 macro_build ((char *) NULL
, &icnt
, &expr1
,
4717 ((bfd_arch_bits_per_address (stdoutput
) == 32
4718 || mips_opts
.isa
< 3)
4720 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4724 else if (mips_pic
== EMBEDDED_PIC
)
4726 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4727 /* The linker may expand the call to a longer sequence which
4728 uses $at, so we must break rather than return. */
4753 /* Itbl support may require additional care here. */
4758 /* Itbl support may require additional care here. */
4763 /* Itbl support may require additional care here. */
4768 /* Itbl support may require additional care here. */
4780 if (mips_cpu
== 4650)
4782 as_bad (_("opcode not supported on this processor"));
4786 /* Itbl support may require additional care here. */
4791 /* Itbl support may require additional care here. */
4796 /* Itbl support may require additional care here. */
4816 if (breg
== treg
|| coproc
|| lr
)
4838 /* Itbl support may require additional care here. */
4843 /* Itbl support may require additional care here. */
4848 /* Itbl support may require additional care here. */
4853 /* Itbl support may require additional care here. */
4869 if (mips_cpu
== 4650)
4871 as_bad (_("opcode not supported on this processor"));
4876 /* Itbl support may require additional care here. */
4880 /* Itbl support may require additional care here. */
4885 /* Itbl support may require additional care here. */
4897 /* Itbl support may require additional care here. */
4898 if (mask
== M_LWC1_AB
4899 || mask
== M_SWC1_AB
4900 || mask
== M_LDC1_AB
4901 || mask
== M_SDC1_AB
4910 if (offset_expr
.X_op
!= O_constant
4911 && offset_expr
.X_op
!= O_symbol
)
4913 as_bad (_("expression too complex"));
4914 offset_expr
.X_op
= O_constant
;
4917 /* A constant expression in PIC code can be handled just as it
4918 is in non PIC code. */
4919 if (mips_pic
== NO_PIC
4920 || offset_expr
.X_op
== O_constant
)
4922 /* If this is a reference to a GP relative symbol, and there
4923 is no base register, we want
4924 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4925 Otherwise, if there is no base register, we want
4926 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4927 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4928 If we have a constant, we need two instructions anyhow,
4929 so we always use the latter form.
4931 If we have a base register, and this is a reference to a
4932 GP relative symbol, we want
4933 addu $tempreg,$breg,$gp
4934 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4936 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4937 addu $tempreg,$tempreg,$breg
4938 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4939 With a constant we always use the latter case. */
4942 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4943 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4948 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4949 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4950 p
= frag_var (rs_machine_dependent
, 8, 0,
4951 RELAX_ENCODE (4, 8, 0, 4, 0,
4952 (mips_opts
.warn_about_macros
4954 && mips_opts
.noat
))),
4955 offset_expr
.X_add_symbol
, (offsetT
) 0,
4959 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4962 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4963 (int) BFD_RELOC_LO16
, tempreg
);
4967 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4968 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4974 ((bfd_arch_bits_per_address (stdoutput
) == 32
4975 || mips_opts
.isa
< 3)
4976 ? "addu" : "daddu"),
4977 "d,v,t", tempreg
, breg
, GP
);
4978 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4979 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4980 p
= frag_var (rs_machine_dependent
, 12, 0,
4981 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4982 offset_expr
.X_add_symbol
, (offsetT
) 0,
4985 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4988 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4989 ((bfd_arch_bits_per_address (stdoutput
) == 32
4990 || mips_opts
.isa
< 3)
4991 ? "addu" : "daddu"),
4992 "d,v,t", tempreg
, tempreg
, breg
);
4995 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4996 (int) BFD_RELOC_LO16
, tempreg
);
4999 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5001 /* If this is a reference to an external symbol, we want
5002 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5004 <op> $treg,0($tempreg)
5006 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5008 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5009 <op> $treg,0($tempreg)
5010 If there is a base register, we add it to $tempreg before
5011 the <op>. If there is a constant, we stick it in the
5012 <op> instruction. We don't handle constants larger than
5013 16 bits, because we have no way to load the upper 16 bits
5014 (actually, we could handle them for the subset of cases
5015 in which we are not using $at). */
5016 assert (offset_expr
.X_op
== O_symbol
);
5017 expr1
.X_add_number
= offset_expr
.X_add_number
;
5018 offset_expr
.X_add_number
= 0;
5019 if (expr1
.X_add_number
< -0x8000
5020 || expr1
.X_add_number
>= 0x8000)
5021 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5023 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5024 ((bfd_arch_bits_per_address (stdoutput
) == 32
5025 || mips_opts
.isa
< 3)
5027 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5029 p
= frag_var (rs_machine_dependent
, 4, 0,
5030 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5031 offset_expr
.X_add_symbol
, (offsetT
) 0,
5033 macro_build (p
, &icnt
, &offset_expr
,
5034 ((bfd_arch_bits_per_address (stdoutput
) == 32
5035 || mips_opts
.isa
< 3)
5036 ? "addiu" : "daddiu"),
5037 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5039 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5040 ((bfd_arch_bits_per_address (stdoutput
) == 32
5041 || mips_opts
.isa
< 3)
5042 ? "addu" : "daddu"),
5043 "d,v,t", tempreg
, tempreg
, breg
);
5044 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5045 (int) BFD_RELOC_LO16
, tempreg
);
5047 else if (mips_pic
== SVR4_PIC
)
5051 /* If this is a reference to an external symbol, we want
5052 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5053 addu $tempreg,$tempreg,$gp
5054 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5055 <op> $treg,0($tempreg)
5057 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5059 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5060 <op> $treg,0($tempreg)
5061 If there is a base register, we add it to $tempreg before
5062 the <op>. If there is a constant, we stick it in the
5063 <op> instruction. We don't handle constants larger than
5064 16 bits, because we have no way to load the upper 16 bits
5065 (actually, we could handle them for the subset of cases
5066 in which we are not using $at). */
5067 assert (offset_expr
.X_op
== O_symbol
);
5068 expr1
.X_add_number
= offset_expr
.X_add_number
;
5069 offset_expr
.X_add_number
= 0;
5070 if (expr1
.X_add_number
< -0x8000
5071 || expr1
.X_add_number
>= 0x8000)
5072 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5073 if (reg_needs_delay (GP
))
5078 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5079 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5081 ((bfd_arch_bits_per_address (stdoutput
) == 32
5082 || mips_opts
.isa
< 3)
5083 ? "addu" : "daddu"),
5084 "d,v,t", tempreg
, tempreg
, GP
);
5085 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5086 ((bfd_arch_bits_per_address (stdoutput
) == 32
5087 || mips_opts
.isa
< 3)
5089 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5091 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5092 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5093 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5096 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5099 macro_build (p
, &icnt
, &offset_expr
,
5100 ((bfd_arch_bits_per_address (stdoutput
) == 32
5101 || mips_opts
.isa
< 3)
5103 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5105 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5107 macro_build (p
, &icnt
, &offset_expr
,
5108 ((bfd_arch_bits_per_address (stdoutput
) == 32
5109 || mips_opts
.isa
< 3)
5110 ? "addiu" : "daddiu"),
5111 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5113 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5114 ((bfd_arch_bits_per_address (stdoutput
) == 32
5115 || mips_opts
.isa
< 3)
5116 ? "addu" : "daddu"),
5117 "d,v,t", tempreg
, tempreg
, breg
);
5118 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5119 (int) BFD_RELOC_LO16
, tempreg
);
5121 else if (mips_pic
== EMBEDDED_PIC
)
5123 /* If there is no base register, we want
5124 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5125 If there is a base register, we want
5126 addu $tempreg,$breg,$gp
5127 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5129 assert (offset_expr
.X_op
== O_symbol
);
5132 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5133 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5138 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5139 ((bfd_arch_bits_per_address (stdoutput
) == 32
5140 || mips_opts
.isa
< 3)
5141 ? "addu" : "daddu"),
5142 "d,v,t", tempreg
, breg
, GP
);
5143 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5144 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5157 load_register (&icnt
, treg
, &imm_expr
, 0);
5161 load_register (&icnt
, treg
, &imm_expr
, 1);
5165 if (imm_expr
.X_op
== O_constant
)
5167 load_register (&icnt
, AT
, &imm_expr
, 0);
5168 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5169 "mtc1", "t,G", AT
, treg
);
5174 assert (offset_expr
.X_op
== O_symbol
5175 && strcmp (segment_name (S_GET_SEGMENT
5176 (offset_expr
.X_add_symbol
)),
5178 && offset_expr
.X_add_number
== 0);
5179 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5180 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5185 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5186 the entire value, and in mips1 mode it is the high order 32
5187 bits of the value and the low order 32 bits are either zero
5188 or in offset_expr. */
5189 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5191 if (mips_opts
.isa
>= 3)
5192 load_register (&icnt
, treg
, &imm_expr
, 1);
5197 if (target_big_endian
)
5209 load_register (&icnt
, hreg
, &imm_expr
, 0);
5212 if (offset_expr
.X_op
== O_absent
)
5213 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5217 assert (offset_expr
.X_op
== O_constant
);
5218 load_register (&icnt
, lreg
, &offset_expr
, 0);
5225 /* We know that sym is in the .rdata section. First we get the
5226 upper 16 bits of the address. */
5227 if (mips_pic
== NO_PIC
)
5229 /* FIXME: This won't work for a 64 bit address. */
5230 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5232 else if (mips_pic
== SVR4_PIC
)
5234 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5235 ((bfd_arch_bits_per_address (stdoutput
) == 32
5236 || mips_opts
.isa
< 3)
5238 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5240 else if (mips_pic
== EMBEDDED_PIC
)
5242 /* For embedded PIC we pick up the entire address off $gp in
5243 a single instruction. */
5244 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5245 ((bfd_arch_bits_per_address (stdoutput
) == 32
5246 || mips_opts
.isa
< 3)
5247 ? "addiu" : "daddiu"),
5248 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5249 offset_expr
.X_op
= O_constant
;
5250 offset_expr
.X_add_number
= 0;
5255 /* Now we load the register(s). */
5256 if (mips_opts
.isa
>= 3)
5257 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5258 treg
, (int) BFD_RELOC_LO16
, AT
);
5261 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5262 treg
, (int) BFD_RELOC_LO16
, AT
);
5265 /* FIXME: How in the world do we deal with the possible
5267 offset_expr
.X_add_number
+= 4;
5268 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5269 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5273 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5274 does not become a variant frag. */
5275 frag_wane (frag_now
);
5281 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5282 the entire value, and in mips1 mode it is the high order 32
5283 bits of the value and the low order 32 bits are either zero
5284 or in offset_expr. */
5285 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5287 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5288 if (mips_opts
.isa
>= 3)
5289 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5290 "dmtc1", "t,S", AT
, treg
);
5293 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5294 "mtc1", "t,G", AT
, treg
+ 1);
5295 if (offset_expr
.X_op
== O_absent
)
5296 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5297 "mtc1", "t,G", 0, treg
);
5300 assert (offset_expr
.X_op
== O_constant
);
5301 load_register (&icnt
, AT
, &offset_expr
, 0);
5302 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5303 "mtc1", "t,G", AT
, treg
);
5309 assert (offset_expr
.X_op
== O_symbol
5310 && offset_expr
.X_add_number
== 0);
5311 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5312 if (strcmp (s
, ".lit8") == 0)
5314 if (mips_opts
.isa
>= 2)
5316 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5317 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5321 r
= BFD_RELOC_MIPS_LITERAL
;
5326 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5327 if (mips_pic
== SVR4_PIC
)
5328 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5329 ((bfd_arch_bits_per_address (stdoutput
) == 32
5330 || mips_opts
.isa
< 3)
5332 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5335 /* FIXME: This won't work for a 64 bit address. */
5336 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5339 if (mips_opts
.isa
>= 2)
5341 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5342 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5344 /* To avoid confusion in tc_gen_reloc, we must ensure
5345 that this does not become a variant frag. */
5346 frag_wane (frag_now
);
5357 if (mips_cpu
== 4650)
5359 as_bad (_("opcode not supported on this processor"));
5362 /* Even on a big endian machine $fn comes before $fn+1. We have
5363 to adjust when loading from memory. */
5366 assert (mips_opts
.isa
< 2);
5367 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5368 target_big_endian
? treg
+ 1 : treg
,
5370 /* FIXME: A possible overflow which I don't know how to deal
5372 offset_expr
.X_add_number
+= 4;
5373 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5374 target_big_endian
? treg
: treg
+ 1,
5377 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5378 does not become a variant frag. */
5379 frag_wane (frag_now
);
5388 * The MIPS assembler seems to check for X_add_number not
5389 * being double aligned and generating:
5392 * addiu at,at,%lo(foo+1)
5395 * But, the resulting address is the same after relocation so why
5396 * generate the extra instruction?
5398 if (mips_cpu
== 4650)
5400 as_bad (_("opcode not supported on this processor"));
5403 /* Itbl support may require additional care here. */
5405 if (mips_opts
.isa
>= 2)
5416 if (mips_cpu
== 4650)
5418 as_bad (_("opcode not supported on this processor"));
5422 if (mips_opts
.isa
>= 2)
5430 /* Itbl support may require additional care here. */
5435 if (mips_opts
.isa
>= 3)
5446 if (mips_opts
.isa
>= 3)
5456 if (offset_expr
.X_op
!= O_symbol
5457 && offset_expr
.X_op
!= O_constant
)
5459 as_bad (_("expression too complex"));
5460 offset_expr
.X_op
= O_constant
;
5463 /* Even on a big endian machine $fn comes before $fn+1. We have
5464 to adjust when loading from memory. We set coproc if we must
5465 load $fn+1 first. */
5466 /* Itbl support may require additional care here. */
5467 if (! target_big_endian
)
5470 if (mips_pic
== NO_PIC
5471 || offset_expr
.X_op
== O_constant
)
5473 /* If this is a reference to a GP relative symbol, we want
5474 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5475 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5476 If we have a base register, we use this
5478 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5479 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5480 If this is not a GP relative symbol, we want
5481 lui $at,<sym> (BFD_RELOC_HI16_S)
5482 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5483 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5484 If there is a base register, we add it to $at after the
5485 lui instruction. If there is a constant, we always use
5487 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5488 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5508 ((bfd_arch_bits_per_address (stdoutput
) == 32
5509 || mips_opts
.isa
< 3)
5510 ? "addu" : "daddu"),
5511 "d,v,t", AT
, breg
, GP
);
5517 /* Itbl support may require additional care here. */
5518 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5519 coproc
? treg
+ 1 : treg
,
5520 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5521 offset_expr
.X_add_number
+= 4;
5523 /* Set mips_optimize to 2 to avoid inserting an
5525 hold_mips_optimize
= mips_optimize
;
5527 /* Itbl support may require additional care here. */
5528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5529 coproc
? treg
: treg
+ 1,
5530 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5531 mips_optimize
= hold_mips_optimize
;
5533 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5534 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5535 used_at
&& mips_opts
.noat
),
5536 offset_expr
.X_add_symbol
, (offsetT
) 0,
5539 /* We just generated two relocs. When tc_gen_reloc
5540 handles this case, it will skip the first reloc and
5541 handle the second. The second reloc already has an
5542 extra addend of 4, which we added above. We must
5543 subtract it out, and then subtract another 4 to make
5544 the first reloc come out right. The second reloc
5545 will come out right because we are going to add 4 to
5546 offset_expr when we build its instruction below.
5548 If we have a symbol, then we don't want to include
5549 the offset, because it will wind up being included
5550 when we generate the reloc. */
5552 if (offset_expr
.X_op
== O_constant
)
5553 offset_expr
.X_add_number
-= 8;
5556 offset_expr
.X_add_number
= -4;
5557 offset_expr
.X_op
= O_constant
;
5560 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5565 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5566 ((bfd_arch_bits_per_address (stdoutput
) == 32
5567 || mips_opts
.isa
< 3)
5568 ? "addu" : "daddu"),
5569 "d,v,t", AT
, breg
, AT
);
5573 /* Itbl support may require additional care here. */
5574 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5575 coproc
? treg
+ 1 : treg
,
5576 (int) BFD_RELOC_LO16
, AT
);
5579 /* FIXME: How do we handle overflow here? */
5580 offset_expr
.X_add_number
+= 4;
5581 /* Itbl support may require additional care here. */
5582 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5583 coproc
? treg
: treg
+ 1,
5584 (int) BFD_RELOC_LO16
, AT
);
5586 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5590 /* If this is a reference to an external symbol, we want
5591 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5596 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5598 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5599 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5600 If there is a base register we add it to $at before the
5601 lwc1 instructions. If there is a constant we include it
5602 in the lwc1 instructions. */
5604 expr1
.X_add_number
= offset_expr
.X_add_number
;
5605 offset_expr
.X_add_number
= 0;
5606 if (expr1
.X_add_number
< -0x8000
5607 || expr1
.X_add_number
>= 0x8000 - 4)
5608 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5613 frag_grow (24 + off
);
5614 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5615 ((bfd_arch_bits_per_address (stdoutput
) == 32
5616 || mips_opts
.isa
< 3)
5618 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5619 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5621 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5622 ((bfd_arch_bits_per_address (stdoutput
) == 32
5623 || mips_opts
.isa
< 3)
5624 ? "addu" : "daddu"),
5625 "d,v,t", AT
, breg
, AT
);
5626 /* Itbl support may require additional care here. */
5627 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5628 coproc
? treg
+ 1 : treg
,
5629 (int) BFD_RELOC_LO16
, AT
);
5630 expr1
.X_add_number
+= 4;
5632 /* Set mips_optimize to 2 to avoid inserting an undesired
5634 hold_mips_optimize
= mips_optimize
;
5636 /* Itbl support may require additional care here. */
5637 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5638 coproc
? treg
: treg
+ 1,
5639 (int) BFD_RELOC_LO16
, AT
);
5640 mips_optimize
= hold_mips_optimize
;
5642 (void) frag_var (rs_machine_dependent
, 0, 0,
5643 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5644 offset_expr
.X_add_symbol
, (offsetT
) 0,
5647 else if (mips_pic
== SVR4_PIC
)
5651 /* If this is a reference to an external symbol, we want
5652 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5654 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5659 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5661 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5662 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5663 If there is a base register we add it to $at before the
5664 lwc1 instructions. If there is a constant we include it
5665 in the lwc1 instructions. */
5667 expr1
.X_add_number
= offset_expr
.X_add_number
;
5668 offset_expr
.X_add_number
= 0;
5669 if (expr1
.X_add_number
< -0x8000
5670 || expr1
.X_add_number
>= 0x8000 - 4)
5671 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5672 if (reg_needs_delay (GP
))
5681 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5682 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5684 ((bfd_arch_bits_per_address (stdoutput
) == 32
5685 || mips_opts
.isa
< 3)
5686 ? "addu" : "daddu"),
5687 "d,v,t", AT
, AT
, GP
);
5688 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5689 ((bfd_arch_bits_per_address (stdoutput
) == 32
5690 || mips_opts
.isa
< 3)
5692 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5693 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5695 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5696 ((bfd_arch_bits_per_address (stdoutput
) == 32
5697 || mips_opts
.isa
< 3)
5698 ? "addu" : "daddu"),
5699 "d,v,t", AT
, breg
, AT
);
5700 /* Itbl support may require additional care here. */
5701 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5702 coproc
? treg
+ 1 : treg
,
5703 (int) BFD_RELOC_LO16
, AT
);
5704 expr1
.X_add_number
+= 4;
5706 /* Set mips_optimize to 2 to avoid inserting an undesired
5708 hold_mips_optimize
= mips_optimize
;
5710 /* Itbl support may require additional care here. */
5711 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5712 coproc
? treg
: treg
+ 1,
5713 (int) BFD_RELOC_LO16
, AT
);
5714 mips_optimize
= hold_mips_optimize
;
5715 expr1
.X_add_number
-= 4;
5717 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5718 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5719 8 + gpdel
+ off
, 1, 0),
5720 offset_expr
.X_add_symbol
, (offsetT
) 0,
5724 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5727 macro_build (p
, &icnt
, &offset_expr
,
5728 ((bfd_arch_bits_per_address (stdoutput
) == 32
5729 || mips_opts
.isa
< 3)
5731 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5733 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5737 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5738 ((bfd_arch_bits_per_address (stdoutput
) == 32
5739 || mips_opts
.isa
< 3)
5740 ? "addu" : "daddu"),
5741 "d,v,t", AT
, breg
, AT
);
5744 /* Itbl support may require additional care here. */
5745 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5746 coproc
? treg
+ 1 : treg
,
5747 (int) BFD_RELOC_LO16
, AT
);
5749 expr1
.X_add_number
+= 4;
5751 /* Set mips_optimize to 2 to avoid inserting an undesired
5753 hold_mips_optimize
= mips_optimize
;
5755 /* Itbl support may require additional care here. */
5756 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5757 coproc
? treg
: treg
+ 1,
5758 (int) BFD_RELOC_LO16
, AT
);
5759 mips_optimize
= hold_mips_optimize
;
5761 else if (mips_pic
== EMBEDDED_PIC
)
5763 /* If there is no base register, we use
5764 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5765 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5766 If we have a base register, we use
5768 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5769 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5779 ((bfd_arch_bits_per_address (stdoutput
) == 32
5780 || mips_opts
.isa
< 3)
5781 ? "addu" : "daddu"),
5782 "d,v,t", AT
, breg
, GP
);
5787 /* Itbl support may require additional care here. */
5788 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5789 coproc
? treg
+ 1 : treg
,
5790 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5791 offset_expr
.X_add_number
+= 4;
5792 /* Itbl support may require additional care here. */
5793 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5794 coproc
? treg
: treg
+ 1,
5795 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5811 assert (bfd_arch_bits_per_address (stdoutput
) == 32 || mips_opts
.isa
< 3);
5812 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5813 (int) BFD_RELOC_LO16
, breg
);
5814 offset_expr
.X_add_number
+= 4;
5815 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5816 (int) BFD_RELOC_LO16
, breg
);
5819 /* New code added to support COPZ instructions.
5820 This code builds table entries out of the macros in mip_opcodes.
5821 R4000 uses interlocks to handle coproc delays.
5822 Other chips (like the R3000) require nops to be inserted for delays.
5824 FIXME: Currently, we require that the user handle delays.
5825 In order to fill delay slots for non-interlocked chips,
5826 we must have a way to specify delays based on the coprocessor.
5827 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5828 What are the side-effects of the cop instruction?
5829 What cache support might we have and what are its effects?
5830 Both coprocessor & memory require delays. how long???
5831 What registers are read/set/modified?
5833 If an itbl is provided to interpret cop instructions,
5834 this knowledge can be encoded in the itbl spec. */
5848 /* For now we just do C (same as Cz). The parameter will be
5849 stored in insn_opcode by mips_ip. */
5850 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5854 #ifdef LOSING_COMPILER
5856 /* Try and see if this is a new itbl instruction.
5857 This code builds table entries out of the macros in mip_opcodes.
5858 FIXME: For now we just assemble the expression and pass it's
5859 value along as a 32-bit immediate.
5860 We may want to have the assembler assemble this value,
5861 so that we gain the assembler's knowledge of delay slots,
5863 Would it be more efficient to use mask (id) here? */
5864 if (itbl_have_entries
5865 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5867 s
= ip
->insn_mo
->name
;
5869 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5870 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5877 as_warn (_("Macro used $at after \".set noat\""));
5882 struct mips_cl_insn
*ip
;
5884 register int treg
, sreg
, dreg
, breg
;
5900 bfd_reloc_code_real_type r
;
5903 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5904 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5905 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5906 mask
= ip
->insn_mo
->mask
;
5908 expr1
.X_op
= O_constant
;
5909 expr1
.X_op_symbol
= NULL
;
5910 expr1
.X_add_symbol
= NULL
;
5911 expr1
.X_add_number
= 1;
5915 #endif /* LOSING_COMPILER */
5920 macro_build ((char *) NULL
, &icnt
, NULL
,
5921 dbl
? "dmultu" : "multu",
5923 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5929 /* The MIPS assembler some times generates shifts and adds. I'm
5930 not trying to be that fancy. GCC should do this for us
5932 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5933 macro_build ((char *) NULL
, &icnt
, NULL
,
5934 dbl
? "dmult" : "mult",
5936 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5949 mips_emit_delays (true);
5950 ++mips_opts
.noreorder
;
5951 mips_any_noreorder
= 1;
5953 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5954 macro_build ((char *) NULL
, &icnt
, NULL
,
5955 dbl
? "dmult" : "mult",
5956 "s,t", sreg
, imm
? AT
: treg
);
5957 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5958 macro_build ((char *) NULL
, &icnt
, NULL
,
5959 dbl
? "dsra32" : "sra",
5960 "d,w,<", dreg
, dreg
, 31);
5961 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5963 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5966 expr1
.X_add_number
= 8;
5967 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5968 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5969 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5971 --mips_opts
.noreorder
;
5972 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5985 mips_emit_delays (true);
5986 ++mips_opts
.noreorder
;
5987 mips_any_noreorder
= 1;
5989 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5990 macro_build ((char *) NULL
, &icnt
, NULL
,
5991 dbl
? "dmultu" : "multu",
5992 "s,t", sreg
, imm
? AT
: treg
);
5993 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5994 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5996 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5999 expr1
.X_add_number
= 8;
6000 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6001 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6002 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6004 --mips_opts
.noreorder
;
6008 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6009 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6010 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6012 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6016 if (imm_expr
.X_op
!= O_constant
)
6017 as_bad (_("rotate count too large"));
6018 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6019 (int) (imm_expr
.X_add_number
& 0x1f));
6020 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6021 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6022 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6026 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6027 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6028 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6030 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6034 if (imm_expr
.X_op
!= O_constant
)
6035 as_bad (_("rotate count too large"));
6036 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6037 (int) (imm_expr
.X_add_number
& 0x1f));
6038 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6039 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6040 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6044 if (mips_cpu
== 4650)
6046 as_bad (_("opcode not supported on this processor"));
6049 assert (mips_opts
.isa
< 2);
6050 /* Even on a big endian machine $fn comes before $fn+1. We have
6051 to adjust when storing to memory. */
6052 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6053 target_big_endian
? treg
+ 1 : treg
,
6054 (int) BFD_RELOC_LO16
, breg
);
6055 offset_expr
.X_add_number
+= 4;
6056 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6057 target_big_endian
? treg
: treg
+ 1,
6058 (int) BFD_RELOC_LO16
, breg
);
6063 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6064 treg
, (int) BFD_RELOC_LO16
);
6066 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6067 sreg
, (int) BFD_RELOC_LO16
);
6070 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6072 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6073 dreg
, (int) BFD_RELOC_LO16
);
6078 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6080 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6081 sreg
, (int) BFD_RELOC_LO16
);
6086 as_warn (_("Instruction %s: result is always false"),
6088 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6091 if (imm_expr
.X_op
== O_constant
6092 && imm_expr
.X_add_number
>= 0
6093 && imm_expr
.X_add_number
< 0x10000)
6095 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6096 sreg
, (int) BFD_RELOC_LO16
);
6099 else if (imm_expr
.X_op
== O_constant
6100 && imm_expr
.X_add_number
> -0x8000
6101 && imm_expr
.X_add_number
< 0)
6103 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6104 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6105 ((bfd_arch_bits_per_address (stdoutput
) == 32
6106 || mips_opts
.isa
< 3)
6107 ? "addiu" : "daddiu"),
6108 "t,r,j", dreg
, sreg
,
6109 (int) BFD_RELOC_LO16
);
6114 load_register (&icnt
, AT
, &imm_expr
, 0);
6115 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6119 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6120 (int) BFD_RELOC_LO16
);
6125 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6131 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6132 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6133 (int) BFD_RELOC_LO16
);
6136 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6138 if (imm_expr
.X_op
== O_constant
6139 && imm_expr
.X_add_number
>= -0x8000
6140 && imm_expr
.X_add_number
< 0x8000)
6142 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6143 mask
== M_SGE_I
? "slti" : "sltiu",
6144 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6149 load_register (&icnt
, AT
, &imm_expr
, 0);
6150 macro_build ((char *) NULL
, &icnt
, NULL
,
6151 mask
== M_SGE_I
? "slt" : "sltu",
6152 "d,v,t", dreg
, sreg
, AT
);
6155 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6156 (int) BFD_RELOC_LO16
);
6161 case M_SGT
: /* sreg > treg <==> treg < sreg */
6167 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6170 case M_SGT_I
: /* sreg > I <==> I < sreg */
6176 load_register (&icnt
, AT
, &imm_expr
, 0);
6177 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6180 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6186 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6187 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6188 (int) BFD_RELOC_LO16
);
6191 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6197 load_register (&icnt
, AT
, &imm_expr
, 0);
6198 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6199 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6200 (int) BFD_RELOC_LO16
);
6204 if (imm_expr
.X_op
== O_constant
6205 && imm_expr
.X_add_number
>= -0x8000
6206 && imm_expr
.X_add_number
< 0x8000)
6208 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6209 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6212 load_register (&icnt
, AT
, &imm_expr
, 0);
6213 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6217 if (imm_expr
.X_op
== O_constant
6218 && imm_expr
.X_add_number
>= -0x8000
6219 && imm_expr
.X_add_number
< 0x8000)
6221 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6222 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6225 load_register (&icnt
, AT
, &imm_expr
, 0);
6226 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6232 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6235 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6239 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6241 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6247 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6249 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6255 as_warn (_("Instruction %s: result is always true"),
6257 macro_build ((char *) NULL
, &icnt
, &expr1
,
6258 ((bfd_arch_bits_per_address (stdoutput
) == 32
6259 || mips_opts
.isa
< 3)
6260 ? "addiu" : "daddiu"),
6261 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6264 if (imm_expr
.X_op
== O_constant
6265 && imm_expr
.X_add_number
>= 0
6266 && imm_expr
.X_add_number
< 0x10000)
6268 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6269 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6272 else if (imm_expr
.X_op
== O_constant
6273 && imm_expr
.X_add_number
> -0x8000
6274 && imm_expr
.X_add_number
< 0)
6276 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6277 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6278 ((bfd_arch_bits_per_address (stdoutput
) == 32
6279 || mips_opts
.isa
< 3)
6280 ? "addiu" : "daddiu"),
6281 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6286 load_register (&icnt
, AT
, &imm_expr
, 0);
6287 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6291 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6299 if (imm_expr
.X_op
== O_constant
6300 && imm_expr
.X_add_number
> -0x8000
6301 && imm_expr
.X_add_number
<= 0x8000)
6303 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6304 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6305 dbl
? "daddi" : "addi",
6306 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6309 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6310 macro_build ((char *) NULL
, &icnt
, NULL
,
6311 dbl
? "dsub" : "sub",
6312 "d,v,t", dreg
, sreg
, AT
);
6318 if (imm_expr
.X_op
== O_constant
6319 && imm_expr
.X_add_number
> -0x8000
6320 && imm_expr
.X_add_number
<= 0x8000)
6322 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6323 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6324 dbl
? "daddiu" : "addiu",
6325 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6328 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6329 macro_build ((char *) NULL
, &icnt
, NULL
,
6330 dbl
? "dsubu" : "subu",
6331 "d,v,t", dreg
, sreg
, AT
);
6352 load_register (&icnt
, AT
, &imm_expr
, 0);
6353 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6358 assert (mips_opts
.isa
< 2);
6359 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6360 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6363 * Is the double cfc1 instruction a bug in the mips assembler;
6364 * or is there a reason for it?
6366 mips_emit_delays (true);
6367 ++mips_opts
.noreorder
;
6368 mips_any_noreorder
= 1;
6369 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6370 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6371 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6372 expr1
.X_add_number
= 3;
6373 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6374 (int) BFD_RELOC_LO16
);
6375 expr1
.X_add_number
= 2;
6376 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6377 (int) BFD_RELOC_LO16
);
6378 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6379 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6380 macro_build ((char *) NULL
, &icnt
, NULL
,
6381 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6382 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6383 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6384 --mips_opts
.noreorder
;
6393 if (offset_expr
.X_add_number
>= 0x7fff)
6394 as_bad (_("operand overflow"));
6395 /* avoid load delay */
6396 if (! target_big_endian
)
6397 offset_expr
.X_add_number
+= 1;
6398 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6399 (int) BFD_RELOC_LO16
, breg
);
6400 if (! target_big_endian
)
6401 offset_expr
.X_add_number
-= 1;
6403 offset_expr
.X_add_number
+= 1;
6404 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6405 (int) BFD_RELOC_LO16
, breg
);
6406 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6407 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6420 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6421 as_bad (_("operand overflow"));
6422 if (! target_big_endian
)
6423 offset_expr
.X_add_number
+= off
;
6424 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6425 (int) BFD_RELOC_LO16
, breg
);
6426 if (! target_big_endian
)
6427 offset_expr
.X_add_number
-= off
;
6429 offset_expr
.X_add_number
+= off
;
6430 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6431 (int) BFD_RELOC_LO16
, breg
);
6444 load_address (&icnt
, AT
, &offset_expr
);
6446 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6447 ((bfd_arch_bits_per_address (stdoutput
) == 32
6448 || mips_opts
.isa
< 3)
6449 ? "addu" : "daddu"),
6450 "d,v,t", AT
, AT
, breg
);
6451 if (! target_big_endian
)
6452 expr1
.X_add_number
= off
;
6454 expr1
.X_add_number
= 0;
6455 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6456 (int) BFD_RELOC_LO16
, AT
);
6457 if (! target_big_endian
)
6458 expr1
.X_add_number
= 0;
6460 expr1
.X_add_number
= off
;
6461 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6462 (int) BFD_RELOC_LO16
, AT
);
6467 load_address (&icnt
, AT
, &offset_expr
);
6469 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6470 ((bfd_arch_bits_per_address (stdoutput
) == 32
6471 || mips_opts
.isa
< 3)
6472 ? "addu" : "daddu"),
6473 "d,v,t", AT
, AT
, breg
);
6474 if (target_big_endian
)
6475 expr1
.X_add_number
= 0;
6476 macro_build ((char *) NULL
, &icnt
, &expr1
,
6477 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6478 (int) BFD_RELOC_LO16
, AT
);
6479 if (target_big_endian
)
6480 expr1
.X_add_number
= 1;
6482 expr1
.X_add_number
= 0;
6483 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6484 (int) BFD_RELOC_LO16
, AT
);
6485 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6487 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6492 if (offset_expr
.X_add_number
>= 0x7fff)
6493 as_bad (_("operand overflow"));
6494 if (target_big_endian
)
6495 offset_expr
.X_add_number
+= 1;
6496 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6497 (int) BFD_RELOC_LO16
, breg
);
6498 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6499 if (target_big_endian
)
6500 offset_expr
.X_add_number
-= 1;
6502 offset_expr
.X_add_number
+= 1;
6503 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6504 (int) BFD_RELOC_LO16
, breg
);
6517 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6518 as_bad (_("operand overflow"));
6519 if (! target_big_endian
)
6520 offset_expr
.X_add_number
+= off
;
6521 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6522 (int) BFD_RELOC_LO16
, breg
);
6523 if (! target_big_endian
)
6524 offset_expr
.X_add_number
-= off
;
6526 offset_expr
.X_add_number
+= off
;
6527 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6528 (int) BFD_RELOC_LO16
, breg
);
6541 load_address (&icnt
, AT
, &offset_expr
);
6543 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6544 ((bfd_arch_bits_per_address (stdoutput
) == 32
6545 || mips_opts
.isa
< 3)
6546 ? "addu" : "daddu"),
6547 "d,v,t", AT
, AT
, breg
);
6548 if (! target_big_endian
)
6549 expr1
.X_add_number
= off
;
6551 expr1
.X_add_number
= 0;
6552 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6553 (int) BFD_RELOC_LO16
, AT
);
6554 if (! target_big_endian
)
6555 expr1
.X_add_number
= 0;
6557 expr1
.X_add_number
= off
;
6558 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6559 (int) BFD_RELOC_LO16
, AT
);
6563 load_address (&icnt
, AT
, &offset_expr
);
6565 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6566 ((bfd_arch_bits_per_address (stdoutput
) == 32
6567 || mips_opts
.isa
< 3)
6568 ? "addu" : "daddu"),
6569 "d,v,t", AT
, AT
, breg
);
6570 if (! target_big_endian
)
6571 expr1
.X_add_number
= 0;
6572 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6573 (int) BFD_RELOC_LO16
, AT
);
6574 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6576 if (! target_big_endian
)
6577 expr1
.X_add_number
= 1;
6579 expr1
.X_add_number
= 0;
6580 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6581 (int) BFD_RELOC_LO16
, AT
);
6582 if (! target_big_endian
)
6583 expr1
.X_add_number
= 0;
6585 expr1
.X_add_number
= 1;
6586 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6587 (int) BFD_RELOC_LO16
, AT
);
6588 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6590 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6595 /* FIXME: Check if this is one of the itbl macros, since they
6596 are added dynamically. */
6597 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6601 as_warn (_("Macro used $at after \".set noat\""));
6604 /* Implement macros in mips16 mode. */
6608 struct mips_cl_insn
*ip
;
6611 int xreg
, yreg
, zreg
, tmp
;
6615 const char *s
, *s2
, *s3
;
6617 mask
= ip
->insn_mo
->mask
;
6619 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6620 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6621 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6625 expr1
.X_op
= O_constant
;
6626 expr1
.X_op_symbol
= NULL
;
6627 expr1
.X_add_symbol
= NULL
;
6628 expr1
.X_add_number
= 1;
6647 mips_emit_delays (true);
6648 ++mips_opts
.noreorder
;
6649 mips_any_noreorder
= 1;
6650 macro_build ((char *) NULL
, &icnt
, NULL
,
6651 dbl
? "ddiv" : "div",
6652 "0,x,y", xreg
, yreg
);
6653 expr1
.X_add_number
= 2;
6654 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6655 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6657 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6658 since that causes an overflow. We should do that as well,
6659 but I don't see how to do the comparisons without a temporary
6661 --mips_opts
.noreorder
;
6662 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6681 mips_emit_delays (true);
6682 ++mips_opts
.noreorder
;
6683 mips_any_noreorder
= 1;
6684 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6685 expr1
.X_add_number
= 2;
6686 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6687 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6688 --mips_opts
.noreorder
;
6689 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6695 macro_build ((char *) NULL
, &icnt
, NULL
,
6696 dbl
? "dmultu" : "multu",
6698 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6706 if (imm_expr
.X_op
!= O_constant
)
6707 as_bad (_("Unsupported large constant"));
6708 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6709 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6710 dbl
? "daddiu" : "addiu",
6711 "y,x,4", yreg
, xreg
);
6715 if (imm_expr
.X_op
!= O_constant
)
6716 as_bad (_("Unsupported large constant"));
6717 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6718 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6723 if (imm_expr
.X_op
!= O_constant
)
6724 as_bad (_("Unsupported large constant"));
6725 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6726 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6749 goto do_reverse_branch
;
6753 goto do_reverse_branch
;
6765 goto do_reverse_branch
;
6776 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6778 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6805 goto do_addone_branch_i
;
6810 goto do_addone_branch_i
;
6825 goto do_addone_branch_i
;
6832 if (imm_expr
.X_op
!= O_constant
)
6833 as_bad (_("Unsupported large constant"));
6834 ++imm_expr
.X_add_number
;
6837 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6838 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6842 expr1
.X_add_number
= 0;
6843 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6845 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6846 "move", "y,X", xreg
, yreg
);
6847 expr1
.X_add_number
= 2;
6848 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6849 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6850 "neg", "x,w", xreg
, xreg
);
6854 /* For consistency checking, verify that all bits are specified either
6855 by the match/mask part of the instruction definition, or by the
6858 validate_mips_insn (opc
)
6859 const struct mips_opcode
*opc
;
6861 const char *p
= opc
->args
;
6863 unsigned long used_bits
= opc
->mask
;
6865 if ((used_bits
& opc
->match
) != opc
->match
)
6867 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6868 opc
->name
, opc
->args
);
6871 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6878 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6879 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6881 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6882 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6883 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6884 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6886 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6889 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6890 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6891 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6892 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6893 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6894 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6895 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6896 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6897 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6898 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6899 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6901 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6902 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6903 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6904 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6906 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6907 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6908 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6909 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6910 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6911 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6912 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6913 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6914 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6917 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6919 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6920 c
, opc
->name
, opc
->args
);
6924 if (used_bits
!= 0xffffffff)
6926 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6927 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6933 /* This routine assembles an instruction into its binary format. As a
6934 side effect, it sets one of the global variables imm_reloc or
6935 offset_reloc to the type of relocation to do if one of the operands
6936 is an address expression. */
6941 struct mips_cl_insn
*ip
;
6946 struct mips_opcode
*insn
;
6949 unsigned int lastregno
= 0;
6952 int full_opcode_match
= 1;
6956 /* If the instruction contains a '.', we first try to match an instruction
6957 including the '.'. Then we try again without the '.'. */
6959 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
6962 /* If we stopped on whitespace, then replace the whitespace with null for
6963 the call to hash_find. Save the character we replaced just in case we
6964 have to re-parse the instruction. */
6965 if (isspace ((unsigned char) *s
))
6971 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
6973 /* If we didn't find the instruction in the opcode table, try again, but
6974 this time with just the instruction up to, but not including the
6978 /* Restore the character we overwrite above (if any). */
6982 /* Scan up to the first '.' or whitespace. */
6983 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
6986 /* If we did not find a '.', then we can quit now. */
6989 insn_error
= "unrecognized opcode";
6993 /* Lookup the instruction in the hash table. */
6995 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6997 insn_error
= "unrecognized opcode";
7001 full_opcode_match
= 0;
7010 assert (strcmp (insn
->name
, str
) == 0);
7012 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
7014 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
7016 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
7018 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
7023 if (insn_isa
<= mips_opts
.isa
)
7025 else if (insn
->pinfo
== INSN_MACRO
)
7027 else if ((mips_cpu
== 4650 && (insn
->membership
& INSN_4650
) != 0)
7028 || (mips_cpu
== 4010 && (insn
->membership
& INSN_4010
) != 0)
7029 || ((mips_cpu
== 4100
7032 && (insn
->membership
& INSN_4100
) != 0)
7033 || (mips_cpu
== 3900 && (insn
->membership
& INSN_3900
) != 0))
7038 if (insn
->pinfo
!= INSN_MACRO
)
7040 if (mips_cpu
== 4650 && (insn
->pinfo
& FP_D
) != 0)
7046 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7047 && strcmp (insn
->name
, insn
[1].name
) == 0)
7053 || insn_isa
<= mips_opts
.isa
)
7054 insn_error
= _("opcode not supported on this processor");
7057 static char buf
[100];
7059 sprintf (buf
, _("opcode requires -mips%d or greater"), insn_isa
);
7066 ip
->insn_opcode
= insn
->match
;
7067 for (args
= insn
->args
;; ++args
)
7073 case '\0': /* end of args */
7086 ip
->insn_opcode
|= lastregno
<< 21;
7091 ip
->insn_opcode
|= lastregno
<< 16;
7095 ip
->insn_opcode
|= lastregno
<< 11;
7101 /* Handle optional base register.
7102 Either the base register is omitted or
7103 we must have a left paren. */
7104 /* This is dependent on the next operand specifier
7105 is a base register specification. */
7106 assert (args
[1] == 'b' || args
[1] == '5'
7107 || args
[1] == '-' || args
[1] == '4');
7111 case ')': /* these must match exactly */
7116 case '<': /* must be at least one digit */
7118 * According to the manual, if the shift amount is greater
7119 * than 31 or less than 0 the the shift amount should be
7120 * mod 32. In reality the mips assembler issues an error.
7121 * We issue a warning and mask out all but the low 5 bits.
7123 my_getExpression (&imm_expr
, s
);
7124 check_absolute_expr (ip
, &imm_expr
);
7125 if ((unsigned long) imm_expr
.X_add_number
> 31)
7127 as_warn (_("Improper shift amount (%ld)"),
7128 (long) imm_expr
.X_add_number
);
7129 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7131 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7132 imm_expr
.X_op
= O_absent
;
7136 case '>': /* shift amount minus 32 */
7137 my_getExpression (&imm_expr
, s
);
7138 check_absolute_expr (ip
, &imm_expr
);
7139 if ((unsigned long) imm_expr
.X_add_number
< 32
7140 || (unsigned long) imm_expr
.X_add_number
> 63)
7142 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7143 imm_expr
.X_op
= O_absent
;
7148 case 'k': /* cache code */
7149 case 'h': /* prefx code */
7150 my_getExpression (&imm_expr
, s
);
7151 check_absolute_expr (ip
, &imm_expr
);
7152 if ((unsigned long) imm_expr
.X_add_number
> 31)
7154 as_warn (_("Invalid value for `%s' (%lu)"),
7156 (unsigned long) imm_expr
.X_add_number
);
7157 imm_expr
.X_add_number
&= 0x1f;
7160 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7162 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7163 imm_expr
.X_op
= O_absent
;
7167 case 'c': /* break code */
7168 my_getExpression (&imm_expr
, s
);
7169 check_absolute_expr (ip
, &imm_expr
);
7170 if ((unsigned) imm_expr
.X_add_number
> 1023)
7172 as_warn (_("Illegal break code (%ld)"),
7173 (long) imm_expr
.X_add_number
);
7174 imm_expr
.X_add_number
&= 0x3ff;
7176 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7177 imm_expr
.X_op
= O_absent
;
7181 case 'q': /* lower break code */
7182 my_getExpression (&imm_expr
, s
);
7183 check_absolute_expr (ip
, &imm_expr
);
7184 if ((unsigned) imm_expr
.X_add_number
> 1023)
7186 as_warn (_("Illegal lower break code (%ld)"),
7187 (long) imm_expr
.X_add_number
);
7188 imm_expr
.X_add_number
&= 0x3ff;
7190 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7191 imm_expr
.X_op
= O_absent
;
7195 case 'B': /* syscall code */
7196 my_getExpression (&imm_expr
, s
);
7197 check_absolute_expr (ip
, &imm_expr
);
7198 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7199 as_warn (_("Illegal syscall code (%ld)"),
7200 (long) imm_expr
.X_add_number
);
7201 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7202 imm_expr
.X_op
= O_absent
;
7206 case 'C': /* Coprocessor code */
7207 my_getExpression (&imm_expr
, s
);
7208 check_absolute_expr (ip
, &imm_expr
);
7209 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7211 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7212 (long) imm_expr
.X_add_number
);
7213 imm_expr
.X_add_number
&= ((1<<25) - 1);
7215 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7216 imm_expr
.X_op
= O_absent
;
7220 case 'P': /* Performance register */
7221 my_getExpression (&imm_expr
, s
);
7222 check_absolute_expr (ip
, &imm_expr
);
7223 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7225 as_warn (_("Invalidate performance regster (%ld)"),
7226 (long) imm_expr
.X_add_number
);
7227 imm_expr
.X_add_number
&= 1;
7229 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7230 imm_expr
.X_op
= O_absent
;
7234 case 'b': /* base register */
7235 case 'd': /* destination register */
7236 case 's': /* source register */
7237 case 't': /* target register */
7238 case 'r': /* both target and source */
7239 case 'v': /* both dest and source */
7240 case 'w': /* both dest and target */
7241 case 'E': /* coprocessor target register */
7242 case 'G': /* coprocessor destination register */
7243 case 'x': /* ignore register name */
7244 case 'z': /* must be zero register */
7249 if (isdigit ((unsigned char) s
[1]))
7259 while (isdigit ((unsigned char) *s
));
7261 as_bad (_("Invalid register number (%d)"), regno
);
7263 else if (*args
== 'E' || *args
== 'G')
7267 if (s
[1] == 'f' && s
[2] == 'p')
7272 else if (s
[1] == 's' && s
[2] == 'p')
7277 else if (s
[1] == 'g' && s
[2] == 'p')
7282 else if (s
[1] == 'a' && s
[2] == 't')
7287 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7292 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7297 else if (itbl_have_entries
)
7302 p
= s
+ 1; /* advance past '$' */
7303 n
= itbl_get_field (&p
); /* n is name */
7305 /* See if this is a register defined in an
7307 if (itbl_get_reg_val (n
, &r
))
7309 /* Get_field advances to the start of
7310 the next field, so we need to back
7311 rack to the end of the last field. */
7315 s
= strchr (s
, '\0');
7328 as_warn (_("Used $at without \".set noat\""));
7334 if (c
== 'r' || c
== 'v' || c
== 'w')
7341 /* 'z' only matches $0. */
7342 if (c
== 'z' && regno
!= 0)
7345 /* Now that we have assembled one operand, we use the args string
7346 * to figure out where it goes in the instruction. */
7353 ip
->insn_opcode
|= regno
<< 21;
7357 ip
->insn_opcode
|= regno
<< 11;
7362 ip
->insn_opcode
|= regno
<< 16;
7365 /* This case exists because on the r3000 trunc
7366 expands into a macro which requires a gp
7367 register. On the r6000 or r4000 it is
7368 assembled into a single instruction which
7369 ignores the register. Thus the insn version
7370 is MIPS_ISA2 and uses 'x', and the macro
7371 version is MIPS_ISA1 and uses 't'. */
7374 /* This case is for the div instruction, which
7375 acts differently if the destination argument
7376 is $0. This only matches $0, and is checked
7377 outside the switch. */
7380 /* Itbl operand; not yet implemented. FIXME ?? */
7382 /* What about all other operands like 'i', which
7383 can be specified in the opcode table? */
7393 ip
->insn_opcode
|= lastregno
<< 21;
7396 ip
->insn_opcode
|= lastregno
<< 16;
7401 case 'D': /* floating point destination register */
7402 case 'S': /* floating point source register */
7403 case 'T': /* floating point target register */
7404 case 'R': /* floating point source register */
7408 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7418 while (isdigit ((unsigned char) *s
));
7421 as_bad (_("Invalid float register number (%d)"), regno
);
7423 if ((regno
& 1) != 0
7424 && mips_opts
.isa
< 3
7425 && ! (strcmp (str
, "mtc1") == 0
7426 || strcmp (str
, "mfc1") == 0
7427 || strcmp (str
, "lwc1") == 0
7428 || strcmp (str
, "swc1") == 0
7429 || strcmp (str
, "l.s") == 0
7430 || strcmp (str
, "s.s") == 0))
7431 as_warn (_("Float register should be even, was %d"),
7439 if (c
== 'V' || c
== 'W')
7449 ip
->insn_opcode
|= regno
<< 6;
7453 ip
->insn_opcode
|= regno
<< 11;
7457 ip
->insn_opcode
|= regno
<< 16;
7460 ip
->insn_opcode
|= regno
<< 21;
7471 ip
->insn_opcode
|= lastregno
<< 11;
7474 ip
->insn_opcode
|= lastregno
<< 16;
7480 my_getExpression (&imm_expr
, s
);
7481 if (imm_expr
.X_op
!= O_big
7482 && imm_expr
.X_op
!= O_constant
)
7483 insn_error
= _("absolute expression required");
7488 my_getExpression (&offset_expr
, s
);
7489 imm_reloc
= BFD_RELOC_32
;
7501 unsigned char temp
[8];
7503 unsigned int length
;
7508 /* These only appear as the last operand in an
7509 instruction, and every instruction that accepts
7510 them in any variant accepts them in all variants.
7511 This means we don't have to worry about backing out
7512 any changes if the instruction does not match.
7514 The difference between them is the size of the
7515 floating point constant and where it goes. For 'F'
7516 and 'L' the constant is 64 bits; for 'f' and 'l' it
7517 is 32 bits. Where the constant is placed is based
7518 on how the MIPS assembler does things:
7521 f -- immediate value
7524 The .lit4 and .lit8 sections are only used if
7525 permitted by the -G argument.
7527 When generating embedded PIC code, we use the
7528 .lit8 section but not the .lit4 section (we can do
7529 .lit4 inline easily; we need to put .lit8
7530 somewhere in the data segment, and using .lit8
7531 permits the linker to eventually combine identical
7534 f64
= *args
== 'F' || *args
== 'L';
7536 save_in
= input_line_pointer
;
7537 input_line_pointer
= s
;
7538 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7540 s
= input_line_pointer
;
7541 input_line_pointer
= save_in
;
7542 if (err
!= NULL
&& *err
!= '\0')
7544 as_bad (_("Bad floating point constant: %s"), err
);
7545 memset (temp
, '\0', sizeof temp
);
7546 length
= f64
? 8 : 4;
7549 assert (length
== (f64
? 8 : 4));
7553 && (! USE_GLOBAL_POINTER_OPT
7554 || mips_pic
== EMBEDDED_PIC
7555 || g_switch_value
< 4
7556 || (temp
[0] == 0 && temp
[1] == 0)
7557 || (temp
[2] == 0 && temp
[3] == 0))))
7559 imm_expr
.X_op
= O_constant
;
7560 if (! target_big_endian
)
7561 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7563 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7566 && ((temp
[0] == 0 && temp
[1] == 0)
7567 || (temp
[2] == 0 && temp
[3] == 0))
7568 && ((temp
[4] == 0 && temp
[5] == 0)
7569 || (temp
[6] == 0 && temp
[7] == 0)))
7571 /* The value is simple enough to load with a
7572 couple of instructions. In mips1 mode, set
7573 imm_expr to the high order 32 bits and
7574 offset_expr to the low order 32 bits.
7575 Otherwise, set imm_expr to the entire 64 bit
7577 if (mips_opts
.isa
< 3)
7579 imm_expr
.X_op
= O_constant
;
7580 offset_expr
.X_op
= O_constant
;
7581 if (! target_big_endian
)
7583 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7584 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7588 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7589 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7591 if (offset_expr
.X_add_number
== 0)
7592 offset_expr
.X_op
= O_absent
;
7594 else if (sizeof (imm_expr
.X_add_number
) > 4)
7596 imm_expr
.X_op
= O_constant
;
7597 if (! target_big_endian
)
7598 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7600 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7604 imm_expr
.X_op
= O_big
;
7605 imm_expr
.X_add_number
= 4;
7606 if (! target_big_endian
)
7608 generic_bignum
[0] = bfd_getl16 (temp
);
7609 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7610 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7611 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7615 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7616 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7617 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7618 generic_bignum
[3] = bfd_getb16 (temp
);
7624 const char *newname
;
7627 /* Switch to the right section. */
7629 subseg
= now_subseg
;
7632 default: /* unused default case avoids warnings. */
7634 newname
= RDATA_SECTION_NAME
;
7635 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7639 newname
= RDATA_SECTION_NAME
;
7642 assert (!USE_GLOBAL_POINTER_OPT
7643 || g_switch_value
>= 4);
7647 new_seg
= subseg_new (newname
, (subsegT
) 0);
7648 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7649 bfd_set_section_flags (stdoutput
, new_seg
,
7654 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7655 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7656 && strcmp (TARGET_OS
, "elf") != 0)
7657 record_alignment (new_seg
, 4);
7659 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7661 as_bad (_("Can't use floating point insn in this section"));
7663 /* Set the argument to the current address in the
7665 offset_expr
.X_op
= O_symbol
;
7666 offset_expr
.X_add_symbol
=
7667 symbol_new ("L0\001", now_seg
,
7668 (valueT
) frag_now_fix (), frag_now
);
7669 offset_expr
.X_add_number
= 0;
7671 /* Put the floating point number into the section. */
7672 p
= frag_more ((int) length
);
7673 memcpy (p
, temp
, length
);
7675 /* Switch back to the original section. */
7676 subseg_set (seg
, subseg
);
7681 case 'i': /* 16 bit unsigned immediate */
7682 case 'j': /* 16 bit signed immediate */
7683 imm_reloc
= BFD_RELOC_LO16
;
7684 c
= my_getSmallExpression (&imm_expr
, s
);
7689 if (imm_expr
.X_op
== O_constant
)
7690 imm_expr
.X_add_number
=
7691 (imm_expr
.X_add_number
>> 16) & 0xffff;
7694 imm_reloc
= BFD_RELOC_HI16_S
;
7695 imm_unmatched_hi
= true;
7698 imm_reloc
= BFD_RELOC_HI16
;
7700 else if (imm_expr
.X_op
== O_constant
)
7701 imm_expr
.X_add_number
&= 0xffff;
7705 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7706 || ((imm_expr
.X_add_number
< 0
7707 || imm_expr
.X_add_number
>= 0x10000)
7708 && imm_expr
.X_op
== O_constant
))
7710 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7711 !strcmp (insn
->name
, insn
[1].name
))
7713 if (imm_expr
.X_op
!= O_constant
7714 && imm_expr
.X_op
!= O_big
)
7715 insn_error
= _("absolute expression required");
7717 as_bad (_("16 bit expression not in range 0..65535"));
7725 /* The upper bound should be 0x8000, but
7726 unfortunately the MIPS assembler accepts numbers
7727 from 0x8000 to 0xffff and sign extends them, and
7728 we want to be compatible. We only permit this
7729 extended range for an instruction which does not
7730 provide any further alternates, since those
7731 alternates may handle other cases. People should
7732 use the numbers they mean, rather than relying on
7733 a mysterious sign extension. */
7734 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7735 strcmp (insn
->name
, insn
[1].name
) == 0);
7740 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7741 || ((imm_expr
.X_add_number
< -0x8000
7742 || imm_expr
.X_add_number
>= max
)
7743 && imm_expr
.X_op
== O_constant
)
7745 && imm_expr
.X_add_number
< 0
7746 && mips_opts
.isa
>= 3
7747 && imm_expr
.X_unsigned
7748 && sizeof (imm_expr
.X_add_number
) <= 4))
7752 if (imm_expr
.X_op
!= O_constant
7753 && imm_expr
.X_op
!= O_big
)
7754 insn_error
= _("absolute expression required");
7756 as_bad (_("16 bit expression not in range -32768..32767"));
7762 case 'o': /* 16 bit offset */
7763 c
= my_getSmallExpression (&offset_expr
, s
);
7765 /* If this value won't fit into a 16 bit offset, then go
7766 find a macro that will generate the 32 bit offset
7767 code pattern. As a special hack, we accept the
7768 difference of two local symbols as a constant. This
7769 is required to suppose embedded PIC switches, which
7770 use an instruction which looks like
7771 lw $4,$L12-$LS12($4)
7772 The problem with handling this in a more general
7773 fashion is that the macro function doesn't expect to
7774 see anything which can be handled in a single
7775 constant instruction. */
7777 && (offset_expr
.X_op
!= O_constant
7778 || offset_expr
.X_add_number
>= 0x8000
7779 || offset_expr
.X_add_number
< -0x8000)
7780 && (mips_pic
!= EMBEDDED_PIC
7781 || offset_expr
.X_op
!= O_subtract
7782 || now_seg
!= text_section
7783 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7787 if (c
== 'h' || c
== 'H')
7789 if (offset_expr
.X_op
!= O_constant
)
7791 offset_expr
.X_add_number
=
7792 (offset_expr
.X_add_number
>> 16) & 0xffff;
7794 offset_reloc
= BFD_RELOC_LO16
;
7798 case 'p': /* pc relative offset */
7799 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7800 my_getExpression (&offset_expr
, s
);
7804 case 'u': /* upper 16 bits */
7805 c
= my_getSmallExpression (&imm_expr
, s
);
7806 imm_reloc
= BFD_RELOC_LO16
;
7811 if (imm_expr
.X_op
== O_constant
)
7812 imm_expr
.X_add_number
=
7813 (imm_expr
.X_add_number
>> 16) & 0xffff;
7816 imm_reloc
= BFD_RELOC_HI16_S
;
7817 imm_unmatched_hi
= true;
7820 imm_reloc
= BFD_RELOC_HI16
;
7822 else if (imm_expr
.X_op
== O_constant
)
7823 imm_expr
.X_add_number
&= 0xffff;
7825 if (imm_expr
.X_op
== O_constant
7826 && (imm_expr
.X_add_number
< 0
7827 || imm_expr
.X_add_number
>= 0x10000))
7828 as_bad (_("lui expression not in range 0..65535"));
7832 case 'a': /* 26 bit address */
7833 my_getExpression (&offset_expr
, s
);
7835 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7838 case 'N': /* 3 bit branch condition code */
7839 case 'M': /* 3 bit compare condition code */
7840 if (strncmp (s
, "$fcc", 4) != 0)
7850 while (isdigit ((unsigned char) *s
));
7852 as_bad (_("invalid condition code register $fcc%d"), regno
);
7854 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7856 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7860 as_bad (_("bad char = '%c'\n"), *args
);
7865 /* Args don't match. */
7866 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7867 !strcmp (insn
->name
, insn
[1].name
))
7873 insn_error
= _("illegal operands");
7878 /* This routine assembles an instruction into its binary format when
7879 assembling for the mips16. As a side effect, it sets one of the
7880 global variables imm_reloc or offset_reloc to the type of
7881 relocation to do if one of the operands is an address expression.
7882 It also sets mips16_small and mips16_ext if the user explicitly
7883 requested a small or extended instruction. */
7888 struct mips_cl_insn
*ip
;
7892 struct mips_opcode
*insn
;
7895 unsigned int lastregno
= 0;
7900 mips16_small
= false;
7903 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7915 if (s
[1] == 't' && s
[2] == ' ')
7918 mips16_small
= true;
7922 else if (s
[1] == 'e' && s
[2] == ' ')
7931 insn_error
= _("unknown opcode");
7935 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7936 mips16_small
= true;
7938 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7940 insn_error
= _("unrecognized opcode");
7947 assert (strcmp (insn
->name
, str
) == 0);
7950 ip
->insn_opcode
= insn
->match
;
7951 ip
->use_extend
= false;
7952 imm_expr
.X_op
= O_absent
;
7953 imm_reloc
= BFD_RELOC_UNUSED
;
7954 offset_expr
.X_op
= O_absent
;
7955 offset_reloc
= BFD_RELOC_UNUSED
;
7956 for (args
= insn
->args
; 1; ++args
)
7963 /* In this switch statement we call break if we did not find
7964 a match, continue if we did find a match, or return if we
7973 /* Stuff the immediate value in now, if we can. */
7974 if (imm_expr
.X_op
== O_constant
7975 && imm_reloc
> BFD_RELOC_UNUSED
7976 && insn
->pinfo
!= INSN_MACRO
)
7978 mips16_immed ((char *) NULL
, 0,
7979 imm_reloc
- BFD_RELOC_UNUSED
,
7980 imm_expr
.X_add_number
, true, mips16_small
,
7981 mips16_ext
, &ip
->insn_opcode
,
7982 &ip
->use_extend
, &ip
->extend
);
7983 imm_expr
.X_op
= O_absent
;
7984 imm_reloc
= BFD_RELOC_UNUSED
;
7998 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8001 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8017 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8019 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8036 if (isdigit ((unsigned char) s
[1]))
8046 while (isdigit ((unsigned char) *s
));
8049 as_bad (_("invalid register number (%d)"), regno
);
8055 if (s
[1] == 'f' && s
[2] == 'p')
8060 else if (s
[1] == 's' && s
[2] == 'p')
8065 else if (s
[1] == 'g' && s
[2] == 'p')
8070 else if (s
[1] == 'a' && s
[2] == 't')
8075 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8080 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8093 if (c
== 'v' || c
== 'w')
8095 regno
= mips16_to_32_reg_map
[lastregno
];
8109 regno
= mips32_to_16_reg_map
[regno
];
8114 regno
= ILLEGAL_REG
;
8119 regno
= ILLEGAL_REG
;
8124 regno
= ILLEGAL_REG
;
8129 if (regno
== AT
&& ! mips_opts
.noat
)
8130 as_warn (_("used $at without \".set noat\""));
8137 if (regno
== ILLEGAL_REG
)
8144 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8148 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8151 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8154 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8160 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8163 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8164 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8174 if (strncmp (s
, "$pc", 3) == 0)
8198 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8200 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8201 and generate the appropriate reloc. If the text
8202 inside %gprel is not a symbol name with an
8203 optional offset, then we generate a normal reloc
8204 and will probably fail later. */
8205 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8206 if (imm_expr
.X_op
== O_symbol
)
8209 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8211 ip
->use_extend
= true;
8218 /* Just pick up a normal expression. */
8219 my_getExpression (&imm_expr
, s
);
8222 if (imm_expr
.X_op
== O_register
)
8224 /* What we thought was an expression turned out to
8227 if (s
[0] == '(' && args
[1] == '(')
8229 /* It looks like the expression was omitted
8230 before a register indirection, which means
8231 that the expression is implicitly zero. We
8232 still set up imm_expr, so that we handle
8233 explicit extensions correctly. */
8234 imm_expr
.X_op
= O_constant
;
8235 imm_expr
.X_add_number
= 0;
8236 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8243 /* We need to relax this instruction. */
8244 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8253 /* We use offset_reloc rather than imm_reloc for the PC
8254 relative operands. This lets macros with both
8255 immediate and address operands work correctly. */
8256 my_getExpression (&offset_expr
, s
);
8258 if (offset_expr
.X_op
== O_register
)
8261 /* We need to relax this instruction. */
8262 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8266 case '6': /* break code */
8267 my_getExpression (&imm_expr
, s
);
8268 check_absolute_expr (ip
, &imm_expr
);
8269 if ((unsigned long) imm_expr
.X_add_number
> 63)
8271 as_warn (_("Invalid value for `%s' (%lu)"),
8273 (unsigned long) imm_expr
.X_add_number
);
8274 imm_expr
.X_add_number
&= 0x3f;
8276 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8277 imm_expr
.X_op
= O_absent
;
8281 case 'a': /* 26 bit address */
8282 my_getExpression (&offset_expr
, s
);
8284 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8285 ip
->insn_opcode
<<= 16;
8288 case 'l': /* register list for entry macro */
8289 case 'L': /* register list for exit macro */
8299 int freg
, reg1
, reg2
;
8301 while (*s
== ' ' || *s
== ',')
8305 as_bad (_("can't parse register list"));
8317 while (isdigit ((unsigned char) *s
))
8339 as_bad (_("invalid register list"));
8344 while (isdigit ((unsigned char) *s
))
8351 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8356 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8361 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8362 mask
|= (reg2
- 3) << 3;
8363 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8364 mask
|= (reg2
- 15) << 1;
8365 else if (reg1
== 31 && reg2
== 31)
8369 as_bad (_("invalid register list"));
8373 /* The mask is filled in in the opcode table for the
8374 benefit of the disassembler. We remove it before
8375 applying the actual mask. */
8376 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8377 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8381 case 'e': /* extend code */
8382 my_getExpression (&imm_expr
, s
);
8383 check_absolute_expr (ip
, &imm_expr
);
8384 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8386 as_warn (_("Invalid value for `%s' (%lu)"),
8388 (unsigned long) imm_expr
.X_add_number
);
8389 imm_expr
.X_add_number
&= 0x7ff;
8391 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8392 imm_expr
.X_op
= O_absent
;
8402 /* Args don't match. */
8403 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8404 strcmp (insn
->name
, insn
[1].name
) == 0)
8411 insn_error
= _("illegal operands");
8417 /* This structure holds information we know about a mips16 immediate
8420 struct mips16_immed_operand
8422 /* The type code used in the argument string in the opcode table. */
8424 /* The number of bits in the short form of the opcode. */
8426 /* The number of bits in the extended form of the opcode. */
8428 /* The amount by which the short form is shifted when it is used;
8429 for example, the sw instruction has a shift count of 2. */
8431 /* The amount by which the short form is shifted when it is stored
8432 into the instruction code. */
8434 /* Non-zero if the short form is unsigned. */
8436 /* Non-zero if the extended form is unsigned. */
8438 /* Non-zero if the value is PC relative. */
8442 /* The mips16 immediate operand types. */
8444 static const struct mips16_immed_operand mips16_immed_operands
[] =
8446 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8447 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8448 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8449 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8450 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8451 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8452 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8453 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8454 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8455 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8456 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8457 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8458 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8459 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8460 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8461 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8462 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8463 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8464 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8465 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8466 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8469 #define MIPS16_NUM_IMMED \
8470 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8472 /* Handle a mips16 instruction with an immediate value. This or's the
8473 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8474 whether an extended value is needed; if one is needed, it sets
8475 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8476 If SMALL is true, an unextended opcode was explicitly requested.
8477 If EXT is true, an extended opcode was explicitly requested. If
8478 WARN is true, warn if EXT does not match reality. */
8481 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8490 unsigned long *insn
;
8491 boolean
*use_extend
;
8492 unsigned short *extend
;
8494 register const struct mips16_immed_operand
*op
;
8495 int mintiny
, maxtiny
;
8498 op
= mips16_immed_operands
;
8499 while (op
->type
!= type
)
8502 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8507 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8510 maxtiny
= 1 << op
->nbits
;
8515 maxtiny
= (1 << op
->nbits
) - 1;
8520 mintiny
= - (1 << (op
->nbits
- 1));
8521 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8524 /* Branch offsets have an implicit 0 in the lowest bit. */
8525 if (type
== 'p' || type
== 'q')
8528 if ((val
& ((1 << op
->shift
) - 1)) != 0
8529 || val
< (mintiny
<< op
->shift
)
8530 || val
> (maxtiny
<< op
->shift
))
8535 if (warn
&& ext
&& ! needext
)
8536 as_warn_where (file
, line
, _("extended operand requested but not required"));
8537 if (small
&& needext
)
8538 as_bad_where (file
, line
, _("invalid unextended operand value"));
8540 if (small
|| (! ext
&& ! needext
))
8544 *use_extend
= false;
8545 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8546 insnval
<<= op
->op_shift
;
8551 long minext
, maxext
;
8557 maxext
= (1 << op
->extbits
) - 1;
8561 minext
= - (1 << (op
->extbits
- 1));
8562 maxext
= (1 << (op
->extbits
- 1)) - 1;
8564 if (val
< minext
|| val
> maxext
)
8565 as_bad_where (file
, line
,
8566 _("operand value out of range for instruction"));
8569 if (op
->extbits
== 16)
8571 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8574 else if (op
->extbits
== 15)
8576 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8581 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8585 *extend
= (unsigned short) extval
;
8594 my_getSmallExpression (ep
, str
)
8605 ((str
[1] == 'h' && str
[2] == 'i')
8606 || (str
[1] == 'H' && str
[2] == 'I')
8607 || (str
[1] == 'l' && str
[2] == 'o'))
8619 * A small expression may be followed by a base register.
8620 * Scan to the end of this operand, and then back over a possible
8621 * base register. Then scan the small expression up to that
8622 * point. (Based on code in sparc.c...)
8624 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8626 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8628 if (isdigit ((unsigned char) sp
[-2]))
8630 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8632 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8638 else if (sp
- 5 >= str
8641 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8642 || (sp
[-3] == 's' && sp
[-2] == 'p')
8643 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8644 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8650 /* no expression means zero offset */
8653 /* %xx(reg) is an error */
8654 ep
->X_op
= O_absent
;
8659 ep
->X_op
= O_constant
;
8662 ep
->X_add_symbol
= NULL
;
8663 ep
->X_op_symbol
= NULL
;
8664 ep
->X_add_number
= 0;
8669 my_getExpression (ep
, str
);
8676 my_getExpression (ep
, str
);
8677 return c
; /* => %hi or %lo encountered */
8681 my_getExpression (ep
, str
)
8687 save_in
= input_line_pointer
;
8688 input_line_pointer
= str
;
8690 expr_end
= input_line_pointer
;
8691 input_line_pointer
= save_in
;
8693 /* If we are in mips16 mode, and this is an expression based on `.',
8694 then we bump the value of the symbol by 1 since that is how other
8695 text symbols are handled. We don't bother to handle complex
8696 expressions, just `.' plus or minus a constant. */
8697 if (mips_opts
.mips16
8698 && ep
->X_op
== O_symbol
8699 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8700 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8701 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8702 && symbol_constant_p (ep
->X_add_symbol
)
8703 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8704 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8707 /* Turn a string in input_line_pointer into a floating point constant
8708 of type type, and store the appropriate bytes in *litP. The number
8709 of LITTLENUMS emitted is stored in *sizeP . An error message is
8710 returned, or NULL on OK. */
8713 md_atof (type
, litP
, sizeP
)
8719 LITTLENUM_TYPE words
[4];
8735 return _("bad call to md_atof");
8738 t
= atof_ieee (input_line_pointer
, type
, words
);
8740 input_line_pointer
= t
;
8744 if (! target_big_endian
)
8746 for (i
= prec
- 1; i
>= 0; i
--)
8748 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8754 for (i
= 0; i
< prec
; i
++)
8756 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8765 md_number_to_chars (buf
, val
, n
)
8770 if (target_big_endian
)
8771 number_to_chars_bigendian (buf
, val
, n
);
8773 number_to_chars_littleendian (buf
, val
, n
);
8776 CONST
char *md_shortopts
= "O::g::G:";
8778 struct option md_longopts
[] = {
8779 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8780 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8781 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8782 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8783 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8784 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8785 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8786 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8787 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8788 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8789 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8790 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8791 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8792 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8793 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8794 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8795 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8796 {"break", no_argument
, NULL
, OPTION_BREAK
},
8797 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8798 #define OPTION_EB (OPTION_MD_BASE + 11)
8799 {"EB", no_argument
, NULL
, OPTION_EB
},
8800 #define OPTION_EL (OPTION_MD_BASE + 12)
8801 {"EL", no_argument
, NULL
, OPTION_EL
},
8802 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8803 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8804 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8805 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8806 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8807 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8808 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8809 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8810 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8811 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8812 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8813 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8814 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8815 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8816 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8817 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8818 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8819 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8820 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8821 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8824 #define OPTION_MABI (OPTION_MD_BASE + 38)
8825 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8827 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8828 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8829 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8830 #define OPTION_32 (OPTION_MD_BASE + 20)
8831 #define OPTION_64 (OPTION_MD_BASE + 21)
8833 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8834 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8835 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8836 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8837 {"32", no_argument
, NULL
, OPTION_32
},
8838 {"64", no_argument
, NULL
, OPTION_64
},
8841 {NULL
, no_argument
, NULL
, 0}
8843 size_t md_longopts_size
= sizeof(md_longopts
);
8846 md_parse_option (c
, arg
)
8861 target_big_endian
= 1;
8865 target_big_endian
= 0;
8869 if (arg
&& arg
[1] == '0')
8879 mips_debug
= atoi (arg
);
8880 /* When the MIPS assembler sees -g or -g2, it does not do
8881 optimizations which limit full symbolic debugging. We take
8882 that to be equivalent to -O0. */
8883 if (mips_debug
== 2)
8907 /* Identify the processor type */
8909 if (strcmp (p
, "default") == 0
8910 || strcmp (p
, "DEFAULT") == 0)
8916 /* We need to cope with the various "vr" prefixes for the 4300
8918 if (*p
== 'v' || *p
== 'V')
8924 if (*p
== 'r' || *p
== 'R')
8931 if (strcmp (p
, "10000") == 0
8932 || strcmp (p
, "10k") == 0
8933 || strcmp (p
, "10K") == 0)
8938 if (strcmp (p
, "2000") == 0
8939 || strcmp (p
, "2k") == 0
8940 || strcmp (p
, "2K") == 0)
8945 if (strcmp (p
, "3000") == 0
8946 || strcmp (p
, "3k") == 0
8947 || strcmp (p
, "3K") == 0)
8949 else if (strcmp (p
, "3900") == 0)
8954 if (strcmp (p
, "4000") == 0
8955 || strcmp (p
, "4k") == 0
8956 || strcmp (p
, "4K") == 0)
8958 else if (strcmp (p
, "4100") == 0)
8960 else if (strcmp (p
, "4111") == 0)
8962 else if (strcmp (p
, "4300") == 0)
8964 else if (strcmp (p
, "4400") == 0)
8966 else if (strcmp (p
, "4600") == 0)
8968 else if (strcmp (p
, "4650") == 0)
8970 else if (strcmp (p
, "4010") == 0)
8975 if (strcmp (p
, "5000") == 0
8976 || strcmp (p
, "5k") == 0
8977 || strcmp (p
, "5K") == 0)
8982 if (strcmp (p
, "6000") == 0
8983 || strcmp (p
, "6k") == 0
8984 || strcmp (p
, "6K") == 0)
8989 if (strcmp (p
, "8000") == 0
8990 || strcmp (p
, "8k") == 0
8991 || strcmp (p
, "8K") == 0)
8996 if (strcmp (p
, "orion") == 0)
9002 && (mips_cpu
!= 4300
9005 && mips_cpu
!= 5000))
9007 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9013 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9024 case OPTION_NO_M4650
:
9031 case OPTION_NO_M4010
:
9038 case OPTION_NO_M4100
:
9046 case OPTION_NO_M3900
:
9050 mips_opts
.mips16
= 1;
9051 mips_no_prev_insn (false);
9054 case OPTION_NO_MIPS16
:
9055 mips_opts
.mips16
= 0;
9056 mips_no_prev_insn (false);
9059 case OPTION_MEMBEDDED_PIC
:
9060 mips_pic
= EMBEDDED_PIC
;
9061 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9063 as_bad (_("-G may not be used with embedded PIC code"));
9066 g_switch_value
= 0x7fffffff;
9069 /* When generating ELF code, we permit -KPIC and -call_shared to
9070 select SVR4_PIC, and -non_shared to select no PIC. This is
9071 intended to be compatible with Irix 5. */
9072 case OPTION_CALL_SHARED
:
9073 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9075 as_bad (_("-call_shared is supported only for ELF format"));
9078 mips_pic
= SVR4_PIC
;
9079 if (g_switch_seen
&& g_switch_value
!= 0)
9081 as_bad (_("-G may not be used with SVR4 PIC code"));
9087 case OPTION_NON_SHARED
:
9088 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9090 as_bad (_("-non_shared is supported only for ELF format"));
9096 /* The -xgot option tells the assembler to use 32 offsets when
9097 accessing the got in SVR4_PIC mode. It is for Irix
9104 if (! USE_GLOBAL_POINTER_OPT
)
9106 as_bad (_("-G is not supported for this configuration"));
9109 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9111 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9115 g_switch_value
= atoi (arg
);
9119 /* The -32 and -64 options tell the assembler to output the 32
9120 bit or the 64 bit MIPS ELF format. */
9127 const char **list
, **l
;
9129 list
= bfd_target_list ();
9130 for (l
= list
; *l
!= NULL
; l
++)
9131 if (strcmp (*l
, "elf64-bigmips") == 0
9132 || strcmp (*l
, "elf64-littlemips") == 0)
9135 as_fatal (_("No compiled in support for 64 bit object file format"));
9143 if (strcmp (arg
,"32") == 0
9144 || strcmp (arg
,"n32") == 0
9145 || strcmp (arg
,"64") == 0
9146 || strcmp (arg
,"o64") == 0
9147 || strcmp (arg
,"eabi") == 0)
9148 mips_abi_string
= arg
;
9160 show (stream
, string
, col_p
, first_p
)
9168 fprintf (stream
, "%24s", "");
9173 fprintf (stream
, ", ");
9177 if (*col_p
+ strlen (string
) > 72)
9179 fprintf (stream
, "\n%24s", "");
9183 fprintf (stream
, "%s", string
);
9184 *col_p
+= strlen (string
);
9191 md_show_usage (stream
)
9196 fprintf(stream
, _("\
9198 -membedded-pic generate embedded position independent code\n\
9199 -EB generate big endian output\n\
9200 -EL generate little endian output\n\
9201 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9202 -G NUM allow referencing objects up to NUM bytes\n\
9203 implicitly with the gp register [default 8]\n"));
9204 fprintf(stream
, _("\
9205 -mips1 generate MIPS ISA I instructions\n\
9206 -mips2 generate MIPS ISA II instructions\n\
9207 -mips3 generate MIPS ISA III instructions\n\
9208 -mips4 generate MIPS ISA IV instructions\n\
9209 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9213 show (stream
, "2000", &column
, &first
);
9214 show (stream
, "3000", &column
, &first
);
9215 show (stream
, "3900", &column
, &first
);
9216 show (stream
, "4000", &column
, &first
);
9217 show (stream
, "4010", &column
, &first
);
9218 show (stream
, "4100", &column
, &first
);
9219 show (stream
, "4111", &column
, &first
);
9220 show (stream
, "4300", &column
, &first
);
9221 show (stream
, "4400", &column
, &first
);
9222 show (stream
, "4600", &column
, &first
);
9223 show (stream
, "4650", &column
, &first
);
9224 show (stream
, "5000", &column
, &first
);
9225 show (stream
, "6000", &column
, &first
);
9226 show (stream
, "8000", &column
, &first
);
9227 show (stream
, "10000", &column
, &first
);
9228 fputc ('\n', stream
);
9230 fprintf (stream
, _("\
9231 -mCPU equivalent to -mcpu=CPU.\n\
9232 -no-mCPU don't generate code specific to CPU.\n\
9233 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9237 show (stream
, "3900", &column
, &first
);
9238 show (stream
, "4010", &column
, &first
);
9239 show (stream
, "4100", &column
, &first
);
9240 show (stream
, "4650", &column
, &first
);
9241 fputc ('\n', stream
);
9243 fprintf(stream
, _("\
9244 -mips16 generate mips16 instructions\n\
9245 -no-mips16 do not generate mips16 instructions\n"));
9246 fprintf(stream
, _("\
9247 -O0 remove unneeded NOPs, do not swap branches\n\
9248 -O remove unneeded NOPs and swap branches\n\
9249 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9250 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9252 fprintf(stream
, _("\
9253 -KPIC, -call_shared generate SVR4 position independent code\n\
9254 -non_shared do not generate position independent code\n\
9255 -xgot assume a 32 bit GOT\n\
9256 -32 create 32 bit object file (default)\n\
9257 -64 create 64 bit object file\n"));
9262 mips_init_after_args ()
9264 /* initialize opcodes */
9265 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9266 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9270 md_pcrel_from (fixP
)
9273 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9274 && fixP
->fx_addsy
!= (symbolS
*) NULL
9275 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9277 /* This makes a branch to an undefined symbol be a branch to the
9278 current location. */
9282 /* return the address of the delay slot */
9283 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9286 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9287 reloc for a cons. We could use the definition there, except that
9288 we want to handle 64 bit relocs specially. */
9291 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9294 unsigned int nbytes
;
9298 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9300 if (nbytes
== 8 && ! mips_64
)
9302 if (target_big_endian
)
9308 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9309 as_bad (_("Unsupported reloc size %d"), nbytes
);
9311 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9314 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9317 /* This is called before the symbol table is processed. In order to
9318 work with gcc when using mips-tfile, we must keep all local labels.
9319 However, in other cases, we want to discard them. If we were
9320 called with -g, but we didn't see any debugging information, it may
9321 mean that gcc is smuggling debugging information through to
9322 mips-tfile, in which case we must generate all local labels. */
9325 mips_frob_file_before_adjust ()
9327 #ifndef NO_ECOFF_DEBUGGING
9330 && ! ecoff_debugging_seen
)
9331 flag_keep_locals
= 1;
9335 /* Sort any unmatched HI16_S relocs so that they immediately precede
9336 the corresponding LO reloc. This is called before md_apply_fix and
9337 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9338 explicit use of the %hi modifier. */
9343 struct mips_hi_fixup
*l
;
9345 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9347 segment_info_type
*seginfo
;
9350 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9352 /* Check quickly whether the next fixup happens to be a matching
9354 if (l
->fixp
->fx_next
!= NULL
9355 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9356 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9357 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9360 /* Look through the fixups for this segment for a matching %lo.
9361 When we find one, move the %hi just in front of it. We do
9362 this in two passes. In the first pass, we try to find a
9363 unique %lo. In the second pass, we permit multiple %hi
9364 relocs for a single %lo (this is a GNU extension). */
9365 seginfo
= seg_info (l
->seg
);
9366 for (pass
= 0; pass
< 2; pass
++)
9371 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9373 /* Check whether this is a %lo fixup which matches l->fixp. */
9374 if (f
->fx_r_type
== BFD_RELOC_LO16
9375 && f
->fx_addsy
== l
->fixp
->fx_addsy
9376 && f
->fx_offset
== l
->fixp
->fx_offset
9379 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9380 || prev
->fx_addsy
!= f
->fx_addsy
9381 || prev
->fx_offset
!= f
->fx_offset
))
9385 /* Move l->fixp before f. */
9386 for (pf
= &seginfo
->fix_root
;
9388 pf
= &(*pf
)->fx_next
)
9389 assert (*pf
!= NULL
);
9391 *pf
= l
->fixp
->fx_next
;
9393 l
->fixp
->fx_next
= f
;
9395 seginfo
->fix_root
= l
->fixp
;
9397 prev
->fx_next
= l
->fixp
;
9408 #if 0 /* GCC code motion plus incomplete dead code elimination
9409 can leave a %hi without a %lo. */
9411 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9412 _("Unmatched %%hi reloc"));
9418 /* When generating embedded PIC code we need to use a special
9419 relocation to represent the difference of two symbols in the .text
9420 section (switch tables use a difference of this sort). See
9421 include/coff/mips.h for details. This macro checks whether this
9422 fixup requires the special reloc. */
9423 #define SWITCH_TABLE(fixp) \
9424 ((fixp)->fx_r_type == BFD_RELOC_32 \
9425 && (fixp)->fx_addsy != NULL \
9426 && (fixp)->fx_subsy != NULL \
9427 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9428 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9430 /* When generating embedded PIC code we must keep all PC relative
9431 relocations, in case the linker has to relax a call. We also need
9432 to keep relocations for switch table entries. */
9436 mips_force_relocation (fixp
)
9439 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9440 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9443 return (mips_pic
== EMBEDDED_PIC
9445 || SWITCH_TABLE (fixp
)
9446 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9447 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9450 /* Apply a fixup to the object file. */
9453 md_apply_fix (fixP
, valueP
)
9460 assert (fixP
->fx_size
== 4
9461 || fixP
->fx_r_type
== BFD_RELOC_16
9462 || fixP
->fx_r_type
== BFD_RELOC_64
9463 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9464 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9468 /* If we aren't adjusting this fixup to be against the section
9469 symbol, we need to adjust the value. */
9471 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9472 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9473 || S_IS_WEAK (fixP
->fx_addsy
)
9474 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9475 && (((bfd_get_section_flags (stdoutput
,
9476 S_GET_SEGMENT (fixP
->fx_addsy
))
9477 & SEC_LINK_ONCE
) != 0)
9478 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9480 sizeof (".gnu.linkonce") - 1))))
9483 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9484 if (value
!= 0 && ! fixP
->fx_pcrel
)
9486 /* In this case, the bfd_install_relocation routine will
9487 incorrectly add the symbol value back in. We just want
9488 the addend to appear in the object file. */
9489 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9495 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9497 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9500 switch (fixP
->fx_r_type
)
9502 case BFD_RELOC_MIPS_JMP
:
9503 case BFD_RELOC_HI16
:
9504 case BFD_RELOC_HI16_S
:
9505 case BFD_RELOC_MIPS_GPREL
:
9506 case BFD_RELOC_MIPS_LITERAL
:
9507 case BFD_RELOC_MIPS_CALL16
:
9508 case BFD_RELOC_MIPS_GOT16
:
9509 case BFD_RELOC_MIPS_GPREL32
:
9510 case BFD_RELOC_MIPS_GOT_HI16
:
9511 case BFD_RELOC_MIPS_GOT_LO16
:
9512 case BFD_RELOC_MIPS_CALL_HI16
:
9513 case BFD_RELOC_MIPS_CALL_LO16
:
9514 case BFD_RELOC_MIPS16_GPREL
:
9516 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9517 _("Invalid PC relative reloc"));
9518 /* Nothing needed to do. The value comes from the reloc entry */
9521 case BFD_RELOC_MIPS16_JMP
:
9522 /* We currently always generate a reloc against a symbol, which
9523 means that we don't want an addend even if the symbol is
9525 fixP
->fx_addnumber
= 0;
9528 case BFD_RELOC_PCREL_HI16_S
:
9529 /* The addend for this is tricky if it is internal, so we just
9530 do everything here rather than in bfd_install_relocation. */
9531 if ((symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9533 /* For an external symbol adjust by the address to make it
9534 pcrel_offset. We use the address of the RELLO reloc
9535 which follows this one. */
9536 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9537 + fixP
->fx_next
->fx_where
);
9542 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9543 if (target_big_endian
)
9545 md_number_to_chars (buf
, value
, 2);
9548 case BFD_RELOC_PCREL_LO16
:
9549 /* The addend for this is tricky if it is internal, so we just
9550 do everything here rather than in bfd_install_relocation. */
9551 if ((symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9552 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9553 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9554 if (target_big_endian
)
9556 md_number_to_chars (buf
, value
, 2);
9560 /* This is handled like BFD_RELOC_32, but we output a sign
9561 extended value if we are only 32 bits. */
9563 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9565 if (8 <= sizeof (valueT
))
9566 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9573 w1
= w2
= fixP
->fx_where
;
9574 if (target_big_endian
)
9578 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9579 if ((value
& 0x80000000) != 0)
9583 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9589 /* If we are deleting this reloc entry, we must fill in the
9590 value now. This can happen if we have a .word which is not
9591 resolved when it appears but is later defined. We also need
9592 to fill in the value if this is an embedded PIC switch table
9595 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9596 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9601 /* If we are deleting this reloc entry, we must fill in the
9603 assert (fixP
->fx_size
== 2);
9605 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9609 case BFD_RELOC_LO16
:
9610 /* When handling an embedded PIC switch statement, we can wind
9611 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9614 if (value
< -0x8000 || value
> 0x7fff)
9615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9616 _("relocation overflow"));
9617 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9618 if (target_big_endian
)
9620 md_number_to_chars (buf
, value
, 2);
9624 case BFD_RELOC_16_PCREL_S2
:
9626 * We need to save the bits in the instruction since fixup_segment()
9627 * might be deleting the relocation entry (i.e., a branch within
9628 * the current segment).
9630 if ((value
& 0x3) != 0)
9631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9632 _("Branch to odd address (%lx)"), value
);
9635 /* update old instruction data */
9636 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9637 if (target_big_endian
)
9638 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9640 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9642 if (value
>= -0x8000 && value
< 0x8000)
9643 insn
|= value
& 0xffff;
9646 /* The branch offset is too large. If this is an
9647 unconditional branch, and we are not generating PIC code,
9648 we can convert it to an absolute jump instruction. */
9649 if (mips_pic
== NO_PIC
9651 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9652 && (fixP
->fx_frag
->fr_address
9653 < text_section
->vma
+ text_section
->_raw_size
)
9654 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9655 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9656 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9658 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9659 insn
= 0x0c000000; /* jal */
9661 insn
= 0x08000000; /* j */
9662 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9664 fixP
->fx_addsy
= section_symbol (text_section
);
9665 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9669 /* FIXME. It would be possible in principle to handle
9670 conditional branches which overflow. They could be
9671 transformed into a branch around a jump. This would
9672 require setting up variant frags for each different
9673 branch type. The native MIPS assembler attempts to
9674 handle these cases, but it appears to do it
9676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9677 _("Branch out of range"));
9681 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9684 case BFD_RELOC_VTABLE_INHERIT
:
9687 && !S_IS_DEFINED (fixP
->fx_addsy
)
9688 && !S_IS_WEAK (fixP
->fx_addsy
))
9689 S_SET_WEAK (fixP
->fx_addsy
);
9692 case BFD_RELOC_VTABLE_ENTRY
:
9708 const struct mips_opcode
*p
;
9709 int treg
, sreg
, dreg
, shamt
;
9714 for (i
= 0; i
< NUMOPCODES
; ++i
)
9716 p
= &mips_opcodes
[i
];
9717 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9719 printf ("%08lx %s\t", oc
, p
->name
);
9720 treg
= (oc
>> 16) & 0x1f;
9721 sreg
= (oc
>> 21) & 0x1f;
9722 dreg
= (oc
>> 11) & 0x1f;
9723 shamt
= (oc
>> 6) & 0x1f;
9725 for (args
= p
->args
;; ++args
)
9736 printf ("%c", *args
);
9740 assert (treg
== sreg
);
9741 printf ("$%d,$%d", treg
, sreg
);
9746 printf ("$%d", dreg
);
9751 printf ("$%d", treg
);
9755 printf ("0x%x", treg
);
9760 printf ("$%d", sreg
);
9764 printf ("0x%08lx", oc
& 0x1ffffff);
9776 printf ("$%d", shamt
);
9787 printf (_("%08lx UNDEFINED\n"), oc
);
9798 name
= input_line_pointer
;
9799 c
= get_symbol_end ();
9800 p
= (symbolS
*) symbol_find_or_make (name
);
9801 *input_line_pointer
= c
;
9805 /* Align the current frag to a given power of two. The MIPS assembler
9806 also automatically adjusts any preceding label. */
9809 mips_align (to
, fill
, label
)
9814 mips_emit_delays (false);
9815 frag_align (to
, fill
, 0);
9816 record_alignment (now_seg
, to
);
9819 assert (S_GET_SEGMENT (label
) == now_seg
);
9820 symbol_set_frag (label
, frag_now
);
9821 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9825 /* Align to a given power of two. .align 0 turns off the automatic
9826 alignment used by the data creating pseudo-ops. */
9833 register long temp_fill
;
9834 long max_alignment
= 15;
9838 o Note that the assembler pulls down any immediately preceeding label
9839 to the aligned address.
9840 o It's not documented but auto alignment is reinstated by
9841 a .align pseudo instruction.
9842 o Note also that after auto alignment is turned off the mips assembler
9843 issues an error on attempt to assemble an improperly aligned data item.
9848 temp
= get_absolute_expression ();
9849 if (temp
> max_alignment
)
9850 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9853 as_warn (_("Alignment negative: 0 assumed."));
9856 if (*input_line_pointer
== ',')
9858 input_line_pointer
++;
9859 temp_fill
= get_absolute_expression ();
9866 mips_align (temp
, (int) temp_fill
,
9867 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9874 demand_empty_rest_of_line ();
9878 mips_flush_pending_output ()
9880 mips_emit_delays (false);
9881 mips_clear_insn_labels ();
9890 /* When generating embedded PIC code, we only use the .text, .lit8,
9891 .sdata and .sbss sections. We change the .data and .rdata
9892 pseudo-ops to use .sdata. */
9893 if (mips_pic
== EMBEDDED_PIC
9894 && (sec
== 'd' || sec
== 'r'))
9898 /* The ELF backend needs to know that we are changing sections, so
9899 that .previous works correctly. We could do something like check
9900 for a obj_section_change_hook macro, but that might be confusing
9901 as it would not be appropriate to use it in the section changing
9902 functions in read.c, since obj-elf.c intercepts those. FIXME:
9903 This should be cleaner, somehow. */
9904 obj_elf_section_change_hook ();
9907 mips_emit_delays (false);
9917 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9918 demand_empty_rest_of_line ();
9922 if (USE_GLOBAL_POINTER_OPT
)
9924 seg
= subseg_new (RDATA_SECTION_NAME
,
9925 (subsegT
) get_absolute_expression ());
9926 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9928 bfd_set_section_flags (stdoutput
, seg
,
9934 if (strcmp (TARGET_OS
, "elf") != 0)
9935 bfd_set_section_alignment (stdoutput
, seg
, 4);
9937 demand_empty_rest_of_line ();
9941 as_bad (_("No read only data section in this object file format"));
9942 demand_empty_rest_of_line ();
9948 if (USE_GLOBAL_POINTER_OPT
)
9950 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9951 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9953 bfd_set_section_flags (stdoutput
, seg
,
9954 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9956 if (strcmp (TARGET_OS
, "elf") != 0)
9957 bfd_set_section_alignment (stdoutput
, seg
, 4);
9959 demand_empty_rest_of_line ();
9964 as_bad (_("Global pointers not supported; recompile -G 0"));
9965 demand_empty_rest_of_line ();
9974 mips_enable_auto_align ()
9985 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9986 mips_emit_delays (false);
9987 if (log_size
> 0 && auto_align
)
9988 mips_align (log_size
, 0, label
);
9989 mips_clear_insn_labels ();
9990 cons (1 << log_size
);
9999 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10001 mips_emit_delays (false);
10006 mips_align (3, 0, label
);
10008 mips_align (2, 0, label
);
10011 mips_clear_insn_labels ();
10016 /* Handle .globl. We need to override it because on Irix 5 you are
10019 where foo is an undefined symbol, to mean that foo should be
10020 considered to be the address of a function. */
10031 name
= input_line_pointer
;
10032 c
= get_symbol_end ();
10033 symbolP
= symbol_find_or_make (name
);
10034 *input_line_pointer
= c
;
10035 SKIP_WHITESPACE ();
10037 /* On Irix 5, every global symbol that is not explicitly labelled as
10038 being a function is apparently labelled as being an object. */
10041 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10046 secname
= input_line_pointer
;
10047 c
= get_symbol_end ();
10048 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10050 as_bad (_("%s: no such section"), secname
);
10051 *input_line_pointer
= c
;
10053 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10054 flag
= BSF_FUNCTION
;
10057 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10059 S_SET_EXTERNAL (symbolP
);
10060 demand_empty_rest_of_line ();
10070 opt
= input_line_pointer
;
10071 c
= get_symbol_end ();
10075 /* FIXME: What does this mean? */
10077 else if (strncmp (opt
, "pic", 3) == 0)
10081 i
= atoi (opt
+ 3);
10085 mips_pic
= SVR4_PIC
;
10087 as_bad (_(".option pic%d not supported"), i
);
10089 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10091 if (g_switch_seen
&& g_switch_value
!= 0)
10092 as_warn (_("-G may not be used with SVR4 PIC code"));
10093 g_switch_value
= 0;
10094 bfd_set_gp_size (stdoutput
, 0);
10098 as_warn (_("Unrecognized option \"%s\""), opt
);
10100 *input_line_pointer
= c
;
10101 demand_empty_rest_of_line ();
10104 /* This structure is used to hold a stack of .set values. */
10106 struct mips_option_stack
10108 struct mips_option_stack
*next
;
10109 struct mips_set_options options
;
10112 static struct mips_option_stack
*mips_opts_stack
;
10114 /* Handle the .set pseudo-op. */
10120 char *name
= input_line_pointer
, ch
;
10122 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10123 input_line_pointer
++;
10124 ch
= *input_line_pointer
;
10125 *input_line_pointer
= '\0';
10127 if (strcmp (name
, "reorder") == 0)
10129 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10131 /* If we still have pending nops, we can discard them. The
10132 usual nop handling will insert any that are still
10134 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10135 * (mips_opts
.mips16
? 2 : 4));
10136 prev_nop_frag
= NULL
;
10138 mips_opts
.noreorder
= 0;
10140 else if (strcmp (name
, "noreorder") == 0)
10142 mips_emit_delays (true);
10143 mips_opts
.noreorder
= 1;
10144 mips_any_noreorder
= 1;
10146 else if (strcmp (name
, "at") == 0)
10148 mips_opts
.noat
= 0;
10150 else if (strcmp (name
, "noat") == 0)
10152 mips_opts
.noat
= 1;
10154 else if (strcmp (name
, "macro") == 0)
10156 mips_opts
.warn_about_macros
= 0;
10158 else if (strcmp (name
, "nomacro") == 0)
10160 if (mips_opts
.noreorder
== 0)
10161 as_bad (_("`noreorder' must be set before `nomacro'"));
10162 mips_opts
.warn_about_macros
= 1;
10164 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10166 mips_opts
.nomove
= 0;
10168 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10170 mips_opts
.nomove
= 1;
10172 else if (strcmp (name
, "bopt") == 0)
10174 mips_opts
.nobopt
= 0;
10176 else if (strcmp (name
, "nobopt") == 0)
10178 mips_opts
.nobopt
= 1;
10180 else if (strcmp (name
, "mips16") == 0
10181 || strcmp (name
, "MIPS-16") == 0)
10182 mips_opts
.mips16
= 1;
10183 else if (strcmp (name
, "nomips16") == 0
10184 || strcmp (name
, "noMIPS-16") == 0)
10185 mips_opts
.mips16
= 0;
10186 else if (strncmp (name
, "mips", 4) == 0)
10190 /* Permit the user to change the ISA on the fly. Needless to
10191 say, misuse can cause serious problems. */
10192 isa
= atoi (name
+ 4);
10194 mips_opts
.isa
= file_mips_isa
;
10195 else if (isa
< 1 || isa
> 4)
10196 as_bad (_("unknown ISA level"));
10198 mips_opts
.isa
= isa
;
10200 else if (strcmp (name
, "autoextend") == 0)
10201 mips_opts
.noautoextend
= 0;
10202 else if (strcmp (name
, "noautoextend") == 0)
10203 mips_opts
.noautoextend
= 1;
10204 else if (strcmp (name
, "push") == 0)
10206 struct mips_option_stack
*s
;
10208 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10209 s
->next
= mips_opts_stack
;
10210 s
->options
= mips_opts
;
10211 mips_opts_stack
= s
;
10213 else if (strcmp (name
, "pop") == 0)
10215 struct mips_option_stack
*s
;
10217 s
= mips_opts_stack
;
10219 as_bad (_(".set pop with no .set push"));
10222 /* If we're changing the reorder mode we need to handle
10223 delay slots correctly. */
10224 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10225 mips_emit_delays (true);
10226 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10228 if (prev_nop_frag
!= NULL
)
10230 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10231 * (mips_opts
.mips16
? 2 : 4));
10232 prev_nop_frag
= NULL
;
10236 mips_opts
= s
->options
;
10237 mips_opts_stack
= s
->next
;
10243 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10245 *input_line_pointer
= ch
;
10246 demand_empty_rest_of_line ();
10249 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10250 .option pic2. It means to generate SVR4 PIC calls. */
10253 s_abicalls (ignore
)
10256 mips_pic
= SVR4_PIC
;
10257 if (USE_GLOBAL_POINTER_OPT
)
10259 if (g_switch_seen
&& g_switch_value
!= 0)
10260 as_warn (_("-G may not be used with SVR4 PIC code"));
10261 g_switch_value
= 0;
10263 bfd_set_gp_size (stdoutput
, 0);
10264 demand_empty_rest_of_line ();
10267 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10268 PIC code. It sets the $gp register for the function based on the
10269 function address, which is in the register named in the argument.
10270 This uses a relocation against _gp_disp, which is handled specially
10271 by the linker. The result is:
10272 lui $gp,%hi(_gp_disp)
10273 addiu $gp,$gp,%lo(_gp_disp)
10274 addu $gp,$gp,.cpload argument
10275 The .cpload argument is normally $25 == $t9. */
10284 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10285 if (mips_pic
!= SVR4_PIC
)
10291 /* .cpload should be a in .set noreorder section. */
10292 if (mips_opts
.noreorder
== 0)
10293 as_warn (_(".cpload not in noreorder section"));
10295 ex
.X_op
= O_symbol
;
10296 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10297 ex
.X_op_symbol
= NULL
;
10298 ex
.X_add_number
= 0;
10300 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10301 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10303 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10304 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10305 (int) BFD_RELOC_LO16
);
10307 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10308 GP
, GP
, tc_get_register (0));
10310 demand_empty_rest_of_line ();
10313 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10314 offset from $sp. The offset is remembered, and after making a PIC
10315 call $gp is restored from that location. */
10318 s_cprestore (ignore
)
10324 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10325 if (mips_pic
!= SVR4_PIC
)
10331 mips_cprestore_offset
= get_absolute_expression ();
10333 ex
.X_op
= O_constant
;
10334 ex
.X_add_symbol
= NULL
;
10335 ex
.X_op_symbol
= NULL
;
10336 ex
.X_add_number
= mips_cprestore_offset
;
10338 macro_build ((char *) NULL
, &icnt
, &ex
,
10339 ((bfd_arch_bits_per_address (stdoutput
) == 32
10340 || mips_opts
.isa
< 3)
10342 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10344 demand_empty_rest_of_line ();
10347 /* Handle the .gpword pseudo-op. This is used when generating PIC
10348 code. It generates a 32 bit GP relative reloc. */
10358 /* When not generating PIC code, this is treated as .word. */
10359 if (mips_pic
!= SVR4_PIC
)
10365 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10366 mips_emit_delays (true);
10368 mips_align (2, 0, label
);
10369 mips_clear_insn_labels ();
10373 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10375 as_bad (_("Unsupported use of .gpword"));
10376 ignore_rest_of_line ();
10380 md_number_to_chars (p
, (valueT
) 0, 4);
10381 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10382 BFD_RELOC_MIPS_GPREL32
);
10384 demand_empty_rest_of_line ();
10387 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10388 tables in SVR4 PIC code. */
10397 /* This is ignored when not generating SVR4 PIC code. */
10398 if (mips_pic
!= SVR4_PIC
)
10404 /* Add $gp to the register named as an argument. */
10405 reg
= tc_get_register (0);
10406 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10407 ((bfd_arch_bits_per_address (stdoutput
) == 32
10408 || mips_opts
.isa
< 3)
10409 ? "addu" : "daddu"),
10410 "d,v,t", reg
, reg
, GP
);
10412 demand_empty_rest_of_line ();
10415 /* Handle the .insn pseudo-op. This marks instruction labels in
10416 mips16 mode. This permits the linker to handle them specially,
10417 such as generating jalx instructions when needed. We also make
10418 them odd for the duration of the assembly, in order to generate the
10419 right sort of code. We will make them even in the adjust_symtab
10420 routine, while leaving them marked. This is convenient for the
10421 debugger and the disassembler. The linker knows to make them odd
10428 if (mips_opts
.mips16
)
10429 mips16_mark_labels ();
10431 demand_empty_rest_of_line ();
10434 /* Handle a .stabn directive. We need these in order to mark a label
10435 as being a mips16 text label correctly. Sometimes the compiler
10436 will emit a label, followed by a .stabn, and then switch sections.
10437 If the label and .stabn are in mips16 mode, then the label is
10438 really a mips16 text label. */
10444 if (type
== 'n' && mips_opts
.mips16
)
10445 mips16_mark_labels ();
10450 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10454 s_mips_weakext (ignore
)
10462 name
= input_line_pointer
;
10463 c
= get_symbol_end ();
10464 symbolP
= symbol_find_or_make (name
);
10465 S_SET_WEAK (symbolP
);
10466 *input_line_pointer
= c
;
10468 SKIP_WHITESPACE ();
10470 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10472 if (S_IS_DEFINED (symbolP
))
10474 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10475 S_GET_NAME (symbolP
));
10476 ignore_rest_of_line ();
10480 if (*input_line_pointer
== ',')
10482 ++input_line_pointer
;
10483 SKIP_WHITESPACE ();
10487 if (exp
.X_op
!= O_symbol
)
10489 as_bad ("bad .weakext directive");
10490 ignore_rest_of_line();
10493 symbol_set_value_expression (symbolP
, &exp
);
10496 demand_empty_rest_of_line ();
10499 /* Parse a register string into a number. Called from the ECOFF code
10500 to parse .frame. The argument is non-zero if this is the frame
10501 register, so that we can record it in mips_frame_reg. */
10504 tc_get_register (frame
)
10509 SKIP_WHITESPACE ();
10510 if (*input_line_pointer
++ != '$')
10512 as_warn (_("expected `$'"));
10515 else if (isdigit ((unsigned char) *input_line_pointer
))
10517 reg
= get_absolute_expression ();
10518 if (reg
< 0 || reg
>= 32)
10520 as_warn (_("Bad register number"));
10526 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10528 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10530 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10532 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10536 as_warn (_("Unrecognized register name"));
10539 input_line_pointer
+= 2;
10542 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10547 md_section_align (seg
, addr
)
10551 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10554 /* We don't need to align ELF sections to the full alignment.
10555 However, Irix 5 may prefer that we align them at least to a 16
10556 byte boundary. We don't bother to align the sections if we are
10557 targeted for an embedded system. */
10558 if (strcmp (TARGET_OS
, "elf") == 0)
10564 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10567 /* Utility routine, called from above as well. If called while the
10568 input file is still being read, it's only an approximation. (For
10569 example, a symbol may later become defined which appeared to be
10570 undefined earlier.) */
10573 nopic_need_relax (sym
, before_relaxing
)
10575 int before_relaxing
;
10580 if (USE_GLOBAL_POINTER_OPT
)
10582 const char *symname
;
10585 /* Find out whether this symbol can be referenced off the GP
10586 register. It can be if it is smaller than the -G size or if
10587 it is in the .sdata or .sbss section. Certain symbols can
10588 not be referenced off the GP, although it appears as though
10590 symname
= S_GET_NAME (sym
);
10591 if (symname
!= (const char *) NULL
10592 && (strcmp (symname
, "eprol") == 0
10593 || strcmp (symname
, "etext") == 0
10594 || strcmp (symname
, "_gp") == 0
10595 || strcmp (symname
, "edata") == 0
10596 || strcmp (symname
, "_fbss") == 0
10597 || strcmp (symname
, "_fdata") == 0
10598 || strcmp (symname
, "_ftext") == 0
10599 || strcmp (symname
, "end") == 0
10600 || strcmp (symname
, "_gp_disp") == 0))
10602 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10604 #ifndef NO_ECOFF_DEBUGGING
10605 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10606 && (symbol_get_obj (sym
)->ecoff_extern_size
10607 <= g_switch_value
))
10609 /* We must defer this decision until after the whole
10610 file has been read, since there might be a .extern
10611 after the first use of this symbol. */
10612 || (before_relaxing
10613 #ifndef NO_ECOFF_DEBUGGING
10614 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10616 && S_GET_VALUE (sym
) == 0)
10617 || (S_GET_VALUE (sym
) != 0
10618 && S_GET_VALUE (sym
) <= g_switch_value
)))
10622 const char *segname
;
10624 segname
= segment_name (S_GET_SEGMENT (sym
));
10625 assert (strcmp (segname
, ".lit8") != 0
10626 && strcmp (segname
, ".lit4") != 0);
10627 change
= (strcmp (segname
, ".sdata") != 0
10628 && strcmp (segname
, ".sbss") != 0);
10633 /* We are not optimizing for the GP register. */
10637 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10638 extended opcode. SEC is the section the frag is in. */
10641 mips16_extended_frag (fragp
, sec
, stretch
)
10647 register const struct mips16_immed_operand
*op
;
10649 int mintiny
, maxtiny
;
10652 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10654 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10657 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10658 op
= mips16_immed_operands
;
10659 while (op
->type
!= type
)
10662 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10667 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10670 maxtiny
= 1 << op
->nbits
;
10675 maxtiny
= (1 << op
->nbits
) - 1;
10680 mintiny
= - (1 << (op
->nbits
- 1));
10681 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10684 /* We can't always call S_GET_VALUE here, because we don't want to
10685 lock in a particular frag address. */
10686 if (symbol_constant_p (fragp
->fr_symbol
))
10688 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10689 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10690 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10692 else if (symbol_equated_p (fragp
->fr_symbol
)
10693 && (symbol_constant_p
10694 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10698 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10699 val
= (S_GET_VALUE (eqsym
)
10700 + symbol_get_frag (eqsym
)->fr_address
10701 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10702 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10703 symsec
= S_GET_SEGMENT (eqsym
);
10712 /* We won't have the section when we are called from
10713 mips_relax_frag. However, we will always have been called
10714 from md_estimate_size_before_relax first. If this is a
10715 branch to a different section, we mark it as such. If SEC is
10716 NULL, and the frag is not marked, then it must be a branch to
10717 the same section. */
10720 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10727 fragp
->fr_subtype
=
10728 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10730 /* FIXME: We should support this, and let the linker
10731 catch branches and loads that are out of range. */
10732 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10733 _("unsupported PC relative reference to different section"));
10739 /* In this case, we know for sure that the symbol fragment is in
10740 the same section. If the fr_address of the symbol fragment
10741 is greater then the address of this fragment we want to add
10742 in STRETCH in order to get a better estimate of the address.
10743 This particularly matters because of the shift bits. */
10745 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10746 >= fragp
->fr_address
))
10750 /* Adjust stretch for any alignment frag. Note that if have
10751 been expanding the earlier code, the symbol may be
10752 defined in what appears to be an earlier frag. FIXME:
10753 This doesn't handle the fr_subtype field, which specifies
10754 a maximum number of bytes to skip when doing an
10757 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10760 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10763 stretch
= - ((- stretch
)
10764 & ~ ((1 << (int) f
->fr_offset
) - 1));
10766 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10775 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10777 /* The base address rules are complicated. The base address of
10778 a branch is the following instruction. The base address of a
10779 PC relative load or add is the instruction itself, but if it
10780 is in a delay slot (in which case it can not be extended) use
10781 the address of the instruction whose delay slot it is in. */
10782 if (type
== 'p' || type
== 'q')
10786 /* If we are currently assuming that this frag should be
10787 extended, then, the current address is two bytes
10789 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10792 /* Ignore the low bit in the target, since it will be set
10793 for a text label. */
10794 if ((val
& 1) != 0)
10797 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10799 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10802 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10804 /* Branch offsets have an implicit 0 in the lowest bit. */
10805 if (type
== 'p' || type
== 'q')
10808 /* If any of the shifted bits are set, we must use an extended
10809 opcode. If the address depends on the size of this
10810 instruction, this can lead to a loop, so we arrange to always
10811 use an extended opcode. We only check this when we are in
10812 the main relaxation loop, when SEC is NULL. */
10813 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10815 fragp
->fr_subtype
=
10816 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10820 /* If we are about to mark a frag as extended because the value
10821 is precisely maxtiny + 1, then there is a chance of an
10822 infinite loop as in the following code:
10827 In this case when the la is extended, foo is 0x3fc bytes
10828 away, so the la can be shrunk, but then foo is 0x400 away, so
10829 the la must be extended. To avoid this loop, we mark the
10830 frag as extended if it was small, and is about to become
10831 extended with a value of maxtiny + 1. */
10832 if (val
== ((maxtiny
+ 1) << op
->shift
)
10833 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10836 fragp
->fr_subtype
=
10837 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10841 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10842 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10844 if ((val
& ((1 << op
->shift
) - 1)) != 0
10845 || val
< (mintiny
<< op
->shift
)
10846 || val
> (maxtiny
<< op
->shift
))
10852 /* Estimate the size of a frag before relaxing. Unless this is the
10853 mips16, we are not really relaxing here, and the final size is
10854 encoded in the subtype information. For the mips16, we have to
10855 decide whether we are using an extended opcode or not. */
10859 md_estimate_size_before_relax (fragp
, segtype
)
10865 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10867 if (mips16_extended_frag (fragp
, segtype
, 0))
10869 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10874 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10879 if (mips_pic
== NO_PIC
)
10881 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10883 else if (mips_pic
== SVR4_PIC
)
10888 sym
= fragp
->fr_symbol
;
10890 /* Handle the case of a symbol equated to another symbol. */
10891 while (symbol_equated_p (sym
)
10892 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10896 /* It's possible to get a loop here in a badly written
10898 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
10904 symsec
= S_GET_SEGMENT (sym
);
10906 /* This must duplicate the test in adjust_reloc_syms. */
10907 change
= (symsec
!= &bfd_und_section
10908 && symsec
!= &bfd_abs_section
10909 && ! bfd_is_com_section (symsec
));
10916 /* Record the offset to the first reloc in the fr_opcode field.
10917 This lets md_convert_frag and tc_gen_reloc know that the code
10918 must be expanded. */
10919 fragp
->fr_opcode
= (fragp
->fr_literal
10921 - RELAX_OLD (fragp
->fr_subtype
)
10922 + RELAX_RELOC1 (fragp
->fr_subtype
));
10923 /* FIXME: This really needs as_warn_where. */
10924 if (RELAX_WARN (fragp
->fr_subtype
))
10925 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
10931 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10934 /* This is called to see whether a reloc against a defined symbol
10935 should be converted into a reloc against a section. Don't adjust
10936 MIPS16 jump relocations, so we don't have to worry about the format
10937 of the offset in the .o file. Don't adjust relocations against
10938 mips16 symbols, so that the linker can find them if it needs to set
10942 mips_fix_adjustable (fixp
)
10945 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10947 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10948 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10950 if (fixp
->fx_addsy
== NULL
)
10953 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10954 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10955 && fixp
->fx_subsy
== NULL
)
10961 /* Translate internal representation of relocation info to BFD target
10965 tc_gen_reloc (section
, fixp
)
10969 static arelent
*retval
[4];
10971 bfd_reloc_code_real_type code
;
10973 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10976 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10977 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10978 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10980 if (mips_pic
== EMBEDDED_PIC
10981 && SWITCH_TABLE (fixp
))
10983 /* For a switch table entry we use a special reloc. The addend
10984 is actually the difference between the reloc address and the
10986 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10987 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10988 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
10989 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10991 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10993 /* We use a special addend for an internal RELLO reloc. */
10994 if (symbol_section_p (fixp
->fx_addsy
))
10995 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10997 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10999 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11001 assert (fixp
->fx_next
!= NULL
11002 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11003 /* We use a special addend for an internal RELHI reloc. The
11004 reloc is relative to the RELLO; adjust the addend
11006 if (symbol_section_p (fixp
->fx_addsy
))
11007 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11008 + fixp
->fx_next
->fx_where
11009 - S_GET_VALUE (fixp
->fx_subsy
));
11011 reloc
->addend
= (fixp
->fx_addnumber
11012 + fixp
->fx_next
->fx_frag
->fr_address
11013 + fixp
->fx_next
->fx_where
);
11015 else if (fixp
->fx_pcrel
== 0)
11016 reloc
->addend
= fixp
->fx_addnumber
;
11019 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11020 /* A gruesome hack which is a result of the gruesome gas reloc
11022 reloc
->addend
= reloc
->address
;
11024 reloc
->addend
= -reloc
->address
;
11027 /* If this is a variant frag, we may need to adjust the existing
11028 reloc and generate a new one. */
11029 if (fixp
->fx_frag
->fr_opcode
!= NULL
11030 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11031 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11032 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11033 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11034 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11035 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11036 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11040 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11042 /* If this is not the last reloc in this frag, then we have two
11043 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11044 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11045 the second one handle all of them. */
11046 if (fixp
->fx_next
!= NULL
11047 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11049 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11050 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11051 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11052 && (fixp
->fx_next
->fx_r_type
11053 == BFD_RELOC_MIPS_GOT_LO16
))
11054 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11055 && (fixp
->fx_next
->fx_r_type
11056 == BFD_RELOC_MIPS_CALL_LO16
)));
11061 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11062 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11063 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11065 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11066 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11067 reloc2
->address
= (reloc
->address
11068 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11069 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11070 reloc2
->addend
= fixp
->fx_addnumber
;
11071 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11072 assert (reloc2
->howto
!= NULL
);
11074 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11078 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11081 reloc3
->address
+= 4;
11084 if (mips_pic
== NO_PIC
)
11086 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11087 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11089 else if (mips_pic
== SVR4_PIC
)
11091 switch (fixp
->fx_r_type
)
11095 case BFD_RELOC_MIPS_GOT16
:
11097 case BFD_RELOC_MIPS_CALL16
:
11098 case BFD_RELOC_MIPS_GOT_LO16
:
11099 case BFD_RELOC_MIPS_CALL_LO16
:
11100 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11108 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11109 to be used in the relocation's section offset. */
11110 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11112 reloc
->address
= reloc
->addend
;
11116 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11117 fixup_segment converted a non-PC relative reloc into a PC
11118 relative reloc. In such a case, we need to convert the reloc
11120 code
= fixp
->fx_r_type
;
11121 if (fixp
->fx_pcrel
)
11126 code
= BFD_RELOC_8_PCREL
;
11129 code
= BFD_RELOC_16_PCREL
;
11132 code
= BFD_RELOC_32_PCREL
;
11135 code
= BFD_RELOC_64_PCREL
;
11137 case BFD_RELOC_8_PCREL
:
11138 case BFD_RELOC_16_PCREL
:
11139 case BFD_RELOC_32_PCREL
:
11140 case BFD_RELOC_64_PCREL
:
11141 case BFD_RELOC_16_PCREL_S2
:
11142 case BFD_RELOC_PCREL_HI16_S
:
11143 case BFD_RELOC_PCREL_LO16
:
11146 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11147 _("Cannot make %s relocation PC relative"),
11148 bfd_get_reloc_code_name (code
));
11152 /* To support a PC relative reloc when generating embedded PIC code
11153 for ECOFF, we use a Cygnus extension. We check for that here to
11154 make sure that we don't let such a reloc escape normally. */
11155 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11156 && code
== BFD_RELOC_16_PCREL_S2
11157 && mips_pic
!= EMBEDDED_PIC
)
11158 reloc
->howto
= NULL
;
11160 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11162 if (reloc
->howto
== NULL
)
11164 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11165 _("Can not represent %s relocation in this object file format"),
11166 bfd_get_reloc_code_name (code
));
11173 /* Relax a machine dependent frag. This returns the amount by which
11174 the current size of the frag should change. */
11177 mips_relax_frag (fragp
, stretch
)
11181 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11184 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11186 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11188 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11193 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11195 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11202 /* Convert a machine dependent frag. */
11205 md_convert_frag (abfd
, asec
, fragp
)
11213 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11216 register const struct mips16_immed_operand
*op
;
11217 boolean small
, ext
;
11220 unsigned long insn
;
11221 boolean use_extend
;
11222 unsigned short extend
;
11224 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11225 op
= mips16_immed_operands
;
11226 while (op
->type
!= type
)
11229 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11240 resolve_symbol_value (fragp
->fr_symbol
, 1);
11241 val
= S_GET_VALUE (fragp
->fr_symbol
);
11246 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11248 /* The rules for the base address of a PC relative reloc are
11249 complicated; see mips16_extended_frag. */
11250 if (type
== 'p' || type
== 'q')
11255 /* Ignore the low bit in the target, since it will be
11256 set for a text label. */
11257 if ((val
& 1) != 0)
11260 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11262 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11265 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11268 /* Make sure the section winds up with the alignment we have
11271 record_alignment (asec
, op
->shift
);
11275 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11276 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11277 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11278 _("extended instruction in delay slot"));
11280 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11282 if (target_big_endian
)
11283 insn
= bfd_getb16 (buf
);
11285 insn
= bfd_getl16 (buf
);
11287 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11288 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11289 small
, ext
, &insn
, &use_extend
, &extend
);
11293 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11294 fragp
->fr_fix
+= 2;
11298 md_number_to_chars (buf
, insn
, 2);
11299 fragp
->fr_fix
+= 2;
11304 if (fragp
->fr_opcode
== NULL
)
11307 old
= RELAX_OLD (fragp
->fr_subtype
);
11308 new = RELAX_NEW (fragp
->fr_subtype
);
11309 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11312 memcpy (fixptr
- old
, fixptr
, new);
11314 fragp
->fr_fix
+= new - old
;
11320 /* This function is called after the relocs have been generated.
11321 We've been storing mips16 text labels as odd. Here we convert them
11322 back to even for the convenience of the debugger. */
11325 mips_frob_file_after_relocs ()
11328 unsigned int count
, i
;
11330 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11333 syms
= bfd_get_outsymbols (stdoutput
);
11334 count
= bfd_get_symcount (stdoutput
);
11335 for (i
= 0; i
< count
; i
++, syms
++)
11337 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11338 && ((*syms
)->value
& 1) != 0)
11340 (*syms
)->value
&= ~1;
11341 /* If the symbol has an odd size, it was probably computed
11342 incorrectly, so adjust that as well. */
11343 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11344 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11351 /* This function is called whenever a label is defined. It is used
11352 when handling branch delays; if a branch has a label, we assume we
11353 can not move it. */
11356 mips_define_label (sym
)
11359 struct insn_label_list
*l
;
11361 if (free_insn_labels
== NULL
)
11362 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11365 l
= free_insn_labels
;
11366 free_insn_labels
= l
->next
;
11370 l
->next
= insn_labels
;
11374 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11376 /* Some special processing for a MIPS ELF file. */
11379 mips_elf_final_processing ()
11381 /* Write out the register information. */
11386 s
.ri_gprmask
= mips_gprmask
;
11387 s
.ri_cprmask
[0] = mips_cprmask
[0];
11388 s
.ri_cprmask
[1] = mips_cprmask
[1];
11389 s
.ri_cprmask
[2] = mips_cprmask
[2];
11390 s
.ri_cprmask
[3] = mips_cprmask
[3];
11391 /* The gp_value field is set by the MIPS ELF backend. */
11393 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11394 ((Elf32_External_RegInfo
*)
11395 mips_regmask_frag
));
11399 Elf64_Internal_RegInfo s
;
11401 s
.ri_gprmask
= mips_gprmask
;
11403 s
.ri_cprmask
[0] = mips_cprmask
[0];
11404 s
.ri_cprmask
[1] = mips_cprmask
[1];
11405 s
.ri_cprmask
[2] = mips_cprmask
[2];
11406 s
.ri_cprmask
[3] = mips_cprmask
[3];
11407 /* The gp_value field is set by the MIPS ELF backend. */
11409 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11410 ((Elf64_External_RegInfo
*)
11411 mips_regmask_frag
));
11414 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11415 sort of BFD interface for this. */
11416 if (mips_any_noreorder
)
11417 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11418 if (mips_pic
!= NO_PIC
)
11419 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11421 /* Set the MIPS ELF ABI flags. */
11422 if (mips_abi_string
== 0)
11424 else if (strcmp (mips_abi_string
,"32") == 0)
11425 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11426 else if (strcmp (mips_abi_string
,"o64") == 0)
11427 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11428 else if (strcmp (mips_abi_string
,"eabi") == 0)
11431 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11433 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11436 if (mips_32bitmode
)
11437 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11440 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11442 typedef struct proc
11445 unsigned long reg_mask
;
11446 unsigned long reg_offset
;
11447 unsigned long fpreg_mask
;
11448 unsigned long fpreg_offset
;
11449 unsigned long frame_offset
;
11450 unsigned long frame_reg
;
11451 unsigned long pc_reg
;
11455 static procS cur_proc
;
11456 static procS
*cur_proc_ptr
;
11457 static int numprocs
;
11467 /* check for premature end, nesting errors, etc */
11469 as_warn (_("missing `.end' at end of assembly"));
11478 if (*input_line_pointer
== '-')
11480 ++input_line_pointer
;
11483 if (!isdigit ((unsigned char) *input_line_pointer
))
11484 as_bad (_("Expected simple number."));
11485 if (input_line_pointer
[0] == '0')
11487 if (input_line_pointer
[1] == 'x')
11489 input_line_pointer
+= 2;
11490 while (isxdigit ((unsigned char) *input_line_pointer
))
11493 val
|= hex_value (*input_line_pointer
++);
11495 return negative
? -val
: val
;
11499 ++input_line_pointer
;
11500 while (isdigit ((unsigned char) *input_line_pointer
))
11503 val
|= *input_line_pointer
++ - '0';
11505 return negative
? -val
: val
;
11508 if (!isdigit ((unsigned char) *input_line_pointer
))
11510 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11511 *input_line_pointer
, *input_line_pointer
);
11512 as_warn (_("Invalid number"));
11515 while (isdigit ((unsigned char) *input_line_pointer
))
11518 val
+= *input_line_pointer
++ - '0';
11520 return negative
? -val
: val
;
11523 /* The .file directive; just like the usual .file directive, but there
11524 is an initial number which is the ECOFF file index. */
11532 line
= get_number ();
11537 /* The .end directive. */
11546 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11549 demand_empty_rest_of_line ();
11554 #ifdef BFD_ASSEMBLER
11555 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11560 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11567 as_warn (_(".end not in text section"));
11571 as_warn (_(".end directive without a preceding .ent directive."));
11572 demand_empty_rest_of_line ();
11578 assert (S_GET_NAME (p
));
11579 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11580 as_warn (_(".end symbol does not match .ent symbol."));
11583 as_warn (_(".end directive missing or unknown symbol"));
11585 #ifdef MIPS_STABS_ELF
11587 segT saved_seg
= now_seg
;
11588 subsegT saved_subseg
= now_subseg
;
11589 fragS
*saved_frag
= frag_now
;
11595 dot
= frag_now_fix ();
11597 #ifdef md_flush_pending_output
11598 md_flush_pending_output ();
11602 subseg_set (pdr_seg
, 0);
11604 /* Write the symbol */
11605 exp
.X_op
= O_symbol
;
11606 exp
.X_add_symbol
= p
;
11607 exp
.X_add_number
= 0;
11608 emit_expr (&exp
, 4);
11610 fragp
= frag_more (7*4);
11612 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11613 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11614 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11615 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11616 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11617 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11618 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11620 subseg_set (saved_seg
, saved_subseg
);
11624 cur_proc_ptr
= NULL
;
11627 /* The .aent and .ent directives. */
11637 symbolP
= get_symbol ();
11638 if (*input_line_pointer
== ',')
11639 input_line_pointer
++;
11640 SKIP_WHITESPACE ();
11641 if (isdigit ((unsigned char) *input_line_pointer
)
11642 || *input_line_pointer
== '-')
11643 number
= get_number ();
11645 #ifdef BFD_ASSEMBLER
11646 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11651 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11658 as_warn (_(".ent or .aent not in text section."));
11660 if (!aent
&& cur_proc_ptr
)
11661 as_warn (_("missing `.end'"));
11665 cur_proc_ptr
= &cur_proc
;
11666 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11668 cur_proc_ptr
->isym
= symbolP
;
11670 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11675 demand_empty_rest_of_line ();
11678 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11679 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11680 s_mips_frame is used so that we can set the PDR information correctly.
11681 We can't use the ecoff routines because they make reference to the ecoff
11682 symbol table (in the mdebug section). */
11685 s_mips_frame (ignore
)
11688 #ifdef MIPS_STABS_ELF
11692 if (cur_proc_ptr
== (procS
*) NULL
)
11694 as_warn (_(".frame outside of .ent"));
11695 demand_empty_rest_of_line ();
11699 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11701 SKIP_WHITESPACE ();
11702 if (*input_line_pointer
++ != ','
11703 || get_absolute_expression_and_terminator (&val
) != ',')
11705 as_warn (_("Bad .frame directive"));
11706 --input_line_pointer
;
11707 demand_empty_rest_of_line ();
11711 cur_proc_ptr
->frame_offset
= val
;
11712 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11714 demand_empty_rest_of_line ();
11717 #endif /* MIPS_STABS_ELF */
11720 /* The .fmask and .mask directives. If the mdebug section is present
11721 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11722 embedded targets, s_mips_mask is used so that we can set the PDR
11723 information correctly. We can't use the ecoff routines because they
11724 make reference to the ecoff symbol table (in the mdebug section). */
11727 s_mips_mask (reg_type
)
11730 #ifdef MIPS_STABS_ELF
11733 if (cur_proc_ptr
== (procS
*) NULL
)
11735 as_warn (_(".mask/.fmask outside of .ent"));
11736 demand_empty_rest_of_line ();
11740 if (get_absolute_expression_and_terminator (&mask
) != ',')
11742 as_warn (_("Bad .mask/.fmask directive"));
11743 --input_line_pointer
;
11744 demand_empty_rest_of_line ();
11748 off
= get_absolute_expression ();
11750 if (reg_type
== 'F')
11752 cur_proc_ptr
->fpreg_mask
= mask
;
11753 cur_proc_ptr
->fpreg_offset
= off
;
11757 cur_proc_ptr
->reg_mask
= mask
;
11758 cur_proc_ptr
->reg_offset
= off
;
11761 demand_empty_rest_of_line ();
11763 s_ignore (reg_type
);
11764 #endif /* MIPS_STABS_ELF */
11767 /* The .loc directive. */
11778 assert (now_seg
== text_section
);
11780 lineno
= get_number ();
11781 addroff
= frag_now_fix ();
11783 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11784 S_SET_TYPE (symbolP
, N_SLINE
);
11785 S_SET_OTHER (symbolP
, 0);
11786 S_SET_DESC (symbolP
, lineno
);
11787 symbolP
->sy_segment
= now_seg
;