1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian
;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode
*insn_mo
;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend
;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode
;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p
: 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p
: 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p
: 1;
161 /* The ABI to use. */
172 /* MIPS ABI we are using for this output file. */
173 static enum mips_abi_level mips_abi
= NO_ABI
;
175 /* Whether or not we have code that can call pic code. */
176 int mips_abicalls
= FALSE
;
178 /* Whether or not we have code which can be put into a shared
180 static bfd_boolean mips_in_shared
= TRUE
;
182 /* This is the set of options which may be modified by the .set
183 pseudo-op. We use a struct so that .set push and .set pop are more
186 struct mips_set_options
188 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
189 if it has not been initialized. Changed by `.set mipsN', and the
190 -mipsN command line option, and the default CPU. */
192 /* Enabled Application Specific Extensions (ASEs). These are set to -1
193 if they have not been initialized. Changed by `.set <asename>', by
194 command line options, and based on the default architecture. */
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Non-zero if we should not reorder instructions. Changed by `.set
207 reorder' and `.set noreorder'. */
209 /* Non-zero if we should not permit the register designated "assembler
210 temporary" to be used in instructions. The value is the register
211 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
212 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
214 /* Non-zero if we should warn when a macro instruction expands into
215 more than one machine instruction. Changed by `.set nomacro' and
217 int warn_about_macros
;
218 /* Non-zero if we should not move instructions. Changed by `.set
219 move', `.set volatile', `.set nomove', and `.set novolatile'. */
221 /* Non-zero if we should not optimize branches by moving the target
222 of the branch into the delay slot. Actually, we don't perform
223 this optimization anyhow. Changed by `.set bopt' and `.set
226 /* Non-zero if we should not autoextend mips16 instructions.
227 Changed by `.set autoextend' and `.set noautoextend'. */
229 /* Restrict general purpose registers and floating point registers
230 to 32 bit. This is initially determined when -mgp32 or -mfp32
231 is passed but can changed if the assembler code uses .set mipsN. */
234 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
235 command line option, and the default CPU. */
237 /* True if ".set sym32" is in effect. */
239 /* True if floating-point operations are not allowed. Changed by .set
240 softfloat or .set hardfloat, by command line options -msoft-float or
241 -mhard-float. The default is false. */
242 bfd_boolean soft_float
;
244 /* True if only single-precision floating-point operations are allowed.
245 Changed by .set singlefloat or .set doublefloat, command-line options
246 -msingle-float or -mdouble-float. The default is false. */
247 bfd_boolean single_float
;
250 /* This is the struct we use to hold the current set of options. Note
251 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
252 -1 to indicate that they have not been initialized. */
254 /* True if -mgp32 was passed. */
255 static int file_mips_gp32
= -1;
257 /* True if -mfp32 was passed. */
258 static int file_mips_fp32
= -1;
260 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
261 static int file_mips_soft_float
= 0;
263 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
264 static int file_mips_single_float
= 0;
266 static struct mips_set_options mips_opts
=
268 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
269 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
270 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
271 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
272 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
273 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
276 /* These variables are filled in with the masks of registers used.
277 The object format code reads them and puts them in the appropriate
279 unsigned long mips_gprmask
;
280 unsigned long mips_cprmask
[4];
282 /* MIPS ISA we are using for this output file. */
283 static int file_mips_isa
= ISA_UNKNOWN
;
285 /* True if any MIPS16 code was produced. */
286 static int file_ase_mips16
;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if we want to create R_MIPS_JALR for jalr $25. */
295 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
297 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
298 because there's no place for any addend, the only acceptable
299 expression is a bare symbol. */
300 #define MIPS_JALR_HINT_P(EXPR) \
301 (!HAVE_IN_PLACE_ADDENDS \
302 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
305 /* True if -mips3d was passed or implied by arguments passed on the
306 command line (e.g., by -march). */
307 static int file_ase_mips3d
;
309 /* True if -mdmx was passed or implied by arguments passed on the
310 command line (e.g., by -march). */
311 static int file_ase_mdmx
;
313 /* True if -msmartmips was passed or implied by arguments passed on the
314 command line (e.g., by -march). */
315 static int file_ase_smartmips
;
317 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
318 || mips_opts.isa == ISA_MIPS32R2)
320 /* True if -mdsp was passed or implied by arguments passed on the
321 command line (e.g., by -march). */
322 static int file_ase_dsp
;
324 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
325 || mips_opts.isa == ISA_MIPS64R2)
327 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
329 /* True if -mdspr2 was passed or implied by arguments passed on the
330 command line (e.g., by -march). */
331 static int file_ase_dspr2
;
333 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
334 || mips_opts.isa == ISA_MIPS64R2)
336 /* True if -mmt was passed or implied by arguments passed on the
337 command line (e.g., by -march). */
338 static int file_ase_mt
;
340 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
341 || mips_opts.isa == ISA_MIPS64R2)
343 /* The argument of the -march= flag. The architecture we are assembling. */
344 static int file_mips_arch
= CPU_UNKNOWN
;
345 static const char *mips_arch_string
;
347 /* The argument of the -mtune= flag. The architecture for which we
349 static int mips_tune
= CPU_UNKNOWN
;
350 static const char *mips_tune_string
;
352 /* True when generating 32-bit code for a 64-bit processor. */
353 static int mips_32bitmode
= 0;
355 /* True if the given ABI requires 32-bit registers. */
356 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
358 /* Likewise 64-bit registers. */
359 #define ABI_NEEDS_64BIT_REGS(ABI) \
361 || (ABI) == N64_ABI \
364 /* Return true if ISA supports 64 bit wide gp registers. */
365 #define ISA_HAS_64BIT_REGS(ISA) \
366 ((ISA) == ISA_MIPS3 \
367 || (ISA) == ISA_MIPS4 \
368 || (ISA) == ISA_MIPS5 \
369 || (ISA) == ISA_MIPS64 \
370 || (ISA) == ISA_MIPS64R2)
372 /* Return true if ISA supports 64 bit wide float registers. */
373 #define ISA_HAS_64BIT_FPRS(ISA) \
374 ((ISA) == ISA_MIPS3 \
375 || (ISA) == ISA_MIPS4 \
376 || (ISA) == ISA_MIPS5 \
377 || (ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64 \
379 || (ISA) == ISA_MIPS64R2)
381 /* Return true if ISA supports 64-bit right rotate (dror et al.)
383 #define ISA_HAS_DROR(ISA) \
384 ((ISA) == ISA_MIPS64R2)
386 /* Return true if ISA supports 32-bit right rotate (ror et al.)
388 #define ISA_HAS_ROR(ISA) \
389 ((ISA) == ISA_MIPS32R2 \
390 || (ISA) == ISA_MIPS64R2 \
391 || mips_opts.ase_smartmips)
393 /* Return true if ISA supports single-precision floats in odd registers. */
394 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
395 ((ISA) == ISA_MIPS32 \
396 || (ISA) == ISA_MIPS32R2 \
397 || (ISA) == ISA_MIPS64 \
398 || (ISA) == ISA_MIPS64R2)
400 /* Return true if ISA supports move to/from high part of a 64-bit
401 floating-point register. */
402 #define ISA_HAS_MXHC1(ISA) \
403 ((ISA) == ISA_MIPS32R2 \
404 || (ISA) == ISA_MIPS64R2)
406 #define HAVE_32BIT_GPRS \
407 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
409 #define HAVE_32BIT_FPRS \
410 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
412 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
413 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
415 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
417 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
419 /* True if relocations are stored in-place. */
420 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
422 /* The ABI-derived address size. */
423 #define HAVE_64BIT_ADDRESSES \
424 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
425 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
427 /* The size of symbolic constants (i.e., expressions of the form
428 "SYMBOL" or "SYMBOL + OFFSET"). */
429 #define HAVE_32BIT_SYMBOLS \
430 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
431 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
433 /* Addresses are loaded in different ways, depending on the address size
434 in use. The n32 ABI Documentation also mandates the use of additions
435 with overflow checking, but existing implementations don't follow it. */
436 #define ADDRESS_ADD_INSN \
437 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
439 #define ADDRESS_ADDI_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
442 #define ADDRESS_LOAD_INSN \
443 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
445 #define ADDRESS_STORE_INSN \
446 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
448 /* Return true if the given CPU supports the MIPS16 ASE. */
449 #define CPU_HAS_MIPS16(cpu) \
450 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
451 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
453 /* True if CPU has a dror instruction. */
454 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
456 /* True if CPU has a ror instruction. */
457 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
459 /* True if CPU has seq/sne and seqi/snei instructions. */
460 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
462 /* True if CPU does not implement the all the coprocessor insns. For these
463 CPUs only those COP insns are accepted that are explicitly marked to be
464 available on the CPU. ISA membership for COP insns is ignored. */
465 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
467 /* True if mflo and mfhi can be immediately followed by instructions
468 which write to the HI and LO registers.
470 According to MIPS specifications, MIPS ISAs I, II, and III need
471 (at least) two instructions between the reads of HI/LO and
472 instructions which write them, and later ISAs do not. Contradicting
473 the MIPS specifications, some MIPS IV processor user manuals (e.g.
474 the UM for the NEC Vr5000) document needing the instructions between
475 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
476 MIPS64 and later ISAs to have the interlocks, plus any specific
477 earlier-ISA CPUs for which CPU documentation declares that the
478 instructions are really interlocked. */
479 #define hilo_interlocks \
480 (mips_opts.isa == ISA_MIPS32 \
481 || mips_opts.isa == ISA_MIPS32R2 \
482 || mips_opts.isa == ISA_MIPS64 \
483 || mips_opts.isa == ISA_MIPS64R2 \
484 || mips_opts.arch == CPU_R4010 \
485 || mips_opts.arch == CPU_R10000 \
486 || mips_opts.arch == CPU_R12000 \
487 || mips_opts.arch == CPU_R14000 \
488 || mips_opts.arch == CPU_R16000 \
489 || mips_opts.arch == CPU_RM7000 \
490 || mips_opts.arch == CPU_VR5500 \
493 /* Whether the processor uses hardware interlocks to protect reads
494 from the GPRs after they are loaded from memory, and thus does not
495 require nops to be inserted. This applies to instructions marked
496 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
498 #define gpr_interlocks \
499 (mips_opts.isa != ISA_MIPS1 \
500 || mips_opts.arch == CPU_R3900)
502 /* Whether the processor uses hardware interlocks to avoid delays
503 required by coprocessor instructions, and thus does not require
504 nops to be inserted. This applies to instructions marked
505 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
506 between instructions marked INSN_WRITE_COND_CODE and ones marked
507 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
508 levels I, II, and III. */
509 /* Itbl support may require additional care here. */
510 #define cop_interlocks \
511 ((mips_opts.isa != ISA_MIPS1 \
512 && mips_opts.isa != ISA_MIPS2 \
513 && mips_opts.isa != ISA_MIPS3) \
514 || mips_opts.arch == CPU_R4300 \
517 /* Whether the processor uses hardware interlocks to protect reads
518 from coprocessor registers after they are loaded from memory, and
519 thus does not require nops to be inserted. This applies to
520 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
521 requires at MIPS ISA level I. */
522 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
524 /* Is this a mfhi or mflo instruction? */
525 #define MF_HILO_INSN(PINFO) \
526 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
528 /* Returns true for a (non floating-point) coprocessor instruction. Reading
529 or writing the condition code is only possible on the coprocessors and
530 these insns are not marked with INSN_COP. Thus for these insns use the
531 condition-code flags. */
532 #define COP_INSN(PINFO) \
533 (PINFO != INSN_MACRO \
534 && ((PINFO) & (FP_S | FP_D)) == 0 \
535 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
537 /* MIPS PIC level. */
539 enum mips_pic_level mips_pic
;
541 /* 1 if we should generate 32 bit offsets from the $gp register in
542 SVR4_PIC mode. Currently has no meaning in other modes. */
543 static int mips_big_got
= 0;
545 /* 1 if trap instructions should used for overflow rather than break
547 static int mips_trap
= 0;
549 /* 1 if double width floating point constants should not be constructed
550 by assembling two single width halves into two single width floating
551 point registers which just happen to alias the double width destination
552 register. On some architectures this aliasing can be disabled by a bit
553 in the status register, and the setting of this bit cannot be determined
554 automatically at assemble time. */
555 static int mips_disable_float_construction
;
557 /* Non-zero if any .set noreorder directives were used. */
559 static int mips_any_noreorder
;
561 /* Non-zero if nops should be inserted when the register referenced in
562 an mfhi/mflo instruction is read in the next two instructions. */
563 static int mips_7000_hilo_fix
;
565 /* The size of objects in the small data section. */
566 static unsigned int g_switch_value
= 8;
567 /* Whether the -G option was used. */
568 static int g_switch_seen
= 0;
573 /* If we can determine in advance that GP optimization won't be
574 possible, we can skip the relaxation stuff that tries to produce
575 GP-relative references. This makes delay slot optimization work
578 This function can only provide a guess, but it seems to work for
579 gcc output. It needs to guess right for gcc, otherwise gcc
580 will put what it thinks is a GP-relative instruction in a branch
583 I don't know if a fix is needed for the SVR4_PIC mode. I've only
584 fixed it for the non-PIC mode. KR 95/04/07 */
585 static int nopic_need_relax (symbolS
*, int);
587 /* handle of the OPCODE hash table */
588 static struct hash_control
*op_hash
= NULL
;
590 /* The opcode hash table we use for the mips16. */
591 static struct hash_control
*mips16_op_hash
= NULL
;
593 /* This array holds the chars that always start a comment. If the
594 pre-processor is disabled, these aren't very useful */
595 const char comment_chars
[] = "#";
597 /* This array holds the chars that only start a comment at the beginning of
598 a line. If the line seems to have the form '# 123 filename'
599 .line and .file directives will appear in the pre-processed output */
600 /* Note that input_file.c hand checks for '#' at the beginning of the
601 first line of the input file. This is because the compiler outputs
602 #NO_APP at the beginning of its output. */
603 /* Also note that C style comments are always supported. */
604 const char line_comment_chars
[] = "#";
606 /* This array holds machine specific line separator characters. */
607 const char line_separator_chars
[] = ";";
609 /* Chars that can be used to separate mant from exp in floating point nums */
610 const char EXP_CHARS
[] = "eE";
612 /* Chars that mean this number is a floating point constant */
615 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
617 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
618 changed in read.c . Ideally it shouldn't have to know about it at all,
619 but nothing is ideal around here.
622 static char *insn_error
;
624 static int auto_align
= 1;
626 /* When outputting SVR4 PIC code, the assembler needs to know the
627 offset in the stack frame from which to restore the $gp register.
628 This is set by the .cprestore pseudo-op, and saved in this
630 static offsetT mips_cprestore_offset
= -1;
632 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
633 more optimizations, it can use a register value instead of a memory-saved
634 offset and even an other register than $gp as global pointer. */
635 static offsetT mips_cpreturn_offset
= -1;
636 static int mips_cpreturn_register
= -1;
637 static int mips_gp_register
= GP
;
638 static int mips_gprel_offset
= 0;
640 /* Whether mips_cprestore_offset has been set in the current function
641 (or whether it has already been warned about, if not). */
642 static int mips_cprestore_valid
= 0;
644 /* This is the register which holds the stack frame, as set by the
645 .frame pseudo-op. This is needed to implement .cprestore. */
646 static int mips_frame_reg
= SP
;
648 /* Whether mips_frame_reg has been set in the current function
649 (or whether it has already been warned about, if not). */
650 static int mips_frame_reg_valid
= 0;
652 /* To output NOP instructions correctly, we need to keep information
653 about the previous two instructions. */
655 /* Whether we are optimizing. The default value of 2 means to remove
656 unneeded NOPs and swap branch instructions when possible. A value
657 of 1 means to not swap branches. A value of 0 means to always
659 static int mips_optimize
= 2;
661 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
662 equivalent to seeing no -g option at all. */
663 static int mips_debug
= 0;
665 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
666 #define MAX_VR4130_NOPS 4
668 /* The maximum number of NOPs needed to fill delay slots. */
669 #define MAX_DELAY_NOPS 2
671 /* The maximum number of NOPs needed for any purpose. */
674 /* A list of previous instructions, with index 0 being the most recent.
675 We need to look back MAX_NOPS instructions when filling delay slots
676 or working around processor errata. We need to look back one
677 instruction further if we're thinking about using history[0] to
678 fill a branch delay slot. */
679 static struct mips_cl_insn history
[1 + MAX_NOPS
];
681 /* Nop instructions used by emit_nop. */
682 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
684 /* The appropriate nop for the current mode. */
685 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
687 /* If this is set, it points to a frag holding nop instructions which
688 were inserted before the start of a noreorder section. If those
689 nops turn out to be unnecessary, the size of the frag can be
691 static fragS
*prev_nop_frag
;
693 /* The number of nop instructions we created in prev_nop_frag. */
694 static int prev_nop_frag_holds
;
696 /* The number of nop instructions that we know we need in
698 static int prev_nop_frag_required
;
700 /* The number of instructions we've seen since prev_nop_frag. */
701 static int prev_nop_frag_since
;
703 /* For ECOFF and ELF, relocations against symbols are done in two
704 parts, with a HI relocation and a LO relocation. Each relocation
705 has only 16 bits of space to store an addend. This means that in
706 order for the linker to handle carries correctly, it must be able
707 to locate both the HI and the LO relocation. This means that the
708 relocations must appear in order in the relocation table.
710 In order to implement this, we keep track of each unmatched HI
711 relocation. We then sort them so that they immediately precede the
712 corresponding LO relocation. */
717 struct mips_hi_fixup
*next
;
720 /* The section this fixup is in. */
724 /* The list of unmatched HI relocs. */
726 static struct mips_hi_fixup
*mips_hi_fixup_list
;
728 /* The frag containing the last explicit relocation operator.
729 Null if explicit relocations have not been used. */
731 static fragS
*prev_reloc_op_frag
;
733 /* Map normal MIPS register numbers to mips16 register numbers. */
735 #define X ILLEGAL_REG
736 static const int mips32_to_16_reg_map
[] =
738 X
, X
, 2, 3, 4, 5, 6, 7,
739 X
, X
, X
, X
, X
, X
, X
, X
,
740 0, 1, X
, X
, X
, X
, X
, X
,
741 X
, X
, X
, X
, X
, X
, X
, X
745 /* Map mips16 register numbers to normal MIPS register numbers. */
747 static const unsigned int mips16_to_32_reg_map
[] =
749 16, 17, 2, 3, 4, 5, 6, 7
752 /* Classifies the kind of instructions we're interested in when
753 implementing -mfix-vr4120. */
754 enum fix_vr4120_class
762 NUM_FIX_VR4120_CLASSES
765 /* ...likewise -mfix-loongson2f-jump. */
766 static bfd_boolean mips_fix_loongson2f_jump
;
768 /* ...likewise -mfix-loongson2f-nop. */
769 static bfd_boolean mips_fix_loongson2f_nop
;
771 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
772 static bfd_boolean mips_fix_loongson2f
;
774 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
775 there must be at least one other instruction between an instruction
776 of type X and an instruction of type Y. */
777 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
779 /* True if -mfix-vr4120 is in force. */
780 static int mips_fix_vr4120
;
782 /* ...likewise -mfix-vr4130. */
783 static int mips_fix_vr4130
;
785 /* ...likewise -mfix-24k. */
786 static int mips_fix_24k
;
788 /* ...likewise -mfix-cn63xxp1 */
789 static bfd_boolean mips_fix_cn63xxp1
;
791 /* We don't relax branches by default, since this causes us to expand
792 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
793 fail to compute the offset before expanding the macro to the most
794 efficient expansion. */
796 static int mips_relax_branch
;
798 /* The expansion of many macros depends on the type of symbol that
799 they refer to. For example, when generating position-dependent code,
800 a macro that refers to a symbol may have two different expansions,
801 one which uses GP-relative addresses and one which uses absolute
802 addresses. When generating SVR4-style PIC, a macro may have
803 different expansions for local and global symbols.
805 We handle these situations by generating both sequences and putting
806 them in variant frags. In position-dependent code, the first sequence
807 will be the GP-relative one and the second sequence will be the
808 absolute one. In SVR4 PIC, the first sequence will be for global
809 symbols and the second will be for local symbols.
811 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
812 SECOND are the lengths of the two sequences in bytes. These fields
813 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
814 the subtype has the following flags:
817 Set if it has been decided that we should use the second
818 sequence instead of the first.
821 Set in the first variant frag if the macro's second implementation
822 is longer than its first. This refers to the macro as a whole,
823 not an individual relaxation.
826 Set in the first variant frag if the macro appeared in a .set nomacro
827 block and if one alternative requires a warning but the other does not.
830 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
833 The frag's "opcode" points to the first fixup for relaxable code.
835 Relaxable macros are generated using a sequence such as:
837 relax_start (SYMBOL);
838 ... generate first expansion ...
840 ... generate second expansion ...
843 The code and fixups for the unwanted alternative are discarded
844 by md_convert_frag. */
845 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
847 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
848 #define RELAX_SECOND(X) ((X) & 0xff)
849 #define RELAX_USE_SECOND 0x10000
850 #define RELAX_SECOND_LONGER 0x20000
851 #define RELAX_NOMACRO 0x40000
852 #define RELAX_DELAY_SLOT 0x80000
854 /* Branch without likely bit. If label is out of range, we turn:
856 beq reg1, reg2, label
866 with the following opcode replacements:
873 bltzal <-> bgezal (with jal label instead of j label)
875 Even though keeping the delay slot instruction in the delay slot of
876 the branch would be more efficient, it would be very tricky to do
877 correctly, because we'd have to introduce a variable frag *after*
878 the delay slot instruction, and expand that instead. Let's do it
879 the easy way for now, even if the branch-not-taken case now costs
880 one additional instruction. Out-of-range branches are not supposed
881 to be common, anyway.
883 Branch likely. If label is out of range, we turn:
885 beql reg1, reg2, label
886 delay slot (annulled if branch not taken)
895 delay slot (executed only if branch taken)
898 It would be possible to generate a shorter sequence by losing the
899 likely bit, generating something like:
904 delay slot (executed only if branch taken)
916 bltzall -> bgezal (with jal label instead of j label)
917 bgezall -> bltzal (ditto)
920 but it's not clear that it would actually improve performance. */
921 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
925 | ((toofar) ? 0x20 : 0) \
926 | ((link) ? 0x40 : 0) \
927 | ((likely) ? 0x80 : 0) \
928 | ((uncond) ? 0x100 : 0)))
929 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
930 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
931 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
932 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
933 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
934 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
936 /* For mips16 code, we use an entirely different form of relaxation.
937 mips16 supports two versions of most instructions which take
938 immediate values: a small one which takes some small value, and a
939 larger one which takes a 16 bit value. Since branches also follow
940 this pattern, relaxing these values is required.
942 We can assemble both mips16 and normal MIPS code in a single
943 object. Therefore, we need to support this type of relaxation at
944 the same time that we support the relaxation described above. We
945 use the high bit of the subtype field to distinguish these cases.
947 The information we store for this type of relaxation is the
948 argument code found in the opcode file for this relocation, whether
949 the user explicitly requested a small or extended form, and whether
950 the relocation is in a jump or jal delay slot. That tells us the
951 size of the value, and how it should be stored. We also store
952 whether the fragment is considered to be extended or not. We also
953 store whether this is known to be a branch to a different section,
954 whether we have tried to relax this frag yet, and whether we have
955 ever extended a PC relative fragment because of a shift count. */
956 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
959 | ((small) ? 0x100 : 0) \
960 | ((ext) ? 0x200 : 0) \
961 | ((dslot) ? 0x400 : 0) \
962 | ((jal_dslot) ? 0x800 : 0))
963 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
964 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
965 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
966 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
967 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
968 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
969 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
970 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
971 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
972 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
973 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
974 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
976 /* Is the given value a sign-extended 32-bit value? */
977 #define IS_SEXT_32BIT_NUM(x) \
978 (((x) &~ (offsetT) 0x7fffffff) == 0 \
979 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
981 /* Is the given value a sign-extended 16-bit value? */
982 #define IS_SEXT_16BIT_NUM(x) \
983 (((x) &~ (offsetT) 0x7fff) == 0 \
984 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
986 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
987 #define IS_ZEXT_32BIT_NUM(x) \
988 (((x) &~ (offsetT) 0xffffffff) == 0 \
989 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
991 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
992 VALUE << SHIFT. VALUE is evaluated exactly once. */
993 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
994 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
995 | (((VALUE) & (MASK)) << (SHIFT)))
997 /* Extract bits MASK << SHIFT from STRUCT and shift them right
999 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1000 (((STRUCT) >> (SHIFT)) & (MASK))
1002 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1003 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1005 include/opcode/mips.h specifies operand fields using the macros
1006 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1007 with "MIPS16OP" instead of "OP". */
1008 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1009 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1010 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1011 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1012 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1014 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1015 #define EXTRACT_OPERAND(FIELD, INSN) \
1016 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1017 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1018 EXTRACT_BITS ((INSN).insn_opcode, \
1019 MIPS16OP_MASK_##FIELD, \
1020 MIPS16OP_SH_##FIELD)
1022 /* Global variables used when generating relaxable macros. See the
1023 comment above RELAX_ENCODE for more details about how relaxation
1026 /* 0 if we're not emitting a relaxable macro.
1027 1 if we're emitting the first of the two relaxation alternatives.
1028 2 if we're emitting the second alternative. */
1031 /* The first relaxable fixup in the current frag. (In other words,
1032 the first fixup that refers to relaxable code.) */
1035 /* sizes[0] says how many bytes of the first alternative are stored in
1036 the current frag. Likewise sizes[1] for the second alternative. */
1037 unsigned int sizes
[2];
1039 /* The symbol on which the choice of sequence depends. */
1043 /* Global variables used to decide whether a macro needs a warning. */
1045 /* True if the macro is in a branch delay slot. */
1046 bfd_boolean delay_slot_p
;
1048 /* For relaxable macros, sizes[0] is the length of the first alternative
1049 in bytes and sizes[1] is the length of the second alternative.
1050 For non-relaxable macros, both elements give the length of the
1052 unsigned int sizes
[2];
1054 /* The first variant frag for this macro. */
1056 } mips_macro_warning
;
1058 /* Prototypes for static functions. */
1060 #define internalError() \
1061 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1063 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1065 static void append_insn
1066 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*);
1067 static void mips_no_prev_insn (void);
1068 static void macro_build (expressionS
*, const char *, const char *, ...);
1069 static void mips16_macro_build
1070 (expressionS
*, const char *, const char *, va_list *);
1071 static void load_register (int, expressionS
*, int);
1072 static void macro_start (void);
1073 static void macro_end (void);
1074 static void macro (struct mips_cl_insn
* ip
);
1075 static void mips16_macro (struct mips_cl_insn
* ip
);
1076 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1077 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1078 static void mips16_immed
1079 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1080 unsigned long *, bfd_boolean
*, unsigned short *);
1081 static size_t my_getSmallExpression
1082 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1083 static void my_getExpression (expressionS
*, char *);
1084 static void s_align (int);
1085 static void s_change_sec (int);
1086 static void s_change_section (int);
1087 static void s_cons (int);
1088 static void s_float_cons (int);
1089 static void s_mips_globl (int);
1090 static void s_option (int);
1091 static void s_mipsset (int);
1092 static void s_abicalls (int);
1093 static void s_cpload (int);
1094 static void s_cpsetup (int);
1095 static void s_cplocal (int);
1096 static void s_cprestore (int);
1097 static void s_cpreturn (int);
1098 static void s_dtprelword (int);
1099 static void s_dtpreldword (int);
1100 static void s_gpvalue (int);
1101 static void s_gpword (int);
1102 static void s_gpdword (int);
1103 static void s_cpadd (int);
1104 static void s_insn (int);
1105 static void md_obj_begin (void);
1106 static void md_obj_end (void);
1107 static void s_mips_ent (int);
1108 static void s_mips_end (int);
1109 static void s_mips_frame (int);
1110 static void s_mips_mask (int reg_type
);
1111 static void s_mips_stab (int);
1112 static void s_mips_weakext (int);
1113 static void s_mips_file (int);
1114 static void s_mips_loc (int);
1115 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1116 static int relaxed_branch_length (fragS
*, asection
*, int);
1117 static int validate_mips_insn (const struct mips_opcode
*);
1119 /* Table and functions used to map between CPU/ISA names, and
1120 ISA levels, and CPU numbers. */
1122 struct mips_cpu_info
1124 const char *name
; /* CPU or ISA name. */
1125 int flags
; /* ASEs available, or ISA flag. */
1126 int isa
; /* ISA level. */
1127 int cpu
; /* CPU number (default CPU if ISA). */
1130 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1131 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1132 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1133 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1134 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1135 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1136 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1138 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1139 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1140 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1144 The following pseudo-ops from the Kane and Heinrich MIPS book
1145 should be defined here, but are currently unsupported: .alias,
1146 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1148 The following pseudo-ops from the Kane and Heinrich MIPS book are
1149 specific to the type of debugging information being generated, and
1150 should be defined by the object format: .aent, .begin, .bend,
1151 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1154 The following pseudo-ops from the Kane and Heinrich MIPS book are
1155 not MIPS CPU specific, but are also not specific to the object file
1156 format. This file is probably the best place to define them, but
1157 they are not currently supported: .asm0, .endr, .lab, .struct. */
1159 static const pseudo_typeS mips_pseudo_table
[] =
1161 /* MIPS specific pseudo-ops. */
1162 {"option", s_option
, 0},
1163 {"set", s_mipsset
, 0},
1164 {"rdata", s_change_sec
, 'r'},
1165 {"sdata", s_change_sec
, 's'},
1166 {"livereg", s_ignore
, 0},
1167 {"abicalls", s_abicalls
, 0},
1168 {"cpload", s_cpload
, 0},
1169 {"cpsetup", s_cpsetup
, 0},
1170 {"cplocal", s_cplocal
, 0},
1171 {"cprestore", s_cprestore
, 0},
1172 {"cpreturn", s_cpreturn
, 0},
1173 {"dtprelword", s_dtprelword
, 0},
1174 {"dtpreldword", s_dtpreldword
, 0},
1175 {"gpvalue", s_gpvalue
, 0},
1176 {"gpword", s_gpword
, 0},
1177 {"gpdword", s_gpdword
, 0},
1178 {"cpadd", s_cpadd
, 0},
1179 {"insn", s_insn
, 0},
1181 /* Relatively generic pseudo-ops that happen to be used on MIPS
1183 {"asciiz", stringer
, 8 + 1},
1184 {"bss", s_change_sec
, 'b'},
1186 {"half", s_cons
, 1},
1187 {"dword", s_cons
, 3},
1188 {"weakext", s_mips_weakext
, 0},
1189 {"origin", s_org
, 0},
1190 {"repeat", s_rept
, 0},
1192 /* For MIPS this is non-standard, but we define it for consistency. */
1193 {"sbss", s_change_sec
, 'B'},
1195 /* These pseudo-ops are defined in read.c, but must be overridden
1196 here for one reason or another. */
1197 {"align", s_align
, 0},
1198 {"byte", s_cons
, 0},
1199 {"data", s_change_sec
, 'd'},
1200 {"double", s_float_cons
, 'd'},
1201 {"float", s_float_cons
, 'f'},
1202 {"globl", s_mips_globl
, 0},
1203 {"global", s_mips_globl
, 0},
1204 {"hword", s_cons
, 1},
1206 {"long", s_cons
, 2},
1207 {"octa", s_cons
, 4},
1208 {"quad", s_cons
, 3},
1209 {"section", s_change_section
, 0},
1210 {"short", s_cons
, 1},
1211 {"single", s_float_cons
, 'f'},
1212 {"stabn", s_mips_stab
, 'n'},
1213 {"text", s_change_sec
, 't'},
1214 {"word", s_cons
, 2},
1216 { "extern", ecoff_directive_extern
, 0},
1221 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1223 /* These pseudo-ops should be defined by the object file format.
1224 However, a.out doesn't support them, so we have versions here. */
1225 {"aent", s_mips_ent
, 1},
1226 {"bgnb", s_ignore
, 0},
1227 {"end", s_mips_end
, 0},
1228 {"endb", s_ignore
, 0},
1229 {"ent", s_mips_ent
, 0},
1230 {"file", s_mips_file
, 0},
1231 {"fmask", s_mips_mask
, 'F'},
1232 {"frame", s_mips_frame
, 0},
1233 {"loc", s_mips_loc
, 0},
1234 {"mask", s_mips_mask
, 'R'},
1235 {"verstamp", s_ignore
, 0},
1239 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1240 purpose of the `.dc.a' internal pseudo-op. */
1243 mips_address_bytes (void)
1245 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1248 extern void pop_insert (const pseudo_typeS
*);
1251 mips_pop_insert (void)
1253 pop_insert (mips_pseudo_table
);
1254 if (! ECOFF_DEBUGGING
)
1255 pop_insert (mips_nonecoff_pseudo_table
);
1258 /* Symbols labelling the current insn. */
1260 struct insn_label_list
1262 struct insn_label_list
*next
;
1266 static struct insn_label_list
*free_insn_labels
;
1267 #define label_list tc_segment_info_data.labels
1269 static void mips_clear_insn_labels (void);
1272 mips_clear_insn_labels (void)
1274 register struct insn_label_list
**pl
;
1275 segment_info_type
*si
;
1279 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1282 si
= seg_info (now_seg
);
1283 *pl
= si
->label_list
;
1284 si
->label_list
= NULL
;
1289 static char *expr_end
;
1291 /* Expressions which appear in instructions. These are set by
1294 static expressionS imm_expr
;
1295 static expressionS imm2_expr
;
1296 static expressionS offset_expr
;
1298 /* Relocs associated with imm_expr and offset_expr. */
1300 static bfd_reloc_code_real_type imm_reloc
[3]
1301 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1302 static bfd_reloc_code_real_type offset_reloc
[3]
1303 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1305 /* These are set by mips16_ip if an explicit extension is used. */
1307 static bfd_boolean mips16_small
, mips16_ext
;
1310 /* The pdr segment for per procedure frame/regmask info. Not used for
1313 static segT pdr_seg
;
1316 /* The default target format to use. */
1318 #if defined (TE_FreeBSD)
1319 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1320 #elif defined (TE_TMIPS)
1321 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1323 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1327 mips_target_format (void)
1329 switch (OUTPUT_FLAVOR
)
1331 case bfd_target_ecoff_flavour
:
1332 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1333 case bfd_target_coff_flavour
:
1335 case bfd_target_elf_flavour
:
1337 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1338 return (target_big_endian
1339 ? "elf32-bigmips-vxworks"
1340 : "elf32-littlemips-vxworks");
1342 return (target_big_endian
1343 ? (HAVE_64BIT_OBJECTS
1344 ? ELF_TARGET ("elf64-", "big")
1346 ? ELF_TARGET ("elf32-n", "big")
1347 : ELF_TARGET ("elf32-", "big")))
1348 : (HAVE_64BIT_OBJECTS
1349 ? ELF_TARGET ("elf64-", "little")
1351 ? ELF_TARGET ("elf32-n", "little")
1352 : ELF_TARGET ("elf32-", "little"))));
1359 /* Return the length of instruction INSN. */
1361 static inline unsigned int
1362 insn_length (const struct mips_cl_insn
*insn
)
1364 if (!mips_opts
.mips16
)
1366 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1369 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1372 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1377 insn
->use_extend
= FALSE
;
1379 insn
->insn_opcode
= mo
->match
;
1382 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1383 insn
->fixp
[i
] = NULL
;
1384 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1385 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1386 insn
->mips16_absolute_jump_p
= 0;
1389 /* Record the current MIPS16 mode in now_seg. */
1392 mips_record_mips16_mode (void)
1394 segment_info_type
*si
;
1396 si
= seg_info (now_seg
);
1397 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1398 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1401 /* Install INSN at the location specified by its "frag" and "where" fields. */
1404 install_insn (const struct mips_cl_insn
*insn
)
1406 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1407 if (!mips_opts
.mips16
)
1408 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1409 else if (insn
->mips16_absolute_jump_p
)
1411 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1412 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1416 if (insn
->use_extend
)
1418 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1421 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1423 mips_record_mips16_mode ();
1426 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1427 and install the opcode in the new location. */
1430 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1435 insn
->where
= where
;
1436 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1437 if (insn
->fixp
[i
] != NULL
)
1439 insn
->fixp
[i
]->fx_frag
= frag
;
1440 insn
->fixp
[i
]->fx_where
= where
;
1442 install_insn (insn
);
1445 /* Add INSN to the end of the output. */
1448 add_fixed_insn (struct mips_cl_insn
*insn
)
1450 char *f
= frag_more (insn_length (insn
));
1451 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1454 /* Start a variant frag and move INSN to the start of the variant part,
1455 marking it as fixed. The other arguments are as for frag_var. */
1458 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1459 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1461 frag_grow (max_chars
);
1462 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1464 frag_var (rs_machine_dependent
, max_chars
, var
,
1465 subtype
, symbol
, offset
, NULL
);
1468 /* Insert N copies of INSN into the history buffer, starting at
1469 position FIRST. Neither FIRST nor N need to be clipped. */
1472 insert_into_history (unsigned int first
, unsigned int n
,
1473 const struct mips_cl_insn
*insn
)
1475 if (mips_relax
.sequence
!= 2)
1479 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1481 history
[i
] = history
[i
- n
];
1487 /* Emit a nop instruction, recording it in the history buffer. */
1492 add_fixed_insn (NOP_INSN
);
1493 insert_into_history (0, 1, NOP_INSN
);
1496 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1497 the idea is to make it obvious at a glance that each errata is
1501 init_vr4120_conflicts (void)
1503 #define CONFLICT(FIRST, SECOND) \
1504 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1506 /* Errata 21 - [D]DIV[U] after [D]MACC */
1507 CONFLICT (MACC
, DIV
);
1508 CONFLICT (DMACC
, DIV
);
1510 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1511 CONFLICT (DMULT
, DMULT
);
1512 CONFLICT (DMULT
, DMACC
);
1513 CONFLICT (DMACC
, DMULT
);
1514 CONFLICT (DMACC
, DMACC
);
1516 /* Errata 24 - MT{LO,HI} after [D]MACC */
1517 CONFLICT (MACC
, MTHILO
);
1518 CONFLICT (DMACC
, MTHILO
);
1520 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1521 instruction is executed immediately after a MACC or DMACC
1522 instruction, the result of [either instruction] is incorrect." */
1523 CONFLICT (MACC
, MULT
);
1524 CONFLICT (MACC
, DMULT
);
1525 CONFLICT (DMACC
, MULT
);
1526 CONFLICT (DMACC
, DMULT
);
1528 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1529 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1530 DDIV or DDIVU instruction, the result of the MACC or
1531 DMACC instruction is incorrect.". */
1532 CONFLICT (DMULT
, MACC
);
1533 CONFLICT (DMULT
, DMACC
);
1534 CONFLICT (DIV
, MACC
);
1535 CONFLICT (DIV
, DMACC
);
1545 #define RTYPE_MASK 0x1ff00
1546 #define RTYPE_NUM 0x00100
1547 #define RTYPE_FPU 0x00200
1548 #define RTYPE_FCC 0x00400
1549 #define RTYPE_VEC 0x00800
1550 #define RTYPE_GP 0x01000
1551 #define RTYPE_CP0 0x02000
1552 #define RTYPE_PC 0x04000
1553 #define RTYPE_ACC 0x08000
1554 #define RTYPE_CCC 0x10000
1555 #define RNUM_MASK 0x000ff
1556 #define RWARN 0x80000
1558 #define GENERIC_REGISTER_NUMBERS \
1559 {"$0", RTYPE_NUM | 0}, \
1560 {"$1", RTYPE_NUM | 1}, \
1561 {"$2", RTYPE_NUM | 2}, \
1562 {"$3", RTYPE_NUM | 3}, \
1563 {"$4", RTYPE_NUM | 4}, \
1564 {"$5", RTYPE_NUM | 5}, \
1565 {"$6", RTYPE_NUM | 6}, \
1566 {"$7", RTYPE_NUM | 7}, \
1567 {"$8", RTYPE_NUM | 8}, \
1568 {"$9", RTYPE_NUM | 9}, \
1569 {"$10", RTYPE_NUM | 10}, \
1570 {"$11", RTYPE_NUM | 11}, \
1571 {"$12", RTYPE_NUM | 12}, \
1572 {"$13", RTYPE_NUM | 13}, \
1573 {"$14", RTYPE_NUM | 14}, \
1574 {"$15", RTYPE_NUM | 15}, \
1575 {"$16", RTYPE_NUM | 16}, \
1576 {"$17", RTYPE_NUM | 17}, \
1577 {"$18", RTYPE_NUM | 18}, \
1578 {"$19", RTYPE_NUM | 19}, \
1579 {"$20", RTYPE_NUM | 20}, \
1580 {"$21", RTYPE_NUM | 21}, \
1581 {"$22", RTYPE_NUM | 22}, \
1582 {"$23", RTYPE_NUM | 23}, \
1583 {"$24", RTYPE_NUM | 24}, \
1584 {"$25", RTYPE_NUM | 25}, \
1585 {"$26", RTYPE_NUM | 26}, \
1586 {"$27", RTYPE_NUM | 27}, \
1587 {"$28", RTYPE_NUM | 28}, \
1588 {"$29", RTYPE_NUM | 29}, \
1589 {"$30", RTYPE_NUM | 30}, \
1590 {"$31", RTYPE_NUM | 31}
1592 #define FPU_REGISTER_NAMES \
1593 {"$f0", RTYPE_FPU | 0}, \
1594 {"$f1", RTYPE_FPU | 1}, \
1595 {"$f2", RTYPE_FPU | 2}, \
1596 {"$f3", RTYPE_FPU | 3}, \
1597 {"$f4", RTYPE_FPU | 4}, \
1598 {"$f5", RTYPE_FPU | 5}, \
1599 {"$f6", RTYPE_FPU | 6}, \
1600 {"$f7", RTYPE_FPU | 7}, \
1601 {"$f8", RTYPE_FPU | 8}, \
1602 {"$f9", RTYPE_FPU | 9}, \
1603 {"$f10", RTYPE_FPU | 10}, \
1604 {"$f11", RTYPE_FPU | 11}, \
1605 {"$f12", RTYPE_FPU | 12}, \
1606 {"$f13", RTYPE_FPU | 13}, \
1607 {"$f14", RTYPE_FPU | 14}, \
1608 {"$f15", RTYPE_FPU | 15}, \
1609 {"$f16", RTYPE_FPU | 16}, \
1610 {"$f17", RTYPE_FPU | 17}, \
1611 {"$f18", RTYPE_FPU | 18}, \
1612 {"$f19", RTYPE_FPU | 19}, \
1613 {"$f20", RTYPE_FPU | 20}, \
1614 {"$f21", RTYPE_FPU | 21}, \
1615 {"$f22", RTYPE_FPU | 22}, \
1616 {"$f23", RTYPE_FPU | 23}, \
1617 {"$f24", RTYPE_FPU | 24}, \
1618 {"$f25", RTYPE_FPU | 25}, \
1619 {"$f26", RTYPE_FPU | 26}, \
1620 {"$f27", RTYPE_FPU | 27}, \
1621 {"$f28", RTYPE_FPU | 28}, \
1622 {"$f29", RTYPE_FPU | 29}, \
1623 {"$f30", RTYPE_FPU | 30}, \
1624 {"$f31", RTYPE_FPU | 31}
1626 #define FPU_CONDITION_CODE_NAMES \
1627 {"$fcc0", RTYPE_FCC | 0}, \
1628 {"$fcc1", RTYPE_FCC | 1}, \
1629 {"$fcc2", RTYPE_FCC | 2}, \
1630 {"$fcc3", RTYPE_FCC | 3}, \
1631 {"$fcc4", RTYPE_FCC | 4}, \
1632 {"$fcc5", RTYPE_FCC | 5}, \
1633 {"$fcc6", RTYPE_FCC | 6}, \
1634 {"$fcc7", RTYPE_FCC | 7}
1636 #define COPROC_CONDITION_CODE_NAMES \
1637 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1638 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1639 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1640 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1641 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1642 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1643 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1644 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1646 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1647 {"$a4", RTYPE_GP | 8}, \
1648 {"$a5", RTYPE_GP | 9}, \
1649 {"$a6", RTYPE_GP | 10}, \
1650 {"$a7", RTYPE_GP | 11}, \
1651 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1652 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1653 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1654 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1655 {"$t0", RTYPE_GP | 12}, \
1656 {"$t1", RTYPE_GP | 13}, \
1657 {"$t2", RTYPE_GP | 14}, \
1658 {"$t3", RTYPE_GP | 15}
1660 #define O32_SYMBOLIC_REGISTER_NAMES \
1661 {"$t0", RTYPE_GP | 8}, \
1662 {"$t1", RTYPE_GP | 9}, \
1663 {"$t2", RTYPE_GP | 10}, \
1664 {"$t3", RTYPE_GP | 11}, \
1665 {"$t4", RTYPE_GP | 12}, \
1666 {"$t5", RTYPE_GP | 13}, \
1667 {"$t6", RTYPE_GP | 14}, \
1668 {"$t7", RTYPE_GP | 15}, \
1669 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1670 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1671 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1672 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1674 /* Remaining symbolic register names */
1675 #define SYMBOLIC_REGISTER_NAMES \
1676 {"$zero", RTYPE_GP | 0}, \
1677 {"$at", RTYPE_GP | 1}, \
1678 {"$AT", RTYPE_GP | 1}, \
1679 {"$v0", RTYPE_GP | 2}, \
1680 {"$v1", RTYPE_GP | 3}, \
1681 {"$a0", RTYPE_GP | 4}, \
1682 {"$a1", RTYPE_GP | 5}, \
1683 {"$a2", RTYPE_GP | 6}, \
1684 {"$a3", RTYPE_GP | 7}, \
1685 {"$s0", RTYPE_GP | 16}, \
1686 {"$s1", RTYPE_GP | 17}, \
1687 {"$s2", RTYPE_GP | 18}, \
1688 {"$s3", RTYPE_GP | 19}, \
1689 {"$s4", RTYPE_GP | 20}, \
1690 {"$s5", RTYPE_GP | 21}, \
1691 {"$s6", RTYPE_GP | 22}, \
1692 {"$s7", RTYPE_GP | 23}, \
1693 {"$t8", RTYPE_GP | 24}, \
1694 {"$t9", RTYPE_GP | 25}, \
1695 {"$k0", RTYPE_GP | 26}, \
1696 {"$kt0", RTYPE_GP | 26}, \
1697 {"$k1", RTYPE_GP | 27}, \
1698 {"$kt1", RTYPE_GP | 27}, \
1699 {"$gp", RTYPE_GP | 28}, \
1700 {"$sp", RTYPE_GP | 29}, \
1701 {"$s8", RTYPE_GP | 30}, \
1702 {"$fp", RTYPE_GP | 30}, \
1703 {"$ra", RTYPE_GP | 31}
1705 #define MIPS16_SPECIAL_REGISTER_NAMES \
1706 {"$pc", RTYPE_PC | 0}
1708 #define MDMX_VECTOR_REGISTER_NAMES \
1709 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1710 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1711 {"$v2", RTYPE_VEC | 2}, \
1712 {"$v3", RTYPE_VEC | 3}, \
1713 {"$v4", RTYPE_VEC | 4}, \
1714 {"$v5", RTYPE_VEC | 5}, \
1715 {"$v6", RTYPE_VEC | 6}, \
1716 {"$v7", RTYPE_VEC | 7}, \
1717 {"$v8", RTYPE_VEC | 8}, \
1718 {"$v9", RTYPE_VEC | 9}, \
1719 {"$v10", RTYPE_VEC | 10}, \
1720 {"$v11", RTYPE_VEC | 11}, \
1721 {"$v12", RTYPE_VEC | 12}, \
1722 {"$v13", RTYPE_VEC | 13}, \
1723 {"$v14", RTYPE_VEC | 14}, \
1724 {"$v15", RTYPE_VEC | 15}, \
1725 {"$v16", RTYPE_VEC | 16}, \
1726 {"$v17", RTYPE_VEC | 17}, \
1727 {"$v18", RTYPE_VEC | 18}, \
1728 {"$v19", RTYPE_VEC | 19}, \
1729 {"$v20", RTYPE_VEC | 20}, \
1730 {"$v21", RTYPE_VEC | 21}, \
1731 {"$v22", RTYPE_VEC | 22}, \
1732 {"$v23", RTYPE_VEC | 23}, \
1733 {"$v24", RTYPE_VEC | 24}, \
1734 {"$v25", RTYPE_VEC | 25}, \
1735 {"$v26", RTYPE_VEC | 26}, \
1736 {"$v27", RTYPE_VEC | 27}, \
1737 {"$v28", RTYPE_VEC | 28}, \
1738 {"$v29", RTYPE_VEC | 29}, \
1739 {"$v30", RTYPE_VEC | 30}, \
1740 {"$v31", RTYPE_VEC | 31}
1742 #define MIPS_DSP_ACCUMULATOR_NAMES \
1743 {"$ac0", RTYPE_ACC | 0}, \
1744 {"$ac1", RTYPE_ACC | 1}, \
1745 {"$ac2", RTYPE_ACC | 2}, \
1746 {"$ac3", RTYPE_ACC | 3}
1748 static const struct regname reg_names
[] = {
1749 GENERIC_REGISTER_NUMBERS
,
1751 FPU_CONDITION_CODE_NAMES
,
1752 COPROC_CONDITION_CODE_NAMES
,
1754 /* The $txx registers depends on the abi,
1755 these will be added later into the symbol table from
1756 one of the tables below once mips_abi is set after
1757 parsing of arguments from the command line. */
1758 SYMBOLIC_REGISTER_NAMES
,
1760 MIPS16_SPECIAL_REGISTER_NAMES
,
1761 MDMX_VECTOR_REGISTER_NAMES
,
1762 MIPS_DSP_ACCUMULATOR_NAMES
,
1766 static const struct regname reg_names_o32
[] = {
1767 O32_SYMBOLIC_REGISTER_NAMES
,
1771 static const struct regname reg_names_n32n64
[] = {
1772 N32N64_SYMBOLIC_REGISTER_NAMES
,
1777 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1784 /* Find end of name. */
1786 if (is_name_beginner (*e
))
1788 while (is_part_of_name (*e
))
1791 /* Terminate name. */
1795 /* Look for a register symbol. */
1796 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1798 int r
= S_GET_VALUE (symbolP
);
1800 reg
= r
& RNUM_MASK
;
1801 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1802 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1803 reg
= (r
& RNUM_MASK
) - 2;
1805 /* Else see if this is a register defined in an itbl entry. */
1806 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1813 if (itbl_get_reg_val (n
, &r
))
1814 reg
= r
& RNUM_MASK
;
1817 /* Advance to next token if a register was recognised. */
1820 else if (types
& RWARN
)
1821 as_warn (_("Unrecognized register name `%s'"), *s
);
1829 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1830 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1833 is_opcode_valid (const struct mips_opcode
*mo
)
1835 int isa
= mips_opts
.isa
;
1838 if (mips_opts
.ase_mdmx
)
1840 if (mips_opts
.ase_dsp
)
1842 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1844 if (mips_opts
.ase_dspr2
)
1846 if (mips_opts
.ase_mt
)
1848 if (mips_opts
.ase_mips3d
)
1850 if (mips_opts
.ase_smartmips
)
1851 isa
|= INSN_SMARTMIPS
;
1853 /* Don't accept instructions based on the ISA if the CPU does not implement
1854 all the coprocessor insns. */
1855 if (NO_ISA_COP (mips_opts
.arch
)
1856 && COP_INSN (mo
->pinfo
))
1859 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1862 /* Check whether the instruction or macro requires single-precision or
1863 double-precision floating-point support. Note that this information is
1864 stored differently in the opcode table for insns and macros. */
1865 if (mo
->pinfo
== INSN_MACRO
)
1867 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1868 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1872 fp_s
= mo
->pinfo
& FP_S
;
1873 fp_d
= mo
->pinfo
& FP_D
;
1876 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1879 if (fp_s
&& mips_opts
.soft_float
)
1885 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1886 selected ISA and architecture. */
1889 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1891 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1894 /* This function is called once, at assembler startup time. It should set up
1895 all the tables, etc. that the MD part of the assembler will need. */
1900 const char *retval
= NULL
;
1904 if (mips_pic
!= NO_PIC
)
1906 if (g_switch_seen
&& g_switch_value
!= 0)
1907 as_bad (_("-G may not be used in position-independent code"));
1911 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1912 as_warn (_("Could not set architecture and machine"));
1914 op_hash
= hash_new ();
1916 for (i
= 0; i
< NUMOPCODES
;)
1918 const char *name
= mips_opcodes
[i
].name
;
1920 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1923 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1924 mips_opcodes
[i
].name
, retval
);
1925 /* Probably a memory allocation problem? Give up now. */
1926 as_fatal (_("Broken assembler. No assembly attempted."));
1930 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1932 if (!validate_mips_insn (&mips_opcodes
[i
]))
1934 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1936 create_insn (&nop_insn
, mips_opcodes
+ i
);
1937 if (mips_fix_loongson2f_nop
)
1938 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
1939 nop_insn
.fixed_p
= 1;
1944 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1947 mips16_op_hash
= hash_new ();
1950 while (i
< bfd_mips16_num_opcodes
)
1952 const char *name
= mips16_opcodes
[i
].name
;
1954 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1956 as_fatal (_("internal: can't hash `%s': %s"),
1957 mips16_opcodes
[i
].name
, retval
);
1960 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1961 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1962 != mips16_opcodes
[i
].match
))
1964 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1965 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1968 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1970 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1971 mips16_nop_insn
.fixed_p
= 1;
1975 while (i
< bfd_mips16_num_opcodes
1976 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1980 as_fatal (_("Broken assembler. No assembly attempted."));
1982 /* We add all the general register names to the symbol table. This
1983 helps us detect invalid uses of them. */
1984 for (i
= 0; reg_names
[i
].name
; i
++)
1985 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1986 reg_names
[i
].num
, /* & RNUM_MASK, */
1987 &zero_address_frag
));
1989 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1990 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1991 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
1992 &zero_address_frag
));
1994 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1995 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1996 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
1997 &zero_address_frag
));
1999 mips_no_prev_insn ();
2002 mips_cprmask
[0] = 0;
2003 mips_cprmask
[1] = 0;
2004 mips_cprmask
[2] = 0;
2005 mips_cprmask
[3] = 0;
2007 /* set the default alignment for the text section (2**2) */
2008 record_alignment (text_section
, 2);
2010 bfd_set_gp_size (stdoutput
, g_switch_value
);
2015 /* On a native system other than VxWorks, sections must be aligned
2016 to 16 byte boundaries. When configured for an embedded ELF
2017 target, we don't bother. */
2018 if (strncmp (TARGET_OS
, "elf", 3) != 0
2019 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2021 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2022 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2023 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2026 /* Create a .reginfo section for register masks and a .mdebug
2027 section for debugging information. */
2035 subseg
= now_subseg
;
2037 /* The ABI says this section should be loaded so that the
2038 running program can access it. However, we don't load it
2039 if we are configured for an embedded target */
2040 flags
= SEC_READONLY
| SEC_DATA
;
2041 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2042 flags
|= SEC_ALLOC
| SEC_LOAD
;
2044 if (mips_abi
!= N64_ABI
)
2046 sec
= subseg_new (".reginfo", (subsegT
) 0);
2048 bfd_set_section_flags (stdoutput
, sec
, flags
);
2049 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2051 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2055 /* The 64-bit ABI uses a .MIPS.options section rather than
2056 .reginfo section. */
2057 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2058 bfd_set_section_flags (stdoutput
, sec
, flags
);
2059 bfd_set_section_alignment (stdoutput
, sec
, 3);
2061 /* Set up the option header. */
2063 Elf_Internal_Options opthdr
;
2066 opthdr
.kind
= ODK_REGINFO
;
2067 opthdr
.size
= (sizeof (Elf_External_Options
)
2068 + sizeof (Elf64_External_RegInfo
));
2071 f
= frag_more (sizeof (Elf_External_Options
));
2072 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2073 (Elf_External_Options
*) f
);
2075 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2079 if (ECOFF_DEBUGGING
)
2081 sec
= subseg_new (".mdebug", (subsegT
) 0);
2082 (void) bfd_set_section_flags (stdoutput
, sec
,
2083 SEC_HAS_CONTENTS
| SEC_READONLY
);
2084 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2086 else if (mips_flag_pdr
)
2088 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2089 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2090 SEC_READONLY
| SEC_RELOC
2092 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2095 subseg_set (seg
, subseg
);
2098 #endif /* OBJ_ELF */
2100 if (! ECOFF_DEBUGGING
)
2103 if (mips_fix_vr4120
)
2104 init_vr4120_conflicts ();
2110 if (! ECOFF_DEBUGGING
)
2115 md_assemble (char *str
)
2117 struct mips_cl_insn insn
;
2118 bfd_reloc_code_real_type unused_reloc
[3]
2119 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2121 imm_expr
.X_op
= O_absent
;
2122 imm2_expr
.X_op
= O_absent
;
2123 offset_expr
.X_op
= O_absent
;
2124 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2125 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2126 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2127 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2128 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2129 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2131 if (mips_opts
.mips16
)
2132 mips16_ip (str
, &insn
);
2135 mips_ip (str
, &insn
);
2136 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2137 str
, insn
.insn_opcode
));
2142 as_bad ("%s `%s'", insn_error
, str
);
2146 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2149 if (mips_opts
.mips16
)
2150 mips16_macro (&insn
);
2157 if (imm_expr
.X_op
!= O_absent
)
2158 append_insn (&insn
, &imm_expr
, imm_reloc
);
2159 else if (offset_expr
.X_op
!= O_absent
)
2160 append_insn (&insn
, &offset_expr
, offset_reloc
);
2162 append_insn (&insn
, NULL
, unused_reloc
);
2166 /* Convenience functions for abstracting away the differences between
2167 MIPS16 and non-MIPS16 relocations. */
2169 static inline bfd_boolean
2170 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2174 case BFD_RELOC_MIPS16_JMP
:
2175 case BFD_RELOC_MIPS16_GPREL
:
2176 case BFD_RELOC_MIPS16_GOT16
:
2177 case BFD_RELOC_MIPS16_CALL16
:
2178 case BFD_RELOC_MIPS16_HI16_S
:
2179 case BFD_RELOC_MIPS16_HI16
:
2180 case BFD_RELOC_MIPS16_LO16
:
2188 static inline bfd_boolean
2189 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2191 return reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
;
2194 static inline bfd_boolean
2195 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2197 return reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
;
2200 static inline bfd_boolean
2201 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2203 return reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
;
2206 /* Return true if the given relocation might need a matching %lo().
2207 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2208 need a matching %lo() when applied to local symbols. */
2210 static inline bfd_boolean
2211 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2213 return (HAVE_IN_PLACE_ADDENDS
2214 && (hi16_reloc_p (reloc
)
2215 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2216 all GOT16 relocations evaluate to "G". */
2217 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2220 /* Return the type of %lo() reloc needed by RELOC, given that
2221 reloc_needs_lo_p. */
2223 static inline bfd_reloc_code_real_type
2224 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2226 return mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
: BFD_RELOC_LO16
;
2229 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2232 static inline bfd_boolean
2233 fixup_has_matching_lo_p (fixS
*fixp
)
2235 return (fixp
->fx_next
!= NULL
2236 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2237 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2238 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2241 /* See whether instruction IP reads register REG. CLASS is the type
2245 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2246 enum mips_regclass regclass
)
2248 if (regclass
== MIPS16_REG
)
2250 gas_assert (mips_opts
.mips16
);
2251 reg
= mips16_to_32_reg_map
[reg
];
2252 regclass
= MIPS_GR_REG
;
2255 /* Don't report on general register ZERO, since it never changes. */
2256 if (regclass
== MIPS_GR_REG
&& reg
== ZERO
)
2259 if (regclass
== MIPS_FP_REG
)
2261 gas_assert (! mips_opts
.mips16
);
2262 /* If we are called with either $f0 or $f1, we must check $f0.
2263 This is not optimal, because it will introduce an unnecessary
2264 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2265 need to distinguish reading both $f0 and $f1 or just one of
2266 them. Note that we don't have to check the other way,
2267 because there is no instruction that sets both $f0 and $f1
2268 and requires a delay. */
2269 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2270 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2271 == (reg
&~ (unsigned) 1)))
2273 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2274 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2275 == (reg
&~ (unsigned) 1)))
2277 if ((ip
->insn_mo
->pinfo2
& INSN2_READ_FPR_Z
)
2278 && ((EXTRACT_OPERAND (FZ
, *ip
) & ~(unsigned) 1)
2279 == (reg
&~ (unsigned) 1)))
2282 else if (! mips_opts
.mips16
)
2284 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2285 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2287 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2288 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2290 if ((ip
->insn_mo
->pinfo2
& INSN2_READ_GPR_D
)
2291 && EXTRACT_OPERAND (RD
, *ip
) == reg
)
2293 if ((ip
->insn_mo
->pinfo2
& INSN2_READ_GPR_Z
)
2294 && EXTRACT_OPERAND (RZ
, *ip
) == reg
)
2299 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2300 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2302 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2303 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2305 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2306 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2309 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2311 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2313 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2315 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2316 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2323 /* This function returns true if modifying a register requires a
2327 reg_needs_delay (unsigned int reg
)
2329 unsigned long prev_pinfo
;
2331 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2332 if (! mips_opts
.noreorder
2333 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2334 && ! gpr_interlocks
)
2335 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2336 && ! cop_interlocks
)))
2338 /* A load from a coprocessor or from memory. All load delays
2339 delay the use of general register rt for one instruction. */
2340 /* Itbl support may require additional care here. */
2341 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2342 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2349 /* Move all labels in insn_labels to the current insertion point. */
2352 mips_move_labels (void)
2354 segment_info_type
*si
= seg_info (now_seg
);
2355 struct insn_label_list
*l
;
2358 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2360 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2361 symbol_set_frag (l
->label
, frag_now
);
2362 val
= (valueT
) frag_now_fix ();
2363 /* mips16 text labels are stored as odd. */
2364 if (mips_opts
.mips16
)
2366 S_SET_VALUE (l
->label
, val
);
2371 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2373 bfd_boolean linkonce
= FALSE
;
2374 segT symseg
= S_GET_SEGMENT (sym
);
2376 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2378 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2381 /* The GNU toolchain uses an extension for ELF: a section
2382 beginning with the magic string .gnu.linkonce is a
2383 linkonce section. */
2384 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2385 sizeof ".gnu.linkonce" - 1) == 0)
2392 /* Mark instruction labels in mips16 mode. This permits the linker to
2393 handle them specially, such as generating jalx instructions when
2394 needed. We also make them odd for the duration of the assembly, in
2395 order to generate the right sort of code. We will make them even
2396 in the adjust_symtab routine, while leaving them marked. This is
2397 convenient for the debugger and the disassembler. The linker knows
2398 to make them odd again. */
2401 mips16_mark_labels (void)
2403 segment_info_type
*si
= seg_info (now_seg
);
2404 struct insn_label_list
*l
;
2406 if (!mips_opts
.mips16
)
2409 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2411 symbolS
*label
= l
->label
;
2413 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2415 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2417 if ((S_GET_VALUE (label
) & 1) == 0
2418 /* Don't adjust the address if the label is global or weak, or
2419 in a link-once section, since we'll be emitting symbol reloc
2420 references to it which will be patched up by the linker, and
2421 the final value of the symbol may or may not be MIPS16. */
2422 && ! S_IS_WEAK (label
)
2423 && ! S_IS_EXTERNAL (label
)
2424 && ! s_is_linkonce (label
, now_seg
))
2425 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2429 /* End the current frag. Make it a variant frag and record the
2433 relax_close_frag (void)
2435 mips_macro_warning
.first_frag
= frag_now
;
2436 frag_var (rs_machine_dependent
, 0, 0,
2437 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2438 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2440 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2441 mips_relax
.first_fixup
= 0;
2444 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2445 See the comment above RELAX_ENCODE for more details. */
2448 relax_start (symbolS
*symbol
)
2450 gas_assert (mips_relax
.sequence
== 0);
2451 mips_relax
.sequence
= 1;
2452 mips_relax
.symbol
= symbol
;
2455 /* Start generating the second version of a relaxable sequence.
2456 See the comment above RELAX_ENCODE for more details. */
2461 gas_assert (mips_relax
.sequence
== 1);
2462 mips_relax
.sequence
= 2;
2465 /* End the current relaxable sequence. */
2470 gas_assert (mips_relax
.sequence
== 2);
2471 relax_close_frag ();
2472 mips_relax
.sequence
= 0;
2475 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2476 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2477 by VR4120 errata. */
2480 classify_vr4120_insn (const char *name
)
2482 if (strncmp (name
, "macc", 4) == 0)
2483 return FIX_VR4120_MACC
;
2484 if (strncmp (name
, "dmacc", 5) == 0)
2485 return FIX_VR4120_DMACC
;
2486 if (strncmp (name
, "mult", 4) == 0)
2487 return FIX_VR4120_MULT
;
2488 if (strncmp (name
, "dmult", 5) == 0)
2489 return FIX_VR4120_DMULT
;
2490 if (strstr (name
, "div"))
2491 return FIX_VR4120_DIV
;
2492 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2493 return FIX_VR4120_MTHILO
;
2494 return NUM_FIX_VR4120_CLASSES
;
2497 #define INSN_ERET 0x42000018
2498 #define INSN_DERET 0x4200001f
2500 /* Return the number of instructions that must separate INSN1 and INSN2,
2501 where INSN1 is the earlier instruction. Return the worst-case value
2502 for any INSN2 if INSN2 is null. */
2505 insns_between (const struct mips_cl_insn
*insn1
,
2506 const struct mips_cl_insn
*insn2
)
2508 unsigned long pinfo1
, pinfo2
;
2510 /* This function needs to know which pinfo flags are set for INSN2
2511 and which registers INSN2 uses. The former is stored in PINFO2 and
2512 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2513 will have every flag set and INSN2_USES_REG will always return true. */
2514 pinfo1
= insn1
->insn_mo
->pinfo
;
2515 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2517 #define INSN2_USES_REG(REG, CLASS) \
2518 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2520 /* For most targets, write-after-read dependencies on the HI and LO
2521 registers must be separated by at least two instructions. */
2522 if (!hilo_interlocks
)
2524 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2526 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2530 /* If we're working around r7000 errata, there must be two instructions
2531 between an mfhi or mflo and any instruction that uses the result. */
2532 if (mips_7000_hilo_fix
2533 && MF_HILO_INSN (pinfo1
)
2534 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2537 /* If we're working around 24K errata, one instruction is required
2538 if an ERET or DERET is followed by a branch instruction. */
2541 if (insn1
->insn_opcode
== INSN_ERET
2542 || insn1
->insn_opcode
== INSN_DERET
)
2545 || insn2
->insn_opcode
== INSN_ERET
2546 || insn2
->insn_opcode
== INSN_DERET
2547 || (insn2
->insn_mo
->pinfo
2548 & (INSN_UNCOND_BRANCH_DELAY
2549 | INSN_COND_BRANCH_DELAY
2550 | INSN_COND_BRANCH_LIKELY
)) != 0)
2555 /* If working around VR4120 errata, check for combinations that need
2556 a single intervening instruction. */
2557 if (mips_fix_vr4120
)
2559 unsigned int class1
, class2
;
2561 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2562 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2566 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2567 if (vr4120_conflicts
[class1
] & (1 << class2
))
2572 if (!mips_opts
.mips16
)
2574 /* Check for GPR or coprocessor load delays. All such delays
2575 are on the RT register. */
2576 /* Itbl support may require additional care here. */
2577 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2578 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2580 know (pinfo1
& INSN_WRITE_GPR_T
);
2581 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2585 /* Check for generic coprocessor hazards.
2587 This case is not handled very well. There is no special
2588 knowledge of CP0 handling, and the coprocessors other than
2589 the floating point unit are not distinguished at all. */
2590 /* Itbl support may require additional care here. FIXME!
2591 Need to modify this to include knowledge about
2592 user specified delays! */
2593 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2594 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2596 /* Handle cases where INSN1 writes to a known general coprocessor
2597 register. There must be a one instruction delay before INSN2
2598 if INSN2 reads that register, otherwise no delay is needed. */
2599 if (pinfo1
& INSN_WRITE_FPR_T
)
2601 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2604 else if (pinfo1
& INSN_WRITE_FPR_S
)
2606 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2611 /* Read-after-write dependencies on the control registers
2612 require a two-instruction gap. */
2613 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2614 && (pinfo2
& INSN_READ_COND_CODE
))
2617 /* We don't know exactly what INSN1 does. If INSN2 is
2618 also a coprocessor instruction, assume there must be
2619 a one instruction gap. */
2620 if (pinfo2
& INSN_COP
)
2625 /* Check for read-after-write dependencies on the coprocessor
2626 control registers in cases where INSN1 does not need a general
2627 coprocessor delay. This means that INSN1 is a floating point
2628 comparison instruction. */
2629 /* Itbl support may require additional care here. */
2630 else if (!cop_interlocks
2631 && (pinfo1
& INSN_WRITE_COND_CODE
)
2632 && (pinfo2
& INSN_READ_COND_CODE
))
2636 #undef INSN2_USES_REG
2641 /* Return the number of nops that would be needed to work around the
2642 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2643 the MAX_VR4130_NOPS instructions described by HIST. */
2646 nops_for_vr4130 (const struct mips_cl_insn
*hist
,
2647 const struct mips_cl_insn
*insn
)
2651 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2652 are not affected by the errata. */
2654 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2655 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2656 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2659 /* Search for the first MFLO or MFHI. */
2660 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2661 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
2663 /* Extract the destination register. */
2664 if (mips_opts
.mips16
)
2665 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, hist
[i
])];
2667 reg
= EXTRACT_OPERAND (RD
, hist
[i
]);
2669 /* No nops are needed if INSN reads that register. */
2670 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2673 /* ...or if any of the intervening instructions do. */
2674 for (j
= 0; j
< i
; j
++)
2675 if (insn_uses_reg (&hist
[j
], reg
, MIPS_GR_REG
))
2678 return MAX_VR4130_NOPS
- i
;
2683 /* Return the number of nops that would be needed if instruction INSN
2684 immediately followed the MAX_NOPS instructions given by HIST,
2685 where HIST[0] is the most recent instruction. If INSN is null,
2686 return the worse-case number of nops for any instruction. */
2689 nops_for_insn (const struct mips_cl_insn
*hist
,
2690 const struct mips_cl_insn
*insn
)
2692 int i
, nops
, tmp_nops
;
2695 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2697 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
2698 if (tmp_nops
> nops
)
2702 if (mips_fix_vr4130
)
2704 tmp_nops
= nops_for_vr4130 (hist
, insn
);
2705 if (tmp_nops
> nops
)
2712 /* The variable arguments provide NUM_INSNS extra instructions that
2713 might be added to HIST. Return the largest number of nops that
2714 would be needed after the extended sequence. */
2717 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*hist
, ...)
2720 struct mips_cl_insn buffer
[MAX_NOPS
];
2721 struct mips_cl_insn
*cursor
;
2724 va_start (args
, hist
);
2725 cursor
= buffer
+ num_insns
;
2726 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2727 while (cursor
> buffer
)
2728 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2730 nops
= nops_for_insn (buffer
, NULL
);
2735 /* Like nops_for_insn, but if INSN is a branch, take into account the
2736 worst-case delay for the branch target. */
2739 nops_for_insn_or_target (const struct mips_cl_insn
*hist
,
2740 const struct mips_cl_insn
*insn
)
2744 nops
= nops_for_insn (hist
, insn
);
2745 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2746 | INSN_COND_BRANCH_DELAY
2747 | INSN_COND_BRANCH_LIKELY
))
2749 tmp_nops
= nops_for_sequence (2, hist
, insn
, NOP_INSN
);
2750 if (tmp_nops
> nops
)
2753 else if (mips_opts
.mips16
2754 && (insn
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2755 | MIPS16_INSN_COND_BRANCH
)))
2757 tmp_nops
= nops_for_sequence (1, hist
, insn
);
2758 if (tmp_nops
> nops
)
2764 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2767 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
2769 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
2770 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
2773 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2774 jr target pc &= 'hffff_ffff_cfff_ffff. */
2777 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
2779 if (strcmp (ip
->insn_mo
->name
, "j") == 0
2780 || strcmp (ip
->insn_mo
->name
, "jr") == 0
2781 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
2789 sreg
= EXTRACT_OPERAND (RS
, *ip
);
2790 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
2793 ep
.X_op
= O_constant
;
2794 ep
.X_add_number
= 0xcfff0000;
2795 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
2796 ep
.X_add_number
= 0xffff;
2797 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
2798 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
2803 fix_loongson2f (struct mips_cl_insn
* ip
)
2805 if (mips_fix_loongson2f_nop
)
2806 fix_loongson2f_nop (ip
);
2808 if (mips_fix_loongson2f_jump
)
2809 fix_loongson2f_jump (ip
);
2812 /* Output an instruction. IP is the instruction information.
2813 ADDRESS_EXPR is an operand of the instruction to be used with
2817 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2818 bfd_reloc_code_real_type
*reloc_type
)
2820 unsigned long prev_pinfo
, pinfo
;
2821 unsigned long prev_pinfo2
, pinfo2
;
2822 relax_stateT prev_insn_frag_type
= 0;
2823 bfd_boolean relaxed_branch
= FALSE
;
2824 segment_info_type
*si
= seg_info (now_seg
);
2826 if (mips_fix_loongson2f
)
2827 fix_loongson2f (ip
);
2829 /* Mark instruction labels in mips16 mode. */
2830 mips16_mark_labels ();
2832 file_ase_mips16
|= mips_opts
.mips16
;
2834 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2835 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
2836 pinfo
= ip
->insn_mo
->pinfo
;
2837 pinfo2
= ip
->insn_mo
->pinfo2
;
2839 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2841 /* There are a lot of optimizations we could do that we don't.
2842 In particular, we do not, in general, reorder instructions.
2843 If you use gcc with optimization, it will reorder
2844 instructions and generally do much more optimization then we
2845 do here; repeating all that work in the assembler would only
2846 benefit hand written assembly code, and does not seem worth
2848 int nops
= (mips_optimize
== 0
2849 ? nops_for_insn (history
, NULL
)
2850 : nops_for_insn_or_target (history
, ip
));
2854 unsigned long old_frag_offset
;
2857 old_frag
= frag_now
;
2858 old_frag_offset
= frag_now_fix ();
2860 for (i
= 0; i
< nops
; i
++)
2865 listing_prev_line ();
2866 /* We may be at the start of a variant frag. In case we
2867 are, make sure there is enough space for the frag
2868 after the frags created by listing_prev_line. The
2869 argument to frag_grow here must be at least as large
2870 as the argument to all other calls to frag_grow in
2871 this file. We don't have to worry about being in the
2872 middle of a variant frag, because the variants insert
2873 all needed nop instructions themselves. */
2877 mips_move_labels ();
2879 #ifndef NO_ECOFF_DEBUGGING
2880 if (ECOFF_DEBUGGING
)
2881 ecoff_fix_loc (old_frag
, old_frag_offset
);
2885 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2887 /* Work out how many nops in prev_nop_frag are needed by IP. */
2888 int nops
= nops_for_insn_or_target (history
, ip
);
2889 gas_assert (nops
<= prev_nop_frag_holds
);
2891 /* Enforce NOPS as a minimum. */
2892 if (nops
> prev_nop_frag_required
)
2893 prev_nop_frag_required
= nops
;
2895 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2897 /* Settle for the current number of nops. Update the history
2898 accordingly (for the benefit of any future .set reorder code). */
2899 prev_nop_frag
= NULL
;
2900 insert_into_history (prev_nop_frag_since
,
2901 prev_nop_frag_holds
, NOP_INSN
);
2905 /* Allow this instruction to replace one of the nops that was
2906 tentatively added to prev_nop_frag. */
2907 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2908 prev_nop_frag_holds
--;
2909 prev_nop_frag_since
++;
2914 /* The value passed to dwarf2_emit_insn is the distance between
2915 the beginning of the current instruction and the address that
2916 should be recorded in the debug tables. For MIPS16 debug info
2917 we want to use ISA-encoded addresses, so we pass -1 for an
2918 address higher by one than the current. */
2919 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2922 /* Record the frag type before frag_var. */
2923 if (history
[0].frag
)
2924 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2927 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2928 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2929 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2930 && mips_relax_branch
2931 /* Don't try branch relaxation within .set nomacro, or within
2932 .set noat if we use $at for PIC computations. If it turns
2933 out that the branch was out-of-range, we'll get an error. */
2934 && !mips_opts
.warn_about_macros
2935 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
2936 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
2937 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
))
2938 && !mips_opts
.mips16
)
2940 relaxed_branch
= TRUE
;
2941 add_relaxed_insn (ip
, (relaxed_branch_length
2943 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2944 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2948 pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2949 pinfo
& INSN_COND_BRANCH_LIKELY
,
2950 pinfo
& INSN_WRITE_GPR_31
,
2952 address_expr
->X_add_symbol
,
2953 address_expr
->X_add_number
);
2954 *reloc_type
= BFD_RELOC_UNUSED
;
2956 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2958 /* We need to set up a variant frag. */
2959 gas_assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2960 add_relaxed_insn (ip
, 4, 0,
2962 (*reloc_type
- BFD_RELOC_UNUSED
,
2963 mips16_small
, mips16_ext
,
2964 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2965 history
[0].mips16_absolute_jump_p
),
2966 make_expr_symbol (address_expr
), 0);
2968 else if (mips_opts
.mips16
2970 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2972 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2973 /* Make sure there is enough room to swap this instruction with
2974 a following jump instruction. */
2976 add_fixed_insn (ip
);
2980 if (mips_opts
.mips16
2981 && mips_opts
.noreorder
2982 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2983 as_warn (_("extended instruction in delay slot"));
2985 if (mips_relax
.sequence
)
2987 /* If we've reached the end of this frag, turn it into a variant
2988 frag and record the information for the instructions we've
2990 if (frag_room () < 4)
2991 relax_close_frag ();
2992 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2995 if (mips_relax
.sequence
!= 2)
2996 mips_macro_warning
.sizes
[0] += 4;
2997 if (mips_relax
.sequence
!= 1)
2998 mips_macro_warning
.sizes
[1] += 4;
3000 if (mips_opts
.mips16
)
3003 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
3005 add_fixed_insn (ip
);
3008 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
3010 if (address_expr
->X_op
== O_constant
)
3014 switch (*reloc_type
)
3017 ip
->insn_opcode
|= address_expr
->X_add_number
;
3020 case BFD_RELOC_MIPS_HIGHEST
:
3021 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
3022 ip
->insn_opcode
|= tmp
& 0xffff;
3025 case BFD_RELOC_MIPS_HIGHER
:
3026 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
3027 ip
->insn_opcode
|= tmp
& 0xffff;
3030 case BFD_RELOC_HI16_S
:
3031 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
3032 ip
->insn_opcode
|= tmp
& 0xffff;
3035 case BFD_RELOC_HI16
:
3036 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
3039 case BFD_RELOC_UNUSED
:
3040 case BFD_RELOC_LO16
:
3041 case BFD_RELOC_MIPS_GOT_DISP
:
3042 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
3045 case BFD_RELOC_MIPS_JMP
:
3046 if ((address_expr
->X_add_number
& 3) != 0)
3047 as_bad (_("jump to misaligned address (0x%lx)"),
3048 (unsigned long) address_expr
->X_add_number
);
3049 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
3052 case BFD_RELOC_MIPS16_JMP
:
3053 if ((address_expr
->X_add_number
& 3) != 0)
3054 as_bad (_("jump to misaligned address (0x%lx)"),
3055 (unsigned long) address_expr
->X_add_number
);
3057 (((address_expr
->X_add_number
& 0x7c0000) << 3)
3058 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
3059 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
3062 case BFD_RELOC_16_PCREL_S2
:
3063 if ((address_expr
->X_add_number
& 3) != 0)
3064 as_bad (_("branch to misaligned address (0x%lx)"),
3065 (unsigned long) address_expr
->X_add_number
);
3066 if (mips_relax_branch
)
3068 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
3069 as_bad (_("branch address range overflow (0x%lx)"),
3070 (unsigned long) address_expr
->X_add_number
);
3071 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
3078 else if (*reloc_type
< BFD_RELOC_UNUSED
)
3081 reloc_howto_type
*howto
;
3084 /* In a compound relocation, it is the final (outermost)
3085 operator that determines the relocated field. */
3086 for (i
= 1; i
< 3; i
++)
3087 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
3090 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
3093 /* To reproduce this failure try assembling gas/testsuites/
3094 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3096 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type
[i
- 1]);
3097 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
3100 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
3101 bfd_get_reloc_size (howto
),
3103 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
3106 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3107 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
3108 && ip
->fixp
[0]->fx_addsy
)
3109 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
3111 /* These relocations can have an addend that won't fit in
3112 4 octets for 64bit assembly. */
3114 && ! howto
->partial_inplace
3115 && (reloc_type
[0] == BFD_RELOC_16
3116 || reloc_type
[0] == BFD_RELOC_32
3117 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
3118 || reloc_type
[0] == BFD_RELOC_GPREL16
3119 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
3120 || reloc_type
[0] == BFD_RELOC_GPREL32
3121 || reloc_type
[0] == BFD_RELOC_64
3122 || reloc_type
[0] == BFD_RELOC_CTOR
3123 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
3124 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
3125 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
3126 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
3127 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
3128 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
3129 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
3130 || hi16_reloc_p (reloc_type
[0])
3131 || lo16_reloc_p (reloc_type
[0])))
3132 ip
->fixp
[0]->fx_no_overflow
= 1;
3134 if (mips_relax
.sequence
)
3136 if (mips_relax
.first_fixup
== 0)
3137 mips_relax
.first_fixup
= ip
->fixp
[0];
3139 else if (reloc_needs_lo_p (*reloc_type
))
3141 struct mips_hi_fixup
*hi_fixup
;
3143 /* Reuse the last entry if it already has a matching %lo. */
3144 hi_fixup
= mips_hi_fixup_list
;
3146 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
3148 hi_fixup
= ((struct mips_hi_fixup
*)
3149 xmalloc (sizeof (struct mips_hi_fixup
)));
3150 hi_fixup
->next
= mips_hi_fixup_list
;
3151 mips_hi_fixup_list
= hi_fixup
;
3153 hi_fixup
->fixp
= ip
->fixp
[0];
3154 hi_fixup
->seg
= now_seg
;
3157 /* Add fixups for the second and third relocations, if given.
3158 Note that the ABI allows the second relocation to be
3159 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3160 moment we only use RSS_UNDEF, but we could add support
3161 for the others if it ever becomes necessary. */
3162 for (i
= 1; i
< 3; i
++)
3163 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
3165 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
3166 ip
->fixp
[0]->fx_size
, NULL
, 0,
3167 FALSE
, reloc_type
[i
]);
3169 /* Use fx_tcbit to mark compound relocs. */
3170 ip
->fixp
[0]->fx_tcbit
= 1;
3171 ip
->fixp
[i
]->fx_tcbit
= 1;
3177 /* Update the register mask information. */
3178 if (! mips_opts
.mips16
)
3180 if ((pinfo
& INSN_WRITE_GPR_D
) || (pinfo2
& INSN2_READ_GPR_D
))
3181 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
3182 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
3183 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
3184 if (pinfo
& INSN_READ_GPR_S
)
3185 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
3186 if (pinfo
& INSN_WRITE_GPR_31
)
3187 mips_gprmask
|= 1 << RA
;
3188 if (pinfo2
& (INSN2_WRITE_GPR_Z
| INSN2_READ_GPR_Z
))
3189 mips_gprmask
|= 1 << EXTRACT_OPERAND (RZ
, *ip
);
3190 if (pinfo
& INSN_WRITE_FPR_D
)
3191 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
3192 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
3193 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
3194 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
3195 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
3196 if ((pinfo
& INSN_READ_FPR_R
) != 0)
3197 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
3198 if (pinfo2
& (INSN2_WRITE_FPR_Z
| INSN2_READ_FPR_Z
))
3199 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FZ
, *ip
);
3200 if (pinfo
& INSN_COP
)
3202 /* We don't keep enough information to sort these cases out.
3203 The itbl support does keep this information however, although
3204 we currently don't support itbl fprmats as part of the cop
3205 instruction. May want to add this support in the future. */
3207 /* Never set the bit for $0, which is always zero. */
3208 mips_gprmask
&= ~1 << 0;
3212 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
3213 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
3214 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
3215 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
3216 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3217 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
3218 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
3219 mips_gprmask
|= 1 << TREG
;
3220 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
3221 mips_gprmask
|= 1 << SP
;
3222 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
3223 mips_gprmask
|= 1 << RA
;
3224 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3225 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3226 if (pinfo
& MIPS16_INSN_READ_Z
)
3227 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
3228 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3229 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3232 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3234 /* Filling the branch delay slot is more complex. We try to
3235 switch the branch with the previous instruction, which we can
3236 do if the previous instruction does not set up a condition
3237 that the branch tests and if the branch is not itself the
3238 target of any branch. */
3239 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3240 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3242 if (mips_optimize
< 2
3243 /* If we have seen .set volatile or .set nomove, don't
3245 || mips_opts
.nomove
!= 0
3246 /* We can't swap if the previous instruction's position
3248 || history
[0].fixed_p
3249 /* If the previous previous insn was in a .set
3250 noreorder, we can't swap. Actually, the MIPS
3251 assembler will swap in this situation. However, gcc
3252 configured -with-gnu-as will generate code like
3258 in which we can not swap the bne and INSN. If gcc is
3259 not configured -with-gnu-as, it does not output the
3261 || history
[1].noreorder_p
3262 /* If the branch is itself the target of a branch, we
3263 can not swap. We cheat on this; all we check for is
3264 whether there is a label on this instruction. If
3265 there are any branches to anything other than a
3266 label, users must use .set noreorder. */
3267 || si
->label_list
!= NULL
3268 /* If the previous instruction is in a variant frag
3269 other than this branch's one, we cannot do the swap.
3270 This does not apply to the mips16, which uses variant
3271 frags for different purposes. */
3272 || (! mips_opts
.mips16
3273 && prev_insn_frag_type
== rs_machine_dependent
)
3274 /* Check for conflicts between the branch and the instructions
3275 before the candidate delay slot. */
3276 || nops_for_insn (history
+ 1, ip
) > 0
3277 /* Check for conflicts between the swapped sequence and the
3278 target of the branch. */
3279 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
3280 /* We do not swap with a trap instruction, since it
3281 complicates trap handlers to have the trap
3282 instruction be in a delay slot. */
3283 || (prev_pinfo
& INSN_TRAP
)
3284 /* If the branch reads a register that the previous
3285 instruction sets, we can not swap. */
3286 || (! mips_opts
.mips16
3287 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3288 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
3290 || (! mips_opts
.mips16
3291 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3292 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3294 || (! mips_opts
.mips16
3295 && (prev_pinfo2
& INSN2_WRITE_GPR_Z
)
3296 && insn_uses_reg (ip
, EXTRACT_OPERAND (RZ
, history
[0]),
3298 || (mips_opts
.mips16
3299 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3301 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3303 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3305 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3307 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3309 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3311 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3312 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3313 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3314 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3315 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3316 && insn_uses_reg (ip
,
3317 MIPS16OP_EXTRACT_REG32R
3318 (history
[0].insn_opcode
),
3320 /* If the branch writes a register that the previous
3321 instruction sets, we can not swap (we know that
3322 branches write only to RD or to $31). */
3323 || (! mips_opts
.mips16
3324 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3325 && (((pinfo
& INSN_WRITE_GPR_D
)
3326 && (EXTRACT_OPERAND (RT
, history
[0])
3327 == EXTRACT_OPERAND (RD
, *ip
)))
3328 || ((pinfo
& INSN_WRITE_GPR_31
)
3329 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3330 || (! mips_opts
.mips16
3331 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3332 && (((pinfo
& INSN_WRITE_GPR_D
)
3333 && (EXTRACT_OPERAND (RD
, history
[0])
3334 == EXTRACT_OPERAND (RD
, *ip
)))
3335 || ((pinfo
& INSN_WRITE_GPR_31
)
3336 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3337 || (mips_opts
.mips16
3338 && (pinfo
& MIPS16_INSN_WRITE_31
)
3339 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3340 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3341 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3343 /* If the branch writes a register that the previous
3344 instruction reads, we can not swap (we know that
3345 branches only write to RD or to $31). */
3346 || (! mips_opts
.mips16
3347 && (pinfo
& INSN_WRITE_GPR_D
)
3348 && insn_uses_reg (&history
[0],
3349 EXTRACT_OPERAND (RD
, *ip
),
3351 || (! mips_opts
.mips16
3352 && (pinfo
& INSN_WRITE_GPR_31
)
3353 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3354 || (mips_opts
.mips16
3355 && (pinfo
& MIPS16_INSN_WRITE_31
)
3356 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3357 /* If one instruction sets a condition code and the
3358 other one uses a condition code, we can not swap. */
3359 || ((pinfo
& INSN_READ_COND_CODE
)
3360 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3361 || ((pinfo
& INSN_WRITE_COND_CODE
)
3362 && (prev_pinfo
& INSN_READ_COND_CODE
))
3363 /* If the previous instruction uses the PC, we can not
3365 || (mips_opts
.mips16
3366 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3367 /* If the previous instruction had a fixup in mips16
3368 mode, we can not swap. This normally means that the
3369 previous instruction was a 4 byte branch anyhow. */
3370 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3371 /* If the previous instruction is a sync, sync.l, or
3372 sync.p, we can not swap. */
3373 || (prev_pinfo
& INSN_SYNC
)
3374 /* If the previous instruction is an ERET or
3375 DERET, avoid the swap. */
3376 || (history
[0].insn_opcode
== INSN_ERET
)
3377 || (history
[0].insn_opcode
== INSN_DERET
))
3379 if (mips_opts
.mips16
3380 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3381 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3382 && ISA_SUPPORTS_MIPS16E
)
3384 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3385 ip
->insn_opcode
|= 0x0080;
3387 insert_into_history (0, 1, ip
);
3391 /* We could do even better for unconditional branches to
3392 portions of this object file; we could pick up the
3393 instruction at the destination, put it in the delay
3394 slot, and bump the destination address. */
3395 insert_into_history (0, 1, ip
);
3399 if (mips_relax
.sequence
)
3400 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3404 /* It looks like we can actually do the swap. */
3405 struct mips_cl_insn delay
= history
[0];
3406 if (mips_opts
.mips16
)
3408 know (delay
.frag
== ip
->frag
);
3409 move_insn (ip
, delay
.frag
, delay
.where
);
3410 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3412 else if (relaxed_branch
)
3414 /* Add the delay slot instruction to the end of the
3415 current frag and shrink the fixed part of the
3416 original frag. If the branch occupies the tail of
3417 the latter, move it backwards to cover the gap. */
3418 delay
.frag
->fr_fix
-= 4;
3419 if (delay
.frag
== ip
->frag
)
3420 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3421 add_fixed_insn (&delay
);
3425 move_insn (&delay
, ip
->frag
, ip
->where
);
3426 move_insn (ip
, history
[0].frag
, history
[0].where
);
3430 insert_into_history (0, 1, &delay
);
3433 /* If that was an unconditional branch, forget the previous
3434 insn information. */
3435 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3437 mips_no_prev_insn ();
3440 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3442 /* We don't yet optimize a branch likely. What we should do
3443 is look at the target, copy the instruction found there
3444 into the delay slot, and increment the branch to jump to
3445 the next instruction. */
3446 insert_into_history (0, 1, ip
);
3450 insert_into_history (0, 1, ip
);
3453 insert_into_history (0, 1, ip
);
3455 /* We just output an insn, so the next one doesn't have a label. */
3456 mips_clear_insn_labels ();
3459 /* Forget that there was any previous instruction or label. */
3462 mips_no_prev_insn (void)
3464 prev_nop_frag
= NULL
;
3465 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3466 mips_clear_insn_labels ();
3469 /* This function must be called before we emit something other than
3470 instructions. It is like mips_no_prev_insn except that it inserts
3471 any NOPS that might be needed by previous instructions. */
3474 mips_emit_delays (void)
3476 if (! mips_opts
.noreorder
)
3478 int nops
= nops_for_insn (history
, NULL
);
3482 add_fixed_insn (NOP_INSN
);
3483 mips_move_labels ();
3486 mips_no_prev_insn ();
3489 /* Start a (possibly nested) noreorder block. */
3492 start_noreorder (void)
3494 if (mips_opts
.noreorder
== 0)
3499 /* None of the instructions before the .set noreorder can be moved. */
3500 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3501 history
[i
].fixed_p
= 1;
3503 /* Insert any nops that might be needed between the .set noreorder
3504 block and the previous instructions. We will later remove any
3505 nops that turn out not to be needed. */
3506 nops
= nops_for_insn (history
, NULL
);
3509 if (mips_optimize
!= 0)
3511 /* Record the frag which holds the nop instructions, so
3512 that we can remove them if we don't need them. */
3513 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3514 prev_nop_frag
= frag_now
;
3515 prev_nop_frag_holds
= nops
;
3516 prev_nop_frag_required
= 0;
3517 prev_nop_frag_since
= 0;
3520 for (; nops
> 0; --nops
)
3521 add_fixed_insn (NOP_INSN
);
3523 /* Move on to a new frag, so that it is safe to simply
3524 decrease the size of prev_nop_frag. */
3525 frag_wane (frag_now
);
3527 mips_move_labels ();
3529 mips16_mark_labels ();
3530 mips_clear_insn_labels ();
3532 mips_opts
.noreorder
++;
3533 mips_any_noreorder
= 1;
3536 /* End a nested noreorder block. */
3539 end_noreorder (void)
3542 mips_opts
.noreorder
--;
3543 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3545 /* Commit to inserting prev_nop_frag_required nops and go back to
3546 handling nop insertion the .set reorder way. */
3547 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3548 * (mips_opts
.mips16
? 2 : 4));
3549 insert_into_history (prev_nop_frag_since
,
3550 prev_nop_frag_required
, NOP_INSN
);
3551 prev_nop_frag
= NULL
;
3555 /* Set up global variables for the start of a new macro. */
3560 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3561 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3562 && (history
[0].insn_mo
->pinfo
3563 & (INSN_UNCOND_BRANCH_DELAY
3564 | INSN_COND_BRANCH_DELAY
3565 | INSN_COND_BRANCH_LIKELY
)) != 0);
3568 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3569 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3570 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3573 macro_warning (relax_substateT subtype
)
3575 if (subtype
& RELAX_DELAY_SLOT
)
3576 return _("Macro instruction expanded into multiple instructions"
3577 " in a branch delay slot");
3578 else if (subtype
& RELAX_NOMACRO
)
3579 return _("Macro instruction expanded into multiple instructions");
3584 /* Finish up a macro. Emit warnings as appropriate. */
3589 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3591 relax_substateT subtype
;
3593 /* Set up the relaxation warning flags. */
3595 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3596 subtype
|= RELAX_SECOND_LONGER
;
3597 if (mips_opts
.warn_about_macros
)
3598 subtype
|= RELAX_NOMACRO
;
3599 if (mips_macro_warning
.delay_slot_p
)
3600 subtype
|= RELAX_DELAY_SLOT
;
3602 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3604 /* Either the macro has a single implementation or both
3605 implementations are longer than 4 bytes. Emit the
3607 const char *msg
= macro_warning (subtype
);
3609 as_warn ("%s", msg
);
3613 /* One implementation might need a warning but the other
3614 definitely doesn't. */
3615 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3620 /* Read a macro's relocation codes from *ARGS and store them in *R.
3621 The first argument in *ARGS will be either the code for a single
3622 relocation or -1 followed by the three codes that make up a
3623 composite relocation. */
3626 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3630 next
= va_arg (*args
, int);
3632 r
[0] = (bfd_reloc_code_real_type
) next
;
3634 for (i
= 0; i
< 3; i
++)
3635 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3638 /* Build an instruction created by a macro expansion. This is passed
3639 a pointer to the count of instructions created so far, an
3640 expression, the name of the instruction to build, an operand format
3641 string, and corresponding arguments. */
3644 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3646 const struct mips_opcode
*mo
;
3647 struct mips_cl_insn insn
;
3648 bfd_reloc_code_real_type r
[3];
3651 va_start (args
, fmt
);
3653 if (mips_opts
.mips16
)
3655 mips16_macro_build (ep
, name
, fmt
, &args
);
3660 r
[0] = BFD_RELOC_UNUSED
;
3661 r
[1] = BFD_RELOC_UNUSED
;
3662 r
[2] = BFD_RELOC_UNUSED
;
3663 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3665 gas_assert (strcmp (name
, mo
->name
) == 0);
3669 /* Search until we get a match for NAME. It is assumed here that
3670 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3671 if (strcmp (fmt
, mo
->args
) == 0
3672 && mo
->pinfo
!= INSN_MACRO
3673 && is_opcode_valid (mo
))
3677 gas_assert (mo
->name
);
3678 gas_assert (strcmp (name
, mo
->name
) == 0);
3681 create_insn (&insn
, mo
);
3699 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3704 /* Note that in the macro case, these arguments are already
3705 in MSB form. (When handling the instruction in the
3706 non-macro case, these arguments are sizes from which
3707 MSB values must be calculated.) */
3708 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3714 /* Note that in the macro case, these arguments are already
3715 in MSBD form. (When handling the instruction in the
3716 non-macro case, these arguments are sizes from which
3717 MSBD values must be calculated.) */
3718 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3722 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3731 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3737 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3741 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3746 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3752 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3757 int tmp
= va_arg (args
, int);
3759 INSERT_OPERAND (RT
, insn
, tmp
);
3760 INSERT_OPERAND (RD
, insn
, tmp
);
3766 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3773 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3777 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3781 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3785 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3789 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3796 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3801 macro_read_relocs (&args
, r
);
3802 gas_assert (*r
== BFD_RELOC_GPREL16
3803 || *r
== BFD_RELOC_MIPS_HIGHER
3804 || *r
== BFD_RELOC_HI16_S
3805 || *r
== BFD_RELOC_LO16
3806 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
3810 macro_read_relocs (&args
, r
);
3814 macro_read_relocs (&args
, r
);
3815 gas_assert (ep
!= NULL
3816 && (ep
->X_op
== O_constant
3817 || (ep
->X_op
== O_symbol
3818 && (*r
== BFD_RELOC_MIPS_HIGHEST
3819 || *r
== BFD_RELOC_HI16_S
3820 || *r
== BFD_RELOC_HI16
3821 || *r
== BFD_RELOC_GPREL16
3822 || *r
== BFD_RELOC_MIPS_GOT_HI16
3823 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3827 gas_assert (ep
!= NULL
);
3830 * This allows macro() to pass an immediate expression for
3831 * creating short branches without creating a symbol.
3833 * We don't allow branch relaxation for these branches, as
3834 * they should only appear in ".set nomacro" anyway.
3836 if (ep
->X_op
== O_constant
)
3838 if ((ep
->X_add_number
& 3) != 0)
3839 as_bad (_("branch to misaligned address (0x%lx)"),
3840 (unsigned long) ep
->X_add_number
);
3841 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3842 as_bad (_("branch address range overflow (0x%lx)"),
3843 (unsigned long) ep
->X_add_number
);
3844 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3848 *r
= BFD_RELOC_16_PCREL_S2
;
3852 gas_assert (ep
!= NULL
);
3853 *r
= BFD_RELOC_MIPS_JMP
;
3857 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3861 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3870 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3872 append_insn (&insn
, ep
, r
);
3876 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3879 struct mips_opcode
*mo
;
3880 struct mips_cl_insn insn
;
3881 bfd_reloc_code_real_type r
[3]
3882 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3884 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3886 gas_assert (strcmp (name
, mo
->name
) == 0);
3888 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3891 gas_assert (mo
->name
);
3892 gas_assert (strcmp (name
, mo
->name
) == 0);
3895 create_insn (&insn
, mo
);
3913 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
3918 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
3922 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
3926 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
3936 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
3943 regno
= va_arg (*args
, int);
3944 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3945 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3966 gas_assert (ep
!= NULL
);
3968 if (ep
->X_op
!= O_constant
)
3969 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3972 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3973 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3976 *r
= BFD_RELOC_UNUSED
;
3982 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
3989 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3991 append_insn (&insn
, ep
, r
);
3995 * Sign-extend 32-bit mode constants that have bit 31 set and all
3996 * higher bits unset.
3999 normalize_constant_expr (expressionS
*ex
)
4001 if (ex
->X_op
== O_constant
4002 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
4003 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
4008 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4009 * all higher bits unset.
4012 normalize_address_expr (expressionS
*ex
)
4014 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
4015 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
4016 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
4017 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
4022 * Generate a "jalr" instruction with a relocation hint to the called
4023 * function. This occurs in NewABI PIC code.
4026 macro_build_jalr (expressionS
*ep
)
4030 if (MIPS_JALR_HINT_P (ep
))
4035 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
4036 if (MIPS_JALR_HINT_P (ep
))
4037 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
4038 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
4042 * Generate a "lui" instruction.
4045 macro_build_lui (expressionS
*ep
, int regnum
)
4047 expressionS high_expr
;
4048 const struct mips_opcode
*mo
;
4049 struct mips_cl_insn insn
;
4050 bfd_reloc_code_real_type r
[3]
4051 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4052 const char *name
= "lui";
4053 const char *fmt
= "t,u";
4055 gas_assert (! mips_opts
.mips16
);
4059 if (high_expr
.X_op
== O_constant
)
4061 /* We can compute the instruction now without a relocation entry. */
4062 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
4064 *r
= BFD_RELOC_UNUSED
;
4068 gas_assert (ep
->X_op
== O_symbol
);
4069 /* _gp_disp is a special case, used from s_cpload.
4070 __gnu_local_gp is used if mips_no_shared. */
4071 gas_assert (mips_pic
== NO_PIC
4073 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
4074 || (! mips_in_shared
4075 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
4076 "__gnu_local_gp") == 0));
4077 *r
= BFD_RELOC_HI16_S
;
4080 mo
= hash_find (op_hash
, name
);
4081 gas_assert (strcmp (name
, mo
->name
) == 0);
4082 gas_assert (strcmp (fmt
, mo
->args
) == 0);
4083 create_insn (&insn
, mo
);
4085 insn
.insn_opcode
= insn
.insn_mo
->match
;
4086 INSERT_OPERAND (RT
, insn
, regnum
);
4087 if (*r
== BFD_RELOC_UNUSED
)
4089 insn
.insn_opcode
|= high_expr
.X_add_number
;
4090 append_insn (&insn
, NULL
, r
);
4093 append_insn (&insn
, &high_expr
, r
);
4096 /* Generate a sequence of instructions to do a load or store from a constant
4097 offset off of a base register (breg) into/from a target register (treg),
4098 using AT if necessary. */
4100 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
4101 int treg
, int breg
, int dbl
)
4103 gas_assert (ep
->X_op
== O_constant
);
4105 /* Sign-extending 32-bit constants makes their handling easier. */
4107 normalize_constant_expr (ep
);
4109 /* Right now, this routine can only handle signed 32-bit constants. */
4110 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
4111 as_warn (_("operand overflow"));
4113 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
4115 /* Signed 16-bit offset will fit in the op. Easy! */
4116 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
4120 /* 32-bit offset, need multiple instructions and AT, like:
4121 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4122 addu $tempreg,$tempreg,$breg
4123 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4124 to handle the complete offset. */
4125 macro_build_lui (ep
, AT
);
4126 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
4127 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
4130 as_bad (_("Macro used $at after \".set noat\""));
4135 * Generates code to set the $at register to true (one)
4136 * if reg is less than the immediate expression.
4139 set_at (int reg
, int unsignedp
)
4141 if (imm_expr
.X_op
== O_constant
4142 && imm_expr
.X_add_number
>= -0x8000
4143 && imm_expr
.X_add_number
< 0x8000)
4144 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
4145 AT
, reg
, BFD_RELOC_LO16
);
4148 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4149 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
4153 /* Warn if an expression is not a constant. */
4156 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
4158 if (ex
->X_op
== O_big
)
4159 as_bad (_("unsupported large constant"));
4160 else if (ex
->X_op
!= O_constant
)
4161 as_bad (_("Instruction %s requires absolute expression"),
4164 if (HAVE_32BIT_GPRS
)
4165 normalize_constant_expr (ex
);
4168 /* Count the leading zeroes by performing a binary chop. This is a
4169 bulky bit of source, but performance is a LOT better for the
4170 majority of values than a simple loop to count the bits:
4171 for (lcnt = 0; (lcnt < 32); lcnt++)
4172 if ((v) & (1 << (31 - lcnt)))
4174 However it is not code size friendly, and the gain will drop a bit
4175 on certain cached systems.
4177 #define COUNT_TOP_ZEROES(v) \
4178 (((v) & ~0xffff) == 0 \
4179 ? ((v) & ~0xff) == 0 \
4180 ? ((v) & ~0xf) == 0 \
4181 ? ((v) & ~0x3) == 0 \
4182 ? ((v) & ~0x1) == 0 \
4187 : ((v) & ~0x7) == 0 \
4190 : ((v) & ~0x3f) == 0 \
4191 ? ((v) & ~0x1f) == 0 \
4194 : ((v) & ~0x7f) == 0 \
4197 : ((v) & ~0xfff) == 0 \
4198 ? ((v) & ~0x3ff) == 0 \
4199 ? ((v) & ~0x1ff) == 0 \
4202 : ((v) & ~0x7ff) == 0 \
4205 : ((v) & ~0x3fff) == 0 \
4206 ? ((v) & ~0x1fff) == 0 \
4209 : ((v) & ~0x7fff) == 0 \
4212 : ((v) & ~0xffffff) == 0 \
4213 ? ((v) & ~0xfffff) == 0 \
4214 ? ((v) & ~0x3ffff) == 0 \
4215 ? ((v) & ~0x1ffff) == 0 \
4218 : ((v) & ~0x7ffff) == 0 \
4221 : ((v) & ~0x3fffff) == 0 \
4222 ? ((v) & ~0x1fffff) == 0 \
4225 : ((v) & ~0x7fffff) == 0 \
4228 : ((v) & ~0xfffffff) == 0 \
4229 ? ((v) & ~0x3ffffff) == 0 \
4230 ? ((v) & ~0x1ffffff) == 0 \
4233 : ((v) & ~0x7ffffff) == 0 \
4236 : ((v) & ~0x3fffffff) == 0 \
4237 ? ((v) & ~0x1fffffff) == 0 \
4240 : ((v) & ~0x7fffffff) == 0 \
4245 * This routine generates the least number of instructions necessary to load
4246 * an absolute expression value into a register.
4249 load_register (int reg
, expressionS
*ep
, int dbl
)
4252 expressionS hi32
, lo32
;
4254 if (ep
->X_op
!= O_big
)
4256 gas_assert (ep
->X_op
== O_constant
);
4258 /* Sign-extending 32-bit constants makes their handling easier. */
4260 normalize_constant_expr (ep
);
4262 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4264 /* We can handle 16 bit signed values with an addiu to
4265 $zero. No need to ever use daddiu here, since $zero and
4266 the result are always correct in 32 bit mode. */
4267 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4270 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4272 /* We can handle 16 bit unsigned values with an ori to
4274 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4277 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4279 /* 32 bit values require an lui. */
4280 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4281 if ((ep
->X_add_number
& 0xffff) != 0)
4282 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4287 /* The value is larger than 32 bits. */
4289 if (!dbl
|| HAVE_32BIT_GPRS
)
4293 sprintf_vma (value
, ep
->X_add_number
);
4294 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4295 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4299 if (ep
->X_op
!= O_big
)
4302 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4303 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4304 hi32
.X_add_number
&= 0xffffffff;
4306 lo32
.X_add_number
&= 0xffffffff;
4310 gas_assert (ep
->X_add_number
> 2);
4311 if (ep
->X_add_number
== 3)
4312 generic_bignum
[3] = 0;
4313 else if (ep
->X_add_number
> 4)
4314 as_bad (_("Number larger than 64 bits"));
4315 lo32
.X_op
= O_constant
;
4316 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4317 hi32
.X_op
= O_constant
;
4318 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4321 if (hi32
.X_add_number
== 0)
4326 unsigned long hi
, lo
;
4328 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4330 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4332 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4335 if (lo32
.X_add_number
& 0x80000000)
4337 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4338 if (lo32
.X_add_number
& 0xffff)
4339 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4344 /* Check for 16bit shifted constant. We know that hi32 is
4345 non-zero, so start the mask on the first bit of the hi32
4350 unsigned long himask
, lomask
;
4354 himask
= 0xffff >> (32 - shift
);
4355 lomask
= (0xffff << shift
) & 0xffffffff;
4359 himask
= 0xffff << (shift
- 32);
4362 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4363 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4367 tmp
.X_op
= O_constant
;
4369 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4370 | (lo32
.X_add_number
>> shift
));
4372 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4373 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4374 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4375 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4380 while (shift
<= (64 - 16));
4382 /* Find the bit number of the lowest one bit, and store the
4383 shifted value in hi/lo. */
4384 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4385 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4389 while ((lo
& 1) == 0)
4394 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4400 while ((hi
& 1) == 0)
4409 /* Optimize if the shifted value is a (power of 2) - 1. */
4410 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4411 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4413 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4418 /* This instruction will set the register to be all
4420 tmp
.X_op
= O_constant
;
4421 tmp
.X_add_number
= (offsetT
) -1;
4422 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4426 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4427 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4429 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4430 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4435 /* Sign extend hi32 before calling load_register, because we can
4436 generally get better code when we load a sign extended value. */
4437 if ((hi32
.X_add_number
& 0x80000000) != 0)
4438 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4439 load_register (reg
, &hi32
, 0);
4442 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4446 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4454 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4456 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4457 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4463 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4467 mid16
.X_add_number
>>= 16;
4468 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4469 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4472 if ((lo32
.X_add_number
& 0xffff) != 0)
4473 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4477 load_delay_nop (void)
4479 if (!gpr_interlocks
)
4480 macro_build (NULL
, "nop", "");
4483 /* Load an address into a register. */
4486 load_address (int reg
, expressionS
*ep
, int *used_at
)
4488 if (ep
->X_op
!= O_constant
4489 && ep
->X_op
!= O_symbol
)
4491 as_bad (_("expression too complex"));
4492 ep
->X_op
= O_constant
;
4495 if (ep
->X_op
== O_constant
)
4497 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4501 if (mips_pic
== NO_PIC
)
4503 /* If this is a reference to a GP relative symbol, we want
4504 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4506 lui $reg,<sym> (BFD_RELOC_HI16_S)
4507 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4508 If we have an addend, we always use the latter form.
4510 With 64bit address space and a usable $at we want
4511 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4512 lui $at,<sym> (BFD_RELOC_HI16_S)
4513 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4514 daddiu $at,<sym> (BFD_RELOC_LO16)
4518 If $at is already in use, we use a path which is suboptimal
4519 on superscalar processors.
4520 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4521 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4523 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4525 daddiu $reg,<sym> (BFD_RELOC_LO16)
4527 For GP relative symbols in 64bit address space we can use
4528 the same sequence as in 32bit address space. */
4529 if (HAVE_64BIT_SYMBOLS
)
4531 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4532 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4534 relax_start (ep
->X_add_symbol
);
4535 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4536 mips_gp_register
, BFD_RELOC_GPREL16
);
4540 if (*used_at
== 0 && mips_opts
.at
)
4542 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4543 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4544 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4545 BFD_RELOC_MIPS_HIGHER
);
4546 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4547 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4548 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4553 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4554 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4555 BFD_RELOC_MIPS_HIGHER
);
4556 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4557 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4558 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4559 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4562 if (mips_relax
.sequence
)
4567 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4568 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4570 relax_start (ep
->X_add_symbol
);
4571 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4572 mips_gp_register
, BFD_RELOC_GPREL16
);
4575 macro_build_lui (ep
, reg
);
4576 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4577 reg
, reg
, BFD_RELOC_LO16
);
4578 if (mips_relax
.sequence
)
4582 else if (!mips_big_got
)
4586 /* If this is a reference to an external symbol, we want
4587 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4589 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4591 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4592 If there is a constant, it must be added in after.
4594 If we have NewABI, we want
4595 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4596 unless we're referencing a global symbol with a non-zero
4597 offset, in which case cst must be added separately. */
4600 if (ep
->X_add_number
)
4602 ex
.X_add_number
= ep
->X_add_number
;
4603 ep
->X_add_number
= 0;
4604 relax_start (ep
->X_add_symbol
);
4605 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4606 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4607 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4608 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4609 ex
.X_op
= O_constant
;
4610 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4611 reg
, reg
, BFD_RELOC_LO16
);
4612 ep
->X_add_number
= ex
.X_add_number
;
4615 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4616 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4617 if (mips_relax
.sequence
)
4622 ex
.X_add_number
= ep
->X_add_number
;
4623 ep
->X_add_number
= 0;
4624 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4625 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4627 relax_start (ep
->X_add_symbol
);
4629 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4633 if (ex
.X_add_number
!= 0)
4635 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4636 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4637 ex
.X_op
= O_constant
;
4638 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4639 reg
, reg
, BFD_RELOC_LO16
);
4643 else if (mips_big_got
)
4647 /* This is the large GOT case. If this is a reference to an
4648 external symbol, we want
4649 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4651 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4653 Otherwise, for a reference to a local symbol in old ABI, we want
4654 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4656 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4657 If there is a constant, it must be added in after.
4659 In the NewABI, for local symbols, with or without offsets, we want:
4660 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4661 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4665 ex
.X_add_number
= ep
->X_add_number
;
4666 ep
->X_add_number
= 0;
4667 relax_start (ep
->X_add_symbol
);
4668 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4669 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4670 reg
, reg
, mips_gp_register
);
4671 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4672 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4673 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4674 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4675 else if (ex
.X_add_number
)
4677 ex
.X_op
= O_constant
;
4678 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4682 ep
->X_add_number
= ex
.X_add_number
;
4684 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4685 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4686 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4687 BFD_RELOC_MIPS_GOT_OFST
);
4692 ex
.X_add_number
= ep
->X_add_number
;
4693 ep
->X_add_number
= 0;
4694 relax_start (ep
->X_add_symbol
);
4695 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4696 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4697 reg
, reg
, mips_gp_register
);
4698 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4699 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4701 if (reg_needs_delay (mips_gp_register
))
4703 /* We need a nop before loading from $gp. This special
4704 check is required because the lui which starts the main
4705 instruction stream does not refer to $gp, and so will not
4706 insert the nop which may be required. */
4707 macro_build (NULL
, "nop", "");
4709 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4710 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4712 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4716 if (ex
.X_add_number
!= 0)
4718 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4719 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4720 ex
.X_op
= O_constant
;
4721 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4729 if (!mips_opts
.at
&& *used_at
== 1)
4730 as_bad (_("Macro used $at after \".set noat\""));
4733 /* Move the contents of register SOURCE into register DEST. */
4736 move_register (int dest
, int source
)
4738 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4742 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4743 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4744 The two alternatives are:
4746 Global symbol Local sybmol
4747 ------------- ------------
4748 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4750 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4752 load_got_offset emits the first instruction and add_got_offset
4753 emits the second for a 16-bit offset or add_got_offset_hilo emits
4754 a sequence to add a 32-bit offset using a scratch register. */
4757 load_got_offset (int dest
, expressionS
*local
)
4762 global
.X_add_number
= 0;
4764 relax_start (local
->X_add_symbol
);
4765 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4766 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4768 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4769 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4774 add_got_offset (int dest
, expressionS
*local
)
4778 global
.X_op
= O_constant
;
4779 global
.X_op_symbol
= NULL
;
4780 global
.X_add_symbol
= NULL
;
4781 global
.X_add_number
= local
->X_add_number
;
4783 relax_start (local
->X_add_symbol
);
4784 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4785 dest
, dest
, BFD_RELOC_LO16
);
4787 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4792 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4795 int hold_mips_optimize
;
4797 global
.X_op
= O_constant
;
4798 global
.X_op_symbol
= NULL
;
4799 global
.X_add_symbol
= NULL
;
4800 global
.X_add_number
= local
->X_add_number
;
4802 relax_start (local
->X_add_symbol
);
4803 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4805 /* Set mips_optimize around the lui instruction to avoid
4806 inserting an unnecessary nop after the lw. */
4807 hold_mips_optimize
= mips_optimize
;
4809 macro_build_lui (&global
, tmp
);
4810 mips_optimize
= hold_mips_optimize
;
4811 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4814 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4819 * This routine implements the seemingly endless macro or synthesized
4820 * instructions and addressing modes in the mips assembly language. Many
4821 * of these macros are simple and are similar to each other. These could
4822 * probably be handled by some kind of table or grammar approach instead of
4823 * this verbose method. Others are not simple macros but are more like
4824 * optimizing code generation.
4825 * One interesting optimization is when several store macros appear
4826 * consecutively that would load AT with the upper half of the same address.
4827 * The ensuing load upper instructions are ommited. This implies some kind
4828 * of global optimization. We currently only optimize within a single macro.
4829 * For many of the load and store macros if the address is specified as a
4830 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4831 * first load register 'at' with zero and use it as the base register. The
4832 * mips assembler simply uses register $zero. Just one tiny optimization
4836 macro (struct mips_cl_insn
*ip
)
4838 unsigned int treg
, sreg
, dreg
, breg
;
4839 unsigned int tempreg
;
4854 bfd_reloc_code_real_type r
;
4855 int hold_mips_optimize
;
4857 gas_assert (! mips_opts
.mips16
);
4859 treg
= EXTRACT_OPERAND (RT
, *ip
);
4860 dreg
= EXTRACT_OPERAND (RD
, *ip
);
4861 sreg
= breg
= EXTRACT_OPERAND (RS
, *ip
);
4862 mask
= ip
->insn_mo
->mask
;
4864 expr1
.X_op
= O_constant
;
4865 expr1
.X_op_symbol
= NULL
;
4866 expr1
.X_add_symbol
= NULL
;
4867 expr1
.X_add_number
= 1;
4881 expr1
.X_add_number
= 8;
4882 macro_build (&expr1
, "bgez", "s,p", sreg
);
4884 macro_build (NULL
, "nop", "");
4886 move_register (dreg
, sreg
);
4887 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4910 if (imm_expr
.X_op
== O_constant
4911 && imm_expr
.X_add_number
>= -0x8000
4912 && imm_expr
.X_add_number
< 0x8000)
4914 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4918 load_register (AT
, &imm_expr
, dbl
);
4919 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4938 if (imm_expr
.X_op
== O_constant
4939 && imm_expr
.X_add_number
>= 0
4940 && imm_expr
.X_add_number
< 0x10000)
4942 if (mask
!= M_NOR_I
)
4943 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4946 macro_build (&imm_expr
, "ori", "t,r,i",
4947 treg
, sreg
, BFD_RELOC_LO16
);
4948 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4954 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4955 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4959 switch (imm_expr
.X_add_number
)
4962 macro_build (NULL
, "nop", "");
4965 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4968 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4969 (int) imm_expr
.X_add_number
);
4988 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4990 macro_build (&offset_expr
, s
, "s,t,p", sreg
, ZERO
);
4994 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4995 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
5003 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
5008 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
5012 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5013 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5019 /* Check for > max integer. */
5020 maxnum
= 0x7fffffff;
5021 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5028 if (imm_expr
.X_op
== O_constant
5029 && imm_expr
.X_add_number
>= maxnum
5030 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5033 /* Result is always false. */
5035 macro_build (NULL
, "nop", "");
5037 macro_build (&offset_expr
, "bnel", "s,t,p", ZERO
, ZERO
);
5040 if (imm_expr
.X_op
!= O_constant
)
5041 as_bad (_("Unsupported large constant"));
5042 ++imm_expr
.X_add_number
;
5046 if (mask
== M_BGEL_I
)
5048 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5050 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
5053 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5055 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5058 maxnum
= 0x7fffffff;
5059 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5066 maxnum
= - maxnum
- 1;
5067 if (imm_expr
.X_op
== O_constant
5068 && imm_expr
.X_add_number
<= maxnum
5069 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5072 /* result is always true */
5073 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
5074 macro_build (&offset_expr
, "b", "p");
5079 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5089 macro_build (&offset_expr
, likely
? "beql" : "beq",
5090 "s,t,p", ZERO
, treg
);
5094 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5095 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5103 && imm_expr
.X_op
== O_constant
5104 && imm_expr
.X_add_number
== -1))
5106 if (imm_expr
.X_op
!= O_constant
)
5107 as_bad (_("Unsupported large constant"));
5108 ++imm_expr
.X_add_number
;
5112 if (mask
== M_BGEUL_I
)
5114 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5116 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5118 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5119 "s,t,p", sreg
, ZERO
);
5124 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5132 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5137 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
5141 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5142 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5150 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5151 "s,t,p", sreg
, ZERO
);
5157 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5158 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5166 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5171 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
5175 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5176 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5182 maxnum
= 0x7fffffff;
5183 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5190 if (imm_expr
.X_op
== O_constant
5191 && imm_expr
.X_add_number
>= maxnum
5192 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5194 if (imm_expr
.X_op
!= O_constant
)
5195 as_bad (_("Unsupported large constant"));
5196 ++imm_expr
.X_add_number
;
5200 if (mask
== M_BLTL_I
)
5202 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5204 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5207 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5209 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5214 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5222 macro_build (&offset_expr
, likely
? "beql" : "beq",
5223 "s,t,p", sreg
, ZERO
);
5229 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5230 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5238 && imm_expr
.X_op
== O_constant
5239 && imm_expr
.X_add_number
== -1))
5241 if (imm_expr
.X_op
!= O_constant
)
5242 as_bad (_("Unsupported large constant"));
5243 ++imm_expr
.X_add_number
;
5247 if (mask
== M_BLTUL_I
)
5249 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5251 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5253 macro_build (&offset_expr
, likely
? "beql" : "beq",
5254 "s,t,p", sreg
, ZERO
);
5259 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5267 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5272 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5276 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5277 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5287 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5288 "s,t,p", ZERO
, treg
);
5292 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5293 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5298 /* Use unsigned arithmetic. */
5302 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5304 as_bad (_("Unsupported large constant"));
5309 pos
= imm_expr
.X_add_number
;
5310 size
= imm2_expr
.X_add_number
;
5315 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
5318 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
5320 as_bad (_("Improper extract size (%lu, position %lu)"),
5321 (unsigned long) size
, (unsigned long) pos
);
5325 if (size
<= 32 && pos
< 32)
5330 else if (size
<= 32)
5340 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5347 /* Use unsigned arithmetic. */
5351 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5353 as_bad (_("Unsupported large constant"));
5358 pos
= imm_expr
.X_add_number
;
5359 size
= imm2_expr
.X_add_number
;
5364 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
5367 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
5369 as_bad (_("Improper insert size (%lu, position %lu)"),
5370 (unsigned long) size
, (unsigned long) pos
);
5374 if (pos
< 32 && (pos
+ size
- 1) < 32)
5389 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5390 (int) (pos
+ size
- 1));
5406 as_warn (_("Divide by zero."));
5408 macro_build (NULL
, "teq", "s,t,q", ZERO
, ZERO
, 7);
5410 macro_build (NULL
, "break", "c", 7);
5417 macro_build (NULL
, "teq", "s,t,q", treg
, ZERO
, 7);
5418 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5422 expr1
.X_add_number
= 8;
5423 macro_build (&expr1
, "bne", "s,t,p", treg
, ZERO
);
5424 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5425 macro_build (NULL
, "break", "c", 7);
5427 expr1
.X_add_number
= -1;
5429 load_register (AT
, &expr1
, dbl
);
5430 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5431 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5434 expr1
.X_add_number
= 1;
5435 load_register (AT
, &expr1
, dbl
);
5436 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5440 expr1
.X_add_number
= 0x80000000;
5441 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5445 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5446 /* We want to close the noreorder block as soon as possible, so
5447 that later insns are available for delay slot filling. */
5452 expr1
.X_add_number
= 8;
5453 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5454 macro_build (NULL
, "nop", "");
5456 /* We want to close the noreorder block as soon as possible, so
5457 that later insns are available for delay slot filling. */
5460 macro_build (NULL
, "break", "c", 6);
5462 macro_build (NULL
, s
, "d", dreg
);
5501 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5503 as_warn (_("Divide by zero."));
5505 macro_build (NULL
, "teq", "s,t,q", ZERO
, ZERO
, 7);
5507 macro_build (NULL
, "break", "c", 7);
5510 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5512 if (strcmp (s2
, "mflo") == 0)
5513 move_register (dreg
, sreg
);
5515 move_register (dreg
, ZERO
);
5518 if (imm_expr
.X_op
== O_constant
5519 && imm_expr
.X_add_number
== -1
5520 && s
[strlen (s
) - 1] != 'u')
5522 if (strcmp (s2
, "mflo") == 0)
5524 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5527 move_register (dreg
, ZERO
);
5532 load_register (AT
, &imm_expr
, dbl
);
5533 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5534 macro_build (NULL
, s2
, "d", dreg
);
5556 macro_build (NULL
, "teq", "s,t,q", treg
, ZERO
, 7);
5557 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5558 /* We want to close the noreorder block as soon as possible, so
5559 that later insns are available for delay slot filling. */
5564 expr1
.X_add_number
= 8;
5565 macro_build (&expr1
, "bne", "s,t,p", treg
, ZERO
);
5566 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5568 /* We want to close the noreorder block as soon as possible, so
5569 that later insns are available for delay slot filling. */
5571 macro_build (NULL
, "break", "c", 7);
5573 macro_build (NULL
, s2
, "d", dreg
);
5585 /* Load the address of a symbol into a register. If breg is not
5586 zero, we then add a base register to it. */
5588 if (dbl
&& HAVE_32BIT_GPRS
)
5589 as_warn (_("dla used to load 32-bit register"));
5591 if (!dbl
&& HAVE_64BIT_OBJECTS
)
5592 as_warn (_("la used to load 64-bit address"));
5594 if (offset_expr
.X_op
== O_constant
5595 && offset_expr
.X_add_number
>= -0x8000
5596 && offset_expr
.X_add_number
< 0x8000)
5598 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5599 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5603 if (mips_opts
.at
&& (treg
== breg
))
5613 if (offset_expr
.X_op
!= O_symbol
5614 && offset_expr
.X_op
!= O_constant
)
5616 as_bad (_("Expression too complex"));
5617 offset_expr
.X_op
= O_constant
;
5620 if (offset_expr
.X_op
== O_constant
)
5621 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5622 else if (mips_pic
== NO_PIC
)
5624 /* If this is a reference to a GP relative symbol, we want
5625 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5627 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5628 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5629 If we have a constant, we need two instructions anyhow,
5630 so we may as well always use the latter form.
5632 With 64bit address space and a usable $at we want
5633 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5634 lui $at,<sym> (BFD_RELOC_HI16_S)
5635 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5636 daddiu $at,<sym> (BFD_RELOC_LO16)
5638 daddu $tempreg,$tempreg,$at
5640 If $at is already in use, we use a path which is suboptimal
5641 on superscalar processors.
5642 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5643 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5645 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5647 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5649 For GP relative symbols in 64bit address space we can use
5650 the same sequence as in 32bit address space. */
5651 if (HAVE_64BIT_SYMBOLS
)
5653 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5654 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5656 relax_start (offset_expr
.X_add_symbol
);
5657 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5658 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5662 if (used_at
== 0 && mips_opts
.at
)
5664 macro_build (&offset_expr
, "lui", "t,u",
5665 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5666 macro_build (&offset_expr
, "lui", "t,u",
5667 AT
, BFD_RELOC_HI16_S
);
5668 macro_build (&offset_expr
, "daddiu", "t,r,j",
5669 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5670 macro_build (&offset_expr
, "daddiu", "t,r,j",
5671 AT
, AT
, BFD_RELOC_LO16
);
5672 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5673 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5678 macro_build (&offset_expr
, "lui", "t,u",
5679 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5680 macro_build (&offset_expr
, "daddiu", "t,r,j",
5681 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5682 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5683 macro_build (&offset_expr
, "daddiu", "t,r,j",
5684 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5685 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5686 macro_build (&offset_expr
, "daddiu", "t,r,j",
5687 tempreg
, tempreg
, BFD_RELOC_LO16
);
5690 if (mips_relax
.sequence
)
5695 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5696 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5698 relax_start (offset_expr
.X_add_symbol
);
5699 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5700 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5703 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5704 as_bad (_("Offset too large"));
5705 macro_build_lui (&offset_expr
, tempreg
);
5706 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5707 tempreg
, tempreg
, BFD_RELOC_LO16
);
5708 if (mips_relax
.sequence
)
5712 else if (!mips_big_got
&& !HAVE_NEWABI
)
5714 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5716 /* If this is a reference to an external symbol, and there
5717 is no constant, we want
5718 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5719 or for lca or if tempreg is PIC_CALL_REG
5720 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5721 For a local symbol, we want
5722 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5724 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5726 If we have a small constant, and this is a reference to
5727 an external symbol, we want
5728 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5730 addiu $tempreg,$tempreg,<constant>
5731 For a local symbol, we want the same instruction
5732 sequence, but we output a BFD_RELOC_LO16 reloc on the
5735 If we have a large constant, and this is a reference to
5736 an external symbol, we want
5737 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5738 lui $at,<hiconstant>
5739 addiu $at,$at,<loconstant>
5740 addu $tempreg,$tempreg,$at
5741 For a local symbol, we want the same instruction
5742 sequence, but we output a BFD_RELOC_LO16 reloc on the
5746 if (offset_expr
.X_add_number
== 0)
5748 if (mips_pic
== SVR4_PIC
5750 && (call
|| tempreg
== PIC_CALL_REG
))
5751 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5753 relax_start (offset_expr
.X_add_symbol
);
5754 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5755 lw_reloc_type
, mips_gp_register
);
5758 /* We're going to put in an addu instruction using
5759 tempreg, so we may as well insert the nop right
5764 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5765 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5767 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5768 tempreg
, tempreg
, BFD_RELOC_LO16
);
5770 /* FIXME: If breg == 0, and the next instruction uses
5771 $tempreg, then if this variant case is used an extra
5772 nop will be generated. */
5774 else if (offset_expr
.X_add_number
>= -0x8000
5775 && offset_expr
.X_add_number
< 0x8000)
5777 load_got_offset (tempreg
, &offset_expr
);
5779 add_got_offset (tempreg
, &offset_expr
);
5783 expr1
.X_add_number
= offset_expr
.X_add_number
;
5784 offset_expr
.X_add_number
=
5785 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5786 load_got_offset (tempreg
, &offset_expr
);
5787 offset_expr
.X_add_number
= expr1
.X_add_number
;
5788 /* If we are going to add in a base register, and the
5789 target register and the base register are the same,
5790 then we are using AT as a temporary register. Since
5791 we want to load the constant into AT, we add our
5792 current AT (from the global offset table) and the
5793 register into the register now, and pretend we were
5794 not using a base register. */
5798 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5803 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5807 else if (!mips_big_got
&& HAVE_NEWABI
)
5809 int add_breg_early
= 0;
5811 /* If this is a reference to an external, and there is no
5812 constant, or local symbol (*), with or without a
5814 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5815 or for lca or if tempreg is PIC_CALL_REG
5816 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5818 If we have a small constant, and this is a reference to
5819 an external symbol, we want
5820 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5821 addiu $tempreg,$tempreg,<constant>
5823 If we have a large constant, and this is a reference to
5824 an external symbol, we want
5825 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5826 lui $at,<hiconstant>
5827 addiu $at,$at,<loconstant>
5828 addu $tempreg,$tempreg,$at
5830 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5831 local symbols, even though it introduces an additional
5834 if (offset_expr
.X_add_number
)
5836 expr1
.X_add_number
= offset_expr
.X_add_number
;
5837 offset_expr
.X_add_number
= 0;
5839 relax_start (offset_expr
.X_add_symbol
);
5840 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5841 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5843 if (expr1
.X_add_number
>= -0x8000
5844 && expr1
.X_add_number
< 0x8000)
5846 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5847 tempreg
, tempreg
, BFD_RELOC_LO16
);
5849 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5851 /* If we are going to add in a base register, and the
5852 target register and the base register are the same,
5853 then we are using AT as a temporary register. Since
5854 we want to load the constant into AT, we add our
5855 current AT (from the global offset table) and the
5856 register into the register now, and pretend we were
5857 not using a base register. */
5862 gas_assert (tempreg
== AT
);
5863 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5869 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5870 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5876 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5879 offset_expr
.X_add_number
= expr1
.X_add_number
;
5881 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5882 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5885 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5886 treg
, tempreg
, breg
);
5892 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5894 relax_start (offset_expr
.X_add_symbol
);
5895 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5896 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5898 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5899 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5904 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5905 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5908 else if (mips_big_got
&& !HAVE_NEWABI
)
5911 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5912 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5913 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5915 /* This is the large GOT case. If this is a reference to an
5916 external symbol, and there is no constant, we want
5917 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5918 addu $tempreg,$tempreg,$gp
5919 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5920 or for lca or if tempreg is PIC_CALL_REG
5921 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5922 addu $tempreg,$tempreg,$gp
5923 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5924 For a local symbol, we want
5925 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5927 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5929 If we have a small constant, and this is a reference to
5930 an external symbol, we want
5931 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5932 addu $tempreg,$tempreg,$gp
5933 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5935 addiu $tempreg,$tempreg,<constant>
5936 For a local symbol, we want
5937 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5939 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5941 If we have a large constant, and this is a reference to
5942 an external symbol, we want
5943 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5944 addu $tempreg,$tempreg,$gp
5945 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5946 lui $at,<hiconstant>
5947 addiu $at,$at,<loconstant>
5948 addu $tempreg,$tempreg,$at
5949 For a local symbol, we want
5950 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5951 lui $at,<hiconstant>
5952 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5953 addu $tempreg,$tempreg,$at
5956 expr1
.X_add_number
= offset_expr
.X_add_number
;
5957 offset_expr
.X_add_number
= 0;
5958 relax_start (offset_expr
.X_add_symbol
);
5959 gpdelay
= reg_needs_delay (mips_gp_register
);
5960 if (expr1
.X_add_number
== 0 && breg
== 0
5961 && (call
|| tempreg
== PIC_CALL_REG
))
5963 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5964 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5966 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5967 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5968 tempreg
, tempreg
, mips_gp_register
);
5969 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5970 tempreg
, lw_reloc_type
, tempreg
);
5971 if (expr1
.X_add_number
== 0)
5975 /* We're going to put in an addu instruction using
5976 tempreg, so we may as well insert the nop right
5981 else if (expr1
.X_add_number
>= -0x8000
5982 && expr1
.X_add_number
< 0x8000)
5985 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5986 tempreg
, tempreg
, BFD_RELOC_LO16
);
5990 /* If we are going to add in a base register, and the
5991 target register and the base register are the same,
5992 then we are using AT as a temporary register. Since
5993 we want to load the constant into AT, we add our
5994 current AT (from the global offset table) and the
5995 register into the register now, and pretend we were
5996 not using a base register. */
6001 gas_assert (tempreg
== AT
);
6003 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6008 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6009 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6013 offset_expr
.X_add_number
=
6014 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
6019 /* This is needed because this instruction uses $gp, but
6020 the first instruction on the main stream does not. */
6021 macro_build (NULL
, "nop", "");
6024 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6025 local_reloc_type
, mips_gp_register
);
6026 if (expr1
.X_add_number
>= -0x8000
6027 && expr1
.X_add_number
< 0x8000)
6030 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6031 tempreg
, tempreg
, BFD_RELOC_LO16
);
6032 /* FIXME: If add_number is 0, and there was no base
6033 register, the external symbol case ended with a load,
6034 so if the symbol turns out to not be external, and
6035 the next instruction uses tempreg, an unnecessary nop
6036 will be inserted. */
6042 /* We must add in the base register now, as in the
6043 external symbol case. */
6044 gas_assert (tempreg
== AT
);
6046 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6049 /* We set breg to 0 because we have arranged to add
6050 it in in both cases. */
6054 macro_build_lui (&expr1
, AT
);
6055 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6056 AT
, AT
, BFD_RELOC_LO16
);
6057 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6058 tempreg
, tempreg
, AT
);
6063 else if (mips_big_got
&& HAVE_NEWABI
)
6065 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
6066 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
6067 int add_breg_early
= 0;
6069 /* This is the large GOT case. If this is a reference to an
6070 external symbol, and there is no constant, we want
6071 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6072 add $tempreg,$tempreg,$gp
6073 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6074 or for lca or if tempreg is PIC_CALL_REG
6075 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6076 add $tempreg,$tempreg,$gp
6077 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6079 If we have a small constant, and this is a reference to
6080 an external symbol, we want
6081 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6082 add $tempreg,$tempreg,$gp
6083 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6084 addi $tempreg,$tempreg,<constant>
6086 If we have a large constant, and this is a reference to
6087 an external symbol, we want
6088 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6089 addu $tempreg,$tempreg,$gp
6090 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6091 lui $at,<hiconstant>
6092 addi $at,$at,<loconstant>
6093 add $tempreg,$tempreg,$at
6095 If we have NewABI, and we know it's a local symbol, we want
6096 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6097 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6098 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6100 relax_start (offset_expr
.X_add_symbol
);
6102 expr1
.X_add_number
= offset_expr
.X_add_number
;
6103 offset_expr
.X_add_number
= 0;
6105 if (expr1
.X_add_number
== 0 && breg
== 0
6106 && (call
|| tempreg
== PIC_CALL_REG
))
6108 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
6109 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
6111 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
6112 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6113 tempreg
, tempreg
, mips_gp_register
);
6114 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6115 tempreg
, lw_reloc_type
, tempreg
);
6117 if (expr1
.X_add_number
== 0)
6119 else if (expr1
.X_add_number
>= -0x8000
6120 && expr1
.X_add_number
< 0x8000)
6122 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
6123 tempreg
, tempreg
, BFD_RELOC_LO16
);
6125 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
6127 /* If we are going to add in a base register, and the
6128 target register and the base register are the same,
6129 then we are using AT as a temporary register. Since
6130 we want to load the constant into AT, we add our
6131 current AT (from the global offset table) and the
6132 register into the register now, and pretend we were
6133 not using a base register. */
6138 gas_assert (tempreg
== AT
);
6139 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6145 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6146 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6151 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6154 offset_expr
.X_add_number
= expr1
.X_add_number
;
6155 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6156 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6157 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6158 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
6161 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6162 treg
, tempreg
, breg
);
6172 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
6177 unsigned long temp
= (treg
<< 16) | (0x01);
6178 macro_build (NULL
, "c2", "C", temp
);
6184 unsigned long temp
= (0x02);
6185 macro_build (NULL
, "c2", "C", temp
);
6191 unsigned long temp
= (treg
<< 16) | (0x02);
6192 macro_build (NULL
, "c2", "C", temp
);
6197 macro_build (NULL
, "c2", "C", 3);
6202 unsigned long temp
= (treg
<< 16) | 0x03;
6203 macro_build (NULL
, "c2", "C", temp
);
6208 /* The j instruction may not be used in PIC code, since it
6209 requires an absolute address. We convert it to a b
6211 if (mips_pic
== NO_PIC
)
6212 macro_build (&offset_expr
, "j", "a");
6214 macro_build (&offset_expr
, "b", "p");
6217 /* The jal instructions must be handled as macros because when
6218 generating PIC code they expand to multi-instruction
6219 sequences. Normally they are simple instructions. */
6224 if (mips_pic
== NO_PIC
)
6225 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6228 if (sreg
!= PIC_CALL_REG
)
6229 as_warn (_("MIPS PIC call to register other than $25"));
6231 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6232 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
6234 if (mips_cprestore_offset
< 0)
6235 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6238 if (!mips_frame_reg_valid
)
6240 as_warn (_("No .frame pseudo-op used in PIC code"));
6241 /* Quiet this warning. */
6242 mips_frame_reg_valid
= 1;
6244 if (!mips_cprestore_valid
)
6246 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6247 /* Quiet this warning. */
6248 mips_cprestore_valid
= 1;
6250 if (mips_opts
.noreorder
)
6251 macro_build (NULL
, "nop", "");
6252 expr1
.X_add_number
= mips_cprestore_offset
;
6253 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6256 HAVE_64BIT_ADDRESSES
);
6264 if (mips_pic
== NO_PIC
)
6265 macro_build (&offset_expr
, "jal", "a");
6266 else if (mips_pic
== SVR4_PIC
)
6268 /* If this is a reference to an external symbol, and we are
6269 using a small GOT, we want
6270 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6274 lw $gp,cprestore($sp)
6275 The cprestore value is set using the .cprestore
6276 pseudo-op. If we are using a big GOT, we want
6277 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6279 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6283 lw $gp,cprestore($sp)
6284 If the symbol is not external, we want
6285 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6287 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6290 lw $gp,cprestore($sp)
6292 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6293 sequences above, minus nops, unless the symbol is local,
6294 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6300 relax_start (offset_expr
.X_add_symbol
);
6301 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6302 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6305 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6306 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6312 relax_start (offset_expr
.X_add_symbol
);
6313 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6314 BFD_RELOC_MIPS_CALL_HI16
);
6315 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6316 PIC_CALL_REG
, mips_gp_register
);
6317 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6318 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6321 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6322 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6324 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6325 PIC_CALL_REG
, PIC_CALL_REG
,
6326 BFD_RELOC_MIPS_GOT_OFST
);
6330 macro_build_jalr (&offset_expr
);
6334 relax_start (offset_expr
.X_add_symbol
);
6337 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6338 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6347 gpdelay
= reg_needs_delay (mips_gp_register
);
6348 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6349 BFD_RELOC_MIPS_CALL_HI16
);
6350 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6351 PIC_CALL_REG
, mips_gp_register
);
6352 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6353 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6358 macro_build (NULL
, "nop", "");
6360 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6361 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6364 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6365 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6367 macro_build_jalr (&offset_expr
);
6369 if (mips_cprestore_offset
< 0)
6370 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6373 if (!mips_frame_reg_valid
)
6375 as_warn (_("No .frame pseudo-op used in PIC code"));
6376 /* Quiet this warning. */
6377 mips_frame_reg_valid
= 1;
6379 if (!mips_cprestore_valid
)
6381 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6382 /* Quiet this warning. */
6383 mips_cprestore_valid
= 1;
6385 if (mips_opts
.noreorder
)
6386 macro_build (NULL
, "nop", "");
6387 expr1
.X_add_number
= mips_cprestore_offset
;
6388 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6391 HAVE_64BIT_ADDRESSES
);
6395 else if (mips_pic
== VXWORKS_PIC
)
6396 as_bad (_("Non-PIC jump used in PIC library"));
6419 /* Itbl support may require additional care here. */
6424 /* Itbl support may require additional care here. */
6429 /* Itbl support may require additional care here. */
6434 /* Itbl support may require additional care here. */
6447 /* Itbl support may require additional care here. */
6452 /* Itbl support may require additional care here. */
6457 /* Itbl support may require additional care here. */
6477 if (breg
== treg
|| coproc
|| lr
)
6498 /* Itbl support may require additional care here. */
6503 /* Itbl support may require additional care here. */
6508 /* Itbl support may require additional care here. */
6513 /* Itbl support may require additional care here. */
6537 /* Itbl support may require additional care here. */
6541 /* Itbl support may require additional care here. */
6546 /* Itbl support may require additional care here. */
6559 && NO_ISA_COP (mips_opts
.arch
)
6560 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
6562 as_bad (_("Opcode not supported on this processor: %s"),
6563 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
6567 /* Itbl support may require additional care here. */
6568 if (mask
== M_LWC1_AB
6569 || mask
== M_SWC1_AB
6570 || mask
== M_LDC1_AB
6571 || mask
== M_SDC1_AB
6575 else if (mask
== M_CACHE_AB
|| mask
== M_PREF_AB
)
6582 if (offset_expr
.X_op
!= O_constant
6583 && offset_expr
.X_op
!= O_symbol
)
6585 as_bad (_("Expression too complex"));
6586 offset_expr
.X_op
= O_constant
;
6589 if (HAVE_32BIT_ADDRESSES
6590 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6594 sprintf_vma (value
, offset_expr
.X_add_number
);
6595 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6598 /* A constant expression in PIC code can be handled just as it
6599 is in non PIC code. */
6600 if (offset_expr
.X_op
== O_constant
)
6602 expr1
.X_add_number
= offset_expr
.X_add_number
;
6603 normalize_address_expr (&expr1
);
6604 if (!IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
6606 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
6607 & ~(bfd_vma
) 0xffff);
6608 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6610 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6611 tempreg
, tempreg
, breg
);
6614 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
6616 else if (mips_pic
== NO_PIC
)
6618 /* If this is a reference to a GP relative symbol, and there
6619 is no base register, we want
6620 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6621 Otherwise, if there is no base register, we want
6622 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6623 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6624 If we have a constant, we need two instructions anyhow,
6625 so we always use the latter form.
6627 If we have a base register, and this is a reference to a
6628 GP relative symbol, we want
6629 addu $tempreg,$breg,$gp
6630 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6632 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6633 addu $tempreg,$tempreg,$breg
6634 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6635 With a constant we always use the latter case.
6637 With 64bit address space and no base register and $at usable,
6639 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6640 lui $at,<sym> (BFD_RELOC_HI16_S)
6641 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6644 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6645 If we have a base register, we want
6646 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6647 lui $at,<sym> (BFD_RELOC_HI16_S)
6648 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6652 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6654 Without $at we can't generate the optimal path for superscalar
6655 processors here since this would require two temporary registers.
6656 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6657 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6659 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6661 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6662 If we have a base register, we want
6663 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6664 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6666 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6668 daddu $tempreg,$tempreg,$breg
6669 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6671 For GP relative symbols in 64bit address space we can use
6672 the same sequence as in 32bit address space. */
6673 if (HAVE_64BIT_SYMBOLS
)
6675 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6676 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6678 relax_start (offset_expr
.X_add_symbol
);
6681 macro_build (&offset_expr
, s
, fmt
, treg
,
6682 BFD_RELOC_GPREL16
, mips_gp_register
);
6686 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6687 tempreg
, breg
, mips_gp_register
);
6688 macro_build (&offset_expr
, s
, fmt
, treg
,
6689 BFD_RELOC_GPREL16
, tempreg
);
6694 if (used_at
== 0 && mips_opts
.at
)
6696 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6697 BFD_RELOC_MIPS_HIGHEST
);
6698 macro_build (&offset_expr
, "lui", "t,u", AT
,
6700 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6701 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6703 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6704 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6705 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6706 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6712 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6713 BFD_RELOC_MIPS_HIGHEST
);
6714 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6715 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6716 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6717 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6718 tempreg
, BFD_RELOC_HI16_S
);
6719 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6721 macro_build (NULL
, "daddu", "d,v,t",
6722 tempreg
, tempreg
, breg
);
6723 macro_build (&offset_expr
, s
, fmt
, treg
,
6724 BFD_RELOC_LO16
, tempreg
);
6727 if (mips_relax
.sequence
)
6734 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6735 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6737 relax_start (offset_expr
.X_add_symbol
);
6738 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6742 macro_build_lui (&offset_expr
, tempreg
);
6743 macro_build (&offset_expr
, s
, fmt
, treg
,
6744 BFD_RELOC_LO16
, tempreg
);
6745 if (mips_relax
.sequence
)
6750 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6751 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6753 relax_start (offset_expr
.X_add_symbol
);
6754 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6755 tempreg
, breg
, mips_gp_register
);
6756 macro_build (&offset_expr
, s
, fmt
, treg
,
6757 BFD_RELOC_GPREL16
, tempreg
);
6760 macro_build_lui (&offset_expr
, tempreg
);
6761 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6762 tempreg
, tempreg
, breg
);
6763 macro_build (&offset_expr
, s
, fmt
, treg
,
6764 BFD_RELOC_LO16
, tempreg
);
6765 if (mips_relax
.sequence
)
6769 else if (!mips_big_got
)
6771 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6773 /* If this is a reference to an external symbol, we want
6774 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6776 <op> $treg,0($tempreg)
6778 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6780 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6781 <op> $treg,0($tempreg)
6784 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6785 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6787 If there is a base register, we add it to $tempreg before
6788 the <op>. If there is a constant, we stick it in the
6789 <op> instruction. We don't handle constants larger than
6790 16 bits, because we have no way to load the upper 16 bits
6791 (actually, we could handle them for the subset of cases
6792 in which we are not using $at). */
6793 gas_assert (offset_expr
.X_op
== O_symbol
);
6796 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6797 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6799 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6800 tempreg
, tempreg
, breg
);
6801 macro_build (&offset_expr
, s
, fmt
, treg
,
6802 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6805 expr1
.X_add_number
= offset_expr
.X_add_number
;
6806 offset_expr
.X_add_number
= 0;
6807 if (expr1
.X_add_number
< -0x8000
6808 || expr1
.X_add_number
>= 0x8000)
6809 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6810 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6811 lw_reloc_type
, mips_gp_register
);
6813 relax_start (offset_expr
.X_add_symbol
);
6815 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6816 tempreg
, BFD_RELOC_LO16
);
6819 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6820 tempreg
, tempreg
, breg
);
6821 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6823 else if (mips_big_got
&& !HAVE_NEWABI
)
6827 /* If this is a reference to an external symbol, we want
6828 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6829 addu $tempreg,$tempreg,$gp
6830 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6831 <op> $treg,0($tempreg)
6833 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6835 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6836 <op> $treg,0($tempreg)
6837 If there is a base register, we add it to $tempreg before
6838 the <op>. If there is a constant, we stick it in the
6839 <op> instruction. We don't handle constants larger than
6840 16 bits, because we have no way to load the upper 16 bits
6841 (actually, we could handle them for the subset of cases
6842 in which we are not using $at). */
6843 gas_assert (offset_expr
.X_op
== O_symbol
);
6844 expr1
.X_add_number
= offset_expr
.X_add_number
;
6845 offset_expr
.X_add_number
= 0;
6846 if (expr1
.X_add_number
< -0x8000
6847 || expr1
.X_add_number
>= 0x8000)
6848 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6849 gpdelay
= reg_needs_delay (mips_gp_register
);
6850 relax_start (offset_expr
.X_add_symbol
);
6851 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6852 BFD_RELOC_MIPS_GOT_HI16
);
6853 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6855 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6856 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6859 macro_build (NULL
, "nop", "");
6860 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6861 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6863 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6864 tempreg
, BFD_RELOC_LO16
);
6868 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6869 tempreg
, tempreg
, breg
);
6870 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6872 else if (mips_big_got
&& HAVE_NEWABI
)
6874 /* If this is a reference to an external symbol, we want
6875 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6876 add $tempreg,$tempreg,$gp
6877 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6878 <op> $treg,<ofst>($tempreg)
6879 Otherwise, for local symbols, we want:
6880 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6881 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6882 gas_assert (offset_expr
.X_op
== O_symbol
);
6883 expr1
.X_add_number
= offset_expr
.X_add_number
;
6884 offset_expr
.X_add_number
= 0;
6885 if (expr1
.X_add_number
< -0x8000
6886 || expr1
.X_add_number
>= 0x8000)
6887 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6888 relax_start (offset_expr
.X_add_symbol
);
6889 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6890 BFD_RELOC_MIPS_GOT_HI16
);
6891 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6893 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6894 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6896 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6897 tempreg
, tempreg
, breg
);
6898 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6901 offset_expr
.X_add_number
= expr1
.X_add_number
;
6902 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6903 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6905 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6906 tempreg
, tempreg
, breg
);
6907 macro_build (&offset_expr
, s
, fmt
, treg
,
6908 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6918 load_register (treg
, &imm_expr
, 0);
6922 load_register (treg
, &imm_expr
, 1);
6926 if (imm_expr
.X_op
== O_constant
)
6929 load_register (AT
, &imm_expr
, 0);
6930 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6935 gas_assert (offset_expr
.X_op
== O_symbol
6936 && strcmp (segment_name (S_GET_SEGMENT
6937 (offset_expr
.X_add_symbol
)),
6939 && offset_expr
.X_add_number
== 0);
6940 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6941 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6946 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6947 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6948 order 32 bits of the value and the low order 32 bits are either
6949 zero or in OFFSET_EXPR. */
6950 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6952 if (HAVE_64BIT_GPRS
)
6953 load_register (treg
, &imm_expr
, 1);
6958 if (target_big_endian
)
6970 load_register (hreg
, &imm_expr
, 0);
6973 if (offset_expr
.X_op
== O_absent
)
6974 move_register (lreg
, 0);
6977 gas_assert (offset_expr
.X_op
== O_constant
);
6978 load_register (lreg
, &offset_expr
, 0);
6985 /* We know that sym is in the .rdata section. First we get the
6986 upper 16 bits of the address. */
6987 if (mips_pic
== NO_PIC
)
6989 macro_build_lui (&offset_expr
, AT
);
6994 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6995 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6999 /* Now we load the register(s). */
7000 if (HAVE_64BIT_GPRS
)
7003 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7008 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7011 /* FIXME: How in the world do we deal with the possible
7013 offset_expr
.X_add_number
+= 4;
7014 macro_build (&offset_expr
, "lw", "t,o(b)",
7015 treg
+ 1, BFD_RELOC_LO16
, AT
);
7021 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7022 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7023 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7024 the value and the low order 32 bits are either zero or in
7026 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
7029 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
7030 if (HAVE_64BIT_FPRS
)
7032 gas_assert (HAVE_64BIT_GPRS
);
7033 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
7037 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
7038 if (offset_expr
.X_op
== O_absent
)
7039 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
7042 gas_assert (offset_expr
.X_op
== O_constant
);
7043 load_register (AT
, &offset_expr
, 0);
7044 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
7050 gas_assert (offset_expr
.X_op
== O_symbol
7051 && offset_expr
.X_add_number
== 0);
7052 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
7053 if (strcmp (s
, ".lit8") == 0)
7055 if (mips_opts
.isa
!= ISA_MIPS1
)
7057 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
7058 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
7061 breg
= mips_gp_register
;
7062 r
= BFD_RELOC_MIPS_LITERAL
;
7067 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
7069 if (mips_pic
!= NO_PIC
)
7070 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7071 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7074 /* FIXME: This won't work for a 64 bit address. */
7075 macro_build_lui (&offset_expr
, AT
);
7078 if (mips_opts
.isa
!= ISA_MIPS1
)
7080 macro_build (&offset_expr
, "ldc1", "T,o(b)",
7081 treg
, BFD_RELOC_LO16
, AT
);
7090 /* Even on a big endian machine $fn comes before $fn+1. We have
7091 to adjust when loading from memory. */
7094 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7095 macro_build (&offset_expr
, "lwc1", "T,o(b)",
7096 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
7097 /* FIXME: A possible overflow which I don't know how to deal
7099 offset_expr
.X_add_number
+= 4;
7100 macro_build (&offset_expr
, "lwc1", "T,o(b)",
7101 target_big_endian
? treg
: treg
+ 1, r
, breg
);
7105 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7106 /* Even on a big endian machine $fn comes before $fn+1. We have
7107 to adjust when storing to memory. */
7108 macro_build (&offset_expr
, "swc1", "T,o(b)",
7109 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7110 offset_expr
.X_add_number
+= 4;
7111 macro_build (&offset_expr
, "swc1", "T,o(b)",
7112 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7117 * The MIPS assembler seems to check for X_add_number not
7118 * being double aligned and generating:
7121 * addiu at,at,%lo(foo+1)
7124 * But, the resulting address is the same after relocation so why
7125 * generate the extra instruction?
7127 /* Itbl support may require additional care here. */
7129 if (mips_opts
.isa
!= ISA_MIPS1
)
7140 if (mips_opts
.isa
!= ISA_MIPS1
)
7148 /* Itbl support may require additional care here. */
7153 if (HAVE_64BIT_GPRS
)
7164 if (HAVE_64BIT_GPRS
)
7174 if (offset_expr
.X_op
!= O_symbol
7175 && offset_expr
.X_op
!= O_constant
)
7177 as_bad (_("Expression too complex"));
7178 offset_expr
.X_op
= O_constant
;
7181 if (HAVE_32BIT_ADDRESSES
7182 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7186 sprintf_vma (value
, offset_expr
.X_add_number
);
7187 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7190 /* Even on a big endian machine $fn comes before $fn+1. We have
7191 to adjust when loading from memory. We set coproc if we must
7192 load $fn+1 first. */
7193 /* Itbl support may require additional care here. */
7194 if (!target_big_endian
)
7197 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
7199 /* If this is a reference to a GP relative symbol, we want
7200 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7201 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7202 If we have a base register, we use this
7204 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7205 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7206 If this is not a GP relative symbol, we want
7207 lui $at,<sym> (BFD_RELOC_HI16_S)
7208 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7209 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7210 If there is a base register, we add it to $at after the
7211 lui instruction. If there is a constant, we always use
7213 if (offset_expr
.X_op
== O_symbol
7214 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7215 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7217 relax_start (offset_expr
.X_add_symbol
);
7220 tempreg
= mips_gp_register
;
7224 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7225 AT
, breg
, mips_gp_register
);
7230 /* Itbl support may require additional care here. */
7231 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7232 BFD_RELOC_GPREL16
, tempreg
);
7233 offset_expr
.X_add_number
+= 4;
7235 /* Set mips_optimize to 2 to avoid inserting an
7237 hold_mips_optimize
= mips_optimize
;
7239 /* Itbl support may require additional care here. */
7240 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7241 BFD_RELOC_GPREL16
, tempreg
);
7242 mips_optimize
= hold_mips_optimize
;
7246 offset_expr
.X_add_number
-= 4;
7249 macro_build_lui (&offset_expr
, AT
);
7251 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7252 /* Itbl support may require additional care here. */
7253 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7254 BFD_RELOC_LO16
, AT
);
7255 /* FIXME: How do we handle overflow here? */
7256 offset_expr
.X_add_number
+= 4;
7257 /* Itbl support may require additional care here. */
7258 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7259 BFD_RELOC_LO16
, AT
);
7260 if (mips_relax
.sequence
)
7263 else if (!mips_big_got
)
7265 /* If this is a reference to an external symbol, we want
7266 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7271 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7273 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7274 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7275 If there is a base register we add it to $at before the
7276 lwc1 instructions. If there is a constant we include it
7277 in the lwc1 instructions. */
7279 expr1
.X_add_number
= offset_expr
.X_add_number
;
7280 if (expr1
.X_add_number
< -0x8000
7281 || expr1
.X_add_number
>= 0x8000 - 4)
7282 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7283 load_got_offset (AT
, &offset_expr
);
7286 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7288 /* Set mips_optimize to 2 to avoid inserting an undesired
7290 hold_mips_optimize
= mips_optimize
;
7293 /* Itbl support may require additional care here. */
7294 relax_start (offset_expr
.X_add_symbol
);
7295 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7296 BFD_RELOC_LO16
, AT
);
7297 expr1
.X_add_number
+= 4;
7298 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7299 BFD_RELOC_LO16
, AT
);
7301 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7302 BFD_RELOC_LO16
, AT
);
7303 offset_expr
.X_add_number
+= 4;
7304 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7305 BFD_RELOC_LO16
, AT
);
7308 mips_optimize
= hold_mips_optimize
;
7310 else if (mips_big_got
)
7314 /* If this is a reference to an external symbol, we want
7315 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7317 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7322 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7324 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7325 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7326 If there is a base register we add it to $at before the
7327 lwc1 instructions. If there is a constant we include it
7328 in the lwc1 instructions. */
7330 expr1
.X_add_number
= offset_expr
.X_add_number
;
7331 offset_expr
.X_add_number
= 0;
7332 if (expr1
.X_add_number
< -0x8000
7333 || expr1
.X_add_number
>= 0x8000 - 4)
7334 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7335 gpdelay
= reg_needs_delay (mips_gp_register
);
7336 relax_start (offset_expr
.X_add_symbol
);
7337 macro_build (&offset_expr
, "lui", "t,u",
7338 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7339 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7340 AT
, AT
, mips_gp_register
);
7341 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7342 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7345 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7346 /* Itbl support may require additional care here. */
7347 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7348 BFD_RELOC_LO16
, AT
);
7349 expr1
.X_add_number
+= 4;
7351 /* Set mips_optimize to 2 to avoid inserting an undesired
7353 hold_mips_optimize
= mips_optimize
;
7355 /* Itbl support may require additional care here. */
7356 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7357 BFD_RELOC_LO16
, AT
);
7358 mips_optimize
= hold_mips_optimize
;
7359 expr1
.X_add_number
-= 4;
7362 offset_expr
.X_add_number
= expr1
.X_add_number
;
7364 macro_build (NULL
, "nop", "");
7365 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7366 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7369 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7370 /* Itbl support may require additional care here. */
7371 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7372 BFD_RELOC_LO16
, AT
);
7373 offset_expr
.X_add_number
+= 4;
7375 /* Set mips_optimize to 2 to avoid inserting an undesired
7377 hold_mips_optimize
= mips_optimize
;
7379 /* Itbl support may require additional care here. */
7380 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7381 BFD_RELOC_LO16
, AT
);
7382 mips_optimize
= hold_mips_optimize
;
7391 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
7394 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
7396 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
7397 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
7399 if (!HAVE_64BIT_GPRS
)
7401 offset_expr
.X_add_number
+= 4;
7402 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
7403 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
7408 /* New code added to support COPZ instructions.
7409 This code builds table entries out of the macros in mip_opcodes.
7410 R4000 uses interlocks to handle coproc delays.
7411 Other chips (like the R3000) require nops to be inserted for delays.
7413 FIXME: Currently, we require that the user handle delays.
7414 In order to fill delay slots for non-interlocked chips,
7415 we must have a way to specify delays based on the coprocessor.
7416 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7417 What are the side-effects of the cop instruction?
7418 What cache support might we have and what are its effects?
7419 Both coprocessor & memory require delays. how long???
7420 What registers are read/set/modified?
7422 If an itbl is provided to interpret cop instructions,
7423 this knowledge can be encoded in the itbl spec. */
7437 if (NO_ISA_COP (mips_opts
.arch
)
7438 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
7440 as_bad (_("opcode not supported on this processor: %s"),
7441 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
7445 /* For now we just do C (same as Cz). The parameter will be
7446 stored in insn_opcode by mips_ip. */
7447 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7451 move_register (dreg
, sreg
);
7457 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7458 macro_build (NULL
, "mflo", "d", dreg
);
7464 /* The MIPS assembler some times generates shifts and adds. I'm
7465 not trying to be that fancy. GCC should do this for us
7468 load_register (AT
, &imm_expr
, dbl
);
7469 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7470 macro_build (NULL
, "mflo", "d", dreg
);
7486 load_register (AT
, &imm_expr
, dbl
);
7487 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7488 macro_build (NULL
, "mflo", "d", dreg
);
7489 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7490 macro_build (NULL
, "mfhi", "d", AT
);
7492 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7495 expr1
.X_add_number
= 8;
7496 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7497 macro_build (NULL
, "nop", "");
7498 macro_build (NULL
, "break", "c", 6);
7501 macro_build (NULL
, "mflo", "d", dreg
);
7517 load_register (AT
, &imm_expr
, dbl
);
7518 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7519 sreg
, imm
? AT
: treg
);
7520 macro_build (NULL
, "mfhi", "d", AT
);
7521 macro_build (NULL
, "mflo", "d", dreg
);
7523 macro_build (NULL
, "tne", "s,t,q", AT
, ZERO
, 6);
7526 expr1
.X_add_number
= 8;
7527 macro_build (&expr1
, "beq", "s,t,p", AT
, ZERO
);
7528 macro_build (NULL
, "nop", "");
7529 macro_build (NULL
, "break", "c", 6);
7535 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7546 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7547 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7551 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
7552 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7553 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7554 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7558 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7569 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7570 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7574 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
7575 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7576 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7577 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7586 if (imm_expr
.X_op
!= O_constant
)
7587 as_bad (_("Improper rotate count"));
7588 rot
= imm_expr
.X_add_number
& 0x3f;
7589 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7591 rot
= (64 - rot
) & 0x3f;
7593 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7595 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7600 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7603 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7604 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7607 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7608 macro_build (NULL
, rr
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7609 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7617 if (imm_expr
.X_op
!= O_constant
)
7618 as_bad (_("Improper rotate count"));
7619 rot
= imm_expr
.X_add_number
& 0x1f;
7620 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7622 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7627 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7631 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7632 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7633 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7638 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7640 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7644 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
7645 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7646 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7647 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7651 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7653 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7657 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
7658 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7659 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7660 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7669 if (imm_expr
.X_op
!= O_constant
)
7670 as_bad (_("Improper rotate count"));
7671 rot
= imm_expr
.X_add_number
& 0x3f;
7672 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7675 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7677 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7682 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7685 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7686 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7689 macro_build (NULL
, rr
, "d,w,<", AT
, sreg
, rot
);
7690 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7691 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7699 if (imm_expr
.X_op
!= O_constant
)
7700 as_bad (_("Improper rotate count"));
7701 rot
= imm_expr
.X_add_number
& 0x1f;
7702 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7704 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7709 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7713 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7714 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7715 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7721 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7723 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7726 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7727 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7732 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7734 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7739 as_warn (_("Instruction %s: result is always false"),
7741 move_register (dreg
, 0);
7744 if (CPU_HAS_SEQ (mips_opts
.arch
)
7745 && -512 <= imm_expr
.X_add_number
7746 && imm_expr
.X_add_number
< 512)
7748 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7749 (int) imm_expr
.X_add_number
);
7752 if (imm_expr
.X_op
== O_constant
7753 && imm_expr
.X_add_number
>= 0
7754 && imm_expr
.X_add_number
< 0x10000)
7756 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7758 else if (imm_expr
.X_op
== O_constant
7759 && imm_expr
.X_add_number
> -0x8000
7760 && imm_expr
.X_add_number
< 0)
7762 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7763 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7764 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7766 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7769 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7770 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7775 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7776 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7779 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7782 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7788 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7789 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7792 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7794 if (imm_expr
.X_op
== O_constant
7795 && imm_expr
.X_add_number
>= -0x8000
7796 && imm_expr
.X_add_number
< 0x8000)
7798 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7799 dreg
, sreg
, BFD_RELOC_LO16
);
7803 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7804 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7808 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7811 case M_SGT
: /* sreg > treg <==> treg < sreg */
7817 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7820 case M_SGT_I
: /* sreg > I <==> I < sreg */
7827 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7828 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7831 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7837 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7838 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7841 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7848 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7849 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7850 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7854 if (imm_expr
.X_op
== O_constant
7855 && imm_expr
.X_add_number
>= -0x8000
7856 && imm_expr
.X_add_number
< 0x8000)
7858 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7862 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7863 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7867 if (imm_expr
.X_op
== O_constant
7868 && imm_expr
.X_add_number
>= -0x8000
7869 && imm_expr
.X_add_number
< 0x8000)
7871 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7876 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7877 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7882 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7884 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7887 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7888 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7893 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7895 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7900 as_warn (_("Instruction %s: result is always true"),
7902 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7903 dreg
, 0, BFD_RELOC_LO16
);
7906 if (CPU_HAS_SEQ (mips_opts
.arch
)
7907 && -512 <= imm_expr
.X_add_number
7908 && imm_expr
.X_add_number
< 512)
7910 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
7911 (int) imm_expr
.X_add_number
);
7914 if (imm_expr
.X_op
== O_constant
7915 && imm_expr
.X_add_number
>= 0
7916 && imm_expr
.X_add_number
< 0x10000)
7918 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7920 else if (imm_expr
.X_op
== O_constant
7921 && imm_expr
.X_add_number
> -0x8000
7922 && imm_expr
.X_add_number
< 0)
7924 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7925 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7926 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7928 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7931 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7932 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
7937 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7938 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7941 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7947 if (imm_expr
.X_op
== O_constant
7948 && imm_expr
.X_add_number
> -0x8000
7949 && imm_expr
.X_add_number
<= 0x8000)
7951 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7952 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7953 dreg
, sreg
, BFD_RELOC_LO16
);
7957 load_register (AT
, &imm_expr
, dbl
);
7958 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7964 if (imm_expr
.X_op
== O_constant
7965 && imm_expr
.X_add_number
> -0x8000
7966 && imm_expr
.X_add_number
<= 0x8000)
7968 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7969 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7970 dreg
, sreg
, BFD_RELOC_LO16
);
7974 load_register (AT
, &imm_expr
, dbl
);
7975 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7997 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7998 macro_build (NULL
, s
, "s,t", sreg
, AT
);
8003 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8005 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
8006 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
8009 * Is the double cfc1 instruction a bug in the mips assembler;
8010 * or is there a reason for it?
8013 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
8014 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
8015 macro_build (NULL
, "nop", "");
8016 expr1
.X_add_number
= 3;
8017 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
8018 expr1
.X_add_number
= 2;
8019 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
8020 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
8021 macro_build (NULL
, "nop", "");
8022 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
8024 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
8025 macro_build (NULL
, "nop", "");
8036 if (offset_expr
.X_add_number
>= 0x7fff)
8037 as_bad (_("Operand overflow"));
8038 if (!target_big_endian
)
8039 ++offset_expr
.X_add_number
;
8040 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8041 if (!target_big_endian
)
8042 --offset_expr
.X_add_number
;
8044 ++offset_expr
.X_add_number
;
8045 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8046 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
8047 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8060 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8061 as_bad (_("Operand overflow"));
8069 if (!target_big_endian
)
8070 offset_expr
.X_add_number
+= off
;
8071 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8072 if (!target_big_endian
)
8073 offset_expr
.X_add_number
-= off
;
8075 offset_expr
.X_add_number
+= off
;
8076 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8078 /* If necessary, move the result in tempreg to the final destination. */
8079 if (treg
== tempreg
)
8081 /* Protect second load's delay slot. */
8083 move_register (treg
, tempreg
);
8097 load_address (AT
, &offset_expr
, &used_at
);
8099 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8100 if (!target_big_endian
)
8101 expr1
.X_add_number
= off
;
8103 expr1
.X_add_number
= 0;
8104 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8105 if (!target_big_endian
)
8106 expr1
.X_add_number
= 0;
8108 expr1
.X_add_number
= off
;
8109 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8115 load_address (AT
, &offset_expr
, &used_at
);
8117 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8118 if (target_big_endian
)
8119 expr1
.X_add_number
= 0;
8120 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
8121 treg
, BFD_RELOC_LO16
, AT
);
8122 if (target_big_endian
)
8123 expr1
.X_add_number
= 1;
8125 expr1
.X_add_number
= 0;
8126 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8127 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8128 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8133 if (offset_expr
.X_add_number
>= 0x7fff)
8134 as_bad (_("Operand overflow"));
8135 if (target_big_endian
)
8136 ++offset_expr
.X_add_number
;
8137 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8138 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
8139 if (target_big_endian
)
8140 --offset_expr
.X_add_number
;
8142 ++offset_expr
.X_add_number
;
8143 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8156 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8157 as_bad (_("Operand overflow"));
8158 if (!target_big_endian
)
8159 offset_expr
.X_add_number
+= off
;
8160 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8161 if (!target_big_endian
)
8162 offset_expr
.X_add_number
-= off
;
8164 offset_expr
.X_add_number
+= off
;
8165 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8179 load_address (AT
, &offset_expr
, &used_at
);
8181 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8182 if (!target_big_endian
)
8183 expr1
.X_add_number
= off
;
8185 expr1
.X_add_number
= 0;
8186 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8187 if (!target_big_endian
)
8188 expr1
.X_add_number
= 0;
8190 expr1
.X_add_number
= off
;
8191 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8196 load_address (AT
, &offset_expr
, &used_at
);
8198 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8199 if (!target_big_endian
)
8200 expr1
.X_add_number
= 0;
8201 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8202 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8203 if (!target_big_endian
)
8204 expr1
.X_add_number
= 1;
8206 expr1
.X_add_number
= 0;
8207 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8208 if (!target_big_endian
)
8209 expr1
.X_add_number
= 0;
8211 expr1
.X_add_number
= 1;
8212 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8213 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8214 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8218 /* FIXME: Check if this is one of the itbl macros, since they
8219 are added dynamically. */
8220 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8223 if (!mips_opts
.at
&& used_at
)
8224 as_bad (_("Macro used $at after \".set noat\""));
8227 /* Implement macros in mips16 mode. */
8230 mips16_macro (struct mips_cl_insn
*ip
)
8233 int xreg
, yreg
, zreg
, tmp
;
8236 const char *s
, *s2
, *s3
;
8238 mask
= ip
->insn_mo
->mask
;
8240 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8241 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8242 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8244 expr1
.X_op
= O_constant
;
8245 expr1
.X_op_symbol
= NULL
;
8246 expr1
.X_add_symbol
= NULL
;
8247 expr1
.X_add_number
= 1;
8267 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8268 expr1
.X_add_number
= 2;
8269 macro_build (&expr1
, "bnez", "x,p", yreg
);
8270 macro_build (NULL
, "break", "6", 7);
8272 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8273 since that causes an overflow. We should do that as well,
8274 but I don't see how to do the comparisons without a temporary
8277 macro_build (NULL
, s
, "x", zreg
);
8297 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8298 expr1
.X_add_number
= 2;
8299 macro_build (&expr1
, "bnez", "x,p", yreg
);
8300 macro_build (NULL
, "break", "6", 7);
8302 macro_build (NULL
, s2
, "x", zreg
);
8308 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8309 macro_build (NULL
, "mflo", "x", zreg
);
8317 if (imm_expr
.X_op
!= O_constant
)
8318 as_bad (_("Unsupported large constant"));
8319 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8320 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8324 if (imm_expr
.X_op
!= O_constant
)
8325 as_bad (_("Unsupported large constant"));
8326 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8327 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8331 if (imm_expr
.X_op
!= O_constant
)
8332 as_bad (_("Unsupported large constant"));
8333 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8334 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8356 goto do_reverse_branch
;
8360 goto do_reverse_branch
;
8372 goto do_reverse_branch
;
8383 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8384 macro_build (&offset_expr
, s2
, "p");
8411 goto do_addone_branch_i
;
8416 goto do_addone_branch_i
;
8431 goto do_addone_branch_i
;
8438 if (imm_expr
.X_op
!= O_constant
)
8439 as_bad (_("Unsupported large constant"));
8440 ++imm_expr
.X_add_number
;
8443 macro_build (&imm_expr
, s
, s3
, xreg
);
8444 macro_build (&offset_expr
, s2
, "p");
8448 expr1
.X_add_number
= 0;
8449 macro_build (&expr1
, "slti", "x,8", yreg
);
8451 move_register (xreg
, yreg
);
8452 expr1
.X_add_number
= 2;
8453 macro_build (&expr1
, "bteqz", "p");
8454 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8458 /* For consistency checking, verify that all bits are specified either
8459 by the match/mask part of the instruction definition, or by the
8462 validate_mips_insn (const struct mips_opcode
*opc
)
8464 const char *p
= opc
->args
;
8466 unsigned long used_bits
= opc
->mask
;
8468 if ((used_bits
& opc
->match
) != opc
->match
)
8470 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8471 opc
->name
, opc
->args
);
8474 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8484 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8485 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8486 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8487 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8488 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8489 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8490 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8491 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8492 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8493 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8494 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8495 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8496 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8498 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8499 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8500 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8501 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8502 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8503 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8504 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8505 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8506 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8507 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8508 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
8509 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
8510 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
8511 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
8512 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
8515 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8516 c
, opc
->name
, opc
->args
);
8520 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8521 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8523 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8524 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8525 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8526 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8528 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8529 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8531 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8532 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8534 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8535 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8536 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8537 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8538 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8539 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8540 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8541 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8542 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8543 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8544 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8545 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8546 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8547 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8548 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8549 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8550 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8552 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8553 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8554 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8555 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8557 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8558 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8559 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8560 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8561 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8562 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8563 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8564 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8565 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8568 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8569 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8570 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8571 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8572 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8575 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8576 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8577 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8578 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8579 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8580 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8581 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8582 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8583 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8584 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8585 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8586 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8587 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8588 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8589 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8590 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8591 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8592 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8594 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8595 c
, opc
->name
, opc
->args
);
8599 if (used_bits
!= 0xffffffff)
8601 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8602 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8608 /* UDI immediates. */
8616 static const struct mips_immed mips_immed
[] = {
8617 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8618 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8619 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8620 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8624 /* Check whether an odd floating-point register is allowed. */
8626 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8628 const char *s
= insn
->name
;
8630 if (insn
->pinfo
== INSN_MACRO
)
8631 /* Let a macro pass, we'll catch it later when it is expanded. */
8634 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8636 /* Allow odd registers for single-precision ops. */
8637 switch (insn
->pinfo
& (FP_S
| FP_D
))
8641 return 1; /* both single precision - ok */
8643 return 0; /* both double precision - fail */
8648 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8649 s
= strchr (insn
->name
, '.');
8651 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8652 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8655 /* Single-precision coprocessor loads and moves are OK too. */
8656 if ((insn
->pinfo
& FP_S
)
8657 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8658 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8664 /* This routine assembles an instruction into its binary format. As a
8665 side effect, it sets one of the global variables imm_reloc or
8666 offset_reloc to the type of relocation to do if one of the operands
8667 is an address expression. */
8670 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8675 struct mips_opcode
*insn
;
8678 unsigned int lastregno
;
8679 unsigned int lastpos
= 0;
8680 unsigned int limlo
, limhi
;
8683 offsetT min_range
, max_range
;
8689 /* If the instruction contains a '.', we first try to match an instruction
8690 including the '.'. Then we try again without the '.'. */
8692 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8695 /* If we stopped on whitespace, then replace the whitespace with null for
8696 the call to hash_find. Save the character we replaced just in case we
8697 have to re-parse the instruction. */
8704 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8706 /* If we didn't find the instruction in the opcode table, try again, but
8707 this time with just the instruction up to, but not including the
8711 /* Restore the character we overwrite above (if any). */
8715 /* Scan up to the first '.' or whitespace. */
8717 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8721 /* If we did not find a '.', then we can quit now. */
8724 insn_error
= _("Unrecognized opcode");
8728 /* Lookup the instruction in the hash table. */
8730 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8732 insn_error
= _("Unrecognized opcode");
8742 gas_assert (strcmp (insn
->name
, str
) == 0);
8744 ok
= is_opcode_valid (insn
);
8747 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8748 && strcmp (insn
->name
, insn
[1].name
) == 0)
8757 static char buf
[100];
8759 _("opcode not supported on this processor: %s (%s)"),
8760 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8761 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8770 create_insn (ip
, insn
);
8773 lastregno
= 0xffffffff;
8774 for (args
= insn
->args
;; ++args
)
8778 s
+= strspn (s
, " \t");
8782 case '\0': /* end of args */
8787 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
8788 my_getExpression (&imm_expr
, s
);
8789 check_absolute_expr (ip
, &imm_expr
);
8790 if ((unsigned long) imm_expr
.X_add_number
!= 1
8791 && (unsigned long) imm_expr
.X_add_number
!= 3)
8793 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8794 (unsigned long) imm_expr
.X_add_number
);
8796 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8797 imm_expr
.X_op
= O_absent
;
8801 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
8802 my_getExpression (&imm_expr
, s
);
8803 check_absolute_expr (ip
, &imm_expr
);
8804 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8806 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8807 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8809 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8810 imm_expr
.X_op
= O_absent
;
8814 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
8815 my_getExpression (&imm_expr
, s
);
8816 check_absolute_expr (ip
, &imm_expr
);
8817 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8819 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8820 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8822 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8823 imm_expr
.X_op
= O_absent
;
8827 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
8828 my_getExpression (&imm_expr
, s
);
8829 check_absolute_expr (ip
, &imm_expr
);
8830 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8832 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8833 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8835 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8836 imm_expr
.X_op
= O_absent
;
8840 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
8841 my_getExpression (&imm_expr
, s
);
8842 check_absolute_expr (ip
, &imm_expr
);
8843 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8845 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8846 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8848 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8849 imm_expr
.X_op
= O_absent
;
8853 case '7': /* Four DSP accumulators in bits 11,12. */
8854 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8855 s
[3] >= '0' && s
[3] <= '3')
8859 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8863 as_bad (_("Invalid dsp acc register"));
8866 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
8867 my_getExpression (&imm_expr
, s
);
8868 check_absolute_expr (ip
, &imm_expr
);
8869 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8871 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8873 (unsigned long) imm_expr
.X_add_number
);
8875 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8876 imm_expr
.X_op
= O_absent
;
8880 case '9': /* Four DSP accumulators in bits 21,22. */
8881 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8882 s
[3] >= '0' && s
[3] <= '3')
8886 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8890 as_bad (_("Invalid dsp acc register"));
8893 case '0': /* DSP 6-bit signed immediate in bit 20. */
8894 my_getExpression (&imm_expr
, s
);
8895 check_absolute_expr (ip
, &imm_expr
);
8896 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8897 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8898 if (imm_expr
.X_add_number
< min_range
||
8899 imm_expr
.X_add_number
> max_range
)
8901 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8902 (long) min_range
, (long) max_range
,
8903 (long) imm_expr
.X_add_number
);
8905 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8906 imm_expr
.X_op
= O_absent
;
8910 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
8911 my_getExpression (&imm_expr
, s
);
8912 check_absolute_expr (ip
, &imm_expr
);
8913 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8915 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8917 (unsigned long) imm_expr
.X_add_number
);
8919 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8920 imm_expr
.X_op
= O_absent
;
8924 case ':': /* DSP 7-bit signed immediate in bit 19. */
8925 my_getExpression (&imm_expr
, s
);
8926 check_absolute_expr (ip
, &imm_expr
);
8927 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8928 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8929 if (imm_expr
.X_add_number
< min_range
||
8930 imm_expr
.X_add_number
> max_range
)
8932 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8933 (long) min_range
, (long) max_range
,
8934 (long) imm_expr
.X_add_number
);
8936 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8937 imm_expr
.X_op
= O_absent
;
8941 case '@': /* DSP 10-bit signed immediate in bit 16. */
8942 my_getExpression (&imm_expr
, s
);
8943 check_absolute_expr (ip
, &imm_expr
);
8944 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8945 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8946 if (imm_expr
.X_add_number
< min_range
||
8947 imm_expr
.X_add_number
> max_range
)
8949 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8950 (long) min_range
, (long) max_range
,
8951 (long) imm_expr
.X_add_number
);
8953 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8954 imm_expr
.X_op
= O_absent
;
8958 case '!': /* MT usermode flag bit. */
8959 my_getExpression (&imm_expr
, s
);
8960 check_absolute_expr (ip
, &imm_expr
);
8961 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8962 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8963 (unsigned long) imm_expr
.X_add_number
);
8964 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8965 imm_expr
.X_op
= O_absent
;
8969 case '$': /* MT load high flag bit. */
8970 my_getExpression (&imm_expr
, s
);
8971 check_absolute_expr (ip
, &imm_expr
);
8972 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8973 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8974 (unsigned long) imm_expr
.X_add_number
);
8975 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8976 imm_expr
.X_op
= O_absent
;
8980 case '*': /* Four DSP accumulators in bits 18,19. */
8981 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8982 s
[3] >= '0' && s
[3] <= '3')
8986 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8990 as_bad (_("Invalid dsp/smartmips acc register"));
8993 case '&': /* Four DSP accumulators in bits 13,14. */
8994 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8995 s
[3] >= '0' && s
[3] <= '3')
8999 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
9003 as_bad (_("Invalid dsp/smartmips acc register"));
9015 INSERT_OPERAND (RS
, *ip
, lastregno
);
9019 INSERT_OPERAND (RT
, *ip
, lastregno
);
9023 INSERT_OPERAND (FT
, *ip
, lastregno
);
9027 INSERT_OPERAND (FS
, *ip
, lastregno
);
9033 /* Handle optional base register.
9034 Either the base register is omitted or
9035 we must have a left paren. */
9036 /* This is dependent on the next operand specifier
9037 is a base register specification. */
9038 gas_assert (args
[1] == 'b');
9042 case ')': /* These must match exactly. */
9049 case '+': /* Opcode extension character. */
9052 case '1': /* UDI immediates. */
9057 const struct mips_immed
*imm
= mips_immed
;
9059 while (imm
->type
&& imm
->type
!= *args
)
9063 my_getExpression (&imm_expr
, s
);
9064 check_absolute_expr (ip
, &imm_expr
);
9065 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
9067 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9068 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
9069 (unsigned long) imm_expr
.X_add_number
,
9070 (unsigned long) imm_expr
.X_add_number
);
9071 imm_expr
.X_add_number
&= imm
->mask
;
9073 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
9075 imm_expr
.X_op
= O_absent
;
9080 case 'A': /* ins/ext position, becomes LSB. */
9089 my_getExpression (&imm_expr
, s
);
9090 check_absolute_expr (ip
, &imm_expr
);
9091 if ((unsigned long) imm_expr
.X_add_number
< limlo
9092 || (unsigned long) imm_expr
.X_add_number
> limhi
)
9094 as_bad (_("Improper position (%lu)"),
9095 (unsigned long) imm_expr
.X_add_number
);
9096 imm_expr
.X_add_number
= limlo
;
9098 lastpos
= imm_expr
.X_add_number
;
9099 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9100 imm_expr
.X_op
= O_absent
;
9104 case 'B': /* ins size, becomes MSB. */
9113 my_getExpression (&imm_expr
, s
);
9114 check_absolute_expr (ip
, &imm_expr
);
9115 /* Check for negative input so that small negative numbers
9116 will not succeed incorrectly. The checks against
9117 (pos+size) transitively check "size" itself,
9118 assuming that "pos" is reasonable. */
9119 if ((long) imm_expr
.X_add_number
< 0
9120 || ((unsigned long) imm_expr
.X_add_number
9122 || ((unsigned long) imm_expr
.X_add_number
9125 as_bad (_("Improper insert size (%lu, position %lu)"),
9126 (unsigned long) imm_expr
.X_add_number
,
9127 (unsigned long) lastpos
);
9128 imm_expr
.X_add_number
= limlo
- lastpos
;
9130 INSERT_OPERAND (INSMSB
, *ip
,
9131 lastpos
+ imm_expr
.X_add_number
- 1);
9132 imm_expr
.X_op
= O_absent
;
9136 case 'C': /* ext size, becomes MSBD. */
9149 my_getExpression (&imm_expr
, s
);
9150 check_absolute_expr (ip
, &imm_expr
);
9151 /* Check for negative input so that small negative numbers
9152 will not succeed incorrectly. The checks against
9153 (pos+size) transitively check "size" itself,
9154 assuming that "pos" is reasonable. */
9155 if ((long) imm_expr
.X_add_number
< 0
9156 || ((unsigned long) imm_expr
.X_add_number
9158 || ((unsigned long) imm_expr
.X_add_number
9161 as_bad (_("Improper extract size (%lu, position %lu)"),
9162 (unsigned long) imm_expr
.X_add_number
,
9163 (unsigned long) lastpos
);
9164 imm_expr
.X_add_number
= limlo
- lastpos
;
9166 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
9167 imm_expr
.X_op
= O_absent
;
9172 /* +D is for disassembly only; never match. */
9176 /* "+I" is like "I", except that imm2_expr is used. */
9177 my_getExpression (&imm2_expr
, s
);
9178 if (imm2_expr
.X_op
!= O_big
9179 && imm2_expr
.X_op
!= O_constant
)
9180 insn_error
= _("absolute expression required");
9181 if (HAVE_32BIT_GPRS
)
9182 normalize_constant_expr (&imm2_expr
);
9186 case 'T': /* Coprocessor register. */
9187 /* +T is for disassembly only; never match. */
9190 case 't': /* Coprocessor register number. */
9191 if (s
[0] == '$' && ISDIGIT (s
[1]))
9201 while (ISDIGIT (*s
));
9203 as_bad (_("Invalid register number (%d)"), regno
);
9206 INSERT_OPERAND (RT
, *ip
, regno
);
9211 as_bad (_("Invalid coprocessor 0 register number"));
9215 /* bbit[01] and bbit[01]32 bit index. Give error if index
9216 is not in the valid range. */
9217 my_getExpression (&imm_expr
, s
);
9218 check_absolute_expr (ip
, &imm_expr
);
9219 if ((unsigned) imm_expr
.X_add_number
> 31)
9221 as_bad (_("Improper bit index (%lu)"),
9222 (unsigned long) imm_expr
.X_add_number
);
9223 imm_expr
.X_add_number
= 0;
9225 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9226 imm_expr
.X_op
= O_absent
;
9231 /* bbit[01] bit index when bbit is used but we generate
9232 bbit[01]32 because the index is over 32. Move to the
9233 next candidate if index is not in the valid range. */
9234 my_getExpression (&imm_expr
, s
);
9235 check_absolute_expr (ip
, &imm_expr
);
9236 if ((unsigned) imm_expr
.X_add_number
< 32
9237 || (unsigned) imm_expr
.X_add_number
> 63)
9239 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9240 imm_expr
.X_op
= O_absent
;
9245 /* cins, cins32, exts and exts32 position field. Give error
9246 if it's not in the valid range. */
9247 my_getExpression (&imm_expr
, s
);
9248 check_absolute_expr (ip
, &imm_expr
);
9249 if ((unsigned) imm_expr
.X_add_number
> 31)
9251 as_bad (_("Improper position (%lu)"),
9252 (unsigned long) imm_expr
.X_add_number
);
9253 imm_expr
.X_add_number
= 0;
9255 /* Make the pos explicit to simplify +S. */
9256 lastpos
= imm_expr
.X_add_number
+ 32;
9257 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9258 imm_expr
.X_op
= O_absent
;
9263 /* cins, cins32, exts and exts32 position field. Move to
9264 the next candidate if it's not in the valid range. */
9265 my_getExpression (&imm_expr
, s
);
9266 check_absolute_expr (ip
, &imm_expr
);
9267 if ((unsigned) imm_expr
.X_add_number
< 32
9268 || (unsigned) imm_expr
.X_add_number
> 63)
9270 lastpos
= imm_expr
.X_add_number
;
9271 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9272 imm_expr
.X_op
= O_absent
;
9277 /* cins and exts length-minus-one field. */
9278 my_getExpression (&imm_expr
, s
);
9279 check_absolute_expr (ip
, &imm_expr
);
9280 if ((unsigned long) imm_expr
.X_add_number
> 31)
9282 as_bad (_("Improper size (%lu)"),
9283 (unsigned long) imm_expr
.X_add_number
);
9284 imm_expr
.X_add_number
= 0;
9286 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9287 imm_expr
.X_op
= O_absent
;
9292 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9293 length-minus-one field. */
9294 my_getExpression (&imm_expr
, s
);
9295 check_absolute_expr (ip
, &imm_expr
);
9296 if ((long) imm_expr
.X_add_number
< 0
9297 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9299 as_bad (_("Improper size (%lu)"),
9300 (unsigned long) imm_expr
.X_add_number
);
9301 imm_expr
.X_add_number
= 0;
9303 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9304 imm_expr
.X_op
= O_absent
;
9309 /* seqi/snei immediate field. */
9310 my_getExpression (&imm_expr
, s
);
9311 check_absolute_expr (ip
, &imm_expr
);
9312 if ((long) imm_expr
.X_add_number
< -512
9313 || (long) imm_expr
.X_add_number
>= 512)
9315 as_bad (_("Improper immediate (%ld)"),
9316 (long) imm_expr
.X_add_number
);
9317 imm_expr
.X_add_number
= 0;
9319 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9320 imm_expr
.X_op
= O_absent
;
9324 case 'a': /* 8-bit signed offset in bit 6 */
9325 my_getExpression (&imm_expr
, s
);
9326 check_absolute_expr (ip
, &imm_expr
);
9327 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
9328 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
9329 if (imm_expr
.X_add_number
< min_range
9330 || imm_expr
.X_add_number
> max_range
)
9332 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9333 (long) min_range
, (long) max_range
,
9334 (long) imm_expr
.X_add_number
);
9336 INSERT_OPERAND (OFFSET_A
, *ip
, imm_expr
.X_add_number
);
9337 imm_expr
.X_op
= O_absent
;
9341 case 'b': /* 8-bit signed offset in bit 3 */
9342 my_getExpression (&imm_expr
, s
);
9343 check_absolute_expr (ip
, &imm_expr
);
9344 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
9345 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
9346 if (imm_expr
.X_add_number
< min_range
9347 || imm_expr
.X_add_number
> max_range
)
9349 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9350 (long) min_range
, (long) max_range
,
9351 (long) imm_expr
.X_add_number
);
9353 INSERT_OPERAND (OFFSET_B
, *ip
, imm_expr
.X_add_number
);
9354 imm_expr
.X_op
= O_absent
;
9358 case 'c': /* 9-bit signed offset in bit 6 */
9359 my_getExpression (&imm_expr
, s
);
9360 check_absolute_expr (ip
, &imm_expr
);
9361 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
9362 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
9363 /* We check the offset range before adjusted. */
9366 if (imm_expr
.X_add_number
< min_range
9367 || imm_expr
.X_add_number
> max_range
)
9369 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9370 (long) min_range
, (long) max_range
,
9371 (long) imm_expr
.X_add_number
);
9373 if (imm_expr
.X_add_number
& 0xf)
9375 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9376 (long) imm_expr
.X_add_number
);
9378 /* Right shift 4 bits to adjust the offset operand. */
9379 INSERT_OPERAND (OFFSET_C
, *ip
, imm_expr
.X_add_number
>> 4);
9380 imm_expr
.X_op
= O_absent
;
9385 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
9387 if (regno
== AT
&& mips_opts
.at
)
9389 if (mips_opts
.at
== ATREG
)
9390 as_warn (_("used $at without \".set noat\""));
9392 as_warn (_("used $%u with \".set at=$%u\""),
9393 regno
, mips_opts
.at
);
9395 INSERT_OPERAND (RZ
, *ip
, regno
);
9399 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
9401 INSERT_OPERAND (FZ
, *ip
, regno
);
9405 as_bad (_("Internal error: bad mips opcode "
9406 "(unknown extension operand type `+%c'): %s %s"),
9407 *args
, insn
->name
, insn
->args
);
9408 /* Further processing is fruitless. */
9413 case '<': /* must be at least one digit */
9415 * According to the manual, if the shift amount is greater
9416 * than 31 or less than 0, then the shift amount should be
9417 * mod 32. In reality the mips assembler issues an error.
9418 * We issue a warning and mask out all but the low 5 bits.
9420 my_getExpression (&imm_expr
, s
);
9421 check_absolute_expr (ip
, &imm_expr
);
9422 if ((unsigned long) imm_expr
.X_add_number
> 31)
9423 as_warn (_("Improper shift amount (%lu)"),
9424 (unsigned long) imm_expr
.X_add_number
);
9425 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9426 imm_expr
.X_op
= O_absent
;
9430 case '>': /* shift amount minus 32 */
9431 my_getExpression (&imm_expr
, s
);
9432 check_absolute_expr (ip
, &imm_expr
);
9433 if ((unsigned long) imm_expr
.X_add_number
< 32
9434 || (unsigned long) imm_expr
.X_add_number
> 63)
9436 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9437 imm_expr
.X_op
= O_absent
;
9441 case 'k': /* CACHE code. */
9442 case 'h': /* PREFX code. */
9443 case '1': /* SYNC type. */
9444 my_getExpression (&imm_expr
, s
);
9445 check_absolute_expr (ip
, &imm_expr
);
9446 if ((unsigned long) imm_expr
.X_add_number
> 31)
9447 as_warn (_("Invalid value for `%s' (%lu)"),
9449 (unsigned long) imm_expr
.X_add_number
);
9452 if (mips_fix_cn63xxp1
&& strcmp ("pref", insn
->name
) == 0)
9453 switch (imm_expr
.X_add_number
)
9462 case 31: /* These are ok. */
9465 default: /* The rest must be changed to 28. */
9466 imm_expr
.X_add_number
= 28;
9469 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9471 else if (*args
== 'h')
9472 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9474 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9475 imm_expr
.X_op
= O_absent
;
9479 case 'c': /* BREAK code. */
9480 my_getExpression (&imm_expr
, s
);
9481 check_absolute_expr (ip
, &imm_expr
);
9482 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9483 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9485 (unsigned long) imm_expr
.X_add_number
);
9486 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9487 imm_expr
.X_op
= O_absent
;
9491 case 'q': /* Lower BREAK code. */
9492 my_getExpression (&imm_expr
, s
);
9493 check_absolute_expr (ip
, &imm_expr
);
9494 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9495 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9497 (unsigned long) imm_expr
.X_add_number
);
9498 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9499 imm_expr
.X_op
= O_absent
;
9503 case 'B': /* 20-bit SYSCALL/BREAK code. */
9504 my_getExpression (&imm_expr
, s
);
9505 check_absolute_expr (ip
, &imm_expr
);
9506 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9507 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9509 (unsigned long) imm_expr
.X_add_number
);
9510 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9511 imm_expr
.X_op
= O_absent
;
9515 case 'C': /* Coprocessor code. */
9516 my_getExpression (&imm_expr
, s
);
9517 check_absolute_expr (ip
, &imm_expr
);
9518 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9520 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9521 (unsigned long) imm_expr
.X_add_number
);
9522 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9524 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9525 imm_expr
.X_op
= O_absent
;
9529 case 'J': /* 19-bit WAIT code. */
9530 my_getExpression (&imm_expr
, s
);
9531 check_absolute_expr (ip
, &imm_expr
);
9532 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9534 as_warn (_("Illegal 19-bit code (%lu)"),
9535 (unsigned long) imm_expr
.X_add_number
);
9536 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9538 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9539 imm_expr
.X_op
= O_absent
;
9543 case 'P': /* Performance register. */
9544 my_getExpression (&imm_expr
, s
);
9545 check_absolute_expr (ip
, &imm_expr
);
9546 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9547 as_warn (_("Invalid performance register (%lu)"),
9548 (unsigned long) imm_expr
.X_add_number
);
9549 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9550 imm_expr
.X_op
= O_absent
;
9554 case 'G': /* Coprocessor destination register. */
9555 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9556 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9558 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9559 INSERT_OPERAND (RD
, *ip
, regno
);
9568 case 'b': /* Base register. */
9569 case 'd': /* Destination register. */
9570 case 's': /* Source register. */
9571 case 't': /* Target register. */
9572 case 'r': /* Both target and source. */
9573 case 'v': /* Both dest and source. */
9574 case 'w': /* Both dest and target. */
9575 case 'E': /* Coprocessor target register. */
9576 case 'K': /* RDHWR destination register. */
9577 case 'x': /* Ignore register name. */
9578 case 'z': /* Must be zero register. */
9579 case 'U': /* Destination register (CLO/CLZ). */
9580 case 'g': /* Coprocessor destination register. */
9582 if (*args
== 'E' || *args
== 'K')
9583 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9586 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9587 if (regno
== AT
&& mips_opts
.at
)
9589 if (mips_opts
.at
== ATREG
)
9590 as_warn (_("Used $at without \".set noat\""));
9592 as_warn (_("Used $%u with \".set at=$%u\""),
9593 regno
, mips_opts
.at
);
9603 if (c
== 'r' || c
== 'v' || c
== 'w')
9610 /* 'z' only matches $0. */
9611 if (c
== 'z' && regno
!= 0)
9614 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
9616 if (regno
== lastregno
)
9619 = _("Source and destination must be different");
9622 if (regno
== 31 && lastregno
== 0xffffffff)
9625 = _("A destination register must be supplied");
9629 /* Now that we have assembled one operand, we use the args
9630 string to figure out where it goes in the instruction. */
9637 INSERT_OPERAND (RS
, *ip
, regno
);
9642 INSERT_OPERAND (RD
, *ip
, regno
);
9645 INSERT_OPERAND (RD
, *ip
, regno
);
9646 INSERT_OPERAND (RT
, *ip
, regno
);
9651 INSERT_OPERAND (RT
, *ip
, regno
);
9654 /* This case exists because on the r3000 trunc
9655 expands into a macro which requires a gp
9656 register. On the r6000 or r4000 it is
9657 assembled into a single instruction which
9658 ignores the register. Thus the insn version
9659 is MIPS_ISA2 and uses 'x', and the macro
9660 version is MIPS_ISA1 and uses 't'. */
9663 /* This case is for the div instruction, which
9664 acts differently if the destination argument
9665 is $0. This only matches $0, and is checked
9666 outside the switch. */
9676 INSERT_OPERAND (RS
, *ip
, lastregno
);
9679 INSERT_OPERAND (RT
, *ip
, lastregno
);
9684 case 'O': /* MDMX alignment immediate constant. */
9685 my_getExpression (&imm_expr
, s
);
9686 check_absolute_expr (ip
, &imm_expr
);
9687 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9688 as_warn (_("Improper align amount (%ld), using low bits"),
9689 (long) imm_expr
.X_add_number
);
9690 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9691 imm_expr
.X_op
= O_absent
;
9695 case 'Q': /* MDMX vector, element sel, or const. */
9698 /* MDMX Immediate. */
9699 my_getExpression (&imm_expr
, s
);
9700 check_absolute_expr (ip
, &imm_expr
);
9701 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9702 as_warn (_("Invalid MDMX Immediate (%ld)"),
9703 (long) imm_expr
.X_add_number
);
9704 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9705 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9706 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9708 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9709 imm_expr
.X_op
= O_absent
;
9713 /* Not MDMX Immediate. Fall through. */
9714 case 'X': /* MDMX destination register. */
9715 case 'Y': /* MDMX source register. */
9716 case 'Z': /* MDMX target register. */
9718 case 'D': /* Floating point destination register. */
9719 case 'S': /* Floating point source register. */
9720 case 'T': /* Floating point target register. */
9721 case 'R': /* Floating point source register. */
9726 || (mips_opts
.ase_mdmx
9727 && (ip
->insn_mo
->pinfo
& FP_D
)
9728 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9729 | INSN_COPROC_MEMORY_DELAY
9730 | INSN_LOAD_COPROC_DELAY
9731 | INSN_LOAD_MEMORY_DELAY
9732 | INSN_STORE_MEMORY
))))
9735 if (reg_lookup (&s
, rtype
, ®no
))
9737 if ((regno
& 1) != 0
9739 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9740 as_warn (_("Float register should be even, was %d"),
9748 if (c
== 'V' || c
== 'W')
9759 INSERT_OPERAND (FD
, *ip
, regno
);
9764 INSERT_OPERAND (FS
, *ip
, regno
);
9767 /* This is like 'Z', but also needs to fix the MDMX
9768 vector/scalar select bits. Note that the
9769 scalar immediate case is handled above. */
9772 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9773 int max_el
= (is_qh
? 3 : 7);
9775 my_getExpression(&imm_expr
, s
);
9776 check_absolute_expr (ip
, &imm_expr
);
9778 if (imm_expr
.X_add_number
> max_el
)
9779 as_bad (_("Bad element selector %ld"),
9780 (long) imm_expr
.X_add_number
);
9781 imm_expr
.X_add_number
&= max_el
;
9782 ip
->insn_opcode
|= (imm_expr
.X_add_number
9785 imm_expr
.X_op
= O_absent
;
9787 as_warn (_("Expecting ']' found '%s'"), s
);
9793 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9794 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9797 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9804 INSERT_OPERAND (FT
, *ip
, regno
);
9807 INSERT_OPERAND (FR
, *ip
, regno
);
9817 INSERT_OPERAND (FS
, *ip
, lastregno
);
9820 INSERT_OPERAND (FT
, *ip
, lastregno
);
9826 my_getExpression (&imm_expr
, s
);
9827 if (imm_expr
.X_op
!= O_big
9828 && imm_expr
.X_op
!= O_constant
)
9829 insn_error
= _("absolute expression required");
9830 if (HAVE_32BIT_GPRS
)
9831 normalize_constant_expr (&imm_expr
);
9836 my_getExpression (&offset_expr
, s
);
9837 normalize_address_expr (&offset_expr
);
9838 *imm_reloc
= BFD_RELOC_32
;
9851 unsigned char temp
[8];
9853 unsigned int length
;
9858 /* These only appear as the last operand in an
9859 instruction, and every instruction that accepts
9860 them in any variant accepts them in all variants.
9861 This means we don't have to worry about backing out
9862 any changes if the instruction does not match.
9864 The difference between them is the size of the
9865 floating point constant and where it goes. For 'F'
9866 and 'L' the constant is 64 bits; for 'f' and 'l' it
9867 is 32 bits. Where the constant is placed is based
9868 on how the MIPS assembler does things:
9871 f -- immediate value
9874 The .lit4 and .lit8 sections are only used if
9875 permitted by the -G argument.
9877 The code below needs to know whether the target register
9878 is 32 or 64 bits wide. It relies on the fact 'f' and
9879 'F' are used with GPR-based instructions and 'l' and
9880 'L' are used with FPR-based instructions. */
9882 f64
= *args
== 'F' || *args
== 'L';
9883 using_gprs
= *args
== 'F' || *args
== 'f';
9885 save_in
= input_line_pointer
;
9886 input_line_pointer
= s
;
9887 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9889 s
= input_line_pointer
;
9890 input_line_pointer
= save_in
;
9891 if (err
!= NULL
&& *err
!= '\0')
9893 as_bad (_("Bad floating point constant: %s"), err
);
9894 memset (temp
, '\0', sizeof temp
);
9895 length
= f64
? 8 : 4;
9898 gas_assert (length
== (unsigned) (f64
? 8 : 4));
9902 && (g_switch_value
< 4
9903 || (temp
[0] == 0 && temp
[1] == 0)
9904 || (temp
[2] == 0 && temp
[3] == 0))))
9906 imm_expr
.X_op
= O_constant
;
9907 if (!target_big_endian
)
9908 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9910 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9913 && !mips_disable_float_construction
9914 /* Constants can only be constructed in GPRs and
9915 copied to FPRs if the GPRs are at least as wide
9916 as the FPRs. Force the constant into memory if
9917 we are using 64-bit FPRs but the GPRs are only
9920 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9921 && ((temp
[0] == 0 && temp
[1] == 0)
9922 || (temp
[2] == 0 && temp
[3] == 0))
9923 && ((temp
[4] == 0 && temp
[5] == 0)
9924 || (temp
[6] == 0 && temp
[7] == 0)))
9926 /* The value is simple enough to load with a couple of
9927 instructions. If using 32-bit registers, set
9928 imm_expr to the high order 32 bits and offset_expr to
9929 the low order 32 bits. Otherwise, set imm_expr to
9930 the entire 64 bit constant. */
9931 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9933 imm_expr
.X_op
= O_constant
;
9934 offset_expr
.X_op
= O_constant
;
9935 if (!target_big_endian
)
9937 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9938 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9942 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9943 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9945 if (offset_expr
.X_add_number
== 0)
9946 offset_expr
.X_op
= O_absent
;
9948 else if (sizeof (imm_expr
.X_add_number
) > 4)
9950 imm_expr
.X_op
= O_constant
;
9951 if (!target_big_endian
)
9952 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9954 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9958 imm_expr
.X_op
= O_big
;
9959 imm_expr
.X_add_number
= 4;
9960 if (!target_big_endian
)
9962 generic_bignum
[0] = bfd_getl16 (temp
);
9963 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9964 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9965 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9969 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9970 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9971 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9972 generic_bignum
[3] = bfd_getb16 (temp
);
9978 const char *newname
;
9981 /* Switch to the right section. */
9983 subseg
= now_subseg
;
9986 default: /* unused default case avoids warnings. */
9988 newname
= RDATA_SECTION_NAME
;
9989 if (g_switch_value
>= 8)
9993 newname
= RDATA_SECTION_NAME
;
9996 gas_assert (g_switch_value
>= 4);
10000 new_seg
= subseg_new (newname
, (subsegT
) 0);
10002 bfd_set_section_flags (stdoutput
, new_seg
,
10007 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
10008 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
10009 record_alignment (new_seg
, 4);
10011 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
10012 if (seg
== now_seg
)
10013 as_bad (_("Can't use floating point insn in this section"));
10015 /* Set the argument to the current address in the
10017 offset_expr
.X_op
= O_symbol
;
10018 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
10019 offset_expr
.X_add_number
= 0;
10021 /* Put the floating point number into the section. */
10022 p
= frag_more ((int) length
);
10023 memcpy (p
, temp
, length
);
10025 /* Switch back to the original section. */
10026 subseg_set (seg
, subseg
);
10031 case 'i': /* 16-bit unsigned immediate. */
10032 case 'j': /* 16-bit signed immediate. */
10033 *imm_reloc
= BFD_RELOC_LO16
;
10034 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
10037 offsetT minval
, maxval
;
10039 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
10040 && strcmp (insn
->name
, insn
[1].name
) == 0);
10042 /* If the expression was written as an unsigned number,
10043 only treat it as signed if there are no more
10047 && sizeof (imm_expr
.X_add_number
) <= 4
10048 && imm_expr
.X_op
== O_constant
10049 && imm_expr
.X_add_number
< 0
10050 && imm_expr
.X_unsigned
10051 && HAVE_64BIT_GPRS
)
10054 /* For compatibility with older assemblers, we accept
10055 0x8000-0xffff as signed 16-bit numbers when only
10056 signed numbers are allowed. */
10058 minval
= 0, maxval
= 0xffff;
10060 minval
= -0x8000, maxval
= 0x7fff;
10062 minval
= -0x8000, maxval
= 0xffff;
10064 if (imm_expr
.X_op
!= O_constant
10065 || imm_expr
.X_add_number
< minval
10066 || imm_expr
.X_add_number
> maxval
)
10070 if (imm_expr
.X_op
== O_constant
10071 || imm_expr
.X_op
== O_big
)
10072 as_bad (_("Expression out of range"));
10078 case 'o': /* 16-bit offset. */
10079 offset_reloc
[0] = BFD_RELOC_LO16
;
10080 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10081 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10083 /* Check whether there is only a single bracketed expression
10084 left. If so, it must be the base register and the
10085 constant must be zero. */
10086 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
10088 offset_expr
.X_op
= O_constant
;
10089 offset_expr
.X_add_number
= 0;
10093 /* If this value won't fit into a 16 bit offset, then go
10094 find a macro that will generate the 32 bit offset
10096 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
10097 && (offset_expr
.X_op
!= O_constant
10098 || offset_expr
.X_add_number
>= 0x8000
10099 || offset_expr
.X_add_number
< -0x8000))
10105 case 'p': /* PC-relative offset. */
10106 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
10107 my_getExpression (&offset_expr
, s
);
10111 case 'u': /* Upper 16 bits. */
10112 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
10113 && imm_expr
.X_op
== O_constant
10114 && (imm_expr
.X_add_number
< 0
10115 || imm_expr
.X_add_number
>= 0x10000))
10116 as_bad (_("lui expression (%lu) not in range 0..65535"),
10117 (unsigned long) imm_expr
.X_add_number
);
10121 case 'a': /* 26-bit address. */
10122 my_getExpression (&offset_expr
, s
);
10124 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
10127 case 'N': /* 3-bit branch condition code. */
10128 case 'M': /* 3-bit compare condition code. */
10130 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
10131 rtype
|= RTYPE_FCC
;
10132 if (!reg_lookup (&s
, rtype
, ®no
))
10134 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
10135 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
10136 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
10137 && (regno
& 1) != 0)
10138 as_warn (_("Condition code register should be even for %s, "
10141 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
10142 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
10143 && (regno
& 3) != 0)
10144 as_warn (_("Condition code register should be 0 or 4 for %s, "
10148 INSERT_OPERAND (BCC
, *ip
, regno
);
10150 INSERT_OPERAND (CCC
, *ip
, regno
);
10154 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
10165 while (ISDIGIT (*s
));
10168 c
= 8; /* Invalid sel value. */
10171 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10172 ip
->insn_opcode
|= c
;
10176 /* Must be at least one digit. */
10177 my_getExpression (&imm_expr
, s
);
10178 check_absolute_expr (ip
, &imm_expr
);
10180 if ((unsigned long) imm_expr
.X_add_number
10181 > (unsigned long) OP_MASK_VECBYTE
)
10183 as_bad (_("bad byte vector index (%ld)"),
10184 (long) imm_expr
.X_add_number
);
10185 imm_expr
.X_add_number
= 0;
10188 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
10189 imm_expr
.X_op
= O_absent
;
10194 my_getExpression (&imm_expr
, s
);
10195 check_absolute_expr (ip
, &imm_expr
);
10197 if ((unsigned long) imm_expr
.X_add_number
10198 > (unsigned long) OP_MASK_VECALIGN
)
10200 as_bad (_("bad byte vector index (%ld)"),
10201 (long) imm_expr
.X_add_number
);
10202 imm_expr
.X_add_number
= 0;
10205 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
10206 imm_expr
.X_op
= O_absent
;
10211 as_bad (_("Bad char = '%c'\n"), *args
);
10216 /* Args don't match. */
10217 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
10218 !strcmp (insn
->name
, insn
[1].name
))
10222 insn_error
= _("Illegal operands");
10226 *(--argsStart
) = save_c
;
10227 insn_error
= _("Illegal operands");
10232 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10234 /* This routine assembles an instruction into its binary format when
10235 assembling for the mips16. As a side effect, it sets one of the
10236 global variables imm_reloc or offset_reloc to the type of
10237 relocation to do if one of the operands is an address expression.
10238 It also sets mips16_small and mips16_ext if the user explicitly
10239 requested a small or extended instruction. */
10242 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
10246 struct mips_opcode
*insn
;
10248 unsigned int regno
;
10249 unsigned int lastregno
= 0;
10255 mips16_small
= FALSE
;
10256 mips16_ext
= FALSE
;
10258 for (s
= str
; ISLOWER (*s
); ++s
)
10270 if (s
[1] == 't' && s
[2] == ' ')
10273 mips16_small
= TRUE
;
10277 else if (s
[1] == 'e' && s
[2] == ' ')
10284 /* Fall through. */
10286 insn_error
= _("unknown opcode");
10290 if (mips_opts
.noautoextend
&& ! mips16_ext
)
10291 mips16_small
= TRUE
;
10293 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
10295 insn_error
= _("unrecognized opcode");
10304 gas_assert (strcmp (insn
->name
, str
) == 0);
10306 ok
= is_opcode_valid_16 (insn
);
10309 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10310 && strcmp (insn
->name
, insn
[1].name
) == 0)
10319 static char buf
[100];
10321 _("opcode not supported on this processor: %s (%s)"),
10322 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10323 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10330 create_insn (ip
, insn
);
10331 imm_expr
.X_op
= O_absent
;
10332 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10333 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10334 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10335 imm2_expr
.X_op
= O_absent
;
10336 offset_expr
.X_op
= O_absent
;
10337 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10338 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10339 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10340 for (args
= insn
->args
; 1; ++args
)
10347 /* In this switch statement we call break if we did not find
10348 a match, continue if we did find a match, or return if we
10357 /* Stuff the immediate value in now, if we can. */
10358 if (imm_expr
.X_op
== O_constant
10359 && *imm_reloc
> BFD_RELOC_UNUSED
10360 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
10361 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
10362 && insn
->pinfo
!= INSN_MACRO
)
10366 switch (*offset_reloc
)
10368 case BFD_RELOC_MIPS16_HI16_S
:
10369 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10372 case BFD_RELOC_MIPS16_HI16
:
10373 tmp
= imm_expr
.X_add_number
>> 16;
10376 case BFD_RELOC_MIPS16_LO16
:
10377 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10381 case BFD_RELOC_UNUSED
:
10382 tmp
= imm_expr
.X_add_number
;
10388 *offset_reloc
= BFD_RELOC_UNUSED
;
10390 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10391 tmp
, TRUE
, mips16_small
,
10392 mips16_ext
, &ip
->insn_opcode
,
10393 &ip
->use_extend
, &ip
->extend
);
10394 imm_expr
.X_op
= O_absent
;
10395 *imm_reloc
= BFD_RELOC_UNUSED
;
10409 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10412 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10428 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10430 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10434 /* Fall through. */
10445 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10447 if (c
== 'v' || c
== 'w')
10450 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10452 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10463 if (c
== 'v' || c
== 'w')
10465 regno
= mips16_to_32_reg_map
[lastregno
];
10479 regno
= mips32_to_16_reg_map
[regno
];
10484 regno
= ILLEGAL_REG
;
10489 regno
= ILLEGAL_REG
;
10494 regno
= ILLEGAL_REG
;
10499 if (regno
== AT
&& mips_opts
.at
)
10501 if (mips_opts
.at
== ATREG
)
10502 as_warn (_("used $at without \".set noat\""));
10504 as_warn (_("used $%u with \".set at=$%u\""),
10505 regno
, mips_opts
.at
);
10513 if (regno
== ILLEGAL_REG
)
10520 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10524 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10527 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10530 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10536 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10539 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10540 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10550 if (strncmp (s
, "$pc", 3) == 0)
10567 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10570 if (imm_expr
.X_op
!= O_constant
)
10573 ip
->use_extend
= TRUE
;
10578 /* We need to relax this instruction. */
10579 *offset_reloc
= *imm_reloc
;
10580 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10585 *imm_reloc
= BFD_RELOC_UNUSED
;
10586 /* Fall through. */
10593 my_getExpression (&imm_expr
, s
);
10594 if (imm_expr
.X_op
== O_register
)
10596 /* What we thought was an expression turned out to
10599 if (s
[0] == '(' && args
[1] == '(')
10601 /* It looks like the expression was omitted
10602 before a register indirection, which means
10603 that the expression is implicitly zero. We
10604 still set up imm_expr, so that we handle
10605 explicit extensions correctly. */
10606 imm_expr
.X_op
= O_constant
;
10607 imm_expr
.X_add_number
= 0;
10608 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10615 /* We need to relax this instruction. */
10616 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10625 /* We use offset_reloc rather than imm_reloc for the PC
10626 relative operands. This lets macros with both
10627 immediate and address operands work correctly. */
10628 my_getExpression (&offset_expr
, s
);
10630 if (offset_expr
.X_op
== O_register
)
10633 /* We need to relax this instruction. */
10634 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10638 case '6': /* break code */
10639 my_getExpression (&imm_expr
, s
);
10640 check_absolute_expr (ip
, &imm_expr
);
10641 if ((unsigned long) imm_expr
.X_add_number
> 63)
10642 as_warn (_("Invalid value for `%s' (%lu)"),
10644 (unsigned long) imm_expr
.X_add_number
);
10645 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10646 imm_expr
.X_op
= O_absent
;
10650 case 'a': /* 26 bit address */
10651 my_getExpression (&offset_expr
, s
);
10653 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10654 ip
->insn_opcode
<<= 16;
10657 case 'l': /* register list for entry macro */
10658 case 'L': /* register list for exit macro */
10668 unsigned int freg
, reg1
, reg2
;
10670 while (*s
== ' ' || *s
== ',')
10672 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10674 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10678 as_bad (_("can't parse register list"));
10688 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10689 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10691 as_bad (_("invalid register list"));
10695 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10697 mask
&= ~ (7 << 3);
10700 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10702 mask
&= ~ (7 << 3);
10705 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10706 mask
|= (reg2
- 3) << 3;
10707 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10708 mask
|= (reg2
- 15) << 1;
10709 else if (reg1
== RA
&& reg2
== RA
)
10713 as_bad (_("invalid register list"));
10717 /* The mask is filled in in the opcode table for the
10718 benefit of the disassembler. We remove it before
10719 applying the actual mask. */
10720 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10721 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10725 case 'm': /* Register list for save insn. */
10726 case 'M': /* Register list for restore insn. */
10729 int framesz
= 0, seen_framesz
= 0;
10730 int nargs
= 0, statics
= 0, sregs
= 0;
10734 unsigned int reg1
, reg2
;
10736 SKIP_SPACE_TABS (s
);
10739 SKIP_SPACE_TABS (s
);
10741 my_getExpression (&imm_expr
, s
);
10742 if (imm_expr
.X_op
== O_constant
)
10744 /* Handle the frame size. */
10747 as_bad (_("more than one frame size in list"));
10751 framesz
= imm_expr
.X_add_number
;
10752 imm_expr
.X_op
= O_absent
;
10757 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10759 as_bad (_("can't parse register list"));
10771 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10774 as_bad (_("can't parse register list"));
10779 while (reg1
<= reg2
)
10781 if (reg1
>= 4 && reg1
<= 7)
10785 nargs
|= 1 << (reg1
- 4);
10787 /* statics $a0-$a3 */
10788 statics
|= 1 << (reg1
- 4);
10790 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10793 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10795 else if (reg1
== 31)
10797 /* Add $ra to insn. */
10802 as_bad (_("unexpected register in list"));
10810 /* Encode args/statics combination. */
10811 if (nargs
& statics
)
10812 as_bad (_("arg/static registers overlap"));
10813 else if (nargs
== 0xf)
10814 /* All $a0-$a3 are args. */
10815 opcode
|= MIPS16_ALL_ARGS
<< 16;
10816 else if (statics
== 0xf)
10817 /* All $a0-$a3 are statics. */
10818 opcode
|= MIPS16_ALL_STATICS
<< 16;
10821 int narg
= 0, nstat
= 0;
10823 /* Count arg registers. */
10824 while (nargs
& 0x1)
10830 as_bad (_("invalid arg register list"));
10832 /* Count static registers. */
10833 while (statics
& 0x8)
10835 statics
= (statics
<< 1) & 0xf;
10839 as_bad (_("invalid static register list"));
10841 /* Encode args/statics. */
10842 opcode
|= ((narg
<< 2) | nstat
) << 16;
10845 /* Encode $s0/$s1. */
10846 if (sregs
& (1 << 0)) /* $s0 */
10848 if (sregs
& (1 << 1)) /* $s1 */
10854 /* Count regs $s2-$s8. */
10862 as_bad (_("invalid static register list"));
10863 /* Encode $s2-$s8. */
10864 opcode
|= nsreg
<< 24;
10867 /* Encode frame size. */
10869 as_bad (_("missing frame size"));
10870 else if ((framesz
& 7) != 0 || framesz
< 0
10871 || framesz
> 0xff * 8)
10872 as_bad (_("invalid frame size"));
10873 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10876 opcode
|= (((framesz
& 0xf0) << 16)
10877 | (framesz
& 0x0f));
10880 /* Finally build the instruction. */
10881 if ((opcode
>> 16) != 0 || framesz
== 0)
10883 ip
->use_extend
= TRUE
;
10884 ip
->extend
= opcode
>> 16;
10886 ip
->insn_opcode
|= opcode
& 0x7f;
10890 case 'e': /* extend code */
10891 my_getExpression (&imm_expr
, s
);
10892 check_absolute_expr (ip
, &imm_expr
);
10893 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10895 as_warn (_("Invalid value for `%s' (%lu)"),
10897 (unsigned long) imm_expr
.X_add_number
);
10898 imm_expr
.X_add_number
&= 0x7ff;
10900 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10901 imm_expr
.X_op
= O_absent
;
10911 /* Args don't match. */
10912 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10913 strcmp (insn
->name
, insn
[1].name
) == 0)
10920 insn_error
= _("illegal operands");
10926 /* This structure holds information we know about a mips16 immediate
10929 struct mips16_immed_operand
10931 /* The type code used in the argument string in the opcode table. */
10933 /* The number of bits in the short form of the opcode. */
10935 /* The number of bits in the extended form of the opcode. */
10937 /* The amount by which the short form is shifted when it is used;
10938 for example, the sw instruction has a shift count of 2. */
10940 /* The amount by which the short form is shifted when it is stored
10941 into the instruction code. */
10943 /* Non-zero if the short form is unsigned. */
10945 /* Non-zero if the extended form is unsigned. */
10947 /* Non-zero if the value is PC relative. */
10951 /* The mips16 immediate operand types. */
10953 static const struct mips16_immed_operand mips16_immed_operands
[] =
10955 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10956 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10957 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10958 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10959 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10960 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10961 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10962 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10963 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10964 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10965 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10966 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10967 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10968 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10969 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10970 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10971 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10972 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10973 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10974 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10975 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10978 #define MIPS16_NUM_IMMED \
10979 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10981 /* Handle a mips16 instruction with an immediate value. This or's the
10982 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10983 whether an extended value is needed; if one is needed, it sets
10984 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10985 If SMALL is true, an unextended opcode was explicitly requested.
10986 If EXT is true, an extended opcode was explicitly requested. If
10987 WARN is true, warn if EXT does not match reality. */
10990 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10991 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10992 unsigned long *insn
, bfd_boolean
*use_extend
,
10993 unsigned short *extend
)
10995 const struct mips16_immed_operand
*op
;
10996 int mintiny
, maxtiny
;
10997 bfd_boolean needext
;
10999 op
= mips16_immed_operands
;
11000 while (op
->type
!= type
)
11003 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11008 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11011 maxtiny
= 1 << op
->nbits
;
11016 maxtiny
= (1 << op
->nbits
) - 1;
11021 mintiny
= - (1 << (op
->nbits
- 1));
11022 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11025 /* Branch offsets have an implicit 0 in the lowest bit. */
11026 if (type
== 'p' || type
== 'q')
11029 if ((val
& ((1 << op
->shift
) - 1)) != 0
11030 || val
< (mintiny
<< op
->shift
)
11031 || val
> (maxtiny
<< op
->shift
))
11036 if (warn
&& ext
&& ! needext
)
11037 as_warn_where (file
, line
,
11038 _("extended operand requested but not required"));
11039 if (small
&& needext
)
11040 as_bad_where (file
, line
, _("invalid unextended operand value"));
11042 if (small
|| (! ext
&& ! needext
))
11046 *use_extend
= FALSE
;
11047 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
11048 insnval
<<= op
->op_shift
;
11053 long minext
, maxext
;
11059 maxext
= (1 << op
->extbits
) - 1;
11063 minext
= - (1 << (op
->extbits
- 1));
11064 maxext
= (1 << (op
->extbits
- 1)) - 1;
11066 if (val
< minext
|| val
> maxext
)
11067 as_bad_where (file
, line
,
11068 _("operand value out of range for instruction"));
11070 *use_extend
= TRUE
;
11071 if (op
->extbits
== 16)
11073 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
11076 else if (op
->extbits
== 15)
11078 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
11083 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
11087 *extend
= (unsigned short) extval
;
11092 struct percent_op_match
11095 bfd_reloc_code_real_type reloc
;
11098 static const struct percent_op_match mips_percent_op
[] =
11100 {"%lo", BFD_RELOC_LO16
},
11102 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
11103 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
11104 {"%call16", BFD_RELOC_MIPS_CALL16
},
11105 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
11106 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
11107 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
11108 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
11109 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
11110 {"%got", BFD_RELOC_MIPS_GOT16
},
11111 {"%gp_rel", BFD_RELOC_GPREL16
},
11112 {"%half", BFD_RELOC_16
},
11113 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
11114 {"%higher", BFD_RELOC_MIPS_HIGHER
},
11115 {"%neg", BFD_RELOC_MIPS_SUB
},
11116 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
11117 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
11118 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
11119 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
11120 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
11121 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
11122 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
11124 {"%hi", BFD_RELOC_HI16_S
}
11127 static const struct percent_op_match mips16_percent_op
[] =
11129 {"%lo", BFD_RELOC_MIPS16_LO16
},
11130 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
11131 {"%got", BFD_RELOC_MIPS16_GOT16
},
11132 {"%call16", BFD_RELOC_MIPS16_CALL16
},
11133 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
11137 /* Return true if *STR points to a relocation operator. When returning true,
11138 move *STR over the operator and store its relocation code in *RELOC.
11139 Leave both *STR and *RELOC alone when returning false. */
11142 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
11144 const struct percent_op_match
*percent_op
;
11147 if (mips_opts
.mips16
)
11149 percent_op
= mips16_percent_op
;
11150 limit
= ARRAY_SIZE (mips16_percent_op
);
11154 percent_op
= mips_percent_op
;
11155 limit
= ARRAY_SIZE (mips_percent_op
);
11158 for (i
= 0; i
< limit
; i
++)
11159 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
11161 int len
= strlen (percent_op
[i
].str
);
11163 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
11166 *str
+= strlen (percent_op
[i
].str
);
11167 *reloc
= percent_op
[i
].reloc
;
11169 /* Check whether the output BFD supports this relocation.
11170 If not, issue an error and fall back on something safe. */
11171 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
11173 as_bad (_("relocation %s isn't supported by the current ABI"),
11174 percent_op
[i
].str
);
11175 *reloc
= BFD_RELOC_UNUSED
;
11183 /* Parse string STR as a 16-bit relocatable operand. Store the
11184 expression in *EP and the relocations in the array starting
11185 at RELOC. Return the number of relocation operators used.
11187 On exit, EXPR_END points to the first character after the expression. */
11190 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
11193 bfd_reloc_code_real_type reversed_reloc
[3];
11194 size_t reloc_index
, i
;
11195 int crux_depth
, str_depth
;
11198 /* Search for the start of the main expression, recoding relocations
11199 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11200 of the main expression and with CRUX_DEPTH containing the number
11201 of open brackets at that point. */
11208 crux_depth
= str_depth
;
11210 /* Skip over whitespace and brackets, keeping count of the number
11212 while (*str
== ' ' || *str
== '\t' || *str
== '(')
11217 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
11218 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
11220 my_getExpression (ep
, crux
);
11223 /* Match every open bracket. */
11224 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
11228 if (crux_depth
> 0)
11229 as_bad (_("unclosed '('"));
11233 if (reloc_index
!= 0)
11235 prev_reloc_op_frag
= frag_now
;
11236 for (i
= 0; i
< reloc_index
; i
++)
11237 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
11240 return reloc_index
;
11244 my_getExpression (expressionS
*ep
, char *str
)
11248 save_in
= input_line_pointer
;
11249 input_line_pointer
= str
;
11251 expr_end
= input_line_pointer
;
11252 input_line_pointer
= save_in
;
11256 md_atof (int type
, char *litP
, int *sizeP
)
11258 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
11262 md_number_to_chars (char *buf
, valueT val
, int n
)
11264 if (target_big_endian
)
11265 number_to_chars_bigendian (buf
, val
, n
);
11267 number_to_chars_littleendian (buf
, val
, n
);
11271 static int support_64bit_objects(void)
11273 const char **list
, **l
;
11276 list
= bfd_target_list ();
11277 for (l
= list
; *l
!= NULL
; l
++)
11278 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
11279 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
11281 yes
= (*l
!= NULL
);
11285 #endif /* OBJ_ELF */
11287 const char *md_shortopts
= "O::g::G:";
11291 OPTION_MARCH
= OPTION_MD_BASE
,
11313 OPTION_NO_SMARTMIPS
,
11316 OPTION_COMPAT_ARCH_BASE
,
11325 OPTION_M7000_HILO_FIX
,
11326 OPTION_MNO_7000_HILO_FIX
,
11329 OPTION_FIX_LOONGSON2F_JUMP
,
11330 OPTION_NO_FIX_LOONGSON2F_JUMP
,
11331 OPTION_FIX_LOONGSON2F_NOP
,
11332 OPTION_NO_FIX_LOONGSON2F_NOP
,
11334 OPTION_NO_FIX_VR4120
,
11336 OPTION_NO_FIX_VR4130
,
11337 OPTION_FIX_CN63XXP1
,
11338 OPTION_NO_FIX_CN63XXP1
,
11345 OPTION_CONSTRUCT_FLOATS
,
11346 OPTION_NO_CONSTRUCT_FLOATS
,
11349 OPTION_RELAX_BRANCH
,
11350 OPTION_NO_RELAX_BRANCH
,
11357 OPTION_SINGLE_FLOAT
,
11358 OPTION_DOUBLE_FLOAT
,
11361 OPTION_CALL_SHARED
,
11362 OPTION_CALL_NONPIC
,
11372 OPTION_MVXWORKS_PIC
,
11373 #endif /* OBJ_ELF */
11377 struct option md_longopts
[] =
11379 /* Options which specify architecture. */
11380 {"march", required_argument
, NULL
, OPTION_MARCH
},
11381 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11382 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11383 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11384 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11385 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11386 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11387 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11388 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11389 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11390 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11391 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11393 /* Options which specify Application Specific Extensions (ASEs). */
11394 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11395 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11396 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11397 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11398 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11399 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11400 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11401 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11402 {"mmt", no_argument
, NULL
, OPTION_MT
},
11403 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11404 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11405 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11406 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11407 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11409 /* Old-style architecture options. Don't add more of these. */
11410 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11411 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11412 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11413 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11414 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11415 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11416 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11417 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11419 /* Options which enable bug fixes. */
11420 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11421 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11422 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11423 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
11424 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
11425 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
11426 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
11427 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11428 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11429 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11430 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11431 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
11432 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
11433 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
11434 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
11436 /* Miscellaneous options. */
11437 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11438 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11439 {"break", no_argument
, NULL
, OPTION_BREAK
},
11440 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11441 {"EB", no_argument
, NULL
, OPTION_EB
},
11442 {"EL", no_argument
, NULL
, OPTION_EL
},
11443 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11444 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11445 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11446 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11447 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11448 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11449 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11450 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11451 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11452 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11453 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11454 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11455 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11456 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11457 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11458 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11460 /* Strictly speaking this next option is ELF specific,
11461 but we allow it for other ports as well in order to
11462 make testing easier. */
11463 {"32", no_argument
, NULL
, OPTION_32
},
11465 /* ELF-specific options. */
11467 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11468 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11469 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
11470 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11471 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11472 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11473 {"n32", no_argument
, NULL
, OPTION_N32
},
11474 {"64", no_argument
, NULL
, OPTION_64
},
11475 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11476 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11477 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11478 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11479 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11480 #endif /* OBJ_ELF */
11482 {NULL
, no_argument
, NULL
, 0}
11484 size_t md_longopts_size
= sizeof (md_longopts
);
11486 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11487 NEW_VALUE. Warn if another value was already specified. Note:
11488 we have to defer parsing the -march and -mtune arguments in order
11489 to handle 'from-abi' correctly, since the ABI might be specified
11490 in a later argument. */
11493 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11495 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11496 as_warn (_("A different %s was already specified, is now %s"),
11497 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11500 *string_ptr
= new_value
;
11504 md_parse_option (int c
, char *arg
)
11508 case OPTION_CONSTRUCT_FLOATS
:
11509 mips_disable_float_construction
= 0;
11512 case OPTION_NO_CONSTRUCT_FLOATS
:
11513 mips_disable_float_construction
= 1;
11525 target_big_endian
= 1;
11529 target_big_endian
= 0;
11535 else if (arg
[0] == '0')
11537 else if (arg
[0] == '1')
11547 mips_debug
= atoi (arg
);
11551 file_mips_isa
= ISA_MIPS1
;
11555 file_mips_isa
= ISA_MIPS2
;
11559 file_mips_isa
= ISA_MIPS3
;
11563 file_mips_isa
= ISA_MIPS4
;
11567 file_mips_isa
= ISA_MIPS5
;
11570 case OPTION_MIPS32
:
11571 file_mips_isa
= ISA_MIPS32
;
11574 case OPTION_MIPS32R2
:
11575 file_mips_isa
= ISA_MIPS32R2
;
11578 case OPTION_MIPS64R2
:
11579 file_mips_isa
= ISA_MIPS64R2
;
11582 case OPTION_MIPS64
:
11583 file_mips_isa
= ISA_MIPS64
;
11587 mips_set_option_string (&mips_tune_string
, arg
);
11591 mips_set_option_string (&mips_arch_string
, arg
);
11595 mips_set_option_string (&mips_arch_string
, "4650");
11596 mips_set_option_string (&mips_tune_string
, "4650");
11599 case OPTION_NO_M4650
:
11603 mips_set_option_string (&mips_arch_string
, "4010");
11604 mips_set_option_string (&mips_tune_string
, "4010");
11607 case OPTION_NO_M4010
:
11611 mips_set_option_string (&mips_arch_string
, "4100");
11612 mips_set_option_string (&mips_tune_string
, "4100");
11615 case OPTION_NO_M4100
:
11619 mips_set_option_string (&mips_arch_string
, "3900");
11620 mips_set_option_string (&mips_tune_string
, "3900");
11623 case OPTION_NO_M3900
:
11627 mips_opts
.ase_mdmx
= 1;
11630 case OPTION_NO_MDMX
:
11631 mips_opts
.ase_mdmx
= 0;
11635 mips_opts
.ase_dsp
= 1;
11636 mips_opts
.ase_dspr2
= 0;
11639 case OPTION_NO_DSP
:
11640 mips_opts
.ase_dsp
= 0;
11641 mips_opts
.ase_dspr2
= 0;
11645 mips_opts
.ase_dspr2
= 1;
11646 mips_opts
.ase_dsp
= 1;
11649 case OPTION_NO_DSPR2
:
11650 mips_opts
.ase_dspr2
= 0;
11651 mips_opts
.ase_dsp
= 0;
11655 mips_opts
.ase_mt
= 1;
11659 mips_opts
.ase_mt
= 0;
11662 case OPTION_MIPS16
:
11663 mips_opts
.mips16
= 1;
11664 mips_no_prev_insn ();
11667 case OPTION_NO_MIPS16
:
11668 mips_opts
.mips16
= 0;
11669 mips_no_prev_insn ();
11672 case OPTION_MIPS3D
:
11673 mips_opts
.ase_mips3d
= 1;
11676 case OPTION_NO_MIPS3D
:
11677 mips_opts
.ase_mips3d
= 0;
11680 case OPTION_SMARTMIPS
:
11681 mips_opts
.ase_smartmips
= 1;
11684 case OPTION_NO_SMARTMIPS
:
11685 mips_opts
.ase_smartmips
= 0;
11688 case OPTION_FIX_24K
:
11692 case OPTION_NO_FIX_24K
:
11696 case OPTION_FIX_LOONGSON2F_JUMP
:
11697 mips_fix_loongson2f_jump
= TRUE
;
11700 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
11701 mips_fix_loongson2f_jump
= FALSE
;
11704 case OPTION_FIX_LOONGSON2F_NOP
:
11705 mips_fix_loongson2f_nop
= TRUE
;
11708 case OPTION_NO_FIX_LOONGSON2F_NOP
:
11709 mips_fix_loongson2f_nop
= FALSE
;
11712 case OPTION_FIX_VR4120
:
11713 mips_fix_vr4120
= 1;
11716 case OPTION_NO_FIX_VR4120
:
11717 mips_fix_vr4120
= 0;
11720 case OPTION_FIX_VR4130
:
11721 mips_fix_vr4130
= 1;
11724 case OPTION_NO_FIX_VR4130
:
11725 mips_fix_vr4130
= 0;
11728 case OPTION_FIX_CN63XXP1
:
11729 mips_fix_cn63xxp1
= TRUE
;
11732 case OPTION_NO_FIX_CN63XXP1
:
11733 mips_fix_cn63xxp1
= FALSE
;
11736 case OPTION_RELAX_BRANCH
:
11737 mips_relax_branch
= 1;
11740 case OPTION_NO_RELAX_BRANCH
:
11741 mips_relax_branch
= 0;
11744 case OPTION_MSHARED
:
11745 mips_in_shared
= TRUE
;
11748 case OPTION_MNO_SHARED
:
11749 mips_in_shared
= FALSE
;
11752 case OPTION_MSYM32
:
11753 mips_opts
.sym32
= TRUE
;
11756 case OPTION_MNO_SYM32
:
11757 mips_opts
.sym32
= FALSE
;
11761 /* When generating ELF code, we permit -KPIC and -call_shared to
11762 select SVR4_PIC, and -non_shared to select no PIC. This is
11763 intended to be compatible with Irix 5. */
11764 case OPTION_CALL_SHARED
:
11767 as_bad (_("-call_shared is supported only for ELF format"));
11770 mips_pic
= SVR4_PIC
;
11771 mips_abicalls
= TRUE
;
11774 case OPTION_CALL_NONPIC
:
11777 as_bad (_("-call_nonpic is supported only for ELF format"));
11781 mips_abicalls
= TRUE
;
11784 case OPTION_NON_SHARED
:
11787 as_bad (_("-non_shared is supported only for ELF format"));
11791 mips_abicalls
= FALSE
;
11794 /* The -xgot option tells the assembler to use 32 bit offsets
11795 when accessing the got in SVR4_PIC mode. It is for Irix
11800 #endif /* OBJ_ELF */
11803 g_switch_value
= atoi (arg
);
11807 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11811 mips_abi
= O32_ABI
;
11812 /* We silently ignore -32 for non-ELF targets. This greatly
11813 simplifies the construction of the MIPS GAS test cases. */
11820 as_bad (_("-n32 is supported for ELF format only"));
11823 mips_abi
= N32_ABI
;
11829 as_bad (_("-64 is supported for ELF format only"));
11832 mips_abi
= N64_ABI
;
11833 if (!support_64bit_objects())
11834 as_fatal (_("No compiled in support for 64 bit object file format"));
11836 #endif /* OBJ_ELF */
11839 file_mips_gp32
= 1;
11843 file_mips_gp32
= 0;
11847 file_mips_fp32
= 1;
11851 file_mips_fp32
= 0;
11854 case OPTION_SINGLE_FLOAT
:
11855 file_mips_single_float
= 1;
11858 case OPTION_DOUBLE_FLOAT
:
11859 file_mips_single_float
= 0;
11862 case OPTION_SOFT_FLOAT
:
11863 file_mips_soft_float
= 1;
11866 case OPTION_HARD_FLOAT
:
11867 file_mips_soft_float
= 0;
11874 as_bad (_("-mabi is supported for ELF format only"));
11877 if (strcmp (arg
, "32") == 0)
11878 mips_abi
= O32_ABI
;
11879 else if (strcmp (arg
, "o64") == 0)
11880 mips_abi
= O64_ABI
;
11881 else if (strcmp (arg
, "n32") == 0)
11882 mips_abi
= N32_ABI
;
11883 else if (strcmp (arg
, "64") == 0)
11885 mips_abi
= N64_ABI
;
11886 if (! support_64bit_objects())
11887 as_fatal (_("No compiled in support for 64 bit object file "
11890 else if (strcmp (arg
, "eabi") == 0)
11891 mips_abi
= EABI_ABI
;
11894 as_fatal (_("invalid abi -mabi=%s"), arg
);
11898 #endif /* OBJ_ELF */
11900 case OPTION_M7000_HILO_FIX
:
11901 mips_7000_hilo_fix
= TRUE
;
11904 case OPTION_MNO_7000_HILO_FIX
:
11905 mips_7000_hilo_fix
= FALSE
;
11909 case OPTION_MDEBUG
:
11910 mips_flag_mdebug
= TRUE
;
11913 case OPTION_NO_MDEBUG
:
11914 mips_flag_mdebug
= FALSE
;
11918 mips_flag_pdr
= TRUE
;
11921 case OPTION_NO_PDR
:
11922 mips_flag_pdr
= FALSE
;
11925 case OPTION_MVXWORKS_PIC
:
11926 mips_pic
= VXWORKS_PIC
;
11928 #endif /* OBJ_ELF */
11934 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
11939 /* Set up globals to generate code for the ISA or processor
11940 described by INFO. */
11943 mips_set_architecture (const struct mips_cpu_info
*info
)
11947 file_mips_arch
= info
->cpu
;
11948 mips_opts
.arch
= info
->cpu
;
11949 mips_opts
.isa
= info
->isa
;
11954 /* Likewise for tuning. */
11957 mips_set_tune (const struct mips_cpu_info
*info
)
11960 mips_tune
= info
->cpu
;
11965 mips_after_parse_args (void)
11967 const struct mips_cpu_info
*arch_info
= 0;
11968 const struct mips_cpu_info
*tune_info
= 0;
11970 /* GP relative stuff not working for PE */
11971 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11973 if (g_switch_seen
&& g_switch_value
!= 0)
11974 as_bad (_("-G not supported in this configuration."));
11975 g_switch_value
= 0;
11978 if (mips_abi
== NO_ABI
)
11979 mips_abi
= MIPS_DEFAULT_ABI
;
11981 /* The following code determines the architecture and register size.
11982 Similar code was added to GCC 3.3 (see override_options() in
11983 config/mips/mips.c). The GAS and GCC code should be kept in sync
11984 as much as possible. */
11986 if (mips_arch_string
!= 0)
11987 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11989 if (file_mips_isa
!= ISA_UNKNOWN
)
11991 /* Handle -mipsN. At this point, file_mips_isa contains the
11992 ISA level specified by -mipsN, while arch_info->isa contains
11993 the -march selection (if any). */
11994 if (arch_info
!= 0)
11996 /* -march takes precedence over -mipsN, since it is more descriptive.
11997 There's no harm in specifying both as long as the ISA levels
11999 if (file_mips_isa
!= arch_info
->isa
)
12000 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12001 mips_cpu_info_from_isa (file_mips_isa
)->name
,
12002 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
12005 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
12008 if (arch_info
== 0)
12009 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
12011 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
12012 as_bad (_("-march=%s is not compatible with the selected ABI"),
12015 mips_set_architecture (arch_info
);
12017 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12018 if (mips_tune_string
!= 0)
12019 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
12021 if (tune_info
== 0)
12022 mips_set_tune (arch_info
);
12024 mips_set_tune (tune_info
);
12026 if (file_mips_gp32
>= 0)
12028 /* The user specified the size of the integer registers. Make sure
12029 it agrees with the ABI and ISA. */
12030 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12031 as_bad (_("-mgp64 used with a 32-bit processor"));
12032 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
12033 as_bad (_("-mgp32 used with a 64-bit ABI"));
12034 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
12035 as_bad (_("-mgp64 used with a 32-bit ABI"));
12039 /* Infer the integer register size from the ABI and processor.
12040 Restrict ourselves to 32-bit registers if that's all the
12041 processor has, or if the ABI cannot handle 64-bit registers. */
12042 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
12043 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
12046 switch (file_mips_fp32
)
12050 /* No user specified float register size.
12051 ??? GAS treats single-float processors as though they had 64-bit
12052 float registers (although it complains when double-precision
12053 instructions are used). As things stand, saying they have 32-bit
12054 registers would lead to spurious "register must be even" messages.
12055 So here we assume float registers are never smaller than the
12057 if (file_mips_gp32
== 0)
12058 /* 64-bit integer registers implies 64-bit float registers. */
12059 file_mips_fp32
= 0;
12060 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
12061 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12062 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12063 file_mips_fp32
= 0;
12065 /* 32-bit float registers. */
12066 file_mips_fp32
= 1;
12069 /* The user specified the size of the float registers. Check if it
12070 agrees with the ABI and ISA. */
12072 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12073 as_bad (_("-mfp64 used with a 32-bit fpu"));
12074 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
12075 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
12076 as_warn (_("-mfp64 used with a 32-bit ABI"));
12079 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
12080 as_warn (_("-mfp32 used with a 64-bit ABI"));
12084 /* End of GCC-shared inference code. */
12086 /* This flag is set when we have a 64-bit capable CPU but use only
12087 32-bit wide registers. Note that EABI does not use it. */
12088 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
12089 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
12090 || mips_abi
== O32_ABI
))
12091 mips_32bitmode
= 1;
12093 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
12094 as_bad (_("trap exception not supported at ISA 1"));
12096 /* If the selected architecture includes support for ASEs, enable
12097 generation of code for them. */
12098 if (mips_opts
.mips16
== -1)
12099 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
12100 if (mips_opts
.ase_mips3d
== -1)
12101 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
12102 && file_mips_fp32
== 0) ? 1 : 0;
12103 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
12104 as_bad (_("-mfp32 used with -mips3d"));
12106 if (mips_opts
.ase_mdmx
== -1)
12107 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
12108 && file_mips_fp32
== 0) ? 1 : 0;
12109 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
12110 as_bad (_("-mfp32 used with -mdmx"));
12112 if (mips_opts
.ase_smartmips
== -1)
12113 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
12114 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
12115 as_warn (_("%s ISA does not support SmartMIPS"),
12116 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12118 if (mips_opts
.ase_dsp
== -1)
12119 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
12120 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
12121 as_warn (_("%s ISA does not support DSP ASE"),
12122 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12124 if (mips_opts
.ase_dspr2
== -1)
12126 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
12127 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
12129 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
12130 as_warn (_("%s ISA does not support DSP R2 ASE"),
12131 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12133 if (mips_opts
.ase_mt
== -1)
12134 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
12135 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
12136 as_warn (_("%s ISA does not support MT ASE"),
12137 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12139 file_mips_isa
= mips_opts
.isa
;
12140 file_ase_mips3d
= mips_opts
.ase_mips3d
;
12141 file_ase_mdmx
= mips_opts
.ase_mdmx
;
12142 file_ase_smartmips
= mips_opts
.ase_smartmips
;
12143 file_ase_dsp
= mips_opts
.ase_dsp
;
12144 file_ase_dspr2
= mips_opts
.ase_dspr2
;
12145 file_ase_mt
= mips_opts
.ase_mt
;
12146 mips_opts
.gp32
= file_mips_gp32
;
12147 mips_opts
.fp32
= file_mips_fp32
;
12148 mips_opts
.soft_float
= file_mips_soft_float
;
12149 mips_opts
.single_float
= file_mips_single_float
;
12151 if (mips_flag_mdebug
< 0)
12153 #ifdef OBJ_MAYBE_ECOFF
12154 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
12155 mips_flag_mdebug
= 1;
12157 #endif /* OBJ_MAYBE_ECOFF */
12158 mips_flag_mdebug
= 0;
12163 mips_init_after_args (void)
12165 /* initialize opcodes */
12166 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
12167 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
12171 md_pcrel_from (fixS
*fixP
)
12173 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12174 switch (fixP
->fx_r_type
)
12176 case BFD_RELOC_16_PCREL_S2
:
12177 case BFD_RELOC_MIPS_JMP
:
12178 /* Return the address of the delay slot. */
12181 /* We have no relocation type for PC relative MIPS16 instructions. */
12182 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
12183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12184 _("PC relative MIPS16 instruction references a different section"));
12189 /* This is called before the symbol table is processed. In order to
12190 work with gcc when using mips-tfile, we must keep all local labels.
12191 However, in other cases, we want to discard them. If we were
12192 called with -g, but we didn't see any debugging information, it may
12193 mean that gcc is smuggling debugging information through to
12194 mips-tfile, in which case we must generate all local labels. */
12197 mips_frob_file_before_adjust (void)
12199 #ifndef NO_ECOFF_DEBUGGING
12200 if (ECOFF_DEBUGGING
12202 && ! ecoff_debugging_seen
)
12203 flag_keep_locals
= 1;
12207 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12208 the corresponding LO16 reloc. This is called before md_apply_fix and
12209 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12210 relocation operators.
12212 For our purposes, a %lo() expression matches a %got() or %hi()
12215 (a) it refers to the same symbol; and
12216 (b) the offset applied in the %lo() expression is no lower than
12217 the offset applied in the %got() or %hi().
12219 (b) allows us to cope with code like:
12222 lh $4,%lo(foo+2)($4)
12224 ...which is legal on RELA targets, and has a well-defined behaviour
12225 if the user knows that adding 2 to "foo" will not induce a carry to
12228 When several %lo()s match a particular %got() or %hi(), we use the
12229 following rules to distinguish them:
12231 (1) %lo()s with smaller offsets are a better match than %lo()s with
12234 (2) %lo()s with no matching %got() or %hi() are better than those
12235 that already have a matching %got() or %hi().
12237 (3) later %lo()s are better than earlier %lo()s.
12239 These rules are applied in order.
12241 (1) means, among other things, that %lo()s with identical offsets are
12242 chosen if they exist.
12244 (2) means that we won't associate several high-part relocations with
12245 the same low-part relocation unless there's no alternative. Having
12246 several high parts for the same low part is a GNU extension; this rule
12247 allows careful users to avoid it.
12249 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12250 with the last high-part relocation being at the front of the list.
12251 It therefore makes sense to choose the last matching low-part
12252 relocation, all other things being equal. It's also easier
12253 to code that way. */
12256 mips_frob_file (void)
12258 struct mips_hi_fixup
*l
;
12259 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
12261 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
12263 segment_info_type
*seginfo
;
12264 bfd_boolean matched_lo_p
;
12265 fixS
**hi_pos
, **lo_pos
, **pos
;
12267 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
12269 /* If a GOT16 relocation turns out to be against a global symbol,
12270 there isn't supposed to be a matching LO. */
12271 if (got16_reloc_p (l
->fixp
->fx_r_type
)
12272 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
12275 /* Check quickly whether the next fixup happens to be a matching %lo. */
12276 if (fixup_has_matching_lo_p (l
->fixp
))
12279 seginfo
= seg_info (l
->seg
);
12281 /* Set HI_POS to the position of this relocation in the chain.
12282 Set LO_POS to the position of the chosen low-part relocation.
12283 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12284 relocation that matches an immediately-preceding high-part
12288 matched_lo_p
= FALSE
;
12289 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
12291 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
12293 if (*pos
== l
->fixp
)
12296 if ((*pos
)->fx_r_type
== looking_for_rtype
12297 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
12298 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
12300 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
12302 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
12305 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
12306 && fixup_has_matching_lo_p (*pos
));
12309 /* If we found a match, remove the high-part relocation from its
12310 current position and insert it before the low-part relocation.
12311 Make the offsets match so that fixup_has_matching_lo_p()
12314 We don't warn about unmatched high-part relocations since some
12315 versions of gcc have been known to emit dead "lui ...%hi(...)"
12317 if (lo_pos
!= NULL
)
12319 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
12320 if (l
->fixp
->fx_next
!= *lo_pos
)
12322 *hi_pos
= l
->fixp
->fx_next
;
12323 l
->fixp
->fx_next
= *lo_pos
;
12330 /* We may have combined relocations without symbols in the N32/N64 ABI.
12331 We have to prevent gas from dropping them. */
12334 mips_force_relocation (fixS
*fixp
)
12336 if (generic_force_reloc (fixp
))
12340 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
12341 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
12342 || hi16_reloc_p (fixp
->fx_r_type
)
12343 || lo16_reloc_p (fixp
->fx_r_type
)))
12349 /* Apply a fixup to the object file. */
12352 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12356 reloc_howto_type
*howto
;
12358 /* We ignore generic BFD relocations we don't know about. */
12359 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12363 gas_assert (fixP
->fx_size
== 4
12364 || fixP
->fx_r_type
== BFD_RELOC_16
12365 || fixP
->fx_r_type
== BFD_RELOC_64
12366 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12367 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12368 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12369 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12370 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12372 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12374 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12376 /* Don't treat parts of a composite relocation as done. There are two
12379 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12380 should nevertheless be emitted if the first part is.
12382 (2) In normal usage, composite relocations are never assembly-time
12383 constants. The easiest way of dealing with the pathological
12384 exceptions is to generate a relocation against STN_UNDEF and
12385 leave everything up to the linker. */
12386 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12389 switch (fixP
->fx_r_type
)
12391 case BFD_RELOC_MIPS_TLS_GD
:
12392 case BFD_RELOC_MIPS_TLS_LDM
:
12393 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12394 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12395 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12396 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12397 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12398 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12399 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12400 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12403 case BFD_RELOC_MIPS_JMP
:
12404 case BFD_RELOC_MIPS_SHIFT5
:
12405 case BFD_RELOC_MIPS_SHIFT6
:
12406 case BFD_RELOC_MIPS_GOT_DISP
:
12407 case BFD_RELOC_MIPS_GOT_PAGE
:
12408 case BFD_RELOC_MIPS_GOT_OFST
:
12409 case BFD_RELOC_MIPS_SUB
:
12410 case BFD_RELOC_MIPS_INSERT_A
:
12411 case BFD_RELOC_MIPS_INSERT_B
:
12412 case BFD_RELOC_MIPS_DELETE
:
12413 case BFD_RELOC_MIPS_HIGHEST
:
12414 case BFD_RELOC_MIPS_HIGHER
:
12415 case BFD_RELOC_MIPS_SCN_DISP
:
12416 case BFD_RELOC_MIPS_REL16
:
12417 case BFD_RELOC_MIPS_RELGOT
:
12418 case BFD_RELOC_MIPS_JALR
:
12419 case BFD_RELOC_HI16
:
12420 case BFD_RELOC_HI16_S
:
12421 case BFD_RELOC_GPREL16
:
12422 case BFD_RELOC_MIPS_LITERAL
:
12423 case BFD_RELOC_MIPS_CALL16
:
12424 case BFD_RELOC_MIPS_GOT16
:
12425 case BFD_RELOC_GPREL32
:
12426 case BFD_RELOC_MIPS_GOT_HI16
:
12427 case BFD_RELOC_MIPS_GOT_LO16
:
12428 case BFD_RELOC_MIPS_CALL_HI16
:
12429 case BFD_RELOC_MIPS_CALL_LO16
:
12430 case BFD_RELOC_MIPS16_GPREL
:
12431 case BFD_RELOC_MIPS16_GOT16
:
12432 case BFD_RELOC_MIPS16_CALL16
:
12433 case BFD_RELOC_MIPS16_HI16
:
12434 case BFD_RELOC_MIPS16_HI16_S
:
12435 case BFD_RELOC_MIPS16_JMP
:
12436 /* Nothing needed to do. The value comes from the reloc entry. */
12440 /* This is handled like BFD_RELOC_32, but we output a sign
12441 extended value if we are only 32 bits. */
12444 if (8 <= sizeof (valueT
))
12445 md_number_to_chars ((char *) buf
, *valP
, 8);
12450 if ((*valP
& 0x80000000) != 0)
12454 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12456 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12462 case BFD_RELOC_RVA
:
12465 /* If we are deleting this reloc entry, we must fill in the
12466 value now. This can happen if we have a .word which is not
12467 resolved when it appears but is later defined. */
12469 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12472 case BFD_RELOC_LO16
:
12473 case BFD_RELOC_MIPS16_LO16
:
12474 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12475 may be safe to remove, but if so it's not obvious. */
12476 /* When handling an embedded PIC switch statement, we can wind
12477 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12480 if (*valP
+ 0x8000 > 0xffff)
12481 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12482 _("relocation overflow"));
12483 if (target_big_endian
)
12485 md_number_to_chars ((char *) buf
, *valP
, 2);
12489 case BFD_RELOC_16_PCREL_S2
:
12490 if ((*valP
& 0x3) != 0)
12491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12492 _("Branch to misaligned address (%lx)"), (long) *valP
);
12494 /* We need to save the bits in the instruction since fixup_segment()
12495 might be deleting the relocation entry (i.e., a branch within
12496 the current segment). */
12497 if (! fixP
->fx_done
)
12500 /* Update old instruction data. */
12501 if (target_big_endian
)
12502 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12504 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12506 if (*valP
+ 0x20000 <= 0x3ffff)
12508 insn
|= (*valP
>> 2) & 0xffff;
12509 md_number_to_chars ((char *) buf
, insn
, 4);
12511 else if (mips_pic
== NO_PIC
12513 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12514 && (fixP
->fx_frag
->fr_address
12515 < text_section
->vma
+ bfd_get_section_size (text_section
))
12516 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12517 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12518 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12520 /* The branch offset is too large. If this is an
12521 unconditional branch, and we are not generating PIC code,
12522 we can convert it to an absolute jump instruction. */
12523 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12524 insn
= 0x0c000000; /* jal */
12526 insn
= 0x08000000; /* j */
12527 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12529 fixP
->fx_addsy
= section_symbol (text_section
);
12530 *valP
+= md_pcrel_from (fixP
);
12531 md_number_to_chars ((char *) buf
, insn
, 4);
12535 /* If we got here, we have branch-relaxation disabled,
12536 and there's nothing we can do to fix this instruction
12537 without turning it into a longer sequence. */
12538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12539 _("Branch out of range"));
12543 case BFD_RELOC_VTABLE_INHERIT
:
12546 && !S_IS_DEFINED (fixP
->fx_addsy
)
12547 && !S_IS_WEAK (fixP
->fx_addsy
))
12548 S_SET_WEAK (fixP
->fx_addsy
);
12551 case BFD_RELOC_VTABLE_ENTRY
:
12559 /* Remember value for tc_gen_reloc. */
12560 fixP
->fx_addnumber
= *valP
;
12570 name
= input_line_pointer
;
12571 c
= get_symbol_end ();
12572 p
= (symbolS
*) symbol_find_or_make (name
);
12573 *input_line_pointer
= c
;
12577 /* Align the current frag to a given power of two. If a particular
12578 fill byte should be used, FILL points to an integer that contains
12579 that byte, otherwise FILL is null.
12581 The MIPS assembler also automatically adjusts any preceding
12585 mips_align (int to
, int *fill
, symbolS
*label
)
12587 mips_emit_delays ();
12588 mips_record_mips16_mode ();
12589 if (fill
== NULL
&& subseg_text_p (now_seg
))
12590 frag_align_code (to
, 0);
12592 frag_align (to
, fill
? *fill
: 0, 0);
12593 record_alignment (now_seg
, to
);
12596 gas_assert (S_GET_SEGMENT (label
) == now_seg
);
12597 symbol_set_frag (label
, frag_now
);
12598 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12602 /* Align to a given power of two. .align 0 turns off the automatic
12603 alignment used by the data creating pseudo-ops. */
12606 s_align (int x ATTRIBUTE_UNUSED
)
12608 int temp
, fill_value
, *fill_ptr
;
12609 long max_alignment
= 28;
12611 /* o Note that the assembler pulls down any immediately preceding label
12612 to the aligned address.
12613 o It's not documented but auto alignment is reinstated by
12614 a .align pseudo instruction.
12615 o Note also that after auto alignment is turned off the mips assembler
12616 issues an error on attempt to assemble an improperly aligned data item.
12619 temp
= get_absolute_expression ();
12620 if (temp
> max_alignment
)
12621 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12624 as_warn (_("Alignment negative: 0 assumed."));
12627 if (*input_line_pointer
== ',')
12629 ++input_line_pointer
;
12630 fill_value
= get_absolute_expression ();
12631 fill_ptr
= &fill_value
;
12637 segment_info_type
*si
= seg_info (now_seg
);
12638 struct insn_label_list
*l
= si
->label_list
;
12639 /* Auto alignment should be switched on by next section change. */
12641 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12648 demand_empty_rest_of_line ();
12652 s_change_sec (int sec
)
12657 /* The ELF backend needs to know that we are changing sections, so
12658 that .previous works correctly. We could do something like check
12659 for an obj_section_change_hook macro, but that might be confusing
12660 as it would not be appropriate to use it in the section changing
12661 functions in read.c, since obj-elf.c intercepts those. FIXME:
12662 This should be cleaner, somehow. */
12664 obj_elf_section_change_hook ();
12667 mips_emit_delays ();
12678 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12679 demand_empty_rest_of_line ();
12683 seg
= subseg_new (RDATA_SECTION_NAME
,
12684 (subsegT
) get_absolute_expression ());
12687 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12688 | SEC_READONLY
| SEC_RELOC
12690 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12691 record_alignment (seg
, 4);
12693 demand_empty_rest_of_line ();
12697 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12700 bfd_set_section_flags (stdoutput
, seg
,
12701 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12702 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12703 record_alignment (seg
, 4);
12705 demand_empty_rest_of_line ();
12709 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
12712 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
12713 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12714 record_alignment (seg
, 4);
12716 demand_empty_rest_of_line ();
12724 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12727 char *section_name
;
12732 int section_entry_size
;
12733 int section_alignment
;
12738 section_name
= input_line_pointer
;
12739 c
= get_symbol_end ();
12741 next_c
= *(input_line_pointer
+ 1);
12743 /* Do we have .section Name<,"flags">? */
12744 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12746 /* just after name is now '\0'. */
12747 *input_line_pointer
= c
;
12748 input_line_pointer
= section_name
;
12749 obj_elf_section (ignore
);
12752 input_line_pointer
++;
12754 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12756 section_type
= get_absolute_expression ();
12759 if (*input_line_pointer
++ == ',')
12760 section_flag
= get_absolute_expression ();
12763 if (*input_line_pointer
++ == ',')
12764 section_entry_size
= get_absolute_expression ();
12766 section_entry_size
= 0;
12767 if (*input_line_pointer
++ == ',')
12768 section_alignment
= get_absolute_expression ();
12770 section_alignment
= 0;
12771 /* FIXME: really ignore? */
12772 (void) section_alignment
;
12774 section_name
= xstrdup (section_name
);
12776 /* When using the generic form of .section (as implemented by obj-elf.c),
12777 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12778 traditionally had to fall back on the more common @progbits instead.
12780 There's nothing really harmful in this, since bfd will correct
12781 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12782 means that, for backwards compatibility, the special_section entries
12783 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12785 Even so, we shouldn't force users of the MIPS .section syntax to
12786 incorrectly label the sections as SHT_PROGBITS. The best compromise
12787 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12788 generic type-checking code. */
12789 if (section_type
== SHT_MIPS_DWARF
)
12790 section_type
= SHT_PROGBITS
;
12792 obj_elf_change_section (section_name
, section_type
, section_flag
,
12793 section_entry_size
, 0, 0, 0);
12795 if (now_seg
->name
!= section_name
)
12796 free (section_name
);
12797 #endif /* OBJ_ELF */
12801 mips_enable_auto_align (void)
12807 s_cons (int log_size
)
12809 segment_info_type
*si
= seg_info (now_seg
);
12810 struct insn_label_list
*l
= si
->label_list
;
12813 label
= l
!= NULL
? l
->label
: NULL
;
12814 mips_emit_delays ();
12815 if (log_size
> 0 && auto_align
)
12816 mips_align (log_size
, 0, label
);
12817 cons (1 << log_size
);
12818 mips_clear_insn_labels ();
12822 s_float_cons (int type
)
12824 segment_info_type
*si
= seg_info (now_seg
);
12825 struct insn_label_list
*l
= si
->label_list
;
12828 label
= l
!= NULL
? l
->label
: NULL
;
12830 mips_emit_delays ();
12835 mips_align (3, 0, label
);
12837 mips_align (2, 0, label
);
12841 mips_clear_insn_labels ();
12844 /* Handle .globl. We need to override it because on Irix 5 you are
12847 where foo is an undefined symbol, to mean that foo should be
12848 considered to be the address of a function. */
12851 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12860 name
= input_line_pointer
;
12861 c
= get_symbol_end ();
12862 symbolP
= symbol_find_or_make (name
);
12863 S_SET_EXTERNAL (symbolP
);
12865 *input_line_pointer
= c
;
12866 SKIP_WHITESPACE ();
12868 /* On Irix 5, every global symbol that is not explicitly labelled as
12869 being a function is apparently labelled as being an object. */
12872 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12873 && (*input_line_pointer
!= ','))
12878 secname
= input_line_pointer
;
12879 c
= get_symbol_end ();
12880 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12882 as_bad (_("%s: no such section"), secname
);
12883 *input_line_pointer
= c
;
12885 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12886 flag
= BSF_FUNCTION
;
12889 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12891 c
= *input_line_pointer
;
12894 input_line_pointer
++;
12895 SKIP_WHITESPACE ();
12896 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12902 demand_empty_rest_of_line ();
12906 s_option (int x ATTRIBUTE_UNUSED
)
12911 opt
= input_line_pointer
;
12912 c
= get_symbol_end ();
12916 /* FIXME: What does this mean? */
12918 else if (strncmp (opt
, "pic", 3) == 0)
12922 i
= atoi (opt
+ 3);
12927 mips_pic
= SVR4_PIC
;
12928 mips_abicalls
= TRUE
;
12931 as_bad (_(".option pic%d not supported"), i
);
12933 if (mips_pic
== SVR4_PIC
)
12935 if (g_switch_seen
&& g_switch_value
!= 0)
12936 as_warn (_("-G may not be used with SVR4 PIC code"));
12937 g_switch_value
= 0;
12938 bfd_set_gp_size (stdoutput
, 0);
12942 as_warn (_("Unrecognized option \"%s\""), opt
);
12944 *input_line_pointer
= c
;
12945 demand_empty_rest_of_line ();
12948 /* This structure is used to hold a stack of .set values. */
12950 struct mips_option_stack
12952 struct mips_option_stack
*next
;
12953 struct mips_set_options options
;
12956 static struct mips_option_stack
*mips_opts_stack
;
12958 /* Handle the .set pseudo-op. */
12961 s_mipsset (int x ATTRIBUTE_UNUSED
)
12963 char *name
= input_line_pointer
, ch
;
12965 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12966 ++input_line_pointer
;
12967 ch
= *input_line_pointer
;
12968 *input_line_pointer
= '\0';
12970 if (strcmp (name
, "reorder") == 0)
12972 if (mips_opts
.noreorder
)
12975 else if (strcmp (name
, "noreorder") == 0)
12977 if (!mips_opts
.noreorder
)
12978 start_noreorder ();
12980 else if (strncmp (name
, "at=", 3) == 0)
12982 char *s
= name
+ 3;
12984 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
12985 as_bad (_("Unrecognized register name `%s'"), s
);
12987 else if (strcmp (name
, "at") == 0)
12989 mips_opts
.at
= ATREG
;
12991 else if (strcmp (name
, "noat") == 0)
12993 mips_opts
.at
= ZERO
;
12995 else if (strcmp (name
, "macro") == 0)
12997 mips_opts
.warn_about_macros
= 0;
12999 else if (strcmp (name
, "nomacro") == 0)
13001 if (mips_opts
.noreorder
== 0)
13002 as_bad (_("`noreorder' must be set before `nomacro'"));
13003 mips_opts
.warn_about_macros
= 1;
13005 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
13007 mips_opts
.nomove
= 0;
13009 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
13011 mips_opts
.nomove
= 1;
13013 else if (strcmp (name
, "bopt") == 0)
13015 mips_opts
.nobopt
= 0;
13017 else if (strcmp (name
, "nobopt") == 0)
13019 mips_opts
.nobopt
= 1;
13021 else if (strcmp (name
, "gp=default") == 0)
13022 mips_opts
.gp32
= file_mips_gp32
;
13023 else if (strcmp (name
, "gp=32") == 0)
13024 mips_opts
.gp32
= 1;
13025 else if (strcmp (name
, "gp=64") == 0)
13027 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13028 as_warn (_("%s isa does not support 64-bit registers"),
13029 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13030 mips_opts
.gp32
= 0;
13032 else if (strcmp (name
, "fp=default") == 0)
13033 mips_opts
.fp32
= file_mips_fp32
;
13034 else if (strcmp (name
, "fp=32") == 0)
13035 mips_opts
.fp32
= 1;
13036 else if (strcmp (name
, "fp=64") == 0)
13038 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13039 as_warn (_("%s isa does not support 64-bit floating point registers"),
13040 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13041 mips_opts
.fp32
= 0;
13043 else if (strcmp (name
, "softfloat") == 0)
13044 mips_opts
.soft_float
= 1;
13045 else if (strcmp (name
, "hardfloat") == 0)
13046 mips_opts
.soft_float
= 0;
13047 else if (strcmp (name
, "singlefloat") == 0)
13048 mips_opts
.single_float
= 1;
13049 else if (strcmp (name
, "doublefloat") == 0)
13050 mips_opts
.single_float
= 0;
13051 else if (strcmp (name
, "mips16") == 0
13052 || strcmp (name
, "MIPS-16") == 0)
13053 mips_opts
.mips16
= 1;
13054 else if (strcmp (name
, "nomips16") == 0
13055 || strcmp (name
, "noMIPS-16") == 0)
13056 mips_opts
.mips16
= 0;
13057 else if (strcmp (name
, "smartmips") == 0)
13059 if (!ISA_SUPPORTS_SMARTMIPS
)
13060 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13061 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13062 mips_opts
.ase_smartmips
= 1;
13064 else if (strcmp (name
, "nosmartmips") == 0)
13065 mips_opts
.ase_smartmips
= 0;
13066 else if (strcmp (name
, "mips3d") == 0)
13067 mips_opts
.ase_mips3d
= 1;
13068 else if (strcmp (name
, "nomips3d") == 0)
13069 mips_opts
.ase_mips3d
= 0;
13070 else if (strcmp (name
, "mdmx") == 0)
13071 mips_opts
.ase_mdmx
= 1;
13072 else if (strcmp (name
, "nomdmx") == 0)
13073 mips_opts
.ase_mdmx
= 0;
13074 else if (strcmp (name
, "dsp") == 0)
13076 if (!ISA_SUPPORTS_DSP_ASE
)
13077 as_warn (_("%s ISA does not support DSP ASE"),
13078 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13079 mips_opts
.ase_dsp
= 1;
13080 mips_opts
.ase_dspr2
= 0;
13082 else if (strcmp (name
, "nodsp") == 0)
13084 mips_opts
.ase_dsp
= 0;
13085 mips_opts
.ase_dspr2
= 0;
13087 else if (strcmp (name
, "dspr2") == 0)
13089 if (!ISA_SUPPORTS_DSPR2_ASE
)
13090 as_warn (_("%s ISA does not support DSP R2 ASE"),
13091 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13092 mips_opts
.ase_dspr2
= 1;
13093 mips_opts
.ase_dsp
= 1;
13095 else if (strcmp (name
, "nodspr2") == 0)
13097 mips_opts
.ase_dspr2
= 0;
13098 mips_opts
.ase_dsp
= 0;
13100 else if (strcmp (name
, "mt") == 0)
13102 if (!ISA_SUPPORTS_MT_ASE
)
13103 as_warn (_("%s ISA does not support MT ASE"),
13104 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13105 mips_opts
.ase_mt
= 1;
13107 else if (strcmp (name
, "nomt") == 0)
13108 mips_opts
.ase_mt
= 0;
13109 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
13113 /* Permit the user to change the ISA and architecture on the fly.
13114 Needless to say, misuse can cause serious problems. */
13115 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
13118 mips_opts
.isa
= file_mips_isa
;
13119 mips_opts
.arch
= file_mips_arch
;
13121 else if (strncmp (name
, "arch=", 5) == 0)
13123 const struct mips_cpu_info
*p
;
13125 p
= mips_parse_cpu("internal use", name
+ 5);
13127 as_bad (_("unknown architecture %s"), name
+ 5);
13130 mips_opts
.arch
= p
->cpu
;
13131 mips_opts
.isa
= p
->isa
;
13134 else if (strncmp (name
, "mips", 4) == 0)
13136 const struct mips_cpu_info
*p
;
13138 p
= mips_parse_cpu("internal use", name
);
13140 as_bad (_("unknown ISA level %s"), name
+ 4);
13143 mips_opts
.arch
= p
->cpu
;
13144 mips_opts
.isa
= p
->isa
;
13148 as_bad (_("unknown ISA or architecture %s"), name
);
13150 switch (mips_opts
.isa
)
13158 mips_opts
.gp32
= 1;
13159 mips_opts
.fp32
= 1;
13166 mips_opts
.gp32
= 0;
13167 mips_opts
.fp32
= 0;
13170 as_bad (_("unknown ISA level %s"), name
+ 4);
13175 mips_opts
.gp32
= file_mips_gp32
;
13176 mips_opts
.fp32
= file_mips_fp32
;
13179 else if (strcmp (name
, "autoextend") == 0)
13180 mips_opts
.noautoextend
= 0;
13181 else if (strcmp (name
, "noautoextend") == 0)
13182 mips_opts
.noautoextend
= 1;
13183 else if (strcmp (name
, "push") == 0)
13185 struct mips_option_stack
*s
;
13187 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
13188 s
->next
= mips_opts_stack
;
13189 s
->options
= mips_opts
;
13190 mips_opts_stack
= s
;
13192 else if (strcmp (name
, "pop") == 0)
13194 struct mips_option_stack
*s
;
13196 s
= mips_opts_stack
;
13198 as_bad (_(".set pop with no .set push"));
13201 /* If we're changing the reorder mode we need to handle
13202 delay slots correctly. */
13203 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
13204 start_noreorder ();
13205 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
13208 mips_opts
= s
->options
;
13209 mips_opts_stack
= s
->next
;
13213 else if (strcmp (name
, "sym32") == 0)
13214 mips_opts
.sym32
= TRUE
;
13215 else if (strcmp (name
, "nosym32") == 0)
13216 mips_opts
.sym32
= FALSE
;
13217 else if (strchr (name
, ','))
13219 /* Generic ".set" directive; use the generic handler. */
13220 *input_line_pointer
= ch
;
13221 input_line_pointer
= name
;
13227 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
13229 *input_line_pointer
= ch
;
13230 demand_empty_rest_of_line ();
13233 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13234 .option pic2. It means to generate SVR4 PIC calls. */
13237 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
13239 mips_pic
= SVR4_PIC
;
13240 mips_abicalls
= TRUE
;
13242 if (g_switch_seen
&& g_switch_value
!= 0)
13243 as_warn (_("-G may not be used with SVR4 PIC code"));
13244 g_switch_value
= 0;
13246 bfd_set_gp_size (stdoutput
, 0);
13247 demand_empty_rest_of_line ();
13250 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13251 PIC code. It sets the $gp register for the function based on the
13252 function address, which is in the register named in the argument.
13253 This uses a relocation against _gp_disp, which is handled specially
13254 by the linker. The result is:
13255 lui $gp,%hi(_gp_disp)
13256 addiu $gp,$gp,%lo(_gp_disp)
13257 addu $gp,$gp,.cpload argument
13258 The .cpload argument is normally $25 == $t9.
13260 The -mno-shared option changes this to:
13261 lui $gp,%hi(__gnu_local_gp)
13262 addiu $gp,$gp,%lo(__gnu_local_gp)
13263 and the argument is ignored. This saves an instruction, but the
13264 resulting code is not position independent; it uses an absolute
13265 address for __gnu_local_gp. Thus code assembled with -mno-shared
13266 can go into an ordinary executable, but not into a shared library. */
13269 s_cpload (int ignore ATTRIBUTE_UNUSED
)
13275 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13276 .cpload is ignored. */
13277 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13283 /* .cpload should be in a .set noreorder section. */
13284 if (mips_opts
.noreorder
== 0)
13285 as_warn (_(".cpload not in noreorder section"));
13287 reg
= tc_get_register (0);
13289 /* If we need to produce a 64-bit address, we are better off using
13290 the default instruction sequence. */
13291 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
13293 ex
.X_op
= O_symbol
;
13294 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
13296 ex
.X_op_symbol
= NULL
;
13297 ex
.X_add_number
= 0;
13299 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13300 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13303 macro_build_lui (&ex
, mips_gp_register
);
13304 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13305 mips_gp_register
, BFD_RELOC_LO16
);
13307 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
13308 mips_gp_register
, reg
);
13311 demand_empty_rest_of_line ();
13314 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13315 .cpsetup $reg1, offset|$reg2, label
13317 If offset is given, this results in:
13318 sd $gp, offset($sp)
13319 lui $gp, %hi(%neg(%gp_rel(label)))
13320 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13321 daddu $gp, $gp, $reg1
13323 If $reg2 is given, this results in:
13324 daddu $reg2, $gp, $0
13325 lui $gp, %hi(%neg(%gp_rel(label)))
13326 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13327 daddu $gp, $gp, $reg1
13328 $reg1 is normally $25 == $t9.
13330 The -mno-shared option replaces the last three instructions with
13332 addiu $gp,$gp,%lo(_gp) */
13335 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
13337 expressionS ex_off
;
13338 expressionS ex_sym
;
13341 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13342 We also need NewABI support. */
13343 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13349 reg1
= tc_get_register (0);
13350 SKIP_WHITESPACE ();
13351 if (*input_line_pointer
!= ',')
13353 as_bad (_("missing argument separator ',' for .cpsetup"));
13357 ++input_line_pointer
;
13358 SKIP_WHITESPACE ();
13359 if (*input_line_pointer
== '$')
13361 mips_cpreturn_register
= tc_get_register (0);
13362 mips_cpreturn_offset
= -1;
13366 mips_cpreturn_offset
= get_absolute_expression ();
13367 mips_cpreturn_register
= -1;
13369 SKIP_WHITESPACE ();
13370 if (*input_line_pointer
!= ',')
13372 as_bad (_("missing argument separator ',' for .cpsetup"));
13376 ++input_line_pointer
;
13377 SKIP_WHITESPACE ();
13378 expression (&ex_sym
);
13381 if (mips_cpreturn_register
== -1)
13383 ex_off
.X_op
= O_constant
;
13384 ex_off
.X_add_symbol
= NULL
;
13385 ex_off
.X_op_symbol
= NULL
;
13386 ex_off
.X_add_number
= mips_cpreturn_offset
;
13388 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13389 BFD_RELOC_LO16
, SP
);
13392 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13393 mips_gp_register
, 0);
13395 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13397 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13398 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13401 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13402 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13403 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13405 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13406 mips_gp_register
, reg1
);
13412 ex
.X_op
= O_symbol
;
13413 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13414 ex
.X_op_symbol
= NULL
;
13415 ex
.X_add_number
= 0;
13417 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13418 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13420 macro_build_lui (&ex
, mips_gp_register
);
13421 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13422 mips_gp_register
, BFD_RELOC_LO16
);
13427 demand_empty_rest_of_line ();
13431 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13433 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13434 .cplocal is ignored. */
13435 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13441 mips_gp_register
= tc_get_register (0);
13442 demand_empty_rest_of_line ();
13445 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13446 offset from $sp. The offset is remembered, and after making a PIC
13447 call $gp is restored from that location. */
13450 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13454 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13455 .cprestore is ignored. */
13456 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13462 mips_cprestore_offset
= get_absolute_expression ();
13463 mips_cprestore_valid
= 1;
13465 ex
.X_op
= O_constant
;
13466 ex
.X_add_symbol
= NULL
;
13467 ex
.X_op_symbol
= NULL
;
13468 ex
.X_add_number
= mips_cprestore_offset
;
13471 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13472 SP
, HAVE_64BIT_ADDRESSES
);
13475 demand_empty_rest_of_line ();
13478 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13479 was given in the preceding .cpsetup, it results in:
13480 ld $gp, offset($sp)
13482 If a register $reg2 was given there, it results in:
13483 daddu $gp, $reg2, $0 */
13486 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13490 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13491 We also need NewABI support. */
13492 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13499 if (mips_cpreturn_register
== -1)
13501 ex
.X_op
= O_constant
;
13502 ex
.X_add_symbol
= NULL
;
13503 ex
.X_op_symbol
= NULL
;
13504 ex
.X_add_number
= mips_cpreturn_offset
;
13506 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13509 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13510 mips_cpreturn_register
, 0);
13513 demand_empty_rest_of_line ();
13516 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13517 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13518 use in DWARF debug information. */
13521 s_dtprel_internal (size_t bytes
)
13528 if (ex
.X_op
!= O_symbol
)
13530 as_bad (_("Unsupported use of %s"), (bytes
== 8
13533 ignore_rest_of_line ();
13536 p
= frag_more (bytes
);
13537 md_number_to_chars (p
, 0, bytes
);
13538 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13540 ? BFD_RELOC_MIPS_TLS_DTPREL64
13541 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13543 demand_empty_rest_of_line ();
13546 /* Handle .dtprelword. */
13549 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13551 s_dtprel_internal (4);
13554 /* Handle .dtpreldword. */
13557 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13559 s_dtprel_internal (8);
13562 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13563 code. It sets the offset to use in gp_rel relocations. */
13566 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13568 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13569 We also need NewABI support. */
13570 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13576 mips_gprel_offset
= get_absolute_expression ();
13578 demand_empty_rest_of_line ();
13581 /* Handle the .gpword pseudo-op. This is used when generating PIC
13582 code. It generates a 32 bit GP relative reloc. */
13585 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13587 segment_info_type
*si
;
13588 struct insn_label_list
*l
;
13593 /* When not generating PIC code, this is treated as .word. */
13594 if (mips_pic
!= SVR4_PIC
)
13600 si
= seg_info (now_seg
);
13601 l
= si
->label_list
;
13602 label
= l
!= NULL
? l
->label
: NULL
;
13603 mips_emit_delays ();
13605 mips_align (2, 0, label
);
13608 mips_clear_insn_labels ();
13610 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13612 as_bad (_("Unsupported use of .gpword"));
13613 ignore_rest_of_line ();
13617 md_number_to_chars (p
, 0, 4);
13618 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13619 BFD_RELOC_GPREL32
);
13621 demand_empty_rest_of_line ();
13625 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13627 segment_info_type
*si
;
13628 struct insn_label_list
*l
;
13633 /* When not generating PIC code, this is treated as .dword. */
13634 if (mips_pic
!= SVR4_PIC
)
13640 si
= seg_info (now_seg
);
13641 l
= si
->label_list
;
13642 label
= l
!= NULL
? l
->label
: NULL
;
13643 mips_emit_delays ();
13645 mips_align (3, 0, label
);
13648 mips_clear_insn_labels ();
13650 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13652 as_bad (_("Unsupported use of .gpdword"));
13653 ignore_rest_of_line ();
13657 md_number_to_chars (p
, 0, 8);
13658 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13659 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13661 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13662 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13663 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13665 demand_empty_rest_of_line ();
13668 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13669 tables in SVR4 PIC code. */
13672 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13676 /* This is ignored when not generating SVR4 PIC code. */
13677 if (mips_pic
!= SVR4_PIC
)
13683 /* Add $gp to the register named as an argument. */
13685 reg
= tc_get_register (0);
13686 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13689 demand_empty_rest_of_line ();
13692 /* Handle the .insn pseudo-op. This marks instruction labels in
13693 mips16 mode. This permits the linker to handle them specially,
13694 such as generating jalx instructions when needed. We also make
13695 them odd for the duration of the assembly, in order to generate the
13696 right sort of code. We will make them even in the adjust_symtab
13697 routine, while leaving them marked. This is convenient for the
13698 debugger and the disassembler. The linker knows to make them odd
13702 s_insn (int ignore ATTRIBUTE_UNUSED
)
13704 mips16_mark_labels ();
13706 demand_empty_rest_of_line ();
13709 /* Handle a .stabn directive. We need these in order to mark a label
13710 as being a mips16 text label correctly. Sometimes the compiler
13711 will emit a label, followed by a .stabn, and then switch sections.
13712 If the label and .stabn are in mips16 mode, then the label is
13713 really a mips16 text label. */
13716 s_mips_stab (int type
)
13719 mips16_mark_labels ();
13724 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13727 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13734 name
= input_line_pointer
;
13735 c
= get_symbol_end ();
13736 symbolP
= symbol_find_or_make (name
);
13737 S_SET_WEAK (symbolP
);
13738 *input_line_pointer
= c
;
13740 SKIP_WHITESPACE ();
13742 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13744 if (S_IS_DEFINED (symbolP
))
13746 as_bad (_("ignoring attempt to redefine symbol %s"),
13747 S_GET_NAME (symbolP
));
13748 ignore_rest_of_line ();
13752 if (*input_line_pointer
== ',')
13754 ++input_line_pointer
;
13755 SKIP_WHITESPACE ();
13759 if (exp
.X_op
!= O_symbol
)
13761 as_bad (_("bad .weakext directive"));
13762 ignore_rest_of_line ();
13765 symbol_set_value_expression (symbolP
, &exp
);
13768 demand_empty_rest_of_line ();
13771 /* Parse a register string into a number. Called from the ECOFF code
13772 to parse .frame. The argument is non-zero if this is the frame
13773 register, so that we can record it in mips_frame_reg. */
13776 tc_get_register (int frame
)
13780 SKIP_WHITESPACE ();
13781 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13785 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13786 mips_frame_reg_valid
= 1;
13787 mips_cprestore_valid
= 0;
13793 md_section_align (asection
*seg
, valueT addr
)
13795 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13799 /* We don't need to align ELF sections to the full alignment.
13800 However, Irix 5 may prefer that we align them at least to a 16
13801 byte boundary. We don't bother to align the sections if we
13802 are targeted for an embedded system. */
13803 if (strncmp (TARGET_OS
, "elf", 3) == 0)
13809 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13812 /* Utility routine, called from above as well. If called while the
13813 input file is still being read, it's only an approximation. (For
13814 example, a symbol may later become defined which appeared to be
13815 undefined earlier.) */
13818 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13823 if (g_switch_value
> 0)
13825 const char *symname
;
13828 /* Find out whether this symbol can be referenced off the $gp
13829 register. It can be if it is smaller than the -G size or if
13830 it is in the .sdata or .sbss section. Certain symbols can
13831 not be referenced off the $gp, although it appears as though
13833 symname
= S_GET_NAME (sym
);
13834 if (symname
!= (const char *) NULL
13835 && (strcmp (symname
, "eprol") == 0
13836 || strcmp (symname
, "etext") == 0
13837 || strcmp (symname
, "_gp") == 0
13838 || strcmp (symname
, "edata") == 0
13839 || strcmp (symname
, "_fbss") == 0
13840 || strcmp (symname
, "_fdata") == 0
13841 || strcmp (symname
, "_ftext") == 0
13842 || strcmp (symname
, "end") == 0
13843 || strcmp (symname
, "_gp_disp") == 0))
13845 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13847 #ifndef NO_ECOFF_DEBUGGING
13848 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13849 && (symbol_get_obj (sym
)->ecoff_extern_size
13850 <= g_switch_value
))
13852 /* We must defer this decision until after the whole
13853 file has been read, since there might be a .extern
13854 after the first use of this symbol. */
13855 || (before_relaxing
13856 #ifndef NO_ECOFF_DEBUGGING
13857 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13859 && S_GET_VALUE (sym
) == 0)
13860 || (S_GET_VALUE (sym
) != 0
13861 && S_GET_VALUE (sym
) <= g_switch_value
)))
13865 const char *segname
;
13867 segname
= segment_name (S_GET_SEGMENT (sym
));
13868 gas_assert (strcmp (segname
, ".lit8") != 0
13869 && strcmp (segname
, ".lit4") != 0);
13870 change
= (strcmp (segname
, ".sdata") != 0
13871 && strcmp (segname
, ".sbss") != 0
13872 && strncmp (segname
, ".sdata.", 7) != 0
13873 && strncmp (segname
, ".sbss.", 6) != 0
13874 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13875 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13880 /* We are not optimizing for the $gp register. */
13885 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13888 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13892 /* Handle the case of a symbol equated to another symbol. */
13893 while (symbol_equated_reloc_p (sym
))
13897 /* It's possible to get a loop here in a badly written program. */
13898 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13904 if (symbol_section_p (sym
))
13907 symsec
= S_GET_SEGMENT (sym
);
13909 /* This must duplicate the test in adjust_reloc_syms. */
13910 return (symsec
!= &bfd_und_section
13911 && symsec
!= &bfd_abs_section
13912 && !bfd_is_com_section (symsec
)
13913 && !s_is_linkonce (sym
, segtype
)
13915 /* A global or weak symbol is treated as external. */
13916 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13922 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13923 extended opcode. SEC is the section the frag is in. */
13926 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13929 const struct mips16_immed_operand
*op
;
13931 int mintiny
, maxtiny
;
13935 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13937 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13940 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13941 op
= mips16_immed_operands
;
13942 while (op
->type
!= type
)
13945 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13950 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13953 maxtiny
= 1 << op
->nbits
;
13958 maxtiny
= (1 << op
->nbits
) - 1;
13963 mintiny
= - (1 << (op
->nbits
- 1));
13964 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13967 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13968 val
= S_GET_VALUE (fragp
->fr_symbol
);
13969 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13975 /* We won't have the section when we are called from
13976 mips_relax_frag. However, we will always have been called
13977 from md_estimate_size_before_relax first. If this is a
13978 branch to a different section, we mark it as such. If SEC is
13979 NULL, and the frag is not marked, then it must be a branch to
13980 the same section. */
13983 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13988 /* Must have been called from md_estimate_size_before_relax. */
13991 fragp
->fr_subtype
=
13992 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13994 /* FIXME: We should support this, and let the linker
13995 catch branches and loads that are out of range. */
13996 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13997 _("unsupported PC relative reference to different section"));
14001 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
14002 /* Assume non-extended on the first relaxation pass.
14003 The address we have calculated will be bogus if this is
14004 a forward branch to another frag, as the forward frag
14005 will have fr_address == 0. */
14009 /* In this case, we know for sure that the symbol fragment is in
14010 the same section. If the relax_marker of the symbol fragment
14011 differs from the relax_marker of this fragment, we have not
14012 yet adjusted the symbol fragment fr_address. We want to add
14013 in STRETCH in order to get a better estimate of the address.
14014 This particularly matters because of the shift bits. */
14016 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
14020 /* Adjust stretch for any alignment frag. Note that if have
14021 been expanding the earlier code, the symbol may be
14022 defined in what appears to be an earlier frag. FIXME:
14023 This doesn't handle the fr_subtype field, which specifies
14024 a maximum number of bytes to skip when doing an
14026 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
14028 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
14031 stretch
= - ((- stretch
)
14032 & ~ ((1 << (int) f
->fr_offset
) - 1));
14034 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
14043 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14045 /* The base address rules are complicated. The base address of
14046 a branch is the following instruction. The base address of a
14047 PC relative load or add is the instruction itself, but if it
14048 is in a delay slot (in which case it can not be extended) use
14049 the address of the instruction whose delay slot it is in. */
14050 if (type
== 'p' || type
== 'q')
14054 /* If we are currently assuming that this frag should be
14055 extended, then, the current address is two bytes
14057 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14060 /* Ignore the low bit in the target, since it will be set
14061 for a text label. */
14062 if ((val
& 1) != 0)
14065 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14067 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14070 val
-= addr
& ~ ((1 << op
->shift
) - 1);
14072 /* Branch offsets have an implicit 0 in the lowest bit. */
14073 if (type
== 'p' || type
== 'q')
14076 /* If any of the shifted bits are set, we must use an extended
14077 opcode. If the address depends on the size of this
14078 instruction, this can lead to a loop, so we arrange to always
14079 use an extended opcode. We only check this when we are in
14080 the main relaxation loop, when SEC is NULL. */
14081 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
14083 fragp
->fr_subtype
=
14084 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14088 /* If we are about to mark a frag as extended because the value
14089 is precisely maxtiny + 1, then there is a chance of an
14090 infinite loop as in the following code:
14095 In this case when the la is extended, foo is 0x3fc bytes
14096 away, so the la can be shrunk, but then foo is 0x400 away, so
14097 the la must be extended. To avoid this loop, we mark the
14098 frag as extended if it was small, and is about to become
14099 extended with a value of maxtiny + 1. */
14100 if (val
== ((maxtiny
+ 1) << op
->shift
)
14101 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
14104 fragp
->fr_subtype
=
14105 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14109 else if (symsec
!= absolute_section
&& sec
!= NULL
)
14110 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
14112 if ((val
& ((1 << op
->shift
) - 1)) != 0
14113 || val
< (mintiny
<< op
->shift
)
14114 || val
> (maxtiny
<< op
->shift
))
14120 /* Compute the length of a branch sequence, and adjust the
14121 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14122 worst-case length is computed, with UPDATE being used to indicate
14123 whether an unconditional (-1), branch-likely (+1) or regular (0)
14124 branch is to be computed. */
14126 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
14128 bfd_boolean toofar
;
14132 && S_IS_DEFINED (fragp
->fr_symbol
)
14133 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
14138 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
14140 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
14144 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
14147 /* If the symbol is not defined or it's in a different segment,
14148 assume the user knows what's going on and emit a short
14154 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14156 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
14157 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
14158 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
14159 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
14165 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
14168 if (mips_pic
!= NO_PIC
)
14170 /* Additional space for PIC loading of target address. */
14172 if (mips_opts
.isa
== ISA_MIPS1
)
14173 /* Additional space for $at-stabilizing nop. */
14177 /* If branch is conditional. */
14178 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
14185 /* Estimate the size of a frag before relaxing. Unless this is the
14186 mips16, we are not really relaxing here, and the final size is
14187 encoded in the subtype information. For the mips16, we have to
14188 decide whether we are using an extended opcode or not. */
14191 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
14195 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14198 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
14200 return fragp
->fr_var
;
14203 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14204 /* We don't want to modify the EXTENDED bit here; it might get us
14205 into infinite loops. We change it only in mips_relax_frag(). */
14206 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
14208 if (mips_pic
== NO_PIC
)
14209 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
14210 else if (mips_pic
== SVR4_PIC
)
14211 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
14212 else if (mips_pic
== VXWORKS_PIC
)
14213 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14220 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
14221 return -RELAX_FIRST (fragp
->fr_subtype
);
14224 return -RELAX_SECOND (fragp
->fr_subtype
);
14227 /* This is called to see whether a reloc against a defined symbol
14228 should be converted into a reloc against a section. */
14231 mips_fix_adjustable (fixS
*fixp
)
14233 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14234 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14237 if (fixp
->fx_addsy
== NULL
)
14240 /* If symbol SYM is in a mergeable section, relocations of the form
14241 SYM + 0 can usually be made section-relative. The mergeable data
14242 is then identified by the section offset rather than by the symbol.
14244 However, if we're generating REL LO16 relocations, the offset is split
14245 between the LO16 and parterning high part relocation. The linker will
14246 need to recalculate the complete offset in order to correctly identify
14249 The linker has traditionally not looked for the parterning high part
14250 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14251 placed anywhere. Rather than break backwards compatibility by changing
14252 this, it seems better not to force the issue, and instead keep the
14253 original symbol. This will work with either linker behavior. */
14254 if ((lo16_reloc_p (fixp
->fx_r_type
)
14255 || reloc_needs_lo_p (fixp
->fx_r_type
))
14256 && HAVE_IN_PLACE_ADDENDS
14257 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
14260 /* There is no place to store an in-place offset for JALR relocations.
14261 Likewise an in-range offset of PC-relative relocations may overflow
14262 the in-place relocatable field if recalculated against the start
14263 address of the symbol's containing section. */
14264 if (HAVE_IN_PLACE_ADDENDS
14265 && (fixp
->fx_pcrel
|| fixp
->fx_r_type
== BFD_RELOC_MIPS_JALR
))
14269 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14270 to a floating-point stub. The same is true for non-R_MIPS16_26
14271 relocations against MIPS16 functions; in this case, the stub becomes
14272 the function's canonical address.
14274 Floating-point stubs are stored in unique .mips16.call.* or
14275 .mips16.fn.* sections. If a stub T for function F is in section S,
14276 the first relocation in section S must be against F; this is how the
14277 linker determines the target function. All relocations that might
14278 resolve to T must also be against F. We therefore have the following
14279 restrictions, which are given in an intentionally-redundant way:
14281 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14284 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14285 if that stub might be used.
14287 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14290 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14291 that stub might be used.
14293 There is a further restriction:
14295 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14296 on targets with in-place addends; the relocation field cannot
14297 encode the low bit.
14299 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14300 against a MIPS16 symbol.
14302 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14303 relocation against some symbol R, no relocation against R may be
14304 reduced. (Note that this deals with (2) as well as (1) because
14305 relocations against global symbols will never be reduced on ELF
14306 targets.) This approach is a little simpler than trying to detect
14307 stub sections, and gives the "all or nothing" per-symbol consistency
14308 that we have for MIPS16 symbols. */
14310 && fixp
->fx_subsy
== NULL
14311 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
14312 || *symbol_get_tc (fixp
->fx_addsy
)))
14319 /* Translate internal representation of relocation info to BFD target
14323 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14325 static arelent
*retval
[4];
14327 bfd_reloc_code_real_type code
;
14329 memset (retval
, 0, sizeof(retval
));
14330 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
14331 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
14332 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14333 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14335 if (fixp
->fx_pcrel
)
14337 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
14339 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14340 Relocations want only the symbol offset. */
14341 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
14344 /* A gruesome hack which is a result of the gruesome gas
14345 reloc handling. What's worse, for COFF (as opposed to
14346 ECOFF), we might need yet another copy of reloc->address.
14347 See bfd_install_relocation. */
14348 reloc
->addend
+= reloc
->address
;
14352 reloc
->addend
= fixp
->fx_addnumber
;
14354 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14355 entry to be used in the relocation's section offset. */
14356 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14358 reloc
->address
= reloc
->addend
;
14362 code
= fixp
->fx_r_type
;
14364 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14365 if (reloc
->howto
== NULL
)
14367 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14368 _("Can not represent %s relocation in this object file format"),
14369 bfd_get_reloc_code_name (code
));
14376 /* Relax a machine dependent frag. This returns the amount by which
14377 the current size of the frag should change. */
14380 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14382 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14384 offsetT old_var
= fragp
->fr_var
;
14386 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14388 return fragp
->fr_var
- old_var
;
14391 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14394 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14396 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14398 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14403 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14405 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14412 /* Convert a machine dependent frag. */
14415 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14417 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14420 unsigned long insn
;
14424 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14426 if (target_big_endian
)
14427 insn
= bfd_getb32 (buf
);
14429 insn
= bfd_getl32 (buf
);
14431 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14433 /* We generate a fixup instead of applying it right now
14434 because, if there are linker relaxations, we're going to
14435 need the relocations. */
14436 exp
.X_op
= O_symbol
;
14437 exp
.X_add_symbol
= fragp
->fr_symbol
;
14438 exp
.X_add_number
= fragp
->fr_offset
;
14440 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14441 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14442 fixp
->fx_file
= fragp
->fr_file
;
14443 fixp
->fx_line
= fragp
->fr_line
;
14445 md_number_to_chars ((char *) buf
, insn
, 4);
14452 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14453 _("Relaxed out-of-range branch into a jump"));
14455 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14458 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14460 /* Reverse the branch. */
14461 switch ((insn
>> 28) & 0xf)
14464 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14465 have the condition reversed by tweaking a single
14466 bit, and their opcodes all have 0x4???????. */
14467 gas_assert ((insn
& 0xf1000000) == 0x41000000);
14468 insn
^= 0x00010000;
14472 /* bltz 0x04000000 bgez 0x04010000
14473 bltzal 0x04100000 bgezal 0x04110000 */
14474 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
14475 insn
^= 0x00010000;
14479 /* beq 0x10000000 bne 0x14000000
14480 blez 0x18000000 bgtz 0x1c000000 */
14481 insn
^= 0x04000000;
14489 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14491 /* Clear the and-link bit. */
14492 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
14494 /* bltzal 0x04100000 bgezal 0x04110000
14495 bltzall 0x04120000 bgezall 0x04130000 */
14496 insn
&= ~0x00100000;
14499 /* Branch over the branch (if the branch was likely) or the
14500 full jump (not likely case). Compute the offset from the
14501 current instruction to branch to. */
14502 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14506 /* How many bytes in instructions we've already emitted? */
14507 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14508 /* How many bytes in instructions from here to the end? */
14509 i
= fragp
->fr_var
- i
;
14511 /* Convert to instruction count. */
14513 /* Branch counts from the next instruction. */
14516 /* Branch over the jump. */
14517 md_number_to_chars ((char *) buf
, insn
, 4);
14521 md_number_to_chars ((char *) buf
, 0, 4);
14524 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14526 /* beql $0, $0, 2f */
14528 /* Compute the PC offset from the current instruction to
14529 the end of the variable frag. */
14530 /* How many bytes in instructions we've already emitted? */
14531 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14532 /* How many bytes in instructions from here to the end? */
14533 i
= fragp
->fr_var
- i
;
14534 /* Convert to instruction count. */
14536 /* Don't decrement i, because we want to branch over the
14540 md_number_to_chars ((char *) buf
, insn
, 4);
14543 md_number_to_chars ((char *) buf
, 0, 4);
14548 if (mips_pic
== NO_PIC
)
14551 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14552 ? 0x0c000000 : 0x08000000);
14553 exp
.X_op
= O_symbol
;
14554 exp
.X_add_symbol
= fragp
->fr_symbol
;
14555 exp
.X_add_number
= fragp
->fr_offset
;
14557 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14558 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14559 fixp
->fx_file
= fragp
->fr_file
;
14560 fixp
->fx_line
= fragp
->fr_line
;
14562 md_number_to_chars ((char *) buf
, insn
, 4);
14567 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
14569 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14570 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
14571 insn
|= at
<< OP_SH_RT
;
14572 exp
.X_op
= O_symbol
;
14573 exp
.X_add_symbol
= fragp
->fr_symbol
;
14574 exp
.X_add_number
= fragp
->fr_offset
;
14576 if (fragp
->fr_offset
)
14578 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14579 exp
.X_add_number
= 0;
14582 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14583 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14584 fixp
->fx_file
= fragp
->fr_file
;
14585 fixp
->fx_line
= fragp
->fr_line
;
14587 md_number_to_chars ((char *) buf
, insn
, 4);
14590 if (mips_opts
.isa
== ISA_MIPS1
)
14593 md_number_to_chars ((char *) buf
, 0, 4);
14597 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14598 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
14599 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
14601 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14602 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14603 fixp
->fx_file
= fragp
->fr_file
;
14604 fixp
->fx_line
= fragp
->fr_line
;
14606 md_number_to_chars ((char *) buf
, insn
, 4);
14610 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14614 insn
|= at
<< OP_SH_RS
;
14616 md_number_to_chars ((char *) buf
, insn
, 4);
14621 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
14622 + fragp
->fr_fix
+ fragp
->fr_var
);
14624 fragp
->fr_fix
+= fragp
->fr_var
;
14629 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14632 const struct mips16_immed_operand
*op
;
14633 bfd_boolean small
, ext
;
14636 unsigned long insn
;
14637 bfd_boolean use_extend
;
14638 unsigned short extend
;
14640 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14641 op
= mips16_immed_operands
;
14642 while (op
->type
!= type
)
14645 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14656 val
= resolve_symbol_value (fragp
->fr_symbol
);
14661 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14663 /* The rules for the base address of a PC relative reloc are
14664 complicated; see mips16_extended_frag. */
14665 if (type
== 'p' || type
== 'q')
14670 /* Ignore the low bit in the target, since it will be
14671 set for a text label. */
14672 if ((val
& 1) != 0)
14675 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14677 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14680 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14683 /* Make sure the section winds up with the alignment we have
14686 record_alignment (asec
, op
->shift
);
14690 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14691 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14692 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14693 _("extended instruction in delay slot"));
14695 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14697 if (target_big_endian
)
14698 insn
= bfd_getb16 (buf
);
14700 insn
= bfd_getl16 (buf
);
14702 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14703 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14704 small
, ext
, &insn
, &use_extend
, &extend
);
14708 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14709 fragp
->fr_fix
+= 2;
14713 md_number_to_chars ((char *) buf
, insn
, 2);
14714 fragp
->fr_fix
+= 2;
14722 first
= RELAX_FIRST (fragp
->fr_subtype
);
14723 second
= RELAX_SECOND (fragp
->fr_subtype
);
14724 fixp
= (fixS
*) fragp
->fr_opcode
;
14726 /* Possibly emit a warning if we've chosen the longer option. */
14727 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14728 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14730 const char *msg
= macro_warning (fragp
->fr_subtype
);
14732 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
14735 /* Go through all the fixups for the first sequence. Disable them
14736 (by marking them as done) if we're going to use the second
14737 sequence instead. */
14739 && fixp
->fx_frag
== fragp
14740 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14742 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14744 fixp
= fixp
->fx_next
;
14747 /* Go through the fixups for the second sequence. Disable them if
14748 we're going to use the first sequence, otherwise adjust their
14749 addresses to account for the relaxation. */
14750 while (fixp
&& fixp
->fx_frag
== fragp
)
14752 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14753 fixp
->fx_where
-= first
;
14756 fixp
= fixp
->fx_next
;
14759 /* Now modify the frag contents. */
14760 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14764 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14765 memmove (start
, start
+ first
, second
);
14766 fragp
->fr_fix
-= first
;
14769 fragp
->fr_fix
-= second
;
14775 /* This function is called after the relocs have been generated.
14776 We've been storing mips16 text labels as odd. Here we convert them
14777 back to even for the convenience of the debugger. */
14780 mips_frob_file_after_relocs (void)
14783 unsigned int count
, i
;
14788 syms
= bfd_get_outsymbols (stdoutput
);
14789 count
= bfd_get_symcount (stdoutput
);
14790 for (i
= 0; i
< count
; i
++, syms
++)
14792 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
14793 && ((*syms
)->value
& 1) != 0)
14795 (*syms
)->value
&= ~1;
14796 /* If the symbol has an odd size, it was probably computed
14797 incorrectly, so adjust that as well. */
14798 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14799 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14806 /* This function is called whenever a label is defined, including fake
14807 labels instantiated off the dot special symbol. It is used when
14808 handling branch delays; if a branch has a label, we assume we cannot
14809 move it. This also bumps the value of the symbol by 1 in compressed
14813 mips_record_label (symbolS
*sym
)
14815 segment_info_type
*si
= seg_info (now_seg
);
14816 struct insn_label_list
*l
;
14818 if (free_insn_labels
== NULL
)
14819 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14822 l
= free_insn_labels
;
14823 free_insn_labels
= l
->next
;
14827 l
->next
= si
->label_list
;
14828 si
->label_list
= l
;
14831 /* This function is called as tc_frob_label() whenever a label is defined
14832 and adds a DWARF-2 record we only want for true labels. */
14835 mips_define_label (symbolS
*sym
)
14837 mips_record_label (sym
);
14839 dwarf2_emit_label (sym
);
14843 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14845 /* Some special processing for a MIPS ELF file. */
14848 mips_elf_final_processing (void)
14850 /* Write out the register information. */
14851 if (mips_abi
!= N64_ABI
)
14855 s
.ri_gprmask
= mips_gprmask
;
14856 s
.ri_cprmask
[0] = mips_cprmask
[0];
14857 s
.ri_cprmask
[1] = mips_cprmask
[1];
14858 s
.ri_cprmask
[2] = mips_cprmask
[2];
14859 s
.ri_cprmask
[3] = mips_cprmask
[3];
14860 /* The gp_value field is set by the MIPS ELF backend. */
14862 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14863 ((Elf32_External_RegInfo
*)
14864 mips_regmask_frag
));
14868 Elf64_Internal_RegInfo s
;
14870 s
.ri_gprmask
= mips_gprmask
;
14872 s
.ri_cprmask
[0] = mips_cprmask
[0];
14873 s
.ri_cprmask
[1] = mips_cprmask
[1];
14874 s
.ri_cprmask
[2] = mips_cprmask
[2];
14875 s
.ri_cprmask
[3] = mips_cprmask
[3];
14876 /* The gp_value field is set by the MIPS ELF backend. */
14878 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14879 ((Elf64_External_RegInfo
*)
14880 mips_regmask_frag
));
14883 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14884 sort of BFD interface for this. */
14885 if (mips_any_noreorder
)
14886 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14887 if (mips_pic
!= NO_PIC
)
14889 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14890 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14893 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14895 /* Set MIPS ELF flags for ASEs. */
14896 /* We may need to define a new flag for DSP ASE, and set this flag when
14897 file_ase_dsp is true. */
14898 /* Same for DSP R2. */
14899 /* We may need to define a new flag for MT ASE, and set this flag when
14900 file_ase_mt is true. */
14901 if (file_ase_mips16
)
14902 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14903 #if 0 /* XXX FIXME */
14904 if (file_ase_mips3d
)
14905 elf_elfheader (stdoutput
)->e_flags
|= ???;
14908 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14910 /* Set the MIPS ELF ABI flags. */
14911 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14912 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14913 else if (mips_abi
== O64_ABI
)
14914 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14915 else if (mips_abi
== EABI_ABI
)
14917 if (!file_mips_gp32
)
14918 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14920 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14922 else if (mips_abi
== N32_ABI
)
14923 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14925 /* Nothing to do for N64_ABI. */
14927 if (mips_32bitmode
)
14928 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14930 #if 0 /* XXX FIXME */
14931 /* 32 bit code with 64 bit FP registers. */
14932 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14933 elf_elfheader (stdoutput
)->e_flags
|= ???;
14937 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14939 typedef struct proc
{
14941 symbolS
*func_end_sym
;
14942 unsigned long reg_mask
;
14943 unsigned long reg_offset
;
14944 unsigned long fpreg_mask
;
14945 unsigned long fpreg_offset
;
14946 unsigned long frame_offset
;
14947 unsigned long frame_reg
;
14948 unsigned long pc_reg
;
14951 static procS cur_proc
;
14952 static procS
*cur_proc_ptr
;
14953 static int numprocs
;
14955 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14959 mips_nop_opcode (void)
14961 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
14964 /* Fill in an rs_align_code fragment. This only needs to do something
14965 for MIPS16 code, where 0 is not a nop. */
14968 mips_handle_align (fragS
*fragp
)
14971 int bytes
, size
, excess
;
14974 if (fragp
->fr_type
!= rs_align_code
)
14977 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14980 opcode
= mips16_nop_insn
.insn_opcode
;
14985 opcode
= nop_insn
.insn_opcode
;
14989 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14990 excess
= bytes
% size
;
14993 /* If we're not inserting a whole number of instructions,
14994 pad the end of the fixed part of the frag with zeros. */
14995 memset (p
, 0, excess
);
14997 fragp
->fr_fix
+= excess
;
15000 md_number_to_chars (p
, opcode
, size
);
15001 fragp
->fr_var
= size
;
15005 md_obj_begin (void)
15012 /* Check for premature end, nesting errors, etc. */
15014 as_warn (_("missing .end at end of assembly"));
15023 if (*input_line_pointer
== '-')
15025 ++input_line_pointer
;
15028 if (!ISDIGIT (*input_line_pointer
))
15029 as_bad (_("expected simple number"));
15030 if (input_line_pointer
[0] == '0')
15032 if (input_line_pointer
[1] == 'x')
15034 input_line_pointer
+= 2;
15035 while (ISXDIGIT (*input_line_pointer
))
15038 val
|= hex_value (*input_line_pointer
++);
15040 return negative
? -val
: val
;
15044 ++input_line_pointer
;
15045 while (ISDIGIT (*input_line_pointer
))
15048 val
|= *input_line_pointer
++ - '0';
15050 return negative
? -val
: val
;
15053 if (!ISDIGIT (*input_line_pointer
))
15055 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15056 *input_line_pointer
, *input_line_pointer
);
15057 as_warn (_("invalid number"));
15060 while (ISDIGIT (*input_line_pointer
))
15063 val
+= *input_line_pointer
++ - '0';
15065 return negative
? -val
: val
;
15068 /* The .file directive; just like the usual .file directive, but there
15069 is an initial number which is the ECOFF file index. In the non-ECOFF
15070 case .file implies DWARF-2. */
15073 s_mips_file (int x ATTRIBUTE_UNUSED
)
15075 static int first_file_directive
= 0;
15077 if (ECOFF_DEBUGGING
)
15086 filename
= dwarf2_directive_file (0);
15088 /* Versions of GCC up to 3.1 start files with a ".file"
15089 directive even for stabs output. Make sure that this
15090 ".file" is handled. Note that you need a version of GCC
15091 after 3.1 in order to support DWARF-2 on MIPS. */
15092 if (filename
!= NULL
&& ! first_file_directive
)
15094 (void) new_logical_line (filename
, -1);
15095 s_app_file_string (filename
, 0);
15097 first_file_directive
= 1;
15101 /* The .loc directive, implying DWARF-2. */
15104 s_mips_loc (int x ATTRIBUTE_UNUSED
)
15106 if (!ECOFF_DEBUGGING
)
15107 dwarf2_directive_loc (0);
15110 /* The .end directive. */
15113 s_mips_end (int x ATTRIBUTE_UNUSED
)
15117 /* Following functions need their own .frame and .cprestore directives. */
15118 mips_frame_reg_valid
= 0;
15119 mips_cprestore_valid
= 0;
15121 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15124 demand_empty_rest_of_line ();
15129 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
15130 as_warn (_(".end not in text section"));
15134 as_warn (_(".end directive without a preceding .ent directive."));
15135 demand_empty_rest_of_line ();
15141 gas_assert (S_GET_NAME (p
));
15142 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
15143 as_warn (_(".end symbol does not match .ent symbol."));
15145 if (debug_type
== DEBUG_STABS
)
15146 stabs_generate_asm_endfunc (S_GET_NAME (p
),
15150 as_warn (_(".end directive missing or unknown symbol"));
15153 /* Create an expression to calculate the size of the function. */
15154 if (p
&& cur_proc_ptr
)
15156 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
15157 expressionS
*exp
= xmalloc (sizeof (expressionS
));
15160 exp
->X_op
= O_subtract
;
15161 exp
->X_add_symbol
= symbol_temp_new_now ();
15162 exp
->X_op_symbol
= p
;
15163 exp
->X_add_number
= 0;
15165 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
15168 /* Generate a .pdr section. */
15169 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
15171 segT saved_seg
= now_seg
;
15172 subsegT saved_subseg
= now_subseg
;
15176 #ifdef md_flush_pending_output
15177 md_flush_pending_output ();
15180 gas_assert (pdr_seg
);
15181 subseg_set (pdr_seg
, 0);
15183 /* Write the symbol. */
15184 exp
.X_op
= O_symbol
;
15185 exp
.X_add_symbol
= p
;
15186 exp
.X_add_number
= 0;
15187 emit_expr (&exp
, 4);
15189 fragp
= frag_more (7 * 4);
15191 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
15192 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
15193 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
15194 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
15195 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
15196 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
15197 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
15199 subseg_set (saved_seg
, saved_subseg
);
15201 #endif /* OBJ_ELF */
15203 cur_proc_ptr
= NULL
;
15206 /* The .aent and .ent directives. */
15209 s_mips_ent (int aent
)
15213 symbolP
= get_symbol ();
15214 if (*input_line_pointer
== ',')
15215 ++input_line_pointer
;
15216 SKIP_WHITESPACE ();
15217 if (ISDIGIT (*input_line_pointer
)
15218 || *input_line_pointer
== '-')
15221 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
15222 as_warn (_(".ent or .aent not in text section."));
15224 if (!aent
&& cur_proc_ptr
)
15225 as_warn (_("missing .end"));
15229 /* This function needs its own .frame and .cprestore directives. */
15230 mips_frame_reg_valid
= 0;
15231 mips_cprestore_valid
= 0;
15233 cur_proc_ptr
= &cur_proc
;
15234 memset (cur_proc_ptr
, '\0', sizeof (procS
));
15236 cur_proc_ptr
->func_sym
= symbolP
;
15240 if (debug_type
== DEBUG_STABS
)
15241 stabs_generate_asm_func (S_GET_NAME (symbolP
),
15242 S_GET_NAME (symbolP
));
15245 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
15247 demand_empty_rest_of_line ();
15250 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15251 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15252 s_mips_frame is used so that we can set the PDR information correctly.
15253 We can't use the ecoff routines because they make reference to the ecoff
15254 symbol table (in the mdebug section). */
15257 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
15260 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15264 if (cur_proc_ptr
== (procS
*) NULL
)
15266 as_warn (_(".frame outside of .ent"));
15267 demand_empty_rest_of_line ();
15271 cur_proc_ptr
->frame_reg
= tc_get_register (1);
15273 SKIP_WHITESPACE ();
15274 if (*input_line_pointer
++ != ','
15275 || get_absolute_expression_and_terminator (&val
) != ',')
15277 as_warn (_("Bad .frame directive"));
15278 --input_line_pointer
;
15279 demand_empty_rest_of_line ();
15283 cur_proc_ptr
->frame_offset
= val
;
15284 cur_proc_ptr
->pc_reg
= tc_get_register (0);
15286 demand_empty_rest_of_line ();
15289 #endif /* OBJ_ELF */
15293 /* The .fmask and .mask directives. If the mdebug section is present
15294 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15295 embedded targets, s_mips_mask is used so that we can set the PDR
15296 information correctly. We can't use the ecoff routines because they
15297 make reference to the ecoff symbol table (in the mdebug section). */
15300 s_mips_mask (int reg_type
)
15303 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15307 if (cur_proc_ptr
== (procS
*) NULL
)
15309 as_warn (_(".mask/.fmask outside of .ent"));
15310 demand_empty_rest_of_line ();
15314 if (get_absolute_expression_and_terminator (&mask
) != ',')
15316 as_warn (_("Bad .mask/.fmask directive"));
15317 --input_line_pointer
;
15318 demand_empty_rest_of_line ();
15322 off
= get_absolute_expression ();
15324 if (reg_type
== 'F')
15326 cur_proc_ptr
->fpreg_mask
= mask
;
15327 cur_proc_ptr
->fpreg_offset
= off
;
15331 cur_proc_ptr
->reg_mask
= mask
;
15332 cur_proc_ptr
->reg_offset
= off
;
15335 demand_empty_rest_of_line ();
15338 #endif /* OBJ_ELF */
15339 s_ignore (reg_type
);
15342 /* A table describing all the processors gas knows about. Names are
15343 matched in the order listed.
15345 To ease comparison, please keep this table in the same order as
15346 gcc's mips_cpu_info_table[]. */
15347 static const struct mips_cpu_info mips_cpu_info_table
[] =
15349 /* Entries for generic ISAs */
15350 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
15351 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
15352 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
15353 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
15354 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
15355 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
15356 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15357 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
15358 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
15361 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
15362 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
15363 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
15366 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
15369 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
15370 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
15371 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
15372 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
15373 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
15374 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
15375 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
15376 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
15377 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
15378 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
15379 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
15380 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
15381 /* ST Microelectronics Loongson 2E and 2F cores */
15382 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
15383 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
15386 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
15387 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
15388 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
15389 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
15390 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
15391 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
15392 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
15393 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
15394 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
15395 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15396 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15397 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15398 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15399 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15400 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15403 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15404 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15405 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15406 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15408 /* MIPS 32 Release 2 */
15409 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15410 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15411 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15412 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15413 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15414 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15415 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15416 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15417 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15418 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15419 /* Deprecated forms of the above. */
15420 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15421 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15422 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15423 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15424 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15425 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15426 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15427 /* Deprecated forms of the above. */
15428 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15429 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15430 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15431 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15432 ISA_MIPS32R2
, CPU_MIPS32R2
},
15433 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15434 ISA_MIPS32R2
, CPU_MIPS32R2
},
15435 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15436 ISA_MIPS32R2
, CPU_MIPS32R2
},
15437 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15438 ISA_MIPS32R2
, CPU_MIPS32R2
},
15439 /* Deprecated forms of the above. */
15440 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15441 ISA_MIPS32R2
, CPU_MIPS32R2
},
15442 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15443 ISA_MIPS32R2
, CPU_MIPS32R2
},
15444 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15445 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15446 ISA_MIPS32R2
, CPU_MIPS32R2
},
15447 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15448 ISA_MIPS32R2
, CPU_MIPS32R2
},
15449 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15450 ISA_MIPS32R2
, CPU_MIPS32R2
},
15451 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15452 ISA_MIPS32R2
, CPU_MIPS32R2
},
15453 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15454 ISA_MIPS32R2
, CPU_MIPS32R2
},
15455 /* Deprecated forms of the above. */
15456 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15457 ISA_MIPS32R2
, CPU_MIPS32R2
},
15458 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15459 ISA_MIPS32R2
, CPU_MIPS32R2
},
15460 /* 1004K cores are multiprocessor versions of the 34K. */
15461 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15462 ISA_MIPS32R2
, CPU_MIPS32R2
},
15463 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15464 ISA_MIPS32R2
, CPU_MIPS32R2
},
15465 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15466 ISA_MIPS32R2
, CPU_MIPS32R2
},
15467 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15468 ISA_MIPS32R2
, CPU_MIPS32R2
},
15471 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15472 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15473 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15474 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15476 /* Broadcom SB-1 CPU core */
15477 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15478 ISA_MIPS64
, CPU_SB1
},
15479 /* Broadcom SB-1A CPU core */
15480 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15481 ISA_MIPS64
, CPU_SB1
},
15483 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
15485 /* MIPS 64 Release 2 */
15487 /* Cavium Networks Octeon CPU core */
15488 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15491 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
15498 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15499 with a final "000" replaced by "k". Ignore case.
15501 Note: this function is shared between GCC and GAS. */
15504 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15506 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15507 given
++, canonical
++;
15509 return ((*given
== 0 && *canonical
== 0)
15510 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15514 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15515 CPU name. We've traditionally allowed a lot of variation here.
15517 Note: this function is shared between GCC and GAS. */
15520 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15522 /* First see if the name matches exactly, or with a final "000"
15523 turned into "k". */
15524 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15527 /* If not, try comparing based on numerical designation alone.
15528 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15529 if (TOLOWER (*given
) == 'r')
15531 if (!ISDIGIT (*given
))
15534 /* Skip over some well-known prefixes in the canonical name,
15535 hoping to find a number there too. */
15536 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15538 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15540 else if (TOLOWER (canonical
[0]) == 'r')
15543 return mips_strict_matching_cpu_name_p (canonical
, given
);
15547 /* Parse an option that takes the name of a processor as its argument.
15548 OPTION is the name of the option and CPU_STRING is the argument.
15549 Return the corresponding processor enumeration if the CPU_STRING is
15550 recognized, otherwise report an error and return null.
15552 A similar function exists in GCC. */
15554 static const struct mips_cpu_info
*
15555 mips_parse_cpu (const char *option
, const char *cpu_string
)
15557 const struct mips_cpu_info
*p
;
15559 /* 'from-abi' selects the most compatible architecture for the given
15560 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15561 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15562 version. Look first at the -mgp options, if given, otherwise base
15563 the choice on MIPS_DEFAULT_64BIT.
15565 Treat NO_ABI like the EABIs. One reason to do this is that the
15566 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15567 architecture. This code picks MIPS I for 'mips' and MIPS III for
15568 'mips64', just as we did in the days before 'from-abi'. */
15569 if (strcasecmp (cpu_string
, "from-abi") == 0)
15571 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15572 return mips_cpu_info_from_isa (ISA_MIPS1
);
15574 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15575 return mips_cpu_info_from_isa (ISA_MIPS3
);
15577 if (file_mips_gp32
>= 0)
15578 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15580 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15585 /* 'default' has traditionally been a no-op. Probably not very useful. */
15586 if (strcasecmp (cpu_string
, "default") == 0)
15589 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15590 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15593 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
15597 /* Return the canonical processor information for ISA (a member of the
15598 ISA_MIPS* enumeration). */
15600 static const struct mips_cpu_info
*
15601 mips_cpu_info_from_isa (int isa
)
15605 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15606 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15607 && isa
== mips_cpu_info_table
[i
].isa
)
15608 return (&mips_cpu_info_table
[i
]);
15613 static const struct mips_cpu_info
*
15614 mips_cpu_info_from_arch (int arch
)
15618 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15619 if (arch
== mips_cpu_info_table
[i
].cpu
)
15620 return (&mips_cpu_info_table
[i
]);
15626 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15630 fprintf (stream
, "%24s", "");
15635 fprintf (stream
, ", ");
15639 if (*col_p
+ strlen (string
) > 72)
15641 fprintf (stream
, "\n%24s", "");
15645 fprintf (stream
, "%s", string
);
15646 *col_p
+= strlen (string
);
15652 md_show_usage (FILE *stream
)
15657 fprintf (stream
, _("\
15659 -EB generate big endian output\n\
15660 -EL generate little endian output\n\
15661 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15662 -G NUM allow referencing objects up to NUM bytes\n\
15663 implicitly with the gp register [default 8]\n"));
15664 fprintf (stream
, _("\
15665 -mips1 generate MIPS ISA I instructions\n\
15666 -mips2 generate MIPS ISA II instructions\n\
15667 -mips3 generate MIPS ISA III instructions\n\
15668 -mips4 generate MIPS ISA IV instructions\n\
15669 -mips5 generate MIPS ISA V instructions\n\
15670 -mips32 generate MIPS32 ISA instructions\n\
15671 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15672 -mips64 generate MIPS64 ISA instructions\n\
15673 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15674 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15678 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15679 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15680 show (stream
, "from-abi", &column
, &first
);
15681 fputc ('\n', stream
);
15683 fprintf (stream
, _("\
15684 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15685 -no-mCPU don't generate code specific to CPU.\n\
15686 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15690 show (stream
, "3900", &column
, &first
);
15691 show (stream
, "4010", &column
, &first
);
15692 show (stream
, "4100", &column
, &first
);
15693 show (stream
, "4650", &column
, &first
);
15694 fputc ('\n', stream
);
15696 fprintf (stream
, _("\
15697 -mips16 generate mips16 instructions\n\
15698 -no-mips16 do not generate mips16 instructions\n"));
15699 fprintf (stream
, _("\
15700 -msmartmips generate smartmips instructions\n\
15701 -mno-smartmips do not generate smartmips instructions\n"));
15702 fprintf (stream
, _("\
15703 -mdsp generate DSP instructions\n\
15704 -mno-dsp do not generate DSP instructions\n"));
15705 fprintf (stream
, _("\
15706 -mdspr2 generate DSP R2 instructions\n\
15707 -mno-dspr2 do not generate DSP R2 instructions\n"));
15708 fprintf (stream
, _("\
15709 -mmt generate MT instructions\n\
15710 -mno-mt do not generate MT instructions\n"));
15711 fprintf (stream
, _("\
15712 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15713 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15714 -mfix-vr4120 work around certain VR4120 errata\n\
15715 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15716 -mfix-24k insert a nop after ERET and DERET instructions\n\
15717 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15718 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15719 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15720 -msym32 assume all symbols have 32-bit values\n\
15721 -O0 remove unneeded NOPs, do not swap branches\n\
15722 -O remove unneeded NOPs and swap branches\n\
15723 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15724 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15725 fprintf (stream
, _("\
15726 -mhard-float allow floating-point instructions\n\
15727 -msoft-float do not allow floating-point instructions\n\
15728 -msingle-float only allow 32-bit floating-point operations\n\
15729 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15730 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15733 fprintf (stream
, _("\
15734 -KPIC, -call_shared generate SVR4 position independent code\n\
15735 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15736 -mvxworks-pic generate VxWorks position independent code\n\
15737 -non_shared do not generate code that can operate with DSOs\n\
15738 -xgot assume a 32 bit GOT\n\
15739 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15740 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15741 position dependent (non shared) code\n\
15742 -mabi=ABI create ABI conformant object file for:\n"));
15746 show (stream
, "32", &column
, &first
);
15747 show (stream
, "o64", &column
, &first
);
15748 show (stream
, "n32", &column
, &first
);
15749 show (stream
, "64", &column
, &first
);
15750 show (stream
, "eabi", &column
, &first
);
15752 fputc ('\n', stream
);
15754 fprintf (stream
, _("\
15755 -32 create o32 ABI object file (default)\n\
15756 -n32 create n32 ABI object file\n\
15757 -64 create 64 ABI object file\n"));
15763 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
15765 if (HAVE_64BIT_SYMBOLS
)
15766 return dwarf2_format_64bit_irix
;
15768 return dwarf2_format_32bit
;
15773 mips_dwarf2_addr_size (void)
15775 if (HAVE_64BIT_OBJECTS
)
15781 /* Standard calling conventions leave the CFA at SP on entry. */
15783 mips_cfi_frame_initial_instructions (void)
15785 cfi_add_CFA_def_cfa_register (SP
);
15789 tc_mips_regname_to_dw2regnum (char *regname
)
15791 unsigned int regnum
= -1;
15794 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))