1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* Whether the processor uses hardware interlocks, and thus does not
152 require nops to be inserted. */
153 static int interlocks
= -1;
155 /* As with "interlocks" this is used by hardware that has FP
156 (co-processor) interlocks. */
157 static int cop_interlocks
= -1;
159 /* MIPS PIC level. */
163 /* Do not generate PIC code. */
166 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
167 not sure what it is supposed to do. */
170 /* Generate PIC code as in the SVR4 MIPS ABI. */
173 /* Generate PIC code without using a global offset table: the data
174 segment has a maximum size of 64K, all data references are off
175 the $gp register, and all text references are PC relative. This
176 is used on some embedded systems. */
180 static enum mips_pic_level mips_pic
;
182 /* 1 if we should generate 32 bit offsets from the GP register in
183 SVR4_PIC mode. Currently has no meaning in other modes. */
184 static int mips_big_got
;
186 /* 1 if trap instructions should used for overflow rather than break
188 static int mips_trap
;
190 /* 1 if we should autoextend mips16 instructions. */
191 static int mips16_autoextend
= 1;
193 static int mips_warn_about_macros
;
194 static int mips_noreorder
;
195 static int mips_any_noreorder
;
196 static int mips_nomove
;
197 static int mips_noat
;
198 static int mips_nobopt
;
200 /* The size of the small data section. */
201 static int g_switch_value
= 8;
202 /* Whether the -G option was used. */
203 static int g_switch_seen
= 0;
208 /* If we can determine in advance that GP optimization won't be
209 possible, we can skip the relaxation stuff that tries to produce
210 GP-relative references. This makes delay slot optimization work
213 This function can only provide a guess, but it seems to work for
214 gcc output. If it guesses wrong, the only loss should be in
215 efficiency; it shouldn't introduce any bugs.
217 I don't know if a fix is needed for the SVR4_PIC mode. I've only
218 fixed it for the non-PIC mode. KR 95/04/07 */
219 static int nopic_need_relax
PARAMS ((symbolS
*));
221 /* handle of the OPCODE hash table */
222 static struct hash_control
*op_hash
= NULL
;
224 /* The opcode hash table we use for the mips16. */
225 static struct hash_control
*mips16_op_hash
= NULL
;
227 /* This array holds the chars that always start a comment. If the
228 pre-processor is disabled, these aren't very useful */
229 const char comment_chars
[] = "#";
231 /* This array holds the chars that only start a comment at the beginning of
232 a line. If the line seems to have the form '# 123 filename'
233 .line and .file directives will appear in the pre-processed output */
234 /* Note that input_file.c hand checks for '#' at the beginning of the
235 first line of the input file. This is because the compiler outputs
236 #NO_APP at the beginning of its output. */
237 /* Also note that C style comments are always supported. */
238 const char line_comment_chars
[] = "#";
240 /* This array holds machine specific line separator characters. */
241 const char line_separator_chars
[] = "";
243 /* Chars that can be used to separate mant from exp in floating point nums */
244 const char EXP_CHARS
[] = "eE";
246 /* Chars that mean this number is a floating point constant */
249 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
251 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
252 changed in read.c . Ideally it shouldn't have to know about it at all,
253 but nothing is ideal around here.
256 static char *insn_error
;
258 static int byte_order
;
260 static int auto_align
= 1;
262 /* Symbol labelling the current insn. */
263 static symbolS
*insn_label
;
265 /* When outputting SVR4 PIC code, the assembler needs to know the
266 offset in the stack frame from which to restore the $gp register.
267 This is set by the .cprestore pseudo-op, and saved in this
269 static offsetT mips_cprestore_offset
= -1;
271 /* This is the register which holds the stack frame, as set by the
272 .frame pseudo-op. This is needed to implement .cprestore. */
273 static int mips_frame_reg
= SP
;
275 /* To output NOP instructions correctly, we need to keep information
276 about the previous two instructions. */
278 /* Whether we are optimizing. The default value of 2 means to remove
279 unneeded NOPs and swap branch instructions when possible. A value
280 of 1 means to not swap branches. A value of 0 means to always
282 static int mips_optimize
= 2;
284 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
285 equivalent to seeing no -g option at all. */
286 static int mips_debug
= 0;
288 /* The previous instruction. */
289 static struct mips_cl_insn prev_insn
;
291 /* The instruction before prev_insn. */
292 static struct mips_cl_insn prev_prev_insn
;
294 /* If we don't want information for prev_insn or prev_prev_insn, we
295 point the insn_mo field at this dummy integer. */
296 static const struct mips_opcode dummy_opcode
= { 0 };
298 /* Non-zero if prev_insn is valid. */
299 static int prev_insn_valid
;
301 /* The frag for the previous instruction. */
302 static struct frag
*prev_insn_frag
;
304 /* The offset into prev_insn_frag for the previous instruction. */
305 static long prev_insn_where
;
307 /* The reloc for the previous instruction, if any. */
308 static fixS
*prev_insn_fixp
;
310 /* Non-zero if the previous instruction was in a delay slot. */
311 static int prev_insn_is_delay_slot
;
313 /* Non-zero if the previous instruction was in a .set noreorder. */
314 static int prev_insn_unreordered
;
316 /* Non-zero if the previous instruction uses an extend opcode (if
318 static int prev_insn_extended
;
320 /* Non-zero if the previous previous instruction was in a .set
322 static int prev_prev_insn_unreordered
;
324 /* For ECOFF and ELF, relocations against symbols are done in two
325 parts, with a HI relocation and a LO relocation. Each relocation
326 has only 16 bits of space to store an addend. This means that in
327 order for the linker to handle carries correctly, it must be able
328 to locate both the HI and the LO relocation. This means that the
329 relocations must appear in order in the relocation table.
331 In order to implement this, we keep track of each unmatched HI
332 relocation. We then sort them so that they immediately precede the
333 corresponding LO relocation. */
338 struct mips_hi_fixup
*next
;
341 /* The section this fixup is in. */
345 /* The list of unmatched HI relocs. */
347 static struct mips_hi_fixup
*mips_hi_fixup_list
;
349 /* Map normal MIPS register numbers to mips16 register numbers. */
351 #define X ILLEGAL_REG
352 static const int mips32_to_16_reg_map
[] =
354 X
, X
, 2, 3, 4, 5, 6, 7,
355 X
, X
, X
, X
, X
, X
, X
, X
,
356 0, 1, X
, X
, X
, X
, X
, X
,
357 X
, X
, X
, X
, X
, X
, X
, X
361 /* Map mips16 register numbers to normal MIPS register numbers. */
363 static const int mips16_to_32_reg_map
[] =
365 16, 17, 2, 3, 4, 5, 6, 7
368 /* Since the MIPS does not have multiple forms of PC relative
369 instructions, we do not have to do relaxing as is done on other
370 platforms. However, we do have to handle GP relative addressing
371 correctly, which turns out to be a similar problem.
373 Every macro that refers to a symbol can occur in (at least) two
374 forms, one with GP relative addressing and one without. For
375 example, loading a global variable into a register generally uses
376 a macro instruction like this:
378 If i can be addressed off the GP register (this is true if it is in
379 the .sbss or .sdata section, or if it is known to be smaller than
380 the -G argument) this will generate the following instruction:
382 This instruction will use a GPREL reloc. If i can not be addressed
383 off the GP register, the following instruction sequence will be used:
386 In this case the first instruction will have a HI16 reloc, and the
387 second reloc will have a LO16 reloc. Both relocs will be against
390 The issue here is that we may not know whether i is GP addressable
391 until after we see the instruction that uses it. Therefore, we
392 want to be able to choose the final instruction sequence only at
393 the end of the assembly. This is similar to the way other
394 platforms choose the size of a PC relative instruction only at the
397 When generating position independent code we do not use GP
398 addressing in quite the same way, but the issue still arises as
399 external symbols and local symbols must be handled differently.
401 We handle these issues by actually generating both possible
402 instruction sequences. The longer one is put in a frag_var with
403 type rs_machine_dependent. We encode what to do with the frag in
404 the subtype field. We encode (1) the number of existing bytes to
405 replace, (2) the number of new bytes to use, (3) the offset from
406 the start of the existing bytes to the first reloc we must generate
407 (that is, the offset is applied from the start of the existing
408 bytes after they are replaced by the new bytes, if any), (4) the
409 offset from the start of the existing bytes to the second reloc,
410 (5) whether a third reloc is needed (the third reloc is always four
411 bytes after the second reloc), and (6) whether to warn if this
412 variant is used (this is sometimes needed if .set nomacro or .set
413 noat is in effect). All these numbers are reasonably small.
415 Generating two instruction sequences must be handled carefully to
416 ensure that delay slots are handled correctly. Fortunately, there
417 are a limited number of cases. When the second instruction
418 sequence is generated, append_insn is directed to maintain the
419 existing delay slot information, so it continues to apply to any
420 code after the second instruction sequence. This means that the
421 second instruction sequence must not impose any requirements not
422 required by the first instruction sequence.
424 These variant frags are then handled in functions called by the
425 machine independent code. md_estimate_size_before_relax returns
426 the final size of the frag. md_convert_frag sets up the final form
427 of the frag. tc_gen_reloc adjust the first reloc and adds a second
429 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
433 | (((reloc1) + 64) << 9) \
434 | (((reloc2) + 64) << 2) \
435 | ((reloc3) ? (1 << 1) : 0) \
437 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
438 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
439 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
440 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
441 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
442 #define RELAX_WARN(i) ((i) & 1)
444 /* For mips16 code, we use an entirely different form of relaxation.
445 mips16 supports two versions of most instructions which take
446 immediate values: a small one which takes some small value, and a
447 larger one which takes a 16 bit value. Since branches also follow
448 this pattern, relaxing these values is required.
450 We can assemble both mips16 and normal MIPS code in a single
451 object. Therefore, we need to support this type of relaxation at
452 the same time that we support the relaxation described above. We
453 use the high bit of the subtype field to distinguish these cases.
455 The information we store for this type of relaxation is simply the
456 argument code found in the opcode file for this relocation, and
457 whether the user explicitly requested a small or extended form.
458 That tells us the size of the value, and how it should be stored.
459 We also store whether the fragment is considered to be extended or
460 not. We also store whether this is known to be a branch to a
461 different section, whether we have tried to relax this frag yet,
462 and whether we have ever extended a PC relative fragment because of
464 #define RELAX_MIPS16_ENCODE(type, small, ext) \
467 | ((small) ? 0x100 : 0) \
468 | ((ext) ? 0x200 : 0))
469 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
470 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
471 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
472 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
473 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x400) != 0)
474 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x400)
475 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x400)
476 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x800) != 0)
477 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x800)
478 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x800)
480 /* Prototypes for static functions. */
483 #define internalError() \
484 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
486 #define internalError() as_fatal ("MIPS internal Error");
489 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
491 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
492 unsigned int reg
, enum mips_regclass
class));
493 static int reg_needs_delay
PARAMS ((int));
494 static void append_insn
PARAMS ((char *place
,
495 struct mips_cl_insn
* ip
,
497 bfd_reloc_code_real_type r
,
499 static void mips_no_prev_insn
PARAMS ((void));
500 static void mips_emit_delays
PARAMS ((void));
502 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
503 const char *name
, const char *fmt
,
506 static void macro_build ();
508 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
509 const char *, const char *,
511 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
512 expressionS
* ep
, int regnum
));
513 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
514 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
516 static void load_register
PARAMS ((int *, int, expressionS
*, int));
517 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
518 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
519 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
520 #ifdef LOSING_COMPILER
521 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
523 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
524 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
525 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
526 boolean
, boolean
, unsigned long *,
527 boolean
*, unsigned short *));
528 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
529 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
530 static symbolS
*get_symbol
PARAMS ((void));
531 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
532 static void s_align
PARAMS ((int));
533 static void s_change_sec
PARAMS ((int));
534 static void s_cons
PARAMS ((int));
535 static void s_float_cons
PARAMS ((int));
536 static void s_mips_globl
PARAMS ((int));
537 static void s_option
PARAMS ((int));
538 static void s_mipsset
PARAMS ((int));
539 static void s_abicalls
PARAMS ((int));
540 static void s_cpload
PARAMS ((int));
541 static void s_cprestore
PARAMS ((int));
542 static void s_gpword
PARAMS ((int));
543 static void s_cpadd
PARAMS ((int));
544 static void md_obj_begin
PARAMS ((void));
545 static void md_obj_end
PARAMS ((void));
546 static long get_number
PARAMS ((void));
547 static void s_ent
PARAMS ((int));
548 static void s_mipsend
PARAMS ((int));
549 static void s_file
PARAMS ((int));
550 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
554 The following pseudo-ops from the Kane and Heinrich MIPS book
555 should be defined here, but are currently unsupported: .alias,
556 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
558 The following pseudo-ops from the Kane and Heinrich MIPS book are
559 specific to the type of debugging information being generated, and
560 should be defined by the object format: .aent, .begin, .bend,
561 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
564 The following pseudo-ops from the Kane and Heinrich MIPS book are
565 not MIPS CPU specific, but are also not specific to the object file
566 format. This file is probably the best place to define them, but
567 they are not currently supported: .asm0, .endr, .lab, .repeat,
568 .struct, .weakext. */
570 static const pseudo_typeS mips_pseudo_table
[] =
572 /* MIPS specific pseudo-ops. */
573 {"option", s_option
, 0},
574 {"set", s_mipsset
, 0},
575 {"rdata", s_change_sec
, 'r'},
576 {"sdata", s_change_sec
, 's'},
577 {"livereg", s_ignore
, 0},
578 {"abicalls", s_abicalls
, 0},
579 {"cpload", s_cpload
, 0},
580 {"cprestore", s_cprestore
, 0},
581 {"gpword", s_gpword
, 0},
582 {"cpadd", s_cpadd
, 0},
584 /* Relatively generic pseudo-ops that happen to be used on MIPS
586 {"asciiz", stringer
, 1},
587 {"bss", s_change_sec
, 'b'},
590 {"dword", s_cons
, 3},
592 /* These pseudo-ops are defined in read.c, but must be overridden
593 here for one reason or another. */
594 {"align", s_align
, 0},
596 {"data", s_change_sec
, 'd'},
597 {"double", s_float_cons
, 'd'},
598 {"float", s_float_cons
, 'f'},
599 {"globl", s_mips_globl
, 0},
600 {"global", s_mips_globl
, 0},
601 {"hword", s_cons
, 1},
606 {"short", s_cons
, 1},
607 {"single", s_float_cons
, 'f'},
608 {"text", s_change_sec
, 't'},
613 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
614 /* These pseudo-ops should be defined by the object file format.
615 However, a.out doesn't support them, so we have versions here. */
617 {"bgnb", s_ignore
, 0},
618 {"end", s_mipsend
, 0},
619 {"endb", s_ignore
, 0},
622 {"fmask", s_ignore
, 'F'},
623 {"frame", s_ignore
, 0},
624 {"loc", s_ignore
, 0},
625 {"mask", s_ignore
, 'R'},
626 {"verstamp", s_ignore
, 0},
630 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
635 pop_insert (mips_pseudo_table
);
636 if (! ECOFF_DEBUGGING
)
637 pop_insert (mips_nonecoff_pseudo_table
);
640 static char *expr_end
;
642 /* Expressions which appear in instructions. These are set by
645 static expressionS imm_expr
;
646 static expressionS offset_expr
;
648 /* Relocs associated with imm_expr and offset_expr. */
650 static bfd_reloc_code_real_type imm_reloc
;
651 static bfd_reloc_code_real_type offset_reloc
;
653 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
655 static boolean imm_unmatched_hi
;
657 /* These are set by mips16_ip if an explicit extension is used. */
659 static boolean mips16_small
, mips16_ext
;
662 * This function is called once, at assembler startup time. It should
663 * set up all the tables, etc. that the MD part of the assembler will need.
669 register const char *retval
= NULL
;
670 register unsigned int i
= 0;
678 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
680 a
= xmalloc (sizeof TARGET_CPU
);
681 strcpy (a
, TARGET_CPU
);
682 a
[(sizeof TARGET_CPU
) - 3] = '\0';
686 if (strcmp (cpu
, "mips") == 0)
692 else if (strcmp (cpu
, "r6000") == 0
693 || strcmp (cpu
, "mips2") == 0)
699 else if (strcmp (cpu
, "mips64") == 0
700 || strcmp (cpu
, "r4000") == 0
701 || strcmp (cpu
, "mips3") == 0)
707 else if (strcmp (cpu
, "r4400") == 0)
713 else if (strcmp (cpu
, "mips64orion") == 0
714 || strcmp (cpu
, "r4600") == 0)
720 else if (strcmp (cpu
, "r4650") == 0)
728 else if (strcmp (cpu
, "mips64vr4300") == 0)
734 else if (strcmp (cpu
, "mips64vr4100") == 0)
742 else if (strcmp (cpu
, "r4010") == 0)
750 else if (strcmp (cpu
, "r5000") == 0
751 || strcmp (cpu
, "mips64vr5000") == 0)
757 else if (strcmp (cpu
, "r8000") == 0
758 || strcmp (cpu
, "mips4") == 0)
764 else if (strcmp (cpu
, "r10000") == 0)
770 else if (strcmp (cpu
, "mips16") == 0)
774 mips_cpu
= 0; /* FIXME */
789 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
804 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
809 if (mips_cpu
== 4300)
814 if (mips_isa
< 2 && mips_trap
)
815 as_bad ("trap exception not supported at ISA 1");
820 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
823 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
826 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
829 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
833 as_warn ("Could not set architecture and machine");
835 file_mips_isa
= mips_isa
;
837 op_hash
= hash_new ();
839 for (i
= 0; i
< NUMOPCODES
;)
841 const char *name
= mips_opcodes
[i
].name
;
843 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
846 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
847 mips_opcodes
[i
].name
, retval
);
848 as_fatal ("Broken assembler. No assembly attempted.");
852 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
853 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
854 != mips_opcodes
[i
].match
))
856 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
857 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
858 as_fatal ("Broken assembler. No assembly attempted.");
862 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
865 mips16_op_hash
= hash_new ();
868 while (i
< bfd_mips16_num_opcodes
)
870 const char *name
= mips16_opcodes
[i
].name
;
872 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
874 as_fatal ("internal error: can't hash `%s': %s\n",
875 mips16_opcodes
[i
].name
, retval
);
878 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
879 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
880 != mips16_opcodes
[i
].match
))
881 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
882 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
885 while (i
< bfd_mips16_num_opcodes
886 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
889 mips_no_prev_insn ();
897 /* set the default alignment for the text section (2**2) */
898 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
899 record_alignment (text_section
, 2);
901 if (USE_GLOBAL_POINTER_OPT
)
902 bfd_set_gp_size (stdoutput
, g_switch_value
);
904 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
906 /* On a native system, sections must be aligned to 16 byte
907 boundaries. When configured for an embedded ELF target, we
909 if (strcmp (TARGET_OS
, "elf") != 0)
911 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
912 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
913 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
916 /* Create a .reginfo section for register masks and a .mdebug
917 section for debugging information. */
928 sec
= subseg_new (".reginfo", (subsegT
) 0);
930 /* The ABI says this section should be loaded so that the
931 running program can access it. */
932 (void) bfd_set_section_flags (stdoutput
, sec
,
933 (SEC_ALLOC
| SEC_LOAD
934 | SEC_READONLY
| SEC_DATA
));
935 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
938 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
943 /* The 64-bit ABI uses a .MIPS.options section rather than
945 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
946 (void) bfd_set_section_flags (stdoutput
, sec
,
947 (SEC_ALLOC
| SEC_LOAD
948 | SEC_READONLY
| SEC_DATA
));
949 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
952 /* Set up the option header. */
954 Elf_Internal_Options opthdr
;
957 opthdr
.kind
= ODK_REGINFO
;
958 opthdr
.size
= (sizeof (Elf_External_Options
)
959 + sizeof (Elf64_External_RegInfo
));
962 f
= frag_more (sizeof (Elf_External_Options
));
963 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
964 (Elf_External_Options
*) f
);
966 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
973 sec
= subseg_new (".mdebug", (subsegT
) 0);
974 (void) bfd_set_section_flags (stdoutput
, sec
,
975 SEC_HAS_CONTENTS
| SEC_READONLY
);
976 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
979 subseg_set (seg
, subseg
);
983 if (! ECOFF_DEBUGGING
)
990 if (! ECOFF_DEBUGGING
)
998 struct mips_cl_insn insn
;
1000 imm_expr
.X_op
= O_absent
;
1001 imm_reloc
= BFD_RELOC_UNUSED
;
1002 imm_unmatched_hi
= false;
1003 offset_expr
.X_op
= O_absent
;
1004 offset_reloc
= BFD_RELOC_UNUSED
;
1007 mips16_ip (str
, &insn
);
1009 mips_ip (str
, &insn
);
1013 as_bad ("%s `%s'", insn_error
, str
);
1017 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1020 mips16_macro (&insn
);
1026 if (imm_expr
.X_op
!= O_absent
)
1027 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1029 else if (offset_expr
.X_op
!= O_absent
)
1030 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1032 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1036 /* See whether instruction IP reads register REG. CLASS is the type
1040 insn_uses_reg (ip
, reg
, class)
1041 struct mips_cl_insn
*ip
;
1043 enum mips_regclass
class;
1045 if (class == MIPS16_REG
)
1048 reg
= mips16_to_32_reg_map
[reg
];
1049 class = MIPS_GR_REG
;
1052 /* Don't report on general register 0, since it never changes. */
1053 if (class == MIPS_GR_REG
&& reg
== 0)
1056 if (class == MIPS_FP_REG
)
1059 /* If we are called with either $f0 or $f1, we must check $f0.
1060 This is not optimal, because it will introduce an unnecessary
1061 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1062 need to distinguish reading both $f0 and $f1 or just one of
1063 them. Note that we don't have to check the other way,
1064 because there is no instruction that sets both $f0 and $f1
1065 and requires a delay. */
1066 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1067 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1068 == (reg
&~ (unsigned) 1)))
1070 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1071 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1072 == (reg
&~ (unsigned) 1)))
1077 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1078 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1080 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1081 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1086 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1087 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1089 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1090 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1092 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1093 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1094 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1096 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1098 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1100 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1102 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1103 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1104 & MIPS16OP_MASK_REGR32
) == reg
)
1111 /* This function returns true if modifying a register requires a
1115 reg_needs_delay (reg
)
1118 unsigned long prev_pinfo
;
1120 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1121 if (! mips_noreorder
1123 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1125 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1127 /* A load from a coprocessor or from memory. All load
1128 delays delay the use of general register rt for one
1129 instruction on the r3000. The r6000 and r4000 use
1131 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1132 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1139 /* Output an instruction. PLACE is where to put the instruction; if
1140 it is NULL, this uses frag_more to get room. IP is the instruction
1141 information. ADDRESS_EXPR is an operand of the instruction to be
1142 used with RELOC_TYPE. */
1145 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1147 struct mips_cl_insn
*ip
;
1148 expressionS
*address_expr
;
1149 bfd_reloc_code_real_type reloc_type
;
1150 boolean unmatched_hi
;
1152 register unsigned long prev_pinfo
, pinfo
;
1157 /* Make sure the section will be aligned appropriately. Note that
1158 we do not insert an alignment directive; it remains the user's
1159 responsibility to align instructions if necessary. Here we only
1160 ensure that the section will have the right default alignment, so
1161 that the right thing will happen if no alignment directive is
1164 record_alignment (now_seg
, 1);
1166 record_alignment (now_seg
, 2);
1168 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1169 pinfo
= ip
->insn_mo
->pinfo
;
1171 if (place
== NULL
&& ! mips_noreorder
)
1173 /* If the previous insn required any delay slots, see if we need
1174 to insert a NOP or two. There are eight kinds of possible
1175 hazards, of which an instruction can have at most one type.
1176 (1) a load from memory delay
1177 (2) a load from a coprocessor delay
1178 (3) an unconditional branch delay
1179 (4) a conditional branch delay
1180 (5) a move to coprocessor register delay
1181 (6) a load coprocessor register from memory delay
1182 (7) a coprocessor condition code delay
1183 (8) a HI/LO special register delay
1185 There are a lot of optimizations we could do that we don't.
1186 In particular, we do not, in general, reorder instructions.
1187 If you use gcc with optimization, it will reorder
1188 instructions and generally do much more optimization then we
1189 do here; repeating all that work in the assembler would only
1190 benefit hand written assembly code, and does not seem worth
1193 /* This is how a NOP is emitted. */
1194 #define emit_nop() \
1196 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1197 : md_number_to_chars (frag_more (4), 0, 4))
1199 /* The previous insn might require a delay slot, depending upon
1200 the contents of the current insn. */
1203 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1204 && ! cop_interlocks
)
1206 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1208 /* A load from a coprocessor or from memory. All load
1209 delays delay the use of general register rt for one
1210 instruction on the r3000. The r6000 and r4000 use
1212 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1213 if (mips_optimize
== 0
1214 || insn_uses_reg (ip
,
1215 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1222 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1223 && ! cop_interlocks
)
1225 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1227 /* A generic coprocessor delay. The previous instruction
1228 modified a coprocessor general or control register. If
1229 it modified a control register, we need to avoid any
1230 coprocessor instruction (this is probably not always
1231 required, but it sometimes is). If it modified a general
1232 register, we avoid using that register.
1234 On the r6000 and r4000 loading a coprocessor register
1235 from memory is interlocked, and does not require a delay.
1237 This case is not handled very well. There is no special
1238 knowledge of CP0 handling, and the coprocessors other
1239 than the floating point unit are not distinguished at
1241 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1243 if (mips_optimize
== 0
1244 || insn_uses_reg (ip
,
1245 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1250 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1252 if (mips_optimize
== 0
1253 || insn_uses_reg (ip
,
1254 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1261 /* We don't know exactly what the previous instruction
1262 does. If the current instruction uses a coprocessor
1263 register, we must insert a NOP. If previous
1264 instruction may set the condition codes, and the
1265 current instruction uses them, we must insert two
1267 if (mips_optimize
== 0
1268 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1269 && (pinfo
& INSN_READ_COND_CODE
)))
1271 else if (pinfo
& INSN_COP
)
1277 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1278 && ! cop_interlocks
)
1280 /* The previous instruction sets the coprocessor condition
1281 codes, but does not require a general coprocessor delay
1282 (this means it is a floating point comparison
1283 instruction). If this instruction uses the condition
1284 codes, we need to insert a single NOP. */
1285 if (mips_optimize
== 0
1286 || (pinfo
& INSN_READ_COND_CODE
))
1289 else if (prev_pinfo
& INSN_READ_LO
)
1291 /* The previous instruction reads the LO register; if the
1292 current instruction writes to the LO register, we must
1293 insert two NOPS. Some newer processors have interlocks. */
1295 && (mips_optimize
== 0
1296 || (pinfo
& INSN_WRITE_LO
)))
1299 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1301 /* The previous instruction reads the HI register; if the
1302 current instruction writes to the HI register, we must
1303 insert a NOP. Some newer processors have interlocks. */
1305 && (mips_optimize
== 0
1306 || (pinfo
& INSN_WRITE_HI
)))
1310 /* There are two cases which require two intervening
1311 instructions: 1) setting the condition codes using a move to
1312 coprocessor instruction which requires a general coprocessor
1313 delay and then reading the condition codes 2) reading the HI
1314 or LO register and then writing to it (except on processors
1315 which have interlocks). If we are not already emitting a NOP
1316 instruction, we must check for these cases compared to the
1317 instruction previous to the previous instruction. */
1321 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1322 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1323 && (pinfo
& INSN_READ_COND_CODE
)
1324 && ! cop_interlocks
)
1325 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1326 && (pinfo
& INSN_WRITE_LO
)
1328 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1329 && (pinfo
& INSN_WRITE_HI
)
1333 /* If we are being given a nop instruction, don't bother with
1334 one of the nops we would otherwise output. This will only
1335 happen when a nop instruction is used with mips_optimize set
1337 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1340 /* Now emit the right number of NOP instructions. */
1344 unsigned long old_frag_offset
;
1347 old_frag
= frag_now
;
1348 old_frag_offset
= frag_now_fix ();
1350 for (i
= 0; i
< nops
; i
++)
1355 listing_prev_line ();
1356 /* We may be at the start of a variant frag. In case we
1357 are, make sure there is enough space for the frag
1358 after the frags created by listing_prev_line. The
1359 argument to frag_grow here must be at least as large
1360 as the argument to all other calls to frag_grow in
1361 this file. We don't have to worry about being in the
1362 middle of a variant frag, because the variants insert
1363 all needed nop instructions themselves. */
1367 if (insn_label
!= NULL
)
1369 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1370 insn_label
->sy_frag
= frag_now
;
1371 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1374 #ifndef NO_ECOFF_DEBUGGING
1375 if (ECOFF_DEBUGGING
)
1376 ecoff_fix_loc (old_frag
, old_frag_offset
);
1381 if (reloc_type
> BFD_RELOC_UNUSED
)
1383 /* We need to set up a variant frag. */
1384 assert (mips16
&& address_expr
!= NULL
);
1385 f
= frag_var (rs_machine_dependent
, 4, 0,
1386 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1387 mips16_small
, mips16_ext
),
1388 make_expr_symbol (address_expr
), (long) 0,
1391 else if (place
!= NULL
)
1393 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1395 /* Make sure there is enough room to swap this instruction with
1396 a following jump instruction. */
1403 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1405 if (address_expr
->X_op
== O_constant
)
1410 ip
->insn_opcode
|= address_expr
->X_add_number
;
1413 case BFD_RELOC_LO16
:
1414 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1417 case BFD_RELOC_MIPS_JMP
:
1418 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1421 case BFD_RELOC_MIPS16_JMP
:
1423 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1424 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1425 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1428 case BFD_RELOC_16_PCREL_S2
:
1438 /* Don't generate a reloc if we are writing into a variant
1442 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1444 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1448 struct mips_hi_fixup
*hi_fixup
;
1450 assert (reloc_type
== BFD_RELOC_HI16_S
);
1451 hi_fixup
= ((struct mips_hi_fixup
*)
1452 xmalloc (sizeof (struct mips_hi_fixup
)));
1453 hi_fixup
->fixp
= fixp
;
1454 hi_fixup
->seg
= now_seg
;
1455 hi_fixup
->next
= mips_hi_fixup_list
;
1456 mips_hi_fixup_list
= hi_fixup
;
1462 if (! mips16
|| reloc_type
== BFD_RELOC_MIPS16_JMP
)
1463 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1468 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1471 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1474 /* Update the register mask information. */
1477 if (pinfo
& INSN_WRITE_GPR_D
)
1478 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1479 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1480 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1481 if (pinfo
& INSN_READ_GPR_S
)
1482 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1483 if (pinfo
& INSN_WRITE_GPR_31
)
1484 mips_gprmask
|= 1 << 31;
1485 if (pinfo
& INSN_WRITE_FPR_D
)
1486 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1487 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1488 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1489 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1490 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1491 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1492 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1493 if (pinfo
& INSN_COP
)
1495 /* We don't keep enough information to sort these cases out. */
1497 /* Never set the bit for $0, which is always zero. */
1498 mips_gprmask
&=~ 1 << 0;
1502 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1503 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1504 & MIPS16OP_MASK_RX
);
1505 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1506 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1507 & MIPS16OP_MASK_RY
);
1508 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1509 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1510 & MIPS16OP_MASK_RZ
);
1511 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1512 mips_gprmask
|= 1 << TREG
;
1513 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1514 mips_gprmask
|= 1 << SP
;
1515 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1516 mips_gprmask
|= 1 << RA
;
1517 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1518 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1519 if (pinfo
& MIPS16_INSN_READ_Z
)
1520 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1521 & MIPS16OP_MASK_MOVE32Z
);
1522 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1523 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1524 & MIPS16OP_MASK_REGR32
);
1527 if (place
== NULL
&& ! mips_noreorder
)
1529 /* Filling the branch delay slot is more complex. We try to
1530 switch the branch with the previous instruction, which we can
1531 do if the previous instruction does not set up a condition
1532 that the branch tests and if the branch is not itself the
1533 target of any branch. */
1534 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1535 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1537 if (mips_optimize
< 2
1538 /* If we have seen .set volatile or .set nomove, don't
1541 /* If we had to emit any NOP instructions, then we
1542 already know we can not swap. */
1544 /* If we don't even know the previous insn, we can not
1546 || ! prev_insn_valid
1547 /* If the previous insn is already in a branch delay
1548 slot, then we can not swap. */
1549 || prev_insn_is_delay_slot
1550 /* If the previous previous insn was in a .set
1551 noreorder, we can't swap. Actually, the MIPS
1552 assembler will swap in this situation. However, gcc
1553 configured -with-gnu-as will generate code like
1559 in which we can not swap the bne and INSN. If gcc is
1560 not configured -with-gnu-as, it does not output the
1561 .set pseudo-ops. We don't have to check
1562 prev_insn_unreordered, because prev_insn_valid will
1563 be 0 in that case. We don't want to use
1564 prev_prev_insn_valid, because we do want to be able
1565 to swap at the start of a function. */
1566 || prev_prev_insn_unreordered
1567 /* If the branch is itself the target of a branch, we
1568 can not swap. We cheat on this; all we check for is
1569 whether there is a label on this instruction. If
1570 there are any branches to anything other than a
1571 label, users must use .set noreorder. */
1572 || insn_label
!= NULL
1573 /* If the previous instruction is in a variant frag, we
1574 can not do the swap. This does not apply to the
1575 mips16, which uses variant frags for different
1578 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1579 /* If the branch reads the condition codes, we don't
1580 even try to swap, because in the sequence
1585 we can not swap, and I don't feel like handling that
1589 && (pinfo
& INSN_READ_COND_CODE
))
1590 /* We can not swap with an instruction that requires a
1591 delay slot, becase the target of the branch might
1592 interfere with that instruction. */
1596 & (INSN_LOAD_COPROC_DELAY
1597 | INSN_COPROC_MOVE_DELAY
1598 | INSN_WRITE_COND_CODE
)))
1606 & (INSN_LOAD_MEMORY_DELAY
1607 | INSN_COPROC_MEMORY_DELAY
)))
1608 /* We can not swap with a branch instruction. */
1610 & (INSN_UNCOND_BRANCH_DELAY
1611 | INSN_COND_BRANCH_DELAY
1612 | INSN_COND_BRANCH_LIKELY
))
1613 /* We do not swap with a trap instruction, since it
1614 complicates trap handlers to have the trap
1615 instruction be in a delay slot. */
1616 || (prev_pinfo
& INSN_TRAP
)
1617 /* If the branch reads a register that the previous
1618 instruction sets, we can not swap. */
1620 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1621 && insn_uses_reg (ip
,
1622 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1626 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1627 && insn_uses_reg (ip
,
1628 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1632 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1633 && insn_uses_reg (ip
,
1634 ((prev_insn
.insn_opcode
1636 & MIPS16OP_MASK_RX
),
1638 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1639 && insn_uses_reg (ip
,
1640 ((prev_insn
.insn_opcode
1642 & MIPS16OP_MASK_RY
),
1644 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1645 && insn_uses_reg (ip
,
1646 ((prev_insn
.insn_opcode
1648 & MIPS16OP_MASK_RZ
),
1650 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1651 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1652 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1653 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1654 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1655 && insn_uses_reg (ip
,
1656 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1659 /* If the branch writes a register that the previous
1660 instruction sets, we can not swap (we know that
1661 branches write only to RD or to $31). */
1663 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1664 && (((pinfo
& INSN_WRITE_GPR_D
)
1665 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1666 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1667 || ((pinfo
& INSN_WRITE_GPR_31
)
1668 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1672 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1673 && (((pinfo
& INSN_WRITE_GPR_D
)
1674 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1675 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1676 || ((pinfo
& INSN_WRITE_GPR_31
)
1677 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1681 && (pinfo
& MIPS16_INSN_WRITE_31
)
1682 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1683 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1684 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1686 /* If the branch writes a register that the previous
1687 instruction reads, we can not swap (we know that
1688 branches only write to RD or to $31). */
1690 && (pinfo
& INSN_WRITE_GPR_D
)
1691 && insn_uses_reg (&prev_insn
,
1692 ((ip
->insn_opcode
>> OP_SH_RD
)
1696 && (pinfo
& INSN_WRITE_GPR_31
)
1697 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1699 && (pinfo
& MIPS16_INSN_WRITE_31
)
1700 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1701 /* If we are generating embedded PIC code, the branch
1702 might be expanded into a sequence which uses $at, so
1703 we can't swap with an instruction which reads it. */
1704 || (mips_pic
== EMBEDDED_PIC
1705 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1706 /* If the previous previous instruction has a load
1707 delay, and sets a register that the branch reads, we
1711 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1713 && (prev_prev_insn
.insn_mo
->pinfo
1714 & INSN_LOAD_MEMORY_DELAY
)))
1715 && insn_uses_reg (ip
,
1716 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1719 /* If one instruction sets a condition code and the
1720 other one uses a condition code, we can not swap. */
1721 || ((pinfo
& INSN_READ_COND_CODE
)
1722 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1723 || ((pinfo
& INSN_WRITE_COND_CODE
)
1724 && (prev_pinfo
& INSN_READ_COND_CODE
))
1725 /* If the previous instruction uses the PC, we can not
1728 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1729 /* If the previous instruction was extended, we can not
1731 || (mips16
&& prev_insn_extended
)
1732 /* If the previous instruction had a fixup in mips16
1733 mode, we can not swap. This normally means that the
1734 previous instruction was a 4 byte branch anyhow. */
1735 || (mips16
&& prev_insn_fixp
))
1737 /* We could do even better for unconditional branches to
1738 portions of this object file; we could pick up the
1739 instruction at the destination, put it in the delay
1740 slot, and bump the destination address. */
1742 /* Update the previous insn information. */
1743 prev_prev_insn
= *ip
;
1744 prev_insn
.insn_mo
= &dummy_opcode
;
1748 /* It looks like we can actually do the swap. */
1754 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1755 memcpy (temp
, prev_f
, 4);
1756 memcpy (prev_f
, f
, 4);
1757 memcpy (f
, temp
, 4);
1760 prev_insn_fixp
->fx_frag
= frag_now
;
1761 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1765 fixp
->fx_frag
= prev_insn_frag
;
1766 fixp
->fx_where
= prev_insn_where
;
1769 else if (reloc_type
> BFD_RELOC_UNUSED
)
1774 /* We are in mips16 mode, and we have just created a
1775 variant frag. We need to extract the old
1776 instruction from the end of the previous frag,
1777 and add it to a new frag. */
1778 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1779 memcpy (temp
, prev_f
, 2);
1780 prev_insn_frag
->fr_fix
-= 2;
1781 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1783 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1784 memcpy (prev_f
, prev_f
+ 2, 2);
1786 memcpy (frag_more (2), temp
, 2);
1793 assert (prev_insn_fixp
== NULL
);
1794 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1795 memcpy (temp
, prev_f
, 2);
1796 memcpy (prev_f
, f
, 2);
1797 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1798 memcpy (f
, temp
, 2);
1801 memcpy (f
, f
+ 2, 2);
1802 memcpy (f
+ 2, temp
, 2);
1806 fixp
->fx_frag
= prev_insn_frag
;
1807 fixp
->fx_where
= prev_insn_where
;
1811 /* Update the previous insn information; leave prev_insn
1813 prev_prev_insn
= *ip
;
1815 prev_insn_is_delay_slot
= 1;
1817 /* If that was an unconditional branch, forget the previous
1818 insn information. */
1819 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1821 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1822 prev_insn
.insn_mo
= &dummy_opcode
;
1825 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1827 /* We don't yet optimize a branch likely. What we should do
1828 is look at the target, copy the instruction found there
1829 into the delay slot, and increment the branch to jump to
1830 the next instruction. */
1832 /* Update the previous insn information. */
1833 prev_prev_insn
= *ip
;
1834 prev_insn
.insn_mo
= &dummy_opcode
;
1838 /* Update the previous insn information. */
1840 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1842 prev_prev_insn
= prev_insn
;
1845 /* Any time we see a branch, we always fill the delay slot
1846 immediately; since this insn is not a branch, we know it
1847 is not in a delay slot. */
1848 prev_insn_is_delay_slot
= 0;
1851 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1852 prev_insn_unreordered
= 0;
1853 prev_insn_frag
= frag_now
;
1854 prev_insn_where
= f
- frag_now
->fr_literal
;
1855 prev_insn_fixp
= fixp
;
1857 prev_insn_extended
= ip
->use_extend
|| reloc_type
> BFD_RELOC_UNUSED
;
1858 prev_insn_valid
= 1;
1861 /* We just output an insn, so the next one doesn't have a label. */
1865 /* This function forgets that there was any previous instruction or
1869 mips_no_prev_insn ()
1871 prev_insn
.insn_mo
= &dummy_opcode
;
1872 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1873 prev_insn_valid
= 0;
1874 prev_insn_is_delay_slot
= 0;
1875 prev_insn_unreordered
= 0;
1876 prev_insn_extended
= 0;
1877 prev_prev_insn_unreordered
= 0;
1881 /* This function must be called whenever we turn on noreorder or emit
1882 something other than instructions. It inserts any NOPS which might
1883 be needed by the previous instruction, and clears the information
1884 kept for the previous instructions. */
1889 if (! mips_noreorder
)
1896 && (! cop_interlocks
1897 && (prev_insn
.insn_mo
->pinfo
1898 & (INSN_LOAD_COPROC_DELAY
1899 | INSN_COPROC_MOVE_DELAY
1900 | INSN_WRITE_COND_CODE
))))
1902 && (prev_insn
.insn_mo
->pinfo
1907 && (prev_insn
.insn_mo
->pinfo
1908 & (INSN_LOAD_MEMORY_DELAY
1909 | INSN_COPROC_MEMORY_DELAY
))))
1914 && (! cop_interlocks
1915 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1917 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1918 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1923 && (! cop_interlocks
1924 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1926 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1927 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1932 if (insn_label
!= NULL
)
1934 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1935 insn_label
->sy_frag
= frag_now
;
1936 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1941 mips_no_prev_insn ();
1944 /* Build an instruction created by a macro expansion. This is passed
1945 a pointer to the count of instructions created so far, an
1946 expression, the name of the instruction to build, an operand format
1947 string, and corresponding arguments. */
1951 macro_build (char *place
,
1959 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1968 struct mips_cl_insn insn
;
1969 bfd_reloc_code_real_type r
;
1973 va_start (args
, fmt
);
1979 * If the macro is about to expand into a second instruction,
1980 * print a warning if needed. We need to pass ip as a parameter
1981 * to generate a better warning message here...
1983 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1984 as_warn ("Macro instruction expanded into multiple instructions");
1987 *counter
+= 1; /* bump instruction counter */
1991 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
1996 r
= BFD_RELOC_UNUSED
;
1997 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1998 assert (insn
.insn_mo
);
1999 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2001 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2002 || insn
.insn_mo
->pinfo
== INSN_MACRO
2003 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2005 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2007 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2009 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2011 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2013 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2017 assert (insn
.insn_mo
->name
);
2018 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2020 insn
.insn_opcode
= insn
.insn_mo
->match
;
2036 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2042 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2047 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2052 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2059 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2063 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2067 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2074 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2080 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2081 assert (r
== BFD_RELOC_MIPS_GPREL
2082 || r
== BFD_RELOC_MIPS_LITERAL
2083 || r
== BFD_RELOC_LO16
2084 || r
== BFD_RELOC_MIPS_GOT16
2085 || r
== BFD_RELOC_MIPS_CALL16
2086 || r
== BFD_RELOC_MIPS_GOT_LO16
2087 || r
== BFD_RELOC_MIPS_CALL_LO16
2088 || (ep
->X_op
== O_subtract
2089 && now_seg
== text_section
2090 && r
== BFD_RELOC_PCREL_LO16
));
2094 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2096 && (ep
->X_op
== O_constant
2097 || (ep
->X_op
== O_symbol
2098 && (r
== BFD_RELOC_HI16_S
2099 || r
== BFD_RELOC_HI16
2100 || r
== BFD_RELOC_MIPS_GOT_HI16
2101 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2102 || (ep
->X_op
== O_subtract
2103 && now_seg
== text_section
2104 && r
== BFD_RELOC_PCREL_HI16_S
)));
2105 if (ep
->X_op
== O_constant
)
2107 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2109 r
= BFD_RELOC_UNUSED
;
2114 assert (ep
!= NULL
);
2116 * This allows macro() to pass an immediate expression for
2117 * creating short branches without creating a symbol.
2118 * Note that the expression still might come from the assembly
2119 * input, in which case the value is not checked for range nor
2120 * is a relocation entry generated (yuck).
2122 if (ep
->X_op
== O_constant
)
2124 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2128 r
= BFD_RELOC_16_PCREL_S2
;
2132 assert (ep
!= NULL
);
2133 r
= BFD_RELOC_MIPS_JMP
;
2142 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2144 append_insn (place
, &insn
, ep
, r
, false);
2148 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2156 struct mips_cl_insn insn
;
2157 bfd_reloc_code_real_type r
;
2159 r
= BFD_RELOC_UNUSED
;
2160 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2161 assert (insn
.insn_mo
);
2162 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2164 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2165 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2168 assert (insn
.insn_mo
->name
);
2169 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2172 insn
.insn_opcode
= insn
.insn_mo
->match
;
2173 insn
.use_extend
= false;
2192 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2197 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2201 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2205 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2215 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2222 regno
= va_arg (args
, int);
2223 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2224 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2245 assert (ep
!= NULL
);
2247 if (ep
->X_op
!= O_constant
)
2248 r
= BFD_RELOC_UNUSED
+ c
;
2251 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2252 false, false, &insn
.insn_opcode
,
2253 &insn
.use_extend
, &insn
.extend
);
2255 r
= BFD_RELOC_UNUSED
;
2261 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2268 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2270 append_insn (place
, &insn
, ep
, r
, false);
2274 * Generate a "lui" instruction.
2277 macro_build_lui (place
, counter
, ep
, regnum
)
2283 expressionS high_expr
;
2284 struct mips_cl_insn insn
;
2285 bfd_reloc_code_real_type r
;
2286 CONST
char *name
= "lui";
2287 CONST
char *fmt
= "t,u";
2295 high_expr
.X_op
= O_constant
;
2296 high_expr
.X_add_number
= ep
->X_add_number
;
2299 if (high_expr
.X_op
== O_constant
)
2301 /* we can compute the instruction now without a relocation entry */
2302 if (high_expr
.X_add_number
& 0x8000)
2303 high_expr
.X_add_number
+= 0x10000;
2304 high_expr
.X_add_number
=
2305 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2306 r
= BFD_RELOC_UNUSED
;
2310 assert (ep
->X_op
== O_symbol
);
2311 /* _gp_disp is a special case, used from s_cpload. */
2312 assert (mips_pic
== NO_PIC
2313 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2314 r
= BFD_RELOC_HI16_S
;
2318 * If the macro is about to expand into a second instruction,
2319 * print a warning if needed. We need to pass ip as a parameter
2320 * to generate a better warning message here...
2322 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2323 as_warn ("Macro instruction expanded into multiple instructions");
2326 *counter
+= 1; /* bump instruction counter */
2328 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2329 assert (insn
.insn_mo
);
2330 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2331 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2333 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2334 if (r
== BFD_RELOC_UNUSED
)
2336 insn
.insn_opcode
|= high_expr
.X_add_number
;
2337 append_insn (place
, &insn
, NULL
, r
, false);
2340 append_insn (place
, &insn
, &high_expr
, r
, false);
2344 * Generates code to set the $at register to true (one)
2345 * if reg is less than the immediate expression.
2348 set_at (counter
, reg
, unsignedp
)
2353 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2354 macro_build ((char *) NULL
, counter
, &imm_expr
,
2355 unsignedp
? "sltiu" : "slti",
2356 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2359 load_register (counter
, AT
, &imm_expr
, 0);
2360 macro_build ((char *) NULL
, counter
, NULL
,
2361 unsignedp
? "sltu" : "slt",
2362 "d,v,t", AT
, reg
, AT
);
2366 /* Warn if an expression is not a constant. */
2369 check_absolute_expr (ip
, ex
)
2370 struct mips_cl_insn
*ip
;
2373 if (ex
->X_op
!= O_constant
)
2374 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2377 /* Count the leading zeroes by performing a binary chop. This is a
2378 bulky bit of source, but performance is a LOT better for the
2379 majority of values than a simple loop to count the bits:
2380 for (lcnt = 0; (lcnt < 32); lcnt++)
2381 if ((v) & (1 << (31 - lcnt)))
2383 However it is not code size friendly, and the gain will drop a bit
2384 on certain cached systems.
2386 #define COUNT_TOP_ZEROES(v) \
2387 (((v) & ~0xffff) == 0 \
2388 ? ((v) & ~0xff) == 0 \
2389 ? ((v) & ~0xf) == 0 \
2390 ? ((v) & ~0x3) == 0 \
2391 ? ((v) & ~0x1) == 0 \
2396 : ((v) & ~0x7) == 0 \
2399 : ((v) & ~0x3f) == 0 \
2400 ? ((v) & ~0x1f) == 0 \
2403 : ((v) & ~0x7f) == 0 \
2406 : ((v) & ~0xfff) == 0 \
2407 ? ((v) & ~0x3ff) == 0 \
2408 ? ((v) & ~0x1ff) == 0 \
2411 : ((v) & ~0x7ff) == 0 \
2414 : ((v) & ~0x3fff) == 0 \
2415 ? ((v) & ~0x1fff) == 0 \
2418 : ((v) & ~0x7fff) == 0 \
2421 : ((v) & ~0xffffff) == 0 \
2422 ? ((v) & ~0xfffff) == 0 \
2423 ? ((v) & ~0x3ffff) == 0 \
2424 ? ((v) & ~0x1ffff) == 0 \
2427 : ((v) & ~0x7ffff) == 0 \
2430 : ((v) & ~0x3fffff) == 0 \
2431 ? ((v) & ~0x1fffff) == 0 \
2434 : ((v) & ~0x7fffff) == 0 \
2437 : ((v) & ~0xfffffff) == 0 \
2438 ? ((v) & ~0x3ffffff) == 0 \
2439 ? ((v) & ~0x1ffffff) == 0 \
2442 : ((v) & ~0x7ffffff) == 0 \
2445 : ((v) & ~0x3fffffff) == 0 \
2446 ? ((v) & ~0x1fffffff) == 0 \
2449 : ((v) & ~0x7fffffff) == 0 \
2454 * This routine generates the least number of instructions neccessary to load
2455 * an absolute expression value into a register.
2458 load_register (counter
, reg
, ep
, dbl
)
2465 expressionS hi32
, lo32
, tmp
;
2467 if (ep
->X_op
!= O_big
)
2469 assert (ep
->X_op
== O_constant
);
2470 if (ep
->X_add_number
< 0x8000
2471 && (ep
->X_add_number
>= 0
2472 || (ep
->X_add_number
>= -0x8000
2475 || sizeof (ep
->X_add_number
) > 4))))
2477 /* We can handle 16 bit signed values with an addiu to
2478 $zero. No need to ever use daddiu here, since $zero and
2479 the result are always correct in 32 bit mode. */
2480 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2481 (int) BFD_RELOC_LO16
);
2484 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2486 /* We can handle 16 bit unsigned values with an ori to
2488 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2489 (int) BFD_RELOC_LO16
);
2492 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2493 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2494 == ~ (offsetT
) 0x7fffffff))
2497 || sizeof (ep
->X_add_number
) > 4
2498 || (ep
->X_add_number
& 0x80000000) == 0))
2499 || ((mips_isa
< 3 || !dbl
)
2500 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2502 /* 32 bit values require an lui. */
2503 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2504 (int) BFD_RELOC_HI16
);
2505 if ((ep
->X_add_number
& 0xffff) != 0)
2506 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2507 (int) BFD_RELOC_LO16
);
2512 /* The value is larger than 32 bits. */
2516 as_bad ("Number larger than 32 bits");
2517 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2518 (int) BFD_RELOC_LO16
);
2522 if (ep
->X_op
!= O_big
)
2526 hi32
.X_add_number
>>= shift
;
2527 hi32
.X_add_number
&= 0xffffffff;
2528 if ((hi32
.X_add_number
& 0x80000000) != 0)
2529 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2531 lo32
.X_add_number
&= 0xffffffff;
2535 assert (ep
->X_add_number
> 2);
2536 if (ep
->X_add_number
== 3)
2537 generic_bignum
[3] = 0;
2538 else if (ep
->X_add_number
> 4)
2539 as_bad ("Number larger than 64 bits");
2540 lo32
.X_op
= O_constant
;
2541 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2542 hi32
.X_op
= O_constant
;
2543 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2546 if (hi32
.X_add_number
== 0)
2550 if (hi32
.X_add_number
== 0xffffffff)
2552 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2554 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
2555 (int) BFD_RELOC_LO16
);
2558 if (lo32
.X_add_number
& 0x80000000)
2560 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2561 (int) BFD_RELOC_HI16
);
2562 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
2563 (int) BFD_RELOC_LO16
);
2568 /* Check for 16bit shifted constant: */
2570 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2571 /* We know that hi32 is non-zero, so start the mask on the first
2572 bit of the hi32 value: */
2576 if ((tmp
.X_add_number
& ~((offsetT
)0xffff << shift
)) == 0)
2578 tmp
.X_op
= O_constant
;
2579 tmp
.X_add_number
>>= shift
;
2580 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2581 (int) BFD_RELOC_LO16
);
2582 macro_build ((char *) NULL
, counter
, NULL
,
2583 (shift
>= 32) ? "dsll32" : "dsll",
2584 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2588 } while (shift
<= (64 - 16));
2592 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2593 while ((tmp
.X_add_number
& 1) == 0)
2595 tmp
.X_add_number
>>= 1;
2598 if (((tmp
.X_add_number
+ 1) & tmp
.X_add_number
) == 0) /* (power-of-2 - 1) */
2600 shift
= COUNT_TOP_ZEROES((unsigned int)hi32
.X_add_number
);
2603 tmp
.X_op
= O_constant
;
2604 tmp
.X_add_number
= (offsetT
)-1;
2605 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
2606 (int) BFD_RELOC_LO16
); /* set all ones */
2610 macro_build ((char *) NULL
, counter
, NULL
,
2611 (freg
>= 32) ? "dsll32" : "dsll",
2613 (freg
>= 32) ? freg
- 32 : freg
);
2615 macro_build ((char *) NULL
, counter
, NULL
, (shift
>= 32) ? "dsrl32" : "dsrl",
2616 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2620 load_register (counter
, reg
, &hi32
, 0);
2623 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2627 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2636 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2638 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2639 (int) BFD_RELOC_HI16
);
2640 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2647 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2652 mid16
.X_add_number
>>= 16;
2653 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2654 freg
, (int) BFD_RELOC_LO16
);
2655 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2659 if ((lo32
.X_add_number
& 0xffff) != 0)
2660 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2661 (int) BFD_RELOC_LO16
);
2664 /* Load an address into a register. */
2667 load_address (counter
, reg
, ep
)
2674 if (ep
->X_op
!= O_constant
2675 && ep
->X_op
!= O_symbol
)
2677 as_bad ("expression too complex");
2678 ep
->X_op
= O_constant
;
2681 if (ep
->X_op
== O_constant
)
2683 load_register (counter
, reg
, ep
, 0);
2687 if (mips_pic
== NO_PIC
)
2689 /* If this is a reference to a GP relative symbol, we want
2690 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2692 lui $reg,<sym> (BFD_RELOC_HI16_S)
2693 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2694 If we have an addend, we always use the latter form. */
2695 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2696 || nopic_need_relax (ep
->X_add_symbol
))
2701 macro_build ((char *) NULL
, counter
, ep
,
2702 mips_isa
< 3 ? "addiu" : "daddiu",
2703 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2704 p
= frag_var (rs_machine_dependent
, 8, 0,
2705 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2706 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2708 macro_build_lui (p
, counter
, ep
, reg
);
2711 macro_build (p
, counter
, ep
,
2712 mips_isa
< 3 ? "addiu" : "daddiu",
2713 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2715 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2719 /* If this is a reference to an external symbol, we want
2720 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2722 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2724 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2725 If there is a constant, it must be added in after. */
2726 ex
.X_add_number
= ep
->X_add_number
;
2727 ep
->X_add_number
= 0;
2729 macro_build ((char *) NULL
, counter
, ep
,
2730 mips_isa
< 3 ? "lw" : "ld",
2731 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2732 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2733 p
= frag_var (rs_machine_dependent
, 4, 0,
2734 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2735 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2736 macro_build (p
, counter
, ep
,
2737 mips_isa
< 3 ? "addiu" : "daddiu",
2738 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2739 if (ex
.X_add_number
!= 0)
2741 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2742 as_bad ("PIC code offset overflow (max 16 signed bits)");
2743 ex
.X_op
= O_constant
;
2744 macro_build ((char *) NULL
, counter
, &ex
,
2745 mips_isa
< 3 ? "addiu" : "daddiu",
2746 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2749 else if (mips_pic
== SVR4_PIC
)
2754 /* This is the large GOT case. If this is a reference to an
2755 external symbol, we want
2756 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2758 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2759 Otherwise, for a reference to a local symbol, we want
2760 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2762 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2763 If there is a constant, it must be added in after. */
2764 ex
.X_add_number
= ep
->X_add_number
;
2765 ep
->X_add_number
= 0;
2766 if (reg_needs_delay (GP
))
2771 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2772 (int) BFD_RELOC_MIPS_GOT_HI16
);
2773 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2774 mips_isa
< 3 ? "addu" : "daddu",
2775 "d,v,t", reg
, reg
, GP
);
2776 macro_build ((char *) NULL
, counter
, ep
,
2777 mips_isa
< 3 ? "lw" : "ld",
2778 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2779 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2780 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2781 mips_warn_about_macros
),
2782 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2785 /* We need a nop before loading from $gp. This special
2786 check is required because the lui which starts the main
2787 instruction stream does not refer to $gp, and so will not
2788 insert the nop which may be required. */
2789 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2792 macro_build (p
, counter
, ep
,
2793 mips_isa
< 3 ? "lw" : "ld",
2794 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2796 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2798 macro_build (p
, counter
, ep
,
2799 mips_isa
< 3 ? "addiu" : "daddiu",
2800 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2801 if (ex
.X_add_number
!= 0)
2803 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2804 as_bad ("PIC code offset overflow (max 16 signed bits)");
2805 ex
.X_op
= O_constant
;
2806 macro_build ((char *) NULL
, counter
, &ex
,
2807 mips_isa
< 3 ? "addiu" : "daddiu",
2808 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2811 else if (mips_pic
== EMBEDDED_PIC
)
2814 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2816 macro_build ((char *) NULL
, counter
, ep
,
2817 mips_isa
< 3 ? "addiu" : "daddiu",
2818 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2826 * This routine implements the seemingly endless macro or synthesized
2827 * instructions and addressing modes in the mips assembly language. Many
2828 * of these macros are simple and are similar to each other. These could
2829 * probably be handled by some kind of table or grammer aproach instead of
2830 * this verbose method. Others are not simple macros but are more like
2831 * optimizing code generation.
2832 * One interesting optimization is when several store macros appear
2833 * consecutivly that would load AT with the upper half of the same address.
2834 * The ensuing load upper instructions are ommited. This implies some kind
2835 * of global optimization. We currently only optimize within a single macro.
2836 * For many of the load and store macros if the address is specified as a
2837 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2838 * first load register 'at' with zero and use it as the base register. The
2839 * mips assembler simply uses register $zero. Just one tiny optimization
2844 struct mips_cl_insn
*ip
;
2846 register int treg
, sreg
, dreg
, breg
;
2861 bfd_reloc_code_real_type r
;
2863 int hold_mips_optimize
;
2867 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2868 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2869 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2870 mask
= ip
->insn_mo
->mask
;
2872 expr1
.X_op
= O_constant
;
2873 expr1
.X_op_symbol
= NULL
;
2874 expr1
.X_add_symbol
= NULL
;
2875 expr1
.X_add_number
= 1;
2887 mips_emit_delays ();
2889 mips_any_noreorder
= 1;
2891 expr1
.X_add_number
= 8;
2892 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2894 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2896 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2897 macro_build ((char *) NULL
, &icnt
, NULL
,
2898 dbl
? "dsub" : "sub",
2899 "d,v,t", dreg
, 0, sreg
);
2922 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2924 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2925 (int) BFD_RELOC_LO16
);
2928 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2929 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2948 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2950 if (mask
!= M_NOR_I
)
2951 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2952 sreg
, (int) BFD_RELOC_LO16
);
2955 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2956 treg
, sreg
, (int) BFD_RELOC_LO16
);
2957 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2963 load_register (&icnt
, AT
, &imm_expr
, 0);
2964 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2981 if (imm_expr
.X_add_number
== 0)
2983 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2987 load_register (&icnt
, AT
, &imm_expr
, 0);
2988 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2996 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2997 likely
? "bgezl" : "bgez",
3003 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3004 likely
? "blezl" : "blez",
3008 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3009 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3010 likely
? "beql" : "beq",
3017 /* check for > max integer */
3018 maxnum
= 0x7fffffff;
3026 if (imm_expr
.X_add_number
>= maxnum
3027 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3030 /* result is always false */
3033 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3034 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3038 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3039 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3044 imm_expr
.X_add_number
++;
3048 if (mask
== M_BGEL_I
)
3050 if (imm_expr
.X_add_number
== 0)
3052 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3053 likely
? "bgezl" : "bgez",
3057 if (imm_expr
.X_add_number
== 1)
3059 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3060 likely
? "bgtzl" : "bgtz",
3064 maxnum
= 0x7fffffff;
3072 maxnum
= - maxnum
- 1;
3073 if (imm_expr
.X_add_number
<= maxnum
3074 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3077 /* result is always true */
3078 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3079 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3082 set_at (&icnt
, sreg
, 0);
3083 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3084 likely
? "beql" : "beq",
3095 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3096 likely
? "beql" : "beq",
3100 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3102 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3103 likely
? "beql" : "beq",
3110 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3112 imm_expr
.X_add_number
++;
3116 if (mask
== M_BGEUL_I
)
3118 if (imm_expr
.X_add_number
== 0)
3120 if (imm_expr
.X_add_number
== 1)
3122 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3123 likely
? "bnel" : "bne",
3127 set_at (&icnt
, sreg
, 1);
3128 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3129 likely
? "beql" : "beq",
3138 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3139 likely
? "bgtzl" : "bgtz",
3145 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3146 likely
? "bltzl" : "bltz",
3150 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3151 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3152 likely
? "bnel" : "bne",
3161 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3162 likely
? "bnel" : "bne",
3168 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3170 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3171 likely
? "bnel" : "bne",
3180 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3181 likely
? "blezl" : "blez",
3187 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3188 likely
? "bgezl" : "bgez",
3192 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3193 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3194 likely
? "beql" : "beq",
3201 maxnum
= 0x7fffffff;
3209 if (imm_expr
.X_add_number
>= maxnum
3210 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3212 imm_expr
.X_add_number
++;
3216 if (mask
== M_BLTL_I
)
3218 if (imm_expr
.X_add_number
== 0)
3220 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3221 likely
? "bltzl" : "bltz",
3225 if (imm_expr
.X_add_number
== 1)
3227 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3228 likely
? "blezl" : "blez",
3232 set_at (&icnt
, sreg
, 0);
3233 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3234 likely
? "bnel" : "bne",
3243 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3244 likely
? "beql" : "beq",
3250 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3252 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3253 likely
? "beql" : "beq",
3260 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3262 imm_expr
.X_add_number
++;
3266 if (mask
== M_BLTUL_I
)
3268 if (imm_expr
.X_add_number
== 0)
3270 if (imm_expr
.X_add_number
== 1)
3272 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3273 likely
? "beql" : "beq",
3277 set_at (&icnt
, sreg
, 1);
3278 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3279 likely
? "bnel" : "bne",
3288 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3289 likely
? "bltzl" : "bltz",
3295 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3296 likely
? "bgtzl" : "bgtz",
3300 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3301 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3302 likely
? "bnel" : "bne",
3313 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3314 likely
? "bnel" : "bne",
3318 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3320 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3321 likely
? "bnel" : "bne",
3337 as_warn ("Divide by zero.");
3339 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3341 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3345 mips_emit_delays ();
3347 mips_any_noreorder
= 1;
3348 macro_build ((char *) NULL
, &icnt
, NULL
,
3349 dbl
? "ddiv" : "div",
3350 "z,s,t", sreg
, treg
);
3352 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3355 expr1
.X_add_number
= 8;
3356 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3357 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3358 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3360 expr1
.X_add_number
= -1;
3361 macro_build ((char *) NULL
, &icnt
, &expr1
,
3362 dbl
? "daddiu" : "addiu",
3363 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3364 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3365 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3368 expr1
.X_add_number
= 1;
3369 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3370 (int) BFD_RELOC_LO16
);
3371 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3376 expr1
.X_add_number
= 0x80000000;
3377 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3378 (int) BFD_RELOC_HI16
);
3381 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3384 expr1
.X_add_number
= 8;
3385 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3386 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3387 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3390 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3429 if (imm_expr
.X_add_number
== 0)
3431 as_warn ("Divide by zero.");
3433 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3435 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3438 if (imm_expr
.X_add_number
== 1)
3440 if (strcmp (s2
, "mflo") == 0)
3441 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3444 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3447 if (imm_expr
.X_add_number
== -1
3448 && s
[strlen (s
) - 1] != 'u')
3450 if (strcmp (s2
, "mflo") == 0)
3453 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3456 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3460 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3464 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3465 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3466 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3485 mips_emit_delays ();
3487 mips_any_noreorder
= 1;
3488 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3490 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3493 expr1
.X_add_number
= 8;
3494 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3495 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3496 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3499 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3505 /* Load the address of a symbol into a register. If breg is not
3506 zero, we then add a base register to it. */
3508 /* When generating embedded PIC code, we permit expressions of
3511 where bar is an address in the .text section. These are used
3512 when getting the addresses of functions. We don't permit
3513 X_add_number to be non-zero, because if the symbol is
3514 external the relaxing code needs to know that any addend is
3515 purely the offset to X_op_symbol. */
3516 if (mips_pic
== EMBEDDED_PIC
3517 && offset_expr
.X_op
== O_subtract
3518 && now_seg
== text_section
3519 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3520 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3521 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3522 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3523 ->sy_value
.X_add_symbol
)
3526 && offset_expr
.X_add_number
== 0)
3528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3529 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3530 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3531 mips_isa
< 3 ? "addiu" : "daddiu",
3532 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3536 if (offset_expr
.X_op
!= O_symbol
3537 && offset_expr
.X_op
!= O_constant
)
3539 as_bad ("expression too complex");
3540 offset_expr
.X_op
= O_constant
;
3554 if (offset_expr
.X_op
== O_constant
)
3555 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3556 else if (mips_pic
== NO_PIC
)
3558 /* If this is a reference to an GP relative symbol, we want
3559 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3561 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3562 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3563 If we have a constant, we need two instructions anyhow,
3564 so we may as well always use the latter form. */
3565 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3566 || nopic_need_relax (offset_expr
.X_add_symbol
))
3571 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3572 mips_isa
< 3 ? "addiu" : "daddiu",
3573 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3574 p
= frag_var (rs_machine_dependent
, 8, 0,
3575 RELAX_ENCODE (4, 8, 0, 4, 0,
3576 mips_warn_about_macros
),
3577 offset_expr
.X_add_symbol
, (long) 0,
3580 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3583 macro_build (p
, &icnt
, &offset_expr
,
3584 mips_isa
< 3 ? "addiu" : "daddiu",
3585 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3587 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3589 /* If this is a reference to an external symbol, and there
3590 is no constant, we want
3591 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3592 For a local symbol, we want
3593 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3595 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3597 If we have a small constant, and this is a reference to
3598 an external symbol, we want
3599 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3601 addiu $tempreg,$tempreg,<constant>
3602 For a local symbol, we want the same instruction
3603 sequence, but we output a BFD_RELOC_LO16 reloc on the
3606 If we have a large constant, and this is a reference to
3607 an external symbol, we want
3608 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3609 lui $at,<hiconstant>
3610 addiu $at,$at,<loconstant>
3611 addu $tempreg,$tempreg,$at
3612 For a local symbol, we want the same instruction
3613 sequence, but we output a BFD_RELOC_LO16 reloc on the
3614 addiu instruction. */
3615 expr1
.X_add_number
= offset_expr
.X_add_number
;
3616 offset_expr
.X_add_number
= 0;
3618 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3620 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3621 if (expr1
.X_add_number
== 0)
3629 /* We're going to put in an addu instruction using
3630 tempreg, so we may as well insert the nop right
3632 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3636 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3637 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3639 ? mips_warn_about_macros
3641 offset_expr
.X_add_symbol
, (long) 0,
3645 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3648 macro_build (p
, &icnt
, &expr1
,
3649 mips_isa
< 3 ? "addiu" : "daddiu",
3650 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3651 /* FIXME: If breg == 0, and the next instruction uses
3652 $tempreg, then if this variant case is used an extra
3653 nop will be generated. */
3655 else if (expr1
.X_add_number
>= -0x8000
3656 && expr1
.X_add_number
< 0x8000)
3658 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3660 macro_build ((char *) NULL
, &icnt
, &expr1
,
3661 mips_isa
< 3 ? "addiu" : "daddiu",
3662 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3663 (void) frag_var (rs_machine_dependent
, 0, 0,
3664 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3665 offset_expr
.X_add_symbol
, (long) 0,
3672 /* If we are going to add in a base register, and the
3673 target register and the base register are the same,
3674 then we are using AT as a temporary register. Since
3675 we want to load the constant into AT, we add our
3676 current AT (from the global offset table) and the
3677 register into the register now, and pretend we were
3678 not using a base register. */
3683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3685 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3686 mips_isa
< 3 ? "addu" : "daddu",
3687 "d,v,t", treg
, AT
, breg
);
3693 /* Set mips_optimize around the lui instruction to avoid
3694 inserting an unnecessary nop after the lw. */
3695 hold_mips_optimize
= mips_optimize
;
3697 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3698 mips_optimize
= hold_mips_optimize
;
3700 macro_build ((char *) NULL
, &icnt
, &expr1
,
3701 mips_isa
< 3 ? "addiu" : "daddiu",
3702 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3703 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3704 mips_isa
< 3 ? "addu" : "daddu",
3705 "d,v,t", tempreg
, tempreg
, AT
);
3706 (void) frag_var (rs_machine_dependent
, 0, 0,
3707 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3708 offset_expr
.X_add_symbol
, (long) 0,
3713 else if (mips_pic
== SVR4_PIC
)
3717 /* This is the large GOT case. If this is a reference to an
3718 external symbol, and there is no constant, we want
3719 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3720 addu $tempreg,$tempreg,$gp
3721 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3722 For a local symbol, we want
3723 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3725 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3727 If we have a small constant, and this is a reference to
3728 an external symbol, we want
3729 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3730 addu $tempreg,$tempreg,$gp
3731 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3733 addiu $tempreg,$tempreg,<constant>
3734 For a local symbol, we want
3735 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3737 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3739 If we have a large constant, and this is a reference to
3740 an external symbol, we want
3741 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3742 addu $tempreg,$tempreg,$gp
3743 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3744 lui $at,<hiconstant>
3745 addiu $at,$at,<loconstant>
3746 addu $tempreg,$tempreg,$at
3747 For a local symbol, we want
3748 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3749 lui $at,<hiconstant>
3750 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3751 addu $tempreg,$tempreg,$at
3753 expr1
.X_add_number
= offset_expr
.X_add_number
;
3754 offset_expr
.X_add_number
= 0;
3756 if (reg_needs_delay (GP
))
3760 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3761 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3762 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3763 mips_isa
< 3 ? "addu" : "daddu",
3764 "d,v,t", tempreg
, tempreg
, GP
);
3765 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3767 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3769 if (expr1
.X_add_number
== 0)
3777 /* We're going to put in an addu instruction using
3778 tempreg, so we may as well insert the nop right
3780 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3785 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3786 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3789 ? mips_warn_about_macros
3791 offset_expr
.X_add_symbol
, (long) 0,
3794 else if (expr1
.X_add_number
>= -0x8000
3795 && expr1
.X_add_number
< 0x8000)
3797 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3799 macro_build ((char *) NULL
, &icnt
, &expr1
,
3800 mips_isa
< 3 ? "addiu" : "daddiu",
3801 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3803 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3804 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3806 ? mips_warn_about_macros
3808 offset_expr
.X_add_symbol
, (long) 0,
3815 /* If we are going to add in a base register, and the
3816 target register and the base register are the same,
3817 then we are using AT as a temporary register. Since
3818 we want to load the constant into AT, we add our
3819 current AT (from the global offset table) and the
3820 register into the register now, and pretend we were
3821 not using a base register. */
3829 assert (tempreg
== AT
);
3830 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3832 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3833 mips_isa
< 3 ? "addu" : "daddu",
3834 "d,v,t", treg
, AT
, breg
);
3839 /* Set mips_optimize around the lui instruction to avoid
3840 inserting an unnecessary nop after the lw. */
3841 hold_mips_optimize
= mips_optimize
;
3843 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3844 mips_optimize
= hold_mips_optimize
;
3846 macro_build ((char *) NULL
, &icnt
, &expr1
,
3847 mips_isa
< 3 ? "addiu" : "daddiu",
3848 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3849 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3850 mips_isa
< 3 ? "addu" : "daddu",
3851 "d,v,t", dreg
, dreg
, AT
);
3853 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3854 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3857 ? mips_warn_about_macros
3859 offset_expr
.X_add_symbol
, (long) 0,
3867 /* This is needed because this instruction uses $gp, but
3868 the first instruction on the main stream does not. */
3869 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3872 macro_build (p
, &icnt
, &offset_expr
,
3874 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3876 if (expr1
.X_add_number
>= -0x8000
3877 && expr1
.X_add_number
< 0x8000)
3879 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3881 macro_build (p
, &icnt
, &expr1
,
3882 mips_isa
< 3 ? "addiu" : "daddiu",
3883 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3884 /* FIXME: If add_number is 0, and there was no base
3885 register, the external symbol case ended with a load,
3886 so if the symbol turns out to not be external, and
3887 the next instruction uses tempreg, an unnecessary nop
3888 will be inserted. */
3894 /* We must add in the base register now, as in the
3895 external symbol case. */
3896 assert (tempreg
== AT
);
3897 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3899 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3900 mips_isa
< 3 ? "addu" : "daddu",
3901 "d,v,t", treg
, AT
, breg
);
3904 /* We set breg to 0 because we have arranged to add
3905 it in in both cases. */
3909 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3911 macro_build (p
, &icnt
, &expr1
,
3912 mips_isa
< 3 ? "addiu" : "daddiu",
3913 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3915 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3916 mips_isa
< 3 ? "addu" : "daddu",
3917 "d,v,t", tempreg
, tempreg
, AT
);
3921 else if (mips_pic
== EMBEDDED_PIC
)
3924 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3926 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3927 mips_isa
< 3 ? "addiu" : "daddiu",
3928 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3934 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3935 mips_isa
< 3 ? "addu" : "daddu",
3936 "d,v,t", treg
, tempreg
, breg
);
3944 /* The j instruction may not be used in PIC code, since it
3945 requires an absolute address. We convert it to a b
3947 if (mips_pic
== NO_PIC
)
3948 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3950 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3953 /* The jal instructions must be handled as macros because when
3954 generating PIC code they expand to multi-instruction
3955 sequences. Normally they are simple instructions. */
3960 if (mips_pic
== NO_PIC
3961 || mips_pic
== EMBEDDED_PIC
)
3962 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3964 else if (mips_pic
== SVR4_PIC
)
3966 if (sreg
!= PIC_CALL_REG
)
3967 as_warn ("MIPS PIC call to register other than $25");
3969 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3971 if (mips_cprestore_offset
< 0)
3972 as_warn ("No .cprestore pseudo-op used in PIC code");
3975 expr1
.X_add_number
= mips_cprestore_offset
;
3976 macro_build ((char *) NULL
, &icnt
, &expr1
,
3977 mips_isa
< 3 ? "lw" : "ld",
3978 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3987 if (mips_pic
== NO_PIC
)
3988 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3989 else if (mips_pic
== SVR4_PIC
)
3991 /* If this is a reference to an external symbol, and we are
3992 using a small GOT, we want
3993 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3997 lw $gp,cprestore($sp)
3998 The cprestore value is set using the .cprestore
3999 pseudo-op. If we are using a big GOT, we want
4000 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4002 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4006 lw $gp,cprestore($sp)
4007 If the symbol is not external, we want
4008 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4010 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4013 lw $gp,cprestore($sp) */
4017 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4018 mips_isa
< 3 ? "lw" : "ld",
4019 "t,o(b)", PIC_CALL_REG
,
4020 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4021 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4023 p
= frag_var (rs_machine_dependent
, 4, 0,
4024 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4025 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4031 if (reg_needs_delay (GP
))
4035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4036 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4037 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4038 mips_isa
< 3 ? "addu" : "daddu",
4039 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4040 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4041 mips_isa
< 3 ? "lw" : "ld",
4042 "t,o(b)", PIC_CALL_REG
,
4043 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4046 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4047 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4049 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4052 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4055 macro_build (p
, &icnt
, &offset_expr
,
4056 mips_isa
< 3 ? "lw" : "ld",
4057 "t,o(b)", PIC_CALL_REG
,
4058 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4060 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4063 macro_build (p
, &icnt
, &offset_expr
,
4064 mips_isa
< 3 ? "addiu" : "daddiu",
4065 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4066 (int) BFD_RELOC_LO16
);
4067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4068 "jalr", "s", PIC_CALL_REG
);
4069 if (mips_cprestore_offset
< 0)
4070 as_warn ("No .cprestore pseudo-op used in PIC code");
4074 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4076 expr1
.X_add_number
= mips_cprestore_offset
;
4077 macro_build ((char *) NULL
, &icnt
, &expr1
,
4078 mips_isa
< 3 ? "lw" : "ld",
4079 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4083 else if (mips_pic
== EMBEDDED_PIC
)
4085 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4086 /* The linker may expand the call to a longer sequence which
4087 uses $at, so we must break rather than return. */
4163 if (breg
== treg
|| coproc
|| lr
)
4232 if (mask
== M_LWC1_AB
4233 || mask
== M_SWC1_AB
4234 || mask
== M_LDC1_AB
4235 || mask
== M_SDC1_AB
4244 if (offset_expr
.X_op
!= O_constant
4245 && offset_expr
.X_op
!= O_symbol
)
4247 as_bad ("expression too complex");
4248 offset_expr
.X_op
= O_constant
;
4251 /* A constant expression in PIC code can be handled just as it
4252 is in non PIC code. */
4253 if (mips_pic
== NO_PIC
4254 || offset_expr
.X_op
== O_constant
)
4256 /* If this is a reference to a GP relative symbol, and there
4257 is no base register, we want
4258 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4259 Otherwise, if there is no base register, we want
4260 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4261 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4262 If we have a constant, we need two instructions anyhow,
4263 so we always use the latter form.
4265 If we have a base register, and this is a reference to a
4266 GP relative symbol, we want
4267 addu $tempreg,$breg,$gp
4268 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4270 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4271 addu $tempreg,$tempreg,$breg
4272 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4273 With a constant we always use the latter case. */
4276 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4277 || nopic_need_relax (offset_expr
.X_add_symbol
))
4282 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4283 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4284 p
= frag_var (rs_machine_dependent
, 8, 0,
4285 RELAX_ENCODE (4, 8, 0, 4, 0,
4286 (mips_warn_about_macros
4287 || (used_at
&& mips_noat
))),
4288 offset_expr
.X_add_symbol
, (long) 0,
4292 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4295 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4296 (int) BFD_RELOC_LO16
, tempreg
);
4300 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4301 || nopic_need_relax (offset_expr
.X_add_symbol
))
4306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4307 mips_isa
< 3 ? "addu" : "daddu",
4308 "d,v,t", tempreg
, breg
, GP
);
4309 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4310 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4311 p
= frag_var (rs_machine_dependent
, 12, 0,
4312 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4313 offset_expr
.X_add_symbol
, (long) 0,
4316 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4319 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4320 mips_isa
< 3 ? "addu" : "daddu",
4321 "d,v,t", tempreg
, tempreg
, breg
);
4324 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4325 (int) BFD_RELOC_LO16
, tempreg
);
4328 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4330 /* If this is a reference to an external symbol, we want
4331 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4333 <op> $treg,0($tempreg)
4335 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4337 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4338 <op> $treg,0($tempreg)
4339 If there is a base register, we add it to $tempreg before
4340 the <op>. If there is a constant, we stick it in the
4341 <op> instruction. We don't handle constants larger than
4342 16 bits, because we have no way to load the upper 16 bits
4343 (actually, we could handle them for the subset of cases
4344 in which we are not using $at). */
4345 assert (offset_expr
.X_op
== O_symbol
);
4346 expr1
.X_add_number
= offset_expr
.X_add_number
;
4347 offset_expr
.X_add_number
= 0;
4348 if (expr1
.X_add_number
< -0x8000
4349 || expr1
.X_add_number
>= 0x8000)
4350 as_bad ("PIC code offset overflow (max 16 signed bits)");
4352 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4353 mips_isa
< 3 ? "lw" : "ld",
4354 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4355 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4356 p
= frag_var (rs_machine_dependent
, 4, 0,
4357 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4358 offset_expr
.X_add_symbol
, (long) 0,
4360 macro_build (p
, &icnt
, &offset_expr
,
4361 mips_isa
< 3 ? "addiu" : "daddiu",
4362 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4364 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4365 mips_isa
< 3 ? "addu" : "daddu",
4366 "d,v,t", tempreg
, tempreg
, breg
);
4367 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4368 (int) BFD_RELOC_LO16
, tempreg
);
4370 else if (mips_pic
== SVR4_PIC
)
4374 /* If this is a reference to an external symbol, we want
4375 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4376 addu $tempreg,$tempreg,$gp
4377 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4378 <op> $treg,0($tempreg)
4380 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4382 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4383 <op> $treg,0($tempreg)
4384 If there is a base register, we add it to $tempreg before
4385 the <op>. If there is a constant, we stick it in the
4386 <op> instruction. We don't handle constants larger than
4387 16 bits, because we have no way to load the upper 16 bits
4388 (actually, we could handle them for the subset of cases
4389 in which we are not using $at). */
4390 assert (offset_expr
.X_op
== O_symbol
);
4391 expr1
.X_add_number
= offset_expr
.X_add_number
;
4392 offset_expr
.X_add_number
= 0;
4393 if (expr1
.X_add_number
< -0x8000
4394 || expr1
.X_add_number
>= 0x8000)
4395 as_bad ("PIC code offset overflow (max 16 signed bits)");
4396 if (reg_needs_delay (GP
))
4401 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4402 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4403 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4404 mips_isa
< 3 ? "addu" : "daddu",
4405 "d,v,t", tempreg
, tempreg
, GP
);
4406 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4407 mips_isa
< 3 ? "lw" : "ld",
4408 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4410 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4411 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4412 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4415 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4418 macro_build (p
, &icnt
, &offset_expr
,
4419 mips_isa
< 3 ? "lw" : "ld",
4420 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4422 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4424 macro_build (p
, &icnt
, &offset_expr
,
4425 mips_isa
< 3 ? "addiu" : "daddiu",
4426 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4429 mips_isa
< 3 ? "addu" : "daddu",
4430 "d,v,t", tempreg
, tempreg
, breg
);
4431 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4432 (int) BFD_RELOC_LO16
, tempreg
);
4434 else if (mips_pic
== EMBEDDED_PIC
)
4436 /* If there is no base register, we want
4437 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4438 If there is a base register, we want
4439 addu $tempreg,$breg,$gp
4440 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4442 assert (offset_expr
.X_op
== O_symbol
);
4445 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4446 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4451 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4452 mips_isa
< 3 ? "addu" : "daddu",
4453 "d,v,t", tempreg
, breg
, GP
);
4454 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4455 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4468 load_register (&icnt
, treg
, &imm_expr
, 0);
4472 load_register (&icnt
, treg
, &imm_expr
, 1);
4476 if (imm_expr
.X_op
== O_constant
)
4478 load_register (&icnt
, AT
, &imm_expr
, 0);
4479 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4480 "mtc1", "t,G", AT
, treg
);
4485 assert (offset_expr
.X_op
== O_symbol
4486 && strcmp (segment_name (S_GET_SEGMENT
4487 (offset_expr
.X_add_symbol
)),
4489 && offset_expr
.X_add_number
== 0);
4490 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4491 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4496 /* We know that sym is in the .rdata section. First we get the
4497 upper 16 bits of the address. */
4498 if (mips_pic
== NO_PIC
)
4500 /* FIXME: This won't work for a 64 bit address. */
4501 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4503 else if (mips_pic
== SVR4_PIC
)
4505 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4506 mips_isa
< 3 ? "lw" : "ld",
4507 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4509 else if (mips_pic
== EMBEDDED_PIC
)
4511 /* For embedded PIC we pick up the entire address off $gp in
4512 a single instruction. */
4513 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4514 mips_isa
< 3 ? "addiu" : "daddiu",
4515 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4516 offset_expr
.X_op
= O_constant
;
4517 offset_expr
.X_add_number
= 0;
4522 /* Now we load the register(s). */
4524 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4525 treg
, (int) BFD_RELOC_LO16
, AT
);
4528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4529 treg
, (int) BFD_RELOC_LO16
, AT
);
4532 /* FIXME: How in the world do we deal with the possible
4534 offset_expr
.X_add_number
+= 4;
4535 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4536 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4540 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4541 does not become a variant frag. */
4542 frag_wane (frag_now
);
4548 assert (offset_expr
.X_op
== O_symbol
4549 && offset_expr
.X_add_number
== 0);
4550 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4551 if (strcmp (s
, ".lit8") == 0)
4555 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4556 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4560 r
= BFD_RELOC_MIPS_LITERAL
;
4565 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4566 if (mips_pic
== SVR4_PIC
)
4567 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4568 mips_isa
< 3 ? "lw" : "ld",
4569 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4572 /* FIXME: This won't work for a 64 bit address. */
4573 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4578 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4579 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4581 /* To avoid confusion in tc_gen_reloc, we must ensure
4582 that this does not become a variant frag. */
4583 frag_wane (frag_now
);
4594 /* Even on a big endian machine $fn comes before $fn+1. We have
4595 to adjust when loading from memory. */
4598 assert (mips_isa
< 2);
4599 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4600 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4602 /* FIXME: A possible overflow which I don't know how to deal
4604 offset_expr
.X_add_number
+= 4;
4605 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4606 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4609 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4610 does not become a variant frag. */
4611 frag_wane (frag_now
);
4620 * The MIPS assembler seems to check for X_add_number not
4621 * being double aligned and generating:
4624 * addiu at,at,%lo(foo+1)
4627 * But, the resulting address is the same after relocation so why
4628 * generate the extra instruction?
4675 if (offset_expr
.X_op
!= O_symbol
4676 && offset_expr
.X_op
!= O_constant
)
4678 as_bad ("expression too complex");
4679 offset_expr
.X_op
= O_constant
;
4682 /* Even on a big endian machine $fn comes before $fn+1. We have
4683 to adjust when loading from memory. We set coproc if we must
4684 load $fn+1 first. */
4685 if (byte_order
== LITTLE_ENDIAN
)
4688 if (mips_pic
== NO_PIC
4689 || offset_expr
.X_op
== O_constant
)
4691 /* If this is a reference to a GP relative symbol, we want
4692 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4693 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4694 If we have a base register, we use this
4696 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4697 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4698 If this is not a GP relative symbol, we want
4699 lui $at,<sym> (BFD_RELOC_HI16_S)
4700 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4701 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4702 If there is a base register, we add it to $at after the
4703 lui instruction. If there is a constant, we always use
4705 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4706 || nopic_need_relax (offset_expr
.X_add_symbol
))
4725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4726 mips_isa
< 3 ? "addu" : "daddu",
4727 "d,v,t", AT
, breg
, GP
);
4733 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4734 coproc
? treg
+ 1 : treg
,
4735 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4736 offset_expr
.X_add_number
+= 4;
4738 /* Set mips_optimize to 2 to avoid inserting an
4740 hold_mips_optimize
= mips_optimize
;
4742 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4743 coproc
? treg
: treg
+ 1,
4744 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4745 mips_optimize
= hold_mips_optimize
;
4747 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4748 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4749 used_at
&& mips_noat
),
4750 offset_expr
.X_add_symbol
, (long) 0,
4753 /* We just generated two relocs. When tc_gen_reloc
4754 handles this case, it will skip the first reloc and
4755 handle the second. The second reloc already has an
4756 extra addend of 4, which we added above. We must
4757 subtract it out, and then subtract another 4 to make
4758 the first reloc come out right. The second reloc
4759 will come out right because we are going to add 4 to
4760 offset_expr when we build its instruction below. */
4761 offset_expr
.X_add_number
-= 8;
4762 offset_expr
.X_op
= O_constant
;
4764 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4769 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4770 mips_isa
< 3 ? "addu" : "daddu",
4771 "d,v,t", AT
, breg
, AT
);
4775 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4776 coproc
? treg
+ 1 : treg
,
4777 (int) BFD_RELOC_LO16
, AT
);
4780 /* FIXME: How do we handle overflow here? */
4781 offset_expr
.X_add_number
+= 4;
4782 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4783 coproc
? treg
: treg
+ 1,
4784 (int) BFD_RELOC_LO16
, AT
);
4786 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4790 /* If this is a reference to an external symbol, we want
4791 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4796 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4798 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4799 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4800 If there is a base register we add it to $at before the
4801 lwc1 instructions. If there is a constant we include it
4802 in the lwc1 instructions. */
4804 expr1
.X_add_number
= offset_expr
.X_add_number
;
4805 offset_expr
.X_add_number
= 0;
4806 if (expr1
.X_add_number
< -0x8000
4807 || expr1
.X_add_number
>= 0x8000 - 4)
4808 as_bad ("PIC code offset overflow (max 16 signed bits)");
4813 frag_grow (24 + off
);
4814 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4815 mips_isa
< 3 ? "lw" : "ld",
4816 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4817 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4819 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4820 mips_isa
< 3 ? "addu" : "daddu",
4821 "d,v,t", AT
, breg
, AT
);
4822 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4823 coproc
? treg
+ 1 : treg
,
4824 (int) BFD_RELOC_LO16
, AT
);
4825 expr1
.X_add_number
+= 4;
4827 /* Set mips_optimize to 2 to avoid inserting an undesired
4829 hold_mips_optimize
= mips_optimize
;
4831 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4832 coproc
? treg
: treg
+ 1,
4833 (int) BFD_RELOC_LO16
, AT
);
4834 mips_optimize
= hold_mips_optimize
;
4836 (void) frag_var (rs_machine_dependent
, 0, 0,
4837 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4838 offset_expr
.X_add_symbol
, (long) 0,
4841 else if (mips_pic
== SVR4_PIC
)
4845 /* If this is a reference to an external symbol, we want
4846 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4848 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4853 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4855 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4856 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4857 If there is a base register we add it to $at before the
4858 lwc1 instructions. If there is a constant we include it
4859 in the lwc1 instructions. */
4861 expr1
.X_add_number
= offset_expr
.X_add_number
;
4862 offset_expr
.X_add_number
= 0;
4863 if (expr1
.X_add_number
< -0x8000
4864 || expr1
.X_add_number
>= 0x8000 - 4)
4865 as_bad ("PIC code offset overflow (max 16 signed bits)");
4866 if (reg_needs_delay (GP
))
4875 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4876 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4877 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4878 mips_isa
< 3 ? "addu" : "daddu",
4879 "d,v,t", AT
, AT
, GP
);
4880 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4881 mips_isa
< 3 ? "lw" : "ld",
4882 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4883 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4885 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4886 mips_isa
< 3 ? "addu" : "daddu",
4887 "d,v,t", AT
, breg
, AT
);
4888 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4889 coproc
? treg
+ 1 : treg
,
4890 (int) BFD_RELOC_LO16
, AT
);
4891 expr1
.X_add_number
+= 4;
4893 /* Set mips_optimize to 2 to avoid inserting an undesired
4895 hold_mips_optimize
= mips_optimize
;
4897 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4898 coproc
? treg
: treg
+ 1,
4899 (int) BFD_RELOC_LO16
, AT
);
4900 mips_optimize
= hold_mips_optimize
;
4901 expr1
.X_add_number
-= 4;
4903 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4904 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4905 8 + gpdel
+ off
, 1, 0),
4906 offset_expr
.X_add_symbol
, (long) 0,
4910 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4913 macro_build (p
, &icnt
, &offset_expr
,
4914 mips_isa
< 3 ? "lw" : "ld",
4915 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4917 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4921 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4922 mips_isa
< 3 ? "addu" : "daddu",
4923 "d,v,t", AT
, breg
, AT
);
4926 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4927 coproc
? treg
+ 1 : treg
,
4928 (int) BFD_RELOC_LO16
, AT
);
4930 expr1
.X_add_number
+= 4;
4932 /* Set mips_optimize to 2 to avoid inserting an undesired
4934 hold_mips_optimize
= mips_optimize
;
4936 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4937 coproc
? treg
: treg
+ 1,
4938 (int) BFD_RELOC_LO16
, AT
);
4939 mips_optimize
= hold_mips_optimize
;
4941 else if (mips_pic
== EMBEDDED_PIC
)
4943 /* If there is no base register, we use
4944 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4945 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4946 If we have a base register, we use
4948 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4949 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4958 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4959 mips_isa
< 3 ? "addu" : "daddu",
4960 "d,v,t", AT
, breg
, GP
);
4965 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4966 coproc
? treg
+ 1 : treg
,
4967 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4968 offset_expr
.X_add_number
+= 4;
4969 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4970 coproc
? treg
: treg
+ 1,
4971 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4987 assert (mips_isa
< 3);
4988 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4989 (int) BFD_RELOC_LO16
, breg
);
4990 offset_expr
.X_add_number
+= 4;
4991 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4992 (int) BFD_RELOC_LO16
, breg
);
4994 #ifdef LOSING_COMPILER
5000 as_warn ("Macro used $at after \".set noat\"");
5005 struct mips_cl_insn
*ip
;
5007 register int treg
, sreg
, dreg
, breg
;
5022 bfd_reloc_code_real_type r
;
5025 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5026 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5027 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5028 mask
= ip
->insn_mo
->mask
;
5030 expr1
.X_op
= O_constant
;
5031 expr1
.X_op_symbol
= NULL
;
5032 expr1
.X_add_symbol
= NULL
;
5033 expr1
.X_add_number
= 1;
5037 #endif /* LOSING_COMPILER */
5042 macro_build ((char *) NULL
, &icnt
, NULL
,
5043 dbl
? "dmultu" : "multu",
5045 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5051 /* The MIPS assembler some times generates shifts and adds. I'm
5052 not trying to be that fancy. GCC should do this for us
5054 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5055 macro_build ((char *) NULL
, &icnt
, NULL
,
5056 dbl
? "dmult" : "mult",
5058 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5064 mips_emit_delays ();
5066 mips_any_noreorder
= 1;
5067 macro_build ((char *) NULL
, &icnt
, NULL
,
5068 dbl
? "dmult" : "mult",
5070 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5071 macro_build ((char *) NULL
, &icnt
, NULL
,
5072 dbl
? "dsra32" : "sra",
5073 "d,w,<", dreg
, dreg
, 31);
5074 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5076 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5079 expr1
.X_add_number
= 8;
5080 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5081 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5082 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5085 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5091 mips_emit_delays ();
5093 mips_any_noreorder
= 1;
5094 macro_build ((char *) NULL
, &icnt
, NULL
,
5095 dbl
? "dmultu" : "multu",
5097 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5098 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5100 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5103 expr1
.X_add_number
= 8;
5104 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5105 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5106 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5112 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5113 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5114 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5116 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5120 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5121 (int) (imm_expr
.X_add_number
& 0x1f));
5122 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5123 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5124 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5128 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5129 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5130 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5132 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5136 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5137 (int) (imm_expr
.X_add_number
& 0x1f));
5138 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5139 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5140 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5144 assert (mips_isa
< 2);
5145 /* Even on a big endian machine $fn comes before $fn+1. We have
5146 to adjust when storing to memory. */
5147 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5148 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
5149 (int) BFD_RELOC_LO16
, breg
);
5150 offset_expr
.X_add_number
+= 4;
5151 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5152 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
5153 (int) BFD_RELOC_LO16
, breg
);
5158 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5159 treg
, (int) BFD_RELOC_LO16
);
5161 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5162 sreg
, (int) BFD_RELOC_LO16
);
5165 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5167 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5168 dreg
, (int) BFD_RELOC_LO16
);
5173 if (imm_expr
.X_add_number
== 0)
5175 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5176 sreg
, (int) BFD_RELOC_LO16
);
5181 as_warn ("Instruction %s: result is always false",
5183 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5186 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5188 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5189 sreg
, (int) BFD_RELOC_LO16
);
5192 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5194 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5195 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5196 mips_isa
< 3 ? "addiu" : "daddiu",
5197 "t,r,j", dreg
, sreg
,
5198 (int) BFD_RELOC_LO16
);
5203 load_register (&icnt
, AT
, &imm_expr
, 0);
5204 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5208 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5209 (int) BFD_RELOC_LO16
);
5214 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5220 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5221 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5222 (int) BFD_RELOC_LO16
);
5225 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5227 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5229 macro_build ((char *) NULL
, &icnt
, &expr1
,
5230 mask
== M_SGE_I
? "slti" : "sltiu",
5231 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5236 load_register (&icnt
, AT
, &imm_expr
, 0);
5237 macro_build ((char *) NULL
, &icnt
, NULL
,
5238 mask
== M_SGE_I
? "slt" : "sltu",
5239 "d,v,t", dreg
, sreg
, AT
);
5242 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5243 (int) BFD_RELOC_LO16
);
5248 case M_SGT
: /* sreg > treg <==> treg < sreg */
5254 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5257 case M_SGT_I
: /* sreg > I <==> I < sreg */
5263 load_register (&icnt
, AT
, &imm_expr
, 0);
5264 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5267 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5273 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5274 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5275 (int) BFD_RELOC_LO16
);
5278 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5284 load_register (&icnt
, AT
, &imm_expr
, 0);
5285 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5286 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5287 (int) BFD_RELOC_LO16
);
5291 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5293 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5294 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5297 load_register (&icnt
, AT
, &imm_expr
, 0);
5298 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5302 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5304 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5305 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5308 load_register (&icnt
, AT
, &imm_expr
, 0);
5309 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5315 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5318 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5322 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5324 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5330 if (imm_expr
.X_add_number
== 0)
5332 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5338 as_warn ("Instruction %s: result is always true",
5340 macro_build ((char *) NULL
, &icnt
, &expr1
,
5341 mips_isa
< 3 ? "addiu" : "daddiu",
5342 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5345 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5347 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5348 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5351 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5353 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5354 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5355 mips_isa
< 3 ? "addiu" : "daddiu",
5356 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5361 load_register (&icnt
, AT
, &imm_expr
, 0);
5362 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5366 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5374 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5376 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5377 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5378 dbl
? "daddi" : "addi",
5379 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5382 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5383 macro_build ((char *) NULL
, &icnt
, NULL
,
5384 dbl
? "dsub" : "sub",
5385 "d,v,t", dreg
, sreg
, AT
);
5391 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5393 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5394 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5395 dbl
? "daddiu" : "addiu",
5396 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5399 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5400 macro_build ((char *) NULL
, &icnt
, NULL
,
5401 dbl
? "dsubu" : "subu",
5402 "d,v,t", dreg
, sreg
, AT
);
5423 load_register (&icnt
, AT
, &imm_expr
, 0);
5424 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5429 assert (mips_isa
< 2);
5430 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5431 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5434 * Is the double cfc1 instruction a bug in the mips assembler;
5435 * or is there a reason for it?
5437 mips_emit_delays ();
5439 mips_any_noreorder
= 1;
5440 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5441 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5442 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5443 expr1
.X_add_number
= 3;
5444 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5445 (int) BFD_RELOC_LO16
);
5446 expr1
.X_add_number
= 2;
5447 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5448 (int) BFD_RELOC_LO16
);
5449 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5450 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5451 macro_build ((char *) NULL
, &icnt
, NULL
,
5452 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5453 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5454 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5464 if (offset_expr
.X_add_number
>= 0x7fff)
5465 as_bad ("operand overflow");
5466 /* avoid load delay */
5467 if (byte_order
== LITTLE_ENDIAN
)
5468 offset_expr
.X_add_number
+= 1;
5469 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5470 (int) BFD_RELOC_LO16
, breg
);
5471 if (byte_order
== LITTLE_ENDIAN
)
5472 offset_expr
.X_add_number
-= 1;
5474 offset_expr
.X_add_number
+= 1;
5475 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5476 (int) BFD_RELOC_LO16
, breg
);
5477 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5478 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5491 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5492 as_bad ("operand overflow");
5493 if (byte_order
== LITTLE_ENDIAN
)
5494 offset_expr
.X_add_number
+= off
;
5495 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5496 (int) BFD_RELOC_LO16
, breg
);
5497 if (byte_order
== LITTLE_ENDIAN
)
5498 offset_expr
.X_add_number
-= off
;
5500 offset_expr
.X_add_number
+= off
;
5501 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5502 (int) BFD_RELOC_LO16
, breg
);
5515 load_address (&icnt
, AT
, &offset_expr
);
5517 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5518 mips_isa
< 3 ? "addu" : "daddu",
5519 "d,v,t", AT
, AT
, breg
);
5520 if (byte_order
== LITTLE_ENDIAN
)
5521 expr1
.X_add_number
= off
;
5523 expr1
.X_add_number
= 0;
5524 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5525 (int) BFD_RELOC_LO16
, AT
);
5526 if (byte_order
== LITTLE_ENDIAN
)
5527 expr1
.X_add_number
= 0;
5529 expr1
.X_add_number
= off
;
5530 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5531 (int) BFD_RELOC_LO16
, AT
);
5536 load_address (&icnt
, AT
, &offset_expr
);
5538 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5539 mips_isa
< 3 ? "addu" : "daddu",
5540 "d,v,t", AT
, AT
, breg
);
5541 if (byte_order
== BIG_ENDIAN
)
5542 expr1
.X_add_number
= 0;
5543 macro_build ((char *) NULL
, &icnt
, &expr1
,
5544 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5545 (int) BFD_RELOC_LO16
, AT
);
5546 if (byte_order
== BIG_ENDIAN
)
5547 expr1
.X_add_number
= 1;
5549 expr1
.X_add_number
= 0;
5550 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5551 (int) BFD_RELOC_LO16
, AT
);
5552 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5554 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5559 if (offset_expr
.X_add_number
>= 0x7fff)
5560 as_bad ("operand overflow");
5561 if (byte_order
== BIG_ENDIAN
)
5562 offset_expr
.X_add_number
+= 1;
5563 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5564 (int) BFD_RELOC_LO16
, breg
);
5565 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5566 if (byte_order
== BIG_ENDIAN
)
5567 offset_expr
.X_add_number
-= 1;
5569 offset_expr
.X_add_number
+= 1;
5570 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5571 (int) BFD_RELOC_LO16
, breg
);
5584 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5585 as_bad ("operand overflow");
5586 if (byte_order
== LITTLE_ENDIAN
)
5587 offset_expr
.X_add_number
+= off
;
5588 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5589 (int) BFD_RELOC_LO16
, breg
);
5590 if (byte_order
== LITTLE_ENDIAN
)
5591 offset_expr
.X_add_number
-= off
;
5593 offset_expr
.X_add_number
+= off
;
5594 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5595 (int) BFD_RELOC_LO16
, breg
);
5608 load_address (&icnt
, AT
, &offset_expr
);
5610 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5611 mips_isa
< 3 ? "addu" : "daddu",
5612 "d,v,t", AT
, AT
, breg
);
5613 if (byte_order
== LITTLE_ENDIAN
)
5614 expr1
.X_add_number
= off
;
5616 expr1
.X_add_number
= 0;
5617 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5618 (int) BFD_RELOC_LO16
, AT
);
5619 if (byte_order
== LITTLE_ENDIAN
)
5620 expr1
.X_add_number
= 0;
5622 expr1
.X_add_number
= off
;
5623 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5624 (int) BFD_RELOC_LO16
, AT
);
5628 load_address (&icnt
, AT
, &offset_expr
);
5630 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5631 mips_isa
< 3 ? "addu" : "daddu",
5632 "d,v,t", AT
, AT
, breg
);
5633 if (byte_order
== LITTLE_ENDIAN
)
5634 expr1
.X_add_number
= 0;
5635 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5636 (int) BFD_RELOC_LO16
, AT
);
5637 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5639 if (byte_order
== LITTLE_ENDIAN
)
5640 expr1
.X_add_number
= 1;
5642 expr1
.X_add_number
= 0;
5643 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5644 (int) BFD_RELOC_LO16
, AT
);
5645 if (byte_order
== LITTLE_ENDIAN
)
5646 expr1
.X_add_number
= 0;
5648 expr1
.X_add_number
= 1;
5649 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5650 (int) BFD_RELOC_LO16
, AT
);
5651 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5653 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5658 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5662 as_warn ("Macro used $at after \".set noat\"");
5665 /* Implement macros in mips16 mode. */
5669 struct mips_cl_insn
*ip
;
5672 int xreg
, yreg
, zreg
, tmp
;
5676 const char *s
, *s2
, *s3
;
5678 mask
= ip
->insn_mo
->mask
;
5680 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5681 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5682 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5686 expr1
.X_op
= O_constant
;
5687 expr1
.X_op_symbol
= NULL
;
5688 expr1
.X_add_symbol
= NULL
;
5689 expr1
.X_add_number
= 1;
5708 mips_emit_delays ();
5710 mips_any_noreorder
= 1;
5711 macro_build ((char *) NULL
, &icnt
, NULL
,
5712 dbl
? "ddiv" : "div",
5713 "0,x,y", xreg
, yreg
);
5714 expr1
.X_add_number
= 4;
5715 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5716 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5717 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5718 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5719 since that causes an overflow. We should do that as well,
5720 but I don't see how to do the comparisons without a temporary
5723 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5742 mips_emit_delays ();
5744 mips_any_noreorder
= 1;
5745 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5746 expr1
.X_add_number
= 4;
5747 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5748 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5749 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5751 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5759 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5760 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5761 dbl
? "daddiu" : "addiu",
5762 "y,x,4", yreg
, xreg
);
5766 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5767 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5772 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5773 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
5796 goto do_reverse_branch
;
5800 goto do_reverse_branch
;
5812 goto do_reverse_branch
;
5823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
5825 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5852 goto do_addone_branch_i
;
5857 goto do_addone_branch_i
;
5872 goto do_addone_branch_i
;
5879 ++imm_expr
.X_add_number
;
5882 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
5883 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5888 /* This routine assembles an instruction into its binary format. As a
5889 side effect, it sets one of the global variables imm_reloc or
5890 offset_reloc to the type of relocation to do if one of the operands
5891 is an address expression. */
5896 struct mips_cl_insn
*ip
;
5901 struct mips_opcode
*insn
;
5904 unsigned int lastregno
= 0;
5909 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5921 as_fatal ("Unknown opcode: `%s'", str
);
5923 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5925 insn_error
= "unrecognized opcode";
5933 assert (strcmp (insn
->name
, str
) == 0);
5935 if (insn
->pinfo
== INSN_MACRO
)
5936 insn_isa
= insn
->match
;
5937 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5939 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5941 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5946 if (insn_isa
> mips_isa
5947 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5949 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5951 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5954 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5955 && strcmp (insn
->name
, insn
[1].name
) == 0)
5960 if (insn_isa
<= mips_isa
)
5961 insn_error
= "opcode not supported on this processor";
5964 static char buf
[100];
5966 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
5973 ip
->insn_opcode
= insn
->match
;
5974 for (args
= insn
->args
;; ++args
)
5980 case '\0': /* end of args */
5993 ip
->insn_opcode
|= lastregno
<< 21;
5998 ip
->insn_opcode
|= lastregno
<< 16;
6002 ip
->insn_opcode
|= lastregno
<< 11;
6008 /* handle optional base register.
6009 Either the base register is omitted or
6010 we must have a left paren. */
6011 /* this is dependent on the next operand specifier
6012 is a 'b' for base register */
6013 assert (args
[1] == 'b');
6017 case ')': /* these must match exactly */
6022 case '<': /* must be at least one digit */
6024 * According to the manual, if the shift amount is greater
6025 * than 31 or less than 0 the the shift amount should be
6026 * mod 32. In reality the mips assembler issues an error.
6027 * We issue a warning and mask out all but the low 5 bits.
6029 my_getExpression (&imm_expr
, s
);
6030 check_absolute_expr (ip
, &imm_expr
);
6031 if ((unsigned long) imm_expr
.X_add_number
> 31)
6033 as_warn ("Improper shift amount (%ld)",
6034 (long) imm_expr
.X_add_number
);
6035 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6037 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6038 imm_expr
.X_op
= O_absent
;
6042 case '>': /* shift amount minus 32 */
6043 my_getExpression (&imm_expr
, s
);
6044 check_absolute_expr (ip
, &imm_expr
);
6045 if ((unsigned long) imm_expr
.X_add_number
< 32
6046 || (unsigned long) imm_expr
.X_add_number
> 63)
6048 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6049 imm_expr
.X_op
= O_absent
;
6053 case 'k': /* cache code */
6054 case 'h': /* prefx code */
6055 my_getExpression (&imm_expr
, s
);
6056 check_absolute_expr (ip
, &imm_expr
);
6057 if ((unsigned long) imm_expr
.X_add_number
> 31)
6059 as_warn ("Invalid value for `%s' (%lu)",
6061 (unsigned long) imm_expr
.X_add_number
);
6062 imm_expr
.X_add_number
&= 0x1f;
6065 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6067 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6068 imm_expr
.X_op
= O_absent
;
6072 case 'c': /* break code */
6073 my_getExpression (&imm_expr
, s
);
6074 check_absolute_expr (ip
, &imm_expr
);
6075 if ((unsigned) imm_expr
.X_add_number
> 1023)
6076 as_warn ("Illegal break code (%ld)",
6077 (long) imm_expr
.X_add_number
);
6078 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6079 imm_expr
.X_op
= O_absent
;
6083 case 'B': /* syscall code */
6084 my_getExpression (&imm_expr
, s
);
6085 check_absolute_expr (ip
, &imm_expr
);
6086 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6087 as_warn ("Illegal syscall code (%ld)",
6088 (long) imm_expr
.X_add_number
);
6089 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6090 imm_expr
.X_op
= O_absent
;
6094 case 'C': /* Coprocessor code */
6095 my_getExpression (&imm_expr
, s
);
6096 check_absolute_expr (ip
, &imm_expr
);
6097 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6099 as_warn ("Coproccesor code > 25 bits (%ld)",
6100 (long) imm_expr
.X_add_number
);
6101 imm_expr
.X_add_number
&= ((1<<25) - 1);
6103 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6104 imm_expr
.X_op
= O_absent
;
6108 case 'b': /* base register */
6109 case 'd': /* destination register */
6110 case 's': /* source register */
6111 case 't': /* target register */
6112 case 'r': /* both target and source */
6113 case 'v': /* both dest and source */
6114 case 'w': /* both dest and target */
6115 case 'E': /* coprocessor target register */
6116 case 'G': /* coprocessor destination register */
6117 case 'x': /* ignore register name */
6118 case 'z': /* must be zero register */
6132 while (isdigit (*s
));
6134 as_bad ("Invalid register number (%d)", regno
);
6136 else if (*args
== 'E' || *args
== 'G')
6140 if (s
[1] == 'f' && s
[2] == 'p')
6145 else if (s
[1] == 's' && s
[2] == 'p')
6150 else if (s
[1] == 'g' && s
[2] == 'p')
6155 else if (s
[1] == 'a' && s
[2] == 't')
6160 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6165 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6177 as_warn ("Used $at without \".set noat\"");
6183 if (c
== 'r' || c
== 'v' || c
== 'w')
6190 /* 'z' only matches $0. */
6191 if (c
== 'z' && regno
!= 0)
6199 ip
->insn_opcode
|= regno
<< 21;
6203 ip
->insn_opcode
|= regno
<< 11;
6208 ip
->insn_opcode
|= regno
<< 16;
6211 /* This case exists because on the r3000 trunc
6212 expands into a macro which requires a gp
6213 register. On the r6000 or r4000 it is
6214 assembled into a single instruction which
6215 ignores the register. Thus the insn version
6216 is MIPS_ISA2 and uses 'x', and the macro
6217 version is MIPS_ISA1 and uses 't'. */
6220 /* This case is for the div instruction, which
6221 acts differently if the destination argument
6222 is $0. This only matches $0, and is checked
6223 outside the switch. */
6234 ip
->insn_opcode
|= lastregno
<< 21;
6237 ip
->insn_opcode
|= lastregno
<< 16;
6242 case 'D': /* floating point destination register */
6243 case 'S': /* floating point source register */
6244 case 'T': /* floating point target register */
6245 case 'R': /* floating point source register */
6249 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6259 while (isdigit (*s
));
6262 as_bad ("Invalid float register number (%d)", regno
);
6264 if ((regno
& 1) != 0
6266 && ! (strcmp (str
, "mtc1") == 0
6267 || strcmp (str
, "mfc1") == 0
6268 || strcmp (str
, "lwc1") == 0
6269 || strcmp (str
, "swc1") == 0
6270 || strcmp (str
, "l.s") == 0
6271 || strcmp (str
, "s.s") == 0))
6272 as_warn ("Float register should be even, was %d",
6280 if (c
== 'V' || c
== 'W')
6290 ip
->insn_opcode
|= regno
<< 6;
6294 ip
->insn_opcode
|= regno
<< 11;
6298 ip
->insn_opcode
|= regno
<< 16;
6301 ip
->insn_opcode
|= regno
<< 21;
6310 ip
->insn_opcode
|= lastregno
<< 11;
6313 ip
->insn_opcode
|= lastregno
<< 16;
6319 my_getExpression (&imm_expr
, s
);
6320 if (imm_expr
.X_op
!= O_big
6321 && imm_expr
.X_op
!= O_constant
)
6322 insn_error
= "absolute expression required";
6327 my_getExpression (&offset_expr
, s
);
6328 imm_reloc
= BFD_RELOC_32
;
6340 unsigned char temp
[8];
6342 unsigned int length
;
6347 /* These only appear as the last operand in an
6348 instruction, and every instruction that accepts
6349 them in any variant accepts them in all variants.
6350 This means we don't have to worry about backing out
6351 any changes if the instruction does not match.
6353 The difference between them is the size of the
6354 floating point constant and where it goes. For 'F'
6355 and 'L' the constant is 64 bits; for 'f' and 'l' it
6356 is 32 bits. Where the constant is placed is based
6357 on how the MIPS assembler does things:
6360 f -- immediate value
6363 The .lit4 and .lit8 sections are only used if
6364 permitted by the -G argument.
6366 When generating embedded PIC code, we use the
6367 .lit8 section but not the .lit4 section (we can do
6368 .lit4 inline easily; we need to put .lit8
6369 somewhere in the data segment, and using .lit8
6370 permits the linker to eventually combine identical
6373 f64
= *args
== 'F' || *args
== 'L';
6375 save_in
= input_line_pointer
;
6376 input_line_pointer
= s
;
6377 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6379 s
= input_line_pointer
;
6380 input_line_pointer
= save_in
;
6381 if (err
!= NULL
&& *err
!= '\0')
6383 as_bad ("Bad floating point constant: %s", err
);
6384 memset (temp
, '\0', sizeof temp
);
6385 length
= f64
? 8 : 4;
6388 assert (length
== (f64
? 8 : 4));
6392 && (! USE_GLOBAL_POINTER_OPT
6393 || mips_pic
== EMBEDDED_PIC
6394 || g_switch_value
< 4)
6397 imm_expr
.X_op
= O_constant
;
6398 if (byte_order
== LITTLE_ENDIAN
)
6399 imm_expr
.X_add_number
=
6400 (((((((int) temp
[3] << 8)
6405 imm_expr
.X_add_number
=
6406 (((((((int) temp
[0] << 8)
6413 const char *newname
;
6416 /* Switch to the right section. */
6418 subseg
= now_subseg
;
6421 default: /* unused default case avoids warnings. */
6423 newname
= RDATA_SECTION_NAME
;
6424 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6428 newname
= RDATA_SECTION_NAME
;
6431 assert (!USE_GLOBAL_POINTER_OPT
6432 || g_switch_value
>= 4);
6436 new_seg
= subseg_new (newname
, (subsegT
) 0);
6437 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6438 bfd_set_section_flags (stdoutput
, new_seg
,
6443 frag_align (*args
== 'l' ? 2 : 3, 0);
6444 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6445 record_alignment (new_seg
, 4);
6447 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6449 as_bad ("Can't use floating point insn in this section");
6451 /* Set the argument to the current address in the
6453 offset_expr
.X_op
= O_symbol
;
6454 offset_expr
.X_add_symbol
=
6455 symbol_new ("L0\001", now_seg
,
6456 (valueT
) frag_now_fix (), frag_now
);
6457 offset_expr
.X_add_number
= 0;
6459 /* Put the floating point number into the section. */
6460 p
= frag_more ((int) length
);
6461 memcpy (p
, temp
, length
);
6463 /* Switch back to the original section. */
6464 subseg_set (seg
, subseg
);
6469 case 'i': /* 16 bit unsigned immediate */
6470 case 'j': /* 16 bit signed immediate */
6471 imm_reloc
= BFD_RELOC_LO16
;
6472 c
= my_getSmallExpression (&imm_expr
, s
);
6477 if (imm_expr
.X_op
== O_constant
)
6478 imm_expr
.X_add_number
=
6479 (imm_expr
.X_add_number
>> 16) & 0xffff;
6482 imm_reloc
= BFD_RELOC_HI16_S
;
6483 imm_unmatched_hi
= true;
6486 imm_reloc
= BFD_RELOC_HI16
;
6491 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6492 || ((imm_expr
.X_add_number
< 0
6493 || imm_expr
.X_add_number
>= 0x10000)
6494 && imm_expr
.X_op
== O_constant
))
6496 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6497 !strcmp (insn
->name
, insn
[1].name
))
6499 if (imm_expr
.X_op
!= O_constant
6500 && imm_expr
.X_op
!= O_big
)
6501 insn_error
= "absolute expression required";
6503 as_bad ("16 bit expression not in range 0..65535");
6511 /* The upper bound should be 0x8000, but
6512 unfortunately the MIPS assembler accepts numbers
6513 from 0x8000 to 0xffff and sign extends them, and
6514 we want to be compatible. We only permit this
6515 extended range for an instruction which does not
6516 provide any further alternates, since those
6517 alternates may handle other cases. People should
6518 use the numbers they mean, rather than relying on
6519 a mysterious sign extension. */
6520 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6521 strcmp (insn
->name
, insn
[1].name
) == 0);
6526 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6527 || ((imm_expr
.X_add_number
< -0x8000
6528 || imm_expr
.X_add_number
>= max
)
6529 && imm_expr
.X_op
== O_constant
)
6531 && imm_expr
.X_add_number
< 0
6533 && imm_expr
.X_unsigned
6534 && sizeof (imm_expr
.X_add_number
) <= 4))
6538 if (imm_expr
.X_op
!= O_constant
6539 && imm_expr
.X_op
!= O_big
)
6540 insn_error
= "absolute expression required";
6542 as_bad ("16 bit expression not in range -32768..32767");
6548 case 'o': /* 16 bit offset */
6549 c
= my_getSmallExpression (&offset_expr
, s
);
6551 /* If this value won't fit into a 16 bit offset, then go
6552 find a macro that will generate the 32 bit offset
6553 code pattern. As a special hack, we accept the
6554 difference of two local symbols as a constant. This
6555 is required to suppose embedded PIC switches, which
6556 use an instruction which looks like
6557 lw $4,$L12-$LS12($4)
6558 The problem with handling this in a more general
6559 fashion is that the macro function doesn't expect to
6560 see anything which can be handled in a single
6561 constant instruction. */
6563 && (offset_expr
.X_op
!= O_constant
6564 || offset_expr
.X_add_number
>= 0x8000
6565 || offset_expr
.X_add_number
< -0x8000)
6566 && (mips_pic
!= EMBEDDED_PIC
6567 || offset_expr
.X_op
!= O_subtract
6568 || now_seg
!= text_section
6569 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6573 offset_reloc
= BFD_RELOC_LO16
;
6574 if (c
== 'h' || c
== 'H')
6576 assert (offset_expr
.X_op
== O_constant
);
6577 offset_expr
.X_add_number
=
6578 (offset_expr
.X_add_number
>> 16) & 0xffff;
6583 case 'p': /* pc relative offset */
6584 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6585 my_getExpression (&offset_expr
, s
);
6589 case 'u': /* upper 16 bits */
6590 c
= my_getSmallExpression (&imm_expr
, s
);
6591 if (imm_expr
.X_op
== O_constant
6592 && (imm_expr
.X_add_number
< 0
6593 || imm_expr
.X_add_number
>= 0x10000))
6594 as_bad ("lui expression not in range 0..65535");
6595 imm_reloc
= BFD_RELOC_LO16
;
6600 if (imm_expr
.X_op
== O_constant
)
6601 imm_expr
.X_add_number
=
6602 (imm_expr
.X_add_number
>> 16) & 0xffff;
6605 imm_reloc
= BFD_RELOC_HI16_S
;
6606 imm_unmatched_hi
= true;
6609 imm_reloc
= BFD_RELOC_HI16
;
6615 case 'a': /* 26 bit address */
6616 my_getExpression (&offset_expr
, s
);
6618 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6621 case 'N': /* 3 bit branch condition code */
6622 case 'M': /* 3 bit compare condition code */
6623 if (strncmp (s
, "$fcc", 4) != 0)
6633 while (isdigit (*s
));
6635 as_bad ("invalid condition code register $fcc%d", regno
);
6637 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6639 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6643 fprintf (stderr
, "bad char = '%c'\n", *args
);
6648 /* Args don't match. */
6649 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6650 !strcmp (insn
->name
, insn
[1].name
))
6656 insn_error
= "illegal operands";
6661 /* This routine assembles an instruction into its binary format when
6662 assembling for the mips16. As a side effect, it sets one of the
6663 global variables imm_reloc or offset_reloc to the type of
6664 relocation to do if one of the operands is an address expression.
6665 It also sets mips16_small and mips16_ext if the user explicitly
6666 requested a small or extended instruction. */
6671 struct mips_cl_insn
*ip
;
6675 struct mips_opcode
*insn
;
6678 unsigned int lastregno
= 0;
6683 mips16_small
= false;
6686 for (s
= str
; islower (*s
); ++s
)
6698 if (s
[1] == 't' && s
[2] == ' ')
6701 mips16_small
= true;
6705 else if (s
[1] == 'e' && s
[2] == ' ')
6714 insn_error
= "unknown opcode";
6718 if (! mips16_autoextend
&& ! mips16_ext
)
6719 mips16_small
= true;
6721 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6723 insn_error
= "unrecognized opcode";
6730 assert (strcmp (insn
->name
, str
) == 0);
6733 ip
->insn_opcode
= insn
->match
;
6734 ip
->use_extend
= false;
6735 imm_expr
.X_op
= O_absent
;
6736 imm_reloc
= BFD_RELOC_UNUSED
;
6737 offset_expr
.X_op
= O_absent
;
6738 offset_reloc
= BFD_RELOC_UNUSED
;
6739 for (args
= insn
->args
; 1; ++args
)
6746 /* In this switch statement we call break if we did not find
6747 a match, continue if we did find a match, or return if we
6756 /* Stuff the immediate value in now, if we can. */
6757 if (imm_expr
.X_op
== O_constant
6758 && imm_reloc
> BFD_RELOC_UNUSED
6759 && insn
->pinfo
!= INSN_MACRO
)
6761 mips16_immed ((char *) NULL
, 0,
6762 imm_reloc
- BFD_RELOC_UNUSED
,
6763 imm_expr
.X_add_number
, true, mips16_small
,
6764 mips16_ext
, &ip
->insn_opcode
,
6765 &ip
->use_extend
, &ip
->extend
);
6766 imm_expr
.X_op
= O_absent
;
6767 imm_reloc
= BFD_RELOC_UNUSED
;
6781 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6784 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6800 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6802 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6829 while (isdigit (*s
));
6832 as_bad ("invalid register number (%d)", regno
);
6838 if (s
[1] == 'f' && s
[2] == 'p')
6843 else if (s
[1] == 's' && s
[2] == 'p')
6848 else if (s
[1] == 'g' && s
[2] == 'p')
6853 else if (s
[1] == 'a' && s
[2] == 't')
6858 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6863 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6876 if (c
== 'v' || c
== 'w')
6878 regno
= mips16_to_32_reg_map
[lastregno
];
6892 regno
= mips32_to_16_reg_map
[regno
];
6897 regno
= ILLEGAL_REG
;
6902 regno
= ILLEGAL_REG
;
6907 regno
= ILLEGAL_REG
;
6912 if (regno
== AT
&& ! mips_noat
)
6913 as_warn ("used $at without \".set noat\"");
6920 if (regno
== ILLEGAL_REG
)
6927 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
6931 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
6934 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
6937 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
6943 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
6946 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
6947 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
6957 if (strncmp (s
, "$pc", 3) == 0)
6980 if (s
[0] == '$' && isdigit (s
[1]))
6982 /* Looks like a register name. */
6985 my_getExpression (&imm_expr
, s
);
6986 /* We need to relax this instruction. */
6987 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
6996 /* We use offset_reloc rather than imm_reloc for the PC
6997 relative operands. This lets macros with both
6998 immediate and address operands work correctly. */
6999 if (s
[0] == '$' && isdigit (s
[1]))
7001 /* Looks like a register name. */
7004 my_getExpression (&offset_expr
, s
);
7005 /* We need to relax this instruction. */
7006 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7010 case '6': /* break code */
7011 my_getExpression (&imm_expr
, s
);
7012 check_absolute_expr (ip
, &imm_expr
);
7013 if ((unsigned long) imm_expr
.X_add_number
> 63)
7015 as_warn ("Invalid value for `%s' (%lu)",
7017 (unsigned long) imm_expr
.X_add_number
);
7018 imm_expr
.X_add_number
&= 0x3f;
7020 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7021 imm_expr
.X_op
= O_absent
;
7025 case 'a': /* 26 bit address */
7026 my_getExpression (&offset_expr
, s
);
7028 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7029 ip
->insn_opcode
<<= 16;
7032 case 'l': /* register list for entry macro */
7033 case 'L': /* register list for exit macro */
7045 while (*s
== ' ' || *s
== ',')
7049 as_bad ("can't parse register list");
7054 while (isdigit (*s
))
7071 while (isdigit (*s
))
7078 if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7079 mask
|= (reg2
- 3) << 3;
7080 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7081 mask
|= (reg2
- 15) << 1;
7082 else if (reg1
== 31 && reg2
== 31)
7085 as_bad ("invalid register list");
7087 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7097 /* Args don't match. */
7098 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7099 strcmp (insn
->name
, insn
[1].name
) == 0)
7106 insn_error
= "illegal operands";
7112 /* This structure holds information we know about a mips16 immediate
7115 struct mips16_immed_operand
7117 /* The type code used in the argument string in the opcode table. */
7119 /* The number of bits in the short form of the opcode. */
7121 /* The number of bits in the extended form of the opcode. */
7123 /* The amount by which the short form is shifted when it is used;
7124 for example, the sw instruction has a shift count of 2. */
7126 /* The amount by which the short form is shifted when it is stored
7127 into the instruction code. */
7129 /* Non-zero if the short form is unsigned. */
7131 /* Non-zero if the extended form is unsigned. */
7133 /* Non-zero if the value is PC relative. */
7137 /* The mips16 immediate operand types. */
7139 static const struct mips16_immed_operand mips16_immed_operands
[] =
7141 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7142 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7143 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7144 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7145 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7146 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7147 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7148 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7149 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7150 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7151 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7152 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7153 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7154 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7155 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7156 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7157 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7158 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7159 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7160 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7161 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7164 #define MIPS16_NUM_IMMED \
7165 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7167 /* Handle a mips16 instruction with an immediate value. This or's the
7168 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7169 whether an extended value is needed; if one is needed, it sets
7170 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7171 If SMALL is true, an unextended opcode was explicitly requested.
7172 If EXT is true, an extended opcode was explicitly requested. If
7173 WARN is true, warn if EXT does not match reality. */
7176 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7185 unsigned long *insn
;
7186 boolean
*use_extend
;
7187 unsigned short *extend
;
7189 register const struct mips16_immed_operand
*op
;
7190 int mintiny
, maxtiny
;
7193 op
= mips16_immed_operands
;
7194 while (op
->type
!= type
)
7197 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7202 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7205 maxtiny
= 1 << op
->nbits
;
7210 maxtiny
= (1 << op
->nbits
) - 1;
7215 mintiny
= - (1 << (op
->nbits
- 1));
7216 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7219 /* Branch offsets have an implicit 0 in the lowest bit. */
7220 if (type
== 'p' || type
== 'q')
7223 as_bad_where (file
, line
, "branch to odd address");
7227 if ((val
& ((1 << op
->shift
) - 1)) != 0
7228 || val
< (mintiny
<< op
->shift
)
7229 || val
> (maxtiny
<< op
->shift
))
7234 if (warn
&& ext
&& ! needext
)
7235 as_warn_where (file
, line
, "extended operand requested but not required");
7236 if (small
&& needext
)
7237 as_bad_where (file
, line
, "invalid unextended operand value");
7239 if (small
|| (! ext
&& ! needext
))
7243 *use_extend
= false;
7244 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7245 insnval
<<= op
->op_shift
;
7250 long minext
, maxext
;
7256 maxext
= (1 << op
->extbits
) - 1;
7260 minext
= - (1 << (op
->extbits
- 1));
7261 maxext
= (1 << (op
->extbits
- 1)) - 1;
7263 if (val
< minext
|| val
> maxext
)
7264 as_bad_where (file
, line
,
7265 "operand value out of range for instruction");
7268 if (op
->extbits
== 16)
7270 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7273 else if (op
->extbits
== 15)
7275 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7280 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7284 *extend
= (unsigned short) extval
;
7293 my_getSmallExpression (ep
, str
)
7304 ((str
[1] == 'h' && str
[2] == 'i')
7305 || (str
[1] == 'H' && str
[2] == 'I')
7306 || (str
[1] == 'l' && str
[2] == 'o'))
7318 * A small expression may be followed by a base register.
7319 * Scan to the end of this operand, and then back over a possible
7320 * base register. Then scan the small expression up to that
7321 * point. (Based on code in sparc.c...)
7323 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7325 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7327 if (isdigit (sp
[-2]))
7329 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7331 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7337 else if (sp
- 5 >= str
7340 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7341 || (sp
[-3] == 's' && sp
[-2] == 'p')
7342 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7343 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7349 /* no expression means zero offset */
7352 /* %xx(reg) is an error */
7353 ep
->X_op
= O_absent
;
7358 ep
->X_op
= O_constant
;
7361 ep
->X_add_symbol
= NULL
;
7362 ep
->X_op_symbol
= NULL
;
7363 ep
->X_add_number
= 0;
7368 my_getExpression (ep
, str
);
7375 my_getExpression (ep
, str
);
7376 return c
; /* => %hi or %lo encountered */
7380 my_getExpression (ep
, str
)
7386 save_in
= input_line_pointer
;
7387 input_line_pointer
= str
;
7389 expr_end
= input_line_pointer
;
7390 input_line_pointer
= save_in
;
7393 /* Turn a string in input_line_pointer into a floating point constant
7394 of type type, and store the appropriate bytes in *litP. The number
7395 of LITTLENUMS emitted is stored in *sizeP . An error message is
7396 returned, or NULL on OK. */
7399 md_atof (type
, litP
, sizeP
)
7405 LITTLENUM_TYPE words
[4];
7421 return "bad call to md_atof";
7424 t
= atof_ieee (input_line_pointer
, type
, words
);
7426 input_line_pointer
= t
;
7430 if (byte_order
== LITTLE_ENDIAN
)
7432 for (i
= prec
- 1; i
>= 0; i
--)
7434 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7440 for (i
= 0; i
< prec
; i
++)
7442 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7451 md_number_to_chars (buf
, val
, n
)
7459 number_to_chars_littleendian (buf
, val
, n
);
7463 number_to_chars_bigendian (buf
, val
, n
);
7471 CONST
char *md_shortopts
= "O::g::G:";
7473 struct option md_longopts
[] = {
7474 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7475 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7476 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7477 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7478 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7479 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7480 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7481 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7482 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7483 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7484 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7485 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7486 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7487 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7488 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7489 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7490 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7491 {"break", no_argument
, NULL
, OPTION_BREAK
},
7492 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7493 #define OPTION_EB (OPTION_MD_BASE + 11)
7494 {"EB", no_argument
, NULL
, OPTION_EB
},
7495 #define OPTION_EL (OPTION_MD_BASE + 12)
7496 {"EL", no_argument
, NULL
, OPTION_EL
},
7497 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7498 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7499 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7500 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7501 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7502 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7503 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7504 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7505 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7506 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7507 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7508 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7509 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7510 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7511 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7512 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7514 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7515 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7516 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7517 #define OPTION_32 (OPTION_MD_BASE + 20)
7518 #define OPTION_64 (OPTION_MD_BASE + 21)
7520 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7521 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7522 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7523 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7524 {"32", no_argument
, NULL
, OPTION_32
},
7525 {"64", no_argument
, NULL
, OPTION_64
},
7528 {NULL
, no_argument
, NULL
, 0}
7530 size_t md_longopts_size
= sizeof(md_longopts
);
7533 md_parse_option (c
, arg
)
7548 target_big_endian
= 1;
7552 target_big_endian
= 0;
7556 if (arg
&& arg
[1] == '0')
7566 mips_debug
= atoi (arg
);
7567 /* When the MIPS assembler sees -g or -g2, it does not do
7568 optimizations which limit full symbolic debugging. We take
7569 that to be equivalent to -O0. */
7570 if (mips_debug
== 2)
7602 /* Identify the processor type */
7604 if (strcmp (p
, "default") == 0
7605 || strcmp (p
, "DEFAULT") == 0)
7611 /* We need to cope with the various "vr" prefixes for the 4300
7613 if (*p
== 'v' || *p
== 'V')
7619 if (*p
== 'r' || *p
== 'R')
7626 if (strcmp (p
, "10000") == 0
7627 || strcmp (p
, "10k") == 0
7628 || strcmp (p
, "10K") == 0)
7633 if (strcmp (p
, "2000") == 0
7634 || strcmp (p
, "2k") == 0
7635 || strcmp (p
, "2K") == 0)
7640 if (strcmp (p
, "3000") == 0
7641 || strcmp (p
, "3k") == 0
7642 || strcmp (p
, "3K") == 0)
7647 if (strcmp (p
, "4000") == 0
7648 || strcmp (p
, "4k") == 0
7649 || strcmp (p
, "4K") == 0)
7651 else if (strcmp (p
, "4100") == 0)
7657 else if (strcmp (p
, "4300") == 0)
7659 else if (strcmp (p
, "4400") == 0)
7661 else if (strcmp (p
, "4600") == 0)
7663 else if (strcmp (p
, "4650") == 0)
7669 else if (strcmp (p
, "4010") == 0)
7678 if (strcmp (p
, "5000") == 0
7679 || strcmp (p
, "5k") == 0
7680 || strcmp (p
, "5K") == 0)
7685 if (strcmp (p
, "6000") == 0
7686 || strcmp (p
, "6k") == 0
7687 || strcmp (p
, "6K") == 0)
7692 if (strcmp (p
, "8000") == 0
7693 || strcmp (p
, "8k") == 0
7694 || strcmp (p
, "8K") == 0)
7699 if (strcmp (p
, "orion") == 0)
7704 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
7706 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
7712 as_bad ("invalid architecture -mcpu=%s", arg
);
7723 case OPTION_NO_M4650
:
7731 case OPTION_NO_M4010
:
7739 case OPTION_NO_M4100
:
7745 mips_no_prev_insn ();
7748 case OPTION_NO_MIPS16
:
7750 mips_no_prev_insn ();
7753 case OPTION_MEMBEDDED_PIC
:
7754 mips_pic
= EMBEDDED_PIC
;
7755 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
7757 as_bad ("-G may not be used with embedded PIC code");
7760 g_switch_value
= 0x7fffffff;
7763 /* When generating ELF code, we permit -KPIC and -call_shared to
7764 select SVR4_PIC, and -non_shared to select no PIC. This is
7765 intended to be compatible with Irix 5. */
7766 case OPTION_CALL_SHARED
:
7767 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7769 as_bad ("-call_shared is supported only for ELF format");
7772 mips_pic
= SVR4_PIC
;
7773 if (g_switch_seen
&& g_switch_value
!= 0)
7775 as_bad ("-G may not be used with SVR4 PIC code");
7781 case OPTION_NON_SHARED
:
7782 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7784 as_bad ("-non_shared is supported only for ELF format");
7790 /* The -xgot option tells the assembler to use 32 offsets when
7791 accessing the got in SVR4_PIC mode. It is for Irix
7798 if (! USE_GLOBAL_POINTER_OPT
)
7800 as_bad ("-G is not supported for this configuration");
7803 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
7805 as_bad ("-G may not be used with SVR4 or embedded PIC code");
7809 g_switch_value
= atoi (arg
);
7813 /* The -32 and -64 options tell the assembler to output the 32
7814 bit or the 64 bit MIPS ELF format. */
7821 const char **list
, **l
;
7823 list
= bfd_target_list ();
7824 for (l
= list
; *l
!= NULL
; l
++)
7825 if (strcmp (*l
, "elf64-bigmips") == 0
7826 || strcmp (*l
, "elf64-littlemips") == 0)
7829 as_fatal ("No compiled in support for 64 bit object file format");
7843 md_show_usage (stream
)
7848 -membedded-pic generate embedded position independent code\n\
7849 -EB generate big endian output\n\
7850 -EL generate little endian output\n\
7851 -g, -g2 do not remove uneeded NOPs or swap branches\n\
7852 -G NUM allow referencing objects up to NUM bytes\n\
7853 implicitly with the gp register [default 8]\n");
7855 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
7856 -mips2, -mcpu=r6000 generate code for r6000\n\
7857 -mips3, -mcpu=r4000 generate code for r4000\n\
7858 -mips4, -mcpu=r8000 generate code for r8000\n\
7859 -mcpu=vr4300 generate code for vr4300\n\
7860 -mcpu=vr4100 generate code for vr4100\n\
7861 -m4650 permit R4650 instructions\n\
7862 -no-m4650 do not permit R4650 instructions\n\
7863 -m4010 permit R4010 instructions\n\
7864 -no-m4010 do not permit R4010 instructions\n\
7865 -m4100 permit VR4100 instructions\n\
7866 -no-m4100 do not permit VR4100 instructions\n");
7868 -mips16 generate mips16 instructions\n\
7869 -no-mips16 do not generate mips16 instructions\n");
7871 -O0 remove unneeded NOPs, do not swap branches\n\
7872 -O remove unneeded NOPs and swap branches\n\
7873 --trap, --no-break trap exception on div by 0 and mult overflow\n\
7874 --break, --no-trap break exception on div by 0 and mult overflow\n");
7877 -KPIC, -call_shared generate SVR4 position independent code\n\
7878 -non_shared do not generate position independent code\n\
7879 -xgot assume a 32 bit GOT\n\
7880 -32 create 32 bit object file (default)\n\
7881 -64 create 64 bit object file\n");
7886 mips_init_after_args ()
7888 if (target_big_endian
)
7889 byte_order
= BIG_ENDIAN
;
7891 byte_order
= LITTLE_ENDIAN
;
7895 md_pcrel_from (fixP
)
7898 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
7899 && fixP
->fx_addsy
!= (symbolS
*) NULL
7900 && ! S_IS_DEFINED (fixP
->fx_addsy
))
7902 /* This makes a branch to an undefined symbol be a branch to the
7903 current location. */
7907 /* return the address of the delay slot */
7908 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7911 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
7912 reloc for a cons. We could use the definition there, except that
7913 we want to handle 64 bit relocs specially. */
7916 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
7919 unsigned int nbytes
;
7923 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
7925 if (nbytes
== 8 && ! mips_64
)
7927 if (byte_order
== BIG_ENDIAN
)
7933 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
7934 as_bad ("Unsupported reloc size %d", nbytes
);
7936 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
7939 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
7942 /* Sort any unmatched HI16_S relocs so that they immediately precede
7943 the corresponding LO reloc. This is called before md_apply_fix and
7944 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
7945 explicit use of the %hi modifier. */
7950 struct mips_hi_fixup
*l
;
7952 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
7954 segment_info_type
*seginfo
;
7957 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
7959 /* Check quickly whether the next fixup happens to be a matching
7961 if (l
->fixp
->fx_next
!= NULL
7962 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
7963 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
7964 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
7967 /* Look through the fixups for this segment for a matching %lo.
7968 When we find one, move the %hi just in front of it. We do
7969 this in two passes. In the first pass, we try to find a
7970 unique %lo. In the second pass, we permit multiple %hi
7971 relocs for a single %lo (this is a GNU extension). */
7972 seginfo
= seg_info (l
->seg
);
7973 for (pass
= 0; pass
< 2; pass
++)
7978 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
7980 /* Check whether this is a %lo fixup which matches l->fixp. */
7981 if (f
->fx_r_type
== BFD_RELOC_LO16
7982 && f
->fx_addsy
== l
->fixp
->fx_addsy
7983 && f
->fx_offset
== l
->fixp
->fx_offset
7986 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
7987 || prev
->fx_addsy
!= f
->fx_addsy
7988 || prev
->fx_offset
!= f
->fx_offset
))
7992 /* Move l->fixp before f. */
7993 for (pf
= &seginfo
->fix_root
;
7995 pf
= &(*pf
)->fx_next
)
7996 assert (*pf
!= NULL
);
7998 *pf
= l
->fixp
->fx_next
;
8000 l
->fixp
->fx_next
= f
;
8002 seginfo
->fix_root
= l
->fixp
;
8004 prev
->fx_next
= l
->fixp
;
8016 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8017 "Unmatched %%hi reloc");
8022 /* When generating embedded PIC code we need to use a special
8023 relocation to represent the difference of two symbols in the .text
8024 section (switch tables use a difference of this sort). See
8025 include/coff/mips.h for details. This macro checks whether this
8026 fixup requires the special reloc. */
8027 #define SWITCH_TABLE(fixp) \
8028 ((fixp)->fx_r_type == BFD_RELOC_32 \
8029 && (fixp)->fx_addsy != NULL \
8030 && (fixp)->fx_subsy != NULL \
8031 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8032 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8034 /* When generating embedded PIC code we must keep all PC relative
8035 relocations, in case the linker has to relax a call. We also need
8036 to keep relocations for switch table entries. */
8040 mips_force_relocation (fixp
)
8043 return (mips_pic
== EMBEDDED_PIC
8045 || SWITCH_TABLE (fixp
)
8046 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8047 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8050 /* Apply a fixup to the object file. */
8053 md_apply_fix (fixP
, valueP
)
8060 assert (fixP
->fx_size
== 4
8061 || fixP
->fx_r_type
== BFD_RELOC_16
8062 || fixP
->fx_r_type
== BFD_RELOC_64
);
8065 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8067 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8070 switch (fixP
->fx_r_type
)
8072 case BFD_RELOC_MIPS_JMP
:
8073 case BFD_RELOC_HI16
:
8074 case BFD_RELOC_HI16_S
:
8075 case BFD_RELOC_MIPS_GPREL
:
8076 case BFD_RELOC_MIPS_LITERAL
:
8077 case BFD_RELOC_MIPS_CALL16
:
8078 case BFD_RELOC_MIPS_GOT16
:
8079 case BFD_RELOC_MIPS_GPREL32
:
8080 case BFD_RELOC_MIPS_GOT_HI16
:
8081 case BFD_RELOC_MIPS_GOT_LO16
:
8082 case BFD_RELOC_MIPS_CALL_HI16
:
8083 case BFD_RELOC_MIPS_CALL_LO16
:
8085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8086 "Invalid PC relative reloc");
8087 /* Nothing needed to do. The value comes from the reloc entry */
8090 case BFD_RELOC_MIPS16_JMP
:
8091 /* We currently always generate a reloc against a symbol, which
8092 means that we don't want an addend even if the symbol is
8094 fixP
->fx_addnumber
= 0;
8097 case BFD_RELOC_PCREL_HI16_S
:
8098 /* The addend for this is tricky if it is internal, so we just
8099 do everything here rather than in bfd_perform_relocation. */
8100 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8102 /* For an external symbol adjust by the address to make it
8103 pcrel_offset. We use the address of the RELLO reloc
8104 which follows this one. */
8105 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8106 + fixP
->fx_next
->fx_where
);
8111 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8112 if (byte_order
== BIG_ENDIAN
)
8114 md_number_to_chars (buf
, value
, 2);
8117 case BFD_RELOC_PCREL_LO16
:
8118 /* The addend for this is tricky if it is internal, so we just
8119 do everything here rather than in bfd_perform_relocation. */
8120 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8121 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8122 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8123 if (byte_order
== BIG_ENDIAN
)
8125 md_number_to_chars (buf
, value
, 2);
8129 /* This is handled like BFD_RELOC_32, but we output a sign
8130 extended value if we are only 32 bits. */
8132 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8134 if (8 <= sizeof (valueT
))
8135 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8142 w1
= w2
= fixP
->fx_where
;
8143 if (byte_order
== BIG_ENDIAN
)
8147 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8148 if ((value
& 0x80000000) != 0)
8152 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8158 /* If we are deleting this reloc entry, we must fill in the
8159 value now. This can happen if we have a .word which is not
8160 resolved when it appears but is later defined. We also need
8161 to fill in the value if this is an embedded PIC switch table
8164 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8165 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8170 /* If we are deleting this reloc entry, we must fill in the
8172 assert (fixP
->fx_size
== 2);
8174 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8178 case BFD_RELOC_LO16
:
8179 /* When handling an embedded PIC switch statement, we can wind
8180 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8183 if (value
< -0x8000 || value
> 0x7fff)
8184 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8185 "relocation overflow");
8186 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8187 if (byte_order
== BIG_ENDIAN
)
8189 md_number_to_chars (buf
, value
, 2);
8193 case BFD_RELOC_16_PCREL_S2
:
8195 * We need to save the bits in the instruction since fixup_segment()
8196 * might be deleting the relocation entry (i.e., a branch within
8197 * the current segment).
8199 /* TinyRISC can branch to odd addresses */
8200 if ((value
& (mips16
? 0x1 : 0x3)) != 0)
8201 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
8202 "Branch to odd address (%lx)", value
);
8205 /* update old instruction data */
8206 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8210 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8214 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8222 if (value
>= -0x8000 && value
< 0x8000)
8223 insn
|= value
& 0xffff;
8226 /* The branch offset is too large. If this is an
8227 unconditional branch, and we are not generating PIC code,
8228 we can convert it to an absolute jump instruction. */
8229 if (mips_pic
== NO_PIC
8231 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8232 && (fixP
->fx_frag
->fr_address
8233 < text_section
->vma
+ text_section
->_raw_size
)
8234 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8235 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8236 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8238 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8239 insn
= 0x0c000000; /* jal */
8241 insn
= 0x08000000; /* j */
8242 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8244 fixP
->fx_addsy
= section_symbol (text_section
);
8245 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8249 /* FIXME. It would be possible in principle to handle
8250 conditional branches which overflow. They could be
8251 transformed into a branch around a jump. This would
8252 require setting up variant frags for each different
8253 branch type. The native MIPS assembler attempts to
8254 handle these cases, but it appears to do it
8256 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8257 "Relocation overflow");
8261 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8276 const struct mips_opcode
*p
;
8277 int treg
, sreg
, dreg
, shamt
;
8282 for (i
= 0; i
< NUMOPCODES
; ++i
)
8284 p
= &mips_opcodes
[i
];
8285 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8287 printf ("%08lx %s\t", oc
, p
->name
);
8288 treg
= (oc
>> 16) & 0x1f;
8289 sreg
= (oc
>> 21) & 0x1f;
8290 dreg
= (oc
>> 11) & 0x1f;
8291 shamt
= (oc
>> 6) & 0x1f;
8293 for (args
= p
->args
;; ++args
)
8304 printf ("%c", *args
);
8308 assert (treg
== sreg
);
8309 printf ("$%d,$%d", treg
, sreg
);
8314 printf ("$%d", dreg
);
8319 printf ("$%d", treg
);
8323 printf ("0x%x", treg
);
8328 printf ("$%d", sreg
);
8332 printf ("0x%08lx", oc
& 0x1ffffff);
8344 printf ("$%d", shamt
);
8355 printf ("%08lx UNDEFINED\n", oc
);
8366 name
= input_line_pointer
;
8367 c
= get_symbol_end ();
8368 p
= (symbolS
*) symbol_find_or_make (name
);
8369 *input_line_pointer
= c
;
8373 /* Align the current frag to a given power of two. The MIPS assembler
8374 also automatically adjusts any preceding label. */
8377 mips_align (to
, fill
, label
)
8382 mips_emit_delays ();
8383 frag_align (to
, fill
);
8384 record_alignment (now_seg
, to
);
8387 assert (S_GET_SEGMENT (label
) == now_seg
);
8388 label
->sy_frag
= frag_now
;
8389 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8393 /* Align to a given power of two. .align 0 turns off the automatic
8394 alignment used by the data creating pseudo-ops. */
8401 register long temp_fill
;
8402 long max_alignment
= 15;
8406 o Note that the assembler pulls down any immediately preceeding label
8407 to the aligned address.
8408 o It's not documented but auto alignment is reinstated by
8409 a .align pseudo instruction.
8410 o Note also that after auto alignment is turned off the mips assembler
8411 issues an error on attempt to assemble an improperly aligned data item.
8416 temp
= get_absolute_expression ();
8417 if (temp
> max_alignment
)
8418 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8421 as_warn ("Alignment negative: 0 assumed.");
8424 if (*input_line_pointer
== ',')
8426 input_line_pointer
++;
8427 temp_fill
= get_absolute_expression ();
8434 mips_align (temp
, (int) temp_fill
, insn_label
);
8441 demand_empty_rest_of_line ();
8445 mips_flush_pending_output ()
8447 mips_emit_delays ();
8457 /* When generating embedded PIC code, we only use the .text, .lit8,
8458 .sdata and .sbss sections. We change the .data and .rdata
8459 pseudo-ops to use .sdata. */
8460 if (mips_pic
== EMBEDDED_PIC
8461 && (sec
== 'd' || sec
== 'r'))
8464 mips_emit_delays ();
8474 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8475 demand_empty_rest_of_line ();
8479 if (USE_GLOBAL_POINTER_OPT
)
8481 seg
= subseg_new (RDATA_SECTION_NAME
,
8482 (subsegT
) get_absolute_expression ());
8483 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8485 bfd_set_section_flags (stdoutput
, seg
,
8491 if (strcmp (TARGET_OS
, "elf") != 0)
8492 bfd_set_section_alignment (stdoutput
, seg
, 4);
8494 demand_empty_rest_of_line ();
8498 as_bad ("No read only data section in this object file format");
8499 demand_empty_rest_of_line ();
8505 if (USE_GLOBAL_POINTER_OPT
)
8507 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8508 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8510 bfd_set_section_flags (stdoutput
, seg
,
8511 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8513 if (strcmp (TARGET_OS
, "elf") != 0)
8514 bfd_set_section_alignment (stdoutput
, seg
, 4);
8516 demand_empty_rest_of_line ();
8521 as_bad ("Global pointers not supported; recompile -G 0");
8522 demand_empty_rest_of_line ();
8531 mips_enable_auto_align ()
8543 mips_emit_delays ();
8544 if (log_size
> 0 && auto_align
)
8545 mips_align (log_size
, 0, label
);
8547 cons (1 << log_size
);
8558 mips_emit_delays ();
8562 mips_align (3, 0, label
);
8564 mips_align (2, 0, label
);
8571 /* Handle .globl. We need to override it because on Irix 5 you are
8574 where foo is an undefined symbol, to mean that foo should be
8575 considered to be the address of a function. */
8586 name
= input_line_pointer
;
8587 c
= get_symbol_end ();
8588 symbolP
= symbol_find_or_make (name
);
8589 *input_line_pointer
= c
;
8592 /* On Irix 5, every global symbol that is not explicitly labelled as
8593 being a function is apparently labelled as being an object. */
8596 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8601 secname
= input_line_pointer
;
8602 c
= get_symbol_end ();
8603 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8605 as_bad ("%s: no such section", secname
);
8606 *input_line_pointer
= c
;
8608 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8609 flag
= BSF_FUNCTION
;
8612 symbolP
->bsym
->flags
|= flag
;
8614 S_SET_EXTERNAL (symbolP
);
8615 demand_empty_rest_of_line ();
8625 opt
= input_line_pointer
;
8626 c
= get_symbol_end ();
8630 /* FIXME: What does this mean? */
8632 else if (strncmp (opt
, "pic", 3) == 0)
8640 mips_pic
= SVR4_PIC
;
8642 as_bad (".option pic%d not supported", i
);
8644 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8646 if (g_switch_seen
&& g_switch_value
!= 0)
8647 as_warn ("-G may not be used with SVR4 PIC code");
8649 bfd_set_gp_size (stdoutput
, 0);
8653 as_warn ("Unrecognized option \"%s\"", opt
);
8655 *input_line_pointer
= c
;
8656 demand_empty_rest_of_line ();
8663 char *name
= input_line_pointer
, ch
;
8665 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8666 input_line_pointer
++;
8667 ch
= *input_line_pointer
;
8668 *input_line_pointer
= '\0';
8670 if (strcmp (name
, "reorder") == 0)
8674 prev_insn_unreordered
= 1;
8675 prev_prev_insn_unreordered
= 1;
8679 else if (strcmp (name
, "noreorder") == 0)
8681 mips_emit_delays ();
8683 mips_any_noreorder
= 1;
8685 else if (strcmp (name
, "at") == 0)
8689 else if (strcmp (name
, "noat") == 0)
8693 else if (strcmp (name
, "macro") == 0)
8695 mips_warn_about_macros
= 0;
8697 else if (strcmp (name
, "nomacro") == 0)
8699 if (mips_noreorder
== 0)
8700 as_bad ("`noreorder' must be set before `nomacro'");
8701 mips_warn_about_macros
= 1;
8703 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
8707 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
8711 else if (strcmp (name
, "bopt") == 0)
8715 else if (strcmp (name
, "nobopt") == 0)
8719 else if (strcmp (name
, "mips16") == 0
8720 || strcmp (name
, "MIPS-16") == 0)
8722 else if (strcmp (name
, "nomips16") == 0
8723 || strcmp (name
, "noMIPS-16") == 0)
8725 else if (strncmp (name
, "mips", 4) == 0)
8729 /* Permit the user to change the ISA on the fly. Needless to
8730 say, misuse can cause serious problems. */
8731 isa
= atoi (name
+ 4);
8733 mips_isa
= file_mips_isa
;
8734 else if (isa
< 1 || isa
> 4)
8735 as_bad ("unknown ISA level");
8739 else if (strcmp (name
, "autoextend") == 0)
8740 mips16_autoextend
= 1;
8741 else if (strcmp (name
, "noautoextend") == 0)
8742 mips16_autoextend
= 0;
8745 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
8747 *input_line_pointer
= ch
;
8748 demand_empty_rest_of_line ();
8751 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
8752 .option pic2. It means to generate SVR4 PIC calls. */
8758 mips_pic
= SVR4_PIC
;
8759 if (USE_GLOBAL_POINTER_OPT
)
8761 if (g_switch_seen
&& g_switch_value
!= 0)
8762 as_warn ("-G may not be used with SVR4 PIC code");
8765 bfd_set_gp_size (stdoutput
, 0);
8766 demand_empty_rest_of_line ();
8769 /* Handle the .cpload pseudo-op. This is used when generating SVR4
8770 PIC code. It sets the $gp register for the function based on the
8771 function address, which is in the register named in the argument.
8772 This uses a relocation against _gp_disp, which is handled specially
8773 by the linker. The result is:
8774 lui $gp,%hi(_gp_disp)
8775 addiu $gp,$gp,%lo(_gp_disp)
8776 addu $gp,$gp,.cpload argument
8777 The .cpload argument is normally $25 == $t9. */
8786 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
8787 if (mips_pic
!= SVR4_PIC
)
8793 /* .cpload should be a in .set noreorder section. */
8794 if (mips_noreorder
== 0)
8795 as_warn (".cpload not in noreorder section");
8798 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
8799 ex
.X_op_symbol
= NULL
;
8800 ex
.X_add_number
= 0;
8802 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
8803 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
8805 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
8806 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
8807 (int) BFD_RELOC_LO16
);
8809 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
8810 GP
, GP
, tc_get_register (0));
8812 demand_empty_rest_of_line ();
8815 /* Handle the .cprestore pseudo-op. This stores $gp into a given
8816 offset from $sp. The offset is remembered, and after making a PIC
8817 call $gp is restored from that location. */
8820 s_cprestore (ignore
)
8826 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
8827 if (mips_pic
!= SVR4_PIC
)
8833 mips_cprestore_offset
= get_absolute_expression ();
8835 ex
.X_op
= O_constant
;
8836 ex
.X_add_symbol
= NULL
;
8837 ex
.X_op_symbol
= NULL
;
8838 ex
.X_add_number
= mips_cprestore_offset
;
8840 macro_build ((char *) NULL
, &icnt
, &ex
,
8841 mips_isa
< 3 ? "sw" : "sd",
8842 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
8844 demand_empty_rest_of_line ();
8847 /* Handle the .gpword pseudo-op. This is used when generating PIC
8848 code. It generates a 32 bit GP relative reloc. */
8858 /* When not generating PIC code, this is treated as .word. */
8859 if (mips_pic
!= SVR4_PIC
)
8866 mips_emit_delays ();
8868 mips_align (2, 0, label
);
8873 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
8875 as_bad ("Unsupported use of .gpword");
8876 ignore_rest_of_line ();
8880 md_number_to_chars (p
, (valueT
) 0, 4);
8881 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
8882 BFD_RELOC_MIPS_GPREL32
);
8884 demand_empty_rest_of_line ();
8887 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
8888 tables in SVR4 PIC code. */
8897 /* This is ignored when not generating SVR4 PIC code. */
8898 if (mips_pic
!= SVR4_PIC
)
8904 /* Add $gp to the register named as an argument. */
8905 reg
= tc_get_register (0);
8906 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8907 mips_isa
< 3 ? "addu" : "daddu",
8908 "d,v,t", reg
, reg
, GP
);
8910 demand_empty_rest_of_line ();
8913 /* Parse a register string into a number. Called from the ECOFF code
8914 to parse .frame. The argument is non-zero if this is the frame
8915 register, so that we can record it in mips_frame_reg. */
8918 tc_get_register (frame
)
8924 if (*input_line_pointer
++ != '$')
8926 as_warn ("expected `$'");
8929 else if (isdigit ((unsigned char) *input_line_pointer
))
8931 reg
= get_absolute_expression ();
8932 if (reg
< 0 || reg
>= 32)
8934 as_warn ("Bad register number");
8940 if (strncmp (input_line_pointer
, "fp", 2) == 0)
8942 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
8944 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
8946 else if (strncmp (input_line_pointer
, "at", 2) == 0)
8950 as_warn ("Unrecognized register name");
8953 input_line_pointer
+= 2;
8956 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
8961 md_section_align (seg
, addr
)
8965 int align
= bfd_get_section_alignment (stdoutput
, seg
);
8968 /* We don't need to align ELF sections to the full alignment.
8969 However, Irix 5 may prefer that we align them at least to a 16
8970 byte boundary. We don't bother to align the sections if we are
8971 targeted for an embedded system. */
8972 if (strcmp (TARGET_OS
, "elf") == 0)
8978 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
8981 /* Utility routine, called from above as well. If called while the
8982 input file is still being read, it's only an approximation. (For
8983 example, a symbol may later become defined which appeared to be
8984 undefined earlier.) */
8987 nopic_need_relax (sym
)
8993 if (USE_GLOBAL_POINTER_OPT
)
8995 const char *symname
;
8998 /* Find out whether this symbol can be referenced off the GP
8999 register. It can be if it is smaller than the -G size or if
9000 it is in the .sdata or .sbss section. Certain symbols can
9001 not be referenced off the GP, although it appears as though
9003 symname
= S_GET_NAME (sym
);
9004 if (symname
!= (const char *) NULL
9005 && (strcmp (symname
, "eprol") == 0
9006 || strcmp (symname
, "etext") == 0
9007 || strcmp (symname
, "_gp") == 0
9008 || strcmp (symname
, "edata") == 0
9009 || strcmp (symname
, "_fbss") == 0
9010 || strcmp (symname
, "_fdata") == 0
9011 || strcmp (symname
, "_ftext") == 0
9012 || strcmp (symname
, "end") == 0
9013 || strcmp (symname
, "_gp_disp") == 0))
9015 else if (! S_IS_DEFINED (sym
)
9017 #ifndef NO_ECOFF_DEBUGGING
9018 || (sym
->ecoff_extern_size
!= 0
9019 && sym
->ecoff_extern_size
<= g_switch_value
)
9021 || (S_GET_VALUE (sym
) != 0
9022 && S_GET_VALUE (sym
) <= g_switch_value
)))
9026 const char *segname
;
9028 segname
= segment_name (S_GET_SEGMENT (sym
));
9029 assert (strcmp (segname
, ".lit8") != 0
9030 && strcmp (segname
, ".lit4") != 0);
9031 change
= (strcmp (segname
, ".sdata") != 0
9032 && strcmp (segname
, ".sbss") != 0);
9037 /* We are not optimizing for the GP register. */
9041 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9042 extended opcode. SEC is the section the frag is in. */
9045 mips16_extended_frag (fragp
, sec
, stretch
)
9051 register const struct mips16_immed_operand
*op
;
9053 int mintiny
, maxtiny
;
9056 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9058 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9061 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9062 op
= mips16_immed_operands
;
9063 while (op
->type
!= type
)
9066 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9071 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9074 maxtiny
= 1 << op
->nbits
;
9079 maxtiny
= (1 << op
->nbits
) - 1;
9084 mintiny
= - (1 << (op
->nbits
- 1));
9085 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9088 /* We can't call S_GET_VALUE here, because we don't want to lock in
9089 a particular frag address. */
9090 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9092 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9093 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9094 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9096 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9097 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9100 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9101 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9102 + fragp
->fr_symbol
->sy_value
.X_add_number
9103 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9104 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9113 /* We won't have the section when we are called from
9114 mips_relax_frag. However, we will always have been called
9115 from md_estimate_size_before_relax first. If this is a
9116 branch to a different section, we mark it as such. If SEC is
9117 NULL, and the frag is not marked, then it must be a branch to
9118 the same section. */
9121 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9129 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9131 /* FIXME: We should support this, and let the linker
9132 catch branches and loads that are out of range. */
9133 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9134 "unsupported PC relative reference to different section");
9140 /* In this case, we know for sure that the symbol fragment is in
9141 the same section. If the fr_address of the symbol fragment
9142 is greater then the address of this fragment we want to add
9143 in STRETCH in order to get a better estimate of the address.
9144 This particularly matters because of the shift bits. */
9146 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9150 /* Adjust stretch for any alignment frag. */
9151 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9154 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9157 stretch
= - ((- stretch
)
9158 & ~ ((1 << (int) f
->fr_offset
) - 1));
9160 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9168 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
9170 /* If we are currently assuming that this frag should be
9171 extended, then the current address is two bytes higher. */
9172 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9175 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9177 /* Branch offsets have an implicit 0 in the lowest bit. */
9178 if (type
== 'p' || type
== 'q')
9181 /* If any of the shifted bits are set, we must use an extended
9182 opcode. If the address depends on the size of this
9183 instruction, this can lead to a loop, so we arrange to always
9184 use an extended opcode. We only check this when we are in
9185 the main relaxation loop, when SEC is NULL. */
9186 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9189 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9193 /* If we are about to mark a frag as extended because the value
9194 is precisely maxtiny + 1, then there is a chance of an
9195 infinite loop as in the following code:
9200 In this case when the la is extended, foo is 0x3fc bytes
9201 away, so the la can be shrunk, but then foo is 0x400 away, so
9202 the la must be extended. To avoid this loop, we mark the
9203 frag as extended if it was small, and is about to become
9204 extended with a value of maxtiny + 1. */
9205 if (val
== ((maxtiny
+ 1) << op
->shift
)
9206 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9210 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9214 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9215 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9217 if ((val
& ((1 << op
->shift
) - 1)) != 0
9218 || val
< (mintiny
<< op
->shift
)
9219 || val
> (maxtiny
<< op
->shift
))
9225 /* Estimate the size of a frag before relaxing. Unless this is the
9226 mips16, we are not really relaxing here, and the final size is
9227 encoded in the subtype information. For the mips16, we have to
9228 decide whether we are using an extended opcode or not. */
9232 md_estimate_size_before_relax (fragp
, segtype
)
9238 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9240 if (mips16_extended_frag (fragp
, segtype
, 0))
9242 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9247 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9252 if (mips_pic
== NO_PIC
)
9254 change
= nopic_need_relax (fragp
->fr_symbol
);
9256 else if (mips_pic
== SVR4_PIC
)
9258 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9260 /* This must duplicate the test in adjust_reloc_syms. */
9261 change
= (symsec
!= &bfd_und_section
9262 && symsec
!= &bfd_abs_section
9263 && ! bfd_is_com_section (symsec
));
9270 /* Record the offset to the first reloc in the fr_opcode field.
9271 This lets md_convert_frag and tc_gen_reloc know that the code
9272 must be expanded. */
9273 fragp
->fr_opcode
= (fragp
->fr_literal
9275 - RELAX_OLD (fragp
->fr_subtype
)
9276 + RELAX_RELOC1 (fragp
->fr_subtype
));
9277 /* FIXME: This really needs as_warn_where. */
9278 if (RELAX_WARN (fragp
->fr_subtype
))
9279 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9285 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9288 /* Translate internal representation of relocation info to BFD target
9292 tc_gen_reloc (section
, fixp
)
9296 static arelent
*retval
[4];
9298 bfd_reloc_code_real_type code
;
9300 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9303 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9304 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9306 if (mips_pic
== EMBEDDED_PIC
9307 && SWITCH_TABLE (fixp
))
9309 /* For a switch table entry we use a special reloc. The addend
9310 is actually the difference between the reloc address and the
9312 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9313 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9314 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9315 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9317 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9319 /* We use a special addend for an internal RELLO reloc. */
9320 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9321 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9323 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9325 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9327 assert (fixp
->fx_next
!= NULL
9328 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9329 /* We use a special addend for an internal RELHI reloc. The
9330 reloc is relative to the RELLO; adjust the addend
9332 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9333 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9334 + fixp
->fx_next
->fx_where
9335 - S_GET_VALUE (fixp
->fx_subsy
));
9337 reloc
->addend
= (fixp
->fx_addnumber
9338 + fixp
->fx_next
->fx_frag
->fr_address
9339 + fixp
->fx_next
->fx_where
);
9341 else if (fixp
->fx_pcrel
== 0)
9342 reloc
->addend
= fixp
->fx_addnumber
;
9345 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9346 /* A gruesome hack which is a result of the gruesome gas reloc
9348 reloc
->addend
= reloc
->address
;
9350 reloc
->addend
= -reloc
->address
;
9353 /* If this is a variant frag, we may need to adjust the existing
9354 reloc and generate a new one. */
9355 if (fixp
->fx_frag
->fr_opcode
!= NULL
9356 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9357 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9358 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9359 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9360 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9361 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9362 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9366 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9368 /* If this is not the last reloc in this frag, then we have two
9369 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9370 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9371 the second one handle all of them. */
9372 if (fixp
->fx_next
!= NULL
9373 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9375 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9376 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9377 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9378 && (fixp
->fx_next
->fx_r_type
9379 == BFD_RELOC_MIPS_GOT_LO16
))
9380 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9381 && (fixp
->fx_next
->fx_r_type
9382 == BFD_RELOC_MIPS_CALL_LO16
)));
9387 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9388 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9389 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9391 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9392 reloc2
->address
= (reloc
->address
9393 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9394 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9395 reloc2
->addend
= fixp
->fx_addnumber
;
9396 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9397 assert (reloc2
->howto
!= NULL
);
9399 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9403 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9406 reloc3
->address
+= 4;
9409 if (mips_pic
== NO_PIC
)
9411 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9412 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9414 else if (mips_pic
== SVR4_PIC
)
9416 switch (fixp
->fx_r_type
)
9420 case BFD_RELOC_MIPS_GOT16
:
9422 case BFD_RELOC_MIPS_CALL16
:
9423 case BFD_RELOC_MIPS_GOT_LO16
:
9424 case BFD_RELOC_MIPS_CALL_LO16
:
9425 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9433 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9434 fixup_segment converted a non-PC relative reloc into a PC
9435 relative reloc. In such a case, we need to convert the reloc
9437 code
= fixp
->fx_r_type
;
9443 code
= BFD_RELOC_8_PCREL
;
9446 code
= BFD_RELOC_16_PCREL
;
9449 code
= BFD_RELOC_32_PCREL
;
9452 code
= BFD_RELOC_64_PCREL
;
9454 case BFD_RELOC_8_PCREL
:
9455 case BFD_RELOC_16_PCREL
:
9456 case BFD_RELOC_32_PCREL
:
9457 case BFD_RELOC_64_PCREL
:
9458 case BFD_RELOC_16_PCREL_S2
:
9459 case BFD_RELOC_PCREL_HI16_S
:
9460 case BFD_RELOC_PCREL_LO16
:
9463 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9464 "Cannot make %s relocation PC relative",
9465 bfd_get_reloc_code_name (code
));
9469 /* To support a PC relative reloc when generating embedded PIC code
9470 for ECOFF, we use a Cygnus extension. We check for that here to
9471 make sure that we don't let such a reloc escape normally. */
9472 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9473 && code
== BFD_RELOC_16_PCREL_S2
9474 && mips_pic
!= EMBEDDED_PIC
)
9475 reloc
->howto
= NULL
;
9477 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9479 if (reloc
->howto
== NULL
)
9481 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9482 "Can not represent %s relocation in this object file format",
9483 bfd_get_reloc_code_name (code
));
9490 /* Relax a machine dependent frag. This returns the amount by which
9491 the current size of the frag should change. */
9494 mips_relax_frag (fragp
, stretch
)
9498 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9501 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9503 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9505 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9510 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9512 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9519 /* Convert a machine dependent frag. */
9522 md_convert_frag (abfd
, asec
, fragp
)
9530 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9533 register const struct mips16_immed_operand
*op
;
9539 unsigned short extend
;
9541 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9542 op
= mips16_immed_operands
;
9543 while (op
->type
!= type
)
9546 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9557 resolve_symbol_value (fragp
->fr_symbol
);
9558 val
= S_GET_VALUE (fragp
->fr_symbol
);
9563 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
9566 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9570 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9577 insn
= bfd_getl16 (buf
);
9580 insn
= bfd_getb16 (buf
);
9584 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
, false, small
,
9585 ext
, &insn
, &use_extend
, &extend
);
9589 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9594 md_number_to_chars (buf
, insn
, 2);
9600 if (fragp
->fr_opcode
== NULL
)
9603 old
= RELAX_OLD (fragp
->fr_subtype
);
9604 new = RELAX_NEW (fragp
->fr_subtype
);
9605 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9608 memcpy (fixptr
- old
, fixptr
, new);
9610 fragp
->fr_fix
+= new - old
;
9614 /* This function is called whenever a label is defined. It is used
9615 when handling branch delays; if a branch has a label, we assume we
9619 mips_define_label (sym
)
9625 S_SET_OTHER (insn_label
, STO_MIPS16
);
9629 /* Decide whether a label is local. This is called by LOCAL_LABEL.
9630 In order to work with gcc when using mips-tfile, we must keep all
9631 local labels. However, in other cases, we want to discard them,
9632 since they are useless. */
9635 mips_local_label (name
)
9638 #ifndef NO_ECOFF_DEBUGGING
9641 && ! ecoff_debugging_seen
)
9643 /* We were called with -g, but we didn't see any debugging
9644 information. That may mean that gcc is smuggling debugging
9645 information through to mips-tfile, in which case we must
9646 generate all local labels. */
9651 /* Here it's OK to discard local labels. */
9653 return name
[0] == '$';
9656 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9658 /* Some special processing for a MIPS ELF file. */
9661 mips_elf_final_processing ()
9663 /* Write out the register information. */
9668 s
.ri_gprmask
= mips_gprmask
;
9669 s
.ri_cprmask
[0] = mips_cprmask
[0];
9670 s
.ri_cprmask
[1] = mips_cprmask
[1];
9671 s
.ri_cprmask
[2] = mips_cprmask
[2];
9672 s
.ri_cprmask
[3] = mips_cprmask
[3];
9673 /* The gp_value field is set by the MIPS ELF backend. */
9675 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
9676 ((Elf32_External_RegInfo
*)
9677 mips_regmask_frag
));
9681 Elf64_Internal_RegInfo s
;
9683 s
.ri_gprmask
= mips_gprmask
;
9685 s
.ri_cprmask
[0] = mips_cprmask
[0];
9686 s
.ri_cprmask
[1] = mips_cprmask
[1];
9687 s
.ri_cprmask
[2] = mips_cprmask
[2];
9688 s
.ri_cprmask
[3] = mips_cprmask
[3];
9689 /* The gp_value field is set by the MIPS ELF backend. */
9691 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
9692 ((Elf64_External_RegInfo
*)
9693 mips_regmask_frag
));
9696 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
9697 sort of BFD interface for this. */
9698 if (mips_any_noreorder
)
9699 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
9700 if (mips_pic
!= NO_PIC
)
9701 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
9704 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
9706 /* These functions should really be defined by the object file format,
9707 since they are related to debugging information. However, this
9708 code has to work for the a.out format, which does not define them,
9709 so we provide simple versions here. These don't actually generate
9710 any debugging information, but they do simple checking and someday
9711 somebody may make them useful. */
9715 struct loc
*loc_next
;
9716 unsigned long loc_fileno
;
9717 unsigned long loc_lineno
;
9718 unsigned long loc_offset
;
9719 unsigned short loc_delta
;
9720 unsigned short loc_count
;
9729 struct proc
*proc_next
;
9730 struct symbol
*proc_isym
;
9731 struct symbol
*proc_end
;
9732 unsigned long proc_reg_mask
;
9733 unsigned long proc_reg_offset
;
9734 unsigned long proc_fpreg_mask
;
9735 unsigned long proc_fpreg_offset
;
9736 unsigned long proc_frameoffset
;
9737 unsigned long proc_framereg
;
9738 unsigned long proc_pcreg
;
9740 struct file
*proc_file
;
9747 struct file
*file_next
;
9748 unsigned long file_fileno
;
9749 struct symbol
*file_symbol
;
9750 struct symbol
*file_end
;
9751 struct proc
*file_proc
;
9756 static struct obstack proc_frags
;
9757 static procS
*proc_lastP
;
9758 static procS
*proc_rootP
;
9759 static int numprocs
;
9764 obstack_begin (&proc_frags
, 0x2000);
9770 /* check for premature end, nesting errors, etc */
9771 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9772 as_warn ("missing `.end' at end of assembly");
9781 if (*input_line_pointer
== '-')
9783 ++input_line_pointer
;
9786 if (!isdigit (*input_line_pointer
))
9787 as_bad ("Expected simple number.");
9788 if (input_line_pointer
[0] == '0')
9790 if (input_line_pointer
[1] == 'x')
9792 input_line_pointer
+= 2;
9793 while (isxdigit (*input_line_pointer
))
9796 val
|= hex_value (*input_line_pointer
++);
9798 return negative
? -val
: val
;
9802 ++input_line_pointer
;
9803 while (isdigit (*input_line_pointer
))
9806 val
|= *input_line_pointer
++ - '0';
9808 return negative
? -val
: val
;
9811 if (!isdigit (*input_line_pointer
))
9813 printf (" *input_line_pointer == '%c' 0x%02x\n",
9814 *input_line_pointer
, *input_line_pointer
);
9815 as_warn ("Invalid number");
9818 while (isdigit (*input_line_pointer
))
9821 val
+= *input_line_pointer
++ - '0';
9823 return negative
? -val
: val
;
9826 /* The .file directive; just like the usual .file directive, but there
9827 is an initial number which is the ECOFF file index. */
9835 line
= get_number ();
9840 /* The .end directive. */
9848 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9851 demand_empty_rest_of_line ();
9855 if (now_seg
!= text_section
)
9856 as_warn (".end not in text section");
9859 as_warn (".end and no .ent seen yet.");
9865 assert (S_GET_NAME (p
));
9866 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
9867 as_warn (".end symbol does not match .ent symbol.");
9870 proc_lastP
->proc_end
= (symbolS
*) 1;
9873 /* The .aent and .ent directives. */
9883 symbolP
= get_symbol ();
9884 if (*input_line_pointer
== ',')
9885 input_line_pointer
++;
9887 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
9888 number
= get_number ();
9889 if (now_seg
!= text_section
)
9890 as_warn (".ent or .aent not in text section.");
9892 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9893 as_warn ("missing `.end'");
9897 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
9898 procP
->proc_isym
= symbolP
;
9899 procP
->proc_reg_mask
= 0;
9900 procP
->proc_reg_offset
= 0;
9901 procP
->proc_fpreg_mask
= 0;
9902 procP
->proc_fpreg_offset
= 0;
9903 procP
->proc_frameoffset
= 0;
9904 procP
->proc_framereg
= 0;
9905 procP
->proc_pcreg
= 0;
9906 procP
->proc_end
= NULL
;
9907 procP
->proc_next
= NULL
;
9909 proc_lastP
->proc_next
= procP
;
9915 demand_empty_rest_of_line ();
9918 /* The .frame directive. */
9931 frame_reg
= tc_get_register (1);
9932 if (*input_line_pointer
== ',')
9933 input_line_pointer
++;
9934 frame_off
= get_absolute_expression ();
9935 if (*input_line_pointer
== ',')
9936 input_line_pointer
++;
9937 pcreg
= tc_get_register (0);
9940 assert (proc_rootP
);
9941 proc_rootP
->proc_framereg
= frame_reg
;
9942 proc_rootP
->proc_frameoffset
= frame_off
;
9943 proc_rootP
->proc_pcreg
= pcreg
;
9944 /* bob macho .frame */
9946 /* We don't have to write out a frame stab for unoptimized code. */
9947 if (!(frame_reg
== FP
&& frame_off
== 0))
9950 as_warn ("No .ent for .frame to use.");
9951 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
9952 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
9953 S_SET_TYPE (symP
, N_RMASK
);
9954 S_SET_OTHER (symP
, 0);
9955 S_SET_DESC (symP
, 0);
9956 symP
->sy_forward
= proc_lastP
->proc_isym
;
9957 /* bob perhaps I should have used pseudo set */
9959 demand_empty_rest_of_line ();
9963 /* The .fmask and .mask directives. */
9970 char str
[100], *strP
;
9976 mask
= get_number ();
9977 if (*input_line_pointer
== ',')
9978 input_line_pointer
++;
9979 off
= get_absolute_expression ();
9981 /* bob only for coff */
9982 assert (proc_rootP
);
9983 if (reg_type
== 'F')
9985 proc_rootP
->proc_fpreg_mask
= mask
;
9986 proc_rootP
->proc_fpreg_offset
= off
;
9990 proc_rootP
->proc_reg_mask
= mask
;
9991 proc_rootP
->proc_reg_offset
= off
;
9994 /* bob macho .mask + .fmask */
9996 /* We don't have to write out a mask stab if no saved regs. */
10000 as_warn ("No .ent for .mask to use.");
10002 for (i
= 0; i
< 32; i
++)
10006 sprintf (strP
, "%c%d,", reg_type
, i
);
10007 strP
+= strlen (strP
);
10011 sprintf (strP
, ";%d,", off
);
10012 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10013 S_SET_TYPE (symP
, N_RMASK
);
10014 S_SET_OTHER (symP
, 0);
10015 S_SET_DESC (symP
, 0);
10016 symP
->sy_forward
= proc_lastP
->proc_isym
;
10017 /* bob perhaps I should have used pseudo set */
10022 /* The .loc directive. */
10033 assert (now_seg
== text_section
);
10035 lineno
= get_number ();
10036 addroff
= frag_now_fix ();
10038 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10039 S_SET_TYPE (symbolP
, N_SLINE
);
10040 S_SET_OTHER (symbolP
, 0);
10041 S_SET_DESC (symbolP
, lineno
);
10042 symbolP
->sy_segment
= now_seg
;