1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* The default target format to use. */
70 #ifdef TARGET_BYTES_BIG_ENDIAN
71 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
73 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
77 #ifdef TARGET_BYTES_BIG_ENDIAN
78 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
80 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
82 #endif /* OBJ_ECOFF */
84 #ifdef TARGET_BYTES_BIG_ENDIAN
85 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
87 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
91 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
93 /* These variables are filled in with the masks of registers used.
94 The object format code reads them and puts them in the appropriate
96 unsigned long mips_gprmask
;
97 unsigned long mips_cprmask
[4];
99 /* MIPS ISA (Instruction Set Architecture) level. */
100 static int mips_isa
= -1;
102 /* MIPS PIC level. 0 is normal, non-PIC code. 2 means to generate
103 SVR4 ABI PIC calls. 1 doesn't mean anything. */
106 static int mips_warn_about_macros
;
107 static int mips_noreorder
;
108 static int mips_any_noreorder
;
109 static int mips_nomove
;
110 static int mips_noat
;
111 static int mips_nobopt
;
114 /* The size of the small data section. */
115 static int g_switch_value
= 8;
121 /* handle of the OPCODE hash table */
122 static struct hash_control
*op_hash
= NULL
;
124 /* This array holds the chars that always start a comment. If the
125 pre-processor is disabled, these aren't very useful */
126 const char comment_chars
[] = "#";
128 /* This array holds the chars that only start a comment at the beginning of
129 a line. If the line seems to have the form '# 123 filename'
130 .line and .file directives will appear in the pre-processed output */
131 /* Note that input_file.c hand checks for '#' at the beginning of the
132 first line of the input file. This is because the compiler outputs
133 #NO_APP at the beginning of its output. */
134 /* Also note that C style comments are always supported. */
135 const char line_comment_chars
[] = "#";
137 /* This array holds machine specific line separator characters. */
138 const char line_separator_chars
[] = "";
140 /* Chars that can be used to separate mant from exp in floating point nums */
141 const char EXP_CHARS
[] = "eE";
143 /* Chars that mean this number is a floating point constant */
146 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
148 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
149 changed in read.c . Ideally it shouldn't have to know about it at all,
150 but nothing is ideal around here.
153 static char *insn_error
;
155 static int byte_order
= BYTE_ORDER
;
157 static int auto_align
= 1;
159 /* Symbol labelling the current insn. */
160 static symbolS
*insn_label
;
162 /* When outputting SVR4 PIC code, the assembler needs to know the
163 offset in the stack frame from which to restore the $gp register.
164 This is set by the .cprestore pseudo-op, and saved in this
166 static offsetT mips_cprestore_offset
= -1;
168 /* This is the register which holds the stack frame, as set by the
169 .frame pseudo-op. This is needed to implement .cprestore. */
170 static int mips_frame_reg
= SP
;
172 /* To output NOP instructions correctly, we need to keep information
173 about the previous two instructions. */
175 /* Whether we are optimizing. The default value of 2 means to remove
176 unneeded NOPs and swap branch instructions when possible. A value
177 of 1 means to not swap branches. A value of 0 means to always
179 static int mips_optimize
= 2;
181 /* The previous instruction. */
182 static struct mips_cl_insn prev_insn
;
184 /* The instruction before prev_insn. */
185 static struct mips_cl_insn prev_prev_insn
;
187 /* If we don't want information for prev_insn or prev_prev_insn, we
188 point the insn_mo field at this dummy integer. */
189 static const struct mips_opcode dummy_opcode
= { 0 };
191 /* Non-zero if prev_insn is valid. */
192 static int prev_insn_valid
;
194 /* The frag for the previous instruction. */
195 static struct frag
*prev_insn_frag
;
197 /* The offset into prev_insn_frag for the previous instruction. */
198 static long prev_insn_where
;
200 /* The reloc for the previous instruction, if any. */
201 static fixS
*prev_insn_fixp
;
203 /* Non-zero if the previous instruction was in a delay slot. */
204 static int prev_insn_is_delay_slot
;
206 /* Non-zero if the previous instruction was in a .set noreorder. */
207 static int prev_insn_unreordered
;
209 /* Non-zero if the previous previous instruction was in a .set
211 static int prev_prev_insn_unreordered
;
213 /* Since the MIPS does not have multiple forms of PC relative
214 instructions, we do not have to do relaxing as is done on other
215 platforms. However, we do have to handle GP relative addressing
216 correctly, which turns out to be a similar problem.
218 Every macro that refers to a symbol can occur in (at least) two
219 forms, one with GP relative addressing and one without. For
220 example, loading a global variable into a register generally uses
221 an macroinstruction like this:
223 If i can be addressed off the GP register (this is true if it is in
224 the .sbss or .sdata section, or if it is known to be smaller than
225 the -G argument) this will generate the following instruction:
227 This instruction will use a GPREL reloc. If i can not be addressed
228 off the GP register, the following instruction sequence will be used:
231 In this case the first instruction will have a HI16 reloc, and the
232 second reloc will have a LO16 reloc. Both relocs will be against
235 The issue here is that we may not know whether i is GP addressable
236 until after we see the instruction that uses it. Therefore, we
237 want to be able to choose the final instruction sequence only at
238 the end of the assembly. This is similar to the way other
239 platforms choose the form of a PC relative instruction only at the
242 When generating position independent code we do not use GP
243 addressing in the same way, but the issue still arises as external
244 symbols and local symbols must be handled differently.
246 We handle these issues by actually generating both possible
247 instruction sequences. The longer one is put in a frag_var with
248 type rs_machine_dependent. We encode what to do with the frag in
249 the subtype field. We encode (1) the number of existing bytes to
250 replace, (2) the number of new bytes to use, (3) the offset from
251 the start of the existing bytes to the first reloc we must generate
252 (that is, the offset is applied from the start of the existing
253 bytes after they are replaced by the new bytes, if any), (4) the
254 offset from the start of the existing bytes to the second reloc,
255 (5) whether a third reloc is needed (the third reloc is always four
256 bytes after the second reloc), and (6) whether to warn if this
257 variant is used (this is sometimes needed if .set nomacro or .set
258 noat is in effect). All these numbers are reasonably small.
260 Generating two instruction sequences must be handled carefully to
261 ensure that delay slots are handled correctly. Fortunately, the
262 issue only arises in a restricted number of cases. When the second
263 instruction sequence is generated, append_insn is directed to
264 maintain the existing delay slot information, so it continues to
265 apply to any code after the second instruction sequence. This
266 means that the second instruction sequence must not impose any
267 requirements not required by the first instruction sequence.
269 These variant frags are then handled in functions called by the
270 machine independent code. md_estimate_size_before_relax returns
271 the final size of the frag. md_convert_frag sets up the final form
272 of the frag. tc_gen_reloc adjust the first reloc and adds a second
274 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
278 | (((reloc1) + 64) << 9) \
279 | (((reloc2) + 64) << 2) \
280 | ((reloc3) ? (1 << 1) : 0) \
282 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
283 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
284 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
285 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
286 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
287 #define RELAX_WARN(i) ((i) & 1)
289 /* Prototypes for static functions. */
292 #define internalError() \
293 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
295 #define internalError() as_fatal ("MIPS internal Error");
298 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
299 unsigned int reg
, int fpr
));
300 static void append_insn
PARAMS ((char *place
,
301 struct mips_cl_insn
* ip
,
303 bfd_reloc_code_real_type r
));
304 static void mips_no_prev_insn
PARAMS ((void));
305 static void mips_emit_delays
PARAMS ((void));
306 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
307 const char *name
, const char *fmt
,
309 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
310 expressionS
* ep
, int regnum
));
311 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
312 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
314 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
315 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
316 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
317 #ifdef LOSING_COMPILER
318 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
320 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
321 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
322 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
323 static symbolS
*get_symbol
PARAMS ((void));
324 static void mips_align
PARAMS ((int to
, int fill
));
325 static void s_align
PARAMS ((int));
326 static void s_stringer
PARAMS ((int));
327 static void s_change_sec
PARAMS ((int));
328 static void s_cons
PARAMS ((int));
329 static void s_err
PARAMS ((int));
330 static void s_extern
PARAMS ((int));
331 static void s_float_cons
PARAMS ((int));
332 static void s_option
PARAMS ((int));
333 static void s_mipsset
PARAMS ((int));
334 static void s_mips_space
PARAMS ((int));
335 static void s_abicalls
PARAMS ((int));
336 static void s_cpload
PARAMS ((int));
337 static void s_cprestore
PARAMS ((int));
338 static void s_gpword
PARAMS ((int));
339 static void s_cpadd
PARAMS ((int));
340 #ifndef ECOFF_DEBUGGING
341 static void md_obj_begin
PARAMS ((void));
342 static void md_obj_end
PARAMS ((void));
343 static long get_number
PARAMS ((void));
344 static void s_ent
PARAMS ((int));
345 static void s_mipsend
PARAMS ((int));
346 static void s_file
PARAMS ((int));
348 static void s_frame
PARAMS ((int));
349 static void s_loc
PARAMS ((int));
350 static void s_mask
PARAMS ((char));
356 The following pseudo-ops from the Kane and Heinrich MIPS book
357 should be defined here, but are currently unsupported: .alias,
358 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
360 The following pseudo-ops from the Kane and Heinrich MIPS book are
361 specific to the type of debugging information being generated, and
362 should be defined by the object format: .aent, .begin, .bend,
363 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
366 The following pseudo-ops from the Kane and Heinrich MIPS book are
367 not MIPS CPU specific, but are also not specific to the object file
368 format. This file is probably the best place to define them, but
369 they are not currently supported: .asm0, .endr, .lab, .repeat,
370 .struct, .weakext. */
372 const pseudo_typeS md_pseudo_table
[] =
374 /* MIPS specific pseudo-ops. */
375 {"option", s_option
, 0},
376 {"set", s_mipsset
, 0},
377 {"rdata", s_change_sec
, 'r'},
378 {"sdata", s_change_sec
, 's'},
379 {"livereg", s_ignore
, 0},
380 { "abicalls", s_abicalls
, 0},
381 { "cpload", s_cpload
, 0},
382 { "cprestore", s_cprestore
, 0},
383 { "gpword", s_gpword
, 0},
384 { "cpadd", s_cpadd
, 0},
386 /* Relatively generic pseudo-ops that happen to be used on MIPS
388 {"asciiz", s_stringer
, 1},
389 {"bss", s_change_sec
, 'b'},
392 {"dword", s_cons
, 3},
394 /* These pseudo-ops are defined in read.c, but must be overridden
395 here for one reason or another. */
396 {"align", s_align
, 0},
397 {"ascii", s_stringer
, 0},
398 {"asciz", s_stringer
, 1},
400 {"data", s_change_sec
, 'd'},
401 {"double", s_float_cons
, 'd'},
402 {"extern", s_extern
, 0},
403 {"float", s_float_cons
, 'f'},
404 {"space", s_mips_space
, 0},
405 {"text", s_change_sec
, 't'},
408 #ifndef ECOFF_DEBUGGING
409 /* These pseudo-ops should be defined by the object file format.
410 However, a.out doesn't support them, so we have versions here. */
412 {"bgnb", s_ignore
, 0},
413 {"end", s_mipsend
, 0},
414 {"endb", s_ignore
, 0},
417 {"fmask", s_ignore
, 'F'},
418 {"frame", s_ignore
, 0},
419 {"loc", s_ignore
, 0},
420 {"mask", s_ignore
, 'R'},
421 {"verstamp", s_ignore
, 0},
428 const relax_typeS md_relax_table
[] =
433 static char *expr_end
;
435 static expressionS imm_expr
;
436 static expressionS offset_expr
;
437 static bfd_reloc_code_real_type imm_reloc
;
438 static bfd_reloc_code_real_type offset_reloc
;
440 /* FIXME: This should be handled in a different way. */
441 extern int target_big_endian
;
444 * This function is called once, at assembler startup time. It should
445 * set up all the tables, etc. that the MD part of the assembler will need.
451 register const char *retval
= NULL
;
452 register unsigned int i
= 0;
456 if (strcmp (TARGET_CPU
, "mips") == 0)
458 else if (strcmp (TARGET_CPU
, "r6000") == 0
459 || strcmp (TARGET_CPU
, "mips2") == 0)
461 else if (strcmp (TARGET_CPU
, "mips64") == 0
462 || strcmp (TARGET_CPU
, "r4000") == 0
463 || strcmp (TARGET_CPU
, "mips3") == 0)
472 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
475 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
478 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
482 as_warn ("Could not set architecture and machine");
484 op_hash
= hash_new ();
486 for (i
= 0; i
< NUMOPCODES
;)
488 const char *name
= mips_opcodes
[i
].name
;
490 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
493 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
494 mips_opcodes
[i
].name
, retval
);
495 as_fatal ("Broken assembler. No assembly attempted.");
499 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
500 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
501 != mips_opcodes
[i
].match
))
503 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
504 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
505 as_fatal ("Broken assembler. No assembly attempted.");
509 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
512 mips_no_prev_insn ();
520 /* set the default alignment for the text section (2**2) */
521 record_alignment (text_section
, 2);
523 /* FIXME: This should be handled in a different way. */
524 target_big_endian
= byte_order
== BIG_ENDIAN
;
527 bfd_set_gp_size (stdoutput
, g_switch_value
);
531 /* Sections must be aligned to 16 byte boundaries. */
532 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
533 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
534 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
536 /* Create a .reginfo section for register masks and a .mdebug
537 section for debugging information. */
545 sec
= subseg_new (".reginfo", (subsegT
) 0);
547 /* The ABI says this section should be loaded so that the running
548 program can access it. */
549 (void) bfd_set_section_flags (stdoutput
, sec
,
550 (SEC_ALLOC
| SEC_LOAD
551 | SEC_READONLY
| SEC_DATA
));
552 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
554 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
556 #ifdef ECOFF_DEBUGGING
557 sec
= subseg_new (".mdebug", (subsegT
) 0);
558 (void) bfd_set_section_flags (stdoutput
, sec
,
559 SEC_HAS_CONTENTS
| SEC_READONLY
);
560 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
563 subseg_set (seg
, subseg
);
567 #ifndef ECOFF_DEBUGGING
575 #ifndef ECOFF_DEBUGGING
584 struct mips_cl_insn insn
;
586 imm_expr
.X_op
= O_absent
;
587 offset_expr
.X_op
= O_absent
;
589 mips_ip (str
, &insn
);
592 as_bad ("%s `%s'", insn_error
, str
);
595 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
601 if (imm_expr
.X_op
!= O_absent
)
602 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
603 else if (offset_expr
.X_op
!= O_absent
)
604 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
606 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
610 /* See whether instruction IP reads register REG. If FPR is non-zero,
611 REG is a floating point register. */
614 insn_uses_reg (ip
, reg
, fpr
)
615 struct mips_cl_insn
*ip
;
619 /* Don't report on general register 0, since it never changes. */
620 if (! fpr
&& reg
== 0)
625 /* If we are called with either $f0 or $f1, we must check $f0.
626 This is not optimal, because it will introduce an unnecessary
627 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
628 need to distinguish reading both $f0 and $f1 or just one of
629 them. Note that we don't have to check the other way,
630 because there is no instruction that sets both $f0 and $f1
631 and requires a delay. */
632 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
633 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
634 == (reg
&~ (unsigned) 1)))
636 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
637 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
638 == (reg
&~ (unsigned) 1)))
643 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
644 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
646 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
647 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
654 /* Output an instruction. PLACE is where to put the instruction; if
655 it is NULL, this uses frag_more to get room. IP is the instruction
656 information. ADDRESS_EXPR is an operand of the instruction to be
657 used with RELOC_TYPE. */
660 append_insn (place
, ip
, address_expr
, reloc_type
)
662 struct mips_cl_insn
*ip
;
663 expressionS
*address_expr
;
664 bfd_reloc_code_real_type reloc_type
;
666 register unsigned long prev_pinfo
, pinfo
;
671 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
672 pinfo
= ip
->insn_mo
->pinfo
;
674 if (place
== NULL
&& ! mips_noreorder
)
676 /* If the previous insn required any delay slots, see if we need
677 to insert a NOP or two. There are eight kinds of possible
678 hazards, of which an instruction can have at most one type.
679 (1) a load from memory delay
680 (2) a load from a coprocessor delay
681 (3) an unconditional branch delay
682 (4) a conditional branch delay
683 (5) a move to coprocessor register delay
684 (6) a load coprocessor register from memory delay
685 (7) a coprocessor condition code delay
686 (8) a HI/LO special register delay
688 There are a lot of optimizations we could do that we don't.
689 In particular, we do not, in general, reorder instructions.
690 If you use gcc with optimization, it will reorder
691 instructions and generally do much more optimization then we
692 do here; repeating all that work in the assembler would only
693 benefit hand written assembly code, and does not seem worth
696 /* This is how a NOP is emitted. */
697 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
699 /* The previous insn might require a delay slot, depending upon
700 the contents of the current insn. */
701 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
703 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
705 /* A load from a coprocessor or from memory. All load
706 delays delay the use of general register rt for one
707 instruction on the r3000. The r6000 and r4000 use
709 know (prev_pinfo
& INSN_WRITE_GPR_T
);
710 if (mips_optimize
== 0
711 || insn_uses_reg (ip
,
712 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
717 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
719 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
721 /* A generic coprocessor delay. The previous instruction
722 modified a coprocessor general or control register. If
723 it modified a control register, we need to avoid any
724 coprocessor instruction (this is probably not always
725 required, but it sometimes is). If it modified a general
726 register, we avoid using that register.
728 On the r6000 and r4000 loading a coprocessor register
729 from memory is interlocked, and does not require a delay.
731 This case is not handled very well. There is no special
732 knowledge of CP0 handling, and the coprocessors other
733 than the floating point unit are not distinguished at
735 if (prev_pinfo
& INSN_WRITE_FPR_T
)
737 if (mips_optimize
== 0
738 || insn_uses_reg (ip
,
739 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
744 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
746 if (mips_optimize
== 0
747 || insn_uses_reg (ip
,
748 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
755 /* We don't know exactly what the previous instruction
756 does. If the current instruction uses a coprocessor
757 register, we must insert a NOP. If previous
758 instruction may set the condition codes, and the
759 current instruction uses them, we must insert two
761 if (mips_optimize
== 0
762 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
763 && (pinfo
& INSN_READ_COND_CODE
)))
765 else if (pinfo
& INSN_COP
)
769 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
771 /* The previous instruction sets the coprocessor condition
772 codes, but does not require a general coprocessor delay
773 (this means it is a floating point comparison
774 instruction). If this instruction uses the condition
775 codes, we need to insert a single NOP. */
776 if (mips_optimize
== 0
777 || (pinfo
& INSN_READ_COND_CODE
))
780 else if (prev_pinfo
& INSN_READ_LO
)
782 /* The previous instruction reads the LO register; if the
783 current instruction writes to the LO register, we must
785 if (mips_optimize
== 0
786 || (pinfo
& INSN_WRITE_LO
))
789 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
791 /* The previous instruction reads the HI register; if the
792 current instruction writes to the HI register, we must
794 if (mips_optimize
== 0
795 || (pinfo
& INSN_WRITE_HI
))
799 /* There are two cases which require two intervening
800 instructions: 1) setting the condition codes using a move to
801 coprocessor instruction which requires a general coprocessor
802 delay and then reading the condition codes 2) reading the HI
803 or LO register and then writing to it. If we are not already
804 emitting a NOP instruction, we must check for these cases
805 compared to the instruction previous to the previous
808 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
809 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
810 && (pinfo
& INSN_READ_COND_CODE
))
811 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
812 && (pinfo
& INSN_WRITE_LO
))
813 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
814 && (pinfo
& INSN_WRITE_HI
))))
817 /* If we are being given a nop instruction, don't bother with
818 one of the nops we would otherwise output. This will only
819 happen when a nop instruction is used with mips_optimize set
821 if (nops
> 0 && ip
->insn_opcode
== 0)
824 /* Now emit the right number of NOP instructions. */
831 listing_prev_line ();
832 if (insn_label
!= NULL
)
834 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
835 insn_label
->sy_frag
= frag_now
;
836 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
846 if (address_expr
!= NULL
)
848 if (address_expr
->X_op
== O_constant
)
853 ip
->insn_opcode
|= address_expr
->X_add_number
;
857 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
860 case BFD_RELOC_MIPS_JMP
:
861 case BFD_RELOC_16_PCREL_S2
:
870 assert (reloc_type
!= BFD_RELOC_UNUSED
);
872 /* Don't generate a reloc if we are writing into a variant
875 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
877 reloc_type
== BFD_RELOC_16_PCREL_S2
,
882 md_number_to_chars (f
, ip
->insn_opcode
, 4);
884 /* Update the register mask information. */
885 if (pinfo
& INSN_WRITE_GPR_D
)
886 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
887 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
888 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
889 if (pinfo
& INSN_READ_GPR_S
)
890 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
891 if (pinfo
& INSN_WRITE_GPR_31
)
892 mips_gprmask
|= 1 << 31;
893 if (pinfo
& INSN_WRITE_FPR_D
)
894 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
895 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
896 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
897 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
898 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
899 if (pinfo
& INSN_COP
)
901 /* We don't keep enough information to sort these cases out. */
903 /* Never set the bit for $0, which is always zero. */
904 mips_gprmask
&=~ 1 << 0;
906 if (place
== NULL
&& ! mips_noreorder
)
908 /* Filling the branch delay slot is more complex. We try to
909 switch the branch with the previous instruction, which we can
910 do if the previous instruction does not set up a condition
911 that the branch tests and if the branch is not itself the
912 target of any branch. */
913 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
914 || (pinfo
& INSN_COND_BRANCH_DELAY
))
916 if (mips_optimize
< 2
917 /* If we have seen .set nobopt, don't optimize. */
919 /* If we have seen .set volatile or .set nomove, don't
922 /* If we had to emit any NOP instructions, then we
923 already know we can not swap. */
925 /* If we don't even know the previous insn, we can not
928 /* If the previous insn is already in a branch delay
929 slot, then we can not swap. */
930 || prev_insn_is_delay_slot
931 /* If the previous previous insn was in a .set
932 noreorder, we can't swap. Actually, the MIPS
933 assembler will swap in this situation. However, gcc
934 configured -with-gnu-as will generate code like
940 in which we can not swap the bne and INSN. If gcc is
941 not configured -with-gnu-as, it does not output the
942 .set pseudo-ops. We don't have to check
943 prev_insn_unreordered, because prev_insn_valid will
944 be 0 in that case. We don't want to use
945 prev_prev_insn_valid, because we do want to be able
946 to swap at the start of a function. */
947 || prev_prev_insn_unreordered
948 /* If the branch is itself the target of a branch, we
949 can not swap. We cheat on this; all we check for is
950 whether there is a label on this instruction. If
951 there are any branches to anything other than a
952 label, users must use .set noreorder. */
953 || insn_label
!= NULL
954 /* If the previous instruction is in a variant frag, we
955 can not do the swap. */
956 || prev_insn_frag
->fr_type
== rs_machine_dependent
957 /* If the branch reads the condition codes, we don't
958 even try to swap, because in the sequence
963 we can not swap, and I don't feel like handling that
965 || (pinfo
& INSN_READ_COND_CODE
)
966 /* We can not swap with an instruction that requires a
967 delay slot, becase the target of the branch might
968 interfere with that instruction. */
970 & (INSN_LOAD_COPROC_DELAY
971 | INSN_COPROC_MOVE_DELAY
972 | INSN_WRITE_COND_CODE
977 & (INSN_LOAD_MEMORY_DELAY
978 | INSN_COPROC_MEMORY_DELAY
)))
979 /* We can not swap with a branch instruction. */
981 & (INSN_UNCOND_BRANCH_DELAY
982 | INSN_COND_BRANCH_DELAY
983 | INSN_COND_BRANCH_LIKELY
))
984 /* We do not swap with a trap instruction, since it
985 complicates trap handlers to have the trap
986 instruction be in a delay slot. */
987 || (prev_pinfo
& INSN_TRAP
)
988 /* If the branch reads a register that the previous
989 instruction sets, we can not swap. */
990 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
991 && insn_uses_reg (ip
,
992 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
995 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
996 && insn_uses_reg (ip
,
997 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1000 /* If the branch writes a register that the previous
1001 instruction sets, we can not swap (we know that
1002 branches write only to RD or to $31). */
1003 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1004 && (((pinfo
& INSN_WRITE_GPR_D
)
1005 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1006 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1007 || ((pinfo
& INSN_WRITE_GPR_31
)
1008 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1011 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1012 && (((pinfo
& INSN_WRITE_GPR_D
)
1013 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1014 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1015 || ((pinfo
& INSN_WRITE_GPR_31
)
1016 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1019 /* If the branch writes a register that the previous
1020 instruction reads, we can not swap (we know that
1021 branches only write to RD or to $31). */
1022 || ((pinfo
& INSN_WRITE_GPR_D
)
1023 && insn_uses_reg (&prev_insn
,
1024 ((ip
->insn_opcode
>> OP_SH_RD
)
1027 || ((pinfo
& INSN_WRITE_GPR_31
)
1028 && insn_uses_reg (&prev_insn
, 31, 0))
1029 /* If the previous previous instruction has a load
1030 delay, and sets a register that the branch reads, we
1032 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1034 && (prev_prev_insn
.insn_mo
->pinfo
1035 & INSN_LOAD_MEMORY_DELAY
)))
1036 && insn_uses_reg (ip
,
1037 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1041 /* We could do even better for unconditional branches to
1042 portions of this object file; we could pick up the
1043 instruction at the destination, put it in the delay
1044 slot, and bump the destination address. */
1046 /* Update the previous insn information. */
1047 prev_prev_insn
= *ip
;
1048 prev_insn
.insn_mo
= &dummy_opcode
;
1055 /* It looks like we can actually do the swap. */
1056 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1057 memcpy (temp
, prev_f
, 4);
1058 memcpy (prev_f
, f
, 4);
1059 memcpy (f
, temp
, 4);
1062 prev_insn_fixp
->fx_frag
= frag_now
;
1063 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1067 fixp
->fx_frag
= prev_insn_frag
;
1068 fixp
->fx_where
= prev_insn_where
;
1070 /* Update the previous insn information; leave prev_insn
1072 prev_prev_insn
= *ip
;
1074 prev_insn_is_delay_slot
= 1;
1076 /* If that was an unconditional branch, forget the previous
1077 insn information. */
1078 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1080 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1081 prev_insn
.insn_mo
= &dummy_opcode
;
1084 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1086 /* We don't yet optimize a branch likely. What we should do
1087 is look at the target, copy the instruction found there
1088 into the delay slot, and increment the branch to jump to
1089 the next instruction. */
1091 /* Update the previous insn information. */
1092 prev_prev_insn
= *ip
;
1093 prev_insn
.insn_mo
= &dummy_opcode
;
1097 /* Update the previous insn information. */
1099 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1101 prev_prev_insn
= prev_insn
;
1104 /* Any time we see a branch, we always fill the delay slot
1105 immediately; since this insn is not a branch, we know it
1106 is not in a delay slot. */
1107 prev_insn_is_delay_slot
= 0;
1110 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1111 prev_insn_unreordered
= 0;
1112 prev_insn_frag
= frag_now
;
1113 prev_insn_where
= f
- frag_now
->fr_literal
;
1114 prev_insn_fixp
= fixp
;
1115 prev_insn_valid
= 1;
1118 /* We just output an insn, so the next one doesn't have a label. */
1122 /* This function forgets that there was any previous instruction or
1126 mips_no_prev_insn ()
1128 prev_insn
.insn_mo
= &dummy_opcode
;
1129 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1130 prev_insn_valid
= 0;
1131 prev_insn_is_delay_slot
= 0;
1132 prev_insn_unreordered
= 0;
1133 prev_prev_insn_unreordered
= 0;
1137 /* This function must be called whenever we turn on noreorder or emit
1138 something other than instructions. It inserts any NOPS which might
1139 be needed by the previous instruction, and clears the information
1140 kept for the previous instructions. */
1145 if (! mips_noreorder
)
1150 if ((prev_insn
.insn_mo
->pinfo
1151 & (INSN_LOAD_COPROC_DELAY
1152 | INSN_COPROC_MOVE_DELAY
1153 | INSN_WRITE_COND_CODE
1157 && (prev_insn
.insn_mo
->pinfo
1158 & (INSN_LOAD_MEMORY_DELAY
1159 | INSN_COPROC_MEMORY_DELAY
))))
1162 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1163 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1164 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1167 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1168 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1169 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1174 if (insn_label
!= NULL
)
1176 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1177 insn_label
->sy_frag
= frag_now
;
1178 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1181 mips_no_prev_insn ();
1185 /* Build an instruction created by a macro expansion. This is passed
1186 a pointer to the count of instructions created so far, an
1187 expression, the name of the instruction to build, an operand format
1188 string, and corresponding arguments. */
1192 macro_build (char *place
,
1198 #else /* ! defined (NO_STDARG) */
1200 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1207 #endif /* ! defined (NO_STDARG) */
1209 struct mips_cl_insn insn
;
1210 bfd_reloc_code_real_type r
;
1214 va_start (args
, fmt
);
1220 * If the macro is about to expand into a second instruction,
1221 * print a warning if needed. We need to pass ip as a parameter
1222 * to generate a better warning message here...
1224 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1225 as_warn ("Macro instruction expanded into multiple instructions");
1228 *counter
+= 1; /* bump instruction counter */
1230 r
= BFD_RELOC_UNUSED
;
1231 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1232 assert (insn
.insn_mo
);
1233 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1235 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1236 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1239 assert (insn
.insn_mo
->name
);
1240 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1242 insn
.insn_opcode
= insn
.insn_mo
->match
;
1258 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1264 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1269 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1274 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1281 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1285 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1289 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1296 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1302 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1303 assert (r
== BFD_RELOC_MIPS_GPREL
1304 || r
== BFD_RELOC_MIPS_LITERAL
1305 || r
== BFD_RELOC_LO16
1306 || r
== BFD_RELOC_MIPS_GOT16
1307 || r
== BFD_RELOC_MIPS_CALL16
);
1311 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1312 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1317 assert (ep
!= NULL
);
1319 * This allows macro() to pass an immediate expression for
1320 * creating short branches without creating a symbol.
1321 * Note that the expression still might come from the assembly
1322 * input, in which case the value is not checked for range nor
1323 * is a relocation entry generated (yuck).
1325 if (ep
->X_op
== O_constant
)
1327 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1331 r
= BFD_RELOC_16_PCREL_S2
;
1335 assert (ep
!= NULL
);
1336 r
= BFD_RELOC_MIPS_JMP
;
1345 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1347 append_insn (place
, &insn
, ep
, r
);
1351 * Generate a "lui" instruction.
1354 macro_build_lui (place
, counter
, ep
, regnum
)
1360 expressionS high_expr
;
1361 struct mips_cl_insn insn
;
1362 bfd_reloc_code_real_type r
;
1363 CONST
char *name
= "lui";
1364 CONST
char *fmt
= "t,u";
1370 high_expr
.X_op
= O_constant
;
1371 high_expr
.X_add_number
= 0;
1374 if (high_expr
.X_op
== O_constant
)
1376 /* we can compute the instruction now without a relocation entry */
1377 if (high_expr
.X_add_number
& 0x8000)
1378 high_expr
.X_add_number
+= 0x10000;
1379 high_expr
.X_add_number
=
1380 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1381 r
= BFD_RELOC_UNUSED
;
1385 assert (ep
->X_op
== O_symbol
);
1386 /* _gp_disp is a special case, used from s_cpload. */
1387 assert (mips_pic
== 0
1388 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1389 r
= BFD_RELOC_HI16_S
;
1393 * If the macro is about to expand into a second instruction,
1394 * print a warning if needed. We need to pass ip as a parameter
1395 * to generate a better warning message here...
1397 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1398 as_warn ("Macro instruction expanded into multiple instructions");
1401 *counter
+= 1; /* bump instruction counter */
1403 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1404 assert (insn
.insn_mo
);
1405 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1406 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1408 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1409 if (r
== BFD_RELOC_UNUSED
)
1411 insn
.insn_opcode
|= high_expr
.X_add_number
;
1412 append_insn (place
, &insn
, NULL
, r
);
1415 append_insn (place
, &insn
, &high_expr
, r
);
1419 * Generates code to set the $at register to true (one)
1420 * if reg is less than the immediate expression.
1423 set_at (counter
, reg
, unsignedp
)
1428 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1429 macro_build ((char *) NULL
, counter
, &imm_expr
,
1430 unsignedp
? "sltiu" : "slti",
1431 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1434 load_register (counter
, AT
, &imm_expr
);
1435 macro_build ((char *) NULL
, counter
, NULL
,
1436 unsignedp
? "sltu" : "slt",
1437 "d,v,t", AT
, reg
, AT
);
1441 /* Warn if an expression is not a constant. */
1444 check_absolute_expr (ip
, ex
)
1445 struct mips_cl_insn
*ip
;
1448 if (ex
->X_op
!= O_constant
)
1449 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1453 * This routine generates the least number of instructions neccessary to load
1454 * an absolute expression value into a register.
1457 load_register (counter
, reg
, ep
)
1462 assert (ep
->X_op
== O_constant
);
1463 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1464 macro_build ((char *) NULL
, counter
, ep
,
1465 mips_isa
< 3 ? "addiu" : "daddiu",
1466 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1467 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1468 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1469 (int) BFD_RELOC_LO16
);
1470 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1471 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1472 == ~ (offsetT
) 0x7fffffff))
1474 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
);
1475 if ((ep
->X_add_number
& 0xffff) != 0)
1476 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1477 (int) BFD_RELOC_LO16
);
1479 else if (mips_isa
< 3)
1481 as_bad ("Number larger than 32 bits");
1482 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1483 (int) BFD_RELOC_LO16
);
1488 expressionS hi32
, lo32
;
1492 hi32
.X_add_number
>>= shift
;
1493 hi32
.X_add_number
&= 0xffffffff;
1494 if ((hi32
.X_add_number
& 0x80000000) != 0)
1495 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1496 load_register (counter
, reg
, &hi32
);
1498 lo32
.X_add_number
&= 0xffffffff;
1499 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1500 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1506 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1509 mid16
.X_add_number
>>= 16;
1510 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1511 reg
, (int) BFD_RELOC_LO16
);
1512 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1515 if ((lo32
.X_add_number
& 0xffff) != 0)
1516 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1517 (int) BFD_RELOC_LO16
);
1521 /* Load an address into a register. */
1524 load_address (counter
, reg
, ep
)
1531 if (ep
->X_op
!= O_constant
1532 && ep
->X_op
!= O_symbol
)
1534 as_bad ("expression too complex");
1535 ep
->X_op
= O_constant
;
1538 if (ep
->X_op
== O_constant
)
1539 load_register (counter
, reg
, ep
);
1540 else if (mips_pic
== 0)
1542 /* If this is a reference to a GP relative symbol, we want
1543 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1545 lui $reg,<sym> (BFD_RELOC_HI16_S)
1546 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1547 If we have an addend, we always use the latter form. */
1548 if (ep
->X_add_number
!= 0)
1553 macro_build ((char *) NULL
, counter
, ep
,
1554 mips_isa
< 3 ? "addiu" : "daddiu",
1555 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1556 p
= frag_var (rs_machine_dependent
, 8, 0,
1557 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1558 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1560 macro_build_lui (p
, counter
, ep
, reg
);
1563 macro_build (p
, counter
, ep
,
1564 mips_isa
< 3 ? "addiu" : "daddiu",
1565 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1571 /* If this is a reference to an external symbol, we want
1572 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1574 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1576 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1577 If there is a constant, it must be added in afterward. */
1578 ex
.X_add_number
= ep
->X_add_number
;
1579 ep
->X_add_number
= 0;
1581 macro_build ((char *) NULL
, counter
, ep
,
1582 mips_isa
< 3 ? "lw" : "ld",
1583 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1584 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1585 p
= frag_var (rs_machine_dependent
, 4, 0,
1586 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1587 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1588 macro_build (p
, counter
, ep
,
1589 mips_isa
< 3 ? "addiu" : "daddiu",
1590 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1591 if (ex
.X_add_number
!= 0)
1593 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1594 as_bad ("PIC code offset overflow (max 16 signed bits)");
1595 ex
.X_op
= O_constant
;
1596 macro_build (p
, counter
, &ex
,
1597 mips_isa
< 3 ? "addiu" : "daddiu",
1598 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1605 * This routine implements the seemingly endless macro or synthesized
1606 * instructions and addressing modes in the mips assembly language. Many
1607 * of these macros are simple and are similar to each other. These could
1608 * probably be handled by some kind of table or grammer aproach instead of
1609 * this verbose method. Others are not simple macros but are more like
1610 * optimizing code generation.
1611 * One interesting optimization is when several store macros appear
1612 * consecutivly that would load AT with the upper half of the same address.
1613 * The ensuing load upper instructions are ommited. This implies some kind
1614 * of global optimization. We currently only optimize within a single macro.
1615 * For many of the load and store macros if the address is specified as a
1616 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1617 * first load register 'at' with zero and use it as the base register. The
1618 * mips assembler simply uses register $zero. Just one tiny optimization
1623 struct mips_cl_insn
*ip
;
1625 register int treg
, sreg
, dreg
, breg
;
1638 bfd_reloc_code_real_type r
;
1641 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1642 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1643 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1644 mask
= ip
->insn_mo
->mask
;
1646 expr1
.X_op
= O_constant
;
1647 expr1
.X_op_symbol
= NULL
;
1648 expr1
.X_add_symbol
= NULL
;
1649 expr1
.X_add_number
= 1;
1661 mips_emit_delays ();
1663 mips_any_noreorder
= 1;
1665 expr1
.X_add_number
= 8;
1666 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1668 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1670 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1671 macro_build ((char *) NULL
, &icnt
, NULL
,
1672 dbl
? "dsub" : "sub",
1673 "d,v,t", dreg
, 0, sreg
);
1696 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1698 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1699 (int) BFD_RELOC_LO16
);
1702 load_register (&icnt
, AT
, &imm_expr
);
1703 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1722 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1724 if (mask
!= M_NOR_I
)
1725 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1726 sreg
, (int) BFD_RELOC_LO16
);
1729 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1730 treg
, sreg
, (int) BFD_RELOC_LO16
);
1731 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "nor", "d,v,t",
1737 load_register (&icnt
, AT
, &imm_expr
);
1738 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1755 if (imm_expr
.X_add_number
== 0)
1757 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1761 load_register (&icnt
, AT
, &imm_expr
);
1762 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1770 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1771 likely
? "bgezl" : "bgez",
1777 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1778 likely
? "blezl" : "blez",
1782 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1783 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1784 likely
? "beql" : "beq",
1791 /* check for > max integer */
1792 maxnum
= 0x7fffffff;
1800 if (imm_expr
.X_add_number
>= maxnum
)
1803 /* result is always false */
1806 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1807 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1811 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1812 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1817 imm_expr
.X_add_number
++;
1821 if (mask
== M_BGEL_I
)
1823 if (imm_expr
.X_add_number
== 0)
1825 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1826 likely
? "bgezl" : "bgez",
1830 if (imm_expr
.X_add_number
== 1)
1832 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1833 likely
? "bgtzl" : "bgtz",
1837 maxnum
= 0x7fffffff;
1845 maxnum
= - maxnum
- 1;
1846 if (imm_expr
.X_add_number
<= maxnum
)
1849 /* result is always true */
1850 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1851 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1854 set_at (&icnt
, sreg
, 0);
1855 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1856 likely
? "beql" : "beq",
1867 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1868 likely
? "beql" : "beq",
1872 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1874 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1875 likely
? "beql" : "beq",
1882 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1884 imm_expr
.X_add_number
++;
1888 if (mask
== M_BGEUL_I
)
1890 if (imm_expr
.X_add_number
== 0)
1892 if (imm_expr
.X_add_number
== 1)
1894 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1895 likely
? "bnel" : "bne",
1899 set_at (&icnt
, sreg
, 1);
1900 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1901 likely
? "beql" : "beq",
1910 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1911 likely
? "bgtzl" : "bgtz",
1917 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1918 likely
? "bltzl" : "bltz",
1922 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1923 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1924 likely
? "bnel" : "bne",
1933 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1934 likely
? "bnel" : "bne",
1940 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1942 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1943 likely
? "bnel" : "bne",
1952 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1953 likely
? "blezl" : "blez",
1959 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1960 likely
? "bgezl" : "bgez",
1964 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1965 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1966 likely
? "beql" : "beq",
1973 maxnum
= 0x7fffffff;
1981 if (imm_expr
.X_add_number
>= maxnum
)
1983 imm_expr
.X_add_number
++;
1987 if (mask
== M_BLTL_I
)
1989 if (imm_expr
.X_add_number
== 0)
1991 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1992 likely
? "bltzl" : "bltz",
1996 if (imm_expr
.X_add_number
== 1)
1998 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1999 likely
? "blezl" : "blez",
2003 set_at (&icnt
, sreg
, 0);
2004 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2005 likely
? "bnel" : "bne",
2014 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2015 likely
? "beql" : "beq",
2021 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2023 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2024 likely
? "beql" : "beq",
2031 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2033 imm_expr
.X_add_number
++;
2037 if (mask
== M_BLTUL_I
)
2039 if (imm_expr
.X_add_number
== 0)
2041 if (imm_expr
.X_add_number
== 1)
2043 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2044 likely
? "beql" : "beq",
2048 set_at (&icnt
, sreg
, 1);
2049 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2050 likely
? "bnel" : "bne",
2059 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2060 likely
? "bltzl" : "bltz",
2066 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2067 likely
? "bgtzl" : "bgtz",
2071 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2072 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2073 likely
? "bnel" : "bne",
2084 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2085 likely
? "bnel" : "bne",
2089 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2091 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2092 likely
? "bnel" : "bne",
2108 as_warn ("Divide by zero.");
2109 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2113 mips_emit_delays ();
2115 mips_any_noreorder
= 1;
2116 macro_build ((char *) NULL
, &icnt
, NULL
,
2117 dbl
? "ddiv" : "div",
2118 "z,s,t", sreg
, treg
);
2119 expr1
.X_add_number
= 8;
2120 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2121 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2122 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2123 expr1
.X_add_number
= -1;
2124 macro_build ((char *) NULL
, &icnt
, &expr1
,
2125 dbl
? "daddiu" : "addiu",
2126 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2127 expr1
.X_add_number
= dbl
? 20 : 16;
2128 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2131 expr1
.X_add_number
= 1;
2132 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2133 (int) BFD_RELOC_LO16
);
2134 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2139 expr1
.X_add_number
= 0x80000000;
2140 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
);
2142 expr1
.X_add_number
= 8;
2143 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2144 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2145 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2147 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2186 if (imm_expr
.X_add_number
== 0)
2188 as_warn ("Divide by zero.");
2189 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2192 if (imm_expr
.X_add_number
== 1)
2194 if (strcmp (s2
, "mflo") == 0)
2195 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2198 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2201 if (imm_expr
.X_add_number
== -1
2202 && s
[strlen (s
) - 1] != 'u')
2204 if (strcmp (s2
, "mflo") == 0)
2207 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2210 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2214 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2218 load_register (&icnt
, AT
, &imm_expr
);
2219 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2220 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2239 mips_emit_delays ();
2241 mips_any_noreorder
= 1;
2242 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2243 expr1
.X_add_number
= 8;
2244 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2245 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2246 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2248 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2252 /* Load the address of a symbol into a register. If M_LA_AB, we
2253 then add a base register to it. */
2254 if (offset_expr
.X_op
!= O_symbol
2255 && offset_expr
.X_op
!= O_constant
)
2257 as_bad ("expression too complex");
2258 offset_expr
.X_op
= O_constant
;
2272 if (offset_expr
.X_op
== O_constant
)
2273 load_register (&icnt
, tempreg
, &offset_expr
);
2274 else if (mips_pic
== 0)
2276 /* If this is a reference to an GP relative symbol, we want
2277 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2279 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2280 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2281 If we have a constant, we need two instructions anyhow,
2282 so we may as well always use the latter form. */
2283 if (offset_expr
.X_add_number
!= 0)
2288 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2289 mips_isa
< 3 ? "addiu" : "daddiu",
2290 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2291 p
= frag_var (rs_machine_dependent
, 8, 0,
2292 RELAX_ENCODE (4, 8, 0, 4, 0,
2293 mips_warn_about_macros
),
2294 offset_expr
.X_add_symbol
, (long) 0,
2297 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2300 macro_build (p
, &icnt
, &offset_expr
,
2301 mips_isa
< 3 ? "addiu" : "daddiu",
2302 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2306 /* If this is a reference to an external symbol, and there
2307 is no constant, we want
2308 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2309 For a local symbol, we want
2310 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2312 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2314 If we have a small constant, and this is a reference to
2315 an external symbol, we want
2316 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2318 addiu $tempreg,$tempreg,<constant>
2319 For a local symbol, we want the same instruction
2320 sequence, but we output a BFD_RELOC_LO16 reloc on the
2323 If we have a large constant, and this is a reference to
2324 an external symbol, we want
2325 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2326 lui $at,<hiconstant>
2327 addiu $at,$at,<loconstant>
2328 addu $tempreg,$tempreg,$at
2329 For a local symbol, we want the same instruction
2330 sequence, but we output a BFD_RELOC_LO16 reloc on the
2331 addiu instruction. */
2332 expr1
.X_add_number
= offset_expr
.X_add_number
;
2333 offset_expr
.X_add_number
= 0;
2335 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2336 mips_isa
< 3 ? "lw" : "ld",
2337 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2338 if (expr1
.X_add_number
== 0)
2346 /* We're going to put in an addu instruction using
2347 tempreg, so we may as well insert the nop right
2349 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2353 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2354 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2356 ? mips_warn_about_macros
2358 offset_expr
.X_add_symbol
, (long) 0,
2362 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2365 macro_build (p
, &icnt
, &expr1
,
2366 mips_isa
< 3 ? "addiu" : "daddiu",
2367 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2368 /* FIXME: If breg == 0, and the next instruction uses
2369 $tempreg, then if this variant case is used an extra
2370 nop will be generated. */
2372 else if (expr1
.X_add_number
>= -0x8000
2373 && expr1
.X_add_number
< 0x8000)
2375 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2377 macro_build ((char *) NULL
, &icnt
, &expr1
,
2378 mips_isa
< 3 ? "addiu" : "daddiu",
2379 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2380 (void) frag_var (rs_machine_dependent
, 0, 0,
2381 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2382 offset_expr
.X_add_symbol
, (long) 0,
2389 /* If we are going to add in a base register, and the
2390 target register and the base register are the same,
2391 then we are using AT as a temporary register. Since
2392 we want to load the constant into AT, we add our
2393 current AT (from the global offset table) and the
2394 register into the register now, and pretend we were
2395 not using a base register. */
2400 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2402 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2403 mips_isa
< 3 ? "addu" : "daddu",
2404 "d,v,t", treg
, AT
, breg
);
2410 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2411 macro_build ((char *) NULL
, &icnt
, &expr1
,
2412 mips_isa
< 3 ? "addiu" : "daddiu",
2413 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2414 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2415 mips_isa
< 3 ? "addu" : "daddu",
2416 "d,v,t", tempreg
, tempreg
, AT
);
2417 (void) frag_var (rs_machine_dependent
, 0, 0,
2418 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2419 offset_expr
.X_add_symbol
, (long) 0,
2426 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2427 mips_isa
< 3 ? "addu" : "daddu",
2428 "d,v,t", treg
, tempreg
, breg
);
2436 /* The j instruction may not be used in PIC code, since it
2437 requires an absolute address. We convert it to a b
2440 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2442 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2445 /* The jal instructions must be handled as macros because when
2446 generating PIC code they expand to multi-instruction
2447 sequences. Normally they are simple instructions. */
2454 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2459 /* I only know how to handle pic2. */
2460 assert (mips_pic
== 2);
2462 if (sreg
!= PIC_CALL_REG
)
2463 as_warn ("MIPS PIC call to register other than $25");
2465 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
2467 if (mips_cprestore_offset
< 0)
2468 as_warn ("No .cprestore pseudo-op used in PIC code");
2471 expr1
.X_add_number
= mips_cprestore_offset
;
2472 macro_build ((char *) NULL
, &icnt
, &expr1
,
2473 mips_isa
< 3 ? "lw" : "ld",
2474 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2485 /* I only know how to handle pic2. */
2486 assert (mips_pic
== 2);
2488 /* If this is a reference to an external symbol, we want
2489 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2493 lw $gp,cprestore($sp)
2494 The cprestore value is set using the .cprestore pseudo-op.
2495 If the symbol is not external, we want
2496 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2498 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2501 lw $gp,cprestore($sp)
2504 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2505 mips_isa
< 3 ? "lw" : "ld",
2506 "t,o(b)", PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL16
, GP
);
2507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2508 p
= frag_var (rs_machine_dependent
, 4, 0,
2509 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2510 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2511 macro_build (p
, &icnt
, &offset_expr
,
2512 mips_isa
< 3 ? "addiu" : "daddiu",
2513 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2514 (int) BFD_RELOC_LO16
);
2515 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "s",
2517 if (mips_cprestore_offset
< 0)
2518 as_warn ("No .cprestore pseudo-op used in PIC code");
2522 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2524 expr1
.X_add_number
= mips_cprestore_offset
;
2525 macro_build ((char *) NULL
, &icnt
, &expr1
,
2526 mips_isa
< 3 ? "lw" : "ld",
2527 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2595 if (breg
== treg
|| coproc
)
2664 if (mask
== M_LWC1_AB
2665 || mask
== M_SWC1_AB
2666 || mask
== M_LDC1_AB
2667 || mask
== M_SDC1_AB
2676 if (offset_expr
.X_op
!= O_constant
2677 && offset_expr
.X_op
!= O_symbol
)
2679 as_bad ("expression too complex");
2680 offset_expr
.X_op
= O_constant
;
2683 /* A constant expression in PIC code can be handled just as it
2684 is in non PIC code. */
2686 || offset_expr
.X_op
== O_constant
)
2688 /* If this is a reference to a GP relative symbol, and there
2689 is no base register, we want
2690 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2692 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2693 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2694 If we have a constant, we need two instructions anyhow,
2695 so we always use the latter form.
2697 If we have a base register, and this is a reference to a
2698 GP relative symbol, we want
2699 addu $tempreg,$breg,$gp
2700 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2702 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2703 addu $tempreg,$tempreg,$breg
2704 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2705 With a constant we always use the latter case. */
2708 if (offset_expr
.X_add_number
!= 0)
2713 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2714 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2715 p
= frag_var (rs_machine_dependent
, 8, 0,
2716 RELAX_ENCODE (4, 8, 0, 4, 0,
2717 (mips_warn_about_macros
2718 || (used_at
&& mips_noat
))),
2719 offset_expr
.X_add_symbol
, (long) 0,
2723 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2726 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2727 (int) BFD_RELOC_LO16
, tempreg
);
2731 if (offset_expr
.X_add_number
!= 0)
2736 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2737 mips_isa
< 3 ? "addu" : "daddu",
2738 "d,v,t", tempreg
, breg
, GP
);
2739 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2740 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2741 p
= frag_var (rs_machine_dependent
, 12, 0,
2742 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2743 offset_expr
.X_add_symbol
, (long) 0,
2746 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2749 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2750 mips_isa
< 3 ? "addu" : "daddu",
2751 "d,v,t", tempreg
, tempreg
, breg
);
2754 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2755 (int) BFD_RELOC_LO16
, tempreg
);
2760 /* If this is a reference to an external symbol, we want
2761 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2763 <op> $treg,0($tempreg)
2765 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2767 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2768 <op> $treg,0($tempreg)
2769 If there is a base register, we add it to $tempreg before
2770 the <op>. If there is a constant, we stick it in the
2771 <op> instruction. We don't handle constants larger than
2772 16 bits, because we have no way to load the upper 16 bits
2773 (actually, we could handle them for the subset of cases
2774 in which we are not using $at). */
2775 assert (offset_expr
.X_op
== O_symbol
);
2776 expr1
.X_add_number
= offset_expr
.X_add_number
;
2777 offset_expr
.X_add_number
= 0;
2778 if (expr1
.X_add_number
< -0x8000
2779 || expr1
.X_add_number
>= 0x8000)
2780 as_bad ("PIC code offset overflow (max 16 signed bits)");
2782 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2783 mips_isa
< 3 ? "lw" : "ld",
2784 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2785 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2786 p
= frag_var (rs_machine_dependent
, 4, 0,
2787 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2788 offset_expr
.X_add_symbol
, (long) 0,
2790 macro_build (p
, &icnt
, &offset_expr
,
2791 mips_isa
< 3 ? "addiu" : "daddiu",
2792 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2794 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2795 mips_isa
< 3 ? "addu" : "daddu",
2796 "d,v,t", tempreg
, tempreg
, breg
);
2797 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2798 (int) BFD_RELOC_LO16
, tempreg
);
2808 load_register (&icnt
, treg
, &imm_expr
);
2814 assert (offset_expr
.X_op
== O_symbol
2815 && strcmp (segment_name (S_GET_SEGMENT
2816 (offset_expr
.X_add_symbol
)),
2818 && offset_expr
.X_add_number
== 0);
2819 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2820 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2824 assert (imm_expr
.X_op
== O_constant
);
2825 load_register (&icnt
, treg
, &imm_expr
);
2830 /* We know that sym is in the .rdata instruction. First we get
2831 the upper 16 bits of the address. */
2834 /* FIXME: This won't work for a 64 bit address. */
2835 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
2839 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2840 mips_isa
< 3 ? "lw" : "ld",
2841 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2843 /* Now we load the register(s). */
2845 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
2846 treg
, (int) BFD_RELOC_LO16
, AT
);
2849 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2850 treg
, (int) BFD_RELOC_LO16
, AT
);
2853 /* FIXME: How in the world do we deal with the possible
2855 offset_expr
.X_add_number
+= 4;
2856 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2857 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
2866 /* Load a floating point number from the .lit8 section. */
2867 assert (offset_expr
.X_op
== O_symbol
2868 && strcmp (segment_name (S_GET_SEGMENT
2869 (offset_expr
.X_add_symbol
)),
2871 && offset_expr
.X_add_number
== 0);
2874 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2875 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2879 r
= BFD_RELOC_MIPS_LITERAL
;
2884 /* Load the double from the .rdata section. */
2885 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2886 mips_isa
< 3 ? "lw" : "ld",
2887 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2890 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2891 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, GP
);
2900 /* Even on a big endian machine $fn comes before $fn+1. We have
2901 to adjust when loading from memory. */
2904 assert (mips_isa
< 2);
2905 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2906 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2908 /* FIXME: A possible overflow which I don't know how to deal
2910 offset_expr
.X_add_number
+= 4;
2911 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2912 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2920 * The MIPS assembler seems to check for X_add_number not
2921 * being double aligned and generating:
2924 * addiu at,at,%lo(foo+1)
2927 * But, the resulting address is the same after relocation so why
2928 * generate the extra instruction?
2975 if (offset_expr
.X_op
!= O_symbol
2976 && offset_expr
.X_op
!= O_constant
)
2978 as_bad ("expression too complex");
2979 offset_expr
.X_op
= O_constant
;
2982 /* Even on a big endian machine $fn comes before $fn+1. We have
2983 to adjust when loading from memory. We set coproc if we must
2984 load $fn+1 first. */
2985 if (byte_order
== LITTLE_ENDIAN
)
2989 || offset_expr
.X_op
== O_constant
)
2991 /* If this is a reference to a GP relative symbol, we want
2992 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2993 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
2994 If we have a base register, we use this
2996 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
2997 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
2998 If this is not a GP relative symbol, we want
2999 lui $at,<sym> (BFD_RELOC_HI16_S)
3000 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3001 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3002 If there is a base register, we add it to $at after the
3003 lui instruction. If there is a constant, we always use
3005 if (offset_expr
.X_add_number
!= 0)
3024 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3025 mips_isa
< 3 ? "addu" : "daddu",
3026 "d,v,t", AT
, breg
, GP
);
3032 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3033 coproc
? treg
+ 1 : treg
,
3034 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3035 offset_expr
.X_add_number
+= 4;
3036 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3037 coproc
? treg
: treg
+ 1,
3038 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3039 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3040 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3041 used_at
&& mips_noat
),
3042 offset_expr
.X_add_symbol
, (long) 0,
3045 /* We just generated two relocs. When tc_gen_reloc
3046 handles this case, it will skip the first reloc and
3047 handle the second. The second reloc already has an
3048 extra addend of 4, which we added above. We must
3049 subtract it out, and then subtract another 4 to make
3050 the first reloc come out right. The second reloc
3051 will come out right because we are going to add 4 to
3052 offset_expr when we build its instruction below. */
3053 offset_expr
.X_add_number
-= 8;
3054 offset_expr
.X_op
= O_constant
;
3056 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3061 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3062 mips_isa
< 3 ? "addu" : "daddu",
3063 "d,v,t", AT
, breg
, AT
);
3067 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3068 coproc
? treg
+ 1 : treg
,
3069 (int) BFD_RELOC_LO16
, AT
);
3072 /* FIXME: How do we handle overflow here? */
3073 offset_expr
.X_add_number
+= 4;
3074 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3075 coproc
? treg
: treg
+ 1,
3076 (int) BFD_RELOC_LO16
, AT
);
3082 /* If this is a reference to an external symbol, we want
3083 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3088 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3090 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3091 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3092 If there is a base register we add it to $at before the
3093 lwc1 instructions. If there is a constant we include it
3094 in the lwc1 instructions. */
3096 expr1
.X_add_number
= offset_expr
.X_add_number
;
3097 offset_expr
.X_add_number
= 0;
3098 if (expr1
.X_add_number
< -0x8000
3099 || expr1
.X_add_number
>= 0x8000 - 4)
3100 as_bad ("PIC code offset overflow (max 16 signed bits)");
3105 frag_grow (16 + off
);
3106 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3107 mips_isa
< 3 ? "lw" : "ld",
3108 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3109 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3111 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3112 mips_isa
< 3 ? "addu" : "daddu",
3113 "d,v,t", AT
, breg
, AT
);
3114 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3115 coproc
? treg
+ 1 : treg
,
3116 (int) BFD_RELOC_LO16
, AT
);
3117 expr1
.X_add_number
+= 4;
3118 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3119 coproc
? treg
: treg
+ 1,
3120 (int) BFD_RELOC_LO16
, AT
);
3121 (void) frag_var (rs_machine_dependent
, 0, 0,
3122 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3123 offset_expr
.X_add_symbol
, (long) 0,
3138 assert (mips_isa
< 3);
3139 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3140 (int) BFD_RELOC_LO16
, breg
);
3141 offset_expr
.X_add_number
+= 4;
3142 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3143 (int) BFD_RELOC_LO16
, breg
);
3145 #ifdef LOSING_COMPILER
3151 as_warn ("Macro used $at after \".set noat\"");
3156 struct mips_cl_insn
*ip
;
3158 register int treg
, sreg
, dreg
, breg
;
3171 bfd_reloc_code_real_type r
;
3174 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3175 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3176 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3177 mask
= ip
->insn_mo
->mask
;
3179 expr1
.X_op
= O_constant
;
3180 expr1
.X_op_symbol
= NULL
;
3181 expr1
.X_add_symbol
= NULL
;
3182 expr1
.X_add_number
= 1;
3186 #endif /* LOSING_COMPILER */
3191 macro_build ((char *) NULL
, &icnt
, NULL
,
3192 dbl
? "dmultu" : "multu",
3194 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3200 /* The MIPS assembler some times generates shifts and adds. I'm
3201 not trying to be that fancy. GCC should do this for us
3203 load_register (&icnt
, AT
, &imm_expr
);
3204 macro_build ((char *) NULL
, &icnt
, NULL
,
3205 dbl
? "dmult" : "mult",
3207 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3213 mips_emit_delays ();
3215 mips_any_noreorder
= 1;
3216 macro_build ((char *) NULL
, &icnt
, NULL
,
3217 dbl
? "dmult" : "mult",
3219 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3220 macro_build ((char *) NULL
, &icnt
, NULL
,
3221 dbl
? "dsra32" : "sra",
3222 "d,w,<", dreg
, dreg
, 31);
3223 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3224 expr1
.X_add_number
= 8;
3225 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3226 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3227 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3229 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3235 mips_emit_delays ();
3237 mips_any_noreorder
= 1;
3238 macro_build ((char *) NULL
, &icnt
, NULL
,
3239 dbl
? "dmultu" : "multu",
3241 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3242 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3243 expr1
.X_add_number
= 8;
3244 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3245 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3246 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3251 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3252 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3253 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3255 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3259 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3260 imm_expr
.X_add_number
& 0x1f);
3261 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3262 (0 - imm_expr
.X_add_number
) & 0x1f);
3263 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3267 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3268 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3269 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3271 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3275 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3276 imm_expr
.X_add_number
& 0x1f);
3277 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3278 (0 - imm_expr
.X_add_number
) & 0x1f);
3279 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3283 assert (mips_isa
< 2);
3284 /* Even on a big endian machine $fn comes before $fn+1. We have
3285 to adjust when storing to memory. */
3286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3287 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3288 (int) BFD_RELOC_LO16
, breg
);
3289 offset_expr
.X_add_number
+= 4;
3290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3291 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3292 (int) BFD_RELOC_LO16
, breg
);
3297 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3298 treg
, (int) BFD_RELOC_LO16
);
3300 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3301 sreg
, (int) BFD_RELOC_LO16
);
3304 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3306 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3307 dreg
, (int) BFD_RELOC_LO16
);
3312 if (imm_expr
.X_add_number
== 0)
3314 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3315 sreg
, (int) BFD_RELOC_LO16
);
3320 as_warn ("Instruction %s: result is always false",
3322 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3325 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3327 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3328 sreg
, (int) BFD_RELOC_LO16
);
3331 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3333 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3334 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3335 mips_isa
< 3 ? "addiu" : "daddiu",
3336 "t,r,j", dreg
, sreg
,
3337 (int) BFD_RELOC_LO16
);
3342 load_register (&icnt
, AT
, &imm_expr
);
3343 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3347 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3348 (int) BFD_RELOC_LO16
);
3353 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3359 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3360 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3361 (int) BFD_RELOC_LO16
);
3364 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3366 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3368 macro_build ((char *) NULL
, &icnt
, &expr1
,
3369 mask
== M_SGE_I
? "slti" : "sltiu",
3370 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3375 load_register (&icnt
, AT
, &imm_expr
);
3376 macro_build ((char *) NULL
, &icnt
, NULL
,
3377 mask
== M_SGE_I
? "slt" : "sltu",
3378 "d,v,t", dreg
, sreg
, AT
);
3381 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3382 (int) BFD_RELOC_LO16
);
3387 case M_SGT
: /* sreg > treg <==> treg < sreg */
3393 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3396 case M_SGT_I
: /* sreg > I <==> I < sreg */
3402 load_register (&icnt
, AT
, &imm_expr
);
3403 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3406 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3412 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3413 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3414 (int) BFD_RELOC_LO16
);
3417 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3423 load_register (&icnt
, AT
, &imm_expr
);
3424 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3425 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3426 (int) BFD_RELOC_LO16
);
3430 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3432 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3433 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3436 load_register (&icnt
, AT
, &imm_expr
);
3437 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3441 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3443 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3444 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3447 load_register (&icnt
, AT
, &imm_expr
);
3448 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3454 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3457 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3461 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3463 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3469 if (imm_expr
.X_add_number
== 0)
3471 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3477 as_warn ("Instruction %s: result is always true",
3479 macro_build ((char *) NULL
, &icnt
, &expr1
,
3480 mips_isa
< 3 ? "addiu" : "daddiu",
3481 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3484 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3486 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3487 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3490 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3492 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3493 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3494 mips_isa
< 3 ? "addiu" : "daddiu",
3495 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3500 load_register (&icnt
, AT
, &imm_expr
);
3501 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3505 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3513 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3515 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3516 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3517 dbl
? "daddi" : "addi",
3518 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3521 load_register (&icnt
, AT
, &imm_expr
);
3522 macro_build ((char *) NULL
, &icnt
, NULL
,
3523 dbl
? "dsub" : "sub",
3524 "d,v,t", dreg
, sreg
, AT
);
3530 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3532 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3533 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3534 dbl
? "daddiu" : "addiu",
3535 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3538 load_register (&icnt
, AT
, &imm_expr
);
3539 macro_build ((char *) NULL
, &icnt
, NULL
,
3540 dbl
? "dsubu" : "subu",
3541 "d,v,t", dreg
, sreg
, AT
);
3562 load_register (&icnt
, AT
, &imm_expr
);
3563 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3568 assert (mips_isa
< 2);
3569 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3570 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3573 * Is the double cfc1 instruction a bug in the mips assembler;
3574 * or is there a reason for it?
3576 mips_emit_delays ();
3578 mips_any_noreorder
= 1;
3579 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3580 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3581 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3582 expr1
.X_add_number
= 3;
3583 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3584 (int) BFD_RELOC_LO16
);
3585 expr1
.X_add_number
= 2;
3586 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3587 (int) BFD_RELOC_LO16
);
3588 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3589 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3590 macro_build ((char *) NULL
, &icnt
, NULL
,
3591 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3592 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3593 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3603 /* avoid load delay */
3604 offset_expr
.X_add_number
+= 1;
3605 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3606 (int) BFD_RELOC_LO16
, breg
);
3607 offset_expr
.X_add_number
-= 1;
3608 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3609 (int) BFD_RELOC_LO16
, breg
);
3610 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3611 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3615 /* does this work on a big endian machine? */
3616 offset_expr
.X_add_number
+= 3;
3617 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3618 (int) BFD_RELOC_LO16
, breg
);
3619 offset_expr
.X_add_number
-= 3;
3620 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3621 (int) BFD_RELOC_LO16
, breg
);
3627 load_address (&icnt
, AT
, &offset_expr
);
3628 if (mask
== M_ULW_A
)
3630 expr1
.X_add_number
= 3;
3631 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3632 (int) BFD_RELOC_LO16
, AT
);
3633 expr1
.X_add_number
= 0;
3634 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3635 (int) BFD_RELOC_LO16
, AT
);
3639 macro_build ((char *) NULL
, &icnt
, &expr1
,
3640 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3641 (int) BFD_RELOC_LO16
, AT
);
3642 expr1
.X_add_number
= 0;
3643 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3644 (int) BFD_RELOC_LO16
, AT
);
3645 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3647 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3653 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3654 (int) BFD_RELOC_LO16
, breg
);
3655 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3656 offset_expr
.X_add_number
+= 1;
3657 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3658 (int) BFD_RELOC_LO16
, breg
);
3662 offset_expr
.X_add_number
+= 3;
3663 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3664 (int) BFD_RELOC_LO16
, breg
);
3665 offset_expr
.X_add_number
-= 3;
3666 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3667 (int) BFD_RELOC_LO16
, breg
);
3672 load_address (&icnt
, AT
, &offset_expr
);
3673 if (mask
== M_USW_A
)
3675 expr1
.X_add_number
= 3;
3676 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3677 (int) BFD_RELOC_LO16
, AT
);
3678 expr1
.X_add_number
= 0;
3679 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3680 (int) BFD_RELOC_LO16
, AT
);
3684 expr1
.X_add_number
= 0;
3685 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3686 (int) BFD_RELOC_LO16
, AT
);
3687 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
3689 expr1
.X_add_number
= 1;
3690 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3691 (int) BFD_RELOC_LO16
, AT
);
3692 expr1
.X_add_number
= 0;
3693 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3694 (int) BFD_RELOC_LO16
, AT
);
3695 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3697 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3703 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
3707 as_warn ("Macro used $at after \".set noat\"");
3712 This routine assembles an instruction into its binary format. As a side
3713 effect it sets one of the global variables imm_reloc or offset_reloc to the
3714 type of relocation to do if one of the operands is an address expression.
3719 struct mips_cl_insn
*ip
;
3724 struct mips_opcode
*insn
;
3727 unsigned int lastregno
= 0;
3732 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
3744 as_warn ("Unknown opcode: `%s'", str
);
3747 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
3749 as_warn ("`%s' not in hash table.", str
);
3750 insn_error
= "ERROR: Unrecognized opcode";
3758 assert (strcmp (insn
->name
, str
) == 0);
3760 if (insn
->pinfo
== INSN_MACRO
)
3761 insn_isa
= insn
->match
;
3762 else if (insn
->pinfo
& INSN_ISA2
)
3764 else if (insn
->pinfo
& INSN_ISA3
)
3769 if (insn_isa
> mips_isa
)
3771 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
3772 && strcmp (insn
->name
, insn
[1].name
) == 0)
3777 insn_error
= "ERROR: instruction not supported on this processor";
3782 ip
->insn_opcode
= insn
->match
;
3783 for (args
= insn
->args
;; ++args
)
3789 case '\0': /* end of args */
3802 ip
->insn_opcode
|= lastregno
<< 21;
3807 ip
->insn_opcode
|= lastregno
<< 16;
3811 ip
->insn_opcode
|= lastregno
<< 11;
3817 /* handle optional base register.
3818 Either the base register is omitted or
3819 we must have a left paren. */
3820 /* this is dependent on the next operand specifier
3821 is a 'b' for base register */
3822 assert (args
[1] == 'b');
3826 case ')': /* these must match exactly */
3831 case '<': /* must be at least one digit */
3833 * According to the manual, if the shift amount is greater
3834 * than 31 or less than 0 the the shift amount should be
3835 * mod 32. In reality the mips assembler issues an error.
3836 * We issue a warning and mask out all but the low 5 bits.
3838 my_getExpression (&imm_expr
, s
);
3839 check_absolute_expr (ip
, &imm_expr
);
3840 if ((unsigned long) imm_expr
.X_add_number
> 31)
3842 as_warn ("Improper shift amount (%ld)",
3843 (long) imm_expr
.X_add_number
);
3844 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
3846 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3847 imm_expr
.X_op
= O_absent
;
3851 case '>': /* shift amount minus 32 */
3852 my_getExpression (&imm_expr
, s
);
3853 check_absolute_expr (ip
, &imm_expr
);
3854 if ((unsigned long) imm_expr
.X_add_number
< 32
3855 || (unsigned long) imm_expr
.X_add_number
> 63)
3857 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
3858 imm_expr
.X_op
= O_absent
;
3862 case 'k': /* cache code */
3863 my_getExpression (&imm_expr
, s
);
3864 check_absolute_expr (ip
, &imm_expr
);
3865 if ((unsigned long) imm_expr
.X_add_number
> 31)
3867 as_warn ("Invalid cahce opcode (%lu)",
3868 (unsigned long) imm_expr
.X_add_number
);
3869 imm_expr
.X_add_number
&= 0x1f;
3871 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
3872 imm_expr
.X_op
= O_absent
;
3876 case 'c': /* break code */
3877 my_getExpression (&imm_expr
, s
);
3878 check_absolute_expr (ip
, &imm_expr
);
3879 if ((unsigned) imm_expr
.X_add_number
> 1023)
3880 as_warn ("Illegal break code (%ld)",
3881 (long) imm_expr
.X_add_number
);
3882 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
3883 imm_expr
.X_op
= O_absent
;
3887 case 'B': /* syscall code */
3888 my_getExpression (&imm_expr
, s
);
3889 check_absolute_expr (ip
, &imm_expr
);
3890 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
3891 as_warn ("Illegal syscall code (%ld)",
3892 (long) imm_expr
.X_add_number
);
3893 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3894 imm_expr
.X_op
= O_absent
;
3898 case 'C': /* Coprocessor code */
3899 my_getExpression (&imm_expr
, s
);
3900 check_absolute_expr (ip
, &imm_expr
);
3901 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
3903 as_warn ("Coproccesor code > 25 bits (%ld)",
3904 (long) imm_expr
.X_add_number
);
3905 imm_expr
.X_add_number
&= ((1<<25) - 1);
3907 ip
->insn_opcode
|= imm_expr
.X_add_number
;
3908 imm_expr
.X_op
= O_absent
;
3912 case 'b': /* base register */
3913 case 'd': /* destination register */
3914 case 's': /* source register */
3915 case 't': /* target register */
3916 case 'r': /* both target and source */
3917 case 'v': /* both dest and source */
3918 case 'w': /* both dest and target */
3919 case 'E': /* coprocessor target register */
3920 case 'G': /* coprocessor destination register */
3921 case 'x': /* ignore register name */
3922 case 'z': /* must be zero register */
3936 while (isdigit (*s
));
3938 as_bad ("Invalid register number (%d)", regno
);
3940 else if (*args
== 'E' || *args
== 'G')
3944 if (s
[1] == 'f' && s
[2] == 'p')
3949 else if (s
[1] == 's' && s
[2] == 'p')
3954 else if (s
[1] == 'g' && s
[2] == 'p')
3959 else if (s
[1] == 'a' && s
[2] == 't')
3967 if (regno
== AT
&& ! mips_noat
)
3968 as_warn ("Used $at without \".set noat\"");
3974 if (c
== 'r' || c
== 'v' || c
== 'w')
3981 /* 'z' only matches $0. */
3982 if (c
== 'z' && regno
!= 0)
3990 ip
->insn_opcode
|= regno
<< 21;
3994 ip
->insn_opcode
|= regno
<< 11;
3999 ip
->insn_opcode
|= regno
<< 16;
4002 /* This case exists because on the r3000 trunc
4003 expands into a macro which requires a gp
4004 register. On the r6000 or r4000 it is
4005 assembled into a single instruction which
4006 ignores the register. Thus the insn version
4007 is MIPS_ISA2 and uses 'x', and the macro
4008 version is MIPS_ISA1 and uses 't'. */
4011 /* This case is for the div instruction, which
4012 acts differently if the destination argument
4013 is $0. This only matches $0, and is checked
4014 outside the switch. */
4025 ip
->insn_opcode
|= lastregno
<< 21;
4028 ip
->insn_opcode
|= lastregno
<< 16;
4033 case 'D': /* floating point destination register */
4034 case 'S': /* floating point source register */
4035 case 'T': /* floating point target register */
4039 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4049 while (isdigit (*s
));
4052 as_bad ("Invalid float register number (%d)", regno
);
4054 if ((regno
& 1) != 0
4056 && ! (strcmp (str
, "mtc1") == 0 ||
4057 strcmp (str
, "mfc1") == 0 ||
4058 strcmp (str
, "lwc1") == 0 ||
4059 strcmp (str
, "swc1") == 0))
4060 as_warn ("Float register should be even, was %d",
4068 if (c
== 'V' || c
== 'W')
4078 ip
->insn_opcode
|= regno
<< 6;
4082 ip
->insn_opcode
|= regno
<< 11;
4086 ip
->insn_opcode
|= regno
<< 16;
4094 ip
->insn_opcode
|= lastregno
<< 11;
4097 ip
->insn_opcode
|= lastregno
<< 16;
4103 my_getExpression (&imm_expr
, s
);
4104 check_absolute_expr (ip
, &imm_expr
);
4109 my_getExpression (&offset_expr
, s
);
4110 imm_reloc
= BFD_RELOC_32
;
4122 unsigned char temp
[8];
4124 unsigned int length
;
4129 /* These only appear as the last operand in an
4130 instruction, and every instruction that accepts
4131 them in any variant accepts them in all variants.
4132 This means we don't have to worry about backing out
4133 any changes if the instruction does not match.
4135 The difference between them is the size of the
4136 floating point constant and where it goes. For 'F'
4137 and 'L' the constant is 64 bits; for 'f' and 'l' it
4138 is 32 bits. Where the constant is placed is based
4139 on how the MIPS assembler does things:
4142 f -- immediate value
4145 When generating PIC code, we do not use the .lit8
4146 or .lit4 sections at all, in order to reserve the
4147 entire global offset table. */
4149 f64
= *args
== 'F' || *args
== 'L';
4151 save_in
= input_line_pointer
;
4152 input_line_pointer
= s
;
4153 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4155 s
= input_line_pointer
;
4156 input_line_pointer
= save_in
;
4157 if (err
!= NULL
&& *err
!= '\0')
4159 as_bad ("Bad floating point constant: %s", err
);
4160 memset (temp
, '\0', sizeof temp
);
4161 length
= f64
? 8 : 4;
4164 assert (length
== (f64
? 8 : 4));
4167 || (mips_pic
!= 0 && *args
== 'l'))
4169 imm_expr
.X_op
= O_constant
;
4170 if (byte_order
== LITTLE_ENDIAN
)
4171 imm_expr
.X_add_number
=
4172 (((((((int) temp
[3] << 8)
4177 imm_expr
.X_add_number
=
4178 (((((((int) temp
[0] << 8)
4185 const char *newname
;
4188 /* Switch to the right section. */
4190 subseg
= now_subseg
;
4193 default: /* unused default case avoids warnings. */
4195 newname
= (mips_pic
== 0 ? ".lit8" : ".rdata");
4201 assert (mips_pic
== 0);
4205 new_seg
= subseg_new (newname
, (subsegT
) 0);
4207 bfd_set_section_alignment (stdoutput
, new_seg
, 4);
4210 as_bad ("Can't use floating point insn in this section");
4212 /* Set the argument to the current address in the
4214 offset_expr
.X_op
= O_symbol
;
4215 offset_expr
.X_add_symbol
=
4216 symbol_new ("L0\001", now_seg
,
4217 (valueT
) frag_now_fix (), frag_now
);
4218 offset_expr
.X_add_number
= 0;
4220 /* Put the floating point number into the section. */
4221 p
= frag_more ((int) length
);
4222 memcpy (p
, temp
, length
);
4224 /* Switch back to the original section. */
4225 subseg_set (seg
, subseg
);
4230 case 'i': /* 16 bit unsigned immediate */
4231 case 'j': /* 16 bit signed immediate */
4232 imm_reloc
= BFD_RELOC_LO16
;
4233 c
= my_getSmallExpression (&imm_expr
, s
);
4238 if (imm_expr
.X_op
== O_constant
)
4239 imm_expr
.X_add_number
=
4240 (imm_expr
.X_add_number
>> 16) & 0xffff;
4242 imm_reloc
= BFD_RELOC_HI16_S
;
4244 imm_reloc
= BFD_RELOC_HI16
;
4248 check_absolute_expr (ip
, &imm_expr
);
4251 if (imm_expr
.X_add_number
< 0
4252 || imm_expr
.X_add_number
>= 0x10000)
4254 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4255 !strcmp (insn
->name
, insn
[1].name
))
4257 as_bad ("16 bit expression not in range 0..65535");
4262 if (imm_expr
.X_add_number
< -0x8000 ||
4263 imm_expr
.X_add_number
>= 0x8000)
4265 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4266 !strcmp (insn
->name
, insn
[1].name
))
4268 as_bad ("16 bit expression not in range -32768..32767");
4274 case 'o': /* 16 bit offset */
4275 c
= my_getSmallExpression (&offset_expr
, s
);
4277 * If this value won't fit into a 16 bit offset, then
4278 * go find a macro that will generate the 32 bit offset
4281 if (offset_expr
.X_op
!= O_constant
4282 || offset_expr
.X_add_number
>= 0x8000
4283 || offset_expr
.X_add_number
< -0x8000)
4286 offset_reloc
= BFD_RELOC_LO16
;
4287 if (c
== 'h' || c
== 'H')
4289 assert (offset_expr
.X_op
== O_constant
);
4290 offset_expr
.X_add_number
=
4291 (offset_expr
.X_add_number
>> 16) & 0xffff;
4296 case 'p': /* pc relative offset */
4297 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4298 my_getExpression (&offset_expr
, s
);
4302 case 'u': /* upper 16 bits */
4303 c
= my_getSmallExpression (&imm_expr
, s
);
4304 if (imm_expr
.X_op
!= O_constant
4305 || imm_expr
.X_add_number
< 0
4306 || imm_expr
.X_add_number
>= 0x10000)
4307 as_bad ("lui expression not in range 0..65535");
4308 imm_reloc
= BFD_RELOC_LO16
;
4313 if (imm_expr
.X_op
== O_constant
)
4314 imm_expr
.X_add_number
=
4315 (imm_expr
.X_add_number
>> 16) & 0xffff;
4317 imm_reloc
= BFD_RELOC_HI16_S
;
4319 imm_reloc
= BFD_RELOC_HI16
;
4325 case 'a': /* 26 bit address */
4326 my_getExpression (&offset_expr
, s
);
4328 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4332 fprintf (stderr
, "bad char = '%c'\n", *args
);
4337 /* Args don't match. */
4338 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4339 !strcmp (insn
->name
, insn
[1].name
))
4345 insn_error
= "ERROR: Illegal operands";
4354 my_getSmallExpression (ep
, str
)
4365 ((str
[1] == 'h' && str
[2] == 'i')
4366 || (str
[1] == 'H' && str
[2] == 'I')
4367 || (str
[1] == 'l' && str
[2] == 'o'))
4379 * A small expression may be followed by a base register.
4380 * Scan to the end of this operand, and then back over a possible
4381 * base register. Then scan the small expression up to that
4382 * point. (Based on code in sparc.c...)
4384 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4386 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4388 if (isdigit (sp
[-2]))
4390 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4392 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4398 else if (sp
- 5 >= str
4401 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4402 || (sp
[-3] == 's' && sp
[-2] == 'p')
4403 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4404 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4410 /* no expression means zero offset */
4413 /* %xx(reg) is an error */
4414 ep
->X_op
= O_absent
;
4419 ep
->X_op
= O_constant
;
4422 ep
->X_add_symbol
= NULL
;
4423 ep
->X_op_symbol
= NULL
;
4424 ep
->X_add_number
= 0;
4429 my_getExpression (ep
, str
);
4436 my_getExpression (ep
, str
);
4437 return c
; /* => %hi or %lo encountered */
4441 my_getExpression (ep
, str
)
4447 save_in
= input_line_pointer
;
4448 input_line_pointer
= str
;
4450 expr_end
= input_line_pointer
;
4451 input_line_pointer
= save_in
;
4454 /* Turn a string in input_line_pointer into a floating point constant
4455 of type type, and store the appropriate bytes in *litP. The number
4456 of LITTLENUMS emitted is stored in *sizeP . An error message is
4457 returned, or NULL on OK. */
4460 md_atof (type
, litP
, sizeP
)
4466 LITTLENUM_TYPE words
[4];
4482 return "bad call to md_atof";
4485 t
= atof_ieee (input_line_pointer
, type
, words
);
4487 input_line_pointer
= t
;
4491 if (byte_order
== LITTLE_ENDIAN
)
4493 for (i
= prec
- 1; i
>= 0; i
--)
4495 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4501 for (i
= 0; i
< prec
; i
++)
4503 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4512 md_number_to_chars (buf
, val
, n
)
4520 number_to_chars_littleendian (buf
, val
, n
);
4524 number_to_chars_bigendian (buf
, val
, n
);
4533 md_parse_option (argP
, cntP
, vecP
)
4538 /* Accept -nocpp but ignore it. */
4539 if (strcmp (*argP
, "nocpp") == 0)
4545 if (strcmp (*argP
, "EL") == 0
4546 || strcmp (*argP
, "EB") == 0)
4548 if ((*argP
)[1] == 'B')
4549 byte_order
= BIG_ENDIAN
;
4551 byte_order
= LITTLE_ENDIAN
;
4554 if ((*argP
)[1] == 'B')
4555 mips_target_format
= "a.out-mips-big";
4557 mips_target_format
= "a.out-mips-little";
4560 if ((*argP
)[1] == 'B')
4561 mips_target_format
= "ecoff-bigmips";
4563 mips_target_format
= "ecoff-littlemips";
4566 if ((*argP
)[1] == 'B')
4567 mips_target_format
= "elf32-bigmips";
4569 mips_target_format
= "elf32-littlemips";
4572 /* FIXME: This breaks -L -EL. */
4580 if ((*argP
)[1] == '0')
4589 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
4594 if (strncmp (*argP
, "mips", 4) == 0)
4596 mips_isa
= atol (*argP
+ 4);
4599 else if (mips_isa
< 1 || mips_isa
> 3)
4601 as_bad ("-mips%d not supported", mips_isa
);
4608 if (strncmp (*argP
, "mcpu=", 5) == 0)
4612 /* Identify the processor type */
4614 if (strcmp (p
, "default") == 0
4615 || strcmp (p
, "DEFAULT") == 0)
4619 if (*p
== 'r' || *p
== 'R')
4626 if (strcmp (p
, "2000") == 0
4627 || strcmp (p
, "2k") == 0
4628 || strcmp (p
, "2K") == 0)
4633 if (strcmp (p
, "3000") == 0
4634 || strcmp (p
, "3k") == 0
4635 || strcmp (p
, "3K") == 0)
4640 if (strcmp (p
, "4000") == 0
4641 || strcmp (p
, "4k") == 0
4642 || strcmp (p
, "4K") == 0)
4647 if (strcmp (p
, "6000") == 0
4648 || strcmp (p
, "6k") == 0
4649 || strcmp (p
, "6K") == 0)
4656 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
4669 if ((*argP
)[1] != '\0')
4670 g_switch_value
= atoi (*argP
+ 1);
4673 **vecP
= (char *) NULL
;
4676 g_switch_value
= atoi (**vecP
);
4679 as_warn ("Number expected after -G");
4685 return 1; /* pretend you parsed the character */
4689 md_pcrel_from (fixP
)
4692 /* return the address of the delay slot */
4693 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4696 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4697 reloc for a cons. We could use the definition there, except that
4698 we want to handle 64 bit relocs specially. */
4701 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
4704 unsigned int nbytes
;
4707 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
4709 FIXME: There is no way to select anything but 32 bit mode right
4713 if (byte_order
== BIG_ENDIAN
)
4718 if (nbytes
!= 2 && nbytes
!= 4)
4719 as_bad ("Unsupported reloc size %d", nbytes
);
4721 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
4722 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
4726 md_apply_fix (fixP
, valueP
)
4733 assert (fixP
->fx_size
== 4);
4736 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
4738 switch (fixP
->fx_r_type
)
4741 case BFD_RELOC_MIPS_JMP
:
4742 case BFD_RELOC_HI16
:
4743 case BFD_RELOC_HI16_S
:
4744 case BFD_RELOC_LO16
:
4745 case BFD_RELOC_MIPS_GPREL
:
4746 case BFD_RELOC_MIPS_LITERAL
:
4747 case BFD_RELOC_MIPS_CALL16
:
4748 case BFD_RELOC_MIPS_GOT16
:
4749 case BFD_RELOC_MIPS_GPREL32
:
4750 /* Nothing needed to do. The value comes from the reloc entry */
4753 case BFD_RELOC_16_PCREL_S2
:
4755 * We need to save the bits in the instruction since fixup_segment()
4756 * might be deleting the relocation entry (i.e., a branch within
4757 * the current segment).
4760 as_warn ("Branch to odd address (%lx)", value
);
4762 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
4763 as_bad ("Relocation overflow");
4765 /* update old instruction data */
4766 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
4770 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
4774 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
4781 insn
|= value
& 0xFFFF;
4782 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
4796 const struct mips_opcode
*p
;
4797 int treg
, sreg
, dreg
, shamt
;
4802 for (i
= 0; i
< NUMOPCODES
; ++i
)
4804 p
= &mips_opcodes
[i
];
4805 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
4807 printf ("%08lx %s\t", oc
, p
->name
);
4808 treg
= (oc
>> 16) & 0x1f;
4809 sreg
= (oc
>> 21) & 0x1f;
4810 dreg
= (oc
>> 11) & 0x1f;
4811 shamt
= (oc
>> 6) & 0x1f;
4813 for (args
= p
->args
;; ++args
)
4824 printf ("%c", *args
);
4828 assert (treg
== sreg
);
4829 printf ("$%d,$%d", treg
, sreg
);
4834 printf ("$%d", dreg
);
4839 printf ("$%d", treg
);
4843 printf ("0x%x", treg
);
4848 printf ("$%d", sreg
);
4852 printf ("0x%08lx", oc
& 0x1ffffff);
4864 printf ("$%d", shamt
);
4875 printf ("%08lx UNDEFINED\n", oc
);
4886 name
= input_line_pointer
;
4887 c
= get_symbol_end ();
4888 p
= (symbolS
*) symbol_find_or_make (name
);
4889 *input_line_pointer
= c
;
4893 /* Align the current frag to a given power of two. The MIPS assembler
4894 also automatically adjusts any preceding label. */
4897 mips_align (to
, fill
)
4901 mips_emit_delays ();
4902 frag_align (to
, fill
);
4903 record_alignment (now_seg
, to
);
4904 if (insn_label
!= NULL
)
4906 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
4907 insn_label
->sy_frag
= frag_now
;
4908 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
4913 /* Align to a given power of two. .align 0 turns off the automatic
4914 alignment used by the data creating pseudo-ops. */
4921 register long temp_fill
;
4922 long max_alignment
= 15;
4926 o Note that the assembler pulls down any immediately preceeding label
4927 to the aligned address.
4928 o It's not documented but auto alignment is reinstated by
4929 a .align pseudo instruction.
4930 o Note also that after auto alignment is turned off the mips assembler
4931 issues an error on attempt to assemble an improperly aligned data item.
4936 temp
= get_absolute_expression ();
4937 if (temp
> max_alignment
)
4938 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
4941 as_warn ("Alignment negative: 0 assumed.");
4944 if (*input_line_pointer
== ',')
4946 input_line_pointer
++;
4947 temp_fill
= get_absolute_expression ();
4954 mips_align (temp
, (int) temp_fill
);
4961 demand_empty_rest_of_line ();
4964 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4965 that there was a previous instruction. */
4968 s_stringer (append_zero
)
4971 mips_emit_delays ();
4973 stringer (append_zero
);
4984 mips_emit_delays ();
4994 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4995 demand_empty_rest_of_line ();
5000 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
5001 demand_empty_rest_of_line ();
5003 #else /* ! defined (OBJ_ECOFF) */
5005 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
5006 bfd_set_section_flags (stdoutput
, seg
,
5012 bfd_set_section_alignment (stdoutput
, seg
, 4);
5013 demand_empty_rest_of_line ();
5015 #else /* ! defined (OBJ_ELF) */
5018 #endif /* ! defined (OBJ_ELF) */
5019 #endif /* ! defined (OBJ_ECOFF) */
5023 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5025 bfd_set_section_flags (stdoutput
, seg
,
5026 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5027 bfd_set_section_alignment (stdoutput
, seg
, 4);
5029 demand_empty_rest_of_line ();
5031 #else /* ! defined (GPOPT) */
5032 as_bad ("Global pointers not supported; recompile -G 0");
5033 demand_empty_rest_of_line ();
5035 #endif /* ! defined (GPOPT) */
5045 mips_emit_delays ();
5046 if (log_size
> 0 && auto_align
)
5047 mips_align (log_size
, 0);
5049 cons (1 << log_size
);
5056 as_fatal ("Encountered `.err', aborting assembly");
5066 symbolP
= get_symbol ();
5067 if (*input_line_pointer
== ',')
5068 input_line_pointer
++;
5069 size
= get_absolute_expression ();
5070 S_SET_VALUE (symbolP
, size
);
5071 S_SET_EXTERNAL (symbolP
);
5073 #ifdef ECOFF_DEBUGGING
5074 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
5075 so we use an additional ECOFF specific field. */
5076 symbolP
->ecoff_undefined
= 1;
5084 mips_emit_delays ();
5104 opt
= input_line_pointer
;
5105 c
= get_symbol_end ();
5109 /* FIXME: What does this mean? */
5111 else if (strncmp (opt
, "pic", 3) == 0)
5113 mips_pic
= atoi (opt
+ 3);
5114 /* Supposedly no other values are used. */
5115 assert (mips_pic
== 0 || mips_pic
== 2);
5118 as_warn ("Unrecognized option \"%s\"", opt
);
5120 *input_line_pointer
= c
;
5121 demand_empty_rest_of_line ();
5128 char *name
= input_line_pointer
, ch
;
5130 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5131 input_line_pointer
++;
5132 ch
= *input_line_pointer
;
5133 *input_line_pointer
= '\0';
5135 if (strcmp (name
, "reorder") == 0)
5139 prev_insn_unreordered
= 1;
5140 prev_prev_insn_unreordered
= 1;
5144 else if (strcmp (name
, "noreorder") == 0)
5146 mips_emit_delays ();
5148 mips_any_noreorder
= 1;
5150 else if (strcmp (name
, "at") == 0)
5154 else if (strcmp (name
, "noat") == 0)
5158 else if (strcmp (name
, "macro") == 0)
5160 mips_warn_about_macros
= 0;
5162 else if (strcmp (name
, "nomacro") == 0)
5164 if (mips_noreorder
== 0)
5165 as_bad ("`noreorder' must be set before `nomacro'");
5166 mips_warn_about_macros
= 1;
5168 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5172 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5176 else if (strcmp (name
, "bopt") == 0)
5180 else if (strcmp (name
, "nobopt") == 0)
5186 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5188 *input_line_pointer
= ch
;
5189 demand_empty_rest_of_line ();
5192 /* The same as the usual .space directive, except that we have to
5193 forget about any previous instruction. */
5196 s_mips_space (param
)
5199 mips_emit_delays ();
5204 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5205 .option pic2. It means to generate SVR4 PIC calls. */
5212 demand_empty_rest_of_line ();
5215 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5216 PIC code. It sets the $gp register for the function based on the
5217 function address, which is in the register named in the argument.
5218 This uses a relocation against _gp_disp, which is handled specially
5219 by the linker. The result is:
5220 lui $gp,%hi(_gp_disp)
5221 addiu $gp,$gp,%lo(_gp_disp)
5222 addu $gp,$gp,.cpload argument
5223 The .cpload argument is normally $25 == $t9. */
5232 /* If we are not generating PIC code, .cpload is ignored. */
5239 /* .cpload should be a in .set noreorder section. */
5240 if (mips_noreorder
== 0)
5241 as_warn (".cpload not in noreorder section");
5244 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5245 ex
.X_op_symbol
= NULL
;
5246 ex
.X_add_number
= 0;
5248 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5249 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5250 (int) BFD_RELOC_LO16
);
5252 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5253 GP
, GP
, tc_get_register (0));
5255 demand_empty_rest_of_line ();
5258 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5259 offset from $sp. The offset is remembered, and after making a PIC
5260 call $gp is restored from that location. */
5263 s_cprestore (ignore
)
5269 /* If we are not generating PIC code, .cprestore is ignored. */
5276 mips_cprestore_offset
= get_absolute_expression ();
5278 ex
.X_op
= O_constant
;
5279 ex
.X_add_symbol
= NULL
;
5280 ex
.X_op_symbol
= NULL
;
5281 ex
.X_add_number
= mips_cprestore_offset
;
5283 macro_build ((char *) NULL
, &icnt
, &ex
,
5284 mips_isa
< 3 ? "sw" : "sd",
5285 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5287 demand_empty_rest_of_line ();
5290 /* Handle the .gpword pseudo-op. This is used when generating PIC
5291 code. It generates a 32 bit GP relative reloc. */
5300 /* When not generating PIC code, this is treated as .word. */
5307 mips_emit_delays ();
5314 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5316 as_bad ("Unsupported use of .gpword");
5317 ignore_rest_of_line ();
5321 md_number_to_chars (p
, (valueT
) 0, 4);
5322 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5323 BFD_RELOC_MIPS_GPREL32
);
5325 demand_empty_rest_of_line ();
5328 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5329 tables in SVR4 PIC code. */
5338 /* This is ignored when not generating SVR4 PIC code. */
5345 /* Add $gp to the register named as an argument. */
5346 reg
= tc_get_register (0);
5347 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5348 mips_isa
< 3 ? "addu" : "daddu",
5349 "d,v,t", reg
, reg
, GP
);
5351 demand_empty_rest_of_line ();
5354 /* Parse a register string into a number. Called from the ECOFF code
5355 to parse .frame. The argument is non-zero if this is the frame
5356 register, so that we can record it in mips_frame_reg. */
5359 tc_get_register (frame
)
5365 if (*input_line_pointer
++ != '$')
5367 as_warn ("expected `$'");
5370 else if (isdigit ((unsigned char) *input_line_pointer
))
5372 reg
= get_absolute_expression ();
5373 if (reg
< 0 || reg
>= 32)
5375 as_warn ("Bad register number");
5381 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5383 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5385 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5387 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5391 as_warn ("Unrecognized register name");
5394 input_line_pointer
+= 2;
5397 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
5402 md_section_align (seg
, addr
)
5406 int align
= bfd_get_section_alignment (stdoutput
, seg
);
5408 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
5411 /* Estimate the size of a frag before relaxing. We are not really
5412 relaxing here, and the final size is encoded in the subtype
5417 md_estimate_size_before_relax (fragp
, segtype
)
5426 const char *symname
;
5428 /* Find out whether this symbol can be referenced off the GP
5429 register. It can be if it is smaller than the -G size or if
5430 it is in the .sdata or .sbss section. Certain symbols can
5431 not be referenced off the GP, although it appears as though
5433 symname
= S_GET_NAME (fragp
->fr_symbol
);
5434 if (symname
!= (const char *) NULL
5435 && (strcmp (symname
, "eprol") == 0
5436 || strcmp (symname
, "etext") == 0
5437 || strcmp (symname
, "_gp") == 0
5438 || strcmp (symname
, "edata") == 0
5439 || strcmp (symname
, "_fbss") == 0
5440 || strcmp (symname
, "_fdata") == 0
5441 || strcmp (symname
, "_ftext") == 0
5442 || strcmp (symname
, "end") == 0
5443 || strcmp (symname
, "_gp_disp") == 0))
5445 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
5446 && S_GET_VALUE (fragp
->fr_symbol
) != 0
5447 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)
5451 const char *segname
;
5453 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
5454 assert (strcmp (segname
, ".lit8") != 0
5455 && strcmp (segname
, ".lit4") != 0);
5456 change
= (strcmp (segname
, ".sdata") != 0
5457 && strcmp (segname
, ".sbss") != 0);
5459 #else /* ! defined (GPOPT) */
5460 /* We are not optimizing for the GP register. */
5462 #endif /* ! defined (GPOPT) */
5466 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
5468 /* This must duplicate the test in adjust_reloc_syms. */
5469 change
= (symsec
!= &bfd_und_section
5470 && symsec
!= &bfd_abs_section
5471 && ! bfd_is_com_section (symsec
));
5476 /* Record the offset to the first reloc in the fr_opcode field.
5477 This lets md_convert_frag and tc_gen_reloc know that the code
5478 must be expanded. */
5479 fragp
->fr_opcode
= (fragp
->fr_literal
5481 - RELAX_OLD (fragp
->fr_subtype
)
5482 + RELAX_RELOC1 (fragp
->fr_subtype
));
5483 /* FIXME: This really needs as_warn_where. */
5484 if (RELAX_WARN (fragp
->fr_subtype
))
5485 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
5491 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
5494 /* Translate internal representation of relocation info to BFD target
5498 tc_gen_reloc (section
, fixp
)
5502 static arelent
*retval
[4];
5505 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
5508 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5509 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5510 if (fixp
->fx_pcrel
== 0)
5511 reloc
->addend
= fixp
->fx_addnumber
;
5516 reloc
->addend
= -reloc
->address
;
5519 /* If this is a variant frag, we may need to adjust the existing
5520 reloc and generate a new one. */
5521 if (fixp
->fx_frag
->fr_opcode
!= NULL
5522 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5523 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
5524 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
5528 /* If this is not the last reloc in this frag, then we have two
5529 GPREL relocs, both of which are being replaced. Let the
5530 second one handle all of them. */
5531 if (fixp
->fx_next
!= NULL
5532 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
5534 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5535 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5540 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
5541 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5542 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
5544 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5545 reloc2
->address
= (reloc
->address
5546 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
5547 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
5548 reloc2
->addend
= fixp
->fx_addnumber
;
5549 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
5550 assert (reloc2
->howto
!= NULL
);
5552 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
5556 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
5559 reloc3
->address
+= 4;
5564 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5565 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
5569 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
5571 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
5572 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
5577 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5579 if (reloc
->howto
== NULL
)
5581 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5582 "Can not represent relocation in this object file format");
5589 /* Convert a machine dependent frag. */
5592 md_convert_frag (abfd
, asec
, fragp
)
5600 if (fragp
->fr_opcode
== NULL
)
5603 old
= RELAX_OLD (fragp
->fr_subtype
);
5604 new = RELAX_NEW (fragp
->fr_subtype
);
5605 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
5608 memcpy (fixptr
- old
, fixptr
, new);
5610 fragp
->fr_fix
+= new - old
;
5613 /* This function is called whenever a label is defined. It is used
5614 when handling branch delays; if a branch has a label, we assume we
5618 mips_define_label (sym
)
5626 /* Some special processing for a MIPS ELF file. */
5629 mips_elf_final_processing ()
5633 /* Write out the .reginfo section. */
5634 s
.ri_gprmask
= mips_gprmask
;
5635 s
.ri_cprmask
[0] = mips_cprmask
[0];
5636 s
.ri_cprmask
[1] = mips_cprmask
[1];
5637 s
.ri_cprmask
[2] = mips_cprmask
[2];
5638 s
.ri_cprmask
[3] = mips_cprmask
[3];
5639 /* The gp_value field is set by the MIPS ELF backend. */
5641 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
5642 ((Elf32_External_RegInfo
*)
5643 mips_regmask_frag
));
5645 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
5646 sort of BFD interface for this. */
5647 if (mips_any_noreorder
)
5648 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
5650 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
5653 #endif /* OBJ_ELF */
5655 #ifndef ECOFF_DEBUGGING
5657 /* These functions should really be defined by the object file format,
5658 since they are related to debugging information. However, this
5659 code has to work for the a.out format, which does not define them,
5660 so we provide simple versions here. These don't actually generate
5661 any debugging information, but they do simple checking and someday
5662 somebody may make them useful. */
5666 struct loc
*loc_next
;
5667 unsigned long loc_fileno
;
5668 unsigned long loc_lineno
;
5669 unsigned long loc_offset
;
5670 unsigned short loc_delta
;
5671 unsigned short loc_count
;
5680 struct proc
*proc_next
;
5681 struct symbol
*proc_isym
;
5682 struct symbol
*proc_end
;
5683 unsigned long proc_reg_mask
;
5684 unsigned long proc_reg_offset
;
5685 unsigned long proc_fpreg_mask
;
5686 unsigned long proc_fpreg_offset
;
5687 unsigned long proc_frameoffset
;
5688 unsigned long proc_framereg
;
5689 unsigned long proc_pcreg
;
5691 struct file
*proc_file
;
5698 struct file
*file_next
;
5699 unsigned long file_fileno
;
5700 struct symbol
*file_symbol
;
5701 struct symbol
*file_end
;
5702 struct proc
*file_proc
;
5707 static struct obstack proc_frags
;
5708 static procS
*proc_lastP
;
5709 static procS
*proc_rootP
;
5710 static int numprocs
;
5715 obstack_begin (&proc_frags
, 0x2000);
5721 /* check for premature end, nesting errors, etc */
5722 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5723 as_warn ("missing `.end' at end of assembly");
5726 extern char hex_value
[];
5734 if (*input_line_pointer
== '-')
5736 ++input_line_pointer
;
5739 if (!isdigit (*input_line_pointer
))
5740 as_bad ("Expected simple number.");
5741 if (input_line_pointer
[0] == '0')
5743 if (input_line_pointer
[1] == 'x')
5745 input_line_pointer
+= 2;
5746 while (isxdigit (*input_line_pointer
))
5749 val
|= hex_value
[(int) *input_line_pointer
++];
5751 return negative
? -val
: val
;
5755 ++input_line_pointer
;
5756 while (isdigit (*input_line_pointer
))
5759 val
|= *input_line_pointer
++ - '0';
5761 return negative
? -val
: val
;
5764 if (!isdigit (*input_line_pointer
))
5766 printf (" *input_line_pointer == '%c' 0x%02x\n",
5767 *input_line_pointer
, *input_line_pointer
);
5768 as_warn ("Invalid number");
5771 while (isdigit (*input_line_pointer
))
5774 val
+= *input_line_pointer
++ - '0';
5776 return negative
? -val
: val
;
5779 /* The .file directive; just like the usual .file directive, but there
5780 is an initial number which is the ECOFF file index. */
5788 line
= get_number ();
5793 /* The .end directive. */
5801 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5804 demand_empty_rest_of_line ();
5808 if (now_seg
!= text_section
)
5809 as_warn (".end not in text section");
5812 as_warn (".end and no .ent seen yet.");
5818 assert (S_GET_NAME (p
));
5819 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
5820 as_warn (".end symbol does not match .ent symbol.");
5823 proc_lastP
->proc_end
= (symbolS
*) 1;
5826 /* The .aent and .ent directives. */
5836 symbolP
= get_symbol ();
5837 if (*input_line_pointer
== ',')
5838 input_line_pointer
++;
5840 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
5841 number
= get_number ();
5842 if (now_seg
!= text_section
)
5843 as_warn (".ent or .aent not in text section.");
5845 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5846 as_warn ("missing `.end'");
5850 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
5851 procP
->proc_isym
= symbolP
;
5852 procP
->proc_reg_mask
= 0;
5853 procP
->proc_reg_offset
= 0;
5854 procP
->proc_fpreg_mask
= 0;
5855 procP
->proc_fpreg_offset
= 0;
5856 procP
->proc_frameoffset
= 0;
5857 procP
->proc_framereg
= 0;
5858 procP
->proc_pcreg
= 0;
5859 procP
->proc_end
= NULL
;
5860 procP
->proc_next
= NULL
;
5862 proc_lastP
->proc_next
= procP
;
5868 demand_empty_rest_of_line ();
5871 /* The .frame directive. */
5884 frame_reg
= tc_get_register (1);
5885 if (*input_line_pointer
== ',')
5886 input_line_pointer
++;
5887 frame_off
= get_absolute_expression ();
5888 if (*input_line_pointer
== ',')
5889 input_line_pointer
++;
5890 pcreg
= tc_get_register (0);
5893 assert (proc_rootP
);
5894 proc_rootP
->proc_framereg
= frame_reg
;
5895 proc_rootP
->proc_frameoffset
= frame_off
;
5896 proc_rootP
->proc_pcreg
= pcreg
;
5897 /* bob macho .frame */
5899 /* We don't have to write out a frame stab for unoptimized code. */
5900 if (!(frame_reg
== FP
&& frame_off
== 0))
5903 as_warn ("No .ent for .frame to use.");
5904 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
5905 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
5906 S_SET_TYPE (symP
, N_RMASK
);
5907 S_SET_OTHER (symP
, 0);
5908 S_SET_DESC (symP
, 0);
5909 symP
->sy_forward
= proc_lastP
->proc_isym
;
5910 /* bob perhaps I should have used pseudo set */
5912 demand_empty_rest_of_line ();
5916 /* The .fmask and .mask directives. */
5923 char str
[100], *strP
;
5929 mask
= get_number ();
5930 if (*input_line_pointer
== ',')
5931 input_line_pointer
++;
5932 off
= get_absolute_expression ();
5934 /* bob only for coff */
5935 assert (proc_rootP
);
5936 if (reg_type
== 'F')
5938 proc_rootP
->proc_fpreg_mask
= mask
;
5939 proc_rootP
->proc_fpreg_offset
= off
;
5943 proc_rootP
->proc_reg_mask
= mask
;
5944 proc_rootP
->proc_reg_offset
= off
;
5947 /* bob macho .mask + .fmask */
5949 /* We don't have to write out a mask stab if no saved regs. */
5953 as_warn ("No .ent for .mask to use.");
5955 for (i
= 0; i
< 32; i
++)
5959 sprintf (strP
, "%c%d,", reg_type
, i
);
5960 strP
+= strlen (strP
);
5964 sprintf (strP
, ";%d,", off
);
5965 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
5966 S_SET_TYPE (symP
, N_RMASK
);
5967 S_SET_OTHER (symP
, 0);
5968 S_SET_DESC (symP
, 0);
5969 symP
->sy_forward
= proc_lastP
->proc_isym
;
5970 /* bob perhaps I should have used pseudo set */
5975 /* The .loc directive. */
5986 assert (now_seg
== text_section
);
5988 lineno
= get_number ();
5989 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
5991 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
5992 S_SET_TYPE (symbolP
, N_SLINE
);
5993 S_SET_OTHER (symbolP
, 0);
5994 S_SET_DESC (symbolP
, lineno
);
5995 symbolP
->sy_segment
= now_seg
;
5999 #endif /* ! defined (ECOFF_DEBUGGING) */