1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Whether we are assembling for the mips16 processor. 0 if we are
152 not, 1 if we are, and -1 if the value has not been initialized.
153 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
154 -nomips16 command line options, and the default CPU. */
156 /* Non-zero if we should not reorder instructions. Changed by `.set
157 reorder' and `.set noreorder'. */
159 /* Non-zero if we should not permit the $at ($1) register to be used
160 in instructions. Changed by `.set at' and `.set noat'. */
162 /* Non-zero if we should warn when a macro instruction expands into
163 more than one machine instruction. Changed by `.set nomacro' and
165 int warn_about_macros
;
166 /* Non-zero if we should not move instructions. Changed by `.set
167 move', `.set volatile', `.set nomove', and `.set novolatile'. */
169 /* Non-zero if we should not optimize branches by moving the target
170 of the branch into the delay slot. Actually, we don't perform
171 this optimization anyhow. Changed by `.set bopt' and `.set
174 /* Non-zero if we should not autoextend mips16 instructions.
175 Changed by `.set autoextend' and `.set noautoextend'. */
179 /* This is the struct we use to hold the current set of options. Note
180 that we must set the isa and mips16 fields to -1 to indicate that
181 they have not been initialized. */
183 static struct mips_set_options mips_opts
= { -1, -1 };
185 /* These variables are filled in with the masks of registers used.
186 The object format code reads them and puts them in the appropriate
188 unsigned long mips_gprmask
;
189 unsigned long mips_cprmask
[4];
191 /* MIPS ISA we are using for this output file. */
192 static int file_mips_isa
;
194 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
195 static int mips_cpu
= -1;
197 /* Whether the 4650 instructions (mad/madu) are permitted. */
198 static int mips_4650
= -1;
200 /* Whether the 4010 instructions are permitted. */
201 static int mips_4010
= -1;
203 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
204 static int mips_4100
= -1;
206 /* start-sanitize-r5900 */
207 /* Whether Toshiba r5900 instructions are permitted. */
208 static int mips_5900
= -1;
209 /* end-sanitize-r5900 */
211 /* Whether Toshiba r3900 instructions are permitted. */
212 static int mips_3900
= -1;
214 /* start-sanitize-tx19 */
215 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
216 The tx19 related options and configuration bits are handled by
218 /* end-sanitize-tx19 */
220 /* Whether the processor uses hardware interlocks to protect
221 reads from the HI and LO registers, and thus does not
222 require nops to be inserted. */
223 #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900)
225 /* Whether the processor uses hardware interlocks to protect reads
226 from the GPRs, and thus does not require nops to be inserted. */
227 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900)
229 /* As with other "interlocks" this is used by hardware that has FP
230 (co-processor) interlocks. */
231 /* Itbl support may require additional care here. */
232 #define cop_interlocks (mips_cpu == 4300)
234 /* MIPS PIC level. */
238 /* Do not generate PIC code. */
241 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
242 not sure what it is supposed to do. */
245 /* Generate PIC code as in the SVR4 MIPS ABI. */
248 /* Generate PIC code without using a global offset table: the data
249 segment has a maximum size of 64K, all data references are off
250 the $gp register, and all text references are PC relative. This
251 is used on some embedded systems. */
255 static enum mips_pic_level mips_pic
;
257 /* 1 if we should generate 32 bit offsets from the GP register in
258 SVR4_PIC mode. Currently has no meaning in other modes. */
259 static int mips_big_got
;
261 /* 1 if trap instructions should used for overflow rather than break
263 static int mips_trap
;
265 /* Non-zero if any .set noreorder directives were used. */
267 static int mips_any_noreorder
;
269 /* The size of the small data section. */
270 static int g_switch_value
= 8;
271 /* Whether the -G option was used. */
272 static int g_switch_seen
= 0;
277 /* If we can determine in advance that GP optimization won't be
278 possible, we can skip the relaxation stuff that tries to produce
279 GP-relative references. This makes delay slot optimization work
282 This function can only provide a guess, but it seems to work for
283 gcc output. If it guesses wrong, the only loss should be in
284 efficiency; it shouldn't introduce any bugs.
286 I don't know if a fix is needed for the SVR4_PIC mode. I've only
287 fixed it for the non-PIC mode. KR 95/04/07 */
288 static int nopic_need_relax
PARAMS ((symbolS
*, int));
290 /* handle of the OPCODE hash table */
291 static struct hash_control
*op_hash
= NULL
;
293 /* The opcode hash table we use for the mips16. */
294 static struct hash_control
*mips16_op_hash
= NULL
;
296 /* This array holds the chars that always start a comment. If the
297 pre-processor is disabled, these aren't very useful */
298 const char comment_chars
[] = "#";
300 /* This array holds the chars that only start a comment at the beginning of
301 a line. If the line seems to have the form '# 123 filename'
302 .line and .file directives will appear in the pre-processed output */
303 /* Note that input_file.c hand checks for '#' at the beginning of the
304 first line of the input file. This is because the compiler outputs
305 #NO_APP at the beginning of its output. */
306 /* Also note that C style comments are always supported. */
307 const char line_comment_chars
[] = "#";
309 /* This array holds machine specific line separator characters. */
310 const char line_separator_chars
[] = "";
312 /* Chars that can be used to separate mant from exp in floating point nums */
313 const char EXP_CHARS
[] = "eE";
315 /* Chars that mean this number is a floating point constant */
318 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
320 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
321 changed in read.c . Ideally it shouldn't have to know about it at all,
322 but nothing is ideal around here.
325 static char *insn_error
;
327 static int auto_align
= 1;
329 /* When outputting SVR4 PIC code, the assembler needs to know the
330 offset in the stack frame from which to restore the $gp register.
331 This is set by the .cprestore pseudo-op, and saved in this
333 static offsetT mips_cprestore_offset
= -1;
335 /* This is the register which holds the stack frame, as set by the
336 .frame pseudo-op. This is needed to implement .cprestore. */
337 static int mips_frame_reg
= SP
;
339 /* To output NOP instructions correctly, we need to keep information
340 about the previous two instructions. */
342 /* Whether we are optimizing. The default value of 2 means to remove
343 unneeded NOPs and swap branch instructions when possible. A value
344 of 1 means to not swap branches. A value of 0 means to always
346 static int mips_optimize
= 2;
348 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
349 equivalent to seeing no -g option at all. */
350 static int mips_debug
= 0;
352 /* The previous instruction. */
353 static struct mips_cl_insn prev_insn
;
355 /* The instruction before prev_insn. */
356 static struct mips_cl_insn prev_prev_insn
;
358 /* If we don't want information for prev_insn or prev_prev_insn, we
359 point the insn_mo field at this dummy integer. */
360 static const struct mips_opcode dummy_opcode
= { 0 };
362 /* Non-zero if prev_insn is valid. */
363 static int prev_insn_valid
;
365 /* The frag for the previous instruction. */
366 static struct frag
*prev_insn_frag
;
368 /* The offset into prev_insn_frag for the previous instruction. */
369 static long prev_insn_where
;
371 /* The reloc type for the previous instruction, if any. */
372 static bfd_reloc_code_real_type prev_insn_reloc_type
;
374 /* The reloc for the previous instruction, if any. */
375 static fixS
*prev_insn_fixp
;
377 /* Non-zero if the previous instruction was in a delay slot. */
378 static int prev_insn_is_delay_slot
;
380 /* Non-zero if the previous instruction was in a .set noreorder. */
381 static int prev_insn_unreordered
;
383 /* Non-zero if the previous instruction uses an extend opcode (if
385 static int prev_insn_extended
;
387 /* Non-zero if the previous previous instruction was in a .set
389 static int prev_prev_insn_unreordered
;
391 /* If this is set, it points to a frag holding nop instructions which
392 were inserted before the start of a noreorder section. If those
393 nops turn out to be unnecessary, the size of the frag can be
395 static fragS
*prev_nop_frag
;
397 /* The number of nop instructions we created in prev_nop_frag. */
398 static int prev_nop_frag_holds
;
400 /* The number of nop instructions that we know we need in
402 static int prev_nop_frag_required
;
404 /* The number of instructions we've seen since prev_nop_frag. */
405 static int prev_nop_frag_since
;
407 /* For ECOFF and ELF, relocations against symbols are done in two
408 parts, with a HI relocation and a LO relocation. Each relocation
409 has only 16 bits of space to store an addend. This means that in
410 order for the linker to handle carries correctly, it must be able
411 to locate both the HI and the LO relocation. This means that the
412 relocations must appear in order in the relocation table.
414 In order to implement this, we keep track of each unmatched HI
415 relocation. We then sort them so that they immediately precede the
416 corresponding LO relocation. */
421 struct mips_hi_fixup
*next
;
424 /* The section this fixup is in. */
428 /* The list of unmatched HI relocs. */
430 static struct mips_hi_fixup
*mips_hi_fixup_list
;
432 /* Map normal MIPS register numbers to mips16 register numbers. */
434 #define X ILLEGAL_REG
435 static const int mips32_to_16_reg_map
[] =
437 X
, X
, 2, 3, 4, 5, 6, 7,
438 X
, X
, X
, X
, X
, X
, X
, X
,
439 0, 1, X
, X
, X
, X
, X
, X
,
440 X
, X
, X
, X
, X
, X
, X
, X
444 /* Map mips16 register numbers to normal MIPS register numbers. */
446 static const int mips16_to_32_reg_map
[] =
448 16, 17, 2, 3, 4, 5, 6, 7
451 /* Since the MIPS does not have multiple forms of PC relative
452 instructions, we do not have to do relaxing as is done on other
453 platforms. However, we do have to handle GP relative addressing
454 correctly, which turns out to be a similar problem.
456 Every macro that refers to a symbol can occur in (at least) two
457 forms, one with GP relative addressing and one without. For
458 example, loading a global variable into a register generally uses
459 a macro instruction like this:
461 If i can be addressed off the GP register (this is true if it is in
462 the .sbss or .sdata section, or if it is known to be smaller than
463 the -G argument) this will generate the following instruction:
465 This instruction will use a GPREL reloc. If i can not be addressed
466 off the GP register, the following instruction sequence will be used:
469 In this case the first instruction will have a HI16 reloc, and the
470 second reloc will have a LO16 reloc. Both relocs will be against
473 The issue here is that we may not know whether i is GP addressable
474 until after we see the instruction that uses it. Therefore, we
475 want to be able to choose the final instruction sequence only at
476 the end of the assembly. This is similar to the way other
477 platforms choose the size of a PC relative instruction only at the
480 When generating position independent code we do not use GP
481 addressing in quite the same way, but the issue still arises as
482 external symbols and local symbols must be handled differently.
484 We handle these issues by actually generating both possible
485 instruction sequences. The longer one is put in a frag_var with
486 type rs_machine_dependent. We encode what to do with the frag in
487 the subtype field. We encode (1) the number of existing bytes to
488 replace, (2) the number of new bytes to use, (3) the offset from
489 the start of the existing bytes to the first reloc we must generate
490 (that is, the offset is applied from the start of the existing
491 bytes after they are replaced by the new bytes, if any), (4) the
492 offset from the start of the existing bytes to the second reloc,
493 (5) whether a third reloc is needed (the third reloc is always four
494 bytes after the second reloc), and (6) whether to warn if this
495 variant is used (this is sometimes needed if .set nomacro or .set
496 noat is in effect). All these numbers are reasonably small.
498 Generating two instruction sequences must be handled carefully to
499 ensure that delay slots are handled correctly. Fortunately, there
500 are a limited number of cases. When the second instruction
501 sequence is generated, append_insn is directed to maintain the
502 existing delay slot information, so it continues to apply to any
503 code after the second instruction sequence. This means that the
504 second instruction sequence must not impose any requirements not
505 required by the first instruction sequence.
507 These variant frags are then handled in functions called by the
508 machine independent code. md_estimate_size_before_relax returns
509 the final size of the frag. md_convert_frag sets up the final form
510 of the frag. tc_gen_reloc adjust the first reloc and adds a second
512 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
516 | (((reloc1) + 64) << 9) \
517 | (((reloc2) + 64) << 2) \
518 | ((reloc3) ? (1 << 1) : 0) \
520 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
521 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
522 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
523 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
524 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
525 #define RELAX_WARN(i) ((i) & 1)
527 /* For mips16 code, we use an entirely different form of relaxation.
528 mips16 supports two versions of most instructions which take
529 immediate values: a small one which takes some small value, and a
530 larger one which takes a 16 bit value. Since branches also follow
531 this pattern, relaxing these values is required.
533 We can assemble both mips16 and normal MIPS code in a single
534 object. Therefore, we need to support this type of relaxation at
535 the same time that we support the relaxation described above. We
536 use the high bit of the subtype field to distinguish these cases.
538 The information we store for this type of relaxation is the
539 argument code found in the opcode file for this relocation, whether
540 the user explicitly requested a small or extended form, and whether
541 the relocation is in a jump or jal delay slot. That tells us the
542 size of the value, and how it should be stored. We also store
543 whether the fragment is considered to be extended or not. We also
544 store whether this is known to be a branch to a different section,
545 whether we have tried to relax this frag yet, and whether we have
546 ever extended a PC relative fragment because of a shift count. */
547 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
550 | ((small) ? 0x100 : 0) \
551 | ((ext) ? 0x200 : 0) \
552 | ((dslot) ? 0x400 : 0) \
553 | ((jal_dslot) ? 0x800 : 0))
554 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
555 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
556 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
557 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
558 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
559 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
560 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
561 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
562 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
563 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
564 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
565 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
567 /* Prototypes for static functions. */
570 #define internalError() \
571 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
573 #define internalError() as_fatal ("MIPS internal Error");
576 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
578 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
579 unsigned int reg
, enum mips_regclass
class));
580 static int reg_needs_delay
PARAMS ((int));
581 static void mips16_mark_labels
PARAMS ((void));
582 static void append_insn
PARAMS ((char *place
,
583 struct mips_cl_insn
* ip
,
585 bfd_reloc_code_real_type r
,
587 static void mips_no_prev_insn
PARAMS ((int));
588 static void mips_emit_delays
PARAMS ((boolean
));
590 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
591 const char *name
, const char *fmt
,
594 static void macro_build ();
596 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
597 const char *, const char *,
599 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
600 expressionS
* ep
, int regnum
));
601 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
602 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
604 static void load_register
PARAMS ((int *, int, expressionS
*, int));
605 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
606 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
607 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
608 #ifdef LOSING_COMPILER
609 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
611 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
612 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
613 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
614 boolean
, boolean
, unsigned long *,
615 boolean
*, unsigned short *));
616 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
617 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
618 static symbolS
*get_symbol
PARAMS ((void));
619 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
620 static void s_align
PARAMS ((int));
621 static void s_change_sec
PARAMS ((int));
622 static void s_cons
PARAMS ((int));
623 static void s_float_cons
PARAMS ((int));
624 static void s_mips_globl
PARAMS ((int));
625 static void s_option
PARAMS ((int));
626 static void s_mipsset
PARAMS ((int));
627 static void s_abicalls
PARAMS ((int));
628 static void s_cpload
PARAMS ((int));
629 static void s_cprestore
PARAMS ((int));
630 static void s_gpword
PARAMS ((int));
631 static void s_cpadd
PARAMS ((int));
632 static void s_insn
PARAMS ((int));
633 static void md_obj_begin
PARAMS ((void));
634 static void md_obj_end
PARAMS ((void));
635 static long get_number
PARAMS ((void));
636 static void s_ent
PARAMS ((int));
637 static void s_mipsend
PARAMS ((int));
638 static void s_file
PARAMS ((int));
639 static void s_mips_stab
PARAMS ((int));
640 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
644 The following pseudo-ops from the Kane and Heinrich MIPS book
645 should be defined here, but are currently unsupported: .alias,
646 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
648 The following pseudo-ops from the Kane and Heinrich MIPS book are
649 specific to the type of debugging information being generated, and
650 should be defined by the object format: .aent, .begin, .bend,
651 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
654 The following pseudo-ops from the Kane and Heinrich MIPS book are
655 not MIPS CPU specific, but are also not specific to the object file
656 format. This file is probably the best place to define them, but
657 they are not currently supported: .asm0, .endr, .lab, .repeat,
658 .struct, .weakext. */
660 static const pseudo_typeS mips_pseudo_table
[] =
662 /* MIPS specific pseudo-ops. */
663 {"option", s_option
, 0},
664 {"set", s_mipsset
, 0},
665 {"rdata", s_change_sec
, 'r'},
666 {"sdata", s_change_sec
, 's'},
667 {"livereg", s_ignore
, 0},
668 {"abicalls", s_abicalls
, 0},
669 {"cpload", s_cpload
, 0},
670 {"cprestore", s_cprestore
, 0},
671 {"gpword", s_gpword
, 0},
672 {"cpadd", s_cpadd
, 0},
675 /* Relatively generic pseudo-ops that happen to be used on MIPS
677 {"asciiz", stringer
, 1},
678 {"bss", s_change_sec
, 'b'},
681 {"dword", s_cons
, 3},
683 /* These pseudo-ops are defined in read.c, but must be overridden
684 here for one reason or another. */
685 {"align", s_align
, 0},
687 {"data", s_change_sec
, 'd'},
688 {"double", s_float_cons
, 'd'},
689 {"float", s_float_cons
, 'f'},
690 {"globl", s_mips_globl
, 0},
691 {"global", s_mips_globl
, 0},
692 {"hword", s_cons
, 1},
697 {"short", s_cons
, 1},
698 {"single", s_float_cons
, 'f'},
699 {"stabn", s_mips_stab
, 'n'},
700 {"text", s_change_sec
, 't'},
705 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
706 /* These pseudo-ops should be defined by the object file format.
707 However, a.out doesn't support them, so we have versions here. */
709 {"bgnb", s_ignore
, 0},
710 {"end", s_mipsend
, 0},
711 {"endb", s_ignore
, 0},
714 {"fmask", s_ignore
, 'F'},
715 {"frame", s_ignore
, 0},
716 {"loc", s_ignore
, 0},
717 {"mask", s_ignore
, 'R'},
718 {"verstamp", s_ignore
, 0},
722 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
727 pop_insert (mips_pseudo_table
);
728 if (! ECOFF_DEBUGGING
)
729 pop_insert (mips_nonecoff_pseudo_table
);
732 /* Symbols labelling the current insn. */
734 struct insn_label_list
736 struct insn_label_list
*next
;
740 static struct insn_label_list
*insn_labels
;
741 static struct insn_label_list
*free_insn_labels
;
743 static void mips_clear_insn_labels
PARAMS ((void));
746 mips_clear_insn_labels ()
748 register struct insn_label_list
**pl
;
750 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
756 static char *expr_end
;
758 /* Expressions which appear in instructions. These are set by
761 static expressionS imm_expr
;
762 static expressionS offset_expr
;
764 /* Relocs associated with imm_expr and offset_expr. */
766 static bfd_reloc_code_real_type imm_reloc
;
767 static bfd_reloc_code_real_type offset_reloc
;
769 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
771 static boolean imm_unmatched_hi
;
773 /* These are set by mips16_ip if an explicit extension is used. */
775 static boolean mips16_small
, mips16_ext
;
778 * This function is called once, at assembler startup time. It should
779 * set up all the tables, etc. that the MD part of the assembler will need.
785 register const char *retval
= NULL
;
786 register unsigned int i
= 0;
788 if (mips_opts
.isa
== -1)
794 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
796 a
= xmalloc (sizeof TARGET_CPU
);
797 strcpy (a
, TARGET_CPU
);
798 a
[(sizeof TARGET_CPU
) - 3] = '\0';
802 if (strcmp (cpu
, "mips") == 0)
808 else if (strcmp (cpu
, "r3900") == 0
809 || strcmp (cpu
, "mipstx39") == 0
810 /* start-sanitize-tx19 */
811 || strcmp (cpu
, "r1900") == 0
812 || strcmp (cpu
, "mipstx19") == 0
813 /* end-sanitize-tx19 */
822 else if (strcmp (cpu
, "r6000") == 0
823 || strcmp (cpu
, "mips2") == 0)
829 else if (strcmp (cpu
, "mips64") == 0
830 || strcmp (cpu
, "r4000") == 0
831 || strcmp (cpu
, "mips3") == 0)
837 else if (strcmp (cpu
, "r4400") == 0)
843 else if (strcmp (cpu
, "mips64orion") == 0
844 || strcmp (cpu
, "r4600") == 0)
850 else if (strcmp (cpu
, "r4650") == 0)
858 else if (strcmp (cpu
, "mips64vr4300") == 0)
864 else if (strcmp (cpu
, "mips64vr4100") == 0)
872 else if (strcmp (cpu
, "r4010") == 0)
880 else if (strcmp (cpu
, "r5000") == 0
881 || strcmp (cpu
, "mips64vr5000") == 0)
887 /* start-sanitize-r5900 */
888 else if (strcmp (cpu
, "r5900") == 0
889 || strcmp (cpu
, "mips64r5900") == 0
890 || strcmp (cpu
, "mips64r5900el") == 0)
898 /* end-sanitize-r5900 */
899 else if (strcmp (cpu
, "r8000") == 0
900 || strcmp (cpu
, "mips4") == 0)
906 else if (strcmp (cpu
, "r10000") == 0)
912 else if (strcmp (cpu
, "mips16") == 0)
916 mips_cpu
= 0; /* FIXME */
929 if (mips_opts
.mips16
< 0)
931 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
932 mips_opts
.mips16
= 1;
934 mips_opts
.mips16
= 0;
946 /* start-sanitize-r5900 */
949 /* end-sanitize-r5900 */
954 if (mips_opts
.isa
< 2 && mips_trap
)
955 as_bad ("trap exception not supported at ISA 1");
957 switch (mips_opts
.isa
)
960 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
963 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
966 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
969 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
973 as_warn ("Could not set architecture and machine");
975 file_mips_isa
= mips_opts
.isa
;
977 op_hash
= hash_new ();
979 for (i
= 0; i
< NUMOPCODES
;)
981 const char *name
= mips_opcodes
[i
].name
;
983 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
986 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
987 mips_opcodes
[i
].name
, retval
);
988 as_fatal ("Broken assembler. No assembly attempted.");
992 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
993 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
994 != mips_opcodes
[i
].match
))
996 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
997 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
998 as_fatal ("Broken assembler. No assembly attempted.");
1002 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1005 mips16_op_hash
= hash_new ();
1008 while (i
< bfd_mips16_num_opcodes
)
1010 const char *name
= mips16_opcodes
[i
].name
;
1012 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1014 as_fatal ("internal error: can't hash `%s': %s\n",
1015 mips16_opcodes
[i
].name
, retval
);
1018 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1019 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1020 != mips16_opcodes
[i
].match
))
1021 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
1022 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1025 while (i
< bfd_mips16_num_opcodes
1026 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1029 /* We add all the general register names to the symbol table. This
1030 helps us detect invalid uses of them. */
1031 for (i
= 0; i
< 32; i
++)
1035 sprintf (buf
, "$%d", i
);
1036 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1037 &zero_address_frag
));
1039 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1040 &zero_address_frag
));
1041 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1042 &zero_address_frag
));
1043 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1044 &zero_address_frag
));
1045 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1046 &zero_address_frag
));
1047 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1048 &zero_address_frag
));
1049 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1050 &zero_address_frag
));
1051 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1052 &zero_address_frag
));
1054 mips_no_prev_insn (false);
1057 mips_cprmask
[0] = 0;
1058 mips_cprmask
[1] = 0;
1059 mips_cprmask
[2] = 0;
1060 mips_cprmask
[3] = 0;
1062 /* set the default alignment for the text section (2**2) */
1063 record_alignment (text_section
, 2);
1065 if (USE_GLOBAL_POINTER_OPT
)
1066 bfd_set_gp_size (stdoutput
, g_switch_value
);
1068 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1070 /* On a native system, sections must be aligned to 16 byte
1071 boundaries. When configured for an embedded ELF target, we
1073 if (strcmp (TARGET_OS
, "elf") != 0)
1075 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1076 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1077 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1080 /* Create a .reginfo section for register masks and a .mdebug
1081 section for debugging information. */
1089 subseg
= now_subseg
;
1091 /* The ABI says this section should be loaded so that the
1092 running program can access it. However, we don't load it
1093 if we are configured for an embedded target */
1094 flags
= SEC_READONLY
| SEC_DATA
;
1095 if (strcmp (TARGET_OS
, "elf") != 0)
1096 flags
|= SEC_ALLOC
| SEC_LOAD
;
1100 sec
= subseg_new (".reginfo", (subsegT
) 0);
1103 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1104 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1107 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1112 /* The 64-bit ABI uses a .MIPS.options section rather than
1113 .reginfo section. */
1114 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1115 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1116 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1119 /* Set up the option header. */
1121 Elf_Internal_Options opthdr
;
1124 opthdr
.kind
= ODK_REGINFO
;
1125 opthdr
.size
= (sizeof (Elf_External_Options
)
1126 + sizeof (Elf64_External_RegInfo
));
1129 f
= frag_more (sizeof (Elf_External_Options
));
1130 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1131 (Elf_External_Options
*) f
);
1133 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1138 if (ECOFF_DEBUGGING
)
1140 sec
= subseg_new (".mdebug", (subsegT
) 0);
1141 (void) bfd_set_section_flags (stdoutput
, sec
,
1142 SEC_HAS_CONTENTS
| SEC_READONLY
);
1143 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1146 subseg_set (seg
, subseg
);
1150 if (! ECOFF_DEBUGGING
)
1157 if (! ECOFF_DEBUGGING
)
1165 struct mips_cl_insn insn
;
1167 imm_expr
.X_op
= O_absent
;
1168 imm_reloc
= BFD_RELOC_UNUSED
;
1169 imm_unmatched_hi
= false;
1170 offset_expr
.X_op
= O_absent
;
1171 offset_reloc
= BFD_RELOC_UNUSED
;
1173 if (mips_opts
.mips16
)
1174 mips16_ip (str
, &insn
);
1177 mips_ip (str
, &insn
);
1178 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1179 str
, insn
.insn_opcode
));
1184 as_bad ("%s `%s'", insn_error
, str
);
1188 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1190 if (mips_opts
.mips16
)
1191 mips16_macro (&insn
);
1197 if (imm_expr
.X_op
!= O_absent
)
1198 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1200 else if (offset_expr
.X_op
!= O_absent
)
1201 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1203 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1207 /* See whether instruction IP reads register REG. CLASS is the type
1211 insn_uses_reg (ip
, reg
, class)
1212 struct mips_cl_insn
*ip
;
1214 enum mips_regclass
class;
1216 if (class == MIPS16_REG
)
1218 assert (mips_opts
.mips16
);
1219 reg
= mips16_to_32_reg_map
[reg
];
1220 class = MIPS_GR_REG
;
1223 /* Don't report on general register 0, since it never changes. */
1224 if (class == MIPS_GR_REG
&& reg
== 0)
1227 if (class == MIPS_FP_REG
)
1229 assert (! mips_opts
.mips16
);
1230 /* If we are called with either $f0 or $f1, we must check $f0.
1231 This is not optimal, because it will introduce an unnecessary
1232 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1233 need to distinguish reading both $f0 and $f1 or just one of
1234 them. Note that we don't have to check the other way,
1235 because there is no instruction that sets both $f0 and $f1
1236 and requires a delay. */
1237 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1238 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1239 == (reg
&~ (unsigned) 1)))
1241 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1242 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1243 == (reg
&~ (unsigned) 1)))
1246 else if (! mips_opts
.mips16
)
1248 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1249 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1251 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1252 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1257 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1258 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1259 & MIPS16OP_MASK_RX
)]
1262 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1263 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1264 & MIPS16OP_MASK_RY
)]
1267 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1268 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1269 & MIPS16OP_MASK_MOVE32Z
)]
1272 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1274 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1276 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1278 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1279 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1280 & MIPS16OP_MASK_REGR32
) == reg
)
1287 /* This function returns true if modifying a register requires a
1291 reg_needs_delay (reg
)
1294 unsigned long prev_pinfo
;
1296 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1297 if (! mips_opts
.noreorder
1298 && mips_opts
.isa
< 4
1299 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1300 || (! gpr_interlocks
1301 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1303 /* A load from a coprocessor or from memory. All load
1304 delays delay the use of general register rt for one
1305 instruction on the r3000. The r6000 and r4000 use
1307 /* Itbl support may require additional care here. */
1308 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1309 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1316 /* Mark instruction labels in mips16 mode. This permits the linker to
1317 handle them specially, such as generating jalx instructions when
1318 needed. We also make them odd for the duration of the assembly, in
1319 order to generate the right sort of code. We will make them even
1320 in the adjust_symtab routine, while leaving them marked. This is
1321 convenient for the debugger and the disassembler. The linker knows
1322 to make them odd again. */
1325 mips16_mark_labels ()
1327 if (mips_opts
.mips16
)
1329 struct insn_label_list
*l
;
1331 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1334 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1335 S_SET_OTHER (l
->label
, STO_MIPS16
);
1337 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1338 ++l
->label
->sy_value
.X_add_number
;
1343 /* Output an instruction. PLACE is where to put the instruction; if
1344 it is NULL, this uses frag_more to get room. IP is the instruction
1345 information. ADDRESS_EXPR is an operand of the instruction to be
1346 used with RELOC_TYPE. */
1349 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1351 struct mips_cl_insn
*ip
;
1352 expressionS
*address_expr
;
1353 bfd_reloc_code_real_type reloc_type
;
1354 boolean unmatched_hi
;
1356 register unsigned long prev_pinfo
, pinfo
;
1361 /* Mark instruction labels in mips16 mode. */
1362 if (mips_opts
.mips16
)
1363 mips16_mark_labels ();
1365 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1366 pinfo
= ip
->insn_mo
->pinfo
;
1368 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1372 /* If the previous insn required any delay slots, see if we need
1373 to insert a NOP or two. There are eight kinds of possible
1374 hazards, of which an instruction can have at most one type.
1375 (1) a load from memory delay
1376 (2) a load from a coprocessor delay
1377 (3) an unconditional branch delay
1378 (4) a conditional branch delay
1379 (5) a move to coprocessor register delay
1380 (6) a load coprocessor register from memory delay
1381 (7) a coprocessor condition code delay
1382 (8) a HI/LO special register delay
1384 There are a lot of optimizations we could do that we don't.
1385 In particular, we do not, in general, reorder instructions.
1386 If you use gcc with optimization, it will reorder
1387 instructions and generally do much more optimization then we
1388 do here; repeating all that work in the assembler would only
1389 benefit hand written assembly code, and does not seem worth
1392 /* This is how a NOP is emitted. */
1393 #define emit_nop() \
1395 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1396 : md_number_to_chars (frag_more (4), 0, 4))
1398 /* The previous insn might require a delay slot, depending upon
1399 the contents of the current insn. */
1400 if (! mips_opts
.mips16
1401 && mips_opts
.isa
< 4
1402 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1403 && ! cop_interlocks
)
1404 || (! gpr_interlocks
1405 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1407 /* A load from a coprocessor or from memory. All load
1408 delays delay the use of general register rt for one
1409 instruction on the r3000. The r6000 and r4000 use
1411 /* Itbl support may require additional care here. */
1412 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1413 if (mips_optimize
== 0
1414 || insn_uses_reg (ip
,
1415 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1420 else if (! mips_opts
.mips16
1421 && mips_opts
.isa
< 4
1422 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1423 && ! cop_interlocks
)
1424 || (mips_opts
.isa
< 2
1425 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1427 /* A generic coprocessor delay. The previous instruction
1428 modified a coprocessor general or control register. If
1429 it modified a control register, we need to avoid any
1430 coprocessor instruction (this is probably not always
1431 required, but it sometimes is). If it modified a general
1432 register, we avoid using that register.
1434 On the r6000 and r4000 loading a coprocessor register
1435 from memory is interlocked, and does not require a delay.
1437 This case is not handled very well. There is no special
1438 knowledge of CP0 handling, and the coprocessors other
1439 than the floating point unit are not distinguished at
1441 /* Itbl support may require additional care here. FIXME!
1442 Need to modify this to include knowledge about
1443 user specified delays! */
1444 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1446 if (mips_optimize
== 0
1447 || insn_uses_reg (ip
,
1448 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1453 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1455 if (mips_optimize
== 0
1456 || insn_uses_reg (ip
,
1457 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1464 /* We don't know exactly what the previous instruction
1465 does. If the current instruction uses a coprocessor
1466 register, we must insert a NOP. If previous
1467 instruction may set the condition codes, and the
1468 current instruction uses them, we must insert two
1470 /* Itbl support may require additional care here. */
1471 if (mips_optimize
== 0
1472 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1473 && (pinfo
& INSN_READ_COND_CODE
)))
1475 else if (pinfo
& INSN_COP
)
1479 else if (! mips_opts
.mips16
1480 && mips_opts
.isa
< 4
1481 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1482 && ! cop_interlocks
)
1484 /* The previous instruction sets the coprocessor condition
1485 codes, but does not require a general coprocessor delay
1486 (this means it is a floating point comparison
1487 instruction). If this instruction uses the condition
1488 codes, we need to insert a single NOP. */
1489 /* Itbl support may require additional care here. */
1490 if (mips_optimize
== 0
1491 || (pinfo
& INSN_READ_COND_CODE
))
1494 else if (prev_pinfo
& INSN_READ_LO
)
1496 /* The previous instruction reads the LO register; if the
1497 current instruction writes to the LO register, we must
1498 insert two NOPS. Some newer processors have interlocks. */
1499 if (! hilo_interlocks
1500 && (mips_optimize
== 0
1501 || (pinfo
& INSN_WRITE_LO
)))
1504 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1506 /* The previous instruction reads the HI register; if the
1507 current instruction writes to the HI register, we must
1508 insert a NOP. Some newer processors have interlocks. */
1509 if (! hilo_interlocks
1510 && (mips_optimize
== 0
1511 || (pinfo
& INSN_WRITE_HI
)))
1515 /* If the previous instruction was in a noreorder section, then
1516 we don't want to insert the nop after all. */
1517 /* Itbl support may require additional care here. */
1518 if (prev_insn_unreordered
)
1521 /* There are two cases which require two intervening
1522 instructions: 1) setting the condition codes using a move to
1523 coprocessor instruction which requires a general coprocessor
1524 delay and then reading the condition codes 2) reading the HI
1525 or LO register and then writing to it (except on processors
1526 which have interlocks). If we are not already emitting a NOP
1527 instruction, we must check for these cases compared to the
1528 instruction previous to the previous instruction. */
1529 if ((! mips_opts
.mips16
1530 && mips_opts
.isa
< 4
1531 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1532 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1533 && (pinfo
& INSN_READ_COND_CODE
)
1534 && ! cop_interlocks
)
1535 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1536 && (pinfo
& INSN_WRITE_LO
)
1537 && ! hilo_interlocks
)
1538 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1539 && (pinfo
& INSN_WRITE_HI
)
1540 && ! hilo_interlocks
))
1545 if (prev_prev_insn_unreordered
)
1548 if (prev_prev_nop
&& nops
== 0)
1551 /* If we are being given a nop instruction, don't bother with
1552 one of the nops we would otherwise output. This will only
1553 happen when a nop instruction is used with mips_optimize set
1556 && ! mips_opts
.noreorder
1557 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1560 /* Now emit the right number of NOP instructions. */
1561 if (nops
> 0 && ! mips_opts
.noreorder
)
1564 unsigned long old_frag_offset
;
1566 struct insn_label_list
*l
;
1568 old_frag
= frag_now
;
1569 old_frag_offset
= frag_now_fix ();
1571 for (i
= 0; i
< nops
; i
++)
1576 listing_prev_line ();
1577 /* We may be at the start of a variant frag. In case we
1578 are, make sure there is enough space for the frag
1579 after the frags created by listing_prev_line. The
1580 argument to frag_grow here must be at least as large
1581 as the argument to all other calls to frag_grow in
1582 this file. We don't have to worry about being in the
1583 middle of a variant frag, because the variants insert
1584 all needed nop instructions themselves. */
1588 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1590 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1591 l
->label
->sy_frag
= frag_now
;
1592 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1593 /* mips16 text labels are stored as odd. */
1594 if (mips_opts
.mips16
)
1595 ++l
->label
->sy_value
.X_add_number
;
1598 #ifndef NO_ECOFF_DEBUGGING
1599 if (ECOFF_DEBUGGING
)
1600 ecoff_fix_loc (old_frag
, old_frag_offset
);
1603 else if (prev_nop_frag
!= NULL
)
1605 /* We have a frag holding nops we may be able to remove. If
1606 we don't need any nops, we can decrease the size of
1607 prev_nop_frag by the size of one instruction. If we do
1608 need some nops, we count them in prev_nops_required. */
1609 if (prev_nop_frag_since
== 0)
1613 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1614 --prev_nop_frag_holds
;
1617 prev_nop_frag_required
+= nops
;
1621 if (prev_prev_nop
== 0)
1623 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1624 --prev_nop_frag_holds
;
1627 ++prev_nop_frag_required
;
1630 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1631 prev_nop_frag
= NULL
;
1633 ++prev_nop_frag_since
;
1635 /* Sanity check: by the time we reach the second instruction
1636 after prev_nop_frag, we should have used up all the nops
1637 one way or another. */
1638 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1642 if (reloc_type
> BFD_RELOC_UNUSED
)
1644 /* We need to set up a variant frag. */
1645 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1646 f
= frag_var (rs_machine_dependent
, 4, 0,
1647 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1648 mips16_small
, mips16_ext
,
1650 & INSN_UNCOND_BRANCH_DELAY
),
1651 (prev_insn_reloc_type
1652 == BFD_RELOC_MIPS16_JMP
)),
1653 make_expr_symbol (address_expr
), (offsetT
) 0,
1656 else if (place
!= NULL
)
1658 else if (mips_opts
.mips16
1660 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1662 /* Make sure there is enough room to swap this instruction with
1663 a following jump instruction. */
1669 if (mips_opts
.mips16
1670 && mips_opts
.noreorder
1671 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1672 as_warn ("extended instruction in delay slot");
1678 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1680 if (address_expr
->X_op
== O_constant
)
1685 ip
->insn_opcode
|= address_expr
->X_add_number
;
1688 case BFD_RELOC_LO16
:
1689 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1692 case BFD_RELOC_MIPS_JMP
:
1693 if ((address_expr
->X_add_number
& 3) != 0)
1694 as_bad ("jump to misaligned address (0x%lx)",
1695 (unsigned long) address_expr
->X_add_number
);
1696 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1699 case BFD_RELOC_MIPS16_JMP
:
1700 if ((address_expr
->X_add_number
& 3) != 0)
1701 as_bad ("jump to misaligned address (0x%lx)",
1702 (unsigned long) address_expr
->X_add_number
);
1704 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1705 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1706 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1709 case BFD_RELOC_16_PCREL_S2
:
1719 /* Don't generate a reloc if we are writing into a variant
1723 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1725 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1729 struct mips_hi_fixup
*hi_fixup
;
1731 assert (reloc_type
== BFD_RELOC_HI16_S
);
1732 hi_fixup
= ((struct mips_hi_fixup
*)
1733 xmalloc (sizeof (struct mips_hi_fixup
)));
1734 hi_fixup
->fixp
= fixp
;
1735 hi_fixup
->seg
= now_seg
;
1736 hi_fixup
->next
= mips_hi_fixup_list
;
1737 mips_hi_fixup_list
= hi_fixup
;
1743 if (! mips_opts
.mips16
)
1744 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1745 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1747 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1748 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1754 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1757 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1760 /* Update the register mask information. */
1761 if (! mips_opts
.mips16
)
1763 if (pinfo
& INSN_WRITE_GPR_D
)
1764 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1765 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1766 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1767 if (pinfo
& INSN_READ_GPR_S
)
1768 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1769 if (pinfo
& INSN_WRITE_GPR_31
)
1770 mips_gprmask
|= 1 << 31;
1771 if (pinfo
& INSN_WRITE_FPR_D
)
1772 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1773 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1774 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1775 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1776 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1777 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1778 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1779 if (pinfo
& INSN_COP
)
1781 /* We don't keep enough information to sort these cases out.
1782 The itbl support does keep this information however, although
1783 we currently don't support itbl fprmats as part of the cop
1784 instruction. May want to add this support in the future. */
1786 /* Never set the bit for $0, which is always zero. */
1787 mips_gprmask
&=~ 1 << 0;
1791 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1792 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1793 & MIPS16OP_MASK_RX
);
1794 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1795 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1796 & MIPS16OP_MASK_RY
);
1797 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1798 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1799 & MIPS16OP_MASK_RZ
);
1800 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1801 mips_gprmask
|= 1 << TREG
;
1802 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1803 mips_gprmask
|= 1 << SP
;
1804 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1805 mips_gprmask
|= 1 << RA
;
1806 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1807 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1808 if (pinfo
& MIPS16_INSN_READ_Z
)
1809 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1810 & MIPS16OP_MASK_MOVE32Z
);
1811 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1812 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1813 & MIPS16OP_MASK_REGR32
);
1816 if (place
== NULL
&& ! mips_opts
.noreorder
)
1818 /* Filling the branch delay slot is more complex. We try to
1819 switch the branch with the previous instruction, which we can
1820 do if the previous instruction does not set up a condition
1821 that the branch tests and if the branch is not itself the
1822 target of any branch. */
1823 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1824 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1826 if (mips_optimize
< 2
1827 /* If we have seen .set volatile or .set nomove, don't
1829 || mips_opts
.nomove
!= 0
1830 /* If we had to emit any NOP instructions, then we
1831 already know we can not swap. */
1833 /* If we don't even know the previous insn, we can not
1835 || ! prev_insn_valid
1836 /* If the previous insn is already in a branch delay
1837 slot, then we can not swap. */
1838 || prev_insn_is_delay_slot
1839 /* If the previous previous insn was in a .set
1840 noreorder, we can't swap. Actually, the MIPS
1841 assembler will swap in this situation. However, gcc
1842 configured -with-gnu-as will generate code like
1848 in which we can not swap the bne and INSN. If gcc is
1849 not configured -with-gnu-as, it does not output the
1850 .set pseudo-ops. We don't have to check
1851 prev_insn_unreordered, because prev_insn_valid will
1852 be 0 in that case. We don't want to use
1853 prev_prev_insn_valid, because we do want to be able
1854 to swap at the start of a function. */
1855 || prev_prev_insn_unreordered
1856 /* If the branch is itself the target of a branch, we
1857 can not swap. We cheat on this; all we check for is
1858 whether there is a label on this instruction. If
1859 there are any branches to anything other than a
1860 label, users must use .set noreorder. */
1861 || insn_labels
!= NULL
1862 /* If the previous instruction is in a variant frag, we
1863 can not do the swap. This does not apply to the
1864 mips16, which uses variant frags for different
1866 || (! mips_opts
.mips16
1867 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1868 /* If the branch reads the condition codes, we don't
1869 even try to swap, because in the sequence
1874 we can not swap, and I don't feel like handling that
1876 || (! mips_opts
.mips16
1877 && mips_opts
.isa
< 4
1878 && (pinfo
& INSN_READ_COND_CODE
))
1879 /* We can not swap with an instruction that requires a
1880 delay slot, becase the target of the branch might
1881 interfere with that instruction. */
1882 || (! mips_opts
.mips16
1883 && mips_opts
.isa
< 4
1885 /* Itbl support may require additional care here. */
1886 & (INSN_LOAD_COPROC_DELAY
1887 | INSN_COPROC_MOVE_DELAY
1888 | INSN_WRITE_COND_CODE
)))
1889 || (! hilo_interlocks
1893 || (! mips_opts
.mips16
1895 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1896 || (! mips_opts
.mips16
1897 && mips_opts
.isa
< 2
1898 /* Itbl support may require additional care here. */
1899 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1900 /* We can not swap with a branch instruction. */
1902 & (INSN_UNCOND_BRANCH_DELAY
1903 | INSN_COND_BRANCH_DELAY
1904 | INSN_COND_BRANCH_LIKELY
))
1905 /* We do not swap with a trap instruction, since it
1906 complicates trap handlers to have the trap
1907 instruction be in a delay slot. */
1908 || (prev_pinfo
& INSN_TRAP
)
1909 /* If the branch reads a register that the previous
1910 instruction sets, we can not swap. */
1911 || (! mips_opts
.mips16
1912 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1913 && insn_uses_reg (ip
,
1914 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1917 || (! mips_opts
.mips16
1918 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1919 && insn_uses_reg (ip
,
1920 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1923 || (mips_opts
.mips16
1924 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1925 && insn_uses_reg (ip
,
1926 ((prev_insn
.insn_opcode
1928 & MIPS16OP_MASK_RX
),
1930 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1931 && insn_uses_reg (ip
,
1932 ((prev_insn
.insn_opcode
1934 & MIPS16OP_MASK_RY
),
1936 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1937 && insn_uses_reg (ip
,
1938 ((prev_insn
.insn_opcode
1940 & MIPS16OP_MASK_RZ
),
1942 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1943 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1944 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1945 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1946 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1947 && insn_uses_reg (ip
,
1948 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1951 /* If the branch writes a register that the previous
1952 instruction sets, we can not swap (we know that
1953 branches write only to RD or to $31). */
1954 || (! mips_opts
.mips16
1955 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1956 && (((pinfo
& INSN_WRITE_GPR_D
)
1957 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1958 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1959 || ((pinfo
& INSN_WRITE_GPR_31
)
1960 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1963 || (! mips_opts
.mips16
1964 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1965 && (((pinfo
& INSN_WRITE_GPR_D
)
1966 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1967 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1968 || ((pinfo
& INSN_WRITE_GPR_31
)
1969 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1972 || (mips_opts
.mips16
1973 && (pinfo
& MIPS16_INSN_WRITE_31
)
1974 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1975 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1976 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1978 /* If the branch writes a register that the previous
1979 instruction reads, we can not swap (we know that
1980 branches only write to RD or to $31). */
1981 || (! mips_opts
.mips16
1982 && (pinfo
& INSN_WRITE_GPR_D
)
1983 && insn_uses_reg (&prev_insn
,
1984 ((ip
->insn_opcode
>> OP_SH_RD
)
1987 || (! mips_opts
.mips16
1988 && (pinfo
& INSN_WRITE_GPR_31
)
1989 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1990 || (mips_opts
.mips16
1991 && (pinfo
& MIPS16_INSN_WRITE_31
)
1992 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1993 /* If we are generating embedded PIC code, the branch
1994 might be expanded into a sequence which uses $at, so
1995 we can't swap with an instruction which reads it. */
1996 || (mips_pic
== EMBEDDED_PIC
1997 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1998 /* If the previous previous instruction has a load
1999 delay, and sets a register that the branch reads, we
2001 || (! mips_opts
.mips16
2002 && mips_opts
.isa
< 4
2003 /* Itbl support may require additional care here. */
2004 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2005 || (! gpr_interlocks
2006 && (prev_prev_insn
.insn_mo
->pinfo
2007 & INSN_LOAD_MEMORY_DELAY
)))
2008 && insn_uses_reg (ip
,
2009 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2012 /* If one instruction sets a condition code and the
2013 other one uses a condition code, we can not swap. */
2014 || ((pinfo
& INSN_READ_COND_CODE
)
2015 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2016 || ((pinfo
& INSN_WRITE_COND_CODE
)
2017 && (prev_pinfo
& INSN_READ_COND_CODE
))
2018 /* If the previous instruction uses the PC, we can not
2020 || (mips_opts
.mips16
2021 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2022 /* If the previous instruction was extended, we can not
2024 || (mips_opts
.mips16
&& prev_insn_extended
)
2025 /* If the previous instruction had a fixup in mips16
2026 mode, we can not swap. This normally means that the
2027 previous instruction was a 4 byte branch anyhow. */
2028 || (mips_opts
.mips16
&& prev_insn_fixp
))
2030 /* We could do even better for unconditional branches to
2031 portions of this object file; we could pick up the
2032 instruction at the destination, put it in the delay
2033 slot, and bump the destination address. */
2035 /* Update the previous insn information. */
2036 prev_prev_insn
= *ip
;
2037 prev_insn
.insn_mo
= &dummy_opcode
;
2041 /* It looks like we can actually do the swap. */
2042 if (! mips_opts
.mips16
)
2047 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2048 memcpy (temp
, prev_f
, 4);
2049 memcpy (prev_f
, f
, 4);
2050 memcpy (f
, temp
, 4);
2053 prev_insn_fixp
->fx_frag
= frag_now
;
2054 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2058 fixp
->fx_frag
= prev_insn_frag
;
2059 fixp
->fx_where
= prev_insn_where
;
2067 assert (prev_insn_fixp
== NULL
);
2068 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2069 memcpy (temp
, prev_f
, 2);
2070 memcpy (prev_f
, f
, 2);
2071 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2073 assert (reloc_type
== BFD_RELOC_UNUSED
);
2074 memcpy (f
, temp
, 2);
2078 memcpy (f
, f
+ 2, 2);
2079 memcpy (f
+ 2, temp
, 2);
2083 fixp
->fx_frag
= prev_insn_frag
;
2084 fixp
->fx_where
= prev_insn_where
;
2088 /* Update the previous insn information; leave prev_insn
2090 prev_prev_insn
= *ip
;
2092 prev_insn_is_delay_slot
= 1;
2094 /* If that was an unconditional branch, forget the previous
2095 insn information. */
2096 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2098 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2099 prev_insn
.insn_mo
= &dummy_opcode
;
2102 prev_insn_fixp
= NULL
;
2103 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2104 prev_insn_extended
= 0;
2106 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2108 /* We don't yet optimize a branch likely. What we should do
2109 is look at the target, copy the instruction found there
2110 into the delay slot, and increment the branch to jump to
2111 the next instruction. */
2113 /* Update the previous insn information. */
2114 prev_prev_insn
= *ip
;
2115 prev_insn
.insn_mo
= &dummy_opcode
;
2116 prev_insn_fixp
= NULL
;
2117 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2118 prev_insn_extended
= 0;
2122 /* Update the previous insn information. */
2124 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2126 prev_prev_insn
= prev_insn
;
2129 /* Any time we see a branch, we always fill the delay slot
2130 immediately; since this insn is not a branch, we know it
2131 is not in a delay slot. */
2132 prev_insn_is_delay_slot
= 0;
2134 prev_insn_fixp
= fixp
;
2135 prev_insn_reloc_type
= reloc_type
;
2136 if (mips_opts
.mips16
)
2137 prev_insn_extended
= (ip
->use_extend
2138 || reloc_type
> BFD_RELOC_UNUSED
);
2141 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2142 prev_insn_unreordered
= 0;
2143 prev_insn_frag
= frag_now
;
2144 prev_insn_where
= f
- frag_now
->fr_literal
;
2145 prev_insn_valid
= 1;
2147 else if (place
== NULL
)
2149 /* We need to record a bit of information even when we are not
2150 reordering, in order to determine the base address for mips16
2151 PC relative relocs. */
2152 prev_prev_insn
= prev_insn
;
2154 prev_insn_reloc_type
= reloc_type
;
2155 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2156 prev_insn_unreordered
= 1;
2159 /* We just output an insn, so the next one doesn't have a label. */
2160 mips_clear_insn_labels ();
2163 /* This function forgets that there was any previous instruction or
2164 label. If PRESERVE is non-zero, it remembers enough information to
2165 know whether nops are needed before a noreorder section. */
2168 mips_no_prev_insn (preserve
)
2173 prev_insn
.insn_mo
= &dummy_opcode
;
2174 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2175 prev_nop_frag
= NULL
;
2176 prev_nop_frag_holds
= 0;
2177 prev_nop_frag_required
= 0;
2178 prev_nop_frag_since
= 0;
2180 prev_insn_valid
= 0;
2181 prev_insn_is_delay_slot
= 0;
2182 prev_insn_unreordered
= 0;
2183 prev_insn_extended
= 0;
2184 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2185 prev_prev_insn_unreordered
= 0;
2186 mips_clear_insn_labels ();
2189 /* This function must be called whenever we turn on noreorder or emit
2190 something other than instructions. It inserts any NOPS which might
2191 be needed by the previous instruction, and clears the information
2192 kept for the previous instructions. The INSNS parameter is true if
2193 instructions are to follow. */
2196 mips_emit_delays (insns
)
2199 if (! mips_opts
.noreorder
)
2204 if ((! mips_opts
.mips16
2205 && mips_opts
.isa
< 4
2206 && (! cop_interlocks
2207 && (prev_insn
.insn_mo
->pinfo
2208 & (INSN_LOAD_COPROC_DELAY
2209 | INSN_COPROC_MOVE_DELAY
2210 | INSN_WRITE_COND_CODE
))))
2211 || (! hilo_interlocks
2212 && (prev_insn
.insn_mo
->pinfo
2215 || (! mips_opts
.mips16
2217 && (prev_insn
.insn_mo
->pinfo
2218 & INSN_LOAD_MEMORY_DELAY
))
2219 || (! mips_opts
.mips16
2220 && mips_opts
.isa
< 2
2221 && (prev_insn
.insn_mo
->pinfo
2222 & INSN_COPROC_MEMORY_DELAY
)))
2224 /* Itbl support may require additional care here. */
2226 if ((! mips_opts
.mips16
2227 && mips_opts
.isa
< 4
2228 && (! cop_interlocks
2229 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2230 || (! hilo_interlocks
2231 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2232 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2235 if (prev_insn_unreordered
)
2238 else if ((! mips_opts
.mips16
2239 && mips_opts
.isa
< 4
2240 && (! cop_interlocks
2241 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2242 || (! hilo_interlocks
2243 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2244 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2246 /* Itbl support may require additional care here. */
2247 if (! prev_prev_insn_unreordered
)
2253 struct insn_label_list
*l
;
2257 /* Record the frag which holds the nop instructions, so
2258 that we can remove them if we don't need them. */
2259 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2260 prev_nop_frag
= frag_now
;
2261 prev_nop_frag_holds
= nops
;
2262 prev_nop_frag_required
= 0;
2263 prev_nop_frag_since
= 0;
2266 for (; nops
> 0; --nops
)
2271 /* Move on to a new frag, so that it is safe to simply
2272 decrease the size of prev_nop_frag. */
2273 frag_wane (frag_now
);
2277 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2279 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2280 l
->label
->sy_frag
= frag_now
;
2281 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2282 /* mips16 text labels are stored as odd. */
2283 if (mips_opts
.mips16
)
2284 ++l
->label
->sy_value
.X_add_number
;
2289 /* Mark instruction labels in mips16 mode. */
2290 if (mips_opts
.mips16
&& insns
)
2291 mips16_mark_labels ();
2293 mips_no_prev_insn (insns
);
2296 /* Build an instruction created by a macro expansion. This is passed
2297 a pointer to the count of instructions created so far, an
2298 expression, the name of the instruction to build, an operand format
2299 string, and corresponding arguments. */
2303 macro_build (char *place
,
2311 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2320 struct mips_cl_insn insn
;
2321 bfd_reloc_code_real_type r
;
2326 va_start (args
, fmt
);
2332 * If the macro is about to expand into a second instruction,
2333 * print a warning if needed. We need to pass ip as a parameter
2334 * to generate a better warning message here...
2336 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2337 as_warn ("Macro instruction expanded into multiple instructions");
2340 *counter
+= 1; /* bump instruction counter */
2342 if (mips_opts
.mips16
)
2344 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2349 r
= BFD_RELOC_UNUSED
;
2350 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2351 assert (insn
.insn_mo
);
2352 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2354 /* Search until we get a match for NAME. */
2357 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2358 insn_isa
= insn
.insn_mo
->match
;
2359 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2361 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2363 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2365 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2370 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2371 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2372 && (insn_isa
<= mips_opts
.isa
2374 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2376 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2378 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2379 /* start-sanitize-r5900 */
2381 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2382 /* end-sanitize-r5900 */
2384 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2385 /* start-sanitize-r5900 */
2386 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2387 /* end-sanitize-r5900 */
2388 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2392 assert (insn
.insn_mo
->name
);
2393 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2396 insn
.insn_opcode
= insn
.insn_mo
->match
;
2412 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2418 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2423 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2428 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2435 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2439 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2443 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2450 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2456 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2457 assert (r
== BFD_RELOC_MIPS_GPREL
2458 || r
== BFD_RELOC_MIPS_LITERAL
2459 || r
== BFD_RELOC_LO16
2460 || r
== BFD_RELOC_MIPS_GOT16
2461 || r
== BFD_RELOC_MIPS_CALL16
2462 || r
== BFD_RELOC_MIPS_GOT_LO16
2463 || r
== BFD_RELOC_MIPS_CALL_LO16
2464 || (ep
->X_op
== O_subtract
2465 && now_seg
== text_section
2466 && r
== BFD_RELOC_PCREL_LO16
));
2470 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2472 && (ep
->X_op
== O_constant
2473 || (ep
->X_op
== O_symbol
2474 && (r
== BFD_RELOC_HI16_S
2475 || r
== BFD_RELOC_HI16
2476 || r
== BFD_RELOC_MIPS_GOT_HI16
2477 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2478 || (ep
->X_op
== O_subtract
2479 && now_seg
== text_section
2480 && r
== BFD_RELOC_PCREL_HI16_S
)));
2481 if (ep
->X_op
== O_constant
)
2483 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2485 r
= BFD_RELOC_UNUSED
;
2490 assert (ep
!= NULL
);
2492 * This allows macro() to pass an immediate expression for
2493 * creating short branches without creating a symbol.
2494 * Note that the expression still might come from the assembly
2495 * input, in which case the value is not checked for range nor
2496 * is a relocation entry generated (yuck).
2498 if (ep
->X_op
== O_constant
)
2500 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2504 r
= BFD_RELOC_16_PCREL_S2
;
2508 assert (ep
!= NULL
);
2509 r
= BFD_RELOC_MIPS_JMP
;
2518 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2520 append_insn (place
, &insn
, ep
, r
, false);
2524 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2532 struct mips_cl_insn insn
;
2533 bfd_reloc_code_real_type r
;
2535 r
= BFD_RELOC_UNUSED
;
2536 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2537 assert (insn
.insn_mo
);
2538 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2540 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2541 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2544 assert (insn
.insn_mo
->name
);
2545 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2548 insn
.insn_opcode
= insn
.insn_mo
->match
;
2549 insn
.use_extend
= false;
2568 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2573 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2577 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2581 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2591 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2598 regno
= va_arg (args
, int);
2599 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2600 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2621 assert (ep
!= NULL
);
2623 if (ep
->X_op
!= O_constant
)
2624 r
= BFD_RELOC_UNUSED
+ c
;
2627 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2628 false, false, &insn
.insn_opcode
,
2629 &insn
.use_extend
, &insn
.extend
);
2631 r
= BFD_RELOC_UNUSED
;
2637 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2644 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2646 append_insn (place
, &insn
, ep
, r
, false);
2650 * Generate a "lui" instruction.
2653 macro_build_lui (place
, counter
, ep
, regnum
)
2659 expressionS high_expr
;
2660 struct mips_cl_insn insn
;
2661 bfd_reloc_code_real_type r
;
2662 CONST
char *name
= "lui";
2663 CONST
char *fmt
= "t,u";
2665 assert (! mips_opts
.mips16
);
2671 high_expr
.X_op
= O_constant
;
2672 high_expr
.X_add_number
= ep
->X_add_number
;
2675 if (high_expr
.X_op
== O_constant
)
2677 /* we can compute the instruction now without a relocation entry */
2678 if (high_expr
.X_add_number
& 0x8000)
2679 high_expr
.X_add_number
+= 0x10000;
2680 high_expr
.X_add_number
=
2681 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2682 r
= BFD_RELOC_UNUSED
;
2686 assert (ep
->X_op
== O_symbol
);
2687 /* _gp_disp is a special case, used from s_cpload. */
2688 assert (mips_pic
== NO_PIC
2689 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2690 r
= BFD_RELOC_HI16_S
;
2694 * If the macro is about to expand into a second instruction,
2695 * print a warning if needed. We need to pass ip as a parameter
2696 * to generate a better warning message here...
2698 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2699 as_warn ("Macro instruction expanded into multiple instructions");
2702 *counter
+= 1; /* bump instruction counter */
2704 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2705 assert (insn
.insn_mo
);
2706 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2707 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2709 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2710 if (r
== BFD_RELOC_UNUSED
)
2712 insn
.insn_opcode
|= high_expr
.X_add_number
;
2713 append_insn (place
, &insn
, NULL
, r
, false);
2716 append_insn (place
, &insn
, &high_expr
, r
, false);
2720 * Generates code to set the $at register to true (one)
2721 * if reg is less than the immediate expression.
2724 set_at (counter
, reg
, unsignedp
)
2729 if (imm_expr
.X_op
== O_constant
2730 && imm_expr
.X_add_number
>= -0x8000
2731 && imm_expr
.X_add_number
< 0x8000)
2732 macro_build ((char *) NULL
, counter
, &imm_expr
,
2733 unsignedp
? "sltiu" : "slti",
2734 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2737 load_register (counter
, AT
, &imm_expr
, 0);
2738 macro_build ((char *) NULL
, counter
, NULL
,
2739 unsignedp
? "sltu" : "slt",
2740 "d,v,t", AT
, reg
, AT
);
2744 /* Warn if an expression is not a constant. */
2747 check_absolute_expr (ip
, ex
)
2748 struct mips_cl_insn
*ip
;
2751 if (ex
->X_op
== O_big
)
2752 as_bad ("unsupported large constant");
2753 else if (ex
->X_op
!= O_constant
)
2754 as_bad ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2757 /* Count the leading zeroes by performing a binary chop. This is a
2758 bulky bit of source, but performance is a LOT better for the
2759 majority of values than a simple loop to count the bits:
2760 for (lcnt = 0; (lcnt < 32); lcnt++)
2761 if ((v) & (1 << (31 - lcnt)))
2763 However it is not code size friendly, and the gain will drop a bit
2764 on certain cached systems.
2766 #define COUNT_TOP_ZEROES(v) \
2767 (((v) & ~0xffff) == 0 \
2768 ? ((v) & ~0xff) == 0 \
2769 ? ((v) & ~0xf) == 0 \
2770 ? ((v) & ~0x3) == 0 \
2771 ? ((v) & ~0x1) == 0 \
2776 : ((v) & ~0x7) == 0 \
2779 : ((v) & ~0x3f) == 0 \
2780 ? ((v) & ~0x1f) == 0 \
2783 : ((v) & ~0x7f) == 0 \
2786 : ((v) & ~0xfff) == 0 \
2787 ? ((v) & ~0x3ff) == 0 \
2788 ? ((v) & ~0x1ff) == 0 \
2791 : ((v) & ~0x7ff) == 0 \
2794 : ((v) & ~0x3fff) == 0 \
2795 ? ((v) & ~0x1fff) == 0 \
2798 : ((v) & ~0x7fff) == 0 \
2801 : ((v) & ~0xffffff) == 0 \
2802 ? ((v) & ~0xfffff) == 0 \
2803 ? ((v) & ~0x3ffff) == 0 \
2804 ? ((v) & ~0x1ffff) == 0 \
2807 : ((v) & ~0x7ffff) == 0 \
2810 : ((v) & ~0x3fffff) == 0 \
2811 ? ((v) & ~0x1fffff) == 0 \
2814 : ((v) & ~0x7fffff) == 0 \
2817 : ((v) & ~0xfffffff) == 0 \
2818 ? ((v) & ~0x3ffffff) == 0 \
2819 ? ((v) & ~0x1ffffff) == 0 \
2822 : ((v) & ~0x7ffffff) == 0 \
2825 : ((v) & ~0x3fffffff) == 0 \
2826 ? ((v) & ~0x1fffffff) == 0 \
2829 : ((v) & ~0x7fffffff) == 0 \
2834 * This routine generates the least number of instructions neccessary to load
2835 * an absolute expression value into a register.
2838 load_register (counter
, reg
, ep
, dbl
)
2845 expressionS hi32
, lo32
;
2847 if (ep
->X_op
!= O_big
)
2849 assert (ep
->X_op
== O_constant
);
2850 if (ep
->X_add_number
< 0x8000
2851 && (ep
->X_add_number
>= 0
2852 || (ep
->X_add_number
>= -0x8000
2855 || sizeof (ep
->X_add_number
) > 4))))
2857 /* We can handle 16 bit signed values with an addiu to
2858 $zero. No need to ever use daddiu here, since $zero and
2859 the result are always correct in 32 bit mode. */
2860 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2861 (int) BFD_RELOC_LO16
);
2864 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2866 /* We can handle 16 bit unsigned values with an ori to
2868 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2869 (int) BFD_RELOC_LO16
);
2872 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2873 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2874 == ~ (offsetT
) 0x7fffffff))
2877 || sizeof (ep
->X_add_number
) > 4
2878 || (ep
->X_add_number
& 0x80000000) == 0))
2879 || ((mips_opts
.isa
< 3 || ! dbl
)
2880 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2881 || (mips_opts
.isa
< 3
2883 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2884 == ~ (offsetT
) 0xffffffff)))
2886 /* 32 bit values require an lui. */
2887 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2888 (int) BFD_RELOC_HI16
);
2889 if ((ep
->X_add_number
& 0xffff) != 0)
2890 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2891 (int) BFD_RELOC_LO16
);
2896 /* The value is larger than 32 bits. */
2898 if (mips_opts
.isa
< 3)
2900 as_bad ("Number larger than 32 bits");
2901 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2902 (int) BFD_RELOC_LO16
);
2906 if (ep
->X_op
!= O_big
)
2909 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2910 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2911 hi32
.X_add_number
&= 0xffffffff;
2913 lo32
.X_add_number
&= 0xffffffff;
2917 assert (ep
->X_add_number
> 2);
2918 if (ep
->X_add_number
== 3)
2919 generic_bignum
[3] = 0;
2920 else if (ep
->X_add_number
> 4)
2921 as_bad ("Number larger than 64 bits");
2922 lo32
.X_op
= O_constant
;
2923 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2924 hi32
.X_op
= O_constant
;
2925 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2928 if (hi32
.X_add_number
== 0)
2933 unsigned long hi
, lo
;
2935 if (hi32
.X_add_number
== 0xffffffff)
2937 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2939 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2940 reg
, 0, (int) BFD_RELOC_LO16
);
2943 if (lo32
.X_add_number
& 0x80000000)
2945 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2946 (int) BFD_RELOC_HI16
);
2947 if (lo32
.X_add_number
& 0xffff)
2948 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2949 reg
, reg
, (int) BFD_RELOC_LO16
);
2954 /* Check for 16bit shifted constant. We know that hi32 is
2955 non-zero, so start the mask on the first bit of the hi32
2960 unsigned long himask
, lomask
;
2964 himask
= 0xffff >> (32 - shift
);
2965 lomask
= (0xffff << shift
) & 0xffffffff;
2969 himask
= 0xffff << (shift
- 32);
2972 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2973 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2977 tmp
.X_op
= O_constant
;
2979 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2980 | (lo32
.X_add_number
>> shift
));
2982 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2983 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2984 (int) BFD_RELOC_LO16
);
2985 macro_build ((char *) NULL
, counter
, NULL
,
2986 (shift
>= 32) ? "dsll32" : "dsll",
2988 (shift
>= 32) ? shift
- 32 : shift
);
2992 } while (shift
<= (64 - 16));
2994 /* Find the bit number of the lowest one bit, and store the
2995 shifted value in hi/lo. */
2996 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2997 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3001 while ((lo
& 1) == 0)
3006 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3012 while ((hi
& 1) == 0)
3021 /* Optimize if the shifted value is a (power of 2) - 1. */
3022 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3023 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3025 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3030 /* This instruction will set the register to be all
3032 tmp
.X_op
= O_constant
;
3033 tmp
.X_add_number
= (offsetT
) -1;
3034 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3035 reg
, 0, (int) BFD_RELOC_LO16
);
3039 macro_build ((char *) NULL
, counter
, NULL
,
3040 (bit
>= 32) ? "dsll32" : "dsll",
3042 (bit
>= 32) ? bit
- 32 : bit
);
3044 macro_build ((char *) NULL
, counter
, NULL
,
3045 (shift
>= 32) ? "dsrl32" : "dsrl",
3047 (shift
>= 32) ? shift
- 32 : shift
);
3052 /* Sign extend hi32 before calling load_register, because we can
3053 generally get better code when we load a sign extended value. */
3054 if ((hi32
.X_add_number
& 0x80000000) != 0)
3055 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3056 load_register (counter
, reg
, &hi32
, 0);
3059 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3063 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3072 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3074 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3075 (int) BFD_RELOC_HI16
);
3076 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3083 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3088 mid16
.X_add_number
>>= 16;
3089 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3090 freg
, (int) BFD_RELOC_LO16
);
3091 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3095 if ((lo32
.X_add_number
& 0xffff) != 0)
3096 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3097 (int) BFD_RELOC_LO16
);
3100 /* Load an address into a register. */
3103 load_address (counter
, reg
, ep
)
3110 if (ep
->X_op
!= O_constant
3111 && ep
->X_op
!= O_symbol
)
3113 as_bad ("expression too complex");
3114 ep
->X_op
= O_constant
;
3117 if (ep
->X_op
== O_constant
)
3119 load_register (counter
, reg
, ep
, 0);
3123 if (mips_pic
== NO_PIC
)
3125 /* If this is a reference to a GP relative symbol, we want
3126 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3128 lui $reg,<sym> (BFD_RELOC_HI16_S)
3129 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3130 If we have an addend, we always use the latter form. */
3131 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3132 || nopic_need_relax (ep
->X_add_symbol
, 1))
3137 macro_build ((char *) NULL
, counter
, ep
,
3138 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3139 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3140 p
= frag_var (rs_machine_dependent
, 8, 0,
3141 RELAX_ENCODE (4, 8, 0, 4, 0,
3142 mips_opts
.warn_about_macros
),
3143 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3145 macro_build_lui (p
, counter
, ep
, reg
);
3148 macro_build (p
, counter
, ep
,
3149 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3150 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3152 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3156 /* If this is a reference to an external symbol, we want
3157 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3159 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3161 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3162 If there is a constant, it must be added in after. */
3163 ex
.X_add_number
= ep
->X_add_number
;
3164 ep
->X_add_number
= 0;
3166 macro_build ((char *) NULL
, counter
, ep
,
3167 mips_opts
.isa
< 3 ? "lw" : "ld",
3168 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3169 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3170 p
= frag_var (rs_machine_dependent
, 4, 0,
3171 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3172 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3173 macro_build (p
, counter
, ep
,
3174 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3175 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3176 if (ex
.X_add_number
!= 0)
3178 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3179 as_bad ("PIC code offset overflow (max 16 signed bits)");
3180 ex
.X_op
= O_constant
;
3181 macro_build ((char *) NULL
, counter
, &ex
,
3182 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3183 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3186 else if (mips_pic
== SVR4_PIC
)
3191 /* This is the large GOT case. If this is a reference to an
3192 external symbol, we want
3193 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3195 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3196 Otherwise, for a reference to a local symbol, we want
3197 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3199 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3200 If there is a constant, it must be added in after. */
3201 ex
.X_add_number
= ep
->X_add_number
;
3202 ep
->X_add_number
= 0;
3203 if (reg_needs_delay (GP
))
3208 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3209 (int) BFD_RELOC_MIPS_GOT_HI16
);
3210 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3211 mips_opts
.isa
< 3 ? "addu" : "daddu",
3212 "d,v,t", reg
, reg
, GP
);
3213 macro_build ((char *) NULL
, counter
, ep
,
3214 mips_opts
.isa
< 3 ? "lw" : "ld",
3215 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3216 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3217 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3218 mips_opts
.warn_about_macros
),
3219 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3222 /* We need a nop before loading from $gp. This special
3223 check is required because the lui which starts the main
3224 instruction stream does not refer to $gp, and so will not
3225 insert the nop which may be required. */
3226 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3229 macro_build (p
, counter
, ep
,
3230 mips_opts
.isa
< 3 ? "lw" : "ld",
3231 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3233 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3235 macro_build (p
, counter
, ep
,
3236 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3237 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3238 if (ex
.X_add_number
!= 0)
3240 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3241 as_bad ("PIC code offset overflow (max 16 signed bits)");
3242 ex
.X_op
= O_constant
;
3243 macro_build ((char *) NULL
, counter
, &ex
,
3244 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3245 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3248 else if (mips_pic
== EMBEDDED_PIC
)
3251 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3253 macro_build ((char *) NULL
, counter
, ep
,
3254 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3255 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3263 * This routine implements the seemingly endless macro or synthesized
3264 * instructions and addressing modes in the mips assembly language. Many
3265 * of these macros are simple and are similar to each other. These could
3266 * probably be handled by some kind of table or grammer aproach instead of
3267 * this verbose method. Others are not simple macros but are more like
3268 * optimizing code generation.
3269 * One interesting optimization is when several store macros appear
3270 * consecutivly that would load AT with the upper half of the same address.
3271 * The ensuing load upper instructions are ommited. This implies some kind
3272 * of global optimization. We currently only optimize within a single macro.
3273 * For many of the load and store macros if the address is specified as a
3274 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3275 * first load register 'at' with zero and use it as the base register. The
3276 * mips assembler simply uses register $zero. Just one tiny optimization
3281 struct mips_cl_insn
*ip
;
3283 register int treg
, sreg
, dreg
, breg
;
3298 bfd_reloc_code_real_type r
;
3300 int hold_mips_optimize
;
3302 assert (! mips_opts
.mips16
);
3304 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3305 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3306 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3307 mask
= ip
->insn_mo
->mask
;
3309 expr1
.X_op
= O_constant
;
3310 expr1
.X_op_symbol
= NULL
;
3311 expr1
.X_add_symbol
= NULL
;
3312 expr1
.X_add_number
= 1;
3324 mips_emit_delays (true);
3325 ++mips_opts
.noreorder
;
3326 mips_any_noreorder
= 1;
3328 expr1
.X_add_number
= 8;
3329 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3331 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3333 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3334 macro_build ((char *) NULL
, &icnt
, NULL
,
3335 dbl
? "dsub" : "sub",
3336 "d,v,t", dreg
, 0, sreg
);
3338 --mips_opts
.noreorder
;
3359 if (imm_expr
.X_op
== O_constant
3360 && imm_expr
.X_add_number
>= -0x8000
3361 && imm_expr
.X_add_number
< 0x8000)
3363 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3364 (int) BFD_RELOC_LO16
);
3367 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3368 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3387 if (imm_expr
.X_op
== O_constant
3388 && imm_expr
.X_add_number
>= 0
3389 && imm_expr
.X_add_number
< 0x10000)
3391 if (mask
!= M_NOR_I
)
3392 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3393 sreg
, (int) BFD_RELOC_LO16
);
3396 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3397 treg
, sreg
, (int) BFD_RELOC_LO16
);
3398 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3404 load_register (&icnt
, AT
, &imm_expr
, 0);
3405 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3422 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3424 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3428 load_register (&icnt
, AT
, &imm_expr
, 0);
3429 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3437 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3438 likely
? "bgezl" : "bgez",
3444 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3445 likely
? "blezl" : "blez",
3449 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3450 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3451 likely
? "beql" : "beq",
3458 /* check for > max integer */
3459 maxnum
= 0x7fffffff;
3460 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3467 if (imm_expr
.X_op
== O_constant
3468 && imm_expr
.X_add_number
>= maxnum
3469 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3472 /* result is always false */
3475 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3476 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3480 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3486 if (imm_expr
.X_op
!= O_constant
)
3487 as_bad ("Unsupported large constant");
3488 imm_expr
.X_add_number
++;
3492 if (mask
== M_BGEL_I
)
3494 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3496 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3497 likely
? "bgezl" : "bgez",
3501 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3503 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3504 likely
? "bgtzl" : "bgtz",
3508 maxnum
= 0x7fffffff;
3509 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3516 maxnum
= - maxnum
- 1;
3517 if (imm_expr
.X_op
== O_constant
3518 && imm_expr
.X_add_number
<= maxnum
3519 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3522 /* result is always true */
3523 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3524 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3527 set_at (&icnt
, sreg
, 0);
3528 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3529 likely
? "beql" : "beq",
3540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3541 likely
? "beql" : "beq",
3545 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3547 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3548 likely
? "beql" : "beq",
3556 || (mips_opts
.isa
< 3
3557 && imm_expr
.X_op
== O_constant
3558 && imm_expr
.X_add_number
== 0xffffffff))
3560 if (imm_expr
.X_op
!= O_constant
)
3561 as_bad ("Unsupported large constant");
3562 imm_expr
.X_add_number
++;
3566 if (mask
== M_BGEUL_I
)
3568 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3570 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3572 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3573 likely
? "bnel" : "bne",
3577 set_at (&icnt
, sreg
, 1);
3578 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3579 likely
? "beql" : "beq",
3588 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3589 likely
? "bgtzl" : "bgtz",
3595 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3596 likely
? "bltzl" : "bltz",
3600 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3601 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3602 likely
? "bnel" : "bne",
3611 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3612 likely
? "bnel" : "bne",
3618 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3620 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3621 likely
? "bnel" : "bne",
3630 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3631 likely
? "blezl" : "blez",
3637 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3638 likely
? "bgezl" : "bgez",
3642 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3643 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3644 likely
? "beql" : "beq",
3651 maxnum
= 0x7fffffff;
3652 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3659 if (imm_expr
.X_op
== O_constant
3660 && imm_expr
.X_add_number
>= maxnum
3661 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3663 if (imm_expr
.X_op
!= O_constant
)
3664 as_bad ("Unsupported large constant");
3665 imm_expr
.X_add_number
++;
3669 if (mask
== M_BLTL_I
)
3671 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3673 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3674 likely
? "bltzl" : "bltz",
3678 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3680 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3681 likely
? "blezl" : "blez",
3685 set_at (&icnt
, sreg
, 0);
3686 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3687 likely
? "bnel" : "bne",
3696 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3697 likely
? "beql" : "beq",
3703 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3705 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3706 likely
? "beql" : "beq",
3714 || (mips_opts
.isa
< 3
3715 && imm_expr
.X_op
== O_constant
3716 && imm_expr
.X_add_number
== 0xffffffff))
3718 if (imm_expr
.X_op
!= O_constant
)
3719 as_bad ("Unsupported large constant");
3720 imm_expr
.X_add_number
++;
3724 if (mask
== M_BLTUL_I
)
3726 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3728 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3730 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3731 likely
? "beql" : "beq",
3735 set_at (&icnt
, sreg
, 1);
3736 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3737 likely
? "bnel" : "bne",
3746 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3747 likely
? "bltzl" : "bltz",
3753 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3754 likely
? "bgtzl" : "bgtz",
3758 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3759 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3760 likely
? "bnel" : "bne",
3771 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3772 likely
? "bnel" : "bne",
3776 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3778 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3779 likely
? "bnel" : "bne",
3795 as_warn ("Divide by zero.");
3797 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3799 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3803 mips_emit_delays (true);
3804 ++mips_opts
.noreorder
;
3805 mips_any_noreorder
= 1;
3806 macro_build ((char *) NULL
, &icnt
, NULL
,
3807 dbl
? "ddiv" : "div",
3808 "z,s,t", sreg
, treg
);
3810 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3813 expr1
.X_add_number
= 8;
3814 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3815 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3816 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3818 expr1
.X_add_number
= -1;
3819 macro_build ((char *) NULL
, &icnt
, &expr1
,
3820 dbl
? "daddiu" : "addiu",
3821 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3822 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3823 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3826 expr1
.X_add_number
= 1;
3827 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3828 (int) BFD_RELOC_LO16
);
3829 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3834 expr1
.X_add_number
= 0x80000000;
3835 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3836 (int) BFD_RELOC_HI16
);
3839 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3842 expr1
.X_add_number
= 8;
3843 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3844 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3845 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3847 --mips_opts
.noreorder
;
3848 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3887 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3889 as_warn ("Divide by zero.");
3891 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3893 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3896 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3898 if (strcmp (s2
, "mflo") == 0)
3899 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3902 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3905 if (imm_expr
.X_op
== O_constant
3906 && imm_expr
.X_add_number
== -1
3907 && s
[strlen (s
) - 1] != 'u')
3909 if (strcmp (s2
, "mflo") == 0)
3912 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3915 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3919 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3923 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3924 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3925 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3944 mips_emit_delays (true);
3945 ++mips_opts
.noreorder
;
3946 mips_any_noreorder
= 1;
3947 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3949 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3952 expr1
.X_add_number
= 8;
3953 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3954 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3955 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3957 --mips_opts
.noreorder
;
3958 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3964 /* Load the address of a symbol into a register. If breg is not
3965 zero, we then add a base register to it. */
3967 /* When generating embedded PIC code, we permit expressions of
3970 where bar is an address in the .text section. These are used
3971 when getting the addresses of functions. We don't permit
3972 X_add_number to be non-zero, because if the symbol is
3973 external the relaxing code needs to know that any addend is
3974 purely the offset to X_op_symbol. */
3975 if (mips_pic
== EMBEDDED_PIC
3976 && offset_expr
.X_op
== O_subtract
3977 && now_seg
== text_section
3978 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3979 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3980 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3981 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3982 ->sy_value
.X_add_symbol
)
3985 && offset_expr
.X_add_number
== 0)
3987 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3988 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3989 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3990 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3991 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3995 if (offset_expr
.X_op
!= O_symbol
3996 && offset_expr
.X_op
!= O_constant
)
3998 as_bad ("expression too complex");
3999 offset_expr
.X_op
= O_constant
;
4013 if (offset_expr
.X_op
== O_constant
)
4014 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4015 else if (mips_pic
== NO_PIC
)
4017 /* If this is a reference to an GP relative symbol, we want
4018 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4020 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4021 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4022 If we have a constant, we need two instructions anyhow,
4023 so we may as well always use the latter form. */
4024 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4025 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4030 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4031 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4032 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4033 p
= frag_var (rs_machine_dependent
, 8, 0,
4034 RELAX_ENCODE (4, 8, 0, 4, 0,
4035 mips_opts
.warn_about_macros
),
4036 offset_expr
.X_add_symbol
, (offsetT
) 0,
4039 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4042 macro_build (p
, &icnt
, &offset_expr
,
4043 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4044 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4046 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4048 /* If this is a reference to an external symbol, and there
4049 is no constant, we want
4050 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4051 For a local symbol, we want
4052 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4054 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4056 If we have a small constant, and this is a reference to
4057 an external symbol, we want
4058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4060 addiu $tempreg,$tempreg,<constant>
4061 For a local symbol, we want the same instruction
4062 sequence, but we output a BFD_RELOC_LO16 reloc on the
4065 If we have a large constant, and this is a reference to
4066 an external symbol, we want
4067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4068 lui $at,<hiconstant>
4069 addiu $at,$at,<loconstant>
4070 addu $tempreg,$tempreg,$at
4071 For a local symbol, we want the same instruction
4072 sequence, but we output a BFD_RELOC_LO16 reloc on the
4073 addiu instruction. */
4074 expr1
.X_add_number
= offset_expr
.X_add_number
;
4075 offset_expr
.X_add_number
= 0;
4077 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4079 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4080 if (expr1
.X_add_number
== 0)
4088 /* We're going to put in an addu instruction using
4089 tempreg, so we may as well insert the nop right
4091 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4095 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4096 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4098 ? mips_opts
.warn_about_macros
4100 offset_expr
.X_add_symbol
, (offsetT
) 0,
4104 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4107 macro_build (p
, &icnt
, &expr1
,
4108 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4109 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4110 /* FIXME: If breg == 0, and the next instruction uses
4111 $tempreg, then if this variant case is used an extra
4112 nop will be generated. */
4114 else if (expr1
.X_add_number
>= -0x8000
4115 && expr1
.X_add_number
< 0x8000)
4117 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4119 macro_build ((char *) NULL
, &icnt
, &expr1
,
4120 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4121 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4122 (void) frag_var (rs_machine_dependent
, 0, 0,
4123 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4124 offset_expr
.X_add_symbol
, (offsetT
) 0,
4131 /* If we are going to add in a base register, and the
4132 target register and the base register are the same,
4133 then we are using AT as a temporary register. Since
4134 we want to load the constant into AT, we add our
4135 current AT (from the global offset table) and the
4136 register into the register now, and pretend we were
4137 not using a base register. */
4142 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4144 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4145 mips_opts
.isa
< 3 ? "addu" : "daddu",
4146 "d,v,t", treg
, AT
, breg
);
4152 /* Set mips_optimize around the lui instruction to avoid
4153 inserting an unnecessary nop after the lw. */
4154 hold_mips_optimize
= mips_optimize
;
4156 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4157 mips_optimize
= hold_mips_optimize
;
4159 macro_build ((char *) NULL
, &icnt
, &expr1
,
4160 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4161 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4162 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4163 mips_opts
.isa
< 3 ? "addu" : "daddu",
4164 "d,v,t", tempreg
, tempreg
, AT
);
4165 (void) frag_var (rs_machine_dependent
, 0, 0,
4166 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4167 offset_expr
.X_add_symbol
, (offsetT
) 0,
4172 else if (mips_pic
== SVR4_PIC
)
4176 /* This is the large GOT case. If this is a reference to an
4177 external symbol, and there is no constant, we want
4178 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4179 addu $tempreg,$tempreg,$gp
4180 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4181 For a local symbol, we want
4182 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4184 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4186 If we have a small constant, and this is a reference to
4187 an external symbol, we want
4188 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4189 addu $tempreg,$tempreg,$gp
4190 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4192 addiu $tempreg,$tempreg,<constant>
4193 For a local symbol, we want
4194 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4196 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4198 If we have a large constant, and this is a reference to
4199 an external symbol, we want
4200 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4201 addu $tempreg,$tempreg,$gp
4202 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4203 lui $at,<hiconstant>
4204 addiu $at,$at,<loconstant>
4205 addu $tempreg,$tempreg,$at
4206 For a local symbol, we want
4207 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4208 lui $at,<hiconstant>
4209 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4210 addu $tempreg,$tempreg,$at
4212 expr1
.X_add_number
= offset_expr
.X_add_number
;
4213 offset_expr
.X_add_number
= 0;
4215 if (reg_needs_delay (GP
))
4219 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4220 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4221 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4222 mips_opts
.isa
< 3 ? "addu" : "daddu",
4223 "d,v,t", tempreg
, tempreg
, GP
);
4224 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4226 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4228 if (expr1
.X_add_number
== 0)
4236 /* We're going to put in an addu instruction using
4237 tempreg, so we may as well insert the nop right
4239 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4244 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4245 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4248 ? mips_opts
.warn_about_macros
4250 offset_expr
.X_add_symbol
, (offsetT
) 0,
4253 else if (expr1
.X_add_number
>= -0x8000
4254 && expr1
.X_add_number
< 0x8000)
4256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4258 macro_build ((char *) NULL
, &icnt
, &expr1
,
4259 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4260 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4262 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4263 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4265 ? mips_opts
.warn_about_macros
4267 offset_expr
.X_add_symbol
, (offsetT
) 0,
4274 /* If we are going to add in a base register, and the
4275 target register and the base register are the same,
4276 then we are using AT as a temporary register. Since
4277 we want to load the constant into AT, we add our
4278 current AT (from the global offset table) and the
4279 register into the register now, and pretend we were
4280 not using a base register. */
4288 assert (tempreg
== AT
);
4289 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4291 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4292 mips_opts
.isa
< 3 ? "addu" : "daddu",
4293 "d,v,t", treg
, AT
, breg
);
4298 /* Set mips_optimize around the lui instruction to avoid
4299 inserting an unnecessary nop after the lw. */
4300 hold_mips_optimize
= mips_optimize
;
4302 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4303 mips_optimize
= hold_mips_optimize
;
4305 macro_build ((char *) NULL
, &icnt
, &expr1
,
4306 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4307 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4308 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4309 mips_opts
.isa
< 3 ? "addu" : "daddu",
4310 "d,v,t", dreg
, dreg
, AT
);
4312 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4313 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4316 ? mips_opts
.warn_about_macros
4318 offset_expr
.X_add_symbol
, (offsetT
) 0,
4326 /* This is needed because this instruction uses $gp, but
4327 the first instruction on the main stream does not. */
4328 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4331 macro_build (p
, &icnt
, &offset_expr
,
4333 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4335 if (expr1
.X_add_number
>= -0x8000
4336 && expr1
.X_add_number
< 0x8000)
4338 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4340 macro_build (p
, &icnt
, &expr1
,
4341 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4342 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4343 /* FIXME: If add_number is 0, and there was no base
4344 register, the external symbol case ended with a load,
4345 so if the symbol turns out to not be external, and
4346 the next instruction uses tempreg, an unnecessary nop
4347 will be inserted. */
4353 /* We must add in the base register now, as in the
4354 external symbol case. */
4355 assert (tempreg
== AT
);
4356 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4358 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4359 mips_opts
.isa
< 3 ? "addu" : "daddu",
4360 "d,v,t", treg
, AT
, breg
);
4363 /* We set breg to 0 because we have arranged to add
4364 it in in both cases. */
4368 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4370 macro_build (p
, &icnt
, &expr1
,
4371 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4372 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4374 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4375 mips_opts
.isa
< 3 ? "addu" : "daddu",
4376 "d,v,t", tempreg
, tempreg
, AT
);
4380 else if (mips_pic
== EMBEDDED_PIC
)
4383 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4385 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4386 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4387 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4393 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4394 mips_opts
.isa
< 3 ? "addu" : "daddu",
4395 "d,v,t", treg
, tempreg
, breg
);
4403 /* The j instruction may not be used in PIC code, since it
4404 requires an absolute address. We convert it to a b
4406 if (mips_pic
== NO_PIC
)
4407 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4409 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4412 /* The jal instructions must be handled as macros because when
4413 generating PIC code they expand to multi-instruction
4414 sequences. Normally they are simple instructions. */
4419 if (mips_pic
== NO_PIC
4420 || mips_pic
== EMBEDDED_PIC
)
4421 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4423 else if (mips_pic
== SVR4_PIC
)
4425 if (sreg
!= PIC_CALL_REG
)
4426 as_warn ("MIPS PIC call to register other than $25");
4428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4430 if (mips_cprestore_offset
< 0)
4431 as_warn ("No .cprestore pseudo-op used in PIC code");
4434 expr1
.X_add_number
= mips_cprestore_offset
;
4435 macro_build ((char *) NULL
, &icnt
, &expr1
,
4436 mips_opts
.isa
< 3 ? "lw" : "ld",
4437 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4446 if (mips_pic
== NO_PIC
)
4447 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4448 else if (mips_pic
== SVR4_PIC
)
4450 /* If this is a reference to an external symbol, and we are
4451 using a small GOT, we want
4452 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4456 lw $gp,cprestore($sp)
4457 The cprestore value is set using the .cprestore
4458 pseudo-op. If we are using a big GOT, we want
4459 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4461 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4465 lw $gp,cprestore($sp)
4466 If the symbol is not external, we want
4467 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4469 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4472 lw $gp,cprestore($sp) */
4476 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4477 mips_opts
.isa
< 3 ? "lw" : "ld",
4478 "t,o(b)", PIC_CALL_REG
,
4479 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4480 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4482 p
= frag_var (rs_machine_dependent
, 4, 0,
4483 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4484 offset_expr
.X_add_symbol
, (offsetT
) 0,
4491 if (reg_needs_delay (GP
))
4495 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4496 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4497 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4498 mips_opts
.isa
< 3 ? "addu" : "daddu",
4499 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4500 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4501 mips_opts
.isa
< 3 ? "lw" : "ld",
4502 "t,o(b)", PIC_CALL_REG
,
4503 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4504 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4506 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4507 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4509 offset_expr
.X_add_symbol
, (offsetT
) 0,
4513 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4516 macro_build (p
, &icnt
, &offset_expr
,
4517 mips_opts
.isa
< 3 ? "lw" : "ld",
4518 "t,o(b)", PIC_CALL_REG
,
4519 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4521 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4524 macro_build (p
, &icnt
, &offset_expr
,
4525 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4526 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4527 (int) BFD_RELOC_LO16
);
4528 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4529 "jalr", "s", PIC_CALL_REG
);
4530 if (mips_cprestore_offset
< 0)
4531 as_warn ("No .cprestore pseudo-op used in PIC code");
4534 if (mips_opts
.noreorder
)
4535 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4537 expr1
.X_add_number
= mips_cprestore_offset
;
4538 macro_build ((char *) NULL
, &icnt
, &expr1
,
4539 mips_opts
.isa
< 3 ? "lw" : "ld",
4540 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4544 else if (mips_pic
== EMBEDDED_PIC
)
4546 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4547 /* The linker may expand the call to a longer sequence which
4548 uses $at, so we must break rather than return. */
4573 /* Itbl support may require additional care here. */
4578 /* Itbl support may require additional care here. */
4583 /* Itbl support may require additional care here. */
4588 /* Itbl support may require additional care here. */
4601 /* Itbl support may require additional care here. */
4606 /* Itbl support may require additional care here. */
4611 /* Itbl support may require additional care here. */
4631 if (breg
== treg
|| coproc
|| lr
)
4653 /* Itbl support may require additional care here. */
4658 /* Itbl support may require additional care here. */
4663 /* Itbl support may require additional care here. */
4668 /* Itbl support may require additional care here. */
4686 /* Itbl support may require additional care here. */
4690 /* Itbl support may require additional care here. */
4695 /* Itbl support may require additional care here. */
4707 /* Itbl support may require additional care here. */
4708 if (mask
== M_LWC1_AB
4709 || mask
== M_SWC1_AB
4710 || mask
== M_LDC1_AB
4711 || mask
== M_SDC1_AB
4720 if (offset_expr
.X_op
!= O_constant
4721 && offset_expr
.X_op
!= O_symbol
)
4723 as_bad ("expression too complex");
4724 offset_expr
.X_op
= O_constant
;
4727 /* A constant expression in PIC code can be handled just as it
4728 is in non PIC code. */
4729 if (mips_pic
== NO_PIC
4730 || offset_expr
.X_op
== O_constant
)
4732 /* If this is a reference to a GP relative symbol, and there
4733 is no base register, we want
4734 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4735 Otherwise, if there is no base register, we want
4736 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4737 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4738 If we have a constant, we need two instructions anyhow,
4739 so we always use the latter form.
4741 If we have a base register, and this is a reference to a
4742 GP relative symbol, we want
4743 addu $tempreg,$breg,$gp
4744 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4746 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4747 addu $tempreg,$tempreg,$breg
4748 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4749 With a constant we always use the latter case. */
4752 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4753 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4758 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4759 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4760 p
= frag_var (rs_machine_dependent
, 8, 0,
4761 RELAX_ENCODE (4, 8, 0, 4, 0,
4762 (mips_opts
.warn_about_macros
4764 && mips_opts
.noat
))),
4765 offset_expr
.X_add_symbol
, (offsetT
) 0,
4769 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4772 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4773 (int) BFD_RELOC_LO16
, tempreg
);
4777 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4778 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4783 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4784 mips_opts
.isa
< 3 ? "addu" : "daddu",
4785 "d,v,t", tempreg
, breg
, GP
);
4786 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4787 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4788 p
= frag_var (rs_machine_dependent
, 12, 0,
4789 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4790 offset_expr
.X_add_symbol
, (offsetT
) 0,
4793 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4796 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4797 mips_opts
.isa
< 3 ? "addu" : "daddu",
4798 "d,v,t", tempreg
, tempreg
, breg
);
4801 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4802 (int) BFD_RELOC_LO16
, tempreg
);
4805 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4807 /* If this is a reference to an external symbol, we want
4808 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4810 <op> $treg,0($tempreg)
4812 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4814 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4815 <op> $treg,0($tempreg)
4816 If there is a base register, we add it to $tempreg before
4817 the <op>. If there is a constant, we stick it in the
4818 <op> instruction. We don't handle constants larger than
4819 16 bits, because we have no way to load the upper 16 bits
4820 (actually, we could handle them for the subset of cases
4821 in which we are not using $at). */
4822 assert (offset_expr
.X_op
== O_symbol
);
4823 expr1
.X_add_number
= offset_expr
.X_add_number
;
4824 offset_expr
.X_add_number
= 0;
4825 if (expr1
.X_add_number
< -0x8000
4826 || expr1
.X_add_number
>= 0x8000)
4827 as_bad ("PIC code offset overflow (max 16 signed bits)");
4829 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4830 mips_opts
.isa
< 3 ? "lw" : "ld",
4831 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4832 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4833 p
= frag_var (rs_machine_dependent
, 4, 0,
4834 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4835 offset_expr
.X_add_symbol
, (offsetT
) 0,
4837 macro_build (p
, &icnt
, &offset_expr
,
4838 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4839 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4842 mips_opts
.isa
< 3 ? "addu" : "daddu",
4843 "d,v,t", tempreg
, tempreg
, breg
);
4844 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4845 (int) BFD_RELOC_LO16
, tempreg
);
4847 else if (mips_pic
== SVR4_PIC
)
4851 /* If this is a reference to an external symbol, we want
4852 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4853 addu $tempreg,$tempreg,$gp
4854 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4855 <op> $treg,0($tempreg)
4857 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4859 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4860 <op> $treg,0($tempreg)
4861 If there is a base register, we add it to $tempreg before
4862 the <op>. If there is a constant, we stick it in the
4863 <op> instruction. We don't handle constants larger than
4864 16 bits, because we have no way to load the upper 16 bits
4865 (actually, we could handle them for the subset of cases
4866 in which we are not using $at). */
4867 assert (offset_expr
.X_op
== O_symbol
);
4868 expr1
.X_add_number
= offset_expr
.X_add_number
;
4869 offset_expr
.X_add_number
= 0;
4870 if (expr1
.X_add_number
< -0x8000
4871 || expr1
.X_add_number
>= 0x8000)
4872 as_bad ("PIC code offset overflow (max 16 signed bits)");
4873 if (reg_needs_delay (GP
))
4878 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4879 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4880 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4881 mips_opts
.isa
< 3 ? "addu" : "daddu",
4882 "d,v,t", tempreg
, tempreg
, GP
);
4883 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4884 mips_opts
.isa
< 3 ? "lw" : "ld",
4885 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4887 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4888 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4889 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
4892 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4895 macro_build (p
, &icnt
, &offset_expr
,
4896 mips_opts
.isa
< 3 ? "lw" : "ld",
4897 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4899 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4901 macro_build (p
, &icnt
, &offset_expr
,
4902 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4903 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4906 mips_opts
.isa
< 3 ? "addu" : "daddu",
4907 "d,v,t", tempreg
, tempreg
, breg
);
4908 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4909 (int) BFD_RELOC_LO16
, tempreg
);
4911 else if (mips_pic
== EMBEDDED_PIC
)
4913 /* If there is no base register, we want
4914 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4915 If there is a base register, we want
4916 addu $tempreg,$breg,$gp
4917 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4919 assert (offset_expr
.X_op
== O_symbol
);
4922 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4923 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4928 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4929 mips_opts
.isa
< 3 ? "addu" : "daddu",
4930 "d,v,t", tempreg
, breg
, GP
);
4931 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4932 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4945 load_register (&icnt
, treg
, &imm_expr
, 0);
4949 load_register (&icnt
, treg
, &imm_expr
, 1);
4953 if (imm_expr
.X_op
== O_constant
)
4955 load_register (&icnt
, AT
, &imm_expr
, 0);
4956 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4957 "mtc1", "t,G", AT
, treg
);
4962 assert (offset_expr
.X_op
== O_symbol
4963 && strcmp (segment_name (S_GET_SEGMENT
4964 (offset_expr
.X_add_symbol
)),
4966 && offset_expr
.X_add_number
== 0);
4967 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4968 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4973 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
4974 the entire value, and in mips1 mode it is the high order 32
4975 bits of the value and the low order 32 bits are either zero
4976 or in offset_expr. */
4977 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
4979 load_register (&icnt
, treg
, &imm_expr
, mips_opts
.isa
>= 3);
4980 if (mips_opts
.isa
< 3 && treg
!= 31)
4982 if (offset_expr
.X_op
== O_absent
)
4983 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
4987 assert (offset_expr
.X_op
== O_constant
);
4988 load_register (&icnt
, treg
+ 1, &offset_expr
, 0);
4994 /* We know that sym is in the .rdata section. First we get the
4995 upper 16 bits of the address. */
4996 if (mips_pic
== NO_PIC
)
4998 /* FIXME: This won't work for a 64 bit address. */
4999 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5001 else if (mips_pic
== SVR4_PIC
)
5003 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5004 mips_opts
.isa
< 3 ? "lw" : "ld",
5005 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5007 else if (mips_pic
== EMBEDDED_PIC
)
5009 /* For embedded PIC we pick up the entire address off $gp in
5010 a single instruction. */
5011 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5012 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5013 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5014 offset_expr
.X_op
= O_constant
;
5015 offset_expr
.X_add_number
= 0;
5020 /* Now we load the register(s). */
5021 if (mips_opts
.isa
>= 3)
5022 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5023 treg
, (int) BFD_RELOC_LO16
, AT
);
5026 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5027 treg
, (int) BFD_RELOC_LO16
, AT
);
5030 /* FIXME: How in the world do we deal with the possible
5032 offset_expr
.X_add_number
+= 4;
5033 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5034 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5038 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5039 does not become a variant frag. */
5040 frag_wane (frag_now
);
5046 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5047 the entire value, and in mips1 mode it is the high order 32
5048 bits of the value and the low order 32 bits are either zero
5049 or in offset_expr. */
5050 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5052 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5053 if (mips_opts
.isa
>= 3)
5054 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5055 "dmtc1", "t,S", AT
, treg
);
5058 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5059 "mtc1", "t,G", AT
, treg
+ 1);
5060 if (offset_expr
.X_op
== O_absent
)
5061 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5062 "mtc1", "t,G", 0, treg
);
5065 assert (offset_expr
.X_op
== O_constant
);
5066 load_register (&icnt
, AT
, &offset_expr
, 0);
5067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5068 "mtc1", "t,G", AT
, treg
);
5074 assert (offset_expr
.X_op
== O_symbol
5075 && offset_expr
.X_add_number
== 0);
5076 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5077 if (strcmp (s
, ".lit8") == 0)
5079 if (mips_opts
.isa
>= 2)
5081 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5082 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5086 r
= BFD_RELOC_MIPS_LITERAL
;
5091 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5092 if (mips_pic
== SVR4_PIC
)
5093 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5094 mips_opts
.isa
< 3 ? "lw" : "ld",
5095 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5098 /* FIXME: This won't work for a 64 bit address. */
5099 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5102 if (mips_opts
.isa
>= 2)
5104 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5105 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5107 /* To avoid confusion in tc_gen_reloc, we must ensure
5108 that this does not become a variant frag. */
5109 frag_wane (frag_now
);
5120 /* Even on a big endian machine $fn comes before $fn+1. We have
5121 to adjust when loading from memory. */
5124 assert (mips_opts
.isa
< 2);
5125 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5126 target_big_endian
? treg
+ 1 : treg
,
5128 /* FIXME: A possible overflow which I don't know how to deal
5130 offset_expr
.X_add_number
+= 4;
5131 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5132 target_big_endian
? treg
: treg
+ 1,
5135 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5136 does not become a variant frag. */
5137 frag_wane (frag_now
);
5146 * The MIPS assembler seems to check for X_add_number not
5147 * being double aligned and generating:
5150 * addiu at,at,%lo(foo+1)
5153 * But, the resulting address is the same after relocation so why
5154 * generate the extra instruction?
5156 /* Itbl support may require additional care here. */
5158 if (mips_opts
.isa
>= 2)
5169 if (mips_opts
.isa
>= 2)
5177 /* Itbl support may require additional care here. */
5182 if (mips_opts
.isa
>= 3)
5193 if (mips_opts
.isa
>= 3)
5203 if (offset_expr
.X_op
!= O_symbol
5204 && offset_expr
.X_op
!= O_constant
)
5206 as_bad ("expression too complex");
5207 offset_expr
.X_op
= O_constant
;
5210 /* Even on a big endian machine $fn comes before $fn+1. We have
5211 to adjust when loading from memory. We set coproc if we must
5212 load $fn+1 first. */
5213 /* Itbl support may require additional care here. */
5214 if (! target_big_endian
)
5217 if (mips_pic
== NO_PIC
5218 || offset_expr
.X_op
== O_constant
)
5220 /* If this is a reference to a GP relative symbol, we want
5221 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5222 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5223 If we have a base register, we use this
5225 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5226 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5227 If this is not a GP relative symbol, we want
5228 lui $at,<sym> (BFD_RELOC_HI16_S)
5229 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5230 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5231 If there is a base register, we add it to $at after the
5232 lui instruction. If there is a constant, we always use
5234 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5235 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5254 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5255 mips_opts
.isa
< 3 ? "addu" : "daddu",
5256 "d,v,t", AT
, breg
, GP
);
5262 /* Itbl support may require additional care here. */
5263 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5264 coproc
? treg
+ 1 : treg
,
5265 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5266 offset_expr
.X_add_number
+= 4;
5268 /* Set mips_optimize to 2 to avoid inserting an
5270 hold_mips_optimize
= mips_optimize
;
5272 /* Itbl support may require additional care here. */
5273 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5274 coproc
? treg
: treg
+ 1,
5275 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5276 mips_optimize
= hold_mips_optimize
;
5278 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5279 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5280 used_at
&& mips_opts
.noat
),
5281 offset_expr
.X_add_symbol
, (offsetT
) 0,
5284 /* We just generated two relocs. When tc_gen_reloc
5285 handles this case, it will skip the first reloc and
5286 handle the second. The second reloc already has an
5287 extra addend of 4, which we added above. We must
5288 subtract it out, and then subtract another 4 to make
5289 the first reloc come out right. The second reloc
5290 will come out right because we are going to add 4 to
5291 offset_expr when we build its instruction below.
5293 If we have a symbol, then we don't want to include
5294 the offset, because it will wind up being included
5295 when we generate the reloc. */
5297 if (offset_expr
.X_op
== O_constant
)
5298 offset_expr
.X_add_number
-= 8;
5301 offset_expr
.X_add_number
= -4;
5302 offset_expr
.X_op
= O_constant
;
5305 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5310 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5311 mips_opts
.isa
< 3 ? "addu" : "daddu",
5312 "d,v,t", AT
, breg
, AT
);
5316 /* Itbl support may require additional care here. */
5317 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5318 coproc
? treg
+ 1 : treg
,
5319 (int) BFD_RELOC_LO16
, AT
);
5322 /* FIXME: How do we handle overflow here? */
5323 offset_expr
.X_add_number
+= 4;
5324 /* Itbl support may require additional care here. */
5325 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5326 coproc
? treg
: treg
+ 1,
5327 (int) BFD_RELOC_LO16
, AT
);
5329 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5333 /* If this is a reference to an external symbol, we want
5334 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5339 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5341 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5342 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5343 If there is a base register we add it to $at before the
5344 lwc1 instructions. If there is a constant we include it
5345 in the lwc1 instructions. */
5347 expr1
.X_add_number
= offset_expr
.X_add_number
;
5348 offset_expr
.X_add_number
= 0;
5349 if (expr1
.X_add_number
< -0x8000
5350 || expr1
.X_add_number
>= 0x8000 - 4)
5351 as_bad ("PIC code offset overflow (max 16 signed bits)");
5356 frag_grow (24 + off
);
5357 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5358 mips_opts
.isa
< 3 ? "lw" : "ld",
5359 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5360 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5362 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5363 mips_opts
.isa
< 3 ? "addu" : "daddu",
5364 "d,v,t", AT
, breg
, AT
);
5365 /* Itbl support may require additional care here. */
5366 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5367 coproc
? treg
+ 1 : treg
,
5368 (int) BFD_RELOC_LO16
, AT
);
5369 expr1
.X_add_number
+= 4;
5371 /* Set mips_optimize to 2 to avoid inserting an undesired
5373 hold_mips_optimize
= mips_optimize
;
5375 /* Itbl support may require additional care here. */
5376 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5377 coproc
? treg
: treg
+ 1,
5378 (int) BFD_RELOC_LO16
, AT
);
5379 mips_optimize
= hold_mips_optimize
;
5381 (void) frag_var (rs_machine_dependent
, 0, 0,
5382 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5383 offset_expr
.X_add_symbol
, (offsetT
) 0,
5386 else if (mips_pic
== SVR4_PIC
)
5390 /* If this is a reference to an external symbol, we want
5391 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5393 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5398 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5400 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5401 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5402 If there is a base register we add it to $at before the
5403 lwc1 instructions. If there is a constant we include it
5404 in the lwc1 instructions. */
5406 expr1
.X_add_number
= offset_expr
.X_add_number
;
5407 offset_expr
.X_add_number
= 0;
5408 if (expr1
.X_add_number
< -0x8000
5409 || expr1
.X_add_number
>= 0x8000 - 4)
5410 as_bad ("PIC code offset overflow (max 16 signed bits)");
5411 if (reg_needs_delay (GP
))
5420 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5421 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5422 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5423 mips_opts
.isa
< 3 ? "addu" : "daddu",
5424 "d,v,t", AT
, AT
, GP
);
5425 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5426 mips_opts
.isa
< 3 ? "lw" : "ld",
5427 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5431 mips_opts
.isa
< 3 ? "addu" : "daddu",
5432 "d,v,t", AT
, breg
, AT
);
5433 /* Itbl support may require additional care here. */
5434 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5435 coproc
? treg
+ 1 : treg
,
5436 (int) BFD_RELOC_LO16
, AT
);
5437 expr1
.X_add_number
+= 4;
5439 /* Set mips_optimize to 2 to avoid inserting an undesired
5441 hold_mips_optimize
= mips_optimize
;
5443 /* Itbl support may require additional care here. */
5444 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5445 coproc
? treg
: treg
+ 1,
5446 (int) BFD_RELOC_LO16
, AT
);
5447 mips_optimize
= hold_mips_optimize
;
5448 expr1
.X_add_number
-= 4;
5450 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5451 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5452 8 + gpdel
+ off
, 1, 0),
5453 offset_expr
.X_add_symbol
, (offsetT
) 0,
5457 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5460 macro_build (p
, &icnt
, &offset_expr
,
5461 mips_opts
.isa
< 3 ? "lw" : "ld",
5462 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5464 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5468 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5469 mips_opts
.isa
< 3 ? "addu" : "daddu",
5470 "d,v,t", AT
, breg
, AT
);
5473 /* Itbl support may require additional care here. */
5474 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5475 coproc
? treg
+ 1 : treg
,
5476 (int) BFD_RELOC_LO16
, AT
);
5478 expr1
.X_add_number
+= 4;
5480 /* Set mips_optimize to 2 to avoid inserting an undesired
5482 hold_mips_optimize
= mips_optimize
;
5484 /* Itbl support may require additional care here. */
5485 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5486 coproc
? treg
: treg
+ 1,
5487 (int) BFD_RELOC_LO16
, AT
);
5488 mips_optimize
= hold_mips_optimize
;
5490 else if (mips_pic
== EMBEDDED_PIC
)
5492 /* If there is no base register, we use
5493 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5494 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5495 If we have a base register, we use
5497 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5498 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5508 mips_opts
.isa
< 3 ? "addu" : "daddu",
5509 "d,v,t", AT
, breg
, GP
);
5514 /* Itbl support may require additional care here. */
5515 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5516 coproc
? treg
+ 1 : treg
,
5517 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5518 offset_expr
.X_add_number
+= 4;
5519 /* Itbl support may require additional care here. */
5520 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5521 coproc
? treg
: treg
+ 1,
5522 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5538 assert (mips_opts
.isa
< 3);
5539 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5540 (int) BFD_RELOC_LO16
, breg
);
5541 offset_expr
.X_add_number
+= 4;
5542 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5543 (int) BFD_RELOC_LO16
, breg
);
5546 /* New code added to support COPZ instructions.
5547 This code builds table entries out of the macros in mip_opcodes.
5548 R4000 uses interlocks to handle coproc delays.
5549 Other chips (like the R3000) require nops to be inserted for delays.
5551 FIXME: Currently, we require that the user handle delays.
5552 In order to fill delay slots for non-interlocked chips,
5553 we must have a way to specify delays based on the coprocessor.
5554 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5555 What are the side-effects of the cop instruction?
5556 What cache support might we have and what are its effects?
5557 Both coprocessor & memory require delays. how long???
5558 What registers are read/set/modified?
5560 If an itbl is provided to interpret cop instructions,
5561 this knowledge can be encoded in the itbl spec. */
5575 /* For now we just do C (same as Cz). */
5576 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "C");
5579 #ifdef LOSING_COMPILER
5581 /* Try and see if this is a new itbl instruction.
5582 This code builds table entries out of the macros in mip_opcodes.
5583 FIXME: For now we just assemble the expression and pass it's
5584 value along as a 32-bit immediate.
5585 We may want to have the assembler assemble this value,
5586 so that we gain the assembler's knowledge of delay slots,
5588 Would it be more efficient to use mask (id) here? */
5589 if (itbl_have_entries
5590 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5592 s
= ip
->insn_mo
->name
;
5594 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5595 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5602 as_warn ("Macro used $at after \".set noat\"");
5607 struct mips_cl_insn
*ip
;
5609 register int treg
, sreg
, dreg
, breg
;
5624 bfd_reloc_code_real_type r
;
5627 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5628 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5629 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5630 mask
= ip
->insn_mo
->mask
;
5632 expr1
.X_op
= O_constant
;
5633 expr1
.X_op_symbol
= NULL
;
5634 expr1
.X_add_symbol
= NULL
;
5635 expr1
.X_add_number
= 1;
5639 #endif /* LOSING_COMPILER */
5644 macro_build ((char *) NULL
, &icnt
, NULL
,
5645 dbl
? "dmultu" : "multu",
5647 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5653 /* The MIPS assembler some times generates shifts and adds. I'm
5654 not trying to be that fancy. GCC should do this for us
5656 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5657 macro_build ((char *) NULL
, &icnt
, NULL
,
5658 dbl
? "dmult" : "mult",
5660 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5666 mips_emit_delays (true);
5667 ++mips_opts
.noreorder
;
5668 mips_any_noreorder
= 1;
5669 macro_build ((char *) NULL
, &icnt
, NULL
,
5670 dbl
? "dmult" : "mult",
5672 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5673 macro_build ((char *) NULL
, &icnt
, NULL
,
5674 dbl
? "dsra32" : "sra",
5675 "d,w,<", dreg
, dreg
, 31);
5676 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5678 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5681 expr1
.X_add_number
= 8;
5682 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5683 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5684 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5686 --mips_opts
.noreorder
;
5687 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5693 mips_emit_delays (true);
5694 ++mips_opts
.noreorder
;
5695 mips_any_noreorder
= 1;
5696 macro_build ((char *) NULL
, &icnt
, NULL
,
5697 dbl
? "dmultu" : "multu",
5699 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5700 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5702 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5705 expr1
.X_add_number
= 8;
5706 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5707 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5708 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5710 --mips_opts
.noreorder
;
5714 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5715 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5716 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5718 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5722 if (imm_expr
.X_op
!= O_constant
)
5723 as_bad ("rotate count too large");
5724 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5725 (int) (imm_expr
.X_add_number
& 0x1f));
5726 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5727 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5728 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5732 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5733 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5734 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5736 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5740 if (imm_expr
.X_op
!= O_constant
)
5741 as_bad ("rotate count too large");
5742 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5743 (int) (imm_expr
.X_add_number
& 0x1f));
5744 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5745 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5746 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5750 assert (mips_opts
.isa
< 2);
5751 /* Even on a big endian machine $fn comes before $fn+1. We have
5752 to adjust when storing to memory. */
5753 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5754 target_big_endian
? treg
+ 1 : treg
,
5755 (int) BFD_RELOC_LO16
, breg
);
5756 offset_expr
.X_add_number
+= 4;
5757 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5758 target_big_endian
? treg
: treg
+ 1,
5759 (int) BFD_RELOC_LO16
, breg
);
5764 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5765 treg
, (int) BFD_RELOC_LO16
);
5767 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5768 sreg
, (int) BFD_RELOC_LO16
);
5771 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5773 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5774 dreg
, (int) BFD_RELOC_LO16
);
5779 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5781 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5782 sreg
, (int) BFD_RELOC_LO16
);
5787 as_warn ("Instruction %s: result is always false",
5789 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5792 if (imm_expr
.X_op
== O_constant
5793 && imm_expr
.X_add_number
>= 0
5794 && imm_expr
.X_add_number
< 0x10000)
5796 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5797 sreg
, (int) BFD_RELOC_LO16
);
5800 else if (imm_expr
.X_op
== O_constant
5801 && imm_expr
.X_add_number
> -0x8000
5802 && imm_expr
.X_add_number
< 0)
5804 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5805 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5806 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5807 "t,r,j", dreg
, sreg
,
5808 (int) BFD_RELOC_LO16
);
5813 load_register (&icnt
, AT
, &imm_expr
, 0);
5814 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5818 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5819 (int) BFD_RELOC_LO16
);
5824 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5830 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5831 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5832 (int) BFD_RELOC_LO16
);
5835 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5837 if (imm_expr
.X_op
== O_constant
5838 && imm_expr
.X_add_number
>= -0x8000
5839 && imm_expr
.X_add_number
< 0x8000)
5841 macro_build ((char *) NULL
, &icnt
, &expr1
,
5842 mask
== M_SGE_I
? "slti" : "sltiu",
5843 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5848 load_register (&icnt
, AT
, &imm_expr
, 0);
5849 macro_build ((char *) NULL
, &icnt
, NULL
,
5850 mask
== M_SGE_I
? "slt" : "sltu",
5851 "d,v,t", dreg
, sreg
, AT
);
5854 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5855 (int) BFD_RELOC_LO16
);
5860 case M_SGT
: /* sreg > treg <==> treg < sreg */
5866 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5869 case M_SGT_I
: /* sreg > I <==> I < sreg */
5875 load_register (&icnt
, AT
, &imm_expr
, 0);
5876 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5879 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5885 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5886 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5887 (int) BFD_RELOC_LO16
);
5890 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5896 load_register (&icnt
, AT
, &imm_expr
, 0);
5897 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5898 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5899 (int) BFD_RELOC_LO16
);
5903 if (imm_expr
.X_op
== O_constant
5904 && imm_expr
.X_add_number
>= -0x8000
5905 && imm_expr
.X_add_number
< 0x8000)
5907 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5908 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5911 load_register (&icnt
, AT
, &imm_expr
, 0);
5912 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5916 if (imm_expr
.X_op
== O_constant
5917 && imm_expr
.X_add_number
>= -0x8000
5918 && imm_expr
.X_add_number
< 0x8000)
5920 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5921 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5924 load_register (&icnt
, AT
, &imm_expr
, 0);
5925 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5931 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5934 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5938 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5940 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5946 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5948 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5954 as_warn ("Instruction %s: result is always true",
5956 macro_build ((char *) NULL
, &icnt
, &expr1
,
5957 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5958 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5961 if (imm_expr
.X_op
== O_constant
5962 && imm_expr
.X_add_number
>= 0
5963 && imm_expr
.X_add_number
< 0x10000)
5965 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5966 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5969 else if (imm_expr
.X_op
== O_constant
5970 && imm_expr
.X_add_number
> -0x8000
5971 && imm_expr
.X_add_number
< 0)
5973 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5974 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5975 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5976 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5981 load_register (&icnt
, AT
, &imm_expr
, 0);
5982 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5986 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5994 if (imm_expr
.X_op
== O_constant
5995 && imm_expr
.X_add_number
> -0x8000
5996 && imm_expr
.X_add_number
<= 0x8000)
5998 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5999 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6000 dbl
? "daddi" : "addi",
6001 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6004 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6005 macro_build ((char *) NULL
, &icnt
, NULL
,
6006 dbl
? "dsub" : "sub",
6007 "d,v,t", dreg
, sreg
, AT
);
6013 if (imm_expr
.X_op
== O_constant
6014 && imm_expr
.X_add_number
> -0x8000
6015 && imm_expr
.X_add_number
<= 0x8000)
6017 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6018 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6019 dbl
? "daddiu" : "addiu",
6020 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6023 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6024 macro_build ((char *) NULL
, &icnt
, NULL
,
6025 dbl
? "dsubu" : "subu",
6026 "d,v,t", dreg
, sreg
, AT
);
6047 load_register (&icnt
, AT
, &imm_expr
, 0);
6048 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6053 assert (mips_opts
.isa
< 2);
6054 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6055 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6058 * Is the double cfc1 instruction a bug in the mips assembler;
6059 * or is there a reason for it?
6061 mips_emit_delays (true);
6062 ++mips_opts
.noreorder
;
6063 mips_any_noreorder
= 1;
6064 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6065 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6066 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6067 expr1
.X_add_number
= 3;
6068 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6069 (int) BFD_RELOC_LO16
);
6070 expr1
.X_add_number
= 2;
6071 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6072 (int) BFD_RELOC_LO16
);
6073 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6074 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6075 macro_build ((char *) NULL
, &icnt
, NULL
,
6076 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6077 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6078 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6079 --mips_opts
.noreorder
;
6088 if (offset_expr
.X_add_number
>= 0x7fff)
6089 as_bad ("operand overflow");
6090 /* avoid load delay */
6091 if (! target_big_endian
)
6092 offset_expr
.X_add_number
+= 1;
6093 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6094 (int) BFD_RELOC_LO16
, breg
);
6095 if (! target_big_endian
)
6096 offset_expr
.X_add_number
-= 1;
6098 offset_expr
.X_add_number
+= 1;
6099 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6100 (int) BFD_RELOC_LO16
, breg
);
6101 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6102 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6115 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6116 as_bad ("operand overflow");
6117 if (! target_big_endian
)
6118 offset_expr
.X_add_number
+= off
;
6119 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6120 (int) BFD_RELOC_LO16
, breg
);
6121 if (! target_big_endian
)
6122 offset_expr
.X_add_number
-= off
;
6124 offset_expr
.X_add_number
+= off
;
6125 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6126 (int) BFD_RELOC_LO16
, breg
);
6139 load_address (&icnt
, AT
, &offset_expr
);
6141 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6142 mips_opts
.isa
< 3 ? "addu" : "daddu",
6143 "d,v,t", AT
, AT
, breg
);
6144 if (! target_big_endian
)
6145 expr1
.X_add_number
= off
;
6147 expr1
.X_add_number
= 0;
6148 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6149 (int) BFD_RELOC_LO16
, AT
);
6150 if (! target_big_endian
)
6151 expr1
.X_add_number
= 0;
6153 expr1
.X_add_number
= off
;
6154 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6155 (int) BFD_RELOC_LO16
, AT
);
6160 load_address (&icnt
, AT
, &offset_expr
);
6162 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6163 mips_opts
.isa
< 3 ? "addu" : "daddu",
6164 "d,v,t", AT
, AT
, breg
);
6165 if (target_big_endian
)
6166 expr1
.X_add_number
= 0;
6167 macro_build ((char *) NULL
, &icnt
, &expr1
,
6168 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6169 (int) BFD_RELOC_LO16
, AT
);
6170 if (target_big_endian
)
6171 expr1
.X_add_number
= 1;
6173 expr1
.X_add_number
= 0;
6174 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6175 (int) BFD_RELOC_LO16
, AT
);
6176 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6178 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6183 if (offset_expr
.X_add_number
>= 0x7fff)
6184 as_bad ("operand overflow");
6185 if (target_big_endian
)
6186 offset_expr
.X_add_number
+= 1;
6187 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6188 (int) BFD_RELOC_LO16
, breg
);
6189 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6190 if (target_big_endian
)
6191 offset_expr
.X_add_number
-= 1;
6193 offset_expr
.X_add_number
+= 1;
6194 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6195 (int) BFD_RELOC_LO16
, breg
);
6208 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6209 as_bad ("operand overflow");
6210 if (! target_big_endian
)
6211 offset_expr
.X_add_number
+= off
;
6212 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6213 (int) BFD_RELOC_LO16
, breg
);
6214 if (! target_big_endian
)
6215 offset_expr
.X_add_number
-= off
;
6217 offset_expr
.X_add_number
+= off
;
6218 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6219 (int) BFD_RELOC_LO16
, breg
);
6232 load_address (&icnt
, AT
, &offset_expr
);
6234 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6235 mips_opts
.isa
< 3 ? "addu" : "daddu",
6236 "d,v,t", AT
, AT
, breg
);
6237 if (! target_big_endian
)
6238 expr1
.X_add_number
= off
;
6240 expr1
.X_add_number
= 0;
6241 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6242 (int) BFD_RELOC_LO16
, AT
);
6243 if (! target_big_endian
)
6244 expr1
.X_add_number
= 0;
6246 expr1
.X_add_number
= off
;
6247 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6248 (int) BFD_RELOC_LO16
, AT
);
6252 load_address (&icnt
, AT
, &offset_expr
);
6254 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6255 mips_opts
.isa
< 3 ? "addu" : "daddu",
6256 "d,v,t", AT
, AT
, breg
);
6257 if (! target_big_endian
)
6258 expr1
.X_add_number
= 0;
6259 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6260 (int) BFD_RELOC_LO16
, AT
);
6261 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6263 if (! target_big_endian
)
6264 expr1
.X_add_number
= 1;
6266 expr1
.X_add_number
= 0;
6267 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6268 (int) BFD_RELOC_LO16
, AT
);
6269 if (! target_big_endian
)
6270 expr1
.X_add_number
= 0;
6272 expr1
.X_add_number
= 1;
6273 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6274 (int) BFD_RELOC_LO16
, AT
);
6275 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6277 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6282 /* FIXME: Check if this is one of the itbl macros, since they
6283 are added dynamically. */
6284 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6288 as_warn ("Macro used $at after \".set noat\"");
6291 /* Implement macros in mips16 mode. */
6295 struct mips_cl_insn
*ip
;
6298 int xreg
, yreg
, zreg
, tmp
;
6302 const char *s
, *s2
, *s3
;
6304 mask
= ip
->insn_mo
->mask
;
6306 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6307 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6308 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6312 expr1
.X_op
= O_constant
;
6313 expr1
.X_op_symbol
= NULL
;
6314 expr1
.X_add_symbol
= NULL
;
6315 expr1
.X_add_number
= 1;
6334 mips_emit_delays (true);
6335 ++mips_opts
.noreorder
;
6336 mips_any_noreorder
= 1;
6337 macro_build ((char *) NULL
, &icnt
, NULL
,
6338 dbl
? "ddiv" : "div",
6339 "0,x,y", xreg
, yreg
);
6340 expr1
.X_add_number
= 2;
6341 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6342 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6343 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6344 since that causes an overflow. We should do that as well,
6345 but I don't see how to do the comparisons without a temporary
6347 --mips_opts
.noreorder
;
6348 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6367 mips_emit_delays (true);
6368 ++mips_opts
.noreorder
;
6369 mips_any_noreorder
= 1;
6370 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6371 expr1
.X_add_number
= 2;
6372 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6373 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6374 --mips_opts
.noreorder
;
6375 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6381 macro_build ((char *) NULL
, &icnt
, NULL
,
6382 dbl
? "dmultu" : "multu",
6384 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6392 if (imm_expr
.X_op
!= O_constant
)
6393 as_bad ("Unsupported large constant");
6394 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6395 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6396 dbl
? "daddiu" : "addiu",
6397 "y,x,4", yreg
, xreg
);
6401 if (imm_expr
.X_op
!= O_constant
)
6402 as_bad ("Unsupported large constant");
6403 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6404 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6409 if (imm_expr
.X_op
!= O_constant
)
6410 as_bad ("Unsupported large constant");
6411 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6412 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6435 goto do_reverse_branch
;
6439 goto do_reverse_branch
;
6451 goto do_reverse_branch
;
6462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6464 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6491 goto do_addone_branch_i
;
6496 goto do_addone_branch_i
;
6511 goto do_addone_branch_i
;
6518 if (imm_expr
.X_op
!= O_constant
)
6519 as_bad ("Unsupported large constant");
6520 ++imm_expr
.X_add_number
;
6523 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6524 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6528 expr1
.X_add_number
= 0;
6529 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6531 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6532 "move", "y,X", xreg
, yreg
);
6533 expr1
.X_add_number
= 2;
6534 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6535 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6536 "neg", "x,w", xreg
, xreg
);
6540 /* This routine assembles an instruction into its binary format. As a
6541 side effect, it sets one of the global variables imm_reloc or
6542 offset_reloc to the type of relocation to do if one of the operands
6543 is an address expression. */
6548 struct mips_cl_insn
*ip
;
6553 struct mips_opcode
*insn
;
6556 unsigned int lastregno
= 0;
6561 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6566 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6568 insn_error
= "unrecognized opcode";
6577 assert (strcmp (insn
->name
, str
) == 0);
6579 if (insn
->pinfo
== INSN_MACRO
)
6580 insn_isa
= insn
->match
;
6581 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
6583 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
6585 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
6587 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
6592 if (insn_isa
<= mips_opts
.isa
)
6594 else if (insn
->pinfo
== INSN_MACRO
)
6596 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
6597 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
6598 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
6599 /* start-sanitize-r5900 */
6600 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
6601 /* end-sanitize-r5900 */
6602 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
6605 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
6607 /* start-sanitize-r5900 */
6608 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
6610 /* end-sanitize-r5900 */
6617 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6618 && strcmp (insn
->name
, insn
[1].name
) == 0)
6624 || insn_isa
<= mips_opts
.isa
)
6625 insn_error
= "opcode not supported on this processor";
6628 static char buf
[100];
6630 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6637 ip
->insn_opcode
= insn
->match
;
6638 for (args
= insn
->args
;; ++args
)
6644 case '\0': /* end of args */
6657 ip
->insn_opcode
|= lastregno
<< 21;
6662 ip
->insn_opcode
|= lastregno
<< 16;
6666 ip
->insn_opcode
|= lastregno
<< 11;
6672 /* handle optional base register.
6673 Either the base register is omitted or
6674 we must have a left paren. */
6675 /* this is dependent on the next operand specifier
6676 is a 'b' for base register */
6677 assert (args
[1] == 'b');
6681 case ')': /* these must match exactly */
6686 case '<': /* must be at least one digit */
6688 * According to the manual, if the shift amount is greater
6689 * than 31 or less than 0 the the shift amount should be
6690 * mod 32. In reality the mips assembler issues an error.
6691 * We issue a warning and mask out all but the low 5 bits.
6693 my_getExpression (&imm_expr
, s
);
6694 check_absolute_expr (ip
, &imm_expr
);
6695 if ((unsigned long) imm_expr
.X_add_number
> 31)
6697 as_warn ("Improper shift amount (%ld)",
6698 (long) imm_expr
.X_add_number
);
6699 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6701 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6702 imm_expr
.X_op
= O_absent
;
6706 case '>': /* shift amount minus 32 */
6707 my_getExpression (&imm_expr
, s
);
6708 check_absolute_expr (ip
, &imm_expr
);
6709 if ((unsigned long) imm_expr
.X_add_number
< 32
6710 || (unsigned long) imm_expr
.X_add_number
> 63)
6712 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6713 imm_expr
.X_op
= O_absent
;
6717 case 'k': /* cache code */
6718 case 'h': /* prefx code */
6719 my_getExpression (&imm_expr
, s
);
6720 check_absolute_expr (ip
, &imm_expr
);
6721 if ((unsigned long) imm_expr
.X_add_number
> 31)
6723 as_warn ("Invalid value for `%s' (%lu)",
6725 (unsigned long) imm_expr
.X_add_number
);
6726 imm_expr
.X_add_number
&= 0x1f;
6729 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6731 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6732 imm_expr
.X_op
= O_absent
;
6736 case 'c': /* break code */
6737 my_getExpression (&imm_expr
, s
);
6738 check_absolute_expr (ip
, &imm_expr
);
6739 if ((unsigned) imm_expr
.X_add_number
> 1023)
6740 as_warn ("Illegal break code (%ld)",
6741 (long) imm_expr
.X_add_number
);
6742 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6743 imm_expr
.X_op
= O_absent
;
6747 case 'B': /* syscall code */
6748 my_getExpression (&imm_expr
, s
);
6749 check_absolute_expr (ip
, &imm_expr
);
6750 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6751 as_warn ("Illegal syscall code (%ld)",
6752 (long) imm_expr
.X_add_number
);
6753 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6754 imm_expr
.X_op
= O_absent
;
6758 case 'C': /* Coprocessor code */
6759 my_getExpression (&imm_expr
, s
);
6760 check_absolute_expr (ip
, &imm_expr
);
6761 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6763 as_warn ("Coproccesor code > 25 bits (%ld)",
6764 (long) imm_expr
.X_add_number
);
6765 imm_expr
.X_add_number
&= ((1<<25) - 1);
6767 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6768 imm_expr
.X_op
= O_absent
;
6772 case 'b': /* base register */
6773 case 'd': /* destination register */
6774 case 's': /* source register */
6775 case 't': /* target register */
6776 case 'r': /* both target and source */
6777 case 'v': /* both dest and source */
6778 case 'w': /* both dest and target */
6779 case 'E': /* coprocessor target register */
6780 case 'G': /* coprocessor destination register */
6781 case 'x': /* ignore register name */
6782 case 'z': /* must be zero register */
6796 while (isdigit (*s
));
6798 as_bad ("Invalid register number (%d)", regno
);
6800 else if (*args
== 'E' || *args
== 'G')
6804 if (s
[1] == 'f' && s
[2] == 'p')
6809 else if (s
[1] == 's' && s
[2] == 'p')
6814 else if (s
[1] == 'g' && s
[2] == 'p')
6819 else if (s
[1] == 'a' && s
[2] == 't')
6824 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6829 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6834 else if (itbl_have_entries
)
6839 p
= s
+1; /* advance past '$' */
6840 n
= itbl_get_field (&p
); /* n is name */
6842 /* See if this is a register defined in an
6844 r
= itbl_get_reg_val (n
);
6847 /* Get_field advances to the start of
6848 the next field, so we need to back
6849 rack to the end of the last field. */
6853 s
= strchr (s
,'\0');
6866 as_warn ("Used $at without \".set noat\"");
6872 if (c
== 'r' || c
== 'v' || c
== 'w')
6879 /* 'z' only matches $0. */
6880 if (c
== 'z' && regno
!= 0)
6883 /* Now that we have assembled one operand, we use the args string
6884 * to figure out where it goes in the instruction. */
6891 ip
->insn_opcode
|= regno
<< 21;
6895 ip
->insn_opcode
|= regno
<< 11;
6900 ip
->insn_opcode
|= regno
<< 16;
6903 /* This case exists because on the r3000 trunc
6904 expands into a macro which requires a gp
6905 register. On the r6000 or r4000 it is
6906 assembled into a single instruction which
6907 ignores the register. Thus the insn version
6908 is MIPS_ISA2 and uses 'x', and the macro
6909 version is MIPS_ISA1 and uses 't'. */
6912 /* This case is for the div instruction, which
6913 acts differently if the destination argument
6914 is $0. This only matches $0, and is checked
6915 outside the switch. */
6918 /* Itbl operand; not yet implemented. FIXME ?? */
6920 /* What about all other operands like 'i', which
6921 can be specified in the opcode table? */
6931 ip
->insn_opcode
|= lastregno
<< 21;
6934 ip
->insn_opcode
|= lastregno
<< 16;
6939 case 'D': /* floating point destination register */
6940 case 'S': /* floating point source register */
6941 case 'T': /* floating point target register */
6942 case 'R': /* floating point source register */
6946 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6956 while (isdigit (*s
));
6959 as_bad ("Invalid float register number (%d)", regno
);
6961 if ((regno
& 1) != 0
6962 && mips_opts
.isa
< 3
6963 && ! (strcmp (str
, "mtc1") == 0
6964 || strcmp (str
, "mfc1") == 0
6965 || strcmp (str
, "lwc1") == 0
6966 || strcmp (str
, "swc1") == 0
6967 || strcmp (str
, "l.s") == 0
6968 || strcmp (str
, "s.s") == 0))
6969 as_warn ("Float register should be even, was %d",
6977 if (c
== 'V' || c
== 'W')
6987 ip
->insn_opcode
|= regno
<< 6;
6991 ip
->insn_opcode
|= regno
<< 11;
6995 ip
->insn_opcode
|= regno
<< 16;
6998 ip
->insn_opcode
|= regno
<< 21;
7007 ip
->insn_opcode
|= lastregno
<< 11;
7010 ip
->insn_opcode
|= lastregno
<< 16;
7016 my_getExpression (&imm_expr
, s
);
7017 if (imm_expr
.X_op
!= O_big
7018 && imm_expr
.X_op
!= O_constant
)
7019 insn_error
= "absolute expression required";
7024 my_getExpression (&offset_expr
, s
);
7025 imm_reloc
= BFD_RELOC_32
;
7037 unsigned char temp
[8];
7039 unsigned int length
;
7044 /* These only appear as the last operand in an
7045 instruction, and every instruction that accepts
7046 them in any variant accepts them in all variants.
7047 This means we don't have to worry about backing out
7048 any changes if the instruction does not match.
7050 The difference between them is the size of the
7051 floating point constant and where it goes. For 'F'
7052 and 'L' the constant is 64 bits; for 'f' and 'l' it
7053 is 32 bits. Where the constant is placed is based
7054 on how the MIPS assembler does things:
7057 f -- immediate value
7060 The .lit4 and .lit8 sections are only used if
7061 permitted by the -G argument.
7063 When generating embedded PIC code, we use the
7064 .lit8 section but not the .lit4 section (we can do
7065 .lit4 inline easily; we need to put .lit8
7066 somewhere in the data segment, and using .lit8
7067 permits the linker to eventually combine identical
7070 f64
= *args
== 'F' || *args
== 'L';
7072 save_in
= input_line_pointer
;
7073 input_line_pointer
= s
;
7074 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7076 s
= input_line_pointer
;
7077 input_line_pointer
= save_in
;
7078 if (err
!= NULL
&& *err
!= '\0')
7080 as_bad ("Bad floating point constant: %s", err
);
7081 memset (temp
, '\0', sizeof temp
);
7082 length
= f64
? 8 : 4;
7085 assert (length
== (f64
? 8 : 4));
7089 && (! USE_GLOBAL_POINTER_OPT
7090 || mips_pic
== EMBEDDED_PIC
7091 || g_switch_value
< 4
7092 || (temp
[0] == 0 && temp
[1] == 0)
7093 || (temp
[2] == 0 && temp
[3] == 0))))
7095 imm_expr
.X_op
= O_constant
;
7096 if (! target_big_endian
)
7097 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7099 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7102 && ((temp
[0] == 0 && temp
[1] == 0)
7103 || (temp
[2] == 0 && temp
[3] == 0))
7104 && ((temp
[4] == 0 && temp
[5] == 0)
7105 || (temp
[6] == 0 && temp
[7] == 0)))
7107 /* The value is simple enough to load with a
7108 couple of instructions. In mips1 mode, set
7109 imm_expr to the high order 32 bits and
7110 offset_expr to the low order 32 bits.
7111 Otherwise, set imm_expr to the entire 64 bit
7113 if (mips_opts
.isa
< 3)
7115 imm_expr
.X_op
= O_constant
;
7116 offset_expr
.X_op
= O_constant
;
7117 if (! target_big_endian
)
7119 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7120 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7124 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7125 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7127 if (offset_expr
.X_add_number
== 0)
7128 offset_expr
.X_op
= O_absent
;
7130 else if (sizeof (imm_expr
.X_add_number
) > 4)
7132 imm_expr
.X_op
= O_constant
;
7133 if (! target_big_endian
)
7134 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7136 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7140 imm_expr
.X_op
= O_big
;
7141 imm_expr
.X_add_number
= 4;
7142 if (! target_big_endian
)
7144 generic_bignum
[0] = bfd_getl16 (temp
);
7145 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7146 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7147 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7151 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7152 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7153 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7154 generic_bignum
[3] = bfd_getb16 (temp
);
7160 const char *newname
;
7163 /* Switch to the right section. */
7165 subseg
= now_subseg
;
7168 default: /* unused default case avoids warnings. */
7170 newname
= RDATA_SECTION_NAME
;
7171 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7175 newname
= RDATA_SECTION_NAME
;
7178 assert (!USE_GLOBAL_POINTER_OPT
7179 || g_switch_value
>= 4);
7183 new_seg
= subseg_new (newname
, (subsegT
) 0);
7184 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7185 bfd_set_section_flags (stdoutput
, new_seg
,
7190 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7191 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7192 && strcmp (TARGET_OS
, "elf") != 0)
7193 record_alignment (new_seg
, 4);
7195 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7197 as_bad ("Can't use floating point insn in this section");
7199 /* Set the argument to the current address in the
7201 offset_expr
.X_op
= O_symbol
;
7202 offset_expr
.X_add_symbol
=
7203 symbol_new ("L0\001", now_seg
,
7204 (valueT
) frag_now_fix (), frag_now
);
7205 offset_expr
.X_add_number
= 0;
7207 /* Put the floating point number into the section. */
7208 p
= frag_more ((int) length
);
7209 memcpy (p
, temp
, length
);
7211 /* Switch back to the original section. */
7212 subseg_set (seg
, subseg
);
7217 case 'i': /* 16 bit unsigned immediate */
7218 case 'j': /* 16 bit signed immediate */
7219 imm_reloc
= BFD_RELOC_LO16
;
7220 c
= my_getSmallExpression (&imm_expr
, s
);
7225 if (imm_expr
.X_op
== O_constant
)
7226 imm_expr
.X_add_number
=
7227 (imm_expr
.X_add_number
>> 16) & 0xffff;
7230 imm_reloc
= BFD_RELOC_HI16_S
;
7231 imm_unmatched_hi
= true;
7234 imm_reloc
= BFD_RELOC_HI16
;
7239 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7240 || ((imm_expr
.X_add_number
< 0
7241 || imm_expr
.X_add_number
>= 0x10000)
7242 && imm_expr
.X_op
== O_constant
))
7244 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7245 !strcmp (insn
->name
, insn
[1].name
))
7247 if (imm_expr
.X_op
!= O_constant
7248 && imm_expr
.X_op
!= O_big
)
7249 insn_error
= "absolute expression required";
7251 as_bad ("16 bit expression not in range 0..65535");
7259 /* The upper bound should be 0x8000, but
7260 unfortunately the MIPS assembler accepts numbers
7261 from 0x8000 to 0xffff and sign extends them, and
7262 we want to be compatible. We only permit this
7263 extended range for an instruction which does not
7264 provide any further alternates, since those
7265 alternates may handle other cases. People should
7266 use the numbers they mean, rather than relying on
7267 a mysterious sign extension. */
7268 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7269 strcmp (insn
->name
, insn
[1].name
) == 0);
7274 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7275 || ((imm_expr
.X_add_number
< -0x8000
7276 || imm_expr
.X_add_number
>= max
)
7277 && imm_expr
.X_op
== O_constant
)
7279 && imm_expr
.X_add_number
< 0
7280 && mips_opts
.isa
>= 3
7281 && imm_expr
.X_unsigned
7282 && sizeof (imm_expr
.X_add_number
) <= 4))
7286 if (imm_expr
.X_op
!= O_constant
7287 && imm_expr
.X_op
!= O_big
)
7288 insn_error
= "absolute expression required";
7290 as_bad ("16 bit expression not in range -32768..32767");
7296 case 'o': /* 16 bit offset */
7297 c
= my_getSmallExpression (&offset_expr
, s
);
7299 /* If this value won't fit into a 16 bit offset, then go
7300 find a macro that will generate the 32 bit offset
7301 code pattern. As a special hack, we accept the
7302 difference of two local symbols as a constant. This
7303 is required to suppose embedded PIC switches, which
7304 use an instruction which looks like
7305 lw $4,$L12-$LS12($4)
7306 The problem with handling this in a more general
7307 fashion is that the macro function doesn't expect to
7308 see anything which can be handled in a single
7309 constant instruction. */
7311 && (offset_expr
.X_op
!= O_constant
7312 || offset_expr
.X_add_number
>= 0x8000
7313 || offset_expr
.X_add_number
< -0x8000)
7314 && (mips_pic
!= EMBEDDED_PIC
7315 || offset_expr
.X_op
!= O_subtract
7316 || now_seg
!= text_section
7317 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7321 offset_reloc
= BFD_RELOC_LO16
;
7322 if (c
== 'h' || c
== 'H')
7324 assert (offset_expr
.X_op
== O_constant
);
7325 offset_expr
.X_add_number
=
7326 (offset_expr
.X_add_number
>> 16) & 0xffff;
7331 case 'p': /* pc relative offset */
7332 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7333 my_getExpression (&offset_expr
, s
);
7337 case 'u': /* upper 16 bits */
7338 c
= my_getSmallExpression (&imm_expr
, s
);
7339 if (imm_expr
.X_op
== O_constant
7340 && (imm_expr
.X_add_number
< 0
7341 || imm_expr
.X_add_number
>= 0x10000))
7342 as_bad ("lui expression not in range 0..65535");
7343 imm_reloc
= BFD_RELOC_LO16
;
7348 if (imm_expr
.X_op
== O_constant
)
7349 imm_expr
.X_add_number
=
7350 (imm_expr
.X_add_number
>> 16) & 0xffff;
7353 imm_reloc
= BFD_RELOC_HI16_S
;
7354 imm_unmatched_hi
= true;
7357 imm_reloc
= BFD_RELOC_HI16
;
7363 case 'a': /* 26 bit address */
7364 my_getExpression (&offset_expr
, s
);
7366 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7369 case 'N': /* 3 bit branch condition code */
7370 case 'M': /* 3 bit compare condition code */
7371 if (strncmp (s
, "$fcc", 4) != 0)
7381 while (isdigit (*s
));
7383 as_bad ("invalid condition code register $fcc%d", regno
);
7385 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7387 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7391 fprintf (stderr
, "bad char = '%c'\n", *args
);
7396 /* Args don't match. */
7397 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7398 !strcmp (insn
->name
, insn
[1].name
))
7404 insn_error
= "illegal operands";
7409 /* This routine assembles an instruction into its binary format when
7410 assembling for the mips16. As a side effect, it sets one of the
7411 global variables imm_reloc or offset_reloc to the type of
7412 relocation to do if one of the operands is an address expression.
7413 It also sets mips16_small and mips16_ext if the user explicitly
7414 requested a small or extended instruction. */
7419 struct mips_cl_insn
*ip
;
7423 struct mips_opcode
*insn
;
7426 unsigned int lastregno
= 0;
7431 mips16_small
= false;
7434 for (s
= str
; islower (*s
); ++s
)
7446 if (s
[1] == 't' && s
[2] == ' ')
7449 mips16_small
= true;
7453 else if (s
[1] == 'e' && s
[2] == ' ')
7462 insn_error
= "unknown opcode";
7466 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7467 mips16_small
= true;
7469 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7471 insn_error
= "unrecognized opcode";
7478 assert (strcmp (insn
->name
, str
) == 0);
7481 ip
->insn_opcode
= insn
->match
;
7482 ip
->use_extend
= false;
7483 imm_expr
.X_op
= O_absent
;
7484 imm_reloc
= BFD_RELOC_UNUSED
;
7485 offset_expr
.X_op
= O_absent
;
7486 offset_reloc
= BFD_RELOC_UNUSED
;
7487 for (args
= insn
->args
; 1; ++args
)
7494 /* In this switch statement we call break if we did not find
7495 a match, continue if we did find a match, or return if we
7504 /* Stuff the immediate value in now, if we can. */
7505 if (imm_expr
.X_op
== O_constant
7506 && imm_reloc
> BFD_RELOC_UNUSED
7507 && insn
->pinfo
!= INSN_MACRO
)
7509 mips16_immed ((char *) NULL
, 0,
7510 imm_reloc
- BFD_RELOC_UNUSED
,
7511 imm_expr
.X_add_number
, true, mips16_small
,
7512 mips16_ext
, &ip
->insn_opcode
,
7513 &ip
->use_extend
, &ip
->extend
);
7514 imm_expr
.X_op
= O_absent
;
7515 imm_reloc
= BFD_RELOC_UNUSED
;
7529 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7532 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7548 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7550 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7577 while (isdigit (*s
));
7580 as_bad ("invalid register number (%d)", regno
);
7586 if (s
[1] == 'f' && s
[2] == 'p')
7591 else if (s
[1] == 's' && s
[2] == 'p')
7596 else if (s
[1] == 'g' && s
[2] == 'p')
7601 else if (s
[1] == 'a' && s
[2] == 't')
7606 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7611 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7624 if (c
== 'v' || c
== 'w')
7626 regno
= mips16_to_32_reg_map
[lastregno
];
7640 regno
= mips32_to_16_reg_map
[regno
];
7645 regno
= ILLEGAL_REG
;
7650 regno
= ILLEGAL_REG
;
7655 regno
= ILLEGAL_REG
;
7660 if (regno
== AT
&& ! mips_opts
.noat
)
7661 as_warn ("used $at without \".set noat\"");
7668 if (regno
== ILLEGAL_REG
)
7675 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7679 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7682 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7685 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7691 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7694 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7695 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7705 if (strncmp (s
, "$pc", 3) == 0)
7729 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7731 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7732 and generate the appropriate reloc. If the text
7733 inside %gprel is not a symbol name with an
7734 optional offset, then we generate a normal reloc
7735 and will probably fail later. */
7736 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7737 if (imm_expr
.X_op
== O_symbol
)
7740 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7742 ip
->use_extend
= true;
7749 /* Just pick up a normal expression. */
7750 my_getExpression (&imm_expr
, s
);
7753 if (imm_expr
.X_op
== O_register
)
7755 /* What we thought was an expression turned out to
7758 if (s
[0] == '(' && args
[1] == '(')
7760 /* It looks like the expression was omitted
7761 before a register indirection, which means
7762 that the expression is implicitly zero. We
7763 still set up imm_expr, so that we handle
7764 explicit extensions correctly. */
7765 imm_expr
.X_op
= O_constant
;
7766 imm_expr
.X_add_number
= 0;
7767 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7774 /* We need to relax this instruction. */
7775 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7784 /* We use offset_reloc rather than imm_reloc for the PC
7785 relative operands. This lets macros with both
7786 immediate and address operands work correctly. */
7787 my_getExpression (&offset_expr
, s
);
7789 if (offset_expr
.X_op
== O_register
)
7792 /* We need to relax this instruction. */
7793 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7797 case '6': /* break code */
7798 my_getExpression (&imm_expr
, s
);
7799 check_absolute_expr (ip
, &imm_expr
);
7800 if ((unsigned long) imm_expr
.X_add_number
> 63)
7802 as_warn ("Invalid value for `%s' (%lu)",
7804 (unsigned long) imm_expr
.X_add_number
);
7805 imm_expr
.X_add_number
&= 0x3f;
7807 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7808 imm_expr
.X_op
= O_absent
;
7812 case 'a': /* 26 bit address */
7813 my_getExpression (&offset_expr
, s
);
7815 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7816 ip
->insn_opcode
<<= 16;
7819 case 'l': /* register list for entry macro */
7820 case 'L': /* register list for exit macro */
7830 int freg
, reg1
, reg2
;
7832 while (*s
== ' ' || *s
== ',')
7836 as_bad ("can't parse register list");
7848 while (isdigit (*s
))
7870 as_bad ("invalid register list");
7875 while (isdigit (*s
))
7882 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7887 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7892 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7893 mask
|= (reg2
- 3) << 3;
7894 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7895 mask
|= (reg2
- 15) << 1;
7896 else if (reg1
== 31 && reg2
== 31)
7900 as_bad ("invalid register list");
7904 /* The mask is filled in in the opcode table for the
7905 benefit of the disassembler. We remove it before
7906 applying the actual mask. */
7907 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7908 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7912 case 'e': /* extend code */
7913 my_getExpression (&imm_expr
, s
);
7914 check_absolute_expr (ip
, &imm_expr
);
7915 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
7917 as_warn ("Invalid value for `%s' (%lu)",
7919 (unsigned long) imm_expr
.X_add_number
);
7920 imm_expr
.X_add_number
&= 0x7ff;
7922 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7923 imm_expr
.X_op
= O_absent
;
7933 /* Args don't match. */
7934 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7935 strcmp (insn
->name
, insn
[1].name
) == 0)
7942 insn_error
= "illegal operands";
7948 /* This structure holds information we know about a mips16 immediate
7951 struct mips16_immed_operand
7953 /* The type code used in the argument string in the opcode table. */
7955 /* The number of bits in the short form of the opcode. */
7957 /* The number of bits in the extended form of the opcode. */
7959 /* The amount by which the short form is shifted when it is used;
7960 for example, the sw instruction has a shift count of 2. */
7962 /* The amount by which the short form is shifted when it is stored
7963 into the instruction code. */
7965 /* Non-zero if the short form is unsigned. */
7967 /* Non-zero if the extended form is unsigned. */
7969 /* Non-zero if the value is PC relative. */
7973 /* The mips16 immediate operand types. */
7975 static const struct mips16_immed_operand mips16_immed_operands
[] =
7977 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7978 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7979 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7980 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7981 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7982 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7983 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7984 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7985 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7986 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7987 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7988 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7989 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7990 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7991 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7992 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7993 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7994 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7995 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7996 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7997 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8000 #define MIPS16_NUM_IMMED \
8001 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8003 /* Handle a mips16 instruction with an immediate value. This or's the
8004 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8005 whether an extended value is needed; if one is needed, it sets
8006 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8007 If SMALL is true, an unextended opcode was explicitly requested.
8008 If EXT is true, an extended opcode was explicitly requested. If
8009 WARN is true, warn if EXT does not match reality. */
8012 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8021 unsigned long *insn
;
8022 boolean
*use_extend
;
8023 unsigned short *extend
;
8025 register const struct mips16_immed_operand
*op
;
8026 int mintiny
, maxtiny
;
8029 op
= mips16_immed_operands
;
8030 while (op
->type
!= type
)
8033 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8038 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8041 maxtiny
= 1 << op
->nbits
;
8046 maxtiny
= (1 << op
->nbits
) - 1;
8051 mintiny
= - (1 << (op
->nbits
- 1));
8052 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8055 /* Branch offsets have an implicit 0 in the lowest bit. */
8056 if (type
== 'p' || type
== 'q')
8059 if ((val
& ((1 << op
->shift
) - 1)) != 0
8060 || val
< (mintiny
<< op
->shift
)
8061 || val
> (maxtiny
<< op
->shift
))
8066 if (warn
&& ext
&& ! needext
)
8067 as_warn_where (file
, line
, "extended operand requested but not required");
8068 if (small
&& needext
)
8069 as_bad_where (file
, line
, "invalid unextended operand value");
8071 if (small
|| (! ext
&& ! needext
))
8075 *use_extend
= false;
8076 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8077 insnval
<<= op
->op_shift
;
8082 long minext
, maxext
;
8088 maxext
= (1 << op
->extbits
) - 1;
8092 minext
= - (1 << (op
->extbits
- 1));
8093 maxext
= (1 << (op
->extbits
- 1)) - 1;
8095 if (val
< minext
|| val
> maxext
)
8096 as_bad_where (file
, line
,
8097 "operand value out of range for instruction");
8100 if (op
->extbits
== 16)
8102 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8105 else if (op
->extbits
== 15)
8107 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8112 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8116 *extend
= (unsigned short) extval
;
8125 my_getSmallExpression (ep
, str
)
8136 ((str
[1] == 'h' && str
[2] == 'i')
8137 || (str
[1] == 'H' && str
[2] == 'I')
8138 || (str
[1] == 'l' && str
[2] == 'o'))
8150 * A small expression may be followed by a base register.
8151 * Scan to the end of this operand, and then back over a possible
8152 * base register. Then scan the small expression up to that
8153 * point. (Based on code in sparc.c...)
8155 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8157 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8159 if (isdigit (sp
[-2]))
8161 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8163 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8169 else if (sp
- 5 >= str
8172 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8173 || (sp
[-3] == 's' && sp
[-2] == 'p')
8174 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8175 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8181 /* no expression means zero offset */
8184 /* %xx(reg) is an error */
8185 ep
->X_op
= O_absent
;
8190 ep
->X_op
= O_constant
;
8193 ep
->X_add_symbol
= NULL
;
8194 ep
->X_op_symbol
= NULL
;
8195 ep
->X_add_number
= 0;
8200 my_getExpression (ep
, str
);
8207 my_getExpression (ep
, str
);
8208 return c
; /* => %hi or %lo encountered */
8212 my_getExpression (ep
, str
)
8218 save_in
= input_line_pointer
;
8219 input_line_pointer
= str
;
8221 expr_end
= input_line_pointer
;
8222 input_line_pointer
= save_in
;
8224 /* If we are in mips16 mode, and this is an expression based on `.',
8225 then we bump the value of the symbol by 1 since that is how other
8226 text symbols are handled. We don't bother to handle complex
8227 expressions, just `.' plus or minus a constant. */
8228 if (mips_opts
.mips16
8229 && ep
->X_op
== O_symbol
8230 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8231 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8232 && ep
->X_add_symbol
->sy_frag
== frag_now
8233 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
8234 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
8235 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8238 /* Turn a string in input_line_pointer into a floating point constant
8239 of type type, and store the appropriate bytes in *litP. The number
8240 of LITTLENUMS emitted is stored in *sizeP . An error message is
8241 returned, or NULL on OK. */
8244 md_atof (type
, litP
, sizeP
)
8250 LITTLENUM_TYPE words
[4];
8266 return "bad call to md_atof";
8269 t
= atof_ieee (input_line_pointer
, type
, words
);
8271 input_line_pointer
= t
;
8275 if (! target_big_endian
)
8277 for (i
= prec
- 1; i
>= 0; i
--)
8279 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8285 for (i
= 0; i
< prec
; i
++)
8287 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8296 md_number_to_chars (buf
, val
, n
)
8301 if (target_big_endian
)
8302 number_to_chars_bigendian (buf
, val
, n
);
8304 number_to_chars_littleendian (buf
, val
, n
);
8307 CONST
char *md_shortopts
= "O::g::G:";
8309 struct option md_longopts
[] = {
8310 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8311 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8312 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8313 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8314 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8315 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8316 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8317 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8318 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8319 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8320 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8321 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8322 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8323 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8324 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8325 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8326 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8327 {"break", no_argument
, NULL
, OPTION_BREAK
},
8328 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8329 #define OPTION_EB (OPTION_MD_BASE + 11)
8330 {"EB", no_argument
, NULL
, OPTION_EB
},
8331 #define OPTION_EL (OPTION_MD_BASE + 12)
8332 {"EL", no_argument
, NULL
, OPTION_EL
},
8333 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8334 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8335 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8336 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8337 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8338 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8339 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8340 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8341 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8342 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8343 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8344 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8345 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8346 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8347 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8348 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8349 /* start-sanitize-r5900 */
8350 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8351 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8352 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8353 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8354 /* end-sanitize-r5900 */
8355 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8356 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8357 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8358 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8360 /* start-sanitize-tx19 */
8361 {"m1900", no_argument
, NULL
, OPTION_M3900
},
8362 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
8363 /* end-sanitize-tx19 */
8365 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8366 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8367 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8368 #define OPTION_32 (OPTION_MD_BASE + 20)
8369 #define OPTION_64 (OPTION_MD_BASE + 21)
8371 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8372 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8373 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8374 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8375 {"32", no_argument
, NULL
, OPTION_32
},
8376 {"64", no_argument
, NULL
, OPTION_64
},
8379 {NULL
, no_argument
, NULL
, 0}
8381 size_t md_longopts_size
= sizeof(md_longopts
);
8384 md_parse_option (c
, arg
)
8399 target_big_endian
= 1;
8403 target_big_endian
= 0;
8407 if (arg
&& arg
[1] == '0')
8417 mips_debug
= atoi (arg
);
8418 /* When the MIPS assembler sees -g or -g2, it does not do
8419 optimizations which limit full symbolic debugging. We take
8420 that to be equivalent to -O0. */
8421 if (mips_debug
== 2)
8453 /* Identify the processor type */
8455 if (strcmp (p
, "default") == 0
8456 || strcmp (p
, "DEFAULT") == 0)
8462 /* We need to cope with the various "vr" prefixes for the 4300
8464 if (*p
== 'v' || *p
== 'V')
8470 if (*p
== 'r' || *p
== 'R')
8477 if (strcmp (p
, "10000") == 0
8478 || strcmp (p
, "10k") == 0
8479 || strcmp (p
, "10K") == 0)
8481 /* start-sanitize-tx19 */
8482 else if (strcmp (p
, "1900") == 0)
8484 /* end-sanitize-tx19 */
8488 if (strcmp (p
, "2000") == 0
8489 || strcmp (p
, "2k") == 0
8490 || strcmp (p
, "2K") == 0)
8495 if (strcmp (p
, "3000") == 0
8496 || strcmp (p
, "3k") == 0
8497 || strcmp (p
, "3K") == 0)
8499 else if (strcmp (p
, "3900") == 0)
8504 if (strcmp (p
, "4000") == 0
8505 || strcmp (p
, "4k") == 0
8506 || strcmp (p
, "4K") == 0)
8508 else if (strcmp (p
, "4100") == 0)
8514 else if (strcmp (p
, "4300") == 0)
8516 else if (strcmp (p
, "4400") == 0)
8518 else if (strcmp (p
, "4600") == 0)
8520 else if (strcmp (p
, "4650") == 0)
8526 else if (strcmp (p
, "4010") == 0)
8535 if (strcmp (p
, "5000") == 0
8536 || strcmp (p
, "5k") == 0
8537 || strcmp (p
, "5K") == 0)
8539 /* start-sanitize-r5900 */
8540 else if (strcmp (p
, "5900") == 0)
8542 /* end-sanitize-r5900 */
8546 if (strcmp (p
, "6000") == 0
8547 || strcmp (p
, "6k") == 0
8548 || strcmp (p
, "6K") == 0)
8553 if (strcmp (p
, "8000") == 0
8554 || strcmp (p
, "8k") == 0
8555 || strcmp (p
, "8K") == 0)
8560 if (strcmp (p
, "orion") == 0)
8565 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8567 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8573 as_bad ("invalid architecture -mcpu=%s", arg
);
8584 case OPTION_NO_M4650
:
8592 case OPTION_NO_M4010
:
8600 case OPTION_NO_M4100
:
8604 /* start-sanitize-r5900 */
8609 case OPTION_NO_M5900
:
8612 /* end-sanitize-r5900 */
8618 case OPTION_NO_M3900
:
8623 mips_opts
.mips16
= 1;
8624 mips_no_prev_insn (false);
8627 case OPTION_NO_MIPS16
:
8628 mips_opts
.mips16
= 0;
8629 mips_no_prev_insn (false);
8632 case OPTION_MEMBEDDED_PIC
:
8633 mips_pic
= EMBEDDED_PIC
;
8634 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8636 as_bad ("-G may not be used with embedded PIC code");
8639 g_switch_value
= 0x7fffffff;
8642 /* When generating ELF code, we permit -KPIC and -call_shared to
8643 select SVR4_PIC, and -non_shared to select no PIC. This is
8644 intended to be compatible with Irix 5. */
8645 case OPTION_CALL_SHARED
:
8646 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8648 as_bad ("-call_shared is supported only for ELF format");
8651 mips_pic
= SVR4_PIC
;
8652 if (g_switch_seen
&& g_switch_value
!= 0)
8654 as_bad ("-G may not be used with SVR4 PIC code");
8660 case OPTION_NON_SHARED
:
8661 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8663 as_bad ("-non_shared is supported only for ELF format");
8669 /* The -xgot option tells the assembler to use 32 offsets when
8670 accessing the got in SVR4_PIC mode. It is for Irix
8677 if (! USE_GLOBAL_POINTER_OPT
)
8679 as_bad ("-G is not supported for this configuration");
8682 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8684 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8688 g_switch_value
= atoi (arg
);
8692 /* The -32 and -64 options tell the assembler to output the 32
8693 bit or the 64 bit MIPS ELF format. */
8700 const char **list
, **l
;
8702 list
= bfd_target_list ();
8703 for (l
= list
; *l
!= NULL
; l
++)
8704 if (strcmp (*l
, "elf64-bigmips") == 0
8705 || strcmp (*l
, "elf64-littlemips") == 0)
8708 as_fatal ("No compiled in support for 64 bit object file format");
8722 md_show_usage (stream
)
8727 -membedded-pic generate embedded position independent code\n\
8728 -EB generate big endian output\n\
8729 -EL generate little endian output\n\
8730 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8731 -G NUM allow referencing objects up to NUM bytes\n\
8732 implicitly with the gp register [default 8]\n");
8734 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8735 -mips2, -mcpu=r6000 generate code for r6000\n\
8736 -mips3, -mcpu=r4000 generate code for r4000\n\
8737 -mips4, -mcpu=r8000 generate code for r8000\n\
8738 -mcpu=vr4300 generate code for vr4300\n\
8739 -mcpu=vr4100 generate code for vr4100\n\
8740 -m4650 permit R4650 instructions\n\
8741 -no-m4650 do not permit R4650 instructions\n\
8742 -m4010 permit R4010 instructions\n\
8743 -no-m4010 do not permit R4010 instructions\n\
8744 -m4100 permit VR4100 instructions\n\
8745 -no-m4100 do not permit VR4100 instructions\n");
8747 -mips16 generate mips16 instructions\n\
8748 -no-mips16 do not generate mips16 instructions\n");
8750 -O0 remove unneeded NOPs, do not swap branches\n\
8751 -O remove unneeded NOPs and swap branches\n\
8752 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8753 --break, --no-trap break exception on div by 0 and mult overflow\n");
8756 -KPIC, -call_shared generate SVR4 position independent code\n\
8757 -non_shared do not generate position independent code\n\
8758 -xgot assume a 32 bit GOT\n\
8759 -32 create 32 bit object file (default)\n\
8760 -64 create 64 bit object file\n");
8765 mips_init_after_args ()
8767 /* initialize opcodes */
8768 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
8769 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
8773 md_pcrel_from (fixP
)
8776 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8777 && fixP
->fx_addsy
!= (symbolS
*) NULL
8778 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8780 /* This makes a branch to an undefined symbol be a branch to the
8781 current location. */
8785 /* return the address of the delay slot */
8786 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8789 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8790 reloc for a cons. We could use the definition there, except that
8791 we want to handle 64 bit relocs specially. */
8794 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8797 unsigned int nbytes
;
8801 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8803 if (nbytes
== 8 && ! mips_64
)
8805 if (target_big_endian
)
8811 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8812 as_bad ("Unsupported reloc size %d", nbytes
);
8814 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8817 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8820 /* This is called before the symbol table is processed. In order to
8821 work with gcc when using mips-tfile, we must keep all local labels.
8822 However, in other cases, we want to discard them. If we were
8823 called with -g, but we didn't see any debugging information, it may
8824 mean that gcc is smuggling debugging information through to
8825 mips-tfile, in which case we must generate all local labels. */
8828 mips_frob_file_before_adjust ()
8830 #ifndef NO_ECOFF_DEBUGGING
8833 && ! ecoff_debugging_seen
)
8834 flag_keep_locals
= 1;
8838 /* Sort any unmatched HI16_S relocs so that they immediately precede
8839 the corresponding LO reloc. This is called before md_apply_fix and
8840 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8841 explicit use of the %hi modifier. */
8846 struct mips_hi_fixup
*l
;
8848 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8850 segment_info_type
*seginfo
;
8853 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8855 /* Check quickly whether the next fixup happens to be a matching
8857 if (l
->fixp
->fx_next
!= NULL
8858 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8859 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8860 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8863 /* Look through the fixups for this segment for a matching %lo.
8864 When we find one, move the %hi just in front of it. We do
8865 this in two passes. In the first pass, we try to find a
8866 unique %lo. In the second pass, we permit multiple %hi
8867 relocs for a single %lo (this is a GNU extension). */
8868 seginfo
= seg_info (l
->seg
);
8869 for (pass
= 0; pass
< 2; pass
++)
8874 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8876 /* Check whether this is a %lo fixup which matches l->fixp. */
8877 if (f
->fx_r_type
== BFD_RELOC_LO16
8878 && f
->fx_addsy
== l
->fixp
->fx_addsy
8879 && f
->fx_offset
== l
->fixp
->fx_offset
8882 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8883 || prev
->fx_addsy
!= f
->fx_addsy
8884 || prev
->fx_offset
!= f
->fx_offset
))
8888 /* Move l->fixp before f. */
8889 for (pf
= &seginfo
->fix_root
;
8891 pf
= &(*pf
)->fx_next
)
8892 assert (*pf
!= NULL
);
8894 *pf
= l
->fixp
->fx_next
;
8896 l
->fixp
->fx_next
= f
;
8898 seginfo
->fix_root
= l
->fixp
;
8900 prev
->fx_next
= l
->fixp
;
8912 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8913 "Unmatched %%hi reloc");
8918 /* When generating embedded PIC code we need to use a special
8919 relocation to represent the difference of two symbols in the .text
8920 section (switch tables use a difference of this sort). See
8921 include/coff/mips.h for details. This macro checks whether this
8922 fixup requires the special reloc. */
8923 #define SWITCH_TABLE(fixp) \
8924 ((fixp)->fx_r_type == BFD_RELOC_32 \
8925 && (fixp)->fx_addsy != NULL \
8926 && (fixp)->fx_subsy != NULL \
8927 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8928 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8930 /* When generating embedded PIC code we must keep all PC relative
8931 relocations, in case the linker has to relax a call. We also need
8932 to keep relocations for switch table entries. */
8936 mips_force_relocation (fixp
)
8939 return (mips_pic
== EMBEDDED_PIC
8941 || SWITCH_TABLE (fixp
)
8942 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8943 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8946 /* Apply a fixup to the object file. */
8949 md_apply_fix (fixP
, valueP
)
8956 assert (fixP
->fx_size
== 4
8957 || fixP
->fx_r_type
== BFD_RELOC_16
8958 || fixP
->fx_r_type
== BFD_RELOC_64
);
8962 /* If we aren't adjusting this fixup to be against the section
8963 symbol, we need to adjust the value. */
8965 if (fixP
->fx_addsy
!= NULL
8966 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8967 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8969 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8970 if (value
!= 0 && ! fixP
->fx_pcrel
)
8972 /* In this case, the bfd_install_relocation routine will
8973 incorrectly add the symbol value back in. We just want
8974 the addend to appear in the object file. */
8975 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8980 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8982 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8985 switch (fixP
->fx_r_type
)
8987 case BFD_RELOC_MIPS_JMP
:
8988 case BFD_RELOC_HI16
:
8989 case BFD_RELOC_HI16_S
:
8990 case BFD_RELOC_MIPS_GPREL
:
8991 case BFD_RELOC_MIPS_LITERAL
:
8992 case BFD_RELOC_MIPS_CALL16
:
8993 case BFD_RELOC_MIPS_GOT16
:
8994 case BFD_RELOC_MIPS_GPREL32
:
8995 case BFD_RELOC_MIPS_GOT_HI16
:
8996 case BFD_RELOC_MIPS_GOT_LO16
:
8997 case BFD_RELOC_MIPS_CALL_HI16
:
8998 case BFD_RELOC_MIPS_CALL_LO16
:
8999 case BFD_RELOC_MIPS16_GPREL
:
9001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9002 "Invalid PC relative reloc");
9003 /* Nothing needed to do. The value comes from the reloc entry */
9006 case BFD_RELOC_MIPS16_JMP
:
9007 /* We currently always generate a reloc against a symbol, which
9008 means that we don't want an addend even if the symbol is
9010 fixP
->fx_addnumber
= 0;
9013 case BFD_RELOC_PCREL_HI16_S
:
9014 /* The addend for this is tricky if it is internal, so we just
9015 do everything here rather than in bfd_install_relocation. */
9016 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9018 /* For an external symbol adjust by the address to make it
9019 pcrel_offset. We use the address of the RELLO reloc
9020 which follows this one. */
9021 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9022 + fixP
->fx_next
->fx_where
);
9027 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9028 if (target_big_endian
)
9030 md_number_to_chars (buf
, value
, 2);
9033 case BFD_RELOC_PCREL_LO16
:
9034 /* The addend for this is tricky if it is internal, so we just
9035 do everything here rather than in bfd_install_relocation. */
9036 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9037 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9038 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9039 if (target_big_endian
)
9041 md_number_to_chars (buf
, value
, 2);
9045 /* This is handled like BFD_RELOC_32, but we output a sign
9046 extended value if we are only 32 bits. */
9048 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9050 if (8 <= sizeof (valueT
))
9051 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9058 w1
= w2
= fixP
->fx_where
;
9059 if (target_big_endian
)
9063 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9064 if ((value
& 0x80000000) != 0)
9068 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9074 /* If we are deleting this reloc entry, we must fill in the
9075 value now. This can happen if we have a .word which is not
9076 resolved when it appears but is later defined. We also need
9077 to fill in the value if this is an embedded PIC switch table
9080 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9081 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9086 /* If we are deleting this reloc entry, we must fill in the
9088 assert (fixP
->fx_size
== 2);
9090 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9094 case BFD_RELOC_LO16
:
9095 /* When handling an embedded PIC switch statement, we can wind
9096 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9099 if (value
< -0x8000 || value
> 0x7fff)
9100 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9101 "relocation overflow");
9102 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9103 if (target_big_endian
)
9105 md_number_to_chars (buf
, value
, 2);
9109 case BFD_RELOC_16_PCREL_S2
:
9111 * We need to save the bits in the instruction since fixup_segment()
9112 * might be deleting the relocation entry (i.e., a branch within
9113 * the current segment).
9115 if ((value
& 0x3) != 0)
9116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9117 "Branch to odd address (%lx)", value
);
9120 /* update old instruction data */
9121 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9122 if (target_big_endian
)
9123 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9125 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9127 if (value
>= -0x8000 && value
< 0x8000)
9128 insn
|= value
& 0xffff;
9131 /* The branch offset is too large. If this is an
9132 unconditional branch, and we are not generating PIC code,
9133 we can convert it to an absolute jump instruction. */
9134 if (mips_pic
== NO_PIC
9136 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9137 && (fixP
->fx_frag
->fr_address
9138 < text_section
->vma
+ text_section
->_raw_size
)
9139 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9140 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9141 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9143 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9144 insn
= 0x0c000000; /* jal */
9146 insn
= 0x08000000; /* j */
9147 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9149 fixP
->fx_addsy
= section_symbol (text_section
);
9150 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9154 /* FIXME. It would be possible in principle to handle
9155 conditional branches which overflow. They could be
9156 transformed into a branch around a jump. This would
9157 require setting up variant frags for each different
9158 branch type. The native MIPS assembler attempts to
9159 handle these cases, but it appears to do it
9161 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9162 "Branch out of range");
9166 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9181 const struct mips_opcode
*p
;
9182 int treg
, sreg
, dreg
, shamt
;
9187 for (i
= 0; i
< NUMOPCODES
; ++i
)
9189 p
= &mips_opcodes
[i
];
9190 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9192 printf ("%08lx %s\t", oc
, p
->name
);
9193 treg
= (oc
>> 16) & 0x1f;
9194 sreg
= (oc
>> 21) & 0x1f;
9195 dreg
= (oc
>> 11) & 0x1f;
9196 shamt
= (oc
>> 6) & 0x1f;
9198 for (args
= p
->args
;; ++args
)
9209 printf ("%c", *args
);
9213 assert (treg
== sreg
);
9214 printf ("$%d,$%d", treg
, sreg
);
9219 printf ("$%d", dreg
);
9224 printf ("$%d", treg
);
9228 printf ("0x%x", treg
);
9233 printf ("$%d", sreg
);
9237 printf ("0x%08lx", oc
& 0x1ffffff);
9249 printf ("$%d", shamt
);
9260 printf ("%08lx UNDEFINED\n", oc
);
9271 name
= input_line_pointer
;
9272 c
= get_symbol_end ();
9273 p
= (symbolS
*) symbol_find_or_make (name
);
9274 *input_line_pointer
= c
;
9278 /* Align the current frag to a given power of two. The MIPS assembler
9279 also automatically adjusts any preceding label. */
9282 mips_align (to
, fill
, label
)
9287 mips_emit_delays (false);
9288 frag_align (to
, fill
, 0);
9289 record_alignment (now_seg
, to
);
9292 assert (S_GET_SEGMENT (label
) == now_seg
);
9293 label
->sy_frag
= frag_now
;
9294 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9298 /* Align to a given power of two. .align 0 turns off the automatic
9299 alignment used by the data creating pseudo-ops. */
9306 register long temp_fill
;
9307 long max_alignment
= 15;
9311 o Note that the assembler pulls down any immediately preceeding label
9312 to the aligned address.
9313 o It's not documented but auto alignment is reinstated by
9314 a .align pseudo instruction.
9315 o Note also that after auto alignment is turned off the mips assembler
9316 issues an error on attempt to assemble an improperly aligned data item.
9321 temp
= get_absolute_expression ();
9322 if (temp
> max_alignment
)
9323 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9326 as_warn ("Alignment negative: 0 assumed.");
9329 if (*input_line_pointer
== ',')
9331 input_line_pointer
++;
9332 temp_fill
= get_absolute_expression ();
9339 mips_align (temp
, (int) temp_fill
,
9340 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9347 demand_empty_rest_of_line ();
9351 mips_flush_pending_output ()
9353 mips_emit_delays (false);
9354 mips_clear_insn_labels ();
9363 /* When generating embedded PIC code, we only use the .text, .lit8,
9364 .sdata and .sbss sections. We change the .data and .rdata
9365 pseudo-ops to use .sdata. */
9366 if (mips_pic
== EMBEDDED_PIC
9367 && (sec
== 'd' || sec
== 'r'))
9371 /* The ELF backend needs to know that we are changing sections, so
9372 that .previous works correctly. We could do something like check
9373 for a obj_section_change_hook macro, but that might be confusing
9374 as it would not be appropriate to use it in the section changing
9375 functions in read.c, since obj-elf.c intercepts those. FIXME:
9376 This should be cleaner, somehow. */
9377 obj_elf_section_change_hook ();
9380 mips_emit_delays (false);
9390 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9391 demand_empty_rest_of_line ();
9395 if (USE_GLOBAL_POINTER_OPT
)
9397 seg
= subseg_new (RDATA_SECTION_NAME
,
9398 (subsegT
) get_absolute_expression ());
9399 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9401 bfd_set_section_flags (stdoutput
, seg
,
9407 if (strcmp (TARGET_OS
, "elf") != 0)
9408 bfd_set_section_alignment (stdoutput
, seg
, 4);
9410 demand_empty_rest_of_line ();
9414 as_bad ("No read only data section in this object file format");
9415 demand_empty_rest_of_line ();
9421 if (USE_GLOBAL_POINTER_OPT
)
9423 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9424 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9426 bfd_set_section_flags (stdoutput
, seg
,
9427 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9429 if (strcmp (TARGET_OS
, "elf") != 0)
9430 bfd_set_section_alignment (stdoutput
, seg
, 4);
9432 demand_empty_rest_of_line ();
9437 as_bad ("Global pointers not supported; recompile -G 0");
9438 demand_empty_rest_of_line ();
9447 mips_enable_auto_align ()
9458 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9459 mips_emit_delays (false);
9460 if (log_size
> 0 && auto_align
)
9461 mips_align (log_size
, 0, label
);
9462 mips_clear_insn_labels ();
9463 cons (1 << log_size
);
9472 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9474 mips_emit_delays (false);
9478 mips_align (3, 0, label
);
9480 mips_align (2, 0, label
);
9482 mips_clear_insn_labels ();
9487 /* Handle .globl. We need to override it because on Irix 5 you are
9490 where foo is an undefined symbol, to mean that foo should be
9491 considered to be the address of a function. */
9502 name
= input_line_pointer
;
9503 c
= get_symbol_end ();
9504 symbolP
= symbol_find_or_make (name
);
9505 *input_line_pointer
= c
;
9508 /* On Irix 5, every global symbol that is not explicitly labelled as
9509 being a function is apparently labelled as being an object. */
9512 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9517 secname
= input_line_pointer
;
9518 c
= get_symbol_end ();
9519 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9521 as_bad ("%s: no such section", secname
);
9522 *input_line_pointer
= c
;
9524 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9525 flag
= BSF_FUNCTION
;
9528 symbolP
->bsym
->flags
|= flag
;
9530 S_SET_EXTERNAL (symbolP
);
9531 demand_empty_rest_of_line ();
9541 opt
= input_line_pointer
;
9542 c
= get_symbol_end ();
9546 /* FIXME: What does this mean? */
9548 else if (strncmp (opt
, "pic", 3) == 0)
9556 mips_pic
= SVR4_PIC
;
9558 as_bad (".option pic%d not supported", i
);
9560 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9562 if (g_switch_seen
&& g_switch_value
!= 0)
9563 as_warn ("-G may not be used with SVR4 PIC code");
9565 bfd_set_gp_size (stdoutput
, 0);
9569 as_warn ("Unrecognized option \"%s\"", opt
);
9571 *input_line_pointer
= c
;
9572 demand_empty_rest_of_line ();
9575 /* This structure is used to hold a stack of .set values. */
9577 struct mips_option_stack
9579 struct mips_option_stack
*next
;
9580 struct mips_set_options options
;
9583 static struct mips_option_stack
*mips_opts_stack
;
9585 /* Handle the .set pseudo-op. */
9591 char *name
= input_line_pointer
, ch
;
9593 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9594 input_line_pointer
++;
9595 ch
= *input_line_pointer
;
9596 *input_line_pointer
= '\0';
9598 if (strcmp (name
, "reorder") == 0)
9600 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
9602 /* If we still have pending nops, we can discard them. The
9603 usual nop handling will insert any that are still
9605 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9606 * (mips_opts
.mips16
? 2 : 4));
9607 prev_nop_frag
= NULL
;
9609 mips_opts
.noreorder
= 0;
9611 else if (strcmp (name
, "noreorder") == 0)
9613 mips_emit_delays (true);
9614 mips_opts
.noreorder
= 1;
9615 mips_any_noreorder
= 1;
9617 else if (strcmp (name
, "at") == 0)
9621 else if (strcmp (name
, "noat") == 0)
9625 else if (strcmp (name
, "macro") == 0)
9627 mips_opts
.warn_about_macros
= 0;
9629 else if (strcmp (name
, "nomacro") == 0)
9631 if (mips_opts
.noreorder
== 0)
9632 as_bad ("`noreorder' must be set before `nomacro'");
9633 mips_opts
.warn_about_macros
= 1;
9635 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9637 mips_opts
.nomove
= 0;
9639 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9641 mips_opts
.nomove
= 1;
9643 else if (strcmp (name
, "bopt") == 0)
9645 mips_opts
.nobopt
= 0;
9647 else if (strcmp (name
, "nobopt") == 0)
9649 mips_opts
.nobopt
= 1;
9651 else if (strcmp (name
, "mips16") == 0
9652 || strcmp (name
, "MIPS-16") == 0)
9653 mips_opts
.mips16
= 1;
9654 else if (strcmp (name
, "nomips16") == 0
9655 || strcmp (name
, "noMIPS-16") == 0)
9656 mips_opts
.mips16
= 0;
9657 else if (strncmp (name
, "mips", 4) == 0)
9661 /* Permit the user to change the ISA on the fly. Needless to
9662 say, misuse can cause serious problems. */
9663 isa
= atoi (name
+ 4);
9665 mips_opts
.isa
= file_mips_isa
;
9666 else if (isa
< 1 || isa
> 4)
9667 as_bad ("unknown ISA level");
9669 mips_opts
.isa
= isa
;
9671 else if (strcmp (name
, "autoextend") == 0)
9672 mips_opts
.noautoextend
= 0;
9673 else if (strcmp (name
, "noautoextend") == 0)
9674 mips_opts
.noautoextend
= 1;
9675 else if (strcmp (name
, "push") == 0)
9677 struct mips_option_stack
*s
;
9679 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
9680 s
->next
= mips_opts_stack
;
9681 s
->options
= mips_opts
;
9682 mips_opts_stack
= s
;
9684 else if (strcmp (name
, "pop") == 0)
9686 struct mips_option_stack
*s
;
9688 s
= mips_opts_stack
;
9690 as_bad (".set pop with no .set push");
9693 /* If we're changing the reorder mode we need to handle
9694 delay slots correctly. */
9695 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
9696 mips_emit_delays (true);
9697 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
9699 if (prev_nop_frag
!= NULL
)
9701 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9702 * (mips_opts
.mips16
? 2 : 4));
9703 prev_nop_frag
= NULL
;
9707 mips_opts
= s
->options
;
9708 mips_opts_stack
= s
->next
;
9714 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9716 *input_line_pointer
= ch
;
9717 demand_empty_rest_of_line ();
9720 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9721 .option pic2. It means to generate SVR4 PIC calls. */
9727 mips_pic
= SVR4_PIC
;
9728 if (USE_GLOBAL_POINTER_OPT
)
9730 if (g_switch_seen
&& g_switch_value
!= 0)
9731 as_warn ("-G may not be used with SVR4 PIC code");
9734 bfd_set_gp_size (stdoutput
, 0);
9735 demand_empty_rest_of_line ();
9738 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9739 PIC code. It sets the $gp register for the function based on the
9740 function address, which is in the register named in the argument.
9741 This uses a relocation against _gp_disp, which is handled specially
9742 by the linker. The result is:
9743 lui $gp,%hi(_gp_disp)
9744 addiu $gp,$gp,%lo(_gp_disp)
9745 addu $gp,$gp,.cpload argument
9746 The .cpload argument is normally $25 == $t9. */
9755 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9756 if (mips_pic
!= SVR4_PIC
)
9762 /* .cpload should be a in .set noreorder section. */
9763 if (mips_opts
.noreorder
== 0)
9764 as_warn (".cpload not in noreorder section");
9767 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9768 ex
.X_op_symbol
= NULL
;
9769 ex
.X_add_number
= 0;
9771 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9772 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9774 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9775 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9776 (int) BFD_RELOC_LO16
);
9778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9779 GP
, GP
, tc_get_register (0));
9781 demand_empty_rest_of_line ();
9784 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9785 offset from $sp. The offset is remembered, and after making a PIC
9786 call $gp is restored from that location. */
9789 s_cprestore (ignore
)
9795 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9796 if (mips_pic
!= SVR4_PIC
)
9802 mips_cprestore_offset
= get_absolute_expression ();
9804 ex
.X_op
= O_constant
;
9805 ex
.X_add_symbol
= NULL
;
9806 ex
.X_op_symbol
= NULL
;
9807 ex
.X_add_number
= mips_cprestore_offset
;
9809 macro_build ((char *) NULL
, &icnt
, &ex
,
9810 mips_opts
.isa
< 3 ? "sw" : "sd",
9811 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9813 demand_empty_rest_of_line ();
9816 /* Handle the .gpword pseudo-op. This is used when generating PIC
9817 code. It generates a 32 bit GP relative reloc. */
9827 /* When not generating PIC code, this is treated as .word. */
9828 if (mips_pic
!= SVR4_PIC
)
9834 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9835 mips_emit_delays (true);
9837 mips_align (2, 0, label
);
9838 mips_clear_insn_labels ();
9842 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9844 as_bad ("Unsupported use of .gpword");
9845 ignore_rest_of_line ();
9849 md_number_to_chars (p
, (valueT
) 0, 4);
9850 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9851 BFD_RELOC_MIPS_GPREL32
);
9853 demand_empty_rest_of_line ();
9856 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9857 tables in SVR4 PIC code. */
9866 /* This is ignored when not generating SVR4 PIC code. */
9867 if (mips_pic
!= SVR4_PIC
)
9873 /* Add $gp to the register named as an argument. */
9874 reg
= tc_get_register (0);
9875 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9876 mips_opts
.isa
< 3 ? "addu" : "daddu",
9877 "d,v,t", reg
, reg
, GP
);
9879 demand_empty_rest_of_line ();
9882 /* Handle the .insn pseudo-op. This marks instruction labels in
9883 mips16 mode. This permits the linker to handle them specially,
9884 such as generating jalx instructions when needed. We also make
9885 them odd for the duration of the assembly, in order to generate the
9886 right sort of code. We will make them even in the adjust_symtab
9887 routine, while leaving them marked. This is convenient for the
9888 debugger and the disassembler. The linker knows to make them odd
9895 if (mips_opts
.mips16
)
9896 mips16_mark_labels ();
9898 demand_empty_rest_of_line ();
9901 /* Handle a .stabn directive. We need these in order to mark a label
9902 as being a mips16 text label correctly. Sometimes the compiler
9903 will emit a label, followed by a .stabn, and then switch sections.
9904 If the label and .stabn are in mips16 mode, then the label is
9905 really a mips16 text label. */
9911 if (type
== 'n' && mips_opts
.mips16
)
9912 mips16_mark_labels ();
9917 /* Parse a register string into a number. Called from the ECOFF code
9918 to parse .frame. The argument is non-zero if this is the frame
9919 register, so that we can record it in mips_frame_reg. */
9922 tc_get_register (frame
)
9928 if (*input_line_pointer
++ != '$')
9930 as_warn ("expected `$'");
9933 else if (isdigit ((unsigned char) *input_line_pointer
))
9935 reg
= get_absolute_expression ();
9936 if (reg
< 0 || reg
>= 32)
9938 as_warn ("Bad register number");
9944 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9946 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9948 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9950 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9954 as_warn ("Unrecognized register name");
9957 input_line_pointer
+= 2;
9960 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9965 md_section_align (seg
, addr
)
9969 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9972 /* We don't need to align ELF sections to the full alignment.
9973 However, Irix 5 may prefer that we align them at least to a 16
9974 byte boundary. We don't bother to align the sections if we are
9975 targeted for an embedded system. */
9976 if (strcmp (TARGET_OS
, "elf") == 0)
9982 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9985 /* Utility routine, called from above as well. If called while the
9986 input file is still being read, it's only an approximation. (For
9987 example, a symbol may later become defined which appeared to be
9988 undefined earlier.) */
9991 nopic_need_relax (sym
, before_relaxing
)
9993 int before_relaxing
;
9998 if (USE_GLOBAL_POINTER_OPT
)
10000 const char *symname
;
10003 /* Find out whether this symbol can be referenced off the GP
10004 register. It can be if it is smaller than the -G size or if
10005 it is in the .sdata or .sbss section. Certain symbols can
10006 not be referenced off the GP, although it appears as though
10008 symname
= S_GET_NAME (sym
);
10009 if (symname
!= (const char *) NULL
10010 && (strcmp (symname
, "eprol") == 0
10011 || strcmp (symname
, "etext") == 0
10012 || strcmp (symname
, "_gp") == 0
10013 || strcmp (symname
, "edata") == 0
10014 || strcmp (symname
, "_fbss") == 0
10015 || strcmp (symname
, "_fdata") == 0
10016 || strcmp (symname
, "_ftext") == 0
10017 || strcmp (symname
, "end") == 0
10018 || strcmp (symname
, "_gp_disp") == 0))
10020 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10022 #ifndef NO_ECOFF_DEBUGGING
10023 || (sym
->ecoff_extern_size
!= 0
10024 && sym
->ecoff_extern_size
<= g_switch_value
)
10026 /* We must defer this decision until after the whole
10027 file has been read, since there might be a .extern
10028 after the first use of this symbol. */
10029 || (before_relaxing
10030 #ifndef NO_ECOFF_DEBUGGING
10031 && sym
->ecoff_extern_size
== 0
10033 && S_GET_VALUE (sym
) == 0)
10034 || (S_GET_VALUE (sym
) != 0
10035 && S_GET_VALUE (sym
) <= g_switch_value
)))
10039 const char *segname
;
10041 segname
= segment_name (S_GET_SEGMENT (sym
));
10042 assert (strcmp (segname
, ".lit8") != 0
10043 && strcmp (segname
, ".lit4") != 0);
10044 change
= (strcmp (segname
, ".sdata") != 0
10045 && strcmp (segname
, ".sbss") != 0);
10050 /* We are not optimizing for the GP register. */
10054 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10055 extended opcode. SEC is the section the frag is in. */
10058 mips16_extended_frag (fragp
, sec
, stretch
)
10064 register const struct mips16_immed_operand
*op
;
10066 int mintiny
, maxtiny
;
10069 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10071 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10074 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10075 op
= mips16_immed_operands
;
10076 while (op
->type
!= type
)
10079 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10084 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10087 maxtiny
= 1 << op
->nbits
;
10092 maxtiny
= (1 << op
->nbits
) - 1;
10097 mintiny
= - (1 << (op
->nbits
- 1));
10098 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10101 /* We can't call S_GET_VALUE here, because we don't want to lock in
10102 a particular frag address. */
10103 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10105 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10106 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10107 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10109 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
10110 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
10113 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
10114 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
10115 + fragp
->fr_symbol
->sy_value
.X_add_number
10116 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10117 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
10126 /* We won't have the section when we are called from
10127 mips_relax_frag. However, we will always have been called
10128 from md_estimate_size_before_relax first. If this is a
10129 branch to a different section, we mark it as such. If SEC is
10130 NULL, and the frag is not marked, then it must be a branch to
10131 the same section. */
10134 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10141 fragp
->fr_subtype
=
10142 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10144 /* FIXME: We should support this, and let the linker
10145 catch branches and loads that are out of range. */
10146 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10147 "unsupported PC relative reference to different section");
10153 /* In this case, we know for sure that the symbol fragment is in
10154 the same section. If the fr_address of the symbol fragment
10155 is greater then the address of this fragment we want to add
10156 in STRETCH in order to get a better estimate of the address.
10157 This particularly matters because of the shift bits. */
10159 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
10163 /* Adjust stretch for any alignment frag. Note that if have
10164 been expanding the earlier code, the symbol may be
10165 defined in what appears to be an earlier frag. FIXME:
10166 This doesn't handle the fr_subtype field, which specifies
10167 a maximum number of bytes to skip when doing an
10170 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
10173 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10176 stretch
= - ((- stretch
)
10177 & ~ ((1 << (int) f
->fr_offset
) - 1));
10179 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10188 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10190 /* The base address rules are complicated. The base address of
10191 a branch is the following instruction. The base address of a
10192 PC relative load or add is the instruction itself, but if it
10193 is in a delay slot (in which case it can not be extended) use
10194 the address of the instruction whose delay slot it is in. */
10195 if (type
== 'p' || type
== 'q')
10199 /* If we are currently assuming that this frag should be
10200 extended, then, the current address is two bytes
10202 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10205 /* Ignore the low bit in the target, since it will be set
10206 for a text label. */
10207 if ((val
& 1) != 0)
10210 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10212 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10215 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10217 /* Branch offsets have an implicit 0 in the lowest bit. */
10218 if (type
== 'p' || type
== 'q')
10221 /* If any of the shifted bits are set, we must use an extended
10222 opcode. If the address depends on the size of this
10223 instruction, this can lead to a loop, so we arrange to always
10224 use an extended opcode. We only check this when we are in
10225 the main relaxation loop, when SEC is NULL. */
10226 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10228 fragp
->fr_subtype
=
10229 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10233 /* If we are about to mark a frag as extended because the value
10234 is precisely maxtiny + 1, then there is a chance of an
10235 infinite loop as in the following code:
10240 In this case when the la is extended, foo is 0x3fc bytes
10241 away, so the la can be shrunk, but then foo is 0x400 away, so
10242 the la must be extended. To avoid this loop, we mark the
10243 frag as extended if it was small, and is about to become
10244 extended with a value of maxtiny + 1. */
10245 if (val
== ((maxtiny
+ 1) << op
->shift
)
10246 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10249 fragp
->fr_subtype
=
10250 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10254 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10255 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
10257 if ((val
& ((1 << op
->shift
) - 1)) != 0
10258 || val
< (mintiny
<< op
->shift
)
10259 || val
> (maxtiny
<< op
->shift
))
10265 /* Estimate the size of a frag before relaxing. Unless this is the
10266 mips16, we are not really relaxing here, and the final size is
10267 encoded in the subtype information. For the mips16, we have to
10268 decide whether we are using an extended opcode or not. */
10272 md_estimate_size_before_relax (fragp
, segtype
)
10278 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10280 if (mips16_extended_frag (fragp
, segtype
, 0))
10282 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10287 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10292 if (mips_pic
== NO_PIC
)
10294 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10296 else if (mips_pic
== SVR4_PIC
)
10301 sym
= fragp
->fr_symbol
;
10303 /* Handle the case of a symbol equated to another symbol. */
10304 while (sym
->sy_value
.X_op
== O_symbol
10305 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10309 /* It's possible to get a loop here in a badly written
10311 n
= sym
->sy_value
.X_add_symbol
;
10317 symsec
= S_GET_SEGMENT (sym
);
10319 /* This must duplicate the test in adjust_reloc_syms. */
10320 change
= (symsec
!= &bfd_und_section
10321 && symsec
!= &bfd_abs_section
10322 && ! bfd_is_com_section (symsec
));
10329 /* Record the offset to the first reloc in the fr_opcode field.
10330 This lets md_convert_frag and tc_gen_reloc know that the code
10331 must be expanded. */
10332 fragp
->fr_opcode
= (fragp
->fr_literal
10334 - RELAX_OLD (fragp
->fr_subtype
)
10335 + RELAX_RELOC1 (fragp
->fr_subtype
));
10336 /* FIXME: This really needs as_warn_where. */
10337 if (RELAX_WARN (fragp
->fr_subtype
))
10338 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
10344 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10347 /* This is called to see whether a reloc against a defined symbol
10348 should be converted into a reloc against a section. Don't adjust
10349 MIPS16 jump relocations, so we don't have to worry about the format
10350 of the offset in the .o file. Don't adjust relocations against
10351 mips16 symbols, so that the linker can find them if it needs to set
10355 mips_fix_adjustable (fixp
)
10358 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10360 if (fixp
->fx_addsy
== NULL
)
10363 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10364 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10365 && fixp
->fx_subsy
== NULL
)
10371 /* Translate internal representation of relocation info to BFD target
10375 tc_gen_reloc (section
, fixp
)
10379 static arelent
*retval
[4];
10381 bfd_reloc_code_real_type code
;
10383 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10386 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10387 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10389 if (mips_pic
== EMBEDDED_PIC
10390 && SWITCH_TABLE (fixp
))
10392 /* For a switch table entry we use a special reloc. The addend
10393 is actually the difference between the reloc address and the
10395 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10396 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10397 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
10398 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10400 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10402 /* We use a special addend for an internal RELLO reloc. */
10403 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10404 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10406 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10408 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10410 assert (fixp
->fx_next
!= NULL
10411 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10412 /* We use a special addend for an internal RELHI reloc. The
10413 reloc is relative to the RELLO; adjust the addend
10415 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10416 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10417 + fixp
->fx_next
->fx_where
10418 - S_GET_VALUE (fixp
->fx_subsy
));
10420 reloc
->addend
= (fixp
->fx_addnumber
10421 + fixp
->fx_next
->fx_frag
->fr_address
10422 + fixp
->fx_next
->fx_where
);
10424 else if (fixp
->fx_pcrel
== 0)
10425 reloc
->addend
= fixp
->fx_addnumber
;
10428 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10429 /* A gruesome hack which is a result of the gruesome gas reloc
10431 reloc
->addend
= reloc
->address
;
10433 reloc
->addend
= -reloc
->address
;
10436 /* If this is a variant frag, we may need to adjust the existing
10437 reloc and generate a new one. */
10438 if (fixp
->fx_frag
->fr_opcode
!= NULL
10439 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10440 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10441 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10442 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10443 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10444 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10445 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10449 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10451 /* If this is not the last reloc in this frag, then we have two
10452 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10453 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10454 the second one handle all of them. */
10455 if (fixp
->fx_next
!= NULL
10456 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10458 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10459 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10460 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10461 && (fixp
->fx_next
->fx_r_type
10462 == BFD_RELOC_MIPS_GOT_LO16
))
10463 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10464 && (fixp
->fx_next
->fx_r_type
10465 == BFD_RELOC_MIPS_CALL_LO16
)));
10470 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10471 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10472 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10474 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10475 reloc2
->address
= (reloc
->address
10476 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
10477 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
10478 reloc2
->addend
= fixp
->fx_addnumber
;
10479 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
10480 assert (reloc2
->howto
!= NULL
);
10482 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
10486 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
10489 reloc3
->address
+= 4;
10492 if (mips_pic
== NO_PIC
)
10494 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
10495 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
10497 else if (mips_pic
== SVR4_PIC
)
10499 switch (fixp
->fx_r_type
)
10503 case BFD_RELOC_MIPS_GOT16
:
10505 case BFD_RELOC_MIPS_CALL16
:
10506 case BFD_RELOC_MIPS_GOT_LO16
:
10507 case BFD_RELOC_MIPS_CALL_LO16
:
10508 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
10516 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
10517 fixup_segment converted a non-PC relative reloc into a PC
10518 relative reloc. In such a case, we need to convert the reloc
10520 code
= fixp
->fx_r_type
;
10521 if (fixp
->fx_pcrel
)
10526 code
= BFD_RELOC_8_PCREL
;
10529 code
= BFD_RELOC_16_PCREL
;
10532 code
= BFD_RELOC_32_PCREL
;
10535 code
= BFD_RELOC_64_PCREL
;
10537 case BFD_RELOC_8_PCREL
:
10538 case BFD_RELOC_16_PCREL
:
10539 case BFD_RELOC_32_PCREL
:
10540 case BFD_RELOC_64_PCREL
:
10541 case BFD_RELOC_16_PCREL_S2
:
10542 case BFD_RELOC_PCREL_HI16_S
:
10543 case BFD_RELOC_PCREL_LO16
:
10546 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10547 "Cannot make %s relocation PC relative",
10548 bfd_get_reloc_code_name (code
));
10552 /* To support a PC relative reloc when generating embedded PIC code
10553 for ECOFF, we use a Cygnus extension. We check for that here to
10554 make sure that we don't let such a reloc escape normally. */
10555 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10556 && code
== BFD_RELOC_16_PCREL_S2
10557 && mips_pic
!= EMBEDDED_PIC
)
10558 reloc
->howto
= NULL
;
10560 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10562 if (reloc
->howto
== NULL
)
10564 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10565 "Can not represent %s relocation in this object file format",
10566 bfd_get_reloc_code_name (code
));
10573 /* Relax a machine dependent frag. This returns the amount by which
10574 the current size of the frag should change. */
10577 mips_relax_frag (fragp
, stretch
)
10581 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10584 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10586 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10588 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10593 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10595 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10602 /* Convert a machine dependent frag. */
10605 md_convert_frag (abfd
, asec
, fragp
)
10613 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10616 register const struct mips16_immed_operand
*op
;
10617 boolean small
, ext
;
10620 unsigned long insn
;
10621 boolean use_extend
;
10622 unsigned short extend
;
10624 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10625 op
= mips16_immed_operands
;
10626 while (op
->type
!= type
)
10629 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10640 resolve_symbol_value (fragp
->fr_symbol
, 1);
10641 val
= S_GET_VALUE (fragp
->fr_symbol
);
10646 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10648 /* The rules for the base address of a PC relative reloc are
10649 complicated; see mips16_extended_frag. */
10650 if (type
== 'p' || type
== 'q')
10655 /* Ignore the low bit in the target, since it will be
10656 set for a text label. */
10657 if ((val
& 1) != 0)
10660 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10662 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10665 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10668 /* Make sure the section winds up with the alignment we have
10671 record_alignment (asec
, op
->shift
);
10675 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10676 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10677 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10678 "extended instruction in delay slot");
10680 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10682 if (target_big_endian
)
10683 insn
= bfd_getb16 (buf
);
10685 insn
= bfd_getl16 (buf
);
10687 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10688 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10689 small
, ext
, &insn
, &use_extend
, &extend
);
10693 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10694 fragp
->fr_fix
+= 2;
10698 md_number_to_chars (buf
, insn
, 2);
10699 fragp
->fr_fix
+= 2;
10704 if (fragp
->fr_opcode
== NULL
)
10707 old
= RELAX_OLD (fragp
->fr_subtype
);
10708 new = RELAX_NEW (fragp
->fr_subtype
);
10709 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10712 memcpy (fixptr
- old
, fixptr
, new);
10714 fragp
->fr_fix
+= new - old
;
10720 /* This function is called after the relocs have been generated.
10721 We've been storing mips16 text labels as odd. Here we convert them
10722 back to even for the convenience of the debugger. */
10725 mips_frob_file_after_relocs ()
10728 unsigned int count
, i
;
10730 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10733 syms
= bfd_get_outsymbols (stdoutput
);
10734 count
= bfd_get_symcount (stdoutput
);
10735 for (i
= 0; i
< count
; i
++, syms
++)
10737 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10738 && ((*syms
)->value
& 1) != 0)
10740 (*syms
)->value
&= ~1;
10741 /* If the symbol has an odd size, it was probably computed
10742 incorrectly, so adjust that as well. */
10743 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10744 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10751 /* This function is called whenever a label is defined. It is used
10752 when handling branch delays; if a branch has a label, we assume we
10753 can not move it. */
10756 mips_define_label (sym
)
10759 struct insn_label_list
*l
;
10761 if (free_insn_labels
== NULL
)
10762 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10765 l
= free_insn_labels
;
10766 free_insn_labels
= l
->next
;
10770 l
->next
= insn_labels
;
10774 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10776 /* Some special processing for a MIPS ELF file. */
10779 mips_elf_final_processing ()
10781 /* Write out the register information. */
10786 s
.ri_gprmask
= mips_gprmask
;
10787 s
.ri_cprmask
[0] = mips_cprmask
[0];
10788 s
.ri_cprmask
[1] = mips_cprmask
[1];
10789 s
.ri_cprmask
[2] = mips_cprmask
[2];
10790 s
.ri_cprmask
[3] = mips_cprmask
[3];
10791 /* The gp_value field is set by the MIPS ELF backend. */
10793 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10794 ((Elf32_External_RegInfo
*)
10795 mips_regmask_frag
));
10799 Elf64_Internal_RegInfo s
;
10801 s
.ri_gprmask
= mips_gprmask
;
10803 s
.ri_cprmask
[0] = mips_cprmask
[0];
10804 s
.ri_cprmask
[1] = mips_cprmask
[1];
10805 s
.ri_cprmask
[2] = mips_cprmask
[2];
10806 s
.ri_cprmask
[3] = mips_cprmask
[3];
10807 /* The gp_value field is set by the MIPS ELF backend. */
10809 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10810 ((Elf64_External_RegInfo
*)
10811 mips_regmask_frag
));
10814 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10815 sort of BFD interface for this. */
10816 if (mips_any_noreorder
)
10817 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10818 if (mips_pic
!= NO_PIC
)
10819 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10822 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10824 /* These functions should really be defined by the object file format,
10825 since they are related to debugging information. However, this
10826 code has to work for the a.out format, which does not define them,
10827 so we provide simple versions here. These don't actually generate
10828 any debugging information, but they do simple checking and someday
10829 somebody may make them useful. */
10833 struct loc
*loc_next
;
10834 unsigned long loc_fileno
;
10835 unsigned long loc_lineno
;
10836 unsigned long loc_offset
;
10837 unsigned short loc_delta
;
10838 unsigned short loc_count
;
10845 typedef struct proc
10847 struct proc
*proc_next
;
10848 struct symbol
*proc_isym
;
10849 struct symbol
*proc_end
;
10850 unsigned long proc_reg_mask
;
10851 unsigned long proc_reg_offset
;
10852 unsigned long proc_fpreg_mask
;
10853 unsigned long proc_fpreg_offset
;
10854 unsigned long proc_frameoffset
;
10855 unsigned long proc_framereg
;
10856 unsigned long proc_pcreg
;
10858 struct file
*proc_file
;
10863 typedef struct file
10865 struct file
*file_next
;
10866 unsigned long file_fileno
;
10867 struct symbol
*file_symbol
;
10868 struct symbol
*file_end
;
10869 struct proc
*file_proc
;
10874 static struct obstack proc_frags
;
10875 static procS
*proc_lastP
;
10876 static procS
*proc_rootP
;
10877 static int numprocs
;
10882 obstack_begin (&proc_frags
, 0x2000);
10888 /* check for premature end, nesting errors, etc */
10889 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10890 as_warn ("missing `.end' at end of assembly");
10899 if (*input_line_pointer
== '-')
10901 ++input_line_pointer
;
10904 if (!isdigit (*input_line_pointer
))
10905 as_bad ("Expected simple number.");
10906 if (input_line_pointer
[0] == '0')
10908 if (input_line_pointer
[1] == 'x')
10910 input_line_pointer
+= 2;
10911 while (isxdigit (*input_line_pointer
))
10914 val
|= hex_value (*input_line_pointer
++);
10916 return negative
? -val
: val
;
10920 ++input_line_pointer
;
10921 while (isdigit (*input_line_pointer
))
10924 val
|= *input_line_pointer
++ - '0';
10926 return negative
? -val
: val
;
10929 if (!isdigit (*input_line_pointer
))
10931 printf (" *input_line_pointer == '%c' 0x%02x\n",
10932 *input_line_pointer
, *input_line_pointer
);
10933 as_warn ("Invalid number");
10936 while (isdigit (*input_line_pointer
))
10939 val
+= *input_line_pointer
++ - '0';
10941 return negative
? -val
: val
;
10944 /* The .file directive; just like the usual .file directive, but there
10945 is an initial number which is the ECOFF file index. */
10953 line
= get_number ();
10958 /* The .end directive. */
10966 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10969 demand_empty_rest_of_line ();
10973 if (now_seg
!= text_section
)
10974 as_warn (".end not in text section");
10977 as_warn (".end and no .ent seen yet.");
10983 assert (S_GET_NAME (p
));
10984 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10985 as_warn (".end symbol does not match .ent symbol.");
10988 proc_lastP
->proc_end
= (symbolS
*) 1;
10991 /* The .aent and .ent directives. */
11001 symbolP
= get_symbol ();
11002 if (*input_line_pointer
== ',')
11003 input_line_pointer
++;
11004 SKIP_WHITESPACE ();
11005 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
11006 number
= get_number ();
11007 if (now_seg
!= text_section
)
11008 as_warn (".ent or .aent not in text section.");
11010 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11011 as_warn ("missing `.end'");
11015 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
11016 procP
->proc_isym
= symbolP
;
11017 procP
->proc_reg_mask
= 0;
11018 procP
->proc_reg_offset
= 0;
11019 procP
->proc_fpreg_mask
= 0;
11020 procP
->proc_fpreg_offset
= 0;
11021 procP
->proc_frameoffset
= 0;
11022 procP
->proc_framereg
= 0;
11023 procP
->proc_pcreg
= 0;
11024 procP
->proc_end
= NULL
;
11025 procP
->proc_next
= NULL
;
11027 proc_lastP
->proc_next
= procP
;
11029 proc_rootP
= procP
;
11030 proc_lastP
= procP
;
11033 demand_empty_rest_of_line ();
11036 /* The .frame directive. */
11049 frame_reg
= tc_get_register (1);
11050 if (*input_line_pointer
== ',')
11051 input_line_pointer
++;
11052 frame_off
= get_absolute_expression ();
11053 if (*input_line_pointer
== ',')
11054 input_line_pointer
++;
11055 pcreg
= tc_get_register (0);
11057 /* bob third eye */
11058 assert (proc_rootP
);
11059 proc_rootP
->proc_framereg
= frame_reg
;
11060 proc_rootP
->proc_frameoffset
= frame_off
;
11061 proc_rootP
->proc_pcreg
= pcreg
;
11062 /* bob macho .frame */
11064 /* We don't have to write out a frame stab for unoptimized code. */
11065 if (!(frame_reg
== FP
&& frame_off
== 0))
11068 as_warn ("No .ent for .frame to use.");
11069 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
11070 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
11071 S_SET_TYPE (symP
, N_RMASK
);
11072 S_SET_OTHER (symP
, 0);
11073 S_SET_DESC (symP
, 0);
11074 symP
->sy_forward
= proc_lastP
->proc_isym
;
11075 /* bob perhaps I should have used pseudo set */
11077 demand_empty_rest_of_line ();
11081 /* The .fmask and .mask directives. */
11088 char str
[100], *strP
;
11094 mask
= get_number ();
11095 if (*input_line_pointer
== ',')
11096 input_line_pointer
++;
11097 off
= get_absolute_expression ();
11099 /* bob only for coff */
11100 assert (proc_rootP
);
11101 if (reg_type
== 'F')
11103 proc_rootP
->proc_fpreg_mask
= mask
;
11104 proc_rootP
->proc_fpreg_offset
= off
;
11108 proc_rootP
->proc_reg_mask
= mask
;
11109 proc_rootP
->proc_reg_offset
= off
;
11112 /* bob macho .mask + .fmask */
11114 /* We don't have to write out a mask stab if no saved regs. */
11118 as_warn ("No .ent for .mask to use.");
11120 for (i
= 0; i
< 32; i
++)
11124 sprintf (strP
, "%c%d,", reg_type
, i
);
11125 strP
+= strlen (strP
);
11129 sprintf (strP
, ";%d,", off
);
11130 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
11131 S_SET_TYPE (symP
, N_RMASK
);
11132 S_SET_OTHER (symP
, 0);
11133 S_SET_DESC (symP
, 0);
11134 symP
->sy_forward
= proc_lastP
->proc_isym
;
11135 /* bob perhaps I should have used pseudo set */
11140 /* The .loc directive. */
11151 assert (now_seg
== text_section
);
11153 lineno
= get_number ();
11154 addroff
= frag_now_fix ();
11156 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11157 S_SET_TYPE (symbolP
, N_SLINE
);
11158 S_SET_OTHER (symbolP
, 0);
11159 S_SET_DESC (symbolP
, lineno
);
11160 symbolP
->sy_segment
= now_seg
;