1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros
;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32
= -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32
= -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts
=
194 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask
;
201 unsigned long mips_cprmask
[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa
= ISA_UNKNOWN
;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16
;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d
;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx
;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch
= CPU_UNKNOWN
;
220 static const char *mips_arch_string
;
221 static const struct mips_cpu_info
*mips_arch_info
;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune
= CPU_UNKNOWN
;
226 static const char *mips_tune_string
;
227 static const struct mips_cpu_info
*mips_tune_info
;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode
= 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
289 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
291 /* Return true if the given CPU supports the MIPS3D ASE. */
292 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
295 /* Return true if the given CPU supports the MDMX ASE. */
296 #define CPU_HAS_MDMX(cpu) (false \
299 /* True if CPU has a dror instruction. */
300 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
302 /* True if CPU has a ror instruction. */
303 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
305 /* Whether the processor uses hardware interlocks to protect
306 reads from the HI and LO registers, and thus does not
307 require nops to be inserted. */
309 #define hilo_interlocks (mips_arch == CPU_R4010 \
310 || mips_arch == CPU_VR5500 \
311 || mips_arch == CPU_SB1 \
314 /* Whether the processor uses hardware interlocks to protect reads
315 from the GPRs, and thus does not require nops to be inserted. */
316 #define gpr_interlocks \
317 (mips_opts.isa != ISA_MIPS1 \
318 || mips_arch == CPU_VR5400 \
319 || mips_arch == CPU_VR5500 \
320 || mips_arch == CPU_R3900)
322 /* As with other "interlocks" this is used by hardware that has FP
323 (co-processor) interlocks. */
324 /* Itbl support may require additional care here. */
325 #define cop_interlocks (mips_arch == CPU_R4300 \
326 || mips_arch == CPU_VR5400 \
327 || mips_arch == CPU_VR5500 \
328 || mips_arch == CPU_SB1 \
331 /* Is this a mfhi or mflo instruction? */
332 #define MF_HILO_INSN(PINFO) \
333 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
335 /* MIPS PIC level. */
337 enum mips_pic_level mips_pic
;
339 /* Warn about all NOPS that the assembler generates. */
340 static int warn_nops
= 0;
342 /* 1 if we should generate 32 bit offsets from the $gp register in
343 SVR4_PIC mode. Currently has no meaning in other modes. */
344 static int mips_big_got
= 0;
346 /* 1 if trap instructions should used for overflow rather than break
348 static int mips_trap
= 0;
350 /* 1 if double width floating point constants should not be constructed
351 by assembling two single width halves into two single width floating
352 point registers which just happen to alias the double width destination
353 register. On some architectures this aliasing can be disabled by a bit
354 in the status register, and the setting of this bit cannot be determined
355 automatically at assemble time. */
356 static int mips_disable_float_construction
;
358 /* Non-zero if any .set noreorder directives were used. */
360 static int mips_any_noreorder
;
362 /* Non-zero if nops should be inserted when the register referenced in
363 an mfhi/mflo instruction is read in the next two instructions. */
364 static int mips_7000_hilo_fix
;
366 /* The size of the small data section. */
367 static unsigned int g_switch_value
= 8;
368 /* Whether the -G option was used. */
369 static int g_switch_seen
= 0;
374 /* If we can determine in advance that GP optimization won't be
375 possible, we can skip the relaxation stuff that tries to produce
376 GP-relative references. This makes delay slot optimization work
379 This function can only provide a guess, but it seems to work for
380 gcc output. It needs to guess right for gcc, otherwise gcc
381 will put what it thinks is a GP-relative instruction in a branch
384 I don't know if a fix is needed for the SVR4_PIC mode. I've only
385 fixed it for the non-PIC mode. KR 95/04/07 */
386 static int nopic_need_relax
PARAMS ((symbolS
*, int));
388 /* handle of the OPCODE hash table */
389 static struct hash_control
*op_hash
= NULL
;
391 /* The opcode hash table we use for the mips16. */
392 static struct hash_control
*mips16_op_hash
= NULL
;
394 /* This array holds the chars that always start a comment. If the
395 pre-processor is disabled, these aren't very useful */
396 const char comment_chars
[] = "#";
398 /* This array holds the chars that only start a comment at the beginning of
399 a line. If the line seems to have the form '# 123 filename'
400 .line and .file directives will appear in the pre-processed output */
401 /* Note that input_file.c hand checks for '#' at the beginning of the
402 first line of the input file. This is because the compiler outputs
403 #NO_APP at the beginning of its output. */
404 /* Also note that C style comments are always supported. */
405 const char line_comment_chars
[] = "#";
407 /* This array holds machine specific line separator characters. */
408 const char line_separator_chars
[] = ";";
410 /* Chars that can be used to separate mant from exp in floating point nums */
411 const char EXP_CHARS
[] = "eE";
413 /* Chars that mean this number is a floating point constant */
416 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
418 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
419 changed in read.c . Ideally it shouldn't have to know about it at all,
420 but nothing is ideal around here.
423 static char *insn_error
;
425 static int auto_align
= 1;
427 /* When outputting SVR4 PIC code, the assembler needs to know the
428 offset in the stack frame from which to restore the $gp register.
429 This is set by the .cprestore pseudo-op, and saved in this
431 static offsetT mips_cprestore_offset
= -1;
433 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
434 more optimizations, it can use a register value instead of a memory-saved
435 offset and even an other register than $gp as global pointer. */
436 static offsetT mips_cpreturn_offset
= -1;
437 static int mips_cpreturn_register
= -1;
438 static int mips_gp_register
= GP
;
439 static int mips_gprel_offset
= 0;
441 /* Whether mips_cprestore_offset has been set in the current function
442 (or whether it has already been warned about, if not). */
443 static int mips_cprestore_valid
= 0;
445 /* This is the register which holds the stack frame, as set by the
446 .frame pseudo-op. This is needed to implement .cprestore. */
447 static int mips_frame_reg
= SP
;
449 /* Whether mips_frame_reg has been set in the current function
450 (or whether it has already been warned about, if not). */
451 static int mips_frame_reg_valid
= 0;
453 /* To output NOP instructions correctly, we need to keep information
454 about the previous two instructions. */
456 /* Whether we are optimizing. The default value of 2 means to remove
457 unneeded NOPs and swap branch instructions when possible. A value
458 of 1 means to not swap branches. A value of 0 means to always
460 static int mips_optimize
= 2;
462 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
463 equivalent to seeing no -g option at all. */
464 static int mips_debug
= 0;
466 /* The previous instruction. */
467 static struct mips_cl_insn prev_insn
;
469 /* The instruction before prev_insn. */
470 static struct mips_cl_insn prev_prev_insn
;
472 /* If we don't want information for prev_insn or prev_prev_insn, we
473 point the insn_mo field at this dummy integer. */
474 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
476 /* Non-zero if prev_insn is valid. */
477 static int prev_insn_valid
;
479 /* The frag for the previous instruction. */
480 static struct frag
*prev_insn_frag
;
482 /* The offset into prev_insn_frag for the previous instruction. */
483 static long prev_insn_where
;
485 /* The reloc type for the previous instruction, if any. */
486 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
488 /* The reloc for the previous instruction, if any. */
489 static fixS
*prev_insn_fixp
[3];
491 /* Non-zero if the previous instruction was in a delay slot. */
492 static int prev_insn_is_delay_slot
;
494 /* Non-zero if the previous instruction was in a .set noreorder. */
495 static int prev_insn_unreordered
;
497 /* Non-zero if the previous instruction uses an extend opcode (if
499 static int prev_insn_extended
;
501 /* Non-zero if the previous previous instruction was in a .set
503 static int prev_prev_insn_unreordered
;
505 /* If this is set, it points to a frag holding nop instructions which
506 were inserted before the start of a noreorder section. If those
507 nops turn out to be unnecessary, the size of the frag can be
509 static fragS
*prev_nop_frag
;
511 /* The number of nop instructions we created in prev_nop_frag. */
512 static int prev_nop_frag_holds
;
514 /* The number of nop instructions that we know we need in
516 static int prev_nop_frag_required
;
518 /* The number of instructions we've seen since prev_nop_frag. */
519 static int prev_nop_frag_since
;
521 /* For ECOFF and ELF, relocations against symbols are done in two
522 parts, with a HI relocation and a LO relocation. Each relocation
523 has only 16 bits of space to store an addend. This means that in
524 order for the linker to handle carries correctly, it must be able
525 to locate both the HI and the LO relocation. This means that the
526 relocations must appear in order in the relocation table.
528 In order to implement this, we keep track of each unmatched HI
529 relocation. We then sort them so that they immediately precede the
530 corresponding LO relocation. */
535 struct mips_hi_fixup
*next
;
538 /* The section this fixup is in. */
542 /* The list of unmatched HI relocs. */
544 static struct mips_hi_fixup
*mips_hi_fixup_list
;
546 /* Map normal MIPS register numbers to mips16 register numbers. */
548 #define X ILLEGAL_REG
549 static const int mips32_to_16_reg_map
[] =
551 X
, X
, 2, 3, 4, 5, 6, 7,
552 X
, X
, X
, X
, X
, X
, X
, X
,
553 0, 1, X
, X
, X
, X
, X
, X
,
554 X
, X
, X
, X
, X
, X
, X
, X
558 /* Map mips16 register numbers to normal MIPS register numbers. */
560 static const unsigned int mips16_to_32_reg_map
[] =
562 16, 17, 2, 3, 4, 5, 6, 7
565 static int mips_fix_4122_bugs
;
567 /* We don't relax branches by default, since this causes us to expand
568 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
569 fail to compute the offset before expanding the macro to the most
570 efficient expansion. */
572 static int mips_relax_branch
;
574 /* Since the MIPS does not have multiple forms of PC relative
575 instructions, we do not have to do relaxing as is done on other
576 platforms. However, we do have to handle GP relative addressing
577 correctly, which turns out to be a similar problem.
579 Every macro that refers to a symbol can occur in (at least) two
580 forms, one with GP relative addressing and one without. For
581 example, loading a global variable into a register generally uses
582 a macro instruction like this:
584 If i can be addressed off the GP register (this is true if it is in
585 the .sbss or .sdata section, or if it is known to be smaller than
586 the -G argument) this will generate the following instruction:
588 This instruction will use a GPREL reloc. If i can not be addressed
589 off the GP register, the following instruction sequence will be used:
592 In this case the first instruction will have a HI16 reloc, and the
593 second reloc will have a LO16 reloc. Both relocs will be against
596 The issue here is that we may not know whether i is GP addressable
597 until after we see the instruction that uses it. Therefore, we
598 want to be able to choose the final instruction sequence only at
599 the end of the assembly. This is similar to the way other
600 platforms choose the size of a PC relative instruction only at the
603 When generating position independent code we do not use GP
604 addressing in quite the same way, but the issue still arises as
605 external symbols and local symbols must be handled differently.
607 We handle these issues by actually generating both possible
608 instruction sequences. The longer one is put in a frag_var with
609 type rs_machine_dependent. We encode what to do with the frag in
610 the subtype field. We encode (1) the number of existing bytes to
611 replace, (2) the number of new bytes to use, (3) the offset from
612 the start of the existing bytes to the first reloc we must generate
613 (that is, the offset is applied from the start of the existing
614 bytes after they are replaced by the new bytes, if any), (4) the
615 offset from the start of the existing bytes to the second reloc,
616 (5) whether a third reloc is needed (the third reloc is always four
617 bytes after the second reloc), and (6) whether to warn if this
618 variant is used (this is sometimes needed if .set nomacro or .set
619 noat is in effect). All these numbers are reasonably small.
621 Generating two instruction sequences must be handled carefully to
622 ensure that delay slots are handled correctly. Fortunately, there
623 are a limited number of cases. When the second instruction
624 sequence is generated, append_insn is directed to maintain the
625 existing delay slot information, so it continues to apply to any
626 code after the second instruction sequence. This means that the
627 second instruction sequence must not impose any requirements not
628 required by the first instruction sequence.
630 These variant frags are then handled in functions called by the
631 machine independent code. md_estimate_size_before_relax returns
632 the final size of the frag. md_convert_frag sets up the final form
633 of the frag. tc_gen_reloc adjust the first reloc and adds a second
635 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
639 | (((reloc1) + 64) << 9) \
640 | (((reloc2) + 64) << 2) \
641 | ((reloc3) ? (1 << 1) : 0) \
643 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
644 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
645 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
646 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
647 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
648 #define RELAX_WARN(i) ((i) & 1)
650 /* Branch without likely bit. If label is out of range, we turn:
652 beq reg1, reg2, label
662 with the following opcode replacements:
669 bltzal <-> bgezal (with jal label instead of j label)
671 Even though keeping the delay slot instruction in the delay slot of
672 the branch would be more efficient, it would be very tricky to do
673 correctly, because we'd have to introduce a variable frag *after*
674 the delay slot instruction, and expand that instead. Let's do it
675 the easy way for now, even if the branch-not-taken case now costs
676 one additional instruction. Out-of-range branches are not supposed
677 to be common, anyway.
679 Branch likely. If label is out of range, we turn:
681 beql reg1, reg2, label
682 delay slot (annulled if branch not taken)
691 delay slot (executed only if branch taken)
694 It would be possible to generate a shorter sequence by losing the
695 likely bit, generating something like:
700 delay slot (executed only if branch taken)
712 bltzall -> bgezal (with jal label instead of j label)
713 bgezall -> bltzal (ditto)
716 but it's not clear that it would actually improve performance. */
717 #define RELAX_BRANCH_ENCODE(reloc_s2, uncond, likely, link, toofar) \
720 | ((toofar) ? 1 : 0) \
722 | ((likely) ? 4 : 0) \
723 | ((uncond) ? 8 : 0) \
724 | ((reloc_s2) ? 16 : 0)))
725 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
726 #define RELAX_BRANCH_RELOC_S2(i) (((i) & 16) != 0)
727 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
728 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
729 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
730 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1))
732 /* For mips16 code, we use an entirely different form of relaxation.
733 mips16 supports two versions of most instructions which take
734 immediate values: a small one which takes some small value, and a
735 larger one which takes a 16 bit value. Since branches also follow
736 this pattern, relaxing these values is required.
738 We can assemble both mips16 and normal MIPS code in a single
739 object. Therefore, we need to support this type of relaxation at
740 the same time that we support the relaxation described above. We
741 use the high bit of the subtype field to distinguish these cases.
743 The information we store for this type of relaxation is the
744 argument code found in the opcode file for this relocation, whether
745 the user explicitly requested a small or extended form, and whether
746 the relocation is in a jump or jal delay slot. That tells us the
747 size of the value, and how it should be stored. We also store
748 whether the fragment is considered to be extended or not. We also
749 store whether this is known to be a branch to a different section,
750 whether we have tried to relax this frag yet, and whether we have
751 ever extended a PC relative fragment because of a shift count. */
752 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
755 | ((small) ? 0x100 : 0) \
756 | ((ext) ? 0x200 : 0) \
757 | ((dslot) ? 0x400 : 0) \
758 | ((jal_dslot) ? 0x800 : 0))
759 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
760 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
761 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
762 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
763 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
764 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
765 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
766 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
767 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
768 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
769 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
770 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
772 /* Is the given value a sign-extended 32-bit value? */
773 #define IS_SEXT_32BIT_NUM(x) \
774 (((x) &~ (offsetT) 0x7fffffff) == 0 \
775 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
777 /* Is the given value a sign-extended 16-bit value? */
778 #define IS_SEXT_16BIT_NUM(x) \
779 (((x) &~ (offsetT) 0x7fff) == 0 \
780 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
783 /* Prototypes for static functions. */
786 #define internalError() \
787 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
789 #define internalError() as_fatal (_("MIPS internal Error"));
792 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
794 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
795 unsigned int reg
, enum mips_regclass
class));
796 static int reg_needs_delay
PARAMS ((unsigned int));
797 static void mips16_mark_labels
PARAMS ((void));
798 static void append_insn
PARAMS ((char *place
,
799 struct mips_cl_insn
* ip
,
801 bfd_reloc_code_real_type
*r
,
803 static void mips_no_prev_insn
PARAMS ((int));
804 static void mips_emit_delays
PARAMS ((boolean
));
806 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
807 const char *name
, const char *fmt
,
810 static void macro_build ();
812 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
813 const char *, const char *,
815 static void macro_build_jalr
PARAMS ((int, expressionS
*));
816 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
817 expressionS
* ep
, int regnum
));
818 static void macro_build_ldst_constoffset
PARAMS ((char *place
, int *counter
,
819 expressionS
* ep
, const char *op
,
820 int valreg
, int breg
));
821 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
822 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
824 static void load_register
PARAMS ((int *, int, expressionS
*, int));
825 static void load_address
PARAMS ((int *, int, expressionS
*, int *));
826 static void move_register
PARAMS ((int *, int, int));
827 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
828 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
829 #ifdef LOSING_COMPILER
830 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
832 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
833 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
834 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
835 boolean
, boolean
, unsigned long *,
836 boolean
*, unsigned short *));
837 static int my_getPercentOp
PARAMS ((char **, unsigned int *, int *));
838 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
839 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
840 static void my_getExpression
PARAMS ((expressionS
*, char *));
842 static int support_64bit_objects
PARAMS((void));
844 static void mips_set_option_string
PARAMS ((const char **, const char *));
845 static symbolS
*get_symbol
PARAMS ((void));
846 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
847 static void s_align
PARAMS ((int));
848 static void s_change_sec
PARAMS ((int));
849 static void s_change_section
PARAMS ((int));
850 static void s_cons
PARAMS ((int));
851 static void s_float_cons
PARAMS ((int));
852 static void s_mips_globl
PARAMS ((int));
853 static void s_option
PARAMS ((int));
854 static void s_mipsset
PARAMS ((int));
855 static void s_abicalls
PARAMS ((int));
856 static void s_cpload
PARAMS ((int));
857 static void s_cpsetup
PARAMS ((int));
858 static void s_cplocal
PARAMS ((int));
859 static void s_cprestore
PARAMS ((int));
860 static void s_cpreturn
PARAMS ((int));
861 static void s_gpvalue
PARAMS ((int));
862 static void s_gpword
PARAMS ((int));
863 static void s_gpdword
PARAMS ((int));
864 static void s_cpadd
PARAMS ((int));
865 static void s_insn
PARAMS ((int));
866 static void md_obj_begin
PARAMS ((void));
867 static void md_obj_end
PARAMS ((void));
868 static long get_number
PARAMS ((void));
869 static void s_mips_ent
PARAMS ((int));
870 static void s_mips_end
PARAMS ((int));
871 static void s_mips_frame
PARAMS ((int));
872 static void s_mips_mask
PARAMS ((int));
873 static void s_mips_stab
PARAMS ((int));
874 static void s_mips_weakext
PARAMS ((int));
875 static void s_mips_file
PARAMS ((int));
876 static void s_mips_loc
PARAMS ((int));
877 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
878 static int relaxed_branch_length (fragS
*, asection
*, int);
879 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
880 static void show
PARAMS ((FILE *, const char *, int *, int *));
882 static int mips_need_elf_addend_fixup
PARAMS ((fixS
*));
885 /* Return values of my_getSmallExpression(). */
892 /* Direct relocation creation by %percent_op(). */
911 /* Table and functions used to map between CPU/ISA names, and
912 ISA levels, and CPU numbers. */
916 const char *name
; /* CPU or ISA name. */
917 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
918 int isa
; /* ISA level. */
919 int cpu
; /* CPU number (default CPU if ISA). */
922 static void mips_set_architecture
PARAMS ((const struct mips_cpu_info
*));
923 static void mips_set_tune
PARAMS ((const struct mips_cpu_info
*));
924 static boolean mips_strict_matching_cpu_name_p
PARAMS ((const char *,
926 static boolean mips_matching_cpu_name_p
PARAMS ((const char *, const char *));
927 static const struct mips_cpu_info
*mips_parse_cpu
PARAMS ((const char *,
929 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
933 The following pseudo-ops from the Kane and Heinrich MIPS book
934 should be defined here, but are currently unsupported: .alias,
935 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
937 The following pseudo-ops from the Kane and Heinrich MIPS book are
938 specific to the type of debugging information being generated, and
939 should be defined by the object format: .aent, .begin, .bend,
940 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
943 The following pseudo-ops from the Kane and Heinrich MIPS book are
944 not MIPS CPU specific, but are also not specific to the object file
945 format. This file is probably the best place to define them, but
946 they are not currently supported: .asm0, .endr, .lab, .repeat,
949 static const pseudo_typeS mips_pseudo_table
[] =
951 /* MIPS specific pseudo-ops. */
952 {"option", s_option
, 0},
953 {"set", s_mipsset
, 0},
954 {"rdata", s_change_sec
, 'r'},
955 {"sdata", s_change_sec
, 's'},
956 {"livereg", s_ignore
, 0},
957 {"abicalls", s_abicalls
, 0},
958 {"cpload", s_cpload
, 0},
959 {"cpsetup", s_cpsetup
, 0},
960 {"cplocal", s_cplocal
, 0},
961 {"cprestore", s_cprestore
, 0},
962 {"cpreturn", s_cpreturn
, 0},
963 {"gpvalue", s_gpvalue
, 0},
964 {"gpword", s_gpword
, 0},
965 {"gpdword", s_gpdword
, 0},
966 {"cpadd", s_cpadd
, 0},
969 /* Relatively generic pseudo-ops that happen to be used on MIPS
971 {"asciiz", stringer
, 1},
972 {"bss", s_change_sec
, 'b'},
975 {"dword", s_cons
, 3},
976 {"weakext", s_mips_weakext
, 0},
978 /* These pseudo-ops are defined in read.c, but must be overridden
979 here for one reason or another. */
980 {"align", s_align
, 0},
982 {"data", s_change_sec
, 'd'},
983 {"double", s_float_cons
, 'd'},
984 {"float", s_float_cons
, 'f'},
985 {"globl", s_mips_globl
, 0},
986 {"global", s_mips_globl
, 0},
987 {"hword", s_cons
, 1},
992 {"section", s_change_section
, 0},
993 {"short", s_cons
, 1},
994 {"single", s_float_cons
, 'f'},
995 {"stabn", s_mips_stab
, 'n'},
996 {"text", s_change_sec
, 't'},
999 { "extern", ecoff_directive_extern
, 0},
1004 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1006 /* These pseudo-ops should be defined by the object file format.
1007 However, a.out doesn't support them, so we have versions here. */
1008 {"aent", s_mips_ent
, 1},
1009 {"bgnb", s_ignore
, 0},
1010 {"end", s_mips_end
, 0},
1011 {"endb", s_ignore
, 0},
1012 {"ent", s_mips_ent
, 0},
1013 {"file", s_mips_file
, 0},
1014 {"fmask", s_mips_mask
, 'F'},
1015 {"frame", s_mips_frame
, 0},
1016 {"loc", s_mips_loc
, 0},
1017 {"mask", s_mips_mask
, 'R'},
1018 {"verstamp", s_ignore
, 0},
1022 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
1027 pop_insert (mips_pseudo_table
);
1028 if (! ECOFF_DEBUGGING
)
1029 pop_insert (mips_nonecoff_pseudo_table
);
1032 /* Symbols labelling the current insn. */
1034 struct insn_label_list
1036 struct insn_label_list
*next
;
1040 static struct insn_label_list
*insn_labels
;
1041 static struct insn_label_list
*free_insn_labels
;
1043 static void mips_clear_insn_labels
PARAMS ((void));
1046 mips_clear_insn_labels ()
1048 register struct insn_label_list
**pl
;
1050 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1056 static char *expr_end
;
1058 /* Expressions which appear in instructions. These are set by
1061 static expressionS imm_expr
;
1062 static expressionS offset_expr
;
1064 /* Relocs associated with imm_expr and offset_expr. */
1066 static bfd_reloc_code_real_type imm_reloc
[3]
1067 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1068 static bfd_reloc_code_real_type offset_reloc
[3]
1069 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1071 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
1073 static boolean imm_unmatched_hi
;
1075 /* These are set by mips16_ip if an explicit extension is used. */
1077 static boolean mips16_small
, mips16_ext
;
1080 /* The pdr segment for per procedure frame/regmask info. Not used for
1083 static segT pdr_seg
;
1086 /* The default target format to use. */
1089 mips_target_format ()
1091 switch (OUTPUT_FLAVOR
)
1093 case bfd_target_aout_flavour
:
1094 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1095 case bfd_target_ecoff_flavour
:
1096 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1097 case bfd_target_coff_flavour
:
1099 case bfd_target_elf_flavour
:
1101 /* This is traditional mips. */
1102 return (target_big_endian
1103 ? (HAVE_64BIT_OBJECTS
1104 ? "elf64-tradbigmips"
1106 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1107 : (HAVE_64BIT_OBJECTS
1108 ? "elf64-tradlittlemips"
1110 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1112 return (target_big_endian
1113 ? (HAVE_64BIT_OBJECTS
1116 ? "elf32-nbigmips" : "elf32-bigmips"))
1117 : (HAVE_64BIT_OBJECTS
1118 ? "elf64-littlemips"
1120 ? "elf32-nlittlemips" : "elf32-littlemips")));
1128 /* This function is called once, at assembler startup time. It should
1129 set up all the tables, etc. that the MD part of the assembler will need. */
1134 register const char *retval
= NULL
;
1138 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1139 as_warn (_("Could not set architecture and machine"));
1141 op_hash
= hash_new ();
1143 for (i
= 0; i
< NUMOPCODES
;)
1145 const char *name
= mips_opcodes
[i
].name
;
1147 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1150 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1151 mips_opcodes
[i
].name
, retval
);
1152 /* Probably a memory allocation problem? Give up now. */
1153 as_fatal (_("Broken assembler. No assembly attempted."));
1157 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1159 if (!validate_mips_insn (&mips_opcodes
[i
]))
1164 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1167 mips16_op_hash
= hash_new ();
1170 while (i
< bfd_mips16_num_opcodes
)
1172 const char *name
= mips16_opcodes
[i
].name
;
1174 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1176 as_fatal (_("internal: can't hash `%s': %s"),
1177 mips16_opcodes
[i
].name
, retval
);
1180 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1181 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1182 != mips16_opcodes
[i
].match
))
1184 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1185 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1190 while (i
< bfd_mips16_num_opcodes
1191 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1195 as_fatal (_("Broken assembler. No assembly attempted."));
1197 /* We add all the general register names to the symbol table. This
1198 helps us detect invalid uses of them. */
1199 for (i
= 0; i
< 32; i
++)
1203 sprintf (buf
, "$%d", i
);
1204 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1205 &zero_address_frag
));
1207 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1208 &zero_address_frag
));
1209 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1210 &zero_address_frag
));
1211 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1212 &zero_address_frag
));
1213 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1214 &zero_address_frag
));
1215 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1216 &zero_address_frag
));
1217 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1218 &zero_address_frag
));
1219 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1220 &zero_address_frag
));
1221 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1222 &zero_address_frag
));
1223 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1224 &zero_address_frag
));
1226 /* If we don't add these register names to the symbol table, they
1227 may end up being added as regular symbols by operand(), and then
1228 make it to the object file as undefined in case they're not
1229 regarded as local symbols. They're local in o32, since `$' is a
1230 local symbol prefix, but not in n32 or n64. */
1231 for (i
= 0; i
< 8; i
++)
1235 sprintf (buf
, "$fcc%i", i
);
1236 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1237 &zero_address_frag
));
1240 mips_no_prev_insn (false);
1243 mips_cprmask
[0] = 0;
1244 mips_cprmask
[1] = 0;
1245 mips_cprmask
[2] = 0;
1246 mips_cprmask
[3] = 0;
1248 /* set the default alignment for the text section (2**2) */
1249 record_alignment (text_section
, 2);
1251 if (USE_GLOBAL_POINTER_OPT
)
1252 bfd_set_gp_size (stdoutput
, g_switch_value
);
1254 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1256 /* On a native system, sections must be aligned to 16 byte
1257 boundaries. When configured for an embedded ELF target, we
1259 if (strcmp (TARGET_OS
, "elf") != 0)
1261 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1262 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1263 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1266 /* Create a .reginfo section for register masks and a .mdebug
1267 section for debugging information. */
1275 subseg
= now_subseg
;
1277 /* The ABI says this section should be loaded so that the
1278 running program can access it. However, we don't load it
1279 if we are configured for an embedded target */
1280 flags
= SEC_READONLY
| SEC_DATA
;
1281 if (strcmp (TARGET_OS
, "elf") != 0)
1282 flags
|= SEC_ALLOC
| SEC_LOAD
;
1284 if (mips_abi
!= N64_ABI
)
1286 sec
= subseg_new (".reginfo", (subsegT
) 0);
1288 bfd_set_section_flags (stdoutput
, sec
, flags
);
1289 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1292 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1297 /* The 64-bit ABI uses a .MIPS.options section rather than
1298 .reginfo section. */
1299 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1300 bfd_set_section_flags (stdoutput
, sec
, flags
);
1301 bfd_set_section_alignment (stdoutput
, sec
, 3);
1304 /* Set up the option header. */
1306 Elf_Internal_Options opthdr
;
1309 opthdr
.kind
= ODK_REGINFO
;
1310 opthdr
.size
= (sizeof (Elf_External_Options
)
1311 + sizeof (Elf64_External_RegInfo
));
1314 f
= frag_more (sizeof (Elf_External_Options
));
1315 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1316 (Elf_External_Options
*) f
);
1318 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1323 if (ECOFF_DEBUGGING
)
1325 sec
= subseg_new (".mdebug", (subsegT
) 0);
1326 (void) bfd_set_section_flags (stdoutput
, sec
,
1327 SEC_HAS_CONTENTS
| SEC_READONLY
);
1328 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1331 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1333 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1334 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1335 SEC_READONLY
| SEC_RELOC
1337 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1341 subseg_set (seg
, subseg
);
1345 if (! ECOFF_DEBUGGING
)
1352 if (! ECOFF_DEBUGGING
)
1360 struct mips_cl_insn insn
;
1361 bfd_reloc_code_real_type unused_reloc
[3]
1362 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1364 imm_expr
.X_op
= O_absent
;
1365 imm_unmatched_hi
= false;
1366 offset_expr
.X_op
= O_absent
;
1367 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1368 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1369 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1370 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1371 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1372 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1374 if (mips_opts
.mips16
)
1375 mips16_ip (str
, &insn
);
1378 mips_ip (str
, &insn
);
1379 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1380 str
, insn
.insn_opcode
));
1385 as_bad ("%s `%s'", insn_error
, str
);
1389 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1391 if (mips_opts
.mips16
)
1392 mips16_macro (&insn
);
1398 if (imm_expr
.X_op
!= O_absent
)
1399 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1400 else if (offset_expr
.X_op
!= O_absent
)
1401 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1403 append_insn (NULL
, &insn
, NULL
, unused_reloc
, false);
1407 /* See whether instruction IP reads register REG. CLASS is the type
1411 insn_uses_reg (ip
, reg
, class)
1412 struct mips_cl_insn
*ip
;
1414 enum mips_regclass
class;
1416 if (class == MIPS16_REG
)
1418 assert (mips_opts
.mips16
);
1419 reg
= mips16_to_32_reg_map
[reg
];
1420 class = MIPS_GR_REG
;
1423 /* Don't report on general register ZERO, since it never changes. */
1424 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1427 if (class == MIPS_FP_REG
)
1429 assert (! mips_opts
.mips16
);
1430 /* If we are called with either $f0 or $f1, we must check $f0.
1431 This is not optimal, because it will introduce an unnecessary
1432 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1433 need to distinguish reading both $f0 and $f1 or just one of
1434 them. Note that we don't have to check the other way,
1435 because there is no instruction that sets both $f0 and $f1
1436 and requires a delay. */
1437 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1438 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1439 == (reg
&~ (unsigned) 1)))
1441 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1442 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1443 == (reg
&~ (unsigned) 1)))
1446 else if (! mips_opts
.mips16
)
1448 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1449 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1451 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1452 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1457 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1458 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1459 & MIPS16OP_MASK_RX
)]
1462 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1463 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1464 & MIPS16OP_MASK_RY
)]
1467 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1468 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1469 & MIPS16OP_MASK_MOVE32Z
)]
1472 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1474 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1476 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1478 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1479 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1480 & MIPS16OP_MASK_REGR32
) == reg
)
1487 /* This function returns true if modifying a register requires a
1491 reg_needs_delay (reg
)
1494 unsigned long prev_pinfo
;
1496 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1497 if (! mips_opts
.noreorder
1498 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1499 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1500 || (! gpr_interlocks
1501 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1503 /* A load from a coprocessor or from memory. All load
1504 delays delay the use of general register rt for one
1505 instruction on the r3000. The r6000 and r4000 use
1507 /* Itbl support may require additional care here. */
1508 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1509 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1516 /* Mark instruction labels in mips16 mode. This permits the linker to
1517 handle them specially, such as generating jalx instructions when
1518 needed. We also make them odd for the duration of the assembly, in
1519 order to generate the right sort of code. We will make them even
1520 in the adjust_symtab routine, while leaving them marked. This is
1521 convenient for the debugger and the disassembler. The linker knows
1522 to make them odd again. */
1525 mips16_mark_labels ()
1527 if (mips_opts
.mips16
)
1529 struct insn_label_list
*l
;
1532 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1535 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1536 S_SET_OTHER (l
->label
, STO_MIPS16
);
1538 val
= S_GET_VALUE (l
->label
);
1540 S_SET_VALUE (l
->label
, val
+ 1);
1545 /* Output an instruction. PLACE is where to put the instruction; if
1546 it is NULL, this uses frag_more to get room. IP is the instruction
1547 information. ADDRESS_EXPR is an operand of the instruction to be
1548 used with RELOC_TYPE. */
1551 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1553 struct mips_cl_insn
*ip
;
1554 expressionS
*address_expr
;
1555 bfd_reloc_code_real_type
*reloc_type
;
1556 boolean unmatched_hi
;
1558 register unsigned long prev_pinfo
, pinfo
;
1563 /* Mark instruction labels in mips16 mode. */
1564 mips16_mark_labels ();
1566 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1567 pinfo
= ip
->insn_mo
->pinfo
;
1569 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1573 /* If the previous insn required any delay slots, see if we need
1574 to insert a NOP or two. There are eight kinds of possible
1575 hazards, of which an instruction can have at most one type.
1576 (1) a load from memory delay
1577 (2) a load from a coprocessor delay
1578 (3) an unconditional branch delay
1579 (4) a conditional branch delay
1580 (5) a move to coprocessor register delay
1581 (6) a load coprocessor register from memory delay
1582 (7) a coprocessor condition code delay
1583 (8) a HI/LO special register delay
1585 There are a lot of optimizations we could do that we don't.
1586 In particular, we do not, in general, reorder instructions.
1587 If you use gcc with optimization, it will reorder
1588 instructions and generally do much more optimization then we
1589 do here; repeating all that work in the assembler would only
1590 benefit hand written assembly code, and does not seem worth
1593 /* This is how a NOP is emitted. */
1594 #define emit_nop() \
1596 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1597 : md_number_to_chars (frag_more (4), 0, 4))
1599 /* The previous insn might require a delay slot, depending upon
1600 the contents of the current insn. */
1601 if (! mips_opts
.mips16
1602 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1603 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1604 && ! cop_interlocks
)
1605 || (! gpr_interlocks
1606 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1608 /* A load from a coprocessor or from memory. All load
1609 delays delay the use of general register rt for one
1610 instruction on the r3000. The r6000 and r4000 use
1612 /* Itbl support may require additional care here. */
1613 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1614 if (mips_optimize
== 0
1615 || insn_uses_reg (ip
,
1616 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1621 else if (! mips_opts
.mips16
1622 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1623 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1624 && ! cop_interlocks
)
1625 || (mips_opts
.isa
== ISA_MIPS1
1626 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1628 /* A generic coprocessor delay. The previous instruction
1629 modified a coprocessor general or control register. If
1630 it modified a control register, we need to avoid any
1631 coprocessor instruction (this is probably not always
1632 required, but it sometimes is). If it modified a general
1633 register, we avoid using that register.
1635 On the r6000 and r4000 loading a coprocessor register
1636 from memory is interlocked, and does not require a delay.
1638 This case is not handled very well. There is no special
1639 knowledge of CP0 handling, and the coprocessors other
1640 than the floating point unit are not distinguished at
1642 /* Itbl support may require additional care here. FIXME!
1643 Need to modify this to include knowledge about
1644 user specified delays! */
1645 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1647 if (mips_optimize
== 0
1648 || insn_uses_reg (ip
,
1649 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1654 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1656 if (mips_optimize
== 0
1657 || insn_uses_reg (ip
,
1658 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1665 /* We don't know exactly what the previous instruction
1666 does. If the current instruction uses a coprocessor
1667 register, we must insert a NOP. If previous
1668 instruction may set the condition codes, and the
1669 current instruction uses them, we must insert two
1671 /* Itbl support may require additional care here. */
1672 if (mips_optimize
== 0
1673 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1674 && (pinfo
& INSN_READ_COND_CODE
)))
1676 else if (pinfo
& INSN_COP
)
1680 else if (! mips_opts
.mips16
1681 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1682 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1683 && ! cop_interlocks
)
1685 /* The previous instruction sets the coprocessor condition
1686 codes, but does not require a general coprocessor delay
1687 (this means it is a floating point comparison
1688 instruction). If this instruction uses the condition
1689 codes, we need to insert a single NOP. */
1690 /* Itbl support may require additional care here. */
1691 if (mips_optimize
== 0
1692 || (pinfo
& INSN_READ_COND_CODE
))
1696 /* If we're fixing up mfhi/mflo for the r7000 and the
1697 previous insn was an mfhi/mflo and the current insn
1698 reads the register that the mfhi/mflo wrote to, then
1701 else if (mips_7000_hilo_fix
1702 && MF_HILO_INSN (prev_pinfo
)
1703 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1710 /* If we're fixing up mfhi/mflo for the r7000 and the
1711 2nd previous insn was an mfhi/mflo and the current insn
1712 reads the register that the mfhi/mflo wrote to, then
1715 else if (mips_7000_hilo_fix
1716 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1717 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1725 else if (prev_pinfo
& INSN_READ_LO
)
1727 /* The previous instruction reads the LO register; if the
1728 current instruction writes to the LO register, we must
1729 insert two NOPS. Some newer processors have interlocks.
1730 Also the tx39's multiply instructions can be exectuted
1731 immediatly after a read from HI/LO (without the delay),
1732 though the tx39's divide insns still do require the
1734 if (! (hilo_interlocks
1735 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1736 && (mips_optimize
== 0
1737 || (pinfo
& INSN_WRITE_LO
)))
1739 /* Most mips16 branch insns don't have a delay slot.
1740 If a read from LO is immediately followed by a branch
1741 to a write to LO we have a read followed by a write
1742 less than 2 insns away. We assume the target of
1743 a branch might be a write to LO, and insert a nop
1744 between a read and an immediately following branch. */
1745 else if (mips_opts
.mips16
1746 && (mips_optimize
== 0
1747 || (pinfo
& MIPS16_INSN_BRANCH
)))
1750 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1752 /* The previous instruction reads the HI register; if the
1753 current instruction writes to the HI register, we must
1754 insert a NOP. Some newer processors have interlocks.
1755 Also the note tx39's multiply above. */
1756 if (! (hilo_interlocks
1757 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1758 && (mips_optimize
== 0
1759 || (pinfo
& INSN_WRITE_HI
)))
1761 /* Most mips16 branch insns don't have a delay slot.
1762 If a read from HI is immediately followed by a branch
1763 to a write to HI we have a read followed by a write
1764 less than 2 insns away. We assume the target of
1765 a branch might be a write to HI, and insert a nop
1766 between a read and an immediately following branch. */
1767 else if (mips_opts
.mips16
1768 && (mips_optimize
== 0
1769 || (pinfo
& MIPS16_INSN_BRANCH
)))
1773 /* If the previous instruction was in a noreorder section, then
1774 we don't want to insert the nop after all. */
1775 /* Itbl support may require additional care here. */
1776 if (prev_insn_unreordered
)
1779 /* There are two cases which require two intervening
1780 instructions: 1) setting the condition codes using a move to
1781 coprocessor instruction which requires a general coprocessor
1782 delay and then reading the condition codes 2) reading the HI
1783 or LO register and then writing to it (except on processors
1784 which have interlocks). If we are not already emitting a NOP
1785 instruction, we must check for these cases compared to the
1786 instruction previous to the previous instruction. */
1787 if ((! mips_opts
.mips16
1788 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1789 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1790 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1791 && (pinfo
& INSN_READ_COND_CODE
)
1792 && ! cop_interlocks
)
1793 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1794 && (pinfo
& INSN_WRITE_LO
)
1795 && ! (hilo_interlocks
1796 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1797 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1798 && (pinfo
& INSN_WRITE_HI
)
1799 && ! (hilo_interlocks
1800 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1805 if (prev_prev_insn_unreordered
)
1808 if (prev_prev_nop
&& nops
== 0)
1811 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
1813 /* We're out of bits in pinfo, so we must resort to string
1814 ops here. Shortcuts are selected based on opcodes being
1815 limited to the VR4122 instruction set. */
1817 const char *pn
= prev_insn
.insn_mo
->name
;
1818 const char *tn
= ip
->insn_mo
->name
;
1819 if (strncmp(pn
, "macc", 4) == 0
1820 || strncmp(pn
, "dmacc", 5) == 0)
1822 /* Errata 21 - [D]DIV[U] after [D]MACC */
1823 if (strstr (tn
, "div"))
1828 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1829 if (pn
[0] == 'd' /* dmacc */
1830 && (strncmp(tn
, "dmult", 5) == 0
1831 || strncmp(tn
, "dmacc", 5) == 0))
1836 /* Errata 24 - MT{LO,HI} after [D]MACC */
1837 if (strcmp (tn
, "mtlo") == 0
1838 || strcmp (tn
, "mthi") == 0)
1844 else if (strncmp(pn
, "dmult", 5) == 0
1845 && (strncmp(tn
, "dmult", 5) == 0
1846 || strncmp(tn
, "dmacc", 5) == 0))
1848 /* Here is the rest of errata 23. */
1851 if (nops
< min_nops
)
1855 /* If we are being given a nop instruction, don't bother with
1856 one of the nops we would otherwise output. This will only
1857 happen when a nop instruction is used with mips_optimize set
1860 && ! mips_opts
.noreorder
1861 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1864 /* Now emit the right number of NOP instructions. */
1865 if (nops
> 0 && ! mips_opts
.noreorder
)
1868 unsigned long old_frag_offset
;
1870 struct insn_label_list
*l
;
1872 old_frag
= frag_now
;
1873 old_frag_offset
= frag_now_fix ();
1875 for (i
= 0; i
< nops
; i
++)
1880 listing_prev_line ();
1881 /* We may be at the start of a variant frag. In case we
1882 are, make sure there is enough space for the frag
1883 after the frags created by listing_prev_line. The
1884 argument to frag_grow here must be at least as large
1885 as the argument to all other calls to frag_grow in
1886 this file. We don't have to worry about being in the
1887 middle of a variant frag, because the variants insert
1888 all needed nop instructions themselves. */
1892 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1896 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1897 symbol_set_frag (l
->label
, frag_now
);
1898 val
= (valueT
) frag_now_fix ();
1899 /* mips16 text labels are stored as odd. */
1900 if (mips_opts
.mips16
)
1902 S_SET_VALUE (l
->label
, val
);
1905 #ifndef NO_ECOFF_DEBUGGING
1906 if (ECOFF_DEBUGGING
)
1907 ecoff_fix_loc (old_frag
, old_frag_offset
);
1910 else if (prev_nop_frag
!= NULL
)
1912 /* We have a frag holding nops we may be able to remove. If
1913 we don't need any nops, we can decrease the size of
1914 prev_nop_frag by the size of one instruction. If we do
1915 need some nops, we count them in prev_nops_required. */
1916 if (prev_nop_frag_since
== 0)
1920 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1921 --prev_nop_frag_holds
;
1924 prev_nop_frag_required
+= nops
;
1928 if (prev_prev_nop
== 0)
1930 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1931 --prev_nop_frag_holds
;
1934 ++prev_nop_frag_required
;
1937 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1938 prev_nop_frag
= NULL
;
1940 ++prev_nop_frag_since
;
1942 /* Sanity check: by the time we reach the second instruction
1943 after prev_nop_frag, we should have used up all the nops
1944 one way or another. */
1945 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1951 && ((*reloc_type
== BFD_RELOC_16_PCREL
1952 && address_expr
->X_op
!= O_constant
)
1953 || *reloc_type
== BFD_RELOC_16_PCREL_S2
)
1954 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
1955 || pinfo
& INSN_COND_BRANCH_LIKELY
)
1956 && mips_relax_branch
1957 /* Don't try branch relaxation within .set nomacro, or within
1958 .set noat if we use $at for PIC computations. If it turns
1959 out that the branch was out-of-range, we'll get an error. */
1960 && !mips_opts
.warn_about_macros
1961 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
1962 && !mips_opts
.mips16
)
1964 f
= frag_var (rs_machine_dependent
,
1965 relaxed_branch_length
1967 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
1968 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
1970 (*reloc_type
== BFD_RELOC_16_PCREL_S2
,
1971 pinfo
& INSN_UNCOND_BRANCH_DELAY
,
1972 pinfo
& INSN_COND_BRANCH_LIKELY
,
1973 pinfo
& INSN_WRITE_GPR_31
,
1975 address_expr
->X_add_symbol
,
1976 address_expr
->X_add_number
,
1978 *reloc_type
= BFD_RELOC_UNUSED
;
1980 else if (*reloc_type
> BFD_RELOC_UNUSED
)
1982 /* We need to set up a variant frag. */
1983 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1984 f
= frag_var (rs_machine_dependent
, 4, 0,
1985 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1986 mips16_small
, mips16_ext
,
1988 & INSN_UNCOND_BRANCH_DELAY
),
1989 (*prev_insn_reloc_type
1990 == BFD_RELOC_MIPS16_JMP
)),
1991 make_expr_symbol (address_expr
), 0, NULL
);
1993 else if (place
!= NULL
)
1995 else if (mips_opts
.mips16
1997 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1999 /* Make sure there is enough room to swap this instruction with
2000 a following jump instruction. */
2006 if (mips_opts
.mips16
2007 && mips_opts
.noreorder
2008 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2009 as_warn (_("extended instruction in delay slot"));
2014 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2015 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2017 if (address_expr
->X_op
== O_constant
)
2021 switch (*reloc_type
)
2024 ip
->insn_opcode
|= address_expr
->X_add_number
;
2027 case BFD_RELOC_MIPS_HIGHEST
:
2028 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2030 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2033 case BFD_RELOC_MIPS_HIGHER
:
2034 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2035 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2038 case BFD_RELOC_HI16_S
:
2039 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2043 case BFD_RELOC_HI16
:
2044 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2047 case BFD_RELOC_LO16
:
2048 case BFD_RELOC_MIPS_GOT_DISP
:
2049 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2052 case BFD_RELOC_MIPS_JMP
:
2053 if ((address_expr
->X_add_number
& 3) != 0)
2054 as_bad (_("jump to misaligned address (0x%lx)"),
2055 (unsigned long) address_expr
->X_add_number
);
2056 if (address_expr
->X_add_number
& ~0xfffffff)
2057 as_bad (_("jump address range overflow (0x%lx)"),
2058 (unsigned long) address_expr
->X_add_number
);
2059 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2062 case BFD_RELOC_MIPS16_JMP
:
2063 if ((address_expr
->X_add_number
& 3) != 0)
2064 as_bad (_("jump to misaligned address (0x%lx)"),
2065 (unsigned long) address_expr
->X_add_number
);
2066 if (address_expr
->X_add_number
& ~0xfffffff)
2067 as_bad (_("jump address range overflow (0x%lx)"),
2068 (unsigned long) address_expr
->X_add_number
);
2070 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2071 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2072 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2075 case BFD_RELOC_16_PCREL
:
2076 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2079 case BFD_RELOC_16_PCREL_S2
:
2089 /* Don't generate a reloc if we are writing into a variant frag. */
2092 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2094 (*reloc_type
== BFD_RELOC_16_PCREL
2095 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
2098 /* These relocations can have an addend that won't fit in
2099 4 octets for 64bit assembly. */
2100 if (HAVE_64BIT_GPRS
&&
2101 (*reloc_type
== BFD_RELOC_16
2102 || *reloc_type
== BFD_RELOC_32
2103 || *reloc_type
== BFD_RELOC_MIPS_JMP
2104 || *reloc_type
== BFD_RELOC_HI16_S
2105 || *reloc_type
== BFD_RELOC_LO16
2106 || *reloc_type
== BFD_RELOC_GPREL16
2107 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2108 || *reloc_type
== BFD_RELOC_GPREL32
2109 || *reloc_type
== BFD_RELOC_64
2110 || *reloc_type
== BFD_RELOC_CTOR
2111 || *reloc_type
== BFD_RELOC_MIPS_SUB
2112 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2113 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2114 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2115 || *reloc_type
== BFD_RELOC_MIPS_REL16
2116 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2117 fixp
[0]->fx_no_overflow
= 1;
2121 struct mips_hi_fixup
*hi_fixup
;
2123 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2124 hi_fixup
= ((struct mips_hi_fixup
*)
2125 xmalloc (sizeof (struct mips_hi_fixup
)));
2126 hi_fixup
->fixp
= fixp
[0];
2127 hi_fixup
->seg
= now_seg
;
2128 hi_fixup
->next
= mips_hi_fixup_list
;
2129 mips_hi_fixup_list
= hi_fixup
;
2132 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2134 /* FIXME: This symbol can be one of
2135 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2136 address_expr
->X_op
= O_absent
;
2137 address_expr
->X_add_symbol
= 0;
2138 address_expr
->X_add_number
= 0;
2140 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2141 4, address_expr
, false,
2144 /* These relocations can have an addend that won't fit in
2145 4 octets for 64bit assembly. */
2146 if (HAVE_64BIT_GPRS
&&
2147 (*reloc_type
== BFD_RELOC_16
2148 || *reloc_type
== BFD_RELOC_32
2149 || *reloc_type
== BFD_RELOC_MIPS_JMP
2150 || *reloc_type
== BFD_RELOC_HI16_S
2151 || *reloc_type
== BFD_RELOC_LO16
2152 || *reloc_type
== BFD_RELOC_GPREL16
2153 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2154 || *reloc_type
== BFD_RELOC_GPREL32
2155 || *reloc_type
== BFD_RELOC_64
2156 || *reloc_type
== BFD_RELOC_CTOR
2157 || *reloc_type
== BFD_RELOC_MIPS_SUB
2158 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2159 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2160 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2161 || *reloc_type
== BFD_RELOC_MIPS_REL16
2162 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2163 fixp
[1]->fx_no_overflow
= 1;
2165 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2167 address_expr
->X_op
= O_absent
;
2168 address_expr
->X_add_symbol
= 0;
2169 address_expr
->X_add_number
= 0;
2171 fixp
[2] = fix_new_exp (frag_now
,
2172 f
- frag_now
->fr_literal
, 4,
2173 address_expr
, false,
2176 /* These relocations can have an addend that won't fit in
2177 4 octets for 64bit assembly. */
2178 if (HAVE_64BIT_GPRS
&&
2179 (*reloc_type
== BFD_RELOC_16
2180 || *reloc_type
== BFD_RELOC_32
2181 || *reloc_type
== BFD_RELOC_MIPS_JMP
2182 || *reloc_type
== BFD_RELOC_HI16_S
2183 || *reloc_type
== BFD_RELOC_LO16
2184 || *reloc_type
== BFD_RELOC_GPREL16
2185 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2186 || *reloc_type
== BFD_RELOC_GPREL32
2187 || *reloc_type
== BFD_RELOC_64
2188 || *reloc_type
== BFD_RELOC_CTOR
2189 || *reloc_type
== BFD_RELOC_MIPS_SUB
2190 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2191 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2192 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2193 || *reloc_type
== BFD_RELOC_MIPS_REL16
2194 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2195 fixp
[2]->fx_no_overflow
= 1;
2202 if (! mips_opts
.mips16
)
2204 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2206 dwarf2_emit_insn (4);
2209 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2211 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2212 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2214 dwarf2_emit_insn (4);
2221 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2224 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2226 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2230 /* Update the register mask information. */
2231 if (! mips_opts
.mips16
)
2233 if (pinfo
& INSN_WRITE_GPR_D
)
2234 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2235 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2236 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2237 if (pinfo
& INSN_READ_GPR_S
)
2238 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2239 if (pinfo
& INSN_WRITE_GPR_31
)
2240 mips_gprmask
|= 1 << RA
;
2241 if (pinfo
& INSN_WRITE_FPR_D
)
2242 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2243 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2244 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2245 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2246 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2247 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2248 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2249 if (pinfo
& INSN_COP
)
2251 /* We don't keep enough information to sort these cases out.
2252 The itbl support does keep this information however, although
2253 we currently don't support itbl fprmats as part of the cop
2254 instruction. May want to add this support in the future. */
2256 /* Never set the bit for $0, which is always zero. */
2257 mips_gprmask
&= ~1 << 0;
2261 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2262 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2263 & MIPS16OP_MASK_RX
);
2264 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2265 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2266 & MIPS16OP_MASK_RY
);
2267 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2268 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2269 & MIPS16OP_MASK_RZ
);
2270 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2271 mips_gprmask
|= 1 << TREG
;
2272 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2273 mips_gprmask
|= 1 << SP
;
2274 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2275 mips_gprmask
|= 1 << RA
;
2276 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2277 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2278 if (pinfo
& MIPS16_INSN_READ_Z
)
2279 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2280 & MIPS16OP_MASK_MOVE32Z
);
2281 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2282 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2283 & MIPS16OP_MASK_REGR32
);
2286 if (place
== NULL
&& ! mips_opts
.noreorder
)
2288 /* Filling the branch delay slot is more complex. We try to
2289 switch the branch with the previous instruction, which we can
2290 do if the previous instruction does not set up a condition
2291 that the branch tests and if the branch is not itself the
2292 target of any branch. */
2293 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2294 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2296 if (mips_optimize
< 2
2297 /* If we have seen .set volatile or .set nomove, don't
2299 || mips_opts
.nomove
!= 0
2300 /* If we had to emit any NOP instructions, then we
2301 already know we can not swap. */
2303 /* If we don't even know the previous insn, we can not
2305 || ! prev_insn_valid
2306 /* If the previous insn is already in a branch delay
2307 slot, then we can not swap. */
2308 || prev_insn_is_delay_slot
2309 /* If the previous previous insn was in a .set
2310 noreorder, we can't swap. Actually, the MIPS
2311 assembler will swap in this situation. However, gcc
2312 configured -with-gnu-as will generate code like
2318 in which we can not swap the bne and INSN. If gcc is
2319 not configured -with-gnu-as, it does not output the
2320 .set pseudo-ops. We don't have to check
2321 prev_insn_unreordered, because prev_insn_valid will
2322 be 0 in that case. We don't want to use
2323 prev_prev_insn_valid, because we do want to be able
2324 to swap at the start of a function. */
2325 || prev_prev_insn_unreordered
2326 /* If the branch is itself the target of a branch, we
2327 can not swap. We cheat on this; all we check for is
2328 whether there is a label on this instruction. If
2329 there are any branches to anything other than a
2330 label, users must use .set noreorder. */
2331 || insn_labels
!= NULL
2332 /* If the previous instruction is in a variant frag, we
2333 can not do the swap. This does not apply to the
2334 mips16, which uses variant frags for different
2336 || (! mips_opts
.mips16
2337 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2338 /* If the branch reads the condition codes, we don't
2339 even try to swap, because in the sequence
2344 we can not swap, and I don't feel like handling that
2346 || (! mips_opts
.mips16
2347 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2348 && (pinfo
& INSN_READ_COND_CODE
))
2349 /* We can not swap with an instruction that requires a
2350 delay slot, becase the target of the branch might
2351 interfere with that instruction. */
2352 || (! mips_opts
.mips16
2353 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2355 /* Itbl support may require additional care here. */
2356 & (INSN_LOAD_COPROC_DELAY
2357 | INSN_COPROC_MOVE_DELAY
2358 | INSN_WRITE_COND_CODE
)))
2359 || (! (hilo_interlocks
2360 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2364 || (! mips_opts
.mips16
2366 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2367 || (! mips_opts
.mips16
2368 && mips_opts
.isa
== ISA_MIPS1
2369 /* Itbl support may require additional care here. */
2370 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2371 /* We can not swap with a branch instruction. */
2373 & (INSN_UNCOND_BRANCH_DELAY
2374 | INSN_COND_BRANCH_DELAY
2375 | INSN_COND_BRANCH_LIKELY
))
2376 /* We do not swap with a trap instruction, since it
2377 complicates trap handlers to have the trap
2378 instruction be in a delay slot. */
2379 || (prev_pinfo
& INSN_TRAP
)
2380 /* If the branch reads a register that the previous
2381 instruction sets, we can not swap. */
2382 || (! mips_opts
.mips16
2383 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2384 && insn_uses_reg (ip
,
2385 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2388 || (! mips_opts
.mips16
2389 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2390 && insn_uses_reg (ip
,
2391 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2394 || (mips_opts
.mips16
2395 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2396 && insn_uses_reg (ip
,
2397 ((prev_insn
.insn_opcode
2399 & MIPS16OP_MASK_RX
),
2401 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2402 && insn_uses_reg (ip
,
2403 ((prev_insn
.insn_opcode
2405 & MIPS16OP_MASK_RY
),
2407 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2408 && insn_uses_reg (ip
,
2409 ((prev_insn
.insn_opcode
2411 & MIPS16OP_MASK_RZ
),
2413 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2414 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2415 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2416 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2417 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2418 && insn_uses_reg (ip
,
2419 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2422 /* If the branch writes a register that the previous
2423 instruction sets, we can not swap (we know that
2424 branches write only to RD or to $31). */
2425 || (! mips_opts
.mips16
2426 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2427 && (((pinfo
& INSN_WRITE_GPR_D
)
2428 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2429 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2430 || ((pinfo
& INSN_WRITE_GPR_31
)
2431 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2434 || (! mips_opts
.mips16
2435 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2436 && (((pinfo
& INSN_WRITE_GPR_D
)
2437 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2438 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2439 || ((pinfo
& INSN_WRITE_GPR_31
)
2440 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2443 || (mips_opts
.mips16
2444 && (pinfo
& MIPS16_INSN_WRITE_31
)
2445 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2446 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2447 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2449 /* If the branch writes a register that the previous
2450 instruction reads, we can not swap (we know that
2451 branches only write to RD or to $31). */
2452 || (! mips_opts
.mips16
2453 && (pinfo
& INSN_WRITE_GPR_D
)
2454 && insn_uses_reg (&prev_insn
,
2455 ((ip
->insn_opcode
>> OP_SH_RD
)
2458 || (! mips_opts
.mips16
2459 && (pinfo
& INSN_WRITE_GPR_31
)
2460 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2461 || (mips_opts
.mips16
2462 && (pinfo
& MIPS16_INSN_WRITE_31
)
2463 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2464 /* If we are generating embedded PIC code, the branch
2465 might be expanded into a sequence which uses $at, so
2466 we can't swap with an instruction which reads it. */
2467 || (mips_pic
== EMBEDDED_PIC
2468 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2469 /* If the previous previous instruction has a load
2470 delay, and sets a register that the branch reads, we
2472 || (! mips_opts
.mips16
2473 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2474 /* Itbl support may require additional care here. */
2475 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2476 || (! gpr_interlocks
2477 && (prev_prev_insn
.insn_mo
->pinfo
2478 & INSN_LOAD_MEMORY_DELAY
)))
2479 && insn_uses_reg (ip
,
2480 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2483 /* If one instruction sets a condition code and the
2484 other one uses a condition code, we can not swap. */
2485 || ((pinfo
& INSN_READ_COND_CODE
)
2486 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2487 || ((pinfo
& INSN_WRITE_COND_CODE
)
2488 && (prev_pinfo
& INSN_READ_COND_CODE
))
2489 /* If the previous instruction uses the PC, we can not
2491 || (mips_opts
.mips16
2492 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2493 /* If the previous instruction was extended, we can not
2495 || (mips_opts
.mips16
&& prev_insn_extended
)
2496 /* If the previous instruction had a fixup in mips16
2497 mode, we can not swap. This normally means that the
2498 previous instruction was a 4 byte branch anyhow. */
2499 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2500 /* If the previous instruction is a sync, sync.l, or
2501 sync.p, we can not swap. */
2502 || (prev_pinfo
& INSN_SYNC
))
2504 /* We could do even better for unconditional branches to
2505 portions of this object file; we could pick up the
2506 instruction at the destination, put it in the delay
2507 slot, and bump the destination address. */
2509 /* Update the previous insn information. */
2510 prev_prev_insn
= *ip
;
2511 prev_insn
.insn_mo
= &dummy_opcode
;
2515 /* It looks like we can actually do the swap. */
2516 if (! mips_opts
.mips16
)
2521 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2522 memcpy (temp
, prev_f
, 4);
2523 memcpy (prev_f
, f
, 4);
2524 memcpy (f
, temp
, 4);
2525 if (prev_insn_fixp
[0])
2527 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2528 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2530 if (prev_insn_fixp
[1])
2532 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2533 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2535 if (prev_insn_fixp
[2])
2537 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2538 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2542 fixp
[0]->fx_frag
= prev_insn_frag
;
2543 fixp
[0]->fx_where
= prev_insn_where
;
2547 fixp
[1]->fx_frag
= prev_insn_frag
;
2548 fixp
[1]->fx_where
= prev_insn_where
;
2552 fixp
[2]->fx_frag
= prev_insn_frag
;
2553 fixp
[2]->fx_where
= prev_insn_where
;
2561 assert (prev_insn_fixp
[0] == NULL
);
2562 assert (prev_insn_fixp
[1] == NULL
);
2563 assert (prev_insn_fixp
[2] == NULL
);
2564 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2565 memcpy (temp
, prev_f
, 2);
2566 memcpy (prev_f
, f
, 2);
2567 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2569 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2570 memcpy (f
, temp
, 2);
2574 memcpy (f
, f
+ 2, 2);
2575 memcpy (f
+ 2, temp
, 2);
2579 fixp
[0]->fx_frag
= prev_insn_frag
;
2580 fixp
[0]->fx_where
= prev_insn_where
;
2584 fixp
[1]->fx_frag
= prev_insn_frag
;
2585 fixp
[1]->fx_where
= prev_insn_where
;
2589 fixp
[2]->fx_frag
= prev_insn_frag
;
2590 fixp
[2]->fx_where
= prev_insn_where
;
2594 /* Update the previous insn information; leave prev_insn
2596 prev_prev_insn
= *ip
;
2598 prev_insn_is_delay_slot
= 1;
2600 /* If that was an unconditional branch, forget the previous
2601 insn information. */
2602 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2604 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2605 prev_insn
.insn_mo
= &dummy_opcode
;
2608 prev_insn_fixp
[0] = NULL
;
2609 prev_insn_fixp
[1] = NULL
;
2610 prev_insn_fixp
[2] = NULL
;
2611 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2612 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2613 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2614 prev_insn_extended
= 0;
2616 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2618 /* We don't yet optimize a branch likely. What we should do
2619 is look at the target, copy the instruction found there
2620 into the delay slot, and increment the branch to jump to
2621 the next instruction. */
2623 /* Update the previous insn information. */
2624 prev_prev_insn
= *ip
;
2625 prev_insn
.insn_mo
= &dummy_opcode
;
2626 prev_insn_fixp
[0] = NULL
;
2627 prev_insn_fixp
[1] = NULL
;
2628 prev_insn_fixp
[2] = NULL
;
2629 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2630 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2631 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2632 prev_insn_extended
= 0;
2636 /* Update the previous insn information. */
2638 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2640 prev_prev_insn
= prev_insn
;
2643 /* Any time we see a branch, we always fill the delay slot
2644 immediately; since this insn is not a branch, we know it
2645 is not in a delay slot. */
2646 prev_insn_is_delay_slot
= 0;
2648 prev_insn_fixp
[0] = fixp
[0];
2649 prev_insn_fixp
[1] = fixp
[1];
2650 prev_insn_fixp
[2] = fixp
[2];
2651 prev_insn_reloc_type
[0] = reloc_type
[0];
2652 prev_insn_reloc_type
[1] = reloc_type
[1];
2653 prev_insn_reloc_type
[2] = reloc_type
[2];
2654 if (mips_opts
.mips16
)
2655 prev_insn_extended
= (ip
->use_extend
2656 || *reloc_type
> BFD_RELOC_UNUSED
);
2659 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2660 prev_insn_unreordered
= 0;
2661 prev_insn_frag
= frag_now
;
2662 prev_insn_where
= f
- frag_now
->fr_literal
;
2663 prev_insn_valid
= 1;
2665 else if (place
== NULL
)
2667 /* We need to record a bit of information even when we are not
2668 reordering, in order to determine the base address for mips16
2669 PC relative relocs. */
2670 prev_prev_insn
= prev_insn
;
2672 prev_insn_reloc_type
[0] = reloc_type
[0];
2673 prev_insn_reloc_type
[1] = reloc_type
[1];
2674 prev_insn_reloc_type
[2] = reloc_type
[2];
2675 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2676 prev_insn_unreordered
= 1;
2679 /* We just output an insn, so the next one doesn't have a label. */
2680 mips_clear_insn_labels ();
2682 /* We must ensure that a fixup associated with an unmatched %hi
2683 reloc does not become a variant frag. Otherwise, the
2684 rearrangement of %hi relocs in frob_file may confuse
2688 frag_wane (frag_now
);
2693 /* This function forgets that there was any previous instruction or
2694 label. If PRESERVE is non-zero, it remembers enough information to
2695 know whether nops are needed before a noreorder section. */
2698 mips_no_prev_insn (preserve
)
2703 prev_insn
.insn_mo
= &dummy_opcode
;
2704 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2705 prev_nop_frag
= NULL
;
2706 prev_nop_frag_holds
= 0;
2707 prev_nop_frag_required
= 0;
2708 prev_nop_frag_since
= 0;
2710 prev_insn_valid
= 0;
2711 prev_insn_is_delay_slot
= 0;
2712 prev_insn_unreordered
= 0;
2713 prev_insn_extended
= 0;
2714 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2715 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2716 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2717 prev_prev_insn_unreordered
= 0;
2718 mips_clear_insn_labels ();
2721 /* This function must be called whenever we turn on noreorder or emit
2722 something other than instructions. It inserts any NOPS which might
2723 be needed by the previous instruction, and clears the information
2724 kept for the previous instructions. The INSNS parameter is true if
2725 instructions are to follow. */
2728 mips_emit_delays (insns
)
2731 if (! mips_opts
.noreorder
)
2736 if ((! mips_opts
.mips16
2737 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2738 && (! cop_interlocks
2739 && (prev_insn
.insn_mo
->pinfo
2740 & (INSN_LOAD_COPROC_DELAY
2741 | INSN_COPROC_MOVE_DELAY
2742 | INSN_WRITE_COND_CODE
))))
2743 || (! hilo_interlocks
2744 && (prev_insn
.insn_mo
->pinfo
2747 || (! mips_opts
.mips16
2749 && (prev_insn
.insn_mo
->pinfo
2750 & INSN_LOAD_MEMORY_DELAY
))
2751 || (! mips_opts
.mips16
2752 && mips_opts
.isa
== ISA_MIPS1
2753 && (prev_insn
.insn_mo
->pinfo
2754 & INSN_COPROC_MEMORY_DELAY
)))
2756 /* Itbl support may require additional care here. */
2758 if ((! mips_opts
.mips16
2759 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2760 && (! cop_interlocks
2761 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2762 || (! hilo_interlocks
2763 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2764 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2767 if (prev_insn_unreordered
)
2770 else if ((! mips_opts
.mips16
2771 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2772 && (! cop_interlocks
2773 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2774 || (! hilo_interlocks
2775 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2776 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2778 /* Itbl support may require additional care here. */
2779 if (! prev_prev_insn_unreordered
)
2783 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
2786 const char *pn
= prev_insn
.insn_mo
->name
;
2787 if (strncmp(pn
, "macc", 4) == 0
2788 || strncmp(pn
, "dmacc", 5) == 0
2789 || strncmp(pn
, "dmult", 5) == 0)
2793 if (nops
< min_nops
)
2799 struct insn_label_list
*l
;
2803 /* Record the frag which holds the nop instructions, so
2804 that we can remove them if we don't need them. */
2805 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2806 prev_nop_frag
= frag_now
;
2807 prev_nop_frag_holds
= nops
;
2808 prev_nop_frag_required
= 0;
2809 prev_nop_frag_since
= 0;
2812 for (; nops
> 0; --nops
)
2817 /* Move on to a new frag, so that it is safe to simply
2818 decrease the size of prev_nop_frag. */
2819 frag_wane (frag_now
);
2823 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2827 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2828 symbol_set_frag (l
->label
, frag_now
);
2829 val
= (valueT
) frag_now_fix ();
2830 /* mips16 text labels are stored as odd. */
2831 if (mips_opts
.mips16
)
2833 S_SET_VALUE (l
->label
, val
);
2838 /* Mark instruction labels in mips16 mode. */
2840 mips16_mark_labels ();
2842 mips_no_prev_insn (insns
);
2845 /* Build an instruction created by a macro expansion. This is passed
2846 a pointer to the count of instructions created so far, an
2847 expression, the name of the instruction to build, an operand format
2848 string, and corresponding arguments. */
2852 macro_build (char *place
,
2860 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2869 struct mips_cl_insn insn
;
2870 bfd_reloc_code_real_type r
[3];
2874 va_start (args
, fmt
);
2880 * If the macro is about to expand into a second instruction,
2881 * print a warning if needed. We need to pass ip as a parameter
2882 * to generate a better warning message here...
2884 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2885 as_warn (_("Macro instruction expanded into multiple instructions"));
2888 * If the macro is about to expand into a second instruction,
2889 * and it is in a delay slot, print a warning.
2893 && mips_opts
.noreorder
2894 && (prev_prev_insn
.insn_mo
->pinfo
2895 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2896 | INSN_COND_BRANCH_LIKELY
)) != 0)
2897 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2900 ++*counter
; /* bump instruction counter */
2902 if (mips_opts
.mips16
)
2904 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2909 r
[0] = BFD_RELOC_UNUSED
;
2910 r
[1] = BFD_RELOC_UNUSED
;
2911 r
[2] = BFD_RELOC_UNUSED
;
2912 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2913 assert (insn
.insn_mo
);
2914 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2916 /* Search until we get a match for NAME. */
2919 /* It is assumed here that macros will never generate
2920 MDMX or MIPS-3D instructions. */
2921 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2922 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2923 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2925 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2927 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2931 assert (insn
.insn_mo
->name
);
2932 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2935 insn
.insn_opcode
= insn
.insn_mo
->match
;
2951 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2955 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2960 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2965 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2970 int tmp
= va_arg (args
, int);
2972 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2973 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2979 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2986 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2990 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2994 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2998 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3002 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3009 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3015 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3016 assert (*r
== BFD_RELOC_GPREL16
3017 || *r
== BFD_RELOC_MIPS_LITERAL
3018 || *r
== BFD_RELOC_MIPS_HIGHER
3019 || *r
== BFD_RELOC_HI16_S
3020 || *r
== BFD_RELOC_LO16
3021 || *r
== BFD_RELOC_MIPS_GOT16
3022 || *r
== BFD_RELOC_MIPS_CALL16
3023 || *r
== BFD_RELOC_MIPS_GOT_DISP
3024 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3025 || *r
== BFD_RELOC_MIPS_GOT_OFST
3026 || *r
== BFD_RELOC_MIPS_GOT_LO16
3027 || *r
== BFD_RELOC_MIPS_CALL_LO16
3028 || (ep
->X_op
== O_subtract
3029 && *r
== BFD_RELOC_PCREL_LO16
));
3033 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3035 && (ep
->X_op
== O_constant
3036 || (ep
->X_op
== O_symbol
3037 && (*r
== BFD_RELOC_MIPS_HIGHEST
3038 || *r
== BFD_RELOC_HI16_S
3039 || *r
== BFD_RELOC_HI16
3040 || *r
== BFD_RELOC_GPREL16
3041 || *r
== BFD_RELOC_MIPS_GOT_HI16
3042 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3043 || (ep
->X_op
== O_subtract
3044 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3048 assert (ep
!= NULL
);
3050 * This allows macro() to pass an immediate expression for
3051 * creating short branches without creating a symbol.
3052 * Note that the expression still might come from the assembly
3053 * input, in which case the value is not checked for range nor
3054 * is a relocation entry generated (yuck).
3056 if (ep
->X_op
== O_constant
)
3058 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3062 if (mips_pic
== EMBEDDED_PIC
)
3063 *r
= BFD_RELOC_16_PCREL_S2
;
3065 *r
= BFD_RELOC_16_PCREL
;
3069 assert (ep
!= NULL
);
3070 *r
= BFD_RELOC_MIPS_JMP
;
3074 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3083 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3085 append_insn (place
, &insn
, ep
, r
, false);
3089 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3091 int *counter ATTRIBUTE_UNUSED
;
3097 struct mips_cl_insn insn
;
3098 bfd_reloc_code_real_type r
[3]
3099 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3101 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3102 assert (insn
.insn_mo
);
3103 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3105 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3106 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3109 assert (insn
.insn_mo
->name
);
3110 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3113 insn
.insn_opcode
= insn
.insn_mo
->match
;
3114 insn
.use_extend
= false;
3133 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3138 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3142 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3146 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3156 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3163 regno
= va_arg (args
, int);
3164 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3165 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3186 assert (ep
!= NULL
);
3188 if (ep
->X_op
!= O_constant
)
3189 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3192 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, false, false,
3193 false, &insn
.insn_opcode
, &insn
.use_extend
,
3196 *r
= BFD_RELOC_UNUSED
;
3202 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3209 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3211 append_insn (place
, &insn
, ep
, r
, false);
3215 * Generate a "jalr" instruction with a relocation hint to the called
3216 * function. This occurs in NewABI PIC code.
3219 macro_build_jalr (icnt
, ep
)
3230 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3233 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3234 0, ep
, false, BFD_RELOC_MIPS_JALR
);
3238 * Generate a "lui" instruction.
3241 macro_build_lui (place
, counter
, ep
, regnum
)
3247 expressionS high_expr
;
3248 struct mips_cl_insn insn
;
3249 bfd_reloc_code_real_type r
[3]
3250 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3251 const char *name
= "lui";
3252 const char *fmt
= "t,u";
3254 assert (! mips_opts
.mips16
);
3260 high_expr
.X_op
= O_constant
;
3261 high_expr
.X_add_number
= ep
->X_add_number
;
3264 if (high_expr
.X_op
== O_constant
)
3266 /* we can compute the instruction now without a relocation entry */
3267 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3269 *r
= BFD_RELOC_UNUSED
;
3273 assert (ep
->X_op
== O_symbol
);
3274 /* _gp_disp is a special case, used from s_cpload. */
3275 assert (mips_pic
== NO_PIC
3277 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3278 *r
= BFD_RELOC_HI16_S
;
3282 * If the macro is about to expand into a second instruction,
3283 * print a warning if needed. We need to pass ip as a parameter
3284 * to generate a better warning message here...
3286 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3287 as_warn (_("Macro instruction expanded into multiple instructions"));
3290 ++*counter
; /* bump instruction counter */
3292 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3293 assert (insn
.insn_mo
);
3294 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3295 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3297 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3298 if (*r
== BFD_RELOC_UNUSED
)
3300 insn
.insn_opcode
|= high_expr
.X_add_number
;
3301 append_insn (place
, &insn
, NULL
, r
, false);
3304 append_insn (place
, &insn
, &high_expr
, r
, false);
3307 /* Generate a sequence of instructions to do a load or store from a constant
3308 offset off of a base register (breg) into/from a target register (treg),
3309 using AT if necessary. */
3311 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3318 assert (ep
->X_op
== O_constant
);
3320 /* Right now, this routine can only handle signed 32-bit contants. */
3321 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3322 as_warn (_("operand overflow"));
3324 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3326 /* Signed 16-bit offset will fit in the op. Easy! */
3327 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3328 (int) BFD_RELOC_LO16
, breg
);
3332 /* 32-bit offset, need multiple instructions and AT, like:
3333 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3334 addu $tempreg,$tempreg,$breg
3335 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3336 to handle the complete offset. */
3337 macro_build_lui (place
, counter
, ep
, AT
);
3340 macro_build (place
, counter
, (expressionS
*) NULL
,
3341 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3342 "d,v,t", AT
, AT
, breg
);
3345 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3346 (int) BFD_RELOC_LO16
, AT
);
3349 as_warn (_("Macro used $at after \".set noat\""));
3354 * Generates code to set the $at register to true (one)
3355 * if reg is less than the immediate expression.
3358 set_at (counter
, reg
, unsignedp
)
3363 if (imm_expr
.X_op
== O_constant
3364 && imm_expr
.X_add_number
>= -0x8000
3365 && imm_expr
.X_add_number
< 0x8000)
3366 macro_build ((char *) NULL
, counter
, &imm_expr
,
3367 unsignedp
? "sltiu" : "slti",
3368 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3371 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3372 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3373 unsignedp
? "sltu" : "slt",
3374 "d,v,t", AT
, reg
, AT
);
3378 /* Warn if an expression is not a constant. */
3381 check_absolute_expr (ip
, ex
)
3382 struct mips_cl_insn
*ip
;
3385 if (ex
->X_op
== O_big
)
3386 as_bad (_("unsupported large constant"));
3387 else if (ex
->X_op
!= O_constant
)
3388 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3391 /* Count the leading zeroes by performing a binary chop. This is a
3392 bulky bit of source, but performance is a LOT better for the
3393 majority of values than a simple loop to count the bits:
3394 for (lcnt = 0; (lcnt < 32); lcnt++)
3395 if ((v) & (1 << (31 - lcnt)))
3397 However it is not code size friendly, and the gain will drop a bit
3398 on certain cached systems.
3400 #define COUNT_TOP_ZEROES(v) \
3401 (((v) & ~0xffff) == 0 \
3402 ? ((v) & ~0xff) == 0 \
3403 ? ((v) & ~0xf) == 0 \
3404 ? ((v) & ~0x3) == 0 \
3405 ? ((v) & ~0x1) == 0 \
3410 : ((v) & ~0x7) == 0 \
3413 : ((v) & ~0x3f) == 0 \
3414 ? ((v) & ~0x1f) == 0 \
3417 : ((v) & ~0x7f) == 0 \
3420 : ((v) & ~0xfff) == 0 \
3421 ? ((v) & ~0x3ff) == 0 \
3422 ? ((v) & ~0x1ff) == 0 \
3425 : ((v) & ~0x7ff) == 0 \
3428 : ((v) & ~0x3fff) == 0 \
3429 ? ((v) & ~0x1fff) == 0 \
3432 : ((v) & ~0x7fff) == 0 \
3435 : ((v) & ~0xffffff) == 0 \
3436 ? ((v) & ~0xfffff) == 0 \
3437 ? ((v) & ~0x3ffff) == 0 \
3438 ? ((v) & ~0x1ffff) == 0 \
3441 : ((v) & ~0x7ffff) == 0 \
3444 : ((v) & ~0x3fffff) == 0 \
3445 ? ((v) & ~0x1fffff) == 0 \
3448 : ((v) & ~0x7fffff) == 0 \
3451 : ((v) & ~0xfffffff) == 0 \
3452 ? ((v) & ~0x3ffffff) == 0 \
3453 ? ((v) & ~0x1ffffff) == 0 \
3456 : ((v) & ~0x7ffffff) == 0 \
3459 : ((v) & ~0x3fffffff) == 0 \
3460 ? ((v) & ~0x1fffffff) == 0 \
3463 : ((v) & ~0x7fffffff) == 0 \
3468 * This routine generates the least number of instructions neccessary to load
3469 * an absolute expression value into a register.
3472 load_register (counter
, reg
, ep
, dbl
)
3479 expressionS hi32
, lo32
;
3481 if (ep
->X_op
!= O_big
)
3483 assert (ep
->X_op
== O_constant
);
3484 if (ep
->X_add_number
< 0x8000
3485 && (ep
->X_add_number
>= 0
3486 || (ep
->X_add_number
>= -0x8000
3489 || sizeof (ep
->X_add_number
) > 4))))
3491 /* We can handle 16 bit signed values with an addiu to
3492 $zero. No need to ever use daddiu here, since $zero and
3493 the result are always correct in 32 bit mode. */
3494 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3495 (int) BFD_RELOC_LO16
);
3498 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3500 /* We can handle 16 bit unsigned values with an ori to
3502 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3503 (int) BFD_RELOC_LO16
);
3506 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3509 || sizeof (ep
->X_add_number
) > 4
3510 || (ep
->X_add_number
& 0x80000000) == 0))
3511 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3512 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3515 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3516 == ~ (offsetT
) 0xffffffff)))
3518 /* 32 bit values require an lui. */
3519 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3520 (int) BFD_RELOC_HI16
);
3521 if ((ep
->X_add_number
& 0xffff) != 0)
3522 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3523 (int) BFD_RELOC_LO16
);
3528 /* The value is larger than 32 bits. */
3530 if (HAVE_32BIT_GPRS
)
3532 as_bad (_("Number (0x%lx) larger than 32 bits"),
3533 (unsigned long) ep
->X_add_number
);
3534 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3535 (int) BFD_RELOC_LO16
);
3539 if (ep
->X_op
!= O_big
)
3542 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3543 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3544 hi32
.X_add_number
&= 0xffffffff;
3546 lo32
.X_add_number
&= 0xffffffff;
3550 assert (ep
->X_add_number
> 2);
3551 if (ep
->X_add_number
== 3)
3552 generic_bignum
[3] = 0;
3553 else if (ep
->X_add_number
> 4)
3554 as_bad (_("Number larger than 64 bits"));
3555 lo32
.X_op
= O_constant
;
3556 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3557 hi32
.X_op
= O_constant
;
3558 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3561 if (hi32
.X_add_number
== 0)
3566 unsigned long hi
, lo
;
3568 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3570 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3572 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3573 reg
, 0, (int) BFD_RELOC_LO16
);
3576 if (lo32
.X_add_number
& 0x80000000)
3578 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3579 (int) BFD_RELOC_HI16
);
3580 if (lo32
.X_add_number
& 0xffff)
3581 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3582 reg
, reg
, (int) BFD_RELOC_LO16
);
3587 /* Check for 16bit shifted constant. We know that hi32 is
3588 non-zero, so start the mask on the first bit of the hi32
3593 unsigned long himask
, lomask
;
3597 himask
= 0xffff >> (32 - shift
);
3598 lomask
= (0xffff << shift
) & 0xffffffff;
3602 himask
= 0xffff << (shift
- 32);
3605 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3606 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3610 tmp
.X_op
= O_constant
;
3612 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3613 | (lo32
.X_add_number
>> shift
));
3615 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3616 macro_build ((char *) NULL
, counter
, &tmp
,
3617 "ori", "t,r,i", reg
, 0,
3618 (int) BFD_RELOC_LO16
);
3619 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3620 (shift
>= 32) ? "dsll32" : "dsll",
3622 (shift
>= 32) ? shift
- 32 : shift
);
3627 while (shift
<= (64 - 16));
3629 /* Find the bit number of the lowest one bit, and store the
3630 shifted value in hi/lo. */
3631 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3632 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3636 while ((lo
& 1) == 0)
3641 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3647 while ((hi
& 1) == 0)
3656 /* Optimize if the shifted value is a (power of 2) - 1. */
3657 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3658 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3660 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3665 /* This instruction will set the register to be all
3667 tmp
.X_op
= O_constant
;
3668 tmp
.X_add_number
= (offsetT
) -1;
3669 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3670 reg
, 0, (int) BFD_RELOC_LO16
);
3674 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3675 (bit
>= 32) ? "dsll32" : "dsll",
3677 (bit
>= 32) ? bit
- 32 : bit
);
3679 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3680 (shift
>= 32) ? "dsrl32" : "dsrl",
3682 (shift
>= 32) ? shift
- 32 : shift
);
3687 /* Sign extend hi32 before calling load_register, because we can
3688 generally get better code when we load a sign extended value. */
3689 if ((hi32
.X_add_number
& 0x80000000) != 0)
3690 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3691 load_register (counter
, reg
, &hi32
, 0);
3694 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3698 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3699 "dsll32", "d,w,<", reg
, freg
, 0);
3707 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3709 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3710 (int) BFD_RELOC_HI16
);
3711 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3712 "dsrl32", "d,w,<", reg
, reg
, 0);
3718 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3719 "d,w,<", reg
, freg
, 16);
3723 mid16
.X_add_number
>>= 16;
3724 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3725 freg
, (int) BFD_RELOC_LO16
);
3726 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3727 "d,w,<", reg
, reg
, 16);
3730 if ((lo32
.X_add_number
& 0xffff) != 0)
3731 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3732 (int) BFD_RELOC_LO16
);
3735 /* Load an address into a register. */
3738 load_address (counter
, reg
, ep
, used_at
)
3746 if (ep
->X_op
!= O_constant
3747 && ep
->X_op
!= O_symbol
)
3749 as_bad (_("expression too complex"));
3750 ep
->X_op
= O_constant
;
3753 if (ep
->X_op
== O_constant
)
3755 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3759 if (mips_pic
== NO_PIC
)
3761 /* If this is a reference to a GP relative symbol, we want
3762 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3764 lui $reg,<sym> (BFD_RELOC_HI16_S)
3765 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3766 If we have an addend, we always use the latter form.
3768 With 64bit address space and a usable $at we want
3769 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3770 lui $at,<sym> (BFD_RELOC_HI16_S)
3771 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3772 daddiu $at,<sym> (BFD_RELOC_LO16)
3776 If $at is already in use, we use an path which is suboptimal
3777 on superscalar processors.
3778 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3779 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3781 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3783 daddiu $reg,<sym> (BFD_RELOC_LO16)
3785 if (HAVE_64BIT_ADDRESSES
)
3787 /* We don't do GP optimization for now because RELAX_ENCODE can't
3788 hold the data for such large chunks. */
3790 if (*used_at
== 0 && ! mips_opts
.noat
)
3792 macro_build (p
, counter
, ep
, "lui", "t,u",
3793 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3794 macro_build (p
, counter
, ep
, "lui", "t,u",
3795 AT
, (int) BFD_RELOC_HI16_S
);
3796 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3797 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3798 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3799 AT
, AT
, (int) BFD_RELOC_LO16
);
3800 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3801 "d,w,<", reg
, reg
, 0);
3802 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3803 "d,v,t", reg
, reg
, AT
);
3808 macro_build (p
, counter
, ep
, "lui", "t,u",
3809 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3810 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3811 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3812 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3813 "d,w,<", reg
, reg
, 16);
3814 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3815 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3816 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3817 "d,w,<", reg
, reg
, 16);
3818 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3819 reg
, reg
, (int) BFD_RELOC_LO16
);
3824 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3825 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3828 macro_build ((char *) NULL
, counter
, ep
,
3829 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3830 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3831 p
= frag_var (rs_machine_dependent
, 8, 0,
3832 RELAX_ENCODE (4, 8, 0, 4, 0,
3833 mips_opts
.warn_about_macros
),
3834 ep
->X_add_symbol
, 0, NULL
);
3836 macro_build_lui (p
, counter
, ep
, reg
);
3839 macro_build (p
, counter
, ep
,
3840 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3841 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3844 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3848 /* If this is a reference to an external symbol, we want
3849 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3851 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3853 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3854 If we have NewABI, we want
3855 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3856 If there is a constant, it must be added in after. */
3857 ex
.X_add_number
= ep
->X_add_number
;
3858 ep
->X_add_number
= 0;
3862 macro_build ((char *) NULL
, counter
, ep
,
3863 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3864 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3868 macro_build ((char *) NULL
, counter
, ep
,
3869 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3870 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3871 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3872 p
= frag_var (rs_machine_dependent
, 4, 0,
3873 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3874 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3875 macro_build (p
, counter
, ep
,
3876 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3877 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3880 if (ex
.X_add_number
!= 0)
3882 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3883 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3884 ex
.X_op
= O_constant
;
3885 macro_build ((char *) NULL
, counter
, &ex
,
3886 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3887 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3890 else if (mips_pic
== SVR4_PIC
)
3895 /* This is the large GOT case. If this is a reference to an
3896 external symbol, we want
3897 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3899 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3900 Otherwise, for a reference to a local symbol, we want
3901 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3903 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3904 If we have NewABI, we want
3905 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3906 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3907 If there is a constant, it must be added in after. */
3908 ex
.X_add_number
= ep
->X_add_number
;
3909 ep
->X_add_number
= 0;
3912 macro_build ((char *) NULL
, counter
, ep
,
3913 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3914 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3915 macro_build (p
, counter
, ep
,
3916 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3917 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
3921 if (reg_needs_delay (mips_gp_register
))
3926 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3927 (int) BFD_RELOC_MIPS_GOT_HI16
);
3928 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3929 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
3930 reg
, mips_gp_register
);
3931 macro_build ((char *) NULL
, counter
, ep
,
3932 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3933 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3934 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3935 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3936 mips_opts
.warn_about_macros
),
3937 ep
->X_add_symbol
, 0, NULL
);
3940 /* We need a nop before loading from $gp. This special
3941 check is required because the lui which starts the main
3942 instruction stream does not refer to $gp, and so will not
3943 insert the nop which may be required. */
3944 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3947 macro_build (p
, counter
, ep
,
3948 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3949 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3951 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3953 macro_build (p
, counter
, ep
,
3954 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3955 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3958 if (ex
.X_add_number
!= 0)
3960 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3961 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3962 ex
.X_op
= O_constant
;
3963 macro_build ((char *) NULL
, counter
, &ex
,
3964 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3965 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3968 else if (mips_pic
== EMBEDDED_PIC
)
3971 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3973 macro_build ((char *) NULL
, counter
, ep
,
3974 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3975 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3981 /* Move the contents of register SOURCE into register DEST. */
3984 move_register (counter
, dest
, source
)
3989 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3990 HAVE_32BIT_GPRS
? "addu" : "daddu",
3991 "d,v,t", dest
, source
, 0);
3996 * This routine implements the seemingly endless macro or synthesized
3997 * instructions and addressing modes in the mips assembly language. Many
3998 * of these macros are simple and are similar to each other. These could
3999 * probably be handled by some kind of table or grammer aproach instead of
4000 * this verbose method. Others are not simple macros but are more like
4001 * optimizing code generation.
4002 * One interesting optimization is when several store macros appear
4003 * consecutivly that would load AT with the upper half of the same address.
4004 * The ensuing load upper instructions are ommited. This implies some kind
4005 * of global optimization. We currently only optimize within a single macro.
4006 * For many of the load and store macros if the address is specified as a
4007 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4008 * first load register 'at' with zero and use it as the base register. The
4009 * mips assembler simply uses register $zero. Just one tiny optimization
4014 struct mips_cl_insn
*ip
;
4016 register int treg
, sreg
, dreg
, breg
;
4032 bfd_reloc_code_real_type r
;
4033 int hold_mips_optimize
;
4035 assert (! mips_opts
.mips16
);
4037 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4038 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4039 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4040 mask
= ip
->insn_mo
->mask
;
4042 expr1
.X_op
= O_constant
;
4043 expr1
.X_op_symbol
= NULL
;
4044 expr1
.X_add_symbol
= NULL
;
4045 expr1
.X_add_number
= 1;
4057 mips_emit_delays (true);
4058 ++mips_opts
.noreorder
;
4059 mips_any_noreorder
= 1;
4061 expr1
.X_add_number
= 8;
4062 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
4064 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4067 move_register (&icnt
, dreg
, sreg
);
4068 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4069 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4071 --mips_opts
.noreorder
;
4092 if (imm_expr
.X_op
== O_constant
4093 && imm_expr
.X_add_number
>= -0x8000
4094 && imm_expr
.X_add_number
< 0x8000)
4096 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
4097 (int) BFD_RELOC_LO16
);
4100 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4101 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4121 if (imm_expr
.X_op
== O_constant
4122 && imm_expr
.X_add_number
>= 0
4123 && imm_expr
.X_add_number
< 0x10000)
4125 if (mask
!= M_NOR_I
)
4126 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4127 sreg
, (int) BFD_RELOC_LO16
);
4130 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4131 treg
, sreg
, (int) BFD_RELOC_LO16
);
4132 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4133 "d,v,t", treg
, treg
, 0);
4138 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4157 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4159 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4163 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4164 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4172 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4173 likely
? "bgezl" : "bgez", "s,p", sreg
);
4178 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4179 likely
? "blezl" : "blez", "s,p", treg
);
4182 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4184 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4185 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4191 /* check for > max integer */
4192 maxnum
= 0x7fffffff;
4193 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4200 if (imm_expr
.X_op
== O_constant
4201 && imm_expr
.X_add_number
>= maxnum
4202 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4205 /* result is always false */
4209 as_warn (_("Branch %s is always false (nop)"),
4211 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4217 as_warn (_("Branch likely %s is always false"),
4219 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4224 if (imm_expr
.X_op
!= O_constant
)
4225 as_bad (_("Unsupported large constant"));
4226 ++imm_expr
.X_add_number
;
4230 if (mask
== M_BGEL_I
)
4232 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4234 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4235 likely
? "bgezl" : "bgez", "s,p", sreg
);
4238 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4240 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4241 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4244 maxnum
= 0x7fffffff;
4245 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4252 maxnum
= - maxnum
- 1;
4253 if (imm_expr
.X_op
== O_constant
4254 && imm_expr
.X_add_number
<= maxnum
4255 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4258 /* result is always true */
4259 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4260 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4263 set_at (&icnt
, sreg
, 0);
4264 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4265 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4275 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4276 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4279 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4280 "d,v,t", AT
, sreg
, treg
);
4281 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4282 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4290 && imm_expr
.X_op
== O_constant
4291 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4293 if (imm_expr
.X_op
!= O_constant
)
4294 as_bad (_("Unsupported large constant"));
4295 ++imm_expr
.X_add_number
;
4299 if (mask
== M_BGEUL_I
)
4301 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4303 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4305 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4306 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4309 set_at (&icnt
, sreg
, 1);
4310 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4311 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4319 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4320 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4325 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4326 likely
? "bltzl" : "bltz", "s,p", treg
);
4329 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4331 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4332 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4340 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4341 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4346 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4347 "d,v,t", AT
, treg
, sreg
);
4348 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4349 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4357 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4358 likely
? "blezl" : "blez", "s,p", sreg
);
4363 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4364 likely
? "bgezl" : "bgez", "s,p", treg
);
4367 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4369 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4370 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4376 maxnum
= 0x7fffffff;
4377 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4384 if (imm_expr
.X_op
== O_constant
4385 && imm_expr
.X_add_number
>= maxnum
4386 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4388 if (imm_expr
.X_op
!= O_constant
)
4389 as_bad (_("Unsupported large constant"));
4390 ++imm_expr
.X_add_number
;
4394 if (mask
== M_BLTL_I
)
4396 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4398 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4399 likely
? "bltzl" : "bltz", "s,p", sreg
);
4402 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4404 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4405 likely
? "blezl" : "blez", "s,p", sreg
);
4408 set_at (&icnt
, sreg
, 0);
4409 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4410 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4418 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4419 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4424 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4425 "d,v,t", AT
, treg
, sreg
);
4426 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4427 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4435 && imm_expr
.X_op
== O_constant
4436 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4438 if (imm_expr
.X_op
!= O_constant
)
4439 as_bad (_("Unsupported large constant"));
4440 ++imm_expr
.X_add_number
;
4444 if (mask
== M_BLTUL_I
)
4446 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4448 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4450 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4451 likely
? "beql" : "beq",
4455 set_at (&icnt
, sreg
, 1);
4456 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4457 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4465 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4466 likely
? "bltzl" : "bltz", "s,p", sreg
);
4471 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4472 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4475 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4477 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4478 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4488 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4489 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4492 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4495 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4496 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4511 as_warn (_("Divide by zero."));
4513 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4516 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4521 mips_emit_delays (true);
4522 ++mips_opts
.noreorder
;
4523 mips_any_noreorder
= 1;
4526 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4527 "s,t,q", treg
, 0, 7);
4528 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4529 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4533 expr1
.X_add_number
= 8;
4534 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4535 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4536 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4537 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4540 expr1
.X_add_number
= -1;
4541 macro_build ((char *) NULL
, &icnt
, &expr1
,
4542 dbl
? "daddiu" : "addiu",
4543 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4544 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4545 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4548 expr1
.X_add_number
= 1;
4549 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4550 (int) BFD_RELOC_LO16
);
4551 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4552 "d,w,<", AT
, AT
, 31);
4556 expr1
.X_add_number
= 0x80000000;
4557 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4558 (int) BFD_RELOC_HI16
);
4562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4563 "s,t,q", sreg
, AT
, 6);
4564 /* We want to close the noreorder block as soon as possible, so
4565 that later insns are available for delay slot filling. */
4566 --mips_opts
.noreorder
;
4570 expr1
.X_add_number
= 8;
4571 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4572 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4575 /* We want to close the noreorder block as soon as possible, so
4576 that later insns are available for delay slot filling. */
4577 --mips_opts
.noreorder
;
4579 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4582 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4621 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4623 as_warn (_("Divide by zero."));
4625 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4628 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4632 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4634 if (strcmp (s2
, "mflo") == 0)
4635 move_register (&icnt
, dreg
, sreg
);
4637 move_register (&icnt
, dreg
, 0);
4640 if (imm_expr
.X_op
== O_constant
4641 && imm_expr
.X_add_number
== -1
4642 && s
[strlen (s
) - 1] != 'u')
4644 if (strcmp (s2
, "mflo") == 0)
4646 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4647 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4650 move_register (&icnt
, dreg
, 0);
4654 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4655 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4657 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4676 mips_emit_delays (true);
4677 ++mips_opts
.noreorder
;
4678 mips_any_noreorder
= 1;
4681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4682 "s,t,q", treg
, 0, 7);
4683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4685 /* We want to close the noreorder block as soon as possible, so
4686 that later insns are available for delay slot filling. */
4687 --mips_opts
.noreorder
;
4691 expr1
.X_add_number
= 8;
4692 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4693 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4696 /* We want to close the noreorder block as soon as possible, so
4697 that later insns are available for delay slot filling. */
4698 --mips_opts
.noreorder
;
4699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4702 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4708 /* Load the address of a symbol into a register. If breg is not
4709 zero, we then add a base register to it. */
4711 if (dbl
&& HAVE_32BIT_GPRS
)
4712 as_warn (_("dla used to load 32-bit register"));
4714 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4715 as_warn (_("la used to load 64-bit address"));
4717 if (offset_expr
.X_op
== O_constant
4718 && offset_expr
.X_add_number
>= -0x8000
4719 && offset_expr
.X_add_number
< 0x8000)
4721 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4722 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4723 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4738 /* When generating embedded PIC code, we permit expressions of
4741 la $treg,foo-bar($breg)
4742 where bar is an address in the current section. These are used
4743 when getting the addresses of functions. We don't permit
4744 X_add_number to be non-zero, because if the symbol is
4745 external the relaxing code needs to know that any addend is
4746 purely the offset to X_op_symbol. */
4747 if (mips_pic
== EMBEDDED_PIC
4748 && offset_expr
.X_op
== O_subtract
4749 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4750 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4751 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4753 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4756 && (offset_expr
.X_add_number
== 0
4757 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4763 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4764 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4768 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4769 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4770 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4771 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4772 "d,v,t", tempreg
, tempreg
, breg
);
4774 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4775 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4776 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4782 if (offset_expr
.X_op
!= O_symbol
4783 && offset_expr
.X_op
!= O_constant
)
4785 as_bad (_("expression too complex"));
4786 offset_expr
.X_op
= O_constant
;
4789 if (offset_expr
.X_op
== O_constant
)
4790 load_register (&icnt
, tempreg
, &offset_expr
,
4791 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4792 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4793 : HAVE_64BIT_ADDRESSES
));
4794 else if (mips_pic
== NO_PIC
)
4796 /* If this is a reference to a GP relative symbol, we want
4797 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4799 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4800 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4801 If we have a constant, we need two instructions anyhow,
4802 so we may as well always use the latter form.
4804 With 64bit address space and a usable $at we want
4805 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4806 lui $at,<sym> (BFD_RELOC_HI16_S)
4807 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4808 daddiu $at,<sym> (BFD_RELOC_LO16)
4810 daddu $tempreg,$tempreg,$at
4812 If $at is already in use, we use an path which is suboptimal
4813 on superscalar processors.
4814 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4815 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4817 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4819 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4822 if (HAVE_64BIT_ADDRESSES
)
4824 /* We don't do GP optimization for now because RELAX_ENCODE can't
4825 hold the data for such large chunks. */
4827 if (used_at
== 0 && ! mips_opts
.noat
)
4829 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4830 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4831 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4832 AT
, (int) BFD_RELOC_HI16_S
);
4833 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4834 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4835 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4836 AT
, AT
, (int) BFD_RELOC_LO16
);
4837 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4838 "d,w,<", tempreg
, tempreg
, 0);
4839 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
4840 "d,v,t", tempreg
, tempreg
, AT
);
4845 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4846 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4847 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4848 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4849 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4850 tempreg
, tempreg
, 16);
4851 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4852 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4853 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4854 tempreg
, tempreg
, 16);
4855 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4856 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4861 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4862 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4865 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4866 "t,r,j", tempreg
, mips_gp_register
,
4867 (int) BFD_RELOC_GPREL16
);
4868 p
= frag_var (rs_machine_dependent
, 8, 0,
4869 RELAX_ENCODE (4, 8, 0, 4, 0,
4870 mips_opts
.warn_about_macros
),
4871 offset_expr
.X_add_symbol
, 0, NULL
);
4873 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4876 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4877 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4880 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4882 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4884 /* If this is a reference to an external symbol, and there
4885 is no constant, we want
4886 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4887 or if tempreg is PIC_CALL_REG
4888 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4889 For a local symbol, we want
4890 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4892 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4894 If we have a small constant, and this is a reference to
4895 an external symbol, we want
4896 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4898 addiu $tempreg,$tempreg,<constant>
4899 For a local symbol, we want the same instruction
4900 sequence, but we output a BFD_RELOC_LO16 reloc on the
4903 If we have a large constant, and this is a reference to
4904 an external symbol, we want
4905 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4906 lui $at,<hiconstant>
4907 addiu $at,$at,<loconstant>
4908 addu $tempreg,$tempreg,$at
4909 For a local symbol, we want the same instruction
4910 sequence, but we output a BFD_RELOC_LO16 reloc on the
4913 For NewABI, we want for local or external data addresses
4914 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4915 For a local function symbol, we want
4916 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4918 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4921 expr1
.X_add_number
= offset_expr
.X_add_number
;
4922 offset_expr
.X_add_number
= 0;
4924 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4925 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4926 else if (HAVE_NEWABI
)
4927 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
4928 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4929 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4930 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
4931 if (expr1
.X_add_number
== 0)
4940 /* We're going to put in an addu instruction using
4941 tempreg, so we may as well insert the nop right
4943 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4947 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4948 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4950 ? mips_opts
.warn_about_macros
4952 offset_expr
.X_add_symbol
, 0, NULL
);
4955 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4958 macro_build (p
, &icnt
, &expr1
,
4959 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4960 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4961 /* FIXME: If breg == 0, and the next instruction uses
4962 $tempreg, then if this variant case is used an extra
4963 nop will be generated. */
4965 else if (expr1
.X_add_number
>= -0x8000
4966 && expr1
.X_add_number
< 0x8000)
4968 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4970 macro_build ((char *) NULL
, &icnt
, &expr1
,
4971 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4972 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4973 frag_var (rs_machine_dependent
, 0, 0,
4974 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4975 offset_expr
.X_add_symbol
, 0, NULL
);
4981 /* If we are going to add in a base register, and the
4982 target register and the base register are the same,
4983 then we are using AT as a temporary register. Since
4984 we want to load the constant into AT, we add our
4985 current AT (from the global offset table) and the
4986 register into the register now, and pretend we were
4987 not using a base register. */
4992 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4994 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4995 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4996 "d,v,t", treg
, AT
, breg
);
5002 /* Set mips_optimize around the lui instruction to avoid
5003 inserting an unnecessary nop after the lw. */
5004 hold_mips_optimize
= mips_optimize
;
5006 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5007 mips_optimize
= hold_mips_optimize
;
5009 macro_build ((char *) NULL
, &icnt
, &expr1
,
5010 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5011 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5012 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5013 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5014 "d,v,t", tempreg
, tempreg
, AT
);
5015 frag_var (rs_machine_dependent
, 0, 0,
5016 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
5017 offset_expr
.X_add_symbol
, 0, NULL
);
5021 else if (mips_pic
== SVR4_PIC
)
5025 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5026 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5027 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5029 /* This is the large GOT case. If this is a reference to an
5030 external symbol, and there is no constant, we want
5031 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5032 addu $tempreg,$tempreg,$gp
5033 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5034 or if tempreg is PIC_CALL_REG
5035 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5036 addu $tempreg,$tempreg,$gp
5037 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5038 For a local symbol, we want
5039 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5041 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5043 If we have a small constant, and this is a reference to
5044 an external symbol, we want
5045 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5046 addu $tempreg,$tempreg,$gp
5047 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5049 addiu $tempreg,$tempreg,<constant>
5050 For a local symbol, we want
5051 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5053 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5055 If we have a large constant, and this is a reference to
5056 an external symbol, we want
5057 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5058 addu $tempreg,$tempreg,$gp
5059 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5060 lui $at,<hiconstant>
5061 addiu $at,$at,<loconstant>
5062 addu $tempreg,$tempreg,$at
5063 For a local symbol, we want
5064 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5065 lui $at,<hiconstant>
5066 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5067 addu $tempreg,$tempreg,$at
5069 For NewABI, we want for local data addresses
5070 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5073 expr1
.X_add_number
= offset_expr
.X_add_number
;
5074 offset_expr
.X_add_number
= 0;
5076 if (reg_needs_delay (mips_gp_register
))
5080 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5082 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5083 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5085 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5086 tempreg
, lui_reloc_type
);
5087 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5088 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5089 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5090 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5091 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5092 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5093 if (expr1
.X_add_number
== 0)
5101 /* We're going to put in an addu instruction using
5102 tempreg, so we may as well insert the nop right
5104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5109 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5110 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
5113 ? mips_opts
.warn_about_macros
5115 offset_expr
.X_add_symbol
, 0, NULL
);
5117 else if (expr1
.X_add_number
>= -0x8000
5118 && expr1
.X_add_number
< 0x8000)
5120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5122 macro_build ((char *) NULL
, &icnt
, &expr1
,
5123 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5124 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5126 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5127 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
5129 ? mips_opts
.warn_about_macros
5131 offset_expr
.X_add_symbol
, 0, NULL
);
5137 /* If we are going to add in a base register, and the
5138 target register and the base register are the same,
5139 then we are using AT as a temporary register. Since
5140 we want to load the constant into AT, we add our
5141 current AT (from the global offset table) and the
5142 register into the register now, and pretend we were
5143 not using a base register. */
5151 assert (tempreg
== AT
);
5152 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5154 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5155 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5156 "d,v,t", treg
, AT
, breg
);
5161 /* Set mips_optimize around the lui instruction to avoid
5162 inserting an unnecessary nop after the lw. */
5163 hold_mips_optimize
= mips_optimize
;
5165 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5166 mips_optimize
= hold_mips_optimize
;
5168 macro_build ((char *) NULL
, &icnt
, &expr1
,
5169 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5170 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5171 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5172 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5173 "d,v,t", dreg
, dreg
, AT
);
5175 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5176 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5179 ? mips_opts
.warn_about_macros
5181 offset_expr
.X_add_symbol
, 0, NULL
);
5188 /* This is needed because this instruction uses $gp, but
5189 the first instruction on the main stream does not. */
5190 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5195 local_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5196 macro_build (p
, &icnt
, &offset_expr
,
5197 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5202 if (expr1
.X_add_number
== 0 && HAVE_NEWABI
)
5204 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
5207 if (expr1
.X_add_number
>= -0x8000
5208 && expr1
.X_add_number
< 0x8000)
5210 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5212 macro_build (p
, &icnt
, &expr1
,
5213 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5214 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5215 /* FIXME: If add_number is 0, and there was no base
5216 register, the external symbol case ended with a load,
5217 so if the symbol turns out to not be external, and
5218 the next instruction uses tempreg, an unnecessary nop
5219 will be inserted. */
5225 /* We must add in the base register now, as in the
5226 external symbol case. */
5227 assert (tempreg
== AT
);
5228 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5230 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5231 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5232 "d,v,t", treg
, AT
, breg
);
5235 /* We set breg to 0 because we have arranged to add
5236 it in in both cases. */
5240 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5242 macro_build (p
, &icnt
, &expr1
,
5243 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5244 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5246 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5247 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5248 "d,v,t", tempreg
, tempreg
, AT
);
5252 else if (mips_pic
== EMBEDDED_PIC
)
5255 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5257 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5258 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5259 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5268 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5269 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5271 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5273 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5274 "d,v,t", treg
, tempreg
, breg
);
5283 /* The j instruction may not be used in PIC code, since it
5284 requires an absolute address. We convert it to a b
5286 if (mips_pic
== NO_PIC
)
5287 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5289 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5292 /* The jal instructions must be handled as macros because when
5293 generating PIC code they expand to multi-instruction
5294 sequences. Normally they are simple instructions. */
5299 if (mips_pic
== NO_PIC
5300 || mips_pic
== EMBEDDED_PIC
)
5301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5303 else if (mips_pic
== SVR4_PIC
)
5305 if (sreg
!= PIC_CALL_REG
)
5306 as_warn (_("MIPS PIC call to register other than $25"));
5308 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5312 if (mips_cprestore_offset
< 0)
5313 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5316 if (! mips_frame_reg_valid
)
5318 as_warn (_("No .frame pseudo-op used in PIC code"));
5319 /* Quiet this warning. */
5320 mips_frame_reg_valid
= 1;
5322 if (! mips_cprestore_valid
)
5324 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5325 /* Quiet this warning. */
5326 mips_cprestore_valid
= 1;
5328 expr1
.X_add_number
= mips_cprestore_offset
;
5329 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5330 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5331 mips_gp_register
, mips_frame_reg
);
5341 if (mips_pic
== NO_PIC
)
5342 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5343 else if (mips_pic
== SVR4_PIC
)
5347 /* If this is a reference to an external symbol, and we are
5348 using a small GOT, we want
5349 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5353 lw $gp,cprestore($sp)
5354 The cprestore value is set using the .cprestore
5355 pseudo-op. If we are using a big GOT, we want
5356 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5358 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5362 lw $gp,cprestore($sp)
5363 If the symbol is not external, we want
5364 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5366 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5369 lw $gp,cprestore($sp)
5371 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5372 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5376 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5377 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5378 "t,o(b)", PIC_CALL_REG
,
5379 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5380 macro_build_jalr (icnt
, &offset_expr
);
5387 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5388 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5389 "t,o(b)", PIC_CALL_REG
,
5390 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5391 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5393 p
= frag_var (rs_machine_dependent
, 4, 0,
5394 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5395 offset_expr
.X_add_symbol
, 0, NULL
);
5401 if (reg_needs_delay (mips_gp_register
))
5405 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5406 "t,u", PIC_CALL_REG
,
5407 (int) BFD_RELOC_MIPS_CALL_HI16
);
5408 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5409 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5410 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5412 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5413 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5414 "t,o(b)", PIC_CALL_REG
,
5415 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5416 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5418 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5419 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5421 offset_expr
.X_add_symbol
, 0, NULL
);
5424 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5427 macro_build (p
, &icnt
, &offset_expr
,
5428 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5429 "t,o(b)", PIC_CALL_REG
,
5430 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5432 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5435 macro_build (p
, &icnt
, &offset_expr
,
5436 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5437 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5438 (int) BFD_RELOC_LO16
);
5439 macro_build_jalr (icnt
, &offset_expr
);
5441 if (mips_cprestore_offset
< 0)
5442 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5445 if (! mips_frame_reg_valid
)
5447 as_warn (_("No .frame pseudo-op used in PIC code"));
5448 /* Quiet this warning. */
5449 mips_frame_reg_valid
= 1;
5451 if (! mips_cprestore_valid
)
5453 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5454 /* Quiet this warning. */
5455 mips_cprestore_valid
= 1;
5457 if (mips_opts
.noreorder
)
5458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5460 expr1
.X_add_number
= mips_cprestore_offset
;
5461 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5462 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5463 mips_gp_register
, mips_frame_reg
);
5467 else if (mips_pic
== EMBEDDED_PIC
)
5469 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5470 /* The linker may expand the call to a longer sequence which
5471 uses $at, so we must break rather than return. */
5496 /* Itbl support may require additional care here. */
5501 /* Itbl support may require additional care here. */
5506 /* Itbl support may require additional care here. */
5511 /* Itbl support may require additional care here. */
5523 if (mips_arch
== CPU_R4650
)
5525 as_bad (_("opcode not supported on this processor"));
5529 /* Itbl support may require additional care here. */
5534 /* Itbl support may require additional care here. */
5539 /* Itbl support may require additional care here. */
5559 if (breg
== treg
|| coproc
|| lr
)
5581 /* Itbl support may require additional care here. */
5586 /* Itbl support may require additional care here. */
5591 /* Itbl support may require additional care here. */
5596 /* Itbl support may require additional care here. */
5612 if (mips_arch
== CPU_R4650
)
5614 as_bad (_("opcode not supported on this processor"));
5619 /* Itbl support may require additional care here. */
5623 /* Itbl support may require additional care here. */
5628 /* Itbl support may require additional care here. */
5640 /* Itbl support may require additional care here. */
5641 if (mask
== M_LWC1_AB
5642 || mask
== M_SWC1_AB
5643 || mask
== M_LDC1_AB
5644 || mask
== M_SDC1_AB
5653 /* For embedded PIC, we allow loads where the offset is calculated
5654 by subtracting a symbol in the current segment from an unknown
5655 symbol, relative to a base register, e.g.:
5656 <op> $treg, <sym>-<localsym>($breg)
5657 This is used by the compiler for switch statements. */
5658 if (mips_pic
== EMBEDDED_PIC
5659 && offset_expr
.X_op
== O_subtract
5660 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5661 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5662 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5664 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5668 && (offset_expr
.X_add_number
== 0
5669 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5671 /* For this case, we output the instructions:
5672 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5673 addiu $tempreg,$tempreg,$breg
5674 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5675 If the relocation would fit entirely in 16 bits, it would be
5677 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5678 instead, but that seems quite difficult. */
5679 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5680 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5682 ((bfd_arch_bits_per_address (stdoutput
) == 32
5683 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5684 ? "addu" : "daddu"),
5685 "d,v,t", tempreg
, tempreg
, breg
);
5686 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5687 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5693 if (offset_expr
.X_op
!= O_constant
5694 && offset_expr
.X_op
!= O_symbol
)
5696 as_bad (_("expression too complex"));
5697 offset_expr
.X_op
= O_constant
;
5700 /* A constant expression in PIC code can be handled just as it
5701 is in non PIC code. */
5702 if (mips_pic
== NO_PIC
5703 || offset_expr
.X_op
== O_constant
)
5707 /* If this is a reference to a GP relative symbol, and there
5708 is no base register, we want
5709 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5710 Otherwise, if there is no base register, we want
5711 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5712 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5713 If we have a constant, we need two instructions anyhow,
5714 so we always use the latter form.
5716 If we have a base register, and this is a reference to a
5717 GP relative symbol, we want
5718 addu $tempreg,$breg,$gp
5719 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5721 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5722 addu $tempreg,$tempreg,$breg
5723 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5724 With a constant we always use the latter case.
5726 With 64bit address space and no base register and $at usable,
5728 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5729 lui $at,<sym> (BFD_RELOC_HI16_S)
5730 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5733 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5734 If we have a base register, we want
5735 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5736 lui $at,<sym> (BFD_RELOC_HI16_S)
5737 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5741 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5743 Without $at we can't generate the optimal path for superscalar
5744 processors here since this would require two temporary registers.
5745 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5746 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5748 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5750 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5751 If we have a base register, we want
5752 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5753 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5755 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5757 daddu $tempreg,$tempreg,$breg
5758 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5760 If we have 64-bit addresses, as an optimization, for
5761 addresses which are 32-bit constants (e.g. kseg0/kseg1
5762 addresses) we fall back to the 32-bit address generation
5763 mechanism since it is more efficient. Note that due to
5764 the signed offset used by memory operations, the 32-bit
5765 range is shifted down by 32768 here. This code should
5766 probably attempt to generate 64-bit constants more
5767 efficiently in general.
5769 if (HAVE_64BIT_ADDRESSES
5770 && !(offset_expr
.X_op
== O_constant
5771 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5775 /* We don't do GP optimization for now because RELAX_ENCODE can't
5776 hold the data for such large chunks. */
5778 if (used_at
== 0 && ! mips_opts
.noat
)
5780 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5781 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5782 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5783 AT
, (int) BFD_RELOC_HI16_S
);
5784 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5785 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5787 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5788 "d,v,t", AT
, AT
, breg
);
5789 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5790 "d,w,<", tempreg
, tempreg
, 0);
5791 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5792 "d,v,t", tempreg
, tempreg
, AT
);
5793 macro_build (p
, &icnt
, &offset_expr
, s
,
5794 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5799 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5800 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5801 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5802 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5803 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5804 "d,w,<", tempreg
, tempreg
, 16);
5805 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5806 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5807 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5808 "d,w,<", tempreg
, tempreg
, 16);
5810 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5811 "d,v,t", tempreg
, tempreg
, breg
);
5812 macro_build (p
, &icnt
, &offset_expr
, s
,
5813 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5821 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5822 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5827 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5828 treg
, (int) BFD_RELOC_GPREL16
,
5830 p
= frag_var (rs_machine_dependent
, 8, 0,
5831 RELAX_ENCODE (4, 8, 0, 4, 0,
5832 (mips_opts
.warn_about_macros
5834 && mips_opts
.noat
))),
5835 offset_expr
.X_add_symbol
, 0, NULL
);
5838 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5841 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5842 (int) BFD_RELOC_LO16
, tempreg
);
5846 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5847 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5852 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5853 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5854 "d,v,t", tempreg
, breg
, mips_gp_register
);
5855 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5856 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5857 p
= frag_var (rs_machine_dependent
, 12, 0,
5858 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5859 offset_expr
.X_add_symbol
, 0, NULL
);
5861 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5864 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5865 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5866 "d,v,t", tempreg
, tempreg
, breg
);
5869 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5870 (int) BFD_RELOC_LO16
, tempreg
);
5873 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5876 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5878 /* If this is a reference to an external symbol, we want
5879 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5881 <op> $treg,0($tempreg)
5883 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5885 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5886 <op> $treg,0($tempreg)
5887 If we have NewABI, we want
5888 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5889 If there is a base register, we add it to $tempreg before
5890 the <op>. If there is a constant, we stick it in the
5891 <op> instruction. We don't handle constants larger than
5892 16 bits, because we have no way to load the upper 16 bits
5893 (actually, we could handle them for the subset of cases
5894 in which we are not using $at). */
5895 assert (offset_expr
.X_op
== O_symbol
);
5896 expr1
.X_add_number
= offset_expr
.X_add_number
;
5897 offset_expr
.X_add_number
= 0;
5899 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5900 if (expr1
.X_add_number
< -0x8000
5901 || expr1
.X_add_number
>= 0x8000)
5902 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5904 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5905 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
5906 (int) lw_reloc_type
, mips_gp_register
);
5907 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5908 p
= frag_var (rs_machine_dependent
, 4, 0,
5909 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5910 offset_expr
.X_add_symbol
, 0, NULL
);
5911 macro_build (p
, &icnt
, &offset_expr
,
5912 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5913 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5915 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5916 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5917 "d,v,t", tempreg
, tempreg
, breg
);
5918 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5919 (int) BFD_RELOC_LO16
, tempreg
);
5921 else if (mips_pic
== SVR4_PIC
)
5926 /* If this is a reference to an external symbol, we want
5927 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5928 addu $tempreg,$tempreg,$gp
5929 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5930 <op> $treg,0($tempreg)
5932 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5934 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5935 <op> $treg,0($tempreg)
5936 If there is a base register, we add it to $tempreg before
5937 the <op>. If there is a constant, we stick it in the
5938 <op> instruction. We don't handle constants larger than
5939 16 bits, because we have no way to load the upper 16 bits
5940 (actually, we could handle them for the subset of cases
5941 in which we are not using $at).
5944 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5945 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5946 <op> $treg,0($tempreg)
5948 assert (offset_expr
.X_op
== O_symbol
);
5949 expr1
.X_add_number
= offset_expr
.X_add_number
;
5950 offset_expr
.X_add_number
= 0;
5951 if (expr1
.X_add_number
< -0x8000
5952 || expr1
.X_add_number
>= 0x8000)
5953 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5956 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5957 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5958 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
5960 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5961 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5962 "t,r,j", tempreg
, tempreg
,
5963 BFD_RELOC_MIPS_GOT_OFST
);
5965 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5966 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5967 "d,v,t", tempreg
, tempreg
, breg
);
5968 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5969 (int) BFD_RELOC_LO16
, tempreg
);
5976 if (reg_needs_delay (mips_gp_register
))
5981 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5982 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5983 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5984 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5985 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5986 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5987 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5988 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5990 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5991 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5992 offset_expr
.X_add_symbol
, 0, NULL
);
5995 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5998 macro_build (p
, &icnt
, &offset_expr
,
5999 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6000 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
6003 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6005 macro_build (p
, &icnt
, &offset_expr
,
6006 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6007 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6009 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6010 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6011 "d,v,t", tempreg
, tempreg
, breg
);
6012 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6013 (int) BFD_RELOC_LO16
, tempreg
);
6015 else if (mips_pic
== EMBEDDED_PIC
)
6017 /* If there is no base register, we want
6018 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6019 If there is a base register, we want
6020 addu $tempreg,$breg,$gp
6021 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6023 assert (offset_expr
.X_op
== O_symbol
);
6026 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6027 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
6032 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6033 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6034 "d,v,t", tempreg
, breg
, mips_gp_register
);
6035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6036 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6049 load_register (&icnt
, treg
, &imm_expr
, 0);
6053 load_register (&icnt
, treg
, &imm_expr
, 1);
6057 if (imm_expr
.X_op
== O_constant
)
6059 load_register (&icnt
, AT
, &imm_expr
, 0);
6060 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6061 "mtc1", "t,G", AT
, treg
);
6066 assert (offset_expr
.X_op
== O_symbol
6067 && strcmp (segment_name (S_GET_SEGMENT
6068 (offset_expr
.X_add_symbol
)),
6070 && offset_expr
.X_add_number
== 0);
6071 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6072 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6077 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6078 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6079 order 32 bits of the value and the low order 32 bits are either
6080 zero or in OFFSET_EXPR. */
6081 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6083 if (HAVE_64BIT_GPRS
)
6084 load_register (&icnt
, treg
, &imm_expr
, 1);
6089 if (target_big_endian
)
6101 load_register (&icnt
, hreg
, &imm_expr
, 0);
6104 if (offset_expr
.X_op
== O_absent
)
6105 move_register (&icnt
, lreg
, 0);
6108 assert (offset_expr
.X_op
== O_constant
);
6109 load_register (&icnt
, lreg
, &offset_expr
, 0);
6116 /* We know that sym is in the .rdata section. First we get the
6117 upper 16 bits of the address. */
6118 if (mips_pic
== NO_PIC
)
6120 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6122 else if (mips_pic
== SVR4_PIC
)
6124 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6125 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6126 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6129 else if (mips_pic
== EMBEDDED_PIC
)
6131 /* For embedded PIC we pick up the entire address off $gp in
6132 a single instruction. */
6133 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6134 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
6135 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
6136 offset_expr
.X_op
= O_constant
;
6137 offset_expr
.X_add_number
= 0;
6142 /* Now we load the register(s). */
6143 if (HAVE_64BIT_GPRS
)
6144 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
6145 treg
, (int) BFD_RELOC_LO16
, AT
);
6148 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6149 treg
, (int) BFD_RELOC_LO16
, AT
);
6152 /* FIXME: How in the world do we deal with the possible
6154 offset_expr
.X_add_number
+= 4;
6155 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6156 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
6160 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6161 does not become a variant frag. */
6162 frag_wane (frag_now
);
6168 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6169 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6170 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6171 the value and the low order 32 bits are either zero or in
6173 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6175 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6176 if (HAVE_64BIT_FPRS
)
6178 assert (HAVE_64BIT_GPRS
);
6179 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6180 "dmtc1", "t,S", AT
, treg
);
6184 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6185 "mtc1", "t,G", AT
, treg
+ 1);
6186 if (offset_expr
.X_op
== O_absent
)
6187 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6188 "mtc1", "t,G", 0, treg
);
6191 assert (offset_expr
.X_op
== O_constant
);
6192 load_register (&icnt
, AT
, &offset_expr
, 0);
6193 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6194 "mtc1", "t,G", AT
, treg
);
6200 assert (offset_expr
.X_op
== O_symbol
6201 && offset_expr
.X_add_number
== 0);
6202 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6203 if (strcmp (s
, ".lit8") == 0)
6205 if (mips_opts
.isa
!= ISA_MIPS1
)
6207 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6208 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6212 breg
= mips_gp_register
;
6213 r
= BFD_RELOC_MIPS_LITERAL
;
6218 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6219 if (mips_pic
== SVR4_PIC
)
6220 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6221 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6222 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6226 /* FIXME: This won't work for a 64 bit address. */
6227 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6230 if (mips_opts
.isa
!= ISA_MIPS1
)
6232 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6233 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6235 /* To avoid confusion in tc_gen_reloc, we must ensure
6236 that this does not become a variant frag. */
6237 frag_wane (frag_now
);
6248 if (mips_arch
== CPU_R4650
)
6250 as_bad (_("opcode not supported on this processor"));
6253 /* Even on a big endian machine $fn comes before $fn+1. We have
6254 to adjust when loading from memory. */
6257 assert (mips_opts
.isa
== ISA_MIPS1
);
6258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6259 target_big_endian
? treg
+ 1 : treg
,
6261 /* FIXME: A possible overflow which I don't know how to deal
6263 offset_expr
.X_add_number
+= 4;
6264 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6265 target_big_endian
? treg
: treg
+ 1,
6268 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6269 does not become a variant frag. */
6270 frag_wane (frag_now
);
6279 * The MIPS assembler seems to check for X_add_number not
6280 * being double aligned and generating:
6283 * addiu at,at,%lo(foo+1)
6286 * But, the resulting address is the same after relocation so why
6287 * generate the extra instruction?
6289 if (mips_arch
== CPU_R4650
)
6291 as_bad (_("opcode not supported on this processor"));
6294 /* Itbl support may require additional care here. */
6296 if (mips_opts
.isa
!= ISA_MIPS1
)
6307 if (mips_arch
== CPU_R4650
)
6309 as_bad (_("opcode not supported on this processor"));
6313 if (mips_opts
.isa
!= ISA_MIPS1
)
6321 /* Itbl support may require additional care here. */
6326 if (HAVE_64BIT_GPRS
)
6337 if (HAVE_64BIT_GPRS
)
6347 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6348 loads for the case of doing a pair of loads to simulate an 'ld'.
6349 This is not currently done by the compiler, and assembly coders
6350 writing embedded-pic code can cope. */
6352 if (offset_expr
.X_op
!= O_symbol
6353 && offset_expr
.X_op
!= O_constant
)
6355 as_bad (_("expression too complex"));
6356 offset_expr
.X_op
= O_constant
;
6359 /* Even on a big endian machine $fn comes before $fn+1. We have
6360 to adjust when loading from memory. We set coproc if we must
6361 load $fn+1 first. */
6362 /* Itbl support may require additional care here. */
6363 if (! target_big_endian
)
6366 if (mips_pic
== NO_PIC
6367 || offset_expr
.X_op
== O_constant
)
6371 /* If this is a reference to a GP relative symbol, we want
6372 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6373 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6374 If we have a base register, we use this
6376 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6377 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6378 If this is not a GP relative symbol, we want
6379 lui $at,<sym> (BFD_RELOC_HI16_S)
6380 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6381 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6382 If there is a base register, we add it to $at after the
6383 lui instruction. If there is a constant, we always use
6385 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6386 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6398 tempreg
= mips_gp_register
;
6405 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6406 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6407 "d,v,t", AT
, breg
, mips_gp_register
);
6413 /* Itbl support may require additional care here. */
6414 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6415 coproc
? treg
+ 1 : treg
,
6416 (int) BFD_RELOC_GPREL16
, tempreg
);
6417 offset_expr
.X_add_number
+= 4;
6419 /* Set mips_optimize to 2 to avoid inserting an
6421 hold_mips_optimize
= mips_optimize
;
6423 /* Itbl support may require additional care here. */
6424 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6425 coproc
? treg
: treg
+ 1,
6426 (int) BFD_RELOC_GPREL16
, tempreg
);
6427 mips_optimize
= hold_mips_optimize
;
6429 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6430 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6431 used_at
&& mips_opts
.noat
),
6432 offset_expr
.X_add_symbol
, 0, NULL
);
6434 /* We just generated two relocs. When tc_gen_reloc
6435 handles this case, it will skip the first reloc and
6436 handle the second. The second reloc already has an
6437 extra addend of 4, which we added above. We must
6438 subtract it out, and then subtract another 4 to make
6439 the first reloc come out right. The second reloc
6440 will come out right because we are going to add 4 to
6441 offset_expr when we build its instruction below.
6443 If we have a symbol, then we don't want to include
6444 the offset, because it will wind up being included
6445 when we generate the reloc. */
6447 if (offset_expr
.X_op
== O_constant
)
6448 offset_expr
.X_add_number
-= 8;
6451 offset_expr
.X_add_number
= -4;
6452 offset_expr
.X_op
= O_constant
;
6455 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6460 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6461 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6462 "d,v,t", AT
, breg
, AT
);
6466 /* Itbl support may require additional care here. */
6467 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6468 coproc
? treg
+ 1 : treg
,
6469 (int) BFD_RELOC_LO16
, AT
);
6472 /* FIXME: How do we handle overflow here? */
6473 offset_expr
.X_add_number
+= 4;
6474 /* Itbl support may require additional care here. */
6475 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6476 coproc
? treg
: treg
+ 1,
6477 (int) BFD_RELOC_LO16
, AT
);
6479 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6483 /* If this is a reference to an external symbol, we want
6484 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6489 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6491 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6492 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6493 If there is a base register we add it to $at before the
6494 lwc1 instructions. If there is a constant we include it
6495 in the lwc1 instructions. */
6497 expr1
.X_add_number
= offset_expr
.X_add_number
;
6498 offset_expr
.X_add_number
= 0;
6499 if (expr1
.X_add_number
< -0x8000
6500 || expr1
.X_add_number
>= 0x8000 - 4)
6501 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6506 frag_grow (24 + off
);
6507 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6508 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
6509 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6510 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6512 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6513 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6514 "d,v,t", AT
, breg
, AT
);
6515 /* Itbl support may require additional care here. */
6516 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6517 coproc
? treg
+ 1 : treg
,
6518 (int) BFD_RELOC_LO16
, AT
);
6519 expr1
.X_add_number
+= 4;
6521 /* Set mips_optimize to 2 to avoid inserting an undesired
6523 hold_mips_optimize
= mips_optimize
;
6525 /* Itbl support may require additional care here. */
6526 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6527 coproc
? treg
: treg
+ 1,
6528 (int) BFD_RELOC_LO16
, AT
);
6529 mips_optimize
= hold_mips_optimize
;
6531 (void) frag_var (rs_machine_dependent
, 0, 0,
6532 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6533 offset_expr
.X_add_symbol
, 0, NULL
);
6535 else if (mips_pic
== SVR4_PIC
)
6540 /* If this is a reference to an external symbol, we want
6541 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6543 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6548 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6550 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6551 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6552 If there is a base register we add it to $at before the
6553 lwc1 instructions. If there is a constant we include it
6554 in the lwc1 instructions. */
6556 expr1
.X_add_number
= offset_expr
.X_add_number
;
6557 offset_expr
.X_add_number
= 0;
6558 if (expr1
.X_add_number
< -0x8000
6559 || expr1
.X_add_number
>= 0x8000 - 4)
6560 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6561 if (reg_needs_delay (mips_gp_register
))
6570 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6571 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6572 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6573 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6574 "d,v,t", AT
, AT
, mips_gp_register
);
6575 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6576 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6577 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6578 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6580 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6581 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6582 "d,v,t", AT
, breg
, AT
);
6583 /* Itbl support may require additional care here. */
6584 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6585 coproc
? treg
+ 1 : treg
,
6586 (int) BFD_RELOC_LO16
, AT
);
6587 expr1
.X_add_number
+= 4;
6589 /* Set mips_optimize to 2 to avoid inserting an undesired
6591 hold_mips_optimize
= mips_optimize
;
6593 /* Itbl support may require additional care here. */
6594 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6595 coproc
? treg
: treg
+ 1,
6596 (int) BFD_RELOC_LO16
, AT
);
6597 mips_optimize
= hold_mips_optimize
;
6598 expr1
.X_add_number
-= 4;
6600 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6601 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6602 8 + gpdel
+ off
, 1, 0),
6603 offset_expr
.X_add_symbol
, 0, NULL
);
6606 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6609 macro_build (p
, &icnt
, &offset_expr
,
6610 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6611 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6614 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6618 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6619 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6620 "d,v,t", AT
, breg
, AT
);
6623 /* Itbl support may require additional care here. */
6624 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6625 coproc
? treg
+ 1 : treg
,
6626 (int) BFD_RELOC_LO16
, AT
);
6628 expr1
.X_add_number
+= 4;
6630 /* Set mips_optimize to 2 to avoid inserting an undesired
6632 hold_mips_optimize
= mips_optimize
;
6634 /* Itbl support may require additional care here. */
6635 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6636 coproc
? treg
: treg
+ 1,
6637 (int) BFD_RELOC_LO16
, AT
);
6638 mips_optimize
= hold_mips_optimize
;
6640 else if (mips_pic
== EMBEDDED_PIC
)
6642 /* If there is no base register, we use
6643 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6644 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6645 If we have a base register, we use
6647 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6648 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6652 tempreg
= mips_gp_register
;
6657 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6658 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6659 "d,v,t", AT
, breg
, mips_gp_register
);
6664 /* Itbl support may require additional care here. */
6665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6666 coproc
? treg
+ 1 : treg
,
6667 (int) BFD_RELOC_GPREL16
, tempreg
);
6668 offset_expr
.X_add_number
+= 4;
6669 /* Itbl support may require additional care here. */
6670 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6671 coproc
? treg
: treg
+ 1,
6672 (int) BFD_RELOC_GPREL16
, tempreg
);
6688 assert (HAVE_32BIT_ADDRESSES
);
6689 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6690 (int) BFD_RELOC_LO16
, breg
);
6691 offset_expr
.X_add_number
+= 4;
6692 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6693 (int) BFD_RELOC_LO16
, breg
);
6696 /* New code added to support COPZ instructions.
6697 This code builds table entries out of the macros in mip_opcodes.
6698 R4000 uses interlocks to handle coproc delays.
6699 Other chips (like the R3000) require nops to be inserted for delays.
6701 FIXME: Currently, we require that the user handle delays.
6702 In order to fill delay slots for non-interlocked chips,
6703 we must have a way to specify delays based on the coprocessor.
6704 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6705 What are the side-effects of the cop instruction?
6706 What cache support might we have and what are its effects?
6707 Both coprocessor & memory require delays. how long???
6708 What registers are read/set/modified?
6710 If an itbl is provided to interpret cop instructions,
6711 this knowledge can be encoded in the itbl spec. */
6725 /* For now we just do C (same as Cz). The parameter will be
6726 stored in insn_opcode by mips_ip. */
6727 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6732 move_register (&icnt
, dreg
, sreg
);
6735 #ifdef LOSING_COMPILER
6737 /* Try and see if this is a new itbl instruction.
6738 This code builds table entries out of the macros in mip_opcodes.
6739 FIXME: For now we just assemble the expression and pass it's
6740 value along as a 32-bit immediate.
6741 We may want to have the assembler assemble this value,
6742 so that we gain the assembler's knowledge of delay slots,
6744 Would it be more efficient to use mask (id) here? */
6745 if (itbl_have_entries
6746 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6748 s
= ip
->insn_mo
->name
;
6750 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6751 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6758 as_warn (_("Macro used $at after \".set noat\""));
6763 struct mips_cl_insn
*ip
;
6765 register int treg
, sreg
, dreg
, breg
;
6781 bfd_reloc_code_real_type r
;
6784 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6785 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6786 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6787 mask
= ip
->insn_mo
->mask
;
6789 expr1
.X_op
= O_constant
;
6790 expr1
.X_op_symbol
= NULL
;
6791 expr1
.X_add_symbol
= NULL
;
6792 expr1
.X_add_number
= 1;
6796 #endif /* LOSING_COMPILER */
6801 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6802 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6810 /* The MIPS assembler some times generates shifts and adds. I'm
6811 not trying to be that fancy. GCC should do this for us
6813 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6814 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6815 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6830 mips_emit_delays (true);
6831 ++mips_opts
.noreorder
;
6832 mips_any_noreorder
= 1;
6834 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6835 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6836 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6839 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6840 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6844 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6845 "s,t,q", dreg
, AT
, 6);
6848 expr1
.X_add_number
= 8;
6849 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6851 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6853 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6856 --mips_opts
.noreorder
;
6857 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6870 mips_emit_delays (true);
6871 ++mips_opts
.noreorder
;
6872 mips_any_noreorder
= 1;
6874 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6875 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6876 dbl
? "dmultu" : "multu",
6877 "s,t", sreg
, imm
? AT
: treg
);
6878 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6880 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6883 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6887 expr1
.X_add_number
= 8;
6888 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6889 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6891 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6894 --mips_opts
.noreorder
;
6898 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6899 "d,v,t", AT
, 0, treg
);
6900 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6901 "d,t,s", AT
, sreg
, AT
);
6902 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6903 "d,t,s", dreg
, sreg
, treg
);
6904 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6905 "d,v,t", dreg
, dreg
, AT
);
6909 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6910 "d,v,t", AT
, 0, treg
);
6911 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6912 "d,t,s", AT
, sreg
, AT
);
6913 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6914 "d,t,s", dreg
, sreg
, treg
);
6915 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6916 "d,v,t", dreg
, dreg
, AT
);
6923 if (imm_expr
.X_op
!= O_constant
)
6924 as_bad (_("rotate count too large"));
6925 rot
= imm_expr
.X_add_number
& 0x3f;
6926 if (CPU_HAS_DROR (mips_arch
))
6928 rot
= (64 - rot
) & 0x3f;
6930 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
6931 "d,w,<", dreg
, sreg
, rot
- 32);
6933 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
6934 "d,w,<", dreg
, sreg
, rot
);
6938 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
6939 "d,w,<", dreg
, sreg
, 0);
6944 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6945 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6947 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6948 "d,w,<", AT
, sreg
, rot
);
6949 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6950 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6951 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6952 "d,v,t", dreg
, dreg
, AT
);
6961 if (imm_expr
.X_op
!= O_constant
)
6962 as_bad (_("rotate count too large"));
6963 rot
= imm_expr
.X_add_number
& 0x1f;
6964 if (CPU_HAS_ROR (mips_arch
))
6966 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
6967 "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6971 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6972 "d,w,<", dreg
, sreg
, 0);
6975 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6976 "d,w,<", AT
, sreg
, rot
);
6977 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6978 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6979 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6980 "d,v,t", dreg
, dreg
, AT
);
6986 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6987 "d,v,t", AT
, 0, treg
);
6988 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6989 "d,t,s", AT
, sreg
, AT
);
6990 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6991 "d,t,s", dreg
, sreg
, treg
);
6992 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6993 "d,v,t", dreg
, dreg
, AT
);
6997 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6998 "d,v,t", AT
, 0, treg
);
6999 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7000 "d,t,s", AT
, sreg
, AT
);
7001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7002 "d,t,s", dreg
, sreg
, treg
);
7003 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7004 "d,v,t", dreg
, dreg
, AT
);
7011 if (imm_expr
.X_op
!= O_constant
)
7012 as_bad (_("rotate count too large"));
7013 rot
= imm_expr
.X_add_number
& 0x3f;
7015 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7016 "d,w,<", dreg
, sreg
, 0);
7021 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7022 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7024 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7025 "d,w,<", AT
, sreg
, rot
);
7026 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7027 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7029 "d,v,t", dreg
, dreg
, AT
);
7038 if (imm_expr
.X_op
!= O_constant
)
7039 as_bad (_("rotate count too large"));
7040 rot
= imm_expr
.X_add_number
& 0x1f;
7042 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7043 "d,w,<", dreg
, sreg
, 0);
7046 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7047 "d,w,<", AT
, sreg
, rot
);
7048 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7049 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7050 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7051 "d,v,t", dreg
, dreg
, AT
);
7057 if (mips_arch
== CPU_R4650
)
7059 as_bad (_("opcode not supported on this processor"));
7062 assert (mips_opts
.isa
== ISA_MIPS1
);
7063 /* Even on a big endian machine $fn comes before $fn+1. We have
7064 to adjust when storing to memory. */
7065 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7066 target_big_endian
? treg
+ 1 : treg
,
7067 (int) BFD_RELOC_LO16
, breg
);
7068 offset_expr
.X_add_number
+= 4;
7069 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7070 target_big_endian
? treg
: treg
+ 1,
7071 (int) BFD_RELOC_LO16
, breg
);
7076 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7077 treg
, (int) BFD_RELOC_LO16
);
7079 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7080 sreg
, (int) BFD_RELOC_LO16
);
7083 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7084 "d,v,t", dreg
, sreg
, treg
);
7085 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7086 dreg
, (int) BFD_RELOC_LO16
);
7091 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7093 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7094 sreg
, (int) BFD_RELOC_LO16
);
7099 as_warn (_("Instruction %s: result is always false"),
7101 move_register (&icnt
, dreg
, 0);
7104 if (imm_expr
.X_op
== O_constant
7105 && imm_expr
.X_add_number
>= 0
7106 && imm_expr
.X_add_number
< 0x10000)
7108 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
7109 sreg
, (int) BFD_RELOC_LO16
);
7112 else if (imm_expr
.X_op
== O_constant
7113 && imm_expr
.X_add_number
> -0x8000
7114 && imm_expr
.X_add_number
< 0)
7116 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7117 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7118 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7119 "t,r,j", dreg
, sreg
,
7120 (int) BFD_RELOC_LO16
);
7125 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7126 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7127 "d,v,t", dreg
, sreg
, AT
);
7130 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7131 (int) BFD_RELOC_LO16
);
7136 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7142 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7144 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7145 (int) BFD_RELOC_LO16
);
7148 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7150 if (imm_expr
.X_op
== O_constant
7151 && imm_expr
.X_add_number
>= -0x8000
7152 && imm_expr
.X_add_number
< 0x8000)
7154 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7155 mask
== M_SGE_I
? "slti" : "sltiu",
7156 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7161 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7162 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7163 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
7167 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7168 (int) BFD_RELOC_LO16
);
7173 case M_SGT
: /* sreg > treg <==> treg < sreg */
7179 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7183 case M_SGT_I
: /* sreg > I <==> I < sreg */
7189 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7190 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7194 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7202 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7203 (int) BFD_RELOC_LO16
);
7206 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7212 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7213 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7215 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7216 (int) BFD_RELOC_LO16
);
7220 if (imm_expr
.X_op
== O_constant
7221 && imm_expr
.X_add_number
>= -0x8000
7222 && imm_expr
.X_add_number
< 0x8000)
7224 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7225 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7228 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7229 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7234 if (imm_expr
.X_op
== O_constant
7235 && imm_expr
.X_add_number
>= -0x8000
7236 && imm_expr
.X_add_number
< 0x8000)
7238 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7239 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7242 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7243 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7244 "d,v,t", dreg
, sreg
, AT
);
7249 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7250 "d,v,t", dreg
, 0, treg
);
7252 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7253 "d,v,t", dreg
, 0, sreg
);
7256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7257 "d,v,t", dreg
, sreg
, treg
);
7258 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7259 "d,v,t", dreg
, 0, dreg
);
7264 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7266 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7267 "d,v,t", dreg
, 0, sreg
);
7272 as_warn (_("Instruction %s: result is always true"),
7274 macro_build ((char *) NULL
, &icnt
, &expr1
,
7275 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7276 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7279 if (imm_expr
.X_op
== O_constant
7280 && imm_expr
.X_add_number
>= 0
7281 && imm_expr
.X_add_number
< 0x10000)
7283 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7284 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7287 else if (imm_expr
.X_op
== O_constant
7288 && imm_expr
.X_add_number
> -0x8000
7289 && imm_expr
.X_add_number
< 0)
7291 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7292 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7293 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7294 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7299 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7300 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7301 "d,v,t", dreg
, sreg
, AT
);
7304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7305 "d,v,t", dreg
, 0, dreg
);
7313 if (imm_expr
.X_op
== O_constant
7314 && imm_expr
.X_add_number
> -0x8000
7315 && imm_expr
.X_add_number
<= 0x8000)
7317 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7318 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7319 dbl
? "daddi" : "addi",
7320 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7323 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7324 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7325 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7331 if (imm_expr
.X_op
== O_constant
7332 && imm_expr
.X_add_number
> -0x8000
7333 && imm_expr
.X_add_number
<= 0x8000)
7335 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7336 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7337 dbl
? "daddiu" : "addiu",
7338 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7341 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7342 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7343 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7364 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7365 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7371 assert (mips_opts
.isa
== ISA_MIPS1
);
7372 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7373 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7376 * Is the double cfc1 instruction a bug in the mips assembler;
7377 * or is there a reason for it?
7379 mips_emit_delays (true);
7380 ++mips_opts
.noreorder
;
7381 mips_any_noreorder
= 1;
7382 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7384 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7386 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7387 expr1
.X_add_number
= 3;
7388 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7389 (int) BFD_RELOC_LO16
);
7390 expr1
.X_add_number
= 2;
7391 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7392 (int) BFD_RELOC_LO16
);
7393 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7395 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7396 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7397 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7398 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7400 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7401 --mips_opts
.noreorder
;
7410 if (offset_expr
.X_add_number
>= 0x7fff)
7411 as_bad (_("operand overflow"));
7412 /* avoid load delay */
7413 if (! target_big_endian
)
7414 ++offset_expr
.X_add_number
;
7415 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7416 (int) BFD_RELOC_LO16
, breg
);
7417 if (! target_big_endian
)
7418 --offset_expr
.X_add_number
;
7420 ++offset_expr
.X_add_number
;
7421 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7422 (int) BFD_RELOC_LO16
, breg
);
7423 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7425 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7439 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7440 as_bad (_("operand overflow"));
7441 if (! target_big_endian
)
7442 offset_expr
.X_add_number
+= off
;
7443 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7444 (int) BFD_RELOC_LO16
, breg
);
7445 if (! target_big_endian
)
7446 offset_expr
.X_add_number
-= off
;
7448 offset_expr
.X_add_number
+= off
;
7449 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7450 (int) BFD_RELOC_LO16
, breg
);
7464 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7467 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7468 "d,v,t", AT
, AT
, breg
);
7469 if (! target_big_endian
)
7470 expr1
.X_add_number
= off
;
7472 expr1
.X_add_number
= 0;
7473 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7474 (int) BFD_RELOC_LO16
, AT
);
7475 if (! target_big_endian
)
7476 expr1
.X_add_number
= 0;
7478 expr1
.X_add_number
= off
;
7479 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7480 (int) BFD_RELOC_LO16
, AT
);
7486 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7489 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7490 "d,v,t", AT
, AT
, breg
);
7491 if (target_big_endian
)
7492 expr1
.X_add_number
= 0;
7493 macro_build ((char *) NULL
, &icnt
, &expr1
,
7494 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7495 (int) BFD_RELOC_LO16
, AT
);
7496 if (target_big_endian
)
7497 expr1
.X_add_number
= 1;
7499 expr1
.X_add_number
= 0;
7500 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7501 (int) BFD_RELOC_LO16
, AT
);
7502 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7504 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7509 if (offset_expr
.X_add_number
>= 0x7fff)
7510 as_bad (_("operand overflow"));
7511 if (target_big_endian
)
7512 ++offset_expr
.X_add_number
;
7513 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7514 (int) BFD_RELOC_LO16
, breg
);
7515 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7517 if (target_big_endian
)
7518 --offset_expr
.X_add_number
;
7520 ++offset_expr
.X_add_number
;
7521 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7522 (int) BFD_RELOC_LO16
, breg
);
7535 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7536 as_bad (_("operand overflow"));
7537 if (! target_big_endian
)
7538 offset_expr
.X_add_number
+= off
;
7539 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7540 (int) BFD_RELOC_LO16
, breg
);
7541 if (! target_big_endian
)
7542 offset_expr
.X_add_number
-= off
;
7544 offset_expr
.X_add_number
+= off
;
7545 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7546 (int) BFD_RELOC_LO16
, breg
);
7560 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7563 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7564 "d,v,t", AT
, AT
, breg
);
7565 if (! target_big_endian
)
7566 expr1
.X_add_number
= off
;
7568 expr1
.X_add_number
= 0;
7569 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7570 (int) BFD_RELOC_LO16
, AT
);
7571 if (! target_big_endian
)
7572 expr1
.X_add_number
= 0;
7574 expr1
.X_add_number
= off
;
7575 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7576 (int) BFD_RELOC_LO16
, AT
);
7581 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7583 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7584 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7585 "d,v,t", AT
, AT
, breg
);
7586 if (! target_big_endian
)
7587 expr1
.X_add_number
= 0;
7588 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7589 (int) BFD_RELOC_LO16
, AT
);
7590 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7592 if (! target_big_endian
)
7593 expr1
.X_add_number
= 1;
7595 expr1
.X_add_number
= 0;
7596 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7597 (int) BFD_RELOC_LO16
, AT
);
7598 if (! target_big_endian
)
7599 expr1
.X_add_number
= 0;
7601 expr1
.X_add_number
= 1;
7602 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7603 (int) BFD_RELOC_LO16
, AT
);
7604 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7606 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7611 /* FIXME: Check if this is one of the itbl macros, since they
7612 are added dynamically. */
7613 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7617 as_warn (_("Macro used $at after \".set noat\""));
7620 /* Implement macros in mips16 mode. */
7624 struct mips_cl_insn
*ip
;
7627 int xreg
, yreg
, zreg
, tmp
;
7631 const char *s
, *s2
, *s3
;
7633 mask
= ip
->insn_mo
->mask
;
7635 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7636 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7637 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7641 expr1
.X_op
= O_constant
;
7642 expr1
.X_op_symbol
= NULL
;
7643 expr1
.X_add_symbol
= NULL
;
7644 expr1
.X_add_number
= 1;
7663 mips_emit_delays (true);
7664 ++mips_opts
.noreorder
;
7665 mips_any_noreorder
= 1;
7666 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7667 dbl
? "ddiv" : "div",
7668 "0,x,y", xreg
, yreg
);
7669 expr1
.X_add_number
= 2;
7670 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7674 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7675 since that causes an overflow. We should do that as well,
7676 but I don't see how to do the comparisons without a temporary
7678 --mips_opts
.noreorder
;
7679 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7698 mips_emit_delays (true);
7699 ++mips_opts
.noreorder
;
7700 mips_any_noreorder
= 1;
7701 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7703 expr1
.X_add_number
= 2;
7704 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7705 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7707 --mips_opts
.noreorder
;
7708 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7714 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7715 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7716 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7725 if (imm_expr
.X_op
!= O_constant
)
7726 as_bad (_("Unsupported large constant"));
7727 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7728 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7729 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7733 if (imm_expr
.X_op
!= O_constant
)
7734 as_bad (_("Unsupported large constant"));
7735 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7736 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7741 if (imm_expr
.X_op
!= O_constant
)
7742 as_bad (_("Unsupported large constant"));
7743 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7744 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7767 goto do_reverse_branch
;
7771 goto do_reverse_branch
;
7783 goto do_reverse_branch
;
7794 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7796 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7823 goto do_addone_branch_i
;
7828 goto do_addone_branch_i
;
7843 goto do_addone_branch_i
;
7850 if (imm_expr
.X_op
!= O_constant
)
7851 as_bad (_("Unsupported large constant"));
7852 ++imm_expr
.X_add_number
;
7855 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7856 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7860 expr1
.X_add_number
= 0;
7861 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7863 move_register (&icnt
, xreg
, yreg
);
7864 expr1
.X_add_number
= 2;
7865 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7866 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7867 "neg", "x,w", xreg
, xreg
);
7871 /* For consistency checking, verify that all bits are specified either
7872 by the match/mask part of the instruction definition, or by the
7875 validate_mips_insn (opc
)
7876 const struct mips_opcode
*opc
;
7878 const char *p
= opc
->args
;
7880 unsigned long used_bits
= opc
->mask
;
7882 if ((used_bits
& opc
->match
) != opc
->match
)
7884 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7885 opc
->name
, opc
->args
);
7888 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7895 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7896 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7898 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7899 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7900 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7901 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7903 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7904 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7906 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7908 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7909 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7910 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7911 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7912 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7913 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7914 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7915 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7916 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7917 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7918 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7919 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7920 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7921 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7922 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7923 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7924 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7926 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7927 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7928 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7929 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7931 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7932 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7933 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7934 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7935 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7936 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7937 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7938 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7939 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7942 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7943 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7944 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7945 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7946 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7950 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7951 c
, opc
->name
, opc
->args
);
7955 if (used_bits
!= 0xffffffff)
7957 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7958 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7964 /* This routine assembles an instruction into its binary format. As a
7965 side effect, it sets one of the global variables imm_reloc or
7966 offset_reloc to the type of relocation to do if one of the operands
7967 is an address expression. */
7972 struct mips_cl_insn
*ip
;
7977 struct mips_opcode
*insn
;
7980 unsigned int lastregno
= 0;
7986 /* If the instruction contains a '.', we first try to match an instruction
7987 including the '.'. Then we try again without the '.'. */
7989 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7992 /* If we stopped on whitespace, then replace the whitespace with null for
7993 the call to hash_find. Save the character we replaced just in case we
7994 have to re-parse the instruction. */
8001 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8003 /* If we didn't find the instruction in the opcode table, try again, but
8004 this time with just the instruction up to, but not including the
8008 /* Restore the character we overwrite above (if any). */
8012 /* Scan up to the first '.' or whitespace. */
8014 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8018 /* If we did not find a '.', then we can quit now. */
8021 insn_error
= "unrecognized opcode";
8025 /* Lookup the instruction in the hash table. */
8027 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8029 insn_error
= "unrecognized opcode";
8039 assert (strcmp (insn
->name
, str
) == 0);
8041 if (OPCODE_IS_MEMBER (insn
,
8043 | (file_ase_mips16
? INSN_MIPS16
: 0)
8044 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8045 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8051 if (insn
->pinfo
!= INSN_MACRO
)
8053 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8059 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8060 && strcmp (insn
->name
, insn
[1].name
) == 0)
8069 static char buf
[100];
8070 if (mips_arch_info
->is_isa
)
8072 _("opcode not supported at this ISA level (%s)"),
8073 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8076 _("opcode not supported on this processor: %s (%s)"),
8077 mips_arch_info
->name
,
8078 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8088 ip
->insn_opcode
= insn
->match
;
8090 for (args
= insn
->args
;; ++args
)
8094 s
+= strspn (s
, " \t");
8098 case '\0': /* end of args */
8111 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8115 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8119 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8123 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8129 /* Handle optional base register.
8130 Either the base register is omitted or
8131 we must have a left paren. */
8132 /* This is dependent on the next operand specifier
8133 is a base register specification. */
8134 assert (args
[1] == 'b' || args
[1] == '5'
8135 || args
[1] == '-' || args
[1] == '4');
8139 case ')': /* these must match exactly */
8146 case '<': /* must be at least one digit */
8148 * According to the manual, if the shift amount is greater
8149 * than 31 or less than 0, then the shift amount should be
8150 * mod 32. In reality the mips assembler issues an error.
8151 * We issue a warning and mask out all but the low 5 bits.
8153 my_getExpression (&imm_expr
, s
);
8154 check_absolute_expr (ip
, &imm_expr
);
8155 if ((unsigned long) imm_expr
.X_add_number
> 31)
8157 as_warn (_("Improper shift amount (%lu)"),
8158 (unsigned long) imm_expr
.X_add_number
);
8159 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8161 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8162 imm_expr
.X_op
= O_absent
;
8166 case '>': /* shift amount minus 32 */
8167 my_getExpression (&imm_expr
, s
);
8168 check_absolute_expr (ip
, &imm_expr
);
8169 if ((unsigned long) imm_expr
.X_add_number
< 32
8170 || (unsigned long) imm_expr
.X_add_number
> 63)
8172 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8173 imm_expr
.X_op
= O_absent
;
8177 case 'k': /* cache code */
8178 case 'h': /* prefx code */
8179 my_getExpression (&imm_expr
, s
);
8180 check_absolute_expr (ip
, &imm_expr
);
8181 if ((unsigned long) imm_expr
.X_add_number
> 31)
8183 as_warn (_("Invalid value for `%s' (%lu)"),
8185 (unsigned long) imm_expr
.X_add_number
);
8186 imm_expr
.X_add_number
&= 0x1f;
8189 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8191 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8192 imm_expr
.X_op
= O_absent
;
8196 case 'c': /* break code */
8197 my_getExpression (&imm_expr
, s
);
8198 check_absolute_expr (ip
, &imm_expr
);
8199 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8201 as_warn (_("Illegal break code (%lu)"),
8202 (unsigned long) imm_expr
.X_add_number
);
8203 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8205 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8206 imm_expr
.X_op
= O_absent
;
8210 case 'q': /* lower break code */
8211 my_getExpression (&imm_expr
, s
);
8212 check_absolute_expr (ip
, &imm_expr
);
8213 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8215 as_warn (_("Illegal lower break code (%lu)"),
8216 (unsigned long) imm_expr
.X_add_number
);
8217 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8219 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8220 imm_expr
.X_op
= O_absent
;
8224 case 'B': /* 20-bit syscall/break code. */
8225 my_getExpression (&imm_expr
, s
);
8226 check_absolute_expr (ip
, &imm_expr
);
8227 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8228 as_warn (_("Illegal 20-bit code (%lu)"),
8229 (unsigned long) imm_expr
.X_add_number
);
8230 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8231 imm_expr
.X_op
= O_absent
;
8235 case 'C': /* Coprocessor code */
8236 my_getExpression (&imm_expr
, s
);
8237 check_absolute_expr (ip
, &imm_expr
);
8238 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8240 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8241 (unsigned long) imm_expr
.X_add_number
);
8242 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8244 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8245 imm_expr
.X_op
= O_absent
;
8249 case 'J': /* 19-bit wait code. */
8250 my_getExpression (&imm_expr
, s
);
8251 check_absolute_expr (ip
, &imm_expr
);
8252 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8253 as_warn (_("Illegal 19-bit code (%lu)"),
8254 (unsigned long) imm_expr
.X_add_number
);
8255 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8256 imm_expr
.X_op
= O_absent
;
8260 case 'P': /* Performance register */
8261 my_getExpression (&imm_expr
, s
);
8262 check_absolute_expr (ip
, &imm_expr
);
8263 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8265 as_warn (_("Invalid performance register (%lu)"),
8266 (unsigned long) imm_expr
.X_add_number
);
8267 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8269 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8270 imm_expr
.X_op
= O_absent
;
8274 case 'b': /* base register */
8275 case 'd': /* destination register */
8276 case 's': /* source register */
8277 case 't': /* target register */
8278 case 'r': /* both target and source */
8279 case 'v': /* both dest and source */
8280 case 'w': /* both dest and target */
8281 case 'E': /* coprocessor target register */
8282 case 'G': /* coprocessor destination register */
8283 case 'x': /* ignore register name */
8284 case 'z': /* must be zero register */
8285 case 'U': /* destination register (clo/clz). */
8300 while (ISDIGIT (*s
));
8302 as_bad (_("Invalid register number (%d)"), regno
);
8304 else if (*args
== 'E' || *args
== 'G')
8308 if (s
[1] == 'r' && s
[2] == 'a')
8313 else if (s
[1] == 'f' && s
[2] == 'p')
8318 else if (s
[1] == 's' && s
[2] == 'p')
8323 else if (s
[1] == 'g' && s
[2] == 'p')
8328 else if (s
[1] == 'a' && s
[2] == 't')
8333 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8338 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8343 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8348 else if (itbl_have_entries
)
8353 p
= s
+ 1; /* advance past '$' */
8354 n
= itbl_get_field (&p
); /* n is name */
8356 /* See if this is a register defined in an
8358 if (itbl_get_reg_val (n
, &r
))
8360 /* Get_field advances to the start of
8361 the next field, so we need to back
8362 rack to the end of the last field. */
8366 s
= strchr (s
, '\0');
8379 as_warn (_("Used $at without \".set noat\""));
8385 if (c
== 'r' || c
== 'v' || c
== 'w')
8392 /* 'z' only matches $0. */
8393 if (c
== 'z' && regno
!= 0)
8396 /* Now that we have assembled one operand, we use the args string
8397 * to figure out where it goes in the instruction. */
8404 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8408 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8411 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8412 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8417 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8420 /* This case exists because on the r3000 trunc
8421 expands into a macro which requires a gp
8422 register. On the r6000 or r4000 it is
8423 assembled into a single instruction which
8424 ignores the register. Thus the insn version
8425 is MIPS_ISA2 and uses 'x', and the macro
8426 version is MIPS_ISA1 and uses 't'. */
8429 /* This case is for the div instruction, which
8430 acts differently if the destination argument
8431 is $0. This only matches $0, and is checked
8432 outside the switch. */
8435 /* Itbl operand; not yet implemented. FIXME ?? */
8437 /* What about all other operands like 'i', which
8438 can be specified in the opcode table? */
8448 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8451 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8456 case 'O': /* MDMX alignment immediate constant. */
8457 my_getExpression (&imm_expr
, s
);
8458 check_absolute_expr (ip
, &imm_expr
);
8459 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8461 as_warn ("Improper align amount (%ld), using low bits",
8462 (long) imm_expr
.X_add_number
);
8463 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8465 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8466 imm_expr
.X_op
= O_absent
;
8470 case 'Q': /* MDMX vector, element sel, or const. */
8473 /* MDMX Immediate. */
8474 my_getExpression (&imm_expr
, s
);
8475 check_absolute_expr (ip
, &imm_expr
);
8476 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8478 as_warn (_("Invalid MDMX Immediate (%ld)"),
8479 (long) imm_expr
.X_add_number
);
8480 imm_expr
.X_add_number
&= OP_MASK_FT
;
8482 imm_expr
.X_add_number
&= OP_MASK_FT
;
8483 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8484 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8486 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8487 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8488 imm_expr
.X_op
= O_absent
;
8492 /* Not MDMX Immediate. Fall through. */
8493 case 'X': /* MDMX destination register. */
8494 case 'Y': /* MDMX source register. */
8495 case 'Z': /* MDMX target register. */
8497 case 'D': /* floating point destination register */
8498 case 'S': /* floating point source register */
8499 case 'T': /* floating point target register */
8500 case 'R': /* floating point source register */
8504 /* Accept $fN for FP and MDMX register numbers, and in
8505 addition accept $vN for MDMX register numbers. */
8506 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8507 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8518 while (ISDIGIT (*s
));
8521 as_bad (_("Invalid float register number (%d)"), regno
);
8523 if ((regno
& 1) != 0
8525 && ! (strcmp (str
, "mtc1") == 0
8526 || strcmp (str
, "mfc1") == 0
8527 || strcmp (str
, "lwc1") == 0
8528 || strcmp (str
, "swc1") == 0
8529 || strcmp (str
, "l.s") == 0
8530 || strcmp (str
, "s.s") == 0))
8531 as_warn (_("Float register should be even, was %d"),
8539 if (c
== 'V' || c
== 'W')
8550 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8555 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8558 /* This is like 'Z', but also needs to fix the MDMX
8559 vector/scalar select bits. Note that the
8560 scalar immediate case is handled above. */
8563 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8564 int max_el
= (is_qh
? 3 : 7);
8566 my_getExpression(&imm_expr
, s
);
8567 check_absolute_expr (ip
, &imm_expr
);
8569 if (imm_expr
.X_add_number
> max_el
)
8570 as_bad(_("Bad element selector %ld"),
8571 (long) imm_expr
.X_add_number
);
8572 imm_expr
.X_add_number
&= max_el
;
8573 ip
->insn_opcode
|= (imm_expr
.X_add_number
8577 as_warn(_("Expecting ']' found '%s'"), s
);
8583 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8584 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8587 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8594 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8597 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8607 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8610 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8616 my_getExpression (&imm_expr
, s
);
8617 if (imm_expr
.X_op
!= O_big
8618 && imm_expr
.X_op
!= O_constant
)
8619 insn_error
= _("absolute expression required");
8624 my_getExpression (&offset_expr
, s
);
8625 *imm_reloc
= BFD_RELOC_32
;
8638 unsigned char temp
[8];
8640 unsigned int length
;
8645 /* These only appear as the last operand in an
8646 instruction, and every instruction that accepts
8647 them in any variant accepts them in all variants.
8648 This means we don't have to worry about backing out
8649 any changes if the instruction does not match.
8651 The difference between them is the size of the
8652 floating point constant and where it goes. For 'F'
8653 and 'L' the constant is 64 bits; for 'f' and 'l' it
8654 is 32 bits. Where the constant is placed is based
8655 on how the MIPS assembler does things:
8658 f -- immediate value
8661 The .lit4 and .lit8 sections are only used if
8662 permitted by the -G argument.
8664 When generating embedded PIC code, we use the
8665 .lit8 section but not the .lit4 section (we can do
8666 .lit4 inline easily; we need to put .lit8
8667 somewhere in the data segment, and using .lit8
8668 permits the linker to eventually combine identical
8671 The code below needs to know whether the target register
8672 is 32 or 64 bits wide. It relies on the fact 'f' and
8673 'F' are used with GPR-based instructions and 'l' and
8674 'L' are used with FPR-based instructions. */
8676 f64
= *args
== 'F' || *args
== 'L';
8677 using_gprs
= *args
== 'F' || *args
== 'f';
8679 save_in
= input_line_pointer
;
8680 input_line_pointer
= s
;
8681 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8683 s
= input_line_pointer
;
8684 input_line_pointer
= save_in
;
8685 if (err
!= NULL
&& *err
!= '\0')
8687 as_bad (_("Bad floating point constant: %s"), err
);
8688 memset (temp
, '\0', sizeof temp
);
8689 length
= f64
? 8 : 4;
8692 assert (length
== (unsigned) (f64
? 8 : 4));
8696 && (! USE_GLOBAL_POINTER_OPT
8697 || mips_pic
== EMBEDDED_PIC
8698 || g_switch_value
< 4
8699 || (temp
[0] == 0 && temp
[1] == 0)
8700 || (temp
[2] == 0 && temp
[3] == 0))))
8702 imm_expr
.X_op
= O_constant
;
8703 if (! target_big_endian
)
8704 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8706 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8709 && ! mips_disable_float_construction
8710 /* Constants can only be constructed in GPRs and
8711 copied to FPRs if the GPRs are at least as wide
8712 as the FPRs. Force the constant into memory if
8713 we are using 64-bit FPRs but the GPRs are only
8716 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8717 && ((temp
[0] == 0 && temp
[1] == 0)
8718 || (temp
[2] == 0 && temp
[3] == 0))
8719 && ((temp
[4] == 0 && temp
[5] == 0)
8720 || (temp
[6] == 0 && temp
[7] == 0)))
8722 /* The value is simple enough to load with a couple of
8723 instructions. If using 32-bit registers, set
8724 imm_expr to the high order 32 bits and offset_expr to
8725 the low order 32 bits. Otherwise, set imm_expr to
8726 the entire 64 bit constant. */
8727 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8729 imm_expr
.X_op
= O_constant
;
8730 offset_expr
.X_op
= O_constant
;
8731 if (! target_big_endian
)
8733 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8734 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8738 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8739 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8741 if (offset_expr
.X_add_number
== 0)
8742 offset_expr
.X_op
= O_absent
;
8744 else if (sizeof (imm_expr
.X_add_number
) > 4)
8746 imm_expr
.X_op
= O_constant
;
8747 if (! target_big_endian
)
8748 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8750 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8754 imm_expr
.X_op
= O_big
;
8755 imm_expr
.X_add_number
= 4;
8756 if (! target_big_endian
)
8758 generic_bignum
[0] = bfd_getl16 (temp
);
8759 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8760 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8761 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8765 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8766 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8767 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8768 generic_bignum
[3] = bfd_getb16 (temp
);
8774 const char *newname
;
8777 /* Switch to the right section. */
8779 subseg
= now_subseg
;
8782 default: /* unused default case avoids warnings. */
8784 newname
= RDATA_SECTION_NAME
;
8785 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8786 || mips_pic
== EMBEDDED_PIC
)
8790 if (mips_pic
== EMBEDDED_PIC
)
8793 newname
= RDATA_SECTION_NAME
;
8796 assert (!USE_GLOBAL_POINTER_OPT
8797 || g_switch_value
>= 4);
8801 new_seg
= subseg_new (newname
, (subsegT
) 0);
8802 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8803 bfd_set_section_flags (stdoutput
, new_seg
,
8808 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8809 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8810 && strcmp (TARGET_OS
, "elf") != 0)
8811 record_alignment (new_seg
, 4);
8813 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8815 as_bad (_("Can't use floating point insn in this section"));
8817 /* Set the argument to the current address in the
8819 offset_expr
.X_op
= O_symbol
;
8820 offset_expr
.X_add_symbol
=
8821 symbol_new ("L0\001", now_seg
,
8822 (valueT
) frag_now_fix (), frag_now
);
8823 offset_expr
.X_add_number
= 0;
8825 /* Put the floating point number into the section. */
8826 p
= frag_more ((int) length
);
8827 memcpy (p
, temp
, length
);
8829 /* Switch back to the original section. */
8830 subseg_set (seg
, subseg
);
8835 case 'i': /* 16 bit unsigned immediate */
8836 case 'j': /* 16 bit signed immediate */
8837 *imm_reloc
= BFD_RELOC_LO16
;
8838 c
= my_getSmallExpression (&imm_expr
, s
);
8845 *imm_reloc
= BFD_RELOC_HI16_S
;
8846 imm_unmatched_hi
= true;
8849 else if (c
== S_EX_HIGHEST
)
8850 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8851 else if (c
== S_EX_HIGHER
)
8852 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8853 else if (c
== S_EX_GP_REL
)
8855 /* This occurs in NewABI only. */
8856 c
= my_getSmallExpression (&imm_expr
, s
);
8858 as_bad (_("bad composition of relocations"));
8861 c
= my_getSmallExpression (&imm_expr
, s
);
8863 as_bad (_("bad composition of relocations"));
8866 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8867 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8868 imm_reloc
[2] = BFD_RELOC_LO16
;
8874 *imm_reloc
= BFD_RELOC_HI16
;
8876 else if (imm_expr
.X_op
== O_constant
)
8877 imm_expr
.X_add_number
&= 0xffff;
8881 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8882 || ((imm_expr
.X_add_number
< 0
8883 || imm_expr
.X_add_number
>= 0x10000)
8884 && imm_expr
.X_op
== O_constant
))
8886 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8887 !strcmp (insn
->name
, insn
[1].name
))
8889 if (imm_expr
.X_op
== O_constant
8890 || imm_expr
.X_op
== O_big
)
8891 as_bad (_("16 bit expression not in range 0..65535"));
8899 /* The upper bound should be 0x8000, but
8900 unfortunately the MIPS assembler accepts numbers
8901 from 0x8000 to 0xffff and sign extends them, and
8902 we want to be compatible. We only permit this
8903 extended range for an instruction which does not
8904 provide any further alternates, since those
8905 alternates may handle other cases. People should
8906 use the numbers they mean, rather than relying on
8907 a mysterious sign extension. */
8908 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8909 strcmp (insn
->name
, insn
[1].name
) == 0);
8914 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8915 || ((imm_expr
.X_add_number
< -0x8000
8916 || imm_expr
.X_add_number
>= max
)
8917 && imm_expr
.X_op
== O_constant
)
8919 && imm_expr
.X_add_number
< 0
8921 && imm_expr
.X_unsigned
8922 && sizeof (imm_expr
.X_add_number
) <= 4))
8926 if (imm_expr
.X_op
== O_constant
8927 || imm_expr
.X_op
== O_big
)
8928 as_bad (_("16 bit expression not in range -32768..32767"));
8934 case 'o': /* 16 bit offset */
8935 c
= my_getSmallExpression (&offset_expr
, s
);
8937 /* If this value won't fit into a 16 bit offset, then go
8938 find a macro that will generate the 32 bit offset
8941 && (offset_expr
.X_op
!= O_constant
8942 || offset_expr
.X_add_number
>= 0x8000
8943 || offset_expr
.X_add_number
< -0x8000))
8948 if (offset_expr
.X_op
!= O_constant
)
8950 offset_expr
.X_add_number
=
8951 (offset_expr
.X_add_number
>> 16) & 0xffff;
8953 *offset_reloc
= BFD_RELOC_LO16
;
8957 case 'p': /* pc relative offset */
8958 if (mips_pic
== EMBEDDED_PIC
)
8959 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8961 *offset_reloc
= BFD_RELOC_16_PCREL
;
8962 my_getExpression (&offset_expr
, s
);
8966 case 'u': /* upper 16 bits */
8967 c
= my_getSmallExpression (&imm_expr
, s
);
8968 *imm_reloc
= BFD_RELOC_LO16
;
8975 *imm_reloc
= BFD_RELOC_HI16_S
;
8976 imm_unmatched_hi
= true;
8979 else if (c
== S_EX_HIGHEST
)
8980 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8981 else if (c
== S_EX_GP_REL
)
8983 /* This occurs in NewABI only. */
8984 c
= my_getSmallExpression (&imm_expr
, s
);
8986 as_bad (_("bad composition of relocations"));
8989 c
= my_getSmallExpression (&imm_expr
, s
);
8991 as_bad (_("bad composition of relocations"));
8994 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8995 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8996 imm_reloc
[2] = BFD_RELOC_HI16_S
;
9002 *imm_reloc
= BFD_RELOC_HI16
;
9004 else if (imm_expr
.X_op
== O_constant
)
9005 imm_expr
.X_add_number
&= 0xffff;
9007 else if (imm_expr
.X_op
== O_constant
9008 && (imm_expr
.X_add_number
< 0
9009 || imm_expr
.X_add_number
>= 0x10000))
9010 as_bad (_("lui expression not in range 0..65535"));
9014 case 'a': /* 26 bit address */
9015 my_getExpression (&offset_expr
, s
);
9017 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9020 case 'N': /* 3 bit branch condition code */
9021 case 'M': /* 3 bit compare condition code */
9022 if (strncmp (s
, "$fcc", 4) != 0)
9032 while (ISDIGIT (*s
));
9034 as_bad (_("invalid condition code register $fcc%d"), regno
);
9036 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9038 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9042 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9053 while (ISDIGIT (*s
));
9056 c
= 8; /* Invalid sel value. */
9059 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9060 ip
->insn_opcode
|= c
;
9064 /* Must be at least one digit. */
9065 my_getExpression (&imm_expr
, s
);
9066 check_absolute_expr (ip
, &imm_expr
);
9068 if ((unsigned long) imm_expr
.X_add_number
9069 > (unsigned long) OP_MASK_VECBYTE
)
9071 as_bad (_("bad byte vector index (%ld)"),
9072 (long) imm_expr
.X_add_number
);
9073 imm_expr
.X_add_number
= 0;
9076 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9077 imm_expr
.X_op
= O_absent
;
9082 my_getExpression (&imm_expr
, s
);
9083 check_absolute_expr (ip
, &imm_expr
);
9085 if ((unsigned long) imm_expr
.X_add_number
9086 > (unsigned long) OP_MASK_VECALIGN
)
9088 as_bad (_("bad byte vector index (%ld)"),
9089 (long) imm_expr
.X_add_number
);
9090 imm_expr
.X_add_number
= 0;
9093 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9094 imm_expr
.X_op
= O_absent
;
9099 as_bad (_("bad char = '%c'\n"), *args
);
9104 /* Args don't match. */
9105 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9106 !strcmp (insn
->name
, insn
[1].name
))
9110 insn_error
= _("illegal operands");
9115 insn_error
= _("illegal operands");
9120 /* This routine assembles an instruction into its binary format when
9121 assembling for the mips16. As a side effect, it sets one of the
9122 global variables imm_reloc or offset_reloc to the type of
9123 relocation to do if one of the operands is an address expression.
9124 It also sets mips16_small and mips16_ext if the user explicitly
9125 requested a small or extended instruction. */
9130 struct mips_cl_insn
*ip
;
9134 struct mips_opcode
*insn
;
9137 unsigned int lastregno
= 0;
9142 mips16_small
= false;
9145 for (s
= str
; ISLOWER (*s
); ++s
)
9157 if (s
[1] == 't' && s
[2] == ' ')
9160 mips16_small
= true;
9164 else if (s
[1] == 'e' && s
[2] == ' ')
9173 insn_error
= _("unknown opcode");
9177 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9178 mips16_small
= true;
9180 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9182 insn_error
= _("unrecognized opcode");
9189 assert (strcmp (insn
->name
, str
) == 0);
9192 ip
->insn_opcode
= insn
->match
;
9193 ip
->use_extend
= false;
9194 imm_expr
.X_op
= O_absent
;
9195 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9196 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9197 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9198 offset_expr
.X_op
= O_absent
;
9199 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9200 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9201 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9202 for (args
= insn
->args
; 1; ++args
)
9209 /* In this switch statement we call break if we did not find
9210 a match, continue if we did find a match, or return if we
9219 /* Stuff the immediate value in now, if we can. */
9220 if (imm_expr
.X_op
== O_constant
9221 && *imm_reloc
> BFD_RELOC_UNUSED
9222 && insn
->pinfo
!= INSN_MACRO
)
9224 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9225 imm_expr
.X_add_number
, true, mips16_small
,
9226 mips16_ext
, &ip
->insn_opcode
,
9227 &ip
->use_extend
, &ip
->extend
);
9228 imm_expr
.X_op
= O_absent
;
9229 *imm_reloc
= BFD_RELOC_UNUSED
;
9243 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9246 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9262 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9264 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9291 while (ISDIGIT (*s
));
9294 as_bad (_("invalid register number (%d)"), regno
);
9300 if (s
[1] == 'r' && s
[2] == 'a')
9305 else if (s
[1] == 'f' && s
[2] == 'p')
9310 else if (s
[1] == 's' && s
[2] == 'p')
9315 else if (s
[1] == 'g' && s
[2] == 'p')
9320 else if (s
[1] == 'a' && s
[2] == 't')
9325 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9330 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9335 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9348 if (c
== 'v' || c
== 'w')
9350 regno
= mips16_to_32_reg_map
[lastregno
];
9364 regno
= mips32_to_16_reg_map
[regno
];
9369 regno
= ILLEGAL_REG
;
9374 regno
= ILLEGAL_REG
;
9379 regno
= ILLEGAL_REG
;
9384 if (regno
== AT
&& ! mips_opts
.noat
)
9385 as_warn (_("used $at without \".set noat\""));
9392 if (regno
== ILLEGAL_REG
)
9399 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9403 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9406 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9409 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9415 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9418 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9419 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9429 if (strncmp (s
, "$pc", 3) == 0)
9453 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9455 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9456 and generate the appropriate reloc. If the text
9457 inside %gprel is not a symbol name with an
9458 optional offset, then we generate a normal reloc
9459 and will probably fail later. */
9460 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9461 if (imm_expr
.X_op
== O_symbol
)
9464 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9466 ip
->use_extend
= true;
9473 /* Just pick up a normal expression. */
9474 my_getExpression (&imm_expr
, s
);
9477 if (imm_expr
.X_op
== O_register
)
9479 /* What we thought was an expression turned out to
9482 if (s
[0] == '(' && args
[1] == '(')
9484 /* It looks like the expression was omitted
9485 before a register indirection, which means
9486 that the expression is implicitly zero. We
9487 still set up imm_expr, so that we handle
9488 explicit extensions correctly. */
9489 imm_expr
.X_op
= O_constant
;
9490 imm_expr
.X_add_number
= 0;
9491 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9498 /* We need to relax this instruction. */
9499 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9508 /* We use offset_reloc rather than imm_reloc for the PC
9509 relative operands. This lets macros with both
9510 immediate and address operands work correctly. */
9511 my_getExpression (&offset_expr
, s
);
9513 if (offset_expr
.X_op
== O_register
)
9516 /* We need to relax this instruction. */
9517 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9521 case '6': /* break code */
9522 my_getExpression (&imm_expr
, s
);
9523 check_absolute_expr (ip
, &imm_expr
);
9524 if ((unsigned long) imm_expr
.X_add_number
> 63)
9526 as_warn (_("Invalid value for `%s' (%lu)"),
9528 (unsigned long) imm_expr
.X_add_number
);
9529 imm_expr
.X_add_number
&= 0x3f;
9531 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9532 imm_expr
.X_op
= O_absent
;
9536 case 'a': /* 26 bit address */
9537 my_getExpression (&offset_expr
, s
);
9539 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9540 ip
->insn_opcode
<<= 16;
9543 case 'l': /* register list for entry macro */
9544 case 'L': /* register list for exit macro */
9554 int freg
, reg1
, reg2
;
9556 while (*s
== ' ' || *s
== ',')
9560 as_bad (_("can't parse register list"));
9572 while (ISDIGIT (*s
))
9594 as_bad (_("invalid register list"));
9599 while (ISDIGIT (*s
))
9606 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9611 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9616 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9617 mask
|= (reg2
- 3) << 3;
9618 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9619 mask
|= (reg2
- 15) << 1;
9620 else if (reg1
== RA
&& reg2
== RA
)
9624 as_bad (_("invalid register list"));
9628 /* The mask is filled in in the opcode table for the
9629 benefit of the disassembler. We remove it before
9630 applying the actual mask. */
9631 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9632 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9636 case 'e': /* extend code */
9637 my_getExpression (&imm_expr
, s
);
9638 check_absolute_expr (ip
, &imm_expr
);
9639 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9641 as_warn (_("Invalid value for `%s' (%lu)"),
9643 (unsigned long) imm_expr
.X_add_number
);
9644 imm_expr
.X_add_number
&= 0x7ff;
9646 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9647 imm_expr
.X_op
= O_absent
;
9657 /* Args don't match. */
9658 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9659 strcmp (insn
->name
, insn
[1].name
) == 0)
9666 insn_error
= _("illegal operands");
9672 /* This structure holds information we know about a mips16 immediate
9675 struct mips16_immed_operand
9677 /* The type code used in the argument string in the opcode table. */
9679 /* The number of bits in the short form of the opcode. */
9681 /* The number of bits in the extended form of the opcode. */
9683 /* The amount by which the short form is shifted when it is used;
9684 for example, the sw instruction has a shift count of 2. */
9686 /* The amount by which the short form is shifted when it is stored
9687 into the instruction code. */
9689 /* Non-zero if the short form is unsigned. */
9691 /* Non-zero if the extended form is unsigned. */
9693 /* Non-zero if the value is PC relative. */
9697 /* The mips16 immediate operand types. */
9699 static const struct mips16_immed_operand mips16_immed_operands
[] =
9701 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9702 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9703 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9704 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9705 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9706 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9707 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9708 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9709 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9710 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9711 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9712 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9713 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9714 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9715 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9716 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9717 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9718 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9719 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9720 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9721 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9724 #define MIPS16_NUM_IMMED \
9725 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9727 /* Handle a mips16 instruction with an immediate value. This or's the
9728 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9729 whether an extended value is needed; if one is needed, it sets
9730 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9731 If SMALL is true, an unextended opcode was explicitly requested.
9732 If EXT is true, an extended opcode was explicitly requested. If
9733 WARN is true, warn if EXT does not match reality. */
9736 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9745 unsigned long *insn
;
9746 boolean
*use_extend
;
9747 unsigned short *extend
;
9749 register const struct mips16_immed_operand
*op
;
9750 int mintiny
, maxtiny
;
9753 op
= mips16_immed_operands
;
9754 while (op
->type
!= type
)
9757 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9762 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9765 maxtiny
= 1 << op
->nbits
;
9770 maxtiny
= (1 << op
->nbits
) - 1;
9775 mintiny
= - (1 << (op
->nbits
- 1));
9776 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9779 /* Branch offsets have an implicit 0 in the lowest bit. */
9780 if (type
== 'p' || type
== 'q')
9783 if ((val
& ((1 << op
->shift
) - 1)) != 0
9784 || val
< (mintiny
<< op
->shift
)
9785 || val
> (maxtiny
<< op
->shift
))
9790 if (warn
&& ext
&& ! needext
)
9791 as_warn_where (file
, line
,
9792 _("extended operand requested but not required"));
9793 if (small
&& needext
)
9794 as_bad_where (file
, line
, _("invalid unextended operand value"));
9796 if (small
|| (! ext
&& ! needext
))
9800 *use_extend
= false;
9801 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9802 insnval
<<= op
->op_shift
;
9807 long minext
, maxext
;
9813 maxext
= (1 << op
->extbits
) - 1;
9817 minext
= - (1 << (op
->extbits
- 1));
9818 maxext
= (1 << (op
->extbits
- 1)) - 1;
9820 if (val
< minext
|| val
> maxext
)
9821 as_bad_where (file
, line
,
9822 _("operand value out of range for instruction"));
9825 if (op
->extbits
== 16)
9827 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9830 else if (op
->extbits
== 15)
9832 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9837 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9841 *extend
= (unsigned short) extval
;
9846 static struct percent_op_match
9849 const enum small_ex_type type
;
9854 {"%call_hi", S_EX_CALL_HI
},
9855 {"%call_lo", S_EX_CALL_LO
},
9856 {"%call16", S_EX_CALL16
},
9857 {"%got_disp", S_EX_GOT_DISP
},
9858 {"%got_page", S_EX_GOT_PAGE
},
9859 {"%got_ofst", S_EX_GOT_OFST
},
9860 {"%got_hi", S_EX_GOT_HI
},
9861 {"%got_lo", S_EX_GOT_LO
},
9863 {"%gp_rel", S_EX_GP_REL
},
9864 {"%half", S_EX_HALF
},
9865 {"%highest", S_EX_HIGHEST
},
9866 {"%higher", S_EX_HIGHER
},
9872 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9873 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9874 can be nested, this is handled by blanking the innermost, parsing the
9875 rest by subsequent calls. */
9878 my_getSmallParser (str
, len
, nestlevel
)
9884 *str
+= strspn (*str
, " \t");
9885 /* Check for expression in parentheses. */
9888 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9891 /* Check for base register. */
9895 && (e
= b
+ strcspn (b
, ") \t"))
9896 && e
- b
> 1 && e
- b
< 4)
9899 && ((b
[1] == 'f' && b
[2] == 'p')
9900 || (b
[1] == 's' && b
[2] == 'p')
9901 || (b
[1] == 'g' && b
[2] == 'p')
9902 || (b
[1] == 'a' && b
[2] == 't')
9904 && ISDIGIT (b
[2]))))
9905 || (ISDIGIT (b
[1])))
9907 *len
= strcspn (*str
, ")") + 1;
9908 return S_EX_REGISTER
;
9912 /* Check for percent_op (in parentheses). */
9913 else if (b
[0] == '%')
9916 return my_getPercentOp (str
, len
, nestlevel
);
9919 /* Some other expression in the parentheses, which can contain
9920 parentheses itself. Attempt to find the matching one. */
9926 for (s
= *str
+ 1; *s
&& pcnt
; s
++, (*len
)++)
9935 /* Check for percent_op (outside of parentheses). */
9936 else if (*str
[0] == '%')
9937 return my_getPercentOp (str
, len
, nestlevel
);
9939 /* Any other expression. */
9944 my_getPercentOp (str
, len
, nestlevel
)
9949 char *tmp
= *str
+ 1;
9952 while (ISALPHA (*tmp
) || *tmp
== '_')
9954 *tmp
= TOLOWER (*tmp
);
9957 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9959 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9963 int type
= percent_op
[i
].type
;
9965 /* Only %hi and %lo are allowed for OldABI. */
9966 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9969 *len
= strlen (percent_op
[i
].str
);
9978 my_getSmallExpression (ep
, str
)
9982 static char *oldstr
= NULL
;
9988 /* Don't update oldstr if the last call had nested percent_op's. We need
9989 it to parse the outer ones later. */
9996 c
= my_getSmallParser (&str
, &len
, &nestlevel
);
9997 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
10000 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
10002 if (nestlevel
>= 0)
10004 /* A percent_op was encountered. Don't try to get an expression if
10005 it is already blanked out. */
10006 if (*(str
+ strspn (str
+ 1, " )")) != ')')
10010 /* Let my_getExpression() stop at the closing parenthesis. */
10011 save
= *(str
+ len
);
10012 *(str
+ len
) = '\0';
10013 my_getExpression (ep
, str
);
10014 *(str
+ len
) = save
;
10018 /* Blank out including the % sign and the proper matching
10021 char *s
= strrchr (oldstr
, '%');
10024 for (end
= strchr (s
, '(') + 1; *end
&& pcnt
; end
++)
10028 else if (*end
== ')')
10032 memset (s
, ' ', end
- s
);
10036 expr_end
= str
+ len
;
10040 else if (c
== S_EX_NONE
)
10042 my_getExpression (ep
, str
);
10044 else if (c
== S_EX_REGISTER
)
10046 ep
->X_op
= O_constant
;
10048 ep
->X_add_symbol
= NULL
;
10049 ep
->X_op_symbol
= NULL
;
10050 ep
->X_add_number
= 0;
10054 as_fatal (_("internal error"));
10057 if (nestlevel
<= 0)
10058 /* All percent_op's have been handled. */
10065 my_getExpression (ep
, str
)
10072 save_in
= input_line_pointer
;
10073 input_line_pointer
= str
;
10075 expr_end
= input_line_pointer
;
10076 input_line_pointer
= save_in
;
10078 /* If we are in mips16 mode, and this is an expression based on `.',
10079 then we bump the value of the symbol by 1 since that is how other
10080 text symbols are handled. We don't bother to handle complex
10081 expressions, just `.' plus or minus a constant. */
10082 if (mips_opts
.mips16
10083 && ep
->X_op
== O_symbol
10084 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10085 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10086 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10087 && symbol_constant_p (ep
->X_add_symbol
)
10088 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10089 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10092 /* Turn a string in input_line_pointer into a floating point constant
10093 of type TYPE, and store the appropriate bytes in *LITP. The number
10094 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10095 returned, or NULL on OK. */
10098 md_atof (type
, litP
, sizeP
)
10104 LITTLENUM_TYPE words
[4];
10120 return _("bad call to md_atof");
10123 t
= atof_ieee (input_line_pointer
, type
, words
);
10125 input_line_pointer
= t
;
10129 if (! target_big_endian
)
10131 for (i
= prec
- 1; i
>= 0; i
--)
10133 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10139 for (i
= 0; i
< prec
; i
++)
10141 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10150 md_number_to_chars (buf
, val
, n
)
10155 if (target_big_endian
)
10156 number_to_chars_bigendian (buf
, val
, n
);
10158 number_to_chars_littleendian (buf
, val
, n
);
10162 static int support_64bit_objects(void)
10164 const char **list
, **l
;
10167 list
= bfd_target_list ();
10168 for (l
= list
; *l
!= NULL
; l
++)
10170 /* This is traditional mips */
10171 if (strcmp (*l
, "elf64-tradbigmips") == 0
10172 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10174 if (strcmp (*l
, "elf64-bigmips") == 0
10175 || strcmp (*l
, "elf64-littlemips") == 0)
10178 yes
= (*l
!= NULL
);
10182 #endif /* OBJ_ELF */
10184 const char *md_shortopts
= "nO::g::G:";
10186 struct option md_longopts
[] =
10188 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10189 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10190 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10191 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10192 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10193 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10194 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10195 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10196 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10197 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10198 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10199 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10200 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10201 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10202 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10203 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10204 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10205 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10206 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10207 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10208 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10209 {"break", no_argument
, NULL
, OPTION_BREAK
},
10210 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10211 #define OPTION_EB (OPTION_MD_BASE + 11)
10212 {"EB", no_argument
, NULL
, OPTION_EB
},
10213 #define OPTION_EL (OPTION_MD_BASE + 12)
10214 {"EL", no_argument
, NULL
, OPTION_EL
},
10215 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10216 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10217 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10218 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10219 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10220 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10221 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10222 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10223 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10224 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10225 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10226 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10227 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10228 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10229 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10230 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10231 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10232 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10233 {"march", required_argument
, NULL
, OPTION_MARCH
},
10234 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10235 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10236 #define OPTION_FP64 (OPTION_MD_BASE + 23)
10237 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10238 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10239 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10240 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10241 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10242 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10243 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10244 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10245 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10246 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10247 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10248 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10249 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10250 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10251 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10252 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10253 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10254 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10255 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10256 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10257 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10258 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10259 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10260 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10261 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10262 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10263 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10264 #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
10265 #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
10266 {"mfix-vr4122-bugs", no_argument
, NULL
, OPTION_FIX_VR4122
},
10267 {"no-mfix-vr4122-bugs", no_argument
, NULL
, OPTION_NO_FIX_VR4122
},
10268 #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39)
10269 #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
10270 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10271 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10273 #define OPTION_ELF_BASE (OPTION_MD_BASE + 41)
10274 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10275 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10276 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10277 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10278 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10279 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10280 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10281 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10282 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10283 #define OPTION_32 (OPTION_ELF_BASE + 4)
10284 {"32", no_argument
, NULL
, OPTION_32
},
10285 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10286 {"n32", no_argument
, NULL
, OPTION_N32
},
10287 #define OPTION_64 (OPTION_ELF_BASE + 6)
10288 {"64", no_argument
, NULL
, OPTION_64
},
10289 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10290 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10291 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10292 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10293 #endif /* OBJ_ELF */
10294 {NULL
, no_argument
, NULL
, 0}
10296 size_t md_longopts_size
= sizeof (md_longopts
);
10298 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10299 NEW_VALUE. Warn if another value was already specified. Note:
10300 we have to defer parsing the -march and -mtune arguments in order
10301 to handle 'from-abi' correctly, since the ABI might be specified
10302 in a later argument. */
10305 mips_set_option_string (string_ptr
, new_value
)
10306 const char **string_ptr
, *new_value
;
10308 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10309 as_warn (_("A different %s was already specified, is now %s"),
10310 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10313 *string_ptr
= new_value
;
10317 md_parse_option (c
, arg
)
10323 case OPTION_CONSTRUCT_FLOATS
:
10324 mips_disable_float_construction
= 0;
10327 case OPTION_NO_CONSTRUCT_FLOATS
:
10328 mips_disable_float_construction
= 1;
10340 target_big_endian
= 1;
10344 target_big_endian
= 0;
10352 if (arg
&& arg
[1] == '0')
10362 mips_debug
= atoi (arg
);
10363 /* When the MIPS assembler sees -g or -g2, it does not do
10364 optimizations which limit full symbolic debugging. We take
10365 that to be equivalent to -O0. */
10366 if (mips_debug
== 2)
10371 file_mips_isa
= ISA_MIPS1
;
10375 file_mips_isa
= ISA_MIPS2
;
10379 file_mips_isa
= ISA_MIPS3
;
10383 file_mips_isa
= ISA_MIPS4
;
10387 file_mips_isa
= ISA_MIPS5
;
10390 case OPTION_MIPS32
:
10391 file_mips_isa
= ISA_MIPS32
;
10394 case OPTION_MIPS64
:
10395 file_mips_isa
= ISA_MIPS64
;
10399 mips_set_option_string (&mips_tune_string
, arg
);
10403 mips_set_option_string (&mips_arch_string
, arg
);
10407 mips_set_option_string (&mips_arch_string
, "4650");
10408 mips_set_option_string (&mips_tune_string
, "4650");
10411 case OPTION_NO_M4650
:
10415 mips_set_option_string (&mips_arch_string
, "4010");
10416 mips_set_option_string (&mips_tune_string
, "4010");
10419 case OPTION_NO_M4010
:
10423 mips_set_option_string (&mips_arch_string
, "4100");
10424 mips_set_option_string (&mips_tune_string
, "4100");
10427 case OPTION_NO_M4100
:
10431 mips_set_option_string (&mips_arch_string
, "3900");
10432 mips_set_option_string (&mips_tune_string
, "3900");
10435 case OPTION_NO_M3900
:
10439 mips_opts
.ase_mdmx
= 1;
10442 case OPTION_NO_MDMX
:
10443 mips_opts
.ase_mdmx
= 0;
10446 case OPTION_MIPS16
:
10447 mips_opts
.mips16
= 1;
10448 mips_no_prev_insn (false);
10451 case OPTION_NO_MIPS16
:
10452 mips_opts
.mips16
= 0;
10453 mips_no_prev_insn (false);
10456 case OPTION_MIPS3D
:
10457 mips_opts
.ase_mips3d
= 1;
10460 case OPTION_NO_MIPS3D
:
10461 mips_opts
.ase_mips3d
= 0;
10464 case OPTION_MEMBEDDED_PIC
:
10465 mips_pic
= EMBEDDED_PIC
;
10466 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10468 as_bad (_("-G may not be used with embedded PIC code"));
10471 g_switch_value
= 0x7fffffff;
10474 case OPTION_FIX_VR4122
:
10475 mips_fix_4122_bugs
= 1;
10478 case OPTION_NO_FIX_VR4122
:
10479 mips_fix_4122_bugs
= 0;
10482 case OPTION_RELAX_BRANCH
:
10483 mips_relax_branch
= 1;
10486 case OPTION_NO_RELAX_BRANCH
:
10487 mips_relax_branch
= 0;
10491 /* When generating ELF code, we permit -KPIC and -call_shared to
10492 select SVR4_PIC, and -non_shared to select no PIC. This is
10493 intended to be compatible with Irix 5. */
10494 case OPTION_CALL_SHARED
:
10495 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10497 as_bad (_("-call_shared is supported only for ELF format"));
10500 mips_pic
= SVR4_PIC
;
10501 if (g_switch_seen
&& g_switch_value
!= 0)
10503 as_bad (_("-G may not be used with SVR4 PIC code"));
10506 g_switch_value
= 0;
10509 case OPTION_NON_SHARED
:
10510 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10512 as_bad (_("-non_shared is supported only for ELF format"));
10518 /* The -xgot option tells the assembler to use 32 offsets when
10519 accessing the got in SVR4_PIC mode. It is for Irix
10524 #endif /* OBJ_ELF */
10527 if (! USE_GLOBAL_POINTER_OPT
)
10529 as_bad (_("-G is not supported for this configuration"));
10532 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10534 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10538 g_switch_value
= atoi (arg
);
10543 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10546 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10548 as_bad (_("-32 is supported for ELF format only"));
10551 mips_abi
= O32_ABI
;
10555 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10557 as_bad (_("-n32 is supported for ELF format only"));
10560 mips_abi
= N32_ABI
;
10564 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10566 as_bad (_("-64 is supported for ELF format only"));
10569 mips_abi
= N64_ABI
;
10570 if (! support_64bit_objects())
10571 as_fatal (_("No compiled in support for 64 bit object file format"));
10573 #endif /* OBJ_ELF */
10576 file_mips_gp32
= 1;
10580 file_mips_gp32
= 0;
10584 file_mips_fp32
= 1;
10588 file_mips_fp32
= 0;
10593 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10595 as_bad (_("-mabi is supported for ELF format only"));
10598 if (strcmp (arg
, "32") == 0)
10599 mips_abi
= O32_ABI
;
10600 else if (strcmp (arg
, "o64") == 0)
10601 mips_abi
= O64_ABI
;
10602 else if (strcmp (arg
, "n32") == 0)
10603 mips_abi
= N32_ABI
;
10604 else if (strcmp (arg
, "64") == 0)
10606 mips_abi
= N64_ABI
;
10607 if (! support_64bit_objects())
10608 as_fatal (_("No compiled in support for 64 bit object file "
10611 else if (strcmp (arg
, "eabi") == 0)
10612 mips_abi
= EABI_ABI
;
10615 as_fatal (_("invalid abi -mabi=%s"), arg
);
10619 #endif /* OBJ_ELF */
10621 case OPTION_M7000_HILO_FIX
:
10622 mips_7000_hilo_fix
= true;
10625 case OPTION_MNO_7000_HILO_FIX
:
10626 mips_7000_hilo_fix
= false;
10630 case OPTION_MDEBUG
:
10631 mips_flag_mdebug
= true;
10634 case OPTION_NO_MDEBUG
:
10635 mips_flag_mdebug
= false;
10637 #endif /* OBJ_ELF */
10646 /* Set up globals to generate code for the ISA or processor
10647 described by INFO. */
10650 mips_set_architecture (info
)
10651 const struct mips_cpu_info
*info
;
10655 mips_arch_info
= info
;
10656 mips_arch
= info
->cpu
;
10657 mips_opts
.isa
= info
->isa
;
10662 /* Likewise for tuning. */
10665 mips_set_tune (info
)
10666 const struct mips_cpu_info
*info
;
10670 mips_tune_info
= info
;
10671 mips_tune
= info
->cpu
;
10677 mips_after_parse_args ()
10679 /* GP relative stuff not working for PE */
10680 if (strncmp (TARGET_OS
, "pe", 2) == 0
10681 && g_switch_value
!= 0)
10684 as_bad (_("-G not supported in this configuration."));
10685 g_switch_value
= 0;
10688 /* The following code determines the architecture and register size.
10689 Similar code was added to GCC 3.3 (see override_options() in
10690 config/mips/mips.c). The GAS and GCC code should be kept in sync
10691 as much as possible. */
10693 if (mips_arch_string
!= 0)
10694 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
10696 if (mips_tune_string
!= 0)
10697 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
10699 if (file_mips_isa
!= ISA_UNKNOWN
)
10701 /* Handle -mipsN. At this point, file_mips_isa contains the
10702 ISA level specified by -mipsN, while mips_opts.isa contains
10703 the -march selection (if any). */
10704 if (mips_arch_info
!= 0)
10706 /* -march takes precedence over -mipsN, since it is more descriptive.
10707 There's no harm in specifying both as long as the ISA levels
10709 if (file_mips_isa
!= mips_opts
.isa
)
10710 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10711 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10712 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10715 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa
));
10718 if (mips_arch_info
== 0)
10719 mips_set_architecture (mips_parse_cpu ("default CPU",
10720 MIPS_CPU_STRING_DEFAULT
));
10722 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10723 as_bad ("-march=%s is not compatible with the selected ABI",
10724 mips_arch_info
->name
);
10726 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10727 if (mips_tune_info
== 0)
10728 mips_set_tune (mips_arch_info
);
10730 if (file_mips_gp32
>= 0)
10732 /* The user specified the size of the integer registers. Make sure
10733 it agrees with the ABI and ISA. */
10734 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10735 as_bad (_("-mgp64 used with a 32-bit processor"));
10736 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10737 as_bad (_("-mgp32 used with a 64-bit ABI"));
10738 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10739 as_bad (_("-mgp64 used with a 32-bit ABI"));
10743 /* Infer the integer register size from the ABI and processor.
10744 Restrict ourselves to 32-bit registers if that's all the
10745 processor has, or if the ABI cannot handle 64-bit registers. */
10746 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10747 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10750 /* ??? GAS treats single-float processors as though they had 64-bit
10751 float registers (although it complains when double-precision
10752 instructions are used). As things stand, saying they have 32-bit
10753 registers would lead to spurious "register must be even" messages.
10754 So here we assume float registers are always the same size as
10755 integer ones, unless the user says otherwise. */
10756 if (file_mips_fp32
< 0)
10757 file_mips_fp32
= file_mips_gp32
;
10759 /* End of GCC-shared inference code. */
10761 /* ??? When do we want this flag to be set? Who uses it? */
10762 if (file_mips_gp32
== 1
10763 && mips_abi
== NO_ABI
10764 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10765 mips_32bitmode
= 1;
10767 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10768 as_bad (_("trap exception not supported at ISA 1"));
10770 /* If the selected architecture includes support for ASEs, enable
10771 generation of code for them. */
10772 if (mips_opts
.mips16
== -1)
10773 mips_opts
.mips16
= (CPU_HAS_MIPS16 (mips_arch
)) ? 1 : 0;
10774 if (mips_opts
.ase_mips3d
== -1)
10775 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (mips_arch
)) ? 1 : 0;
10776 if (mips_opts
.ase_mdmx
== -1)
10777 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (mips_arch
)) ? 1 : 0;
10779 file_mips_isa
= mips_opts
.isa
;
10780 file_ase_mips16
= mips_opts
.mips16
;
10781 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10782 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10783 mips_opts
.gp32
= file_mips_gp32
;
10784 mips_opts
.fp32
= file_mips_fp32
;
10786 if (mips_flag_mdebug
< 0)
10788 #ifdef OBJ_MAYBE_ECOFF
10789 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10790 mips_flag_mdebug
= 1;
10792 #endif /* OBJ_MAYBE_ECOFF */
10793 mips_flag_mdebug
= 0;
10798 mips_init_after_args ()
10800 /* initialize opcodes */
10801 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10802 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10806 md_pcrel_from (fixP
)
10809 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10810 && fixP
->fx_addsy
!= (symbolS
*) NULL
10811 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10813 /* This makes a branch to an undefined symbol be a branch to the
10814 current location. */
10815 if (mips_pic
== EMBEDDED_PIC
)
10821 /* Return the address of the delay slot. */
10822 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10825 /* This is called before the symbol table is processed. In order to
10826 work with gcc when using mips-tfile, we must keep all local labels.
10827 However, in other cases, we want to discard them. If we were
10828 called with -g, but we didn't see any debugging information, it may
10829 mean that gcc is smuggling debugging information through to
10830 mips-tfile, in which case we must generate all local labels. */
10833 mips_frob_file_before_adjust ()
10835 #ifndef NO_ECOFF_DEBUGGING
10836 if (ECOFF_DEBUGGING
10838 && ! ecoff_debugging_seen
)
10839 flag_keep_locals
= 1;
10843 /* Sort any unmatched HI16_S relocs so that they immediately precede
10844 the corresponding LO reloc. This is called before md_apply_fix3 and
10845 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10846 explicit use of the %hi modifier. */
10851 struct mips_hi_fixup
*l
;
10853 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10855 segment_info_type
*seginfo
;
10858 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10860 /* Check quickly whether the next fixup happens to be a matching
10862 if (l
->fixp
->fx_next
!= NULL
10863 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10864 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10865 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10868 /* Look through the fixups for this segment for a matching %lo.
10869 When we find one, move the %hi just in front of it. We do
10870 this in two passes. In the first pass, we try to find a
10871 unique %lo. In the second pass, we permit multiple %hi
10872 relocs for a single %lo (this is a GNU extension). */
10873 seginfo
= seg_info (l
->seg
);
10874 for (pass
= 0; pass
< 2; pass
++)
10879 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10881 /* Check whether this is a %lo fixup which matches l->fixp. */
10882 if (f
->fx_r_type
== BFD_RELOC_LO16
10883 && f
->fx_addsy
== l
->fixp
->fx_addsy
10884 && f
->fx_offset
== l
->fixp
->fx_offset
10887 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10888 || prev
->fx_addsy
!= f
->fx_addsy
10889 || prev
->fx_offset
!= f
->fx_offset
))
10893 /* Move l->fixp before f. */
10894 for (pf
= &seginfo
->fix_root
;
10896 pf
= &(*pf
)->fx_next
)
10897 assert (*pf
!= NULL
);
10899 *pf
= l
->fixp
->fx_next
;
10901 l
->fixp
->fx_next
= f
;
10903 seginfo
->fix_root
= l
->fixp
;
10905 prev
->fx_next
= l
->fixp
;
10916 #if 0 /* GCC code motion plus incomplete dead code elimination
10917 can leave a %hi without a %lo. */
10919 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10920 _("Unmatched %%hi reloc"));
10926 /* When generating embedded PIC code we need to use a special
10927 relocation to represent the difference of two symbols in the .text
10928 section (switch tables use a difference of this sort). See
10929 include/coff/mips.h for details. This macro checks whether this
10930 fixup requires the special reloc. */
10931 #define SWITCH_TABLE(fixp) \
10932 ((fixp)->fx_r_type == BFD_RELOC_32 \
10933 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10934 && (fixp)->fx_addsy != NULL \
10935 && (fixp)->fx_subsy != NULL \
10936 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10937 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10939 /* When generating embedded PIC code we must keep all PC relative
10940 relocations, in case the linker has to relax a call. We also need
10941 to keep relocations for switch table entries.
10943 We may have combined relocations without symbols in the N32/N64 ABI.
10944 We have to prevent gas from dropping them. */
10947 mips_force_relocation (fixp
)
10950 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10951 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
10952 || S_FORCE_RELOC (fixp
->fx_addsy
))
10956 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10957 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10958 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10959 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10962 return (mips_pic
== EMBEDDED_PIC
10964 || SWITCH_TABLE (fixp
)
10965 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10966 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10971 mips_need_elf_addend_fixup (fixP
)
10974 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
10976 if (mips_pic
== EMBEDDED_PIC
10977 && S_IS_WEAK (fixP
->fx_addsy
))
10979 if (mips_pic
!= EMBEDDED_PIC
10980 && (S_IS_WEAK (fixP
->fx_addsy
)
10981 || S_IS_EXTERNAL (fixP
->fx_addsy
))
10982 && !S_IS_COMMON (fixP
->fx_addsy
))
10984 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10985 && (((bfd_get_section_flags (stdoutput
,
10986 S_GET_SEGMENT (fixP
->fx_addsy
))
10987 & (SEC_LINK_ONCE
| SEC_MERGE
)) != 0)
10988 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10990 sizeof (".gnu.linkonce") - 1)))
10996 /* Apply a fixup to the object file. */
10999 md_apply_fix3 (fixP
, valP
, seg
)
11002 segT seg ATTRIBUTE_UNUSED
;
11007 static int previous_fx_r_type
= 0;
11009 /* FIXME: Maybe just return for all reloc types not listed below?
11010 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
11011 if (fixP
->fx_r_type
== BFD_RELOC_8
)
11014 assert (fixP
->fx_size
== 4
11015 || fixP
->fx_r_type
== BFD_RELOC_16
11016 || fixP
->fx_r_type
== BFD_RELOC_32
11017 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
11018 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
11019 || fixP
->fx_r_type
== BFD_RELOC_LO16
11020 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
11021 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
11022 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
11023 || fixP
->fx_r_type
== BFD_RELOC_64
11024 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11025 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11026 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
11027 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
11028 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
11029 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
11030 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
11031 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11032 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
11033 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JALR
);
11037 /* If we aren't adjusting this fixup to be against the section
11038 symbol, we need to adjust the value. */
11040 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11042 if (mips_need_elf_addend_fixup (fixP
))
11044 reloc_howto_type
*howto
;
11045 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
11049 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11050 if (value
!= 0 && howto
->partial_inplace
11051 && (! fixP
->fx_pcrel
|| howto
->pcrel_offset
))
11053 /* In this case, the bfd_install_relocation routine will
11054 incorrectly add the symbol value back in. We just want
11055 the addend to appear in the object file.
11057 howto->pcrel_offset is added for R_MIPS_PC16, which is
11058 generated for code like
11069 /* Make sure the addend is still non-zero. If it became zero
11070 after the last operation, set it to a spurious value and
11071 subtract the same value from the object file's contents. */
11076 /* The in-place addends for LO16 relocations are signed;
11077 leave the matching HI16 in-place addends as zero. */
11078 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
11080 bfd_vma contents
, mask
, field
;
11082 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
11085 target_big_endian
);
11087 /* MASK has bits set where the relocation should go.
11088 FIELD is -value, shifted into the appropriate place
11089 for this relocation. */
11090 mask
= 1 << (howto
->bitsize
- 1);
11091 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
11092 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
11094 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
11095 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11097 target_big_endian
);
11103 /* This code was generated using trial and error and so is
11104 fragile and not trustworthy. If you change it, you should
11105 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11106 they still pass. */
11107 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
11109 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11111 /* BFD's REL handling, for MIPS, is _very_ weird.
11112 This gives the right results, but it can't possibly
11113 be the way things are supposed to work. */
11114 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
11115 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
11116 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
11117 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11122 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
11124 /* We are not done if this is a composite relocation to set up gp. */
11125 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11126 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11127 || (fixP
->fx_r_type
== BFD_RELOC_64
11128 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11129 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11130 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11131 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11132 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11134 previous_fx_r_type
= fixP
->fx_r_type
;
11136 switch (fixP
->fx_r_type
)
11138 case BFD_RELOC_MIPS_JMP
:
11139 case BFD_RELOC_MIPS_SHIFT5
:
11140 case BFD_RELOC_MIPS_SHIFT6
:
11141 case BFD_RELOC_MIPS_GOT_DISP
:
11142 case BFD_RELOC_MIPS_GOT_PAGE
:
11143 case BFD_RELOC_MIPS_GOT_OFST
:
11144 case BFD_RELOC_MIPS_SUB
:
11145 case BFD_RELOC_MIPS_INSERT_A
:
11146 case BFD_RELOC_MIPS_INSERT_B
:
11147 case BFD_RELOC_MIPS_DELETE
:
11148 case BFD_RELOC_MIPS_HIGHEST
:
11149 case BFD_RELOC_MIPS_HIGHER
:
11150 case BFD_RELOC_MIPS_SCN_DISP
:
11151 case BFD_RELOC_MIPS_REL16
:
11152 case BFD_RELOC_MIPS_RELGOT
:
11153 case BFD_RELOC_MIPS_JALR
:
11154 case BFD_RELOC_HI16
:
11155 case BFD_RELOC_HI16_S
:
11156 case BFD_RELOC_GPREL16
:
11157 case BFD_RELOC_MIPS_LITERAL
:
11158 case BFD_RELOC_MIPS_CALL16
:
11159 case BFD_RELOC_MIPS_GOT16
:
11160 case BFD_RELOC_GPREL32
:
11161 case BFD_RELOC_MIPS_GOT_HI16
:
11162 case BFD_RELOC_MIPS_GOT_LO16
:
11163 case BFD_RELOC_MIPS_CALL_HI16
:
11164 case BFD_RELOC_MIPS_CALL_LO16
:
11165 case BFD_RELOC_MIPS16_GPREL
:
11166 if (fixP
->fx_pcrel
)
11167 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11168 _("Invalid PC relative reloc"));
11169 /* Nothing needed to do. The value comes from the reloc entry */
11172 case BFD_RELOC_MIPS16_JMP
:
11173 /* We currently always generate a reloc against a symbol, which
11174 means that we don't want an addend even if the symbol is
11176 fixP
->fx_addnumber
= 0;
11179 case BFD_RELOC_PCREL_HI16_S
:
11180 /* The addend for this is tricky if it is internal, so we just
11181 do everything here rather than in bfd_install_relocation. */
11182 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11187 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11189 /* For an external symbol adjust by the address to make it
11190 pcrel_offset. We use the address of the RELLO reloc
11191 which follows this one. */
11192 value
+= (fixP
->fx_next
->fx_frag
->fr_address
11193 + fixP
->fx_next
->fx_where
);
11195 value
= ((value
+ 0x8000) >> 16) & 0xffff;
11196 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11197 if (target_big_endian
)
11199 md_number_to_chars ((char *) buf
, value
, 2);
11202 case BFD_RELOC_PCREL_LO16
:
11203 /* The addend for this is tricky if it is internal, so we just
11204 do everything here rather than in bfd_install_relocation. */
11205 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11210 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11211 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11212 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11213 if (target_big_endian
)
11215 md_number_to_chars ((char *) buf
, value
, 2);
11219 /* This is handled like BFD_RELOC_32, but we output a sign
11220 extended value if we are only 32 bits. */
11222 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11224 if (8 <= sizeof (valueT
))
11225 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11232 w1
= w2
= fixP
->fx_where
;
11233 if (target_big_endian
)
11237 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
11238 if ((value
& 0x80000000) != 0)
11242 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
11247 case BFD_RELOC_RVA
:
11249 /* If we are deleting this reloc entry, we must fill in the
11250 value now. This can happen if we have a .word which is not
11251 resolved when it appears but is later defined. We also need
11252 to fill in the value if this is an embedded PIC switch table
11255 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11256 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11261 /* If we are deleting this reloc entry, we must fill in the
11263 assert (fixP
->fx_size
== 2);
11265 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11269 case BFD_RELOC_LO16
:
11270 /* When handling an embedded PIC switch statement, we can wind
11271 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11274 if (value
+ 0x8000 > 0xffff)
11275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11276 _("relocation overflow"));
11277 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11278 if (target_big_endian
)
11280 md_number_to_chars ((char *) buf
, value
, 2);
11284 case BFD_RELOC_16_PCREL_S2
:
11285 if ((value
& 0x3) != 0)
11286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11287 _("Branch to odd address (%lx)"), (long) value
);
11289 /* Fall through. */
11291 case BFD_RELOC_16_PCREL
:
11293 * We need to save the bits in the instruction since fixup_segment()
11294 * might be deleting the relocation entry (i.e., a branch within
11295 * the current segment).
11297 if (!fixP
->fx_done
&& value
!= 0)
11299 /* If 'value' is zero, the remaining reloc code won't actually
11300 do the store, so it must be done here. This is probably
11301 a bug somewhere. */
11303 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11304 || fixP
->fx_addsy
== NULL
/* ??? */
11305 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
11306 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11308 value
= (offsetT
) value
>> 2;
11310 /* update old instruction data */
11311 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
11312 if (target_big_endian
)
11313 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11315 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11317 if (value
+ 0x8000 <= 0xffff)
11318 insn
|= value
& 0xffff;
11321 /* The branch offset is too large. If this is an
11322 unconditional branch, and we are not generating PIC code,
11323 we can convert it to an absolute jump instruction. */
11324 if (mips_pic
== NO_PIC
11326 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11327 && (fixP
->fx_frag
->fr_address
11328 < text_section
->vma
+ text_section
->_raw_size
)
11329 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11330 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11331 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11333 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11334 insn
= 0x0c000000; /* jal */
11336 insn
= 0x08000000; /* j */
11337 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11339 fixP
->fx_addsy
= section_symbol (text_section
);
11340 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
11344 /* If we got here, we have branch-relaxation disabled,
11345 and there's nothing we can do to fix this instruction
11346 without turning it into a longer sequence. */
11347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11348 _("Branch out of range"));
11352 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11355 case BFD_RELOC_VTABLE_INHERIT
:
11358 && !S_IS_DEFINED (fixP
->fx_addsy
)
11359 && !S_IS_WEAK (fixP
->fx_addsy
))
11360 S_SET_WEAK (fixP
->fx_addsy
);
11363 case BFD_RELOC_VTABLE_ENTRY
:
11377 const struct mips_opcode
*p
;
11378 int treg
, sreg
, dreg
, shamt
;
11383 for (i
= 0; i
< NUMOPCODES
; ++i
)
11385 p
= &mips_opcodes
[i
];
11386 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11388 printf ("%08lx %s\t", oc
, p
->name
);
11389 treg
= (oc
>> 16) & 0x1f;
11390 sreg
= (oc
>> 21) & 0x1f;
11391 dreg
= (oc
>> 11) & 0x1f;
11392 shamt
= (oc
>> 6) & 0x1f;
11394 for (args
= p
->args
;; ++args
)
11405 printf ("%c", *args
);
11409 assert (treg
== sreg
);
11410 printf ("$%d,$%d", treg
, sreg
);
11415 printf ("$%d", dreg
);
11420 printf ("$%d", treg
);
11424 printf ("0x%x", treg
);
11429 printf ("$%d", sreg
);
11433 printf ("0x%08lx", oc
& 0x1ffffff);
11440 printf ("%d", imm
);
11445 printf ("$%d", shamt
);
11456 printf (_("%08lx UNDEFINED\n"), oc
);
11467 name
= input_line_pointer
;
11468 c
= get_symbol_end ();
11469 p
= (symbolS
*) symbol_find_or_make (name
);
11470 *input_line_pointer
= c
;
11474 /* Align the current frag to a given power of two. The MIPS assembler
11475 also automatically adjusts any preceding label. */
11478 mips_align (to
, fill
, label
)
11483 mips_emit_delays (false);
11484 frag_align (to
, fill
, 0);
11485 record_alignment (now_seg
, to
);
11488 assert (S_GET_SEGMENT (label
) == now_seg
);
11489 symbol_set_frag (label
, frag_now
);
11490 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11494 /* Align to a given power of two. .align 0 turns off the automatic
11495 alignment used by the data creating pseudo-ops. */
11499 int x ATTRIBUTE_UNUSED
;
11502 register long temp_fill
;
11503 long max_alignment
= 15;
11507 o Note that the assembler pulls down any immediately preceeding label
11508 to the aligned address.
11509 o It's not documented but auto alignment is reinstated by
11510 a .align pseudo instruction.
11511 o Note also that after auto alignment is turned off the mips assembler
11512 issues an error on attempt to assemble an improperly aligned data item.
11517 temp
= get_absolute_expression ();
11518 if (temp
> max_alignment
)
11519 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11522 as_warn (_("Alignment negative: 0 assumed."));
11525 if (*input_line_pointer
== ',')
11527 ++input_line_pointer
;
11528 temp_fill
= get_absolute_expression ();
11535 mips_align (temp
, (int) temp_fill
,
11536 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11543 demand_empty_rest_of_line ();
11547 mips_flush_pending_output ()
11549 mips_emit_delays (false);
11550 mips_clear_insn_labels ();
11559 /* When generating embedded PIC code, we only use the .text, .lit8,
11560 .sdata and .sbss sections. We change the .data and .rdata
11561 pseudo-ops to use .sdata. */
11562 if (mips_pic
== EMBEDDED_PIC
11563 && (sec
== 'd' || sec
== 'r'))
11567 /* The ELF backend needs to know that we are changing sections, so
11568 that .previous works correctly. We could do something like check
11569 for an obj_section_change_hook macro, but that might be confusing
11570 as it would not be appropriate to use it in the section changing
11571 functions in read.c, since obj-elf.c intercepts those. FIXME:
11572 This should be cleaner, somehow. */
11573 obj_elf_section_change_hook ();
11576 mips_emit_delays (false);
11586 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11587 demand_empty_rest_of_line ();
11591 if (USE_GLOBAL_POINTER_OPT
)
11593 seg
= subseg_new (RDATA_SECTION_NAME
,
11594 (subsegT
) get_absolute_expression ());
11595 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11597 bfd_set_section_flags (stdoutput
, seg
,
11603 if (strcmp (TARGET_OS
, "elf") != 0)
11604 record_alignment (seg
, 4);
11606 demand_empty_rest_of_line ();
11610 as_bad (_("No read only data section in this object file format"));
11611 demand_empty_rest_of_line ();
11617 if (USE_GLOBAL_POINTER_OPT
)
11619 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11620 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11622 bfd_set_section_flags (stdoutput
, seg
,
11623 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11625 if (strcmp (TARGET_OS
, "elf") != 0)
11626 record_alignment (seg
, 4);
11628 demand_empty_rest_of_line ();
11633 as_bad (_("Global pointers not supported; recompile -G 0"));
11634 demand_empty_rest_of_line ();
11643 s_change_section (ignore
)
11644 int ignore ATTRIBUTE_UNUSED
;
11647 char *section_name
;
11652 int section_entry_size
;
11653 int section_alignment
;
11655 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11658 section_name
= input_line_pointer
;
11659 c
= get_symbol_end ();
11660 next_c
= *(input_line_pointer
+ 1);
11662 /* Do we have .section Name<,"flags">? */
11663 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11665 /* just after name is now '\0'. */
11666 *input_line_pointer
= c
;
11667 input_line_pointer
= section_name
;
11668 obj_elf_section (ignore
);
11671 input_line_pointer
++;
11673 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11675 section_type
= get_absolute_expression ();
11678 if (*input_line_pointer
++ == ',')
11679 section_flag
= get_absolute_expression ();
11682 if (*input_line_pointer
++ == ',')
11683 section_entry_size
= get_absolute_expression ();
11685 section_entry_size
= 0;
11686 if (*input_line_pointer
++ == ',')
11687 section_alignment
= get_absolute_expression ();
11689 section_alignment
= 0;
11691 obj_elf_change_section (section_name
, section_type
, section_flag
,
11692 section_entry_size
, 0, 0, 0);
11693 #endif /* OBJ_ELF */
11697 mips_enable_auto_align ()
11708 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11709 mips_emit_delays (false);
11710 if (log_size
> 0 && auto_align
)
11711 mips_align (log_size
, 0, label
);
11712 mips_clear_insn_labels ();
11713 cons (1 << log_size
);
11717 s_float_cons (type
)
11722 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11724 mips_emit_delays (false);
11729 mips_align (3, 0, label
);
11731 mips_align (2, 0, label
);
11734 mips_clear_insn_labels ();
11739 /* Handle .globl. We need to override it because on Irix 5 you are
11742 where foo is an undefined symbol, to mean that foo should be
11743 considered to be the address of a function. */
11747 int x ATTRIBUTE_UNUSED
;
11754 name
= input_line_pointer
;
11755 c
= get_symbol_end ();
11756 symbolP
= symbol_find_or_make (name
);
11757 *input_line_pointer
= c
;
11758 SKIP_WHITESPACE ();
11760 /* On Irix 5, every global symbol that is not explicitly labelled as
11761 being a function is apparently labelled as being an object. */
11764 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11769 secname
= input_line_pointer
;
11770 c
= get_symbol_end ();
11771 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11773 as_bad (_("%s: no such section"), secname
);
11774 *input_line_pointer
= c
;
11776 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11777 flag
= BSF_FUNCTION
;
11780 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11782 S_SET_EXTERNAL (symbolP
);
11783 demand_empty_rest_of_line ();
11788 int x ATTRIBUTE_UNUSED
;
11793 opt
= input_line_pointer
;
11794 c
= get_symbol_end ();
11798 /* FIXME: What does this mean? */
11800 else if (strncmp (opt
, "pic", 3) == 0)
11804 i
= atoi (opt
+ 3);
11808 mips_pic
= SVR4_PIC
;
11810 as_bad (_(".option pic%d not supported"), i
);
11812 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11814 if (g_switch_seen
&& g_switch_value
!= 0)
11815 as_warn (_("-G may not be used with SVR4 PIC code"));
11816 g_switch_value
= 0;
11817 bfd_set_gp_size (stdoutput
, 0);
11821 as_warn (_("Unrecognized option \"%s\""), opt
);
11823 *input_line_pointer
= c
;
11824 demand_empty_rest_of_line ();
11827 /* This structure is used to hold a stack of .set values. */
11829 struct mips_option_stack
11831 struct mips_option_stack
*next
;
11832 struct mips_set_options options
;
11835 static struct mips_option_stack
*mips_opts_stack
;
11837 /* Handle the .set pseudo-op. */
11841 int x ATTRIBUTE_UNUSED
;
11843 char *name
= input_line_pointer
, ch
;
11845 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11846 ++input_line_pointer
;
11847 ch
= *input_line_pointer
;
11848 *input_line_pointer
= '\0';
11850 if (strcmp (name
, "reorder") == 0)
11852 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11854 /* If we still have pending nops, we can discard them. The
11855 usual nop handling will insert any that are still
11857 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11858 * (mips_opts
.mips16
? 2 : 4));
11859 prev_nop_frag
= NULL
;
11861 mips_opts
.noreorder
= 0;
11863 else if (strcmp (name
, "noreorder") == 0)
11865 mips_emit_delays (true);
11866 mips_opts
.noreorder
= 1;
11867 mips_any_noreorder
= 1;
11869 else if (strcmp (name
, "at") == 0)
11871 mips_opts
.noat
= 0;
11873 else if (strcmp (name
, "noat") == 0)
11875 mips_opts
.noat
= 1;
11877 else if (strcmp (name
, "macro") == 0)
11879 mips_opts
.warn_about_macros
= 0;
11881 else if (strcmp (name
, "nomacro") == 0)
11883 if (mips_opts
.noreorder
== 0)
11884 as_bad (_("`noreorder' must be set before `nomacro'"));
11885 mips_opts
.warn_about_macros
= 1;
11887 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11889 mips_opts
.nomove
= 0;
11891 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11893 mips_opts
.nomove
= 1;
11895 else if (strcmp (name
, "bopt") == 0)
11897 mips_opts
.nobopt
= 0;
11899 else if (strcmp (name
, "nobopt") == 0)
11901 mips_opts
.nobopt
= 1;
11903 else if (strcmp (name
, "mips16") == 0
11904 || strcmp (name
, "MIPS-16") == 0)
11905 mips_opts
.mips16
= 1;
11906 else if (strcmp (name
, "nomips16") == 0
11907 || strcmp (name
, "noMIPS-16") == 0)
11908 mips_opts
.mips16
= 0;
11909 else if (strcmp (name
, "mips3d") == 0)
11910 mips_opts
.ase_mips3d
= 1;
11911 else if (strcmp (name
, "nomips3d") == 0)
11912 mips_opts
.ase_mips3d
= 0;
11913 else if (strcmp (name
, "mdmx") == 0)
11914 mips_opts
.ase_mdmx
= 1;
11915 else if (strcmp (name
, "nomdmx") == 0)
11916 mips_opts
.ase_mdmx
= 0;
11917 else if (strncmp (name
, "mips", 4) == 0)
11921 /* Permit the user to change the ISA on the fly. Needless to
11922 say, misuse can cause serious problems. */
11923 isa
= atoi (name
+ 4);
11927 mips_opts
.gp32
= file_mips_gp32
;
11928 mips_opts
.fp32
= file_mips_fp32
;
11933 mips_opts
.gp32
= 1;
11934 mips_opts
.fp32
= 1;
11940 mips_opts
.gp32
= 0;
11941 mips_opts
.fp32
= 0;
11944 as_bad (_("unknown ISA level %s"), name
+ 4);
11950 case 0: mips_opts
.isa
= file_mips_isa
; break;
11951 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11952 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11953 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11954 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11955 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11956 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11957 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11958 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11961 else if (strcmp (name
, "autoextend") == 0)
11962 mips_opts
.noautoextend
= 0;
11963 else if (strcmp (name
, "noautoextend") == 0)
11964 mips_opts
.noautoextend
= 1;
11965 else if (strcmp (name
, "push") == 0)
11967 struct mips_option_stack
*s
;
11969 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11970 s
->next
= mips_opts_stack
;
11971 s
->options
= mips_opts
;
11972 mips_opts_stack
= s
;
11974 else if (strcmp (name
, "pop") == 0)
11976 struct mips_option_stack
*s
;
11978 s
= mips_opts_stack
;
11980 as_bad (_(".set pop with no .set push"));
11983 /* If we're changing the reorder mode we need to handle
11984 delay slots correctly. */
11985 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11986 mips_emit_delays (true);
11987 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11989 if (prev_nop_frag
!= NULL
)
11991 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11992 * (mips_opts
.mips16
? 2 : 4));
11993 prev_nop_frag
= NULL
;
11997 mips_opts
= s
->options
;
11998 mips_opts_stack
= s
->next
;
12004 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12006 *input_line_pointer
= ch
;
12007 demand_empty_rest_of_line ();
12010 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12011 .option pic2. It means to generate SVR4 PIC calls. */
12014 s_abicalls (ignore
)
12015 int ignore ATTRIBUTE_UNUSED
;
12017 mips_pic
= SVR4_PIC
;
12018 if (USE_GLOBAL_POINTER_OPT
)
12020 if (g_switch_seen
&& g_switch_value
!= 0)
12021 as_warn (_("-G may not be used with SVR4 PIC code"));
12022 g_switch_value
= 0;
12024 bfd_set_gp_size (stdoutput
, 0);
12025 demand_empty_rest_of_line ();
12028 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12029 PIC code. It sets the $gp register for the function based on the
12030 function address, which is in the register named in the argument.
12031 This uses a relocation against _gp_disp, which is handled specially
12032 by the linker. The result is:
12033 lui $gp,%hi(_gp_disp)
12034 addiu $gp,$gp,%lo(_gp_disp)
12035 addu $gp,$gp,.cpload argument
12036 The .cpload argument is normally $25 == $t9. */
12040 int ignore ATTRIBUTE_UNUSED
;
12045 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12046 .cpload is ignored. */
12047 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12053 /* .cpload should be in a .set noreorder section. */
12054 if (mips_opts
.noreorder
== 0)
12055 as_warn (_(".cpload not in noreorder section"));
12057 ex
.X_op
= O_symbol
;
12058 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12059 ex
.X_op_symbol
= NULL
;
12060 ex
.X_add_number
= 0;
12062 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12063 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12065 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
12066 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
12067 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
12069 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
12070 mips_gp_register
, mips_gp_register
, tc_get_register (0));
12072 demand_empty_rest_of_line ();
12075 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12076 .cpsetup $reg1, offset|$reg2, label
12078 If offset is given, this results in:
12079 sd $gp, offset($sp)
12080 lui $gp, %hi(%neg(%gp_rel(label)))
12081 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12082 daddu $gp, $gp, $reg1
12084 If $reg2 is given, this results in:
12085 daddu $reg2, $gp, $0
12086 lui $gp, %hi(%neg(%gp_rel(label)))
12087 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12088 daddu $gp, $gp, $reg1
12089 $reg1 is normally $25 == $t9. */
12092 int ignore ATTRIBUTE_UNUSED
;
12094 expressionS ex_off
;
12095 expressionS ex_sym
;
12100 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12101 We also need NewABI support. */
12102 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12108 reg1
= tc_get_register (0);
12109 SKIP_WHITESPACE ();
12110 if (*input_line_pointer
!= ',')
12112 as_bad (_("missing argument separator ',' for .cpsetup"));
12116 ++input_line_pointer
;
12117 SKIP_WHITESPACE ();
12118 if (*input_line_pointer
== '$')
12120 mips_cpreturn_register
= tc_get_register (0);
12121 mips_cpreturn_offset
= -1;
12125 mips_cpreturn_offset
= get_absolute_expression ();
12126 mips_cpreturn_register
= -1;
12128 SKIP_WHITESPACE ();
12129 if (*input_line_pointer
!= ',')
12131 as_bad (_("missing argument separator ',' for .cpsetup"));
12135 ++input_line_pointer
;
12136 SKIP_WHITESPACE ();
12137 expression (&ex_sym
);
12139 if (mips_cpreturn_register
== -1)
12141 ex_off
.X_op
= O_constant
;
12142 ex_off
.X_add_symbol
= NULL
;
12143 ex_off
.X_op_symbol
= NULL
;
12144 ex_off
.X_add_number
= mips_cpreturn_offset
;
12146 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
12147 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12150 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12151 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
12153 /* Ensure there's room for the next two instructions, so that `f'
12154 doesn't end up with an address in the wrong frag. */
12157 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
12158 (int) BFD_RELOC_GPREL16
);
12159 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12160 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12161 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12162 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12165 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
12166 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
12167 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12168 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12169 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12170 0, NULL
, 0, 0, BFD_RELOC_LO16
);
12172 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12173 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
12174 mips_gp_register
, mips_gp_register
, reg1
);
12176 demand_empty_rest_of_line ();
12181 int ignore ATTRIBUTE_UNUSED
;
12183 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12184 .cplocal is ignored. */
12185 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12191 mips_gp_register
= tc_get_register (0);
12192 demand_empty_rest_of_line ();
12195 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12196 offset from $sp. The offset is remembered, and after making a PIC
12197 call $gp is restored from that location. */
12200 s_cprestore (ignore
)
12201 int ignore ATTRIBUTE_UNUSED
;
12206 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12207 .cprestore is ignored. */
12208 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12214 mips_cprestore_offset
= get_absolute_expression ();
12215 mips_cprestore_valid
= 1;
12217 ex
.X_op
= O_constant
;
12218 ex
.X_add_symbol
= NULL
;
12219 ex
.X_op_symbol
= NULL
;
12220 ex
.X_add_number
= mips_cprestore_offset
;
12222 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
,
12223 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
12224 mips_gp_register
, SP
);
12226 demand_empty_rest_of_line ();
12229 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12230 was given in the preceeding .gpsetup, it results in:
12231 ld $gp, offset($sp)
12233 If a register $reg2 was given there, it results in:
12234 daddiu $gp, $gp, $reg2
12237 s_cpreturn (ignore
)
12238 int ignore ATTRIBUTE_UNUSED
;
12243 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12244 We also need NewABI support. */
12245 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12251 if (mips_cpreturn_register
== -1)
12253 ex
.X_op
= O_constant
;
12254 ex
.X_add_symbol
= NULL
;
12255 ex
.X_op_symbol
= NULL
;
12256 ex
.X_add_number
= mips_cpreturn_offset
;
12258 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
12259 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12262 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12263 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
12265 demand_empty_rest_of_line ();
12268 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12269 code. It sets the offset to use in gp_rel relocations. */
12273 int ignore ATTRIBUTE_UNUSED
;
12275 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12276 We also need NewABI support. */
12277 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12283 mips_gprel_offset
= get_absolute_expression ();
12285 demand_empty_rest_of_line ();
12288 /* Handle the .gpword pseudo-op. This is used when generating PIC
12289 code. It generates a 32 bit GP relative reloc. */
12293 int ignore ATTRIBUTE_UNUSED
;
12299 /* When not generating PIC code, this is treated as .word. */
12300 if (mips_pic
!= SVR4_PIC
)
12306 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12307 mips_emit_delays (true);
12309 mips_align (2, 0, label
);
12310 mips_clear_insn_labels ();
12314 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12316 as_bad (_("Unsupported use of .gpword"));
12317 ignore_rest_of_line ();
12321 md_number_to_chars (p
, (valueT
) 0, 4);
12322 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
12323 BFD_RELOC_GPREL32
);
12325 demand_empty_rest_of_line ();
12330 int ignore ATTRIBUTE_UNUSED
;
12336 /* When not generating PIC code, this is treated as .dword. */
12337 if (mips_pic
!= SVR4_PIC
)
12343 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12344 mips_emit_delays (true);
12346 mips_align (3, 0, label
);
12347 mips_clear_insn_labels ();
12351 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12353 as_bad (_("Unsupported use of .gpdword"));
12354 ignore_rest_of_line ();
12358 md_number_to_chars (p
, (valueT
) 0, 8);
12359 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, false,
12360 BFD_RELOC_GPREL32
);
12362 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12363 ex
.X_op
= O_absent
;
12364 ex
.X_add_symbol
= 0;
12365 ex
.X_add_number
= 0;
12366 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, false,
12369 demand_empty_rest_of_line ();
12372 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12373 tables in SVR4 PIC code. */
12377 int ignore ATTRIBUTE_UNUSED
;
12382 /* This is ignored when not generating SVR4 PIC code. */
12383 if (mips_pic
!= SVR4_PIC
)
12389 /* Add $gp to the register named as an argument. */
12390 reg
= tc_get_register (0);
12391 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12392 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
12393 "d,v,t", reg
, reg
, mips_gp_register
);
12395 demand_empty_rest_of_line ();
12398 /* Handle the .insn pseudo-op. This marks instruction labels in
12399 mips16 mode. This permits the linker to handle them specially,
12400 such as generating jalx instructions when needed. We also make
12401 them odd for the duration of the assembly, in order to generate the
12402 right sort of code. We will make them even in the adjust_symtab
12403 routine, while leaving them marked. This is convenient for the
12404 debugger and the disassembler. The linker knows to make them odd
12409 int ignore ATTRIBUTE_UNUSED
;
12411 mips16_mark_labels ();
12413 demand_empty_rest_of_line ();
12416 /* Handle a .stabn directive. We need these in order to mark a label
12417 as being a mips16 text label correctly. Sometimes the compiler
12418 will emit a label, followed by a .stabn, and then switch sections.
12419 If the label and .stabn are in mips16 mode, then the label is
12420 really a mips16 text label. */
12427 mips16_mark_labels ();
12432 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12436 s_mips_weakext (ignore
)
12437 int ignore ATTRIBUTE_UNUSED
;
12444 name
= input_line_pointer
;
12445 c
= get_symbol_end ();
12446 symbolP
= symbol_find_or_make (name
);
12447 S_SET_WEAK (symbolP
);
12448 *input_line_pointer
= c
;
12450 SKIP_WHITESPACE ();
12452 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12454 if (S_IS_DEFINED (symbolP
))
12456 as_bad ("ignoring attempt to redefine symbol %s",
12457 S_GET_NAME (symbolP
));
12458 ignore_rest_of_line ();
12462 if (*input_line_pointer
== ',')
12464 ++input_line_pointer
;
12465 SKIP_WHITESPACE ();
12469 if (exp
.X_op
!= O_symbol
)
12471 as_bad ("bad .weakext directive");
12472 ignore_rest_of_line ();
12475 symbol_set_value_expression (symbolP
, &exp
);
12478 demand_empty_rest_of_line ();
12481 /* Parse a register string into a number. Called from the ECOFF code
12482 to parse .frame. The argument is non-zero if this is the frame
12483 register, so that we can record it in mips_frame_reg. */
12486 tc_get_register (frame
)
12491 SKIP_WHITESPACE ();
12492 if (*input_line_pointer
++ != '$')
12494 as_warn (_("expected `$'"));
12497 else if (ISDIGIT (*input_line_pointer
))
12499 reg
= get_absolute_expression ();
12500 if (reg
< 0 || reg
>= 32)
12502 as_warn (_("Bad register number"));
12508 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12511 input_line_pointer
+= 2;
12513 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12516 input_line_pointer
+= 2;
12518 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12521 input_line_pointer
+= 2;
12523 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12526 input_line_pointer
+= 2;
12528 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12531 input_line_pointer
+= 2;
12533 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12536 input_line_pointer
+= 3;
12538 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12541 input_line_pointer
+= 3;
12543 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12546 input_line_pointer
+= 4;
12550 as_warn (_("Unrecognized register name"));
12552 while (ISALNUM(*input_line_pointer
))
12553 input_line_pointer
++;
12558 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12559 mips_frame_reg_valid
= 1;
12560 mips_cprestore_valid
= 0;
12566 md_section_align (seg
, addr
)
12570 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12573 /* We don't need to align ELF sections to the full alignment.
12574 However, Irix 5 may prefer that we align them at least to a 16
12575 byte boundary. We don't bother to align the sections if we are
12576 targeted for an embedded system. */
12577 if (strcmp (TARGET_OS
, "elf") == 0)
12583 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12586 /* Utility routine, called from above as well. If called while the
12587 input file is still being read, it's only an approximation. (For
12588 example, a symbol may later become defined which appeared to be
12589 undefined earlier.) */
12592 nopic_need_relax (sym
, before_relaxing
)
12594 int before_relaxing
;
12599 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12601 const char *symname
;
12604 /* Find out whether this symbol can be referenced off the $gp
12605 register. It can be if it is smaller than the -G size or if
12606 it is in the .sdata or .sbss section. Certain symbols can
12607 not be referenced off the $gp, although it appears as though
12609 symname
= S_GET_NAME (sym
);
12610 if (symname
!= (const char *) NULL
12611 && (strcmp (symname
, "eprol") == 0
12612 || strcmp (symname
, "etext") == 0
12613 || strcmp (symname
, "_gp") == 0
12614 || strcmp (symname
, "edata") == 0
12615 || strcmp (symname
, "_fbss") == 0
12616 || strcmp (symname
, "_fdata") == 0
12617 || strcmp (symname
, "_ftext") == 0
12618 || strcmp (symname
, "end") == 0
12619 || strcmp (symname
, "_gp_disp") == 0))
12621 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12623 #ifndef NO_ECOFF_DEBUGGING
12624 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12625 && (symbol_get_obj (sym
)->ecoff_extern_size
12626 <= g_switch_value
))
12628 /* We must defer this decision until after the whole
12629 file has been read, since there might be a .extern
12630 after the first use of this symbol. */
12631 || (before_relaxing
12632 #ifndef NO_ECOFF_DEBUGGING
12633 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12635 && S_GET_VALUE (sym
) == 0)
12636 || (S_GET_VALUE (sym
) != 0
12637 && S_GET_VALUE (sym
) <= g_switch_value
)))
12641 const char *segname
;
12643 segname
= segment_name (S_GET_SEGMENT (sym
));
12644 assert (strcmp (segname
, ".lit8") != 0
12645 && strcmp (segname
, ".lit4") != 0);
12646 change
= (strcmp (segname
, ".sdata") != 0
12647 && strcmp (segname
, ".sbss") != 0
12648 && strncmp (segname
, ".sdata.", 7) != 0
12649 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12654 /* We are not optimizing for the $gp register. */
12658 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12659 extended opcode. SEC is the section the frag is in. */
12662 mips16_extended_frag (fragp
, sec
, stretch
)
12668 register const struct mips16_immed_operand
*op
;
12670 int mintiny
, maxtiny
;
12674 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12676 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12679 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12680 op
= mips16_immed_operands
;
12681 while (op
->type
!= type
)
12684 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12689 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12692 maxtiny
= 1 << op
->nbits
;
12697 maxtiny
= (1 << op
->nbits
) - 1;
12702 mintiny
= - (1 << (op
->nbits
- 1));
12703 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12706 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12707 val
= S_GET_VALUE (fragp
->fr_symbol
);
12708 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12714 /* We won't have the section when we are called from
12715 mips_relax_frag. However, we will always have been called
12716 from md_estimate_size_before_relax first. If this is a
12717 branch to a different section, we mark it as such. If SEC is
12718 NULL, and the frag is not marked, then it must be a branch to
12719 the same section. */
12722 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12727 /* Must have been called from md_estimate_size_before_relax. */
12730 fragp
->fr_subtype
=
12731 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12733 /* FIXME: We should support this, and let the linker
12734 catch branches and loads that are out of range. */
12735 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12736 _("unsupported PC relative reference to different section"));
12740 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12741 /* Assume non-extended on the first relaxation pass.
12742 The address we have calculated will be bogus if this is
12743 a forward branch to another frag, as the forward frag
12744 will have fr_address == 0. */
12748 /* In this case, we know for sure that the symbol fragment is in
12749 the same section. If the relax_marker of the symbol fragment
12750 differs from the relax_marker of this fragment, we have not
12751 yet adjusted the symbol fragment fr_address. We want to add
12752 in STRETCH in order to get a better estimate of the address.
12753 This particularly matters because of the shift bits. */
12755 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12759 /* Adjust stretch for any alignment frag. Note that if have
12760 been expanding the earlier code, the symbol may be
12761 defined in what appears to be an earlier frag. FIXME:
12762 This doesn't handle the fr_subtype field, which specifies
12763 a maximum number of bytes to skip when doing an
12765 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12767 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12770 stretch
= - ((- stretch
)
12771 & ~ ((1 << (int) f
->fr_offset
) - 1));
12773 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12782 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12784 /* The base address rules are complicated. The base address of
12785 a branch is the following instruction. The base address of a
12786 PC relative load or add is the instruction itself, but if it
12787 is in a delay slot (in which case it can not be extended) use
12788 the address of the instruction whose delay slot it is in. */
12789 if (type
== 'p' || type
== 'q')
12793 /* If we are currently assuming that this frag should be
12794 extended, then, the current address is two bytes
12796 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12799 /* Ignore the low bit in the target, since it will be set
12800 for a text label. */
12801 if ((val
& 1) != 0)
12804 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12806 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12809 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12811 /* Branch offsets have an implicit 0 in the lowest bit. */
12812 if (type
== 'p' || type
== 'q')
12815 /* If any of the shifted bits are set, we must use an extended
12816 opcode. If the address depends on the size of this
12817 instruction, this can lead to a loop, so we arrange to always
12818 use an extended opcode. We only check this when we are in
12819 the main relaxation loop, when SEC is NULL. */
12820 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12822 fragp
->fr_subtype
=
12823 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12827 /* If we are about to mark a frag as extended because the value
12828 is precisely maxtiny + 1, then there is a chance of an
12829 infinite loop as in the following code:
12834 In this case when the la is extended, foo is 0x3fc bytes
12835 away, so the la can be shrunk, but then foo is 0x400 away, so
12836 the la must be extended. To avoid this loop, we mark the
12837 frag as extended if it was small, and is about to become
12838 extended with a value of maxtiny + 1. */
12839 if (val
== ((maxtiny
+ 1) << op
->shift
)
12840 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12843 fragp
->fr_subtype
=
12844 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12848 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12849 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12851 if ((val
& ((1 << op
->shift
) - 1)) != 0
12852 || val
< (mintiny
<< op
->shift
)
12853 || val
> (maxtiny
<< op
->shift
))
12859 /* Compute the length of a branch sequence, and adjust the
12860 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12861 worst-case length is computed, with UPDATE being used to indicate
12862 whether an unconditional (-1), branch-likely (+1) or regular (0)
12863 branch is to be computed. */
12865 relaxed_branch_length (fragp
, sec
, update
)
12874 && S_IS_DEFINED (fragp
->fr_symbol
)
12875 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12880 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12882 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12886 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12889 /* If the symbol is not defined or it's in a different segment,
12890 assume the user knows what's going on and emit a short
12896 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12898 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_RELOC_S2 (fragp
->fr_subtype
),
12899 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12900 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12901 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12907 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12910 if (mips_pic
!= NO_PIC
)
12912 /* Additional space for PIC loading of target address. */
12914 if (mips_opts
.isa
== ISA_MIPS1
)
12915 /* Additional space for $at-stabilizing nop. */
12919 /* If branch is conditional. */
12920 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12927 /* Estimate the size of a frag before relaxing. Unless this is the
12928 mips16, we are not really relaxing here, and the final size is
12929 encoded in the subtype information. For the mips16, we have to
12930 decide whether we are using an extended opcode or not. */
12933 md_estimate_size_before_relax (fragp
, segtype
)
12938 boolean linkonce
= false;
12940 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12943 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false);
12945 return fragp
->fr_var
;
12948 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12949 /* We don't want to modify the EXTENDED bit here; it might get us
12950 into infinite loops. We change it only in mips_relax_frag(). */
12951 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12953 if (mips_pic
== NO_PIC
)
12955 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12957 else if (mips_pic
== SVR4_PIC
)
12962 sym
= fragp
->fr_symbol
;
12964 /* Handle the case of a symbol equated to another symbol. */
12965 while (symbol_equated_reloc_p (sym
))
12969 /* It's possible to get a loop here in a badly written
12971 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12977 symsec
= S_GET_SEGMENT (sym
);
12979 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12980 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12982 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12986 /* The GNU toolchain uses an extension for ELF: a section
12987 beginning with the magic string .gnu.linkonce is a linkonce
12989 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12990 sizeof ".gnu.linkonce" - 1) == 0)
12994 /* This must duplicate the test in adjust_reloc_syms. */
12995 change
= (symsec
!= &bfd_und_section
12996 && symsec
!= &bfd_abs_section
12997 && ! bfd_is_com_section (symsec
)
13000 /* A global or weak symbol is treated as external. */
13001 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13002 || (! S_IS_WEAK (sym
)
13003 && (! S_IS_EXTERNAL (sym
)
13004 || mips_pic
== EMBEDDED_PIC
)))
13013 /* Record the offset to the first reloc in the fr_opcode field.
13014 This lets md_convert_frag and tc_gen_reloc know that the code
13015 must be expanded. */
13016 fragp
->fr_opcode
= (fragp
->fr_literal
13018 - RELAX_OLD (fragp
->fr_subtype
)
13019 + RELAX_RELOC1 (fragp
->fr_subtype
));
13020 /* FIXME: This really needs as_warn_where. */
13021 if (RELAX_WARN (fragp
->fr_subtype
))
13022 as_warn (_("AT used after \".set noat\" or macro used after "
13023 "\".set nomacro\""));
13025 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
13031 /* This is called to see whether a reloc against a defined symbol
13032 should be converted into a reloc against a section. Don't adjust
13033 MIPS16 jump relocations, so we don't have to worry about the format
13034 of the offset in the .o file. Don't adjust relocations against
13035 mips16 symbols, so that the linker can find them if it needs to set
13039 mips_fix_adjustable (fixp
)
13042 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13045 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13046 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13049 if (fixp
->fx_addsy
== NULL
)
13053 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13054 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13055 && fixp
->fx_subsy
== NULL
)
13062 /* Translate internal representation of relocation info to BFD target
13066 tc_gen_reloc (section
, fixp
)
13067 asection
*section ATTRIBUTE_UNUSED
;
13070 static arelent
*retval
[4];
13072 bfd_reloc_code_real_type code
;
13074 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
13077 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13078 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13079 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13081 if (mips_pic
== EMBEDDED_PIC
13082 && SWITCH_TABLE (fixp
))
13084 /* For a switch table entry we use a special reloc. The addend
13085 is actually the difference between the reloc address and the
13087 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13088 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13089 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13090 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13092 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
13094 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13095 reloc
->addend
= fixp
->fx_addnumber
;
13098 /* We use a special addend for an internal RELLO reloc. */
13099 if (symbol_section_p (fixp
->fx_addsy
))
13100 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13102 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13105 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13107 assert (fixp
->fx_next
!= NULL
13108 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13110 /* The reloc is relative to the RELLO; adjust the addend
13112 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13113 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
13116 /* We use a special addend for an internal RELHI reloc. */
13117 if (symbol_section_p (fixp
->fx_addsy
))
13118 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
13119 + fixp
->fx_next
->fx_where
13120 - S_GET_VALUE (fixp
->fx_subsy
));
13122 reloc
->addend
= (fixp
->fx_addnumber
13123 + fixp
->fx_next
->fx_frag
->fr_address
13124 + fixp
->fx_next
->fx_where
);
13127 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13128 reloc
->addend
= fixp
->fx_addnumber
;
13131 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
13132 /* A gruesome hack which is a result of the gruesome gas reloc
13134 reloc
->addend
= reloc
->address
;
13136 reloc
->addend
= -reloc
->address
;
13139 /* If this is a variant frag, we may need to adjust the existing
13140 reloc and generate a new one. */
13141 if (fixp
->fx_frag
->fr_opcode
!= NULL
13142 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13144 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
13145 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
13146 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13147 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
13148 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13149 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
13154 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
13156 /* If this is not the last reloc in this frag, then we have two
13157 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13158 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13159 the second one handle all of them. */
13160 if (fixp
->fx_next
!= NULL
13161 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
13163 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13164 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
13165 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13166 && (fixp
->fx_next
->fx_r_type
13167 == BFD_RELOC_MIPS_GOT_LO16
))
13168 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13169 && (fixp
->fx_next
->fx_r_type
13170 == BFD_RELOC_MIPS_CALL_LO16
)));
13175 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
13176 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13177 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
13179 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13180 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13181 reloc2
->address
= (reloc
->address
13182 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
13183 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
13184 reloc2
->addend
= fixp
->fx_addnumber
;
13185 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
13186 assert (reloc2
->howto
!= NULL
);
13188 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
13192 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
13195 reloc3
->address
+= 4;
13198 if (mips_pic
== NO_PIC
)
13200 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
13201 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
13203 else if (mips_pic
== SVR4_PIC
)
13205 switch (fixp
->fx_r_type
)
13209 case BFD_RELOC_MIPS_GOT16
:
13211 case BFD_RELOC_MIPS_GOT_LO16
:
13212 case BFD_RELOC_MIPS_CALL_LO16
:
13213 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13215 case BFD_RELOC_MIPS_CALL16
:
13218 /* BFD_RELOC_MIPS_GOT16;*/
13219 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
13220 reloc2
->howto
= bfd_reloc_type_lookup
13221 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
13224 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13231 /* newabi uses R_MIPS_GOT_DISP for local symbols */
13232 if (HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
)
13234 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
13239 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13240 entry to be used in the relocation's section offset. */
13241 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13243 reloc
->address
= reloc
->addend
;
13247 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13248 fixup_segment converted a non-PC relative reloc into a PC
13249 relative reloc. In such a case, we need to convert the reloc
13251 code
= fixp
->fx_r_type
;
13252 if (fixp
->fx_pcrel
)
13257 code
= BFD_RELOC_8_PCREL
;
13260 code
= BFD_RELOC_16_PCREL
;
13263 code
= BFD_RELOC_32_PCREL
;
13266 code
= BFD_RELOC_64_PCREL
;
13268 case BFD_RELOC_8_PCREL
:
13269 case BFD_RELOC_16_PCREL
:
13270 case BFD_RELOC_32_PCREL
:
13271 case BFD_RELOC_64_PCREL
:
13272 case BFD_RELOC_16_PCREL_S2
:
13273 case BFD_RELOC_PCREL_HI16_S
:
13274 case BFD_RELOC_PCREL_LO16
:
13277 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13278 _("Cannot make %s relocation PC relative"),
13279 bfd_get_reloc_code_name (code
));
13284 /* md_apply_fix3 has a double-subtraction hack to get
13285 bfd_install_relocation to behave nicely. GPREL relocations are
13286 handled correctly without this hack, so undo it here. We can't
13287 stop md_apply_fix3 from subtracting twice in the first place since
13288 the fake addend is required for variant frags above. */
13289 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
13290 && (code
== BFD_RELOC_GPREL16
|| code
== BFD_RELOC_MIPS16_GPREL
)
13291 && reloc
->addend
!= 0
13292 && mips_need_elf_addend_fixup (fixp
))
13293 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
13296 /* To support a PC relative reloc when generating embedded PIC code
13297 for ECOFF, we use a Cygnus extension. We check for that here to
13298 make sure that we don't let such a reloc escape normally. */
13299 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13300 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13301 && code
== BFD_RELOC_16_PCREL_S2
13302 && mips_pic
!= EMBEDDED_PIC
)
13303 reloc
->howto
= NULL
;
13305 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13307 if (reloc
->howto
== NULL
)
13309 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13310 _("Can not represent %s relocation in this object file format"),
13311 bfd_get_reloc_code_name (code
));
13318 /* Relax a machine dependent frag. This returns the amount by which
13319 the current size of the frag should change. */
13322 mips_relax_frag (sec
, fragp
, stretch
)
13327 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13329 offsetT old_var
= fragp
->fr_var
;
13331 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
13333 return fragp
->fr_var
- old_var
;
13336 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13339 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13341 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13343 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13348 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13350 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13357 /* Convert a machine dependent frag. */
13360 md_convert_frag (abfd
, asec
, fragp
)
13361 bfd
*abfd ATTRIBUTE_UNUSED
;
13368 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13371 unsigned long insn
;
13375 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13377 if (target_big_endian
)
13378 insn
= bfd_getb32 (buf
);
13380 insn
= bfd_getl32 (buf
);
13382 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13384 /* We generate a fixup instead of applying it right now
13385 because, if there are linker relaxations, we're going to
13386 need the relocations. */
13387 exp
.X_op
= O_symbol
;
13388 exp
.X_add_symbol
= fragp
->fr_symbol
;
13389 exp
.X_add_number
= fragp
->fr_offset
;
13391 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13393 RELAX_BRANCH_RELOC_S2 (fragp
->fr_subtype
)
13394 ? BFD_RELOC_16_PCREL_S2
13395 : BFD_RELOC_16_PCREL
);
13396 fixp
->fx_file
= fragp
->fr_file
;
13397 fixp
->fx_line
= fragp
->fr_line
;
13399 md_number_to_chars ((char *)buf
, insn
, 4);
13406 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13407 _("relaxed out-of-range branch into a jump"));
13409 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13412 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13414 /* Reverse the branch. */
13415 switch ((insn
>> 28) & 0xf)
13418 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13419 have the condition reversed by tweaking a single
13420 bit, and their opcodes all have 0x4???????. */
13421 assert ((insn
& 0xf1000000) == 0x41000000);
13422 insn
^= 0x00010000;
13426 /* bltz 0x04000000 bgez 0x04010000
13427 bltzal 0x04100000 bgezal 0x04110000 */
13428 assert ((insn
& 0xfc0e0000) == 0x04000000);
13429 insn
^= 0x00010000;
13433 /* beq 0x10000000 bne 0x14000000
13434 blez 0x18000000 bgtz 0x1c000000 */
13435 insn
^= 0x04000000;
13443 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13445 /* Clear the and-link bit. */
13446 assert ((insn
& 0xfc1c0000) == 0x04100000);
13448 /* bltzal 0x04100000 bgezal 0x04110000
13449 bltzall 0x04120000 bgezall 0x04130000 */
13450 insn
&= ~0x00100000;
13453 /* Branch over the branch (if the branch was likely) or the
13454 full jump (not likely case). Compute the offset from the
13455 current instruction to branch to. */
13456 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13460 /* How many bytes in instructions we've already emitted? */
13461 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13462 /* How many bytes in instructions from here to the end? */
13463 i
= fragp
->fr_var
- i
;
13465 /* Convert to instruction count. */
13467 /* Branch counts from the next instruction. */
13470 /* Branch over the jump. */
13471 md_number_to_chars ((char *)buf
, insn
, 4);
13475 md_number_to_chars ((char*)buf
, 0, 4);
13478 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13480 /* beql $0, $0, 2f */
13482 /* Compute the PC offset from the current instruction to
13483 the end of the variable frag. */
13484 /* How many bytes in instructions we've already emitted? */
13485 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13486 /* How many bytes in instructions from here to the end? */
13487 i
= fragp
->fr_var
- i
;
13488 /* Convert to instruction count. */
13490 /* Don't decrement i, because we want to branch over the
13494 md_number_to_chars ((char *)buf
, insn
, 4);
13497 md_number_to_chars ((char *)buf
, 0, 4);
13502 if (mips_pic
== NO_PIC
)
13505 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13506 ? 0x0c000000 : 0x08000000);
13507 exp
.X_op
= O_symbol
;
13508 exp
.X_add_symbol
= fragp
->fr_symbol
;
13509 exp
.X_add_number
= fragp
->fr_offset
;
13511 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13512 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13513 fixp
->fx_file
= fragp
->fr_file
;
13514 fixp
->fx_line
= fragp
->fr_line
;
13516 md_number_to_chars ((char*)buf
, insn
, 4);
13521 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13522 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13523 exp
.X_op
= O_symbol
;
13524 exp
.X_add_symbol
= fragp
->fr_symbol
;
13525 exp
.X_add_number
= fragp
->fr_offset
;
13527 if (fragp
->fr_offset
)
13529 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13530 exp
.X_add_number
= 0;
13533 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13534 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13535 fixp
->fx_file
= fragp
->fr_file
;
13536 fixp
->fx_line
= fragp
->fr_line
;
13538 md_number_to_chars ((char*)buf
, insn
, 4);
13541 if (mips_opts
.isa
== ISA_MIPS1
)
13544 md_number_to_chars ((char*)buf
, 0, 4);
13548 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13549 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13551 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13552 4, &exp
, 0, BFD_RELOC_LO16
);
13553 fixp
->fx_file
= fragp
->fr_file
;
13554 fixp
->fx_line
= fragp
->fr_line
;
13556 md_number_to_chars ((char*)buf
, insn
, 4);
13560 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13565 md_number_to_chars ((char*)buf
, insn
, 4);
13570 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13571 + fragp
->fr_fix
+ fragp
->fr_var
);
13573 fragp
->fr_fix
+= fragp
->fr_var
;
13578 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13581 register const struct mips16_immed_operand
*op
;
13582 boolean small
, ext
;
13585 unsigned long insn
;
13586 boolean use_extend
;
13587 unsigned short extend
;
13589 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13590 op
= mips16_immed_operands
;
13591 while (op
->type
!= type
)
13594 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13605 resolve_symbol_value (fragp
->fr_symbol
);
13606 val
= S_GET_VALUE (fragp
->fr_symbol
);
13611 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13613 /* The rules for the base address of a PC relative reloc are
13614 complicated; see mips16_extended_frag. */
13615 if (type
== 'p' || type
== 'q')
13620 /* Ignore the low bit in the target, since it will be
13621 set for a text label. */
13622 if ((val
& 1) != 0)
13625 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13627 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13630 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13633 /* Make sure the section winds up with the alignment we have
13636 record_alignment (asec
, op
->shift
);
13640 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13641 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13642 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13643 _("extended instruction in delay slot"));
13645 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13647 if (target_big_endian
)
13648 insn
= bfd_getb16 (buf
);
13650 insn
= bfd_getl16 (buf
);
13652 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13653 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13654 small
, ext
, &insn
, &use_extend
, &extend
);
13658 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13659 fragp
->fr_fix
+= 2;
13663 md_number_to_chars ((char *) buf
, insn
, 2);
13664 fragp
->fr_fix
+= 2;
13669 if (fragp
->fr_opcode
== NULL
)
13672 old
= RELAX_OLD (fragp
->fr_subtype
);
13673 new = RELAX_NEW (fragp
->fr_subtype
);
13674 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
13677 memcpy (fixptr
- old
, fixptr
, new);
13679 fragp
->fr_fix
+= new - old
;
13685 /* This function is called after the relocs have been generated.
13686 We've been storing mips16 text labels as odd. Here we convert them
13687 back to even for the convenience of the debugger. */
13690 mips_frob_file_after_relocs ()
13693 unsigned int count
, i
;
13695 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13698 syms
= bfd_get_outsymbols (stdoutput
);
13699 count
= bfd_get_symcount (stdoutput
);
13700 for (i
= 0; i
< count
; i
++, syms
++)
13702 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13703 && ((*syms
)->value
& 1) != 0)
13705 (*syms
)->value
&= ~1;
13706 /* If the symbol has an odd size, it was probably computed
13707 incorrectly, so adjust that as well. */
13708 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13709 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13716 /* This function is called whenever a label is defined. It is used
13717 when handling branch delays; if a branch has a label, we assume we
13718 can not move it. */
13721 mips_define_label (sym
)
13724 struct insn_label_list
*l
;
13726 if (free_insn_labels
== NULL
)
13727 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13730 l
= free_insn_labels
;
13731 free_insn_labels
= l
->next
;
13735 l
->next
= insn_labels
;
13739 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13741 /* Some special processing for a MIPS ELF file. */
13744 mips_elf_final_processing ()
13746 /* Write out the register information. */
13747 if (mips_abi
!= N64_ABI
)
13751 s
.ri_gprmask
= mips_gprmask
;
13752 s
.ri_cprmask
[0] = mips_cprmask
[0];
13753 s
.ri_cprmask
[1] = mips_cprmask
[1];
13754 s
.ri_cprmask
[2] = mips_cprmask
[2];
13755 s
.ri_cprmask
[3] = mips_cprmask
[3];
13756 /* The gp_value field is set by the MIPS ELF backend. */
13758 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13759 ((Elf32_External_RegInfo
*)
13760 mips_regmask_frag
));
13764 Elf64_Internal_RegInfo s
;
13766 s
.ri_gprmask
= mips_gprmask
;
13768 s
.ri_cprmask
[0] = mips_cprmask
[0];
13769 s
.ri_cprmask
[1] = mips_cprmask
[1];
13770 s
.ri_cprmask
[2] = mips_cprmask
[2];
13771 s
.ri_cprmask
[3] = mips_cprmask
[3];
13772 /* The gp_value field is set by the MIPS ELF backend. */
13774 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13775 ((Elf64_External_RegInfo
*)
13776 mips_regmask_frag
));
13779 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13780 sort of BFD interface for this. */
13781 if (mips_any_noreorder
)
13782 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13783 if (mips_pic
!= NO_PIC
)
13784 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13786 /* Set MIPS ELF flags for ASEs. */
13787 if (file_ase_mips16
)
13788 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13789 #if 0 /* XXX FIXME */
13790 if (file_ase_mips3d
)
13791 elf_elfheader (stdoutput
)->e_flags
|= ???;
13794 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13796 /* Set the MIPS ELF ABI flags. */
13797 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13798 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13799 else if (mips_abi
== O64_ABI
)
13800 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13801 else if (mips_abi
== EABI_ABI
)
13803 if (!file_mips_gp32
)
13804 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13806 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13808 else if (mips_abi
== N32_ABI
)
13809 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13811 /* Nothing to do for N64_ABI. */
13813 if (mips_32bitmode
)
13814 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13817 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13819 typedef struct proc
{
13821 unsigned long reg_mask
;
13822 unsigned long reg_offset
;
13823 unsigned long fpreg_mask
;
13824 unsigned long fpreg_offset
;
13825 unsigned long frame_offset
;
13826 unsigned long frame_reg
;
13827 unsigned long pc_reg
;
13830 static procS cur_proc
;
13831 static procS
*cur_proc_ptr
;
13832 static int numprocs
;
13834 /* Fill in an rs_align_code fragment. */
13837 mips_handle_align (fragp
)
13840 if (fragp
->fr_type
!= rs_align_code
)
13843 if (mips_opts
.mips16
)
13845 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13846 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13851 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13852 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13860 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13864 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13875 /* check for premature end, nesting errors, etc */
13877 as_warn (_("missing .end at end of assembly"));
13886 if (*input_line_pointer
== '-')
13888 ++input_line_pointer
;
13891 if (!ISDIGIT (*input_line_pointer
))
13892 as_bad (_("expected simple number"));
13893 if (input_line_pointer
[0] == '0')
13895 if (input_line_pointer
[1] == 'x')
13897 input_line_pointer
+= 2;
13898 while (ISXDIGIT (*input_line_pointer
))
13901 val
|= hex_value (*input_line_pointer
++);
13903 return negative
? -val
: val
;
13907 ++input_line_pointer
;
13908 while (ISDIGIT (*input_line_pointer
))
13911 val
|= *input_line_pointer
++ - '0';
13913 return negative
? -val
: val
;
13916 if (!ISDIGIT (*input_line_pointer
))
13918 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13919 *input_line_pointer
, *input_line_pointer
);
13920 as_warn (_("invalid number"));
13923 while (ISDIGIT (*input_line_pointer
))
13926 val
+= *input_line_pointer
++ - '0';
13928 return negative
? -val
: val
;
13931 /* The .file directive; just like the usual .file directive, but there
13932 is an initial number which is the ECOFF file index. In the non-ECOFF
13933 case .file implies DWARF-2. */
13937 int x ATTRIBUTE_UNUSED
;
13939 static int first_file_directive
= 0;
13941 if (ECOFF_DEBUGGING
)
13950 filename
= dwarf2_directive_file (0);
13952 /* Versions of GCC up to 3.1 start files with a ".file"
13953 directive even for stabs output. Make sure that this
13954 ".file" is handled. Note that you need a version of GCC
13955 after 3.1 in order to support DWARF-2 on MIPS. */
13956 if (filename
!= NULL
&& ! first_file_directive
)
13958 (void) new_logical_line (filename
, -1);
13959 s_app_file_string (filename
);
13961 first_file_directive
= 1;
13965 /* The .loc directive, implying DWARF-2. */
13969 int x ATTRIBUTE_UNUSED
;
13971 if (!ECOFF_DEBUGGING
)
13972 dwarf2_directive_loc (0);
13975 /* The .end directive. */
13979 int x ATTRIBUTE_UNUSED
;
13984 /* Following functions need their own .frame and .cprestore directives. */
13985 mips_frame_reg_valid
= 0;
13986 mips_cprestore_valid
= 0;
13988 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13991 demand_empty_rest_of_line ();
13996 #ifdef BFD_ASSEMBLER
13997 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14002 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
14009 as_warn (_(".end not in text section"));
14013 as_warn (_(".end directive without a preceding .ent directive."));
14014 demand_empty_rest_of_line ();
14020 assert (S_GET_NAME (p
));
14021 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
14022 as_warn (_(".end symbol does not match .ent symbol."));
14024 if (debug_type
== DEBUG_STABS
)
14025 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14029 as_warn (_(".end directive missing or unknown symbol"));
14032 /* Generate a .pdr section. */
14033 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14035 segT saved_seg
= now_seg
;
14036 subsegT saved_subseg
= now_subseg
;
14041 dot
= frag_now_fix ();
14043 #ifdef md_flush_pending_output
14044 md_flush_pending_output ();
14048 subseg_set (pdr_seg
, 0);
14050 /* Write the symbol. */
14051 exp
.X_op
= O_symbol
;
14052 exp
.X_add_symbol
= p
;
14053 exp
.X_add_number
= 0;
14054 emit_expr (&exp
, 4);
14056 fragp
= frag_more (7 * 4);
14058 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
14059 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
14060 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
14061 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
14062 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
14063 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
14064 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
14066 subseg_set (saved_seg
, saved_subseg
);
14068 #endif /* OBJ_ELF */
14070 cur_proc_ptr
= NULL
;
14073 /* The .aent and .ent directives. */
14082 symbolP
= get_symbol ();
14083 if (*input_line_pointer
== ',')
14084 ++input_line_pointer
;
14085 SKIP_WHITESPACE ();
14086 if (ISDIGIT (*input_line_pointer
)
14087 || *input_line_pointer
== '-')
14090 #ifdef BFD_ASSEMBLER
14091 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14096 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
14103 as_warn (_(".ent or .aent not in text section."));
14105 if (!aent
&& cur_proc_ptr
)
14106 as_warn (_("missing .end"));
14110 /* This function needs its own .frame and .cprestore directives. */
14111 mips_frame_reg_valid
= 0;
14112 mips_cprestore_valid
= 0;
14114 cur_proc_ptr
= &cur_proc
;
14115 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14117 cur_proc_ptr
->isym
= symbolP
;
14119 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14123 if (debug_type
== DEBUG_STABS
)
14124 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14125 S_GET_NAME (symbolP
));
14128 demand_empty_rest_of_line ();
14131 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14132 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14133 s_mips_frame is used so that we can set the PDR information correctly.
14134 We can't use the ecoff routines because they make reference to the ecoff
14135 symbol table (in the mdebug section). */
14138 s_mips_frame (ignore
)
14139 int ignore ATTRIBUTE_UNUSED
;
14142 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14146 if (cur_proc_ptr
== (procS
*) NULL
)
14148 as_warn (_(".frame outside of .ent"));
14149 demand_empty_rest_of_line ();
14153 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14155 SKIP_WHITESPACE ();
14156 if (*input_line_pointer
++ != ','
14157 || get_absolute_expression_and_terminator (&val
) != ',')
14159 as_warn (_("Bad .frame directive"));
14160 --input_line_pointer
;
14161 demand_empty_rest_of_line ();
14165 cur_proc_ptr
->frame_offset
= val
;
14166 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14168 demand_empty_rest_of_line ();
14171 #endif /* OBJ_ELF */
14175 /* The .fmask and .mask directives. If the mdebug section is present
14176 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14177 embedded targets, s_mips_mask is used so that we can set the PDR
14178 information correctly. We can't use the ecoff routines because they
14179 make reference to the ecoff symbol table (in the mdebug section). */
14182 s_mips_mask (reg_type
)
14186 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14190 if (cur_proc_ptr
== (procS
*) NULL
)
14192 as_warn (_(".mask/.fmask outside of .ent"));
14193 demand_empty_rest_of_line ();
14197 if (get_absolute_expression_and_terminator (&mask
) != ',')
14199 as_warn (_("Bad .mask/.fmask directive"));
14200 --input_line_pointer
;
14201 demand_empty_rest_of_line ();
14205 off
= get_absolute_expression ();
14207 if (reg_type
== 'F')
14209 cur_proc_ptr
->fpreg_mask
= mask
;
14210 cur_proc_ptr
->fpreg_offset
= off
;
14214 cur_proc_ptr
->reg_mask
= mask
;
14215 cur_proc_ptr
->reg_offset
= off
;
14218 demand_empty_rest_of_line ();
14221 #endif /* OBJ_ELF */
14222 s_ignore (reg_type
);
14225 /* The .loc directive. */
14236 assert (now_seg
== text_section
);
14238 lineno
= get_number ();
14239 addroff
= frag_now_fix ();
14241 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14242 S_SET_TYPE (symbolP
, N_SLINE
);
14243 S_SET_OTHER (symbolP
, 0);
14244 S_SET_DESC (symbolP
, lineno
);
14245 symbolP
->sy_segment
= now_seg
;
14249 /* A table describing all the processors gas knows about. Names are
14250 matched in the order listed.
14252 To ease comparison, please keep this table in the same order as
14253 gcc's mips_cpu_info_table[]. */
14254 static const struct mips_cpu_info mips_cpu_info_table
[] =
14256 /* Entries for generic ISAs */
14257 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14258 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14259 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14260 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14261 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14262 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14263 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14266 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14267 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14268 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14271 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14274 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14275 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14276 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14277 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14278 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14279 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14280 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14281 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14282 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14283 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14284 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14285 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14288 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14289 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14290 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14291 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14292 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14293 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14294 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14295 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14296 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14297 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14298 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14299 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
14302 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
14303 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14304 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14307 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14308 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14310 /* Broadcom SB-1 CPU core */
14311 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14318 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14319 with a final "000" replaced by "k". Ignore case.
14321 Note: this function is shared between GCC and GAS. */
14324 mips_strict_matching_cpu_name_p (canonical
, given
)
14325 const char *canonical
, *given
;
14327 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14328 given
++, canonical
++;
14330 return ((*given
== 0 && *canonical
== 0)
14331 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14335 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14336 CPU name. We've traditionally allowed a lot of variation here.
14338 Note: this function is shared between GCC and GAS. */
14341 mips_matching_cpu_name_p (canonical
, given
)
14342 const char *canonical
, *given
;
14344 /* First see if the name matches exactly, or with a final "000"
14345 turned into "k". */
14346 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14349 /* If not, try comparing based on numerical designation alone.
14350 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14351 if (TOLOWER (*given
) == 'r')
14353 if (!ISDIGIT (*given
))
14356 /* Skip over some well-known prefixes in the canonical name,
14357 hoping to find a number there too. */
14358 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14360 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14362 else if (TOLOWER (canonical
[0]) == 'r')
14365 return mips_strict_matching_cpu_name_p (canonical
, given
);
14369 /* Parse an option that takes the name of a processor as its argument.
14370 OPTION is the name of the option and CPU_STRING is the argument.
14371 Return the corresponding processor enumeration if the CPU_STRING is
14372 recognized, otherwise report an error and return null.
14374 A similar function exists in GCC. */
14376 static const struct mips_cpu_info
*
14377 mips_parse_cpu (option
, cpu_string
)
14378 const char *option
, *cpu_string
;
14380 const struct mips_cpu_info
*p
;
14382 /* 'from-abi' selects the most compatible architecture for the given
14383 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14384 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14385 version. Look first at the -mgp options, if given, otherwise base
14386 the choice on MIPS_DEFAULT_64BIT.
14388 Treat NO_ABI like the EABIs. One reason to do this is that the
14389 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14390 architecture. This code picks MIPS I for 'mips' and MIPS III for
14391 'mips64', just as we did in the days before 'from-abi'. */
14392 if (strcasecmp (cpu_string
, "from-abi") == 0)
14394 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14395 return mips_cpu_info_from_isa (ISA_MIPS1
);
14397 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14398 return mips_cpu_info_from_isa (ISA_MIPS3
);
14400 if (file_mips_gp32
>= 0)
14401 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14403 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14408 /* 'default' has traditionally been a no-op. Probably not very useful. */
14409 if (strcasecmp (cpu_string
, "default") == 0)
14412 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14413 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14416 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14420 /* Return the canonical processor information for ISA (a member of the
14421 ISA_MIPS* enumeration). */
14423 static const struct mips_cpu_info
*
14424 mips_cpu_info_from_isa (isa
)
14429 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14430 if (mips_cpu_info_table
[i
].is_isa
14431 && isa
== mips_cpu_info_table
[i
].isa
)
14432 return (&mips_cpu_info_table
[i
]);
14438 show (stream
, string
, col_p
, first_p
)
14440 const char *string
;
14446 fprintf (stream
, "%24s", "");
14451 fprintf (stream
, ", ");
14455 if (*col_p
+ strlen (string
) > 72)
14457 fprintf (stream
, "\n%24s", "");
14461 fprintf (stream
, "%s", string
);
14462 *col_p
+= strlen (string
);
14468 md_show_usage (stream
)
14474 fprintf (stream
, _("\
14476 -membedded-pic generate embedded position independent code\n\
14477 -EB generate big endian output\n\
14478 -EL generate little endian output\n\
14479 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14480 -G NUM allow referencing objects up to NUM bytes\n\
14481 implicitly with the gp register [default 8]\n"));
14482 fprintf (stream
, _("\
14483 -mips1 generate MIPS ISA I instructions\n\
14484 -mips2 generate MIPS ISA II instructions\n\
14485 -mips3 generate MIPS ISA III instructions\n\
14486 -mips4 generate MIPS ISA IV instructions\n\
14487 -mips5 generate MIPS ISA V instructions\n\
14488 -mips32 generate MIPS32 ISA instructions\n\
14489 -mips64 generate MIPS64 ISA instructions\n\
14490 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14494 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14495 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14496 show (stream
, "from-abi", &column
, &first
);
14497 fputc ('\n', stream
);
14499 fprintf (stream
, _("\
14500 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14501 -no-mCPU don't generate code specific to CPU.\n\
14502 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14506 show (stream
, "3900", &column
, &first
);
14507 show (stream
, "4010", &column
, &first
);
14508 show (stream
, "4100", &column
, &first
);
14509 show (stream
, "4650", &column
, &first
);
14510 fputc ('\n', stream
);
14512 fprintf (stream
, _("\
14513 -mips16 generate mips16 instructions\n\
14514 -no-mips16 do not generate mips16 instructions\n"));
14515 fprintf (stream
, _("\
14516 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14517 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14518 -O0 remove unneeded NOPs, do not swap branches\n\
14519 -O remove unneeded NOPs and swap branches\n\
14520 -n warn about NOPs generated from macros\n\
14521 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14522 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14523 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14525 fprintf (stream
, _("\
14526 -KPIC, -call_shared generate SVR4 position independent code\n\
14527 -non_shared do not generate position independent code\n\
14528 -xgot assume a 32 bit GOT\n\
14529 -mabi=ABI create ABI conformant object file for:\n"));
14533 show (stream
, "32", &column
, &first
);
14534 show (stream
, "o64", &column
, &first
);
14535 show (stream
, "n32", &column
, &first
);
14536 show (stream
, "64", &column
, &first
);
14537 show (stream
, "eabi", &column
, &first
);
14539 fputc ('\n', stream
);
14541 fprintf (stream
, _("\
14542 -32 create o32 ABI object file (default)\n\
14543 -n32 create n32 ABI object file\n\
14544 -64 create 64 ABI object file\n"));