1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF.
107 Note that the default is always 32 bit, even if "configured" for
108 64 bit [e.g. --target=mips64-elf]. */
111 /* The default target format to use. */
113 mips_target_format ()
115 switch (OUTPUT_FLAVOR
)
117 case bfd_target_aout_flavour
:
118 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
119 case bfd_target_ecoff_flavour
:
120 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
121 case bfd_target_coff_flavour
:
123 case bfd_target_elf_flavour
:
125 /* This is traditional mips */
126 return (target_big_endian
127 ? "elf32-tradbigmips" : "elf32-tradlittlemips");
129 return (target_big_endian
130 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
131 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
139 /* The name of the readonly data section. */
140 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
142 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
144 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
146 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
150 /* This is the set of options which may be modified by the .set
151 pseudo-op. We use a struct so that .set push and .set pop are more
154 struct mips_set_options
156 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
157 if it has not been initialized. Changed by `.set mipsN', and the
158 -mipsN command line option, and the default CPU. */
160 /* Whether we are assembling for the mips16 processor. 0 if we are
161 not, 1 if we are, and -1 if the value has not been initialized.
162 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
163 -nomips16 command line options, and the default CPU. */
165 /* Non-zero if we should not reorder instructions. Changed by `.set
166 reorder' and `.set noreorder'. */
168 /* Non-zero if we should not permit the $at ($1) register to be used
169 in instructions. Changed by `.set at' and `.set noat'. */
171 /* Non-zero if we should warn when a macro instruction expands into
172 more than one machine instruction. Changed by `.set nomacro' and
174 int warn_about_macros
;
175 /* Non-zero if we should not move instructions. Changed by `.set
176 move', `.set volatile', `.set nomove', and `.set novolatile'. */
178 /* Non-zero if we should not optimize branches by moving the target
179 of the branch into the delay slot. Actually, we don't perform
180 this optimization anyhow. Changed by `.set bopt' and `.set
183 /* Non-zero if we should not autoextend mips16 instructions.
184 Changed by `.set autoextend' and `.set noautoextend'. */
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa and mips16 fields to -1 to indicate that
190 they have not been initialized. */
192 static struct mips_set_options mips_opts
= { -1, -1, 0, 0, 0, 0, 0, 0 };
194 /* These variables are filled in with the masks of registers used.
195 The object format code reads them and puts them in the appropriate
197 unsigned long mips_gprmask
;
198 unsigned long mips_cprmask
[4];
200 /* MIPS ISA we are using for this output file. */
201 static int file_mips_isa
;
203 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
204 static int mips_cpu
= -1;
206 /* The argument of the -mabi= flag. */
207 static char* mips_abi_string
= 0;
209 /* Wether we should mark the file EABI64 or EABI32. */
210 static int mips_eabi64
= 0;
212 /* If they asked for mips1 or mips2 and a cpu that is
213 mips3 or greater, then mark the object file 32BITMODE. */
214 static int mips_32bitmode
= 0;
216 /* True if -mgp32 was passed. */
217 static int mips_gp32
= 0;
219 /* Some ISA's have delay slots for instructions which read or write
220 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
221 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
222 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
223 delay slot in this ISA. The uses of this macro assume that any
224 ISA that has delay slots for one of these, has them for all. They
225 also assume that ISAs which don't have delays for these insns, don't
226 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
227 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
233 /* Return true if ISA supports 64 bit gp register instructions. */
234 #define ISA_HAS_64BIT_REGS(ISA) ( \
239 /* Whether the processor uses hardware interlocks to protect
240 reads from the HI and LO registers, and thus does not
241 require nops to be inserted.
243 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
244 -mcpu=FOO schedules for FOO, but still produces code that meets the
245 requirements of MIPS ISA I. For example, it won't generate any
246 FOO-specific instructions, and it will still assume that any
247 scheduling hazards described in MIPS ISA I are there, even if FOO
248 has interlocks. -mFOO gives GCC permission to generate code that
249 will only run on a FOO; it will generate FOO-specific instructions,
250 and assume interlocks provided by a FOO.
252 However, GAS currently doesn't make this distinction; before Jan 28
253 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
254 assumptions. The GCC driver passes these flags through to GAS, so
255 if GAS actually does anything that doesn't meet MIPS ISA I with
256 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
258 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
259 which seems senseless --- why generate code which will only run on
260 a FOO, but schedule for something else?
262 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
264 -- Jim Blandy <jimb@cygnus.com> */
266 #define hilo_interlocks (mips_cpu == 4010 \
269 /* Whether the processor uses hardware interlocks to protect reads
270 from the GPRs, and thus does not require nops to be inserted. */
271 #define gpr_interlocks \
272 (mips_opts.isa != 1 \
275 /* As with other "interlocks" this is used by hardware that has FP
276 (co-processor) interlocks. */
277 /* Itbl support may require additional care here. */
278 #define cop_interlocks (mips_cpu == 4300 \
281 /* Is this a mfhi or mflo instruction? */
282 #define MF_HILO_INSN(PINFO) \
283 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
285 /* MIPS PIC level. */
289 /* Do not generate PIC code. */
292 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
293 not sure what it is supposed to do. */
296 /* Generate PIC code as in the SVR4 MIPS ABI. */
299 /* Generate PIC code without using a global offset table: the data
300 segment has a maximum size of 64K, all data references are off
301 the $gp register, and all text references are PC relative. This
302 is used on some embedded systems. */
306 static enum mips_pic_level mips_pic
;
308 /* 1 if we should generate 32 bit offsets from the GP register in
309 SVR4_PIC mode. Currently has no meaning in other modes. */
310 static int mips_big_got
;
312 /* 1 if trap instructions should used for overflow rather than break
314 static int mips_trap
;
316 /* 1 if double width floating point constants should not be constructed
317 by a assembling two single width halves into two single width floating
318 point registers which just happen to alias the double width destination
319 register. On some architectures this aliasing can be disabled by a bit
320 in the status register, and the setting of this bit cannot be determined
321 automatically at assemble time. */
322 static int mips_disable_float_construction
;
324 /* Non-zero if any .set noreorder directives were used. */
326 static int mips_any_noreorder
;
328 /* Non-zero if nops should be inserted when the register referenced in
329 an mfhi/mflo instruction is read in the next two instructions. */
330 static int mips_7000_hilo_fix
;
332 /* The size of the small data section. */
333 static int g_switch_value
= 8;
334 /* Whether the -G option was used. */
335 static int g_switch_seen
= 0;
340 /* If we can determine in advance that GP optimization won't be
341 possible, we can skip the relaxation stuff that tries to produce
342 GP-relative references. This makes delay slot optimization work
345 This function can only provide a guess, but it seems to work for
346 gcc output. It needs to guess right for gcc, otherwise gcc
347 will put what it thinks is a GP-relative instruction in a branch
350 I don't know if a fix is needed for the SVR4_PIC mode. I've only
351 fixed it for the non-PIC mode. KR 95/04/07 */
352 static int nopic_need_relax
PARAMS ((symbolS
*, int));
354 /* handle of the OPCODE hash table */
355 static struct hash_control
*op_hash
= NULL
;
357 /* The opcode hash table we use for the mips16. */
358 static struct hash_control
*mips16_op_hash
= NULL
;
360 /* This array holds the chars that always start a comment. If the
361 pre-processor is disabled, these aren't very useful */
362 const char comment_chars
[] = "#";
364 /* This array holds the chars that only start a comment at the beginning of
365 a line. If the line seems to have the form '# 123 filename'
366 .line and .file directives will appear in the pre-processed output */
367 /* Note that input_file.c hand checks for '#' at the beginning of the
368 first line of the input file. This is because the compiler outputs
369 #NO_APP at the beginning of its output. */
370 /* Also note that C style comments are always supported. */
371 const char line_comment_chars
[] = "#";
373 /* This array holds machine specific line separator characters. */
374 const char line_separator_chars
[] = ";";
376 /* Chars that can be used to separate mant from exp in floating point nums */
377 const char EXP_CHARS
[] = "eE";
379 /* Chars that mean this number is a floating point constant */
382 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
384 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
385 changed in read.c . Ideally it shouldn't have to know about it at all,
386 but nothing is ideal around here.
389 static char *insn_error
;
391 static int auto_align
= 1;
393 /* When outputting SVR4 PIC code, the assembler needs to know the
394 offset in the stack frame from which to restore the $gp register.
395 This is set by the .cprestore pseudo-op, and saved in this
397 static offsetT mips_cprestore_offset
= -1;
399 /* This is the register which holds the stack frame, as set by the
400 .frame pseudo-op. This is needed to implement .cprestore. */
401 static int mips_frame_reg
= SP
;
403 /* To output NOP instructions correctly, we need to keep information
404 about the previous two instructions. */
406 /* Whether we are optimizing. The default value of 2 means to remove
407 unneeded NOPs and swap branch instructions when possible. A value
408 of 1 means to not swap branches. A value of 0 means to always
410 static int mips_optimize
= 2;
412 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
413 equivalent to seeing no -g option at all. */
414 static int mips_debug
= 0;
416 /* The previous instruction. */
417 static struct mips_cl_insn prev_insn
;
419 /* The instruction before prev_insn. */
420 static struct mips_cl_insn prev_prev_insn
;
422 /* If we don't want information for prev_insn or prev_prev_insn, we
423 point the insn_mo field at this dummy integer. */
424 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
426 /* Non-zero if prev_insn is valid. */
427 static int prev_insn_valid
;
429 /* The frag for the previous instruction. */
430 static struct frag
*prev_insn_frag
;
432 /* The offset into prev_insn_frag for the previous instruction. */
433 static long prev_insn_where
;
435 /* The reloc type for the previous instruction, if any. */
436 static bfd_reloc_code_real_type prev_insn_reloc_type
;
438 /* The reloc for the previous instruction, if any. */
439 static fixS
*prev_insn_fixp
;
441 /* Non-zero if the previous instruction was in a delay slot. */
442 static int prev_insn_is_delay_slot
;
444 /* Non-zero if the previous instruction was in a .set noreorder. */
445 static int prev_insn_unreordered
;
447 /* Non-zero if the previous instruction uses an extend opcode (if
449 static int prev_insn_extended
;
451 /* Non-zero if the previous previous instruction was in a .set
453 static int prev_prev_insn_unreordered
;
455 /* If this is set, it points to a frag holding nop instructions which
456 were inserted before the start of a noreorder section. If those
457 nops turn out to be unnecessary, the size of the frag can be
459 static fragS
*prev_nop_frag
;
461 /* The number of nop instructions we created in prev_nop_frag. */
462 static int prev_nop_frag_holds
;
464 /* The number of nop instructions that we know we need in
466 static int prev_nop_frag_required
;
468 /* The number of instructions we've seen since prev_nop_frag. */
469 static int prev_nop_frag_since
;
471 /* For ECOFF and ELF, relocations against symbols are done in two
472 parts, with a HI relocation and a LO relocation. Each relocation
473 has only 16 bits of space to store an addend. This means that in
474 order for the linker to handle carries correctly, it must be able
475 to locate both the HI and the LO relocation. This means that the
476 relocations must appear in order in the relocation table.
478 In order to implement this, we keep track of each unmatched HI
479 relocation. We then sort them so that they immediately precede the
480 corresponding LO relocation. */
485 struct mips_hi_fixup
*next
;
488 /* The section this fixup is in. */
492 /* The list of unmatched HI relocs. */
494 static struct mips_hi_fixup
*mips_hi_fixup_list
;
496 /* Map normal MIPS register numbers to mips16 register numbers. */
498 #define X ILLEGAL_REG
499 static const int mips32_to_16_reg_map
[] =
501 X
, X
, 2, 3, 4, 5, 6, 7,
502 X
, X
, X
, X
, X
, X
, X
, X
,
503 0, 1, X
, X
, X
, X
, X
, X
,
504 X
, X
, X
, X
, X
, X
, X
, X
508 /* Map mips16 register numbers to normal MIPS register numbers. */
510 static const int mips16_to_32_reg_map
[] =
512 16, 17, 2, 3, 4, 5, 6, 7
515 /* Since the MIPS does not have multiple forms of PC relative
516 instructions, we do not have to do relaxing as is done on other
517 platforms. However, we do have to handle GP relative addressing
518 correctly, which turns out to be a similar problem.
520 Every macro that refers to a symbol can occur in (at least) two
521 forms, one with GP relative addressing and one without. For
522 example, loading a global variable into a register generally uses
523 a macro instruction like this:
525 If i can be addressed off the GP register (this is true if it is in
526 the .sbss or .sdata section, or if it is known to be smaller than
527 the -G argument) this will generate the following instruction:
529 This instruction will use a GPREL reloc. If i can not be addressed
530 off the GP register, the following instruction sequence will be used:
533 In this case the first instruction will have a HI16 reloc, and the
534 second reloc will have a LO16 reloc. Both relocs will be against
537 The issue here is that we may not know whether i is GP addressable
538 until after we see the instruction that uses it. Therefore, we
539 want to be able to choose the final instruction sequence only at
540 the end of the assembly. This is similar to the way other
541 platforms choose the size of a PC relative instruction only at the
544 When generating position independent code we do not use GP
545 addressing in quite the same way, but the issue still arises as
546 external symbols and local symbols must be handled differently.
548 We handle these issues by actually generating both possible
549 instruction sequences. The longer one is put in a frag_var with
550 type rs_machine_dependent. We encode what to do with the frag in
551 the subtype field. We encode (1) the number of existing bytes to
552 replace, (2) the number of new bytes to use, (3) the offset from
553 the start of the existing bytes to the first reloc we must generate
554 (that is, the offset is applied from the start of the existing
555 bytes after they are replaced by the new bytes, if any), (4) the
556 offset from the start of the existing bytes to the second reloc,
557 (5) whether a third reloc is needed (the third reloc is always four
558 bytes after the second reloc), and (6) whether to warn if this
559 variant is used (this is sometimes needed if .set nomacro or .set
560 noat is in effect). All these numbers are reasonably small.
562 Generating two instruction sequences must be handled carefully to
563 ensure that delay slots are handled correctly. Fortunately, there
564 are a limited number of cases. When the second instruction
565 sequence is generated, append_insn is directed to maintain the
566 existing delay slot information, so it continues to apply to any
567 code after the second instruction sequence. This means that the
568 second instruction sequence must not impose any requirements not
569 required by the first instruction sequence.
571 These variant frags are then handled in functions called by the
572 machine independent code. md_estimate_size_before_relax returns
573 the final size of the frag. md_convert_frag sets up the final form
574 of the frag. tc_gen_reloc adjust the first reloc and adds a second
576 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
580 | (((reloc1) + 64) << 9) \
581 | (((reloc2) + 64) << 2) \
582 | ((reloc3) ? (1 << 1) : 0) \
584 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
585 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
586 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
587 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
588 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
589 #define RELAX_WARN(i) ((i) & 1)
591 /* For mips16 code, we use an entirely different form of relaxation.
592 mips16 supports two versions of most instructions which take
593 immediate values: a small one which takes some small value, and a
594 larger one which takes a 16 bit value. Since branches also follow
595 this pattern, relaxing these values is required.
597 We can assemble both mips16 and normal MIPS code in a single
598 object. Therefore, we need to support this type of relaxation at
599 the same time that we support the relaxation described above. We
600 use the high bit of the subtype field to distinguish these cases.
602 The information we store for this type of relaxation is the
603 argument code found in the opcode file for this relocation, whether
604 the user explicitly requested a small or extended form, and whether
605 the relocation is in a jump or jal delay slot. That tells us the
606 size of the value, and how it should be stored. We also store
607 whether the fragment is considered to be extended or not. We also
608 store whether this is known to be a branch to a different section,
609 whether we have tried to relax this frag yet, and whether we have
610 ever extended a PC relative fragment because of a shift count. */
611 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
614 | ((small) ? 0x100 : 0) \
615 | ((ext) ? 0x200 : 0) \
616 | ((dslot) ? 0x400 : 0) \
617 | ((jal_dslot) ? 0x800 : 0))
618 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
619 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
620 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
621 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
622 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
623 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
624 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
625 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
626 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
627 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
628 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
629 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
631 /* Prototypes for static functions. */
634 #define internalError() \
635 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
637 #define internalError() as_fatal (_("MIPS internal Error"));
640 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
642 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
643 unsigned int reg
, enum mips_regclass
class));
644 static int reg_needs_delay
PARAMS ((int));
645 static void mips16_mark_labels
PARAMS ((void));
646 static void append_insn
PARAMS ((char *place
,
647 struct mips_cl_insn
* ip
,
649 bfd_reloc_code_real_type r
,
651 static void mips_no_prev_insn
PARAMS ((int));
652 static void mips_emit_delays
PARAMS ((boolean
));
654 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
655 const char *name
, const char *fmt
,
658 static void macro_build ();
660 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
661 const char *, const char *,
663 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
664 expressionS
* ep
, int regnum
));
665 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
666 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
668 static void load_register
PARAMS ((int *, int, expressionS
*, int));
669 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
670 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
671 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
672 #ifdef LOSING_COMPILER
673 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
675 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
676 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
677 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
678 boolean
, boolean
, unsigned long *,
679 boolean
*, unsigned short *));
680 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
681 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
682 static symbolS
*get_symbol
PARAMS ((void));
683 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
684 static void s_align
PARAMS ((int));
685 static void s_change_sec
PARAMS ((int));
686 static void s_cons
PARAMS ((int));
687 static void s_float_cons
PARAMS ((int));
688 static void s_mips_globl
PARAMS ((int));
689 static void s_option
PARAMS ((int));
690 static void s_mipsset
PARAMS ((int));
691 static void s_abicalls
PARAMS ((int));
692 static void s_cpload
PARAMS ((int));
693 static void s_cprestore
PARAMS ((int));
694 static void s_gpword
PARAMS ((int));
695 static void s_cpadd
PARAMS ((int));
696 static void s_insn
PARAMS ((int));
697 static void md_obj_begin
PARAMS ((void));
698 static void md_obj_end
PARAMS ((void));
699 static long get_number
PARAMS ((void));
700 static void s_mips_ent
PARAMS ((int));
701 static void s_mips_end
PARAMS ((int));
702 static void s_mips_frame
PARAMS ((int));
703 static void s_mips_mask
PARAMS ((int));
704 static void s_mips_stab
PARAMS ((int));
705 static void s_mips_weakext
PARAMS ((int));
706 static void s_file
PARAMS ((int));
707 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
710 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
714 The following pseudo-ops from the Kane and Heinrich MIPS book
715 should be defined here, but are currently unsupported: .alias,
716 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
718 The following pseudo-ops from the Kane and Heinrich MIPS book are
719 specific to the type of debugging information being generated, and
720 should be defined by the object format: .aent, .begin, .bend,
721 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
724 The following pseudo-ops from the Kane and Heinrich MIPS book are
725 not MIPS CPU specific, but are also not specific to the object file
726 format. This file is probably the best place to define them, but
727 they are not currently supported: .asm0, .endr, .lab, .repeat,
730 static const pseudo_typeS mips_pseudo_table
[] =
732 /* MIPS specific pseudo-ops. */
733 {"option", s_option
, 0},
734 {"set", s_mipsset
, 0},
735 {"rdata", s_change_sec
, 'r'},
736 {"sdata", s_change_sec
, 's'},
737 {"livereg", s_ignore
, 0},
738 {"abicalls", s_abicalls
, 0},
739 {"cpload", s_cpload
, 0},
740 {"cprestore", s_cprestore
, 0},
741 {"gpword", s_gpword
, 0},
742 {"cpadd", s_cpadd
, 0},
745 /* Relatively generic pseudo-ops that happen to be used on MIPS
747 {"asciiz", stringer
, 1},
748 {"bss", s_change_sec
, 'b'},
751 {"dword", s_cons
, 3},
752 {"weakext", s_mips_weakext
, 0},
754 /* These pseudo-ops are defined in read.c, but must be overridden
755 here for one reason or another. */
756 {"align", s_align
, 0},
758 {"data", s_change_sec
, 'd'},
759 {"double", s_float_cons
, 'd'},
760 {"float", s_float_cons
, 'f'},
761 {"globl", s_mips_globl
, 0},
762 {"global", s_mips_globl
, 0},
763 {"hword", s_cons
, 1},
768 {"short", s_cons
, 1},
769 {"single", s_float_cons
, 'f'},
770 {"stabn", s_mips_stab
, 'n'},
771 {"text", s_change_sec
, 't'},
776 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
777 /* These pseudo-ops should be defined by the object file format.
778 However, a.out doesn't support them, so we have versions here. */
779 {"aent", s_mips_ent
, 1},
780 {"bgnb", s_ignore
, 0},
781 {"end", s_mips_end
, 0},
782 {"endb", s_ignore
, 0},
783 {"ent", s_mips_ent
, 0},
785 {"fmask", s_mips_mask
, 'F'},
786 {"frame", s_mips_frame
, 0},
787 {"loc", s_ignore
, 0},
788 {"mask", s_mips_mask
, 'R'},
789 {"verstamp", s_ignore
, 0},
793 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
798 pop_insert (mips_pseudo_table
);
799 if (! ECOFF_DEBUGGING
)
800 pop_insert (mips_nonecoff_pseudo_table
);
803 /* Symbols labelling the current insn. */
805 struct insn_label_list
807 struct insn_label_list
*next
;
811 static struct insn_label_list
*insn_labels
;
812 static struct insn_label_list
*free_insn_labels
;
814 static void mips_clear_insn_labels
PARAMS ((void));
817 mips_clear_insn_labels ()
819 register struct insn_label_list
**pl
;
821 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
827 static char *expr_end
;
829 /* Expressions which appear in instructions. These are set by
832 static expressionS imm_expr
;
833 static expressionS offset_expr
;
835 /* Relocs associated with imm_expr and offset_expr. */
837 static bfd_reloc_code_real_type imm_reloc
;
838 static bfd_reloc_code_real_type offset_reloc
;
840 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
842 static boolean imm_unmatched_hi
;
844 /* These are set by mips16_ip if an explicit extension is used. */
846 static boolean mips16_small
, mips16_ext
;
848 #ifdef MIPS_STABS_ELF
849 /* The pdr segment for per procedure frame/regmask info */
855 * This function is called once, at assembler startup time. It should
856 * set up all the tables, etc. that the MD part of the assembler will need.
862 register const char *retval
= NULL
;
863 register unsigned int i
= 0;
867 int mips_isa_from_cpu
;
869 /* GP relative stuff not working for PE */
870 if (strncmp (TARGET_OS
, "pe", 2) == 0
871 && g_switch_value
!= 0)
874 as_bad (_("-G not supported in this configuration."));
879 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
881 a
= xmalloc (sizeof TARGET_CPU
);
882 strcpy (a
, TARGET_CPU
);
883 a
[(sizeof TARGET_CPU
) - 3] = '\0';
889 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
890 just the generic 'mips', in which case set mips_cpu based
891 on the given ISA, if any. */
893 if (strcmp (cpu
, "mips") == 0)
895 if (mips_opts
.isa
< 0)
898 else if (mips_opts
.isa
== 2)
901 else if (mips_opts
.isa
== 3)
904 else if (mips_opts
.isa
== 4)
911 else if (strcmp (cpu
, "r3900") == 0
912 || strcmp (cpu
, "mipstx39") == 0
916 else if (strcmp (cpu
, "r6000") == 0
917 || strcmp (cpu
, "mips2") == 0)
920 else if (strcmp (cpu
, "mips64") == 0
921 || strcmp (cpu
, "r4000") == 0
922 || strcmp (cpu
, "mips3") == 0)
925 else if (strcmp (cpu
, "r4400") == 0)
928 else if (strcmp (cpu
, "mips64orion") == 0
929 || strcmp (cpu
, "r4600") == 0)
932 else if (strcmp (cpu
, "r4650") == 0)
935 else if (strcmp (cpu
, "mips64vr4300") == 0)
938 else if (strcmp (cpu
, "mips64vr4111") == 0)
941 else if (strcmp (cpu
, "mips64vr4100") == 0)
944 else if (strcmp (cpu
, "r4010") == 0)
948 else if (strcmp (cpu
, "r5000") == 0
949 || strcmp (cpu
, "mips64vr5000") == 0)
954 else if (strcmp (cpu
, "r8000") == 0
955 || strcmp (cpu
, "mips4") == 0)
958 else if (strcmp (cpu
, "r10000") == 0)
961 else if (strcmp (cpu
, "mips16") == 0)
962 mips_cpu
= 0; /* FIXME */
970 mips_isa_from_cpu
= 1;
972 else if (mips_cpu
== 6000
974 mips_isa_from_cpu
= 2;
976 else if (mips_cpu
== 4000
983 mips_isa_from_cpu
= 3;
985 else if (mips_cpu
== 5000
987 || mips_cpu
== 10000)
988 mips_isa_from_cpu
= 4;
991 mips_isa_from_cpu
= -1;
993 if (mips_opts
.isa
== -1)
995 if (mips_isa_from_cpu
!= -1)
996 mips_opts
.isa
= mips_isa_from_cpu
;
1001 if (mips_opts
.mips16
< 0)
1003 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
1004 mips_opts
.mips16
= 1;
1006 mips_opts
.mips16
= 0;
1009 /* End of TARGET_CPU processing, get rid of malloced memory
1018 if (mips_opts
.isa
== 1 && mips_trap
)
1019 as_bad (_("trap exception not supported at ISA 1"));
1021 /* Set the EABI kind based on the ISA before the user gets
1022 to change the ISA with directives. This isn't really
1023 the best, but then neither is basing the abi on the isa. */
1024 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1026 && 0 == strcmp (mips_abi_string
,"eabi"))
1029 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1031 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1033 /* If they asked for mips1 or mips2 and a cpu that is
1034 mips3 or greater, then mark the object file 32BITMODE. */
1035 if (mips_isa_from_cpu
!= -1
1036 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1037 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1042 switch (mips_opts
.isa
)
1045 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1048 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1051 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1054 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1060 as_warn (_("Could not set architecture and machine"));
1062 file_mips_isa
= mips_opts
.isa
;
1064 op_hash
= hash_new ();
1066 for (i
= 0; i
< NUMOPCODES
;)
1068 const char *name
= mips_opcodes
[i
].name
;
1070 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1073 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1074 mips_opcodes
[i
].name
, retval
);
1075 /* Probably a memory allocation problem? Give up now. */
1076 as_fatal (_("Broken assembler. No assembly attempted."));
1080 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1082 if (!validate_mips_insn (&mips_opcodes
[i
]))
1087 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1090 mips16_op_hash
= hash_new ();
1093 while (i
< bfd_mips16_num_opcodes
)
1095 const char *name
= mips16_opcodes
[i
].name
;
1097 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1099 as_fatal (_("internal: can't hash `%s': %s"),
1100 mips16_opcodes
[i
].name
, retval
);
1103 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1104 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1105 != mips16_opcodes
[i
].match
))
1107 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1108 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1113 while (i
< bfd_mips16_num_opcodes
1114 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1118 as_fatal (_("Broken assembler. No assembly attempted."));
1120 /* We add all the general register names to the symbol table. This
1121 helps us detect invalid uses of them. */
1122 for (i
= 0; i
< 32; i
++)
1126 sprintf (buf
, "$%d", i
);
1127 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1128 &zero_address_frag
));
1130 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1131 &zero_address_frag
));
1132 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1133 &zero_address_frag
));
1134 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1135 &zero_address_frag
));
1136 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1137 &zero_address_frag
));
1138 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1139 &zero_address_frag
));
1140 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1141 &zero_address_frag
));
1142 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1143 &zero_address_frag
));
1145 mips_no_prev_insn (false);
1148 mips_cprmask
[0] = 0;
1149 mips_cprmask
[1] = 0;
1150 mips_cprmask
[2] = 0;
1151 mips_cprmask
[3] = 0;
1153 /* set the default alignment for the text section (2**2) */
1154 record_alignment (text_section
, 2);
1156 if (USE_GLOBAL_POINTER_OPT
)
1157 bfd_set_gp_size (stdoutput
, g_switch_value
);
1159 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1161 /* On a native system, sections must be aligned to 16 byte
1162 boundaries. When configured for an embedded ELF target, we
1164 if (strcmp (TARGET_OS
, "elf") != 0)
1166 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1167 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1168 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1171 /* Create a .reginfo section for register masks and a .mdebug
1172 section for debugging information. */
1180 subseg
= now_subseg
;
1182 /* The ABI says this section should be loaded so that the
1183 running program can access it. However, we don't load it
1184 if we are configured for an embedded target */
1185 flags
= SEC_READONLY
| SEC_DATA
;
1186 if (strcmp (TARGET_OS
, "elf") != 0)
1187 flags
|= SEC_ALLOC
| SEC_LOAD
;
1191 sec
= subseg_new (".reginfo", (subsegT
) 0);
1194 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1195 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1198 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1203 /* The 64-bit ABI uses a .MIPS.options section rather than
1204 .reginfo section. */
1205 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1206 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1207 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1210 /* Set up the option header. */
1212 Elf_Internal_Options opthdr
;
1215 opthdr
.kind
= ODK_REGINFO
;
1216 opthdr
.size
= (sizeof (Elf_External_Options
)
1217 + sizeof (Elf64_External_RegInfo
));
1220 f
= frag_more (sizeof (Elf_External_Options
));
1221 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1222 (Elf_External_Options
*) f
);
1224 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1229 if (ECOFF_DEBUGGING
)
1231 sec
= subseg_new (".mdebug", (subsegT
) 0);
1232 (void) bfd_set_section_flags (stdoutput
, sec
,
1233 SEC_HAS_CONTENTS
| SEC_READONLY
);
1234 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1237 #ifdef MIPS_STABS_ELF
1238 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1239 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1240 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1241 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1244 subseg_set (seg
, subseg
);
1248 if (! ECOFF_DEBUGGING
)
1255 if (! ECOFF_DEBUGGING
)
1263 struct mips_cl_insn insn
;
1265 imm_expr
.X_op
= O_absent
;
1266 imm_reloc
= BFD_RELOC_UNUSED
;
1267 imm_unmatched_hi
= false;
1268 offset_expr
.X_op
= O_absent
;
1269 offset_reloc
= BFD_RELOC_UNUSED
;
1271 if (mips_opts
.mips16
)
1272 mips16_ip (str
, &insn
);
1275 mips_ip (str
, &insn
);
1276 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1277 str
, insn
.insn_opcode
));
1282 as_bad ("%s `%s'", insn_error
, str
);
1286 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1288 if (mips_opts
.mips16
)
1289 mips16_macro (&insn
);
1295 if (imm_expr
.X_op
!= O_absent
)
1296 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1298 else if (offset_expr
.X_op
!= O_absent
)
1299 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1301 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1305 /* See whether instruction IP reads register REG. CLASS is the type
1309 insn_uses_reg (ip
, reg
, class)
1310 struct mips_cl_insn
*ip
;
1312 enum mips_regclass
class;
1314 if (class == MIPS16_REG
)
1316 assert (mips_opts
.mips16
);
1317 reg
= mips16_to_32_reg_map
[reg
];
1318 class = MIPS_GR_REG
;
1321 /* Don't report on general register 0, since it never changes. */
1322 if (class == MIPS_GR_REG
&& reg
== 0)
1325 if (class == MIPS_FP_REG
)
1327 assert (! mips_opts
.mips16
);
1328 /* If we are called with either $f0 or $f1, we must check $f0.
1329 This is not optimal, because it will introduce an unnecessary
1330 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1331 need to distinguish reading both $f0 and $f1 or just one of
1332 them. Note that we don't have to check the other way,
1333 because there is no instruction that sets both $f0 and $f1
1334 and requires a delay. */
1335 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1336 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1337 == (reg
&~ (unsigned) 1)))
1339 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1340 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1341 == (reg
&~ (unsigned) 1)))
1344 else if (! mips_opts
.mips16
)
1346 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1347 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1349 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1350 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1355 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1356 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1357 & MIPS16OP_MASK_RX
)]
1360 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1361 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1362 & MIPS16OP_MASK_RY
)]
1365 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1366 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1367 & MIPS16OP_MASK_MOVE32Z
)]
1370 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1372 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1374 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1376 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1377 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1378 & MIPS16OP_MASK_REGR32
) == reg
)
1385 /* This function returns true if modifying a register requires a
1389 reg_needs_delay (reg
)
1392 unsigned long prev_pinfo
;
1394 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1395 if (! mips_opts
.noreorder
1396 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1397 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1398 || (! gpr_interlocks
1399 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1401 /* A load from a coprocessor or from memory. All load
1402 delays delay the use of general register rt for one
1403 instruction on the r3000. The r6000 and r4000 use
1405 /* Itbl support may require additional care here. */
1406 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1407 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1414 /* Mark instruction labels in mips16 mode. This permits the linker to
1415 handle them specially, such as generating jalx instructions when
1416 needed. We also make them odd for the duration of the assembly, in
1417 order to generate the right sort of code. We will make them even
1418 in the adjust_symtab routine, while leaving them marked. This is
1419 convenient for the debugger and the disassembler. The linker knows
1420 to make them odd again. */
1423 mips16_mark_labels ()
1425 if (mips_opts
.mips16
)
1427 struct insn_label_list
*l
;
1429 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1432 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1433 S_SET_OTHER (l
->label
, STO_MIPS16
);
1435 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1436 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1441 /* Output an instruction. PLACE is where to put the instruction; if
1442 it is NULL, this uses frag_more to get room. IP is the instruction
1443 information. ADDRESS_EXPR is an operand of the instruction to be
1444 used with RELOC_TYPE. */
1447 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1449 struct mips_cl_insn
*ip
;
1450 expressionS
*address_expr
;
1451 bfd_reloc_code_real_type reloc_type
;
1452 boolean unmatched_hi
;
1454 register unsigned long prev_pinfo
, pinfo
;
1459 /* Mark instruction labels in mips16 mode. */
1460 if (mips_opts
.mips16
)
1461 mips16_mark_labels ();
1463 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1464 pinfo
= ip
->insn_mo
->pinfo
;
1466 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1470 /* If the previous insn required any delay slots, see if we need
1471 to insert a NOP or two. There are eight kinds of possible
1472 hazards, of which an instruction can have at most one type.
1473 (1) a load from memory delay
1474 (2) a load from a coprocessor delay
1475 (3) an unconditional branch delay
1476 (4) a conditional branch delay
1477 (5) a move to coprocessor register delay
1478 (6) a load coprocessor register from memory delay
1479 (7) a coprocessor condition code delay
1480 (8) a HI/LO special register delay
1482 There are a lot of optimizations we could do that we don't.
1483 In particular, we do not, in general, reorder instructions.
1484 If you use gcc with optimization, it will reorder
1485 instructions and generally do much more optimization then we
1486 do here; repeating all that work in the assembler would only
1487 benefit hand written assembly code, and does not seem worth
1490 /* This is how a NOP is emitted. */
1491 #define emit_nop() \
1493 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1494 : md_number_to_chars (frag_more (4), 0, 4))
1496 /* The previous insn might require a delay slot, depending upon
1497 the contents of the current insn. */
1498 if (! mips_opts
.mips16
1499 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1500 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1501 && ! cop_interlocks
)
1502 || (! gpr_interlocks
1503 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1505 /* A load from a coprocessor or from memory. All load
1506 delays delay the use of general register rt for one
1507 instruction on the r3000. The r6000 and r4000 use
1509 /* Itbl support may require additional care here. */
1510 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1511 if (mips_optimize
== 0
1512 || insn_uses_reg (ip
,
1513 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1518 else if (! mips_opts
.mips16
1519 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1520 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1521 && ! cop_interlocks
)
1522 || (mips_opts
.isa
== 1
1523 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1525 /* A generic coprocessor delay. The previous instruction
1526 modified a coprocessor general or control register. If
1527 it modified a control register, we need to avoid any
1528 coprocessor instruction (this is probably not always
1529 required, but it sometimes is). If it modified a general
1530 register, we avoid using that register.
1532 On the r6000 and r4000 loading a coprocessor register
1533 from memory is interlocked, and does not require a delay.
1535 This case is not handled very well. There is no special
1536 knowledge of CP0 handling, and the coprocessors other
1537 than the floating point unit are not distinguished at
1539 /* Itbl support may require additional care here. FIXME!
1540 Need to modify this to include knowledge about
1541 user specified delays! */
1542 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1544 if (mips_optimize
== 0
1545 || insn_uses_reg (ip
,
1546 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1551 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1553 if (mips_optimize
== 0
1554 || insn_uses_reg (ip
,
1555 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1562 /* We don't know exactly what the previous instruction
1563 does. If the current instruction uses a coprocessor
1564 register, we must insert a NOP. If previous
1565 instruction may set the condition codes, and the
1566 current instruction uses them, we must insert two
1568 /* Itbl support may require additional care here. */
1569 if (mips_optimize
== 0
1570 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1571 && (pinfo
& INSN_READ_COND_CODE
)))
1573 else if (pinfo
& INSN_COP
)
1577 else if (! mips_opts
.mips16
1578 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1579 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1580 && ! cop_interlocks
)
1582 /* The previous instruction sets the coprocessor condition
1583 codes, but does not require a general coprocessor delay
1584 (this means it is a floating point comparison
1585 instruction). If this instruction uses the condition
1586 codes, we need to insert a single NOP. */
1587 /* Itbl support may require additional care here. */
1588 if (mips_optimize
== 0
1589 || (pinfo
& INSN_READ_COND_CODE
))
1593 /* If we're fixing up mfhi/mflo for the r7000 and the
1594 previous insn was an mfhi/mflo and the current insn
1595 reads the register that the mfhi/mflo wrote to, then
1598 else if (mips_7000_hilo_fix
1599 && MF_HILO_INSN (prev_pinfo
)
1600 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1608 /* If we're fixing up mfhi/mflo for the r7000 and the
1609 2nd previous insn was an mfhi/mflo and the current insn
1610 reads the register that the mfhi/mflo wrote to, then
1613 else if (mips_7000_hilo_fix
1614 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1615 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1623 else if (prev_pinfo
& INSN_READ_LO
)
1625 /* The previous instruction reads the LO register; if the
1626 current instruction writes to the LO register, we must
1627 insert two NOPS. Some newer processors have interlocks.
1628 Also the tx39's multiply instructions can be exectuted
1629 immediatly after a read from HI/LO (without the delay),
1630 though the tx39's divide insns still do require the
1632 if (! (hilo_interlocks
1633 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1634 && (mips_optimize
== 0
1635 || (pinfo
& INSN_WRITE_LO
)))
1637 /* Most mips16 branch insns don't have a delay slot.
1638 If a read from LO is immediately followed by a branch
1639 to a write to LO we have a read followed by a write
1640 less than 2 insns away. We assume the target of
1641 a branch might be a write to LO, and insert a nop
1642 between a read and an immediately following branch. */
1643 else if (mips_opts
.mips16
1644 && (mips_optimize
== 0
1645 || (pinfo
& MIPS16_INSN_BRANCH
)))
1648 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1650 /* The previous instruction reads the HI register; if the
1651 current instruction writes to the HI register, we must
1652 insert a NOP. Some newer processors have interlocks.
1653 Also the note tx39's multiply above. */
1654 if (! (hilo_interlocks
1655 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1656 && (mips_optimize
== 0
1657 || (pinfo
& INSN_WRITE_HI
)))
1659 /* Most mips16 branch insns don't have a delay slot.
1660 If a read from HI is immediately followed by a branch
1661 to a write to HI we have a read followed by a write
1662 less than 2 insns away. We assume the target of
1663 a branch might be a write to HI, and insert a nop
1664 between a read and an immediately following branch. */
1665 else if (mips_opts
.mips16
1666 && (mips_optimize
== 0
1667 || (pinfo
& MIPS16_INSN_BRANCH
)))
1671 /* If the previous instruction was in a noreorder section, then
1672 we don't want to insert the nop after all. */
1673 /* Itbl support may require additional care here. */
1674 if (prev_insn_unreordered
)
1677 /* There are two cases which require two intervening
1678 instructions: 1) setting the condition codes using a move to
1679 coprocessor instruction which requires a general coprocessor
1680 delay and then reading the condition codes 2) reading the HI
1681 or LO register and then writing to it (except on processors
1682 which have interlocks). If we are not already emitting a NOP
1683 instruction, we must check for these cases compared to the
1684 instruction previous to the previous instruction. */
1685 if ((! mips_opts
.mips16
1686 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1687 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1688 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1689 && (pinfo
& INSN_READ_COND_CODE
)
1690 && ! cop_interlocks
)
1691 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1692 && (pinfo
& INSN_WRITE_LO
)
1693 && ! (hilo_interlocks
1694 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
))))
1695 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1696 && (pinfo
& INSN_WRITE_HI
)
1697 && ! (hilo_interlocks
1698 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))))
1703 if (prev_prev_insn_unreordered
)
1706 if (prev_prev_nop
&& nops
== 0)
1709 /* If we are being given a nop instruction, don't bother with
1710 one of the nops we would otherwise output. This will only
1711 happen when a nop instruction is used with mips_optimize set
1714 && ! mips_opts
.noreorder
1715 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1718 /* Now emit the right number of NOP instructions. */
1719 if (nops
> 0 && ! mips_opts
.noreorder
)
1722 unsigned long old_frag_offset
;
1724 struct insn_label_list
*l
;
1726 old_frag
= frag_now
;
1727 old_frag_offset
= frag_now_fix ();
1729 for (i
= 0; i
< nops
; i
++)
1734 listing_prev_line ();
1735 /* We may be at the start of a variant frag. In case we
1736 are, make sure there is enough space for the frag
1737 after the frags created by listing_prev_line. The
1738 argument to frag_grow here must be at least as large
1739 as the argument to all other calls to frag_grow in
1740 this file. We don't have to worry about being in the
1741 middle of a variant frag, because the variants insert
1742 all needed nop instructions themselves. */
1746 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1748 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1749 symbol_set_frag (l
->label
, frag_now
);
1750 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1751 /* mips16 text labels are stored as odd. */
1752 if (mips_opts
.mips16
)
1753 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1756 #ifndef NO_ECOFF_DEBUGGING
1757 if (ECOFF_DEBUGGING
)
1758 ecoff_fix_loc (old_frag
, old_frag_offset
);
1761 else if (prev_nop_frag
!= NULL
)
1763 /* We have a frag holding nops we may be able to remove. If
1764 we don't need any nops, we can decrease the size of
1765 prev_nop_frag by the size of one instruction. If we do
1766 need some nops, we count them in prev_nops_required. */
1767 if (prev_nop_frag_since
== 0)
1771 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1772 --prev_nop_frag_holds
;
1775 prev_nop_frag_required
+= nops
;
1779 if (prev_prev_nop
== 0)
1781 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1782 --prev_nop_frag_holds
;
1785 ++prev_nop_frag_required
;
1788 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1789 prev_nop_frag
= NULL
;
1791 ++prev_nop_frag_since
;
1793 /* Sanity check: by the time we reach the second instruction
1794 after prev_nop_frag, we should have used up all the nops
1795 one way or another. */
1796 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1800 if (reloc_type
> BFD_RELOC_UNUSED
)
1802 /* We need to set up a variant frag. */
1803 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1804 f
= frag_var (rs_machine_dependent
, 4, 0,
1805 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1806 mips16_small
, mips16_ext
,
1808 & INSN_UNCOND_BRANCH_DELAY
),
1809 (prev_insn_reloc_type
1810 == BFD_RELOC_MIPS16_JMP
)),
1811 make_expr_symbol (address_expr
), (offsetT
) 0,
1814 else if (place
!= NULL
)
1816 else if (mips_opts
.mips16
1818 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1820 /* Make sure there is enough room to swap this instruction with
1821 a following jump instruction. */
1827 if (mips_opts
.mips16
1828 && mips_opts
.noreorder
1829 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1830 as_warn (_("extended instruction in delay slot"));
1836 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1838 if (address_expr
->X_op
== O_constant
)
1843 ip
->insn_opcode
|= address_expr
->X_add_number
;
1846 case BFD_RELOC_LO16
:
1847 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1850 case BFD_RELOC_MIPS_JMP
:
1851 if ((address_expr
->X_add_number
& 3) != 0)
1852 as_bad (_("jump to misaligned address (0x%lx)"),
1853 (unsigned long) address_expr
->X_add_number
);
1854 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1857 case BFD_RELOC_MIPS16_JMP
:
1858 if ((address_expr
->X_add_number
& 3) != 0)
1859 as_bad (_("jump to misaligned address (0x%lx)"),
1860 (unsigned long) address_expr
->X_add_number
);
1862 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1863 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1864 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1868 case BFD_RELOC_16_PCREL_S2
:
1878 /* Don't generate a reloc if we are writing into a variant
1882 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1884 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1888 struct mips_hi_fixup
*hi_fixup
;
1890 assert (reloc_type
== BFD_RELOC_HI16_S
);
1891 hi_fixup
= ((struct mips_hi_fixup
*)
1892 xmalloc (sizeof (struct mips_hi_fixup
)));
1893 hi_fixup
->fixp
= fixp
;
1894 hi_fixup
->seg
= now_seg
;
1895 hi_fixup
->next
= mips_hi_fixup_list
;
1896 mips_hi_fixup_list
= hi_fixup
;
1902 if (! mips_opts
.mips16
)
1903 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1904 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1906 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1907 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1913 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1916 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1919 /* Update the register mask information. */
1920 if (! mips_opts
.mips16
)
1922 if (pinfo
& INSN_WRITE_GPR_D
)
1923 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1924 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1925 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1926 if (pinfo
& INSN_READ_GPR_S
)
1927 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1928 if (pinfo
& INSN_WRITE_GPR_31
)
1929 mips_gprmask
|= 1 << 31;
1930 if (pinfo
& INSN_WRITE_FPR_D
)
1931 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1932 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1933 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1934 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1935 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1936 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1937 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1938 if (pinfo
& INSN_COP
)
1940 /* We don't keep enough information to sort these cases out.
1941 The itbl support does keep this information however, although
1942 we currently don't support itbl fprmats as part of the cop
1943 instruction. May want to add this support in the future. */
1945 /* Never set the bit for $0, which is always zero. */
1946 mips_gprmask
&=~ 1 << 0;
1950 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1951 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1952 & MIPS16OP_MASK_RX
);
1953 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1954 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1955 & MIPS16OP_MASK_RY
);
1956 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1957 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1958 & MIPS16OP_MASK_RZ
);
1959 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1960 mips_gprmask
|= 1 << TREG
;
1961 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1962 mips_gprmask
|= 1 << SP
;
1963 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1964 mips_gprmask
|= 1 << RA
;
1965 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1966 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1967 if (pinfo
& MIPS16_INSN_READ_Z
)
1968 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1969 & MIPS16OP_MASK_MOVE32Z
);
1970 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1971 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1972 & MIPS16OP_MASK_REGR32
);
1975 if (place
== NULL
&& ! mips_opts
.noreorder
)
1977 /* Filling the branch delay slot is more complex. We try to
1978 switch the branch with the previous instruction, which we can
1979 do if the previous instruction does not set up a condition
1980 that the branch tests and if the branch is not itself the
1981 target of any branch. */
1982 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1983 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1985 if (mips_optimize
< 2
1986 /* If we have seen .set volatile or .set nomove, don't
1988 || mips_opts
.nomove
!= 0
1989 /* If we had to emit any NOP instructions, then we
1990 already know we can not swap. */
1992 /* If we don't even know the previous insn, we can not
1994 || ! prev_insn_valid
1995 /* If the previous insn is already in a branch delay
1996 slot, then we can not swap. */
1997 || prev_insn_is_delay_slot
1998 /* If the previous previous insn was in a .set
1999 noreorder, we can't swap. Actually, the MIPS
2000 assembler will swap in this situation. However, gcc
2001 configured -with-gnu-as will generate code like
2007 in which we can not swap the bne and INSN. If gcc is
2008 not configured -with-gnu-as, it does not output the
2009 .set pseudo-ops. We don't have to check
2010 prev_insn_unreordered, because prev_insn_valid will
2011 be 0 in that case. We don't want to use
2012 prev_prev_insn_valid, because we do want to be able
2013 to swap at the start of a function. */
2014 || prev_prev_insn_unreordered
2015 /* If the branch is itself the target of a branch, we
2016 can not swap. We cheat on this; all we check for is
2017 whether there is a label on this instruction. If
2018 there are any branches to anything other than a
2019 label, users must use .set noreorder. */
2020 || insn_labels
!= NULL
2021 /* If the previous instruction is in a variant frag, we
2022 can not do the swap. This does not apply to the
2023 mips16, which uses variant frags for different
2025 || (! mips_opts
.mips16
2026 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2027 /* If the branch reads the condition codes, we don't
2028 even try to swap, because in the sequence
2033 we can not swap, and I don't feel like handling that
2035 || (! mips_opts
.mips16
2036 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2037 && (pinfo
& INSN_READ_COND_CODE
))
2038 /* We can not swap with an instruction that requires a
2039 delay slot, becase the target of the branch might
2040 interfere with that instruction. */
2041 || (! mips_opts
.mips16
2042 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2044 /* Itbl support may require additional care here. */
2045 & (INSN_LOAD_COPROC_DELAY
2046 | INSN_COPROC_MOVE_DELAY
2047 | INSN_WRITE_COND_CODE
)))
2048 || (! (hilo_interlocks
2049 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
2053 || (! mips_opts
.mips16
2055 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2056 || (! mips_opts
.mips16
2057 && mips_opts
.isa
== 1
2058 /* Itbl support may require additional care here. */
2059 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2060 /* We can not swap with a branch instruction. */
2062 & (INSN_UNCOND_BRANCH_DELAY
2063 | INSN_COND_BRANCH_DELAY
2064 | INSN_COND_BRANCH_LIKELY
))
2065 /* We do not swap with a trap instruction, since it
2066 complicates trap handlers to have the trap
2067 instruction be in a delay slot. */
2068 || (prev_pinfo
& INSN_TRAP
)
2069 /* If the branch reads a register that the previous
2070 instruction sets, we can not swap. */
2071 || (! mips_opts
.mips16
2072 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2073 && insn_uses_reg (ip
,
2074 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2077 || (! mips_opts
.mips16
2078 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2079 && insn_uses_reg (ip
,
2080 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2083 || (mips_opts
.mips16
2084 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2085 && insn_uses_reg (ip
,
2086 ((prev_insn
.insn_opcode
2088 & MIPS16OP_MASK_RX
),
2090 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2091 && insn_uses_reg (ip
,
2092 ((prev_insn
.insn_opcode
2094 & MIPS16OP_MASK_RY
),
2096 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2097 && insn_uses_reg (ip
,
2098 ((prev_insn
.insn_opcode
2100 & MIPS16OP_MASK_RZ
),
2102 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2103 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2104 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2105 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2106 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2107 && insn_uses_reg (ip
,
2108 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2111 /* If the branch writes a register that the previous
2112 instruction sets, we can not swap (we know that
2113 branches write only to RD or to $31). */
2114 || (! mips_opts
.mips16
2115 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2116 && (((pinfo
& INSN_WRITE_GPR_D
)
2117 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2118 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2119 || ((pinfo
& INSN_WRITE_GPR_31
)
2120 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2123 || (! mips_opts
.mips16
2124 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2125 && (((pinfo
& INSN_WRITE_GPR_D
)
2126 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2127 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2128 || ((pinfo
& INSN_WRITE_GPR_31
)
2129 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2132 || (mips_opts
.mips16
2133 && (pinfo
& MIPS16_INSN_WRITE_31
)
2134 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2135 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2136 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2138 /* If the branch writes a register that the previous
2139 instruction reads, we can not swap (we know that
2140 branches only write to RD or to $31). */
2141 || (! mips_opts
.mips16
2142 && (pinfo
& INSN_WRITE_GPR_D
)
2143 && insn_uses_reg (&prev_insn
,
2144 ((ip
->insn_opcode
>> OP_SH_RD
)
2147 || (! mips_opts
.mips16
2148 && (pinfo
& INSN_WRITE_GPR_31
)
2149 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2150 || (mips_opts
.mips16
2151 && (pinfo
& MIPS16_INSN_WRITE_31
)
2152 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2153 /* If we are generating embedded PIC code, the branch
2154 might be expanded into a sequence which uses $at, so
2155 we can't swap with an instruction which reads it. */
2156 || (mips_pic
== EMBEDDED_PIC
2157 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2158 /* If the previous previous instruction has a load
2159 delay, and sets a register that the branch reads, we
2161 || (! mips_opts
.mips16
2162 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2163 /* Itbl support may require additional care here. */
2164 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2165 || (! gpr_interlocks
2166 && (prev_prev_insn
.insn_mo
->pinfo
2167 & INSN_LOAD_MEMORY_DELAY
)))
2168 && insn_uses_reg (ip
,
2169 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2172 /* If one instruction sets a condition code and the
2173 other one uses a condition code, we can not swap. */
2174 || ((pinfo
& INSN_READ_COND_CODE
)
2175 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2176 || ((pinfo
& INSN_WRITE_COND_CODE
)
2177 && (prev_pinfo
& INSN_READ_COND_CODE
))
2178 /* If the previous instruction uses the PC, we can not
2180 || (mips_opts
.mips16
2181 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2182 /* If the previous instruction was extended, we can not
2184 || (mips_opts
.mips16
&& prev_insn_extended
)
2185 /* If the previous instruction had a fixup in mips16
2186 mode, we can not swap. This normally means that the
2187 previous instruction was a 4 byte branch anyhow. */
2188 || (mips_opts
.mips16
&& prev_insn_fixp
)
2189 /* If the previous instruction is a sync, sync.l, or
2190 sync.p, we can not swap. */
2191 || (prev_pinfo
& INSN_SYNC
))
2193 /* We could do even better for unconditional branches to
2194 portions of this object file; we could pick up the
2195 instruction at the destination, put it in the delay
2196 slot, and bump the destination address. */
2198 /* Update the previous insn information. */
2199 prev_prev_insn
= *ip
;
2200 prev_insn
.insn_mo
= &dummy_opcode
;
2204 /* It looks like we can actually do the swap. */
2205 if (! mips_opts
.mips16
)
2210 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2211 memcpy (temp
, prev_f
, 4);
2212 memcpy (prev_f
, f
, 4);
2213 memcpy (f
, temp
, 4);
2216 prev_insn_fixp
->fx_frag
= frag_now
;
2217 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2221 fixp
->fx_frag
= prev_insn_frag
;
2222 fixp
->fx_where
= prev_insn_where
;
2230 assert (prev_insn_fixp
== NULL
);
2231 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2232 memcpy (temp
, prev_f
, 2);
2233 memcpy (prev_f
, f
, 2);
2234 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2236 assert (reloc_type
== BFD_RELOC_UNUSED
);
2237 memcpy (f
, temp
, 2);
2241 memcpy (f
, f
+ 2, 2);
2242 memcpy (f
+ 2, temp
, 2);
2246 fixp
->fx_frag
= prev_insn_frag
;
2247 fixp
->fx_where
= prev_insn_where
;
2251 /* Update the previous insn information; leave prev_insn
2253 prev_prev_insn
= *ip
;
2255 prev_insn_is_delay_slot
= 1;
2257 /* If that was an unconditional branch, forget the previous
2258 insn information. */
2259 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2261 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2262 prev_insn
.insn_mo
= &dummy_opcode
;
2265 prev_insn_fixp
= NULL
;
2266 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2267 prev_insn_extended
= 0;
2269 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2271 /* We don't yet optimize a branch likely. What we should do
2272 is look at the target, copy the instruction found there
2273 into the delay slot, and increment the branch to jump to
2274 the next instruction. */
2276 /* Update the previous insn information. */
2277 prev_prev_insn
= *ip
;
2278 prev_insn
.insn_mo
= &dummy_opcode
;
2279 prev_insn_fixp
= NULL
;
2280 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2281 prev_insn_extended
= 0;
2285 /* Update the previous insn information. */
2287 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2289 prev_prev_insn
= prev_insn
;
2292 /* Any time we see a branch, we always fill the delay slot
2293 immediately; since this insn is not a branch, we know it
2294 is not in a delay slot. */
2295 prev_insn_is_delay_slot
= 0;
2297 prev_insn_fixp
= fixp
;
2298 prev_insn_reloc_type
= reloc_type
;
2299 if (mips_opts
.mips16
)
2300 prev_insn_extended
= (ip
->use_extend
2301 || reloc_type
> BFD_RELOC_UNUSED
);
2304 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2305 prev_insn_unreordered
= 0;
2306 prev_insn_frag
= frag_now
;
2307 prev_insn_where
= f
- frag_now
->fr_literal
;
2308 prev_insn_valid
= 1;
2310 else if (place
== NULL
)
2312 /* We need to record a bit of information even when we are not
2313 reordering, in order to determine the base address for mips16
2314 PC relative relocs. */
2315 prev_prev_insn
= prev_insn
;
2317 prev_insn_reloc_type
= reloc_type
;
2318 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2319 prev_insn_unreordered
= 1;
2322 /* We just output an insn, so the next one doesn't have a label. */
2323 mips_clear_insn_labels ();
2325 /* We must ensure that a fixup associated with an unmatched %hi
2326 reloc does not become a variant frag. Otherwise, the
2327 rearrangement of %hi relocs in frob_file may confuse
2331 frag_wane (frag_now
);
2336 /* This function forgets that there was any previous instruction or
2337 label. If PRESERVE is non-zero, it remembers enough information to
2338 know whether nops are needed before a noreorder section. */
2341 mips_no_prev_insn (preserve
)
2346 prev_insn
.insn_mo
= &dummy_opcode
;
2347 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2348 prev_nop_frag
= NULL
;
2349 prev_nop_frag_holds
= 0;
2350 prev_nop_frag_required
= 0;
2351 prev_nop_frag_since
= 0;
2353 prev_insn_valid
= 0;
2354 prev_insn_is_delay_slot
= 0;
2355 prev_insn_unreordered
= 0;
2356 prev_insn_extended
= 0;
2357 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2358 prev_prev_insn_unreordered
= 0;
2359 mips_clear_insn_labels ();
2362 /* This function must be called whenever we turn on noreorder or emit
2363 something other than instructions. It inserts any NOPS which might
2364 be needed by the previous instruction, and clears the information
2365 kept for the previous instructions. The INSNS parameter is true if
2366 instructions are to follow. */
2369 mips_emit_delays (insns
)
2372 if (! mips_opts
.noreorder
)
2377 if ((! mips_opts
.mips16
2378 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2379 && (! cop_interlocks
2380 && (prev_insn
.insn_mo
->pinfo
2381 & (INSN_LOAD_COPROC_DELAY
2382 | INSN_COPROC_MOVE_DELAY
2383 | INSN_WRITE_COND_CODE
))))
2384 || (! hilo_interlocks
2385 && (prev_insn
.insn_mo
->pinfo
2388 || (! mips_opts
.mips16
2390 && (prev_insn
.insn_mo
->pinfo
2391 & INSN_LOAD_MEMORY_DELAY
))
2392 || (! mips_opts
.mips16
2393 && mips_opts
.isa
== 1
2394 && (prev_insn
.insn_mo
->pinfo
2395 & INSN_COPROC_MEMORY_DELAY
)))
2397 /* Itbl support may require additional care here. */
2399 if ((! mips_opts
.mips16
2400 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2401 && (! cop_interlocks
2402 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2403 || (! hilo_interlocks
2404 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2405 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2408 if (prev_insn_unreordered
)
2411 else if ((! mips_opts
.mips16
2412 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2413 && (! cop_interlocks
2414 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2415 || (! hilo_interlocks
2416 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2417 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2419 /* Itbl support may require additional care here. */
2420 if (! prev_prev_insn_unreordered
)
2426 struct insn_label_list
*l
;
2430 /* Record the frag which holds the nop instructions, so
2431 that we can remove them if we don't need them. */
2432 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2433 prev_nop_frag
= frag_now
;
2434 prev_nop_frag_holds
= nops
;
2435 prev_nop_frag_required
= 0;
2436 prev_nop_frag_since
= 0;
2439 for (; nops
> 0; --nops
)
2444 /* Move on to a new frag, so that it is safe to simply
2445 decrease the size of prev_nop_frag. */
2446 frag_wane (frag_now
);
2450 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2452 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2453 symbol_set_frag (l
->label
, frag_now
);
2454 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2455 /* mips16 text labels are stored as odd. */
2456 if (mips_opts
.mips16
)
2457 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2462 /* Mark instruction labels in mips16 mode. */
2463 if (mips_opts
.mips16
&& insns
)
2464 mips16_mark_labels ();
2466 mips_no_prev_insn (insns
);
2469 /* Build an instruction created by a macro expansion. This is passed
2470 a pointer to the count of instructions created so far, an
2471 expression, the name of the instruction to build, an operand format
2472 string, and corresponding arguments. */
2476 macro_build (char *place
,
2484 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2493 struct mips_cl_insn insn
;
2494 bfd_reloc_code_real_type r
;
2498 va_start (args
, fmt
);
2504 * If the macro is about to expand into a second instruction,
2505 * print a warning if needed. We need to pass ip as a parameter
2506 * to generate a better warning message here...
2508 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2509 as_warn (_("Macro instruction expanded into multiple instructions"));
2512 *counter
+= 1; /* bump instruction counter */
2514 if (mips_opts
.mips16
)
2516 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2521 r
= BFD_RELOC_UNUSED
;
2522 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2523 assert (insn
.insn_mo
);
2524 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2526 /* Search until we get a match for NAME. */
2529 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2530 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2531 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2533 && (mips_cpu
!= 4650 || (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2537 assert (insn
.insn_mo
->name
);
2538 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2541 insn
.insn_opcode
= insn
.insn_mo
->match
;
2557 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2563 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2568 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2573 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2580 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2584 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2588 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2592 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2599 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2605 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2606 assert (r
== BFD_RELOC_MIPS_GPREL
2607 || r
== BFD_RELOC_MIPS_LITERAL
2608 || r
== BFD_RELOC_LO16
2609 || r
== BFD_RELOC_MIPS_GOT16
2610 || r
== BFD_RELOC_MIPS_CALL16
2611 || r
== BFD_RELOC_MIPS_GOT_LO16
2612 || r
== BFD_RELOC_MIPS_CALL_LO16
2613 || (ep
->X_op
== O_subtract
2614 && r
== BFD_RELOC_PCREL_LO16
));
2618 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2620 && (ep
->X_op
== O_constant
2621 || (ep
->X_op
== O_symbol
2622 && (r
== BFD_RELOC_HI16_S
2623 || r
== BFD_RELOC_HI16
2624 || r
== BFD_RELOC_MIPS_GOT_HI16
2625 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2626 || (ep
->X_op
== O_subtract
2627 && r
== BFD_RELOC_PCREL_HI16_S
)));
2628 if (ep
->X_op
== O_constant
)
2630 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2632 r
= BFD_RELOC_UNUSED
;
2637 assert (ep
!= NULL
);
2639 * This allows macro() to pass an immediate expression for
2640 * creating short branches without creating a symbol.
2641 * Note that the expression still might come from the assembly
2642 * input, in which case the value is not checked for range nor
2643 * is a relocation entry generated (yuck).
2645 if (ep
->X_op
== O_constant
)
2647 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2651 r
= BFD_RELOC_16_PCREL_S2
;
2655 assert (ep
!= NULL
);
2656 r
= BFD_RELOC_MIPS_JMP
;
2660 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2669 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2671 append_insn (place
, &insn
, ep
, r
, false);
2675 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2677 int *counter ATTRIBUTE_UNUSED
;
2683 struct mips_cl_insn insn
;
2684 bfd_reloc_code_real_type r
;
2686 r
= BFD_RELOC_UNUSED
;
2687 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2688 assert (insn
.insn_mo
);
2689 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2691 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2692 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2695 assert (insn
.insn_mo
->name
);
2696 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2699 insn
.insn_opcode
= insn
.insn_mo
->match
;
2700 insn
.use_extend
= false;
2719 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2724 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2728 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2732 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2742 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2749 regno
= va_arg (args
, int);
2750 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2751 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2772 assert (ep
!= NULL
);
2774 if (ep
->X_op
!= O_constant
)
2775 r
= BFD_RELOC_UNUSED
+ c
;
2778 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2779 false, false, &insn
.insn_opcode
,
2780 &insn
.use_extend
, &insn
.extend
);
2782 r
= BFD_RELOC_UNUSED
;
2788 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2795 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2797 append_insn (place
, &insn
, ep
, r
, false);
2801 * Generate a "lui" instruction.
2804 macro_build_lui (place
, counter
, ep
, regnum
)
2810 expressionS high_expr
;
2811 struct mips_cl_insn insn
;
2812 bfd_reloc_code_real_type r
;
2813 CONST
char *name
= "lui";
2814 CONST
char *fmt
= "t,u";
2816 assert (! mips_opts
.mips16
);
2822 high_expr
.X_op
= O_constant
;
2823 high_expr
.X_add_number
= ep
->X_add_number
;
2826 if (high_expr
.X_op
== O_constant
)
2828 /* we can compute the instruction now without a relocation entry */
2829 if (high_expr
.X_add_number
& 0x8000)
2830 high_expr
.X_add_number
+= 0x10000;
2831 high_expr
.X_add_number
=
2832 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2833 r
= BFD_RELOC_UNUSED
;
2837 assert (ep
->X_op
== O_symbol
);
2838 /* _gp_disp is a special case, used from s_cpload. */
2839 assert (mips_pic
== NO_PIC
2840 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2841 r
= BFD_RELOC_HI16_S
;
2845 * If the macro is about to expand into a second instruction,
2846 * print a warning if needed. We need to pass ip as a parameter
2847 * to generate a better warning message here...
2849 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2850 as_warn (_("Macro instruction expanded into multiple instructions"));
2853 *counter
+= 1; /* bump instruction counter */
2855 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2856 assert (insn
.insn_mo
);
2857 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2858 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2860 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2861 if (r
== BFD_RELOC_UNUSED
)
2863 insn
.insn_opcode
|= high_expr
.X_add_number
;
2864 append_insn (place
, &insn
, NULL
, r
, false);
2867 append_insn (place
, &insn
, &high_expr
, r
, false);
2871 * Generates code to set the $at register to true (one)
2872 * if reg is less than the immediate expression.
2875 set_at (counter
, reg
, unsignedp
)
2880 if (imm_expr
.X_op
== O_constant
2881 && imm_expr
.X_add_number
>= -0x8000
2882 && imm_expr
.X_add_number
< 0x8000)
2883 macro_build ((char *) NULL
, counter
, &imm_expr
,
2884 unsignedp
? "sltiu" : "slti",
2885 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2888 load_register (counter
, AT
, &imm_expr
, 0);
2889 macro_build ((char *) NULL
, counter
, NULL
,
2890 unsignedp
? "sltu" : "slt",
2891 "d,v,t", AT
, reg
, AT
);
2895 /* Warn if an expression is not a constant. */
2898 check_absolute_expr (ip
, ex
)
2899 struct mips_cl_insn
*ip
;
2902 if (ex
->X_op
== O_big
)
2903 as_bad (_("unsupported large constant"));
2904 else if (ex
->X_op
!= O_constant
)
2905 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2908 /* Count the leading zeroes by performing a binary chop. This is a
2909 bulky bit of source, but performance is a LOT better for the
2910 majority of values than a simple loop to count the bits:
2911 for (lcnt = 0; (lcnt < 32); lcnt++)
2912 if ((v) & (1 << (31 - lcnt)))
2914 However it is not code size friendly, and the gain will drop a bit
2915 on certain cached systems.
2917 #define COUNT_TOP_ZEROES(v) \
2918 (((v) & ~0xffff) == 0 \
2919 ? ((v) & ~0xff) == 0 \
2920 ? ((v) & ~0xf) == 0 \
2921 ? ((v) & ~0x3) == 0 \
2922 ? ((v) & ~0x1) == 0 \
2927 : ((v) & ~0x7) == 0 \
2930 : ((v) & ~0x3f) == 0 \
2931 ? ((v) & ~0x1f) == 0 \
2934 : ((v) & ~0x7f) == 0 \
2937 : ((v) & ~0xfff) == 0 \
2938 ? ((v) & ~0x3ff) == 0 \
2939 ? ((v) & ~0x1ff) == 0 \
2942 : ((v) & ~0x7ff) == 0 \
2945 : ((v) & ~0x3fff) == 0 \
2946 ? ((v) & ~0x1fff) == 0 \
2949 : ((v) & ~0x7fff) == 0 \
2952 : ((v) & ~0xffffff) == 0 \
2953 ? ((v) & ~0xfffff) == 0 \
2954 ? ((v) & ~0x3ffff) == 0 \
2955 ? ((v) & ~0x1ffff) == 0 \
2958 : ((v) & ~0x7ffff) == 0 \
2961 : ((v) & ~0x3fffff) == 0 \
2962 ? ((v) & ~0x1fffff) == 0 \
2965 : ((v) & ~0x7fffff) == 0 \
2968 : ((v) & ~0xfffffff) == 0 \
2969 ? ((v) & ~0x3ffffff) == 0 \
2970 ? ((v) & ~0x1ffffff) == 0 \
2973 : ((v) & ~0x7ffffff) == 0 \
2976 : ((v) & ~0x3fffffff) == 0 \
2977 ? ((v) & ~0x1fffffff) == 0 \
2980 : ((v) & ~0x7fffffff) == 0 \
2985 * This routine generates the least number of instructions neccessary to load
2986 * an absolute expression value into a register.
2989 load_register (counter
, reg
, ep
, dbl
)
2996 expressionS hi32
, lo32
;
2998 if (ep
->X_op
!= O_big
)
3000 assert (ep
->X_op
== O_constant
);
3001 if (ep
->X_add_number
< 0x8000
3002 && (ep
->X_add_number
>= 0
3003 || (ep
->X_add_number
>= -0x8000
3006 || sizeof (ep
->X_add_number
) > 4))))
3008 /* We can handle 16 bit signed values with an addiu to
3009 $zero. No need to ever use daddiu here, since $zero and
3010 the result are always correct in 32 bit mode. */
3011 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3012 (int) BFD_RELOC_LO16
);
3015 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3017 /* We can handle 16 bit unsigned values with an ori to
3019 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3020 (int) BFD_RELOC_LO16
);
3023 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3024 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3025 == ~ (offsetT
) 0x7fffffff))
3028 || sizeof (ep
->X_add_number
) > 4
3029 || (ep
->X_add_number
& 0x80000000) == 0))
3030 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
3031 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3032 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3034 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3035 == ~ (offsetT
) 0xffffffff)))
3037 /* 32 bit values require an lui. */
3038 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3039 (int) BFD_RELOC_HI16
);
3040 if ((ep
->X_add_number
& 0xffff) != 0)
3041 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3042 (int) BFD_RELOC_LO16
);
3047 /* The value is larger than 32 bits. */
3049 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3051 as_bad (_("Number larger than 32 bits"));
3052 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3053 (int) BFD_RELOC_LO16
);
3057 if (ep
->X_op
!= O_big
)
3060 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3061 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3062 hi32
.X_add_number
&= 0xffffffff;
3064 lo32
.X_add_number
&= 0xffffffff;
3068 assert (ep
->X_add_number
> 2);
3069 if (ep
->X_add_number
== 3)
3070 generic_bignum
[3] = 0;
3071 else if (ep
->X_add_number
> 4)
3072 as_bad (_("Number larger than 64 bits"));
3073 lo32
.X_op
= O_constant
;
3074 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3075 hi32
.X_op
= O_constant
;
3076 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3079 if (hi32
.X_add_number
== 0)
3084 unsigned long hi
, lo
;
3086 if (hi32
.X_add_number
== 0xffffffff)
3088 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3090 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3091 reg
, 0, (int) BFD_RELOC_LO16
);
3094 if (lo32
.X_add_number
& 0x80000000)
3096 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3097 (int) BFD_RELOC_HI16
);
3098 if (lo32
.X_add_number
& 0xffff)
3099 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3100 reg
, reg
, (int) BFD_RELOC_LO16
);
3105 /* Check for 16bit shifted constant. We know that hi32 is
3106 non-zero, so start the mask on the first bit of the hi32
3111 unsigned long himask
, lomask
;
3115 himask
= 0xffff >> (32 - shift
);
3116 lomask
= (0xffff << shift
) & 0xffffffff;
3120 himask
= 0xffff << (shift
- 32);
3123 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3124 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3128 tmp
.X_op
= O_constant
;
3130 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3131 | (lo32
.X_add_number
>> shift
));
3133 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3134 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3135 (int) BFD_RELOC_LO16
);
3136 macro_build ((char *) NULL
, counter
, NULL
,
3137 (shift
>= 32) ? "dsll32" : "dsll",
3139 (shift
>= 32) ? shift
- 32 : shift
);
3143 } while (shift
<= (64 - 16));
3145 /* Find the bit number of the lowest one bit, and store the
3146 shifted value in hi/lo. */
3147 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3148 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3152 while ((lo
& 1) == 0)
3157 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3163 while ((hi
& 1) == 0)
3172 /* Optimize if the shifted value is a (power of 2) - 1. */
3173 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3174 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3176 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3181 /* This instruction will set the register to be all
3183 tmp
.X_op
= O_constant
;
3184 tmp
.X_add_number
= (offsetT
) -1;
3185 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3186 reg
, 0, (int) BFD_RELOC_LO16
);
3190 macro_build ((char *) NULL
, counter
, NULL
,
3191 (bit
>= 32) ? "dsll32" : "dsll",
3193 (bit
>= 32) ? bit
- 32 : bit
);
3195 macro_build ((char *) NULL
, counter
, NULL
,
3196 (shift
>= 32) ? "dsrl32" : "dsrl",
3198 (shift
>= 32) ? shift
- 32 : shift
);
3203 /* Sign extend hi32 before calling load_register, because we can
3204 generally get better code when we load a sign extended value. */
3205 if ((hi32
.X_add_number
& 0x80000000) != 0)
3206 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3207 load_register (counter
, reg
, &hi32
, 0);
3210 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3214 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3223 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3225 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3226 (int) BFD_RELOC_HI16
);
3227 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3234 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3239 mid16
.X_add_number
>>= 16;
3240 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3241 freg
, (int) BFD_RELOC_LO16
);
3242 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3246 if ((lo32
.X_add_number
& 0xffff) != 0)
3247 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3248 (int) BFD_RELOC_LO16
);
3251 /* Load an address into a register. */
3254 load_address (counter
, reg
, ep
)
3261 if (ep
->X_op
!= O_constant
3262 && ep
->X_op
!= O_symbol
)
3264 as_bad (_("expression too complex"));
3265 ep
->X_op
= O_constant
;
3268 if (ep
->X_op
== O_constant
)
3270 load_register (counter
, reg
, ep
, 0);
3274 if (mips_pic
== NO_PIC
)
3276 /* If this is a reference to a GP relative symbol, we want
3277 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3279 lui $reg,<sym> (BFD_RELOC_HI16_S)
3280 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3281 If we have an addend, we always use the latter form. */
3282 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3283 || nopic_need_relax (ep
->X_add_symbol
, 1))
3288 macro_build ((char *) NULL
, counter
, ep
,
3289 ((bfd_arch_bits_per_address (stdoutput
) == 32
3290 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3291 ? "addiu" : "daddiu"),
3292 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3293 p
= frag_var (rs_machine_dependent
, 8, 0,
3294 RELAX_ENCODE (4, 8, 0, 4, 0,
3295 mips_opts
.warn_about_macros
),
3296 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3298 macro_build_lui (p
, counter
, ep
, reg
);
3301 macro_build (p
, counter
, ep
,
3302 ((bfd_arch_bits_per_address (stdoutput
) == 32
3303 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3304 ? "addiu" : "daddiu"),
3305 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3307 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3311 /* If this is a reference to an external symbol, we want
3312 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3314 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3316 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3317 If there is a constant, it must be added in after. */
3318 ex
.X_add_number
= ep
->X_add_number
;
3319 ep
->X_add_number
= 0;
3321 macro_build ((char *) NULL
, counter
, ep
,
3322 ((bfd_arch_bits_per_address (stdoutput
) == 32
3323 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3325 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3326 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3327 p
= frag_var (rs_machine_dependent
, 4, 0,
3328 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3329 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3330 macro_build (p
, counter
, ep
,
3331 ((bfd_arch_bits_per_address (stdoutput
) == 32
3332 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3333 ? "addiu" : "daddiu"),
3334 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3335 if (ex
.X_add_number
!= 0)
3337 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3338 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3339 ex
.X_op
= O_constant
;
3340 macro_build ((char *) NULL
, counter
, &ex
,
3341 ((bfd_arch_bits_per_address (stdoutput
) == 32
3342 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3343 ? "addiu" : "daddiu"),
3344 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3347 else if (mips_pic
== SVR4_PIC
)
3352 /* This is the large GOT case. If this is a reference to an
3353 external symbol, we want
3354 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3356 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3357 Otherwise, for a reference to a local symbol, we want
3358 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3360 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3361 If there is a constant, it must be added in after. */
3362 ex
.X_add_number
= ep
->X_add_number
;
3363 ep
->X_add_number
= 0;
3364 if (reg_needs_delay (GP
))
3369 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3370 (int) BFD_RELOC_MIPS_GOT_HI16
);
3371 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3372 ((bfd_arch_bits_per_address (stdoutput
) == 32
3373 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3374 ? "addu" : "daddu"),
3375 "d,v,t", reg
, reg
, GP
);
3376 macro_build ((char *) NULL
, counter
, ep
,
3377 ((bfd_arch_bits_per_address (stdoutput
) == 32
3378 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3380 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3381 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3382 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3383 mips_opts
.warn_about_macros
),
3384 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3387 /* We need a nop before loading from $gp. This special
3388 check is required because the lui which starts the main
3389 instruction stream does not refer to $gp, and so will not
3390 insert the nop which may be required. */
3391 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3394 macro_build (p
, counter
, ep
,
3395 ((bfd_arch_bits_per_address (stdoutput
) == 32
3396 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3398 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3400 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3402 macro_build (p
, counter
, ep
,
3403 ((bfd_arch_bits_per_address (stdoutput
) == 32
3404 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3405 ? "addiu" : "daddiu"),
3406 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3407 if (ex
.X_add_number
!= 0)
3409 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3410 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3411 ex
.X_op
= O_constant
;
3412 macro_build ((char *) NULL
, counter
, &ex
,
3413 ((bfd_arch_bits_per_address (stdoutput
) == 32
3414 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3415 ? "addiu" : "daddiu"),
3416 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3419 else if (mips_pic
== EMBEDDED_PIC
)
3422 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3424 macro_build ((char *) NULL
, counter
, ep
,
3425 ((bfd_arch_bits_per_address (stdoutput
) == 32
3426 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3427 ? "addiu" : "daddiu"),
3428 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3436 * This routine implements the seemingly endless macro or synthesized
3437 * instructions and addressing modes in the mips assembly language. Many
3438 * of these macros are simple and are similar to each other. These could
3439 * probably be handled by some kind of table or grammer aproach instead of
3440 * this verbose method. Others are not simple macros but are more like
3441 * optimizing code generation.
3442 * One interesting optimization is when several store macros appear
3443 * consecutivly that would load AT with the upper half of the same address.
3444 * The ensuing load upper instructions are ommited. This implies some kind
3445 * of global optimization. We currently only optimize within a single macro.
3446 * For many of the load and store macros if the address is specified as a
3447 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3448 * first load register 'at' with zero and use it as the base register. The
3449 * mips assembler simply uses register $zero. Just one tiny optimization
3454 struct mips_cl_insn
*ip
;
3456 register int treg
, sreg
, dreg
, breg
;
3472 bfd_reloc_code_real_type r
;
3474 int hold_mips_optimize
;
3476 assert (! mips_opts
.mips16
);
3478 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3479 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3480 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3481 mask
= ip
->insn_mo
->mask
;
3483 expr1
.X_op
= O_constant
;
3484 expr1
.X_op_symbol
= NULL
;
3485 expr1
.X_add_symbol
= NULL
;
3486 expr1
.X_add_number
= 1;
3498 mips_emit_delays (true);
3499 ++mips_opts
.noreorder
;
3500 mips_any_noreorder
= 1;
3502 expr1
.X_add_number
= 8;
3503 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3505 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3507 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3508 macro_build ((char *) NULL
, &icnt
, NULL
,
3509 dbl
? "dsub" : "sub",
3510 "d,v,t", dreg
, 0, sreg
);
3512 --mips_opts
.noreorder
;
3533 if (imm_expr
.X_op
== O_constant
3534 && imm_expr
.X_add_number
>= -0x8000
3535 && imm_expr
.X_add_number
< 0x8000)
3537 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3538 (int) BFD_RELOC_LO16
);
3541 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3542 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3561 if (imm_expr
.X_op
== O_constant
3562 && imm_expr
.X_add_number
>= 0
3563 && imm_expr
.X_add_number
< 0x10000)
3565 if (mask
!= M_NOR_I
)
3566 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3567 sreg
, (int) BFD_RELOC_LO16
);
3570 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3571 treg
, sreg
, (int) BFD_RELOC_LO16
);
3572 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3578 load_register (&icnt
, AT
, &imm_expr
, 0);
3579 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3596 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3598 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3602 load_register (&icnt
, AT
, &imm_expr
, 0);
3603 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3611 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3612 likely
? "bgezl" : "bgez",
3618 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3619 likely
? "blezl" : "blez",
3623 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3624 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3625 likely
? "beql" : "beq",
3632 /* check for > max integer */
3633 maxnum
= 0x7fffffff;
3634 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3641 if (imm_expr
.X_op
== O_constant
3642 && imm_expr
.X_add_number
>= maxnum
3643 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3646 /* result is always false */
3649 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3650 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3654 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3655 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3660 if (imm_expr
.X_op
!= O_constant
)
3661 as_bad (_("Unsupported large constant"));
3662 imm_expr
.X_add_number
++;
3666 if (mask
== M_BGEL_I
)
3668 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3670 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3671 likely
? "bgezl" : "bgez",
3675 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3677 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3678 likely
? "bgtzl" : "bgtz",
3682 maxnum
= 0x7fffffff;
3683 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3690 maxnum
= - maxnum
- 1;
3691 if (imm_expr
.X_op
== O_constant
3692 && imm_expr
.X_add_number
<= maxnum
3693 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3696 /* result is always true */
3697 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3698 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3701 set_at (&icnt
, sreg
, 0);
3702 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3703 likely
? "beql" : "beq",
3714 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3715 likely
? "beql" : "beq",
3719 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3721 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3722 likely
? "beql" : "beq",
3730 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3731 && imm_expr
.X_op
== O_constant
3732 && imm_expr
.X_add_number
== 0xffffffff))
3734 if (imm_expr
.X_op
!= O_constant
)
3735 as_bad (_("Unsupported large constant"));
3736 imm_expr
.X_add_number
++;
3740 if (mask
== M_BGEUL_I
)
3742 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3744 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3746 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3747 likely
? "bnel" : "bne",
3751 set_at (&icnt
, sreg
, 1);
3752 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3753 likely
? "beql" : "beq",
3762 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3763 likely
? "bgtzl" : "bgtz",
3769 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3770 likely
? "bltzl" : "bltz",
3774 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3775 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3776 likely
? "bnel" : "bne",
3785 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3786 likely
? "bnel" : "bne",
3792 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3794 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3795 likely
? "bnel" : "bne",
3804 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3805 likely
? "blezl" : "blez",
3811 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3812 likely
? "bgezl" : "bgez",
3816 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3817 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3818 likely
? "beql" : "beq",
3825 maxnum
= 0x7fffffff;
3826 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3833 if (imm_expr
.X_op
== O_constant
3834 && imm_expr
.X_add_number
>= maxnum
3835 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3837 if (imm_expr
.X_op
!= O_constant
)
3838 as_bad (_("Unsupported large constant"));
3839 imm_expr
.X_add_number
++;
3843 if (mask
== M_BLTL_I
)
3845 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3847 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3848 likely
? "bltzl" : "bltz",
3852 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3854 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3855 likely
? "blezl" : "blez",
3859 set_at (&icnt
, sreg
, 0);
3860 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3861 likely
? "bnel" : "bne",
3870 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3871 likely
? "beql" : "beq",
3877 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3879 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3880 likely
? "beql" : "beq",
3888 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3889 && imm_expr
.X_op
== O_constant
3890 && imm_expr
.X_add_number
== 0xffffffff))
3892 if (imm_expr
.X_op
!= O_constant
)
3893 as_bad (_("Unsupported large constant"));
3894 imm_expr
.X_add_number
++;
3898 if (mask
== M_BLTUL_I
)
3900 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3902 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3904 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3905 likely
? "beql" : "beq",
3909 set_at (&icnt
, sreg
, 1);
3910 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3911 likely
? "bnel" : "bne",
3920 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3921 likely
? "bltzl" : "bltz",
3927 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3928 likely
? "bgtzl" : "bgtz",
3932 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3933 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3934 likely
? "bnel" : "bne",
3945 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3946 likely
? "bnel" : "bne",
3950 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3952 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3953 likely
? "bnel" : "bne",
3969 as_warn (_("Divide by zero."));
3971 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3973 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3977 mips_emit_delays (true);
3978 ++mips_opts
.noreorder
;
3979 mips_any_noreorder
= 1;
3982 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3983 macro_build ((char *) NULL
, &icnt
, NULL
,
3984 dbl
? "ddiv" : "div",
3985 "z,s,t", sreg
, treg
);
3989 expr1
.X_add_number
= 8;
3990 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3991 macro_build ((char *) NULL
, &icnt
, NULL
,
3992 dbl
? "ddiv" : "div",
3993 "z,s,t", sreg
, treg
);
3994 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3996 expr1
.X_add_number
= -1;
3997 macro_build ((char *) NULL
, &icnt
, &expr1
,
3998 dbl
? "daddiu" : "addiu",
3999 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4000 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4001 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4004 expr1
.X_add_number
= 1;
4005 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4006 (int) BFD_RELOC_LO16
);
4007 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4012 expr1
.X_add_number
= 0x80000000;
4013 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4014 (int) BFD_RELOC_HI16
);
4018 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4019 /* We want to close the noreorder block as soon as possible, so
4020 that later insns are available for delay slot filling. */
4021 --mips_opts
.noreorder
;
4025 expr1
.X_add_number
= 8;
4026 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4027 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4029 /* We want to close the noreorder block as soon as possible, so
4030 that later insns are available for delay slot filling. */
4031 --mips_opts
.noreorder
;
4033 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4035 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4074 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4076 as_warn (_("Divide by zero."));
4078 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4080 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4083 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4085 if (strcmp (s2
, "mflo") == 0)
4086 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4089 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4092 if (imm_expr
.X_op
== O_constant
4093 && imm_expr
.X_add_number
== -1
4094 && s
[strlen (s
) - 1] != 'u')
4096 if (strcmp (s2
, "mflo") == 0)
4099 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4102 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4106 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4110 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4111 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4112 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4131 mips_emit_delays (true);
4132 ++mips_opts
.noreorder
;
4133 mips_any_noreorder
= 1;
4136 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4137 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4138 /* We want to close the noreorder block as soon as possible, so
4139 that later insns are available for delay slot filling. */
4140 --mips_opts
.noreorder
;
4144 expr1
.X_add_number
= 8;
4145 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4146 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4148 /* We want to close the noreorder block as soon as possible, so
4149 that later insns are available for delay slot filling. */
4150 --mips_opts
.noreorder
;
4151 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4153 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4159 /* Load the address of a symbol into a register. If breg is not
4160 zero, we then add a base register to it. */
4162 /* When generating embedded PIC code, we permit expressions of
4165 where bar is an address in the current section. These are used
4166 when getting the addresses of functions. We don't permit
4167 X_add_number to be non-zero, because if the symbol is
4168 external the relaxing code needs to know that any addend is
4169 purely the offset to X_op_symbol. */
4170 if (mips_pic
== EMBEDDED_PIC
4171 && offset_expr
.X_op
== O_subtract
4172 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4173 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4174 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4176 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4180 && (offset_expr
.X_add_number
== 0
4181 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4183 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4184 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4185 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4186 ((bfd_arch_bits_per_address (stdoutput
) == 32
4187 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4188 ? "addiu" : "daddiu"),
4189 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4193 if (offset_expr
.X_op
!= O_symbol
4194 && offset_expr
.X_op
!= O_constant
)
4196 as_bad (_("expression too complex"));
4197 offset_expr
.X_op
= O_constant
;
4211 if (offset_expr
.X_op
== O_constant
)
4212 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4213 else if (mips_pic
== NO_PIC
)
4215 /* If this is a reference to an GP relative symbol, we want
4216 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4218 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4219 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4220 If we have a constant, we need two instructions anyhow,
4221 so we may as well always use the latter form. */
4222 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4223 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4228 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4229 ((bfd_arch_bits_per_address (stdoutput
) == 32
4230 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4231 ? "addiu" : "daddiu"),
4232 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4233 p
= frag_var (rs_machine_dependent
, 8, 0,
4234 RELAX_ENCODE (4, 8, 0, 4, 0,
4235 mips_opts
.warn_about_macros
),
4236 offset_expr
.X_add_symbol
, (offsetT
) 0,
4239 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4242 macro_build (p
, &icnt
, &offset_expr
,
4243 ((bfd_arch_bits_per_address (stdoutput
) == 32
4244 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4245 ? "addiu" : "daddiu"),
4246 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4248 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4250 /* If this is a reference to an external symbol, and there
4251 is no constant, we want
4252 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4253 For a local symbol, we want
4254 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4256 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4258 If we have a small constant, and this is a reference to
4259 an external symbol, we want
4260 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4262 addiu $tempreg,$tempreg,<constant>
4263 For a local symbol, we want the same instruction
4264 sequence, but we output a BFD_RELOC_LO16 reloc on the
4267 If we have a large constant, and this is a reference to
4268 an external symbol, we want
4269 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4270 lui $at,<hiconstant>
4271 addiu $at,$at,<loconstant>
4272 addu $tempreg,$tempreg,$at
4273 For a local symbol, we want the same instruction
4274 sequence, but we output a BFD_RELOC_LO16 reloc on the
4275 addiu instruction. */
4276 expr1
.X_add_number
= offset_expr
.X_add_number
;
4277 offset_expr
.X_add_number
= 0;
4279 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4281 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4282 if (expr1
.X_add_number
== 0)
4290 /* We're going to put in an addu instruction using
4291 tempreg, so we may as well insert the nop right
4293 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4297 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4298 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4300 ? mips_opts
.warn_about_macros
4302 offset_expr
.X_add_symbol
, (offsetT
) 0,
4306 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4309 macro_build (p
, &icnt
, &expr1
,
4310 ((bfd_arch_bits_per_address (stdoutput
) == 32
4311 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4312 ? "addiu" : "daddiu"),
4313 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4314 /* FIXME: If breg == 0, and the next instruction uses
4315 $tempreg, then if this variant case is used an extra
4316 nop will be generated. */
4318 else if (expr1
.X_add_number
>= -0x8000
4319 && expr1
.X_add_number
< 0x8000)
4321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4323 macro_build ((char *) NULL
, &icnt
, &expr1
,
4324 ((bfd_arch_bits_per_address (stdoutput
) == 32
4325 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4326 ? "addiu" : "daddiu"),
4327 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4328 (void) frag_var (rs_machine_dependent
, 0, 0,
4329 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4330 offset_expr
.X_add_symbol
, (offsetT
) 0,
4337 /* If we are going to add in a base register, and the
4338 target register and the base register are the same,
4339 then we are using AT as a temporary register. Since
4340 we want to load the constant into AT, we add our
4341 current AT (from the global offset table) and the
4342 register into the register now, and pretend we were
4343 not using a base register. */
4348 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4350 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4351 ((bfd_arch_bits_per_address (stdoutput
) == 32
4352 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4353 ? "addu" : "daddu"),
4354 "d,v,t", treg
, AT
, breg
);
4360 /* Set mips_optimize around the lui instruction to avoid
4361 inserting an unnecessary nop after the lw. */
4362 hold_mips_optimize
= mips_optimize
;
4364 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4365 mips_optimize
= hold_mips_optimize
;
4367 macro_build ((char *) NULL
, &icnt
, &expr1
,
4368 ((bfd_arch_bits_per_address (stdoutput
) == 32
4369 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4370 ? "addiu" : "daddiu"),
4371 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4372 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4373 ((bfd_arch_bits_per_address (stdoutput
) == 32
4374 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4375 ? "addu" : "daddu"),
4376 "d,v,t", tempreg
, tempreg
, AT
);
4377 (void) frag_var (rs_machine_dependent
, 0, 0,
4378 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4379 offset_expr
.X_add_symbol
, (offsetT
) 0,
4384 else if (mips_pic
== SVR4_PIC
)
4388 /* This is the large GOT case. If this is a reference to an
4389 external symbol, and there is no constant, we want
4390 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4391 addu $tempreg,$tempreg,$gp
4392 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4393 For a local symbol, we want
4394 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4396 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4398 If we have a small constant, and this is a reference to
4399 an external symbol, we want
4400 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4401 addu $tempreg,$tempreg,$gp
4402 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4404 addiu $tempreg,$tempreg,<constant>
4405 For a local symbol, we want
4406 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4408 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4410 If we have a large constant, and this is a reference to
4411 an external symbol, we want
4412 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4413 addu $tempreg,$tempreg,$gp
4414 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4415 lui $at,<hiconstant>
4416 addiu $at,$at,<loconstant>
4417 addu $tempreg,$tempreg,$at
4418 For a local symbol, we want
4419 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4420 lui $at,<hiconstant>
4421 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4422 addu $tempreg,$tempreg,$at
4424 expr1
.X_add_number
= offset_expr
.X_add_number
;
4425 offset_expr
.X_add_number
= 0;
4427 if (reg_needs_delay (GP
))
4431 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4432 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4433 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4434 ((bfd_arch_bits_per_address (stdoutput
) == 32
4435 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4436 ? "addu" : "daddu"),
4437 "d,v,t", tempreg
, tempreg
, GP
);
4438 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4440 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4442 if (expr1
.X_add_number
== 0)
4450 /* We're going to put in an addu instruction using
4451 tempreg, so we may as well insert the nop right
4453 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4458 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4459 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4462 ? mips_opts
.warn_about_macros
4464 offset_expr
.X_add_symbol
, (offsetT
) 0,
4467 else if (expr1
.X_add_number
>= -0x8000
4468 && expr1
.X_add_number
< 0x8000)
4470 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4472 macro_build ((char *) NULL
, &icnt
, &expr1
,
4473 ((bfd_arch_bits_per_address (stdoutput
) == 32
4474 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4475 ? "addiu" : "daddiu"),
4476 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4478 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4479 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4481 ? mips_opts
.warn_about_macros
4483 offset_expr
.X_add_symbol
, (offsetT
) 0,
4490 /* If we are going to add in a base register, and the
4491 target register and the base register are the same,
4492 then we are using AT as a temporary register. Since
4493 we want to load the constant into AT, we add our
4494 current AT (from the global offset table) and the
4495 register into the register now, and pretend we were
4496 not using a base register. */
4504 assert (tempreg
== AT
);
4505 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4508 ((bfd_arch_bits_per_address (stdoutput
) == 32
4509 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4510 ? "addu" : "daddu"),
4511 "d,v,t", treg
, AT
, breg
);
4516 /* Set mips_optimize around the lui instruction to avoid
4517 inserting an unnecessary nop after the lw. */
4518 hold_mips_optimize
= mips_optimize
;
4520 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4521 mips_optimize
= hold_mips_optimize
;
4523 macro_build ((char *) NULL
, &icnt
, &expr1
,
4524 ((bfd_arch_bits_per_address (stdoutput
) == 32
4525 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4526 ? "addiu" : "daddiu"),
4527 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4528 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4529 ((bfd_arch_bits_per_address (stdoutput
) == 32
4530 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4531 ? "addu" : "daddu"),
4532 "d,v,t", dreg
, dreg
, AT
);
4534 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4535 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4538 ? mips_opts
.warn_about_macros
4540 offset_expr
.X_add_symbol
, (offsetT
) 0,
4548 /* This is needed because this instruction uses $gp, but
4549 the first instruction on the main stream does not. */
4550 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4553 macro_build (p
, &icnt
, &offset_expr
,
4555 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4557 if (expr1
.X_add_number
>= -0x8000
4558 && expr1
.X_add_number
< 0x8000)
4560 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4562 macro_build (p
, &icnt
, &expr1
,
4563 ((bfd_arch_bits_per_address (stdoutput
) == 32
4564 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4565 ? "addiu" : "daddiu"),
4566 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4567 /* FIXME: If add_number is 0, and there was no base
4568 register, the external symbol case ended with a load,
4569 so if the symbol turns out to not be external, and
4570 the next instruction uses tempreg, an unnecessary nop
4571 will be inserted. */
4577 /* We must add in the base register now, as in the
4578 external symbol case. */
4579 assert (tempreg
== AT
);
4580 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4582 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4583 ((bfd_arch_bits_per_address (stdoutput
) == 32
4584 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4585 ? "addu" : "daddu"),
4586 "d,v,t", treg
, AT
, breg
);
4589 /* We set breg to 0 because we have arranged to add
4590 it in in both cases. */
4594 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4596 macro_build (p
, &icnt
, &expr1
,
4597 ((bfd_arch_bits_per_address (stdoutput
) == 32
4598 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4599 ? "addiu" : "daddiu"),
4600 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4602 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4603 ((bfd_arch_bits_per_address (stdoutput
) == 32
4604 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4605 ? "addu" : "daddu"),
4606 "d,v,t", tempreg
, tempreg
, AT
);
4610 else if (mips_pic
== EMBEDDED_PIC
)
4613 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4615 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4616 ((bfd_arch_bits_per_address (stdoutput
) == 32
4617 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4618 ? "addiu" : "daddiu"),
4619 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4625 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4626 ((bfd_arch_bits_per_address (stdoutput
) == 32
4627 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4628 ? "addu" : "daddu"),
4629 "d,v,t", treg
, tempreg
, breg
);
4637 /* The j instruction may not be used in PIC code, since it
4638 requires an absolute address. We convert it to a b
4640 if (mips_pic
== NO_PIC
)
4641 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4643 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4646 /* The jal instructions must be handled as macros because when
4647 generating PIC code they expand to multi-instruction
4648 sequences. Normally they are simple instructions. */
4653 if (mips_pic
== NO_PIC
4654 || mips_pic
== EMBEDDED_PIC
)
4655 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4657 else if (mips_pic
== SVR4_PIC
)
4659 if (sreg
!= PIC_CALL_REG
)
4660 as_warn (_("MIPS PIC call to register other than $25"));
4662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4664 if (mips_cprestore_offset
< 0)
4665 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4668 expr1
.X_add_number
= mips_cprestore_offset
;
4669 macro_build ((char *) NULL
, &icnt
, &expr1
,
4670 ((bfd_arch_bits_per_address (stdoutput
) == 32
4671 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4673 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4682 if (mips_pic
== NO_PIC
)
4683 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4684 else if (mips_pic
== SVR4_PIC
)
4686 /* If this is a reference to an external symbol, and we are
4687 using a small GOT, we want
4688 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4692 lw $gp,cprestore($sp)
4693 The cprestore value is set using the .cprestore
4694 pseudo-op. If we are using a big GOT, we want
4695 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4697 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4701 lw $gp,cprestore($sp)
4702 If the symbol is not external, we want
4703 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4705 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4708 lw $gp,cprestore($sp) */
4712 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4713 ((bfd_arch_bits_per_address (stdoutput
) == 32
4714 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4716 "t,o(b)", PIC_CALL_REG
,
4717 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4718 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4720 p
= frag_var (rs_machine_dependent
, 4, 0,
4721 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4722 offset_expr
.X_add_symbol
, (offsetT
) 0,
4729 if (reg_needs_delay (GP
))
4733 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4734 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4735 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4736 ((bfd_arch_bits_per_address (stdoutput
) == 32
4737 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4738 ? "addu" : "daddu"),
4739 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4740 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4741 ((bfd_arch_bits_per_address (stdoutput
) == 32
4742 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4744 "t,o(b)", PIC_CALL_REG
,
4745 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4746 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4748 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4749 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4751 offset_expr
.X_add_symbol
, (offsetT
) 0,
4755 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4758 macro_build (p
, &icnt
, &offset_expr
,
4759 ((bfd_arch_bits_per_address (stdoutput
) == 32
4760 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4762 "t,o(b)", PIC_CALL_REG
,
4763 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4765 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4768 macro_build (p
, &icnt
, &offset_expr
,
4769 ((bfd_arch_bits_per_address (stdoutput
) == 32
4770 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4771 ? "addiu" : "daddiu"),
4772 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4773 (int) BFD_RELOC_LO16
);
4774 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4775 "jalr", "s", PIC_CALL_REG
);
4776 if (mips_cprestore_offset
< 0)
4777 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4780 if (mips_opts
.noreorder
)
4781 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4783 expr1
.X_add_number
= mips_cprestore_offset
;
4784 macro_build ((char *) NULL
, &icnt
, &expr1
,
4785 ((bfd_arch_bits_per_address (stdoutput
) == 32
4786 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4788 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4792 else if (mips_pic
== EMBEDDED_PIC
)
4794 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4795 /* The linker may expand the call to a longer sequence which
4796 uses $at, so we must break rather than return. */
4821 /* Itbl support may require additional care here. */
4826 /* Itbl support may require additional care here. */
4831 /* Itbl support may require additional care here. */
4836 /* Itbl support may require additional care here. */
4848 if (mips_cpu
== 4650)
4850 as_bad (_("opcode not supported on this processor"));
4854 /* Itbl support may require additional care here. */
4859 /* Itbl support may require additional care here. */
4864 /* Itbl support may require additional care here. */
4884 if (breg
== treg
|| coproc
|| lr
)
4906 /* Itbl support may require additional care here. */
4911 /* Itbl support may require additional care here. */
4916 /* Itbl support may require additional care here. */
4921 /* Itbl support may require additional care here. */
4937 if (mips_cpu
== 4650)
4939 as_bad (_("opcode not supported on this processor"));
4944 /* Itbl support may require additional care here. */
4948 /* Itbl support may require additional care here. */
4953 /* Itbl support may require additional care here. */
4965 /* Itbl support may require additional care here. */
4966 if (mask
== M_LWC1_AB
4967 || mask
== M_SWC1_AB
4968 || mask
== M_LDC1_AB
4969 || mask
== M_SDC1_AB
4978 if (offset_expr
.X_op
!= O_constant
4979 && offset_expr
.X_op
!= O_symbol
)
4981 as_bad (_("expression too complex"));
4982 offset_expr
.X_op
= O_constant
;
4985 /* A constant expression in PIC code can be handled just as it
4986 is in non PIC code. */
4987 if (mips_pic
== NO_PIC
4988 || offset_expr
.X_op
== O_constant
)
4990 /* If this is a reference to a GP relative symbol, and there
4991 is no base register, we want
4992 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4993 Otherwise, if there is no base register, we want
4994 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4995 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4996 If we have a constant, we need two instructions anyhow,
4997 so we always use the latter form.
4999 If we have a base register, and this is a reference to a
5000 GP relative symbol, we want
5001 addu $tempreg,$breg,$gp
5002 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5004 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5005 addu $tempreg,$tempreg,$breg
5006 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5007 With a constant we always use the latter case. */
5010 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5011 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5016 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5017 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5018 p
= frag_var (rs_machine_dependent
, 8, 0,
5019 RELAX_ENCODE (4, 8, 0, 4, 0,
5020 (mips_opts
.warn_about_macros
5022 && mips_opts
.noat
))),
5023 offset_expr
.X_add_symbol
, (offsetT
) 0,
5027 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5030 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5031 (int) BFD_RELOC_LO16
, tempreg
);
5035 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5036 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5042 ((bfd_arch_bits_per_address (stdoutput
) == 32
5043 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5044 ? "addu" : "daddu"),
5045 "d,v,t", tempreg
, breg
, GP
);
5046 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5047 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5048 p
= frag_var (rs_machine_dependent
, 12, 0,
5049 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5050 offset_expr
.X_add_symbol
, (offsetT
) 0,
5053 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5056 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5057 ((bfd_arch_bits_per_address (stdoutput
) == 32
5058 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5059 ? "addu" : "daddu"),
5060 "d,v,t", tempreg
, tempreg
, breg
);
5063 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5064 (int) BFD_RELOC_LO16
, tempreg
);
5067 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5069 /* If this is a reference to an external symbol, we want
5070 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5072 <op> $treg,0($tempreg)
5074 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5076 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5077 <op> $treg,0($tempreg)
5078 If there is a base register, we add it to $tempreg before
5079 the <op>. If there is a constant, we stick it in the
5080 <op> instruction. We don't handle constants larger than
5081 16 bits, because we have no way to load the upper 16 bits
5082 (actually, we could handle them for the subset of cases
5083 in which we are not using $at). */
5084 assert (offset_expr
.X_op
== O_symbol
);
5085 expr1
.X_add_number
= offset_expr
.X_add_number
;
5086 offset_expr
.X_add_number
= 0;
5087 if (expr1
.X_add_number
< -0x8000
5088 || expr1
.X_add_number
>= 0x8000)
5089 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5091 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5092 ((bfd_arch_bits_per_address (stdoutput
) == 32
5093 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5095 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5096 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5097 p
= frag_var (rs_machine_dependent
, 4, 0,
5098 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5099 offset_expr
.X_add_symbol
, (offsetT
) 0,
5101 macro_build (p
, &icnt
, &offset_expr
,
5102 ((bfd_arch_bits_per_address (stdoutput
) == 32
5103 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5104 ? "addiu" : "daddiu"),
5105 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5107 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5108 ((bfd_arch_bits_per_address (stdoutput
) == 32
5109 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5110 ? "addu" : "daddu"),
5111 "d,v,t", tempreg
, tempreg
, breg
);
5112 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5113 (int) BFD_RELOC_LO16
, tempreg
);
5115 else if (mips_pic
== SVR4_PIC
)
5119 /* If this is a reference to an external symbol, we want
5120 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5121 addu $tempreg,$tempreg,$gp
5122 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5123 <op> $treg,0($tempreg)
5125 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5127 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5128 <op> $treg,0($tempreg)
5129 If there is a base register, we add it to $tempreg before
5130 the <op>. If there is a constant, we stick it in the
5131 <op> instruction. We don't handle constants larger than
5132 16 bits, because we have no way to load the upper 16 bits
5133 (actually, we could handle them for the subset of cases
5134 in which we are not using $at). */
5135 assert (offset_expr
.X_op
== O_symbol
);
5136 expr1
.X_add_number
= offset_expr
.X_add_number
;
5137 offset_expr
.X_add_number
= 0;
5138 if (expr1
.X_add_number
< -0x8000
5139 || expr1
.X_add_number
>= 0x8000)
5140 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5141 if (reg_needs_delay (GP
))
5146 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5147 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5148 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5149 ((bfd_arch_bits_per_address (stdoutput
) == 32
5150 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5151 ? "addu" : "daddu"),
5152 "d,v,t", tempreg
, tempreg
, GP
);
5153 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5154 ((bfd_arch_bits_per_address (stdoutput
) == 32
5155 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5157 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5159 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5160 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5161 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5164 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5167 macro_build (p
, &icnt
, &offset_expr
,
5168 ((bfd_arch_bits_per_address (stdoutput
) == 32
5169 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5171 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5173 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5175 macro_build (p
, &icnt
, &offset_expr
,
5176 ((bfd_arch_bits_per_address (stdoutput
) == 32
5177 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5178 ? "addiu" : "daddiu"),
5179 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5181 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5182 ((bfd_arch_bits_per_address (stdoutput
) == 32
5183 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5184 ? "addu" : "daddu"),
5185 "d,v,t", tempreg
, tempreg
, breg
);
5186 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5187 (int) BFD_RELOC_LO16
, tempreg
);
5189 else if (mips_pic
== EMBEDDED_PIC
)
5191 /* If there is no base register, we want
5192 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5193 If there is a base register, we want
5194 addu $tempreg,$breg,$gp
5195 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5197 assert (offset_expr
.X_op
== O_symbol
);
5200 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5201 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5206 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5207 ((bfd_arch_bits_per_address (stdoutput
) == 32
5208 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5209 ? "addu" : "daddu"),
5210 "d,v,t", tempreg
, breg
, GP
);
5211 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5212 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5225 load_register (&icnt
, treg
, &imm_expr
, 0);
5229 load_register (&icnt
, treg
, &imm_expr
, 1);
5233 if (imm_expr
.X_op
== O_constant
)
5235 load_register (&icnt
, AT
, &imm_expr
, 0);
5236 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5237 "mtc1", "t,G", AT
, treg
);
5242 assert (offset_expr
.X_op
== O_symbol
5243 && strcmp (segment_name (S_GET_SEGMENT
5244 (offset_expr
.X_add_symbol
)),
5246 && offset_expr
.X_add_number
== 0);
5247 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5248 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5253 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5254 the entire value, and in mips1 mode it is the high order 32
5255 bits of the value and the low order 32 bits are either zero
5256 or in offset_expr. */
5257 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5259 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5260 load_register (&icnt
, treg
, &imm_expr
, 1);
5265 if (target_big_endian
)
5277 load_register (&icnt
, hreg
, &imm_expr
, 0);
5280 if (offset_expr
.X_op
== O_absent
)
5281 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5285 assert (offset_expr
.X_op
== O_constant
);
5286 load_register (&icnt
, lreg
, &offset_expr
, 0);
5293 /* We know that sym is in the .rdata section. First we get the
5294 upper 16 bits of the address. */
5295 if (mips_pic
== NO_PIC
)
5297 /* FIXME: This won't work for a 64 bit address. */
5298 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5300 else if (mips_pic
== SVR4_PIC
)
5302 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5303 ((bfd_arch_bits_per_address (stdoutput
) == 32
5304 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5306 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5308 else if (mips_pic
== EMBEDDED_PIC
)
5310 /* For embedded PIC we pick up the entire address off $gp in
5311 a single instruction. */
5312 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5313 ((bfd_arch_bits_per_address (stdoutput
) == 32
5314 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5315 ? "addiu" : "daddiu"),
5316 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5317 offset_expr
.X_op
= O_constant
;
5318 offset_expr
.X_add_number
= 0;
5323 /* Now we load the register(s). */
5324 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5325 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5326 treg
, (int) BFD_RELOC_LO16
, AT
);
5329 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5330 treg
, (int) BFD_RELOC_LO16
, AT
);
5333 /* FIXME: How in the world do we deal with the possible
5335 offset_expr
.X_add_number
+= 4;
5336 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5337 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5341 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5342 does not become a variant frag. */
5343 frag_wane (frag_now
);
5349 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5350 the entire value, and in mips1 mode it is the high order 32
5351 bits of the value and the low order 32 bits are either zero
5352 or in offset_expr. */
5353 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5355 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5356 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5357 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5358 "dmtc1", "t,S", AT
, treg
);
5361 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5362 "mtc1", "t,G", AT
, treg
+ 1);
5363 if (offset_expr
.X_op
== O_absent
)
5364 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5365 "mtc1", "t,G", 0, treg
);
5368 assert (offset_expr
.X_op
== O_constant
);
5369 load_register (&icnt
, AT
, &offset_expr
, 0);
5370 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5371 "mtc1", "t,G", AT
, treg
);
5377 assert (offset_expr
.X_op
== O_symbol
5378 && offset_expr
.X_add_number
== 0);
5379 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5380 if (strcmp (s
, ".lit8") == 0)
5382 if (mips_opts
.isa
!= 1)
5384 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5385 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5389 r
= BFD_RELOC_MIPS_LITERAL
;
5394 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5395 if (mips_pic
== SVR4_PIC
)
5396 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5397 ((bfd_arch_bits_per_address (stdoutput
) == 32
5398 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5400 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5403 /* FIXME: This won't work for a 64 bit address. */
5404 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5407 if (mips_opts
.isa
!= 1)
5409 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5410 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5412 /* To avoid confusion in tc_gen_reloc, we must ensure
5413 that this does not become a variant frag. */
5414 frag_wane (frag_now
);
5425 if (mips_cpu
== 4650)
5427 as_bad (_("opcode not supported on this processor"));
5430 /* Even on a big endian machine $fn comes before $fn+1. We have
5431 to adjust when loading from memory. */
5434 assert (mips_opts
.isa
== 1);
5435 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5436 target_big_endian
? treg
+ 1 : treg
,
5438 /* FIXME: A possible overflow which I don't know how to deal
5440 offset_expr
.X_add_number
+= 4;
5441 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5442 target_big_endian
? treg
: treg
+ 1,
5445 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5446 does not become a variant frag. */
5447 frag_wane (frag_now
);
5456 * The MIPS assembler seems to check for X_add_number not
5457 * being double aligned and generating:
5460 * addiu at,at,%lo(foo+1)
5463 * But, the resulting address is the same after relocation so why
5464 * generate the extra instruction?
5466 if (mips_cpu
== 4650)
5468 as_bad (_("opcode not supported on this processor"));
5471 /* Itbl support may require additional care here. */
5473 if (mips_opts
.isa
!= 1)
5484 if (mips_cpu
== 4650)
5486 as_bad (_("opcode not supported on this processor"));
5490 if (mips_opts
.isa
!= 1)
5498 /* Itbl support may require additional care here. */
5503 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5514 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5524 if (offset_expr
.X_op
!= O_symbol
5525 && offset_expr
.X_op
!= O_constant
)
5527 as_bad (_("expression too complex"));
5528 offset_expr
.X_op
= O_constant
;
5531 /* Even on a big endian machine $fn comes before $fn+1. We have
5532 to adjust when loading from memory. We set coproc if we must
5533 load $fn+1 first. */
5534 /* Itbl support may require additional care here. */
5535 if (! target_big_endian
)
5538 if (mips_pic
== NO_PIC
5539 || offset_expr
.X_op
== O_constant
)
5541 /* If this is a reference to a GP relative symbol, we want
5542 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5543 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5544 If we have a base register, we use this
5546 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5547 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5548 If this is not a GP relative symbol, we want
5549 lui $at,<sym> (BFD_RELOC_HI16_S)
5550 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5551 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5552 If there is a base register, we add it to $at after the
5553 lui instruction. If there is a constant, we always use
5555 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5556 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5575 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5576 ((bfd_arch_bits_per_address (stdoutput
) == 32
5577 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5578 ? "addu" : "daddu"),
5579 "d,v,t", AT
, breg
, GP
);
5585 /* Itbl support may require additional care here. */
5586 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5587 coproc
? treg
+ 1 : treg
,
5588 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5589 offset_expr
.X_add_number
+= 4;
5591 /* Set mips_optimize to 2 to avoid inserting an
5593 hold_mips_optimize
= mips_optimize
;
5595 /* Itbl support may require additional care here. */
5596 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5597 coproc
? treg
: treg
+ 1,
5598 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5599 mips_optimize
= hold_mips_optimize
;
5601 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5602 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5603 used_at
&& mips_opts
.noat
),
5604 offset_expr
.X_add_symbol
, (offsetT
) 0,
5607 /* We just generated two relocs. When tc_gen_reloc
5608 handles this case, it will skip the first reloc and
5609 handle the second. The second reloc already has an
5610 extra addend of 4, which we added above. We must
5611 subtract it out, and then subtract another 4 to make
5612 the first reloc come out right. The second reloc
5613 will come out right because we are going to add 4 to
5614 offset_expr when we build its instruction below.
5616 If we have a symbol, then we don't want to include
5617 the offset, because it will wind up being included
5618 when we generate the reloc. */
5620 if (offset_expr
.X_op
== O_constant
)
5621 offset_expr
.X_add_number
-= 8;
5624 offset_expr
.X_add_number
= -4;
5625 offset_expr
.X_op
= O_constant
;
5628 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5633 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5634 ((bfd_arch_bits_per_address (stdoutput
) == 32
5635 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5636 ? "addu" : "daddu"),
5637 "d,v,t", AT
, breg
, AT
);
5641 /* Itbl support may require additional care here. */
5642 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5643 coproc
? treg
+ 1 : treg
,
5644 (int) BFD_RELOC_LO16
, AT
);
5647 /* FIXME: How do we handle overflow here? */
5648 offset_expr
.X_add_number
+= 4;
5649 /* Itbl support may require additional care here. */
5650 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5651 coproc
? treg
: treg
+ 1,
5652 (int) BFD_RELOC_LO16
, AT
);
5654 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5658 /* If this is a reference to an external symbol, we want
5659 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5664 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5666 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5667 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5668 If there is a base register we add it to $at before the
5669 lwc1 instructions. If there is a constant we include it
5670 in the lwc1 instructions. */
5672 expr1
.X_add_number
= offset_expr
.X_add_number
;
5673 offset_expr
.X_add_number
= 0;
5674 if (expr1
.X_add_number
< -0x8000
5675 || expr1
.X_add_number
>= 0x8000 - 4)
5676 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5681 frag_grow (24 + off
);
5682 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5683 ((bfd_arch_bits_per_address (stdoutput
) == 32
5684 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5686 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5687 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5689 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5690 ((bfd_arch_bits_per_address (stdoutput
) == 32
5691 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5692 ? "addu" : "daddu"),
5693 "d,v,t", AT
, breg
, AT
);
5694 /* Itbl support may require additional care here. */
5695 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5696 coproc
? treg
+ 1 : treg
,
5697 (int) BFD_RELOC_LO16
, AT
);
5698 expr1
.X_add_number
+= 4;
5700 /* Set mips_optimize to 2 to avoid inserting an undesired
5702 hold_mips_optimize
= mips_optimize
;
5704 /* Itbl support may require additional care here. */
5705 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5706 coproc
? treg
: treg
+ 1,
5707 (int) BFD_RELOC_LO16
, AT
);
5708 mips_optimize
= hold_mips_optimize
;
5710 (void) frag_var (rs_machine_dependent
, 0, 0,
5711 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5712 offset_expr
.X_add_symbol
, (offsetT
) 0,
5715 else if (mips_pic
== SVR4_PIC
)
5719 /* If this is a reference to an external symbol, we want
5720 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5722 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5727 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5729 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5730 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5731 If there is a base register we add it to $at before the
5732 lwc1 instructions. If there is a constant we include it
5733 in the lwc1 instructions. */
5735 expr1
.X_add_number
= offset_expr
.X_add_number
;
5736 offset_expr
.X_add_number
= 0;
5737 if (expr1
.X_add_number
< -0x8000
5738 || expr1
.X_add_number
>= 0x8000 - 4)
5739 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5740 if (reg_needs_delay (GP
))
5749 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5750 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5751 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5752 ((bfd_arch_bits_per_address (stdoutput
) == 32
5753 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5754 ? "addu" : "daddu"),
5755 "d,v,t", AT
, AT
, GP
);
5756 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5757 ((bfd_arch_bits_per_address (stdoutput
) == 32
5758 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5760 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5761 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5764 ((bfd_arch_bits_per_address (stdoutput
) == 32
5765 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5766 ? "addu" : "daddu"),
5767 "d,v,t", AT
, breg
, AT
);
5768 /* Itbl support may require additional care here. */
5769 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5770 coproc
? treg
+ 1 : treg
,
5771 (int) BFD_RELOC_LO16
, AT
);
5772 expr1
.X_add_number
+= 4;
5774 /* Set mips_optimize to 2 to avoid inserting an undesired
5776 hold_mips_optimize
= mips_optimize
;
5778 /* Itbl support may require additional care here. */
5779 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5780 coproc
? treg
: treg
+ 1,
5781 (int) BFD_RELOC_LO16
, AT
);
5782 mips_optimize
= hold_mips_optimize
;
5783 expr1
.X_add_number
-= 4;
5785 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5786 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5787 8 + gpdel
+ off
, 1, 0),
5788 offset_expr
.X_add_symbol
, (offsetT
) 0,
5792 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5795 macro_build (p
, &icnt
, &offset_expr
,
5796 ((bfd_arch_bits_per_address (stdoutput
) == 32
5797 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5799 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5801 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5805 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5806 ((bfd_arch_bits_per_address (stdoutput
) == 32
5807 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5808 ? "addu" : "daddu"),
5809 "d,v,t", AT
, breg
, AT
);
5812 /* Itbl support may require additional care here. */
5813 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5814 coproc
? treg
+ 1 : treg
,
5815 (int) BFD_RELOC_LO16
, AT
);
5817 expr1
.X_add_number
+= 4;
5819 /* Set mips_optimize to 2 to avoid inserting an undesired
5821 hold_mips_optimize
= mips_optimize
;
5823 /* Itbl support may require additional care here. */
5824 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5825 coproc
? treg
: treg
+ 1,
5826 (int) BFD_RELOC_LO16
, AT
);
5827 mips_optimize
= hold_mips_optimize
;
5829 else if (mips_pic
== EMBEDDED_PIC
)
5831 /* If there is no base register, we use
5832 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5833 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5834 If we have a base register, we use
5836 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5837 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5846 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5847 ((bfd_arch_bits_per_address (stdoutput
) == 32
5848 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5849 ? "addu" : "daddu"),
5850 "d,v,t", AT
, breg
, GP
);
5855 /* Itbl support may require additional care here. */
5856 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5857 coproc
? treg
+ 1 : treg
,
5858 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5859 offset_expr
.X_add_number
+= 4;
5860 /* Itbl support may require additional care here. */
5861 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5862 coproc
? treg
: treg
+ 1,
5863 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5879 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5880 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5881 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5882 (int) BFD_RELOC_LO16
, breg
);
5883 offset_expr
.X_add_number
+= 4;
5884 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5885 (int) BFD_RELOC_LO16
, breg
);
5888 /* New code added to support COPZ instructions.
5889 This code builds table entries out of the macros in mip_opcodes.
5890 R4000 uses interlocks to handle coproc delays.
5891 Other chips (like the R3000) require nops to be inserted for delays.
5893 FIXME: Currently, we require that the user handle delays.
5894 In order to fill delay slots for non-interlocked chips,
5895 we must have a way to specify delays based on the coprocessor.
5896 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5897 What are the side-effects of the cop instruction?
5898 What cache support might we have and what are its effects?
5899 Both coprocessor & memory require delays. how long???
5900 What registers are read/set/modified?
5902 If an itbl is provided to interpret cop instructions,
5903 this knowledge can be encoded in the itbl spec. */
5917 /* For now we just do C (same as Cz). The parameter will be
5918 stored in insn_opcode by mips_ip. */
5919 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5923 #ifdef LOSING_COMPILER
5925 /* Try and see if this is a new itbl instruction.
5926 This code builds table entries out of the macros in mip_opcodes.
5927 FIXME: For now we just assemble the expression and pass it's
5928 value along as a 32-bit immediate.
5929 We may want to have the assembler assemble this value,
5930 so that we gain the assembler's knowledge of delay slots,
5932 Would it be more efficient to use mask (id) here? */
5933 if (itbl_have_entries
5934 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5936 s
= ip
->insn_mo
->name
;
5938 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5939 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5946 as_warn (_("Macro used $at after \".set noat\""));
5951 struct mips_cl_insn
*ip
;
5953 register int treg
, sreg
, dreg
, breg
;
5969 bfd_reloc_code_real_type r
;
5972 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5973 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5974 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5975 mask
= ip
->insn_mo
->mask
;
5977 expr1
.X_op
= O_constant
;
5978 expr1
.X_op_symbol
= NULL
;
5979 expr1
.X_add_symbol
= NULL
;
5980 expr1
.X_add_number
= 1;
5984 #endif /* LOSING_COMPILER */
5989 macro_build ((char *) NULL
, &icnt
, NULL
,
5990 dbl
? "dmultu" : "multu",
5992 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5998 /* The MIPS assembler some times generates shifts and adds. I'm
5999 not trying to be that fancy. GCC should do this for us
6001 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6002 macro_build ((char *) NULL
, &icnt
, NULL
,
6003 dbl
? "dmult" : "mult",
6005 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6018 mips_emit_delays (true);
6019 ++mips_opts
.noreorder
;
6020 mips_any_noreorder
= 1;
6022 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6023 macro_build ((char *) NULL
, &icnt
, NULL
,
6024 dbl
? "dmult" : "mult",
6025 "s,t", sreg
, imm
? AT
: treg
);
6026 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6027 macro_build ((char *) NULL
, &icnt
, NULL
,
6028 dbl
? "dsra32" : "sra",
6029 "d,w,<", dreg
, dreg
, 31);
6030 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6032 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6035 expr1
.X_add_number
= 8;
6036 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6037 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6038 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6040 --mips_opts
.noreorder
;
6041 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6054 mips_emit_delays (true);
6055 ++mips_opts
.noreorder
;
6056 mips_any_noreorder
= 1;
6058 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6059 macro_build ((char *) NULL
, &icnt
, NULL
,
6060 dbl
? "dmultu" : "multu",
6061 "s,t", sreg
, imm
? AT
: treg
);
6062 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6063 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6065 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6068 expr1
.X_add_number
= 8;
6069 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6070 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6071 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6073 --mips_opts
.noreorder
;
6077 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6078 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6079 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6081 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6085 if (imm_expr
.X_op
!= O_constant
)
6086 as_bad (_("rotate count too large"));
6087 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6088 (int) (imm_expr
.X_add_number
& 0x1f));
6089 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6090 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6091 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6095 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6096 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6097 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6099 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6103 if (imm_expr
.X_op
!= O_constant
)
6104 as_bad (_("rotate count too large"));
6105 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6106 (int) (imm_expr
.X_add_number
& 0x1f));
6107 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6108 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6109 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6113 if (mips_cpu
== 4650)
6115 as_bad (_("opcode not supported on this processor"));
6118 assert (mips_opts
.isa
== 1);
6119 /* Even on a big endian machine $fn comes before $fn+1. We have
6120 to adjust when storing to memory. */
6121 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6122 target_big_endian
? treg
+ 1 : treg
,
6123 (int) BFD_RELOC_LO16
, breg
);
6124 offset_expr
.X_add_number
+= 4;
6125 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6126 target_big_endian
? treg
: treg
+ 1,
6127 (int) BFD_RELOC_LO16
, breg
);
6132 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6133 treg
, (int) BFD_RELOC_LO16
);
6135 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6136 sreg
, (int) BFD_RELOC_LO16
);
6139 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6141 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6142 dreg
, (int) BFD_RELOC_LO16
);
6147 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6149 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6150 sreg
, (int) BFD_RELOC_LO16
);
6155 as_warn (_("Instruction %s: result is always false"),
6157 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6160 if (imm_expr
.X_op
== O_constant
6161 && imm_expr
.X_add_number
>= 0
6162 && imm_expr
.X_add_number
< 0x10000)
6164 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6165 sreg
, (int) BFD_RELOC_LO16
);
6168 else if (imm_expr
.X_op
== O_constant
6169 && imm_expr
.X_add_number
> -0x8000
6170 && imm_expr
.X_add_number
< 0)
6172 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6173 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6174 ((bfd_arch_bits_per_address (stdoutput
) == 32
6175 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6176 ? "addiu" : "daddiu"),
6177 "t,r,j", dreg
, sreg
,
6178 (int) BFD_RELOC_LO16
);
6183 load_register (&icnt
, AT
, &imm_expr
, 0);
6184 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6188 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6189 (int) BFD_RELOC_LO16
);
6194 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6200 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6201 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6202 (int) BFD_RELOC_LO16
);
6205 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6207 if (imm_expr
.X_op
== O_constant
6208 && imm_expr
.X_add_number
>= -0x8000
6209 && imm_expr
.X_add_number
< 0x8000)
6211 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6212 mask
== M_SGE_I
? "slti" : "sltiu",
6213 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6218 load_register (&icnt
, AT
, &imm_expr
, 0);
6219 macro_build ((char *) NULL
, &icnt
, NULL
,
6220 mask
== M_SGE_I
? "slt" : "sltu",
6221 "d,v,t", dreg
, sreg
, AT
);
6224 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6225 (int) BFD_RELOC_LO16
);
6230 case M_SGT
: /* sreg > treg <==> treg < sreg */
6236 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6239 case M_SGT_I
: /* sreg > I <==> I < sreg */
6245 load_register (&icnt
, AT
, &imm_expr
, 0);
6246 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6249 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6255 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6256 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6257 (int) BFD_RELOC_LO16
);
6260 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6266 load_register (&icnt
, AT
, &imm_expr
, 0);
6267 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6268 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6269 (int) BFD_RELOC_LO16
);
6273 if (imm_expr
.X_op
== O_constant
6274 && imm_expr
.X_add_number
>= -0x8000
6275 && imm_expr
.X_add_number
< 0x8000)
6277 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6278 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6281 load_register (&icnt
, AT
, &imm_expr
, 0);
6282 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6286 if (imm_expr
.X_op
== O_constant
6287 && imm_expr
.X_add_number
>= -0x8000
6288 && imm_expr
.X_add_number
< 0x8000)
6290 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6291 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6294 load_register (&icnt
, AT
, &imm_expr
, 0);
6295 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6301 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6304 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6308 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6310 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6316 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6318 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6324 as_warn (_("Instruction %s: result is always true"),
6326 macro_build ((char *) NULL
, &icnt
, &expr1
,
6327 ((bfd_arch_bits_per_address (stdoutput
) == 32
6328 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6329 ? "addiu" : "daddiu"),
6330 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6333 if (imm_expr
.X_op
== O_constant
6334 && imm_expr
.X_add_number
>= 0
6335 && imm_expr
.X_add_number
< 0x10000)
6337 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6338 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6341 else if (imm_expr
.X_op
== O_constant
6342 && imm_expr
.X_add_number
> -0x8000
6343 && imm_expr
.X_add_number
< 0)
6345 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6346 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6347 ((bfd_arch_bits_per_address (stdoutput
) == 32
6348 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6349 ? "addiu" : "daddiu"),
6350 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6355 load_register (&icnt
, AT
, &imm_expr
, 0);
6356 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6360 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6368 if (imm_expr
.X_op
== O_constant
6369 && imm_expr
.X_add_number
> -0x8000
6370 && imm_expr
.X_add_number
<= 0x8000)
6372 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6373 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6374 dbl
? "daddi" : "addi",
6375 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6378 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6379 macro_build ((char *) NULL
, &icnt
, NULL
,
6380 dbl
? "dsub" : "sub",
6381 "d,v,t", dreg
, sreg
, AT
);
6387 if (imm_expr
.X_op
== O_constant
6388 && imm_expr
.X_add_number
> -0x8000
6389 && imm_expr
.X_add_number
<= 0x8000)
6391 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6392 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6393 dbl
? "daddiu" : "addiu",
6394 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6397 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6398 macro_build ((char *) NULL
, &icnt
, NULL
,
6399 dbl
? "dsubu" : "subu",
6400 "d,v,t", dreg
, sreg
, AT
);
6421 load_register (&icnt
, AT
, &imm_expr
, 0);
6422 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6427 assert (mips_opts
.isa
== 1);
6428 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6429 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6432 * Is the double cfc1 instruction a bug in the mips assembler;
6433 * or is there a reason for it?
6435 mips_emit_delays (true);
6436 ++mips_opts
.noreorder
;
6437 mips_any_noreorder
= 1;
6438 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6439 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6440 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6441 expr1
.X_add_number
= 3;
6442 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6443 (int) BFD_RELOC_LO16
);
6444 expr1
.X_add_number
= 2;
6445 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6446 (int) BFD_RELOC_LO16
);
6447 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6448 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6449 macro_build ((char *) NULL
, &icnt
, NULL
,
6450 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6451 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6452 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6453 --mips_opts
.noreorder
;
6462 if (offset_expr
.X_add_number
>= 0x7fff)
6463 as_bad (_("operand overflow"));
6464 /* avoid load delay */
6465 if (! target_big_endian
)
6466 offset_expr
.X_add_number
+= 1;
6467 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6468 (int) BFD_RELOC_LO16
, breg
);
6469 if (! target_big_endian
)
6470 offset_expr
.X_add_number
-= 1;
6472 offset_expr
.X_add_number
+= 1;
6473 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6474 (int) BFD_RELOC_LO16
, breg
);
6475 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6476 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6489 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6490 as_bad (_("operand overflow"));
6491 if (! target_big_endian
)
6492 offset_expr
.X_add_number
+= off
;
6493 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6494 (int) BFD_RELOC_LO16
, breg
);
6495 if (! target_big_endian
)
6496 offset_expr
.X_add_number
-= off
;
6498 offset_expr
.X_add_number
+= off
;
6499 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6500 (int) BFD_RELOC_LO16
, breg
);
6513 load_address (&icnt
, AT
, &offset_expr
);
6515 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6516 ((bfd_arch_bits_per_address (stdoutput
) == 32
6517 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6518 ? "addu" : "daddu"),
6519 "d,v,t", AT
, AT
, breg
);
6520 if (! target_big_endian
)
6521 expr1
.X_add_number
= off
;
6523 expr1
.X_add_number
= 0;
6524 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6525 (int) BFD_RELOC_LO16
, AT
);
6526 if (! target_big_endian
)
6527 expr1
.X_add_number
= 0;
6529 expr1
.X_add_number
= off
;
6530 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6531 (int) BFD_RELOC_LO16
, AT
);
6536 load_address (&icnt
, AT
, &offset_expr
);
6538 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6539 ((bfd_arch_bits_per_address (stdoutput
) == 32
6540 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6541 ? "addu" : "daddu"),
6542 "d,v,t", AT
, AT
, breg
);
6543 if (target_big_endian
)
6544 expr1
.X_add_number
= 0;
6545 macro_build ((char *) NULL
, &icnt
, &expr1
,
6546 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6547 (int) BFD_RELOC_LO16
, AT
);
6548 if (target_big_endian
)
6549 expr1
.X_add_number
= 1;
6551 expr1
.X_add_number
= 0;
6552 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6553 (int) BFD_RELOC_LO16
, AT
);
6554 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6556 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6561 if (offset_expr
.X_add_number
>= 0x7fff)
6562 as_bad (_("operand overflow"));
6563 if (target_big_endian
)
6564 offset_expr
.X_add_number
+= 1;
6565 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6566 (int) BFD_RELOC_LO16
, breg
);
6567 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6568 if (target_big_endian
)
6569 offset_expr
.X_add_number
-= 1;
6571 offset_expr
.X_add_number
+= 1;
6572 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6573 (int) BFD_RELOC_LO16
, breg
);
6586 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6587 as_bad (_("operand overflow"));
6588 if (! target_big_endian
)
6589 offset_expr
.X_add_number
+= off
;
6590 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6591 (int) BFD_RELOC_LO16
, breg
);
6592 if (! target_big_endian
)
6593 offset_expr
.X_add_number
-= off
;
6595 offset_expr
.X_add_number
+= off
;
6596 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6597 (int) BFD_RELOC_LO16
, breg
);
6610 load_address (&icnt
, AT
, &offset_expr
);
6612 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6613 ((bfd_arch_bits_per_address (stdoutput
) == 32
6614 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6615 ? "addu" : "daddu"),
6616 "d,v,t", AT
, AT
, breg
);
6617 if (! target_big_endian
)
6618 expr1
.X_add_number
= off
;
6620 expr1
.X_add_number
= 0;
6621 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6622 (int) BFD_RELOC_LO16
, AT
);
6623 if (! target_big_endian
)
6624 expr1
.X_add_number
= 0;
6626 expr1
.X_add_number
= off
;
6627 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6628 (int) BFD_RELOC_LO16
, AT
);
6632 load_address (&icnt
, AT
, &offset_expr
);
6634 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6635 ((bfd_arch_bits_per_address (stdoutput
) == 32
6636 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6637 ? "addu" : "daddu"),
6638 "d,v,t", AT
, AT
, breg
);
6639 if (! target_big_endian
)
6640 expr1
.X_add_number
= 0;
6641 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6642 (int) BFD_RELOC_LO16
, AT
);
6643 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6645 if (! target_big_endian
)
6646 expr1
.X_add_number
= 1;
6648 expr1
.X_add_number
= 0;
6649 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6650 (int) BFD_RELOC_LO16
, AT
);
6651 if (! target_big_endian
)
6652 expr1
.X_add_number
= 0;
6654 expr1
.X_add_number
= 1;
6655 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6656 (int) BFD_RELOC_LO16
, AT
);
6657 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6659 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6664 /* FIXME: Check if this is one of the itbl macros, since they
6665 are added dynamically. */
6666 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6670 as_warn (_("Macro used $at after \".set noat\""));
6673 /* Implement macros in mips16 mode. */
6677 struct mips_cl_insn
*ip
;
6680 int xreg
, yreg
, zreg
, tmp
;
6684 const char *s
, *s2
, *s3
;
6686 mask
= ip
->insn_mo
->mask
;
6688 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6689 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6690 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6694 expr1
.X_op
= O_constant
;
6695 expr1
.X_op_symbol
= NULL
;
6696 expr1
.X_add_symbol
= NULL
;
6697 expr1
.X_add_number
= 1;
6716 mips_emit_delays (true);
6717 ++mips_opts
.noreorder
;
6718 mips_any_noreorder
= 1;
6719 macro_build ((char *) NULL
, &icnt
, NULL
,
6720 dbl
? "ddiv" : "div",
6721 "0,x,y", xreg
, yreg
);
6722 expr1
.X_add_number
= 2;
6723 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6724 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6726 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6727 since that causes an overflow. We should do that as well,
6728 but I don't see how to do the comparisons without a temporary
6730 --mips_opts
.noreorder
;
6731 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6750 mips_emit_delays (true);
6751 ++mips_opts
.noreorder
;
6752 mips_any_noreorder
= 1;
6753 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6754 expr1
.X_add_number
= 2;
6755 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6756 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6757 --mips_opts
.noreorder
;
6758 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6764 macro_build ((char *) NULL
, &icnt
, NULL
,
6765 dbl
? "dmultu" : "multu",
6767 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6775 if (imm_expr
.X_op
!= O_constant
)
6776 as_bad (_("Unsupported large constant"));
6777 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6778 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6779 dbl
? "daddiu" : "addiu",
6780 "y,x,4", yreg
, xreg
);
6784 if (imm_expr
.X_op
!= O_constant
)
6785 as_bad (_("Unsupported large constant"));
6786 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6787 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6792 if (imm_expr
.X_op
!= O_constant
)
6793 as_bad (_("Unsupported large constant"));
6794 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6795 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6818 goto do_reverse_branch
;
6822 goto do_reverse_branch
;
6834 goto do_reverse_branch
;
6845 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6847 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6874 goto do_addone_branch_i
;
6879 goto do_addone_branch_i
;
6894 goto do_addone_branch_i
;
6901 if (imm_expr
.X_op
!= O_constant
)
6902 as_bad (_("Unsupported large constant"));
6903 ++imm_expr
.X_add_number
;
6906 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6907 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6911 expr1
.X_add_number
= 0;
6912 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6914 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6915 "move", "y,X", xreg
, yreg
);
6916 expr1
.X_add_number
= 2;
6917 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6918 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6919 "neg", "x,w", xreg
, xreg
);
6923 /* For consistency checking, verify that all bits are specified either
6924 by the match/mask part of the instruction definition, or by the
6927 validate_mips_insn (opc
)
6928 const struct mips_opcode
*opc
;
6930 const char *p
= opc
->args
;
6932 unsigned long used_bits
= opc
->mask
;
6934 if ((used_bits
& opc
->match
) != opc
->match
)
6936 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6937 opc
->name
, opc
->args
);
6940 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6947 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6948 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6950 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6951 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6952 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6953 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6955 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6958 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6959 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6960 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6961 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6962 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6963 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6964 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6965 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6966 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6967 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6968 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6970 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6971 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6972 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6973 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6975 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6976 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6977 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6978 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6979 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6980 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6981 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6982 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6983 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6986 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6988 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6989 c
, opc
->name
, opc
->args
);
6993 if (used_bits
!= 0xffffffff)
6995 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6996 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7002 /* This routine assembles an instruction into its binary format. As a
7003 side effect, it sets one of the global variables imm_reloc or
7004 offset_reloc to the type of relocation to do if one of the operands
7005 is an address expression. */
7010 struct mips_cl_insn
*ip
;
7015 struct mips_opcode
*insn
;
7018 unsigned int lastregno
= 0;
7021 int full_opcode_match
= 1;
7025 /* If the instruction contains a '.', we first try to match an instruction
7026 including the '.'. Then we try again without the '.'. */
7028 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
7031 /* If we stopped on whitespace, then replace the whitespace with null for
7032 the call to hash_find. Save the character we replaced just in case we
7033 have to re-parse the instruction. */
7034 if (isspace ((unsigned char) *s
))
7040 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7042 /* If we didn't find the instruction in the opcode table, try again, but
7043 this time with just the instruction up to, but not including the
7047 /* Restore the character we overwrite above (if any). */
7051 /* Scan up to the first '.' or whitespace. */
7052 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7055 /* If we did not find a '.', then we can quit now. */
7058 insn_error
= "unrecognized opcode";
7062 /* Lookup the instruction in the hash table. */
7064 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7066 insn_error
= "unrecognized opcode";
7070 full_opcode_match
= 0;
7078 assert (strcmp (insn
->name
, str
) == 0);
7080 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7085 if (insn
->pinfo
!= INSN_MACRO
)
7087 if (mips_cpu
== 4650 && (insn
->pinfo
& FP_D
) != 0)
7093 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7094 && strcmp (insn
->name
, insn
[1].name
) == 0)
7101 static char buf
[100];
7103 _("opcode not supported on this processor: %d (MIPS%d)"),
7104 mips_cpu
, mips_opts
.isa
);
7112 ip
->insn_opcode
= insn
->match
;
7113 for (args
= insn
->args
;; ++args
)
7119 case '\0': /* end of args */
7132 ip
->insn_opcode
|= lastregno
<< 21;
7137 ip
->insn_opcode
|= lastregno
<< 16;
7141 ip
->insn_opcode
|= lastregno
<< 11;
7147 /* Handle optional base register.
7148 Either the base register is omitted or
7149 we must have a left paren. */
7150 /* This is dependent on the next operand specifier
7151 is a base register specification. */
7152 assert (args
[1] == 'b' || args
[1] == '5'
7153 || args
[1] == '-' || args
[1] == '4');
7157 case ')': /* these must match exactly */
7162 case '<': /* must be at least one digit */
7164 * According to the manual, if the shift amount is greater
7165 * than 31 or less than 0 the the shift amount should be
7166 * mod 32. In reality the mips assembler issues an error.
7167 * We issue a warning and mask out all but the low 5 bits.
7169 my_getExpression (&imm_expr
, s
);
7170 check_absolute_expr (ip
, &imm_expr
);
7171 if ((unsigned long) imm_expr
.X_add_number
> 31)
7173 as_warn (_("Improper shift amount (%ld)"),
7174 (long) imm_expr
.X_add_number
);
7175 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7177 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7178 imm_expr
.X_op
= O_absent
;
7182 case '>': /* shift amount minus 32 */
7183 my_getExpression (&imm_expr
, s
);
7184 check_absolute_expr (ip
, &imm_expr
);
7185 if ((unsigned long) imm_expr
.X_add_number
< 32
7186 || (unsigned long) imm_expr
.X_add_number
> 63)
7188 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7189 imm_expr
.X_op
= O_absent
;
7194 case 'k': /* cache code */
7195 case 'h': /* prefx code */
7196 my_getExpression (&imm_expr
, s
);
7197 check_absolute_expr (ip
, &imm_expr
);
7198 if ((unsigned long) imm_expr
.X_add_number
> 31)
7200 as_warn (_("Invalid value for `%s' (%lu)"),
7202 (unsigned long) imm_expr
.X_add_number
);
7203 imm_expr
.X_add_number
&= 0x1f;
7206 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7208 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7209 imm_expr
.X_op
= O_absent
;
7213 case 'c': /* break code */
7214 my_getExpression (&imm_expr
, s
);
7215 check_absolute_expr (ip
, &imm_expr
);
7216 if ((unsigned) imm_expr
.X_add_number
> 1023)
7218 as_warn (_("Illegal break code (%ld)"),
7219 (long) imm_expr
.X_add_number
);
7220 imm_expr
.X_add_number
&= 0x3ff;
7222 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7223 imm_expr
.X_op
= O_absent
;
7227 case 'q': /* lower break code */
7228 my_getExpression (&imm_expr
, s
);
7229 check_absolute_expr (ip
, &imm_expr
);
7230 if ((unsigned) imm_expr
.X_add_number
> 1023)
7232 as_warn (_("Illegal lower break code (%ld)"),
7233 (long) imm_expr
.X_add_number
);
7234 imm_expr
.X_add_number
&= 0x3ff;
7236 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7237 imm_expr
.X_op
= O_absent
;
7241 case 'B': /* syscall code */
7242 my_getExpression (&imm_expr
, s
);
7243 check_absolute_expr (ip
, &imm_expr
);
7244 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7245 as_warn (_("Illegal syscall code (%ld)"),
7246 (long) imm_expr
.X_add_number
);
7247 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7248 imm_expr
.X_op
= O_absent
;
7252 case 'C': /* Coprocessor code */
7253 my_getExpression (&imm_expr
, s
);
7254 check_absolute_expr (ip
, &imm_expr
);
7255 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7257 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7258 (long) imm_expr
.X_add_number
);
7259 imm_expr
.X_add_number
&= ((1<<25) - 1);
7261 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7262 imm_expr
.X_op
= O_absent
;
7266 case 'P': /* Performance register */
7267 my_getExpression (&imm_expr
, s
);
7268 check_absolute_expr (ip
, &imm_expr
);
7269 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7271 as_warn (_("Invalidate performance regster (%ld)"),
7272 (long) imm_expr
.X_add_number
);
7273 imm_expr
.X_add_number
&= 1;
7275 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7276 imm_expr
.X_op
= O_absent
;
7280 case 'b': /* base register */
7281 case 'd': /* destination register */
7282 case 's': /* source register */
7283 case 't': /* target register */
7284 case 'r': /* both target and source */
7285 case 'v': /* both dest and source */
7286 case 'w': /* both dest and target */
7287 case 'E': /* coprocessor target register */
7288 case 'G': /* coprocessor destination register */
7289 case 'x': /* ignore register name */
7290 case 'z': /* must be zero register */
7295 if (isdigit ((unsigned char) s
[1]))
7305 while (isdigit ((unsigned char) *s
));
7307 as_bad (_("Invalid register number (%d)"), regno
);
7309 else if (*args
== 'E' || *args
== 'G')
7313 if (s
[1] == 'f' && s
[2] == 'p')
7318 else if (s
[1] == 's' && s
[2] == 'p')
7323 else if (s
[1] == 'g' && s
[2] == 'p')
7328 else if (s
[1] == 'a' && s
[2] == 't')
7333 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7338 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7343 else if (itbl_have_entries
)
7348 p
= s
+ 1; /* advance past '$' */
7349 n
= itbl_get_field (&p
); /* n is name */
7351 /* See if this is a register defined in an
7353 if (itbl_get_reg_val (n
, &r
))
7355 /* Get_field advances to the start of
7356 the next field, so we need to back
7357 rack to the end of the last field. */
7361 s
= strchr (s
, '\0');
7374 as_warn (_("Used $at without \".set noat\""));
7380 if (c
== 'r' || c
== 'v' || c
== 'w')
7387 /* 'z' only matches $0. */
7388 if (c
== 'z' && regno
!= 0)
7391 /* Now that we have assembled one operand, we use the args string
7392 * to figure out where it goes in the instruction. */
7399 ip
->insn_opcode
|= regno
<< 21;
7403 ip
->insn_opcode
|= regno
<< 11;
7408 ip
->insn_opcode
|= regno
<< 16;
7411 /* This case exists because on the r3000 trunc
7412 expands into a macro which requires a gp
7413 register. On the r6000 or r4000 it is
7414 assembled into a single instruction which
7415 ignores the register. Thus the insn version
7416 is MIPS_ISA2 and uses 'x', and the macro
7417 version is MIPS_ISA1 and uses 't'. */
7420 /* This case is for the div instruction, which
7421 acts differently if the destination argument
7422 is $0. This only matches $0, and is checked
7423 outside the switch. */
7426 /* Itbl operand; not yet implemented. FIXME ?? */
7428 /* What about all other operands like 'i', which
7429 can be specified in the opcode table? */
7439 ip
->insn_opcode
|= lastregno
<< 21;
7442 ip
->insn_opcode
|= lastregno
<< 16;
7447 case 'D': /* floating point destination register */
7448 case 'S': /* floating point source register */
7449 case 'T': /* floating point target register */
7450 case 'R': /* floating point source register */
7454 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7464 while (isdigit ((unsigned char) *s
));
7467 as_bad (_("Invalid float register number (%d)"), regno
);
7469 if ((regno
& 1) != 0
7470 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7471 && ! (strcmp (str
, "mtc1") == 0
7472 || strcmp (str
, "mfc1") == 0
7473 || strcmp (str
, "lwc1") == 0
7474 || strcmp (str
, "swc1") == 0
7475 || strcmp (str
, "l.s") == 0
7476 || strcmp (str
, "s.s") == 0))
7477 as_warn (_("Float register should be even, was %d"),
7485 if (c
== 'V' || c
== 'W')
7495 ip
->insn_opcode
|= regno
<< 6;
7499 ip
->insn_opcode
|= regno
<< 11;
7503 ip
->insn_opcode
|= regno
<< 16;
7506 ip
->insn_opcode
|= regno
<< 21;
7517 ip
->insn_opcode
|= lastregno
<< 11;
7520 ip
->insn_opcode
|= lastregno
<< 16;
7526 my_getExpression (&imm_expr
, s
);
7527 if (imm_expr
.X_op
!= O_big
7528 && imm_expr
.X_op
!= O_constant
)
7529 insn_error
= _("absolute expression required");
7534 my_getExpression (&offset_expr
, s
);
7535 imm_reloc
= BFD_RELOC_32
;
7547 unsigned char temp
[8];
7549 unsigned int length
;
7554 /* These only appear as the last operand in an
7555 instruction, and every instruction that accepts
7556 them in any variant accepts them in all variants.
7557 This means we don't have to worry about backing out
7558 any changes if the instruction does not match.
7560 The difference between them is the size of the
7561 floating point constant and where it goes. For 'F'
7562 and 'L' the constant is 64 bits; for 'f' and 'l' it
7563 is 32 bits. Where the constant is placed is based
7564 on how the MIPS assembler does things:
7567 f -- immediate value
7570 The .lit4 and .lit8 sections are only used if
7571 permitted by the -G argument.
7573 When generating embedded PIC code, we use the
7574 .lit8 section but not the .lit4 section (we can do
7575 .lit4 inline easily; we need to put .lit8
7576 somewhere in the data segment, and using .lit8
7577 permits the linker to eventually combine identical
7580 f64
= *args
== 'F' || *args
== 'L';
7582 save_in
= input_line_pointer
;
7583 input_line_pointer
= s
;
7584 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7586 s
= input_line_pointer
;
7587 input_line_pointer
= save_in
;
7588 if (err
!= NULL
&& *err
!= '\0')
7590 as_bad (_("Bad floating point constant: %s"), err
);
7591 memset (temp
, '\0', sizeof temp
);
7592 length
= f64
? 8 : 4;
7595 assert (length
== (f64
? 8 : 4));
7599 && (! USE_GLOBAL_POINTER_OPT
7600 || mips_pic
== EMBEDDED_PIC
7601 || g_switch_value
< 4
7602 || (temp
[0] == 0 && temp
[1] == 0)
7603 || (temp
[2] == 0 && temp
[3] == 0))))
7605 imm_expr
.X_op
= O_constant
;
7606 if (! target_big_endian
)
7607 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7609 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7612 && ! mips_disable_float_construction
7613 && ((temp
[0] == 0 && temp
[1] == 0)
7614 || (temp
[2] == 0 && temp
[3] == 0))
7615 && ((temp
[4] == 0 && temp
[5] == 0)
7616 || (temp
[6] == 0 && temp
[7] == 0)))
7618 /* The value is simple enough to load with a
7619 couple of instructions. In mips1 mode, set
7620 imm_expr to the high order 32 bits and
7621 offset_expr to the low order 32 bits.
7622 Otherwise, set imm_expr to the entire 64 bit
7624 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7626 imm_expr
.X_op
= O_constant
;
7627 offset_expr
.X_op
= O_constant
;
7628 if (! target_big_endian
)
7630 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7631 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7635 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7636 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7638 if (offset_expr
.X_add_number
== 0)
7639 offset_expr
.X_op
= O_absent
;
7641 else if (sizeof (imm_expr
.X_add_number
) > 4)
7643 imm_expr
.X_op
= O_constant
;
7644 if (! target_big_endian
)
7645 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7647 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7651 imm_expr
.X_op
= O_big
;
7652 imm_expr
.X_add_number
= 4;
7653 if (! target_big_endian
)
7655 generic_bignum
[0] = bfd_getl16 (temp
);
7656 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7657 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7658 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7662 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7663 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7664 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7665 generic_bignum
[3] = bfd_getb16 (temp
);
7671 const char *newname
;
7674 /* Switch to the right section. */
7676 subseg
= now_subseg
;
7679 default: /* unused default case avoids warnings. */
7681 newname
= RDATA_SECTION_NAME
;
7682 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7683 || mips_pic
== EMBEDDED_PIC
)
7687 if (mips_pic
== EMBEDDED_PIC
)
7690 newname
= RDATA_SECTION_NAME
;
7693 assert (!USE_GLOBAL_POINTER_OPT
7694 || g_switch_value
>= 4);
7698 new_seg
= subseg_new (newname
, (subsegT
) 0);
7699 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7700 bfd_set_section_flags (stdoutput
, new_seg
,
7705 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7706 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7707 && strcmp (TARGET_OS
, "elf") != 0)
7708 record_alignment (new_seg
, 4);
7710 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7712 as_bad (_("Can't use floating point insn in this section"));
7714 /* Set the argument to the current address in the
7716 offset_expr
.X_op
= O_symbol
;
7717 offset_expr
.X_add_symbol
=
7718 symbol_new ("L0\001", now_seg
,
7719 (valueT
) frag_now_fix (), frag_now
);
7720 offset_expr
.X_add_number
= 0;
7722 /* Put the floating point number into the section. */
7723 p
= frag_more ((int) length
);
7724 memcpy (p
, temp
, length
);
7726 /* Switch back to the original section. */
7727 subseg_set (seg
, subseg
);
7732 case 'i': /* 16 bit unsigned immediate */
7733 case 'j': /* 16 bit signed immediate */
7734 imm_reloc
= BFD_RELOC_LO16
;
7735 c
= my_getSmallExpression (&imm_expr
, s
);
7740 if (imm_expr
.X_op
== O_constant
)
7741 imm_expr
.X_add_number
=
7742 (imm_expr
.X_add_number
>> 16) & 0xffff;
7745 imm_reloc
= BFD_RELOC_HI16_S
;
7746 imm_unmatched_hi
= true;
7749 imm_reloc
= BFD_RELOC_HI16
;
7751 else if (imm_expr
.X_op
== O_constant
)
7752 imm_expr
.X_add_number
&= 0xffff;
7756 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7757 || ((imm_expr
.X_add_number
< 0
7758 || imm_expr
.X_add_number
>= 0x10000)
7759 && imm_expr
.X_op
== O_constant
))
7761 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7762 !strcmp (insn
->name
, insn
[1].name
))
7764 if (imm_expr
.X_op
== O_constant
7765 || imm_expr
.X_op
== O_big
)
7766 as_bad (_("16 bit expression not in range 0..65535"));
7774 /* The upper bound should be 0x8000, but
7775 unfortunately the MIPS assembler accepts numbers
7776 from 0x8000 to 0xffff and sign extends them, and
7777 we want to be compatible. We only permit this
7778 extended range for an instruction which does not
7779 provide any further alternates, since those
7780 alternates may handle other cases. People should
7781 use the numbers they mean, rather than relying on
7782 a mysterious sign extension. */
7783 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7784 strcmp (insn
->name
, insn
[1].name
) == 0);
7789 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7790 || ((imm_expr
.X_add_number
< -0x8000
7791 || imm_expr
.X_add_number
>= max
)
7792 && imm_expr
.X_op
== O_constant
)
7794 && imm_expr
.X_add_number
< 0
7795 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7796 && imm_expr
.X_unsigned
7797 && sizeof (imm_expr
.X_add_number
) <= 4))
7801 if (imm_expr
.X_op
== O_constant
7802 || imm_expr
.X_op
== O_big
)
7803 as_bad (_("16 bit expression not in range -32768..32767"));
7809 case 'o': /* 16 bit offset */
7810 c
= my_getSmallExpression (&offset_expr
, s
);
7812 /* If this value won't fit into a 16 bit offset, then go
7813 find a macro that will generate the 32 bit offset
7814 code pattern. As a special hack, we accept the
7815 difference of two local symbols as a constant. This
7816 is required to suppose embedded PIC switches, which
7817 use an instruction which looks like
7818 lw $4,$L12-$LS12($4)
7819 The problem with handling this in a more general
7820 fashion is that the macro function doesn't expect to
7821 see anything which can be handled in a single
7822 constant instruction. */
7824 && (offset_expr
.X_op
!= O_constant
7825 || offset_expr
.X_add_number
>= 0x8000
7826 || offset_expr
.X_add_number
< -0x8000)
7827 && (mips_pic
!= EMBEDDED_PIC
7828 || offset_expr
.X_op
!= O_subtract
7829 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7833 if (c
== 'h' || c
== 'H')
7835 if (offset_expr
.X_op
!= O_constant
)
7837 offset_expr
.X_add_number
=
7838 (offset_expr
.X_add_number
>> 16) & 0xffff;
7840 offset_reloc
= BFD_RELOC_LO16
;
7844 case 'p': /* pc relative offset */
7845 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7846 my_getExpression (&offset_expr
, s
);
7850 case 'u': /* upper 16 bits */
7851 c
= my_getSmallExpression (&imm_expr
, s
);
7852 imm_reloc
= BFD_RELOC_LO16
;
7857 if (imm_expr
.X_op
== O_constant
)
7858 imm_expr
.X_add_number
=
7859 (imm_expr
.X_add_number
>> 16) & 0xffff;
7862 imm_reloc
= BFD_RELOC_HI16_S
;
7863 imm_unmatched_hi
= true;
7866 imm_reloc
= BFD_RELOC_HI16
;
7868 else if (imm_expr
.X_op
== O_constant
)
7869 imm_expr
.X_add_number
&= 0xffff;
7871 if (imm_expr
.X_op
== O_constant
7872 && (imm_expr
.X_add_number
< 0
7873 || imm_expr
.X_add_number
>= 0x10000))
7874 as_bad (_("lui expression not in range 0..65535"));
7878 case 'a': /* 26 bit address */
7879 my_getExpression (&offset_expr
, s
);
7881 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7884 case 'N': /* 3 bit branch condition code */
7885 case 'M': /* 3 bit compare condition code */
7886 if (strncmp (s
, "$fcc", 4) != 0)
7896 while (isdigit ((unsigned char) *s
));
7898 as_bad (_("invalid condition code register $fcc%d"), regno
);
7900 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7902 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7906 as_bad (_("bad char = '%c'\n"), *args
);
7911 /* Args don't match. */
7912 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7913 !strcmp (insn
->name
, insn
[1].name
))
7919 insn_error
= _("illegal operands");
7924 /* This routine assembles an instruction into its binary format when
7925 assembling for the mips16. As a side effect, it sets one of the
7926 global variables imm_reloc or offset_reloc to the type of
7927 relocation to do if one of the operands is an address expression.
7928 It also sets mips16_small and mips16_ext if the user explicitly
7929 requested a small or extended instruction. */
7934 struct mips_cl_insn
*ip
;
7938 struct mips_opcode
*insn
;
7941 unsigned int lastregno
= 0;
7946 mips16_small
= false;
7949 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7961 if (s
[1] == 't' && s
[2] == ' ')
7964 mips16_small
= true;
7968 else if (s
[1] == 'e' && s
[2] == ' ')
7977 insn_error
= _("unknown opcode");
7981 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7982 mips16_small
= true;
7984 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7986 insn_error
= _("unrecognized opcode");
7993 assert (strcmp (insn
->name
, str
) == 0);
7996 ip
->insn_opcode
= insn
->match
;
7997 ip
->use_extend
= false;
7998 imm_expr
.X_op
= O_absent
;
7999 imm_reloc
= BFD_RELOC_UNUSED
;
8000 offset_expr
.X_op
= O_absent
;
8001 offset_reloc
= BFD_RELOC_UNUSED
;
8002 for (args
= insn
->args
; 1; ++args
)
8009 /* In this switch statement we call break if we did not find
8010 a match, continue if we did find a match, or return if we
8019 /* Stuff the immediate value in now, if we can. */
8020 if (imm_expr
.X_op
== O_constant
8021 && imm_reloc
> BFD_RELOC_UNUSED
8022 && insn
->pinfo
!= INSN_MACRO
)
8024 mips16_immed ((char *) NULL
, 0,
8025 imm_reloc
- BFD_RELOC_UNUSED
,
8026 imm_expr
.X_add_number
, true, mips16_small
,
8027 mips16_ext
, &ip
->insn_opcode
,
8028 &ip
->use_extend
, &ip
->extend
);
8029 imm_expr
.X_op
= O_absent
;
8030 imm_reloc
= BFD_RELOC_UNUSED
;
8044 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8047 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8063 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8065 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8082 if (isdigit ((unsigned char) s
[1]))
8092 while (isdigit ((unsigned char) *s
));
8095 as_bad (_("invalid register number (%d)"), regno
);
8101 if (s
[1] == 'f' && s
[2] == 'p')
8106 else if (s
[1] == 's' && s
[2] == 'p')
8111 else if (s
[1] == 'g' && s
[2] == 'p')
8116 else if (s
[1] == 'a' && s
[2] == 't')
8121 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8126 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8139 if (c
== 'v' || c
== 'w')
8141 regno
= mips16_to_32_reg_map
[lastregno
];
8155 regno
= mips32_to_16_reg_map
[regno
];
8160 regno
= ILLEGAL_REG
;
8165 regno
= ILLEGAL_REG
;
8170 regno
= ILLEGAL_REG
;
8175 if (regno
== AT
&& ! mips_opts
.noat
)
8176 as_warn (_("used $at without \".set noat\""));
8183 if (regno
== ILLEGAL_REG
)
8190 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8194 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8197 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8200 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8206 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8209 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8210 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8220 if (strncmp (s
, "$pc", 3) == 0)
8244 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8246 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8247 and generate the appropriate reloc. If the text
8248 inside %gprel is not a symbol name with an
8249 optional offset, then we generate a normal reloc
8250 and will probably fail later. */
8251 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8252 if (imm_expr
.X_op
== O_symbol
)
8255 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8257 ip
->use_extend
= true;
8264 /* Just pick up a normal expression. */
8265 my_getExpression (&imm_expr
, s
);
8268 if (imm_expr
.X_op
== O_register
)
8270 /* What we thought was an expression turned out to
8273 if (s
[0] == '(' && args
[1] == '(')
8275 /* It looks like the expression was omitted
8276 before a register indirection, which means
8277 that the expression is implicitly zero. We
8278 still set up imm_expr, so that we handle
8279 explicit extensions correctly. */
8280 imm_expr
.X_op
= O_constant
;
8281 imm_expr
.X_add_number
= 0;
8282 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8289 /* We need to relax this instruction. */
8290 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8299 /* We use offset_reloc rather than imm_reloc for the PC
8300 relative operands. This lets macros with both
8301 immediate and address operands work correctly. */
8302 my_getExpression (&offset_expr
, s
);
8304 if (offset_expr
.X_op
== O_register
)
8307 /* We need to relax this instruction. */
8308 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8312 case '6': /* break code */
8313 my_getExpression (&imm_expr
, s
);
8314 check_absolute_expr (ip
, &imm_expr
);
8315 if ((unsigned long) imm_expr
.X_add_number
> 63)
8317 as_warn (_("Invalid value for `%s' (%lu)"),
8319 (unsigned long) imm_expr
.X_add_number
);
8320 imm_expr
.X_add_number
&= 0x3f;
8322 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8323 imm_expr
.X_op
= O_absent
;
8327 case 'a': /* 26 bit address */
8328 my_getExpression (&offset_expr
, s
);
8330 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8331 ip
->insn_opcode
<<= 16;
8334 case 'l': /* register list for entry macro */
8335 case 'L': /* register list for exit macro */
8345 int freg
, reg1
, reg2
;
8347 while (*s
== ' ' || *s
== ',')
8351 as_bad (_("can't parse register list"));
8363 while (isdigit ((unsigned char) *s
))
8385 as_bad (_("invalid register list"));
8390 while (isdigit ((unsigned char) *s
))
8397 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8402 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8407 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8408 mask
|= (reg2
- 3) << 3;
8409 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8410 mask
|= (reg2
- 15) << 1;
8411 else if (reg1
== 31 && reg2
== 31)
8415 as_bad (_("invalid register list"));
8419 /* The mask is filled in in the opcode table for the
8420 benefit of the disassembler. We remove it before
8421 applying the actual mask. */
8422 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8423 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8427 case 'e': /* extend code */
8428 my_getExpression (&imm_expr
, s
);
8429 check_absolute_expr (ip
, &imm_expr
);
8430 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8432 as_warn (_("Invalid value for `%s' (%lu)"),
8434 (unsigned long) imm_expr
.X_add_number
);
8435 imm_expr
.X_add_number
&= 0x7ff;
8437 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8438 imm_expr
.X_op
= O_absent
;
8448 /* Args don't match. */
8449 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8450 strcmp (insn
->name
, insn
[1].name
) == 0)
8457 insn_error
= _("illegal operands");
8463 /* This structure holds information we know about a mips16 immediate
8466 struct mips16_immed_operand
8468 /* The type code used in the argument string in the opcode table. */
8470 /* The number of bits in the short form of the opcode. */
8472 /* The number of bits in the extended form of the opcode. */
8474 /* The amount by which the short form is shifted when it is used;
8475 for example, the sw instruction has a shift count of 2. */
8477 /* The amount by which the short form is shifted when it is stored
8478 into the instruction code. */
8480 /* Non-zero if the short form is unsigned. */
8482 /* Non-zero if the extended form is unsigned. */
8484 /* Non-zero if the value is PC relative. */
8488 /* The mips16 immediate operand types. */
8490 static const struct mips16_immed_operand mips16_immed_operands
[] =
8492 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8493 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8494 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8495 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8496 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8497 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8498 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8499 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8500 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8501 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8502 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8503 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8504 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8505 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8506 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8507 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8508 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8509 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8510 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8511 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8512 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8515 #define MIPS16_NUM_IMMED \
8516 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8518 /* Handle a mips16 instruction with an immediate value. This or's the
8519 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8520 whether an extended value is needed; if one is needed, it sets
8521 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8522 If SMALL is true, an unextended opcode was explicitly requested.
8523 If EXT is true, an extended opcode was explicitly requested. If
8524 WARN is true, warn if EXT does not match reality. */
8527 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8536 unsigned long *insn
;
8537 boolean
*use_extend
;
8538 unsigned short *extend
;
8540 register const struct mips16_immed_operand
*op
;
8541 int mintiny
, maxtiny
;
8544 op
= mips16_immed_operands
;
8545 while (op
->type
!= type
)
8548 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8553 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8556 maxtiny
= 1 << op
->nbits
;
8561 maxtiny
= (1 << op
->nbits
) - 1;
8566 mintiny
= - (1 << (op
->nbits
- 1));
8567 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8570 /* Branch offsets have an implicit 0 in the lowest bit. */
8571 if (type
== 'p' || type
== 'q')
8574 if ((val
& ((1 << op
->shift
) - 1)) != 0
8575 || val
< (mintiny
<< op
->shift
)
8576 || val
> (maxtiny
<< op
->shift
))
8581 if (warn
&& ext
&& ! needext
)
8582 as_warn_where (file
, line
, _("extended operand requested but not required"));
8583 if (small
&& needext
)
8584 as_bad_where (file
, line
, _("invalid unextended operand value"));
8586 if (small
|| (! ext
&& ! needext
))
8590 *use_extend
= false;
8591 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8592 insnval
<<= op
->op_shift
;
8597 long minext
, maxext
;
8603 maxext
= (1 << op
->extbits
) - 1;
8607 minext
= - (1 << (op
->extbits
- 1));
8608 maxext
= (1 << (op
->extbits
- 1)) - 1;
8610 if (val
< minext
|| val
> maxext
)
8611 as_bad_where (file
, line
,
8612 _("operand value out of range for instruction"));
8615 if (op
->extbits
== 16)
8617 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8620 else if (op
->extbits
== 15)
8622 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8627 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8631 *extend
= (unsigned short) extval
;
8640 my_getSmallExpression (ep
, str
)
8651 ((str
[1] == 'h' && str
[2] == 'i')
8652 || (str
[1] == 'H' && str
[2] == 'I')
8653 || (str
[1] == 'l' && str
[2] == 'o'))
8665 * A small expression may be followed by a base register.
8666 * Scan to the end of this operand, and then back over a possible
8667 * base register. Then scan the small expression up to that
8668 * point. (Based on code in sparc.c...)
8670 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8672 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8674 if (isdigit ((unsigned char) sp
[-2]))
8676 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8678 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8684 else if (sp
- 5 >= str
8687 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8688 || (sp
[-3] == 's' && sp
[-2] == 'p')
8689 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8690 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8696 /* no expression means zero offset */
8699 /* %xx(reg) is an error */
8700 ep
->X_op
= O_absent
;
8705 ep
->X_op
= O_constant
;
8708 ep
->X_add_symbol
= NULL
;
8709 ep
->X_op_symbol
= NULL
;
8710 ep
->X_add_number
= 0;
8715 my_getExpression (ep
, str
);
8722 my_getExpression (ep
, str
);
8723 return c
; /* => %hi or %lo encountered */
8727 my_getExpression (ep
, str
)
8733 save_in
= input_line_pointer
;
8734 input_line_pointer
= str
;
8736 expr_end
= input_line_pointer
;
8737 input_line_pointer
= save_in
;
8739 /* If we are in mips16 mode, and this is an expression based on `.',
8740 then we bump the value of the symbol by 1 since that is how other
8741 text symbols are handled. We don't bother to handle complex
8742 expressions, just `.' plus or minus a constant. */
8743 if (mips_opts
.mips16
8744 && ep
->X_op
== O_symbol
8745 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8746 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8747 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8748 && symbol_constant_p (ep
->X_add_symbol
)
8749 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8750 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8753 /* Turn a string in input_line_pointer into a floating point constant
8754 of type TYPE, and store the appropriate bytes in *LITP. The number
8755 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8756 returned, or NULL on OK. */
8759 md_atof (type
, litP
, sizeP
)
8765 LITTLENUM_TYPE words
[4];
8781 return _("bad call to md_atof");
8784 t
= atof_ieee (input_line_pointer
, type
, words
);
8786 input_line_pointer
= t
;
8790 if (! target_big_endian
)
8792 for (i
= prec
- 1; i
>= 0; i
--)
8794 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8800 for (i
= 0; i
< prec
; i
++)
8802 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8811 md_number_to_chars (buf
, val
, n
)
8816 if (target_big_endian
)
8817 number_to_chars_bigendian (buf
, val
, n
);
8819 number_to_chars_littleendian (buf
, val
, n
);
8822 CONST
char *md_shortopts
= "O::g::G:";
8824 struct option md_longopts
[] = {
8825 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8826 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8827 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8828 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8829 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8830 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8831 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8832 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8833 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8834 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8835 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8836 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8837 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8839 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8840 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8842 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8843 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8844 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8845 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8846 {"break", no_argument
, NULL
, OPTION_BREAK
},
8847 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8848 #define OPTION_EB (OPTION_MD_BASE + 11)
8849 {"EB", no_argument
, NULL
, OPTION_EB
},
8850 #define OPTION_EL (OPTION_MD_BASE + 12)
8851 {"EL", no_argument
, NULL
, OPTION_EL
},
8852 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8853 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8854 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8855 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8856 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8857 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8858 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8859 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8860 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8861 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8862 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8863 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8865 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8866 #define OPTION_32 (OPTION_MD_BASE + 20)
8867 #define OPTION_64 (OPTION_MD_BASE + 21)
8869 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8870 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8871 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8872 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8874 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8875 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8876 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8877 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8879 #define OPTION_MABI (OPTION_MD_BASE + 38)
8880 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8882 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 39)
8883 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8884 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 40)
8885 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8888 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8889 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8890 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8891 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8892 {"32", no_argument
, NULL
, OPTION_32
},
8893 {"64", no_argument
, NULL
, OPTION_64
},
8896 #define OPTION_GP32 (OPTION_MD_BASE + 41)
8897 #define OPTION_GP64 (OPTION_MD_BASE + 42)
8898 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8899 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8901 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 43)
8902 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
8904 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 44)
8905 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
8907 {NULL
, no_argument
, NULL
, 0}
8909 size_t md_longopts_size
= sizeof(md_longopts
);
8912 md_parse_option (c
, arg
)
8918 case OPTION_CONSTRUCT_FLOATS
:
8919 mips_disable_float_construction
= 0;
8922 case OPTION_NO_CONSTRUCT_FLOATS
:
8923 mips_disable_float_construction
= 1;
8935 target_big_endian
= 1;
8939 target_big_endian
= 0;
8943 if (arg
&& arg
[1] == '0')
8953 mips_debug
= atoi (arg
);
8954 /* When the MIPS assembler sees -g or -g2, it does not do
8955 optimizations which limit full symbolic debugging. We take
8956 that to be equivalent to -O0. */
8957 if (mips_debug
== 2)
8981 /* Identify the processor type */
8983 if (strcmp (p
, "default") == 0
8984 || strcmp (p
, "DEFAULT") == 0)
8990 /* We need to cope with the various "vr" prefixes for the 4300
8992 if (*p
== 'v' || *p
== 'V')
8998 if (*p
== 'r' || *p
== 'R')
9005 if (strcmp (p
, "10000") == 0
9006 || strcmp (p
, "10k") == 0
9007 || strcmp (p
, "10K") == 0)
9012 if (strcmp (p
, "2000") == 0
9013 || strcmp (p
, "2k") == 0
9014 || strcmp (p
, "2K") == 0)
9019 if (strcmp (p
, "3000") == 0
9020 || strcmp (p
, "3k") == 0
9021 || strcmp (p
, "3K") == 0)
9023 else if (strcmp (p
, "3900") == 0)
9028 if (strcmp (p
, "4000") == 0
9029 || strcmp (p
, "4k") == 0
9030 || strcmp (p
, "4K") == 0)
9032 else if (strcmp (p
, "4100") == 0)
9034 else if (strcmp (p
, "4111") == 0)
9036 else if (strcmp (p
, "4300") == 0)
9038 else if (strcmp (p
, "4400") == 0)
9040 else if (strcmp (p
, "4600") == 0)
9042 else if (strcmp (p
, "4650") == 0)
9044 else if (strcmp (p
, "4010") == 0)
9049 if (strcmp (p
, "5000") == 0
9050 || strcmp (p
, "5k") == 0
9051 || strcmp (p
, "5K") == 0)
9056 if (strcmp (p
, "6000") == 0
9057 || strcmp (p
, "6k") == 0
9058 || strcmp (p
, "6K") == 0)
9063 if (strcmp (p
, "8000") == 0
9064 || strcmp (p
, "8k") == 0
9065 || strcmp (p
, "8K") == 0)
9070 if (strcmp (p
, "orion") == 0)
9076 switch (atoi (p
+ 1))
9092 && (mips_cpu
!= 4300
9095 && mips_cpu
!= 5000))
9097 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9103 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9114 case OPTION_NO_M4650
:
9121 case OPTION_NO_M4010
:
9128 case OPTION_NO_M4100
:
9136 case OPTION_NO_M3900
:
9140 mips_opts
.mips16
= 1;
9141 mips_no_prev_insn (false);
9144 case OPTION_NO_MIPS16
:
9145 mips_opts
.mips16
= 0;
9146 mips_no_prev_insn (false);
9149 case OPTION_MEMBEDDED_PIC
:
9150 mips_pic
= EMBEDDED_PIC
;
9151 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9153 as_bad (_("-G may not be used with embedded PIC code"));
9156 g_switch_value
= 0x7fffffff;
9159 /* When generating ELF code, we permit -KPIC and -call_shared to
9160 select SVR4_PIC, and -non_shared to select no PIC. This is
9161 intended to be compatible with Irix 5. */
9162 case OPTION_CALL_SHARED
:
9163 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9165 as_bad (_("-call_shared is supported only for ELF format"));
9168 mips_pic
= SVR4_PIC
;
9169 if (g_switch_seen
&& g_switch_value
!= 0)
9171 as_bad (_("-G may not be used with SVR4 PIC code"));
9177 case OPTION_NON_SHARED
:
9178 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9180 as_bad (_("-non_shared is supported only for ELF format"));
9186 /* The -xgot option tells the assembler to use 32 offsets when
9187 accessing the got in SVR4_PIC mode. It is for Irix
9194 if (! USE_GLOBAL_POINTER_OPT
)
9196 as_bad (_("-G is not supported for this configuration"));
9199 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9201 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9205 g_switch_value
= atoi (arg
);
9209 /* The -32 and -64 options tell the assembler to output the 32
9210 bit or the 64 bit MIPS ELF format. */
9217 const char **list
, **l
;
9219 list
= bfd_target_list ();
9220 for (l
= list
; *l
!= NULL
; l
++)
9221 if (strcmp (*l
, "elf64-bigmips") == 0
9222 || strcmp (*l
, "elf64-littlemips") == 0)
9225 as_fatal (_("No compiled in support for 64 bit object file format"));
9235 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9236 flag in object files because to do so would make it
9237 impossible to link with libraries compiled without "-gp32".
9238 This is unnecessarily restrictive.
9240 We could solve this problem by adding "-gp32" multilibs to
9241 gcc, but to set this flag before gcc is built with such
9242 multilibs will break too many systems. */
9244 /* mips_32bitmode = 1; */
9250 /* mips_32bitmode = 0; */
9254 if (strcmp (arg
,"32") == 0
9255 || strcmp (arg
,"n32") == 0
9256 || strcmp (arg
,"64") == 0
9257 || strcmp (arg
,"o64") == 0
9258 || strcmp (arg
,"eabi") == 0)
9259 mips_abi_string
= arg
;
9262 case OPTION_M7000_HILO_FIX
:
9263 mips_7000_hilo_fix
= true;
9266 case OPTION_NO_M7000_HILO_FIX
:
9267 mips_7000_hilo_fix
= false;
9279 show (stream
, string
, col_p
, first_p
)
9287 fprintf (stream
, "%24s", "");
9292 fprintf (stream
, ", ");
9296 if (*col_p
+ strlen (string
) > 72)
9298 fprintf (stream
, "\n%24s", "");
9302 fprintf (stream
, "%s", string
);
9303 *col_p
+= strlen (string
);
9310 md_show_usage (stream
)
9315 fprintf(stream
, _("\
9317 -membedded-pic generate embedded position independent code\n\
9318 -EB generate big endian output\n\
9319 -EL generate little endian output\n\
9320 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9321 -G NUM allow referencing objects up to NUM bytes\n\
9322 implicitly with the gp register [default 8]\n"));
9323 fprintf(stream
, _("\
9324 -mips1 generate MIPS ISA I instructions\n\
9325 -mips2 generate MIPS ISA II instructions\n\
9326 -mips3 generate MIPS ISA III instructions\n\
9327 -mips4 generate MIPS ISA IV instructions\n\
9328 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9332 show (stream
, "2000", &column
, &first
);
9333 show (stream
, "3000", &column
, &first
);
9334 show (stream
, "3900", &column
, &first
);
9335 show (stream
, "4000", &column
, &first
);
9336 show (stream
, "4010", &column
, &first
);
9337 show (stream
, "4100", &column
, &first
);
9338 show (stream
, "4111", &column
, &first
);
9339 show (stream
, "4300", &column
, &first
);
9340 show (stream
, "4400", &column
, &first
);
9341 show (stream
, "4600", &column
, &first
);
9342 show (stream
, "4650", &column
, &first
);
9343 show (stream
, "5000", &column
, &first
);
9344 show (stream
, "6000", &column
, &first
);
9345 show (stream
, "8000", &column
, &first
);
9346 show (stream
, "10000", &column
, &first
);
9347 fputc ('\n', stream
);
9349 fprintf (stream
, _("\
9350 -mCPU equivalent to -mcpu=CPU.\n\
9351 -no-mCPU don't generate code specific to CPU.\n\
9352 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9356 show (stream
, "3900", &column
, &first
);
9357 show (stream
, "4010", &column
, &first
);
9358 show (stream
, "4100", &column
, &first
);
9359 show (stream
, "4650", &column
, &first
);
9360 fputc ('\n', stream
);
9362 fprintf(stream
, _("\
9363 -mips16 generate mips16 instructions\n\
9364 -no-mips16 do not generate mips16 instructions\n"));
9365 fprintf(stream
, _("\
9366 -O0 remove unneeded NOPs, do not swap branches\n\
9367 -O remove unneeded NOPs and swap branches\n\
9368 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9369 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9370 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9372 fprintf(stream
, _("\
9373 -KPIC, -call_shared generate SVR4 position independent code\n\
9374 -non_shared do not generate position independent code\n\
9375 -xgot assume a 32 bit GOT\n\
9376 -32 create 32 bit object file (default)\n\
9377 -64 create 64 bit object file\n"));
9382 mips_init_after_args ()
9384 /* initialize opcodes */
9385 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9386 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9390 md_pcrel_from (fixP
)
9393 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9394 && fixP
->fx_addsy
!= (symbolS
*) NULL
9395 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9397 /* This makes a branch to an undefined symbol be a branch to the
9398 current location. */
9402 /* return the address of the delay slot */
9403 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9406 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9407 reloc for a cons. We could use the definition there, except that
9408 we want to handle 64 bit relocs specially. */
9411 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9412 fragS
*frag ATTRIBUTE_UNUSED
;
9414 unsigned int nbytes
;
9418 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9420 if (nbytes
== 8 && ! mips_64
)
9422 if (target_big_endian
)
9428 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9429 as_bad (_("Unsupported reloc size %d"), nbytes
);
9431 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9434 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9437 /* This is called before the symbol table is processed. In order to
9438 work with gcc when using mips-tfile, we must keep all local labels.
9439 However, in other cases, we want to discard them. If we were
9440 called with -g, but we didn't see any debugging information, it may
9441 mean that gcc is smuggling debugging information through to
9442 mips-tfile, in which case we must generate all local labels. */
9445 mips_frob_file_before_adjust ()
9447 #ifndef NO_ECOFF_DEBUGGING
9450 && ! ecoff_debugging_seen
)
9451 flag_keep_locals
= 1;
9455 /* Sort any unmatched HI16_S relocs so that they immediately precede
9456 the corresponding LO reloc. This is called before md_apply_fix and
9457 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9458 explicit use of the %hi modifier. */
9463 struct mips_hi_fixup
*l
;
9465 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9467 segment_info_type
*seginfo
;
9470 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9472 /* Check quickly whether the next fixup happens to be a matching
9474 if (l
->fixp
->fx_next
!= NULL
9475 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9476 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9477 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9480 /* Look through the fixups for this segment for a matching %lo.
9481 When we find one, move the %hi just in front of it. We do
9482 this in two passes. In the first pass, we try to find a
9483 unique %lo. In the second pass, we permit multiple %hi
9484 relocs for a single %lo (this is a GNU extension). */
9485 seginfo
= seg_info (l
->seg
);
9486 for (pass
= 0; pass
< 2; pass
++)
9491 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9493 /* Check whether this is a %lo fixup which matches l->fixp. */
9494 if (f
->fx_r_type
== BFD_RELOC_LO16
9495 && f
->fx_addsy
== l
->fixp
->fx_addsy
9496 && f
->fx_offset
== l
->fixp
->fx_offset
9499 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9500 || prev
->fx_addsy
!= f
->fx_addsy
9501 || prev
->fx_offset
!= f
->fx_offset
))
9505 /* Move l->fixp before f. */
9506 for (pf
= &seginfo
->fix_root
;
9508 pf
= &(*pf
)->fx_next
)
9509 assert (*pf
!= NULL
);
9511 *pf
= l
->fixp
->fx_next
;
9513 l
->fixp
->fx_next
= f
;
9515 seginfo
->fix_root
= l
->fixp
;
9517 prev
->fx_next
= l
->fixp
;
9528 #if 0 /* GCC code motion plus incomplete dead code elimination
9529 can leave a %hi without a %lo. */
9531 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9532 _("Unmatched %%hi reloc"));
9538 /* When generating embedded PIC code we need to use a special
9539 relocation to represent the difference of two symbols in the .text
9540 section (switch tables use a difference of this sort). See
9541 include/coff/mips.h for details. This macro checks whether this
9542 fixup requires the special reloc. */
9543 #define SWITCH_TABLE(fixp) \
9544 ((fixp)->fx_r_type == BFD_RELOC_32 \
9545 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9546 && (fixp)->fx_addsy != NULL \
9547 && (fixp)->fx_subsy != NULL \
9548 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9549 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9551 /* When generating embedded PIC code we must keep all PC relative
9552 relocations, in case the linker has to relax a call. We also need
9553 to keep relocations for switch table entries. */
9557 mips_force_relocation (fixp
)
9560 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9561 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9564 return (mips_pic
== EMBEDDED_PIC
9566 || SWITCH_TABLE (fixp
)
9567 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9568 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9571 /* Apply a fixup to the object file. */
9574 md_apply_fix (fixP
, valueP
)
9581 assert (fixP
->fx_size
== 4
9582 || fixP
->fx_r_type
== BFD_RELOC_16
9583 || fixP
->fx_r_type
== BFD_RELOC_64
9584 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9585 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9589 /* If we aren't adjusting this fixup to be against the section
9590 symbol, we need to adjust the value. */
9592 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9594 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9595 || S_IS_WEAK (fixP
->fx_addsy
)
9596 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9597 && (((bfd_get_section_flags (stdoutput
,
9598 S_GET_SEGMENT (fixP
->fx_addsy
))
9599 & SEC_LINK_ONCE
) != 0)
9600 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9602 sizeof (".gnu.linkonce") - 1))))
9605 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9606 if (value
!= 0 && ! fixP
->fx_pcrel
)
9608 /* In this case, the bfd_install_relocation routine will
9609 incorrectly add the symbol value back in. We just want
9610 the addend to appear in the object file.
9611 FIXME: If this makes VALUE zero, we're toast. */
9612 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9616 /* This code was generated using trial and error and so is
9617 fragile and not trustworthy. If you change it, you should
9618 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9620 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9622 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9624 /* BFD's REL handling, for MIPS, is _very_ weird.
9625 This gives the right results, but it can't possibly
9626 be the way things are supposed to work. */
9627 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9628 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9629 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9634 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9636 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9639 switch (fixP
->fx_r_type
)
9641 case BFD_RELOC_MIPS_JMP
:
9642 case BFD_RELOC_HI16
:
9643 case BFD_RELOC_HI16_S
:
9644 case BFD_RELOC_MIPS_GPREL
:
9645 case BFD_RELOC_MIPS_LITERAL
:
9646 case BFD_RELOC_MIPS_CALL16
:
9647 case BFD_RELOC_MIPS_GOT16
:
9648 case BFD_RELOC_MIPS_GPREL32
:
9649 case BFD_RELOC_MIPS_GOT_HI16
:
9650 case BFD_RELOC_MIPS_GOT_LO16
:
9651 case BFD_RELOC_MIPS_CALL_HI16
:
9652 case BFD_RELOC_MIPS_CALL_LO16
:
9653 case BFD_RELOC_MIPS16_GPREL
:
9655 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9656 _("Invalid PC relative reloc"));
9657 /* Nothing needed to do. The value comes from the reloc entry */
9660 case BFD_RELOC_MIPS16_JMP
:
9661 /* We currently always generate a reloc against a symbol, which
9662 means that we don't want an addend even if the symbol is
9664 fixP
->fx_addnumber
= 0;
9667 case BFD_RELOC_PCREL_HI16_S
:
9668 /* The addend for this is tricky if it is internal, so we just
9669 do everything here rather than in bfd_install_relocation. */
9670 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9675 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9677 /* For an external symbol adjust by the address to make it
9678 pcrel_offset. We use the address of the RELLO reloc
9679 which follows this one. */
9680 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9681 + fixP
->fx_next
->fx_where
);
9686 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9687 if (target_big_endian
)
9689 md_number_to_chars (buf
, value
, 2);
9692 case BFD_RELOC_PCREL_LO16
:
9693 /* The addend for this is tricky if it is internal, so we just
9694 do everything here rather than in bfd_install_relocation. */
9695 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9700 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9701 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9702 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9703 if (target_big_endian
)
9705 md_number_to_chars (buf
, value
, 2);
9709 /* This is handled like BFD_RELOC_32, but we output a sign
9710 extended value if we are only 32 bits. */
9712 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9714 if (8 <= sizeof (valueT
))
9715 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9722 w1
= w2
= fixP
->fx_where
;
9723 if (target_big_endian
)
9727 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9728 if ((value
& 0x80000000) != 0)
9732 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9739 /* If we are deleting this reloc entry, we must fill in the
9740 value now. This can happen if we have a .word which is not
9741 resolved when it appears but is later defined. We also need
9742 to fill in the value if this is an embedded PIC switch table
9745 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9746 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9751 /* If we are deleting this reloc entry, we must fill in the
9753 assert (fixP
->fx_size
== 2);
9755 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9759 case BFD_RELOC_LO16
:
9760 /* When handling an embedded PIC switch statement, we can wind
9761 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9764 if (value
< -0x8000 || value
> 0x7fff)
9765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9766 _("relocation overflow"));
9767 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9768 if (target_big_endian
)
9770 md_number_to_chars (buf
, value
, 2);
9774 case BFD_RELOC_16_PCREL_S2
:
9776 * We need to save the bits in the instruction since fixup_segment()
9777 * might be deleting the relocation entry (i.e., a branch within
9778 * the current segment).
9780 if ((value
& 0x3) != 0)
9781 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9782 _("Branch to odd address (%lx)"), value
);
9784 if (!fixP
->fx_done
&& value
!= 0)
9786 /* If 'value' is zero, the remaining reloc code won't actually
9787 do the store, so it must be done here. This is probably
9790 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9794 /* update old instruction data */
9795 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9796 if (target_big_endian
)
9797 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9799 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9801 if (value
>= -0x8000 && value
< 0x8000)
9802 insn
|= value
& 0xffff;
9805 /* The branch offset is too large. If this is an
9806 unconditional branch, and we are not generating PIC code,
9807 we can convert it to an absolute jump instruction. */
9808 if (mips_pic
== NO_PIC
9810 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9811 && (fixP
->fx_frag
->fr_address
9812 < text_section
->vma
+ text_section
->_raw_size
)
9813 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9814 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9815 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9817 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9818 insn
= 0x0c000000; /* jal */
9820 insn
= 0x08000000; /* j */
9821 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9823 fixP
->fx_addsy
= section_symbol (text_section
);
9824 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9828 /* FIXME. It would be possible in principle to handle
9829 conditional branches which overflow. They could be
9830 transformed into a branch around a jump. This would
9831 require setting up variant frags for each different
9832 branch type. The native MIPS assembler attempts to
9833 handle these cases, but it appears to do it
9835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9836 _("Branch out of range"));
9840 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9843 case BFD_RELOC_VTABLE_INHERIT
:
9846 && !S_IS_DEFINED (fixP
->fx_addsy
)
9847 && !S_IS_WEAK (fixP
->fx_addsy
))
9848 S_SET_WEAK (fixP
->fx_addsy
);
9851 case BFD_RELOC_VTABLE_ENTRY
:
9867 const struct mips_opcode
*p
;
9868 int treg
, sreg
, dreg
, shamt
;
9873 for (i
= 0; i
< NUMOPCODES
; ++i
)
9875 p
= &mips_opcodes
[i
];
9876 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9878 printf ("%08lx %s\t", oc
, p
->name
);
9879 treg
= (oc
>> 16) & 0x1f;
9880 sreg
= (oc
>> 21) & 0x1f;
9881 dreg
= (oc
>> 11) & 0x1f;
9882 shamt
= (oc
>> 6) & 0x1f;
9884 for (args
= p
->args
;; ++args
)
9895 printf ("%c", *args
);
9899 assert (treg
== sreg
);
9900 printf ("$%d,$%d", treg
, sreg
);
9905 printf ("$%d", dreg
);
9910 printf ("$%d", treg
);
9914 printf ("0x%x", treg
);
9919 printf ("$%d", sreg
);
9923 printf ("0x%08lx", oc
& 0x1ffffff);
9935 printf ("$%d", shamt
);
9946 printf (_("%08lx UNDEFINED\n"), oc
);
9957 name
= input_line_pointer
;
9958 c
= get_symbol_end ();
9959 p
= (symbolS
*) symbol_find_or_make (name
);
9960 *input_line_pointer
= c
;
9964 /* Align the current frag to a given power of two. The MIPS assembler
9965 also automatically adjusts any preceding label. */
9968 mips_align (to
, fill
, label
)
9973 mips_emit_delays (false);
9974 frag_align (to
, fill
, 0);
9975 record_alignment (now_seg
, to
);
9978 assert (S_GET_SEGMENT (label
) == now_seg
);
9979 symbol_set_frag (label
, frag_now
);
9980 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9984 /* Align to a given power of two. .align 0 turns off the automatic
9985 alignment used by the data creating pseudo-ops. */
9989 int x ATTRIBUTE_UNUSED
;
9992 register long temp_fill
;
9993 long max_alignment
= 15;
9997 o Note that the assembler pulls down any immediately preceeding label
9998 to the aligned address.
9999 o It's not documented but auto alignment is reinstated by
10000 a .align pseudo instruction.
10001 o Note also that after auto alignment is turned off the mips assembler
10002 issues an error on attempt to assemble an improperly aligned data item.
10007 temp
= get_absolute_expression ();
10008 if (temp
> max_alignment
)
10009 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10012 as_warn (_("Alignment negative: 0 assumed."));
10015 if (*input_line_pointer
== ',')
10017 input_line_pointer
++;
10018 temp_fill
= get_absolute_expression ();
10025 mips_align (temp
, (int) temp_fill
,
10026 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10033 demand_empty_rest_of_line ();
10037 mips_flush_pending_output ()
10039 mips_emit_delays (false);
10040 mips_clear_insn_labels ();
10049 /* When generating embedded PIC code, we only use the .text, .lit8,
10050 .sdata and .sbss sections. We change the .data and .rdata
10051 pseudo-ops to use .sdata. */
10052 if (mips_pic
== EMBEDDED_PIC
10053 && (sec
== 'd' || sec
== 'r'))
10057 /* The ELF backend needs to know that we are changing sections, so
10058 that .previous works correctly. We could do something like check
10059 for a obj_section_change_hook macro, but that might be confusing
10060 as it would not be appropriate to use it in the section changing
10061 functions in read.c, since obj-elf.c intercepts those. FIXME:
10062 This should be cleaner, somehow. */
10063 obj_elf_section_change_hook ();
10066 mips_emit_delays (false);
10076 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10077 demand_empty_rest_of_line ();
10081 if (USE_GLOBAL_POINTER_OPT
)
10083 seg
= subseg_new (RDATA_SECTION_NAME
,
10084 (subsegT
) get_absolute_expression ());
10085 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10087 bfd_set_section_flags (stdoutput
, seg
,
10093 if (strcmp (TARGET_OS
, "elf") != 0)
10094 record_alignment (seg
, 4);
10096 demand_empty_rest_of_line ();
10100 as_bad (_("No read only data section in this object file format"));
10101 demand_empty_rest_of_line ();
10107 if (USE_GLOBAL_POINTER_OPT
)
10109 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10110 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10112 bfd_set_section_flags (stdoutput
, seg
,
10113 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10115 if (strcmp (TARGET_OS
, "elf") != 0)
10116 record_alignment (seg
, 4);
10118 demand_empty_rest_of_line ();
10123 as_bad (_("Global pointers not supported; recompile -G 0"));
10124 demand_empty_rest_of_line ();
10133 mips_enable_auto_align ()
10144 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10145 mips_emit_delays (false);
10146 if (log_size
> 0 && auto_align
)
10147 mips_align (log_size
, 0, label
);
10148 mips_clear_insn_labels ();
10149 cons (1 << log_size
);
10153 s_float_cons (type
)
10158 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10160 mips_emit_delays (false);
10165 mips_align (3, 0, label
);
10167 mips_align (2, 0, label
);
10170 mips_clear_insn_labels ();
10175 /* Handle .globl. We need to override it because on Irix 5 you are
10178 where foo is an undefined symbol, to mean that foo should be
10179 considered to be the address of a function. */
10183 int x ATTRIBUTE_UNUSED
;
10190 name
= input_line_pointer
;
10191 c
= get_symbol_end ();
10192 symbolP
= symbol_find_or_make (name
);
10193 *input_line_pointer
= c
;
10194 SKIP_WHITESPACE ();
10196 /* On Irix 5, every global symbol that is not explicitly labelled as
10197 being a function is apparently labelled as being an object. */
10200 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10205 secname
= input_line_pointer
;
10206 c
= get_symbol_end ();
10207 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10209 as_bad (_("%s: no such section"), secname
);
10210 *input_line_pointer
= c
;
10212 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10213 flag
= BSF_FUNCTION
;
10216 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10218 S_SET_EXTERNAL (symbolP
);
10219 demand_empty_rest_of_line ();
10224 int x ATTRIBUTE_UNUSED
;
10229 opt
= input_line_pointer
;
10230 c
= get_symbol_end ();
10234 /* FIXME: What does this mean? */
10236 else if (strncmp (opt
, "pic", 3) == 0)
10240 i
= atoi (opt
+ 3);
10244 mips_pic
= SVR4_PIC
;
10246 as_bad (_(".option pic%d not supported"), i
);
10248 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10250 if (g_switch_seen
&& g_switch_value
!= 0)
10251 as_warn (_("-G may not be used with SVR4 PIC code"));
10252 g_switch_value
= 0;
10253 bfd_set_gp_size (stdoutput
, 0);
10257 as_warn (_("Unrecognized option \"%s\""), opt
);
10259 *input_line_pointer
= c
;
10260 demand_empty_rest_of_line ();
10263 /* This structure is used to hold a stack of .set values. */
10265 struct mips_option_stack
10267 struct mips_option_stack
*next
;
10268 struct mips_set_options options
;
10271 static struct mips_option_stack
*mips_opts_stack
;
10273 /* Handle the .set pseudo-op. */
10277 int x ATTRIBUTE_UNUSED
;
10279 char *name
= input_line_pointer
, ch
;
10281 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10282 input_line_pointer
++;
10283 ch
= *input_line_pointer
;
10284 *input_line_pointer
= '\0';
10286 if (strcmp (name
, "reorder") == 0)
10288 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10290 /* If we still have pending nops, we can discard them. The
10291 usual nop handling will insert any that are still
10293 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10294 * (mips_opts
.mips16
? 2 : 4));
10295 prev_nop_frag
= NULL
;
10297 mips_opts
.noreorder
= 0;
10299 else if (strcmp (name
, "noreorder") == 0)
10301 mips_emit_delays (true);
10302 mips_opts
.noreorder
= 1;
10303 mips_any_noreorder
= 1;
10305 else if (strcmp (name
, "at") == 0)
10307 mips_opts
.noat
= 0;
10309 else if (strcmp (name
, "noat") == 0)
10311 mips_opts
.noat
= 1;
10313 else if (strcmp (name
, "macro") == 0)
10315 mips_opts
.warn_about_macros
= 0;
10317 else if (strcmp (name
, "nomacro") == 0)
10319 if (mips_opts
.noreorder
== 0)
10320 as_bad (_("`noreorder' must be set before `nomacro'"));
10321 mips_opts
.warn_about_macros
= 1;
10323 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10325 mips_opts
.nomove
= 0;
10327 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10329 mips_opts
.nomove
= 1;
10331 else if (strcmp (name
, "bopt") == 0)
10333 mips_opts
.nobopt
= 0;
10335 else if (strcmp (name
, "nobopt") == 0)
10337 mips_opts
.nobopt
= 1;
10339 else if (strcmp (name
, "mips16") == 0
10340 || strcmp (name
, "MIPS-16") == 0)
10341 mips_opts
.mips16
= 1;
10342 else if (strcmp (name
, "nomips16") == 0
10343 || strcmp (name
, "noMIPS-16") == 0)
10344 mips_opts
.mips16
= 0;
10345 else if (strncmp (name
, "mips", 4) == 0)
10349 /* Permit the user to change the ISA on the fly. Needless to
10350 say, misuse can cause serious problems. */
10351 isa
= atoi (name
+ 4);
10353 mips_opts
.isa
= file_mips_isa
;
10354 else if (isa
< 1 || isa
> 4)
10355 as_bad (_("unknown ISA level"));
10357 mips_opts
.isa
= isa
;
10359 else if (strcmp (name
, "autoextend") == 0)
10360 mips_opts
.noautoextend
= 0;
10361 else if (strcmp (name
, "noautoextend") == 0)
10362 mips_opts
.noautoextend
= 1;
10363 else if (strcmp (name
, "push") == 0)
10365 struct mips_option_stack
*s
;
10367 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10368 s
->next
= mips_opts_stack
;
10369 s
->options
= mips_opts
;
10370 mips_opts_stack
= s
;
10372 else if (strcmp (name
, "pop") == 0)
10374 struct mips_option_stack
*s
;
10376 s
= mips_opts_stack
;
10378 as_bad (_(".set pop with no .set push"));
10381 /* If we're changing the reorder mode we need to handle
10382 delay slots correctly. */
10383 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10384 mips_emit_delays (true);
10385 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10387 if (prev_nop_frag
!= NULL
)
10389 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10390 * (mips_opts
.mips16
? 2 : 4));
10391 prev_nop_frag
= NULL
;
10395 mips_opts
= s
->options
;
10396 mips_opts_stack
= s
->next
;
10402 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10404 *input_line_pointer
= ch
;
10405 demand_empty_rest_of_line ();
10408 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10409 .option pic2. It means to generate SVR4 PIC calls. */
10412 s_abicalls (ignore
)
10413 int ignore ATTRIBUTE_UNUSED
;
10415 mips_pic
= SVR4_PIC
;
10416 if (USE_GLOBAL_POINTER_OPT
)
10418 if (g_switch_seen
&& g_switch_value
!= 0)
10419 as_warn (_("-G may not be used with SVR4 PIC code"));
10420 g_switch_value
= 0;
10422 bfd_set_gp_size (stdoutput
, 0);
10423 demand_empty_rest_of_line ();
10426 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10427 PIC code. It sets the $gp register for the function based on the
10428 function address, which is in the register named in the argument.
10429 This uses a relocation against _gp_disp, which is handled specially
10430 by the linker. The result is:
10431 lui $gp,%hi(_gp_disp)
10432 addiu $gp,$gp,%lo(_gp_disp)
10433 addu $gp,$gp,.cpload argument
10434 The .cpload argument is normally $25 == $t9. */
10438 int ignore ATTRIBUTE_UNUSED
;
10443 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10444 if (mips_pic
!= SVR4_PIC
)
10450 /* .cpload should be a in .set noreorder section. */
10451 if (mips_opts
.noreorder
== 0)
10452 as_warn (_(".cpload not in noreorder section"));
10454 ex
.X_op
= O_symbol
;
10455 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10456 ex
.X_op_symbol
= NULL
;
10457 ex
.X_add_number
= 0;
10459 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10460 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10462 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10463 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10464 (int) BFD_RELOC_LO16
);
10466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10467 GP
, GP
, tc_get_register (0));
10469 demand_empty_rest_of_line ();
10472 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10473 offset from $sp. The offset is remembered, and after making a PIC
10474 call $gp is restored from that location. */
10477 s_cprestore (ignore
)
10478 int ignore ATTRIBUTE_UNUSED
;
10483 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10484 if (mips_pic
!= SVR4_PIC
)
10490 mips_cprestore_offset
= get_absolute_expression ();
10492 ex
.X_op
= O_constant
;
10493 ex
.X_add_symbol
= NULL
;
10494 ex
.X_op_symbol
= NULL
;
10495 ex
.X_add_number
= mips_cprestore_offset
;
10497 macro_build ((char *) NULL
, &icnt
, &ex
,
10498 ((bfd_arch_bits_per_address (stdoutput
) == 32
10499 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10501 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10503 demand_empty_rest_of_line ();
10506 /* Handle the .gpword pseudo-op. This is used when generating PIC
10507 code. It generates a 32 bit GP relative reloc. */
10511 int ignore ATTRIBUTE_UNUSED
;
10517 /* When not generating PIC code, this is treated as .word. */
10518 if (mips_pic
!= SVR4_PIC
)
10524 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10525 mips_emit_delays (true);
10527 mips_align (2, 0, label
);
10528 mips_clear_insn_labels ();
10532 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10534 as_bad (_("Unsupported use of .gpword"));
10535 ignore_rest_of_line ();
10539 md_number_to_chars (p
, (valueT
) 0, 4);
10540 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10541 BFD_RELOC_MIPS_GPREL32
);
10543 demand_empty_rest_of_line ();
10546 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10547 tables in SVR4 PIC code. */
10551 int ignore ATTRIBUTE_UNUSED
;
10556 /* This is ignored when not generating SVR4 PIC code. */
10557 if (mips_pic
!= SVR4_PIC
)
10563 /* Add $gp to the register named as an argument. */
10564 reg
= tc_get_register (0);
10565 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10566 ((bfd_arch_bits_per_address (stdoutput
) == 32
10567 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10568 ? "addu" : "daddu"),
10569 "d,v,t", reg
, reg
, GP
);
10571 demand_empty_rest_of_line ();
10574 /* Handle the .insn pseudo-op. This marks instruction labels in
10575 mips16 mode. This permits the linker to handle them specially,
10576 such as generating jalx instructions when needed. We also make
10577 them odd for the duration of the assembly, in order to generate the
10578 right sort of code. We will make them even in the adjust_symtab
10579 routine, while leaving them marked. This is convenient for the
10580 debugger and the disassembler. The linker knows to make them odd
10585 int ignore ATTRIBUTE_UNUSED
;
10587 if (mips_opts
.mips16
)
10588 mips16_mark_labels ();
10590 demand_empty_rest_of_line ();
10593 /* Handle a .stabn directive. We need these in order to mark a label
10594 as being a mips16 text label correctly. Sometimes the compiler
10595 will emit a label, followed by a .stabn, and then switch sections.
10596 If the label and .stabn are in mips16 mode, then the label is
10597 really a mips16 text label. */
10603 if (type
== 'n' && mips_opts
.mips16
)
10604 mips16_mark_labels ();
10609 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10613 s_mips_weakext (ignore
)
10614 int ignore ATTRIBUTE_UNUSED
;
10621 name
= input_line_pointer
;
10622 c
= get_symbol_end ();
10623 symbolP
= symbol_find_or_make (name
);
10624 S_SET_WEAK (symbolP
);
10625 *input_line_pointer
= c
;
10627 SKIP_WHITESPACE ();
10629 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10631 if (S_IS_DEFINED (symbolP
))
10633 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10634 S_GET_NAME (symbolP
));
10635 ignore_rest_of_line ();
10639 if (*input_line_pointer
== ',')
10641 ++input_line_pointer
;
10642 SKIP_WHITESPACE ();
10646 if (exp
.X_op
!= O_symbol
)
10648 as_bad ("bad .weakext directive");
10649 ignore_rest_of_line();
10652 symbol_set_value_expression (symbolP
, &exp
);
10655 demand_empty_rest_of_line ();
10658 /* Parse a register string into a number. Called from the ECOFF code
10659 to parse .frame. The argument is non-zero if this is the frame
10660 register, so that we can record it in mips_frame_reg. */
10663 tc_get_register (frame
)
10668 SKIP_WHITESPACE ();
10669 if (*input_line_pointer
++ != '$')
10671 as_warn (_("expected `$'"));
10674 else if (isdigit ((unsigned char) *input_line_pointer
))
10676 reg
= get_absolute_expression ();
10677 if (reg
< 0 || reg
>= 32)
10679 as_warn (_("Bad register number"));
10685 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10687 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10689 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10691 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10695 as_warn (_("Unrecognized register name"));
10698 input_line_pointer
+= 2;
10701 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10706 md_section_align (seg
, addr
)
10710 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10713 /* We don't need to align ELF sections to the full alignment.
10714 However, Irix 5 may prefer that we align them at least to a 16
10715 byte boundary. We don't bother to align the sections if we are
10716 targeted for an embedded system. */
10717 if (strcmp (TARGET_OS
, "elf") == 0)
10723 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10726 /* Utility routine, called from above as well. If called while the
10727 input file is still being read, it's only an approximation. (For
10728 example, a symbol may later become defined which appeared to be
10729 undefined earlier.) */
10732 nopic_need_relax (sym
, before_relaxing
)
10734 int before_relaxing
;
10739 if (USE_GLOBAL_POINTER_OPT
)
10741 const char *symname
;
10744 /* Find out whether this symbol can be referenced off the GP
10745 register. It can be if it is smaller than the -G size or if
10746 it is in the .sdata or .sbss section. Certain symbols can
10747 not be referenced off the GP, although it appears as though
10749 symname
= S_GET_NAME (sym
);
10750 if (symname
!= (const char *) NULL
10751 && (strcmp (symname
, "eprol") == 0
10752 || strcmp (symname
, "etext") == 0
10753 || strcmp (symname
, "_gp") == 0
10754 || strcmp (symname
, "edata") == 0
10755 || strcmp (symname
, "_fbss") == 0
10756 || strcmp (symname
, "_fdata") == 0
10757 || strcmp (symname
, "_ftext") == 0
10758 || strcmp (symname
, "end") == 0
10759 || strcmp (symname
, "_gp_disp") == 0))
10761 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10763 #ifndef NO_ECOFF_DEBUGGING
10764 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10765 && (symbol_get_obj (sym
)->ecoff_extern_size
10766 <= g_switch_value
))
10768 /* We must defer this decision until after the whole
10769 file has been read, since there might be a .extern
10770 after the first use of this symbol. */
10771 || (before_relaxing
10772 #ifndef NO_ECOFF_DEBUGGING
10773 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10775 && S_GET_VALUE (sym
) == 0)
10776 || (S_GET_VALUE (sym
) != 0
10777 && S_GET_VALUE (sym
) <= g_switch_value
)))
10781 const char *segname
;
10783 segname
= segment_name (S_GET_SEGMENT (sym
));
10784 assert (strcmp (segname
, ".lit8") != 0
10785 && strcmp (segname
, ".lit4") != 0);
10786 change
= (strcmp (segname
, ".sdata") != 0
10787 && strcmp (segname
, ".sbss") != 0
10788 && strncmp (segname
, ".sdata.", 7) != 0
10789 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10794 /* We are not optimizing for the GP register. */
10798 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10799 extended opcode. SEC is the section the frag is in. */
10802 mips16_extended_frag (fragp
, sec
, stretch
)
10808 register const struct mips16_immed_operand
*op
;
10810 int mintiny
, maxtiny
;
10813 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10815 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10818 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10819 op
= mips16_immed_operands
;
10820 while (op
->type
!= type
)
10823 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10828 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10831 maxtiny
= 1 << op
->nbits
;
10836 maxtiny
= (1 << op
->nbits
) - 1;
10841 mintiny
= - (1 << (op
->nbits
- 1));
10842 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10845 /* We can't always call S_GET_VALUE here, because we don't want to
10846 lock in a particular frag address. */
10847 if (symbol_constant_p (fragp
->fr_symbol
))
10849 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10850 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10851 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10853 else if (symbol_equated_p (fragp
->fr_symbol
)
10854 && (symbol_constant_p
10855 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10859 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10860 val
= (S_GET_VALUE (eqsym
)
10861 + symbol_get_frag (eqsym
)->fr_address
10862 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10863 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10864 symsec
= S_GET_SEGMENT (eqsym
);
10873 /* We won't have the section when we are called from
10874 mips_relax_frag. However, we will always have been called
10875 from md_estimate_size_before_relax first. If this is a
10876 branch to a different section, we mark it as such. If SEC is
10877 NULL, and the frag is not marked, then it must be a branch to
10878 the same section. */
10881 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10888 fragp
->fr_subtype
=
10889 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10891 /* FIXME: We should support this, and let the linker
10892 catch branches and loads that are out of range. */
10893 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10894 _("unsupported PC relative reference to different section"));
10900 /* In this case, we know for sure that the symbol fragment is in
10901 the same section. If the fr_address of the symbol fragment
10902 is greater then the address of this fragment we want to add
10903 in STRETCH in order to get a better estimate of the address.
10904 This particularly matters because of the shift bits. */
10906 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10907 >= fragp
->fr_address
))
10911 /* Adjust stretch for any alignment frag. Note that if have
10912 been expanding the earlier code, the symbol may be
10913 defined in what appears to be an earlier frag. FIXME:
10914 This doesn't handle the fr_subtype field, which specifies
10915 a maximum number of bytes to skip when doing an
10918 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10921 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10924 stretch
= - ((- stretch
)
10925 & ~ ((1 << (int) f
->fr_offset
) - 1));
10927 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10936 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10938 /* The base address rules are complicated. The base address of
10939 a branch is the following instruction. The base address of a
10940 PC relative load or add is the instruction itself, but if it
10941 is in a delay slot (in which case it can not be extended) use
10942 the address of the instruction whose delay slot it is in. */
10943 if (type
== 'p' || type
== 'q')
10947 /* If we are currently assuming that this frag should be
10948 extended, then, the current address is two bytes
10950 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10953 /* Ignore the low bit in the target, since it will be set
10954 for a text label. */
10955 if ((val
& 1) != 0)
10958 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10960 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10963 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10965 /* Branch offsets have an implicit 0 in the lowest bit. */
10966 if (type
== 'p' || type
== 'q')
10969 /* If any of the shifted bits are set, we must use an extended
10970 opcode. If the address depends on the size of this
10971 instruction, this can lead to a loop, so we arrange to always
10972 use an extended opcode. We only check this when we are in
10973 the main relaxation loop, when SEC is NULL. */
10974 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10976 fragp
->fr_subtype
=
10977 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10981 /* If we are about to mark a frag as extended because the value
10982 is precisely maxtiny + 1, then there is a chance of an
10983 infinite loop as in the following code:
10988 In this case when the la is extended, foo is 0x3fc bytes
10989 away, so the la can be shrunk, but then foo is 0x400 away, so
10990 the la must be extended. To avoid this loop, we mark the
10991 frag as extended if it was small, and is about to become
10992 extended with a value of maxtiny + 1. */
10993 if (val
== ((maxtiny
+ 1) << op
->shift
)
10994 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10997 fragp
->fr_subtype
=
10998 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11002 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11003 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11005 if ((val
& ((1 << op
->shift
) - 1)) != 0
11006 || val
< (mintiny
<< op
->shift
)
11007 || val
> (maxtiny
<< op
->shift
))
11013 /* Estimate the size of a frag before relaxing. Unless this is the
11014 mips16, we are not really relaxing here, and the final size is
11015 encoded in the subtype information. For the mips16, we have to
11016 decide whether we are using an extended opcode or not. */
11020 md_estimate_size_before_relax (fragp
, segtype
)
11025 boolean linkonce
= false;
11027 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11029 if (mips16_extended_frag (fragp
, segtype
, 0))
11031 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11036 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11041 if (mips_pic
== NO_PIC
)
11043 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11045 else if (mips_pic
== SVR4_PIC
)
11050 sym
= fragp
->fr_symbol
;
11052 /* Handle the case of a symbol equated to another symbol. */
11053 while (symbol_equated_p (sym
)
11054 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11058 /* It's possible to get a loop here in a badly written
11060 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11066 symsec
= S_GET_SEGMENT (sym
);
11068 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11069 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11071 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11075 /* The GNU toolchain uses an extension for ELF: a section
11076 beginning with the magic string .gnu.linkonce is a linkonce
11078 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11079 sizeof ".gnu.linkonce" - 1) == 0)
11083 /* This must duplicate the test in adjust_reloc_syms. */
11084 change
= (symsec
!= &bfd_und_section
11085 && symsec
!= &bfd_abs_section
11086 && ! bfd_is_com_section (symsec
)
11089 /* A weak symbol is treated as external. */
11090 && ! S_IS_WEAK (sym
)
11099 /* Record the offset to the first reloc in the fr_opcode field.
11100 This lets md_convert_frag and tc_gen_reloc know that the code
11101 must be expanded. */
11102 fragp
->fr_opcode
= (fragp
->fr_literal
11104 - RELAX_OLD (fragp
->fr_subtype
)
11105 + RELAX_RELOC1 (fragp
->fr_subtype
));
11106 /* FIXME: This really needs as_warn_where. */
11107 if (RELAX_WARN (fragp
->fr_subtype
))
11108 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11114 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11117 /* This is called to see whether a reloc against a defined symbol
11118 should be converted into a reloc against a section. Don't adjust
11119 MIPS16 jump relocations, so we don't have to worry about the format
11120 of the offset in the .o file. Don't adjust relocations against
11121 mips16 symbols, so that the linker can find them if it needs to set
11125 mips_fix_adjustable (fixp
)
11128 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11130 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11131 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11133 if (fixp
->fx_addsy
== NULL
)
11136 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11137 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11138 && fixp
->fx_subsy
== NULL
)
11144 /* Translate internal representation of relocation info to BFD target
11148 tc_gen_reloc (section
, fixp
)
11149 asection
*section ATTRIBUTE_UNUSED
;
11152 static arelent
*retval
[4];
11154 bfd_reloc_code_real_type code
;
11156 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11159 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11160 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11161 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11163 if (mips_pic
== EMBEDDED_PIC
11164 && SWITCH_TABLE (fixp
))
11166 /* For a switch table entry we use a special reloc. The addend
11167 is actually the difference between the reloc address and the
11169 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11170 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11171 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11172 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11174 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11175 reloc
->addend
= fixp
->fx_addnumber
;
11176 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11178 /* We use a special addend for an internal RELLO reloc. */
11179 if (symbol_section_p (fixp
->fx_addsy
))
11180 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11182 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11184 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11186 assert (fixp
->fx_next
!= NULL
11187 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11188 /* We use a special addend for an internal RELHI reloc. The
11189 reloc is relative to the RELLO; adjust the addend
11191 if (symbol_section_p (fixp
->fx_addsy
))
11192 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11193 + fixp
->fx_next
->fx_where
11194 - S_GET_VALUE (fixp
->fx_subsy
));
11196 reloc
->addend
= (fixp
->fx_addnumber
11197 + fixp
->fx_next
->fx_frag
->fr_address
11198 + fixp
->fx_next
->fx_where
);
11202 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11203 /* A gruesome hack which is a result of the gruesome gas reloc
11205 reloc
->addend
= reloc
->address
;
11207 reloc
->addend
= -reloc
->address
;
11210 /* If this is a variant frag, we may need to adjust the existing
11211 reloc and generate a new one. */
11212 if (fixp
->fx_frag
->fr_opcode
!= NULL
11213 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11214 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11215 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11216 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11217 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11218 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11219 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11223 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11225 /* If this is not the last reloc in this frag, then we have two
11226 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11227 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11228 the second one handle all of them. */
11229 if (fixp
->fx_next
!= NULL
11230 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11232 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11233 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11234 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11235 && (fixp
->fx_next
->fx_r_type
11236 == BFD_RELOC_MIPS_GOT_LO16
))
11237 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11238 && (fixp
->fx_next
->fx_r_type
11239 == BFD_RELOC_MIPS_CALL_LO16
)));
11244 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11245 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11246 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11248 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11249 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11250 reloc2
->address
= (reloc
->address
11251 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11252 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11253 reloc2
->addend
= fixp
->fx_addnumber
;
11254 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11255 assert (reloc2
->howto
!= NULL
);
11257 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11261 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11264 reloc3
->address
+= 4;
11267 if (mips_pic
== NO_PIC
)
11269 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11270 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11272 else if (mips_pic
== SVR4_PIC
)
11274 switch (fixp
->fx_r_type
)
11278 case BFD_RELOC_MIPS_GOT16
:
11280 case BFD_RELOC_MIPS_CALL16
:
11281 case BFD_RELOC_MIPS_GOT_LO16
:
11282 case BFD_RELOC_MIPS_CALL_LO16
:
11283 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11291 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11292 to be used in the relocation's section offset. */
11293 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11295 reloc
->address
= reloc
->addend
;
11299 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11300 fixup_segment converted a non-PC relative reloc into a PC
11301 relative reloc. In such a case, we need to convert the reloc
11303 code
= fixp
->fx_r_type
;
11304 if (fixp
->fx_pcrel
)
11309 code
= BFD_RELOC_8_PCREL
;
11312 code
= BFD_RELOC_16_PCREL
;
11315 code
= BFD_RELOC_32_PCREL
;
11318 code
= BFD_RELOC_64_PCREL
;
11320 case BFD_RELOC_8_PCREL
:
11321 case BFD_RELOC_16_PCREL
:
11322 case BFD_RELOC_32_PCREL
:
11323 case BFD_RELOC_64_PCREL
:
11324 case BFD_RELOC_16_PCREL_S2
:
11325 case BFD_RELOC_PCREL_HI16_S
:
11326 case BFD_RELOC_PCREL_LO16
:
11329 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11330 _("Cannot make %s relocation PC relative"),
11331 bfd_get_reloc_code_name (code
));
11335 /* To support a PC relative reloc when generating embedded PIC code
11336 for ECOFF, we use a Cygnus extension. We check for that here to
11337 make sure that we don't let such a reloc escape normally. */
11338 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11339 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11340 && code
== BFD_RELOC_16_PCREL_S2
11341 && mips_pic
!= EMBEDDED_PIC
)
11342 reloc
->howto
= NULL
;
11344 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11346 if (reloc
->howto
== NULL
)
11348 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11349 _("Can not represent %s relocation in this object file format"),
11350 bfd_get_reloc_code_name (code
));
11357 /* Relax a machine dependent frag. This returns the amount by which
11358 the current size of the frag should change. */
11361 mips_relax_frag (fragp
, stretch
)
11365 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11368 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11370 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11372 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11377 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11379 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11386 /* Convert a machine dependent frag. */
11389 md_convert_frag (abfd
, asec
, fragp
)
11390 bfd
*abfd ATTRIBUTE_UNUSED
;
11397 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11400 register const struct mips16_immed_operand
*op
;
11401 boolean small
, ext
;
11404 unsigned long insn
;
11405 boolean use_extend
;
11406 unsigned short extend
;
11408 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11409 op
= mips16_immed_operands
;
11410 while (op
->type
!= type
)
11413 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11424 resolve_symbol_value (fragp
->fr_symbol
, 1);
11425 val
= S_GET_VALUE (fragp
->fr_symbol
);
11430 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11432 /* The rules for the base address of a PC relative reloc are
11433 complicated; see mips16_extended_frag. */
11434 if (type
== 'p' || type
== 'q')
11439 /* Ignore the low bit in the target, since it will be
11440 set for a text label. */
11441 if ((val
& 1) != 0)
11444 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11446 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11449 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11452 /* Make sure the section winds up with the alignment we have
11455 record_alignment (asec
, op
->shift
);
11459 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11460 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11461 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11462 _("extended instruction in delay slot"));
11464 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11466 if (target_big_endian
)
11467 insn
= bfd_getb16 (buf
);
11469 insn
= bfd_getl16 (buf
);
11471 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11472 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11473 small
, ext
, &insn
, &use_extend
, &extend
);
11477 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11478 fragp
->fr_fix
+= 2;
11482 md_number_to_chars (buf
, insn
, 2);
11483 fragp
->fr_fix
+= 2;
11488 if (fragp
->fr_opcode
== NULL
)
11491 old
= RELAX_OLD (fragp
->fr_subtype
);
11492 new = RELAX_NEW (fragp
->fr_subtype
);
11493 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11496 memcpy (fixptr
- old
, fixptr
, new);
11498 fragp
->fr_fix
+= new - old
;
11504 /* This function is called after the relocs have been generated.
11505 We've been storing mips16 text labels as odd. Here we convert them
11506 back to even for the convenience of the debugger. */
11509 mips_frob_file_after_relocs ()
11512 unsigned int count
, i
;
11514 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11517 syms
= bfd_get_outsymbols (stdoutput
);
11518 count
= bfd_get_symcount (stdoutput
);
11519 for (i
= 0; i
< count
; i
++, syms
++)
11521 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11522 && ((*syms
)->value
& 1) != 0)
11524 (*syms
)->value
&= ~1;
11525 /* If the symbol has an odd size, it was probably computed
11526 incorrectly, so adjust that as well. */
11527 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11528 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11535 /* This function is called whenever a label is defined. It is used
11536 when handling branch delays; if a branch has a label, we assume we
11537 can not move it. */
11540 mips_define_label (sym
)
11543 struct insn_label_list
*l
;
11545 if (free_insn_labels
== NULL
)
11546 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11549 l
= free_insn_labels
;
11550 free_insn_labels
= l
->next
;
11554 l
->next
= insn_labels
;
11558 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11560 /* Some special processing for a MIPS ELF file. */
11563 mips_elf_final_processing ()
11565 /* Write out the register information. */
11570 s
.ri_gprmask
= mips_gprmask
;
11571 s
.ri_cprmask
[0] = mips_cprmask
[0];
11572 s
.ri_cprmask
[1] = mips_cprmask
[1];
11573 s
.ri_cprmask
[2] = mips_cprmask
[2];
11574 s
.ri_cprmask
[3] = mips_cprmask
[3];
11575 /* The gp_value field is set by the MIPS ELF backend. */
11577 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11578 ((Elf32_External_RegInfo
*)
11579 mips_regmask_frag
));
11583 Elf64_Internal_RegInfo s
;
11585 s
.ri_gprmask
= mips_gprmask
;
11587 s
.ri_cprmask
[0] = mips_cprmask
[0];
11588 s
.ri_cprmask
[1] = mips_cprmask
[1];
11589 s
.ri_cprmask
[2] = mips_cprmask
[2];
11590 s
.ri_cprmask
[3] = mips_cprmask
[3];
11591 /* The gp_value field is set by the MIPS ELF backend. */
11593 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11594 ((Elf64_External_RegInfo
*)
11595 mips_regmask_frag
));
11598 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11599 sort of BFD interface for this. */
11600 if (mips_any_noreorder
)
11601 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11602 if (mips_pic
!= NO_PIC
)
11603 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11605 /* Set the MIPS ELF ABI flags. */
11606 if (mips_abi_string
== 0)
11608 else if (strcmp (mips_abi_string
,"32") == 0)
11609 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11610 else if (strcmp (mips_abi_string
,"o64") == 0)
11611 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11612 else if (strcmp (mips_abi_string
,"eabi") == 0)
11615 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11617 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11620 if (mips_32bitmode
)
11621 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11624 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11626 typedef struct proc
11629 unsigned long reg_mask
;
11630 unsigned long reg_offset
;
11631 unsigned long fpreg_mask
;
11632 unsigned long fpreg_offset
;
11633 unsigned long frame_offset
;
11634 unsigned long frame_reg
;
11635 unsigned long pc_reg
;
11639 static procS cur_proc
;
11640 static procS
*cur_proc_ptr
;
11641 static int numprocs
;
11643 /* When we align code in the .text section of mips16, use the correct two
11644 byte nop pattern of 0x6500 (move $0,$0) */
11647 mips_do_align (n
, fill
, len
, max
)
11650 int len ATTRIBUTE_UNUSED
;
11654 && subseg_text_p (now_seg
)
11656 && mips_opts
.mips16
)
11658 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11659 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11661 frag_align (1, 0, 0);
11663 if (target_big_endian
)
11664 frag_align_pattern (n
, be_nop
, 2, max
);
11666 frag_align_pattern (n
, le_nop
, 2, max
);
11681 /* check for premature end, nesting errors, etc */
11683 as_warn (_("missing `.end' at end of assembly"));
11692 if (*input_line_pointer
== '-')
11694 ++input_line_pointer
;
11697 if (!isdigit ((unsigned char) *input_line_pointer
))
11698 as_bad (_("Expected simple number."));
11699 if (input_line_pointer
[0] == '0')
11701 if (input_line_pointer
[1] == 'x')
11703 input_line_pointer
+= 2;
11704 while (isxdigit ((unsigned char) *input_line_pointer
))
11707 val
|= hex_value (*input_line_pointer
++);
11709 return negative
? -val
: val
;
11713 ++input_line_pointer
;
11714 while (isdigit ((unsigned char) *input_line_pointer
))
11717 val
|= *input_line_pointer
++ - '0';
11719 return negative
? -val
: val
;
11722 if (!isdigit ((unsigned char) *input_line_pointer
))
11724 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11725 *input_line_pointer
, *input_line_pointer
);
11726 as_warn (_("Invalid number"));
11729 while (isdigit ((unsigned char) *input_line_pointer
))
11732 val
+= *input_line_pointer
++ - '0';
11734 return negative
? -val
: val
;
11737 /* The .file directive; just like the usual .file directive, but there
11738 is an initial number which is the ECOFF file index. */
11742 int x ATTRIBUTE_UNUSED
;
11746 line
= get_number ();
11751 /* The .end directive. */
11755 int x ATTRIBUTE_UNUSED
;
11760 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11763 demand_empty_rest_of_line ();
11768 #ifdef BFD_ASSEMBLER
11769 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11774 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11781 as_warn (_(".end not in text section"));
11785 as_warn (_(".end directive without a preceding .ent directive."));
11786 demand_empty_rest_of_line ();
11792 assert (S_GET_NAME (p
));
11793 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11794 as_warn (_(".end symbol does not match .ent symbol."));
11797 as_warn (_(".end directive missing or unknown symbol"));
11799 #ifdef MIPS_STABS_ELF
11801 segT saved_seg
= now_seg
;
11802 subsegT saved_subseg
= now_subseg
;
11803 fragS
*saved_frag
= frag_now
;
11809 dot
= frag_now_fix ();
11811 #ifdef md_flush_pending_output
11812 md_flush_pending_output ();
11816 subseg_set (pdr_seg
, 0);
11818 /* Write the symbol */
11819 exp
.X_op
= O_symbol
;
11820 exp
.X_add_symbol
= p
;
11821 exp
.X_add_number
= 0;
11822 emit_expr (&exp
, 4);
11824 fragp
= frag_more (7*4);
11826 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11827 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11828 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11829 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11830 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11831 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11832 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11834 subseg_set (saved_seg
, saved_subseg
);
11838 cur_proc_ptr
= NULL
;
11841 /* The .aent and .ent directives. */
11851 symbolP
= get_symbol ();
11852 if (*input_line_pointer
== ',')
11853 input_line_pointer
++;
11854 SKIP_WHITESPACE ();
11855 if (isdigit ((unsigned char) *input_line_pointer
)
11856 || *input_line_pointer
== '-')
11857 number
= get_number ();
11859 #ifdef BFD_ASSEMBLER
11860 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11865 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11872 as_warn (_(".ent or .aent not in text section."));
11874 if (!aent
&& cur_proc_ptr
)
11875 as_warn (_("missing `.end'"));
11879 cur_proc_ptr
= &cur_proc
;
11880 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11882 cur_proc_ptr
->isym
= symbolP
;
11884 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11889 demand_empty_rest_of_line ();
11892 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11893 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11894 s_mips_frame is used so that we can set the PDR information correctly.
11895 We can't use the ecoff routines because they make reference to the ecoff
11896 symbol table (in the mdebug section). */
11899 s_mips_frame (ignore
)
11902 #ifdef MIPS_STABS_ELF
11906 if (cur_proc_ptr
== (procS
*) NULL
)
11908 as_warn (_(".frame outside of .ent"));
11909 demand_empty_rest_of_line ();
11913 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11915 SKIP_WHITESPACE ();
11916 if (*input_line_pointer
++ != ','
11917 || get_absolute_expression_and_terminator (&val
) != ',')
11919 as_warn (_("Bad .frame directive"));
11920 --input_line_pointer
;
11921 demand_empty_rest_of_line ();
11925 cur_proc_ptr
->frame_offset
= val
;
11926 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11928 demand_empty_rest_of_line ();
11931 #endif /* MIPS_STABS_ELF */
11934 /* The .fmask and .mask directives. If the mdebug section is present
11935 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11936 embedded targets, s_mips_mask is used so that we can set the PDR
11937 information correctly. We can't use the ecoff routines because they
11938 make reference to the ecoff symbol table (in the mdebug section). */
11941 s_mips_mask (reg_type
)
11944 #ifdef MIPS_STABS_ELF
11947 if (cur_proc_ptr
== (procS
*) NULL
)
11949 as_warn (_(".mask/.fmask outside of .ent"));
11950 demand_empty_rest_of_line ();
11954 if (get_absolute_expression_and_terminator (&mask
) != ',')
11956 as_warn (_("Bad .mask/.fmask directive"));
11957 --input_line_pointer
;
11958 demand_empty_rest_of_line ();
11962 off
= get_absolute_expression ();
11964 if (reg_type
== 'F')
11966 cur_proc_ptr
->fpreg_mask
= mask
;
11967 cur_proc_ptr
->fpreg_offset
= off
;
11971 cur_proc_ptr
->reg_mask
= mask
;
11972 cur_proc_ptr
->reg_offset
= off
;
11975 demand_empty_rest_of_line ();
11977 s_ignore (reg_type
);
11978 #endif /* MIPS_STABS_ELF */
11981 /* The .loc directive. */
11992 assert (now_seg
== text_section
);
11994 lineno
= get_number ();
11995 addroff
= frag_now_fix ();
11997 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11998 S_SET_TYPE (symbolP
, N_SLINE
);
11999 S_SET_OTHER (symbolP
, 0);
12000 S_SET_DESC (symbolP
, lineno
);
12001 symbolP
->sy_segment
= now_seg
;