1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode
;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p
: 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p
: 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p
: 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p
: 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p
: 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi
= NO_ABI
;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls
= FALSE
;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared
= TRUE
;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). These are set to -1
212 if they have not been initialized. Changed by `.set <asename>', by
213 command line options, and based on the default architecture. */
221 /* Whether we are assembling for the mips16 processor. 0 if we are
222 not, 1 if we are, and -1 if the value has not been initialized.
223 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
224 -nomips16 command line options, and the default CPU. */
226 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
227 1 if we are, and -1 if the value has not been initialized. Changed
228 by `.set micromips' and `.set nomicromips', and the -mmicromips
229 and -mno-micromips command line options, and the default CPU. */
231 /* Non-zero if we should not reorder instructions. Changed by `.set
232 reorder' and `.set noreorder'. */
234 /* Non-zero if we should not permit the register designated "assembler
235 temporary" to be used in instructions. The value is the register
236 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
237 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
239 /* Non-zero if we should warn when a macro instruction expands into
240 more than one machine instruction. Changed by `.set nomacro' and
242 int warn_about_macros
;
243 /* Non-zero if we should not move instructions. Changed by `.set
244 move', `.set volatile', `.set nomove', and `.set novolatile'. */
246 /* Non-zero if we should not optimize branches by moving the target
247 of the branch into the delay slot. Actually, we don't perform
248 this optimization anyhow. Changed by `.set bopt' and `.set
251 /* Non-zero if we should not autoextend mips16 instructions.
252 Changed by `.set autoextend' and `.set noautoextend'. */
254 /* Restrict general purpose registers and floating point registers
255 to 32 bit. This is initially determined when -mgp32 or -mfp32
256 is passed but can changed if the assembler code uses .set mipsN. */
259 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
260 command line option, and the default CPU. */
262 /* True if ".set sym32" is in effect. */
264 /* True if floating-point operations are not allowed. Changed by .set
265 softfloat or .set hardfloat, by command line options -msoft-float or
266 -mhard-float. The default is false. */
267 bfd_boolean soft_float
;
269 /* True if only single-precision floating-point operations are allowed.
270 Changed by .set singlefloat or .set doublefloat, command-line options
271 -msingle-float or -mdouble-float. The default is false. */
272 bfd_boolean single_float
;
275 /* This is the struct we use to hold the current set of options. Note
276 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
277 -1 to indicate that they have not been initialized. */
279 /* True if -mgp32 was passed. */
280 static int file_mips_gp32
= -1;
282 /* True if -mfp32 was passed. */
283 static int file_mips_fp32
= -1;
285 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
286 static int file_mips_soft_float
= 0;
288 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
289 static int file_mips_single_float
= 0;
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
294 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
295 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
296 /* at */ ATREG
, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
297 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
298 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
301 /* These variables are filled in with the masks of registers used.
302 The object format code reads them and puts them in the appropriate
304 unsigned long mips_gprmask
;
305 unsigned long mips_cprmask
[4];
307 /* MIPS ISA we are using for this output file. */
308 static int file_mips_isa
= ISA_UNKNOWN
;
310 /* True if any MIPS16 code was produced. */
311 static int file_ase_mips16
;
313 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
314 || mips_opts.isa == ISA_MIPS32R2 \
315 || mips_opts.isa == ISA_MIPS64 \
316 || mips_opts.isa == ISA_MIPS64R2)
318 /* True if any microMIPS code was produced. */
319 static int file_ase_micromips
;
321 /* True if we want to create R_MIPS_JALR for jalr $25. */
323 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
325 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328 #define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
333 /* True if -mips3d was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mips3d
;
337 /* True if -mdmx was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mdmx
;
341 /* True if -msmartmips was passed or implied by arguments passed on the
342 command line (e.g., by -march). */
343 static int file_ase_smartmips
;
345 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
346 || mips_opts.isa == ISA_MIPS32R2)
348 /* True if -mdsp was passed or implied by arguments passed on the
349 command line (e.g., by -march). */
350 static int file_ase_dsp
;
352 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
353 || mips_opts.isa == ISA_MIPS64R2 \
354 || mips_opts.micromips)
356 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
358 /* True if -mdspr2 was passed or implied by arguments passed on the
359 command line (e.g., by -march). */
360 static int file_ase_dspr2
;
362 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
363 || mips_opts.isa == ISA_MIPS64R2 \
364 || mips_opts.micromips)
366 /* True if -mmt was passed or implied by arguments passed on the
367 command line (e.g., by -march). */
368 static int file_ase_mt
;
370 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
371 || mips_opts.isa == ISA_MIPS64R2)
373 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
374 || mips_opts.isa == ISA_MIPS64R2 \
375 || mips_opts.micromips)
377 /* The argument of the -march= flag. The architecture we are assembling. */
378 static int file_mips_arch
= CPU_UNKNOWN
;
379 static const char *mips_arch_string
;
381 /* The argument of the -mtune= flag. The architecture for which we
383 static int mips_tune
= CPU_UNKNOWN
;
384 static const char *mips_tune_string
;
386 /* True when generating 32-bit code for a 64-bit processor. */
387 static int mips_32bitmode
= 0;
389 /* True if the given ABI requires 32-bit registers. */
390 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
392 /* Likewise 64-bit registers. */
393 #define ABI_NEEDS_64BIT_REGS(ABI) \
395 || (ABI) == N64_ABI \
398 /* Return true if ISA supports 64 bit wide gp registers. */
399 #define ISA_HAS_64BIT_REGS(ISA) \
400 ((ISA) == ISA_MIPS3 \
401 || (ISA) == ISA_MIPS4 \
402 || (ISA) == ISA_MIPS5 \
403 || (ISA) == ISA_MIPS64 \
404 || (ISA) == ISA_MIPS64R2)
406 /* Return true if ISA supports 64 bit wide float registers. */
407 #define ISA_HAS_64BIT_FPRS(ISA) \
408 ((ISA) == ISA_MIPS3 \
409 || (ISA) == ISA_MIPS4 \
410 || (ISA) == ISA_MIPS5 \
411 || (ISA) == ISA_MIPS32R2 \
412 || (ISA) == ISA_MIPS64 \
413 || (ISA) == ISA_MIPS64R2)
415 /* Return true if ISA supports 64-bit right rotate (dror et al.)
417 #define ISA_HAS_DROR(ISA) \
418 ((ISA) == ISA_MIPS64R2 \
419 || (mips_opts.micromips \
420 && ISA_HAS_64BIT_REGS (ISA)) \
423 /* Return true if ISA supports 32-bit right rotate (ror et al.)
425 #define ISA_HAS_ROR(ISA) \
426 ((ISA) == ISA_MIPS32R2 \
427 || (ISA) == ISA_MIPS64R2 \
428 || mips_opts.ase_smartmips \
429 || mips_opts.micromips \
432 /* Return true if ISA supports single-precision floats in odd registers. */
433 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
434 ((ISA) == ISA_MIPS32 \
435 || (ISA) == ISA_MIPS32R2 \
436 || (ISA) == ISA_MIPS64 \
437 || (ISA) == ISA_MIPS64R2)
439 /* Return true if ISA supports move to/from high part of a 64-bit
440 floating-point register. */
441 #define ISA_HAS_MXHC1(ISA) \
442 ((ISA) == ISA_MIPS32R2 \
443 || (ISA) == ISA_MIPS64R2)
445 #define HAVE_32BIT_GPRS \
446 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
448 #define HAVE_32BIT_FPRS \
449 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
451 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
452 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
454 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
456 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
458 /* True if relocations are stored in-place. */
459 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
461 /* The ABI-derived address size. */
462 #define HAVE_64BIT_ADDRESSES \
463 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
464 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
466 /* The size of symbolic constants (i.e., expressions of the form
467 "SYMBOL" or "SYMBOL + OFFSET"). */
468 #define HAVE_32BIT_SYMBOLS \
469 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
470 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
472 /* Addresses are loaded in different ways, depending on the address size
473 in use. The n32 ABI Documentation also mandates the use of additions
474 with overflow checking, but existing implementations don't follow it. */
475 #define ADDRESS_ADD_INSN \
476 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
478 #define ADDRESS_ADDI_INSN \
479 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
481 #define ADDRESS_LOAD_INSN \
482 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
484 #define ADDRESS_STORE_INSN \
485 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
487 /* Return true if the given CPU supports the MIPS16 ASE. */
488 #define CPU_HAS_MIPS16(cpu) \
489 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
490 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
492 /* Return true if the given CPU supports the microMIPS ASE. */
493 #define CPU_HAS_MICROMIPS(cpu) 0
495 /* True if CPU has a dror instruction. */
496 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
498 /* True if CPU has a ror instruction. */
499 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
501 /* True if CPU is in the Octeon family */
502 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
504 /* True if CPU has seq/sne and seqi/snei instructions. */
505 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
507 /* True if mflo and mfhi can be immediately followed by instructions
508 which write to the HI and LO registers.
510 According to MIPS specifications, MIPS ISAs I, II, and III need
511 (at least) two instructions between the reads of HI/LO and
512 instructions which write them, and later ISAs do not. Contradicting
513 the MIPS specifications, some MIPS IV processor user manuals (e.g.
514 the UM for the NEC Vr5000) document needing the instructions between
515 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
516 MIPS64 and later ISAs to have the interlocks, plus any specific
517 earlier-ISA CPUs for which CPU documentation declares that the
518 instructions are really interlocked. */
519 #define hilo_interlocks \
520 (mips_opts.isa == ISA_MIPS32 \
521 || mips_opts.isa == ISA_MIPS32R2 \
522 || mips_opts.isa == ISA_MIPS64 \
523 || mips_opts.isa == ISA_MIPS64R2 \
524 || mips_opts.arch == CPU_R4010 \
525 || mips_opts.arch == CPU_R5900 \
526 || mips_opts.arch == CPU_R10000 \
527 || mips_opts.arch == CPU_R12000 \
528 || mips_opts.arch == CPU_R14000 \
529 || mips_opts.arch == CPU_R16000 \
530 || mips_opts.arch == CPU_RM7000 \
531 || mips_opts.arch == CPU_VR5500 \
532 || mips_opts.micromips \
535 /* Whether the processor uses hardware interlocks to protect reads
536 from the GPRs after they are loaded from memory, and thus does not
537 require nops to be inserted. This applies to instructions marked
538 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
539 level I and microMIPS mode instructions are always interlocked. */
540 #define gpr_interlocks \
541 (mips_opts.isa != ISA_MIPS1 \
542 || mips_opts.arch == CPU_R3900 \
543 || mips_opts.arch == CPU_R5900 \
544 || mips_opts.micromips \
547 /* Whether the processor uses hardware interlocks to avoid delays
548 required by coprocessor instructions, and thus does not require
549 nops to be inserted. This applies to instructions marked
550 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
551 between instructions marked INSN_WRITE_COND_CODE and ones marked
552 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
553 levels I, II, and III and microMIPS mode instructions are always
555 /* Itbl support may require additional care here. */
556 #define cop_interlocks \
557 ((mips_opts.isa != ISA_MIPS1 \
558 && mips_opts.isa != ISA_MIPS2 \
559 && mips_opts.isa != ISA_MIPS3) \
560 || mips_opts.arch == CPU_R4300 \
561 || mips_opts.micromips \
564 /* Whether the processor uses hardware interlocks to protect reads
565 from coprocessor registers after they are loaded from memory, and
566 thus does not require nops to be inserted. This applies to
567 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
568 requires at MIPS ISA level I and microMIPS mode instructions are
569 always interlocked. */
570 #define cop_mem_interlocks \
571 (mips_opts.isa != ISA_MIPS1 \
572 || mips_opts.micromips \
575 /* Is this a mfhi or mflo instruction? */
576 #define MF_HILO_INSN(PINFO) \
577 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
579 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
580 has been selected. This implies, in particular, that addresses of text
581 labels have their LSB set. */
582 #define HAVE_CODE_COMPRESSION \
583 ((mips_opts.mips16 | mips_opts.micromips) != 0)
585 /* MIPS PIC level. */
587 enum mips_pic_level mips_pic
;
589 /* 1 if we should generate 32 bit offsets from the $gp register in
590 SVR4_PIC mode. Currently has no meaning in other modes. */
591 static int mips_big_got
= 0;
593 /* 1 if trap instructions should used for overflow rather than break
595 static int mips_trap
= 0;
597 /* 1 if double width floating point constants should not be constructed
598 by assembling two single width halves into two single width floating
599 point registers which just happen to alias the double width destination
600 register. On some architectures this aliasing can be disabled by a bit
601 in the status register, and the setting of this bit cannot be determined
602 automatically at assemble time. */
603 static int mips_disable_float_construction
;
605 /* Non-zero if any .set noreorder directives were used. */
607 static int mips_any_noreorder
;
609 /* Non-zero if nops should be inserted when the register referenced in
610 an mfhi/mflo instruction is read in the next two instructions. */
611 static int mips_7000_hilo_fix
;
613 /* The size of objects in the small data section. */
614 static unsigned int g_switch_value
= 8;
615 /* Whether the -G option was used. */
616 static int g_switch_seen
= 0;
621 /* If we can determine in advance that GP optimization won't be
622 possible, we can skip the relaxation stuff that tries to produce
623 GP-relative references. This makes delay slot optimization work
626 This function can only provide a guess, but it seems to work for
627 gcc output. It needs to guess right for gcc, otherwise gcc
628 will put what it thinks is a GP-relative instruction in a branch
631 I don't know if a fix is needed for the SVR4_PIC mode. I've only
632 fixed it for the non-PIC mode. KR 95/04/07 */
633 static int nopic_need_relax (symbolS
*, int);
635 /* handle of the OPCODE hash table */
636 static struct hash_control
*op_hash
= NULL
;
638 /* The opcode hash table we use for the mips16. */
639 static struct hash_control
*mips16_op_hash
= NULL
;
641 /* The opcode hash table we use for the microMIPS ASE. */
642 static struct hash_control
*micromips_op_hash
= NULL
;
644 /* This array holds the chars that always start a comment. If the
645 pre-processor is disabled, these aren't very useful */
646 const char comment_chars
[] = "#";
648 /* This array holds the chars that only start a comment at the beginning of
649 a line. If the line seems to have the form '# 123 filename'
650 .line and .file directives will appear in the pre-processed output */
651 /* Note that input_file.c hand checks for '#' at the beginning of the
652 first line of the input file. This is because the compiler outputs
653 #NO_APP at the beginning of its output. */
654 /* Also note that C style comments are always supported. */
655 const char line_comment_chars
[] = "#";
657 /* This array holds machine specific line separator characters. */
658 const char line_separator_chars
[] = ";";
660 /* Chars that can be used to separate mant from exp in floating point nums */
661 const char EXP_CHARS
[] = "eE";
663 /* Chars that mean this number is a floating point constant */
666 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
668 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
669 changed in read.c . Ideally it shouldn't have to know about it at all,
670 but nothing is ideal around here.
673 static char *insn_error
;
675 static int auto_align
= 1;
677 /* When outputting SVR4 PIC code, the assembler needs to know the
678 offset in the stack frame from which to restore the $gp register.
679 This is set by the .cprestore pseudo-op, and saved in this
681 static offsetT mips_cprestore_offset
= -1;
683 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
684 more optimizations, it can use a register value instead of a memory-saved
685 offset and even an other register than $gp as global pointer. */
686 static offsetT mips_cpreturn_offset
= -1;
687 static int mips_cpreturn_register
= -1;
688 static int mips_gp_register
= GP
;
689 static int mips_gprel_offset
= 0;
691 /* Whether mips_cprestore_offset has been set in the current function
692 (or whether it has already been warned about, if not). */
693 static int mips_cprestore_valid
= 0;
695 /* This is the register which holds the stack frame, as set by the
696 .frame pseudo-op. This is needed to implement .cprestore. */
697 static int mips_frame_reg
= SP
;
699 /* Whether mips_frame_reg has been set in the current function
700 (or whether it has already been warned about, if not). */
701 static int mips_frame_reg_valid
= 0;
703 /* To output NOP instructions correctly, we need to keep information
704 about the previous two instructions. */
706 /* Whether we are optimizing. The default value of 2 means to remove
707 unneeded NOPs and swap branch instructions when possible. A value
708 of 1 means to not swap branches. A value of 0 means to always
710 static int mips_optimize
= 2;
712 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
713 equivalent to seeing no -g option at all. */
714 static int mips_debug
= 0;
716 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
717 #define MAX_VR4130_NOPS 4
719 /* The maximum number of NOPs needed to fill delay slots. */
720 #define MAX_DELAY_NOPS 2
722 /* The maximum number of NOPs needed for any purpose. */
725 /* A list of previous instructions, with index 0 being the most recent.
726 We need to look back MAX_NOPS instructions when filling delay slots
727 or working around processor errata. We need to look back one
728 instruction further if we're thinking about using history[0] to
729 fill a branch delay slot. */
730 static struct mips_cl_insn history
[1 + MAX_NOPS
];
732 /* Nop instructions used by emit_nop. */
733 static struct mips_cl_insn nop_insn
;
734 static struct mips_cl_insn mips16_nop_insn
;
735 static struct mips_cl_insn micromips_nop16_insn
;
736 static struct mips_cl_insn micromips_nop32_insn
;
738 /* The appropriate nop for the current mode. */
739 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
740 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
742 /* The size of NOP_INSN in bytes. */
743 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
745 /* If this is set, it points to a frag holding nop instructions which
746 were inserted before the start of a noreorder section. If those
747 nops turn out to be unnecessary, the size of the frag can be
749 static fragS
*prev_nop_frag
;
751 /* The number of nop instructions we created in prev_nop_frag. */
752 static int prev_nop_frag_holds
;
754 /* The number of nop instructions that we know we need in
756 static int prev_nop_frag_required
;
758 /* The number of instructions we've seen since prev_nop_frag. */
759 static int prev_nop_frag_since
;
761 /* For ECOFF and ELF, relocations against symbols are done in two
762 parts, with a HI relocation and a LO relocation. Each relocation
763 has only 16 bits of space to store an addend. This means that in
764 order for the linker to handle carries correctly, it must be able
765 to locate both the HI and the LO relocation. This means that the
766 relocations must appear in order in the relocation table.
768 In order to implement this, we keep track of each unmatched HI
769 relocation. We then sort them so that they immediately precede the
770 corresponding LO relocation. */
775 struct mips_hi_fixup
*next
;
778 /* The section this fixup is in. */
782 /* The list of unmatched HI relocs. */
784 static struct mips_hi_fixup
*mips_hi_fixup_list
;
786 /* The frag containing the last explicit relocation operator.
787 Null if explicit relocations have not been used. */
789 static fragS
*prev_reloc_op_frag
;
791 /* Map normal MIPS register numbers to mips16 register numbers. */
793 #define X ILLEGAL_REG
794 static const int mips32_to_16_reg_map
[] =
796 X
, X
, 2, 3, 4, 5, 6, 7,
797 X
, X
, X
, X
, X
, X
, X
, X
,
798 0, 1, X
, X
, X
, X
, X
, X
,
799 X
, X
, X
, X
, X
, X
, X
, X
803 /* Map mips16 register numbers to normal MIPS register numbers. */
805 static const unsigned int mips16_to_32_reg_map
[] =
807 16, 17, 2, 3, 4, 5, 6, 7
810 /* Map normal MIPS register numbers to microMIPS register numbers. */
812 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
813 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
814 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
815 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
816 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
817 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
818 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
820 #define X ILLEGAL_REG
821 /* reg type h: 4, 5, 6. */
822 static const int mips32_to_micromips_reg_h_map
[] =
824 X
, X
, X
, X
, 4, 5, 6, X
,
825 X
, X
, X
, X
, X
, X
, X
, X
,
826 X
, X
, X
, X
, X
, X
, X
, X
,
827 X
, X
, X
, X
, X
, X
, X
, X
830 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
831 static const int mips32_to_micromips_reg_m_map
[] =
833 0, X
, 2, 3, X
, X
, X
, X
,
834 X
, X
, X
, X
, X
, X
, X
, X
,
835 4, 1, 5, 6, 7, X
, X
, X
,
836 X
, X
, X
, X
, X
, X
, X
, X
839 /* reg type q: 0, 2-7. 17. */
840 static const int mips32_to_micromips_reg_q_map
[] =
842 0, X
, 2, 3, 4, 5, 6, 7,
843 X
, X
, X
, X
, X
, X
, X
, X
,
844 X
, 1, X
, X
, X
, X
, X
, X
,
845 X
, X
, X
, X
, X
, X
, X
, X
848 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
851 /* Map microMIPS register numbers to normal MIPS register numbers. */
853 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
854 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
855 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
856 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
857 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
858 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
860 /* The microMIPS registers with type h. */
861 static const unsigned int micromips_to_32_reg_h_map
[] =
863 5, 5, 6, 4, 4, 4, 4, 4
866 /* The microMIPS registers with type i. */
867 static const unsigned int micromips_to_32_reg_i_map
[] =
869 6, 7, 7, 21, 22, 5, 6, 7
872 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
874 /* The microMIPS registers with type m. */
875 static const unsigned int micromips_to_32_reg_m_map
[] =
877 0, 17, 2, 3, 16, 18, 19, 20
880 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
882 /* The microMIPS registers with type q. */
883 static const unsigned int micromips_to_32_reg_q_map
[] =
885 0, 17, 2, 3, 4, 5, 6, 7
888 /* microMIPS imm type B. */
889 static const int micromips_imm_b_map
[] =
891 1, 4, 8, 12, 16, 20, 24, -1
894 /* microMIPS imm type C. */
895 static const int micromips_imm_c_map
[] =
897 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
900 /* Classifies the kind of instructions we're interested in when
901 implementing -mfix-vr4120. */
902 enum fix_vr4120_class
910 NUM_FIX_VR4120_CLASSES
913 /* ...likewise -mfix-loongson2f-jump. */
914 static bfd_boolean mips_fix_loongson2f_jump
;
916 /* ...likewise -mfix-loongson2f-nop. */
917 static bfd_boolean mips_fix_loongson2f_nop
;
919 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
920 static bfd_boolean mips_fix_loongson2f
;
922 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
923 there must be at least one other instruction between an instruction
924 of type X and an instruction of type Y. */
925 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
927 /* True if -mfix-vr4120 is in force. */
928 static int mips_fix_vr4120
;
930 /* ...likewise -mfix-vr4130. */
931 static int mips_fix_vr4130
;
933 /* ...likewise -mfix-24k. */
934 static int mips_fix_24k
;
936 /* ...likewise -mfix-cn63xxp1 */
937 static bfd_boolean mips_fix_cn63xxp1
;
939 /* We don't relax branches by default, since this causes us to expand
940 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
941 fail to compute the offset before expanding the macro to the most
942 efficient expansion. */
944 static int mips_relax_branch
;
946 /* The expansion of many macros depends on the type of symbol that
947 they refer to. For example, when generating position-dependent code,
948 a macro that refers to a symbol may have two different expansions,
949 one which uses GP-relative addresses and one which uses absolute
950 addresses. When generating SVR4-style PIC, a macro may have
951 different expansions for local and global symbols.
953 We handle these situations by generating both sequences and putting
954 them in variant frags. In position-dependent code, the first sequence
955 will be the GP-relative one and the second sequence will be the
956 absolute one. In SVR4 PIC, the first sequence will be for global
957 symbols and the second will be for local symbols.
959 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
960 SECOND are the lengths of the two sequences in bytes. These fields
961 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
962 the subtype has the following flags:
965 Set if it has been decided that we should use the second
966 sequence instead of the first.
969 Set in the first variant frag if the macro's second implementation
970 is longer than its first. This refers to the macro as a whole,
971 not an individual relaxation.
974 Set in the first variant frag if the macro appeared in a .set nomacro
975 block and if one alternative requires a warning but the other does not.
978 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
981 RELAX_DELAY_SLOT_16BIT
982 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
985 RELAX_DELAY_SLOT_SIZE_FIRST
986 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
987 the macro is of the wrong size for the branch delay slot.
989 RELAX_DELAY_SLOT_SIZE_SECOND
990 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
991 the macro is of the wrong size for the branch delay slot.
993 The frag's "opcode" points to the first fixup for relaxable code.
995 Relaxable macros are generated using a sequence such as:
997 relax_start (SYMBOL);
998 ... generate first expansion ...
1000 ... generate second expansion ...
1003 The code and fixups for the unwanted alternative are discarded
1004 by md_convert_frag. */
1005 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1007 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1008 #define RELAX_SECOND(X) ((X) & 0xff)
1009 #define RELAX_USE_SECOND 0x10000
1010 #define RELAX_SECOND_LONGER 0x20000
1011 #define RELAX_NOMACRO 0x40000
1012 #define RELAX_DELAY_SLOT 0x80000
1013 #define RELAX_DELAY_SLOT_16BIT 0x100000
1014 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1015 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1017 /* Branch without likely bit. If label is out of range, we turn:
1019 beq reg1, reg2, label
1029 with the following opcode replacements:
1036 bltzal <-> bgezal (with jal label instead of j label)
1038 Even though keeping the delay slot instruction in the delay slot of
1039 the branch would be more efficient, it would be very tricky to do
1040 correctly, because we'd have to introduce a variable frag *after*
1041 the delay slot instruction, and expand that instead. Let's do it
1042 the easy way for now, even if the branch-not-taken case now costs
1043 one additional instruction. Out-of-range branches are not supposed
1044 to be common, anyway.
1046 Branch likely. If label is out of range, we turn:
1048 beql reg1, reg2, label
1049 delay slot (annulled if branch not taken)
1058 delay slot (executed only if branch taken)
1061 It would be possible to generate a shorter sequence by losing the
1062 likely bit, generating something like:
1067 delay slot (executed only if branch taken)
1079 bltzall -> bgezal (with jal label instead of j label)
1080 bgezall -> bltzal (ditto)
1083 but it's not clear that it would actually improve performance. */
1084 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1085 ((relax_substateT) \
1088 | ((toofar) ? 0x20 : 0) \
1089 | ((link) ? 0x40 : 0) \
1090 | ((likely) ? 0x80 : 0) \
1091 | ((uncond) ? 0x100 : 0)))
1092 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1093 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1094 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1095 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1096 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1097 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1099 /* For mips16 code, we use an entirely different form of relaxation.
1100 mips16 supports two versions of most instructions which take
1101 immediate values: a small one which takes some small value, and a
1102 larger one which takes a 16 bit value. Since branches also follow
1103 this pattern, relaxing these values is required.
1105 We can assemble both mips16 and normal MIPS code in a single
1106 object. Therefore, we need to support this type of relaxation at
1107 the same time that we support the relaxation described above. We
1108 use the high bit of the subtype field to distinguish these cases.
1110 The information we store for this type of relaxation is the
1111 argument code found in the opcode file for this relocation, whether
1112 the user explicitly requested a small or extended form, and whether
1113 the relocation is in a jump or jal delay slot. That tells us the
1114 size of the value, and how it should be stored. We also store
1115 whether the fragment is considered to be extended or not. We also
1116 store whether this is known to be a branch to a different section,
1117 whether we have tried to relax this frag yet, and whether we have
1118 ever extended a PC relative fragment because of a shift count. */
1119 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1122 | ((small) ? 0x100 : 0) \
1123 | ((ext) ? 0x200 : 0) \
1124 | ((dslot) ? 0x400 : 0) \
1125 | ((jal_dslot) ? 0x800 : 0))
1126 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1127 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1128 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1129 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1130 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1131 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1132 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1133 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1134 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1135 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1136 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1137 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1139 /* For microMIPS code, we use relaxation similar to one we use for
1140 MIPS16 code. Some instructions that take immediate values support
1141 two encodings: a small one which takes some small value, and a
1142 larger one which takes a 16 bit value. As some branches also follow
1143 this pattern, relaxing these values is required.
1145 We can assemble both microMIPS and normal MIPS code in a single
1146 object. Therefore, we need to support this type of relaxation at
1147 the same time that we support the relaxation described above. We
1148 use one of the high bits of the subtype field to distinguish these
1151 The information we store for this type of relaxation is the argument
1152 code found in the opcode file for this relocation, the register
1153 selected as the assembler temporary, whether the branch is
1154 unconditional, whether it is compact, whether it stores the link
1155 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1156 branches to a sequence of instructions is enabled, and whether the
1157 displacement of a branch is too large to fit as an immediate argument
1158 of a 16-bit and a 32-bit branch, respectively. */
1159 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1160 relax32, toofar16, toofar32) \
1163 | (((at) & 0x1f) << 8) \
1164 | ((uncond) ? 0x2000 : 0) \
1165 | ((compact) ? 0x4000 : 0) \
1166 | ((link) ? 0x8000 : 0) \
1167 | ((relax32) ? 0x10000 : 0) \
1168 | ((toofar16) ? 0x20000 : 0) \
1169 | ((toofar32) ? 0x40000 : 0))
1170 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1171 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1172 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1173 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1174 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1175 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1176 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1178 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1179 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1180 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1181 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1182 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1183 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1185 /* Sign-extend 16-bit value X. */
1186 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1188 /* Is the given value a sign-extended 32-bit value? */
1189 #define IS_SEXT_32BIT_NUM(x) \
1190 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1191 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1193 /* Is the given value a sign-extended 16-bit value? */
1194 #define IS_SEXT_16BIT_NUM(x) \
1195 (((x) &~ (offsetT) 0x7fff) == 0 \
1196 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1198 /* Is the given value a sign-extended 12-bit value? */
1199 #define IS_SEXT_12BIT_NUM(x) \
1200 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1202 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1203 #define IS_ZEXT_32BIT_NUM(x) \
1204 (((x) &~ (offsetT) 0xffffffff) == 0 \
1205 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1207 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1208 VALUE << SHIFT. VALUE is evaluated exactly once. */
1209 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1210 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1211 | (((VALUE) & (MASK)) << (SHIFT)))
1213 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1215 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1216 (((STRUCT) >> (SHIFT)) & (MASK))
1218 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1219 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1221 include/opcode/mips.h specifies operand fields using the macros
1222 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1223 with "MIPS16OP" instead of "OP". */
1224 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1227 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1228 OP_MASK_##FIELD, OP_SH_##FIELD); \
1230 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1231 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1233 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1234 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1235 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1237 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1238 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1240 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1241 : EXTRACT_BITS ((INSN).insn_opcode, \
1242 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1243 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1244 EXTRACT_BITS ((INSN).insn_opcode, \
1245 MIPS16OP_MASK_##FIELD, \
1246 MIPS16OP_SH_##FIELD)
1248 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1249 #define MIPS16_EXTEND (0xf000U << 16)
1251 /* Whether or not we are emitting a branch-likely macro. */
1252 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1254 /* Global variables used when generating relaxable macros. See the
1255 comment above RELAX_ENCODE for more details about how relaxation
1258 /* 0 if we're not emitting a relaxable macro.
1259 1 if we're emitting the first of the two relaxation alternatives.
1260 2 if we're emitting the second alternative. */
1263 /* The first relaxable fixup in the current frag. (In other words,
1264 the first fixup that refers to relaxable code.) */
1267 /* sizes[0] says how many bytes of the first alternative are stored in
1268 the current frag. Likewise sizes[1] for the second alternative. */
1269 unsigned int sizes
[2];
1271 /* The symbol on which the choice of sequence depends. */
1275 /* Global variables used to decide whether a macro needs a warning. */
1277 /* True if the macro is in a branch delay slot. */
1278 bfd_boolean delay_slot_p
;
1280 /* Set to the length in bytes required if the macro is in a delay slot
1281 that requires a specific length of instruction, otherwise zero. */
1282 unsigned int delay_slot_length
;
1284 /* For relaxable macros, sizes[0] is the length of the first alternative
1285 in bytes and sizes[1] is the length of the second alternative.
1286 For non-relaxable macros, both elements give the length of the
1288 unsigned int sizes
[2];
1290 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1291 instruction of the first alternative in bytes and first_insn_sizes[1]
1292 is the length of the first instruction of the second alternative.
1293 For non-relaxable macros, both elements give the length of the first
1294 instruction in bytes.
1296 Set to zero if we haven't yet seen the first instruction. */
1297 unsigned int first_insn_sizes
[2];
1299 /* For relaxable macros, insns[0] is the number of instructions for the
1300 first alternative and insns[1] is the number of instructions for the
1303 For non-relaxable macros, both elements give the number of
1304 instructions for the macro. */
1305 unsigned int insns
[2];
1307 /* The first variant frag for this macro. */
1309 } mips_macro_warning
;
1311 /* Prototypes for static functions. */
1313 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1315 static void append_insn
1316 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1317 bfd_boolean expansionp
);
1318 static void mips_no_prev_insn (void);
1319 static void macro_build (expressionS
*, const char *, const char *, ...);
1320 static void mips16_macro_build
1321 (expressionS
*, const char *, const char *, va_list *);
1322 static void load_register (int, expressionS
*, int);
1323 static void macro_start (void);
1324 static void macro_end (void);
1325 static void macro (struct mips_cl_insn
* ip
);
1326 static void mips16_macro (struct mips_cl_insn
* ip
);
1327 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1328 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1329 static void mips16_immed
1330 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1331 unsigned int, unsigned long *);
1332 static size_t my_getSmallExpression
1333 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1334 static void my_getExpression (expressionS
*, char *);
1335 static void s_align (int);
1336 static void s_change_sec (int);
1337 static void s_change_section (int);
1338 static void s_cons (int);
1339 static void s_float_cons (int);
1340 static void s_mips_globl (int);
1341 static void s_option (int);
1342 static void s_mipsset (int);
1343 static void s_abicalls (int);
1344 static void s_cpload (int);
1345 static void s_cpsetup (int);
1346 static void s_cplocal (int);
1347 static void s_cprestore (int);
1348 static void s_cpreturn (int);
1349 static void s_dtprelword (int);
1350 static void s_dtpreldword (int);
1351 static void s_tprelword (int);
1352 static void s_tpreldword (int);
1353 static void s_gpvalue (int);
1354 static void s_gpword (int);
1355 static void s_gpdword (int);
1356 static void s_cpadd (int);
1357 static void s_insn (int);
1358 static void md_obj_begin (void);
1359 static void md_obj_end (void);
1360 static void s_mips_ent (int);
1361 static void s_mips_end (int);
1362 static void s_mips_frame (int);
1363 static void s_mips_mask (int reg_type
);
1364 static void s_mips_stab (int);
1365 static void s_mips_weakext (int);
1366 static void s_mips_file (int);
1367 static void s_mips_loc (int);
1368 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1369 static int relaxed_branch_length (fragS
*, asection
*, int);
1370 static int validate_mips_insn (const struct mips_opcode
*);
1371 static int validate_micromips_insn (const struct mips_opcode
*);
1372 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1373 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1375 /* Table and functions used to map between CPU/ISA names, and
1376 ISA levels, and CPU numbers. */
1378 struct mips_cpu_info
1380 const char *name
; /* CPU or ISA name. */
1381 int flags
; /* ASEs available, or ISA flag. */
1382 int isa
; /* ISA level. */
1383 int cpu
; /* CPU number (default CPU if ISA). */
1386 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1387 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1388 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1389 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1390 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1391 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1392 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1393 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1395 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1396 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1397 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1401 The following pseudo-ops from the Kane and Heinrich MIPS book
1402 should be defined here, but are currently unsupported: .alias,
1403 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1405 The following pseudo-ops from the Kane and Heinrich MIPS book are
1406 specific to the type of debugging information being generated, and
1407 should be defined by the object format: .aent, .begin, .bend,
1408 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1411 The following pseudo-ops from the Kane and Heinrich MIPS book are
1412 not MIPS CPU specific, but are also not specific to the object file
1413 format. This file is probably the best place to define them, but
1414 they are not currently supported: .asm0, .endr, .lab, .struct. */
1416 static const pseudo_typeS mips_pseudo_table
[] =
1418 /* MIPS specific pseudo-ops. */
1419 {"option", s_option
, 0},
1420 {"set", s_mipsset
, 0},
1421 {"rdata", s_change_sec
, 'r'},
1422 {"sdata", s_change_sec
, 's'},
1423 {"livereg", s_ignore
, 0},
1424 {"abicalls", s_abicalls
, 0},
1425 {"cpload", s_cpload
, 0},
1426 {"cpsetup", s_cpsetup
, 0},
1427 {"cplocal", s_cplocal
, 0},
1428 {"cprestore", s_cprestore
, 0},
1429 {"cpreturn", s_cpreturn
, 0},
1430 {"dtprelword", s_dtprelword
, 0},
1431 {"dtpreldword", s_dtpreldword
, 0},
1432 {"tprelword", s_tprelword
, 0},
1433 {"tpreldword", s_tpreldword
, 0},
1434 {"gpvalue", s_gpvalue
, 0},
1435 {"gpword", s_gpword
, 0},
1436 {"gpdword", s_gpdword
, 0},
1437 {"cpadd", s_cpadd
, 0},
1438 {"insn", s_insn
, 0},
1440 /* Relatively generic pseudo-ops that happen to be used on MIPS
1442 {"asciiz", stringer
, 8 + 1},
1443 {"bss", s_change_sec
, 'b'},
1445 {"half", s_cons
, 1},
1446 {"dword", s_cons
, 3},
1447 {"weakext", s_mips_weakext
, 0},
1448 {"origin", s_org
, 0},
1449 {"repeat", s_rept
, 0},
1451 /* For MIPS this is non-standard, but we define it for consistency. */
1452 {"sbss", s_change_sec
, 'B'},
1454 /* These pseudo-ops are defined in read.c, but must be overridden
1455 here for one reason or another. */
1456 {"align", s_align
, 0},
1457 {"byte", s_cons
, 0},
1458 {"data", s_change_sec
, 'd'},
1459 {"double", s_float_cons
, 'd'},
1460 {"float", s_float_cons
, 'f'},
1461 {"globl", s_mips_globl
, 0},
1462 {"global", s_mips_globl
, 0},
1463 {"hword", s_cons
, 1},
1465 {"long", s_cons
, 2},
1466 {"octa", s_cons
, 4},
1467 {"quad", s_cons
, 3},
1468 {"section", s_change_section
, 0},
1469 {"short", s_cons
, 1},
1470 {"single", s_float_cons
, 'f'},
1471 {"stabn", s_mips_stab
, 'n'},
1472 {"text", s_change_sec
, 't'},
1473 {"word", s_cons
, 2},
1475 { "extern", ecoff_directive_extern
, 0},
1480 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1482 /* These pseudo-ops should be defined by the object file format.
1483 However, a.out doesn't support them, so we have versions here. */
1484 {"aent", s_mips_ent
, 1},
1485 {"bgnb", s_ignore
, 0},
1486 {"end", s_mips_end
, 0},
1487 {"endb", s_ignore
, 0},
1488 {"ent", s_mips_ent
, 0},
1489 {"file", s_mips_file
, 0},
1490 {"fmask", s_mips_mask
, 'F'},
1491 {"frame", s_mips_frame
, 0},
1492 {"loc", s_mips_loc
, 0},
1493 {"mask", s_mips_mask
, 'R'},
1494 {"verstamp", s_ignore
, 0},
1498 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1499 purpose of the `.dc.a' internal pseudo-op. */
1502 mips_address_bytes (void)
1504 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1507 extern void pop_insert (const pseudo_typeS
*);
1510 mips_pop_insert (void)
1512 pop_insert (mips_pseudo_table
);
1513 if (! ECOFF_DEBUGGING
)
1514 pop_insert (mips_nonecoff_pseudo_table
);
1517 /* Symbols labelling the current insn. */
1519 struct insn_label_list
1521 struct insn_label_list
*next
;
1525 static struct insn_label_list
*free_insn_labels
;
1526 #define label_list tc_segment_info_data.labels
1528 static void mips_clear_insn_labels (void);
1529 static void mips_mark_labels (void);
1530 static void mips_compressed_mark_labels (void);
1533 mips_clear_insn_labels (void)
1535 register struct insn_label_list
**pl
;
1536 segment_info_type
*si
;
1540 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1543 si
= seg_info (now_seg
);
1544 *pl
= si
->label_list
;
1545 si
->label_list
= NULL
;
1549 /* Mark instruction labels in MIPS16/microMIPS mode. */
1552 mips_mark_labels (void)
1554 if (HAVE_CODE_COMPRESSION
)
1555 mips_compressed_mark_labels ();
1558 static char *expr_end
;
1560 /* Expressions which appear in instructions. These are set by
1563 static expressionS imm_expr
;
1564 static expressionS imm2_expr
;
1565 static expressionS offset_expr
;
1567 /* Relocs associated with imm_expr and offset_expr. */
1569 static bfd_reloc_code_real_type imm_reloc
[3]
1570 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1571 static bfd_reloc_code_real_type offset_reloc
[3]
1572 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1574 /* This is set to the resulting size of the instruction to be produced
1575 by mips16_ip if an explicit extension is used or by mips_ip if an
1576 explicit size is supplied. */
1578 static unsigned int forced_insn_length
;
1580 /* True if we are assembling an instruction. All dot symbols defined during
1581 this time should be treated as code labels. */
1583 static bfd_boolean mips_assembling_insn
;
1586 /* The pdr segment for per procedure frame/regmask info. Not used for
1589 static segT pdr_seg
;
1592 /* The default target format to use. */
1594 #if defined (TE_FreeBSD)
1595 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1596 #elif defined (TE_TMIPS)
1597 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1599 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1603 mips_target_format (void)
1605 switch (OUTPUT_FLAVOR
)
1607 case bfd_target_ecoff_flavour
:
1608 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1609 case bfd_target_coff_flavour
:
1611 case bfd_target_elf_flavour
:
1613 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1614 return (target_big_endian
1615 ? "elf32-bigmips-vxworks"
1616 : "elf32-littlemips-vxworks");
1618 return (target_big_endian
1619 ? (HAVE_64BIT_OBJECTS
1620 ? ELF_TARGET ("elf64-", "big")
1622 ? ELF_TARGET ("elf32-n", "big")
1623 : ELF_TARGET ("elf32-", "big")))
1624 : (HAVE_64BIT_OBJECTS
1625 ? ELF_TARGET ("elf64-", "little")
1627 ? ELF_TARGET ("elf32-n", "little")
1628 : ELF_TARGET ("elf32-", "little"))));
1635 /* Return the length of a microMIPS instruction in bytes. If bits of
1636 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1637 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1638 major opcode) will require further modifications to the opcode
1641 static inline unsigned int
1642 micromips_insn_length (const struct mips_opcode
*mo
)
1644 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1647 /* Return the length of MIPS16 instruction OPCODE. */
1649 static inline unsigned int
1650 mips16_opcode_length (unsigned long opcode
)
1652 return (opcode
>> 16) == 0 ? 2 : 4;
1655 /* Return the length of instruction INSN. */
1657 static inline unsigned int
1658 insn_length (const struct mips_cl_insn
*insn
)
1660 if (mips_opts
.micromips
)
1661 return micromips_insn_length (insn
->insn_mo
);
1662 else if (mips_opts
.mips16
)
1663 return mips16_opcode_length (insn
->insn_opcode
);
1668 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1671 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1676 insn
->insn_opcode
= mo
->match
;
1679 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1680 insn
->fixp
[i
] = NULL
;
1681 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1682 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1683 insn
->mips16_absolute_jump_p
= 0;
1684 insn
->complete_p
= 0;
1685 insn
->cleared_p
= 0;
1688 /* Record the current MIPS16/microMIPS mode in now_seg. */
1691 mips_record_compressed_mode (void)
1693 segment_info_type
*si
;
1695 si
= seg_info (now_seg
);
1696 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1697 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1698 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1699 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1702 /* Read a standard MIPS instruction from BUF. */
1704 static unsigned long
1705 read_insn (char *buf
)
1707 if (target_big_endian
)
1708 return bfd_getb32 ((bfd_byte
*) buf
);
1710 return bfd_getl32 ((bfd_byte
*) buf
);
1713 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1717 write_insn (char *buf
, unsigned int insn
)
1719 md_number_to_chars (buf
, insn
, 4);
1723 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1724 has length LENGTH. */
1726 static unsigned long
1727 read_compressed_insn (char *buf
, unsigned int length
)
1733 for (i
= 0; i
< length
; i
+= 2)
1736 if (target_big_endian
)
1737 insn
|= bfd_getb16 ((char *) buf
);
1739 insn
|= bfd_getl16 ((char *) buf
);
1745 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1746 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1749 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
1753 for (i
= 0; i
< length
; i
+= 2)
1754 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
1755 return buf
+ length
;
1758 /* Install INSN at the location specified by its "frag" and "where" fields. */
1761 install_insn (const struct mips_cl_insn
*insn
)
1763 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1764 if (HAVE_CODE_COMPRESSION
)
1765 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
1767 write_insn (f
, insn
->insn_opcode
);
1768 mips_record_compressed_mode ();
1771 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1772 and install the opcode in the new location. */
1775 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1780 insn
->where
= where
;
1781 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1782 if (insn
->fixp
[i
] != NULL
)
1784 insn
->fixp
[i
]->fx_frag
= frag
;
1785 insn
->fixp
[i
]->fx_where
= where
;
1787 install_insn (insn
);
1790 /* Add INSN to the end of the output. */
1793 add_fixed_insn (struct mips_cl_insn
*insn
)
1795 char *f
= frag_more (insn_length (insn
));
1796 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1799 /* Start a variant frag and move INSN to the start of the variant part,
1800 marking it as fixed. The other arguments are as for frag_var. */
1803 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1804 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1806 frag_grow (max_chars
);
1807 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1809 frag_var (rs_machine_dependent
, max_chars
, var
,
1810 subtype
, symbol
, offset
, NULL
);
1813 /* Insert N copies of INSN into the history buffer, starting at
1814 position FIRST. Neither FIRST nor N need to be clipped. */
1817 insert_into_history (unsigned int first
, unsigned int n
,
1818 const struct mips_cl_insn
*insn
)
1820 if (mips_relax
.sequence
!= 2)
1824 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1826 history
[i
] = history
[i
- n
];
1832 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1833 the idea is to make it obvious at a glance that each errata is
1837 init_vr4120_conflicts (void)
1839 #define CONFLICT(FIRST, SECOND) \
1840 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1842 /* Errata 21 - [D]DIV[U] after [D]MACC */
1843 CONFLICT (MACC
, DIV
);
1844 CONFLICT (DMACC
, DIV
);
1846 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1847 CONFLICT (DMULT
, DMULT
);
1848 CONFLICT (DMULT
, DMACC
);
1849 CONFLICT (DMACC
, DMULT
);
1850 CONFLICT (DMACC
, DMACC
);
1852 /* Errata 24 - MT{LO,HI} after [D]MACC */
1853 CONFLICT (MACC
, MTHILO
);
1854 CONFLICT (DMACC
, MTHILO
);
1856 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1857 instruction is executed immediately after a MACC or DMACC
1858 instruction, the result of [either instruction] is incorrect." */
1859 CONFLICT (MACC
, MULT
);
1860 CONFLICT (MACC
, DMULT
);
1861 CONFLICT (DMACC
, MULT
);
1862 CONFLICT (DMACC
, DMULT
);
1864 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1865 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1866 DDIV or DDIVU instruction, the result of the MACC or
1867 DMACC instruction is incorrect.". */
1868 CONFLICT (DMULT
, MACC
);
1869 CONFLICT (DMULT
, DMACC
);
1870 CONFLICT (DIV
, MACC
);
1871 CONFLICT (DIV
, DMACC
);
1881 #define RTYPE_MASK 0x1ff00
1882 #define RTYPE_NUM 0x00100
1883 #define RTYPE_FPU 0x00200
1884 #define RTYPE_FCC 0x00400
1885 #define RTYPE_VEC 0x00800
1886 #define RTYPE_GP 0x01000
1887 #define RTYPE_CP0 0x02000
1888 #define RTYPE_PC 0x04000
1889 #define RTYPE_ACC 0x08000
1890 #define RTYPE_CCC 0x10000
1891 #define RNUM_MASK 0x000ff
1892 #define RWARN 0x80000
1894 #define GENERIC_REGISTER_NUMBERS \
1895 {"$0", RTYPE_NUM | 0}, \
1896 {"$1", RTYPE_NUM | 1}, \
1897 {"$2", RTYPE_NUM | 2}, \
1898 {"$3", RTYPE_NUM | 3}, \
1899 {"$4", RTYPE_NUM | 4}, \
1900 {"$5", RTYPE_NUM | 5}, \
1901 {"$6", RTYPE_NUM | 6}, \
1902 {"$7", RTYPE_NUM | 7}, \
1903 {"$8", RTYPE_NUM | 8}, \
1904 {"$9", RTYPE_NUM | 9}, \
1905 {"$10", RTYPE_NUM | 10}, \
1906 {"$11", RTYPE_NUM | 11}, \
1907 {"$12", RTYPE_NUM | 12}, \
1908 {"$13", RTYPE_NUM | 13}, \
1909 {"$14", RTYPE_NUM | 14}, \
1910 {"$15", RTYPE_NUM | 15}, \
1911 {"$16", RTYPE_NUM | 16}, \
1912 {"$17", RTYPE_NUM | 17}, \
1913 {"$18", RTYPE_NUM | 18}, \
1914 {"$19", RTYPE_NUM | 19}, \
1915 {"$20", RTYPE_NUM | 20}, \
1916 {"$21", RTYPE_NUM | 21}, \
1917 {"$22", RTYPE_NUM | 22}, \
1918 {"$23", RTYPE_NUM | 23}, \
1919 {"$24", RTYPE_NUM | 24}, \
1920 {"$25", RTYPE_NUM | 25}, \
1921 {"$26", RTYPE_NUM | 26}, \
1922 {"$27", RTYPE_NUM | 27}, \
1923 {"$28", RTYPE_NUM | 28}, \
1924 {"$29", RTYPE_NUM | 29}, \
1925 {"$30", RTYPE_NUM | 30}, \
1926 {"$31", RTYPE_NUM | 31}
1928 #define FPU_REGISTER_NAMES \
1929 {"$f0", RTYPE_FPU | 0}, \
1930 {"$f1", RTYPE_FPU | 1}, \
1931 {"$f2", RTYPE_FPU | 2}, \
1932 {"$f3", RTYPE_FPU | 3}, \
1933 {"$f4", RTYPE_FPU | 4}, \
1934 {"$f5", RTYPE_FPU | 5}, \
1935 {"$f6", RTYPE_FPU | 6}, \
1936 {"$f7", RTYPE_FPU | 7}, \
1937 {"$f8", RTYPE_FPU | 8}, \
1938 {"$f9", RTYPE_FPU | 9}, \
1939 {"$f10", RTYPE_FPU | 10}, \
1940 {"$f11", RTYPE_FPU | 11}, \
1941 {"$f12", RTYPE_FPU | 12}, \
1942 {"$f13", RTYPE_FPU | 13}, \
1943 {"$f14", RTYPE_FPU | 14}, \
1944 {"$f15", RTYPE_FPU | 15}, \
1945 {"$f16", RTYPE_FPU | 16}, \
1946 {"$f17", RTYPE_FPU | 17}, \
1947 {"$f18", RTYPE_FPU | 18}, \
1948 {"$f19", RTYPE_FPU | 19}, \
1949 {"$f20", RTYPE_FPU | 20}, \
1950 {"$f21", RTYPE_FPU | 21}, \
1951 {"$f22", RTYPE_FPU | 22}, \
1952 {"$f23", RTYPE_FPU | 23}, \
1953 {"$f24", RTYPE_FPU | 24}, \
1954 {"$f25", RTYPE_FPU | 25}, \
1955 {"$f26", RTYPE_FPU | 26}, \
1956 {"$f27", RTYPE_FPU | 27}, \
1957 {"$f28", RTYPE_FPU | 28}, \
1958 {"$f29", RTYPE_FPU | 29}, \
1959 {"$f30", RTYPE_FPU | 30}, \
1960 {"$f31", RTYPE_FPU | 31}
1962 #define FPU_CONDITION_CODE_NAMES \
1963 {"$fcc0", RTYPE_FCC | 0}, \
1964 {"$fcc1", RTYPE_FCC | 1}, \
1965 {"$fcc2", RTYPE_FCC | 2}, \
1966 {"$fcc3", RTYPE_FCC | 3}, \
1967 {"$fcc4", RTYPE_FCC | 4}, \
1968 {"$fcc5", RTYPE_FCC | 5}, \
1969 {"$fcc6", RTYPE_FCC | 6}, \
1970 {"$fcc7", RTYPE_FCC | 7}
1972 #define COPROC_CONDITION_CODE_NAMES \
1973 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1974 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1975 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1976 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1977 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1978 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1979 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1980 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1982 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1983 {"$a4", RTYPE_GP | 8}, \
1984 {"$a5", RTYPE_GP | 9}, \
1985 {"$a6", RTYPE_GP | 10}, \
1986 {"$a7", RTYPE_GP | 11}, \
1987 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1988 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1989 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1990 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1991 {"$t0", RTYPE_GP | 12}, \
1992 {"$t1", RTYPE_GP | 13}, \
1993 {"$t2", RTYPE_GP | 14}, \
1994 {"$t3", RTYPE_GP | 15}
1996 #define O32_SYMBOLIC_REGISTER_NAMES \
1997 {"$t0", RTYPE_GP | 8}, \
1998 {"$t1", RTYPE_GP | 9}, \
1999 {"$t2", RTYPE_GP | 10}, \
2000 {"$t3", RTYPE_GP | 11}, \
2001 {"$t4", RTYPE_GP | 12}, \
2002 {"$t5", RTYPE_GP | 13}, \
2003 {"$t6", RTYPE_GP | 14}, \
2004 {"$t7", RTYPE_GP | 15}, \
2005 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2006 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2007 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2008 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2010 /* Remaining symbolic register names */
2011 #define SYMBOLIC_REGISTER_NAMES \
2012 {"$zero", RTYPE_GP | 0}, \
2013 {"$at", RTYPE_GP | 1}, \
2014 {"$AT", RTYPE_GP | 1}, \
2015 {"$v0", RTYPE_GP | 2}, \
2016 {"$v1", RTYPE_GP | 3}, \
2017 {"$a0", RTYPE_GP | 4}, \
2018 {"$a1", RTYPE_GP | 5}, \
2019 {"$a2", RTYPE_GP | 6}, \
2020 {"$a3", RTYPE_GP | 7}, \
2021 {"$s0", RTYPE_GP | 16}, \
2022 {"$s1", RTYPE_GP | 17}, \
2023 {"$s2", RTYPE_GP | 18}, \
2024 {"$s3", RTYPE_GP | 19}, \
2025 {"$s4", RTYPE_GP | 20}, \
2026 {"$s5", RTYPE_GP | 21}, \
2027 {"$s6", RTYPE_GP | 22}, \
2028 {"$s7", RTYPE_GP | 23}, \
2029 {"$t8", RTYPE_GP | 24}, \
2030 {"$t9", RTYPE_GP | 25}, \
2031 {"$k0", RTYPE_GP | 26}, \
2032 {"$kt0", RTYPE_GP | 26}, \
2033 {"$k1", RTYPE_GP | 27}, \
2034 {"$kt1", RTYPE_GP | 27}, \
2035 {"$gp", RTYPE_GP | 28}, \
2036 {"$sp", RTYPE_GP | 29}, \
2037 {"$s8", RTYPE_GP | 30}, \
2038 {"$fp", RTYPE_GP | 30}, \
2039 {"$ra", RTYPE_GP | 31}
2041 #define MIPS16_SPECIAL_REGISTER_NAMES \
2042 {"$pc", RTYPE_PC | 0}
2044 #define MDMX_VECTOR_REGISTER_NAMES \
2045 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2046 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2047 {"$v2", RTYPE_VEC | 2}, \
2048 {"$v3", RTYPE_VEC | 3}, \
2049 {"$v4", RTYPE_VEC | 4}, \
2050 {"$v5", RTYPE_VEC | 5}, \
2051 {"$v6", RTYPE_VEC | 6}, \
2052 {"$v7", RTYPE_VEC | 7}, \
2053 {"$v8", RTYPE_VEC | 8}, \
2054 {"$v9", RTYPE_VEC | 9}, \
2055 {"$v10", RTYPE_VEC | 10}, \
2056 {"$v11", RTYPE_VEC | 11}, \
2057 {"$v12", RTYPE_VEC | 12}, \
2058 {"$v13", RTYPE_VEC | 13}, \
2059 {"$v14", RTYPE_VEC | 14}, \
2060 {"$v15", RTYPE_VEC | 15}, \
2061 {"$v16", RTYPE_VEC | 16}, \
2062 {"$v17", RTYPE_VEC | 17}, \
2063 {"$v18", RTYPE_VEC | 18}, \
2064 {"$v19", RTYPE_VEC | 19}, \
2065 {"$v20", RTYPE_VEC | 20}, \
2066 {"$v21", RTYPE_VEC | 21}, \
2067 {"$v22", RTYPE_VEC | 22}, \
2068 {"$v23", RTYPE_VEC | 23}, \
2069 {"$v24", RTYPE_VEC | 24}, \
2070 {"$v25", RTYPE_VEC | 25}, \
2071 {"$v26", RTYPE_VEC | 26}, \
2072 {"$v27", RTYPE_VEC | 27}, \
2073 {"$v28", RTYPE_VEC | 28}, \
2074 {"$v29", RTYPE_VEC | 29}, \
2075 {"$v30", RTYPE_VEC | 30}, \
2076 {"$v31", RTYPE_VEC | 31}
2078 #define MIPS_DSP_ACCUMULATOR_NAMES \
2079 {"$ac0", RTYPE_ACC | 0}, \
2080 {"$ac1", RTYPE_ACC | 1}, \
2081 {"$ac2", RTYPE_ACC | 2}, \
2082 {"$ac3", RTYPE_ACC | 3}
2084 static const struct regname reg_names
[] = {
2085 GENERIC_REGISTER_NUMBERS
,
2087 FPU_CONDITION_CODE_NAMES
,
2088 COPROC_CONDITION_CODE_NAMES
,
2090 /* The $txx registers depends on the abi,
2091 these will be added later into the symbol table from
2092 one of the tables below once mips_abi is set after
2093 parsing of arguments from the command line. */
2094 SYMBOLIC_REGISTER_NAMES
,
2096 MIPS16_SPECIAL_REGISTER_NAMES
,
2097 MDMX_VECTOR_REGISTER_NAMES
,
2098 MIPS_DSP_ACCUMULATOR_NAMES
,
2102 static const struct regname reg_names_o32
[] = {
2103 O32_SYMBOLIC_REGISTER_NAMES
,
2107 static const struct regname reg_names_n32n64
[] = {
2108 N32N64_SYMBOLIC_REGISTER_NAMES
,
2112 /* Check if S points at a valid register specifier according to TYPES.
2113 If so, then return 1, advance S to consume the specifier and store
2114 the register's number in REGNOP, otherwise return 0. */
2117 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2124 /* Find end of name. */
2126 if (is_name_beginner (*e
))
2128 while (is_part_of_name (*e
))
2131 /* Terminate name. */
2135 /* Look for a register symbol. */
2136 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2138 int r
= S_GET_VALUE (symbolP
);
2140 reg
= r
& RNUM_MASK
;
2141 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2142 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2143 reg
= (r
& RNUM_MASK
) - 2;
2145 /* Else see if this is a register defined in an itbl entry. */
2146 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2153 if (itbl_get_reg_val (n
, &r
))
2154 reg
= r
& RNUM_MASK
;
2157 /* Advance to next token if a register was recognised. */
2160 else if (types
& RWARN
)
2161 as_warn (_("Unrecognized register name `%s'"), *s
);
2169 /* Check if S points at a valid register list according to TYPES.
2170 If so, then return 1, advance S to consume the list and store
2171 the registers present on the list as a bitmask of ones in REGLISTP,
2172 otherwise return 0. A valid list comprises a comma-separated
2173 enumeration of valid single registers and/or dash-separated
2174 contiguous register ranges as determined by their numbers.
2176 As a special exception if one of s0-s7 registers is specified as
2177 the range's lower delimiter and s8 (fp) is its upper one, then no
2178 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2179 are selected; they have to be listed separately if needed. */
2182 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2184 unsigned int reglist
= 0;
2185 unsigned int lastregno
;
2186 bfd_boolean ok
= TRUE
;
2187 unsigned int regmask
;
2188 char *s_endlist
= *s
;
2192 while (reg_lookup (s
, types
, ®no
))
2198 ok
= reg_lookup (s
, types
, &lastregno
);
2199 if (ok
&& lastregno
< regno
)
2205 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2210 regmask
= 1 << lastregno
;
2211 regmask
= (regmask
<< 1) - 1;
2212 regmask
^= (1 << regno
) - 1;
2226 *reglistp
= reglist
;
2227 return ok
&& reglist
!= 0;
2230 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2231 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2234 is_opcode_valid (const struct mips_opcode
*mo
)
2236 int isa
= mips_opts
.isa
;
2239 if (mips_opts
.ase_mdmx
)
2241 if (mips_opts
.ase_dsp
)
2243 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2245 if (mips_opts
.ase_dspr2
)
2247 if (mips_opts
.ase_mt
)
2249 if (mips_opts
.ase_mips3d
)
2251 if (mips_opts
.ase_smartmips
)
2252 isa
|= INSN_SMARTMIPS
;
2253 if (mips_opts
.ase_mcu
)
2256 if (!opcode_is_member (mo
, isa
, mips_opts
.arch
))
2259 /* Check whether the instruction or macro requires single-precision or
2260 double-precision floating-point support. Note that this information is
2261 stored differently in the opcode table for insns and macros. */
2262 if (mo
->pinfo
== INSN_MACRO
)
2264 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2265 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2269 fp_s
= mo
->pinfo
& FP_S
;
2270 fp_d
= mo
->pinfo
& FP_D
;
2273 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2276 if (fp_s
&& mips_opts
.soft_float
)
2282 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2283 selected ISA and architecture. */
2286 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2288 return opcode_is_member (mo
, mips_opts
.isa
, mips_opts
.arch
);
2291 /* Return TRUE if the size of the microMIPS opcode MO matches one
2292 explicitly requested. Always TRUE in the standard MIPS mode. */
2295 is_size_valid (const struct mips_opcode
*mo
)
2297 if (!mips_opts
.micromips
)
2300 if (!forced_insn_length
)
2302 if (mo
->pinfo
== INSN_MACRO
)
2304 return forced_insn_length
== micromips_insn_length (mo
);
2307 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2308 of the preceding instruction. Always TRUE in the standard MIPS mode.
2310 We don't accept macros in 16-bit delay slots to avoid a case where
2311 a macro expansion fails because it relies on a preceding 32-bit real
2312 instruction to have matched and does not handle the operands correctly.
2313 The only macros that may expand to 16-bit instructions are JAL that
2314 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2315 and BGT (that likewise cannot be placed in a delay slot) that decay to
2316 a NOP. In all these cases the macros precede any corresponding real
2317 instruction definitions in the opcode table, so they will match in the
2318 second pass where the size of the delay slot is ignored and therefore
2319 produce correct code. */
2322 is_delay_slot_valid (const struct mips_opcode
*mo
)
2324 if (!mips_opts
.micromips
)
2327 if (mo
->pinfo
== INSN_MACRO
)
2328 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2329 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2330 && micromips_insn_length (mo
) != 4)
2332 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2333 && micromips_insn_length (mo
) != 2)
2339 /* This function is called once, at assembler startup time. It should set up
2340 all the tables, etc. that the MD part of the assembler will need. */
2345 const char *retval
= NULL
;
2349 if (mips_pic
!= NO_PIC
)
2351 if (g_switch_seen
&& g_switch_value
!= 0)
2352 as_bad (_("-G may not be used in position-independent code"));
2356 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2357 as_warn (_("Could not set architecture and machine"));
2359 op_hash
= hash_new ();
2361 for (i
= 0; i
< NUMOPCODES
;)
2363 const char *name
= mips_opcodes
[i
].name
;
2365 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2368 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2369 mips_opcodes
[i
].name
, retval
);
2370 /* Probably a memory allocation problem? Give up now. */
2371 as_fatal (_("Broken assembler. No assembly attempted."));
2375 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2377 if (!validate_mips_insn (&mips_opcodes
[i
]))
2379 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2381 create_insn (&nop_insn
, mips_opcodes
+ i
);
2382 if (mips_fix_loongson2f_nop
)
2383 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2384 nop_insn
.fixed_p
= 1;
2389 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2392 mips16_op_hash
= hash_new ();
2395 while (i
< bfd_mips16_num_opcodes
)
2397 const char *name
= mips16_opcodes
[i
].name
;
2399 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2401 as_fatal (_("internal: can't hash `%s': %s"),
2402 mips16_opcodes
[i
].name
, retval
);
2405 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2406 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2407 != mips16_opcodes
[i
].match
))
2409 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2410 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2413 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2415 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2416 mips16_nop_insn
.fixed_p
= 1;
2420 while (i
< bfd_mips16_num_opcodes
2421 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2424 micromips_op_hash
= hash_new ();
2427 while (i
< bfd_micromips_num_opcodes
)
2429 const char *name
= micromips_opcodes
[i
].name
;
2431 retval
= hash_insert (micromips_op_hash
, name
,
2432 (void *) µmips_opcodes
[i
]);
2434 as_fatal (_("internal: can't hash `%s': %s"),
2435 micromips_opcodes
[i
].name
, retval
);
2437 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2439 struct mips_cl_insn
*micromips_nop_insn
;
2441 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2444 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2445 micromips_nop_insn
= µmips_nop16_insn
;
2446 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2447 micromips_nop_insn
= µmips_nop32_insn
;
2451 if (micromips_nop_insn
->insn_mo
== NULL
2452 && strcmp (name
, "nop") == 0)
2454 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2455 micromips_nop_insn
->fixed_p
= 1;
2458 while (++i
< bfd_micromips_num_opcodes
2459 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2463 as_fatal (_("Broken assembler. No assembly attempted."));
2465 /* We add all the general register names to the symbol table. This
2466 helps us detect invalid uses of them. */
2467 for (i
= 0; reg_names
[i
].name
; i
++)
2468 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2469 reg_names
[i
].num
, /* & RNUM_MASK, */
2470 &zero_address_frag
));
2472 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2473 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2474 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2475 &zero_address_frag
));
2477 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2478 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2479 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2480 &zero_address_frag
));
2482 mips_no_prev_insn ();
2485 mips_cprmask
[0] = 0;
2486 mips_cprmask
[1] = 0;
2487 mips_cprmask
[2] = 0;
2488 mips_cprmask
[3] = 0;
2490 /* set the default alignment for the text section (2**2) */
2491 record_alignment (text_section
, 2);
2493 bfd_set_gp_size (stdoutput
, g_switch_value
);
2498 /* On a native system other than VxWorks, sections must be aligned
2499 to 16 byte boundaries. When configured for an embedded ELF
2500 target, we don't bother. */
2501 if (strncmp (TARGET_OS
, "elf", 3) != 0
2502 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2504 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2505 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2506 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2509 /* Create a .reginfo section for register masks and a .mdebug
2510 section for debugging information. */
2518 subseg
= now_subseg
;
2520 /* The ABI says this section should be loaded so that the
2521 running program can access it. However, we don't load it
2522 if we are configured for an embedded target */
2523 flags
= SEC_READONLY
| SEC_DATA
;
2524 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2525 flags
|= SEC_ALLOC
| SEC_LOAD
;
2527 if (mips_abi
!= N64_ABI
)
2529 sec
= subseg_new (".reginfo", (subsegT
) 0);
2531 bfd_set_section_flags (stdoutput
, sec
, flags
);
2532 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2534 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2538 /* The 64-bit ABI uses a .MIPS.options section rather than
2539 .reginfo section. */
2540 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2541 bfd_set_section_flags (stdoutput
, sec
, flags
);
2542 bfd_set_section_alignment (stdoutput
, sec
, 3);
2544 /* Set up the option header. */
2546 Elf_Internal_Options opthdr
;
2549 opthdr
.kind
= ODK_REGINFO
;
2550 opthdr
.size
= (sizeof (Elf_External_Options
)
2551 + sizeof (Elf64_External_RegInfo
));
2554 f
= frag_more (sizeof (Elf_External_Options
));
2555 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2556 (Elf_External_Options
*) f
);
2558 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2562 if (ECOFF_DEBUGGING
)
2564 sec
= subseg_new (".mdebug", (subsegT
) 0);
2565 (void) bfd_set_section_flags (stdoutput
, sec
,
2566 SEC_HAS_CONTENTS
| SEC_READONLY
);
2567 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2569 else if (mips_flag_pdr
)
2571 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2572 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2573 SEC_READONLY
| SEC_RELOC
2575 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2578 subseg_set (seg
, subseg
);
2581 #endif /* OBJ_ELF */
2583 if (! ECOFF_DEBUGGING
)
2586 if (mips_fix_vr4120
)
2587 init_vr4120_conflicts ();
2593 mips_emit_delays ();
2594 if (! ECOFF_DEBUGGING
)
2599 md_assemble (char *str
)
2601 struct mips_cl_insn insn
;
2602 bfd_reloc_code_real_type unused_reloc
[3]
2603 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2605 imm_expr
.X_op
= O_absent
;
2606 imm2_expr
.X_op
= O_absent
;
2607 offset_expr
.X_op
= O_absent
;
2608 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2609 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2610 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2611 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2612 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2613 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2615 mips_mark_labels ();
2616 mips_assembling_insn
= TRUE
;
2618 if (mips_opts
.mips16
)
2619 mips16_ip (str
, &insn
);
2622 mips_ip (str
, &insn
);
2623 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2624 str
, insn
.insn_opcode
));
2628 as_bad ("%s `%s'", insn_error
, str
);
2629 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2632 if (mips_opts
.mips16
)
2633 mips16_macro (&insn
);
2640 if (imm_expr
.X_op
!= O_absent
)
2641 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2642 else if (offset_expr
.X_op
!= O_absent
)
2643 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2645 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2648 mips_assembling_insn
= FALSE
;
2651 /* Convenience functions for abstracting away the differences between
2652 MIPS16 and non-MIPS16 relocations. */
2654 static inline bfd_boolean
2655 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2659 case BFD_RELOC_MIPS16_JMP
:
2660 case BFD_RELOC_MIPS16_GPREL
:
2661 case BFD_RELOC_MIPS16_GOT16
:
2662 case BFD_RELOC_MIPS16_CALL16
:
2663 case BFD_RELOC_MIPS16_HI16_S
:
2664 case BFD_RELOC_MIPS16_HI16
:
2665 case BFD_RELOC_MIPS16_LO16
:
2673 static inline bfd_boolean
2674 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2678 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2679 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2680 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2681 case BFD_RELOC_MICROMIPS_GPREL16
:
2682 case BFD_RELOC_MICROMIPS_JMP
:
2683 case BFD_RELOC_MICROMIPS_HI16
:
2684 case BFD_RELOC_MICROMIPS_HI16_S
:
2685 case BFD_RELOC_MICROMIPS_LO16
:
2686 case BFD_RELOC_MICROMIPS_LITERAL
:
2687 case BFD_RELOC_MICROMIPS_GOT16
:
2688 case BFD_RELOC_MICROMIPS_CALL16
:
2689 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2690 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2691 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2692 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2693 case BFD_RELOC_MICROMIPS_SUB
:
2694 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2695 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2696 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2697 case BFD_RELOC_MICROMIPS_HIGHEST
:
2698 case BFD_RELOC_MICROMIPS_HIGHER
:
2699 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2700 case BFD_RELOC_MICROMIPS_JALR
:
2708 static inline bfd_boolean
2709 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2711 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2714 static inline bfd_boolean
2715 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2717 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2718 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2721 static inline bfd_boolean
2722 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2724 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2725 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2728 static inline bfd_boolean
2729 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2731 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2732 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2735 static inline bfd_boolean
2736 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2738 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2741 /* Return true if the given relocation might need a matching %lo().
2742 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2743 need a matching %lo() when applied to local symbols. */
2745 static inline bfd_boolean
2746 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2748 return (HAVE_IN_PLACE_ADDENDS
2749 && (hi16_reloc_p (reloc
)
2750 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2751 all GOT16 relocations evaluate to "G". */
2752 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2755 /* Return the type of %lo() reloc needed by RELOC, given that
2756 reloc_needs_lo_p. */
2758 static inline bfd_reloc_code_real_type
2759 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2761 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2762 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2766 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2769 static inline bfd_boolean
2770 fixup_has_matching_lo_p (fixS
*fixp
)
2772 return (fixp
->fx_next
!= NULL
2773 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2774 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2775 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2778 /* This function returns true if modifying a register requires a
2782 reg_needs_delay (unsigned int reg
)
2784 unsigned long prev_pinfo
;
2786 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2787 if (! mips_opts
.noreorder
2788 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2789 && ! gpr_interlocks
)
2790 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2791 && ! cop_interlocks
)))
2793 /* A load from a coprocessor or from memory. All load delays
2794 delay the use of general register rt for one instruction. */
2795 /* Itbl support may require additional care here. */
2796 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2797 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2804 /* Move all labels in LABELS to the current insertion point. TEXT_P
2805 says whether the labels refer to text or data. */
2808 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
2810 struct insn_label_list
*l
;
2813 for (l
= labels
; l
!= NULL
; l
= l
->next
)
2815 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2816 symbol_set_frag (l
->label
, frag_now
);
2817 val
= (valueT
) frag_now_fix ();
2818 /* MIPS16/microMIPS text labels are stored as odd. */
2819 if (text_p
&& HAVE_CODE_COMPRESSION
)
2821 S_SET_VALUE (l
->label
, val
);
2825 /* Move all labels in insn_labels to the current insertion point
2826 and treat them as text labels. */
2829 mips_move_text_labels (void)
2831 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
2835 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2837 bfd_boolean linkonce
= FALSE
;
2838 segT symseg
= S_GET_SEGMENT (sym
);
2840 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2842 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2845 /* The GNU toolchain uses an extension for ELF: a section
2846 beginning with the magic string .gnu.linkonce is a
2847 linkonce section. */
2848 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2849 sizeof ".gnu.linkonce" - 1) == 0)
2856 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2857 linker to handle them specially, such as generating jalx instructions
2858 when needed. We also make them odd for the duration of the assembly,
2859 in order to generate the right sort of code. We will make them even
2860 in the adjust_symtab routine, while leaving them marked. This is
2861 convenient for the debugger and the disassembler. The linker knows
2862 to make them odd again. */
2865 mips_compressed_mark_label (symbolS
*label
)
2867 gas_assert (HAVE_CODE_COMPRESSION
);
2869 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2872 if (mips_opts
.mips16
)
2873 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2875 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2878 if ((S_GET_VALUE (label
) & 1) == 0
2879 /* Don't adjust the address if the label is global or weak, or
2880 in a link-once section, since we'll be emitting symbol reloc
2881 references to it which will be patched up by the linker, and
2882 the final value of the symbol may or may not be MIPS16/microMIPS. */
2883 && !S_IS_WEAK (label
)
2884 && !S_IS_EXTERNAL (label
)
2885 && !s_is_linkonce (label
, now_seg
))
2886 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2889 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2892 mips_compressed_mark_labels (void)
2894 struct insn_label_list
*l
;
2896 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
2897 mips_compressed_mark_label (l
->label
);
2900 /* End the current frag. Make it a variant frag and record the
2904 relax_close_frag (void)
2906 mips_macro_warning
.first_frag
= frag_now
;
2907 frag_var (rs_machine_dependent
, 0, 0,
2908 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2909 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2911 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2912 mips_relax
.first_fixup
= 0;
2915 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2916 See the comment above RELAX_ENCODE for more details. */
2919 relax_start (symbolS
*symbol
)
2921 gas_assert (mips_relax
.sequence
== 0);
2922 mips_relax
.sequence
= 1;
2923 mips_relax
.symbol
= symbol
;
2926 /* Start generating the second version of a relaxable sequence.
2927 See the comment above RELAX_ENCODE for more details. */
2932 gas_assert (mips_relax
.sequence
== 1);
2933 mips_relax
.sequence
= 2;
2936 /* End the current relaxable sequence. */
2941 gas_assert (mips_relax
.sequence
== 2);
2942 relax_close_frag ();
2943 mips_relax
.sequence
= 0;
2946 /* Return true if IP is a delayed branch or jump. */
2948 static inline bfd_boolean
2949 delayed_branch_p (const struct mips_cl_insn
*ip
)
2951 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2952 | INSN_COND_BRANCH_DELAY
2953 | INSN_COND_BRANCH_LIKELY
)) != 0;
2956 /* Return true if IP is a compact branch or jump. */
2958 static inline bfd_boolean
2959 compact_branch_p (const struct mips_cl_insn
*ip
)
2961 if (mips_opts
.mips16
)
2962 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2963 | MIPS16_INSN_COND_BRANCH
)) != 0;
2965 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
2966 | INSN2_COND_BRANCH
)) != 0;
2969 /* Return true if IP is an unconditional branch or jump. */
2971 static inline bfd_boolean
2972 uncond_branch_p (const struct mips_cl_insn
*ip
)
2974 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
2975 || (mips_opts
.mips16
2976 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
2977 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
2980 /* Return true if IP is a branch-likely instruction. */
2982 static inline bfd_boolean
2983 branch_likely_p (const struct mips_cl_insn
*ip
)
2985 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
2988 /* Return the type of nop that should be used to fill the delay slot
2989 of delayed branch IP. */
2991 static struct mips_cl_insn
*
2992 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
2994 if (mips_opts
.micromips
2995 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
2996 return µmips_nop32_insn
;
3000 /* Return the mask of core registers that IP reads or writes. */
3003 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3005 unsigned long pinfo2
;
3009 pinfo2
= ip
->insn_mo
->pinfo2
;
3010 if (mips_opts
.micromips
)
3012 if (pinfo2
& INSN2_MOD_GPR_MD
)
3013 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3014 if (pinfo2
& INSN2_MOD_GPR_MF
)
3015 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3016 if (pinfo2
& INSN2_MOD_SP
)
3022 /* Return the mask of core registers that IP reads. */
3025 gpr_read_mask (const struct mips_cl_insn
*ip
)
3027 unsigned long pinfo
, pinfo2
;
3030 mask
= gpr_mod_mask (ip
);
3031 pinfo
= ip
->insn_mo
->pinfo
;
3032 pinfo2
= ip
->insn_mo
->pinfo2
;
3033 if (mips_opts
.mips16
)
3035 if (pinfo
& MIPS16_INSN_READ_X
)
3036 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3037 if (pinfo
& MIPS16_INSN_READ_Y
)
3038 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3039 if (pinfo
& MIPS16_INSN_READ_T
)
3041 if (pinfo
& MIPS16_INSN_READ_SP
)
3043 if (pinfo
& MIPS16_INSN_READ_31
)
3045 if (pinfo
& MIPS16_INSN_READ_Z
)
3046 mask
|= 1 << (mips16_to_32_reg_map
3047 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3048 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3049 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3053 if (pinfo2
& INSN2_READ_GPR_D
)
3054 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3055 if (pinfo
& INSN_READ_GPR_T
)
3056 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3057 if (pinfo
& INSN_READ_GPR_S
)
3058 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3059 if (pinfo2
& INSN2_READ_GP
)
3061 if (pinfo2
& INSN2_READ_GPR_31
)
3063 if (pinfo2
& INSN2_READ_GPR_Z
)
3064 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3066 if (mips_opts
.micromips
)
3068 if (pinfo2
& INSN2_READ_GPR_MC
)
3069 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3070 if (pinfo2
& INSN2_READ_GPR_ME
)
3071 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3072 if (pinfo2
& INSN2_READ_GPR_MG
)
3073 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3074 if (pinfo2
& INSN2_READ_GPR_MJ
)
3075 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3076 if (pinfo2
& INSN2_READ_GPR_MMN
)
3078 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3079 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3081 if (pinfo2
& INSN2_READ_GPR_MP
)
3082 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3083 if (pinfo2
& INSN2_READ_GPR_MQ
)
3084 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3086 /* Don't include register 0. */
3090 /* Return the mask of core registers that IP writes. */
3093 gpr_write_mask (const struct mips_cl_insn
*ip
)
3095 unsigned long pinfo
, pinfo2
;
3098 mask
= gpr_mod_mask (ip
);
3099 pinfo
= ip
->insn_mo
->pinfo
;
3100 pinfo2
= ip
->insn_mo
->pinfo2
;
3101 if (mips_opts
.mips16
)
3103 if (pinfo
& MIPS16_INSN_WRITE_X
)
3104 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3105 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3106 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3107 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3108 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3109 if (pinfo
& MIPS16_INSN_WRITE_T
)
3111 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3113 if (pinfo
& MIPS16_INSN_WRITE_31
)
3115 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3116 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3120 if (pinfo
& INSN_WRITE_GPR_D
)
3121 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3122 if (pinfo
& INSN_WRITE_GPR_T
)
3123 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3124 if (pinfo
& INSN_WRITE_GPR_S
)
3125 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3126 if (pinfo
& INSN_WRITE_GPR_31
)
3128 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3129 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3131 if (mips_opts
.micromips
)
3133 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3134 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3135 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3137 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3138 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3140 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3141 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3142 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3143 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3145 /* Don't include register 0. */
3149 /* Return the mask of floating-point registers that IP reads. */
3152 fpr_read_mask (const struct mips_cl_insn
*ip
)
3154 unsigned long pinfo
, pinfo2
;
3158 pinfo
= ip
->insn_mo
->pinfo
;
3159 pinfo2
= ip
->insn_mo
->pinfo2
;
3160 if (!mips_opts
.mips16
)
3162 if (pinfo2
& INSN2_READ_FPR_D
)
3163 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3164 if (pinfo
& INSN_READ_FPR_S
)
3165 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3166 if (pinfo
& INSN_READ_FPR_T
)
3167 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3168 if (pinfo
& INSN_READ_FPR_R
)
3169 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3170 if (pinfo2
& INSN2_READ_FPR_Z
)
3171 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3173 /* Conservatively treat all operands to an FP_D instruction are doubles.
3174 (This is overly pessimistic for things like cvt.d.s.) */
3175 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3180 /* Return the mask of floating-point registers that IP writes. */
3183 fpr_write_mask (const struct mips_cl_insn
*ip
)
3185 unsigned long pinfo
, pinfo2
;
3189 pinfo
= ip
->insn_mo
->pinfo
;
3190 pinfo2
= ip
->insn_mo
->pinfo2
;
3191 if (!mips_opts
.mips16
)
3193 if (pinfo
& INSN_WRITE_FPR_D
)
3194 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3195 if (pinfo
& INSN_WRITE_FPR_S
)
3196 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3197 if (pinfo
& INSN_WRITE_FPR_T
)
3198 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3199 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3200 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3202 /* Conservatively treat all operands to an FP_D instruction are doubles.
3203 (This is overly pessimistic for things like cvt.s.d.) */
3204 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3209 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3210 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3211 by VR4120 errata. */
3214 classify_vr4120_insn (const char *name
)
3216 if (strncmp (name
, "macc", 4) == 0)
3217 return FIX_VR4120_MACC
;
3218 if (strncmp (name
, "dmacc", 5) == 0)
3219 return FIX_VR4120_DMACC
;
3220 if (strncmp (name
, "mult", 4) == 0)
3221 return FIX_VR4120_MULT
;
3222 if (strncmp (name
, "dmult", 5) == 0)
3223 return FIX_VR4120_DMULT
;
3224 if (strstr (name
, "div"))
3225 return FIX_VR4120_DIV
;
3226 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3227 return FIX_VR4120_MTHILO
;
3228 return NUM_FIX_VR4120_CLASSES
;
3231 #define INSN_ERET 0x42000018
3232 #define INSN_DERET 0x4200001f
3234 /* Return the number of instructions that must separate INSN1 and INSN2,
3235 where INSN1 is the earlier instruction. Return the worst-case value
3236 for any INSN2 if INSN2 is null. */
3239 insns_between (const struct mips_cl_insn
*insn1
,
3240 const struct mips_cl_insn
*insn2
)
3242 unsigned long pinfo1
, pinfo2
;
3245 /* This function needs to know which pinfo flags are set for INSN2
3246 and which registers INSN2 uses. The former is stored in PINFO2 and
3247 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3248 will have every flag set and INSN2_USES_GPR will always return true. */
3249 pinfo1
= insn1
->insn_mo
->pinfo
;
3250 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3252 #define INSN2_USES_GPR(REG) \
3253 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3255 /* For most targets, write-after-read dependencies on the HI and LO
3256 registers must be separated by at least two instructions. */
3257 if (!hilo_interlocks
)
3259 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3261 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3265 /* If we're working around r7000 errata, there must be two instructions
3266 between an mfhi or mflo and any instruction that uses the result. */
3267 if (mips_7000_hilo_fix
3268 && !mips_opts
.micromips
3269 && MF_HILO_INSN (pinfo1
)
3270 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3273 /* If we're working around 24K errata, one instruction is required
3274 if an ERET or DERET is followed by a branch instruction. */
3275 if (mips_fix_24k
&& !mips_opts
.micromips
)
3277 if (insn1
->insn_opcode
== INSN_ERET
3278 || insn1
->insn_opcode
== INSN_DERET
)
3281 || insn2
->insn_opcode
== INSN_ERET
3282 || insn2
->insn_opcode
== INSN_DERET
3283 || delayed_branch_p (insn2
))
3288 /* If working around VR4120 errata, check for combinations that need
3289 a single intervening instruction. */
3290 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3292 unsigned int class1
, class2
;
3294 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3295 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3299 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3300 if (vr4120_conflicts
[class1
] & (1 << class2
))
3305 if (!HAVE_CODE_COMPRESSION
)
3307 /* Check for GPR or coprocessor load delays. All such delays
3308 are on the RT register. */
3309 /* Itbl support may require additional care here. */
3310 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3311 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3313 know (pinfo1
& INSN_WRITE_GPR_T
);
3314 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3318 /* Check for generic coprocessor hazards.
3320 This case is not handled very well. There is no special
3321 knowledge of CP0 handling, and the coprocessors other than
3322 the floating point unit are not distinguished at all. */
3323 /* Itbl support may require additional care here. FIXME!
3324 Need to modify this to include knowledge about
3325 user specified delays! */
3326 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3327 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3329 /* Handle cases where INSN1 writes to a known general coprocessor
3330 register. There must be a one instruction delay before INSN2
3331 if INSN2 reads that register, otherwise no delay is needed. */
3332 mask
= fpr_write_mask (insn1
);
3335 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3340 /* Read-after-write dependencies on the control registers
3341 require a two-instruction gap. */
3342 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3343 && (pinfo2
& INSN_READ_COND_CODE
))
3346 /* We don't know exactly what INSN1 does. If INSN2 is
3347 also a coprocessor instruction, assume there must be
3348 a one instruction gap. */
3349 if (pinfo2
& INSN_COP
)
3354 /* Check for read-after-write dependencies on the coprocessor
3355 control registers in cases where INSN1 does not need a general
3356 coprocessor delay. This means that INSN1 is a floating point
3357 comparison instruction. */
3358 /* Itbl support may require additional care here. */
3359 else if (!cop_interlocks
3360 && (pinfo1
& INSN_WRITE_COND_CODE
)
3361 && (pinfo2
& INSN_READ_COND_CODE
))
3365 #undef INSN2_USES_GPR
3370 /* Return the number of nops that would be needed to work around the
3371 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3372 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3373 that are contained within the first IGNORE instructions of HIST. */
3376 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3377 const struct mips_cl_insn
*insn
)
3382 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3383 are not affected by the errata. */
3385 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3386 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3387 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3390 /* Search for the first MFLO or MFHI. */
3391 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3392 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3394 /* Extract the destination register. */
3395 mask
= gpr_write_mask (&hist
[i
]);
3397 /* No nops are needed if INSN reads that register. */
3398 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3401 /* ...or if any of the intervening instructions do. */
3402 for (j
= 0; j
< i
; j
++)
3403 if (gpr_read_mask (&hist
[j
]) & mask
)
3407 return MAX_VR4130_NOPS
- i
;
3412 #define BASE_REG_EQ(INSN1, INSN2) \
3413 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3414 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3416 /* Return the minimum alignment for this store instruction. */
3419 fix_24k_align_to (const struct mips_opcode
*mo
)
3421 if (strcmp (mo
->name
, "sh") == 0)
3424 if (strcmp (mo
->name
, "swc1") == 0
3425 || strcmp (mo
->name
, "swc2") == 0
3426 || strcmp (mo
->name
, "sw") == 0
3427 || strcmp (mo
->name
, "sc") == 0
3428 || strcmp (mo
->name
, "s.s") == 0)
3431 if (strcmp (mo
->name
, "sdc1") == 0
3432 || strcmp (mo
->name
, "sdc2") == 0
3433 || strcmp (mo
->name
, "s.d") == 0)
3440 struct fix_24k_store_info
3442 /* Immediate offset, if any, for this store instruction. */
3444 /* Alignment required by this store instruction. */
3446 /* True for register offsets. */
3447 int register_offset
;
3450 /* Comparison function used by qsort. */
3453 fix_24k_sort (const void *a
, const void *b
)
3455 const struct fix_24k_store_info
*pos1
= a
;
3456 const struct fix_24k_store_info
*pos2
= b
;
3458 return (pos1
->off
- pos2
->off
);
3461 /* INSN is a store instruction. Try to record the store information
3462 in STINFO. Return false if the information isn't known. */
3465 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3466 const struct mips_cl_insn
*insn
)
3468 /* The instruction must have a known offset. */
3469 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3472 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3473 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3477 /* Return the number of nops that would be needed to work around the 24k
3478 "lost data on stores during refill" errata if instruction INSN
3479 immediately followed the 2 instructions described by HIST.
3480 Ignore hazards that are contained within the first IGNORE
3481 instructions of HIST.
3483 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3484 for the data cache refills and store data. The following describes
3485 the scenario where the store data could be lost.
3487 * A data cache miss, due to either a load or a store, causing fill
3488 data to be supplied by the memory subsystem
3489 * The first three doublewords of fill data are returned and written
3491 * A sequence of four stores occurs in consecutive cycles around the
3492 final doubleword of the fill:
3496 * Zero, One or more instructions
3499 The four stores A-D must be to different doublewords of the line that
3500 is being filled. The fourth instruction in the sequence above permits
3501 the fill of the final doubleword to be transferred from the FSB into
3502 the cache. In the sequence above, the stores may be either integer
3503 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3504 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3505 different doublewords on the line. If the floating point unit is
3506 running in 1:2 mode, it is not possible to create the sequence above
3507 using only floating point store instructions.
3509 In this case, the cache line being filled is incorrectly marked
3510 invalid, thereby losing the data from any store to the line that
3511 occurs between the original miss and the completion of the five
3512 cycle sequence shown above.
3514 The workarounds are:
3516 * Run the data cache in write-through mode.
3517 * Insert a non-store instruction between
3518 Store A and Store B or Store B and Store C. */
3521 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3522 const struct mips_cl_insn
*insn
)
3524 struct fix_24k_store_info pos
[3];
3525 int align
, i
, base_offset
;
3530 /* If the previous instruction wasn't a store, there's nothing to
3532 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3535 /* If the instructions after the previous one are unknown, we have
3536 to assume the worst. */
3540 /* Check whether we are dealing with three consecutive stores. */
3541 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3542 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3545 /* If we don't know the relationship between the store addresses,
3546 assume the worst. */
3547 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3548 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3551 if (!fix_24k_record_store_info (&pos
[0], insn
)
3552 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3553 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3556 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3558 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3559 X bytes and such that the base register + X is known to be aligned
3562 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3566 align
= pos
[0].align_to
;
3567 base_offset
= pos
[0].off
;
3568 for (i
= 1; i
< 3; i
++)
3569 if (align
< pos
[i
].align_to
)
3571 align
= pos
[i
].align_to
;
3572 base_offset
= pos
[i
].off
;
3574 for (i
= 0; i
< 3; i
++)
3575 pos
[i
].off
-= base_offset
;
3578 pos
[0].off
&= ~align
+ 1;
3579 pos
[1].off
&= ~align
+ 1;
3580 pos
[2].off
&= ~align
+ 1;
3582 /* If any two stores write to the same chunk, they also write to the
3583 same doubleword. The offsets are still sorted at this point. */
3584 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3587 /* A range of at least 9 bytes is needed for the stores to be in
3588 non-overlapping doublewords. */
3589 if (pos
[2].off
- pos
[0].off
<= 8)
3592 if (pos
[2].off
- pos
[1].off
>= 24
3593 || pos
[1].off
- pos
[0].off
>= 24
3594 || pos
[2].off
- pos
[0].off
>= 32)
3600 /* Return the number of nops that would be needed if instruction INSN
3601 immediately followed the MAX_NOPS instructions given by HIST,
3602 where HIST[0] is the most recent instruction. Ignore hazards
3603 between INSN and the first IGNORE instructions in HIST.
3605 If INSN is null, return the worse-case number of nops for any
3609 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3610 const struct mips_cl_insn
*insn
)
3612 int i
, nops
, tmp_nops
;
3615 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3617 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3618 if (tmp_nops
> nops
)
3622 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3624 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3625 if (tmp_nops
> nops
)
3629 if (mips_fix_24k
&& !mips_opts
.micromips
)
3631 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3632 if (tmp_nops
> nops
)
3639 /* The variable arguments provide NUM_INSNS extra instructions that
3640 might be added to HIST. Return the largest number of nops that
3641 would be needed after the extended sequence, ignoring hazards
3642 in the first IGNORE instructions. */
3645 nops_for_sequence (int num_insns
, int ignore
,
3646 const struct mips_cl_insn
*hist
, ...)
3649 struct mips_cl_insn buffer
[MAX_NOPS
];
3650 struct mips_cl_insn
*cursor
;
3653 va_start (args
, hist
);
3654 cursor
= buffer
+ num_insns
;
3655 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3656 while (cursor
> buffer
)
3657 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3659 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3664 /* Like nops_for_insn, but if INSN is a branch, take into account the
3665 worst-case delay for the branch target. */
3668 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3669 const struct mips_cl_insn
*insn
)
3673 nops
= nops_for_insn (ignore
, hist
, insn
);
3674 if (delayed_branch_p (insn
))
3676 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3677 hist
, insn
, get_delay_slot_nop (insn
));
3678 if (tmp_nops
> nops
)
3681 else if (compact_branch_p (insn
))
3683 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3684 if (tmp_nops
> nops
)
3690 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3693 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3695 gas_assert (!HAVE_CODE_COMPRESSION
);
3696 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3697 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3700 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3701 jr target pc &= 'hffff_ffff_cfff_ffff. */
3704 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3706 gas_assert (!HAVE_CODE_COMPRESSION
);
3707 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3708 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3709 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3717 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3718 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3721 ep
.X_op
= O_constant
;
3722 ep
.X_add_number
= 0xcfff0000;
3723 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3724 ep
.X_add_number
= 0xffff;
3725 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3726 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3731 fix_loongson2f (struct mips_cl_insn
* ip
)
3733 if (mips_fix_loongson2f_nop
)
3734 fix_loongson2f_nop (ip
);
3736 if (mips_fix_loongson2f_jump
)
3737 fix_loongson2f_jump (ip
);
3740 /* IP is a branch that has a delay slot, and we need to fill it
3741 automatically. Return true if we can do that by swapping IP
3742 with the previous instruction.
3743 ADDRESS_EXPR is an operand of the instruction to be used with
3747 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3748 bfd_reloc_code_real_type
*reloc_type
)
3750 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3751 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3753 /* -O2 and above is required for this optimization. */
3754 if (mips_optimize
< 2)
3757 /* If we have seen .set volatile or .set nomove, don't optimize. */
3758 if (mips_opts
.nomove
)
3761 /* We can't swap if the previous instruction's position is fixed. */
3762 if (history
[0].fixed_p
)
3765 /* If the previous previous insn was in a .set noreorder, we can't
3766 swap. Actually, the MIPS assembler will swap in this situation.
3767 However, gcc configured -with-gnu-as will generate code like
3775 in which we can not swap the bne and INSN. If gcc is not configured
3776 -with-gnu-as, it does not output the .set pseudo-ops. */
3777 if (history
[1].noreorder_p
)
3780 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3781 This means that the previous instruction was a 4-byte one anyhow. */
3782 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3785 /* If the branch is itself the target of a branch, we can not swap.
3786 We cheat on this; all we check for is whether there is a label on
3787 this instruction. If there are any branches to anything other than
3788 a label, users must use .set noreorder. */
3789 if (seg_info (now_seg
)->label_list
)
3792 /* If the previous instruction is in a variant frag other than this
3793 branch's one, we cannot do the swap. This does not apply to
3794 MIPS16 code, which uses variant frags for different purposes. */
3795 if (!mips_opts
.mips16
3797 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3800 /* We do not swap with instructions that cannot architecturally
3801 be placed in a branch delay slot, such as SYNC or ERET. We
3802 also refrain from swapping with a trap instruction, since it
3803 complicates trap handlers to have the trap instruction be in
3805 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3806 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3809 /* Check for conflicts between the branch and the instructions
3810 before the candidate delay slot. */
3811 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3814 /* Check for conflicts between the swapped sequence and the
3815 target of the branch. */
3816 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3819 /* If the branch reads a register that the previous
3820 instruction sets, we can not swap. */
3821 gpr_read
= gpr_read_mask (ip
);
3822 prev_gpr_write
= gpr_write_mask (&history
[0]);
3823 if (gpr_read
& prev_gpr_write
)
3826 /* If the branch writes a register that the previous
3827 instruction sets, we can not swap. */
3828 gpr_write
= gpr_write_mask (ip
);
3829 if (gpr_write
& prev_gpr_write
)
3832 /* If the branch writes a register that the previous
3833 instruction reads, we can not swap. */
3834 prev_gpr_read
= gpr_read_mask (&history
[0]);
3835 if (gpr_write
& prev_gpr_read
)
3838 /* If one instruction sets a condition code and the
3839 other one uses a condition code, we can not swap. */
3840 pinfo
= ip
->insn_mo
->pinfo
;
3841 if ((pinfo
& INSN_READ_COND_CODE
)
3842 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3844 if ((pinfo
& INSN_WRITE_COND_CODE
)
3845 && (prev_pinfo
& INSN_READ_COND_CODE
))
3848 /* If the previous instruction uses the PC, we can not swap. */
3849 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3850 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3852 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3855 /* If the previous instruction has an incorrect size for a fixed
3856 branch delay slot in microMIPS mode, we cannot swap. */
3857 pinfo2
= ip
->insn_mo
->pinfo2
;
3858 if (mips_opts
.micromips
3859 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3860 && insn_length (history
) != 2)
3862 if (mips_opts
.micromips
3863 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3864 && insn_length (history
) != 4)
3867 /* On R5900 short loops need to be fixed by inserting a nop in
3868 the branch delay slots.
3869 A short loop can be terminated too early. */
3870 if (mips_opts
.arch
== CPU_R5900
3871 /* Check if instruction has a parameter, ignore "j $31". */
3872 && (address_expr
!= NULL
)
3873 /* Parameter must be 16 bit. */
3874 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
3875 /* Branch to same segment. */
3876 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
3877 /* Branch to same code fragment. */
3878 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
3879 /* Can only calculate branch offset if value is known. */
3880 && symbol_constant_p(address_expr
->X_add_symbol
)
3881 /* Check if branch is really conditional. */
3882 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
3883 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
3884 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
3887 /* Check if loop is shorter than 6 instructions including
3888 branch and delay slot. */
3889 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
3896 /* When the loop includes branches or jumps,
3897 it is not a short loop. */
3898 for (i
= 0; i
< (distance
/ 4); i
++)
3900 if ((history
[i
].cleared_p
)
3901 || delayed_branch_p(&history
[i
]))
3909 /* Insert nop after branch to fix short loop. */
3918 /* Decide how we should add IP to the instruction stream.
3919 ADDRESS_EXPR is an operand of the instruction to be used with
3922 static enum append_method
3923 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3924 bfd_reloc_code_real_type
*reloc_type
)
3926 unsigned long pinfo
;
3928 /* The relaxed version of a macro sequence must be inherently
3930 if (mips_relax
.sequence
== 2)
3933 /* We must not dabble with instructions in a ".set norerorder" block. */
3934 if (mips_opts
.noreorder
)
3937 /* Otherwise, it's our responsibility to fill branch delay slots. */
3938 if (delayed_branch_p (ip
))
3940 if (!branch_likely_p (ip
)
3941 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
3944 pinfo
= ip
->insn_mo
->pinfo
;
3945 if (mips_opts
.mips16
3946 && ISA_SUPPORTS_MIPS16E
3947 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
3948 return APPEND_ADD_COMPACT
;
3950 return APPEND_ADD_WITH_NOP
;
3956 /* IP is a MIPS16 instruction whose opcode we have just changed.
3957 Point IP->insn_mo to the new opcode's definition. */
3960 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
3962 const struct mips_opcode
*mo
, *end
;
3964 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
3965 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
3966 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
3974 /* For microMIPS macros, we need to generate a local number label
3975 as the target of branches. */
3976 #define MICROMIPS_LABEL_CHAR '\037'
3977 static unsigned long micromips_target_label
;
3978 static char micromips_target_name
[32];
3981 micromips_label_name (void)
3983 char *p
= micromips_target_name
;
3984 char symbol_name_temporary
[24];
3992 l
= micromips_target_label
;
3993 #ifdef LOCAL_LABEL_PREFIX
3994 *p
++ = LOCAL_LABEL_PREFIX
;
3997 *p
++ = MICROMIPS_LABEL_CHAR
;
4000 symbol_name_temporary
[i
++] = l
% 10 + '0';
4005 *p
++ = symbol_name_temporary
[--i
];
4008 return micromips_target_name
;
4012 micromips_label_expr (expressionS
*label_expr
)
4014 label_expr
->X_op
= O_symbol
;
4015 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
4016 label_expr
->X_add_number
= 0;
4020 micromips_label_inc (void)
4022 micromips_target_label
++;
4023 *micromips_target_name
= '\0';
4027 micromips_add_label (void)
4031 s
= colon (micromips_label_name ());
4032 micromips_label_inc ();
4033 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4035 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
4041 /* If assembling microMIPS code, then return the microMIPS reloc
4042 corresponding to the requested one if any. Otherwise return
4043 the reloc unchanged. */
4045 static bfd_reloc_code_real_type
4046 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
4048 static const bfd_reloc_code_real_type relocs
[][2] =
4050 /* Keep sorted incrementally by the left-hand key. */
4051 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
4052 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
4053 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
4054 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
4055 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
4056 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
4057 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
4058 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
4059 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
4060 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
4061 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
4062 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
4063 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
4064 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
4065 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
4066 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
4067 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
4068 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
4069 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4070 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4071 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4072 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4073 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4074 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4075 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4076 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4077 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4079 bfd_reloc_code_real_type r
;
4082 if (!mips_opts
.micromips
)
4084 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4090 return relocs
[i
][1];
4095 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4096 Return true on success, storing the resolved value in RESULT. */
4099 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
4104 case BFD_RELOC_MIPS_HIGHEST
:
4105 case BFD_RELOC_MICROMIPS_HIGHEST
:
4106 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
4109 case BFD_RELOC_MIPS_HIGHER
:
4110 case BFD_RELOC_MICROMIPS_HIGHER
:
4111 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
4114 case BFD_RELOC_HI16_S
:
4115 case BFD_RELOC_MICROMIPS_HI16_S
:
4116 case BFD_RELOC_MIPS16_HI16_S
:
4117 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
4120 case BFD_RELOC_HI16
:
4121 case BFD_RELOC_MICROMIPS_HI16
:
4122 case BFD_RELOC_MIPS16_HI16
:
4123 *result
= (operand
>> 16) & 0xffff;
4126 case BFD_RELOC_LO16
:
4127 case BFD_RELOC_MICROMIPS_LO16
:
4128 case BFD_RELOC_MIPS16_LO16
:
4129 *result
= operand
& 0xffff;
4132 case BFD_RELOC_UNUSED
:
4141 /* Output an instruction. IP is the instruction information.
4142 ADDRESS_EXPR is an operand of the instruction to be used with
4143 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4144 a macro expansion. */
4147 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4148 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4150 unsigned long prev_pinfo2
, pinfo
;
4151 bfd_boolean relaxed_branch
= FALSE
;
4152 enum append_method method
;
4153 bfd_boolean relax32
;
4156 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4157 fix_loongson2f (ip
);
4159 file_ase_mips16
|= mips_opts
.mips16
;
4160 file_ase_micromips
|= mips_opts
.micromips
;
4162 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4163 pinfo
= ip
->insn_mo
->pinfo
;
4165 if (mips_opts
.micromips
4167 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4168 && micromips_insn_length (ip
->insn_mo
) != 2)
4169 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4170 && micromips_insn_length (ip
->insn_mo
) != 4)))
4171 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4172 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4174 if (address_expr
== NULL
)
4176 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
4177 && reloc_type
[1] == BFD_RELOC_UNUSED
4178 && reloc_type
[2] == BFD_RELOC_UNUSED
4179 && address_expr
->X_op
== O_constant
)
4181 switch (*reloc_type
)
4183 case BFD_RELOC_MIPS_JMP
:
4187 shift
= mips_opts
.micromips
? 1 : 2;
4188 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4189 as_bad (_("jump to misaligned address (0x%lx)"),
4190 (unsigned long) address_expr
->X_add_number
);
4191 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4197 case BFD_RELOC_MIPS16_JMP
:
4198 if ((address_expr
->X_add_number
& 3) != 0)
4199 as_bad (_("jump to misaligned address (0x%lx)"),
4200 (unsigned long) address_expr
->X_add_number
);
4202 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4203 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4204 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4208 case BFD_RELOC_16_PCREL_S2
:
4212 shift
= mips_opts
.micromips
? 1 : 2;
4213 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4214 as_bad (_("branch to misaligned address (0x%lx)"),
4215 (unsigned long) address_expr
->X_add_number
);
4216 if (!mips_relax_branch
)
4218 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4219 & ~((1 << (shift
+ 16)) - 1))
4220 as_bad (_("branch address range overflow (0x%lx)"),
4221 (unsigned long) address_expr
->X_add_number
);
4222 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4232 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
4235 ip
->insn_opcode
|= value
& 0xffff;
4243 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4245 /* There are a lot of optimizations we could do that we don't.
4246 In particular, we do not, in general, reorder instructions.
4247 If you use gcc with optimization, it will reorder
4248 instructions and generally do much more optimization then we
4249 do here; repeating all that work in the assembler would only
4250 benefit hand written assembly code, and does not seem worth
4252 int nops
= (mips_optimize
== 0
4253 ? nops_for_insn (0, history
, NULL
)
4254 : nops_for_insn_or_target (0, history
, ip
));
4258 unsigned long old_frag_offset
;
4261 old_frag
= frag_now
;
4262 old_frag_offset
= frag_now_fix ();
4264 for (i
= 0; i
< nops
; i
++)
4265 add_fixed_insn (NOP_INSN
);
4266 insert_into_history (0, nops
, NOP_INSN
);
4270 listing_prev_line ();
4271 /* We may be at the start of a variant frag. In case we
4272 are, make sure there is enough space for the frag
4273 after the frags created by listing_prev_line. The
4274 argument to frag_grow here must be at least as large
4275 as the argument to all other calls to frag_grow in
4276 this file. We don't have to worry about being in the
4277 middle of a variant frag, because the variants insert
4278 all needed nop instructions themselves. */
4282 mips_move_text_labels ();
4284 #ifndef NO_ECOFF_DEBUGGING
4285 if (ECOFF_DEBUGGING
)
4286 ecoff_fix_loc (old_frag
, old_frag_offset
);
4290 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4294 /* Work out how many nops in prev_nop_frag are needed by IP,
4295 ignoring hazards generated by the first prev_nop_frag_since
4297 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4298 gas_assert (nops
<= prev_nop_frag_holds
);
4300 /* Enforce NOPS as a minimum. */
4301 if (nops
> prev_nop_frag_required
)
4302 prev_nop_frag_required
= nops
;
4304 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4306 /* Settle for the current number of nops. Update the history
4307 accordingly (for the benefit of any future .set reorder code). */
4308 prev_nop_frag
= NULL
;
4309 insert_into_history (prev_nop_frag_since
,
4310 prev_nop_frag_holds
, NOP_INSN
);
4314 /* Allow this instruction to replace one of the nops that was
4315 tentatively added to prev_nop_frag. */
4316 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4317 prev_nop_frag_holds
--;
4318 prev_nop_frag_since
++;
4322 method
= get_append_method (ip
, address_expr
, reloc_type
);
4323 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4326 /* The value passed to dwarf2_emit_insn is the distance between
4327 the beginning of the current instruction and the address that
4328 should be recorded in the debug tables. This is normally the
4331 For MIPS16/microMIPS debug info we want to use ISA-encoded
4332 addresses, so we use -1 for an address higher by one than the
4335 If the instruction produced is a branch that we will swap with
4336 the preceding instruction, then we add the displacement by which
4337 the branch will be moved backwards. This is more appropriate
4338 and for MIPS16/microMIPS code also prevents a debugger from
4339 placing a breakpoint in the middle of the branch (and corrupting
4340 code if software breakpoints are used). */
4341 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION
? -1 : 0) + branch_disp
);
4344 relax32
= (mips_relax_branch
4345 /* Don't try branch relaxation within .set nomacro, or within
4346 .set noat if we use $at for PIC computations. If it turns
4347 out that the branch was out-of-range, we'll get an error. */
4348 && !mips_opts
.warn_about_macros
4349 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4350 /* Don't relax BPOSGE32/64 as they have no complementing
4352 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
)));
4354 if (!HAVE_CODE_COMPRESSION
4357 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4358 && delayed_branch_p (ip
))
4360 relaxed_branch
= TRUE
;
4361 add_relaxed_insn (ip
, (relaxed_branch_length
4363 uncond_branch_p (ip
) ? -1
4364 : branch_likely_p (ip
) ? 1
4368 uncond_branch_p (ip
),
4369 branch_likely_p (ip
),
4370 pinfo
& INSN_WRITE_GPR_31
,
4372 address_expr
->X_add_symbol
,
4373 address_expr
->X_add_number
);
4374 *reloc_type
= BFD_RELOC_UNUSED
;
4376 else if (mips_opts
.micromips
4378 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4379 || *reloc_type
> BFD_RELOC_UNUSED
)
4380 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4381 /* Don't try branch relaxation when users specify
4382 16-bit/32-bit instructions. */
4383 && !forced_insn_length
)
4385 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4386 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4387 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4388 int compact
= compact_branch_p (ip
);
4389 int al
= pinfo
& INSN_WRITE_GPR_31
;
4392 gas_assert (address_expr
!= NULL
);
4393 gas_assert (!mips_relax
.sequence
);
4395 relaxed_branch
= TRUE
;
4396 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4397 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4398 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4400 address_expr
->X_add_symbol
,
4401 address_expr
->X_add_number
);
4402 *reloc_type
= BFD_RELOC_UNUSED
;
4404 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4406 /* We need to set up a variant frag. */
4407 gas_assert (address_expr
!= NULL
);
4408 add_relaxed_insn (ip
, 4, 0,
4410 (*reloc_type
- BFD_RELOC_UNUSED
,
4411 forced_insn_length
== 2, forced_insn_length
== 4,
4412 delayed_branch_p (&history
[0]),
4413 history
[0].mips16_absolute_jump_p
),
4414 make_expr_symbol (address_expr
), 0);
4416 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4418 if (!delayed_branch_p (ip
))
4419 /* Make sure there is enough room to swap this instruction with
4420 a following jump instruction. */
4422 add_fixed_insn (ip
);
4426 if (mips_opts
.mips16
4427 && mips_opts
.noreorder
4428 && delayed_branch_p (&history
[0]))
4429 as_warn (_("extended instruction in delay slot"));
4431 if (mips_relax
.sequence
)
4433 /* If we've reached the end of this frag, turn it into a variant
4434 frag and record the information for the instructions we've
4436 if (frag_room () < 4)
4437 relax_close_frag ();
4438 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4441 if (mips_relax
.sequence
!= 2)
4443 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4444 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4445 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4446 mips_macro_warning
.insns
[0]++;
4448 if (mips_relax
.sequence
!= 1)
4450 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4451 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4452 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4453 mips_macro_warning
.insns
[1]++;
4456 if (mips_opts
.mips16
)
4459 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4461 add_fixed_insn (ip
);
4464 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4466 bfd_reloc_code_real_type final_type
[3];
4467 reloc_howto_type
*howto0
;
4468 reloc_howto_type
*howto
;
4471 /* Perform any necessary conversion to microMIPS relocations
4472 and find out how many relocations there actually are. */
4473 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4474 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4476 /* In a compound relocation, it is the final (outermost)
4477 operator that determines the relocated field. */
4478 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4482 /* To reproduce this failure try assembling gas/testsuites/
4483 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4485 as_bad (_("Unsupported MIPS relocation number %d"),
4487 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4491 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4492 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4493 bfd_get_reloc_size (howto
),
4495 howto0
&& howto0
->pc_relative
,
4498 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4499 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4500 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4502 /* These relocations can have an addend that won't fit in
4503 4 octets for 64bit assembly. */
4505 && ! howto
->partial_inplace
4506 && (reloc_type
[0] == BFD_RELOC_16
4507 || reloc_type
[0] == BFD_RELOC_32
4508 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4509 || reloc_type
[0] == BFD_RELOC_GPREL16
4510 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4511 || reloc_type
[0] == BFD_RELOC_GPREL32
4512 || reloc_type
[0] == BFD_RELOC_64
4513 || reloc_type
[0] == BFD_RELOC_CTOR
4514 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4515 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4516 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4517 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4518 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4519 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4520 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4521 || hi16_reloc_p (reloc_type
[0])
4522 || lo16_reloc_p (reloc_type
[0])))
4523 ip
->fixp
[0]->fx_no_overflow
= 1;
4525 /* These relocations can have an addend that won't fit in 2 octets. */
4526 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4527 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
4528 ip
->fixp
[0]->fx_no_overflow
= 1;
4530 if (mips_relax
.sequence
)
4532 if (mips_relax
.first_fixup
== 0)
4533 mips_relax
.first_fixup
= ip
->fixp
[0];
4535 else if (reloc_needs_lo_p (*reloc_type
))
4537 struct mips_hi_fixup
*hi_fixup
;
4539 /* Reuse the last entry if it already has a matching %lo. */
4540 hi_fixup
= mips_hi_fixup_list
;
4542 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4544 hi_fixup
= ((struct mips_hi_fixup
*)
4545 xmalloc (sizeof (struct mips_hi_fixup
)));
4546 hi_fixup
->next
= mips_hi_fixup_list
;
4547 mips_hi_fixup_list
= hi_fixup
;
4549 hi_fixup
->fixp
= ip
->fixp
[0];
4550 hi_fixup
->seg
= now_seg
;
4553 /* Add fixups for the second and third relocations, if given.
4554 Note that the ABI allows the second relocation to be
4555 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4556 moment we only use RSS_UNDEF, but we could add support
4557 for the others if it ever becomes necessary. */
4558 for (i
= 1; i
< 3; i
++)
4559 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4561 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4562 ip
->fixp
[0]->fx_size
, NULL
, 0,
4563 FALSE
, final_type
[i
]);
4565 /* Use fx_tcbit to mark compound relocs. */
4566 ip
->fixp
[0]->fx_tcbit
= 1;
4567 ip
->fixp
[i
]->fx_tcbit
= 1;
4572 /* Update the register mask information. */
4573 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4574 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4579 insert_into_history (0, 1, ip
);
4582 case APPEND_ADD_WITH_NOP
:
4584 struct mips_cl_insn
*nop
;
4586 insert_into_history (0, 1, ip
);
4587 nop
= get_delay_slot_nop (ip
);
4588 add_fixed_insn (nop
);
4589 insert_into_history (0, 1, nop
);
4590 if (mips_relax
.sequence
)
4591 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4595 case APPEND_ADD_COMPACT
:
4596 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4597 gas_assert (mips_opts
.mips16
);
4598 ip
->insn_opcode
|= 0x0080;
4599 find_altered_mips16_opcode (ip
);
4601 insert_into_history (0, 1, ip
);
4606 struct mips_cl_insn delay
= history
[0];
4607 if (mips_opts
.mips16
)
4609 know (delay
.frag
== ip
->frag
);
4610 move_insn (ip
, delay
.frag
, delay
.where
);
4611 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4613 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4615 /* Add the delay slot instruction to the end of the
4616 current frag and shrink the fixed part of the
4617 original frag. If the branch occupies the tail of
4618 the latter, move it backwards to cover the gap. */
4619 delay
.frag
->fr_fix
-= branch_disp
;
4620 if (delay
.frag
== ip
->frag
)
4621 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4622 add_fixed_insn (&delay
);
4626 move_insn (&delay
, ip
->frag
,
4627 ip
->where
- branch_disp
+ insn_length (ip
));
4628 move_insn (ip
, history
[0].frag
, history
[0].where
);
4632 insert_into_history (0, 1, &delay
);
4637 /* If we have just completed an unconditional branch, clear the history. */
4638 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4639 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4643 mips_no_prev_insn ();
4645 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4647 history
[i
].cleared_p
= 1;
4651 /* We need to emit a label at the end of branch-likely macros. */
4652 if (emit_branch_likely_macro
)
4654 emit_branch_likely_macro
= FALSE
;
4655 micromips_add_label ();
4658 /* We just output an insn, so the next one doesn't have a label. */
4659 mips_clear_insn_labels ();
4662 /* Forget that there was any previous instruction or label.
4663 When BRANCH is true, the branch history is also flushed. */
4666 mips_no_prev_insn (void)
4668 prev_nop_frag
= NULL
;
4669 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4670 mips_clear_insn_labels ();
4673 /* This function must be called before we emit something other than
4674 instructions. It is like mips_no_prev_insn except that it inserts
4675 any NOPS that might be needed by previous instructions. */
4678 mips_emit_delays (void)
4680 if (! mips_opts
.noreorder
)
4682 int nops
= nops_for_insn (0, history
, NULL
);
4686 add_fixed_insn (NOP_INSN
);
4687 mips_move_text_labels ();
4690 mips_no_prev_insn ();
4693 /* Start a (possibly nested) noreorder block. */
4696 start_noreorder (void)
4698 if (mips_opts
.noreorder
== 0)
4703 /* None of the instructions before the .set noreorder can be moved. */
4704 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4705 history
[i
].fixed_p
= 1;
4707 /* Insert any nops that might be needed between the .set noreorder
4708 block and the previous instructions. We will later remove any
4709 nops that turn out not to be needed. */
4710 nops
= nops_for_insn (0, history
, NULL
);
4713 if (mips_optimize
!= 0)
4715 /* Record the frag which holds the nop instructions, so
4716 that we can remove them if we don't need them. */
4717 frag_grow (nops
* NOP_INSN_SIZE
);
4718 prev_nop_frag
= frag_now
;
4719 prev_nop_frag_holds
= nops
;
4720 prev_nop_frag_required
= 0;
4721 prev_nop_frag_since
= 0;
4724 for (; nops
> 0; --nops
)
4725 add_fixed_insn (NOP_INSN
);
4727 /* Move on to a new frag, so that it is safe to simply
4728 decrease the size of prev_nop_frag. */
4729 frag_wane (frag_now
);
4731 mips_move_text_labels ();
4733 mips_mark_labels ();
4734 mips_clear_insn_labels ();
4736 mips_opts
.noreorder
++;
4737 mips_any_noreorder
= 1;
4740 /* End a nested noreorder block. */
4743 end_noreorder (void)
4745 mips_opts
.noreorder
--;
4746 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4748 /* Commit to inserting prev_nop_frag_required nops and go back to
4749 handling nop insertion the .set reorder way. */
4750 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4752 insert_into_history (prev_nop_frag_since
,
4753 prev_nop_frag_required
, NOP_INSN
);
4754 prev_nop_frag
= NULL
;
4758 /* Set up global variables for the start of a new macro. */
4763 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4764 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4765 sizeof (mips_macro_warning
.first_insn_sizes
));
4766 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4767 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4768 && delayed_branch_p (&history
[0]));
4769 switch (history
[0].insn_mo
->pinfo2
4770 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4772 case INSN2_BRANCH_DELAY_32BIT
:
4773 mips_macro_warning
.delay_slot_length
= 4;
4775 case INSN2_BRANCH_DELAY_16BIT
:
4776 mips_macro_warning
.delay_slot_length
= 2;
4779 mips_macro_warning
.delay_slot_length
= 0;
4782 mips_macro_warning
.first_frag
= NULL
;
4785 /* Given that a macro is longer than one instruction or of the wrong size,
4786 return the appropriate warning for it. Return null if no warning is
4787 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4788 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4789 and RELAX_NOMACRO. */
4792 macro_warning (relax_substateT subtype
)
4794 if (subtype
& RELAX_DELAY_SLOT
)
4795 return _("Macro instruction expanded into multiple instructions"
4796 " in a branch delay slot");
4797 else if (subtype
& RELAX_NOMACRO
)
4798 return _("Macro instruction expanded into multiple instructions");
4799 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4800 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4801 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4802 ? _("Macro instruction expanded into a wrong size instruction"
4803 " in a 16-bit branch delay slot")
4804 : _("Macro instruction expanded into a wrong size instruction"
4805 " in a 32-bit branch delay slot"));
4810 /* Finish up a macro. Emit warnings as appropriate. */
4815 /* Relaxation warning flags. */
4816 relax_substateT subtype
= 0;
4818 /* Check delay slot size requirements. */
4819 if (mips_macro_warning
.delay_slot_length
== 2)
4820 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4821 if (mips_macro_warning
.delay_slot_length
!= 0)
4823 if (mips_macro_warning
.delay_slot_length
4824 != mips_macro_warning
.first_insn_sizes
[0])
4825 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4826 if (mips_macro_warning
.delay_slot_length
4827 != mips_macro_warning
.first_insn_sizes
[1])
4828 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4831 /* Check instruction count requirements. */
4832 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4834 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4835 subtype
|= RELAX_SECOND_LONGER
;
4836 if (mips_opts
.warn_about_macros
)
4837 subtype
|= RELAX_NOMACRO
;
4838 if (mips_macro_warning
.delay_slot_p
)
4839 subtype
|= RELAX_DELAY_SLOT
;
4842 /* If both alternatives fail to fill a delay slot correctly,
4843 emit the warning now. */
4844 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4845 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4850 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4851 | RELAX_DELAY_SLOT_SIZE_FIRST
4852 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4853 msg
= macro_warning (s
);
4855 as_warn ("%s", msg
);
4859 /* If both implementations are longer than 1 instruction, then emit the
4861 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4866 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4867 msg
= macro_warning (s
);
4869 as_warn ("%s", msg
);
4873 /* If any flags still set, then one implementation might need a warning
4874 and the other either will need one of a different kind or none at all.
4875 Pass any remaining flags over to relaxation. */
4876 if (mips_macro_warning
.first_frag
!= NULL
)
4877 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4880 /* Instruction operand formats used in macros that vary between
4881 standard MIPS and microMIPS code. */
4883 static const char * const brk_fmt
[2] = { "c", "mF" };
4884 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4885 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4886 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4887 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4888 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4889 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4890 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4892 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4893 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4894 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4895 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4896 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4897 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4898 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4899 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4901 /* Read a macro's relocation codes from *ARGS and store them in *R.
4902 The first argument in *ARGS will be either the code for a single
4903 relocation or -1 followed by the three codes that make up a
4904 composite relocation. */
4907 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4911 next
= va_arg (*args
, int);
4913 r
[0] = (bfd_reloc_code_real_type
) next
;
4915 for (i
= 0; i
< 3; i
++)
4916 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4919 /* Build an instruction created by a macro expansion. This is passed
4920 a pointer to the count of instructions created so far, an
4921 expression, the name of the instruction to build, an operand format
4922 string, and corresponding arguments. */
4925 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4927 const struct mips_opcode
*mo
= NULL
;
4928 bfd_reloc_code_real_type r
[3];
4929 const struct mips_opcode
*amo
;
4930 struct hash_control
*hash
;
4931 struct mips_cl_insn insn
;
4934 va_start (args
, fmt
);
4936 if (mips_opts
.mips16
)
4938 mips16_macro_build (ep
, name
, fmt
, &args
);
4943 r
[0] = BFD_RELOC_UNUSED
;
4944 r
[1] = BFD_RELOC_UNUSED
;
4945 r
[2] = BFD_RELOC_UNUSED
;
4946 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
4947 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
4949 gas_assert (strcmp (name
, amo
->name
) == 0);
4953 /* Search until we get a match for NAME. It is assumed here that
4954 macros will never generate MDMX, MIPS-3D, or MT instructions.
4955 We try to match an instruction that fulfils the branch delay
4956 slot instruction length requirement (if any) of the previous
4957 instruction. While doing this we record the first instruction
4958 seen that matches all the other conditions and use it anyway
4959 if the requirement cannot be met; we will issue an appropriate
4960 warning later on. */
4961 if (strcmp (fmt
, amo
->args
) == 0
4962 && amo
->pinfo
!= INSN_MACRO
4963 && is_opcode_valid (amo
)
4964 && is_size_valid (amo
))
4966 if (is_delay_slot_valid (amo
))
4976 gas_assert (amo
->name
);
4978 while (strcmp (name
, amo
->name
) == 0);
4981 create_insn (&insn
, mo
);
4999 INSERT_OPERAND (mips_opts
.micromips
,
5000 EXTLSB
, insn
, va_arg (args
, int));
5005 /* Note that in the macro case, these arguments are already
5006 in MSB form. (When handling the instruction in the
5007 non-macro case, these arguments are sizes from which
5008 MSB values must be calculated.) */
5009 INSERT_OPERAND (mips_opts
.micromips
,
5010 INSMSB
, insn
, va_arg (args
, int));
5016 /* Note that in the macro case, these arguments are already
5017 in MSBD form. (When handling the instruction in the
5018 non-macro case, these arguments are sizes from which
5019 MSBD values must be calculated.) */
5020 INSERT_OPERAND (mips_opts
.micromips
,
5021 EXTMSBD
, insn
, va_arg (args
, int));
5025 gas_assert (!mips_opts
.micromips
);
5026 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
5035 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
5039 gas_assert (mips_opts
.micromips
);
5043 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
5047 gas_assert (!mips_opts
.micromips
);
5048 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
5052 gas_assert (!mips_opts
.micromips
);
5054 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
5058 if (mips_opts
.micromips
)
5059 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
5061 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
5065 gas_assert (!mips_opts
.micromips
);
5067 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
5071 gas_assert (!mips_opts
.micromips
);
5073 int tmp
= va_arg (args
, int);
5075 INSERT_OPERAND (0, RT
, insn
, tmp
);
5076 INSERT_OPERAND (0, RD
, insn
, tmp
);
5082 gas_assert (!mips_opts
.micromips
);
5083 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
5090 INSERT_OPERAND (mips_opts
.micromips
,
5091 SHAMT
, insn
, va_arg (args
, int));
5095 gas_assert (!mips_opts
.micromips
);
5096 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
5100 gas_assert (!mips_opts
.micromips
);
5101 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
5105 gas_assert (!mips_opts
.micromips
);
5106 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5110 gas_assert (!mips_opts
.micromips
);
5111 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5118 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5123 macro_read_relocs (&args
, r
);
5124 gas_assert (*r
== BFD_RELOC_GPREL16
5125 || *r
== BFD_RELOC_MIPS_HIGHER
5126 || *r
== BFD_RELOC_HI16_S
5127 || *r
== BFD_RELOC_LO16
5128 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5132 macro_read_relocs (&args
, r
);
5136 macro_read_relocs (&args
, r
);
5137 gas_assert (ep
!= NULL
5138 && (ep
->X_op
== O_constant
5139 || (ep
->X_op
== O_symbol
5140 && (*r
== BFD_RELOC_MIPS_HIGHEST
5141 || *r
== BFD_RELOC_HI16_S
5142 || *r
== BFD_RELOC_HI16
5143 || *r
== BFD_RELOC_GPREL16
5144 || *r
== BFD_RELOC_MIPS_GOT_HI16
5145 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5149 gas_assert (ep
!= NULL
);
5152 * This allows macro() to pass an immediate expression for
5153 * creating short branches without creating a symbol.
5155 * We don't allow branch relaxation for these branches, as
5156 * they should only appear in ".set nomacro" anyway.
5158 if (ep
->X_op
== O_constant
)
5160 /* For microMIPS we always use relocations for branches.
5161 So we should not resolve immediate values. */
5162 gas_assert (!mips_opts
.micromips
);
5164 if ((ep
->X_add_number
& 3) != 0)
5165 as_bad (_("branch to misaligned address (0x%lx)"),
5166 (unsigned long) ep
->X_add_number
);
5167 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5168 as_bad (_("branch address range overflow (0x%lx)"),
5169 (unsigned long) ep
->X_add_number
);
5170 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5174 *r
= BFD_RELOC_16_PCREL_S2
;
5178 gas_assert (ep
!= NULL
);
5179 *r
= BFD_RELOC_MIPS_JMP
;
5183 gas_assert (!mips_opts
.micromips
);
5184 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5188 INSERT_OPERAND (mips_opts
.micromips
,
5189 CACHE
, insn
, va_arg (args
, unsigned long));
5193 gas_assert (mips_opts
.micromips
);
5194 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5198 gas_assert (mips_opts
.micromips
);
5199 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5203 INSERT_OPERAND (mips_opts
.micromips
,
5204 3BITPOS
, insn
, va_arg (args
, unsigned int));
5208 INSERT_OPERAND (mips_opts
.micromips
,
5209 OFFSET12
, insn
, va_arg (args
, unsigned long));
5213 gas_assert (mips_opts
.micromips
);
5214 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5217 case 'm': /* Opcode extension character. */
5218 gas_assert (mips_opts
.micromips
);
5222 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5226 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5230 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5244 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5246 append_insn (&insn
, ep
, r
, TRUE
);
5250 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5253 struct mips_opcode
*mo
;
5254 struct mips_cl_insn insn
;
5255 bfd_reloc_code_real_type r
[3]
5256 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5258 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5260 gas_assert (strcmp (name
, mo
->name
) == 0);
5262 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5265 gas_assert (mo
->name
);
5266 gas_assert (strcmp (name
, mo
->name
) == 0);
5269 create_insn (&insn
, mo
);
5287 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5292 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5296 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5300 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5310 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5317 regno
= va_arg (*args
, int);
5318 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5319 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5342 gas_assert (ep
!= NULL
);
5344 if (ep
->X_op
!= O_constant
)
5345 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5346 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
5348 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
5350 *r
= BFD_RELOC_UNUSED
;
5356 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5363 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5365 append_insn (&insn
, ep
, r
, TRUE
);
5369 * Sign-extend 32-bit mode constants that have bit 31 set and all
5370 * higher bits unset.
5373 normalize_constant_expr (expressionS
*ex
)
5375 if (ex
->X_op
== O_constant
5376 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5377 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5382 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5383 * all higher bits unset.
5386 normalize_address_expr (expressionS
*ex
)
5388 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5389 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5390 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5391 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5396 * Generate a "jalr" instruction with a relocation hint to the called
5397 * function. This occurs in NewABI PIC code.
5400 macro_build_jalr (expressionS
*ep
, int cprestore
)
5402 static const bfd_reloc_code_real_type jalr_relocs
[2]
5403 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5404 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5408 if (MIPS_JALR_HINT_P (ep
))
5413 if (mips_opts
.micromips
)
5415 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5416 if (MIPS_JALR_HINT_P (ep
)
5417 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5418 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5420 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5423 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5424 if (MIPS_JALR_HINT_P (ep
))
5425 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5429 * Generate a "lui" instruction.
5432 macro_build_lui (expressionS
*ep
, int regnum
)
5434 gas_assert (! mips_opts
.mips16
);
5436 if (ep
->X_op
!= O_constant
)
5438 gas_assert (ep
->X_op
== O_symbol
);
5439 /* _gp_disp is a special case, used from s_cpload.
5440 __gnu_local_gp is used if mips_no_shared. */
5441 gas_assert (mips_pic
== NO_PIC
5443 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5444 || (! mips_in_shared
5445 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5446 "__gnu_local_gp") == 0));
5449 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5452 /* Generate a sequence of instructions to do a load or store from a constant
5453 offset off of a base register (breg) into/from a target register (treg),
5454 using AT if necessary. */
5456 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5457 int treg
, int breg
, int dbl
)
5459 gas_assert (ep
->X_op
== O_constant
);
5461 /* Sign-extending 32-bit constants makes their handling easier. */
5463 normalize_constant_expr (ep
);
5465 /* Right now, this routine can only handle signed 32-bit constants. */
5466 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5467 as_warn (_("operand overflow"));
5469 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5471 /* Signed 16-bit offset will fit in the op. Easy! */
5472 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5476 /* 32-bit offset, need multiple instructions and AT, like:
5477 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5478 addu $tempreg,$tempreg,$breg
5479 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5480 to handle the complete offset. */
5481 macro_build_lui (ep
, AT
);
5482 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5483 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5486 as_bad (_("Macro used $at after \".set noat\""));
5491 * Generates code to set the $at register to true (one)
5492 * if reg is less than the immediate expression.
5495 set_at (int reg
, int unsignedp
)
5497 if (imm_expr
.X_op
== O_constant
5498 && imm_expr
.X_add_number
>= -0x8000
5499 && imm_expr
.X_add_number
< 0x8000)
5500 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5501 AT
, reg
, BFD_RELOC_LO16
);
5504 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5505 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5509 /* Warn if an expression is not a constant. */
5512 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5514 if (ex
->X_op
== O_big
)
5515 as_bad (_("unsupported large constant"));
5516 else if (ex
->X_op
!= O_constant
)
5517 as_bad (_("Instruction %s requires absolute expression"),
5520 if (HAVE_32BIT_GPRS
)
5521 normalize_constant_expr (ex
);
5524 /* Count the leading zeroes by performing a binary chop. This is a
5525 bulky bit of source, but performance is a LOT better for the
5526 majority of values than a simple loop to count the bits:
5527 for (lcnt = 0; (lcnt < 32); lcnt++)
5528 if ((v) & (1 << (31 - lcnt)))
5530 However it is not code size friendly, and the gain will drop a bit
5531 on certain cached systems.
5533 #define COUNT_TOP_ZEROES(v) \
5534 (((v) & ~0xffff) == 0 \
5535 ? ((v) & ~0xff) == 0 \
5536 ? ((v) & ~0xf) == 0 \
5537 ? ((v) & ~0x3) == 0 \
5538 ? ((v) & ~0x1) == 0 \
5543 : ((v) & ~0x7) == 0 \
5546 : ((v) & ~0x3f) == 0 \
5547 ? ((v) & ~0x1f) == 0 \
5550 : ((v) & ~0x7f) == 0 \
5553 : ((v) & ~0xfff) == 0 \
5554 ? ((v) & ~0x3ff) == 0 \
5555 ? ((v) & ~0x1ff) == 0 \
5558 : ((v) & ~0x7ff) == 0 \
5561 : ((v) & ~0x3fff) == 0 \
5562 ? ((v) & ~0x1fff) == 0 \
5565 : ((v) & ~0x7fff) == 0 \
5568 : ((v) & ~0xffffff) == 0 \
5569 ? ((v) & ~0xfffff) == 0 \
5570 ? ((v) & ~0x3ffff) == 0 \
5571 ? ((v) & ~0x1ffff) == 0 \
5574 : ((v) & ~0x7ffff) == 0 \
5577 : ((v) & ~0x3fffff) == 0 \
5578 ? ((v) & ~0x1fffff) == 0 \
5581 : ((v) & ~0x7fffff) == 0 \
5584 : ((v) & ~0xfffffff) == 0 \
5585 ? ((v) & ~0x3ffffff) == 0 \
5586 ? ((v) & ~0x1ffffff) == 0 \
5589 : ((v) & ~0x7ffffff) == 0 \
5592 : ((v) & ~0x3fffffff) == 0 \
5593 ? ((v) & ~0x1fffffff) == 0 \
5596 : ((v) & ~0x7fffffff) == 0 \
5601 * This routine generates the least number of instructions necessary to load
5602 * an absolute expression value into a register.
5605 load_register (int reg
, expressionS
*ep
, int dbl
)
5608 expressionS hi32
, lo32
;
5610 if (ep
->X_op
!= O_big
)
5612 gas_assert (ep
->X_op
== O_constant
);
5614 /* Sign-extending 32-bit constants makes their handling easier. */
5616 normalize_constant_expr (ep
);
5618 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5620 /* We can handle 16 bit signed values with an addiu to
5621 $zero. No need to ever use daddiu here, since $zero and
5622 the result are always correct in 32 bit mode. */
5623 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5626 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5628 /* We can handle 16 bit unsigned values with an ori to
5630 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5633 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5635 /* 32 bit values require an lui. */
5636 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5637 if ((ep
->X_add_number
& 0xffff) != 0)
5638 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5643 /* The value is larger than 32 bits. */
5645 if (!dbl
|| HAVE_32BIT_GPRS
)
5649 sprintf_vma (value
, ep
->X_add_number
);
5650 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5651 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5655 if (ep
->X_op
!= O_big
)
5658 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5659 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5660 hi32
.X_add_number
&= 0xffffffff;
5662 lo32
.X_add_number
&= 0xffffffff;
5666 gas_assert (ep
->X_add_number
> 2);
5667 if (ep
->X_add_number
== 3)
5668 generic_bignum
[3] = 0;
5669 else if (ep
->X_add_number
> 4)
5670 as_bad (_("Number larger than 64 bits"));
5671 lo32
.X_op
= O_constant
;
5672 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5673 hi32
.X_op
= O_constant
;
5674 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5677 if (hi32
.X_add_number
== 0)
5682 unsigned long hi
, lo
;
5684 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5686 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5688 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5691 if (lo32
.X_add_number
& 0x80000000)
5693 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5694 if (lo32
.X_add_number
& 0xffff)
5695 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5700 /* Check for 16bit shifted constant. We know that hi32 is
5701 non-zero, so start the mask on the first bit of the hi32
5706 unsigned long himask
, lomask
;
5710 himask
= 0xffff >> (32 - shift
);
5711 lomask
= (0xffff << shift
) & 0xffffffff;
5715 himask
= 0xffff << (shift
- 32);
5718 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5719 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5723 tmp
.X_op
= O_constant
;
5725 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5726 | (lo32
.X_add_number
>> shift
));
5728 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5729 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5730 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5731 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5736 while (shift
<= (64 - 16));
5738 /* Find the bit number of the lowest one bit, and store the
5739 shifted value in hi/lo. */
5740 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5741 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5745 while ((lo
& 1) == 0)
5750 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5756 while ((hi
& 1) == 0)
5765 /* Optimize if the shifted value is a (power of 2) - 1. */
5766 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5767 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5769 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5774 /* This instruction will set the register to be all
5776 tmp
.X_op
= O_constant
;
5777 tmp
.X_add_number
= (offsetT
) -1;
5778 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5782 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5783 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5785 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5786 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5791 /* Sign extend hi32 before calling load_register, because we can
5792 generally get better code when we load a sign extended value. */
5793 if ((hi32
.X_add_number
& 0x80000000) != 0)
5794 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5795 load_register (reg
, &hi32
, 0);
5798 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5802 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5810 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5812 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5813 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5819 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5823 mid16
.X_add_number
>>= 16;
5824 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5825 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5828 if ((lo32
.X_add_number
& 0xffff) != 0)
5829 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5833 load_delay_nop (void)
5835 if (!gpr_interlocks
)
5836 macro_build (NULL
, "nop", "");
5839 /* Load an address into a register. */
5842 load_address (int reg
, expressionS
*ep
, int *used_at
)
5844 if (ep
->X_op
!= O_constant
5845 && ep
->X_op
!= O_symbol
)
5847 as_bad (_("expression too complex"));
5848 ep
->X_op
= O_constant
;
5851 if (ep
->X_op
== O_constant
)
5853 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5857 if (mips_pic
== NO_PIC
)
5859 /* If this is a reference to a GP relative symbol, we want
5860 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5862 lui $reg,<sym> (BFD_RELOC_HI16_S)
5863 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5864 If we have an addend, we always use the latter form.
5866 With 64bit address space and a usable $at we want
5867 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5868 lui $at,<sym> (BFD_RELOC_HI16_S)
5869 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5870 daddiu $at,<sym> (BFD_RELOC_LO16)
5874 If $at is already in use, we use a path which is suboptimal
5875 on superscalar processors.
5876 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5877 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5879 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5881 daddiu $reg,<sym> (BFD_RELOC_LO16)
5883 For GP relative symbols in 64bit address space we can use
5884 the same sequence as in 32bit address space. */
5885 if (HAVE_64BIT_SYMBOLS
)
5887 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5888 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5890 relax_start (ep
->X_add_symbol
);
5891 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5892 mips_gp_register
, BFD_RELOC_GPREL16
);
5896 if (*used_at
== 0 && mips_opts
.at
)
5898 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5899 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5900 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5901 BFD_RELOC_MIPS_HIGHER
);
5902 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5903 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5904 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5909 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5910 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5911 BFD_RELOC_MIPS_HIGHER
);
5912 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5913 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5914 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5915 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5918 if (mips_relax
.sequence
)
5923 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5924 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5926 relax_start (ep
->X_add_symbol
);
5927 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5928 mips_gp_register
, BFD_RELOC_GPREL16
);
5931 macro_build_lui (ep
, reg
);
5932 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
5933 reg
, reg
, BFD_RELOC_LO16
);
5934 if (mips_relax
.sequence
)
5938 else if (!mips_big_got
)
5942 /* If this is a reference to an external symbol, we want
5943 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5945 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5947 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5948 If there is a constant, it must be added in after.
5950 If we have NewABI, we want
5951 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5952 unless we're referencing a global symbol with a non-zero
5953 offset, in which case cst must be added separately. */
5956 if (ep
->X_add_number
)
5958 ex
.X_add_number
= ep
->X_add_number
;
5959 ep
->X_add_number
= 0;
5960 relax_start (ep
->X_add_symbol
);
5961 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5962 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5963 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5964 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5965 ex
.X_op
= O_constant
;
5966 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5967 reg
, reg
, BFD_RELOC_LO16
);
5968 ep
->X_add_number
= ex
.X_add_number
;
5971 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5972 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5973 if (mips_relax
.sequence
)
5978 ex
.X_add_number
= ep
->X_add_number
;
5979 ep
->X_add_number
= 0;
5980 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5981 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5983 relax_start (ep
->X_add_symbol
);
5985 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5989 if (ex
.X_add_number
!= 0)
5991 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5992 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5993 ex
.X_op
= O_constant
;
5994 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5995 reg
, reg
, BFD_RELOC_LO16
);
5999 else if (mips_big_got
)
6003 /* This is the large GOT case. If this is a reference to an
6004 external symbol, we want
6005 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6007 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6009 Otherwise, for a reference to a local symbol in old ABI, we want
6010 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6012 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6013 If there is a constant, it must be added in after.
6015 In the NewABI, for local symbols, with or without offsets, we want:
6016 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6017 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6021 ex
.X_add_number
= ep
->X_add_number
;
6022 ep
->X_add_number
= 0;
6023 relax_start (ep
->X_add_symbol
);
6024 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6025 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6026 reg
, reg
, mips_gp_register
);
6027 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6028 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6029 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6030 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6031 else if (ex
.X_add_number
)
6033 ex
.X_op
= O_constant
;
6034 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6038 ep
->X_add_number
= ex
.X_add_number
;
6040 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6041 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6042 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6043 BFD_RELOC_MIPS_GOT_OFST
);
6048 ex
.X_add_number
= ep
->X_add_number
;
6049 ep
->X_add_number
= 0;
6050 relax_start (ep
->X_add_symbol
);
6051 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6052 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6053 reg
, reg
, mips_gp_register
);
6054 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6055 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6057 if (reg_needs_delay (mips_gp_register
))
6059 /* We need a nop before loading from $gp. This special
6060 check is required because the lui which starts the main
6061 instruction stream does not refer to $gp, and so will not
6062 insert the nop which may be required. */
6063 macro_build (NULL
, "nop", "");
6065 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6066 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6068 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6072 if (ex
.X_add_number
!= 0)
6074 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6075 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6076 ex
.X_op
= O_constant
;
6077 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6085 if (!mips_opts
.at
&& *used_at
== 1)
6086 as_bad (_("Macro used $at after \".set noat\""));
6089 /* Move the contents of register SOURCE into register DEST. */
6092 move_register (int dest
, int source
)
6094 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6095 instruction specifically requires a 32-bit one. */
6096 if (mips_opts
.micromips
6097 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6098 macro_build (NULL
, "move", "mp,mj", dest
, source
);
6100 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
6104 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6105 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6106 The two alternatives are:
6108 Global symbol Local sybmol
6109 ------------- ------------
6110 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6112 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6114 load_got_offset emits the first instruction and add_got_offset
6115 emits the second for a 16-bit offset or add_got_offset_hilo emits
6116 a sequence to add a 32-bit offset using a scratch register. */
6119 load_got_offset (int dest
, expressionS
*local
)
6124 global
.X_add_number
= 0;
6126 relax_start (local
->X_add_symbol
);
6127 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6128 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6130 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6131 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6136 add_got_offset (int dest
, expressionS
*local
)
6140 global
.X_op
= O_constant
;
6141 global
.X_op_symbol
= NULL
;
6142 global
.X_add_symbol
= NULL
;
6143 global
.X_add_number
= local
->X_add_number
;
6145 relax_start (local
->X_add_symbol
);
6146 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6147 dest
, dest
, BFD_RELOC_LO16
);
6149 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6154 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6157 int hold_mips_optimize
;
6159 global
.X_op
= O_constant
;
6160 global
.X_op_symbol
= NULL
;
6161 global
.X_add_symbol
= NULL
;
6162 global
.X_add_number
= local
->X_add_number
;
6164 relax_start (local
->X_add_symbol
);
6165 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6167 /* Set mips_optimize around the lui instruction to avoid
6168 inserting an unnecessary nop after the lw. */
6169 hold_mips_optimize
= mips_optimize
;
6171 macro_build_lui (&global
, tmp
);
6172 mips_optimize
= hold_mips_optimize
;
6173 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6176 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6179 /* Emit a sequence of instructions to emulate a branch likely operation.
6180 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6181 is its complementing branch with the original condition negated.
6182 CALL is set if the original branch specified the link operation.
6183 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6185 Code like this is produced in the noreorder mode:
6190 delay slot (executed only if branch taken)
6198 delay slot (executed only if branch taken)
6201 In the reorder mode the delay slot would be filled with a nop anyway,
6202 so code produced is simply:
6207 This function is used when producing code for the microMIPS ASE that
6208 does not implement branch likely instructions in hardware. */
6211 macro_build_branch_likely (const char *br
, const char *brneg
,
6212 int call
, expressionS
*ep
, const char *fmt
,
6213 unsigned int sreg
, unsigned int treg
)
6215 int noreorder
= mips_opts
.noreorder
;
6218 gas_assert (mips_opts
.micromips
);
6222 micromips_label_expr (&expr1
);
6223 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6224 macro_build (NULL
, "nop", "");
6225 macro_build (ep
, call
? "bal" : "b", "p");
6227 /* Set to true so that append_insn adds a label. */
6228 emit_branch_likely_macro
= TRUE
;
6232 macro_build (ep
, br
, fmt
, sreg
, treg
);
6233 macro_build (NULL
, "nop", "");
6238 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6239 the condition code tested. EP specifies the branch target. */
6242 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6269 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6272 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6273 the register tested. EP specifies the branch target. */
6276 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6278 const char *brneg
= NULL
;
6288 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6292 gas_assert (mips_opts
.micromips
);
6301 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6308 br
= mips_opts
.micromips
? "blez" : "blezl";
6315 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6319 gas_assert (mips_opts
.micromips
);
6327 if (mips_opts
.micromips
&& brneg
)
6328 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6330 macro_build (ep
, br
, "s,p", sreg
);
6333 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6334 TREG as the registers tested. EP specifies the branch target. */
6337 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6338 unsigned int sreg
, unsigned int treg
)
6340 const char *brneg
= NULL
;
6352 br
= mips_opts
.micromips
? "beq" : "beql";
6361 br
= mips_opts
.micromips
? "bne" : "bnel";
6367 if (mips_opts
.micromips
&& brneg
)
6368 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6370 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6375 * This routine implements the seemingly endless macro or synthesized
6376 * instructions and addressing modes in the mips assembly language. Many
6377 * of these macros are simple and are similar to each other. These could
6378 * probably be handled by some kind of table or grammar approach instead of
6379 * this verbose method. Others are not simple macros but are more like
6380 * optimizing code generation.
6381 * One interesting optimization is when several store macros appear
6382 * consecutively that would load AT with the upper half of the same address.
6383 * The ensuing load upper instructions are ommited. This implies some kind
6384 * of global optimization. We currently only optimize within a single macro.
6385 * For many of the load and store macros if the address is specified as a
6386 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6387 * first load register 'at' with zero and use it as the base register. The
6388 * mips assembler simply uses register $zero. Just one tiny optimization
6392 macro (struct mips_cl_insn
*ip
)
6394 unsigned int treg
, sreg
, dreg
, breg
;
6395 unsigned int tempreg
;
6398 expressionS label_expr
;
6417 bfd_reloc_code_real_type r
;
6418 int hold_mips_optimize
;
6420 gas_assert (! mips_opts
.mips16
);
6422 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6423 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6424 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6425 mask
= ip
->insn_mo
->mask
;
6427 label_expr
.X_op
= O_constant
;
6428 label_expr
.X_op_symbol
= NULL
;
6429 label_expr
.X_add_symbol
= NULL
;
6430 label_expr
.X_add_number
= 0;
6432 expr1
.X_op
= O_constant
;
6433 expr1
.X_op_symbol
= NULL
;
6434 expr1
.X_add_symbol
= NULL
;
6435 expr1
.X_add_number
= 1;
6450 if (mips_opts
.micromips
)
6451 micromips_label_expr (&label_expr
);
6453 label_expr
.X_add_number
= 8;
6454 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6456 macro_build (NULL
, "nop", "");
6458 move_register (dreg
, sreg
);
6459 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6460 if (mips_opts
.micromips
)
6461 micromips_add_label ();
6478 if (!mips_opts
.micromips
)
6480 if (imm_expr
.X_op
== O_constant
6481 && imm_expr
.X_add_number
>= -0x200
6482 && imm_expr
.X_add_number
< 0x200)
6484 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6493 if (imm_expr
.X_op
== O_constant
6494 && imm_expr
.X_add_number
>= -0x8000
6495 && imm_expr
.X_add_number
< 0x8000)
6497 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6502 load_register (AT
, &imm_expr
, dbl
);
6503 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6522 if (imm_expr
.X_op
== O_constant
6523 && imm_expr
.X_add_number
>= 0
6524 && imm_expr
.X_add_number
< 0x10000)
6526 if (mask
!= M_NOR_I
)
6527 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6530 macro_build (&imm_expr
, "ori", "t,r,i",
6531 treg
, sreg
, BFD_RELOC_LO16
);
6532 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6538 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6539 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6543 switch (imm_expr
.X_add_number
)
6546 macro_build (NULL
, "nop", "");
6549 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6553 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6554 (int) imm_expr
.X_add_number
);
6557 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6558 (unsigned long) imm_expr
.X_add_number
);
6567 gas_assert (mips_opts
.micromips
);
6568 macro_build_branch_ccl (mask
, &offset_expr
,
6569 EXTRACT_OPERAND (1, BCC
, *ip
));
6576 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6582 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6587 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6594 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6596 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6600 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6601 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6602 &offset_expr
, AT
, ZERO
);
6612 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6618 /* Check for > max integer. */
6619 maxnum
= 0x7fffffff;
6620 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6627 if (imm_expr
.X_op
== O_constant
6628 && imm_expr
.X_add_number
>= maxnum
6629 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6632 /* Result is always false. */
6634 macro_build (NULL
, "nop", "");
6636 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6639 if (imm_expr
.X_op
!= O_constant
)
6640 as_bad (_("Unsupported large constant"));
6641 ++imm_expr
.X_add_number
;
6645 if (mask
== M_BGEL_I
)
6647 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6649 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6650 &offset_expr
, sreg
);
6653 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6655 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6656 &offset_expr
, sreg
);
6659 maxnum
= 0x7fffffff;
6660 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6667 maxnum
= - maxnum
- 1;
6668 if (imm_expr
.X_op
== O_constant
6669 && imm_expr
.X_add_number
<= maxnum
6670 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6673 /* result is always true */
6674 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6675 macro_build (&offset_expr
, "b", "p");
6680 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6681 &offset_expr
, AT
, ZERO
);
6690 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6691 &offset_expr
, ZERO
, treg
);
6695 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6696 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6697 &offset_expr
, AT
, ZERO
);
6706 && imm_expr
.X_op
== O_constant
6707 && imm_expr
.X_add_number
== -1))
6709 if (imm_expr
.X_op
!= O_constant
)
6710 as_bad (_("Unsupported large constant"));
6711 ++imm_expr
.X_add_number
;
6715 if (mask
== M_BGEUL_I
)
6717 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6719 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6720 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6721 &offset_expr
, sreg
, ZERO
);
6726 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6727 &offset_expr
, AT
, ZERO
);
6735 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6737 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6741 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6742 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6743 &offset_expr
, AT
, ZERO
);
6751 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6752 &offset_expr
, sreg
, ZERO
);
6758 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6759 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6760 &offset_expr
, AT
, ZERO
);
6768 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6770 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6774 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6775 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6776 &offset_expr
, AT
, ZERO
);
6783 maxnum
= 0x7fffffff;
6784 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6791 if (imm_expr
.X_op
== O_constant
6792 && imm_expr
.X_add_number
>= maxnum
6793 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6795 if (imm_expr
.X_op
!= O_constant
)
6796 as_bad (_("Unsupported large constant"));
6797 ++imm_expr
.X_add_number
;
6801 if (mask
== M_BLTL_I
)
6803 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6804 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6805 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6806 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6811 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6812 &offset_expr
, AT
, ZERO
);
6820 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6821 &offset_expr
, sreg
, ZERO
);
6827 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6828 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6829 &offset_expr
, AT
, ZERO
);
6838 && imm_expr
.X_op
== O_constant
6839 && imm_expr
.X_add_number
== -1))
6841 if (imm_expr
.X_op
!= O_constant
)
6842 as_bad (_("Unsupported large constant"));
6843 ++imm_expr
.X_add_number
;
6847 if (mask
== M_BLTUL_I
)
6849 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6851 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6852 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6853 &offset_expr
, sreg
, ZERO
);
6858 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6859 &offset_expr
, AT
, ZERO
);
6867 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6869 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6873 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6874 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6875 &offset_expr
, AT
, ZERO
);
6885 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6886 &offset_expr
, ZERO
, treg
);
6890 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6891 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6892 &offset_expr
, AT
, ZERO
);
6898 /* Use unsigned arithmetic. */
6902 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6904 as_bad (_("Unsupported large constant"));
6909 pos
= imm_expr
.X_add_number
;
6910 size
= imm2_expr
.X_add_number
;
6915 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6918 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6920 as_bad (_("Improper extract size (%lu, position %lu)"),
6921 (unsigned long) size
, (unsigned long) pos
);
6925 if (size
<= 32 && pos
< 32)
6930 else if (size
<= 32)
6940 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6947 /* Use unsigned arithmetic. */
6951 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6953 as_bad (_("Unsupported large constant"));
6958 pos
= imm_expr
.X_add_number
;
6959 size
= imm2_expr
.X_add_number
;
6964 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6967 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6969 as_bad (_("Improper insert size (%lu, position %lu)"),
6970 (unsigned long) size
, (unsigned long) pos
);
6974 if (pos
< 32 && (pos
+ size
- 1) < 32)
6989 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6990 (int) (pos
+ size
- 1));
7006 as_warn (_("Divide by zero."));
7008 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7010 macro_build (NULL
, "break", BRK_FMT
, 7);
7017 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7018 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7022 if (mips_opts
.micromips
)
7023 micromips_label_expr (&label_expr
);
7025 label_expr
.X_add_number
= 8;
7026 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7027 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7028 macro_build (NULL
, "break", BRK_FMT
, 7);
7029 if (mips_opts
.micromips
)
7030 micromips_add_label ();
7032 expr1
.X_add_number
= -1;
7034 load_register (AT
, &expr1
, dbl
);
7035 if (mips_opts
.micromips
)
7036 micromips_label_expr (&label_expr
);
7038 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
7039 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
7042 expr1
.X_add_number
= 1;
7043 load_register (AT
, &expr1
, dbl
);
7044 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
7048 expr1
.X_add_number
= 0x80000000;
7049 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
7053 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
7054 /* We want to close the noreorder block as soon as possible, so
7055 that later insns are available for delay slot filling. */
7060 if (mips_opts
.micromips
)
7061 micromips_label_expr (&label_expr
);
7063 label_expr
.X_add_number
= 8;
7064 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
7065 macro_build (NULL
, "nop", "");
7067 /* We want to close the noreorder block as soon as possible, so
7068 that later insns are available for delay slot filling. */
7071 macro_build (NULL
, "break", BRK_FMT
, 6);
7073 if (mips_opts
.micromips
)
7074 micromips_add_label ();
7075 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7114 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7116 as_warn (_("Divide by zero."));
7118 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7120 macro_build (NULL
, "break", BRK_FMT
, 7);
7123 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7125 if (strcmp (s2
, "mflo") == 0)
7126 move_register (dreg
, sreg
);
7128 move_register (dreg
, ZERO
);
7131 if (imm_expr
.X_op
== O_constant
7132 && imm_expr
.X_add_number
== -1
7133 && s
[strlen (s
) - 1] != 'u')
7135 if (strcmp (s2
, "mflo") == 0)
7137 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7140 move_register (dreg
, ZERO
);
7145 load_register (AT
, &imm_expr
, dbl
);
7146 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7147 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7169 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7170 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7171 /* We want to close the noreorder block as soon as possible, so
7172 that later insns are available for delay slot filling. */
7177 if (mips_opts
.micromips
)
7178 micromips_label_expr (&label_expr
);
7180 label_expr
.X_add_number
= 8;
7181 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7182 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7184 /* We want to close the noreorder block as soon as possible, so
7185 that later insns are available for delay slot filling. */
7187 macro_build (NULL
, "break", BRK_FMT
, 7);
7188 if (mips_opts
.micromips
)
7189 micromips_add_label ();
7191 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7203 /* Load the address of a symbol into a register. If breg is not
7204 zero, we then add a base register to it. */
7206 if (dbl
&& HAVE_32BIT_GPRS
)
7207 as_warn (_("dla used to load 32-bit register"));
7209 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7210 as_warn (_("la used to load 64-bit address"));
7212 if (offset_expr
.X_op
== O_constant
7213 && offset_expr
.X_add_number
>= -0x8000
7214 && offset_expr
.X_add_number
< 0x8000)
7216 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7217 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7221 if (mips_opts
.at
&& (treg
== breg
))
7231 if (offset_expr
.X_op
!= O_symbol
7232 && offset_expr
.X_op
!= O_constant
)
7234 as_bad (_("Expression too complex"));
7235 offset_expr
.X_op
= O_constant
;
7238 if (offset_expr
.X_op
== O_constant
)
7239 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7240 else if (mips_pic
== NO_PIC
)
7242 /* If this is a reference to a GP relative symbol, we want
7243 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7245 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7246 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7247 If we have a constant, we need two instructions anyhow,
7248 so we may as well always use the latter form.
7250 With 64bit address space and a usable $at we want
7251 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7252 lui $at,<sym> (BFD_RELOC_HI16_S)
7253 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7254 daddiu $at,<sym> (BFD_RELOC_LO16)
7256 daddu $tempreg,$tempreg,$at
7258 If $at is already in use, we use a path which is suboptimal
7259 on superscalar processors.
7260 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7261 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7263 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7265 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7267 For GP relative symbols in 64bit address space we can use
7268 the same sequence as in 32bit address space. */
7269 if (HAVE_64BIT_SYMBOLS
)
7271 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7272 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7274 relax_start (offset_expr
.X_add_symbol
);
7275 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7276 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7280 if (used_at
== 0 && mips_opts
.at
)
7282 macro_build (&offset_expr
, "lui", LUI_FMT
,
7283 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7284 macro_build (&offset_expr
, "lui", LUI_FMT
,
7285 AT
, BFD_RELOC_HI16_S
);
7286 macro_build (&offset_expr
, "daddiu", "t,r,j",
7287 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7288 macro_build (&offset_expr
, "daddiu", "t,r,j",
7289 AT
, AT
, BFD_RELOC_LO16
);
7290 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7291 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7296 macro_build (&offset_expr
, "lui", LUI_FMT
,
7297 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7298 macro_build (&offset_expr
, "daddiu", "t,r,j",
7299 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7300 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7301 macro_build (&offset_expr
, "daddiu", "t,r,j",
7302 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7303 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7304 macro_build (&offset_expr
, "daddiu", "t,r,j",
7305 tempreg
, tempreg
, BFD_RELOC_LO16
);
7308 if (mips_relax
.sequence
)
7313 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7314 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7316 relax_start (offset_expr
.X_add_symbol
);
7317 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7318 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7321 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7322 as_bad (_("Offset too large"));
7323 macro_build_lui (&offset_expr
, tempreg
);
7324 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7325 tempreg
, tempreg
, BFD_RELOC_LO16
);
7326 if (mips_relax
.sequence
)
7330 else if (!mips_big_got
&& !HAVE_NEWABI
)
7332 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7334 /* If this is a reference to an external symbol, and there
7335 is no constant, we want
7336 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7337 or for lca or if tempreg is PIC_CALL_REG
7338 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7339 For a local symbol, we want
7340 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7342 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7344 If we have a small constant, and this is a reference to
7345 an external symbol, we want
7346 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7348 addiu $tempreg,$tempreg,<constant>
7349 For a local symbol, we want the same instruction
7350 sequence, but we output a BFD_RELOC_LO16 reloc on the
7353 If we have a large constant, and this is a reference to
7354 an external symbol, we want
7355 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7356 lui $at,<hiconstant>
7357 addiu $at,$at,<loconstant>
7358 addu $tempreg,$tempreg,$at
7359 For a local symbol, we want the same instruction
7360 sequence, but we output a BFD_RELOC_LO16 reloc on the
7364 if (offset_expr
.X_add_number
== 0)
7366 if (mips_pic
== SVR4_PIC
7368 && (call
|| tempreg
== PIC_CALL_REG
))
7369 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7371 relax_start (offset_expr
.X_add_symbol
);
7372 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7373 lw_reloc_type
, mips_gp_register
);
7376 /* We're going to put in an addu instruction using
7377 tempreg, so we may as well insert the nop right
7382 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7383 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7385 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7386 tempreg
, tempreg
, BFD_RELOC_LO16
);
7388 /* FIXME: If breg == 0, and the next instruction uses
7389 $tempreg, then if this variant case is used an extra
7390 nop will be generated. */
7392 else if (offset_expr
.X_add_number
>= -0x8000
7393 && offset_expr
.X_add_number
< 0x8000)
7395 load_got_offset (tempreg
, &offset_expr
);
7397 add_got_offset (tempreg
, &offset_expr
);
7401 expr1
.X_add_number
= offset_expr
.X_add_number
;
7402 offset_expr
.X_add_number
=
7403 SEXT_16BIT (offset_expr
.X_add_number
);
7404 load_got_offset (tempreg
, &offset_expr
);
7405 offset_expr
.X_add_number
= expr1
.X_add_number
;
7406 /* If we are going to add in a base register, and the
7407 target register and the base register are the same,
7408 then we are using AT as a temporary register. Since
7409 we want to load the constant into AT, we add our
7410 current AT (from the global offset table) and the
7411 register into the register now, and pretend we were
7412 not using a base register. */
7416 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7421 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7425 else if (!mips_big_got
&& HAVE_NEWABI
)
7427 int add_breg_early
= 0;
7429 /* If this is a reference to an external, and there is no
7430 constant, or local symbol (*), with or without a
7432 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7433 or for lca or if tempreg is PIC_CALL_REG
7434 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7436 If we have a small constant, and this is a reference to
7437 an external symbol, we want
7438 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7439 addiu $tempreg,$tempreg,<constant>
7441 If we have a large constant, and this is a reference to
7442 an external symbol, we want
7443 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7444 lui $at,<hiconstant>
7445 addiu $at,$at,<loconstant>
7446 addu $tempreg,$tempreg,$at
7448 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7449 local symbols, even though it introduces an additional
7452 if (offset_expr
.X_add_number
)
7454 expr1
.X_add_number
= offset_expr
.X_add_number
;
7455 offset_expr
.X_add_number
= 0;
7457 relax_start (offset_expr
.X_add_symbol
);
7458 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7459 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7461 if (expr1
.X_add_number
>= -0x8000
7462 && expr1
.X_add_number
< 0x8000)
7464 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7465 tempreg
, tempreg
, BFD_RELOC_LO16
);
7467 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7469 /* If we are going to add in a base register, and the
7470 target register and the base register are the same,
7471 then we are using AT as a temporary register. Since
7472 we want to load the constant into AT, we add our
7473 current AT (from the global offset table) and the
7474 register into the register now, and pretend we were
7475 not using a base register. */
7480 gas_assert (tempreg
== AT
);
7481 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7487 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7488 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7494 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7497 offset_expr
.X_add_number
= expr1
.X_add_number
;
7499 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7500 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7503 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7504 treg
, tempreg
, breg
);
7510 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7512 relax_start (offset_expr
.X_add_symbol
);
7513 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7514 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7516 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7517 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7522 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7523 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7526 else if (mips_big_got
&& !HAVE_NEWABI
)
7529 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7530 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7531 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7533 /* This is the large GOT case. If this is a reference to an
7534 external symbol, and there is no constant, we want
7535 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7536 addu $tempreg,$tempreg,$gp
7537 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7538 or for lca or if tempreg is PIC_CALL_REG
7539 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7540 addu $tempreg,$tempreg,$gp
7541 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7542 For a local symbol, we want
7543 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7545 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7547 If we have a small constant, and this is a reference to
7548 an external symbol, we want
7549 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7550 addu $tempreg,$tempreg,$gp
7551 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7553 addiu $tempreg,$tempreg,<constant>
7554 For a local symbol, we want
7555 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7557 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7559 If we have a large constant, and this is a reference to
7560 an external symbol, we want
7561 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7562 addu $tempreg,$tempreg,$gp
7563 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7564 lui $at,<hiconstant>
7565 addiu $at,$at,<loconstant>
7566 addu $tempreg,$tempreg,$at
7567 For a local symbol, we want
7568 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7569 lui $at,<hiconstant>
7570 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7571 addu $tempreg,$tempreg,$at
7574 expr1
.X_add_number
= offset_expr
.X_add_number
;
7575 offset_expr
.X_add_number
= 0;
7576 relax_start (offset_expr
.X_add_symbol
);
7577 gpdelay
= reg_needs_delay (mips_gp_register
);
7578 if (expr1
.X_add_number
== 0 && breg
== 0
7579 && (call
|| tempreg
== PIC_CALL_REG
))
7581 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7582 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7584 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7585 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7586 tempreg
, tempreg
, mips_gp_register
);
7587 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7588 tempreg
, lw_reloc_type
, tempreg
);
7589 if (expr1
.X_add_number
== 0)
7593 /* We're going to put in an addu instruction using
7594 tempreg, so we may as well insert the nop right
7599 else if (expr1
.X_add_number
>= -0x8000
7600 && expr1
.X_add_number
< 0x8000)
7603 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7604 tempreg
, tempreg
, BFD_RELOC_LO16
);
7608 /* If we are going to add in a base register, and the
7609 target register and the base register are the same,
7610 then we are using AT as a temporary register. Since
7611 we want to load the constant into AT, we add our
7612 current AT (from the global offset table) and the
7613 register into the register now, and pretend we were
7614 not using a base register. */
7619 gas_assert (tempreg
== AT
);
7621 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7626 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7627 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7631 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
7636 /* This is needed because this instruction uses $gp, but
7637 the first instruction on the main stream does not. */
7638 macro_build (NULL
, "nop", "");
7641 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7642 local_reloc_type
, mips_gp_register
);
7643 if (expr1
.X_add_number
>= -0x8000
7644 && expr1
.X_add_number
< 0x8000)
7647 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7648 tempreg
, tempreg
, BFD_RELOC_LO16
);
7649 /* FIXME: If add_number is 0, and there was no base
7650 register, the external symbol case ended with a load,
7651 so if the symbol turns out to not be external, and
7652 the next instruction uses tempreg, an unnecessary nop
7653 will be inserted. */
7659 /* We must add in the base register now, as in the
7660 external symbol case. */
7661 gas_assert (tempreg
== AT
);
7663 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7666 /* We set breg to 0 because we have arranged to add
7667 it in in both cases. */
7671 macro_build_lui (&expr1
, AT
);
7672 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7673 AT
, AT
, BFD_RELOC_LO16
);
7674 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7675 tempreg
, tempreg
, AT
);
7680 else if (mips_big_got
&& HAVE_NEWABI
)
7682 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7683 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7684 int add_breg_early
= 0;
7686 /* This is the large GOT case. If this is a reference to an
7687 external symbol, and there is no constant, we want
7688 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7689 add $tempreg,$tempreg,$gp
7690 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7691 or for lca or if tempreg is PIC_CALL_REG
7692 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7693 add $tempreg,$tempreg,$gp
7694 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7696 If we have a small constant, and this is a reference to
7697 an external symbol, we want
7698 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7699 add $tempreg,$tempreg,$gp
7700 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7701 addi $tempreg,$tempreg,<constant>
7703 If we have a large constant, and this is a reference to
7704 an external symbol, we want
7705 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7706 addu $tempreg,$tempreg,$gp
7707 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7708 lui $at,<hiconstant>
7709 addi $at,$at,<loconstant>
7710 add $tempreg,$tempreg,$at
7712 If we have NewABI, and we know it's a local symbol, we want
7713 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7714 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7715 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7717 relax_start (offset_expr
.X_add_symbol
);
7719 expr1
.X_add_number
= offset_expr
.X_add_number
;
7720 offset_expr
.X_add_number
= 0;
7722 if (expr1
.X_add_number
== 0 && breg
== 0
7723 && (call
|| tempreg
== PIC_CALL_REG
))
7725 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7726 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7728 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7729 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7730 tempreg
, tempreg
, mips_gp_register
);
7731 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7732 tempreg
, lw_reloc_type
, tempreg
);
7734 if (expr1
.X_add_number
== 0)
7736 else if (expr1
.X_add_number
>= -0x8000
7737 && expr1
.X_add_number
< 0x8000)
7739 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7740 tempreg
, tempreg
, BFD_RELOC_LO16
);
7742 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7744 /* If we are going to add in a base register, and the
7745 target register and the base register are the same,
7746 then we are using AT as a temporary register. Since
7747 we want to load the constant into AT, we add our
7748 current AT (from the global offset table) and the
7749 register into the register now, and pretend we were
7750 not using a base register. */
7755 gas_assert (tempreg
== AT
);
7756 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7762 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7763 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7768 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7771 offset_expr
.X_add_number
= expr1
.X_add_number
;
7772 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7773 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7774 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7775 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7778 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7779 treg
, tempreg
, breg
);
7789 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7793 gas_assert (!mips_opts
.micromips
);
7795 unsigned long temp
= (treg
<< 16) | (0x01);
7796 macro_build (NULL
, "c2", "C", temp
);
7801 gas_assert (!mips_opts
.micromips
);
7803 unsigned long temp
= (0x02);
7804 macro_build (NULL
, "c2", "C", temp
);
7809 gas_assert (!mips_opts
.micromips
);
7811 unsigned long temp
= (treg
<< 16) | (0x02);
7812 macro_build (NULL
, "c2", "C", temp
);
7817 gas_assert (!mips_opts
.micromips
);
7818 macro_build (NULL
, "c2", "C", 3);
7822 gas_assert (!mips_opts
.micromips
);
7824 unsigned long temp
= (treg
<< 16) | 0x03;
7825 macro_build (NULL
, "c2", "C", temp
);
7830 /* The j instruction may not be used in PIC code, since it
7831 requires an absolute address. We convert it to a b
7833 if (mips_pic
== NO_PIC
)
7834 macro_build (&offset_expr
, "j", "a");
7836 macro_build (&offset_expr
, "b", "p");
7839 /* The jal instructions must be handled as macros because when
7840 generating PIC code they expand to multi-instruction
7841 sequences. Normally they are simple instructions. */
7846 gas_assert (mips_opts
.micromips
);
7854 if (mips_pic
== NO_PIC
)
7856 s
= jals
? "jalrs" : "jalr";
7857 if (mips_opts
.micromips
7859 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7860 macro_build (NULL
, s
, "mj", sreg
);
7862 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7866 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7867 && mips_cprestore_offset
>= 0);
7869 if (sreg
!= PIC_CALL_REG
)
7870 as_warn (_("MIPS PIC call to register other than $25"));
7872 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7873 ? "jalrs" : "jalr");
7874 if (mips_opts
.micromips
7876 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7877 macro_build (NULL
, s
, "mj", sreg
);
7879 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7880 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7882 if (mips_cprestore_offset
< 0)
7883 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7886 if (!mips_frame_reg_valid
)
7888 as_warn (_("No .frame pseudo-op used in PIC code"));
7889 /* Quiet this warning. */
7890 mips_frame_reg_valid
= 1;
7892 if (!mips_cprestore_valid
)
7894 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7895 /* Quiet this warning. */
7896 mips_cprestore_valid
= 1;
7898 if (mips_opts
.noreorder
)
7899 macro_build (NULL
, "nop", "");
7900 expr1
.X_add_number
= mips_cprestore_offset
;
7901 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7904 HAVE_64BIT_ADDRESSES
);
7912 gas_assert (mips_opts
.micromips
);
7916 if (mips_pic
== NO_PIC
)
7917 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7918 else if (mips_pic
== SVR4_PIC
)
7920 /* If this is a reference to an external symbol, and we are
7921 using a small GOT, we want
7922 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7926 lw $gp,cprestore($sp)
7927 The cprestore value is set using the .cprestore
7928 pseudo-op. If we are using a big GOT, we want
7929 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7931 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7935 lw $gp,cprestore($sp)
7936 If the symbol is not external, we want
7937 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7939 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7942 lw $gp,cprestore($sp)
7944 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7945 sequences above, minus nops, unless the symbol is local,
7946 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7952 relax_start (offset_expr
.X_add_symbol
);
7953 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7954 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7957 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7958 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
7964 relax_start (offset_expr
.X_add_symbol
);
7965 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7966 BFD_RELOC_MIPS_CALL_HI16
);
7967 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7968 PIC_CALL_REG
, mips_gp_register
);
7969 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7970 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7973 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7974 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
7976 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7977 PIC_CALL_REG
, PIC_CALL_REG
,
7978 BFD_RELOC_MIPS_GOT_OFST
);
7982 macro_build_jalr (&offset_expr
, 0);
7986 relax_start (offset_expr
.X_add_symbol
);
7989 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7990 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7999 gpdelay
= reg_needs_delay (mips_gp_register
);
8000 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8001 BFD_RELOC_MIPS_CALL_HI16
);
8002 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8003 PIC_CALL_REG
, mips_gp_register
);
8004 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8005 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8010 macro_build (NULL
, "nop", "");
8012 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8013 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
8016 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8017 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
8019 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
8021 if (mips_cprestore_offset
< 0)
8022 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8025 if (!mips_frame_reg_valid
)
8027 as_warn (_("No .frame pseudo-op used in PIC code"));
8028 /* Quiet this warning. */
8029 mips_frame_reg_valid
= 1;
8031 if (!mips_cprestore_valid
)
8033 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8034 /* Quiet this warning. */
8035 mips_cprestore_valid
= 1;
8037 if (mips_opts
.noreorder
)
8038 macro_build (NULL
, "nop", "");
8039 expr1
.X_add_number
= mips_cprestore_offset
;
8040 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8043 HAVE_64BIT_ADDRESSES
);
8047 else if (mips_pic
== VXWORKS_PIC
)
8048 as_bad (_("Non-PIC jump used in PIC library"));
8058 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8066 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8097 gas_assert (!mips_opts
.micromips
);
8100 /* Itbl support may require additional care here. */
8107 /* Itbl support may require additional care here. */
8115 off12
= mips_opts
.micromips
;
8116 /* Itbl support may require additional care here. */
8121 gas_assert (!mips_opts
.micromips
);
8124 /* Itbl support may require additional care here. */
8132 off12
= mips_opts
.micromips
;
8139 off12
= mips_opts
.micromips
;
8145 /* Itbl support may require additional care here. */
8153 off12
= mips_opts
.micromips
;
8154 /* Itbl support may require additional care here. */
8161 /* Itbl support may require additional care here. */
8169 off12
= mips_opts
.micromips
;
8176 off12
= mips_opts
.micromips
;
8183 off12
= mips_opts
.micromips
;
8190 off12
= mips_opts
.micromips
;
8197 off12
= mips_opts
.micromips
;
8202 gas_assert (mips_opts
.micromips
);
8211 gas_assert (mips_opts
.micromips
);
8220 gas_assert (mips_opts
.micromips
);
8228 gas_assert (mips_opts
.micromips
);
8235 if (breg
== treg
+ lp
)
8238 tempreg
= treg
+ lp
;
8258 gas_assert (!mips_opts
.micromips
);
8261 /* Itbl support may require additional care here. */
8268 /* Itbl support may require additional care here. */
8276 off12
= mips_opts
.micromips
;
8277 /* Itbl support may require additional care here. */
8282 gas_assert (!mips_opts
.micromips
);
8285 /* Itbl support may require additional care here. */
8293 off12
= mips_opts
.micromips
;
8300 off12
= mips_opts
.micromips
;
8307 off12
= mips_opts
.micromips
;
8314 off12
= mips_opts
.micromips
;
8320 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8321 off12
= mips_opts
.micromips
;
8327 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8328 off12
= mips_opts
.micromips
;
8335 /* Itbl support may require additional care here. */
8342 off12
= mips_opts
.micromips
;
8343 /* Itbl support may require additional care here. */
8348 gas_assert (!mips_opts
.micromips
);
8351 /* Itbl support may require additional care here. */
8359 off12
= mips_opts
.micromips
;
8366 off12
= mips_opts
.micromips
;
8371 gas_assert (mips_opts
.micromips
);
8379 gas_assert (mips_opts
.micromips
);
8387 gas_assert (mips_opts
.micromips
);
8395 gas_assert (mips_opts
.micromips
);
8404 if (offset_expr
.X_op
!= O_constant
8405 && offset_expr
.X_op
!= O_symbol
)
8407 as_bad (_("Expression too complex"));
8408 offset_expr
.X_op
= O_constant
;
8411 if (HAVE_32BIT_ADDRESSES
8412 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8416 sprintf_vma (value
, offset_expr
.X_add_number
);
8417 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8420 /* A constant expression in PIC code can be handled just as it
8421 is in non PIC code. */
8422 if (offset_expr
.X_op
== O_constant
)
8426 expr1
.X_add_number
= offset_expr
.X_add_number
;
8427 normalize_address_expr (&expr1
);
8428 if (!off12
&& !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8430 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8431 & ~(bfd_vma
) 0xffff);
8434 else if (off12
&& !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8436 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8437 & ~(bfd_vma
) 0xfff);
8442 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8444 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8445 tempreg
, tempreg
, breg
);
8450 if (offset_expr
.X_add_number
== 0)
8453 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8454 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8455 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8458 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8460 macro_build (NULL
, s
, fmt
,
8461 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8463 else if (off12
|| off0
)
8465 /* A 12-bit or 0-bit offset field is too narrow to be used
8466 for a low-part relocation, so load the whole address into
8467 the auxillary register. In the case of "A(b)" addresses,
8468 we first load absolute address "A" into the register and
8469 then add base register "b". In the case of "o(b)" addresses,
8470 we simply need to add 16-bit offset "o" to base register "b", and
8471 offset_reloc already contains the relocations associated
8475 load_address (tempreg
, &offset_expr
, &used_at
);
8477 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8478 tempreg
, tempreg
, breg
);
8481 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8483 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8484 expr1
.X_add_number
= 0;
8486 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8488 macro_build (NULL
, s
, fmt
,
8489 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8491 else if (mips_pic
== NO_PIC
)
8493 /* If this is a reference to a GP relative symbol, and there
8494 is no base register, we want
8495 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8496 Otherwise, if there is no base register, we want
8497 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8498 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8499 If we have a constant, we need two instructions anyhow,
8500 so we always use the latter form.
8502 If we have a base register, and this is a reference to a
8503 GP relative symbol, we want
8504 addu $tempreg,$breg,$gp
8505 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8507 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8508 addu $tempreg,$tempreg,$breg
8509 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8510 With a constant we always use the latter case.
8512 With 64bit address space and no base register and $at usable,
8514 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8515 lui $at,<sym> (BFD_RELOC_HI16_S)
8516 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8519 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8520 If we have a base register, we want
8521 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8522 lui $at,<sym> (BFD_RELOC_HI16_S)
8523 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8527 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8529 Without $at we can't generate the optimal path for superscalar
8530 processors here since this would require two temporary registers.
8531 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8532 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8534 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8536 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8537 If we have a base register, we want
8538 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8539 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8541 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8543 daddu $tempreg,$tempreg,$breg
8544 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8546 For GP relative symbols in 64bit address space we can use
8547 the same sequence as in 32bit address space. */
8548 if (HAVE_64BIT_SYMBOLS
)
8550 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8551 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8553 relax_start (offset_expr
.X_add_symbol
);
8556 macro_build (&offset_expr
, s
, fmt
, treg
,
8557 BFD_RELOC_GPREL16
, mips_gp_register
);
8561 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8562 tempreg
, breg
, mips_gp_register
);
8563 macro_build (&offset_expr
, s
, fmt
, treg
,
8564 BFD_RELOC_GPREL16
, tempreg
);
8569 if (used_at
== 0 && mips_opts
.at
)
8571 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8572 BFD_RELOC_MIPS_HIGHEST
);
8573 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8575 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8576 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8578 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8579 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8580 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8581 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8587 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8588 BFD_RELOC_MIPS_HIGHEST
);
8589 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8590 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8591 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8592 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8593 tempreg
, BFD_RELOC_HI16_S
);
8594 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8596 macro_build (NULL
, "daddu", "d,v,t",
8597 tempreg
, tempreg
, breg
);
8598 macro_build (&offset_expr
, s
, fmt
, treg
,
8599 BFD_RELOC_LO16
, tempreg
);
8602 if (mips_relax
.sequence
)
8609 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8610 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8612 relax_start (offset_expr
.X_add_symbol
);
8613 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8617 macro_build_lui (&offset_expr
, tempreg
);
8618 macro_build (&offset_expr
, s
, fmt
, treg
,
8619 BFD_RELOC_LO16
, tempreg
);
8620 if (mips_relax
.sequence
)
8625 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8626 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8628 relax_start (offset_expr
.X_add_symbol
);
8629 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8630 tempreg
, breg
, mips_gp_register
);
8631 macro_build (&offset_expr
, s
, fmt
, treg
,
8632 BFD_RELOC_GPREL16
, tempreg
);
8635 macro_build_lui (&offset_expr
, tempreg
);
8636 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8637 tempreg
, tempreg
, breg
);
8638 macro_build (&offset_expr
, s
, fmt
, treg
,
8639 BFD_RELOC_LO16
, tempreg
);
8640 if (mips_relax
.sequence
)
8644 else if (!mips_big_got
)
8646 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8648 /* If this is a reference to an external symbol, we want
8649 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8651 <op> $treg,0($tempreg)
8653 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8655 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8656 <op> $treg,0($tempreg)
8659 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8660 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8662 If there is a base register, we add it to $tempreg before
8663 the <op>. If there is a constant, we stick it in the
8664 <op> instruction. We don't handle constants larger than
8665 16 bits, because we have no way to load the upper 16 bits
8666 (actually, we could handle them for the subset of cases
8667 in which we are not using $at). */
8668 gas_assert (offset_expr
.X_op
== O_symbol
);
8671 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8672 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8674 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8675 tempreg
, tempreg
, breg
);
8676 macro_build (&offset_expr
, s
, fmt
, treg
,
8677 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8680 expr1
.X_add_number
= offset_expr
.X_add_number
;
8681 offset_expr
.X_add_number
= 0;
8682 if (expr1
.X_add_number
< -0x8000
8683 || expr1
.X_add_number
>= 0x8000)
8684 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8685 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8686 lw_reloc_type
, mips_gp_register
);
8688 relax_start (offset_expr
.X_add_symbol
);
8690 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8691 tempreg
, BFD_RELOC_LO16
);
8694 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8695 tempreg
, tempreg
, breg
);
8696 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8698 else if (mips_big_got
&& !HAVE_NEWABI
)
8702 /* If this is a reference to an external symbol, we want
8703 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8704 addu $tempreg,$tempreg,$gp
8705 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8706 <op> $treg,0($tempreg)
8708 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8710 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8711 <op> $treg,0($tempreg)
8712 If there is a base register, we add it to $tempreg before
8713 the <op>. If there is a constant, we stick it in the
8714 <op> instruction. We don't handle constants larger than
8715 16 bits, because we have no way to load the upper 16 bits
8716 (actually, we could handle them for the subset of cases
8717 in which we are not using $at). */
8718 gas_assert (offset_expr
.X_op
== O_symbol
);
8719 expr1
.X_add_number
= offset_expr
.X_add_number
;
8720 offset_expr
.X_add_number
= 0;
8721 if (expr1
.X_add_number
< -0x8000
8722 || expr1
.X_add_number
>= 0x8000)
8723 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8724 gpdelay
= reg_needs_delay (mips_gp_register
);
8725 relax_start (offset_expr
.X_add_symbol
);
8726 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8727 BFD_RELOC_MIPS_GOT_HI16
);
8728 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8730 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8731 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8734 macro_build (NULL
, "nop", "");
8735 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8736 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8738 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8739 tempreg
, BFD_RELOC_LO16
);
8743 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8744 tempreg
, tempreg
, breg
);
8745 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8747 else if (mips_big_got
&& HAVE_NEWABI
)
8749 /* If this is a reference to an external symbol, we want
8750 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8751 add $tempreg,$tempreg,$gp
8752 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8753 <op> $treg,<ofst>($tempreg)
8754 Otherwise, for local symbols, we want:
8755 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8756 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8757 gas_assert (offset_expr
.X_op
== O_symbol
);
8758 expr1
.X_add_number
= offset_expr
.X_add_number
;
8759 offset_expr
.X_add_number
= 0;
8760 if (expr1
.X_add_number
< -0x8000
8761 || expr1
.X_add_number
>= 0x8000)
8762 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8763 relax_start (offset_expr
.X_add_symbol
);
8764 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8765 BFD_RELOC_MIPS_GOT_HI16
);
8766 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8768 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8769 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8771 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8772 tempreg
, tempreg
, breg
);
8773 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8776 offset_expr
.X_add_number
= expr1
.X_add_number
;
8777 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8778 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8780 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8781 tempreg
, tempreg
, breg
);
8782 macro_build (&offset_expr
, s
, fmt
, treg
,
8783 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8793 load_register (treg
, &imm_expr
, 0);
8797 load_register (treg
, &imm_expr
, 1);
8801 if (imm_expr
.X_op
== O_constant
)
8804 load_register (AT
, &imm_expr
, 0);
8805 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8810 gas_assert (offset_expr
.X_op
== O_symbol
8811 && strcmp (segment_name (S_GET_SEGMENT
8812 (offset_expr
.X_add_symbol
)),
8814 && offset_expr
.X_add_number
== 0);
8815 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
8816 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8821 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8822 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8823 order 32 bits of the value and the low order 32 bits are either
8824 zero or in OFFSET_EXPR. */
8825 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8827 if (HAVE_64BIT_GPRS
)
8828 load_register (treg
, &imm_expr
, 1);
8833 if (target_big_endian
)
8845 load_register (hreg
, &imm_expr
, 0);
8848 if (offset_expr
.X_op
== O_absent
)
8849 move_register (lreg
, 0);
8852 gas_assert (offset_expr
.X_op
== O_constant
);
8853 load_register (lreg
, &offset_expr
, 0);
8860 /* We know that sym is in the .rdata section. First we get the
8861 upper 16 bits of the address. */
8862 if (mips_pic
== NO_PIC
)
8864 macro_build_lui (&offset_expr
, AT
);
8869 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8870 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8874 /* Now we load the register(s). */
8875 if (HAVE_64BIT_GPRS
)
8878 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8883 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8886 /* FIXME: How in the world do we deal with the possible
8888 offset_expr
.X_add_number
+= 4;
8889 macro_build (&offset_expr
, "lw", "t,o(b)",
8890 treg
+ 1, BFD_RELOC_LO16
, AT
);
8896 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8897 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8898 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8899 the value and the low order 32 bits are either zero or in
8901 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8904 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
8905 if (HAVE_64BIT_FPRS
)
8907 gas_assert (HAVE_64BIT_GPRS
);
8908 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
8912 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
8913 if (offset_expr
.X_op
== O_absent
)
8914 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
8917 gas_assert (offset_expr
.X_op
== O_constant
);
8918 load_register (AT
, &offset_expr
, 0);
8919 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8925 gas_assert (offset_expr
.X_op
== O_symbol
8926 && offset_expr
.X_add_number
== 0);
8927 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
8928 if (strcmp (s
, ".lit8") == 0)
8930 if ((mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8931 && (mips_opts
.arch
!= CPU_R5900
))
8933 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
8934 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8937 breg
= mips_gp_register
;
8938 r
= BFD_RELOC_MIPS_LITERAL
;
8943 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
8945 if (mips_pic
!= NO_PIC
)
8946 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8947 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8950 /* FIXME: This won't work for a 64 bit address. */
8951 macro_build_lui (&offset_expr
, AT
);
8954 if ((mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8955 && (mips_opts
.arch
!= CPU_R5900
))
8957 macro_build (&offset_expr
, "ldc1", "T,o(b)",
8958 treg
, BFD_RELOC_LO16
, AT
);
8967 /* Even on a big endian machine $fn comes before $fn+1. We have
8968 to adjust when loading from memory. */
8971 gas_assert (!mips_opts
.micromips
);
8972 gas_assert ((mips_opts
.isa
== ISA_MIPS1
)
8973 || (mips_opts
.arch
== CPU_R5900
));
8974 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8975 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
8976 /* FIXME: A possible overflow which I don't know how to deal
8978 offset_expr
.X_add_number
+= 4;
8979 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8980 target_big_endian
? treg
: treg
+ 1, r
, breg
);
8984 gas_assert (!mips_opts
.micromips
);
8985 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8986 /* Even on a big endian machine $fn comes before $fn+1. We have
8987 to adjust when storing to memory. */
8988 macro_build (&offset_expr
, "swc1", "T,o(b)",
8989 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
8990 offset_expr
.X_add_number
+= 4;
8991 macro_build (&offset_expr
, "swc1", "T,o(b)",
8992 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
8996 gas_assert (!mips_opts
.micromips
);
8998 * The MIPS assembler seems to check for X_add_number not
8999 * being double aligned and generating:
9002 * addiu at,at,%lo(foo+1)
9005 * But, the resulting address is the same after relocation so why
9006 * generate the extra instruction?
9008 /* Itbl support may require additional care here. */
9011 if ((mips_opts
.isa
!= ISA_MIPS1
) && (mips_opts
.arch
!= CPU_R5900
))
9020 gas_assert (!mips_opts
.micromips
);
9021 /* Itbl support may require additional care here. */
9024 if ((mips_opts
.isa
!= ISA_MIPS1
) && (mips_opts
.arch
!= CPU_R5900
))
9044 if (HAVE_64BIT_GPRS
)
9054 if (HAVE_64BIT_GPRS
)
9062 if (offset_expr
.X_op
!= O_symbol
9063 && offset_expr
.X_op
!= O_constant
)
9065 as_bad (_("Expression too complex"));
9066 offset_expr
.X_op
= O_constant
;
9069 if (HAVE_32BIT_ADDRESSES
9070 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9074 sprintf_vma (value
, offset_expr
.X_add_number
);
9075 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9078 /* Even on a big endian machine $fn comes before $fn+1. We have
9079 to adjust when loading from memory. We set coproc if we must
9080 load $fn+1 first. */
9081 /* Itbl support may require additional care here. */
9082 if (!target_big_endian
)
9085 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
9087 /* If this is a reference to a GP relative symbol, we want
9088 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9089 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9090 If we have a base register, we use this
9092 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9093 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9094 If this is not a GP relative symbol, we want
9095 lui $at,<sym> (BFD_RELOC_HI16_S)
9096 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9097 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9098 If there is a base register, we add it to $at after the
9099 lui instruction. If there is a constant, we always use
9101 if (offset_expr
.X_op
== O_symbol
9102 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9103 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9105 relax_start (offset_expr
.X_add_symbol
);
9108 tempreg
= mips_gp_register
;
9112 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9113 AT
, breg
, mips_gp_register
);
9118 /* Itbl support may require additional care here. */
9119 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9120 BFD_RELOC_GPREL16
, tempreg
);
9121 offset_expr
.X_add_number
+= 4;
9123 /* Set mips_optimize to 2 to avoid inserting an
9125 hold_mips_optimize
= mips_optimize
;
9127 /* Itbl support may require additional care here. */
9128 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9129 BFD_RELOC_GPREL16
, tempreg
);
9130 mips_optimize
= hold_mips_optimize
;
9134 offset_expr
.X_add_number
-= 4;
9137 macro_build_lui (&offset_expr
, AT
);
9139 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9140 /* Itbl support may require additional care here. */
9141 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9142 BFD_RELOC_LO16
, AT
);
9143 /* FIXME: How do we handle overflow here? */
9144 offset_expr
.X_add_number
+= 4;
9145 /* Itbl support may require additional care here. */
9146 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9147 BFD_RELOC_LO16
, AT
);
9148 if (mips_relax
.sequence
)
9151 else if (!mips_big_got
)
9153 /* If this is a reference to an external symbol, we want
9154 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9159 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9161 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9162 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9163 If there is a base register we add it to $at before the
9164 lwc1 instructions. If there is a constant we include it
9165 in the lwc1 instructions. */
9167 expr1
.X_add_number
= offset_expr
.X_add_number
;
9168 if (expr1
.X_add_number
< -0x8000
9169 || expr1
.X_add_number
>= 0x8000 - 4)
9170 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9171 load_got_offset (AT
, &offset_expr
);
9174 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9176 /* Set mips_optimize to 2 to avoid inserting an undesired
9178 hold_mips_optimize
= mips_optimize
;
9181 /* Itbl support may require additional care here. */
9182 relax_start (offset_expr
.X_add_symbol
);
9183 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9184 BFD_RELOC_LO16
, AT
);
9185 expr1
.X_add_number
+= 4;
9186 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9187 BFD_RELOC_LO16
, AT
);
9189 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9190 BFD_RELOC_LO16
, AT
);
9191 offset_expr
.X_add_number
+= 4;
9192 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9193 BFD_RELOC_LO16
, AT
);
9196 mips_optimize
= hold_mips_optimize
;
9198 else if (mips_big_got
)
9202 /* If this is a reference to an external symbol, we want
9203 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9205 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9210 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9212 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9213 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9214 If there is a base register we add it to $at before the
9215 lwc1 instructions. If there is a constant we include it
9216 in the lwc1 instructions. */
9218 expr1
.X_add_number
= offset_expr
.X_add_number
;
9219 offset_expr
.X_add_number
= 0;
9220 if (expr1
.X_add_number
< -0x8000
9221 || expr1
.X_add_number
>= 0x8000 - 4)
9222 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9223 gpdelay
= reg_needs_delay (mips_gp_register
);
9224 relax_start (offset_expr
.X_add_symbol
);
9225 macro_build (&offset_expr
, "lui", LUI_FMT
,
9226 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9227 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9228 AT
, AT
, mips_gp_register
);
9229 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9230 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9233 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9234 /* Itbl support may require additional care here. */
9235 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9236 BFD_RELOC_LO16
, AT
);
9237 expr1
.X_add_number
+= 4;
9239 /* Set mips_optimize to 2 to avoid inserting an undesired
9241 hold_mips_optimize
= mips_optimize
;
9243 /* Itbl support may require additional care here. */
9244 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9245 BFD_RELOC_LO16
, AT
);
9246 mips_optimize
= hold_mips_optimize
;
9247 expr1
.X_add_number
-= 4;
9250 offset_expr
.X_add_number
= expr1
.X_add_number
;
9252 macro_build (NULL
, "nop", "");
9253 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9254 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9257 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9258 /* Itbl support may require additional care here. */
9259 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9260 BFD_RELOC_LO16
, AT
);
9261 offset_expr
.X_add_number
+= 4;
9263 /* Set mips_optimize to 2 to avoid inserting an undesired
9265 hold_mips_optimize
= mips_optimize
;
9267 /* Itbl support may require additional care here. */
9268 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9269 BFD_RELOC_LO16
, AT
);
9270 mips_optimize
= hold_mips_optimize
;
9279 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9282 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9284 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9285 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9287 if (!HAVE_64BIT_GPRS
)
9289 offset_expr
.X_add_number
+= 4;
9290 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9291 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9312 /* New code added to support COPZ instructions.
9313 This code builds table entries out of the macros in mip_opcodes.
9314 R4000 uses interlocks to handle coproc delays.
9315 Other chips (like the R3000) require nops to be inserted for delays.
9317 FIXME: Currently, we require that the user handle delays.
9318 In order to fill delay slots for non-interlocked chips,
9319 we must have a way to specify delays based on the coprocessor.
9320 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9321 What are the side-effects of the cop instruction?
9322 What cache support might we have and what are its effects?
9323 Both coprocessor & memory require delays. how long???
9324 What registers are read/set/modified?
9326 If an itbl is provided to interpret cop instructions,
9327 this knowledge can be encoded in the itbl spec. */
9341 gas_assert (!mips_opts
.micromips
);
9342 /* For now we just do C (same as Cz). The parameter will be
9343 stored in insn_opcode by mips_ip. */
9344 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9348 move_register (dreg
, sreg
);
9354 if (mips_opts
.arch
== CPU_R5900
)
9356 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
9360 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9361 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9368 /* The MIPS assembler some times generates shifts and adds. I'm
9369 not trying to be that fancy. GCC should do this for us
9372 load_register (AT
, &imm_expr
, dbl
);
9373 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9374 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9390 load_register (AT
, &imm_expr
, dbl
);
9391 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9392 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9393 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9394 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9396 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9399 if (mips_opts
.micromips
)
9400 micromips_label_expr (&label_expr
);
9402 label_expr
.X_add_number
= 8;
9403 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9404 macro_build (NULL
, "nop", "");
9405 macro_build (NULL
, "break", BRK_FMT
, 6);
9406 if (mips_opts
.micromips
)
9407 micromips_add_label ();
9410 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9426 load_register (AT
, &imm_expr
, dbl
);
9427 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9428 sreg
, imm
? AT
: treg
);
9429 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9430 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9432 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9435 if (mips_opts
.micromips
)
9436 micromips_label_expr (&label_expr
);
9438 label_expr
.X_add_number
= 8;
9439 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9440 macro_build (NULL
, "nop", "");
9441 macro_build (NULL
, "break", BRK_FMT
, 6);
9442 if (mips_opts
.micromips
)
9443 micromips_add_label ();
9449 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9460 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9461 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9465 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9466 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9467 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9468 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9472 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9483 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9484 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9488 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9489 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9490 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9491 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9500 if (imm_expr
.X_op
!= O_constant
)
9501 as_bad (_("Improper rotate count"));
9502 rot
= imm_expr
.X_add_number
& 0x3f;
9503 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9505 rot
= (64 - rot
) & 0x3f;
9507 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9509 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9514 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9517 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9518 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9521 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9522 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9523 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9531 if (imm_expr
.X_op
!= O_constant
)
9532 as_bad (_("Improper rotate count"));
9533 rot
= imm_expr
.X_add_number
& 0x1f;
9534 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9536 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9541 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9545 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9546 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9547 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9552 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9554 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9558 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9559 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9560 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9561 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9565 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9567 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9571 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9572 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9573 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9574 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9583 if (imm_expr
.X_op
!= O_constant
)
9584 as_bad (_("Improper rotate count"));
9585 rot
= imm_expr
.X_add_number
& 0x3f;
9586 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9589 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9591 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9596 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9599 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9600 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9603 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9604 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9605 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9613 if (imm_expr
.X_op
!= O_constant
)
9614 as_bad (_("Improper rotate count"));
9615 rot
= imm_expr
.X_add_number
& 0x1f;
9616 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9618 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9623 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9627 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9628 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9629 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9635 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9637 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9640 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9641 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9646 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9648 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9653 as_warn (_("Instruction %s: result is always false"),
9655 move_register (dreg
, 0);
9658 if (CPU_HAS_SEQ (mips_opts
.arch
)
9659 && -512 <= imm_expr
.X_add_number
9660 && imm_expr
.X_add_number
< 512)
9662 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9663 (int) imm_expr
.X_add_number
);
9666 if (imm_expr
.X_op
== O_constant
9667 && imm_expr
.X_add_number
>= 0
9668 && imm_expr
.X_add_number
< 0x10000)
9670 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9672 else if (imm_expr
.X_op
== O_constant
9673 && imm_expr
.X_add_number
> -0x8000
9674 && imm_expr
.X_add_number
< 0)
9676 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9677 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9678 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9680 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9683 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9684 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9689 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9690 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9693 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9696 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9702 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9703 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9706 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9708 if (imm_expr
.X_op
== O_constant
9709 && imm_expr
.X_add_number
>= -0x8000
9710 && imm_expr
.X_add_number
< 0x8000)
9712 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9713 dreg
, sreg
, BFD_RELOC_LO16
);
9717 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9718 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9722 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9725 case M_SGT
: /* sreg > treg <==> treg < sreg */
9731 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9734 case M_SGT_I
: /* sreg > I <==> I < sreg */
9741 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9742 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9745 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9751 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9752 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9755 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9762 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9763 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9764 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9768 if (imm_expr
.X_op
== O_constant
9769 && imm_expr
.X_add_number
>= -0x8000
9770 && imm_expr
.X_add_number
< 0x8000)
9772 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9776 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9777 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9781 if (imm_expr
.X_op
== O_constant
9782 && imm_expr
.X_add_number
>= -0x8000
9783 && imm_expr
.X_add_number
< 0x8000)
9785 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9790 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9791 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9796 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9798 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9801 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9802 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9807 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9809 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9814 as_warn (_("Instruction %s: result is always true"),
9816 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
9817 dreg
, 0, BFD_RELOC_LO16
);
9820 if (CPU_HAS_SEQ (mips_opts
.arch
)
9821 && -512 <= imm_expr
.X_add_number
9822 && imm_expr
.X_add_number
< 512)
9824 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
9825 (int) imm_expr
.X_add_number
);
9828 if (imm_expr
.X_op
== O_constant
9829 && imm_expr
.X_add_number
>= 0
9830 && imm_expr
.X_add_number
< 0x10000)
9832 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9834 else if (imm_expr
.X_op
== O_constant
9835 && imm_expr
.X_add_number
> -0x8000
9836 && imm_expr
.X_add_number
< 0)
9838 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9839 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9840 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9842 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9845 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9846 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
9851 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9852 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9855 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9870 if (!mips_opts
.micromips
)
9872 if (imm_expr
.X_op
== O_constant
9873 && imm_expr
.X_add_number
> -0x200
9874 && imm_expr
.X_add_number
<= 0x200)
9876 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
9885 if (imm_expr
.X_op
== O_constant
9886 && imm_expr
.X_add_number
> -0x8000
9887 && imm_expr
.X_add_number
<= 0x8000)
9889 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9890 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9895 load_register (AT
, &imm_expr
, dbl
);
9896 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
9918 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9919 macro_build (NULL
, s
, "s,t", sreg
, AT
);
9924 gas_assert (!mips_opts
.micromips
);
9925 gas_assert ((mips_opts
.isa
== ISA_MIPS1
) || (mips_opts
.arch
== CPU_R5900
));
9927 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
9928 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
9931 * Is the double cfc1 instruction a bug in the mips assembler;
9932 * or is there a reason for it?
9935 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9936 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9937 macro_build (NULL
, "nop", "");
9938 expr1
.X_add_number
= 3;
9939 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
9940 expr1
.X_add_number
= 2;
9941 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
9942 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
9943 macro_build (NULL
, "nop", "");
9944 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
9946 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
9947 macro_build (NULL
, "nop", "");
9970 off12
= mips_opts
.micromips
;
9978 off12
= mips_opts
.micromips
;
9994 off12
= mips_opts
.micromips
;
10003 off12
= mips_opts
.micromips
;
10008 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
10009 as_bad (_("Operand overflow"));
10012 expr1
.X_add_number
= 0;
10017 load_address (tempreg
, ep
, &used_at
);
10019 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10020 tempreg
, tempreg
, breg
);
10026 && (offset_expr
.X_op
!= O_constant
10027 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
10028 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
10032 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
10033 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10038 else if (!ust
&& treg
== breg
)
10049 if (!target_big_endian
)
10050 ep
->X_add_number
+= off
;
10052 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10054 macro_build (NULL
, s
, "t,~(b)",
10055 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10057 if (!target_big_endian
)
10058 ep
->X_add_number
-= off
;
10060 ep
->X_add_number
+= off
;
10062 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10064 macro_build (NULL
, s2
, "t,~(b)",
10065 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10067 /* If necessary, move the result in tempreg to the final destination. */
10068 if (!ust
&& treg
!= tempreg
)
10070 /* Protect second load's delay slot. */
10072 move_register (treg
, tempreg
);
10078 if (target_big_endian
== ust
)
10079 ep
->X_add_number
+= off
;
10080 tempreg
= ust
|| ab
? treg
: AT
;
10081 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10083 /* For halfword transfers we need a temporary register to shuffle
10084 bytes. Unfortunately for M_USH_A we have none available before
10085 the next store as AT holds the base address. We deal with this
10086 case by clobbering TREG and then restoring it as with ULH. */
10087 tempreg
= ust
== ab
? treg
: AT
;
10089 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
10091 if (target_big_endian
== ust
)
10092 ep
->X_add_number
-= off
;
10094 ep
->X_add_number
+= off
;
10095 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10097 /* For M_USH_A re-retrieve the LSB. */
10100 if (target_big_endian
)
10101 ep
->X_add_number
+= off
;
10103 ep
->X_add_number
-= off
;
10104 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
10106 /* For ULH and M_USH_A OR the LSB in. */
10109 tempreg
= !ab
? AT
: treg
;
10110 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
10111 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
10116 /* FIXME: Check if this is one of the itbl macros, since they
10117 are added dynamically. */
10118 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
10121 if (!mips_opts
.at
&& used_at
)
10122 as_bad (_("Macro used $at after \".set noat\""));
10125 /* Implement macros in mips16 mode. */
10128 mips16_macro (struct mips_cl_insn
*ip
)
10131 int xreg
, yreg
, zreg
, tmp
;
10134 const char *s
, *s2
, *s3
;
10136 mask
= ip
->insn_mo
->mask
;
10138 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10139 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10140 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10142 expr1
.X_op
= O_constant
;
10143 expr1
.X_op_symbol
= NULL
;
10144 expr1
.X_add_symbol
= NULL
;
10145 expr1
.X_add_number
= 1;
10164 start_noreorder ();
10165 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10166 expr1
.X_add_number
= 2;
10167 macro_build (&expr1
, "bnez", "x,p", yreg
);
10168 macro_build (NULL
, "break", "6", 7);
10170 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10171 since that causes an overflow. We should do that as well,
10172 but I don't see how to do the comparisons without a temporary
10175 macro_build (NULL
, s
, "x", zreg
);
10194 start_noreorder ();
10195 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10196 expr1
.X_add_number
= 2;
10197 macro_build (&expr1
, "bnez", "x,p", yreg
);
10198 macro_build (NULL
, "break", "6", 7);
10200 macro_build (NULL
, s2
, "x", zreg
);
10206 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10207 macro_build (NULL
, "mflo", "x", zreg
);
10215 if (imm_expr
.X_op
!= O_constant
)
10216 as_bad (_("Unsupported large constant"));
10217 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10218 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10222 if (imm_expr
.X_op
!= O_constant
)
10223 as_bad (_("Unsupported large constant"));
10224 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10225 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10229 if (imm_expr
.X_op
!= O_constant
)
10230 as_bad (_("Unsupported large constant"));
10231 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10232 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10254 goto do_reverse_branch
;
10258 goto do_reverse_branch
;
10270 goto do_reverse_branch
;
10281 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10282 macro_build (&offset_expr
, s2
, "p");
10309 goto do_addone_branch_i
;
10314 goto do_addone_branch_i
;
10329 goto do_addone_branch_i
;
10335 do_addone_branch_i
:
10336 if (imm_expr
.X_op
!= O_constant
)
10337 as_bad (_("Unsupported large constant"));
10338 ++imm_expr
.X_add_number
;
10341 macro_build (&imm_expr
, s
, s3
, xreg
);
10342 macro_build (&offset_expr
, s2
, "p");
10346 expr1
.X_add_number
= 0;
10347 macro_build (&expr1
, "slti", "x,8", yreg
);
10349 move_register (xreg
, yreg
);
10350 expr1
.X_add_number
= 2;
10351 macro_build (&expr1
, "bteqz", "p");
10352 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10356 /* For consistency checking, verify that all bits are specified either
10357 by the match/mask part of the instruction definition, or by the
10360 validate_mips_insn (const struct mips_opcode
*opc
)
10362 const char *p
= opc
->args
;
10364 unsigned long used_bits
= opc
->mask
;
10366 if ((used_bits
& opc
->match
) != opc
->match
)
10368 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10369 opc
->name
, opc
->args
);
10372 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10382 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10383 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10384 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10385 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10386 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10387 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10388 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10389 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10390 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10391 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10392 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10393 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10394 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10396 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10397 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10398 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10399 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10400 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10401 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10402 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10403 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10404 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10405 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10406 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10407 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10408 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10409 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10410 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10413 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10414 c
, opc
->name
, opc
->args
);
10418 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10419 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10421 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10422 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10423 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10424 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10426 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10427 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10429 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10430 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10432 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10433 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10434 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10435 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10436 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10437 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10438 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10439 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10440 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10441 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10442 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10443 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10444 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10445 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10446 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10447 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10448 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10450 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10451 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10452 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10453 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10455 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10456 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10457 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10458 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10459 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10460 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10461 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10462 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10463 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10466 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10467 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10468 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10469 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10470 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10473 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10474 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10475 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10476 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10477 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10478 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10479 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10480 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10481 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10482 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10483 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10484 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10485 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10486 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10487 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10488 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10489 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10490 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10491 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10492 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10494 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10495 c
, opc
->name
, opc
->args
);
10499 if (used_bits
!= 0xffffffff)
10501 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10502 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10508 /* For consistency checking, verify that the length implied matches the
10509 major opcode and that all bits are specified either by the match/mask
10510 part of the instruction definition, or by the operand list. */
10513 validate_micromips_insn (const struct mips_opcode
*opc
)
10515 unsigned long match
= opc
->match
;
10516 unsigned long mask
= opc
->mask
;
10517 const char *p
= opc
->args
;
10518 unsigned long insn_bits
;
10519 unsigned long used_bits
;
10520 unsigned long major
;
10521 unsigned int length
;
10525 if ((mask
& match
) != match
)
10527 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10528 opc
->name
, opc
->args
);
10531 length
= micromips_insn_length (opc
);
10532 if (length
!= 2 && length
!= 4)
10534 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10535 "%s %s"), length
, opc
->name
, opc
->args
);
10538 major
= match
>> (10 + 8 * (length
- 2));
10539 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10540 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10542 as_bad (_("Internal error: bad microMIPS opcode "
10543 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10547 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10548 insn_bits
= 1 << 4 * length
;
10549 insn_bits
<<= 4 * length
;
10552 #define USE_BITS(field) \
10553 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10564 case 'A': USE_BITS (EXTLSB
); break;
10565 case 'B': USE_BITS (INSMSB
); break;
10566 case 'C': USE_BITS (EXTMSBD
); break;
10567 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10568 case 'E': USE_BITS (EXTLSB
); break;
10569 case 'F': USE_BITS (INSMSB
); break;
10570 case 'G': USE_BITS (EXTMSBD
); break;
10571 case 'H': USE_BITS (EXTMSBD
); break;
10573 as_bad (_("Internal error: bad mips opcode "
10574 "(unknown extension operand type `%c%c'): %s %s"),
10575 e
, c
, opc
->name
, opc
->args
);
10583 case 'A': USE_BITS (IMMA
); break;
10584 case 'B': USE_BITS (IMMB
); break;
10585 case 'C': USE_BITS (IMMC
); break;
10586 case 'D': USE_BITS (IMMD
); break;
10587 case 'E': USE_BITS (IMME
); break;
10588 case 'F': USE_BITS (IMMF
); break;
10589 case 'G': USE_BITS (IMMG
); break;
10590 case 'H': USE_BITS (IMMH
); break;
10591 case 'I': USE_BITS (IMMI
); break;
10592 case 'J': USE_BITS (IMMJ
); break;
10593 case 'L': USE_BITS (IMML
); break;
10594 case 'M': USE_BITS (IMMM
); break;
10595 case 'N': USE_BITS (IMMN
); break;
10596 case 'O': USE_BITS (IMMO
); break;
10597 case 'P': USE_BITS (IMMP
); break;
10598 case 'Q': USE_BITS (IMMQ
); break;
10599 case 'U': USE_BITS (IMMU
); break;
10600 case 'W': USE_BITS (IMMW
); break;
10601 case 'X': USE_BITS (IMMX
); break;
10602 case 'Y': USE_BITS (IMMY
); break;
10605 case 'b': USE_BITS (MB
); break;
10606 case 'c': USE_BITS (MC
); break;
10607 case 'd': USE_BITS (MD
); break;
10608 case 'e': USE_BITS (ME
); break;
10609 case 'f': USE_BITS (MF
); break;
10610 case 'g': USE_BITS (MG
); break;
10611 case 'h': USE_BITS (MH
); break;
10612 case 'i': USE_BITS (MI
); break;
10613 case 'j': USE_BITS (MJ
); break;
10614 case 'l': USE_BITS (ML
); break;
10615 case 'm': USE_BITS (MM
); break;
10616 case 'n': USE_BITS (MN
); break;
10617 case 'p': USE_BITS (MP
); break;
10618 case 'q': USE_BITS (MQ
); break;
10626 as_bad (_("Internal error: bad mips opcode "
10627 "(unknown extension operand type `%c%c'): %s %s"),
10628 e
, c
, opc
->name
, opc
->args
);
10632 case '.': USE_BITS (OFFSET10
); break;
10633 case '1': USE_BITS (STYPE
); break;
10634 case '2': USE_BITS (BP
); break;
10635 case '3': USE_BITS (SA3
); break;
10636 case '4': USE_BITS (SA4
); break;
10637 case '5': USE_BITS (IMM8
); break;
10638 case '6': USE_BITS (RS
); break;
10639 case '7': USE_BITS (DSPACC
); break;
10640 case '8': USE_BITS (WRDSP
); break;
10641 case '0': USE_BITS (DSPSFT
); break;
10642 case '<': USE_BITS (SHAMT
); break;
10643 case '>': USE_BITS (SHAMT
); break;
10644 case '@': USE_BITS (IMM10
); break;
10645 case 'B': USE_BITS (CODE10
); break;
10646 case 'C': USE_BITS (COPZ
); break;
10647 case 'D': USE_BITS (FD
); break;
10648 case 'E': USE_BITS (RT
); break;
10649 case 'G': USE_BITS (RS
); break;
10650 case 'H': USE_BITS (SEL
); break;
10651 case 'K': USE_BITS (RS
); break;
10652 case 'M': USE_BITS (CCC
); break;
10653 case 'N': USE_BITS (BCC
); break;
10654 case 'R': USE_BITS (FR
); break;
10655 case 'S': USE_BITS (FS
); break;
10656 case 'T': USE_BITS (FT
); break;
10657 case 'V': USE_BITS (FS
); break;
10658 case '\\': USE_BITS (3BITPOS
); break;
10659 case '^': USE_BITS (RD
); break;
10660 case 'a': USE_BITS (TARGET
); break;
10661 case 'b': USE_BITS (RS
); break;
10662 case 'c': USE_BITS (CODE
); break;
10663 case 'd': USE_BITS (RD
); break;
10664 case 'h': USE_BITS (PREFX
); break;
10665 case 'i': USE_BITS (IMMEDIATE
); break;
10666 case 'j': USE_BITS (DELTA
); break;
10667 case 'k': USE_BITS (CACHE
); break;
10668 case 'n': USE_BITS (RT
); break;
10669 case 'o': USE_BITS (DELTA
); break;
10670 case 'p': USE_BITS (DELTA
); break;
10671 case 'q': USE_BITS (CODE2
); break;
10672 case 'r': USE_BITS (RS
); break;
10673 case 's': USE_BITS (RS
); break;
10674 case 't': USE_BITS (RT
); break;
10675 case 'u': USE_BITS (IMMEDIATE
); break;
10676 case 'v': USE_BITS (RS
); break;
10677 case 'w': USE_BITS (RT
); break;
10678 case 'y': USE_BITS (RS3
); break;
10680 case '|': USE_BITS (TRAP
); break;
10681 case '~': USE_BITS (OFFSET12
); break;
10683 as_bad (_("Internal error: bad microMIPS opcode "
10684 "(unknown operand type `%c'): %s %s"),
10685 c
, opc
->name
, opc
->args
);
10689 if (used_bits
!= insn_bits
)
10691 if (~used_bits
& insn_bits
)
10692 as_bad (_("Internal error: bad microMIPS opcode "
10693 "(bits 0x%lx undefined): %s %s"),
10694 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10695 if (used_bits
& ~insn_bits
)
10696 as_bad (_("Internal error: bad microMIPS opcode "
10697 "(bits 0x%lx defined): %s %s"),
10698 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10704 /* UDI immediates. */
10705 struct mips_immed
{
10707 unsigned int shift
;
10708 unsigned long mask
;
10712 static const struct mips_immed mips_immed
[] = {
10713 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10714 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10715 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10716 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10720 /* Check whether an odd floating-point register is allowed. */
10722 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10724 const char *s
= insn
->name
;
10726 if (insn
->pinfo
== INSN_MACRO
)
10727 /* Let a macro pass, we'll catch it later when it is expanded. */
10730 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || (mips_opts
.arch
== CPU_R5900
))
10732 /* Allow odd registers for single-precision ops. */
10733 switch (insn
->pinfo
& (FP_S
| FP_D
))
10737 return 1; /* both single precision - ok */
10739 return 0; /* both double precision - fail */
10744 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10745 s
= strchr (insn
->name
, '.');
10747 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10748 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10751 /* Single-precision coprocessor loads and moves are OK too. */
10752 if ((insn
->pinfo
& FP_S
)
10753 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10754 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10760 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10761 taking bits from BIT up. */
10763 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10765 return (ep
->X_op
== O_constant
10766 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10767 && ep
->X_add_number
>= min
<< bit
10768 && ep
->X_add_number
< max
<< bit
);
10771 /* This routine assembles an instruction into its binary format. As a
10772 side effect, it sets one of the global variables imm_reloc or
10773 offset_reloc to the type of relocation to do if one of the operands
10774 is an address expression. */
10777 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10779 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10780 bfd_boolean need_delay_slot_ok
= TRUE
;
10781 struct mips_opcode
*firstinsn
= NULL
;
10782 const struct mips_opcode
*past
;
10783 struct hash_control
*hash
;
10787 struct mips_opcode
*insn
;
10789 unsigned int regno
;
10790 unsigned int lastregno
;
10791 unsigned int destregno
= 0;
10792 unsigned int lastpos
= 0;
10793 unsigned int limlo
, limhi
;
10795 offsetT min_range
, max_range
;
10799 unsigned int rtype
;
10805 if (mips_opts
.micromips
)
10807 hash
= micromips_op_hash
;
10808 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10813 past
= &mips_opcodes
[NUMOPCODES
];
10815 forced_insn_length
= 0;
10818 /* We first try to match an instruction up to a space or to the end. */
10819 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10822 /* Make a copy of the instruction so that we can fiddle with it. */
10823 name
= alloca (end
+ 1);
10824 memcpy (name
, str
, end
);
10829 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10831 if (insn
!= NULL
|| !mips_opts
.micromips
)
10833 if (forced_insn_length
)
10836 /* See if there's an instruction size override suffix,
10837 either `16' or `32', at the end of the mnemonic proper,
10838 that defines the operation, i.e. before the first `.'
10839 character if any. Strip it and retry. */
10840 dot
= strchr (name
, '.');
10841 opend
= dot
!= NULL
? dot
- name
: end
;
10844 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10845 forced_insn_length
= 2;
10846 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
10847 forced_insn_length
= 4;
10850 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
10854 insn_error
= _("Unrecognized opcode");
10858 /* For microMIPS instructions placed in a fixed-length branch delay slot
10859 we make up to two passes over the relevant fragment of the opcode
10860 table. First we try instructions that meet the delay slot's length
10861 requirement. If none matched, then we retry with the remaining ones
10862 and if one matches, then we use it and then issue an appropriate
10863 warning later on. */
10864 argsStart
= s
= str
+ end
;
10867 bfd_boolean delay_slot_ok
;
10868 bfd_boolean size_ok
;
10871 gas_assert (strcmp (insn
->name
, name
) == 0);
10873 ok
= is_opcode_valid (insn
);
10874 size_ok
= is_size_valid (insn
);
10875 delay_slot_ok
= is_delay_slot_valid (insn
);
10876 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
10879 wrong_delay_slot_insns
= TRUE
;
10881 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
10883 static char buf
[256];
10885 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
10890 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
10892 gas_assert (firstinsn
);
10893 need_delay_slot_ok
= FALSE
;
10903 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
10904 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10905 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10907 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
10908 8 * forced_insn_length
);
10914 create_insn (ip
, insn
);
10917 lastregno
= 0xffffffff;
10918 for (args
= insn
->args
;; ++args
)
10922 s
+= strspn (s
, " \t");
10926 case '\0': /* end of args */
10932 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10933 code) or 14 (for microMIPS code). */
10934 my_getExpression (&imm_expr
, s
);
10935 check_absolute_expr (ip
, &imm_expr
);
10936 if ((unsigned long) imm_expr
.X_add_number
!= 1
10937 && (unsigned long) imm_expr
.X_add_number
!= 3)
10939 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10940 (unsigned long) imm_expr
.X_add_number
);
10942 INSERT_OPERAND (mips_opts
.micromips
,
10943 BP
, *ip
, imm_expr
.X_add_number
);
10944 imm_expr
.X_op
= O_absent
;
10949 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10950 code) or 21 (for microMIPS code). */
10952 unsigned long mask
= (mips_opts
.micromips
10953 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
10955 my_getExpression (&imm_expr
, s
);
10956 check_absolute_expr (ip
, &imm_expr
);
10957 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10958 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10959 mask
, (unsigned long) imm_expr
.X_add_number
);
10960 INSERT_OPERAND (mips_opts
.micromips
,
10961 SA3
, *ip
, imm_expr
.X_add_number
);
10962 imm_expr
.X_op
= O_absent
;
10968 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10969 code) or 21 (for microMIPS code). */
10971 unsigned long mask
= (mips_opts
.micromips
10972 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
10974 my_getExpression (&imm_expr
, s
);
10975 check_absolute_expr (ip
, &imm_expr
);
10976 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10977 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10978 mask
, (unsigned long) imm_expr
.X_add_number
);
10979 INSERT_OPERAND (mips_opts
.micromips
,
10980 SA4
, *ip
, imm_expr
.X_add_number
);
10981 imm_expr
.X_op
= O_absent
;
10987 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10988 code) or 16 (for microMIPS code). */
10990 unsigned long mask
= (mips_opts
.micromips
10991 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
10993 my_getExpression (&imm_expr
, s
);
10994 check_absolute_expr (ip
, &imm_expr
);
10995 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10996 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10997 mask
, (unsigned long) imm_expr
.X_add_number
);
10998 INSERT_OPERAND (mips_opts
.micromips
,
10999 IMM8
, *ip
, imm_expr
.X_add_number
);
11000 imm_expr
.X_op
= O_absent
;
11006 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11007 code) or 21 (for microMIPS code). */
11009 unsigned long mask
= (mips_opts
.micromips
11010 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
11012 my_getExpression (&imm_expr
, s
);
11013 check_absolute_expr (ip
, &imm_expr
);
11014 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11015 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11016 mask
, (unsigned long) imm_expr
.X_add_number
);
11017 INSERT_OPERAND (mips_opts
.micromips
,
11018 RS
, *ip
, imm_expr
.X_add_number
);
11019 imm_expr
.X_op
= O_absent
;
11024 case '7': /* Four DSP accumulators in bits 11,12. */
11025 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11026 && s
[3] >= '0' && s
[3] <= '3')
11028 regno
= s
[3] - '0';
11030 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
11034 as_bad (_("Invalid dsp acc register"));
11038 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11039 code) or 14 (for microMIPS code). */
11041 unsigned long mask
= (mips_opts
.micromips
11042 ? MICROMIPSOP_MASK_WRDSP
11045 my_getExpression (&imm_expr
, s
);
11046 check_absolute_expr (ip
, &imm_expr
);
11047 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11048 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11049 mask
, (unsigned long) imm_expr
.X_add_number
);
11050 INSERT_OPERAND (mips_opts
.micromips
,
11051 WRDSP
, *ip
, imm_expr
.X_add_number
);
11052 imm_expr
.X_op
= O_absent
;
11057 case '9': /* Four DSP accumulators in bits 21,22. */
11058 gas_assert (!mips_opts
.micromips
);
11059 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11060 && s
[3] >= '0' && s
[3] <= '3')
11062 regno
= s
[3] - '0';
11064 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
11068 as_bad (_("Invalid dsp acc register"));
11072 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11073 code) or 20 (for microMIPS code). */
11075 long mask
= (mips_opts
.micromips
11076 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
11078 my_getExpression (&imm_expr
, s
);
11079 check_absolute_expr (ip
, &imm_expr
);
11080 min_range
= -((mask
+ 1) >> 1);
11081 max_range
= ((mask
+ 1) >> 1) - 1;
11082 if (imm_expr
.X_add_number
< min_range
11083 || imm_expr
.X_add_number
> max_range
)
11084 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11085 (long) min_range
, (long) max_range
,
11086 (long) imm_expr
.X_add_number
);
11087 INSERT_OPERAND (mips_opts
.micromips
,
11088 DSPSFT
, *ip
, imm_expr
.X_add_number
);
11089 imm_expr
.X_op
= O_absent
;
11094 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11095 gas_assert (!mips_opts
.micromips
);
11096 my_getExpression (&imm_expr
, s
);
11097 check_absolute_expr (ip
, &imm_expr
);
11098 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
11100 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11102 (unsigned long) imm_expr
.X_add_number
);
11104 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
11105 imm_expr
.X_op
= O_absent
;
11109 case ':': /* DSP 7-bit signed immediate in bit 19. */
11110 gas_assert (!mips_opts
.micromips
);
11111 my_getExpression (&imm_expr
, s
);
11112 check_absolute_expr (ip
, &imm_expr
);
11113 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11114 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11115 if (imm_expr
.X_add_number
< min_range
||
11116 imm_expr
.X_add_number
> max_range
)
11118 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11119 (long) min_range
, (long) max_range
,
11120 (long) imm_expr
.X_add_number
);
11122 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11123 imm_expr
.X_op
= O_absent
;
11127 case '@': /* DSP 10-bit signed immediate in bit 16. */
11129 long mask
= (mips_opts
.micromips
11130 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11132 my_getExpression (&imm_expr
, s
);
11133 check_absolute_expr (ip
, &imm_expr
);
11134 min_range
= -((mask
+ 1) >> 1);
11135 max_range
= ((mask
+ 1) >> 1) - 1;
11136 if (imm_expr
.X_add_number
< min_range
11137 || imm_expr
.X_add_number
> max_range
)
11138 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11139 (long) min_range
, (long) max_range
,
11140 (long) imm_expr
.X_add_number
);
11141 INSERT_OPERAND (mips_opts
.micromips
,
11142 IMM10
, *ip
, imm_expr
.X_add_number
);
11143 imm_expr
.X_op
= O_absent
;
11148 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11149 gas_assert (mips_opts
.micromips
);
11150 my_getExpression (&imm_expr
, s
);
11151 check_absolute_expr (ip
, &imm_expr
);
11152 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11153 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11154 MICROMIPSOP_MASK_RD
,
11155 (unsigned long) imm_expr
.X_add_number
);
11156 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11157 imm_expr
.X_op
= O_absent
;
11161 case '!': /* MT usermode flag bit. */
11162 gas_assert (!mips_opts
.micromips
);
11163 my_getExpression (&imm_expr
, s
);
11164 check_absolute_expr (ip
, &imm_expr
);
11165 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11166 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11167 (unsigned long) imm_expr
.X_add_number
);
11168 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11169 imm_expr
.X_op
= O_absent
;
11173 case '$': /* MT load high flag bit. */
11174 gas_assert (!mips_opts
.micromips
);
11175 my_getExpression (&imm_expr
, s
);
11176 check_absolute_expr (ip
, &imm_expr
);
11177 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11178 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11179 (unsigned long) imm_expr
.X_add_number
);
11180 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11181 imm_expr
.X_op
= O_absent
;
11185 case '*': /* Four DSP accumulators in bits 18,19. */
11186 gas_assert (!mips_opts
.micromips
);
11187 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11188 s
[3] >= '0' && s
[3] <= '3')
11190 regno
= s
[3] - '0';
11192 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11196 as_bad (_("Invalid dsp/smartmips acc register"));
11199 case '&': /* Four DSP accumulators in bits 13,14. */
11200 gas_assert (!mips_opts
.micromips
);
11201 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11202 s
[3] >= '0' && s
[3] <= '3')
11204 regno
= s
[3] - '0';
11206 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11210 as_bad (_("Invalid dsp/smartmips acc register"));
11213 case '\\': /* 3-bit bit position. */
11215 unsigned long mask
= (mips_opts
.micromips
11216 ? MICROMIPSOP_MASK_3BITPOS
11217 : OP_MASK_3BITPOS
);
11219 my_getExpression (&imm_expr
, s
);
11220 check_absolute_expr (ip
, &imm_expr
);
11221 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11222 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11224 mask
, (unsigned long) imm_expr
.X_add_number
);
11225 INSERT_OPERAND (mips_opts
.micromips
,
11226 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11227 imm_expr
.X_op
= O_absent
;
11241 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11245 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11249 gas_assert (!mips_opts
.micromips
);
11250 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11254 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11260 /* Handle optional base register.
11261 Either the base register is omitted or
11262 we must have a left paren. */
11263 /* This is dependent on the next operand specifier
11264 is a base register specification. */
11265 gas_assert (args
[1] == 'b'
11266 || (mips_opts
.micromips
11268 && (args
[2] == 'l' || args
[2] == 'n'
11269 || args
[2] == 's' || args
[2] == 'a')));
11270 if (*s
== '\0' && args
[1] == 'b')
11272 /* Fall through. */
11274 case ')': /* These must match exactly. */
11279 case '[': /* These must match exactly. */
11281 gas_assert (!mips_opts
.micromips
);
11286 case '+': /* Opcode extension character. */
11289 case '1': /* UDI immediates. */
11293 gas_assert (!mips_opts
.micromips
);
11295 const struct mips_immed
*imm
= mips_immed
;
11297 while (imm
->type
&& imm
->type
!= *args
)
11301 my_getExpression (&imm_expr
, s
);
11302 check_absolute_expr (ip
, &imm_expr
);
11303 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11305 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11306 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11307 (unsigned long) imm_expr
.X_add_number
,
11308 (unsigned long) imm_expr
.X_add_number
);
11309 imm_expr
.X_add_number
&= imm
->mask
;
11311 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11313 imm_expr
.X_op
= O_absent
;
11318 case 'A': /* ins/ext position, becomes LSB. */
11327 my_getExpression (&imm_expr
, s
);
11328 check_absolute_expr (ip
, &imm_expr
);
11329 if ((unsigned long) imm_expr
.X_add_number
< limlo
11330 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11332 as_bad (_("Improper position (%lu)"),
11333 (unsigned long) imm_expr
.X_add_number
);
11334 imm_expr
.X_add_number
= limlo
;
11336 lastpos
= imm_expr
.X_add_number
;
11337 INSERT_OPERAND (mips_opts
.micromips
,
11338 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11339 imm_expr
.X_op
= O_absent
;
11343 case 'B': /* ins size, becomes MSB. */
11352 my_getExpression (&imm_expr
, s
);
11353 check_absolute_expr (ip
, &imm_expr
);
11354 /* Check for negative input so that small negative numbers
11355 will not succeed incorrectly. The checks against
11356 (pos+size) transitively check "size" itself,
11357 assuming that "pos" is reasonable. */
11358 if ((long) imm_expr
.X_add_number
< 0
11359 || ((unsigned long) imm_expr
.X_add_number
11361 || ((unsigned long) imm_expr
.X_add_number
11362 + lastpos
) > limhi
)
11364 as_bad (_("Improper insert size (%lu, position %lu)"),
11365 (unsigned long) imm_expr
.X_add_number
,
11366 (unsigned long) lastpos
);
11367 imm_expr
.X_add_number
= limlo
- lastpos
;
11369 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11370 lastpos
+ imm_expr
.X_add_number
- 1);
11371 imm_expr
.X_op
= O_absent
;
11375 case 'C': /* ext size, becomes MSBD. */
11388 my_getExpression (&imm_expr
, s
);
11389 check_absolute_expr (ip
, &imm_expr
);
11390 /* Check for negative input so that small negative numbers
11391 will not succeed incorrectly. The checks against
11392 (pos+size) transitively check "size" itself,
11393 assuming that "pos" is reasonable. */
11394 if ((long) imm_expr
.X_add_number
< 0
11395 || ((unsigned long) imm_expr
.X_add_number
11397 || ((unsigned long) imm_expr
.X_add_number
11398 + lastpos
) > limhi
)
11400 as_bad (_("Improper extract size (%lu, position %lu)"),
11401 (unsigned long) imm_expr
.X_add_number
,
11402 (unsigned long) lastpos
);
11403 imm_expr
.X_add_number
= limlo
- lastpos
;
11405 INSERT_OPERAND (mips_opts
.micromips
,
11406 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11407 imm_expr
.X_op
= O_absent
;
11412 /* +D is for disassembly only; never match. */
11416 /* "+I" is like "I", except that imm2_expr is used. */
11417 my_getExpression (&imm2_expr
, s
);
11418 if (imm2_expr
.X_op
!= O_big
11419 && imm2_expr
.X_op
!= O_constant
)
11420 insn_error
= _("absolute expression required");
11421 if (HAVE_32BIT_GPRS
)
11422 normalize_constant_expr (&imm2_expr
);
11426 case 'T': /* Coprocessor register. */
11427 gas_assert (!mips_opts
.micromips
);
11428 /* +T is for disassembly only; never match. */
11431 case 't': /* Coprocessor register number. */
11432 gas_assert (!mips_opts
.micromips
);
11433 if (s
[0] == '$' && ISDIGIT (s
[1]))
11443 while (ISDIGIT (*s
));
11445 as_bad (_("Invalid register number (%d)"), regno
);
11448 INSERT_OPERAND (0, RT
, *ip
, regno
);
11453 as_bad (_("Invalid coprocessor 0 register number"));
11457 /* bbit[01] and bbit[01]32 bit index. Give error if index
11458 is not in the valid range. */
11459 gas_assert (!mips_opts
.micromips
);
11460 my_getExpression (&imm_expr
, s
);
11461 check_absolute_expr (ip
, &imm_expr
);
11462 if ((unsigned) imm_expr
.X_add_number
> 31)
11464 as_bad (_("Improper bit index (%lu)"),
11465 (unsigned long) imm_expr
.X_add_number
);
11466 imm_expr
.X_add_number
= 0;
11468 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11469 imm_expr
.X_op
= O_absent
;
11474 /* bbit[01] bit index when bbit is used but we generate
11475 bbit[01]32 because the index is over 32. Move to the
11476 next candidate if index is not in the valid range. */
11477 gas_assert (!mips_opts
.micromips
);
11478 my_getExpression (&imm_expr
, s
);
11479 check_absolute_expr (ip
, &imm_expr
);
11480 if ((unsigned) imm_expr
.X_add_number
< 32
11481 || (unsigned) imm_expr
.X_add_number
> 63)
11483 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11484 imm_expr
.X_op
= O_absent
;
11489 /* cins, cins32, exts and exts32 position field. Give error
11490 if it's not in the valid range. */
11491 gas_assert (!mips_opts
.micromips
);
11492 my_getExpression (&imm_expr
, s
);
11493 check_absolute_expr (ip
, &imm_expr
);
11494 if ((unsigned) imm_expr
.X_add_number
> 31)
11496 as_bad (_("Improper position (%lu)"),
11497 (unsigned long) imm_expr
.X_add_number
);
11498 imm_expr
.X_add_number
= 0;
11500 /* Make the pos explicit to simplify +S. */
11501 lastpos
= imm_expr
.X_add_number
+ 32;
11502 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11503 imm_expr
.X_op
= O_absent
;
11508 /* cins, cins32, exts and exts32 position field. Move to
11509 the next candidate if it's not in the valid range. */
11510 gas_assert (!mips_opts
.micromips
);
11511 my_getExpression (&imm_expr
, s
);
11512 check_absolute_expr (ip
, &imm_expr
);
11513 if ((unsigned) imm_expr
.X_add_number
< 32
11514 || (unsigned) imm_expr
.X_add_number
> 63)
11516 lastpos
= imm_expr
.X_add_number
;
11517 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11518 imm_expr
.X_op
= O_absent
;
11523 /* cins and exts length-minus-one field. */
11524 gas_assert (!mips_opts
.micromips
);
11525 my_getExpression (&imm_expr
, s
);
11526 check_absolute_expr (ip
, &imm_expr
);
11527 if ((unsigned long) imm_expr
.X_add_number
> 31)
11529 as_bad (_("Improper size (%lu)"),
11530 (unsigned long) imm_expr
.X_add_number
);
11531 imm_expr
.X_add_number
= 0;
11533 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11534 imm_expr
.X_op
= O_absent
;
11539 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11540 length-minus-one field. */
11541 gas_assert (!mips_opts
.micromips
);
11542 my_getExpression (&imm_expr
, s
);
11543 check_absolute_expr (ip
, &imm_expr
);
11544 if ((long) imm_expr
.X_add_number
< 0
11545 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11547 as_bad (_("Improper size (%lu)"),
11548 (unsigned long) imm_expr
.X_add_number
);
11549 imm_expr
.X_add_number
= 0;
11551 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11552 imm_expr
.X_op
= O_absent
;
11557 /* seqi/snei immediate field. */
11558 gas_assert (!mips_opts
.micromips
);
11559 my_getExpression (&imm_expr
, s
);
11560 check_absolute_expr (ip
, &imm_expr
);
11561 if ((long) imm_expr
.X_add_number
< -512
11562 || (long) imm_expr
.X_add_number
>= 512)
11564 as_bad (_("Improper immediate (%ld)"),
11565 (long) imm_expr
.X_add_number
);
11566 imm_expr
.X_add_number
= 0;
11568 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11569 imm_expr
.X_op
= O_absent
;
11573 case 'a': /* 8-bit signed offset in bit 6 */
11574 gas_assert (!mips_opts
.micromips
);
11575 my_getExpression (&imm_expr
, s
);
11576 check_absolute_expr (ip
, &imm_expr
);
11577 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11578 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11579 if (imm_expr
.X_add_number
< min_range
11580 || imm_expr
.X_add_number
> max_range
)
11582 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11583 (long) min_range
, (long) max_range
,
11584 (long) imm_expr
.X_add_number
);
11586 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11587 imm_expr
.X_op
= O_absent
;
11591 case 'b': /* 8-bit signed offset in bit 3 */
11592 gas_assert (!mips_opts
.micromips
);
11593 my_getExpression (&imm_expr
, s
);
11594 check_absolute_expr (ip
, &imm_expr
);
11595 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11596 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11597 if (imm_expr
.X_add_number
< min_range
11598 || imm_expr
.X_add_number
> max_range
)
11600 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11601 (long) min_range
, (long) max_range
,
11602 (long) imm_expr
.X_add_number
);
11604 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11605 imm_expr
.X_op
= O_absent
;
11609 case 'c': /* 9-bit signed offset in bit 6 */
11610 gas_assert (!mips_opts
.micromips
);
11611 my_getExpression (&imm_expr
, s
);
11612 check_absolute_expr (ip
, &imm_expr
);
11613 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11614 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11615 /* We check the offset range before adjusted. */
11618 if (imm_expr
.X_add_number
< min_range
11619 || imm_expr
.X_add_number
> max_range
)
11621 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11622 (long) min_range
, (long) max_range
,
11623 (long) imm_expr
.X_add_number
);
11625 if (imm_expr
.X_add_number
& 0xf)
11627 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11628 (long) imm_expr
.X_add_number
);
11630 /* Right shift 4 bits to adjust the offset operand. */
11631 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11632 imm_expr
.X_add_number
>> 4);
11633 imm_expr
.X_op
= O_absent
;
11638 gas_assert (!mips_opts
.micromips
);
11639 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11641 if (regno
== AT
&& mips_opts
.at
)
11643 if (mips_opts
.at
== ATREG
)
11644 as_warn (_("used $at without \".set noat\""));
11646 as_warn (_("used $%u with \".set at=$%u\""),
11647 regno
, mips_opts
.at
);
11649 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11653 gas_assert (!mips_opts
.micromips
);
11654 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11656 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11660 as_bad (_("Internal error: bad %s opcode "
11661 "(unknown extension operand type `+%c'): %s %s"),
11662 mips_opts
.micromips
? "microMIPS" : "MIPS",
11663 *args
, insn
->name
, insn
->args
);
11664 /* Further processing is fruitless. */
11669 case '.': /* 10-bit offset. */
11670 gas_assert (mips_opts
.micromips
);
11671 case '~': /* 12-bit offset. */
11673 int shift
= *args
== '.' ? 9 : 11;
11676 /* Check whether there is only a single bracketed expression
11677 left. If so, it must be the base register and the
11678 constant must be zero. */
11679 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11682 /* If this value won't fit into the offset, then go find
11683 a macro that will generate a 16- or 32-bit offset code
11685 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11686 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11687 || imm_expr
.X_add_number
>= 1 << shift
11688 || imm_expr
.X_add_number
< -1 << shift
))
11691 imm_expr
.X_op
= O_absent
;
11695 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11697 INSERT_OPERAND (mips_opts
.micromips
,
11698 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11699 imm_expr
.X_op
= O_absent
;
11704 case '<': /* must be at least one digit */
11706 * According to the manual, if the shift amount is greater
11707 * than 31 or less than 0, then the shift amount should be
11708 * mod 32. In reality the mips assembler issues an error.
11709 * We issue a warning and mask out all but the low 5 bits.
11711 my_getExpression (&imm_expr
, s
);
11712 check_absolute_expr (ip
, &imm_expr
);
11713 if ((unsigned long) imm_expr
.X_add_number
> 31)
11714 as_warn (_("Improper shift amount (%lu)"),
11715 (unsigned long) imm_expr
.X_add_number
);
11716 INSERT_OPERAND (mips_opts
.micromips
,
11717 SHAMT
, *ip
, imm_expr
.X_add_number
);
11718 imm_expr
.X_op
= O_absent
;
11722 case '>': /* shift amount minus 32 */
11723 my_getExpression (&imm_expr
, s
);
11724 check_absolute_expr (ip
, &imm_expr
);
11725 if ((unsigned long) imm_expr
.X_add_number
< 32
11726 || (unsigned long) imm_expr
.X_add_number
> 63)
11728 INSERT_OPERAND (mips_opts
.micromips
,
11729 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11730 imm_expr
.X_op
= O_absent
;
11734 case 'k': /* CACHE code. */
11735 case 'h': /* PREFX code. */
11736 case '1': /* SYNC type. */
11737 my_getExpression (&imm_expr
, s
);
11738 check_absolute_expr (ip
, &imm_expr
);
11739 if ((unsigned long) imm_expr
.X_add_number
> 31)
11740 as_warn (_("Invalid value for `%s' (%lu)"),
11742 (unsigned long) imm_expr
.X_add_number
);
11746 if (mips_fix_cn63xxp1
11747 && !mips_opts
.micromips
11748 && strcmp ("pref", insn
->name
) == 0)
11749 switch (imm_expr
.X_add_number
)
11758 case 31: /* These are ok. */
11761 default: /* The rest must be changed to 28. */
11762 imm_expr
.X_add_number
= 28;
11765 INSERT_OPERAND (mips_opts
.micromips
,
11766 CACHE
, *ip
, imm_expr
.X_add_number
);
11769 INSERT_OPERAND (mips_opts
.micromips
,
11770 PREFX
, *ip
, imm_expr
.X_add_number
);
11773 INSERT_OPERAND (mips_opts
.micromips
,
11774 STYPE
, *ip
, imm_expr
.X_add_number
);
11777 imm_expr
.X_op
= O_absent
;
11781 case 'c': /* BREAK code. */
11783 unsigned long mask
= (mips_opts
.micromips
11784 ? MICROMIPSOP_MASK_CODE
11787 my_getExpression (&imm_expr
, s
);
11788 check_absolute_expr (ip
, &imm_expr
);
11789 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11790 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11792 mask
, (unsigned long) imm_expr
.X_add_number
);
11793 INSERT_OPERAND (mips_opts
.micromips
,
11794 CODE
, *ip
, imm_expr
.X_add_number
);
11795 imm_expr
.X_op
= O_absent
;
11800 case 'q': /* Lower BREAK code. */
11802 unsigned long mask
= (mips_opts
.micromips
11803 ? MICROMIPSOP_MASK_CODE2
11806 my_getExpression (&imm_expr
, s
);
11807 check_absolute_expr (ip
, &imm_expr
);
11808 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11809 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11811 mask
, (unsigned long) imm_expr
.X_add_number
);
11812 INSERT_OPERAND (mips_opts
.micromips
,
11813 CODE2
, *ip
, imm_expr
.X_add_number
);
11814 imm_expr
.X_op
= O_absent
;
11819 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11821 unsigned long mask
= (mips_opts
.micromips
11822 ? MICROMIPSOP_MASK_CODE10
11825 my_getExpression (&imm_expr
, s
);
11826 check_absolute_expr (ip
, &imm_expr
);
11827 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11828 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11830 mask
, (unsigned long) imm_expr
.X_add_number
);
11831 if (mips_opts
.micromips
)
11832 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
11834 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
11835 imm_expr
.X_op
= O_absent
;
11840 case 'C': /* 25- or 23-bit coprocessor code. */
11842 unsigned long mask
= (mips_opts
.micromips
11843 ? MICROMIPSOP_MASK_COPZ
11846 my_getExpression (&imm_expr
, s
);
11847 check_absolute_expr (ip
, &imm_expr
);
11848 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11849 as_warn (_("Coproccesor code > %u bits (%lu)"),
11850 mips_opts
.micromips
? 23U : 25U,
11851 (unsigned long) imm_expr
.X_add_number
);
11852 INSERT_OPERAND (mips_opts
.micromips
,
11853 COPZ
, *ip
, imm_expr
.X_add_number
);
11854 imm_expr
.X_op
= O_absent
;
11859 case 'J': /* 19-bit WAIT code. */
11860 gas_assert (!mips_opts
.micromips
);
11861 my_getExpression (&imm_expr
, s
);
11862 check_absolute_expr (ip
, &imm_expr
);
11863 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
11865 as_warn (_("Illegal 19-bit code (%lu)"),
11866 (unsigned long) imm_expr
.X_add_number
);
11867 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
11869 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
11870 imm_expr
.X_op
= O_absent
;
11874 case 'P': /* Performance register. */
11875 gas_assert (!mips_opts
.micromips
);
11876 my_getExpression (&imm_expr
, s
);
11877 check_absolute_expr (ip
, &imm_expr
);
11878 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
11879 as_warn (_("Invalid performance register (%lu)"),
11880 (unsigned long) imm_expr
.X_add_number
);
11881 if (imm_expr
.X_add_number
!= 0 && mips_opts
.arch
== CPU_R5900
11882 && (!strcmp(insn
->name
,"mfps") || !strcmp(insn
->name
,"mtps")))
11883 as_warn (_("Invalid performance register (%lu)"),
11884 (unsigned long) imm_expr
.X_add_number
);
11885 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
11886 imm_expr
.X_op
= O_absent
;
11890 case 'G': /* Coprocessor destination register. */
11892 unsigned long opcode
= ip
->insn_opcode
;
11893 unsigned long mask
;
11894 unsigned int types
;
11897 if (mips_opts
.micromips
)
11899 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
11900 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
11901 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
11905 case 0x000000fc: /* mfc0 */
11906 case 0x000002fc: /* mtc0 */
11907 case 0x580000fc: /* dmfc0 */
11908 case 0x580002fc: /* dmtc0 */
11918 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
11919 cop0
= opcode
== OP_OP_COP0
;
11921 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
11922 ok
= reg_lookup (&s
, types
, ®no
);
11923 if (mips_opts
.micromips
)
11924 INSERT_OPERAND (1, RS
, *ip
, regno
);
11926 INSERT_OPERAND (0, RD
, *ip
, regno
);
11935 case 'y': /* ALNV.PS source register. */
11936 gas_assert (mips_opts
.micromips
);
11938 case 'x': /* Ignore register name. */
11939 case 'U': /* Destination register (CLO/CLZ). */
11940 case 'g': /* Coprocessor destination register. */
11941 gas_assert (!mips_opts
.micromips
);
11942 case 'b': /* Base register. */
11943 case 'd': /* Destination register. */
11944 case 's': /* Source register. */
11945 case 't': /* Target register. */
11946 case 'r': /* Both target and source. */
11947 case 'v': /* Both dest and source. */
11948 case 'w': /* Both dest and target. */
11949 case 'E': /* Coprocessor target register. */
11950 case 'K': /* RDHWR destination register. */
11951 case 'z': /* Must be zero register. */
11954 if (*args
== 'E' || *args
== 'K')
11955 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
11958 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
11959 if (regno
== AT
&& mips_opts
.at
)
11961 if (mips_opts
.at
== ATREG
)
11962 as_warn (_("Used $at without \".set noat\""));
11964 as_warn (_("Used $%u with \".set at=$%u\""),
11965 regno
, mips_opts
.at
);
11975 if (c
== 'r' || c
== 'v' || c
== 'w')
11982 /* 'z' only matches $0. */
11983 if (c
== 'z' && regno
!= 0)
11986 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
11988 if (regno
== lastregno
)
11991 = _("Source and destination must be different");
11994 if (regno
== 31 && lastregno
== 0xffffffff)
11997 = _("A destination register must be supplied");
12001 /* Now that we have assembled one operand, we use the args
12002 string to figure out where it goes in the instruction. */
12009 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
12013 if (mips_opts
.micromips
)
12014 INSERT_OPERAND (1, RS
, *ip
, regno
);
12016 INSERT_OPERAND (0, RD
, *ip
, regno
);
12021 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
12025 gas_assert (!mips_opts
.micromips
);
12026 INSERT_OPERAND (0, RD
, *ip
, regno
);
12027 INSERT_OPERAND (0, RT
, *ip
, regno
);
12033 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
12037 gas_assert (mips_opts
.micromips
);
12038 INSERT_OPERAND (1, RS3
, *ip
, regno
);
12042 /* This case exists because on the r3000 trunc
12043 expands into a macro which requires a gp
12044 register. On the r6000 or r4000 it is
12045 assembled into a single instruction which
12046 ignores the register. Thus the insn version
12047 is MIPS_ISA2 and uses 'x', and the macro
12048 version is MIPS_ISA1 and uses 't'. */
12052 /* This case is for the div instruction, which
12053 acts differently if the destination argument
12054 is $0. This only matches $0, and is checked
12055 outside the switch. */
12065 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12069 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12074 case 'O': /* MDMX alignment immediate constant. */
12075 gas_assert (!mips_opts
.micromips
);
12076 my_getExpression (&imm_expr
, s
);
12077 check_absolute_expr (ip
, &imm_expr
);
12078 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
12079 as_warn (_("Improper align amount (%ld), using low bits"),
12080 (long) imm_expr
.X_add_number
);
12081 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
12082 imm_expr
.X_op
= O_absent
;
12086 case 'Q': /* MDMX vector, element sel, or const. */
12089 /* MDMX Immediate. */
12090 gas_assert (!mips_opts
.micromips
);
12091 my_getExpression (&imm_expr
, s
);
12092 check_absolute_expr (ip
, &imm_expr
);
12093 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
12094 as_warn (_("Invalid MDMX Immediate (%ld)"),
12095 (long) imm_expr
.X_add_number
);
12096 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
12097 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12098 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
12100 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
12101 imm_expr
.X_op
= O_absent
;
12105 /* Not MDMX Immediate. Fall through. */
12106 case 'X': /* MDMX destination register. */
12107 case 'Y': /* MDMX source register. */
12108 case 'Z': /* MDMX target register. */
12111 gas_assert (!mips_opts
.micromips
);
12112 case 'D': /* Floating point destination register. */
12113 case 'S': /* Floating point source register. */
12114 case 'T': /* Floating point target register. */
12115 case 'R': /* Floating point source register. */
12119 || (mips_opts
.ase_mdmx
12120 && (ip
->insn_mo
->pinfo
& FP_D
)
12121 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12122 | INSN_COPROC_MEMORY_DELAY
12123 | INSN_LOAD_COPROC_DELAY
12124 | INSN_LOAD_MEMORY_DELAY
12125 | INSN_STORE_MEMORY
))))
12126 rtype
|= RTYPE_VEC
;
12128 if (reg_lookup (&s
, rtype
, ®no
))
12130 if ((regno
& 1) != 0
12132 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12133 as_warn (_("Float register should be even, was %d"),
12141 if (c
== 'V' || c
== 'W')
12152 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12158 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12162 /* This is like 'Z', but also needs to fix the MDMX
12163 vector/scalar select bits. Note that the
12164 scalar immediate case is handled above. */
12167 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12168 int max_el
= (is_qh
? 3 : 7);
12170 my_getExpression(&imm_expr
, s
);
12171 check_absolute_expr (ip
, &imm_expr
);
12173 if (imm_expr
.X_add_number
> max_el
)
12174 as_bad (_("Bad element selector %ld"),
12175 (long) imm_expr
.X_add_number
);
12176 imm_expr
.X_add_number
&= max_el
;
12177 ip
->insn_opcode
|= (imm_expr
.X_add_number
12180 imm_expr
.X_op
= O_absent
;
12182 as_warn (_("Expecting ']' found '%s'"), s
);
12188 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12189 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12192 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12195 /* Fall through. */
12199 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12203 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12213 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12217 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12223 my_getExpression (&imm_expr
, s
);
12224 if (imm_expr
.X_op
!= O_big
12225 && imm_expr
.X_op
!= O_constant
)
12226 insn_error
= _("absolute expression required");
12227 if (HAVE_32BIT_GPRS
)
12228 normalize_constant_expr (&imm_expr
);
12233 my_getExpression (&offset_expr
, s
);
12234 normalize_address_expr (&offset_expr
);
12235 *imm_reloc
= BFD_RELOC_32
;
12248 unsigned char temp
[8];
12250 unsigned int length
;
12255 /* These only appear as the last operand in an
12256 instruction, and every instruction that accepts
12257 them in any variant accepts them in all variants.
12258 This means we don't have to worry about backing out
12259 any changes if the instruction does not match.
12261 The difference between them is the size of the
12262 floating point constant and where it goes. For 'F'
12263 and 'L' the constant is 64 bits; for 'f' and 'l' it
12264 is 32 bits. Where the constant is placed is based
12265 on how the MIPS assembler does things:
12268 f -- immediate value
12271 The .lit4 and .lit8 sections are only used if
12272 permitted by the -G argument.
12274 The code below needs to know whether the target register
12275 is 32 or 64 bits wide. It relies on the fact 'f' and
12276 'F' are used with GPR-based instructions and 'l' and
12277 'L' are used with FPR-based instructions. */
12279 f64
= *args
== 'F' || *args
== 'L';
12280 using_gprs
= *args
== 'F' || *args
== 'f';
12282 save_in
= input_line_pointer
;
12283 input_line_pointer
= s
;
12284 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12286 s
= input_line_pointer
;
12287 input_line_pointer
= save_in
;
12288 if (err
!= NULL
&& *err
!= '\0')
12290 as_bad (_("Bad floating point constant: %s"), err
);
12291 memset (temp
, '\0', sizeof temp
);
12292 length
= f64
? 8 : 4;
12295 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12299 && (g_switch_value
< 4
12300 || (temp
[0] == 0 && temp
[1] == 0)
12301 || (temp
[2] == 0 && temp
[3] == 0))))
12303 imm_expr
.X_op
= O_constant
;
12304 if (!target_big_endian
)
12305 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12307 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12309 else if (length
> 4
12310 && !mips_disable_float_construction
12311 /* Constants can only be constructed in GPRs and
12312 copied to FPRs if the GPRs are at least as wide
12313 as the FPRs. Force the constant into memory if
12314 we are using 64-bit FPRs but the GPRs are only
12317 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12318 && ((temp
[0] == 0 && temp
[1] == 0)
12319 || (temp
[2] == 0 && temp
[3] == 0))
12320 && ((temp
[4] == 0 && temp
[5] == 0)
12321 || (temp
[6] == 0 && temp
[7] == 0)))
12323 /* The value is simple enough to load with a couple of
12324 instructions. If using 32-bit registers, set
12325 imm_expr to the high order 32 bits and offset_expr to
12326 the low order 32 bits. Otherwise, set imm_expr to
12327 the entire 64 bit constant. */
12328 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12330 imm_expr
.X_op
= O_constant
;
12331 offset_expr
.X_op
= O_constant
;
12332 if (!target_big_endian
)
12334 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12335 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12339 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12340 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12342 if (offset_expr
.X_add_number
== 0)
12343 offset_expr
.X_op
= O_absent
;
12345 else if (sizeof (imm_expr
.X_add_number
) > 4)
12347 imm_expr
.X_op
= O_constant
;
12348 if (!target_big_endian
)
12349 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12351 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12355 imm_expr
.X_op
= O_big
;
12356 imm_expr
.X_add_number
= 4;
12357 if (!target_big_endian
)
12359 generic_bignum
[0] = bfd_getl16 (temp
);
12360 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12361 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12362 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12366 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12367 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12368 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12369 generic_bignum
[3] = bfd_getb16 (temp
);
12375 const char *newname
;
12378 /* Switch to the right section. */
12380 subseg
= now_subseg
;
12383 default: /* unused default case avoids warnings. */
12385 newname
= RDATA_SECTION_NAME
;
12386 if (g_switch_value
>= 8)
12390 newname
= RDATA_SECTION_NAME
;
12393 gas_assert (g_switch_value
>= 4);
12397 new_seg
= subseg_new (newname
, (subsegT
) 0);
12399 bfd_set_section_flags (stdoutput
, new_seg
,
12404 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12405 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12406 record_alignment (new_seg
, 4);
12408 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12409 if (seg
== now_seg
)
12410 as_bad (_("Can't use floating point insn in this section"));
12412 /* Set the argument to the current address in the
12414 offset_expr
.X_op
= O_symbol
;
12415 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12416 offset_expr
.X_add_number
= 0;
12418 /* Put the floating point number into the section. */
12419 p
= frag_more ((int) length
);
12420 memcpy (p
, temp
, length
);
12422 /* Switch back to the original section. */
12423 subseg_set (seg
, subseg
);
12428 case 'i': /* 16-bit unsigned immediate. */
12429 case 'j': /* 16-bit signed immediate. */
12430 *imm_reloc
= BFD_RELOC_LO16
;
12431 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12434 offsetT minval
, maxval
;
12436 more
= (insn
+ 1 < past
12437 && strcmp (insn
->name
, insn
[1].name
) == 0);
12439 /* If the expression was written as an unsigned number,
12440 only treat it as signed if there are no more
12444 && sizeof (imm_expr
.X_add_number
) <= 4
12445 && imm_expr
.X_op
== O_constant
12446 && imm_expr
.X_add_number
< 0
12447 && imm_expr
.X_unsigned
12448 && HAVE_64BIT_GPRS
)
12451 /* For compatibility with older assemblers, we accept
12452 0x8000-0xffff as signed 16-bit numbers when only
12453 signed numbers are allowed. */
12455 minval
= 0, maxval
= 0xffff;
12457 minval
= -0x8000, maxval
= 0x7fff;
12459 minval
= -0x8000, maxval
= 0xffff;
12461 if (imm_expr
.X_op
!= O_constant
12462 || imm_expr
.X_add_number
< minval
12463 || imm_expr
.X_add_number
> maxval
)
12467 if (imm_expr
.X_op
== O_constant
12468 || imm_expr
.X_op
== O_big
)
12469 as_bad (_("Expression out of range"));
12475 case 'o': /* 16-bit offset. */
12476 offset_reloc
[0] = BFD_RELOC_LO16
;
12477 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12478 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12480 /* Check whether there is only a single bracketed expression
12481 left. If so, it must be the base register and the
12482 constant must be zero. */
12483 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12485 offset_expr
.X_op
= O_constant
;
12486 offset_expr
.X_add_number
= 0;
12490 /* If this value won't fit into a 16 bit offset, then go
12491 find a macro that will generate the 32 bit offset
12493 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12494 && (offset_expr
.X_op
!= O_constant
12495 || offset_expr
.X_add_number
>= 0x8000
12496 || offset_expr
.X_add_number
< -0x8000))
12502 case 'p': /* PC-relative offset. */
12503 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12504 my_getExpression (&offset_expr
, s
);
12508 case 'u': /* Upper 16 bits. */
12509 *imm_reloc
= BFD_RELOC_LO16
;
12510 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12511 && imm_expr
.X_op
== O_constant
12512 && (imm_expr
.X_add_number
< 0
12513 || imm_expr
.X_add_number
>= 0x10000))
12514 as_bad (_("lui expression (%lu) not in range 0..65535"),
12515 (unsigned long) imm_expr
.X_add_number
);
12519 case 'a': /* 26-bit address. */
12520 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12521 my_getExpression (&offset_expr
, s
);
12525 case 'N': /* 3-bit branch condition code. */
12526 case 'M': /* 3-bit compare condition code. */
12528 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12529 rtype
|= RTYPE_FCC
;
12530 if (!reg_lookup (&s
, rtype
, ®no
))
12532 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12533 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12534 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12535 && (regno
& 1) != 0)
12536 as_warn (_("Condition code register should be even for %s, "
12539 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12540 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12541 && (regno
& 3) != 0)
12542 as_warn (_("Condition code register should be 0 or 4 for %s, "
12546 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12548 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12552 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12563 while (ISDIGIT (*s
));
12566 c
= 8; /* Invalid sel value. */
12569 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12570 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12574 gas_assert (!mips_opts
.micromips
);
12575 /* Must be at least one digit. */
12576 my_getExpression (&imm_expr
, s
);
12577 check_absolute_expr (ip
, &imm_expr
);
12579 if ((unsigned long) imm_expr
.X_add_number
12580 > (unsigned long) OP_MASK_VECBYTE
)
12582 as_bad (_("bad byte vector index (%ld)"),
12583 (long) imm_expr
.X_add_number
);
12584 imm_expr
.X_add_number
= 0;
12587 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12588 imm_expr
.X_op
= O_absent
;
12593 gas_assert (!mips_opts
.micromips
);
12594 my_getExpression (&imm_expr
, s
);
12595 check_absolute_expr (ip
, &imm_expr
);
12597 if ((unsigned long) imm_expr
.X_add_number
12598 > (unsigned long) OP_MASK_VECALIGN
)
12600 as_bad (_("bad byte vector index (%ld)"),
12601 (long) imm_expr
.X_add_number
);
12602 imm_expr
.X_add_number
= 0;
12605 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12606 imm_expr
.X_op
= O_absent
;
12610 case 'm': /* Opcode extension character. */
12611 gas_assert (mips_opts
.micromips
);
12616 if (strncmp (s
, "$pc", 3) == 0)
12644 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12645 if (regno
== AT
&& mips_opts
.at
)
12647 if (mips_opts
.at
== ATREG
)
12648 as_warn (_("Used $at without \".set noat\""));
12650 as_warn (_("Used $%u with \".set at=$%u\""),
12651 regno
, mips_opts
.at
);
12657 gas_assert (args
[1] == ',');
12663 gas_assert (args
[1] == ',');
12665 continue; /* Nothing to do. */
12671 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12673 if (regno
== lastregno
)
12676 = _("Source and destination must be different");
12679 if (regno
== 31 && lastregno
== 0xffffffff)
12682 = _("A destination register must be supplied");
12693 gas_assert (args
[1] == ',');
12700 gas_assert (args
[1] == ',');
12703 continue; /* Nothing to do. */
12707 /* Make sure regno is the same as lastregno. */
12708 if (c
== 't' && regno
!= lastregno
)
12711 /* Make sure regno is the same as destregno. */
12712 if (c
== 'x' && regno
!= destregno
)
12715 /* We need to save regno, before regno maps to the
12716 microMIPS register encoding. */
12726 regno
= ILLEGAL_REG
;
12730 regno
= mips32_to_micromips_reg_b_map
[regno
];
12734 regno
= mips32_to_micromips_reg_c_map
[regno
];
12738 regno
= mips32_to_micromips_reg_d_map
[regno
];
12742 regno
= mips32_to_micromips_reg_e_map
[regno
];
12746 regno
= mips32_to_micromips_reg_f_map
[regno
];
12750 regno
= mips32_to_micromips_reg_g_map
[regno
];
12754 regno
= mips32_to_micromips_reg_h_map
[regno
];
12758 switch (EXTRACT_OPERAND (1, MI
, *ip
))
12763 else if (regno
== 22)
12765 else if (regno
== 5)
12767 else if (regno
== 6)
12769 else if (regno
== 7)
12772 regno
= ILLEGAL_REG
;
12778 else if (regno
== 7)
12781 regno
= ILLEGAL_REG
;
12788 regno
= ILLEGAL_REG
;
12792 regno
= ILLEGAL_REG
;
12798 regno
= mips32_to_micromips_reg_l_map
[regno
];
12802 regno
= mips32_to_micromips_reg_m_map
[regno
];
12806 regno
= mips32_to_micromips_reg_n_map
[regno
];
12810 regno
= mips32_to_micromips_reg_q_map
[regno
];
12815 regno
= ILLEGAL_REG
;
12820 regno
= ILLEGAL_REG
;
12825 regno
= ILLEGAL_REG
;
12828 case 'j': /* Do nothing. */
12838 if (regno
== ILLEGAL_REG
)
12844 INSERT_OPERAND (1, MB
, *ip
, regno
);
12848 INSERT_OPERAND (1, MC
, *ip
, regno
);
12852 INSERT_OPERAND (1, MD
, *ip
, regno
);
12856 INSERT_OPERAND (1, ME
, *ip
, regno
);
12860 INSERT_OPERAND (1, MF
, *ip
, regno
);
12864 INSERT_OPERAND (1, MG
, *ip
, regno
);
12868 INSERT_OPERAND (1, MH
, *ip
, regno
);
12872 INSERT_OPERAND (1, MI
, *ip
, regno
);
12876 INSERT_OPERAND (1, MJ
, *ip
, regno
);
12880 INSERT_OPERAND (1, ML
, *ip
, regno
);
12884 INSERT_OPERAND (1, MM
, *ip
, regno
);
12888 INSERT_OPERAND (1, MN
, *ip
, regno
);
12892 INSERT_OPERAND (1, MP
, *ip
, regno
);
12896 INSERT_OPERAND (1, MQ
, *ip
, regno
);
12899 case 'a': /* Do nothing. */
12900 case 's': /* Do nothing. */
12901 case 't': /* Do nothing. */
12902 case 'x': /* Do nothing. */
12903 case 'y': /* Do nothing. */
12904 case 'z': /* Do nothing. */
12914 bfd_reloc_code_real_type r
[3];
12918 /* Check whether there is only a single bracketed
12919 expression left. If so, it must be the base register
12920 and the constant must be zero. */
12921 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12923 INSERT_OPERAND (1, IMMA
, *ip
, 0);
12927 if (my_getSmallExpression (&ep
, r
, s
) > 0
12928 || !expr_const_in_range (&ep
, -64, 64, 2))
12931 imm
= ep
.X_add_number
>> 2;
12932 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
12939 bfd_reloc_code_real_type r
[3];
12943 if (my_getSmallExpression (&ep
, r
, s
) > 0
12944 || ep
.X_op
!= O_constant
)
12947 for (imm
= 0; imm
< 8; imm
++)
12948 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
12953 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
12960 bfd_reloc_code_real_type r
[3];
12964 if (my_getSmallExpression (&ep
, r
, s
) > 0
12965 || ep
.X_op
!= O_constant
)
12968 for (imm
= 0; imm
< 16; imm
++)
12969 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
12974 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
12979 case 'D': /* pc relative offset */
12980 case 'E': /* pc relative offset */
12981 my_getExpression (&offset_expr
, s
);
12982 if (offset_expr
.X_op
== O_register
)
12985 if (!forced_insn_length
)
12986 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12988 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12990 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12996 bfd_reloc_code_real_type r
[3];
13000 if (my_getSmallExpression (&ep
, r
, s
) > 0
13001 || !expr_const_in_range (&ep
, 0, 16, 0))
13004 imm
= ep
.X_add_number
;
13005 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
13012 bfd_reloc_code_real_type r
[3];
13016 /* Check whether there is only a single bracketed
13017 expression left. If so, it must be the base register
13018 and the constant must be zero. */
13019 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13021 INSERT_OPERAND (1, IMMG
, *ip
, 0);
13025 if (my_getSmallExpression (&ep
, r
, s
) > 0
13026 || !expr_const_in_range (&ep
, -1, 15, 0))
13029 imm
= ep
.X_add_number
& 15;
13030 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
13037 bfd_reloc_code_real_type r
[3];
13041 /* Check whether there is only a single bracketed
13042 expression left. If so, it must be the base register
13043 and the constant must be zero. */
13044 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13046 INSERT_OPERAND (1, IMMH
, *ip
, 0);
13050 if (my_getSmallExpression (&ep
, r
, s
) > 0
13051 || !expr_const_in_range (&ep
, 0, 16, 1))
13054 imm
= ep
.X_add_number
>> 1;
13055 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
13062 bfd_reloc_code_real_type r
[3];
13066 if (my_getSmallExpression (&ep
, r
, s
) > 0
13067 || !expr_const_in_range (&ep
, -1, 127, 0))
13070 imm
= ep
.X_add_number
& 127;
13071 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
13078 bfd_reloc_code_real_type r
[3];
13082 /* Check whether there is only a single bracketed
13083 expression left. If so, it must be the base register
13084 and the constant must be zero. */
13085 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13087 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
13091 if (my_getSmallExpression (&ep
, r
, s
) > 0
13092 || !expr_const_in_range (&ep
, 0, 16, 2))
13095 imm
= ep
.X_add_number
>> 2;
13096 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
13103 bfd_reloc_code_real_type r
[3];
13107 /* Check whether there is only a single bracketed
13108 expression left. If so, it must be the base register
13109 and the constant must be zero. */
13110 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13112 INSERT_OPERAND (1, IMML
, *ip
, 0);
13116 if (my_getSmallExpression (&ep
, r
, s
) > 0
13117 || !expr_const_in_range (&ep
, 0, 16, 0))
13120 imm
= ep
.X_add_number
;
13121 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13128 bfd_reloc_code_real_type r
[3];
13132 if (my_getSmallExpression (&ep
, r
, s
) > 0
13133 || !expr_const_in_range (&ep
, 1, 9, 0))
13136 imm
= ep
.X_add_number
& 7;
13137 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13142 case 'N': /* Register list for lwm and swm. */
13144 /* A comma-separated list of registers and/or
13145 dash-separated contiguous ranges including
13146 both ra and a set of one or more registers
13147 starting at s0 up to s3 which have to be
13154 and any permutations of these. */
13155 unsigned int reglist
;
13158 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13161 if ((reglist
& 0xfff1ffff) != 0x80010000)
13164 reglist
= (reglist
>> 17) & 7;
13166 if ((reglist
& -reglist
) != reglist
)
13169 imm
= ffs (reglist
) - 1;
13170 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13174 case 'O': /* sdbbp 4-bit code. */
13176 bfd_reloc_code_real_type r
[3];
13180 if (my_getSmallExpression (&ep
, r
, s
) > 0
13181 || !expr_const_in_range (&ep
, 0, 16, 0))
13184 imm
= ep
.X_add_number
;
13185 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13192 bfd_reloc_code_real_type r
[3];
13196 if (my_getSmallExpression (&ep
, r
, s
) > 0
13197 || !expr_const_in_range (&ep
, 0, 32, 2))
13200 imm
= ep
.X_add_number
>> 2;
13201 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13208 bfd_reloc_code_real_type r
[3];
13212 if (my_getSmallExpression (&ep
, r
, s
) > 0
13213 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13216 imm
= ep
.X_add_number
>> 2;
13217 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13224 bfd_reloc_code_real_type r
[3];
13228 /* Check whether there is only a single bracketed
13229 expression left. If so, it must be the base register
13230 and the constant must be zero. */
13231 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13233 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13237 if (my_getSmallExpression (&ep
, r
, s
) > 0
13238 || !expr_const_in_range (&ep
, 0, 32, 2))
13241 imm
= ep
.X_add_number
>> 2;
13242 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13249 bfd_reloc_code_real_type r
[3];
13253 if (my_getSmallExpression (&ep
, r
, s
) > 0
13254 || !expr_const_in_range (&ep
, 0, 64, 2))
13257 imm
= ep
.X_add_number
>> 2;
13258 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13265 bfd_reloc_code_real_type r
[3];
13269 if (my_getSmallExpression (&ep
, r
, s
) > 0
13270 || !expr_const_in_range (&ep
, -8, 8, 0))
13273 imm
= ep
.X_add_number
;
13274 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13281 bfd_reloc_code_real_type r
[3];
13285 if (my_getSmallExpression (&ep
, r
, s
) > 0
13286 || expr_const_in_range (&ep
, -2, 2, 2)
13287 || !expr_const_in_range (&ep
, -258, 258, 2))
13290 imm
= ep
.X_add_number
>> 2;
13291 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13292 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13299 bfd_reloc_code_real_type r
[3];
13302 if (my_getSmallExpression (&ep
, r
, s
) > 0
13303 || !expr_const_in_range (&ep
, 0, 1, 0))
13310 as_bad (_("Internal error: bad microMIPS opcode "
13311 "(unknown extension operand type `m%c'): %s %s"),
13312 *args
, insn
->name
, insn
->args
);
13313 /* Further processing is fruitless. */
13318 case 'n': /* Register list for 32-bit lwm and swm. */
13319 gas_assert (mips_opts
.micromips
);
13321 /* A comma-separated list of registers and/or
13322 dash-separated contiguous ranges including
13323 at least one of ra and a set of one or more
13324 registers starting at s0 up to s7 and then
13325 s8 which have to be consecutive, e.g.:
13333 and any permutations of these. */
13334 unsigned int reglist
;
13338 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13341 if ((reglist
& 0x3f00ffff) != 0)
13344 ra
= (reglist
>> 27) & 0x10;
13345 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13347 if ((reglist
& -reglist
) != reglist
)
13350 imm
= (ffs (reglist
) - 1) | ra
;
13351 INSERT_OPERAND (1, RT
, *ip
, imm
);
13352 imm_expr
.X_op
= O_absent
;
13356 case '|': /* 4-bit trap code. */
13357 gas_assert (mips_opts
.micromips
);
13358 my_getExpression (&imm_expr
, s
);
13359 check_absolute_expr (ip
, &imm_expr
);
13360 if ((unsigned long) imm_expr
.X_add_number
13361 > MICROMIPSOP_MASK_TRAP
)
13362 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13363 (unsigned long) imm_expr
.X_add_number
,
13364 ip
->insn_mo
->name
);
13365 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13366 imm_expr
.X_op
= O_absent
;
13371 as_bad (_("Bad char = '%c'\n"), *args
);
13376 /* Args don't match. */
13378 insn_error
= _("Illegal operands");
13379 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13384 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13386 gas_assert (firstinsn
);
13387 need_delay_slot_ok
= FALSE
;
13396 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13398 /* This routine assembles an instruction into its binary format when
13399 assembling for the mips16. As a side effect, it sets one of the
13400 global variables imm_reloc or offset_reloc to the type of relocation
13401 to do if one of the operands is an address expression. It also sets
13402 forced_insn_length to the resulting instruction size in bytes if the
13403 user explicitly requested a small or extended instruction. */
13406 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13410 struct mips_opcode
*insn
;
13412 unsigned int regno
;
13413 unsigned int lastregno
= 0;
13419 forced_insn_length
= 0;
13421 for (s
= str
; ISLOWER (*s
); ++s
)
13433 if (s
[1] == 't' && s
[2] == ' ')
13436 forced_insn_length
= 2;
13440 else if (s
[1] == 'e' && s
[2] == ' ')
13443 forced_insn_length
= 4;
13447 /* Fall through. */
13449 insn_error
= _("unknown opcode");
13453 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13454 forced_insn_length
= 2;
13456 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13458 insn_error
= _("unrecognized opcode");
13467 gas_assert (strcmp (insn
->name
, str
) == 0);
13469 ok
= is_opcode_valid_16 (insn
);
13472 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13473 && strcmp (insn
->name
, insn
[1].name
) == 0)
13482 static char buf
[100];
13484 _("Opcode not supported on this processor: %s (%s)"),
13485 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13486 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13493 create_insn (ip
, insn
);
13494 imm_expr
.X_op
= O_absent
;
13495 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13496 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13497 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13498 imm2_expr
.X_op
= O_absent
;
13499 offset_expr
.X_op
= O_absent
;
13500 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13501 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13502 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13503 for (args
= insn
->args
; 1; ++args
)
13510 /* In this switch statement we call break if we did not find
13511 a match, continue if we did find a match, or return if we
13522 /* Stuff the immediate value in now, if we can. */
13523 if (imm_expr
.X_op
== O_constant
13524 && *imm_reloc
> BFD_RELOC_UNUSED
13525 && insn
->pinfo
!= INSN_MACRO
13526 && calculate_reloc (*offset_reloc
,
13527 imm_expr
.X_add_number
, &value
))
13529 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13530 *offset_reloc
, value
, forced_insn_length
,
13532 imm_expr
.X_op
= O_absent
;
13533 *imm_reloc
= BFD_RELOC_UNUSED
;
13534 *offset_reloc
= BFD_RELOC_UNUSED
;
13548 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13551 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13567 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13569 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13573 /* Fall through. */
13584 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13586 if (c
== 'v' || c
== 'w')
13589 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13591 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13602 if (c
== 'v' || c
== 'w')
13604 regno
= mips16_to_32_reg_map
[lastregno
];
13618 regno
= mips32_to_16_reg_map
[regno
];
13623 regno
= ILLEGAL_REG
;
13628 regno
= ILLEGAL_REG
;
13633 regno
= ILLEGAL_REG
;
13638 if (regno
== AT
&& mips_opts
.at
)
13640 if (mips_opts
.at
== ATREG
)
13641 as_warn (_("used $at without \".set noat\""));
13643 as_warn (_("used $%u with \".set at=$%u\""),
13644 regno
, mips_opts
.at
);
13652 if (regno
== ILLEGAL_REG
)
13659 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13663 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13666 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13669 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13675 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13678 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13679 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13689 if (strncmp (s
, "$pc", 3) == 0)
13706 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13709 if (imm_expr
.X_op
!= O_constant
)
13711 forced_insn_length
= 4;
13712 ip
->insn_opcode
|= MIPS16_EXTEND
;
13716 /* We need to relax this instruction. */
13717 *offset_reloc
= *imm_reloc
;
13718 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13723 *imm_reloc
= BFD_RELOC_UNUSED
;
13724 /* Fall through. */
13731 my_getExpression (&imm_expr
, s
);
13732 if (imm_expr
.X_op
== O_register
)
13734 /* What we thought was an expression turned out to
13737 if (s
[0] == '(' && args
[1] == '(')
13739 /* It looks like the expression was omitted
13740 before a register indirection, which means
13741 that the expression is implicitly zero. We
13742 still set up imm_expr, so that we handle
13743 explicit extensions correctly. */
13744 imm_expr
.X_op
= O_constant
;
13745 imm_expr
.X_add_number
= 0;
13746 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13753 /* We need to relax this instruction. */
13754 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13763 /* We use offset_reloc rather than imm_reloc for the PC
13764 relative operands. This lets macros with both
13765 immediate and address operands work correctly. */
13766 my_getExpression (&offset_expr
, s
);
13768 if (offset_expr
.X_op
== O_register
)
13771 /* We need to relax this instruction. */
13772 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13776 case '6': /* break code */
13777 my_getExpression (&imm_expr
, s
);
13778 check_absolute_expr (ip
, &imm_expr
);
13779 if ((unsigned long) imm_expr
.X_add_number
> 63)
13780 as_warn (_("Invalid value for `%s' (%lu)"),
13782 (unsigned long) imm_expr
.X_add_number
);
13783 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13784 imm_expr
.X_op
= O_absent
;
13788 case 'a': /* 26 bit address */
13789 my_getExpression (&offset_expr
, s
);
13791 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13792 ip
->insn_opcode
<<= 16;
13795 case 'l': /* register list for entry macro */
13796 case 'L': /* register list for exit macro */
13806 unsigned int freg
, reg1
, reg2
;
13808 while (*s
== ' ' || *s
== ',')
13810 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13812 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13816 as_bad (_("can't parse register list"));
13826 if (!reg_lookup (&s
, freg
? RTYPE_FPU
13827 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
13829 as_bad (_("invalid register list"));
13833 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
13835 mask
&= ~ (7 << 3);
13838 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
13840 mask
&= ~ (7 << 3);
13843 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
13844 mask
|= (reg2
- 3) << 3;
13845 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
13846 mask
|= (reg2
- 15) << 1;
13847 else if (reg1
== RA
&& reg2
== RA
)
13851 as_bad (_("invalid register list"));
13855 /* The mask is filled in in the opcode table for the
13856 benefit of the disassembler. We remove it before
13857 applying the actual mask. */
13858 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
13859 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
13863 case 'm': /* Register list for save insn. */
13864 case 'M': /* Register list for restore insn. */
13866 int opcode
= ip
->insn_opcode
;
13867 int framesz
= 0, seen_framesz
= 0;
13868 int nargs
= 0, statics
= 0, sregs
= 0;
13872 unsigned int reg1
, reg2
;
13874 SKIP_SPACE_TABS (s
);
13877 SKIP_SPACE_TABS (s
);
13879 my_getExpression (&imm_expr
, s
);
13880 if (imm_expr
.X_op
== O_constant
)
13882 /* Handle the frame size. */
13885 as_bad (_("more than one frame size in list"));
13889 framesz
= imm_expr
.X_add_number
;
13890 imm_expr
.X_op
= O_absent
;
13895 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13897 as_bad (_("can't parse register list"));
13909 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
13912 as_bad (_("can't parse register list"));
13917 while (reg1
<= reg2
)
13919 if (reg1
>= 4 && reg1
<= 7)
13923 nargs
|= 1 << (reg1
- 4);
13925 /* statics $a0-$a3 */
13926 statics
|= 1 << (reg1
- 4);
13928 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
13931 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
13933 else if (reg1
== 31)
13935 /* Add $ra to insn. */
13940 as_bad (_("unexpected register in list"));
13948 /* Encode args/statics combination. */
13949 if (nargs
& statics
)
13950 as_bad (_("arg/static registers overlap"));
13951 else if (nargs
== 0xf)
13952 /* All $a0-$a3 are args. */
13953 opcode
|= MIPS16_ALL_ARGS
<< 16;
13954 else if (statics
== 0xf)
13955 /* All $a0-$a3 are statics. */
13956 opcode
|= MIPS16_ALL_STATICS
<< 16;
13959 int narg
= 0, nstat
= 0;
13961 /* Count arg registers. */
13962 while (nargs
& 0x1)
13968 as_bad (_("invalid arg register list"));
13970 /* Count static registers. */
13971 while (statics
& 0x8)
13973 statics
= (statics
<< 1) & 0xf;
13977 as_bad (_("invalid static register list"));
13979 /* Encode args/statics. */
13980 opcode
|= ((narg
<< 2) | nstat
) << 16;
13983 /* Encode $s0/$s1. */
13984 if (sregs
& (1 << 0)) /* $s0 */
13986 if (sregs
& (1 << 1)) /* $s1 */
13992 /* Count regs $s2-$s8. */
14000 as_bad (_("invalid static register list"));
14001 /* Encode $s2-$s8. */
14002 opcode
|= nsreg
<< 24;
14005 /* Encode frame size. */
14007 as_bad (_("missing frame size"));
14008 else if ((framesz
& 7) != 0 || framesz
< 0
14009 || framesz
> 0xff * 8)
14010 as_bad (_("invalid frame size"));
14011 else if (framesz
!= 128 || (opcode
>> 16) != 0)
14014 opcode
|= (((framesz
& 0xf0) << 16)
14015 | (framesz
& 0x0f));
14018 /* Finally build the instruction. */
14019 if ((opcode
>> 16) != 0 || framesz
== 0)
14020 opcode
|= MIPS16_EXTEND
;
14021 ip
->insn_opcode
= opcode
;
14025 case 'e': /* extend code */
14026 my_getExpression (&imm_expr
, s
);
14027 check_absolute_expr (ip
, &imm_expr
);
14028 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
14030 as_warn (_("Invalid value for `%s' (%lu)"),
14032 (unsigned long) imm_expr
.X_add_number
);
14033 imm_expr
.X_add_number
&= 0x7ff;
14035 ip
->insn_opcode
|= imm_expr
.X_add_number
;
14036 imm_expr
.X_op
= O_absent
;
14046 /* Args don't match. */
14047 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
14048 strcmp (insn
->name
, insn
[1].name
) == 0)
14055 insn_error
= _("illegal operands");
14061 /* This structure holds information we know about a mips16 immediate
14064 struct mips16_immed_operand
14066 /* The type code used in the argument string in the opcode table. */
14068 /* The number of bits in the short form of the opcode. */
14070 /* The number of bits in the extended form of the opcode. */
14072 /* The amount by which the short form is shifted when it is used;
14073 for example, the sw instruction has a shift count of 2. */
14075 /* The amount by which the short form is shifted when it is stored
14076 into the instruction code. */
14078 /* Non-zero if the short form is unsigned. */
14080 /* Non-zero if the extended form is unsigned. */
14082 /* Non-zero if the value is PC relative. */
14086 /* The mips16 immediate operand types. */
14088 static const struct mips16_immed_operand mips16_immed_operands
[] =
14090 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14091 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14092 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14093 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14094 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
14095 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14096 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14097 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14098 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14099 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
14100 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14101 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14102 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14103 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
14104 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14105 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14106 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14107 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14108 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
14109 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
14110 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
14113 #define MIPS16_NUM_IMMED \
14114 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14116 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14117 NBITS is the number of significant bits in VAL. */
14119 static unsigned long
14120 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14125 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14128 else if (nbits
== 15)
14130 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14135 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14138 return (extval
<< 16) | val
;
14141 /* Install immediate value VAL into MIPS16 instruction *INSN,
14142 extending it if necessary. The instruction in *INSN may
14143 already be extended.
14145 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14146 if none. In the former case, VAL is a 16-bit number with no
14147 defined signedness.
14149 TYPE is the type of the immediate field. USER_INSN_LENGTH
14150 is the length that the user requested, or 0 if none. */
14153 mips16_immed (char *file
, unsigned int line
, int type
,
14154 bfd_reloc_code_real_type reloc
, offsetT val
,
14155 unsigned int user_insn_length
, unsigned long *insn
)
14157 const struct mips16_immed_operand
*op
;
14158 int mintiny
, maxtiny
;
14160 op
= mips16_immed_operands
;
14161 while (op
->type
!= type
)
14164 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14169 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14172 maxtiny
= 1 << op
->nbits
;
14177 maxtiny
= (1 << op
->nbits
) - 1;
14179 if (reloc
!= BFD_RELOC_UNUSED
)
14184 mintiny
= - (1 << (op
->nbits
- 1));
14185 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14186 if (reloc
!= BFD_RELOC_UNUSED
)
14187 val
= SEXT_16BIT (val
);
14190 /* Branch offsets have an implicit 0 in the lowest bit. */
14191 if (type
== 'p' || type
== 'q')
14194 if ((val
& ((1 << op
->shift
) - 1)) != 0
14195 || val
< (mintiny
<< op
->shift
)
14196 || val
> (maxtiny
<< op
->shift
))
14198 /* We need an extended instruction. */
14199 if (user_insn_length
== 2)
14200 as_bad_where (file
, line
, _("invalid unextended operand value"));
14202 *insn
|= MIPS16_EXTEND
;
14204 else if (user_insn_length
== 4)
14206 /* The operand doesn't force an unextended instruction to be extended.
14207 Warn if the user wanted an extended instruction anyway. */
14208 *insn
|= MIPS16_EXTEND
;
14209 as_warn_where (file
, line
,
14210 _("extended operand requested but not required"));
14213 if (mips16_opcode_length (*insn
) == 2)
14217 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14218 insnval
<<= op
->op_shift
;
14223 long minext
, maxext
;
14225 if (reloc
== BFD_RELOC_UNUSED
)
14230 maxext
= (1 << op
->extbits
) - 1;
14234 minext
= - (1 << (op
->extbits
- 1));
14235 maxext
= (1 << (op
->extbits
- 1)) - 1;
14237 if (val
< minext
|| val
> maxext
)
14238 as_bad_where (file
, line
,
14239 _("operand value out of range for instruction"));
14242 *insn
|= mips16_immed_extend (val
, op
->extbits
);
14246 struct percent_op_match
14249 bfd_reloc_code_real_type reloc
;
14252 static const struct percent_op_match mips_percent_op
[] =
14254 {"%lo", BFD_RELOC_LO16
},
14256 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14257 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14258 {"%call16", BFD_RELOC_MIPS_CALL16
},
14259 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14260 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14261 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14262 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14263 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14264 {"%got", BFD_RELOC_MIPS_GOT16
},
14265 {"%gp_rel", BFD_RELOC_GPREL16
},
14266 {"%half", BFD_RELOC_16
},
14267 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14268 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14269 {"%neg", BFD_RELOC_MIPS_SUB
},
14270 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14271 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14272 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14273 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14274 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14275 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14276 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14278 {"%hi", BFD_RELOC_HI16_S
}
14281 static const struct percent_op_match mips16_percent_op
[] =
14283 {"%lo", BFD_RELOC_MIPS16_LO16
},
14284 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14285 {"%got", BFD_RELOC_MIPS16_GOT16
},
14286 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14287 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14288 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14289 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14290 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14291 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14292 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14293 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14294 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14298 /* Return true if *STR points to a relocation operator. When returning true,
14299 move *STR over the operator and store its relocation code in *RELOC.
14300 Leave both *STR and *RELOC alone when returning false. */
14303 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14305 const struct percent_op_match
*percent_op
;
14308 if (mips_opts
.mips16
)
14310 percent_op
= mips16_percent_op
;
14311 limit
= ARRAY_SIZE (mips16_percent_op
);
14315 percent_op
= mips_percent_op
;
14316 limit
= ARRAY_SIZE (mips_percent_op
);
14319 for (i
= 0; i
< limit
; i
++)
14320 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14322 int len
= strlen (percent_op
[i
].str
);
14324 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14327 *str
+= strlen (percent_op
[i
].str
);
14328 *reloc
= percent_op
[i
].reloc
;
14330 /* Check whether the output BFD supports this relocation.
14331 If not, issue an error and fall back on something safe. */
14332 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14334 as_bad (_("relocation %s isn't supported by the current ABI"),
14335 percent_op
[i
].str
);
14336 *reloc
= BFD_RELOC_UNUSED
;
14344 /* Parse string STR as a 16-bit relocatable operand. Store the
14345 expression in *EP and the relocations in the array starting
14346 at RELOC. Return the number of relocation operators used.
14348 On exit, EXPR_END points to the first character after the expression. */
14351 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14354 bfd_reloc_code_real_type reversed_reloc
[3];
14355 size_t reloc_index
, i
;
14356 int crux_depth
, str_depth
;
14359 /* Search for the start of the main expression, recoding relocations
14360 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14361 of the main expression and with CRUX_DEPTH containing the number
14362 of open brackets at that point. */
14369 crux_depth
= str_depth
;
14371 /* Skip over whitespace and brackets, keeping count of the number
14373 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14378 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14379 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14381 my_getExpression (ep
, crux
);
14384 /* Match every open bracket. */
14385 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14389 if (crux_depth
> 0)
14390 as_bad (_("unclosed '('"));
14394 if (reloc_index
!= 0)
14396 prev_reloc_op_frag
= frag_now
;
14397 for (i
= 0; i
< reloc_index
; i
++)
14398 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14401 return reloc_index
;
14405 my_getExpression (expressionS
*ep
, char *str
)
14409 save_in
= input_line_pointer
;
14410 input_line_pointer
= str
;
14412 expr_end
= input_line_pointer
;
14413 input_line_pointer
= save_in
;
14417 md_atof (int type
, char *litP
, int *sizeP
)
14419 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14423 md_number_to_chars (char *buf
, valueT val
, int n
)
14425 if (target_big_endian
)
14426 number_to_chars_bigendian (buf
, val
, n
);
14428 number_to_chars_littleendian (buf
, val
, n
);
14432 static int support_64bit_objects(void)
14434 const char **list
, **l
;
14437 list
= bfd_target_list ();
14438 for (l
= list
; *l
!= NULL
; l
++)
14439 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14440 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14442 yes
= (*l
!= NULL
);
14446 #endif /* OBJ_ELF */
14448 const char *md_shortopts
= "O::g::G:";
14452 OPTION_MARCH
= OPTION_MD_BASE
,
14474 OPTION_NO_SMARTMIPS
,
14478 OPTION_NO_MICROMIPS
,
14481 OPTION_COMPAT_ARCH_BASE
,
14490 OPTION_M7000_HILO_FIX
,
14491 OPTION_MNO_7000_HILO_FIX
,
14494 OPTION_FIX_LOONGSON2F_JUMP
,
14495 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14496 OPTION_FIX_LOONGSON2F_NOP
,
14497 OPTION_NO_FIX_LOONGSON2F_NOP
,
14499 OPTION_NO_FIX_VR4120
,
14501 OPTION_NO_FIX_VR4130
,
14502 OPTION_FIX_CN63XXP1
,
14503 OPTION_NO_FIX_CN63XXP1
,
14510 OPTION_CONSTRUCT_FLOATS
,
14511 OPTION_NO_CONSTRUCT_FLOATS
,
14514 OPTION_RELAX_BRANCH
,
14515 OPTION_NO_RELAX_BRANCH
,
14522 OPTION_SINGLE_FLOAT
,
14523 OPTION_DOUBLE_FLOAT
,
14526 OPTION_CALL_SHARED
,
14527 OPTION_CALL_NONPIC
,
14537 OPTION_MVXWORKS_PIC
,
14538 #endif /* OBJ_ELF */
14542 struct option md_longopts
[] =
14544 /* Options which specify architecture. */
14545 {"march", required_argument
, NULL
, OPTION_MARCH
},
14546 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14547 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14548 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14549 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14550 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14551 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14552 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14553 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14554 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14555 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14556 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14558 /* Options which specify Application Specific Extensions (ASEs). */
14559 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14560 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14561 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14562 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14563 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14564 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14565 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14566 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14567 {"mmt", no_argument
, NULL
, OPTION_MT
},
14568 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14569 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14570 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14571 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14572 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14573 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14574 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14575 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
14576 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
14578 /* Old-style architecture options. Don't add more of these. */
14579 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14580 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14581 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14582 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14583 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14584 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14585 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14586 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14588 /* Options which enable bug fixes. */
14589 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14590 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14591 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14592 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14593 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14594 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14595 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14596 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14597 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14598 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14599 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14600 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14601 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14602 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14603 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14605 /* Miscellaneous options. */
14606 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14607 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14608 {"break", no_argument
, NULL
, OPTION_BREAK
},
14609 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14610 {"EB", no_argument
, NULL
, OPTION_EB
},
14611 {"EL", no_argument
, NULL
, OPTION_EL
},
14612 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14613 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14614 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14615 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14616 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14617 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14618 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14619 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14620 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14621 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14622 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14623 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14624 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14625 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14626 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14627 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14629 /* Strictly speaking this next option is ELF specific,
14630 but we allow it for other ports as well in order to
14631 make testing easier. */
14632 {"32", no_argument
, NULL
, OPTION_32
},
14634 /* ELF-specific options. */
14636 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14637 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14638 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14639 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14640 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14641 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14642 {"n32", no_argument
, NULL
, OPTION_N32
},
14643 {"64", no_argument
, NULL
, OPTION_64
},
14644 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14645 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14646 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14647 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14648 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14649 #endif /* OBJ_ELF */
14651 {NULL
, no_argument
, NULL
, 0}
14653 size_t md_longopts_size
= sizeof (md_longopts
);
14655 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14656 NEW_VALUE. Warn if another value was already specified. Note:
14657 we have to defer parsing the -march and -mtune arguments in order
14658 to handle 'from-abi' correctly, since the ABI might be specified
14659 in a later argument. */
14662 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14664 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14665 as_warn (_("A different %s was already specified, is now %s"),
14666 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14669 *string_ptr
= new_value
;
14673 md_parse_option (int c
, char *arg
)
14677 case OPTION_CONSTRUCT_FLOATS
:
14678 mips_disable_float_construction
= 0;
14681 case OPTION_NO_CONSTRUCT_FLOATS
:
14682 mips_disable_float_construction
= 1;
14694 target_big_endian
= 1;
14698 target_big_endian
= 0;
14704 else if (arg
[0] == '0')
14706 else if (arg
[0] == '1')
14716 mips_debug
= atoi (arg
);
14720 file_mips_isa
= ISA_MIPS1
;
14724 file_mips_isa
= ISA_MIPS2
;
14728 file_mips_isa
= ISA_MIPS3
;
14732 file_mips_isa
= ISA_MIPS4
;
14736 file_mips_isa
= ISA_MIPS5
;
14739 case OPTION_MIPS32
:
14740 file_mips_isa
= ISA_MIPS32
;
14743 case OPTION_MIPS32R2
:
14744 file_mips_isa
= ISA_MIPS32R2
;
14747 case OPTION_MIPS64R2
:
14748 file_mips_isa
= ISA_MIPS64R2
;
14751 case OPTION_MIPS64
:
14752 file_mips_isa
= ISA_MIPS64
;
14756 mips_set_option_string (&mips_tune_string
, arg
);
14760 mips_set_option_string (&mips_arch_string
, arg
);
14764 mips_set_option_string (&mips_arch_string
, "4650");
14765 mips_set_option_string (&mips_tune_string
, "4650");
14768 case OPTION_NO_M4650
:
14772 mips_set_option_string (&mips_arch_string
, "4010");
14773 mips_set_option_string (&mips_tune_string
, "4010");
14776 case OPTION_NO_M4010
:
14780 mips_set_option_string (&mips_arch_string
, "4100");
14781 mips_set_option_string (&mips_tune_string
, "4100");
14784 case OPTION_NO_M4100
:
14788 mips_set_option_string (&mips_arch_string
, "3900");
14789 mips_set_option_string (&mips_tune_string
, "3900");
14792 case OPTION_NO_M3900
:
14796 mips_opts
.ase_mdmx
= 1;
14799 case OPTION_NO_MDMX
:
14800 mips_opts
.ase_mdmx
= 0;
14804 mips_opts
.ase_dsp
= 1;
14805 mips_opts
.ase_dspr2
= 0;
14808 case OPTION_NO_DSP
:
14809 mips_opts
.ase_dsp
= 0;
14810 mips_opts
.ase_dspr2
= 0;
14814 mips_opts
.ase_dspr2
= 1;
14815 mips_opts
.ase_dsp
= 1;
14818 case OPTION_NO_DSPR2
:
14819 mips_opts
.ase_dspr2
= 0;
14820 mips_opts
.ase_dsp
= 0;
14824 mips_opts
.ase_mt
= 1;
14828 mips_opts
.ase_mt
= 0;
14832 mips_opts
.ase_mcu
= 1;
14835 case OPTION_NO_MCU
:
14836 mips_opts
.ase_mcu
= 0;
14839 case OPTION_MICROMIPS
:
14840 if (mips_opts
.mips16
== 1)
14842 as_bad (_("-mmicromips cannot be used with -mips16"));
14845 mips_opts
.micromips
= 1;
14846 mips_no_prev_insn ();
14849 case OPTION_NO_MICROMIPS
:
14850 mips_opts
.micromips
= 0;
14851 mips_no_prev_insn ();
14854 case OPTION_MIPS16
:
14855 if (mips_opts
.micromips
== 1)
14857 as_bad (_("-mips16 cannot be used with -micromips"));
14860 mips_opts
.mips16
= 1;
14861 mips_no_prev_insn ();
14864 case OPTION_NO_MIPS16
:
14865 mips_opts
.mips16
= 0;
14866 mips_no_prev_insn ();
14869 case OPTION_MIPS3D
:
14870 mips_opts
.ase_mips3d
= 1;
14873 case OPTION_NO_MIPS3D
:
14874 mips_opts
.ase_mips3d
= 0;
14877 case OPTION_SMARTMIPS
:
14878 mips_opts
.ase_smartmips
= 1;
14881 case OPTION_NO_SMARTMIPS
:
14882 mips_opts
.ase_smartmips
= 0;
14885 case OPTION_FIX_24K
:
14889 case OPTION_NO_FIX_24K
:
14893 case OPTION_FIX_LOONGSON2F_JUMP
:
14894 mips_fix_loongson2f_jump
= TRUE
;
14897 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14898 mips_fix_loongson2f_jump
= FALSE
;
14901 case OPTION_FIX_LOONGSON2F_NOP
:
14902 mips_fix_loongson2f_nop
= TRUE
;
14905 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14906 mips_fix_loongson2f_nop
= FALSE
;
14909 case OPTION_FIX_VR4120
:
14910 mips_fix_vr4120
= 1;
14913 case OPTION_NO_FIX_VR4120
:
14914 mips_fix_vr4120
= 0;
14917 case OPTION_FIX_VR4130
:
14918 mips_fix_vr4130
= 1;
14921 case OPTION_NO_FIX_VR4130
:
14922 mips_fix_vr4130
= 0;
14925 case OPTION_FIX_CN63XXP1
:
14926 mips_fix_cn63xxp1
= TRUE
;
14929 case OPTION_NO_FIX_CN63XXP1
:
14930 mips_fix_cn63xxp1
= FALSE
;
14933 case OPTION_RELAX_BRANCH
:
14934 mips_relax_branch
= 1;
14937 case OPTION_NO_RELAX_BRANCH
:
14938 mips_relax_branch
= 0;
14941 case OPTION_MSHARED
:
14942 mips_in_shared
= TRUE
;
14945 case OPTION_MNO_SHARED
:
14946 mips_in_shared
= FALSE
;
14949 case OPTION_MSYM32
:
14950 mips_opts
.sym32
= TRUE
;
14953 case OPTION_MNO_SYM32
:
14954 mips_opts
.sym32
= FALSE
;
14958 /* When generating ELF code, we permit -KPIC and -call_shared to
14959 select SVR4_PIC, and -non_shared to select no PIC. This is
14960 intended to be compatible with Irix 5. */
14961 case OPTION_CALL_SHARED
:
14964 as_bad (_("-call_shared is supported only for ELF format"));
14967 mips_pic
= SVR4_PIC
;
14968 mips_abicalls
= TRUE
;
14971 case OPTION_CALL_NONPIC
:
14974 as_bad (_("-call_nonpic is supported only for ELF format"));
14978 mips_abicalls
= TRUE
;
14981 case OPTION_NON_SHARED
:
14984 as_bad (_("-non_shared is supported only for ELF format"));
14988 mips_abicalls
= FALSE
;
14991 /* The -xgot option tells the assembler to use 32 bit offsets
14992 when accessing the got in SVR4_PIC mode. It is for Irix
14997 #endif /* OBJ_ELF */
15000 g_switch_value
= atoi (arg
);
15004 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15008 mips_abi
= O32_ABI
;
15009 /* We silently ignore -32 for non-ELF targets. This greatly
15010 simplifies the construction of the MIPS GAS test cases. */
15017 as_bad (_("-n32 is supported for ELF format only"));
15020 mips_abi
= N32_ABI
;
15026 as_bad (_("-64 is supported for ELF format only"));
15029 mips_abi
= N64_ABI
;
15030 if (!support_64bit_objects())
15031 as_fatal (_("No compiled in support for 64 bit object file format"));
15033 #endif /* OBJ_ELF */
15036 file_mips_gp32
= 1;
15040 file_mips_gp32
= 0;
15044 file_mips_fp32
= 1;
15048 file_mips_fp32
= 0;
15051 case OPTION_SINGLE_FLOAT
:
15052 file_mips_single_float
= 1;
15055 case OPTION_DOUBLE_FLOAT
:
15056 file_mips_single_float
= 0;
15059 case OPTION_SOFT_FLOAT
:
15060 file_mips_soft_float
= 1;
15063 case OPTION_HARD_FLOAT
:
15064 file_mips_soft_float
= 0;
15071 as_bad (_("-mabi is supported for ELF format only"));
15074 if (strcmp (arg
, "32") == 0)
15075 mips_abi
= O32_ABI
;
15076 else if (strcmp (arg
, "o64") == 0)
15077 mips_abi
= O64_ABI
;
15078 else if (strcmp (arg
, "n32") == 0)
15079 mips_abi
= N32_ABI
;
15080 else if (strcmp (arg
, "64") == 0)
15082 mips_abi
= N64_ABI
;
15083 if (! support_64bit_objects())
15084 as_fatal (_("No compiled in support for 64 bit object file "
15087 else if (strcmp (arg
, "eabi") == 0)
15088 mips_abi
= EABI_ABI
;
15091 as_fatal (_("invalid abi -mabi=%s"), arg
);
15095 #endif /* OBJ_ELF */
15097 case OPTION_M7000_HILO_FIX
:
15098 mips_7000_hilo_fix
= TRUE
;
15101 case OPTION_MNO_7000_HILO_FIX
:
15102 mips_7000_hilo_fix
= FALSE
;
15106 case OPTION_MDEBUG
:
15107 mips_flag_mdebug
= TRUE
;
15110 case OPTION_NO_MDEBUG
:
15111 mips_flag_mdebug
= FALSE
;
15115 mips_flag_pdr
= TRUE
;
15118 case OPTION_NO_PDR
:
15119 mips_flag_pdr
= FALSE
;
15122 case OPTION_MVXWORKS_PIC
:
15123 mips_pic
= VXWORKS_PIC
;
15125 #endif /* OBJ_ELF */
15131 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15136 /* Set up globals to generate code for the ISA or processor
15137 described by INFO. */
15140 mips_set_architecture (const struct mips_cpu_info
*info
)
15144 file_mips_arch
= info
->cpu
;
15145 mips_opts
.arch
= info
->cpu
;
15146 mips_opts
.isa
= info
->isa
;
15151 /* Likewise for tuning. */
15154 mips_set_tune (const struct mips_cpu_info
*info
)
15157 mips_tune
= info
->cpu
;
15162 mips_after_parse_args (void)
15164 const struct mips_cpu_info
*arch_info
= 0;
15165 const struct mips_cpu_info
*tune_info
= 0;
15167 /* GP relative stuff not working for PE */
15168 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15170 if (g_switch_seen
&& g_switch_value
!= 0)
15171 as_bad (_("-G not supported in this configuration."));
15172 g_switch_value
= 0;
15175 if (mips_abi
== NO_ABI
)
15176 mips_abi
= MIPS_DEFAULT_ABI
;
15178 /* The following code determines the architecture and register size.
15179 Similar code was added to GCC 3.3 (see override_options() in
15180 config/mips/mips.c). The GAS and GCC code should be kept in sync
15181 as much as possible. */
15183 if (mips_arch_string
!= 0)
15184 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15186 if (file_mips_isa
!= ISA_UNKNOWN
)
15188 /* Handle -mipsN. At this point, file_mips_isa contains the
15189 ISA level specified by -mipsN, while arch_info->isa contains
15190 the -march selection (if any). */
15191 if (arch_info
!= 0)
15193 /* -march takes precedence over -mipsN, since it is more descriptive.
15194 There's no harm in specifying both as long as the ISA levels
15196 if (file_mips_isa
!= arch_info
->isa
)
15197 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15198 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15199 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15202 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15205 if (arch_info
== 0)
15207 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15208 gas_assert (arch_info
);
15211 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15212 as_bad (_("-march=%s is not compatible with the selected ABI"),
15215 mips_set_architecture (arch_info
);
15217 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15218 if (mips_tune_string
!= 0)
15219 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15221 if (tune_info
== 0)
15222 mips_set_tune (arch_info
);
15224 mips_set_tune (tune_info
);
15226 if (file_mips_gp32
>= 0)
15228 /* The user specified the size of the integer registers. Make sure
15229 it agrees with the ABI and ISA. */
15230 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15231 as_bad (_("-mgp64 used with a 32-bit processor"));
15232 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15233 as_bad (_("-mgp32 used with a 64-bit ABI"));
15234 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15235 as_bad (_("-mgp64 used with a 32-bit ABI"));
15239 /* Infer the integer register size from the ABI and processor.
15240 Restrict ourselves to 32-bit registers if that's all the
15241 processor has, or if the ABI cannot handle 64-bit registers. */
15242 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15243 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15246 switch (file_mips_fp32
)
15250 /* No user specified float register size.
15251 ??? GAS treats single-float processors as though they had 64-bit
15252 float registers (although it complains when double-precision
15253 instructions are used). As things stand, saying they have 32-bit
15254 registers would lead to spurious "register must be even" messages.
15255 So here we assume float registers are never smaller than the
15257 if (file_mips_gp32
== 0)
15258 /* 64-bit integer registers implies 64-bit float registers. */
15259 file_mips_fp32
= 0;
15260 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
15261 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15262 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15263 file_mips_fp32
= 0;
15265 /* 32-bit float registers. */
15266 file_mips_fp32
= 1;
15269 /* The user specified the size of the float registers. Check if it
15270 agrees with the ABI and ISA. */
15272 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15273 as_bad (_("-mfp64 used with a 32-bit fpu"));
15274 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15275 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15276 as_warn (_("-mfp64 used with a 32-bit ABI"));
15279 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15280 as_warn (_("-mfp32 used with a 64-bit ABI"));
15284 /* End of GCC-shared inference code. */
15286 /* This flag is set when we have a 64-bit capable CPU but use only
15287 32-bit wide registers. Note that EABI does not use it. */
15288 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15289 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15290 || mips_abi
== O32_ABI
))
15291 mips_32bitmode
= 1;
15293 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15294 as_bad (_("trap exception not supported at ISA 1"));
15296 /* If the selected architecture includes support for ASEs, enable
15297 generation of code for them. */
15298 if (mips_opts
.mips16
== -1)
15299 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15300 if (mips_opts
.micromips
== -1)
15301 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15302 if (mips_opts
.ase_mips3d
== -1)
15303 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
15304 && file_mips_fp32
== 0) ? 1 : 0;
15305 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
15306 as_bad (_("-mfp32 used with -mips3d"));
15308 if (mips_opts
.ase_mdmx
== -1)
15309 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
15310 && file_mips_fp32
== 0) ? 1 : 0;
15311 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
15312 as_bad (_("-mfp32 used with -mdmx"));
15314 if (mips_opts
.ase_smartmips
== -1)
15315 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15316 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15317 as_warn (_("%s ISA does not support SmartMIPS"),
15318 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15320 if (mips_opts
.ase_dsp
== -1)
15321 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15322 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15323 as_warn (_("%s ISA does not support DSP ASE"),
15324 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15326 if (mips_opts
.ase_dspr2
== -1)
15328 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15329 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15331 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15332 as_warn (_("%s ISA does not support DSP R2 ASE"),
15333 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15335 if (mips_opts
.ase_mt
== -1)
15336 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15337 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15338 as_warn (_("%s ISA does not support MT ASE"),
15339 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15341 if (mips_opts
.ase_mcu
== -1)
15342 mips_opts
.ase_mcu
= (arch_info
->flags
& MIPS_CPU_ASE_MCU
) ? 1 : 0;
15343 if (mips_opts
.ase_mcu
&& !ISA_SUPPORTS_MCU_ASE
)
15344 as_warn (_("%s ISA does not support MCU ASE"),
15345 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15347 file_mips_isa
= mips_opts
.isa
;
15348 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15349 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15350 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15351 file_ase_dsp
= mips_opts
.ase_dsp
;
15352 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15353 file_ase_mt
= mips_opts
.ase_mt
;
15354 mips_opts
.gp32
= file_mips_gp32
;
15355 mips_opts
.fp32
= file_mips_fp32
;
15356 mips_opts
.soft_float
= file_mips_soft_float
;
15357 mips_opts
.single_float
= file_mips_single_float
;
15359 if (mips_flag_mdebug
< 0)
15361 #ifdef OBJ_MAYBE_ECOFF
15362 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15363 mips_flag_mdebug
= 1;
15365 #endif /* OBJ_MAYBE_ECOFF */
15366 mips_flag_mdebug
= 0;
15371 mips_init_after_args (void)
15373 /* initialize opcodes */
15374 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15375 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15379 md_pcrel_from (fixS
*fixP
)
15381 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15382 switch (fixP
->fx_r_type
)
15384 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15385 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15386 /* Return the address of the delay slot. */
15389 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15390 case BFD_RELOC_MICROMIPS_JMP
:
15391 case BFD_RELOC_16_PCREL_S2
:
15392 case BFD_RELOC_MIPS_JMP
:
15393 /* Return the address of the delay slot. */
15397 /* We have no relocation type for PC relative MIPS16 instructions. */
15398 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15400 _("PC relative MIPS16 instruction references a different section"));
15405 /* This is called before the symbol table is processed. In order to
15406 work with gcc when using mips-tfile, we must keep all local labels.
15407 However, in other cases, we want to discard them. If we were
15408 called with -g, but we didn't see any debugging information, it may
15409 mean that gcc is smuggling debugging information through to
15410 mips-tfile, in which case we must generate all local labels. */
15413 mips_frob_file_before_adjust (void)
15415 #ifndef NO_ECOFF_DEBUGGING
15416 if (ECOFF_DEBUGGING
15418 && ! ecoff_debugging_seen
)
15419 flag_keep_locals
= 1;
15423 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15424 the corresponding LO16 reloc. This is called before md_apply_fix and
15425 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15426 relocation operators.
15428 For our purposes, a %lo() expression matches a %got() or %hi()
15431 (a) it refers to the same symbol; and
15432 (b) the offset applied in the %lo() expression is no lower than
15433 the offset applied in the %got() or %hi().
15435 (b) allows us to cope with code like:
15438 lh $4,%lo(foo+2)($4)
15440 ...which is legal on RELA targets, and has a well-defined behaviour
15441 if the user knows that adding 2 to "foo" will not induce a carry to
15444 When several %lo()s match a particular %got() or %hi(), we use the
15445 following rules to distinguish them:
15447 (1) %lo()s with smaller offsets are a better match than %lo()s with
15450 (2) %lo()s with no matching %got() or %hi() are better than those
15451 that already have a matching %got() or %hi().
15453 (3) later %lo()s are better than earlier %lo()s.
15455 These rules are applied in order.
15457 (1) means, among other things, that %lo()s with identical offsets are
15458 chosen if they exist.
15460 (2) means that we won't associate several high-part relocations with
15461 the same low-part relocation unless there's no alternative. Having
15462 several high parts for the same low part is a GNU extension; this rule
15463 allows careful users to avoid it.
15465 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15466 with the last high-part relocation being at the front of the list.
15467 It therefore makes sense to choose the last matching low-part
15468 relocation, all other things being equal. It's also easier
15469 to code that way. */
15472 mips_frob_file (void)
15474 struct mips_hi_fixup
*l
;
15475 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15477 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15479 segment_info_type
*seginfo
;
15480 bfd_boolean matched_lo_p
;
15481 fixS
**hi_pos
, **lo_pos
, **pos
;
15483 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15485 /* If a GOT16 relocation turns out to be against a global symbol,
15486 there isn't supposed to be a matching LO. Ignore %gots against
15487 constants; we'll report an error for those later. */
15488 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15489 && !(l
->fixp
->fx_addsy
15490 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15493 /* Check quickly whether the next fixup happens to be a matching %lo. */
15494 if (fixup_has_matching_lo_p (l
->fixp
))
15497 seginfo
= seg_info (l
->seg
);
15499 /* Set HI_POS to the position of this relocation in the chain.
15500 Set LO_POS to the position of the chosen low-part relocation.
15501 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15502 relocation that matches an immediately-preceding high-part
15506 matched_lo_p
= FALSE
;
15507 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15509 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15511 if (*pos
== l
->fixp
)
15514 if ((*pos
)->fx_r_type
== looking_for_rtype
15515 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15516 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15518 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15520 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15523 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15524 && fixup_has_matching_lo_p (*pos
));
15527 /* If we found a match, remove the high-part relocation from its
15528 current position and insert it before the low-part relocation.
15529 Make the offsets match so that fixup_has_matching_lo_p()
15532 We don't warn about unmatched high-part relocations since some
15533 versions of gcc have been known to emit dead "lui ...%hi(...)"
15535 if (lo_pos
!= NULL
)
15537 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15538 if (l
->fixp
->fx_next
!= *lo_pos
)
15540 *hi_pos
= l
->fixp
->fx_next
;
15541 l
->fixp
->fx_next
= *lo_pos
;
15549 mips_force_relocation (fixS
*fixp
)
15551 if (generic_force_reloc (fixp
))
15554 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15555 so that the linker relaxation can update targets. */
15556 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15557 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15558 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15564 /* Read the instruction associated with RELOC from BUF. */
15566 static unsigned int
15567 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15569 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15570 return read_compressed_insn (buf
, 4);
15572 return read_insn (buf
);
15575 /* Write instruction INSN to BUF, given that it has been relocated
15579 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15580 unsigned long insn
)
15582 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15583 write_compressed_insn (buf
, insn
, 4);
15585 write_insn (buf
, insn
);
15588 /* Apply a fixup to the object file. */
15591 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15594 unsigned long insn
;
15595 reloc_howto_type
*howto
;
15597 /* We ignore generic BFD relocations we don't know about. */
15598 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15602 gas_assert (fixP
->fx_size
== 2
15603 || fixP
->fx_size
== 4
15604 || fixP
->fx_r_type
== BFD_RELOC_16
15605 || fixP
->fx_r_type
== BFD_RELOC_64
15606 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15607 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15608 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15609 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15610 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15611 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15613 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15615 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15616 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15617 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15618 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
15620 /* Don't treat parts of a composite relocation as done. There are two
15623 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15624 should nevertheless be emitted if the first part is.
15626 (2) In normal usage, composite relocations are never assembly-time
15627 constants. The easiest way of dealing with the pathological
15628 exceptions is to generate a relocation against STN_UNDEF and
15629 leave everything up to the linker. */
15630 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15633 switch (fixP
->fx_r_type
)
15635 case BFD_RELOC_MIPS_TLS_GD
:
15636 case BFD_RELOC_MIPS_TLS_LDM
:
15637 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15638 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15639 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15640 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15641 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15642 case BFD_RELOC_MIPS_TLS_TPREL32
:
15643 case BFD_RELOC_MIPS_TLS_TPREL64
:
15644 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15645 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15646 case BFD_RELOC_MICROMIPS_TLS_GD
:
15647 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15648 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15649 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15650 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15651 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15652 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15653 case BFD_RELOC_MIPS16_TLS_GD
:
15654 case BFD_RELOC_MIPS16_TLS_LDM
:
15655 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15656 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15657 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15658 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15659 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15660 if (!fixP
->fx_addsy
)
15662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15663 _("TLS relocation against a constant"));
15666 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15669 case BFD_RELOC_MIPS_JMP
:
15670 case BFD_RELOC_MIPS_SHIFT5
:
15671 case BFD_RELOC_MIPS_SHIFT6
:
15672 case BFD_RELOC_MIPS_GOT_DISP
:
15673 case BFD_RELOC_MIPS_GOT_PAGE
:
15674 case BFD_RELOC_MIPS_GOT_OFST
:
15675 case BFD_RELOC_MIPS_SUB
:
15676 case BFD_RELOC_MIPS_INSERT_A
:
15677 case BFD_RELOC_MIPS_INSERT_B
:
15678 case BFD_RELOC_MIPS_DELETE
:
15679 case BFD_RELOC_MIPS_HIGHEST
:
15680 case BFD_RELOC_MIPS_HIGHER
:
15681 case BFD_RELOC_MIPS_SCN_DISP
:
15682 case BFD_RELOC_MIPS_REL16
:
15683 case BFD_RELOC_MIPS_RELGOT
:
15684 case BFD_RELOC_MIPS_JALR
:
15685 case BFD_RELOC_HI16
:
15686 case BFD_RELOC_HI16_S
:
15687 case BFD_RELOC_LO16
:
15688 case BFD_RELOC_GPREL16
:
15689 case BFD_RELOC_MIPS_LITERAL
:
15690 case BFD_RELOC_MIPS_CALL16
:
15691 case BFD_RELOC_MIPS_GOT16
:
15692 case BFD_RELOC_GPREL32
:
15693 case BFD_RELOC_MIPS_GOT_HI16
:
15694 case BFD_RELOC_MIPS_GOT_LO16
:
15695 case BFD_RELOC_MIPS_CALL_HI16
:
15696 case BFD_RELOC_MIPS_CALL_LO16
:
15697 case BFD_RELOC_MIPS16_GPREL
:
15698 case BFD_RELOC_MIPS16_GOT16
:
15699 case BFD_RELOC_MIPS16_CALL16
:
15700 case BFD_RELOC_MIPS16_HI16
:
15701 case BFD_RELOC_MIPS16_HI16_S
:
15702 case BFD_RELOC_MIPS16_LO16
:
15703 case BFD_RELOC_MIPS16_JMP
:
15704 case BFD_RELOC_MICROMIPS_JMP
:
15705 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15706 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15707 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15708 case BFD_RELOC_MICROMIPS_SUB
:
15709 case BFD_RELOC_MICROMIPS_HIGHEST
:
15710 case BFD_RELOC_MICROMIPS_HIGHER
:
15711 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15712 case BFD_RELOC_MICROMIPS_JALR
:
15713 case BFD_RELOC_MICROMIPS_HI16
:
15714 case BFD_RELOC_MICROMIPS_HI16_S
:
15715 case BFD_RELOC_MICROMIPS_LO16
:
15716 case BFD_RELOC_MICROMIPS_GPREL16
:
15717 case BFD_RELOC_MICROMIPS_LITERAL
:
15718 case BFD_RELOC_MICROMIPS_CALL16
:
15719 case BFD_RELOC_MICROMIPS_GOT16
:
15720 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15721 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15722 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15723 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15728 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15730 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15731 if (mips16_reloc_p (fixP
->fx_r_type
))
15732 insn
|= mips16_immed_extend (value
, 16);
15734 insn
|= (value
& 0xffff);
15735 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15739 _("Unsupported constant in relocation"));
15744 /* This is handled like BFD_RELOC_32, but we output a sign
15745 extended value if we are only 32 bits. */
15748 if (8 <= sizeof (valueT
))
15749 md_number_to_chars (buf
, *valP
, 8);
15754 if ((*valP
& 0x80000000) != 0)
15758 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15759 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15764 case BFD_RELOC_RVA
:
15767 /* If we are deleting this reloc entry, we must fill in the
15768 value now. This can happen if we have a .word which is not
15769 resolved when it appears but is later defined. */
15771 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15774 case BFD_RELOC_16_PCREL_S2
:
15775 if ((*valP
& 0x3) != 0)
15776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15777 _("Branch to misaligned address (%lx)"), (long) *valP
);
15779 /* We need to save the bits in the instruction since fixup_segment()
15780 might be deleting the relocation entry (i.e., a branch within
15781 the current segment). */
15782 if (! fixP
->fx_done
)
15785 /* Update old instruction data. */
15786 insn
= read_insn (buf
);
15788 if (*valP
+ 0x20000 <= 0x3ffff)
15790 insn
|= (*valP
>> 2) & 0xffff;
15791 write_insn (buf
, insn
);
15793 else if (mips_pic
== NO_PIC
15795 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15796 && (fixP
->fx_frag
->fr_address
15797 < text_section
->vma
+ bfd_get_section_size (text_section
))
15798 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15799 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15800 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15802 /* The branch offset is too large. If this is an
15803 unconditional branch, and we are not generating PIC code,
15804 we can convert it to an absolute jump instruction. */
15805 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15806 insn
= 0x0c000000; /* jal */
15808 insn
= 0x08000000; /* j */
15809 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15811 fixP
->fx_addsy
= section_symbol (text_section
);
15812 *valP
+= md_pcrel_from (fixP
);
15813 write_insn (buf
, insn
);
15817 /* If we got here, we have branch-relaxation disabled,
15818 and there's nothing we can do to fix this instruction
15819 without turning it into a longer sequence. */
15820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15821 _("Branch out of range"));
15825 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15826 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15827 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15828 /* We adjust the offset back to even. */
15829 if ((*valP
& 0x1) != 0)
15832 if (! fixP
->fx_done
)
15835 /* Should never visit here, because we keep the relocation. */
15839 case BFD_RELOC_VTABLE_INHERIT
:
15842 && !S_IS_DEFINED (fixP
->fx_addsy
)
15843 && !S_IS_WEAK (fixP
->fx_addsy
))
15844 S_SET_WEAK (fixP
->fx_addsy
);
15847 case BFD_RELOC_VTABLE_ENTRY
:
15855 /* Remember value for tc_gen_reloc. */
15856 fixP
->fx_addnumber
= *valP
;
15866 name
= input_line_pointer
;
15867 c
= get_symbol_end ();
15868 p
= (symbolS
*) symbol_find_or_make (name
);
15869 *input_line_pointer
= c
;
15873 /* Align the current frag to a given power of two. If a particular
15874 fill byte should be used, FILL points to an integer that contains
15875 that byte, otherwise FILL is null.
15877 This function used to have the comment:
15879 The MIPS assembler also automatically adjusts any preceding label.
15881 The implementation therefore applied the adjustment to a maximum of
15882 one label. However, other label adjustments are applied to batches
15883 of labels, and adjusting just one caused problems when new labels
15884 were added for the sake of debugging or unwind information.
15885 We therefore adjust all preceding labels (given as LABELS) instead. */
15888 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15890 mips_emit_delays ();
15891 mips_record_compressed_mode ();
15892 if (fill
== NULL
&& subseg_text_p (now_seg
))
15893 frag_align_code (to
, 0);
15895 frag_align (to
, fill
? *fill
: 0, 0);
15896 record_alignment (now_seg
, to
);
15897 mips_move_labels (labels
, FALSE
);
15900 /* Align to a given power of two. .align 0 turns off the automatic
15901 alignment used by the data creating pseudo-ops. */
15904 s_align (int x ATTRIBUTE_UNUSED
)
15906 int temp
, fill_value
, *fill_ptr
;
15907 long max_alignment
= 28;
15909 /* o Note that the assembler pulls down any immediately preceding label
15910 to the aligned address.
15911 o It's not documented but auto alignment is reinstated by
15912 a .align pseudo instruction.
15913 o Note also that after auto alignment is turned off the mips assembler
15914 issues an error on attempt to assemble an improperly aligned data item.
15917 temp
= get_absolute_expression ();
15918 if (temp
> max_alignment
)
15919 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
15922 as_warn (_("Alignment negative: 0 assumed."));
15925 if (*input_line_pointer
== ',')
15927 ++input_line_pointer
;
15928 fill_value
= get_absolute_expression ();
15929 fill_ptr
= &fill_value
;
15935 segment_info_type
*si
= seg_info (now_seg
);
15936 struct insn_label_list
*l
= si
->label_list
;
15937 /* Auto alignment should be switched on by next section change. */
15939 mips_align (temp
, fill_ptr
, l
);
15946 demand_empty_rest_of_line ();
15950 s_change_sec (int sec
)
15955 /* The ELF backend needs to know that we are changing sections, so
15956 that .previous works correctly. We could do something like check
15957 for an obj_section_change_hook macro, but that might be confusing
15958 as it would not be appropriate to use it in the section changing
15959 functions in read.c, since obj-elf.c intercepts those. FIXME:
15960 This should be cleaner, somehow. */
15962 obj_elf_section_change_hook ();
15965 mips_emit_delays ();
15976 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15977 demand_empty_rest_of_line ();
15981 seg
= subseg_new (RDATA_SECTION_NAME
,
15982 (subsegT
) get_absolute_expression ());
15985 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15986 | SEC_READONLY
| SEC_RELOC
15988 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15989 record_alignment (seg
, 4);
15991 demand_empty_rest_of_line ();
15995 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15998 bfd_set_section_flags (stdoutput
, seg
,
15999 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16000 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16001 record_alignment (seg
, 4);
16003 demand_empty_rest_of_line ();
16007 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16010 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16011 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16012 record_alignment (seg
, 4);
16014 demand_empty_rest_of_line ();
16022 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16025 char *section_name
;
16030 int section_entry_size
;
16031 int section_alignment
;
16036 section_name
= input_line_pointer
;
16037 c
= get_symbol_end ();
16039 next_c
= *(input_line_pointer
+ 1);
16041 /* Do we have .section Name<,"flags">? */
16042 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16044 /* just after name is now '\0'. */
16045 *input_line_pointer
= c
;
16046 input_line_pointer
= section_name
;
16047 obj_elf_section (ignore
);
16050 input_line_pointer
++;
16052 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16054 section_type
= get_absolute_expression ();
16057 if (*input_line_pointer
++ == ',')
16058 section_flag
= get_absolute_expression ();
16061 if (*input_line_pointer
++ == ',')
16062 section_entry_size
= get_absolute_expression ();
16064 section_entry_size
= 0;
16065 if (*input_line_pointer
++ == ',')
16066 section_alignment
= get_absolute_expression ();
16068 section_alignment
= 0;
16069 /* FIXME: really ignore? */
16070 (void) section_alignment
;
16072 section_name
= xstrdup (section_name
);
16074 /* When using the generic form of .section (as implemented by obj-elf.c),
16075 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16076 traditionally had to fall back on the more common @progbits instead.
16078 There's nothing really harmful in this, since bfd will correct
16079 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16080 means that, for backwards compatibility, the special_section entries
16081 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16083 Even so, we shouldn't force users of the MIPS .section syntax to
16084 incorrectly label the sections as SHT_PROGBITS. The best compromise
16085 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16086 generic type-checking code. */
16087 if (section_type
== SHT_MIPS_DWARF
)
16088 section_type
= SHT_PROGBITS
;
16090 obj_elf_change_section (section_name
, section_type
, section_flag
,
16091 section_entry_size
, 0, 0, 0);
16093 if (now_seg
->name
!= section_name
)
16094 free (section_name
);
16095 #endif /* OBJ_ELF */
16099 mips_enable_auto_align (void)
16105 s_cons (int log_size
)
16107 segment_info_type
*si
= seg_info (now_seg
);
16108 struct insn_label_list
*l
= si
->label_list
;
16110 mips_emit_delays ();
16111 if (log_size
> 0 && auto_align
)
16112 mips_align (log_size
, 0, l
);
16113 cons (1 << log_size
);
16114 mips_clear_insn_labels ();
16118 s_float_cons (int type
)
16120 segment_info_type
*si
= seg_info (now_seg
);
16121 struct insn_label_list
*l
= si
->label_list
;
16123 mips_emit_delays ();
16128 mips_align (3, 0, l
);
16130 mips_align (2, 0, l
);
16134 mips_clear_insn_labels ();
16137 /* Handle .globl. We need to override it because on Irix 5 you are
16140 where foo is an undefined symbol, to mean that foo should be
16141 considered to be the address of a function. */
16144 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16153 name
= input_line_pointer
;
16154 c
= get_symbol_end ();
16155 symbolP
= symbol_find_or_make (name
);
16156 S_SET_EXTERNAL (symbolP
);
16158 *input_line_pointer
= c
;
16159 SKIP_WHITESPACE ();
16161 /* On Irix 5, every global symbol that is not explicitly labelled as
16162 being a function is apparently labelled as being an object. */
16165 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16166 && (*input_line_pointer
!= ','))
16171 secname
= input_line_pointer
;
16172 c
= get_symbol_end ();
16173 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16175 as_bad (_("%s: no such section"), secname
);
16176 *input_line_pointer
= c
;
16178 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16179 flag
= BSF_FUNCTION
;
16182 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16184 c
= *input_line_pointer
;
16187 input_line_pointer
++;
16188 SKIP_WHITESPACE ();
16189 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16195 demand_empty_rest_of_line ();
16199 s_option (int x ATTRIBUTE_UNUSED
)
16204 opt
= input_line_pointer
;
16205 c
= get_symbol_end ();
16209 /* FIXME: What does this mean? */
16211 else if (strncmp (opt
, "pic", 3) == 0)
16215 i
= atoi (opt
+ 3);
16220 mips_pic
= SVR4_PIC
;
16221 mips_abicalls
= TRUE
;
16224 as_bad (_(".option pic%d not supported"), i
);
16226 if (mips_pic
== SVR4_PIC
)
16228 if (g_switch_seen
&& g_switch_value
!= 0)
16229 as_warn (_("-G may not be used with SVR4 PIC code"));
16230 g_switch_value
= 0;
16231 bfd_set_gp_size (stdoutput
, 0);
16235 as_warn (_("Unrecognized option \"%s\""), opt
);
16237 *input_line_pointer
= c
;
16238 demand_empty_rest_of_line ();
16241 /* This structure is used to hold a stack of .set values. */
16243 struct mips_option_stack
16245 struct mips_option_stack
*next
;
16246 struct mips_set_options options
;
16249 static struct mips_option_stack
*mips_opts_stack
;
16251 /* Handle the .set pseudo-op. */
16254 s_mipsset (int x ATTRIBUTE_UNUSED
)
16256 char *name
= input_line_pointer
, ch
;
16258 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16259 ++input_line_pointer
;
16260 ch
= *input_line_pointer
;
16261 *input_line_pointer
= '\0';
16263 if (strcmp (name
, "reorder") == 0)
16265 if (mips_opts
.noreorder
)
16268 else if (strcmp (name
, "noreorder") == 0)
16270 if (!mips_opts
.noreorder
)
16271 start_noreorder ();
16273 else if (strncmp (name
, "at=", 3) == 0)
16275 char *s
= name
+ 3;
16277 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16278 as_bad (_("Unrecognized register name `%s'"), s
);
16280 else if (strcmp (name
, "at") == 0)
16282 mips_opts
.at
= ATREG
;
16284 else if (strcmp (name
, "noat") == 0)
16286 mips_opts
.at
= ZERO
;
16288 else if (strcmp (name
, "macro") == 0)
16290 mips_opts
.warn_about_macros
= 0;
16292 else if (strcmp (name
, "nomacro") == 0)
16294 if (mips_opts
.noreorder
== 0)
16295 as_bad (_("`noreorder' must be set before `nomacro'"));
16296 mips_opts
.warn_about_macros
= 1;
16298 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16300 mips_opts
.nomove
= 0;
16302 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16304 mips_opts
.nomove
= 1;
16306 else if (strcmp (name
, "bopt") == 0)
16308 mips_opts
.nobopt
= 0;
16310 else if (strcmp (name
, "nobopt") == 0)
16312 mips_opts
.nobopt
= 1;
16314 else if (strcmp (name
, "gp=default") == 0)
16315 mips_opts
.gp32
= file_mips_gp32
;
16316 else if (strcmp (name
, "gp=32") == 0)
16317 mips_opts
.gp32
= 1;
16318 else if (strcmp (name
, "gp=64") == 0)
16320 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16321 as_warn (_("%s isa does not support 64-bit registers"),
16322 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16323 mips_opts
.gp32
= 0;
16325 else if (strcmp (name
, "fp=default") == 0)
16326 mips_opts
.fp32
= file_mips_fp32
;
16327 else if (strcmp (name
, "fp=32") == 0)
16328 mips_opts
.fp32
= 1;
16329 else if (strcmp (name
, "fp=64") == 0)
16331 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16332 as_warn (_("%s isa does not support 64-bit floating point registers"),
16333 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16334 mips_opts
.fp32
= 0;
16336 else if (strcmp (name
, "softfloat") == 0)
16337 mips_opts
.soft_float
= 1;
16338 else if (strcmp (name
, "hardfloat") == 0)
16339 mips_opts
.soft_float
= 0;
16340 else if (strcmp (name
, "singlefloat") == 0)
16341 mips_opts
.single_float
= 1;
16342 else if (strcmp (name
, "doublefloat") == 0)
16343 mips_opts
.single_float
= 0;
16344 else if (strcmp (name
, "mips16") == 0
16345 || strcmp (name
, "MIPS-16") == 0)
16347 if (mips_opts
.micromips
== 1)
16348 as_fatal (_("`mips16' cannot be used with `micromips'"));
16349 mips_opts
.mips16
= 1;
16351 else if (strcmp (name
, "nomips16") == 0
16352 || strcmp (name
, "noMIPS-16") == 0)
16353 mips_opts
.mips16
= 0;
16354 else if (strcmp (name
, "micromips") == 0)
16356 if (mips_opts
.mips16
== 1)
16357 as_fatal (_("`micromips' cannot be used with `mips16'"));
16358 mips_opts
.micromips
= 1;
16360 else if (strcmp (name
, "nomicromips") == 0)
16361 mips_opts
.micromips
= 0;
16362 else if (strcmp (name
, "smartmips") == 0)
16364 if (!ISA_SUPPORTS_SMARTMIPS
)
16365 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16366 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16367 mips_opts
.ase_smartmips
= 1;
16369 else if (strcmp (name
, "nosmartmips") == 0)
16370 mips_opts
.ase_smartmips
= 0;
16371 else if (strcmp (name
, "mips3d") == 0)
16372 mips_opts
.ase_mips3d
= 1;
16373 else if (strcmp (name
, "nomips3d") == 0)
16374 mips_opts
.ase_mips3d
= 0;
16375 else if (strcmp (name
, "mdmx") == 0)
16376 mips_opts
.ase_mdmx
= 1;
16377 else if (strcmp (name
, "nomdmx") == 0)
16378 mips_opts
.ase_mdmx
= 0;
16379 else if (strcmp (name
, "dsp") == 0)
16381 if (!ISA_SUPPORTS_DSP_ASE
)
16382 as_warn (_("%s ISA does not support DSP ASE"),
16383 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16384 mips_opts
.ase_dsp
= 1;
16385 mips_opts
.ase_dspr2
= 0;
16387 else if (strcmp (name
, "nodsp") == 0)
16389 mips_opts
.ase_dsp
= 0;
16390 mips_opts
.ase_dspr2
= 0;
16392 else if (strcmp (name
, "dspr2") == 0)
16394 if (!ISA_SUPPORTS_DSPR2_ASE
)
16395 as_warn (_("%s ISA does not support DSP R2 ASE"),
16396 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16397 mips_opts
.ase_dspr2
= 1;
16398 mips_opts
.ase_dsp
= 1;
16400 else if (strcmp (name
, "nodspr2") == 0)
16402 mips_opts
.ase_dspr2
= 0;
16403 mips_opts
.ase_dsp
= 0;
16405 else if (strcmp (name
, "mt") == 0)
16407 if (!ISA_SUPPORTS_MT_ASE
)
16408 as_warn (_("%s ISA does not support MT ASE"),
16409 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16410 mips_opts
.ase_mt
= 1;
16412 else if (strcmp (name
, "nomt") == 0)
16413 mips_opts
.ase_mt
= 0;
16414 else if (strcmp (name
, "mcu") == 0)
16415 mips_opts
.ase_mcu
= 1;
16416 else if (strcmp (name
, "nomcu") == 0)
16417 mips_opts
.ase_mcu
= 0;
16418 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16422 /* Permit the user to change the ISA and architecture on the fly.
16423 Needless to say, misuse can cause serious problems. */
16424 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16427 mips_opts
.isa
= file_mips_isa
;
16428 mips_opts
.arch
= file_mips_arch
;
16430 else if (strncmp (name
, "arch=", 5) == 0)
16432 const struct mips_cpu_info
*p
;
16434 p
= mips_parse_cpu("internal use", name
+ 5);
16436 as_bad (_("unknown architecture %s"), name
+ 5);
16439 mips_opts
.arch
= p
->cpu
;
16440 mips_opts
.isa
= p
->isa
;
16443 else if (strncmp (name
, "mips", 4) == 0)
16445 const struct mips_cpu_info
*p
;
16447 p
= mips_parse_cpu("internal use", name
);
16449 as_bad (_("unknown ISA level %s"), name
+ 4);
16452 mips_opts
.arch
= p
->cpu
;
16453 mips_opts
.isa
= p
->isa
;
16457 as_bad (_("unknown ISA or architecture %s"), name
);
16459 switch (mips_opts
.isa
)
16467 mips_opts
.gp32
= 1;
16468 mips_opts
.fp32
= 1;
16475 mips_opts
.gp32
= 0;
16476 if (mips_opts
.arch
== CPU_R5900
)
16478 mips_opts
.fp32
= 1;
16482 mips_opts
.fp32
= 0;
16486 as_bad (_("unknown ISA level %s"), name
+ 4);
16491 mips_opts
.gp32
= file_mips_gp32
;
16492 mips_opts
.fp32
= file_mips_fp32
;
16495 else if (strcmp (name
, "autoextend") == 0)
16496 mips_opts
.noautoextend
= 0;
16497 else if (strcmp (name
, "noautoextend") == 0)
16498 mips_opts
.noautoextend
= 1;
16499 else if (strcmp (name
, "push") == 0)
16501 struct mips_option_stack
*s
;
16503 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16504 s
->next
= mips_opts_stack
;
16505 s
->options
= mips_opts
;
16506 mips_opts_stack
= s
;
16508 else if (strcmp (name
, "pop") == 0)
16510 struct mips_option_stack
*s
;
16512 s
= mips_opts_stack
;
16514 as_bad (_(".set pop with no .set push"));
16517 /* If we're changing the reorder mode we need to handle
16518 delay slots correctly. */
16519 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16520 start_noreorder ();
16521 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16524 mips_opts
= s
->options
;
16525 mips_opts_stack
= s
->next
;
16529 else if (strcmp (name
, "sym32") == 0)
16530 mips_opts
.sym32
= TRUE
;
16531 else if (strcmp (name
, "nosym32") == 0)
16532 mips_opts
.sym32
= FALSE
;
16533 else if (strchr (name
, ','))
16535 /* Generic ".set" directive; use the generic handler. */
16536 *input_line_pointer
= ch
;
16537 input_line_pointer
= name
;
16543 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16545 *input_line_pointer
= ch
;
16546 demand_empty_rest_of_line ();
16549 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16550 .option pic2. It means to generate SVR4 PIC calls. */
16553 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16555 mips_pic
= SVR4_PIC
;
16556 mips_abicalls
= TRUE
;
16558 if (g_switch_seen
&& g_switch_value
!= 0)
16559 as_warn (_("-G may not be used with SVR4 PIC code"));
16560 g_switch_value
= 0;
16562 bfd_set_gp_size (stdoutput
, 0);
16563 demand_empty_rest_of_line ();
16566 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16567 PIC code. It sets the $gp register for the function based on the
16568 function address, which is in the register named in the argument.
16569 This uses a relocation against _gp_disp, which is handled specially
16570 by the linker. The result is:
16571 lui $gp,%hi(_gp_disp)
16572 addiu $gp,$gp,%lo(_gp_disp)
16573 addu $gp,$gp,.cpload argument
16574 The .cpload argument is normally $25 == $t9.
16576 The -mno-shared option changes this to:
16577 lui $gp,%hi(__gnu_local_gp)
16578 addiu $gp,$gp,%lo(__gnu_local_gp)
16579 and the argument is ignored. This saves an instruction, but the
16580 resulting code is not position independent; it uses an absolute
16581 address for __gnu_local_gp. Thus code assembled with -mno-shared
16582 can go into an ordinary executable, but not into a shared library. */
16585 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16591 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16592 .cpload is ignored. */
16593 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16599 if (mips_opts
.mips16
)
16601 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16602 ignore_rest_of_line ();
16606 /* .cpload should be in a .set noreorder section. */
16607 if (mips_opts
.noreorder
== 0)
16608 as_warn (_(".cpload not in noreorder section"));
16610 reg
= tc_get_register (0);
16612 /* If we need to produce a 64-bit address, we are better off using
16613 the default instruction sequence. */
16614 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16616 ex
.X_op
= O_symbol
;
16617 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16619 ex
.X_op_symbol
= NULL
;
16620 ex
.X_add_number
= 0;
16622 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16623 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16626 macro_build_lui (&ex
, mips_gp_register
);
16627 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16628 mips_gp_register
, BFD_RELOC_LO16
);
16630 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16631 mips_gp_register
, reg
);
16634 demand_empty_rest_of_line ();
16637 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16638 .cpsetup $reg1, offset|$reg2, label
16640 If offset is given, this results in:
16641 sd $gp, offset($sp)
16642 lui $gp, %hi(%neg(%gp_rel(label)))
16643 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16644 daddu $gp, $gp, $reg1
16646 If $reg2 is given, this results in:
16647 daddu $reg2, $gp, $0
16648 lui $gp, %hi(%neg(%gp_rel(label)))
16649 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16650 daddu $gp, $gp, $reg1
16651 $reg1 is normally $25 == $t9.
16653 The -mno-shared option replaces the last three instructions with
16655 addiu $gp,$gp,%lo(_gp) */
16658 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16660 expressionS ex_off
;
16661 expressionS ex_sym
;
16664 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16665 We also need NewABI support. */
16666 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16672 if (mips_opts
.mips16
)
16674 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16675 ignore_rest_of_line ();
16679 reg1
= tc_get_register (0);
16680 SKIP_WHITESPACE ();
16681 if (*input_line_pointer
!= ',')
16683 as_bad (_("missing argument separator ',' for .cpsetup"));
16687 ++input_line_pointer
;
16688 SKIP_WHITESPACE ();
16689 if (*input_line_pointer
== '$')
16691 mips_cpreturn_register
= tc_get_register (0);
16692 mips_cpreturn_offset
= -1;
16696 mips_cpreturn_offset
= get_absolute_expression ();
16697 mips_cpreturn_register
= -1;
16699 SKIP_WHITESPACE ();
16700 if (*input_line_pointer
!= ',')
16702 as_bad (_("missing argument separator ',' for .cpsetup"));
16706 ++input_line_pointer
;
16707 SKIP_WHITESPACE ();
16708 expression (&ex_sym
);
16711 if (mips_cpreturn_register
== -1)
16713 ex_off
.X_op
= O_constant
;
16714 ex_off
.X_add_symbol
= NULL
;
16715 ex_off
.X_op_symbol
= NULL
;
16716 ex_off
.X_add_number
= mips_cpreturn_offset
;
16718 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16719 BFD_RELOC_LO16
, SP
);
16722 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16723 mips_gp_register
, 0);
16725 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16727 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16728 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16731 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16732 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16733 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16735 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16736 mips_gp_register
, reg1
);
16742 ex
.X_op
= O_symbol
;
16743 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16744 ex
.X_op_symbol
= NULL
;
16745 ex
.X_add_number
= 0;
16747 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16748 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16750 macro_build_lui (&ex
, mips_gp_register
);
16751 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16752 mips_gp_register
, BFD_RELOC_LO16
);
16757 demand_empty_rest_of_line ();
16761 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16763 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16764 .cplocal is ignored. */
16765 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16771 if (mips_opts
.mips16
)
16773 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16774 ignore_rest_of_line ();
16778 mips_gp_register
= tc_get_register (0);
16779 demand_empty_rest_of_line ();
16782 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16783 offset from $sp. The offset is remembered, and after making a PIC
16784 call $gp is restored from that location. */
16787 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16791 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16792 .cprestore is ignored. */
16793 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16799 if (mips_opts
.mips16
)
16801 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16802 ignore_rest_of_line ();
16806 mips_cprestore_offset
= get_absolute_expression ();
16807 mips_cprestore_valid
= 1;
16809 ex
.X_op
= O_constant
;
16810 ex
.X_add_symbol
= NULL
;
16811 ex
.X_op_symbol
= NULL
;
16812 ex
.X_add_number
= mips_cprestore_offset
;
16815 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16816 SP
, HAVE_64BIT_ADDRESSES
);
16819 demand_empty_rest_of_line ();
16822 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16823 was given in the preceding .cpsetup, it results in:
16824 ld $gp, offset($sp)
16826 If a register $reg2 was given there, it results in:
16827 daddu $gp, $reg2, $0 */
16830 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16834 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16835 We also need NewABI support. */
16836 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16842 if (mips_opts
.mips16
)
16844 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16845 ignore_rest_of_line ();
16850 if (mips_cpreturn_register
== -1)
16852 ex
.X_op
= O_constant
;
16853 ex
.X_add_symbol
= NULL
;
16854 ex
.X_op_symbol
= NULL
;
16855 ex
.X_add_number
= mips_cpreturn_offset
;
16857 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16860 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16861 mips_cpreturn_register
, 0);
16864 demand_empty_rest_of_line ();
16867 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16868 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16869 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16870 debug information or MIPS16 TLS. */
16873 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16874 bfd_reloc_code_real_type rtype
)
16881 if (ex
.X_op
!= O_symbol
)
16883 as_bad (_("Unsupported use of %s"), dirstr
);
16884 ignore_rest_of_line ();
16887 p
= frag_more (bytes
);
16888 md_number_to_chars (p
, 0, bytes
);
16889 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16890 demand_empty_rest_of_line ();
16891 mips_clear_insn_labels ();
16894 /* Handle .dtprelword. */
16897 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16899 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16902 /* Handle .dtpreldword. */
16905 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16907 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16910 /* Handle .tprelword. */
16913 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16915 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16918 /* Handle .tpreldword. */
16921 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16923 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16926 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16927 code. It sets the offset to use in gp_rel relocations. */
16930 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16932 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16933 We also need NewABI support. */
16934 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16940 mips_gprel_offset
= get_absolute_expression ();
16942 demand_empty_rest_of_line ();
16945 /* Handle the .gpword pseudo-op. This is used when generating PIC
16946 code. It generates a 32 bit GP relative reloc. */
16949 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16951 segment_info_type
*si
;
16952 struct insn_label_list
*l
;
16956 /* When not generating PIC code, this is treated as .word. */
16957 if (mips_pic
!= SVR4_PIC
)
16963 si
= seg_info (now_seg
);
16964 l
= si
->label_list
;
16965 mips_emit_delays ();
16967 mips_align (2, 0, l
);
16970 mips_clear_insn_labels ();
16972 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16974 as_bad (_("Unsupported use of .gpword"));
16975 ignore_rest_of_line ();
16979 md_number_to_chars (p
, 0, 4);
16980 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16981 BFD_RELOC_GPREL32
);
16983 demand_empty_rest_of_line ();
16987 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16989 segment_info_type
*si
;
16990 struct insn_label_list
*l
;
16994 /* When not generating PIC code, this is treated as .dword. */
16995 if (mips_pic
!= SVR4_PIC
)
17001 si
= seg_info (now_seg
);
17002 l
= si
->label_list
;
17003 mips_emit_delays ();
17005 mips_align (3, 0, l
);
17008 mips_clear_insn_labels ();
17010 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17012 as_bad (_("Unsupported use of .gpdword"));
17013 ignore_rest_of_line ();
17017 md_number_to_chars (p
, 0, 8);
17018 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17019 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17021 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17022 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17023 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17025 demand_empty_rest_of_line ();
17028 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17029 tables in SVR4 PIC code. */
17032 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17036 /* This is ignored when not generating SVR4 PIC code. */
17037 if (mips_pic
!= SVR4_PIC
)
17043 /* Add $gp to the register named as an argument. */
17045 reg
= tc_get_register (0);
17046 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17049 demand_empty_rest_of_line ();
17052 /* Handle the .insn pseudo-op. This marks instruction labels in
17053 mips16/micromips mode. This permits the linker to handle them specially,
17054 such as generating jalx instructions when needed. We also make
17055 them odd for the duration of the assembly, in order to generate the
17056 right sort of code. We will make them even in the adjust_symtab
17057 routine, while leaving them marked. This is convenient for the
17058 debugger and the disassembler. The linker knows to make them odd
17062 s_insn (int ignore ATTRIBUTE_UNUSED
)
17064 mips_mark_labels ();
17066 demand_empty_rest_of_line ();
17069 /* Handle a .stabn directive. We need these in order to mark a label
17070 as being a mips16 text label correctly. Sometimes the compiler
17071 will emit a label, followed by a .stabn, and then switch sections.
17072 If the label and .stabn are in mips16 mode, then the label is
17073 really a mips16 text label. */
17076 s_mips_stab (int type
)
17079 mips_mark_labels ();
17084 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17087 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17094 name
= input_line_pointer
;
17095 c
= get_symbol_end ();
17096 symbolP
= symbol_find_or_make (name
);
17097 S_SET_WEAK (symbolP
);
17098 *input_line_pointer
= c
;
17100 SKIP_WHITESPACE ();
17102 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17104 if (S_IS_DEFINED (symbolP
))
17106 as_bad (_("ignoring attempt to redefine symbol %s"),
17107 S_GET_NAME (symbolP
));
17108 ignore_rest_of_line ();
17112 if (*input_line_pointer
== ',')
17114 ++input_line_pointer
;
17115 SKIP_WHITESPACE ();
17119 if (exp
.X_op
!= O_symbol
)
17121 as_bad (_("bad .weakext directive"));
17122 ignore_rest_of_line ();
17125 symbol_set_value_expression (symbolP
, &exp
);
17128 demand_empty_rest_of_line ();
17131 /* Parse a register string into a number. Called from the ECOFF code
17132 to parse .frame. The argument is non-zero if this is the frame
17133 register, so that we can record it in mips_frame_reg. */
17136 tc_get_register (int frame
)
17140 SKIP_WHITESPACE ();
17141 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17145 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17146 mips_frame_reg_valid
= 1;
17147 mips_cprestore_valid
= 0;
17153 md_section_align (asection
*seg
, valueT addr
)
17155 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17159 /* We don't need to align ELF sections to the full alignment.
17160 However, Irix 5 may prefer that we align them at least to a 16
17161 byte boundary. We don't bother to align the sections if we
17162 are targeted for an embedded system. */
17163 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17169 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17172 /* Utility routine, called from above as well. If called while the
17173 input file is still being read, it's only an approximation. (For
17174 example, a symbol may later become defined which appeared to be
17175 undefined earlier.) */
17178 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17183 if (g_switch_value
> 0)
17185 const char *symname
;
17188 /* Find out whether this symbol can be referenced off the $gp
17189 register. It can be if it is smaller than the -G size or if
17190 it is in the .sdata or .sbss section. Certain symbols can
17191 not be referenced off the $gp, although it appears as though
17193 symname
= S_GET_NAME (sym
);
17194 if (symname
!= (const char *) NULL
17195 && (strcmp (symname
, "eprol") == 0
17196 || strcmp (symname
, "etext") == 0
17197 || strcmp (symname
, "_gp") == 0
17198 || strcmp (symname
, "edata") == 0
17199 || strcmp (symname
, "_fbss") == 0
17200 || strcmp (symname
, "_fdata") == 0
17201 || strcmp (symname
, "_ftext") == 0
17202 || strcmp (symname
, "end") == 0
17203 || strcmp (symname
, "_gp_disp") == 0))
17205 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17207 #ifndef NO_ECOFF_DEBUGGING
17208 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17209 && (symbol_get_obj (sym
)->ecoff_extern_size
17210 <= g_switch_value
))
17212 /* We must defer this decision until after the whole
17213 file has been read, since there might be a .extern
17214 after the first use of this symbol. */
17215 || (before_relaxing
17216 #ifndef NO_ECOFF_DEBUGGING
17217 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17219 && S_GET_VALUE (sym
) == 0)
17220 || (S_GET_VALUE (sym
) != 0
17221 && S_GET_VALUE (sym
) <= g_switch_value
)))
17225 const char *segname
;
17227 segname
= segment_name (S_GET_SEGMENT (sym
));
17228 gas_assert (strcmp (segname
, ".lit8") != 0
17229 && strcmp (segname
, ".lit4") != 0);
17230 change
= (strcmp (segname
, ".sdata") != 0
17231 && strcmp (segname
, ".sbss") != 0
17232 && strncmp (segname
, ".sdata.", 7) != 0
17233 && strncmp (segname
, ".sbss.", 6) != 0
17234 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17235 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17240 /* We are not optimizing for the $gp register. */
17245 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17248 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17252 /* Handle the case of a symbol equated to another symbol. */
17253 while (symbol_equated_reloc_p (sym
))
17257 /* It's possible to get a loop here in a badly written program. */
17258 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17264 if (symbol_section_p (sym
))
17267 symsec
= S_GET_SEGMENT (sym
);
17269 /* This must duplicate the test in adjust_reloc_syms. */
17270 return (!bfd_is_und_section (symsec
)
17271 && !bfd_is_abs_section (symsec
)
17272 && !bfd_is_com_section (symsec
)
17273 && !s_is_linkonce (sym
, segtype
)
17275 /* A global or weak symbol is treated as external. */
17276 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17282 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17283 extended opcode. SEC is the section the frag is in. */
17286 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17289 const struct mips16_immed_operand
*op
;
17291 int mintiny
, maxtiny
;
17295 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17297 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17300 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17301 op
= mips16_immed_operands
;
17302 while (op
->type
!= type
)
17305 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17310 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17313 maxtiny
= 1 << op
->nbits
;
17318 maxtiny
= (1 << op
->nbits
) - 1;
17323 mintiny
= - (1 << (op
->nbits
- 1));
17324 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17327 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17328 val
= S_GET_VALUE (fragp
->fr_symbol
);
17329 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17335 /* We won't have the section when we are called from
17336 mips_relax_frag. However, we will always have been called
17337 from md_estimate_size_before_relax first. If this is a
17338 branch to a different section, we mark it as such. If SEC is
17339 NULL, and the frag is not marked, then it must be a branch to
17340 the same section. */
17343 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17348 /* Must have been called from md_estimate_size_before_relax. */
17351 fragp
->fr_subtype
=
17352 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17354 /* FIXME: We should support this, and let the linker
17355 catch branches and loads that are out of range. */
17356 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17357 _("unsupported PC relative reference to different section"));
17361 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17362 /* Assume non-extended on the first relaxation pass.
17363 The address we have calculated will be bogus if this is
17364 a forward branch to another frag, as the forward frag
17365 will have fr_address == 0. */
17369 /* In this case, we know for sure that the symbol fragment is in
17370 the same section. If the relax_marker of the symbol fragment
17371 differs from the relax_marker of this fragment, we have not
17372 yet adjusted the symbol fragment fr_address. We want to add
17373 in STRETCH in order to get a better estimate of the address.
17374 This particularly matters because of the shift bits. */
17376 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17380 /* Adjust stretch for any alignment frag. Note that if have
17381 been expanding the earlier code, the symbol may be
17382 defined in what appears to be an earlier frag. FIXME:
17383 This doesn't handle the fr_subtype field, which specifies
17384 a maximum number of bytes to skip when doing an
17386 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17388 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17391 stretch
= - ((- stretch
)
17392 & ~ ((1 << (int) f
->fr_offset
) - 1));
17394 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17403 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17405 /* The base address rules are complicated. The base address of
17406 a branch is the following instruction. The base address of a
17407 PC relative load or add is the instruction itself, but if it
17408 is in a delay slot (in which case it can not be extended) use
17409 the address of the instruction whose delay slot it is in. */
17410 if (type
== 'p' || type
== 'q')
17414 /* If we are currently assuming that this frag should be
17415 extended, then, the current address is two bytes
17417 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17420 /* Ignore the low bit in the target, since it will be set
17421 for a text label. */
17422 if ((val
& 1) != 0)
17425 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17427 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17430 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17432 /* Branch offsets have an implicit 0 in the lowest bit. */
17433 if (type
== 'p' || type
== 'q')
17436 /* If any of the shifted bits are set, we must use an extended
17437 opcode. If the address depends on the size of this
17438 instruction, this can lead to a loop, so we arrange to always
17439 use an extended opcode. We only check this when we are in
17440 the main relaxation loop, when SEC is NULL. */
17441 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17443 fragp
->fr_subtype
=
17444 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17448 /* If we are about to mark a frag as extended because the value
17449 is precisely maxtiny + 1, then there is a chance of an
17450 infinite loop as in the following code:
17455 In this case when the la is extended, foo is 0x3fc bytes
17456 away, so the la can be shrunk, but then foo is 0x400 away, so
17457 the la must be extended. To avoid this loop, we mark the
17458 frag as extended if it was small, and is about to become
17459 extended with a value of maxtiny + 1. */
17460 if (val
== ((maxtiny
+ 1) << op
->shift
)
17461 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17464 fragp
->fr_subtype
=
17465 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17469 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17470 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17472 if ((val
& ((1 << op
->shift
) - 1)) != 0
17473 || val
< (mintiny
<< op
->shift
)
17474 || val
> (maxtiny
<< op
->shift
))
17480 /* Compute the length of a branch sequence, and adjust the
17481 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17482 worst-case length is computed, with UPDATE being used to indicate
17483 whether an unconditional (-1), branch-likely (+1) or regular (0)
17484 branch is to be computed. */
17486 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17488 bfd_boolean toofar
;
17492 && S_IS_DEFINED (fragp
->fr_symbol
)
17493 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17498 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17500 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17504 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17507 /* If the symbol is not defined or it's in a different segment,
17508 assume the user knows what's going on and emit a short
17514 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17516 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17517 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17518 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17519 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17525 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17528 if (mips_pic
!= NO_PIC
)
17530 /* Additional space for PIC loading of target address. */
17532 if (mips_opts
.isa
== ISA_MIPS1
)
17533 /* Additional space for $at-stabilizing nop. */
17537 /* If branch is conditional. */
17538 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17545 /* Compute the length of a branch sequence, and adjust the
17546 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17547 worst-case length is computed, with UPDATE being used to indicate
17548 whether an unconditional (-1), or regular (0) branch is to be
17552 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17554 bfd_boolean toofar
;
17558 && S_IS_DEFINED (fragp
->fr_symbol
)
17559 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17564 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17565 /* Ignore the low bit in the target, since it will be set
17566 for a text label. */
17567 if ((val
& 1) != 0)
17570 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17574 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17577 /* If the symbol is not defined or it's in a different segment,
17578 assume the user knows what's going on and emit a short
17584 if (fragp
&& update
17585 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17586 fragp
->fr_subtype
= (toofar
17587 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17588 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17593 bfd_boolean compact_known
= fragp
!= NULL
;
17594 bfd_boolean compact
= FALSE
;
17595 bfd_boolean uncond
;
17598 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17600 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17602 uncond
= update
< 0;
17604 /* If label is out of range, we turn branch <br>:
17606 <br> label # 4 bytes
17612 nop # 2 bytes if compact && !PIC
17615 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17618 /* If assembling PIC code, we further turn:
17624 lw/ld at, %got(label)(gp) # 4 bytes
17625 d/addiu at, %lo(label) # 4 bytes
17628 if (mips_pic
!= NO_PIC
)
17631 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17633 <brneg> 0f # 4 bytes
17634 nop # 2 bytes if !compact
17637 length
+= (compact_known
&& compact
) ? 4 : 6;
17643 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17644 bit accordingly. */
17647 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17649 bfd_boolean toofar
;
17652 && S_IS_DEFINED (fragp
->fr_symbol
)
17653 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17659 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17660 /* Ignore the low bit in the target, since it will be set
17661 for a text label. */
17662 if ((val
& 1) != 0)
17665 /* Assume this is a 2-byte branch. */
17666 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17668 /* We try to avoid the infinite loop by not adding 2 more bytes for
17673 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17675 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17676 else if (type
== 'E')
17677 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17682 /* If the symbol is not defined or it's in a different segment,
17683 we emit a normal 32-bit branch. */
17686 if (fragp
&& update
17687 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17689 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17690 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17698 /* Estimate the size of a frag before relaxing. Unless this is the
17699 mips16, we are not really relaxing here, and the final size is
17700 encoded in the subtype information. For the mips16, we have to
17701 decide whether we are using an extended opcode or not. */
17704 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17708 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17711 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17713 return fragp
->fr_var
;
17716 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17717 /* We don't want to modify the EXTENDED bit here; it might get us
17718 into infinite loops. We change it only in mips_relax_frag(). */
17719 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17721 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17725 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17726 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17727 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17728 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17729 fragp
->fr_var
= length
;
17734 if (mips_pic
== NO_PIC
)
17735 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17736 else if (mips_pic
== SVR4_PIC
)
17737 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17738 else if (mips_pic
== VXWORKS_PIC
)
17739 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17746 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17747 return -RELAX_FIRST (fragp
->fr_subtype
);
17750 return -RELAX_SECOND (fragp
->fr_subtype
);
17753 /* This is called to see whether a reloc against a defined symbol
17754 should be converted into a reloc against a section. */
17757 mips_fix_adjustable (fixS
*fixp
)
17759 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17760 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17763 if (fixp
->fx_addsy
== NULL
)
17766 /* If symbol SYM is in a mergeable section, relocations of the form
17767 SYM + 0 can usually be made section-relative. The mergeable data
17768 is then identified by the section offset rather than by the symbol.
17770 However, if we're generating REL LO16 relocations, the offset is split
17771 between the LO16 and parterning high part relocation. The linker will
17772 need to recalculate the complete offset in order to correctly identify
17775 The linker has traditionally not looked for the parterning high part
17776 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17777 placed anywhere. Rather than break backwards compatibility by changing
17778 this, it seems better not to force the issue, and instead keep the
17779 original symbol. This will work with either linker behavior. */
17780 if ((lo16_reloc_p (fixp
->fx_r_type
)
17781 || reloc_needs_lo_p (fixp
->fx_r_type
))
17782 && HAVE_IN_PLACE_ADDENDS
17783 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17786 /* There is no place to store an in-place offset for JALR relocations.
17787 Likewise an in-range offset of PC-relative relocations may overflow
17788 the in-place relocatable field if recalculated against the start
17789 address of the symbol's containing section. */
17790 if (HAVE_IN_PLACE_ADDENDS
17791 && (fixp
->fx_pcrel
|| jalr_reloc_p (fixp
->fx_r_type
)))
17795 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17796 to a floating-point stub. The same is true for non-R_MIPS16_26
17797 relocations against MIPS16 functions; in this case, the stub becomes
17798 the function's canonical address.
17800 Floating-point stubs are stored in unique .mips16.call.* or
17801 .mips16.fn.* sections. If a stub T for function F is in section S,
17802 the first relocation in section S must be against F; this is how the
17803 linker determines the target function. All relocations that might
17804 resolve to T must also be against F. We therefore have the following
17805 restrictions, which are given in an intentionally-redundant way:
17807 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17810 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17811 if that stub might be used.
17813 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17816 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17817 that stub might be used.
17819 There is a further restriction:
17821 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17822 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17823 targets with in-place addends; the relocation field cannot
17824 encode the low bit.
17826 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17827 against a MIPS16 symbol. We deal with (5) by by not reducing any
17828 such relocations on REL targets.
17830 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17831 relocation against some symbol R, no relocation against R may be
17832 reduced. (Note that this deals with (2) as well as (1) because
17833 relocations against global symbols will never be reduced on ELF
17834 targets.) This approach is a little simpler than trying to detect
17835 stub sections, and gives the "all or nothing" per-symbol consistency
17836 that we have for MIPS16 symbols. */
17838 && fixp
->fx_subsy
== NULL
17839 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17840 || *symbol_get_tc (fixp
->fx_addsy
)
17841 || (HAVE_IN_PLACE_ADDENDS
17842 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17843 && jmp_reloc_p (fixp
->fx_r_type
))))
17850 /* Translate internal representation of relocation info to BFD target
17854 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17856 static arelent
*retval
[4];
17858 bfd_reloc_code_real_type code
;
17860 memset (retval
, 0, sizeof(retval
));
17861 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17862 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17863 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17864 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17866 if (fixp
->fx_pcrel
)
17868 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17869 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17870 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17871 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17873 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17874 Relocations want only the symbol offset. */
17875 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17878 /* A gruesome hack which is a result of the gruesome gas
17879 reloc handling. What's worse, for COFF (as opposed to
17880 ECOFF), we might need yet another copy of reloc->address.
17881 See bfd_install_relocation. */
17882 reloc
->addend
+= reloc
->address
;
17886 reloc
->addend
= fixp
->fx_addnumber
;
17888 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17889 entry to be used in the relocation's section offset. */
17890 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17892 reloc
->address
= reloc
->addend
;
17896 code
= fixp
->fx_r_type
;
17898 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17899 if (reloc
->howto
== NULL
)
17901 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17902 _("Can not represent %s relocation in this object file format"),
17903 bfd_get_reloc_code_name (code
));
17910 /* Relax a machine dependent frag. This returns the amount by which
17911 the current size of the frag should change. */
17914 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17916 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17918 offsetT old_var
= fragp
->fr_var
;
17920 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17922 return fragp
->fr_var
- old_var
;
17925 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17927 offsetT old_var
= fragp
->fr_var
;
17928 offsetT new_var
= 4;
17930 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17931 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17932 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17933 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17934 fragp
->fr_var
= new_var
;
17936 return new_var
- old_var
;
17939 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17942 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17944 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17946 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17951 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17953 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17960 /* Convert a machine dependent frag. */
17963 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17965 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17968 unsigned long insn
;
17972 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17973 insn
= read_insn (buf
);
17975 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17977 /* We generate a fixup instead of applying it right now
17978 because, if there are linker relaxations, we're going to
17979 need the relocations. */
17980 exp
.X_op
= O_symbol
;
17981 exp
.X_add_symbol
= fragp
->fr_symbol
;
17982 exp
.X_add_number
= fragp
->fr_offset
;
17984 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17985 BFD_RELOC_16_PCREL_S2
);
17986 fixp
->fx_file
= fragp
->fr_file
;
17987 fixp
->fx_line
= fragp
->fr_line
;
17989 buf
= write_insn (buf
, insn
);
17995 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17996 _("Relaxed out-of-range branch into a jump"));
17998 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18001 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18003 /* Reverse the branch. */
18004 switch ((insn
>> 28) & 0xf)
18007 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
18008 have the condition reversed by tweaking a single
18009 bit, and their opcodes all have 0x4???????. */
18010 gas_assert ((insn
& 0xf1000000) == 0x41000000);
18011 insn
^= 0x00010000;
18015 /* bltz 0x04000000 bgez 0x04010000
18016 bltzal 0x04100000 bgezal 0x04110000 */
18017 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18018 insn
^= 0x00010000;
18022 /* beq 0x10000000 bne 0x14000000
18023 blez 0x18000000 bgtz 0x1c000000 */
18024 insn
^= 0x04000000;
18032 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18034 /* Clear the and-link bit. */
18035 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18037 /* bltzal 0x04100000 bgezal 0x04110000
18038 bltzall 0x04120000 bgezall 0x04130000 */
18039 insn
&= ~0x00100000;
18042 /* Branch over the branch (if the branch was likely) or the
18043 full jump (not likely case). Compute the offset from the
18044 current instruction to branch to. */
18045 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18049 /* How many bytes in instructions we've already emitted? */
18050 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18051 /* How many bytes in instructions from here to the end? */
18052 i
= fragp
->fr_var
- i
;
18054 /* Convert to instruction count. */
18056 /* Branch counts from the next instruction. */
18059 /* Branch over the jump. */
18060 buf
= write_insn (buf
, insn
);
18063 buf
= write_insn (buf
, 0);
18065 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18067 /* beql $0, $0, 2f */
18069 /* Compute the PC offset from the current instruction to
18070 the end of the variable frag. */
18071 /* How many bytes in instructions we've already emitted? */
18072 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18073 /* How many bytes in instructions from here to the end? */
18074 i
= fragp
->fr_var
- i
;
18075 /* Convert to instruction count. */
18077 /* Don't decrement i, because we want to branch over the
18081 buf
= write_insn (buf
, insn
);
18082 buf
= write_insn (buf
, 0);
18086 if (mips_pic
== NO_PIC
)
18089 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18090 ? 0x0c000000 : 0x08000000);
18091 exp
.X_op
= O_symbol
;
18092 exp
.X_add_symbol
= fragp
->fr_symbol
;
18093 exp
.X_add_number
= fragp
->fr_offset
;
18095 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18096 FALSE
, BFD_RELOC_MIPS_JMP
);
18097 fixp
->fx_file
= fragp
->fr_file
;
18098 fixp
->fx_line
= fragp
->fr_line
;
18100 buf
= write_insn (buf
, insn
);
18104 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18106 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18107 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18108 insn
|= at
<< OP_SH_RT
;
18109 exp
.X_op
= O_symbol
;
18110 exp
.X_add_symbol
= fragp
->fr_symbol
;
18111 exp
.X_add_number
= fragp
->fr_offset
;
18113 if (fragp
->fr_offset
)
18115 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18116 exp
.X_add_number
= 0;
18119 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18120 FALSE
, BFD_RELOC_MIPS_GOT16
);
18121 fixp
->fx_file
= fragp
->fr_file
;
18122 fixp
->fx_line
= fragp
->fr_line
;
18124 buf
= write_insn (buf
, insn
);
18126 if (mips_opts
.isa
== ISA_MIPS1
)
18128 buf
= write_insn (buf
, 0);
18130 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18131 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18132 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18134 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18135 FALSE
, BFD_RELOC_LO16
);
18136 fixp
->fx_file
= fragp
->fr_file
;
18137 fixp
->fx_line
= fragp
->fr_line
;
18139 buf
= write_insn (buf
, insn
);
18142 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18146 insn
|= at
<< OP_SH_RS
;
18148 buf
= write_insn (buf
, insn
);
18152 fragp
->fr_fix
+= fragp
->fr_var
;
18153 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18157 /* Relax microMIPS branches. */
18158 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18160 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18161 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18162 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18163 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18164 bfd_boolean short_ds
;
18165 unsigned long insn
;
18169 exp
.X_op
= O_symbol
;
18170 exp
.X_add_symbol
= fragp
->fr_symbol
;
18171 exp
.X_add_number
= fragp
->fr_offset
;
18173 fragp
->fr_fix
+= fragp
->fr_var
;
18175 /* Handle 16-bit branches that fit or are forced to fit. */
18176 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18178 /* We generate a fixup instead of applying it right now,
18179 because if there is linker relaxation, we're going to
18180 need the relocations. */
18182 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18183 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18184 else if (type
== 'E')
18185 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18186 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18190 fixp
->fx_file
= fragp
->fr_file
;
18191 fixp
->fx_line
= fragp
->fr_line
;
18193 /* These relocations can have an addend that won't fit in
18195 fixp
->fx_no_overflow
= 1;
18200 /* Handle 32-bit branches that fit or are forced to fit. */
18201 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18202 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18204 /* We generate a fixup instead of applying it right now,
18205 because if there is linker relaxation, we're going to
18206 need the relocations. */
18207 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18208 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18209 fixp
->fx_file
= fragp
->fr_file
;
18210 fixp
->fx_line
= fragp
->fr_line
;
18216 /* Relax 16-bit branches to 32-bit branches. */
18219 insn
= read_compressed_insn (buf
, 2);
18221 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18222 insn
= 0x94000000; /* beq */
18223 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18225 unsigned long regno
;
18227 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18228 regno
= micromips_to_32_reg_d_map
[regno
];
18229 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18230 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18235 /* Nothing else to do, just write it out. */
18236 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18237 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18239 buf
= write_compressed_insn (buf
, insn
, 4);
18240 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18245 insn
= read_compressed_insn (buf
, 4);
18247 /* Relax 32-bit branches to a sequence of instructions. */
18248 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18249 _("Relaxed out-of-range branch into a jump"));
18251 /* Set the short-delay-slot bit. */
18252 short_ds
= al
&& (insn
& 0x02000000) != 0;
18254 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18258 /* Reverse the branch. */
18259 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18260 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18261 insn
^= 0x20000000;
18262 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18263 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18264 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18265 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18266 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18267 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18268 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18269 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18270 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18271 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18272 insn
^= 0x00400000;
18273 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18274 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18275 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18276 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18277 insn
^= 0x00200000;
18283 /* Clear the and-link and short-delay-slot bits. */
18284 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18286 /* bltzal 0x40200000 bgezal 0x40600000 */
18287 /* bltzals 0x42200000 bgezals 0x42600000 */
18288 insn
&= ~0x02200000;
18291 /* Make a label at the end for use with the branch. */
18292 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18293 micromips_label_inc ();
18294 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18296 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18300 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18301 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18302 fixp
->fx_file
= fragp
->fr_file
;
18303 fixp
->fx_line
= fragp
->fr_line
;
18305 /* Branch over the jump. */
18306 buf
= write_compressed_insn (buf
, insn
, 4);
18309 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18312 if (mips_pic
== NO_PIC
)
18314 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18316 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18317 insn
= al
? jal
: 0xd4000000;
18319 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18320 BFD_RELOC_MICROMIPS_JMP
);
18321 fixp
->fx_file
= fragp
->fr_file
;
18322 fixp
->fx_line
= fragp
->fr_line
;
18324 buf
= write_compressed_insn (buf
, insn
, 4);
18327 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18331 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18332 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18333 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18335 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18336 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18337 insn
|= at
<< MICROMIPSOP_SH_RT
;
18339 if (exp
.X_add_number
)
18341 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18342 exp
.X_add_number
= 0;
18345 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18346 BFD_RELOC_MICROMIPS_GOT16
);
18347 fixp
->fx_file
= fragp
->fr_file
;
18348 fixp
->fx_line
= fragp
->fr_line
;
18350 buf
= write_compressed_insn (buf
, insn
, 4);
18352 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18353 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18354 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18356 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18357 BFD_RELOC_MICROMIPS_LO16
);
18358 fixp
->fx_file
= fragp
->fr_file
;
18359 fixp
->fx_line
= fragp
->fr_line
;
18361 buf
= write_compressed_insn (buf
, insn
, 4);
18363 /* jr/jrc/jalr/jalrs $at */
18364 insn
= al
? jalr
: jr
;
18365 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18367 buf
= write_compressed_insn (buf
, insn
, 2);
18370 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18374 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18377 const struct mips16_immed_operand
*op
;
18380 unsigned int user_length
, length
;
18381 unsigned long insn
;
18384 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18385 op
= mips16_immed_operands
;
18386 while (op
->type
!= type
)
18389 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18390 val
= resolve_symbol_value (fragp
->fr_symbol
);
18395 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18397 /* The rules for the base address of a PC relative reloc are
18398 complicated; see mips16_extended_frag. */
18399 if (type
== 'p' || type
== 'q')
18404 /* Ignore the low bit in the target, since it will be
18405 set for a text label. */
18406 if ((val
& 1) != 0)
18409 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18411 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18414 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18417 /* Make sure the section winds up with the alignment we have
18420 record_alignment (asec
, op
->shift
);
18424 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18425 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18426 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18427 _("extended instruction in delay slot"));
18429 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18431 insn
= read_compressed_insn (buf
, 2);
18433 insn
|= MIPS16_EXTEND
;
18435 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18437 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18442 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18443 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18445 length
= (ext
? 4 : 2);
18446 gas_assert (mips16_opcode_length (insn
) == length
);
18447 write_compressed_insn (buf
, insn
, length
);
18448 fragp
->fr_fix
+= length
;
18452 relax_substateT subtype
= fragp
->fr_subtype
;
18453 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18454 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18458 first
= RELAX_FIRST (subtype
);
18459 second
= RELAX_SECOND (subtype
);
18460 fixp
= (fixS
*) fragp
->fr_opcode
;
18462 /* If the delay slot chosen does not match the size of the instruction,
18463 then emit a warning. */
18464 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18465 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18470 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18471 | RELAX_DELAY_SLOT_SIZE_FIRST
18472 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18473 msg
= macro_warning (s
);
18475 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18479 /* Possibly emit a warning if we've chosen the longer option. */
18480 if (use_second
== second_longer
)
18486 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18487 msg
= macro_warning (s
);
18489 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18493 /* Go through all the fixups for the first sequence. Disable them
18494 (by marking them as done) if we're going to use the second
18495 sequence instead. */
18497 && fixp
->fx_frag
== fragp
18498 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18500 if (subtype
& RELAX_USE_SECOND
)
18502 fixp
= fixp
->fx_next
;
18505 /* Go through the fixups for the second sequence. Disable them if
18506 we're going to use the first sequence, otherwise adjust their
18507 addresses to account for the relaxation. */
18508 while (fixp
&& fixp
->fx_frag
== fragp
)
18510 if (subtype
& RELAX_USE_SECOND
)
18511 fixp
->fx_where
-= first
;
18514 fixp
= fixp
->fx_next
;
18517 /* Now modify the frag contents. */
18518 if (subtype
& RELAX_USE_SECOND
)
18522 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18523 memmove (start
, start
+ first
, second
);
18524 fragp
->fr_fix
-= first
;
18527 fragp
->fr_fix
-= second
;
18533 /* This function is called after the relocs have been generated.
18534 We've been storing mips16 text labels as odd. Here we convert them
18535 back to even for the convenience of the debugger. */
18538 mips_frob_file_after_relocs (void)
18541 unsigned int count
, i
;
18546 syms
= bfd_get_outsymbols (stdoutput
);
18547 count
= bfd_get_symcount (stdoutput
);
18548 for (i
= 0; i
< count
; i
++, syms
++)
18549 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18550 && ((*syms
)->value
& 1) != 0)
18552 (*syms
)->value
&= ~1;
18553 /* If the symbol has an odd size, it was probably computed
18554 incorrectly, so adjust that as well. */
18555 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18556 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18562 /* This function is called whenever a label is defined, including fake
18563 labels instantiated off the dot special symbol. It is used when
18564 handling branch delays; if a branch has a label, we assume we cannot
18565 move it. This also bumps the value of the symbol by 1 in compressed
18569 mips_record_label (symbolS
*sym
)
18571 segment_info_type
*si
= seg_info (now_seg
);
18572 struct insn_label_list
*l
;
18574 if (free_insn_labels
== NULL
)
18575 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18578 l
= free_insn_labels
;
18579 free_insn_labels
= l
->next
;
18583 l
->next
= si
->label_list
;
18584 si
->label_list
= l
;
18587 /* This function is called as tc_frob_label() whenever a label is defined
18588 and adds a DWARF-2 record we only want for true labels. */
18591 mips_define_label (symbolS
*sym
)
18593 mips_record_label (sym
);
18595 dwarf2_emit_label (sym
);
18599 /* This function is called by tc_new_dot_label whenever a new dot symbol
18603 mips_add_dot_label (symbolS
*sym
)
18605 mips_record_label (sym
);
18606 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18607 mips_compressed_mark_label (sym
);
18610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18612 /* Some special processing for a MIPS ELF file. */
18615 mips_elf_final_processing (void)
18617 /* Write out the register information. */
18618 if (mips_abi
!= N64_ABI
)
18622 s
.ri_gprmask
= mips_gprmask
;
18623 s
.ri_cprmask
[0] = mips_cprmask
[0];
18624 s
.ri_cprmask
[1] = mips_cprmask
[1];
18625 s
.ri_cprmask
[2] = mips_cprmask
[2];
18626 s
.ri_cprmask
[3] = mips_cprmask
[3];
18627 /* The gp_value field is set by the MIPS ELF backend. */
18629 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18630 ((Elf32_External_RegInfo
*)
18631 mips_regmask_frag
));
18635 Elf64_Internal_RegInfo s
;
18637 s
.ri_gprmask
= mips_gprmask
;
18639 s
.ri_cprmask
[0] = mips_cprmask
[0];
18640 s
.ri_cprmask
[1] = mips_cprmask
[1];
18641 s
.ri_cprmask
[2] = mips_cprmask
[2];
18642 s
.ri_cprmask
[3] = mips_cprmask
[3];
18643 /* The gp_value field is set by the MIPS ELF backend. */
18645 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18646 ((Elf64_External_RegInfo
*)
18647 mips_regmask_frag
));
18650 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18651 sort of BFD interface for this. */
18652 if (mips_any_noreorder
)
18653 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18654 if (mips_pic
!= NO_PIC
)
18656 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18657 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18660 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18662 /* Set MIPS ELF flags for ASEs. */
18663 /* We may need to define a new flag for DSP ASE, and set this flag when
18664 file_ase_dsp is true. */
18665 /* Same for DSP R2. */
18666 /* We may need to define a new flag for MT ASE, and set this flag when
18667 file_ase_mt is true. */
18668 if (file_ase_mips16
)
18669 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18670 if (file_ase_micromips
)
18671 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18672 #if 0 /* XXX FIXME */
18673 if (file_ase_mips3d
)
18674 elf_elfheader (stdoutput
)->e_flags
|= ???;
18677 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18679 /* Set the MIPS ELF ABI flags. */
18680 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18681 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18682 else if (mips_abi
== O64_ABI
)
18683 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18684 else if (mips_abi
== EABI_ABI
)
18686 if (!file_mips_gp32
)
18687 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18689 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18691 else if (mips_abi
== N32_ABI
)
18692 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18694 /* Nothing to do for N64_ABI. */
18696 if (mips_32bitmode
)
18697 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18699 #if 0 /* XXX FIXME */
18700 /* 32 bit code with 64 bit FP registers. */
18701 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18702 elf_elfheader (stdoutput
)->e_flags
|= ???;
18706 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18708 typedef struct proc
{
18710 symbolS
*func_end_sym
;
18711 unsigned long reg_mask
;
18712 unsigned long reg_offset
;
18713 unsigned long fpreg_mask
;
18714 unsigned long fpreg_offset
;
18715 unsigned long frame_offset
;
18716 unsigned long frame_reg
;
18717 unsigned long pc_reg
;
18720 static procS cur_proc
;
18721 static procS
*cur_proc_ptr
;
18722 static int numprocs
;
18724 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18725 as "2", and a normal nop as "0". */
18727 #define NOP_OPCODE_MIPS 0
18728 #define NOP_OPCODE_MIPS16 1
18729 #define NOP_OPCODE_MICROMIPS 2
18732 mips_nop_opcode (void)
18734 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18735 return NOP_OPCODE_MICROMIPS
;
18736 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18737 return NOP_OPCODE_MIPS16
;
18739 return NOP_OPCODE_MIPS
;
18742 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18743 32-bit microMIPS NOPs here (if applicable). */
18746 mips_handle_align (fragS
*fragp
)
18750 int bytes
, size
, excess
;
18753 if (fragp
->fr_type
!= rs_align_code
)
18756 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18758 switch (nop_opcode
)
18760 case NOP_OPCODE_MICROMIPS
:
18761 opcode
= micromips_nop32_insn
.insn_opcode
;
18764 case NOP_OPCODE_MIPS16
:
18765 opcode
= mips16_nop_insn
.insn_opcode
;
18768 case NOP_OPCODE_MIPS
:
18770 opcode
= nop_insn
.insn_opcode
;
18775 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18776 excess
= bytes
% size
;
18778 /* Handle the leading part if we're not inserting a whole number of
18779 instructions, and make it the end of the fixed part of the frag.
18780 Try to fit in a short microMIPS NOP if applicable and possible,
18781 and use zeroes otherwise. */
18782 gas_assert (excess
< 4);
18783 fragp
->fr_fix
+= excess
;
18788 /* Fall through. */
18790 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
18792 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18796 /* Fall through. */
18799 /* Fall through. */
18804 md_number_to_chars (p
, opcode
, size
);
18805 fragp
->fr_var
= size
;
18809 md_obj_begin (void)
18816 /* Check for premature end, nesting errors, etc. */
18818 as_warn (_("missing .end at end of assembly"));
18827 if (*input_line_pointer
== '-')
18829 ++input_line_pointer
;
18832 if (!ISDIGIT (*input_line_pointer
))
18833 as_bad (_("expected simple number"));
18834 if (input_line_pointer
[0] == '0')
18836 if (input_line_pointer
[1] == 'x')
18838 input_line_pointer
+= 2;
18839 while (ISXDIGIT (*input_line_pointer
))
18842 val
|= hex_value (*input_line_pointer
++);
18844 return negative
? -val
: val
;
18848 ++input_line_pointer
;
18849 while (ISDIGIT (*input_line_pointer
))
18852 val
|= *input_line_pointer
++ - '0';
18854 return negative
? -val
: val
;
18857 if (!ISDIGIT (*input_line_pointer
))
18859 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18860 *input_line_pointer
, *input_line_pointer
);
18861 as_warn (_("invalid number"));
18864 while (ISDIGIT (*input_line_pointer
))
18867 val
+= *input_line_pointer
++ - '0';
18869 return negative
? -val
: val
;
18872 /* The .file directive; just like the usual .file directive, but there
18873 is an initial number which is the ECOFF file index. In the non-ECOFF
18874 case .file implies DWARF-2. */
18877 s_mips_file (int x ATTRIBUTE_UNUSED
)
18879 static int first_file_directive
= 0;
18881 if (ECOFF_DEBUGGING
)
18890 filename
= dwarf2_directive_file (0);
18892 /* Versions of GCC up to 3.1 start files with a ".file"
18893 directive even for stabs output. Make sure that this
18894 ".file" is handled. Note that you need a version of GCC
18895 after 3.1 in order to support DWARF-2 on MIPS. */
18896 if (filename
!= NULL
&& ! first_file_directive
)
18898 (void) new_logical_line (filename
, -1);
18899 s_app_file_string (filename
, 0);
18901 first_file_directive
= 1;
18905 /* The .loc directive, implying DWARF-2. */
18908 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18910 if (!ECOFF_DEBUGGING
)
18911 dwarf2_directive_loc (0);
18914 /* The .end directive. */
18917 s_mips_end (int x ATTRIBUTE_UNUSED
)
18921 /* Following functions need their own .frame and .cprestore directives. */
18922 mips_frame_reg_valid
= 0;
18923 mips_cprestore_valid
= 0;
18925 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18928 demand_empty_rest_of_line ();
18933 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18934 as_warn (_(".end not in text section"));
18938 as_warn (_(".end directive without a preceding .ent directive."));
18939 demand_empty_rest_of_line ();
18945 gas_assert (S_GET_NAME (p
));
18946 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18947 as_warn (_(".end symbol does not match .ent symbol."));
18949 if (debug_type
== DEBUG_STABS
)
18950 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18954 as_warn (_(".end directive missing or unknown symbol"));
18957 /* Create an expression to calculate the size of the function. */
18958 if (p
&& cur_proc_ptr
)
18960 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18961 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18964 exp
->X_op
= O_subtract
;
18965 exp
->X_add_symbol
= symbol_temp_new_now ();
18966 exp
->X_op_symbol
= p
;
18967 exp
->X_add_number
= 0;
18969 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18972 /* Generate a .pdr section. */
18973 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
18975 segT saved_seg
= now_seg
;
18976 subsegT saved_subseg
= now_subseg
;
18980 #ifdef md_flush_pending_output
18981 md_flush_pending_output ();
18984 gas_assert (pdr_seg
);
18985 subseg_set (pdr_seg
, 0);
18987 /* Write the symbol. */
18988 exp
.X_op
= O_symbol
;
18989 exp
.X_add_symbol
= p
;
18990 exp
.X_add_number
= 0;
18991 emit_expr (&exp
, 4);
18993 fragp
= frag_more (7 * 4);
18995 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18996 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18997 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18998 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18999 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19000 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19001 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19003 subseg_set (saved_seg
, saved_subseg
);
19005 #endif /* OBJ_ELF */
19007 cur_proc_ptr
= NULL
;
19010 /* The .aent and .ent directives. */
19013 s_mips_ent (int aent
)
19017 symbolP
= get_symbol ();
19018 if (*input_line_pointer
== ',')
19019 ++input_line_pointer
;
19020 SKIP_WHITESPACE ();
19021 if (ISDIGIT (*input_line_pointer
)
19022 || *input_line_pointer
== '-')
19025 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19026 as_warn (_(".ent or .aent not in text section."));
19028 if (!aent
&& cur_proc_ptr
)
19029 as_warn (_("missing .end"));
19033 /* This function needs its own .frame and .cprestore directives. */
19034 mips_frame_reg_valid
= 0;
19035 mips_cprestore_valid
= 0;
19037 cur_proc_ptr
= &cur_proc
;
19038 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19040 cur_proc_ptr
->func_sym
= symbolP
;
19044 if (debug_type
== DEBUG_STABS
)
19045 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19046 S_GET_NAME (symbolP
));
19049 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19051 demand_empty_rest_of_line ();
19054 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19055 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19056 s_mips_frame is used so that we can set the PDR information correctly.
19057 We can't use the ecoff routines because they make reference to the ecoff
19058 symbol table (in the mdebug section). */
19061 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19064 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19068 if (cur_proc_ptr
== (procS
*) NULL
)
19070 as_warn (_(".frame outside of .ent"));
19071 demand_empty_rest_of_line ();
19075 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19077 SKIP_WHITESPACE ();
19078 if (*input_line_pointer
++ != ','
19079 || get_absolute_expression_and_terminator (&val
) != ',')
19081 as_warn (_("Bad .frame directive"));
19082 --input_line_pointer
;
19083 demand_empty_rest_of_line ();
19087 cur_proc_ptr
->frame_offset
= val
;
19088 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19090 demand_empty_rest_of_line ();
19093 #endif /* OBJ_ELF */
19097 /* The .fmask and .mask directives. If the mdebug section is present
19098 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19099 embedded targets, s_mips_mask is used so that we can set the PDR
19100 information correctly. We can't use the ecoff routines because they
19101 make reference to the ecoff symbol table (in the mdebug section). */
19104 s_mips_mask (int reg_type
)
19107 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19111 if (cur_proc_ptr
== (procS
*) NULL
)
19113 as_warn (_(".mask/.fmask outside of .ent"));
19114 demand_empty_rest_of_line ();
19118 if (get_absolute_expression_and_terminator (&mask
) != ',')
19120 as_warn (_("Bad .mask/.fmask directive"));
19121 --input_line_pointer
;
19122 demand_empty_rest_of_line ();
19126 off
= get_absolute_expression ();
19128 if (reg_type
== 'F')
19130 cur_proc_ptr
->fpreg_mask
= mask
;
19131 cur_proc_ptr
->fpreg_offset
= off
;
19135 cur_proc_ptr
->reg_mask
= mask
;
19136 cur_proc_ptr
->reg_offset
= off
;
19139 demand_empty_rest_of_line ();
19142 #endif /* OBJ_ELF */
19143 s_ignore (reg_type
);
19146 /* A table describing all the processors gas knows about. Names are
19147 matched in the order listed.
19149 To ease comparison, please keep this table in the same order as
19150 gcc's mips_cpu_info_table[]. */
19151 static const struct mips_cpu_info mips_cpu_info_table
[] =
19153 /* Entries for generic ISAs */
19154 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
19155 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
19156 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
19157 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
19158 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
19159 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
19160 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19161 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
19162 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
19165 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
19166 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
19167 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
19170 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
19173 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
19174 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
19175 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
19176 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
19177 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
19178 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
19179 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
19180 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
19181 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
19182 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
19183 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
19184 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
19185 { "r5900", 0, ISA_MIPS3
, CPU_R5900
},
19186 /* ST Microelectronics Loongson 2E and 2F cores */
19187 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19188 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19191 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
19192 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
19193 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
19194 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
19195 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
19196 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
19197 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
19198 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
19199 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
19200 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
19201 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
19202 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
19203 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
19204 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
19205 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
19208 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
19209 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
19210 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
19211 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19213 /* MIPS 32 Release 2 */
19214 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19215 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19216 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19217 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19218 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19219 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19220 { "m14k", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19221 { "m14kc", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19222 { "m14ke", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19223 ISA_MIPS32R2
, CPU_MIPS32R2
},
19224 { "m14kec", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19225 ISA_MIPS32R2
, CPU_MIPS32R2
},
19226 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19227 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19228 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19229 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19230 /* Deprecated forms of the above. */
19231 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19232 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19233 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19234 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19235 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19236 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19237 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19238 /* Deprecated forms of the above. */
19239 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19240 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19241 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19242 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19243 ISA_MIPS32R2
, CPU_MIPS32R2
},
19244 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19245 ISA_MIPS32R2
, CPU_MIPS32R2
},
19246 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19247 ISA_MIPS32R2
, CPU_MIPS32R2
},
19248 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19249 ISA_MIPS32R2
, CPU_MIPS32R2
},
19250 /* Deprecated forms of the above. */
19251 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19252 ISA_MIPS32R2
, CPU_MIPS32R2
},
19253 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19254 ISA_MIPS32R2
, CPU_MIPS32R2
},
19255 /* 34Kn is a 34kc without DSP. */
19256 { "34kn", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19257 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19258 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19259 ISA_MIPS32R2
, CPU_MIPS32R2
},
19260 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19261 ISA_MIPS32R2
, CPU_MIPS32R2
},
19262 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19263 ISA_MIPS32R2
, CPU_MIPS32R2
},
19264 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19265 ISA_MIPS32R2
, CPU_MIPS32R2
},
19266 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19267 ISA_MIPS32R2
, CPU_MIPS32R2
},
19268 /* Deprecated forms of the above. */
19269 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19270 ISA_MIPS32R2
, CPU_MIPS32R2
},
19271 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19272 ISA_MIPS32R2
, CPU_MIPS32R2
},
19273 /* 1004K cores are multiprocessor versions of the 34K. */
19274 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19275 ISA_MIPS32R2
, CPU_MIPS32R2
},
19276 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19277 ISA_MIPS32R2
, CPU_MIPS32R2
},
19278 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19279 ISA_MIPS32R2
, CPU_MIPS32R2
},
19280 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19281 ISA_MIPS32R2
, CPU_MIPS32R2
},
19284 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
19285 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
19286 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19287 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19289 /* Broadcom SB-1 CPU core */
19290 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19291 ISA_MIPS64
, CPU_SB1
},
19292 /* Broadcom SB-1A CPU core */
19293 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19294 ISA_MIPS64
, CPU_SB1
},
19296 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19298 /* MIPS 64 Release 2 */
19300 /* Cavium Networks Octeon CPU core */
19301 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
19302 { "octeon+", 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19303 { "octeon2", 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19306 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
19309 XLP is mostly like XLR, with the prominent exception that it is
19310 MIPS64R2 rather than MIPS64. */
19311 { "xlp", 0, ISA_MIPS64R2
, CPU_XLR
},
19318 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19319 with a final "000" replaced by "k". Ignore case.
19321 Note: this function is shared between GCC and GAS. */
19324 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19326 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19327 given
++, canonical
++;
19329 return ((*given
== 0 && *canonical
== 0)
19330 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19334 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19335 CPU name. We've traditionally allowed a lot of variation here.
19337 Note: this function is shared between GCC and GAS. */
19340 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19342 /* First see if the name matches exactly, or with a final "000"
19343 turned into "k". */
19344 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19347 /* If not, try comparing based on numerical designation alone.
19348 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19349 if (TOLOWER (*given
) == 'r')
19351 if (!ISDIGIT (*given
))
19354 /* Skip over some well-known prefixes in the canonical name,
19355 hoping to find a number there too. */
19356 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19358 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19360 else if (TOLOWER (canonical
[0]) == 'r')
19363 return mips_strict_matching_cpu_name_p (canonical
, given
);
19367 /* Parse an option that takes the name of a processor as its argument.
19368 OPTION is the name of the option and CPU_STRING is the argument.
19369 Return the corresponding processor enumeration if the CPU_STRING is
19370 recognized, otherwise report an error and return null.
19372 A similar function exists in GCC. */
19374 static const struct mips_cpu_info
*
19375 mips_parse_cpu (const char *option
, const char *cpu_string
)
19377 const struct mips_cpu_info
*p
;
19379 /* 'from-abi' selects the most compatible architecture for the given
19380 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19381 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19382 version. Look first at the -mgp options, if given, otherwise base
19383 the choice on MIPS_DEFAULT_64BIT.
19385 Treat NO_ABI like the EABIs. One reason to do this is that the
19386 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19387 architecture. This code picks MIPS I for 'mips' and MIPS III for
19388 'mips64', just as we did in the days before 'from-abi'. */
19389 if (strcasecmp (cpu_string
, "from-abi") == 0)
19391 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19392 return mips_cpu_info_from_isa (ISA_MIPS1
);
19394 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19395 return mips_cpu_info_from_isa (ISA_MIPS3
);
19397 if (file_mips_gp32
>= 0)
19398 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19400 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19405 /* 'default' has traditionally been a no-op. Probably not very useful. */
19406 if (strcasecmp (cpu_string
, "default") == 0)
19409 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19410 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19413 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19417 /* Return the canonical processor information for ISA (a member of the
19418 ISA_MIPS* enumeration). */
19420 static const struct mips_cpu_info
*
19421 mips_cpu_info_from_isa (int isa
)
19425 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19426 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19427 && isa
== mips_cpu_info_table
[i
].isa
)
19428 return (&mips_cpu_info_table
[i
]);
19433 static const struct mips_cpu_info
*
19434 mips_cpu_info_from_arch (int arch
)
19438 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19439 if (arch
== mips_cpu_info_table
[i
].cpu
)
19440 return (&mips_cpu_info_table
[i
]);
19446 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19450 fprintf (stream
, "%24s", "");
19455 fprintf (stream
, ", ");
19459 if (*col_p
+ strlen (string
) > 72)
19461 fprintf (stream
, "\n%24s", "");
19465 fprintf (stream
, "%s", string
);
19466 *col_p
+= strlen (string
);
19472 md_show_usage (FILE *stream
)
19477 fprintf (stream
, _("\
19479 -EB generate big endian output\n\
19480 -EL generate little endian output\n\
19481 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19482 -G NUM allow referencing objects up to NUM bytes\n\
19483 implicitly with the gp register [default 8]\n"));
19484 fprintf (stream
, _("\
19485 -mips1 generate MIPS ISA I instructions\n\
19486 -mips2 generate MIPS ISA II instructions\n\
19487 -mips3 generate MIPS ISA III instructions\n\
19488 -mips4 generate MIPS ISA IV instructions\n\
19489 -mips5 generate MIPS ISA V instructions\n\
19490 -mips32 generate MIPS32 ISA instructions\n\
19491 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19492 -mips64 generate MIPS64 ISA instructions\n\
19493 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19494 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19498 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19499 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19500 show (stream
, "from-abi", &column
, &first
);
19501 fputc ('\n', stream
);
19503 fprintf (stream
, _("\
19504 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19505 -no-mCPU don't generate code specific to CPU.\n\
19506 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19510 show (stream
, "3900", &column
, &first
);
19511 show (stream
, "4010", &column
, &first
);
19512 show (stream
, "4100", &column
, &first
);
19513 show (stream
, "4650", &column
, &first
);
19514 fputc ('\n', stream
);
19516 fprintf (stream
, _("\
19517 -mips16 generate mips16 instructions\n\
19518 -no-mips16 do not generate mips16 instructions\n"));
19519 fprintf (stream
, _("\
19520 -mmicromips generate microMIPS instructions\n\
19521 -mno-micromips do not generate microMIPS instructions\n"));
19522 fprintf (stream
, _("\
19523 -msmartmips generate smartmips instructions\n\
19524 -mno-smartmips do not generate smartmips instructions\n"));
19525 fprintf (stream
, _("\
19526 -mdsp generate DSP instructions\n\
19527 -mno-dsp do not generate DSP instructions\n"));
19528 fprintf (stream
, _("\
19529 -mdspr2 generate DSP R2 instructions\n\
19530 -mno-dspr2 do not generate DSP R2 instructions\n"));
19531 fprintf (stream
, _("\
19532 -mmt generate MT instructions\n\
19533 -mno-mt do not generate MT instructions\n"));
19534 fprintf (stream
, _("\
19535 -mmcu generate MCU instructions\n\
19536 -mno-mcu do not generate MCU instructions\n"));
19537 fprintf (stream
, _("\
19538 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19539 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19540 -mfix-vr4120 work around certain VR4120 errata\n\
19541 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19542 -mfix-24k insert a nop after ERET and DERET instructions\n\
19543 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19544 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19545 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19546 -msym32 assume all symbols have 32-bit values\n\
19547 -O0 remove unneeded NOPs, do not swap branches\n\
19548 -O remove unneeded NOPs and swap branches\n\
19549 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19550 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19551 fprintf (stream
, _("\
19552 -mhard-float allow floating-point instructions\n\
19553 -msoft-float do not allow floating-point instructions\n\
19554 -msingle-float only allow 32-bit floating-point operations\n\
19555 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19556 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19559 fprintf (stream
, _("\
19560 -KPIC, -call_shared generate SVR4 position independent code\n\
19561 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19562 -mvxworks-pic generate VxWorks position independent code\n\
19563 -non_shared do not generate code that can operate with DSOs\n\
19564 -xgot assume a 32 bit GOT\n\
19565 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19566 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19567 position dependent (non shared) code\n\
19568 -mabi=ABI create ABI conformant object file for:\n"));
19572 show (stream
, "32", &column
, &first
);
19573 show (stream
, "o64", &column
, &first
);
19574 show (stream
, "n32", &column
, &first
);
19575 show (stream
, "64", &column
, &first
);
19576 show (stream
, "eabi", &column
, &first
);
19578 fputc ('\n', stream
);
19580 fprintf (stream
, _("\
19581 -32 create o32 ABI object file (default)\n\
19582 -n32 create n32 ABI object file\n\
19583 -64 create 64 ABI object file\n"));
19589 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19591 if (HAVE_64BIT_SYMBOLS
)
19592 return dwarf2_format_64bit_irix
;
19594 return dwarf2_format_32bit
;
19599 mips_dwarf2_addr_size (void)
19601 if (HAVE_64BIT_OBJECTS
)
19607 /* Standard calling conventions leave the CFA at SP on entry. */
19609 mips_cfi_frame_initial_instructions (void)
19611 cfi_add_CFA_def_cfa_register (SP
);
19615 tc_mips_regname_to_dw2regnum (char *regname
)
19617 unsigned int regnum
= -1;
19620 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))