1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32
= -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32
= -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float
= 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float
= 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008
= FALSE
;
281 static struct mips_set_options mips_opts
=
283 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
287 /* soft_float */ FALSE
, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase
;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit
;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch
= CPU_UNKNOWN
;
331 static const char *mips_arch_string
;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune
= CPU_UNKNOWN
;
336 static const char *mips_tune_string
;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode
= 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic
;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got
= 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap
= 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction
;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder
;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix
;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value
= 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen
= 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS
*, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control
*op_hash
= NULL
;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control
*mips16_op_hash
= NULL
;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control
*micromips_op_hash
= NULL
;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars
[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars
[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars
[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS
[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 static char *insn_error
;
635 static int auto_align
= 1;
637 /* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
641 static offsetT mips_cprestore_offset
= -1;
643 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
644 more optimizations, it can use a register value instead of a memory-saved
645 offset and even an other register than $gp as global pointer. */
646 static offsetT mips_cpreturn_offset
= -1;
647 static int mips_cpreturn_register
= -1;
648 static int mips_gp_register
= GP
;
649 static int mips_gprel_offset
= 0;
651 /* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_cprestore_valid
= 0;
655 /* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657 static int mips_frame_reg
= SP
;
659 /* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661 static int mips_frame_reg_valid
= 0;
663 /* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
666 /* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
670 static int mips_optimize
= 2;
672 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674 static int mips_debug
= 0;
676 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677 #define MAX_VR4130_NOPS 4
679 /* The maximum number of NOPs needed to fill delay slots. */
680 #define MAX_DELAY_NOPS 2
682 /* The maximum number of NOPs needed for any purpose. */
685 /* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690 static struct mips_cl_insn history
[1 + MAX_NOPS
];
692 /* Nop instructions used by emit_nop. */
693 static struct mips_cl_insn nop_insn
;
694 static struct mips_cl_insn mips16_nop_insn
;
695 static struct mips_cl_insn micromips_nop16_insn
;
696 static struct mips_cl_insn micromips_nop32_insn
;
698 /* The appropriate nop for the current mode. */
699 #define NOP_INSN (mips_opts.mips16 \
701 : (mips_opts.micromips \
702 ? (mips_opts.insn32 \
703 ? µmips_nop32_insn \
704 : µmips_nop16_insn) \
707 /* The size of NOP_INSN in bytes. */
708 #define NOP_INSN_SIZE ((mips_opts.mips16 \
709 || (mips_opts.micromips && !mips_opts.insn32)) \
712 /* If this is set, it points to a frag holding nop instructions which
713 were inserted before the start of a noreorder section. If those
714 nops turn out to be unnecessary, the size of the frag can be
716 static fragS
*prev_nop_frag
;
718 /* The number of nop instructions we created in prev_nop_frag. */
719 static int prev_nop_frag_holds
;
721 /* The number of nop instructions that we know we need in
723 static int prev_nop_frag_required
;
725 /* The number of instructions we've seen since prev_nop_frag. */
726 static int prev_nop_frag_since
;
728 /* Relocations against symbols are sometimes done in two parts, with a HI
729 relocation and a LO relocation. Each relocation has only 16 bits of
730 space to store an addend. This means that in order for the linker to
731 handle carries correctly, it must be able to locate both the HI and
732 the LO relocation. This means that the relocations must appear in
733 order in the relocation table.
735 In order to implement this, we keep track of each unmatched HI
736 relocation. We then sort them so that they immediately precede the
737 corresponding LO relocation. */
742 struct mips_hi_fixup
*next
;
745 /* The section this fixup is in. */
749 /* The list of unmatched HI relocs. */
751 static struct mips_hi_fixup
*mips_hi_fixup_list
;
753 /* The frag containing the last explicit relocation operator.
754 Null if explicit relocations have not been used. */
756 static fragS
*prev_reloc_op_frag
;
758 /* Map mips16 register numbers to normal MIPS register numbers. */
760 static const unsigned int mips16_to_32_reg_map
[] =
762 16, 17, 2, 3, 4, 5, 6, 7
765 /* Map microMIPS register numbers to normal MIPS register numbers. */
767 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
768 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
769 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
770 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
771 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
772 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
774 /* The microMIPS registers with type h. */
775 static const unsigned int micromips_to_32_reg_h_map1
[] =
777 5, 5, 6, 4, 4, 4, 4, 4
779 static const unsigned int micromips_to_32_reg_h_map2
[] =
781 6, 7, 7, 21, 22, 5, 6, 7
784 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
786 /* The microMIPS registers with type m. */
787 static const unsigned int micromips_to_32_reg_m_map
[] =
789 0, 17, 2, 3, 16, 18, 19, 20
792 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
794 /* The microMIPS registers with type q. */
795 static const unsigned int micromips_to_32_reg_q_map
[] =
797 0, 17, 2, 3, 4, 5, 6, 7
800 /* Classifies the kind of instructions we're interested in when
801 implementing -mfix-vr4120. */
802 enum fix_vr4120_class
810 NUM_FIX_VR4120_CLASSES
813 /* ...likewise -mfix-loongson2f-jump. */
814 static bfd_boolean mips_fix_loongson2f_jump
;
816 /* ...likewise -mfix-loongson2f-nop. */
817 static bfd_boolean mips_fix_loongson2f_nop
;
819 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
820 static bfd_boolean mips_fix_loongson2f
;
822 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
823 there must be at least one other instruction between an instruction
824 of type X and an instruction of type Y. */
825 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
827 /* True if -mfix-vr4120 is in force. */
828 static int mips_fix_vr4120
;
830 /* ...likewise -mfix-vr4130. */
831 static int mips_fix_vr4130
;
833 /* ...likewise -mfix-24k. */
834 static int mips_fix_24k
;
836 /* ...likewise -mfix-cn63xxp1 */
837 static bfd_boolean mips_fix_cn63xxp1
;
839 /* We don't relax branches by default, since this causes us to expand
840 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
841 fail to compute the offset before expanding the macro to the most
842 efficient expansion. */
844 static int mips_relax_branch
;
846 /* The expansion of many macros depends on the type of symbol that
847 they refer to. For example, when generating position-dependent code,
848 a macro that refers to a symbol may have two different expansions,
849 one which uses GP-relative addresses and one which uses absolute
850 addresses. When generating SVR4-style PIC, a macro may have
851 different expansions for local and global symbols.
853 We handle these situations by generating both sequences and putting
854 them in variant frags. In position-dependent code, the first sequence
855 will be the GP-relative one and the second sequence will be the
856 absolute one. In SVR4 PIC, the first sequence will be for global
857 symbols and the second will be for local symbols.
859 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
860 SECOND are the lengths of the two sequences in bytes. These fields
861 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
862 the subtype has the following flags:
865 Set if it has been decided that we should use the second
866 sequence instead of the first.
869 Set in the first variant frag if the macro's second implementation
870 is longer than its first. This refers to the macro as a whole,
871 not an individual relaxation.
874 Set in the first variant frag if the macro appeared in a .set nomacro
875 block and if one alternative requires a warning but the other does not.
878 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
881 RELAX_DELAY_SLOT_16BIT
882 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
885 RELAX_DELAY_SLOT_SIZE_FIRST
886 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
887 the macro is of the wrong size for the branch delay slot.
889 RELAX_DELAY_SLOT_SIZE_SECOND
890 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
891 the macro is of the wrong size for the branch delay slot.
893 The frag's "opcode" points to the first fixup for relaxable code.
895 Relaxable macros are generated using a sequence such as:
897 relax_start (SYMBOL);
898 ... generate first expansion ...
900 ... generate second expansion ...
903 The code and fixups for the unwanted alternative are discarded
904 by md_convert_frag. */
905 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
907 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
908 #define RELAX_SECOND(X) ((X) & 0xff)
909 #define RELAX_USE_SECOND 0x10000
910 #define RELAX_SECOND_LONGER 0x20000
911 #define RELAX_NOMACRO 0x40000
912 #define RELAX_DELAY_SLOT 0x80000
913 #define RELAX_DELAY_SLOT_16BIT 0x100000
914 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
915 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
917 /* Branch without likely bit. If label is out of range, we turn:
919 beq reg1, reg2, label
929 with the following opcode replacements:
936 bltzal <-> bgezal (with jal label instead of j label)
938 Even though keeping the delay slot instruction in the delay slot of
939 the branch would be more efficient, it would be very tricky to do
940 correctly, because we'd have to introduce a variable frag *after*
941 the delay slot instruction, and expand that instead. Let's do it
942 the easy way for now, even if the branch-not-taken case now costs
943 one additional instruction. Out-of-range branches are not supposed
944 to be common, anyway.
946 Branch likely. If label is out of range, we turn:
948 beql reg1, reg2, label
949 delay slot (annulled if branch not taken)
958 delay slot (executed only if branch taken)
961 It would be possible to generate a shorter sequence by losing the
962 likely bit, generating something like:
967 delay slot (executed only if branch taken)
979 bltzall -> bgezal (with jal label instead of j label)
980 bgezall -> bltzal (ditto)
983 but it's not clear that it would actually improve performance. */
984 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
988 | ((toofar) ? 0x20 : 0) \
989 | ((link) ? 0x40 : 0) \
990 | ((likely) ? 0x80 : 0) \
991 | ((uncond) ? 0x100 : 0)))
992 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
993 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
994 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
995 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
996 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
997 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
999 /* For mips16 code, we use an entirely different form of relaxation.
1000 mips16 supports two versions of most instructions which take
1001 immediate values: a small one which takes some small value, and a
1002 larger one which takes a 16 bit value. Since branches also follow
1003 this pattern, relaxing these values is required.
1005 We can assemble both mips16 and normal MIPS code in a single
1006 object. Therefore, we need to support this type of relaxation at
1007 the same time that we support the relaxation described above. We
1008 use the high bit of the subtype field to distinguish these cases.
1010 The information we store for this type of relaxation is the
1011 argument code found in the opcode file for this relocation, whether
1012 the user explicitly requested a small or extended form, and whether
1013 the relocation is in a jump or jal delay slot. That tells us the
1014 size of the value, and how it should be stored. We also store
1015 whether the fragment is considered to be extended or not. We also
1016 store whether this is known to be a branch to a different section,
1017 whether we have tried to relax this frag yet, and whether we have
1018 ever extended a PC relative fragment because of a shift count. */
1019 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1022 | ((small) ? 0x100 : 0) \
1023 | ((ext) ? 0x200 : 0) \
1024 | ((dslot) ? 0x400 : 0) \
1025 | ((jal_dslot) ? 0x800 : 0))
1026 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1027 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1028 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1029 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1030 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1031 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1032 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1033 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1034 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1035 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1036 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1037 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1039 /* For microMIPS code, we use relaxation similar to one we use for
1040 MIPS16 code. Some instructions that take immediate values support
1041 two encodings: a small one which takes some small value, and a
1042 larger one which takes a 16 bit value. As some branches also follow
1043 this pattern, relaxing these values is required.
1045 We can assemble both microMIPS and normal MIPS code in a single
1046 object. Therefore, we need to support this type of relaxation at
1047 the same time that we support the relaxation described above. We
1048 use one of the high bits of the subtype field to distinguish these
1051 The information we store for this type of relaxation is the argument
1052 code found in the opcode file for this relocation, the register
1053 selected as the assembler temporary, whether the branch is
1054 unconditional, whether it is compact, whether it stores the link
1055 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1056 branches to a sequence of instructions is enabled, and whether the
1057 displacement of a branch is too large to fit as an immediate argument
1058 of a 16-bit and a 32-bit branch, respectively. */
1059 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1060 relax32, toofar16, toofar32) \
1063 | (((at) & 0x1f) << 8) \
1064 | ((uncond) ? 0x2000 : 0) \
1065 | ((compact) ? 0x4000 : 0) \
1066 | ((link) ? 0x8000 : 0) \
1067 | ((relax32) ? 0x10000 : 0) \
1068 | ((toofar16) ? 0x20000 : 0) \
1069 | ((toofar32) ? 0x40000 : 0))
1070 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1071 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1072 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1073 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1074 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1075 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1076 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1078 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1079 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1080 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1081 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1082 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1083 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1085 /* Sign-extend 16-bit value X. */
1086 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1088 /* Is the given value a sign-extended 32-bit value? */
1089 #define IS_SEXT_32BIT_NUM(x) \
1090 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1091 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1093 /* Is the given value a sign-extended 16-bit value? */
1094 #define IS_SEXT_16BIT_NUM(x) \
1095 (((x) &~ (offsetT) 0x7fff) == 0 \
1096 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1098 /* Is the given value a sign-extended 12-bit value? */
1099 #define IS_SEXT_12BIT_NUM(x) \
1100 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1102 /* Is the given value a sign-extended 9-bit value? */
1103 #define IS_SEXT_9BIT_NUM(x) \
1104 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1106 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1107 #define IS_ZEXT_32BIT_NUM(x) \
1108 (((x) &~ (offsetT) 0xffffffff) == 0 \
1109 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1111 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1113 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1114 (((STRUCT) >> (SHIFT)) & (MASK))
1116 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1117 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1119 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1120 : EXTRACT_BITS ((INSN).insn_opcode, \
1121 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1122 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1123 EXTRACT_BITS ((INSN).insn_opcode, \
1124 MIPS16OP_MASK_##FIELD, \
1125 MIPS16OP_SH_##FIELD)
1127 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1128 #define MIPS16_EXTEND (0xf000U << 16)
1130 /* Whether or not we are emitting a branch-likely macro. */
1131 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1133 /* Global variables used when generating relaxable macros. See the
1134 comment above RELAX_ENCODE for more details about how relaxation
1137 /* 0 if we're not emitting a relaxable macro.
1138 1 if we're emitting the first of the two relaxation alternatives.
1139 2 if we're emitting the second alternative. */
1142 /* The first relaxable fixup in the current frag. (In other words,
1143 the first fixup that refers to relaxable code.) */
1146 /* sizes[0] says how many bytes of the first alternative are stored in
1147 the current frag. Likewise sizes[1] for the second alternative. */
1148 unsigned int sizes
[2];
1150 /* The symbol on which the choice of sequence depends. */
1154 /* Global variables used to decide whether a macro needs a warning. */
1156 /* True if the macro is in a branch delay slot. */
1157 bfd_boolean delay_slot_p
;
1159 /* Set to the length in bytes required if the macro is in a delay slot
1160 that requires a specific length of instruction, otherwise zero. */
1161 unsigned int delay_slot_length
;
1163 /* For relaxable macros, sizes[0] is the length of the first alternative
1164 in bytes and sizes[1] is the length of the second alternative.
1165 For non-relaxable macros, both elements give the length of the
1167 unsigned int sizes
[2];
1169 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1170 instruction of the first alternative in bytes and first_insn_sizes[1]
1171 is the length of the first instruction of the second alternative.
1172 For non-relaxable macros, both elements give the length of the first
1173 instruction in bytes.
1175 Set to zero if we haven't yet seen the first instruction. */
1176 unsigned int first_insn_sizes
[2];
1178 /* For relaxable macros, insns[0] is the number of instructions for the
1179 first alternative and insns[1] is the number of instructions for the
1182 For non-relaxable macros, both elements give the number of
1183 instructions for the macro. */
1184 unsigned int insns
[2];
1186 /* The first variant frag for this macro. */
1188 } mips_macro_warning
;
1190 /* Prototypes for static functions. */
1192 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1194 static void append_insn
1195 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1196 bfd_boolean expansionp
);
1197 static void mips_no_prev_insn (void);
1198 static void macro_build (expressionS
*, const char *, const char *, ...);
1199 static void mips16_macro_build
1200 (expressionS
*, const char *, const char *, va_list *);
1201 static void load_register (int, expressionS
*, int);
1202 static void macro_start (void);
1203 static void macro_end (void);
1204 static void macro (struct mips_cl_insn
*ip
, char *str
);
1205 static void mips16_macro (struct mips_cl_insn
* ip
);
1206 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1207 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1208 static void mips16_immed
1209 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1210 unsigned int, unsigned long *);
1211 static size_t my_getSmallExpression
1212 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1213 static void my_getExpression (expressionS
*, char *);
1214 static void s_align (int);
1215 static void s_change_sec (int);
1216 static void s_change_section (int);
1217 static void s_cons (int);
1218 static void s_float_cons (int);
1219 static void s_mips_globl (int);
1220 static void s_option (int);
1221 static void s_mipsset (int);
1222 static void s_abicalls (int);
1223 static void s_cpload (int);
1224 static void s_cpsetup (int);
1225 static void s_cplocal (int);
1226 static void s_cprestore (int);
1227 static void s_cpreturn (int);
1228 static void s_dtprelword (int);
1229 static void s_dtpreldword (int);
1230 static void s_tprelword (int);
1231 static void s_tpreldword (int);
1232 static void s_gpvalue (int);
1233 static void s_gpword (int);
1234 static void s_gpdword (int);
1235 static void s_ehword (int);
1236 static void s_cpadd (int);
1237 static void s_insn (int);
1238 static void s_nan (int);
1239 static void md_obj_begin (void);
1240 static void md_obj_end (void);
1241 static void s_mips_ent (int);
1242 static void s_mips_end (int);
1243 static void s_mips_frame (int);
1244 static void s_mips_mask (int reg_type
);
1245 static void s_mips_stab (int);
1246 static void s_mips_weakext (int);
1247 static void s_mips_file (int);
1248 static void s_mips_loc (int);
1249 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1250 static int relaxed_branch_length (fragS
*, asection
*, int);
1251 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1252 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1254 /* Table and functions used to map between CPU/ISA names, and
1255 ISA levels, and CPU numbers. */
1257 struct mips_cpu_info
1259 const char *name
; /* CPU or ISA name. */
1260 int flags
; /* MIPS_CPU_* flags. */
1261 int ase
; /* Set of ASEs implemented by the CPU. */
1262 int isa
; /* ISA level. */
1263 int cpu
; /* CPU number (default CPU if ISA). */
1266 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1268 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1269 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1270 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1272 /* Command-line options. */
1273 const char *md_shortopts
= "O::g::G:";
1277 OPTION_MARCH
= OPTION_MD_BASE
,
1301 OPTION_NO_SMARTMIPS
,
1307 OPTION_NO_MICROMIPS
,
1310 OPTION_COMPAT_ARCH_BASE
,
1319 OPTION_M7000_HILO_FIX
,
1320 OPTION_MNO_7000_HILO_FIX
,
1323 OPTION_FIX_LOONGSON2F_JUMP
,
1324 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1325 OPTION_FIX_LOONGSON2F_NOP
,
1326 OPTION_NO_FIX_LOONGSON2F_NOP
,
1328 OPTION_NO_FIX_VR4120
,
1330 OPTION_NO_FIX_VR4130
,
1331 OPTION_FIX_CN63XXP1
,
1332 OPTION_NO_FIX_CN63XXP1
,
1339 OPTION_CONSTRUCT_FLOATS
,
1340 OPTION_NO_CONSTRUCT_FLOATS
,
1343 OPTION_RELAX_BRANCH
,
1344 OPTION_NO_RELAX_BRANCH
,
1353 OPTION_SINGLE_FLOAT
,
1354 OPTION_DOUBLE_FLOAT
,
1367 OPTION_MVXWORKS_PIC
,
1372 struct option md_longopts
[] =
1374 /* Options which specify architecture. */
1375 {"march", required_argument
, NULL
, OPTION_MARCH
},
1376 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1377 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1378 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1379 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1380 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1381 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1382 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1383 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1384 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1385 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1386 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1388 /* Options which specify Application Specific Extensions (ASEs). */
1389 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1390 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1391 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1392 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1393 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1394 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1395 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1396 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1397 {"mmt", no_argument
, NULL
, OPTION_MT
},
1398 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1399 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1400 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1401 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1402 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1403 {"meva", no_argument
, NULL
, OPTION_EVA
},
1404 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1405 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1406 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1407 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1408 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1409 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1410 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1412 /* Old-style architecture options. Don't add more of these. */
1413 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1414 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1415 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1416 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1417 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1418 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1419 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1420 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1422 /* Options which enable bug fixes. */
1423 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1424 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1425 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1426 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1427 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1428 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1429 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1430 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1431 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1432 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1433 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1434 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1435 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1436 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1437 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1439 /* Miscellaneous options. */
1440 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1441 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1442 {"break", no_argument
, NULL
, OPTION_BREAK
},
1443 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1444 {"EB", no_argument
, NULL
, OPTION_EB
},
1445 {"EL", no_argument
, NULL
, OPTION_EL
},
1446 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1447 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1448 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1449 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1450 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1451 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1452 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1453 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1454 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1455 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1456 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1457 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1458 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1459 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1460 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1461 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1462 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1463 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1465 /* Strictly speaking this next option is ELF specific,
1466 but we allow it for other ports as well in order to
1467 make testing easier. */
1468 {"32", no_argument
, NULL
, OPTION_32
},
1470 /* ELF-specific options. */
1471 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1472 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1473 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1474 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1475 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1476 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1477 {"n32", no_argument
, NULL
, OPTION_N32
},
1478 {"64", no_argument
, NULL
, OPTION_64
},
1479 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1480 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1481 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1482 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1483 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1484 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1486 {NULL
, no_argument
, NULL
, 0}
1488 size_t md_longopts_size
= sizeof (md_longopts
);
1490 /* Information about either an Application Specific Extension or an
1491 optional architecture feature that, for simplicity, we treat in the
1492 same way as an ASE. */
1495 /* The name of the ASE, used in both the command-line and .set options. */
1498 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1499 and 64-bit architectures, the flags here refer to the subset that
1500 is available on both. */
1503 /* The ASE_* flag used for instructions that are available on 64-bit
1504 architectures but that are not included in FLAGS. */
1505 unsigned int flags64
;
1507 /* The command-line options that turn the ASE on and off. */
1511 /* The minimum required architecture revisions for MIPS32, MIPS64,
1512 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1515 int micromips32_rev
;
1516 int micromips64_rev
;
1519 /* A table of all supported ASEs. */
1520 static const struct mips_ase mips_ases
[] = {
1521 { "dsp", ASE_DSP
, ASE_DSP64
,
1522 OPTION_DSP
, OPTION_NO_DSP
,
1525 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1526 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1529 { "eva", ASE_EVA
, 0,
1530 OPTION_EVA
, OPTION_NO_EVA
,
1533 { "mcu", ASE_MCU
, 0,
1534 OPTION_MCU
, OPTION_NO_MCU
,
1537 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1538 { "mdmx", ASE_MDMX
, 0,
1539 OPTION_MDMX
, OPTION_NO_MDMX
,
1542 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1543 { "mips3d", ASE_MIPS3D
, 0,
1544 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1548 OPTION_MT
, OPTION_NO_MT
,
1551 { "smartmips", ASE_SMARTMIPS
, 0,
1552 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1555 { "virt", ASE_VIRT
, ASE_VIRT64
,
1556 OPTION_VIRT
, OPTION_NO_VIRT
,
1560 /* The set of ASEs that require -mfp64. */
1561 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1563 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1564 static const unsigned int mips_ase_groups
[] = {
1570 The following pseudo-ops from the Kane and Heinrich MIPS book
1571 should be defined here, but are currently unsupported: .alias,
1572 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1574 The following pseudo-ops from the Kane and Heinrich MIPS book are
1575 specific to the type of debugging information being generated, and
1576 should be defined by the object format: .aent, .begin, .bend,
1577 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1580 The following pseudo-ops from the Kane and Heinrich MIPS book are
1581 not MIPS CPU specific, but are also not specific to the object file
1582 format. This file is probably the best place to define them, but
1583 they are not currently supported: .asm0, .endr, .lab, .struct. */
1585 static const pseudo_typeS mips_pseudo_table
[] =
1587 /* MIPS specific pseudo-ops. */
1588 {"option", s_option
, 0},
1589 {"set", s_mipsset
, 0},
1590 {"rdata", s_change_sec
, 'r'},
1591 {"sdata", s_change_sec
, 's'},
1592 {"livereg", s_ignore
, 0},
1593 {"abicalls", s_abicalls
, 0},
1594 {"cpload", s_cpload
, 0},
1595 {"cpsetup", s_cpsetup
, 0},
1596 {"cplocal", s_cplocal
, 0},
1597 {"cprestore", s_cprestore
, 0},
1598 {"cpreturn", s_cpreturn
, 0},
1599 {"dtprelword", s_dtprelword
, 0},
1600 {"dtpreldword", s_dtpreldword
, 0},
1601 {"tprelword", s_tprelword
, 0},
1602 {"tpreldword", s_tpreldword
, 0},
1603 {"gpvalue", s_gpvalue
, 0},
1604 {"gpword", s_gpword
, 0},
1605 {"gpdword", s_gpdword
, 0},
1606 {"ehword", s_ehword
, 0},
1607 {"cpadd", s_cpadd
, 0},
1608 {"insn", s_insn
, 0},
1611 /* Relatively generic pseudo-ops that happen to be used on MIPS
1613 {"asciiz", stringer
, 8 + 1},
1614 {"bss", s_change_sec
, 'b'},
1616 {"half", s_cons
, 1},
1617 {"dword", s_cons
, 3},
1618 {"weakext", s_mips_weakext
, 0},
1619 {"origin", s_org
, 0},
1620 {"repeat", s_rept
, 0},
1622 /* For MIPS this is non-standard, but we define it for consistency. */
1623 {"sbss", s_change_sec
, 'B'},
1625 /* These pseudo-ops are defined in read.c, but must be overridden
1626 here for one reason or another. */
1627 {"align", s_align
, 0},
1628 {"byte", s_cons
, 0},
1629 {"data", s_change_sec
, 'd'},
1630 {"double", s_float_cons
, 'd'},
1631 {"float", s_float_cons
, 'f'},
1632 {"globl", s_mips_globl
, 0},
1633 {"global", s_mips_globl
, 0},
1634 {"hword", s_cons
, 1},
1636 {"long", s_cons
, 2},
1637 {"octa", s_cons
, 4},
1638 {"quad", s_cons
, 3},
1639 {"section", s_change_section
, 0},
1640 {"short", s_cons
, 1},
1641 {"single", s_float_cons
, 'f'},
1642 {"stabd", s_mips_stab
, 'd'},
1643 {"stabn", s_mips_stab
, 'n'},
1644 {"stabs", s_mips_stab
, 's'},
1645 {"text", s_change_sec
, 't'},
1646 {"word", s_cons
, 2},
1648 { "extern", ecoff_directive_extern
, 0},
1653 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1655 /* These pseudo-ops should be defined by the object file format.
1656 However, a.out doesn't support them, so we have versions here. */
1657 {"aent", s_mips_ent
, 1},
1658 {"bgnb", s_ignore
, 0},
1659 {"end", s_mips_end
, 0},
1660 {"endb", s_ignore
, 0},
1661 {"ent", s_mips_ent
, 0},
1662 {"file", s_mips_file
, 0},
1663 {"fmask", s_mips_mask
, 'F'},
1664 {"frame", s_mips_frame
, 0},
1665 {"loc", s_mips_loc
, 0},
1666 {"mask", s_mips_mask
, 'R'},
1667 {"verstamp", s_ignore
, 0},
1671 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1672 purpose of the `.dc.a' internal pseudo-op. */
1675 mips_address_bytes (void)
1677 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1680 extern void pop_insert (const pseudo_typeS
*);
1683 mips_pop_insert (void)
1685 pop_insert (mips_pseudo_table
);
1686 if (! ECOFF_DEBUGGING
)
1687 pop_insert (mips_nonecoff_pseudo_table
);
1690 /* Symbols labelling the current insn. */
1692 struct insn_label_list
1694 struct insn_label_list
*next
;
1698 static struct insn_label_list
*free_insn_labels
;
1699 #define label_list tc_segment_info_data.labels
1701 static void mips_clear_insn_labels (void);
1702 static void mips_mark_labels (void);
1703 static void mips_compressed_mark_labels (void);
1706 mips_clear_insn_labels (void)
1708 register struct insn_label_list
**pl
;
1709 segment_info_type
*si
;
1713 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1716 si
= seg_info (now_seg
);
1717 *pl
= si
->label_list
;
1718 si
->label_list
= NULL
;
1722 /* Mark instruction labels in MIPS16/microMIPS mode. */
1725 mips_mark_labels (void)
1727 if (HAVE_CODE_COMPRESSION
)
1728 mips_compressed_mark_labels ();
1731 static char *expr_end
;
1733 /* Expressions which appear in macro instructions. These are set by
1734 mips_ip and read by macro. */
1736 static expressionS imm_expr
;
1737 static expressionS imm2_expr
;
1739 /* The relocatable field in an instruction and the relocs associated
1740 with it. These variables are used for instructions like LUI and
1741 JAL as well as true offsets. They are also used for address
1742 operands in macros. */
1744 static expressionS offset_expr
;
1745 static bfd_reloc_code_real_type offset_reloc
[3]
1746 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1748 /* This is set to the resulting size of the instruction to be produced
1749 by mips16_ip if an explicit extension is used or by mips_ip if an
1750 explicit size is supplied. */
1752 static unsigned int forced_insn_length
;
1754 /* True if we are assembling an instruction. All dot symbols defined during
1755 this time should be treated as code labels. */
1757 static bfd_boolean mips_assembling_insn
;
1759 /* The pdr segment for per procedure frame/regmask info. Not used for
1762 static segT pdr_seg
;
1764 /* The default target format to use. */
1766 #if defined (TE_FreeBSD)
1767 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1768 #elif defined (TE_TMIPS)
1769 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1771 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1775 mips_target_format (void)
1777 switch (OUTPUT_FLAVOR
)
1779 case bfd_target_elf_flavour
:
1781 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1782 return (target_big_endian
1783 ? "elf32-bigmips-vxworks"
1784 : "elf32-littlemips-vxworks");
1786 return (target_big_endian
1787 ? (HAVE_64BIT_OBJECTS
1788 ? ELF_TARGET ("elf64-", "big")
1790 ? ELF_TARGET ("elf32-n", "big")
1791 : ELF_TARGET ("elf32-", "big")))
1792 : (HAVE_64BIT_OBJECTS
1793 ? ELF_TARGET ("elf64-", "little")
1795 ? ELF_TARGET ("elf32-n", "little")
1796 : ELF_TARGET ("elf32-", "little"))));
1803 /* Return the ISA revision that is currently in use, or 0 if we are
1804 generating code for MIPS V or below. */
1809 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1812 /* microMIPS implies revision 2 or above. */
1813 if (mips_opts
.micromips
)
1816 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1822 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1825 mips_ase_mask (unsigned int flags
)
1829 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1830 if (flags
& mips_ase_groups
[i
])
1831 flags
|= mips_ase_groups
[i
];
1835 /* Check whether the current ISA supports ASE. Issue a warning if
1839 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1843 static unsigned int warned_isa
;
1844 static unsigned int warned_fp32
;
1846 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1847 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1849 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1850 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1851 && (warned_isa
& ase
->flags
) != ase
->flags
)
1853 warned_isa
|= ase
->flags
;
1854 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1855 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1857 as_warn (_("The %d-bit %s architecture does not support the"
1858 " `%s' extension"), size
, base
, ase
->name
);
1860 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1861 ase
->name
, base
, size
, min_rev
);
1863 if ((ase
->flags
& FP64_ASES
)
1865 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1867 warned_fp32
|= ase
->flags
;
1868 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1872 /* Check all enabled ASEs to see whether they are supported by the
1873 chosen architecture. */
1876 mips_check_isa_supports_ases (void)
1878 unsigned int i
, mask
;
1880 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1882 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1883 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1884 mips_check_isa_supports_ase (&mips_ases
[i
]);
1888 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1889 that were affected. */
1892 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1896 mask
= mips_ase_mask (ase
->flags
);
1897 mips_opts
.ase
&= ~mask
;
1899 mips_opts
.ase
|= ase
->flags
;
1903 /* Return the ASE called NAME, or null if none. */
1905 static const struct mips_ase
*
1906 mips_lookup_ase (const char *name
)
1910 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1911 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1912 return &mips_ases
[i
];
1916 /* Return the length of a microMIPS instruction in bytes. If bits of
1917 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1918 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1919 major opcode) will require further modifications to the opcode
1922 static inline unsigned int
1923 micromips_insn_length (const struct mips_opcode
*mo
)
1925 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1928 /* Return the length of MIPS16 instruction OPCODE. */
1930 static inline unsigned int
1931 mips16_opcode_length (unsigned long opcode
)
1933 return (opcode
>> 16) == 0 ? 2 : 4;
1936 /* Return the length of instruction INSN. */
1938 static inline unsigned int
1939 insn_length (const struct mips_cl_insn
*insn
)
1941 if (mips_opts
.micromips
)
1942 return micromips_insn_length (insn
->insn_mo
);
1943 else if (mips_opts
.mips16
)
1944 return mips16_opcode_length (insn
->insn_opcode
);
1949 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1952 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1957 insn
->insn_opcode
= mo
->match
;
1960 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1961 insn
->fixp
[i
] = NULL
;
1962 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1963 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1964 insn
->mips16_absolute_jump_p
= 0;
1965 insn
->complete_p
= 0;
1966 insn
->cleared_p
= 0;
1969 /* Install UVAL as the value of OPERAND in INSN. */
1972 insn_insert_operand (struct mips_cl_insn
*insn
,
1973 const struct mips_operand
*operand
, unsigned int uval
)
1975 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
1978 /* Record the current MIPS16/microMIPS mode in now_seg. */
1981 mips_record_compressed_mode (void)
1983 segment_info_type
*si
;
1985 si
= seg_info (now_seg
);
1986 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1987 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1988 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1989 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1992 /* Read a standard MIPS instruction from BUF. */
1994 static unsigned long
1995 read_insn (char *buf
)
1997 if (target_big_endian
)
1998 return bfd_getb32 ((bfd_byte
*) buf
);
2000 return bfd_getl32 ((bfd_byte
*) buf
);
2003 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2007 write_insn (char *buf
, unsigned int insn
)
2009 md_number_to_chars (buf
, insn
, 4);
2013 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2014 has length LENGTH. */
2016 static unsigned long
2017 read_compressed_insn (char *buf
, unsigned int length
)
2023 for (i
= 0; i
< length
; i
+= 2)
2026 if (target_big_endian
)
2027 insn
|= bfd_getb16 ((char *) buf
);
2029 insn
|= bfd_getl16 ((char *) buf
);
2035 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2036 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2039 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2043 for (i
= 0; i
< length
; i
+= 2)
2044 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2045 return buf
+ length
;
2048 /* Install INSN at the location specified by its "frag" and "where" fields. */
2051 install_insn (const struct mips_cl_insn
*insn
)
2053 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2054 if (HAVE_CODE_COMPRESSION
)
2055 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2057 write_insn (f
, insn
->insn_opcode
);
2058 mips_record_compressed_mode ();
2061 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2062 and install the opcode in the new location. */
2065 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2070 insn
->where
= where
;
2071 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2072 if (insn
->fixp
[i
] != NULL
)
2074 insn
->fixp
[i
]->fx_frag
= frag
;
2075 insn
->fixp
[i
]->fx_where
= where
;
2077 install_insn (insn
);
2080 /* Add INSN to the end of the output. */
2083 add_fixed_insn (struct mips_cl_insn
*insn
)
2085 char *f
= frag_more (insn_length (insn
));
2086 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2089 /* Start a variant frag and move INSN to the start of the variant part,
2090 marking it as fixed. The other arguments are as for frag_var. */
2093 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2094 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2096 frag_grow (max_chars
);
2097 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2099 frag_var (rs_machine_dependent
, max_chars
, var
,
2100 subtype
, symbol
, offset
, NULL
);
2103 /* Insert N copies of INSN into the history buffer, starting at
2104 position FIRST. Neither FIRST nor N need to be clipped. */
2107 insert_into_history (unsigned int first
, unsigned int n
,
2108 const struct mips_cl_insn
*insn
)
2110 if (mips_relax
.sequence
!= 2)
2114 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2116 history
[i
] = history
[i
- n
];
2122 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2123 the idea is to make it obvious at a glance that each errata is
2127 init_vr4120_conflicts (void)
2129 #define CONFLICT(FIRST, SECOND) \
2130 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2132 /* Errata 21 - [D]DIV[U] after [D]MACC */
2133 CONFLICT (MACC
, DIV
);
2134 CONFLICT (DMACC
, DIV
);
2136 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2137 CONFLICT (DMULT
, DMULT
);
2138 CONFLICT (DMULT
, DMACC
);
2139 CONFLICT (DMACC
, DMULT
);
2140 CONFLICT (DMACC
, DMACC
);
2142 /* Errata 24 - MT{LO,HI} after [D]MACC */
2143 CONFLICT (MACC
, MTHILO
);
2144 CONFLICT (DMACC
, MTHILO
);
2146 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2147 instruction is executed immediately after a MACC or DMACC
2148 instruction, the result of [either instruction] is incorrect." */
2149 CONFLICT (MACC
, MULT
);
2150 CONFLICT (MACC
, DMULT
);
2151 CONFLICT (DMACC
, MULT
);
2152 CONFLICT (DMACC
, DMULT
);
2154 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2155 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2156 DDIV or DDIVU instruction, the result of the MACC or
2157 DMACC instruction is incorrect.". */
2158 CONFLICT (DMULT
, MACC
);
2159 CONFLICT (DMULT
, DMACC
);
2160 CONFLICT (DIV
, MACC
);
2161 CONFLICT (DIV
, DMACC
);
2171 #define RTYPE_MASK 0x1ff00
2172 #define RTYPE_NUM 0x00100
2173 #define RTYPE_FPU 0x00200
2174 #define RTYPE_FCC 0x00400
2175 #define RTYPE_VEC 0x00800
2176 #define RTYPE_GP 0x01000
2177 #define RTYPE_CP0 0x02000
2178 #define RTYPE_PC 0x04000
2179 #define RTYPE_ACC 0x08000
2180 #define RTYPE_CCC 0x10000
2181 #define RNUM_MASK 0x000ff
2182 #define RWARN 0x80000
2184 #define GENERIC_REGISTER_NUMBERS \
2185 {"$0", RTYPE_NUM | 0}, \
2186 {"$1", RTYPE_NUM | 1}, \
2187 {"$2", RTYPE_NUM | 2}, \
2188 {"$3", RTYPE_NUM | 3}, \
2189 {"$4", RTYPE_NUM | 4}, \
2190 {"$5", RTYPE_NUM | 5}, \
2191 {"$6", RTYPE_NUM | 6}, \
2192 {"$7", RTYPE_NUM | 7}, \
2193 {"$8", RTYPE_NUM | 8}, \
2194 {"$9", RTYPE_NUM | 9}, \
2195 {"$10", RTYPE_NUM | 10}, \
2196 {"$11", RTYPE_NUM | 11}, \
2197 {"$12", RTYPE_NUM | 12}, \
2198 {"$13", RTYPE_NUM | 13}, \
2199 {"$14", RTYPE_NUM | 14}, \
2200 {"$15", RTYPE_NUM | 15}, \
2201 {"$16", RTYPE_NUM | 16}, \
2202 {"$17", RTYPE_NUM | 17}, \
2203 {"$18", RTYPE_NUM | 18}, \
2204 {"$19", RTYPE_NUM | 19}, \
2205 {"$20", RTYPE_NUM | 20}, \
2206 {"$21", RTYPE_NUM | 21}, \
2207 {"$22", RTYPE_NUM | 22}, \
2208 {"$23", RTYPE_NUM | 23}, \
2209 {"$24", RTYPE_NUM | 24}, \
2210 {"$25", RTYPE_NUM | 25}, \
2211 {"$26", RTYPE_NUM | 26}, \
2212 {"$27", RTYPE_NUM | 27}, \
2213 {"$28", RTYPE_NUM | 28}, \
2214 {"$29", RTYPE_NUM | 29}, \
2215 {"$30", RTYPE_NUM | 30}, \
2216 {"$31", RTYPE_NUM | 31}
2218 #define FPU_REGISTER_NAMES \
2219 {"$f0", RTYPE_FPU | 0}, \
2220 {"$f1", RTYPE_FPU | 1}, \
2221 {"$f2", RTYPE_FPU | 2}, \
2222 {"$f3", RTYPE_FPU | 3}, \
2223 {"$f4", RTYPE_FPU | 4}, \
2224 {"$f5", RTYPE_FPU | 5}, \
2225 {"$f6", RTYPE_FPU | 6}, \
2226 {"$f7", RTYPE_FPU | 7}, \
2227 {"$f8", RTYPE_FPU | 8}, \
2228 {"$f9", RTYPE_FPU | 9}, \
2229 {"$f10", RTYPE_FPU | 10}, \
2230 {"$f11", RTYPE_FPU | 11}, \
2231 {"$f12", RTYPE_FPU | 12}, \
2232 {"$f13", RTYPE_FPU | 13}, \
2233 {"$f14", RTYPE_FPU | 14}, \
2234 {"$f15", RTYPE_FPU | 15}, \
2235 {"$f16", RTYPE_FPU | 16}, \
2236 {"$f17", RTYPE_FPU | 17}, \
2237 {"$f18", RTYPE_FPU | 18}, \
2238 {"$f19", RTYPE_FPU | 19}, \
2239 {"$f20", RTYPE_FPU | 20}, \
2240 {"$f21", RTYPE_FPU | 21}, \
2241 {"$f22", RTYPE_FPU | 22}, \
2242 {"$f23", RTYPE_FPU | 23}, \
2243 {"$f24", RTYPE_FPU | 24}, \
2244 {"$f25", RTYPE_FPU | 25}, \
2245 {"$f26", RTYPE_FPU | 26}, \
2246 {"$f27", RTYPE_FPU | 27}, \
2247 {"$f28", RTYPE_FPU | 28}, \
2248 {"$f29", RTYPE_FPU | 29}, \
2249 {"$f30", RTYPE_FPU | 30}, \
2250 {"$f31", RTYPE_FPU | 31}
2252 #define FPU_CONDITION_CODE_NAMES \
2253 {"$fcc0", RTYPE_FCC | 0}, \
2254 {"$fcc1", RTYPE_FCC | 1}, \
2255 {"$fcc2", RTYPE_FCC | 2}, \
2256 {"$fcc3", RTYPE_FCC | 3}, \
2257 {"$fcc4", RTYPE_FCC | 4}, \
2258 {"$fcc5", RTYPE_FCC | 5}, \
2259 {"$fcc6", RTYPE_FCC | 6}, \
2260 {"$fcc7", RTYPE_FCC | 7}
2262 #define COPROC_CONDITION_CODE_NAMES \
2263 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2264 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2265 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2266 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2267 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2268 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2269 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2270 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2272 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2273 {"$a4", RTYPE_GP | 8}, \
2274 {"$a5", RTYPE_GP | 9}, \
2275 {"$a6", RTYPE_GP | 10}, \
2276 {"$a7", RTYPE_GP | 11}, \
2277 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2278 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2279 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2280 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2281 {"$t0", RTYPE_GP | 12}, \
2282 {"$t1", RTYPE_GP | 13}, \
2283 {"$t2", RTYPE_GP | 14}, \
2284 {"$t3", RTYPE_GP | 15}
2286 #define O32_SYMBOLIC_REGISTER_NAMES \
2287 {"$t0", RTYPE_GP | 8}, \
2288 {"$t1", RTYPE_GP | 9}, \
2289 {"$t2", RTYPE_GP | 10}, \
2290 {"$t3", RTYPE_GP | 11}, \
2291 {"$t4", RTYPE_GP | 12}, \
2292 {"$t5", RTYPE_GP | 13}, \
2293 {"$t6", RTYPE_GP | 14}, \
2294 {"$t7", RTYPE_GP | 15}, \
2295 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2296 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2297 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2298 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2300 /* Remaining symbolic register names */
2301 #define SYMBOLIC_REGISTER_NAMES \
2302 {"$zero", RTYPE_GP | 0}, \
2303 {"$at", RTYPE_GP | 1}, \
2304 {"$AT", RTYPE_GP | 1}, \
2305 {"$v0", RTYPE_GP | 2}, \
2306 {"$v1", RTYPE_GP | 3}, \
2307 {"$a0", RTYPE_GP | 4}, \
2308 {"$a1", RTYPE_GP | 5}, \
2309 {"$a2", RTYPE_GP | 6}, \
2310 {"$a3", RTYPE_GP | 7}, \
2311 {"$s0", RTYPE_GP | 16}, \
2312 {"$s1", RTYPE_GP | 17}, \
2313 {"$s2", RTYPE_GP | 18}, \
2314 {"$s3", RTYPE_GP | 19}, \
2315 {"$s4", RTYPE_GP | 20}, \
2316 {"$s5", RTYPE_GP | 21}, \
2317 {"$s6", RTYPE_GP | 22}, \
2318 {"$s7", RTYPE_GP | 23}, \
2319 {"$t8", RTYPE_GP | 24}, \
2320 {"$t9", RTYPE_GP | 25}, \
2321 {"$k0", RTYPE_GP | 26}, \
2322 {"$kt0", RTYPE_GP | 26}, \
2323 {"$k1", RTYPE_GP | 27}, \
2324 {"$kt1", RTYPE_GP | 27}, \
2325 {"$gp", RTYPE_GP | 28}, \
2326 {"$sp", RTYPE_GP | 29}, \
2327 {"$s8", RTYPE_GP | 30}, \
2328 {"$fp", RTYPE_GP | 30}, \
2329 {"$ra", RTYPE_GP | 31}
2331 #define MIPS16_SPECIAL_REGISTER_NAMES \
2332 {"$pc", RTYPE_PC | 0}
2334 #define MDMX_VECTOR_REGISTER_NAMES \
2335 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2336 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2337 {"$v2", RTYPE_VEC | 2}, \
2338 {"$v3", RTYPE_VEC | 3}, \
2339 {"$v4", RTYPE_VEC | 4}, \
2340 {"$v5", RTYPE_VEC | 5}, \
2341 {"$v6", RTYPE_VEC | 6}, \
2342 {"$v7", RTYPE_VEC | 7}, \
2343 {"$v8", RTYPE_VEC | 8}, \
2344 {"$v9", RTYPE_VEC | 9}, \
2345 {"$v10", RTYPE_VEC | 10}, \
2346 {"$v11", RTYPE_VEC | 11}, \
2347 {"$v12", RTYPE_VEC | 12}, \
2348 {"$v13", RTYPE_VEC | 13}, \
2349 {"$v14", RTYPE_VEC | 14}, \
2350 {"$v15", RTYPE_VEC | 15}, \
2351 {"$v16", RTYPE_VEC | 16}, \
2352 {"$v17", RTYPE_VEC | 17}, \
2353 {"$v18", RTYPE_VEC | 18}, \
2354 {"$v19", RTYPE_VEC | 19}, \
2355 {"$v20", RTYPE_VEC | 20}, \
2356 {"$v21", RTYPE_VEC | 21}, \
2357 {"$v22", RTYPE_VEC | 22}, \
2358 {"$v23", RTYPE_VEC | 23}, \
2359 {"$v24", RTYPE_VEC | 24}, \
2360 {"$v25", RTYPE_VEC | 25}, \
2361 {"$v26", RTYPE_VEC | 26}, \
2362 {"$v27", RTYPE_VEC | 27}, \
2363 {"$v28", RTYPE_VEC | 28}, \
2364 {"$v29", RTYPE_VEC | 29}, \
2365 {"$v30", RTYPE_VEC | 30}, \
2366 {"$v31", RTYPE_VEC | 31}
2368 #define MIPS_DSP_ACCUMULATOR_NAMES \
2369 {"$ac0", RTYPE_ACC | 0}, \
2370 {"$ac1", RTYPE_ACC | 1}, \
2371 {"$ac2", RTYPE_ACC | 2}, \
2372 {"$ac3", RTYPE_ACC | 3}
2374 static const struct regname reg_names
[] = {
2375 GENERIC_REGISTER_NUMBERS
,
2377 FPU_CONDITION_CODE_NAMES
,
2378 COPROC_CONDITION_CODE_NAMES
,
2380 /* The $txx registers depends on the abi,
2381 these will be added later into the symbol table from
2382 one of the tables below once mips_abi is set after
2383 parsing of arguments from the command line. */
2384 SYMBOLIC_REGISTER_NAMES
,
2386 MIPS16_SPECIAL_REGISTER_NAMES
,
2387 MDMX_VECTOR_REGISTER_NAMES
,
2388 MIPS_DSP_ACCUMULATOR_NAMES
,
2392 static const struct regname reg_names_o32
[] = {
2393 O32_SYMBOLIC_REGISTER_NAMES
,
2397 static const struct regname reg_names_n32n64
[] = {
2398 N32N64_SYMBOLIC_REGISTER_NAMES
,
2402 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2403 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2404 of these register symbols, return the associated vector register,
2405 otherwise return SYMVAL itself. */
2408 mips_prefer_vec_regno (unsigned int symval
)
2410 if ((symval
& -2) == (RTYPE_GP
| 2))
2411 return RTYPE_VEC
| (symval
& 1);
2415 /* Return true if the string at *SPTR is a valid register name. If so,
2416 move *SPTR past the register and store the register's symbol value
2417 in *SYMVAL. This symbol value includes the register number
2418 (RNUM_MASK) and register type (RTYPE_MASK). */
2421 mips_parse_register (char **sptr
, unsigned int *symval
)
2427 /* Find end of name. */
2429 if (is_name_beginner (*e
))
2431 while (is_part_of_name (*e
))
2434 /* Terminate name. */
2438 /* Look up the name. */
2439 symbol
= symbol_find (s
);
2442 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2446 *symval
= S_GET_VALUE (symbol
);
2450 /* Check if SPTR points at a valid register specifier according to TYPES.
2451 If so, then return 1, advance S to consume the specifier and store
2452 the register's number in REGNOP, otherwise return 0. */
2455 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2459 if (mips_parse_register (s
, ®no
))
2461 if (types
& RTYPE_VEC
)
2462 regno
= mips_prefer_vec_regno (regno
);
2471 as_warn (_("Unrecognized register name `%s'"), *s
);
2476 return regno
<= RNUM_MASK
;
2479 /* Token types for parsed operand lists. */
2480 enum mips_operand_token_type
{
2481 /* A plain register, e.g. $f2. */
2484 /* An element of a vector, e.g. $v0[1]. */
2487 /* A continuous range of registers, e.g. $s0-$s4. */
2490 /* A (possibly relocated) expression. */
2493 /* A floating-point value. */
2496 /* A single character. This can be '(', ')' or ',', but '(' only appears
2500 /* The end of the operand list. */
2504 /* A parsed operand token. */
2505 struct mips_operand_token
2507 /* The type of token. */
2508 enum mips_operand_token_type type
;
2511 /* The register symbol value for an OT_REG. */
2514 /* The register symbol value and index for an OT_REG_ELEMENT. */
2520 /* The two register symbol values involved in an OT_REG_RANGE. */
2522 unsigned int regno1
;
2523 unsigned int regno2
;
2526 /* The value of an OT_INTEGER. The value is represented as an
2527 expression and the relocation operators that were applied to
2528 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2529 relocation operators were used. */
2532 bfd_reloc_code_real_type relocs
[3];
2535 /* The binary data for an OT_FLOAT constant, and the number of bytes
2538 unsigned char data
[8];
2542 /* The character represented by an OT_CHAR. */
2547 /* An obstack used to construct lists of mips_operand_tokens. */
2548 static struct obstack mips_operand_tokens
;
2550 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2553 mips_add_token (struct mips_operand_token
*token
,
2554 enum mips_operand_token_type type
)
2557 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2560 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2561 and OT_REG tokens for them if so, and return a pointer to the first
2562 unconsumed character. Return null otherwise. */
2565 mips_parse_base_start (char *s
)
2567 struct mips_operand_token token
;
2574 SKIP_SPACE_TABS (s
);
2575 if (!mips_parse_register (&s
, ®no
))
2579 mips_add_token (&token
, OT_CHAR
);
2581 token
.u
.regno
= regno
;
2582 mips_add_token (&token
, OT_REG
);
2587 /* Parse one or more tokens from S. Return a pointer to the first
2588 unconsumed character on success. Return null if an error was found
2589 and store the error text in insn_error. FLOAT_FORMAT is as for
2590 mips_parse_arguments. */
2593 mips_parse_argument_token (char *s
, char float_format
)
2595 char *end
, *save_in
, *err
;
2596 unsigned int regno1
, regno2
;
2597 struct mips_operand_token token
;
2599 /* First look for "($reg", since we want to treat that as an
2600 OT_CHAR and OT_REG rather than an expression. */
2601 end
= mips_parse_base_start (s
);
2605 /* Handle other characters that end up as OT_CHARs. */
2606 if (*s
== ')' || *s
== ',')
2609 mips_add_token (&token
, OT_CHAR
);
2614 /* Handle tokens that start with a register. */
2615 if (mips_parse_register (&s
, ®no1
))
2617 SKIP_SPACE_TABS (s
);
2620 /* A register range. */
2622 SKIP_SPACE_TABS (s
);
2623 if (!mips_parse_register (&s
, ®no2
))
2625 insn_error
= _("Invalid register range");
2629 token
.u
.reg_range
.regno1
= regno1
;
2630 token
.u
.reg_range
.regno2
= regno2
;
2631 mips_add_token (&token
, OT_REG_RANGE
);
2636 /* A vector element. */
2637 expressionS element
;
2640 SKIP_SPACE_TABS (s
);
2641 my_getExpression (&element
, s
);
2642 if (element
.X_op
!= O_constant
)
2644 insn_error
= _("Vector element must be constant");
2648 SKIP_SPACE_TABS (s
);
2651 insn_error
= _("Missing `]'");
2656 token
.u
.reg_element
.regno
= regno1
;
2657 token
.u
.reg_element
.index
= element
.X_add_number
;
2658 mips_add_token (&token
, OT_REG_ELEMENT
);
2662 /* Looks like just a plain register. */
2663 token
.u
.regno
= regno1
;
2664 mips_add_token (&token
, OT_REG
);
2670 /* First try to treat expressions as floats. */
2671 save_in
= input_line_pointer
;
2672 input_line_pointer
= s
;
2673 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
2674 &token
.u
.flt
.length
);
2675 end
= input_line_pointer
;
2676 input_line_pointer
= save_in
;
2684 mips_add_token (&token
, OT_FLOAT
);
2689 /* Treat everything else as an integer expression. */
2690 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
2691 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
2692 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
2693 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
2695 mips_add_token (&token
, OT_INTEGER
);
2699 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
2700 if expressions should be treated as 32-bit floating-point constants,
2701 'd' if they should be treated as 64-bit floating-point constants,
2702 or 0 if they should be treated as integer expressions (the usual case).
2704 Return a list of tokens on success, otherwise return 0. The caller
2705 must obstack_free the list after use. */
2707 static struct mips_operand_token
*
2708 mips_parse_arguments (char *s
, char float_format
)
2710 struct mips_operand_token token
;
2712 SKIP_SPACE_TABS (s
);
2715 s
= mips_parse_argument_token (s
, float_format
);
2718 obstack_free (&mips_operand_tokens
,
2719 obstack_finish (&mips_operand_tokens
));
2722 SKIP_SPACE_TABS (s
);
2724 mips_add_token (&token
, OT_END
);
2725 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
2728 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2729 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2732 is_opcode_valid (const struct mips_opcode
*mo
)
2734 int isa
= mips_opts
.isa
;
2735 int ase
= mips_opts
.ase
;
2739 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2740 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2741 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
2742 ase
|= mips_ases
[i
].flags64
;
2744 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2747 /* Check whether the instruction or macro requires single-precision or
2748 double-precision floating-point support. Note that this information is
2749 stored differently in the opcode table for insns and macros. */
2750 if (mo
->pinfo
== INSN_MACRO
)
2752 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2753 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2757 fp_s
= mo
->pinfo
& FP_S
;
2758 fp_d
= mo
->pinfo
& FP_D
;
2761 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2764 if (fp_s
&& mips_opts
.soft_float
)
2770 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2771 selected ISA and architecture. */
2774 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2776 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2779 /* Return TRUE if the size of the microMIPS opcode MO matches one
2780 explicitly requested. Always TRUE in the standard MIPS mode. */
2783 is_size_valid (const struct mips_opcode
*mo
)
2785 if (!mips_opts
.micromips
)
2788 if (mips_opts
.insn32
)
2790 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
2792 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
2795 if (!forced_insn_length
)
2797 if (mo
->pinfo
== INSN_MACRO
)
2799 return forced_insn_length
== micromips_insn_length (mo
);
2802 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2803 of the preceding instruction. Always TRUE in the standard MIPS mode.
2805 We don't accept macros in 16-bit delay slots to avoid a case where
2806 a macro expansion fails because it relies on a preceding 32-bit real
2807 instruction to have matched and does not handle the operands correctly.
2808 The only macros that may expand to 16-bit instructions are JAL that
2809 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2810 and BGT (that likewise cannot be placed in a delay slot) that decay to
2811 a NOP. In all these cases the macros precede any corresponding real
2812 instruction definitions in the opcode table, so they will match in the
2813 second pass where the size of the delay slot is ignored and therefore
2814 produce correct code. */
2817 is_delay_slot_valid (const struct mips_opcode
*mo
)
2819 if (!mips_opts
.micromips
)
2822 if (mo
->pinfo
== INSN_MACRO
)
2823 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2824 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2825 && micromips_insn_length (mo
) != 4)
2827 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2828 && micromips_insn_length (mo
) != 2)
2834 /* For consistency checking, verify that all bits of OPCODE are
2835 specified either by the match/mask part of the instruction
2836 definition, or by the operand list. INSN_BITS says which
2837 bits of the instruction are significant and DECODE_OPERAND
2838 provides the mips_operand description of each operand. */
2841 validate_mips_insn (const struct mips_opcode
*opcode
,
2842 unsigned long insn_bits
,
2843 const struct mips_operand
*(*decode_operand
) (const char *))
2846 unsigned long used_bits
, doubled
, undefined
;
2847 const struct mips_operand
*operand
;
2849 if ((opcode
->mask
& opcode
->match
) != opcode
->match
)
2851 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
2852 opcode
->name
, opcode
->args
);
2856 for (s
= opcode
->args
; *s
; ++s
)
2865 operand
= decode_operand (s
);
2868 as_bad (_("internal: unknown operand type: %s %s"),
2869 opcode
->name
, opcode
->args
);
2872 used_bits
|= ((1 << operand
->size
) - 1) << operand
->lsb
;
2873 if (operand
->type
== OP_MDMX_IMM_REG
)
2874 /* Bit 5 is the format selector (OB vs QH). The opcode table
2875 has separate entries for each format. */
2876 used_bits
&= ~(1 << (operand
->lsb
+ 5));
2877 /* Skip prefix characters. */
2878 if (*s
== '+' || *s
== 'm')
2882 doubled
= used_bits
& opcode
->mask
& insn_bits
;
2885 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
2886 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
2889 used_bits
|= opcode
->mask
;
2890 undefined
= ~used_bits
& insn_bits
;
2893 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
2894 undefined
, opcode
->name
, opcode
->args
);
2897 used_bits
&= ~insn_bits
;
2900 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
2901 used_bits
, opcode
->name
, opcode
->args
);
2907 /* The microMIPS version of validate_mips_insn. */
2910 validate_micromips_insn (const struct mips_opcode
*opc
)
2912 unsigned long insn_bits
;
2913 unsigned long major
;
2914 unsigned int length
;
2916 length
= micromips_insn_length (opc
);
2917 if (length
!= 2 && length
!= 4)
2919 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
2920 "%s %s"), length
, opc
->name
, opc
->args
);
2923 major
= opc
->match
>> (10 + 8 * (length
- 2));
2924 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
2925 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
2927 as_bad (_("Internal error: bad microMIPS opcode "
2928 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
2932 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
2933 insn_bits
= 1 << 4 * length
;
2934 insn_bits
<<= 4 * length
;
2936 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
);
2939 /* This function is called once, at assembler startup time. It should set up
2940 all the tables, etc. that the MD part of the assembler will need. */
2945 const char *retval
= NULL
;
2949 if (mips_pic
!= NO_PIC
)
2951 if (g_switch_seen
&& g_switch_value
!= 0)
2952 as_bad (_("-G may not be used in position-independent code"));
2956 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2957 as_warn (_("Could not set architecture and machine"));
2959 op_hash
= hash_new ();
2961 for (i
= 0; i
< NUMOPCODES
;)
2963 const char *name
= mips_opcodes
[i
].name
;
2965 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2968 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2969 mips_opcodes
[i
].name
, retval
);
2970 /* Probably a memory allocation problem? Give up now. */
2971 as_fatal (_("Broken assembler. No assembly attempted."));
2975 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2977 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
2978 decode_mips_operand
))
2980 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2982 create_insn (&nop_insn
, mips_opcodes
+ i
);
2983 if (mips_fix_loongson2f_nop
)
2984 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2985 nop_insn
.fixed_p
= 1;
2990 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2993 mips16_op_hash
= hash_new ();
2996 while (i
< bfd_mips16_num_opcodes
)
2998 const char *name
= mips16_opcodes
[i
].name
;
3000 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3002 as_fatal (_("internal: can't hash `%s': %s"),
3003 mips16_opcodes
[i
].name
, retval
);
3006 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
3007 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
3008 != mips16_opcodes
[i
].match
))
3010 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
3011 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
3014 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3016 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3017 mips16_nop_insn
.fixed_p
= 1;
3021 while (i
< bfd_mips16_num_opcodes
3022 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3025 micromips_op_hash
= hash_new ();
3028 while (i
< bfd_micromips_num_opcodes
)
3030 const char *name
= micromips_opcodes
[i
].name
;
3032 retval
= hash_insert (micromips_op_hash
, name
,
3033 (void *) µmips_opcodes
[i
]);
3035 as_fatal (_("internal: can't hash `%s': %s"),
3036 micromips_opcodes
[i
].name
, retval
);
3038 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3040 struct mips_cl_insn
*micromips_nop_insn
;
3042 if (!validate_micromips_insn (µmips_opcodes
[i
]))
3045 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3046 micromips_nop_insn
= µmips_nop16_insn
;
3047 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3048 micromips_nop_insn
= µmips_nop32_insn
;
3052 if (micromips_nop_insn
->insn_mo
== NULL
3053 && strcmp (name
, "nop") == 0)
3055 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3056 micromips_nop_insn
->fixed_p
= 1;
3059 while (++i
< bfd_micromips_num_opcodes
3060 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3064 as_fatal (_("Broken assembler. No assembly attempted."));
3066 /* We add all the general register names to the symbol table. This
3067 helps us detect invalid uses of them. */
3068 for (i
= 0; reg_names
[i
].name
; i
++)
3069 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3070 reg_names
[i
].num
, /* & RNUM_MASK, */
3071 &zero_address_frag
));
3073 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3074 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3075 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3076 &zero_address_frag
));
3078 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3079 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3080 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3081 &zero_address_frag
));
3083 obstack_init (&mips_operand_tokens
);
3085 mips_no_prev_insn ();
3088 mips_cprmask
[0] = 0;
3089 mips_cprmask
[1] = 0;
3090 mips_cprmask
[2] = 0;
3091 mips_cprmask
[3] = 0;
3093 /* set the default alignment for the text section (2**2) */
3094 record_alignment (text_section
, 2);
3096 bfd_set_gp_size (stdoutput
, g_switch_value
);
3098 /* On a native system other than VxWorks, sections must be aligned
3099 to 16 byte boundaries. When configured for an embedded ELF
3100 target, we don't bother. */
3101 if (strncmp (TARGET_OS
, "elf", 3) != 0
3102 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3104 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3105 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3106 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3109 /* Create a .reginfo section for register masks and a .mdebug
3110 section for debugging information. */
3118 subseg
= now_subseg
;
3120 /* The ABI says this section should be loaded so that the
3121 running program can access it. However, we don't load it
3122 if we are configured for an embedded target */
3123 flags
= SEC_READONLY
| SEC_DATA
;
3124 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3125 flags
|= SEC_ALLOC
| SEC_LOAD
;
3127 if (mips_abi
!= N64_ABI
)
3129 sec
= subseg_new (".reginfo", (subsegT
) 0);
3131 bfd_set_section_flags (stdoutput
, sec
, flags
);
3132 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3134 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3138 /* The 64-bit ABI uses a .MIPS.options section rather than
3139 .reginfo section. */
3140 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3141 bfd_set_section_flags (stdoutput
, sec
, flags
);
3142 bfd_set_section_alignment (stdoutput
, sec
, 3);
3144 /* Set up the option header. */
3146 Elf_Internal_Options opthdr
;
3149 opthdr
.kind
= ODK_REGINFO
;
3150 opthdr
.size
= (sizeof (Elf_External_Options
)
3151 + sizeof (Elf64_External_RegInfo
));
3154 f
= frag_more (sizeof (Elf_External_Options
));
3155 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3156 (Elf_External_Options
*) f
);
3158 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3162 if (ECOFF_DEBUGGING
)
3164 sec
= subseg_new (".mdebug", (subsegT
) 0);
3165 (void) bfd_set_section_flags (stdoutput
, sec
,
3166 SEC_HAS_CONTENTS
| SEC_READONLY
);
3167 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3169 else if (mips_flag_pdr
)
3171 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3172 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3173 SEC_READONLY
| SEC_RELOC
3175 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3178 subseg_set (seg
, subseg
);
3181 if (! ECOFF_DEBUGGING
)
3184 if (mips_fix_vr4120
)
3185 init_vr4120_conflicts ();
3191 mips_emit_delays ();
3192 if (! ECOFF_DEBUGGING
)
3197 md_assemble (char *str
)
3199 struct mips_cl_insn insn
;
3200 bfd_reloc_code_real_type unused_reloc
[3]
3201 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3203 imm_expr
.X_op
= O_absent
;
3204 imm2_expr
.X_op
= O_absent
;
3205 offset_expr
.X_op
= O_absent
;
3206 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3207 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3208 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3210 mips_mark_labels ();
3211 mips_assembling_insn
= TRUE
;
3213 if (mips_opts
.mips16
)
3214 mips16_ip (str
, &insn
);
3217 mips_ip (str
, &insn
);
3218 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3219 str
, insn
.insn_opcode
));
3223 as_bad ("%s `%s'", insn_error
, str
);
3224 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3227 if (mips_opts
.mips16
)
3228 mips16_macro (&insn
);
3235 if (offset_expr
.X_op
!= O_absent
)
3236 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3238 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3241 mips_assembling_insn
= FALSE
;
3244 /* Convenience functions for abstracting away the differences between
3245 MIPS16 and non-MIPS16 relocations. */
3247 static inline bfd_boolean
3248 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3252 case BFD_RELOC_MIPS16_JMP
:
3253 case BFD_RELOC_MIPS16_GPREL
:
3254 case BFD_RELOC_MIPS16_GOT16
:
3255 case BFD_RELOC_MIPS16_CALL16
:
3256 case BFD_RELOC_MIPS16_HI16_S
:
3257 case BFD_RELOC_MIPS16_HI16
:
3258 case BFD_RELOC_MIPS16_LO16
:
3266 static inline bfd_boolean
3267 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3271 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3272 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3273 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3274 case BFD_RELOC_MICROMIPS_GPREL16
:
3275 case BFD_RELOC_MICROMIPS_JMP
:
3276 case BFD_RELOC_MICROMIPS_HI16
:
3277 case BFD_RELOC_MICROMIPS_HI16_S
:
3278 case BFD_RELOC_MICROMIPS_LO16
:
3279 case BFD_RELOC_MICROMIPS_LITERAL
:
3280 case BFD_RELOC_MICROMIPS_GOT16
:
3281 case BFD_RELOC_MICROMIPS_CALL16
:
3282 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3283 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3284 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3285 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3286 case BFD_RELOC_MICROMIPS_SUB
:
3287 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3288 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3289 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3290 case BFD_RELOC_MICROMIPS_HIGHEST
:
3291 case BFD_RELOC_MICROMIPS_HIGHER
:
3292 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3293 case BFD_RELOC_MICROMIPS_JALR
:
3301 static inline bfd_boolean
3302 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3304 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3307 static inline bfd_boolean
3308 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3310 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3311 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3314 static inline bfd_boolean
3315 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3317 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3318 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3321 static inline bfd_boolean
3322 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3324 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3325 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3328 static inline bfd_boolean
3329 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3331 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3334 static inline bfd_boolean
3335 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3337 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3338 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3341 /* Return true if RELOC is a PC-relative relocation that does not have
3342 full address range. */
3344 static inline bfd_boolean
3345 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3349 case BFD_RELOC_16_PCREL_S2
:
3350 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3351 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3352 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3355 case BFD_RELOC_32_PCREL
:
3356 return HAVE_64BIT_ADDRESSES
;
3363 /* Return true if the given relocation might need a matching %lo().
3364 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3365 need a matching %lo() when applied to local symbols. */
3367 static inline bfd_boolean
3368 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3370 return (HAVE_IN_PLACE_ADDENDS
3371 && (hi16_reloc_p (reloc
)
3372 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3373 all GOT16 relocations evaluate to "G". */
3374 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3377 /* Return the type of %lo() reloc needed by RELOC, given that
3378 reloc_needs_lo_p. */
3380 static inline bfd_reloc_code_real_type
3381 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3383 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3384 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3388 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3391 static inline bfd_boolean
3392 fixup_has_matching_lo_p (fixS
*fixp
)
3394 return (fixp
->fx_next
!= NULL
3395 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3396 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3397 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3400 /* Move all labels in LABELS to the current insertion point. TEXT_P
3401 says whether the labels refer to text or data. */
3404 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3406 struct insn_label_list
*l
;
3409 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3411 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3412 symbol_set_frag (l
->label
, frag_now
);
3413 val
= (valueT
) frag_now_fix ();
3414 /* MIPS16/microMIPS text labels are stored as odd. */
3415 if (text_p
&& HAVE_CODE_COMPRESSION
)
3417 S_SET_VALUE (l
->label
, val
);
3421 /* Move all labels in insn_labels to the current insertion point
3422 and treat them as text labels. */
3425 mips_move_text_labels (void)
3427 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3431 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3433 bfd_boolean linkonce
= FALSE
;
3434 segT symseg
= S_GET_SEGMENT (sym
);
3436 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3438 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3440 /* The GNU toolchain uses an extension for ELF: a section
3441 beginning with the magic string .gnu.linkonce is a
3442 linkonce section. */
3443 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3444 sizeof ".gnu.linkonce" - 1) == 0)
3450 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3451 linker to handle them specially, such as generating jalx instructions
3452 when needed. We also make them odd for the duration of the assembly,
3453 in order to generate the right sort of code. We will make them even
3454 in the adjust_symtab routine, while leaving them marked. This is
3455 convenient for the debugger and the disassembler. The linker knows
3456 to make them odd again. */
3459 mips_compressed_mark_label (symbolS
*label
)
3461 gas_assert (HAVE_CODE_COMPRESSION
);
3463 if (mips_opts
.mips16
)
3464 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3466 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3467 if ((S_GET_VALUE (label
) & 1) == 0
3468 /* Don't adjust the address if the label is global or weak, or
3469 in a link-once section, since we'll be emitting symbol reloc
3470 references to it which will be patched up by the linker, and
3471 the final value of the symbol may or may not be MIPS16/microMIPS. */
3472 && !S_IS_WEAK (label
)
3473 && !S_IS_EXTERNAL (label
)
3474 && !s_is_linkonce (label
, now_seg
))
3475 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3478 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3481 mips_compressed_mark_labels (void)
3483 struct insn_label_list
*l
;
3485 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3486 mips_compressed_mark_label (l
->label
);
3489 /* End the current frag. Make it a variant frag and record the
3493 relax_close_frag (void)
3495 mips_macro_warning
.first_frag
= frag_now
;
3496 frag_var (rs_machine_dependent
, 0, 0,
3497 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3498 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3500 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3501 mips_relax
.first_fixup
= 0;
3504 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3505 See the comment above RELAX_ENCODE for more details. */
3508 relax_start (symbolS
*symbol
)
3510 gas_assert (mips_relax
.sequence
== 0);
3511 mips_relax
.sequence
= 1;
3512 mips_relax
.symbol
= symbol
;
3515 /* Start generating the second version of a relaxable sequence.
3516 See the comment above RELAX_ENCODE for more details. */
3521 gas_assert (mips_relax
.sequence
== 1);
3522 mips_relax
.sequence
= 2;
3525 /* End the current relaxable sequence. */
3530 gas_assert (mips_relax
.sequence
== 2);
3531 relax_close_frag ();
3532 mips_relax
.sequence
= 0;
3535 /* Return true if IP is a delayed branch or jump. */
3537 static inline bfd_boolean
3538 delayed_branch_p (const struct mips_cl_insn
*ip
)
3540 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3541 | INSN_COND_BRANCH_DELAY
3542 | INSN_COND_BRANCH_LIKELY
)) != 0;
3545 /* Return true if IP is a compact branch or jump. */
3547 static inline bfd_boolean
3548 compact_branch_p (const struct mips_cl_insn
*ip
)
3550 if (mips_opts
.mips16
)
3551 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
3552 | MIPS16_INSN_COND_BRANCH
)) != 0;
3554 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3555 | INSN2_COND_BRANCH
)) != 0;
3558 /* Return true if IP is an unconditional branch or jump. */
3560 static inline bfd_boolean
3561 uncond_branch_p (const struct mips_cl_insn
*ip
)
3563 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3564 || (mips_opts
.mips16
3565 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3566 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3569 /* Return true if IP is a branch-likely instruction. */
3571 static inline bfd_boolean
3572 branch_likely_p (const struct mips_cl_insn
*ip
)
3574 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3577 /* Return the type of nop that should be used to fill the delay slot
3578 of delayed branch IP. */
3580 static struct mips_cl_insn
*
3581 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3583 if (mips_opts
.micromips
3584 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3585 return µmips_nop32_insn
;
3589 /* Return the mask of core registers that IP reads or writes. */
3592 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3594 unsigned long pinfo2
;
3598 pinfo2
= ip
->insn_mo
->pinfo2
;
3599 if (mips_opts
.micromips
)
3601 if (pinfo2
& INSN2_MOD_GPR_MD
)
3602 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3603 if (pinfo2
& INSN2_MOD_GPR_MF
)
3604 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3605 if (pinfo2
& INSN2_MOD_SP
)
3611 /* Return the mask of core registers that IP reads. */
3614 gpr_read_mask (const struct mips_cl_insn
*ip
)
3616 unsigned long pinfo
, pinfo2
;
3619 mask
= gpr_mod_mask (ip
);
3620 pinfo
= ip
->insn_mo
->pinfo
;
3621 pinfo2
= ip
->insn_mo
->pinfo2
;
3622 if (mips_opts
.mips16
)
3624 if (pinfo
& MIPS16_INSN_READ_X
)
3625 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3626 if (pinfo
& MIPS16_INSN_READ_Y
)
3627 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3628 if (pinfo
& MIPS16_INSN_READ_T
)
3630 if (pinfo
& MIPS16_INSN_READ_SP
)
3632 if (pinfo
& MIPS16_INSN_READ_31
)
3634 if (pinfo
& MIPS16_INSN_READ_Z
)
3635 mask
|= 1 << (mips16_to_32_reg_map
3636 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3637 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3638 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3642 if (pinfo2
& INSN2_READ_GPR_D
)
3643 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3644 if (pinfo
& INSN_READ_GPR_T
)
3645 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3646 if (pinfo
& INSN_READ_GPR_S
)
3647 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3648 if (pinfo2
& INSN2_READ_GP
)
3650 if (pinfo2
& INSN2_READ_GPR_31
)
3652 if (pinfo2
& INSN2_READ_GPR_Z
)
3653 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3655 if (mips_opts
.micromips
)
3657 if (pinfo2
& INSN2_READ_GPR_MC
)
3658 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3659 if (pinfo2
& INSN2_READ_GPR_ME
)
3660 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3661 if (pinfo2
& INSN2_READ_GPR_MG
)
3662 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3663 if (pinfo2
& INSN2_READ_GPR_MJ
)
3664 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3665 if (pinfo2
& INSN2_READ_GPR_MMN
)
3667 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3668 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3670 if (pinfo2
& INSN2_READ_GPR_MP
)
3671 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3672 if (pinfo2
& INSN2_READ_GPR_MQ
)
3673 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3675 /* Don't include register 0. */
3679 /* Return the mask of core registers that IP writes. */
3682 gpr_write_mask (const struct mips_cl_insn
*ip
)
3684 unsigned long pinfo
, pinfo2
;
3687 mask
= gpr_mod_mask (ip
);
3688 pinfo
= ip
->insn_mo
->pinfo
;
3689 pinfo2
= ip
->insn_mo
->pinfo2
;
3690 if (mips_opts
.mips16
)
3692 if (pinfo
& MIPS16_INSN_WRITE_X
)
3693 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3694 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3695 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3696 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3697 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3698 if (pinfo
& MIPS16_INSN_WRITE_T
)
3700 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3702 if (pinfo
& MIPS16_INSN_WRITE_31
)
3704 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3705 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3709 if (pinfo
& INSN_WRITE_GPR_D
)
3710 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3711 if (pinfo
& INSN_WRITE_GPR_T
)
3712 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3713 if (pinfo
& INSN_WRITE_GPR_S
)
3714 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3715 if (pinfo
& INSN_WRITE_GPR_31
)
3717 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3718 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3720 if (mips_opts
.micromips
)
3722 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3723 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3724 if (pinfo2
& INSN2_WRITE_GPR_MH
)
3726 mask
|= 1 << micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
3727 mask
|= 1 << micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
3729 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3730 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3731 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3732 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3734 /* Don't include register 0. */
3738 /* Return the mask of floating-point registers that IP reads. */
3741 fpr_read_mask (const struct mips_cl_insn
*ip
)
3743 unsigned long pinfo
, pinfo2
;
3747 pinfo
= ip
->insn_mo
->pinfo
;
3748 pinfo2
= ip
->insn_mo
->pinfo2
;
3749 if (!mips_opts
.mips16
)
3751 if (pinfo2
& INSN2_READ_FPR_D
)
3752 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3753 if (pinfo
& INSN_READ_FPR_S
)
3754 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3755 if (pinfo
& INSN_READ_FPR_T
)
3756 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3757 if (pinfo
& INSN_READ_FPR_R
)
3758 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3759 if (pinfo2
& INSN2_READ_FPR_Z
)
3760 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3762 /* Conservatively treat all operands to an FP_D instruction are doubles.
3763 (This is overly pessimistic for things like cvt.d.s.) */
3764 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3769 /* Return the mask of floating-point registers that IP writes. */
3772 fpr_write_mask (const struct mips_cl_insn
*ip
)
3774 unsigned long pinfo
, pinfo2
;
3778 pinfo
= ip
->insn_mo
->pinfo
;
3779 pinfo2
= ip
->insn_mo
->pinfo2
;
3780 if (!mips_opts
.mips16
)
3782 if (pinfo
& INSN_WRITE_FPR_D
)
3783 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3784 if (pinfo
& INSN_WRITE_FPR_S
)
3785 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3786 if (pinfo
& INSN_WRITE_FPR_T
)
3787 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3788 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3789 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3791 /* Conservatively treat all operands to an FP_D instruction are doubles.
3792 (This is overly pessimistic for things like cvt.s.d.) */
3793 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3798 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
3799 Check whether that is allowed. */
3802 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
3804 const char *s
= insn
->name
;
3806 if (insn
->pinfo
== INSN_MACRO
)
3807 /* Let a macro pass, we'll catch it later when it is expanded. */
3810 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
3812 /* Allow odd registers for single-precision ops. */
3813 switch (insn
->pinfo
& (FP_S
| FP_D
))
3824 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
3825 s
= strchr (insn
->name
, '.');
3826 if (s
!= NULL
&& opnum
== 2)
3827 s
= strchr (s
+ 1, '.');
3828 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
3831 /* Single-precision coprocessor loads and moves are OK too. */
3832 if ((insn
->pinfo
& FP_S
)
3833 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
3834 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
3840 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
3841 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
3842 this operand is normally printed in hex or decimal. */
3845 report_bad_range (struct mips_cl_insn
*insn
, int argnum
,
3846 offsetT val
, int min_val
, int max_val
,
3847 bfd_boolean print_hex
)
3849 if (print_hex
&& val
>= 0)
3850 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3852 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3854 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3856 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3858 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
3860 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3863 /* Report an invalid combination of position and size operands for a bitfield
3864 operation. POS and SIZE are the values that were given. */
3867 report_bad_field (offsetT pos
, offsetT size
)
3869 as_bad (_("Invalid field specification (position %ld, size %ld)"),
3870 (unsigned long) pos
, (unsigned long) size
);
3873 /* Information about an instruction argument that we're trying to match. */
3874 struct mips_arg_info
3876 /* The instruction so far. */
3877 struct mips_cl_insn
*insn
;
3879 /* The first unconsumed operand token. */
3880 struct mips_operand_token
*token
;
3882 /* The 1-based operand number, in terms of insn->insn_mo->args. */
3885 /* The 1-based argument number, for error reporting. This does not
3886 count elided optional registers, etc.. */
3889 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
3890 unsigned int last_regno
;
3892 /* If the first operand was an OP_REG, this is the register that it
3893 specified, otherwise it is ILLEGAL_REG. */
3894 unsigned int dest_regno
;
3896 /* The value of the last OP_INT operand. Only used for OP_MSB,
3897 where it gives the lsb position. */
3898 unsigned int last_op_int
;
3900 /* If true, match routines should silently reject invalid arguments.
3901 If false, match routines can accept invalid arguments as long as
3902 they report an appropriate error. They still have the option of
3903 silently rejecting arguments, in which case a generic "Invalid operands"
3904 style of error will be used instead. */
3905 bfd_boolean soft_match
;
3907 /* If true, the OP_INT match routine should treat plain symbolic operands
3908 as if a relocation operator like %lo(...) had been used. This is only
3909 ever true if the operand can be relocated. */
3910 bfd_boolean allow_nonconst
;
3912 /* When true, the OP_INT match routine should allow unsigned N-bit
3913 arguments to be used where a signed N-bit operand is expected. */
3914 bfd_boolean lax_max
;
3916 /* True if a reference to the current AT register was seen. */
3917 bfd_boolean seen_at
;
3920 /* Try to match an OT_CHAR token for character CH. Consume the token
3921 and return true on success, otherwise return false. */
3924 match_char (struct mips_arg_info
*arg
, char ch
)
3926 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
3936 /* Try to get an expression from the next tokens in ARG. Consume the
3937 tokens and return true on success, storing the expression value in
3938 VALUE and relocation types in R. */
3941 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
3942 bfd_reloc_code_real_type
*r
)
3944 if (arg
->token
->type
== OT_INTEGER
)
3946 *value
= arg
->token
->u
.integer
.value
;
3947 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
3952 /* Error-reporting is more consistent if we treat registers as O_register
3953 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
3954 then handled in the same way. */
3955 if (arg
->token
->type
== OT_REG
)
3957 value
->X_add_number
= arg
->token
->u
.regno
;
3960 else if (arg
->token
[0].type
== OT_CHAR
3961 && arg
->token
[0].u
.ch
== '('
3962 && arg
->token
[1].type
== OT_REG
3963 && arg
->token
[2].type
== OT_CHAR
3964 && arg
->token
[2].u
.ch
== ')')
3966 value
->X_add_number
= arg
->token
[1].u
.regno
;
3972 value
->X_op
= O_register
;
3973 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
3977 /* Try to get a constant expression from the next tokens in ARG. Consume
3978 the tokens and return return true on success, storing the constant value
3979 in *VALUE. Use FALLBACK as the value if the match succeeded with an
3983 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
, offsetT fallback
)
3986 bfd_reloc_code_real_type r
[3];
3988 if (!match_expression (arg
, &ex
, r
))
3991 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
3992 *value
= ex
.X_add_number
;
3995 if (arg
->soft_match
)
3997 as_bad (_("Operand %d of `%s' must be constant"),
3998 arg
->argnum
, arg
->insn
->insn_mo
->name
);
4004 /* Return the RTYPE_* flags for a register operand of type TYPE that
4005 appears in instruction OPCODE. */
4008 convert_reg_type (const struct mips_opcode
*opcode
,
4009 enum mips_reg_operand_type type
)
4014 return RTYPE_NUM
| RTYPE_GP
;
4017 /* Allow vector register names for MDMX if the instruction is a 64-bit
4018 FPR load, store or move (including moves to and from GPRs). */
4019 if ((mips_opts
.ase
& ASE_MDMX
)
4020 && (opcode
->pinfo
& FP_D
)
4021 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4022 | INSN_COPROC_MEMORY_DELAY
4023 | INSN_LOAD_COPROC_DELAY
4024 | INSN_LOAD_MEMORY_DELAY
4025 | INSN_STORE_MEMORY
)))
4026 return RTYPE_FPU
| RTYPE_VEC
;
4030 if (opcode
->pinfo
& (FP_D
| FP_S
))
4031 return RTYPE_CCC
| RTYPE_FCC
;
4035 if (opcode
->membership
& INSN_5400
)
4037 return RTYPE_FPU
| RTYPE_VEC
;
4043 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4044 return RTYPE_NUM
| RTYPE_CP0
;
4053 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4056 check_regno (struct mips_arg_info
*arg
,
4057 enum mips_reg_operand_type type
, unsigned int regno
)
4059 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4060 arg
->seen_at
= TRUE
;
4062 if (type
== OP_REG_FP
4065 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4066 as_warn (_("Float register should be even, was %d"), regno
);
4068 if (type
== OP_REG_CCC
)
4073 name
= arg
->insn
->insn_mo
->name
;
4074 length
= strlen (name
);
4075 if ((regno
& 1) != 0
4076 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4077 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4078 as_warn (_("Condition code register should be even for %s, was %d"),
4081 if ((regno
& 3) != 0
4082 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4083 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4088 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4089 a register of type TYPE. Return true on success, storing the register
4090 number in *REGNO and warning about any dubious uses. */
4093 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4094 unsigned int symval
, unsigned int *regno
)
4096 if (type
== OP_REG_VEC
)
4097 symval
= mips_prefer_vec_regno (symval
);
4098 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4101 *regno
= symval
& RNUM_MASK
;
4102 check_regno (arg
, type
, *regno
);
4106 /* Try to interpret the next token in ARG as a register of type TYPE.
4107 Consume the token and return true on success, storing the register
4108 number in *REGNO. Return false on failure. */
4111 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4112 unsigned int *regno
)
4114 if (arg
->token
->type
== OT_REG
4115 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4123 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4124 Consume the token and return true on success, storing the register numbers
4125 in *REGNO1 and *REGNO2. Return false on failure. */
4128 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4129 unsigned int *regno1
, unsigned int *regno2
)
4131 if (match_reg (arg
, type
, regno1
))
4136 if (arg
->token
->type
== OT_REG_RANGE
4137 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4138 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4139 && *regno1
<= *regno2
)
4147 /* OP_INT matcher. */
4150 match_int_operand (struct mips_arg_info
*arg
,
4151 const struct mips_operand
*operand_base
)
4153 const struct mips_int_operand
*operand
;
4154 unsigned int uval
, mask
;
4155 int min_val
, max_val
, factor
;
4157 bfd_boolean print_hex
;
4159 operand
= (const struct mips_int_operand
*) operand_base
;
4160 factor
= 1 << operand
->shift
;
4161 mask
= (1 << operand_base
->size
) - 1;
4162 max_val
= (operand
->max_val
+ operand
->bias
) << operand
->shift
;
4163 min_val
= max_val
- (mask
<< operand
->shift
);
4165 max_val
= mask
<< operand
->shift
;
4167 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4168 /* Assume we have an elided offset. The later match will fail
4169 if this turns out to be wrong. */
4171 else if (operand_base
->lsb
== 0
4172 && operand_base
->size
== 16
4173 && operand
->shift
== 0
4174 && operand
->bias
== 0
4175 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4177 /* The operand can be relocated. */
4178 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4181 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4182 /* Relocation operators were used. Accept the arguent and
4183 leave the relocation value in offset_expr and offset_relocs
4184 for the caller to process. */
4187 if (offset_expr
.X_op
!= O_constant
)
4189 /* If non-constant operands are allowed then leave them for
4190 the caller to process, otherwise fail the match. */
4191 if (!arg
->allow_nonconst
)
4193 offset_reloc
[0] = BFD_RELOC_LO16
;
4197 /* Clear the global state; we're going to install the operand
4199 sval
= offset_expr
.X_add_number
;
4200 offset_expr
.X_op
= O_absent
;
4204 if (!match_const_int (arg
, &sval
, min_val
))
4208 arg
->last_op_int
= sval
;
4210 /* Check the range. If there's a problem, record the lowest acceptable
4211 value in arg->last_op_int in order to prevent an unhelpful error
4214 Bit counts have traditionally been printed in hex by the disassembler
4215 but printed as decimal in error messages. Only resort to hex if
4216 the operand is bigger than 6 bits. */
4217 print_hex
= operand
->print_hex
&& operand_base
->size
> 6;
4218 if (sval
< min_val
|| sval
> max_val
)
4220 if (arg
->soft_match
)
4222 report_bad_range (arg
->insn
, arg
->argnum
, sval
, min_val
, max_val
,
4224 arg
->last_op_int
= min_val
;
4226 else if (sval
% factor
)
4228 if (arg
->soft_match
)
4230 as_bad (print_hex
&& sval
>= 0
4231 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4232 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4233 arg
->argnum
, arg
->insn
->insn_mo
->name
, factor
,
4234 (unsigned long) sval
);
4235 arg
->last_op_int
= min_val
;
4238 uval
= (unsigned int) sval
>> operand
->shift
;
4239 uval
-= operand
->bias
;
4241 /* Handle -mfix-cn63xxp1. */
4243 && mips_fix_cn63xxp1
4244 && !mips_opts
.micromips
4245 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4260 /* The rest must be changed to 28. */
4265 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4269 /* OP_MAPPED_INT matcher. */
4272 match_mapped_int_operand (struct mips_arg_info
*arg
,
4273 const struct mips_operand
*operand_base
)
4275 const struct mips_mapped_int_operand
*operand
;
4276 unsigned int uval
, num_vals
;
4279 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4280 if (!match_const_int (arg
, &sval
, operand
->int_map
[0]))
4283 num_vals
= 1 << operand_base
->size
;
4284 for (uval
= 0; uval
< num_vals
; uval
++)
4285 if (operand
->int_map
[uval
] == sval
)
4287 if (uval
== num_vals
)
4290 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4294 /* OP_MSB matcher. */
4297 match_msb_operand (struct mips_arg_info
*arg
,
4298 const struct mips_operand
*operand_base
)
4300 const struct mips_msb_operand
*operand
;
4301 int min_val
, max_val
, max_high
;
4302 offsetT size
, sval
, high
;
4304 operand
= (const struct mips_msb_operand
*) operand_base
;
4305 min_val
= operand
->bias
;
4306 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4307 max_high
= operand
->opsize
;
4309 if (!match_const_int (arg
, &size
, 1))
4312 high
= size
+ arg
->last_op_int
;
4313 sval
= operand
->add_lsb
? high
: size
;
4315 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4317 if (arg
->soft_match
)
4319 report_bad_field (arg
->last_op_int
, size
);
4322 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4326 /* OP_REG matcher. */
4329 match_reg_operand (struct mips_arg_info
*arg
,
4330 const struct mips_operand
*operand_base
)
4332 const struct mips_reg_operand
*operand
;
4333 unsigned int regno
, uval
, num_vals
;
4335 operand
= (const struct mips_reg_operand
*) operand_base
;
4336 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4339 if (operand
->reg_map
)
4341 num_vals
= 1 << operand
->root
.size
;
4342 for (uval
= 0; uval
< num_vals
; uval
++)
4343 if (operand
->reg_map
[uval
] == regno
)
4345 if (num_vals
== uval
)
4351 arg
->last_regno
= regno
;
4352 if (arg
->opnum
== 1)
4353 arg
->dest_regno
= regno
;
4354 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4358 /* OP_REG_PAIR matcher. */
4361 match_reg_pair_operand (struct mips_arg_info
*arg
,
4362 const struct mips_operand
*operand_base
)
4364 const struct mips_reg_pair_operand
*operand
;
4365 unsigned int regno1
, regno2
, uval
, num_vals
;
4367 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4368 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4369 || !match_char (arg
, ',')
4370 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4373 num_vals
= 1 << operand_base
->size
;
4374 for (uval
= 0; uval
< num_vals
; uval
++)
4375 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4377 if (uval
== num_vals
)
4380 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4384 /* OP_PCREL matcher. The caller chooses the relocation type. */
4387 match_pcrel_operand (struct mips_arg_info
*arg
)
4389 bfd_reloc_code_real_type r
[3];
4391 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4394 /* OP_PERF_REG matcher. */
4397 match_perf_reg_operand (struct mips_arg_info
*arg
,
4398 const struct mips_operand
*operand
)
4402 if (!match_const_int (arg
, &sval
, 0))
4407 || (mips_opts
.arch
== CPU_R5900
4408 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4409 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4411 if (arg
->soft_match
)
4413 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval
);
4416 insn_insert_operand (arg
->insn
, operand
, sval
);
4420 /* OP_ADDIUSP matcher. */
4423 match_addiusp_operand (struct mips_arg_info
*arg
,
4424 const struct mips_operand
*operand
)
4429 if (!match_const_int (arg
, &sval
, -256))
4436 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4439 uval
= (unsigned int) sval
;
4440 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4441 insn_insert_operand (arg
->insn
, operand
, uval
);
4445 /* OP_CLO_CLZ_DEST matcher. */
4448 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4449 const struct mips_operand
*operand
)
4453 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4456 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4460 /* OP_LWM_SWM_LIST matcher. */
4463 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4464 const struct mips_operand
*operand
)
4466 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4467 struct mips_arg_info reset
;
4470 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4474 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4479 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4482 while (match_char (arg
, ',')
4483 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4486 if (operand
->size
== 2)
4488 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4494 and any permutations of these. */
4495 if ((reglist
& 0xfff1ffff) != 0x80010000)
4498 sregs
= (reglist
>> 17) & 7;
4503 /* The list must include at least one of ra and s0-sN,
4504 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4505 which are $23 and $30 respectively.) E.g.:
4513 and any permutations of these. */
4514 if ((reglist
& 0x3f00ffff) != 0)
4517 ra
= (reglist
>> 27) & 0x10;
4518 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4521 if ((sregs
& -sregs
) != sregs
)
4524 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4528 /* OP_ENTRY_EXIT_LIST matcher. */
4531 match_entry_exit_operand (struct mips_arg_info
*arg
,
4532 const struct mips_operand
*operand
)
4535 bfd_boolean is_exit
;
4537 /* The format is the same for both ENTRY and EXIT, but the constraints
4539 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4540 mask
= (is_exit
? 7 << 3 : 0);
4543 unsigned int regno1
, regno2
;
4544 bfd_boolean is_freg
;
4546 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4548 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4553 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4556 mask
|= (5 + regno2
) << 3;
4558 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4559 mask
|= (regno2
- 3) << 3;
4560 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4561 mask
|= (regno2
- 15) << 1;
4562 else if (regno1
== RA
&& regno2
== RA
)
4567 while (match_char (arg
, ','));
4569 insn_insert_operand (arg
->insn
, operand
, mask
);
4573 /* OP_SAVE_RESTORE_LIST matcher. */
4576 match_save_restore_list_operand (struct mips_arg_info
*arg
)
4578 unsigned int opcode
, args
, statics
, sregs
;
4579 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
4584 opcode
= arg
->insn
->insn_opcode
;
4586 num_frame_sizes
= 0;
4592 unsigned int regno1
, regno2
;
4594 if (arg
->token
->type
== OT_INTEGER
)
4596 /* Handle the frame size. */
4597 if (!match_const_int (arg
, &frame_size
, 0))
4599 num_frame_sizes
+= 1;
4603 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4606 while (regno1
<= regno2
)
4608 if (regno1
>= 4 && regno1
<= 7)
4610 if (num_frame_sizes
== 0)
4612 args
|= 1 << (regno1
- 4);
4614 /* statics $a0-$a3 */
4615 statics
|= 1 << (regno1
- 4);
4617 else if (regno1
>= 16 && regno1
<= 23)
4619 sregs
|= 1 << (regno1
- 16);
4620 else if (regno1
== 30)
4623 else if (regno1
== 31)
4624 /* Add $ra to insn. */
4634 while (match_char (arg
, ','));
4636 /* Encode args/statics combination. */
4639 else if (args
== 0xf)
4640 /* All $a0-$a3 are args. */
4641 opcode
|= MIPS16_ALL_ARGS
<< 16;
4642 else if (statics
== 0xf)
4643 /* All $a0-$a3 are statics. */
4644 opcode
|= MIPS16_ALL_STATICS
<< 16;
4647 /* Count arg registers. */
4657 /* Count static registers. */
4659 while (statics
& 0x8)
4661 statics
= (statics
<< 1) & 0xf;
4667 /* Encode args/statics. */
4668 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
4671 /* Encode $s0/$s1. */
4672 if (sregs
& (1 << 0)) /* $s0 */
4674 if (sregs
& (1 << 1)) /* $s1 */
4678 /* Encode $s2-$s8. */
4687 opcode
|= num_sregs
<< 24;
4689 /* Encode frame size. */
4690 if (num_frame_sizes
== 0)
4691 error
= _("Missing frame size");
4692 else if (num_frame_sizes
> 1)
4693 error
= _("Frame size specified twice");
4694 else if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
4695 error
= _("Invalid frame size");
4696 else if (frame_size
!= 128 || (opcode
>> 16) != 0)
4699 opcode
|= (((frame_size
& 0xf0) << 16)
4700 | (frame_size
& 0x0f));
4705 if (arg
->soft_match
)
4707 as_bad ("%s", error
);
4710 /* Finally build the instruction. */
4711 if ((opcode
>> 16) != 0 || frame_size
== 0)
4712 opcode
|= MIPS16_EXTEND
;
4713 arg
->insn
->insn_opcode
= opcode
;
4717 /* OP_MDMX_IMM_REG matcher. */
4720 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
4721 const struct mips_operand
*operand
)
4723 unsigned int regno
, uval
;
4725 const struct mips_opcode
*opcode
;
4727 /* The mips_opcode records whether this is an octobyte or quadhalf
4728 instruction. Start out with that bit in place. */
4729 opcode
= arg
->insn
->insn_mo
;
4730 uval
= mips_extract_operand (operand
, opcode
->match
);
4731 is_qh
= (uval
!= 0);
4733 if (arg
->token
->type
== OT_REG
|| arg
->token
->type
== OT_REG_ELEMENT
)
4735 if ((opcode
->membership
& INSN_5400
)
4736 && strcmp (opcode
->name
, "rzu.ob") == 0)
4738 if (arg
->soft_match
)
4740 as_bad (_("Operand %d of `%s' must be an immediate"),
4741 arg
->argnum
, opcode
->name
);
4744 /* Check whether this is a vector register or a broadcast of
4745 a single element. */
4746 if (arg
->token
->type
== OT_REG_ELEMENT
)
4748 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.reg_element
.regno
,
4751 if (arg
->token
->u
.reg_element
.index
> (is_qh
? 3 : 7))
4753 if (arg
->soft_match
)
4755 as_bad (_("Invalid element selector"));
4758 uval
|= arg
->token
->u
.reg_element
.index
<< (is_qh
? 2 : 1) << 5;
4762 /* A full vector. */
4763 if ((opcode
->membership
& INSN_5400
)
4764 && (strcmp (opcode
->name
, "sll.ob") == 0
4765 || strcmp (opcode
->name
, "srl.ob") == 0))
4767 if (arg
->soft_match
)
4769 as_bad (_("Operand %d of `%s' must be scalar"),
4770 arg
->argnum
, opcode
->name
);
4773 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
4776 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
4778 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
4787 if (!match_const_int (arg
, &sval
, 0))
4789 if (sval
< 0 || sval
> 31)
4791 if (arg
->soft_match
)
4793 report_bad_range (arg
->insn
, arg
->argnum
, sval
, 0, 31, FALSE
);
4795 uval
|= (sval
& 31);
4797 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
4799 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
4801 insn_insert_operand (arg
->insn
, operand
, uval
);
4805 /* OP_PC matcher. */
4808 match_pc_operand (struct mips_arg_info
*arg
)
4810 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
4818 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
4819 register that we need to match. */
4822 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
4826 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
4829 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
4830 the length of the value in bytes (4 for float, 8 for double) and
4831 USING_GPRS says whether the destination is a GPR rather than an FPR.
4833 Return the constant in IMM and OFFSET as follows:
4835 - If the constant should be loaded via memory, set IMM to O_absent and
4836 OFFSET to the memory address.
4838 - Otherwise, if the constant should be loaded into two 32-bit registers,
4839 set IMM to the O_constant to load into the high register and OFFSET
4840 to the corresponding value for the low register.
4842 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
4844 These constants only appear as the last operand in an instruction,
4845 and every instruction that accepts them in any variant accepts them
4846 in all variants. This means we don't have to worry about backing out
4847 any changes if the instruction does not match. We just match
4848 unconditionally and report an error if the constant is invalid. */
4851 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
4852 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
4857 const char *newname
;
4858 unsigned char *data
;
4860 /* Where the constant is placed is based on how the MIPS assembler
4863 length == 4 && using_gprs -- immediate value only
4864 length == 8 && using_gprs -- .rdata or immediate value
4865 length == 4 && !using_gprs -- .lit4 or immediate value
4866 length == 8 && !using_gprs -- .lit8 or immediate value
4868 The .lit4 and .lit8 sections are only used if permitted by the
4870 if (arg
->token
->type
!= OT_FLOAT
)
4873 gas_assert (arg
->token
->u
.flt
.length
== length
);
4874 data
= arg
->token
->u
.flt
.data
;
4877 /* Handle 32-bit constants for which an immediate value is best. */
4880 || g_switch_value
< 4
4881 || (data
[0] == 0 && data
[1] == 0)
4882 || (data
[2] == 0 && data
[3] == 0)))
4884 imm
->X_op
= O_constant
;
4885 if (!target_big_endian
)
4886 imm
->X_add_number
= bfd_getl32 (data
);
4888 imm
->X_add_number
= bfd_getb32 (data
);
4889 offset
->X_op
= O_absent
;
4893 /* Handle 64-bit constants for which an immediate value is best. */
4895 && !mips_disable_float_construction
4896 /* Constants can only be constructed in GPRs and copied
4897 to FPRs if the GPRs are at least as wide as the FPRs.
4898 Force the constant into memory if we are using 64-bit FPRs
4899 but the GPRs are only 32 bits wide. */
4900 /* ??? No longer true with the addition of MTHC1, but this
4901 is legacy code... */
4902 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
4903 && ((data
[0] == 0 && data
[1] == 0)
4904 || (data
[2] == 0 && data
[3] == 0))
4905 && ((data
[4] == 0 && data
[5] == 0)
4906 || (data
[6] == 0 && data
[7] == 0)))
4908 /* The value is simple enough to load with a couple of instructions.
4909 If using 32-bit registers, set IMM to the high order 32 bits and
4910 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
4912 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
4914 imm
->X_op
= O_constant
;
4915 offset
->X_op
= O_constant
;
4916 if (!target_big_endian
)
4918 imm
->X_add_number
= bfd_getl32 (data
+ 4);
4919 offset
->X_add_number
= bfd_getl32 (data
);
4923 imm
->X_add_number
= bfd_getb32 (data
);
4924 offset
->X_add_number
= bfd_getb32 (data
+ 4);
4926 if (offset
->X_add_number
== 0)
4927 offset
->X_op
= O_absent
;
4931 imm
->X_op
= O_constant
;
4932 if (!target_big_endian
)
4933 imm
->X_add_number
= bfd_getl64 (data
);
4935 imm
->X_add_number
= bfd_getb64 (data
);
4936 offset
->X_op
= O_absent
;
4941 /* Switch to the right section. */
4943 subseg
= now_subseg
;
4946 gas_assert (!using_gprs
&& g_switch_value
>= 4);
4951 if (using_gprs
|| g_switch_value
< 8)
4952 newname
= RDATA_SECTION_NAME
;
4957 new_seg
= subseg_new (newname
, (subsegT
) 0);
4958 bfd_set_section_flags (stdoutput
, new_seg
,
4959 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
4960 frag_align (length
== 4 ? 2 : 3, 0, 0);
4961 if (strncmp (TARGET_OS
, "elf", 3) != 0)
4962 record_alignment (new_seg
, 4);
4964 record_alignment (new_seg
, length
== 4 ? 2 : 3);
4966 as_bad (_("Can't use floating point insn in this section"));
4968 /* Set the argument to the current address in the section. */
4969 imm
->X_op
= O_absent
;
4970 offset
->X_op
= O_symbol
;
4971 offset
->X_add_symbol
= symbol_temp_new_now ();
4972 offset
->X_add_number
= 0;
4974 /* Put the floating point number into the section. */
4975 p
= frag_more (length
);
4976 memcpy (p
, data
, length
);
4978 /* Switch back to the original section. */
4979 subseg_set (seg
, subseg
);
4983 /* S is the text seen for ARG. Match it against OPERAND. Return the end
4984 of the argument text if the match is successful, otherwise return null. */
4987 match_operand (struct mips_arg_info
*arg
,
4988 const struct mips_operand
*operand
)
4990 switch (operand
->type
)
4993 return match_int_operand (arg
, operand
);
4996 return match_mapped_int_operand (arg
, operand
);
4999 return match_msb_operand (arg
, operand
);
5002 return match_reg_operand (arg
, operand
);
5005 return match_reg_pair_operand (arg
, operand
);
5008 return match_pcrel_operand (arg
);
5011 return match_perf_reg_operand (arg
, operand
);
5013 case OP_ADDIUSP_INT
:
5014 return match_addiusp_operand (arg
, operand
);
5016 case OP_CLO_CLZ_DEST
:
5017 return match_clo_clz_dest_operand (arg
, operand
);
5019 case OP_LWM_SWM_LIST
:
5020 return match_lwm_swm_list_operand (arg
, operand
);
5022 case OP_ENTRY_EXIT_LIST
:
5023 return match_entry_exit_operand (arg
, operand
);
5025 case OP_SAVE_RESTORE_LIST
:
5026 return match_save_restore_list_operand (arg
);
5028 case OP_MDMX_IMM_REG
:
5029 return match_mdmx_imm_reg_operand (arg
, operand
);
5031 case OP_REPEAT_DEST_REG
:
5032 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5034 case OP_REPEAT_PREV_REG
:
5035 return match_tied_reg_operand (arg
, arg
->last_regno
);
5038 return match_pc_operand (arg
);
5043 /* ARG is the state after successfully matching an instruction.
5044 Issue any queued-up warnings. */
5047 check_completed_insn (struct mips_arg_info
*arg
)
5052 as_warn (_("Used $at without \".set noat\""));
5054 as_warn (_("Used $%u with \".set at=$%u\""), AT
, AT
);
5058 /* Return true if modifying general-purpose register REG needs a delay. */
5061 reg_needs_delay (unsigned int reg
)
5063 unsigned long prev_pinfo
;
5065 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5066 if (!mips_opts
.noreorder
5067 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
) && !gpr_interlocks
)
5068 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5069 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5075 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5076 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5077 by VR4120 errata. */
5080 classify_vr4120_insn (const char *name
)
5082 if (strncmp (name
, "macc", 4) == 0)
5083 return FIX_VR4120_MACC
;
5084 if (strncmp (name
, "dmacc", 5) == 0)
5085 return FIX_VR4120_DMACC
;
5086 if (strncmp (name
, "mult", 4) == 0)
5087 return FIX_VR4120_MULT
;
5088 if (strncmp (name
, "dmult", 5) == 0)
5089 return FIX_VR4120_DMULT
;
5090 if (strstr (name
, "div"))
5091 return FIX_VR4120_DIV
;
5092 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5093 return FIX_VR4120_MTHILO
;
5094 return NUM_FIX_VR4120_CLASSES
;
5097 #define INSN_ERET 0x42000018
5098 #define INSN_DERET 0x4200001f
5100 /* Return the number of instructions that must separate INSN1 and INSN2,
5101 where INSN1 is the earlier instruction. Return the worst-case value
5102 for any INSN2 if INSN2 is null. */
5105 insns_between (const struct mips_cl_insn
*insn1
,
5106 const struct mips_cl_insn
*insn2
)
5108 unsigned long pinfo1
, pinfo2
;
5111 /* If INFO2 is null, pessimistically assume that all flags are set for
5112 the second instruction. */
5113 pinfo1
= insn1
->insn_mo
->pinfo
;
5114 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5116 /* For most targets, write-after-read dependencies on the HI and LO
5117 registers must be separated by at least two instructions. */
5118 if (!hilo_interlocks
)
5120 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5122 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5126 /* If we're working around r7000 errata, there must be two instructions
5127 between an mfhi or mflo and any instruction that uses the result. */
5128 if (mips_7000_hilo_fix
5129 && !mips_opts
.micromips
5130 && MF_HILO_INSN (pinfo1
)
5131 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5134 /* If we're working around 24K errata, one instruction is required
5135 if an ERET or DERET is followed by a branch instruction. */
5136 if (mips_fix_24k
&& !mips_opts
.micromips
)
5138 if (insn1
->insn_opcode
== INSN_ERET
5139 || insn1
->insn_opcode
== INSN_DERET
)
5142 || insn2
->insn_opcode
== INSN_ERET
5143 || insn2
->insn_opcode
== INSN_DERET
5144 || delayed_branch_p (insn2
))
5149 /* If working around VR4120 errata, check for combinations that need
5150 a single intervening instruction. */
5151 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5153 unsigned int class1
, class2
;
5155 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5156 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5160 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5161 if (vr4120_conflicts
[class1
] & (1 << class2
))
5166 if (!HAVE_CODE_COMPRESSION
)
5168 /* Check for GPR or coprocessor load delays. All such delays
5169 are on the RT register. */
5170 /* Itbl support may require additional care here. */
5171 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
5172 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5174 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5178 /* Check for generic coprocessor hazards.
5180 This case is not handled very well. There is no special
5181 knowledge of CP0 handling, and the coprocessors other than
5182 the floating point unit are not distinguished at all. */
5183 /* Itbl support may require additional care here. FIXME!
5184 Need to modify this to include knowledge about
5185 user specified delays! */
5186 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5187 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5189 /* Handle cases where INSN1 writes to a known general coprocessor
5190 register. There must be a one instruction delay before INSN2
5191 if INSN2 reads that register, otherwise no delay is needed. */
5192 mask
= fpr_write_mask (insn1
);
5195 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5200 /* Read-after-write dependencies on the control registers
5201 require a two-instruction gap. */
5202 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5203 && (pinfo2
& INSN_READ_COND_CODE
))
5206 /* We don't know exactly what INSN1 does. If INSN2 is
5207 also a coprocessor instruction, assume there must be
5208 a one instruction gap. */
5209 if (pinfo2
& INSN_COP
)
5214 /* Check for read-after-write dependencies on the coprocessor
5215 control registers in cases where INSN1 does not need a general
5216 coprocessor delay. This means that INSN1 is a floating point
5217 comparison instruction. */
5218 /* Itbl support may require additional care here. */
5219 else if (!cop_interlocks
5220 && (pinfo1
& INSN_WRITE_COND_CODE
)
5221 && (pinfo2
& INSN_READ_COND_CODE
))
5228 /* Return the number of nops that would be needed to work around the
5229 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5230 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5231 that are contained within the first IGNORE instructions of HIST. */
5234 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5235 const struct mips_cl_insn
*insn
)
5240 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5241 are not affected by the errata. */
5243 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5244 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5245 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5248 /* Search for the first MFLO or MFHI. */
5249 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5250 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5252 /* Extract the destination register. */
5253 mask
= gpr_write_mask (&hist
[i
]);
5255 /* No nops are needed if INSN reads that register. */
5256 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5259 /* ...or if any of the intervening instructions do. */
5260 for (j
= 0; j
< i
; j
++)
5261 if (gpr_read_mask (&hist
[j
]) & mask
)
5265 return MAX_VR4130_NOPS
- i
;
5270 #define BASE_REG_EQ(INSN1, INSN2) \
5271 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5272 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5274 /* Return the minimum alignment for this store instruction. */
5277 fix_24k_align_to (const struct mips_opcode
*mo
)
5279 if (strcmp (mo
->name
, "sh") == 0)
5282 if (strcmp (mo
->name
, "swc1") == 0
5283 || strcmp (mo
->name
, "swc2") == 0
5284 || strcmp (mo
->name
, "sw") == 0
5285 || strcmp (mo
->name
, "sc") == 0
5286 || strcmp (mo
->name
, "s.s") == 0)
5289 if (strcmp (mo
->name
, "sdc1") == 0
5290 || strcmp (mo
->name
, "sdc2") == 0
5291 || strcmp (mo
->name
, "s.d") == 0)
5298 struct fix_24k_store_info
5300 /* Immediate offset, if any, for this store instruction. */
5302 /* Alignment required by this store instruction. */
5304 /* True for register offsets. */
5305 int register_offset
;
5308 /* Comparison function used by qsort. */
5311 fix_24k_sort (const void *a
, const void *b
)
5313 const struct fix_24k_store_info
*pos1
= a
;
5314 const struct fix_24k_store_info
*pos2
= b
;
5316 return (pos1
->off
- pos2
->off
);
5319 /* INSN is a store instruction. Try to record the store information
5320 in STINFO. Return false if the information isn't known. */
5323 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5324 const struct mips_cl_insn
*insn
)
5326 /* The instruction must have a known offset. */
5327 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5330 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5331 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5335 /* Return the number of nops that would be needed to work around the 24k
5336 "lost data on stores during refill" errata if instruction INSN
5337 immediately followed the 2 instructions described by HIST.
5338 Ignore hazards that are contained within the first IGNORE
5339 instructions of HIST.
5341 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5342 for the data cache refills and store data. The following describes
5343 the scenario where the store data could be lost.
5345 * A data cache miss, due to either a load or a store, causing fill
5346 data to be supplied by the memory subsystem
5347 * The first three doublewords of fill data are returned and written
5349 * A sequence of four stores occurs in consecutive cycles around the
5350 final doubleword of the fill:
5354 * Zero, One or more instructions
5357 The four stores A-D must be to different doublewords of the line that
5358 is being filled. The fourth instruction in the sequence above permits
5359 the fill of the final doubleword to be transferred from the FSB into
5360 the cache. In the sequence above, the stores may be either integer
5361 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5362 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5363 different doublewords on the line. If the floating point unit is
5364 running in 1:2 mode, it is not possible to create the sequence above
5365 using only floating point store instructions.
5367 In this case, the cache line being filled is incorrectly marked
5368 invalid, thereby losing the data from any store to the line that
5369 occurs between the original miss and the completion of the five
5370 cycle sequence shown above.
5372 The workarounds are:
5374 * Run the data cache in write-through mode.
5375 * Insert a non-store instruction between
5376 Store A and Store B or Store B and Store C. */
5379 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5380 const struct mips_cl_insn
*insn
)
5382 struct fix_24k_store_info pos
[3];
5383 int align
, i
, base_offset
;
5388 /* If the previous instruction wasn't a store, there's nothing to
5390 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5393 /* If the instructions after the previous one are unknown, we have
5394 to assume the worst. */
5398 /* Check whether we are dealing with three consecutive stores. */
5399 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5400 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5403 /* If we don't know the relationship between the store addresses,
5404 assume the worst. */
5405 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5406 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5409 if (!fix_24k_record_store_info (&pos
[0], insn
)
5410 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5411 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5414 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5416 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5417 X bytes and such that the base register + X is known to be aligned
5420 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5424 align
= pos
[0].align_to
;
5425 base_offset
= pos
[0].off
;
5426 for (i
= 1; i
< 3; i
++)
5427 if (align
< pos
[i
].align_to
)
5429 align
= pos
[i
].align_to
;
5430 base_offset
= pos
[i
].off
;
5432 for (i
= 0; i
< 3; i
++)
5433 pos
[i
].off
-= base_offset
;
5436 pos
[0].off
&= ~align
+ 1;
5437 pos
[1].off
&= ~align
+ 1;
5438 pos
[2].off
&= ~align
+ 1;
5440 /* If any two stores write to the same chunk, they also write to the
5441 same doubleword. The offsets are still sorted at this point. */
5442 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5445 /* A range of at least 9 bytes is needed for the stores to be in
5446 non-overlapping doublewords. */
5447 if (pos
[2].off
- pos
[0].off
<= 8)
5450 if (pos
[2].off
- pos
[1].off
>= 24
5451 || pos
[1].off
- pos
[0].off
>= 24
5452 || pos
[2].off
- pos
[0].off
>= 32)
5458 /* Return the number of nops that would be needed if instruction INSN
5459 immediately followed the MAX_NOPS instructions given by HIST,
5460 where HIST[0] is the most recent instruction. Ignore hazards
5461 between INSN and the first IGNORE instructions in HIST.
5463 If INSN is null, return the worse-case number of nops for any
5467 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
5468 const struct mips_cl_insn
*insn
)
5470 int i
, nops
, tmp_nops
;
5473 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
5475 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
5476 if (tmp_nops
> nops
)
5480 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
5482 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
5483 if (tmp_nops
> nops
)
5487 if (mips_fix_24k
&& !mips_opts
.micromips
)
5489 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
5490 if (tmp_nops
> nops
)
5497 /* The variable arguments provide NUM_INSNS extra instructions that
5498 might be added to HIST. Return the largest number of nops that
5499 would be needed after the extended sequence, ignoring hazards
5500 in the first IGNORE instructions. */
5503 nops_for_sequence (int num_insns
, int ignore
,
5504 const struct mips_cl_insn
*hist
, ...)
5507 struct mips_cl_insn buffer
[MAX_NOPS
];
5508 struct mips_cl_insn
*cursor
;
5511 va_start (args
, hist
);
5512 cursor
= buffer
+ num_insns
;
5513 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
5514 while (cursor
> buffer
)
5515 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
5517 nops
= nops_for_insn (ignore
, buffer
, NULL
);
5522 /* Like nops_for_insn, but if INSN is a branch, take into account the
5523 worst-case delay for the branch target. */
5526 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
5527 const struct mips_cl_insn
*insn
)
5531 nops
= nops_for_insn (ignore
, hist
, insn
);
5532 if (delayed_branch_p (insn
))
5534 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
5535 hist
, insn
, get_delay_slot_nop (insn
));
5536 if (tmp_nops
> nops
)
5539 else if (compact_branch_p (insn
))
5541 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
5542 if (tmp_nops
> nops
)
5548 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5551 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
5553 gas_assert (!HAVE_CODE_COMPRESSION
);
5554 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
5555 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
5558 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5559 jr target pc &= 'hffff_ffff_cfff_ffff. */
5562 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
5564 gas_assert (!HAVE_CODE_COMPRESSION
);
5565 if (strcmp (ip
->insn_mo
->name
, "j") == 0
5566 || strcmp (ip
->insn_mo
->name
, "jr") == 0
5567 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
5575 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
5576 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
5579 ep
.X_op
= O_constant
;
5580 ep
.X_add_number
= 0xcfff0000;
5581 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
5582 ep
.X_add_number
= 0xffff;
5583 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
5584 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
5589 fix_loongson2f (struct mips_cl_insn
* ip
)
5591 if (mips_fix_loongson2f_nop
)
5592 fix_loongson2f_nop (ip
);
5594 if (mips_fix_loongson2f_jump
)
5595 fix_loongson2f_jump (ip
);
5598 /* IP is a branch that has a delay slot, and we need to fill it
5599 automatically. Return true if we can do that by swapping IP
5600 with the previous instruction.
5601 ADDRESS_EXPR is an operand of the instruction to be used with
5605 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5606 bfd_reloc_code_real_type
*reloc_type
)
5608 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
5609 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
5611 /* -O2 and above is required for this optimization. */
5612 if (mips_optimize
< 2)
5615 /* If we have seen .set volatile or .set nomove, don't optimize. */
5616 if (mips_opts
.nomove
)
5619 /* We can't swap if the previous instruction's position is fixed. */
5620 if (history
[0].fixed_p
)
5623 /* If the previous previous insn was in a .set noreorder, we can't
5624 swap. Actually, the MIPS assembler will swap in this situation.
5625 However, gcc configured -with-gnu-as will generate code like
5633 in which we can not swap the bne and INSN. If gcc is not configured
5634 -with-gnu-as, it does not output the .set pseudo-ops. */
5635 if (history
[1].noreorder_p
)
5638 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5639 This means that the previous instruction was a 4-byte one anyhow. */
5640 if (mips_opts
.mips16
&& history
[0].fixp
[0])
5643 /* If the branch is itself the target of a branch, we can not swap.
5644 We cheat on this; all we check for is whether there is a label on
5645 this instruction. If there are any branches to anything other than
5646 a label, users must use .set noreorder. */
5647 if (seg_info (now_seg
)->label_list
)
5650 /* If the previous instruction is in a variant frag other than this
5651 branch's one, we cannot do the swap. This does not apply to
5652 MIPS16 code, which uses variant frags for different purposes. */
5653 if (!mips_opts
.mips16
5655 && history
[0].frag
->fr_type
== rs_machine_dependent
)
5658 /* We do not swap with instructions that cannot architecturally
5659 be placed in a branch delay slot, such as SYNC or ERET. We
5660 also refrain from swapping with a trap instruction, since it
5661 complicates trap handlers to have the trap instruction be in
5663 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5664 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
5667 /* Check for conflicts between the branch and the instructions
5668 before the candidate delay slot. */
5669 if (nops_for_insn (0, history
+ 1, ip
) > 0)
5672 /* Check for conflicts between the swapped sequence and the
5673 target of the branch. */
5674 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
5677 /* If the branch reads a register that the previous
5678 instruction sets, we can not swap. */
5679 gpr_read
= gpr_read_mask (ip
);
5680 prev_gpr_write
= gpr_write_mask (&history
[0]);
5681 if (gpr_read
& prev_gpr_write
)
5684 /* If the branch writes a register that the previous
5685 instruction sets, we can not swap. */
5686 gpr_write
= gpr_write_mask (ip
);
5687 if (gpr_write
& prev_gpr_write
)
5690 /* If the branch writes a register that the previous
5691 instruction reads, we can not swap. */
5692 prev_gpr_read
= gpr_read_mask (&history
[0]);
5693 if (gpr_write
& prev_gpr_read
)
5696 /* If one instruction sets a condition code and the
5697 other one uses a condition code, we can not swap. */
5698 pinfo
= ip
->insn_mo
->pinfo
;
5699 if ((pinfo
& INSN_READ_COND_CODE
)
5700 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
5702 if ((pinfo
& INSN_WRITE_COND_CODE
)
5703 && (prev_pinfo
& INSN_READ_COND_CODE
))
5706 /* If the previous instruction uses the PC, we can not swap. */
5707 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
5708 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
5710 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
5713 /* If the previous instruction has an incorrect size for a fixed
5714 branch delay slot in microMIPS mode, we cannot swap. */
5715 pinfo2
= ip
->insn_mo
->pinfo2
;
5716 if (mips_opts
.micromips
5717 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
5718 && insn_length (history
) != 2)
5720 if (mips_opts
.micromips
5721 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
5722 && insn_length (history
) != 4)
5725 /* On R5900 short loops need to be fixed by inserting a nop in
5726 the branch delay slots.
5727 A short loop can be terminated too early. */
5728 if (mips_opts
.arch
== CPU_R5900
5729 /* Check if instruction has a parameter, ignore "j $31". */
5730 && (address_expr
!= NULL
)
5731 /* Parameter must be 16 bit. */
5732 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
5733 /* Branch to same segment. */
5734 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
5735 /* Branch to same code fragment. */
5736 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
5737 /* Can only calculate branch offset if value is known. */
5738 && symbol_constant_p(address_expr
->X_add_symbol
)
5739 /* Check if branch is really conditional. */
5740 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5741 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
5742 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5745 /* Check if loop is shorter than 6 instructions including
5746 branch and delay slot. */
5747 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
5754 /* When the loop includes branches or jumps,
5755 it is not a short loop. */
5756 for (i
= 0; i
< (distance
/ 4); i
++)
5758 if ((history
[i
].cleared_p
)
5759 || delayed_branch_p(&history
[i
]))
5767 /* Insert nop after branch to fix short loop. */
5776 /* Decide how we should add IP to the instruction stream.
5777 ADDRESS_EXPR is an operand of the instruction to be used with
5780 static enum append_method
5781 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5782 bfd_reloc_code_real_type
*reloc_type
)
5784 unsigned long pinfo
;
5786 /* The relaxed version of a macro sequence must be inherently
5788 if (mips_relax
.sequence
== 2)
5791 /* We must not dabble with instructions in a ".set norerorder" block. */
5792 if (mips_opts
.noreorder
)
5795 /* Otherwise, it's our responsibility to fill branch delay slots. */
5796 if (delayed_branch_p (ip
))
5798 if (!branch_likely_p (ip
)
5799 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
5802 pinfo
= ip
->insn_mo
->pinfo
;
5803 if (mips_opts
.mips16
5804 && ISA_SUPPORTS_MIPS16E
5805 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
5806 return APPEND_ADD_COMPACT
;
5808 return APPEND_ADD_WITH_NOP
;
5814 /* IP is a MIPS16 instruction whose opcode we have just changed.
5815 Point IP->insn_mo to the new opcode's definition. */
5818 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
5820 const struct mips_opcode
*mo
, *end
;
5822 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
5823 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
5824 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
5832 /* For microMIPS macros, we need to generate a local number label
5833 as the target of branches. */
5834 #define MICROMIPS_LABEL_CHAR '\037'
5835 static unsigned long micromips_target_label
;
5836 static char micromips_target_name
[32];
5839 micromips_label_name (void)
5841 char *p
= micromips_target_name
;
5842 char symbol_name_temporary
[24];
5850 l
= micromips_target_label
;
5851 #ifdef LOCAL_LABEL_PREFIX
5852 *p
++ = LOCAL_LABEL_PREFIX
;
5855 *p
++ = MICROMIPS_LABEL_CHAR
;
5858 symbol_name_temporary
[i
++] = l
% 10 + '0';
5863 *p
++ = symbol_name_temporary
[--i
];
5866 return micromips_target_name
;
5870 micromips_label_expr (expressionS
*label_expr
)
5872 label_expr
->X_op
= O_symbol
;
5873 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
5874 label_expr
->X_add_number
= 0;
5878 micromips_label_inc (void)
5880 micromips_target_label
++;
5881 *micromips_target_name
= '\0';
5885 micromips_add_label (void)
5889 s
= colon (micromips_label_name ());
5890 micromips_label_inc ();
5891 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
5894 /* If assembling microMIPS code, then return the microMIPS reloc
5895 corresponding to the requested one if any. Otherwise return
5896 the reloc unchanged. */
5898 static bfd_reloc_code_real_type
5899 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
5901 static const bfd_reloc_code_real_type relocs
[][2] =
5903 /* Keep sorted incrementally by the left-hand key. */
5904 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
5905 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
5906 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
5907 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
5908 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
5909 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
5910 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
5911 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
5912 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
5913 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
5914 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
5915 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
5916 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
5917 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
5918 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
5919 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
5920 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
5921 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
5922 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
5923 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
5924 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
5925 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
5926 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
5927 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
5928 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
5929 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
5930 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
5932 bfd_reloc_code_real_type r
;
5935 if (!mips_opts
.micromips
)
5937 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
5943 return relocs
[i
][1];
5948 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
5949 Return true on success, storing the resolved value in RESULT. */
5952 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
5957 case BFD_RELOC_MIPS_HIGHEST
:
5958 case BFD_RELOC_MICROMIPS_HIGHEST
:
5959 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
5962 case BFD_RELOC_MIPS_HIGHER
:
5963 case BFD_RELOC_MICROMIPS_HIGHER
:
5964 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
5967 case BFD_RELOC_HI16_S
:
5968 case BFD_RELOC_MICROMIPS_HI16_S
:
5969 case BFD_RELOC_MIPS16_HI16_S
:
5970 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
5973 case BFD_RELOC_HI16
:
5974 case BFD_RELOC_MICROMIPS_HI16
:
5975 case BFD_RELOC_MIPS16_HI16
:
5976 *result
= (operand
>> 16) & 0xffff;
5979 case BFD_RELOC_LO16
:
5980 case BFD_RELOC_MICROMIPS_LO16
:
5981 case BFD_RELOC_MIPS16_LO16
:
5982 *result
= operand
& 0xffff;
5985 case BFD_RELOC_UNUSED
:
5994 /* Output an instruction. IP is the instruction information.
5995 ADDRESS_EXPR is an operand of the instruction to be used with
5996 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
5997 a macro expansion. */
6000 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6001 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6003 unsigned long prev_pinfo2
, pinfo
;
6004 bfd_boolean relaxed_branch
= FALSE
;
6005 enum append_method method
;
6006 bfd_boolean relax32
;
6009 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6010 fix_loongson2f (ip
);
6012 file_ase_mips16
|= mips_opts
.mips16
;
6013 file_ase_micromips
|= mips_opts
.micromips
;
6015 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6016 pinfo
= ip
->insn_mo
->pinfo
;
6018 if (mips_opts
.micromips
6020 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6021 && micromips_insn_length (ip
->insn_mo
) != 2)
6022 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6023 && micromips_insn_length (ip
->insn_mo
) != 4)))
6024 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6025 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6027 if (address_expr
== NULL
)
6029 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6030 && reloc_type
[1] == BFD_RELOC_UNUSED
6031 && reloc_type
[2] == BFD_RELOC_UNUSED
6032 && address_expr
->X_op
== O_constant
)
6034 switch (*reloc_type
)
6036 case BFD_RELOC_MIPS_JMP
:
6040 shift
= mips_opts
.micromips
? 1 : 2;
6041 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6042 as_bad (_("jump to misaligned address (0x%lx)"),
6043 (unsigned long) address_expr
->X_add_number
);
6044 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6050 case BFD_RELOC_MIPS16_JMP
:
6051 if ((address_expr
->X_add_number
& 3) != 0)
6052 as_bad (_("jump to misaligned address (0x%lx)"),
6053 (unsigned long) address_expr
->X_add_number
);
6055 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6056 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6057 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6061 case BFD_RELOC_16_PCREL_S2
:
6065 shift
= mips_opts
.micromips
? 1 : 2;
6066 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6067 as_bad (_("branch to misaligned address (0x%lx)"),
6068 (unsigned long) address_expr
->X_add_number
);
6069 if (!mips_relax_branch
)
6071 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6072 & ~((1 << (shift
+ 16)) - 1))
6073 as_bad (_("branch address range overflow (0x%lx)"),
6074 (unsigned long) address_expr
->X_add_number
);
6075 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6085 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6088 ip
->insn_opcode
|= value
& 0xffff;
6096 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6098 /* There are a lot of optimizations we could do that we don't.
6099 In particular, we do not, in general, reorder instructions.
6100 If you use gcc with optimization, it will reorder
6101 instructions and generally do much more optimization then we
6102 do here; repeating all that work in the assembler would only
6103 benefit hand written assembly code, and does not seem worth
6105 int nops
= (mips_optimize
== 0
6106 ? nops_for_insn (0, history
, NULL
)
6107 : nops_for_insn_or_target (0, history
, ip
));
6111 unsigned long old_frag_offset
;
6114 old_frag
= frag_now
;
6115 old_frag_offset
= frag_now_fix ();
6117 for (i
= 0; i
< nops
; i
++)
6118 add_fixed_insn (NOP_INSN
);
6119 insert_into_history (0, nops
, NOP_INSN
);
6123 listing_prev_line ();
6124 /* We may be at the start of a variant frag. In case we
6125 are, make sure there is enough space for the frag
6126 after the frags created by listing_prev_line. The
6127 argument to frag_grow here must be at least as large
6128 as the argument to all other calls to frag_grow in
6129 this file. We don't have to worry about being in the
6130 middle of a variant frag, because the variants insert
6131 all needed nop instructions themselves. */
6135 mips_move_text_labels ();
6137 #ifndef NO_ECOFF_DEBUGGING
6138 if (ECOFF_DEBUGGING
)
6139 ecoff_fix_loc (old_frag
, old_frag_offset
);
6143 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6147 /* Work out how many nops in prev_nop_frag are needed by IP,
6148 ignoring hazards generated by the first prev_nop_frag_since
6150 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6151 gas_assert (nops
<= prev_nop_frag_holds
);
6153 /* Enforce NOPS as a minimum. */
6154 if (nops
> prev_nop_frag_required
)
6155 prev_nop_frag_required
= nops
;
6157 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6159 /* Settle for the current number of nops. Update the history
6160 accordingly (for the benefit of any future .set reorder code). */
6161 prev_nop_frag
= NULL
;
6162 insert_into_history (prev_nop_frag_since
,
6163 prev_nop_frag_holds
, NOP_INSN
);
6167 /* Allow this instruction to replace one of the nops that was
6168 tentatively added to prev_nop_frag. */
6169 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6170 prev_nop_frag_holds
--;
6171 prev_nop_frag_since
++;
6175 method
= get_append_method (ip
, address_expr
, reloc_type
);
6176 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6178 dwarf2_emit_insn (0);
6179 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6180 so "move" the instruction address accordingly.
6182 Also, it doesn't seem appropriate for the assembler to reorder .loc
6183 entries. If this instruction is a branch that we are going to swap
6184 with the previous instruction, the two instructions should be
6185 treated as a unit, and the debug information for both instructions
6186 should refer to the start of the branch sequence. Using the
6187 current position is certainly wrong when swapping a 32-bit branch
6188 and a 16-bit delay slot, since the current position would then be
6189 in the middle of a branch. */
6190 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6192 relax32
= (mips_relax_branch
6193 /* Don't try branch relaxation within .set nomacro, or within
6194 .set noat if we use $at for PIC computations. If it turns
6195 out that the branch was out-of-range, we'll get an error. */
6196 && !mips_opts
.warn_about_macros
6197 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6198 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6199 as they have no complementing branches. */
6200 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6202 if (!HAVE_CODE_COMPRESSION
6205 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6206 && delayed_branch_p (ip
))
6208 relaxed_branch
= TRUE
;
6209 add_relaxed_insn (ip
, (relaxed_branch_length
6211 uncond_branch_p (ip
) ? -1
6212 : branch_likely_p (ip
) ? 1
6216 uncond_branch_p (ip
),
6217 branch_likely_p (ip
),
6218 pinfo
& INSN_WRITE_GPR_31
,
6220 address_expr
->X_add_symbol
,
6221 address_expr
->X_add_number
);
6222 *reloc_type
= BFD_RELOC_UNUSED
;
6224 else if (mips_opts
.micromips
6226 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6227 || *reloc_type
> BFD_RELOC_UNUSED
)
6228 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6229 /* Don't try branch relaxation when users specify
6230 16-bit/32-bit instructions. */
6231 && !forced_insn_length
)
6233 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6234 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6235 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6236 int compact
= compact_branch_p (ip
);
6237 int al
= pinfo
& INSN_WRITE_GPR_31
;
6240 gas_assert (address_expr
!= NULL
);
6241 gas_assert (!mips_relax
.sequence
);
6243 relaxed_branch
= TRUE
;
6244 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6245 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6246 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6248 address_expr
->X_add_symbol
,
6249 address_expr
->X_add_number
);
6250 *reloc_type
= BFD_RELOC_UNUSED
;
6252 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6254 /* We need to set up a variant frag. */
6255 gas_assert (address_expr
!= NULL
);
6256 add_relaxed_insn (ip
, 4, 0,
6258 (*reloc_type
- BFD_RELOC_UNUSED
,
6259 forced_insn_length
== 2, forced_insn_length
== 4,
6260 delayed_branch_p (&history
[0]),
6261 history
[0].mips16_absolute_jump_p
),
6262 make_expr_symbol (address_expr
), 0);
6264 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6266 if (!delayed_branch_p (ip
))
6267 /* Make sure there is enough room to swap this instruction with
6268 a following jump instruction. */
6270 add_fixed_insn (ip
);
6274 if (mips_opts
.mips16
6275 && mips_opts
.noreorder
6276 && delayed_branch_p (&history
[0]))
6277 as_warn (_("extended instruction in delay slot"));
6279 if (mips_relax
.sequence
)
6281 /* If we've reached the end of this frag, turn it into a variant
6282 frag and record the information for the instructions we've
6284 if (frag_room () < 4)
6285 relax_close_frag ();
6286 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6289 if (mips_relax
.sequence
!= 2)
6291 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6292 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6293 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6294 mips_macro_warning
.insns
[0]++;
6296 if (mips_relax
.sequence
!= 1)
6298 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6299 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6300 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6301 mips_macro_warning
.insns
[1]++;
6304 if (mips_opts
.mips16
)
6307 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6309 add_fixed_insn (ip
);
6312 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6314 bfd_reloc_code_real_type final_type
[3];
6315 reloc_howto_type
*howto0
;
6316 reloc_howto_type
*howto
;
6319 /* Perform any necessary conversion to microMIPS relocations
6320 and find out how many relocations there actually are. */
6321 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6322 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6324 /* In a compound relocation, it is the final (outermost)
6325 operator that determines the relocated field. */
6326 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6331 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6332 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6333 bfd_get_reloc_size (howto
),
6335 howto0
&& howto0
->pc_relative
,
6338 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6339 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6340 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6342 /* These relocations can have an addend that won't fit in
6343 4 octets for 64bit assembly. */
6345 && ! howto
->partial_inplace
6346 && (reloc_type
[0] == BFD_RELOC_16
6347 || reloc_type
[0] == BFD_RELOC_32
6348 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6349 || reloc_type
[0] == BFD_RELOC_GPREL16
6350 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6351 || reloc_type
[0] == BFD_RELOC_GPREL32
6352 || reloc_type
[0] == BFD_RELOC_64
6353 || reloc_type
[0] == BFD_RELOC_CTOR
6354 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6355 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6356 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6357 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6358 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6359 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6360 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6361 || hi16_reloc_p (reloc_type
[0])
6362 || lo16_reloc_p (reloc_type
[0])))
6363 ip
->fixp
[0]->fx_no_overflow
= 1;
6365 /* These relocations can have an addend that won't fit in 2 octets. */
6366 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6367 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6368 ip
->fixp
[0]->fx_no_overflow
= 1;
6370 if (mips_relax
.sequence
)
6372 if (mips_relax
.first_fixup
== 0)
6373 mips_relax
.first_fixup
= ip
->fixp
[0];
6375 else if (reloc_needs_lo_p (*reloc_type
))
6377 struct mips_hi_fixup
*hi_fixup
;
6379 /* Reuse the last entry if it already has a matching %lo. */
6380 hi_fixup
= mips_hi_fixup_list
;
6382 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6384 hi_fixup
= ((struct mips_hi_fixup
*)
6385 xmalloc (sizeof (struct mips_hi_fixup
)));
6386 hi_fixup
->next
= mips_hi_fixup_list
;
6387 mips_hi_fixup_list
= hi_fixup
;
6389 hi_fixup
->fixp
= ip
->fixp
[0];
6390 hi_fixup
->seg
= now_seg
;
6393 /* Add fixups for the second and third relocations, if given.
6394 Note that the ABI allows the second relocation to be
6395 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6396 moment we only use RSS_UNDEF, but we could add support
6397 for the others if it ever becomes necessary. */
6398 for (i
= 1; i
< 3; i
++)
6399 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6401 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6402 ip
->fixp
[0]->fx_size
, NULL
, 0,
6403 FALSE
, final_type
[i
]);
6405 /* Use fx_tcbit to mark compound relocs. */
6406 ip
->fixp
[0]->fx_tcbit
= 1;
6407 ip
->fixp
[i
]->fx_tcbit
= 1;
6412 /* Update the register mask information. */
6413 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6414 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6419 insert_into_history (0, 1, ip
);
6422 case APPEND_ADD_WITH_NOP
:
6424 struct mips_cl_insn
*nop
;
6426 insert_into_history (0, 1, ip
);
6427 nop
= get_delay_slot_nop (ip
);
6428 add_fixed_insn (nop
);
6429 insert_into_history (0, 1, nop
);
6430 if (mips_relax
.sequence
)
6431 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6435 case APPEND_ADD_COMPACT
:
6436 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6437 gas_assert (mips_opts
.mips16
);
6438 ip
->insn_opcode
|= 0x0080;
6439 find_altered_mips16_opcode (ip
);
6441 insert_into_history (0, 1, ip
);
6446 struct mips_cl_insn delay
= history
[0];
6447 if (mips_opts
.mips16
)
6449 know (delay
.frag
== ip
->frag
);
6450 move_insn (ip
, delay
.frag
, delay
.where
);
6451 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6453 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6455 /* Add the delay slot instruction to the end of the
6456 current frag and shrink the fixed part of the
6457 original frag. If the branch occupies the tail of
6458 the latter, move it backwards to cover the gap. */
6459 delay
.frag
->fr_fix
-= branch_disp
;
6460 if (delay
.frag
== ip
->frag
)
6461 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6462 add_fixed_insn (&delay
);
6466 move_insn (&delay
, ip
->frag
,
6467 ip
->where
- branch_disp
+ insn_length (ip
));
6468 move_insn (ip
, history
[0].frag
, history
[0].where
);
6472 insert_into_history (0, 1, &delay
);
6477 /* If we have just completed an unconditional branch, clear the history. */
6478 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
6479 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
6483 mips_no_prev_insn ();
6485 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6486 history
[i
].cleared_p
= 1;
6489 /* We need to emit a label at the end of branch-likely macros. */
6490 if (emit_branch_likely_macro
)
6492 emit_branch_likely_macro
= FALSE
;
6493 micromips_add_label ();
6496 /* We just output an insn, so the next one doesn't have a label. */
6497 mips_clear_insn_labels ();
6500 /* Forget that there was any previous instruction or label.
6501 When BRANCH is true, the branch history is also flushed. */
6504 mips_no_prev_insn (void)
6506 prev_nop_frag
= NULL
;
6507 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
6508 mips_clear_insn_labels ();
6511 /* This function must be called before we emit something other than
6512 instructions. It is like mips_no_prev_insn except that it inserts
6513 any NOPS that might be needed by previous instructions. */
6516 mips_emit_delays (void)
6518 if (! mips_opts
.noreorder
)
6520 int nops
= nops_for_insn (0, history
, NULL
);
6524 add_fixed_insn (NOP_INSN
);
6525 mips_move_text_labels ();
6528 mips_no_prev_insn ();
6531 /* Start a (possibly nested) noreorder block. */
6534 start_noreorder (void)
6536 if (mips_opts
.noreorder
== 0)
6541 /* None of the instructions before the .set noreorder can be moved. */
6542 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6543 history
[i
].fixed_p
= 1;
6545 /* Insert any nops that might be needed between the .set noreorder
6546 block and the previous instructions. We will later remove any
6547 nops that turn out not to be needed. */
6548 nops
= nops_for_insn (0, history
, NULL
);
6551 if (mips_optimize
!= 0)
6553 /* Record the frag which holds the nop instructions, so
6554 that we can remove them if we don't need them. */
6555 frag_grow (nops
* NOP_INSN_SIZE
);
6556 prev_nop_frag
= frag_now
;
6557 prev_nop_frag_holds
= nops
;
6558 prev_nop_frag_required
= 0;
6559 prev_nop_frag_since
= 0;
6562 for (; nops
> 0; --nops
)
6563 add_fixed_insn (NOP_INSN
);
6565 /* Move on to a new frag, so that it is safe to simply
6566 decrease the size of prev_nop_frag. */
6567 frag_wane (frag_now
);
6569 mips_move_text_labels ();
6571 mips_mark_labels ();
6572 mips_clear_insn_labels ();
6574 mips_opts
.noreorder
++;
6575 mips_any_noreorder
= 1;
6578 /* End a nested noreorder block. */
6581 end_noreorder (void)
6583 mips_opts
.noreorder
--;
6584 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
6586 /* Commit to inserting prev_nop_frag_required nops and go back to
6587 handling nop insertion the .set reorder way. */
6588 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
6590 insert_into_history (prev_nop_frag_since
,
6591 prev_nop_frag_required
, NOP_INSN
);
6592 prev_nop_frag
= NULL
;
6596 /* Set up global variables for the start of a new macro. */
6601 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
6602 memset (&mips_macro_warning
.first_insn_sizes
, 0,
6603 sizeof (mips_macro_warning
.first_insn_sizes
));
6604 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
6605 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
6606 && delayed_branch_p (&history
[0]));
6607 switch (history
[0].insn_mo
->pinfo2
6608 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
6610 case INSN2_BRANCH_DELAY_32BIT
:
6611 mips_macro_warning
.delay_slot_length
= 4;
6613 case INSN2_BRANCH_DELAY_16BIT
:
6614 mips_macro_warning
.delay_slot_length
= 2;
6617 mips_macro_warning
.delay_slot_length
= 0;
6620 mips_macro_warning
.first_frag
= NULL
;
6623 /* Given that a macro is longer than one instruction or of the wrong size,
6624 return the appropriate warning for it. Return null if no warning is
6625 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6626 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6627 and RELAX_NOMACRO. */
6630 macro_warning (relax_substateT subtype
)
6632 if (subtype
& RELAX_DELAY_SLOT
)
6633 return _("Macro instruction expanded into multiple instructions"
6634 " in a branch delay slot");
6635 else if (subtype
& RELAX_NOMACRO
)
6636 return _("Macro instruction expanded into multiple instructions");
6637 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
6638 | RELAX_DELAY_SLOT_SIZE_SECOND
))
6639 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
6640 ? _("Macro instruction expanded into a wrong size instruction"
6641 " in a 16-bit branch delay slot")
6642 : _("Macro instruction expanded into a wrong size instruction"
6643 " in a 32-bit branch delay slot"));
6648 /* Finish up a macro. Emit warnings as appropriate. */
6653 /* Relaxation warning flags. */
6654 relax_substateT subtype
= 0;
6656 /* Check delay slot size requirements. */
6657 if (mips_macro_warning
.delay_slot_length
== 2)
6658 subtype
|= RELAX_DELAY_SLOT_16BIT
;
6659 if (mips_macro_warning
.delay_slot_length
!= 0)
6661 if (mips_macro_warning
.delay_slot_length
6662 != mips_macro_warning
.first_insn_sizes
[0])
6663 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
6664 if (mips_macro_warning
.delay_slot_length
6665 != mips_macro_warning
.first_insn_sizes
[1])
6666 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
6669 /* Check instruction count requirements. */
6670 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
6672 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
6673 subtype
|= RELAX_SECOND_LONGER
;
6674 if (mips_opts
.warn_about_macros
)
6675 subtype
|= RELAX_NOMACRO
;
6676 if (mips_macro_warning
.delay_slot_p
)
6677 subtype
|= RELAX_DELAY_SLOT
;
6680 /* If both alternatives fail to fill a delay slot correctly,
6681 emit the warning now. */
6682 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
6683 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
6688 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
6689 | RELAX_DELAY_SLOT_SIZE_FIRST
6690 | RELAX_DELAY_SLOT_SIZE_SECOND
);
6691 msg
= macro_warning (s
);
6693 as_warn ("%s", msg
);
6697 /* If both implementations are longer than 1 instruction, then emit the
6699 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
6704 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
6705 msg
= macro_warning (s
);
6707 as_warn ("%s", msg
);
6711 /* If any flags still set, then one implementation might need a warning
6712 and the other either will need one of a different kind or none at all.
6713 Pass any remaining flags over to relaxation. */
6714 if (mips_macro_warning
.first_frag
!= NULL
)
6715 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
6718 /* Instruction operand formats used in macros that vary between
6719 standard MIPS and microMIPS code. */
6721 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
6722 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
6723 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
6724 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
6725 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
6726 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
6727 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
6728 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
6730 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
6731 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
6732 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
6733 #define LUI_FMT (lui_fmt[mips_opts.micromips])
6734 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
6735 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
6736 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
6737 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
6739 /* Read a macro's relocation codes from *ARGS and store them in *R.
6740 The first argument in *ARGS will be either the code for a single
6741 relocation or -1 followed by the three codes that make up a
6742 composite relocation. */
6745 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
6749 next
= va_arg (*args
, int);
6751 r
[0] = (bfd_reloc_code_real_type
) next
;
6754 for (i
= 0; i
< 3; i
++)
6755 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
6756 /* This function is only used for 16-bit relocation fields.
6757 To make the macro code simpler, treat an unrelocated value
6758 in the same way as BFD_RELOC_LO16. */
6759 if (r
[0] == BFD_RELOC_UNUSED
)
6760 r
[0] = BFD_RELOC_LO16
;
6764 /* Build an instruction created by a macro expansion. This is passed
6765 a pointer to the count of instructions created so far, an
6766 expression, the name of the instruction to build, an operand format
6767 string, and corresponding arguments. */
6770 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
6772 const struct mips_opcode
*mo
= NULL
;
6773 bfd_reloc_code_real_type r
[3];
6774 const struct mips_opcode
*amo
;
6775 const struct mips_operand
*operand
;
6776 struct hash_control
*hash
;
6777 struct mips_cl_insn insn
;
6781 va_start (args
, fmt
);
6783 if (mips_opts
.mips16
)
6785 mips16_macro_build (ep
, name
, fmt
, &args
);
6790 r
[0] = BFD_RELOC_UNUSED
;
6791 r
[1] = BFD_RELOC_UNUSED
;
6792 r
[2] = BFD_RELOC_UNUSED
;
6793 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
6794 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
6796 gas_assert (strcmp (name
, amo
->name
) == 0);
6800 /* Search until we get a match for NAME. It is assumed here that
6801 macros will never generate MDMX, MIPS-3D, or MT instructions.
6802 We try to match an instruction that fulfils the branch delay
6803 slot instruction length requirement (if any) of the previous
6804 instruction. While doing this we record the first instruction
6805 seen that matches all the other conditions and use it anyway
6806 if the requirement cannot be met; we will issue an appropriate
6807 warning later on. */
6808 if (strcmp (fmt
, amo
->args
) == 0
6809 && amo
->pinfo
!= INSN_MACRO
6810 && is_opcode_valid (amo
)
6811 && is_size_valid (amo
))
6813 if (is_delay_slot_valid (amo
))
6823 gas_assert (amo
->name
);
6825 while (strcmp (name
, amo
->name
) == 0);
6828 create_insn (&insn
, mo
);
6841 macro_read_relocs (&args
, r
);
6842 gas_assert (*r
== BFD_RELOC_GPREL16
6843 || *r
== BFD_RELOC_MIPS_HIGHER
6844 || *r
== BFD_RELOC_HI16_S
6845 || *r
== BFD_RELOC_LO16
6846 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
6850 macro_read_relocs (&args
, r
);
6854 macro_read_relocs (&args
, r
);
6855 gas_assert (ep
!= NULL
6856 && (ep
->X_op
== O_constant
6857 || (ep
->X_op
== O_symbol
6858 && (*r
== BFD_RELOC_MIPS_HIGHEST
6859 || *r
== BFD_RELOC_HI16_S
6860 || *r
== BFD_RELOC_HI16
6861 || *r
== BFD_RELOC_GPREL16
6862 || *r
== BFD_RELOC_MIPS_GOT_HI16
6863 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
6867 gas_assert (ep
!= NULL
);
6870 * This allows macro() to pass an immediate expression for
6871 * creating short branches without creating a symbol.
6873 * We don't allow branch relaxation for these branches, as
6874 * they should only appear in ".set nomacro" anyway.
6876 if (ep
->X_op
== O_constant
)
6878 /* For microMIPS we always use relocations for branches.
6879 So we should not resolve immediate values. */
6880 gas_assert (!mips_opts
.micromips
);
6882 if ((ep
->X_add_number
& 3) != 0)
6883 as_bad (_("branch to misaligned address (0x%lx)"),
6884 (unsigned long) ep
->X_add_number
);
6885 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
6886 as_bad (_("branch address range overflow (0x%lx)"),
6887 (unsigned long) ep
->X_add_number
);
6888 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
6892 *r
= BFD_RELOC_16_PCREL_S2
;
6896 gas_assert (ep
!= NULL
);
6897 *r
= BFD_RELOC_MIPS_JMP
;
6901 operand
= (mips_opts
.micromips
6902 ? decode_micromips_operand (fmt
)
6903 : decode_mips_operand (fmt
));
6907 uval
= va_arg (args
, int);
6908 if (operand
->type
== OP_CLO_CLZ_DEST
)
6909 uval
|= (uval
<< 5);
6910 insn_insert_operand (&insn
, operand
, uval
);
6912 if (*fmt
== '+' || *fmt
== 'm')
6918 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
6920 append_insn (&insn
, ep
, r
, TRUE
);
6924 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
6927 struct mips_opcode
*mo
;
6928 struct mips_cl_insn insn
;
6929 const struct mips_operand
*operand
;
6930 bfd_reloc_code_real_type r
[3]
6931 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
6933 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
6935 gas_assert (strcmp (name
, mo
->name
) == 0);
6937 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
6940 gas_assert (mo
->name
);
6941 gas_assert (strcmp (name
, mo
->name
) == 0);
6944 create_insn (&insn
, mo
);
6982 gas_assert (ep
!= NULL
);
6984 if (ep
->X_op
!= O_constant
)
6985 *r
= (int) BFD_RELOC_UNUSED
+ c
;
6986 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
6988 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
6990 *r
= BFD_RELOC_UNUSED
;
6996 operand
= decode_mips16_operand (c
, FALSE
);
7000 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
7005 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7007 append_insn (&insn
, ep
, r
, TRUE
);
7011 * Sign-extend 32-bit mode constants that have bit 31 set and all
7012 * higher bits unset.
7015 normalize_constant_expr (expressionS
*ex
)
7017 if (ex
->X_op
== O_constant
7018 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7019 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7024 * Sign-extend 32-bit mode address offsets that have bit 31 set and
7025 * all higher bits unset.
7028 normalize_address_expr (expressionS
*ex
)
7030 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7031 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7032 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7033 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7038 * Generate a "jalr" instruction with a relocation hint to the called
7039 * function. This occurs in NewABI PIC code.
7042 macro_build_jalr (expressionS
*ep
, int cprestore
)
7044 static const bfd_reloc_code_real_type jalr_relocs
[2]
7045 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
7046 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
7050 if (MIPS_JALR_HINT_P (ep
))
7055 if (mips_opts
.micromips
)
7057 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
7058 ? "jalr" : "jalrs");
7059 if (MIPS_JALR_HINT_P (ep
)
7061 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7062 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
7064 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
7067 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
7068 if (MIPS_JALR_HINT_P (ep
))
7069 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
7073 * Generate a "lui" instruction.
7076 macro_build_lui (expressionS
*ep
, int regnum
)
7078 gas_assert (! mips_opts
.mips16
);
7080 if (ep
->X_op
!= O_constant
)
7082 gas_assert (ep
->X_op
== O_symbol
);
7083 /* _gp_disp is a special case, used from s_cpload.
7084 __gnu_local_gp is used if mips_no_shared. */
7085 gas_assert (mips_pic
== NO_PIC
7087 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
7088 || (! mips_in_shared
7089 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
7090 "__gnu_local_gp") == 0));
7093 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
7096 /* Generate a sequence of instructions to do a load or store from a constant
7097 offset off of a base register (breg) into/from a target register (treg),
7098 using AT if necessary. */
7100 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
7101 int treg
, int breg
, int dbl
)
7103 gas_assert (ep
->X_op
== O_constant
);
7105 /* Sign-extending 32-bit constants makes their handling easier. */
7107 normalize_constant_expr (ep
);
7109 /* Right now, this routine can only handle signed 32-bit constants. */
7110 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
7111 as_warn (_("operand overflow"));
7113 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
7115 /* Signed 16-bit offset will fit in the op. Easy! */
7116 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7120 /* 32-bit offset, need multiple instructions and AT, like:
7121 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7122 addu $tempreg,$tempreg,$breg
7123 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7124 to handle the complete offset. */
7125 macro_build_lui (ep
, AT
);
7126 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7127 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7130 as_bad (_("Macro used $at after \".set noat\""));
7135 * Generates code to set the $at register to true (one)
7136 * if reg is less than the immediate expression.
7139 set_at (int reg
, int unsignedp
)
7141 if (imm_expr
.X_op
== O_constant
7142 && imm_expr
.X_add_number
>= -0x8000
7143 && imm_expr
.X_add_number
< 0x8000)
7144 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
7145 AT
, reg
, BFD_RELOC_LO16
);
7148 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7149 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
7153 /* Count the leading zeroes by performing a binary chop. This is a
7154 bulky bit of source, but performance is a LOT better for the
7155 majority of values than a simple loop to count the bits:
7156 for (lcnt = 0; (lcnt < 32); lcnt++)
7157 if ((v) & (1 << (31 - lcnt)))
7159 However it is not code size friendly, and the gain will drop a bit
7160 on certain cached systems.
7162 #define COUNT_TOP_ZEROES(v) \
7163 (((v) & ~0xffff) == 0 \
7164 ? ((v) & ~0xff) == 0 \
7165 ? ((v) & ~0xf) == 0 \
7166 ? ((v) & ~0x3) == 0 \
7167 ? ((v) & ~0x1) == 0 \
7172 : ((v) & ~0x7) == 0 \
7175 : ((v) & ~0x3f) == 0 \
7176 ? ((v) & ~0x1f) == 0 \
7179 : ((v) & ~0x7f) == 0 \
7182 : ((v) & ~0xfff) == 0 \
7183 ? ((v) & ~0x3ff) == 0 \
7184 ? ((v) & ~0x1ff) == 0 \
7187 : ((v) & ~0x7ff) == 0 \
7190 : ((v) & ~0x3fff) == 0 \
7191 ? ((v) & ~0x1fff) == 0 \
7194 : ((v) & ~0x7fff) == 0 \
7197 : ((v) & ~0xffffff) == 0 \
7198 ? ((v) & ~0xfffff) == 0 \
7199 ? ((v) & ~0x3ffff) == 0 \
7200 ? ((v) & ~0x1ffff) == 0 \
7203 : ((v) & ~0x7ffff) == 0 \
7206 : ((v) & ~0x3fffff) == 0 \
7207 ? ((v) & ~0x1fffff) == 0 \
7210 : ((v) & ~0x7fffff) == 0 \
7213 : ((v) & ~0xfffffff) == 0 \
7214 ? ((v) & ~0x3ffffff) == 0 \
7215 ? ((v) & ~0x1ffffff) == 0 \
7218 : ((v) & ~0x7ffffff) == 0 \
7221 : ((v) & ~0x3fffffff) == 0 \
7222 ? ((v) & ~0x1fffffff) == 0 \
7225 : ((v) & ~0x7fffffff) == 0 \
7230 * This routine generates the least number of instructions necessary to load
7231 * an absolute expression value into a register.
7234 load_register (int reg
, expressionS
*ep
, int dbl
)
7237 expressionS hi32
, lo32
;
7239 if (ep
->X_op
!= O_big
)
7241 gas_assert (ep
->X_op
== O_constant
);
7243 /* Sign-extending 32-bit constants makes their handling easier. */
7245 normalize_constant_expr (ep
);
7247 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
7249 /* We can handle 16 bit signed values with an addiu to
7250 $zero. No need to ever use daddiu here, since $zero and
7251 the result are always correct in 32 bit mode. */
7252 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7255 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
7257 /* We can handle 16 bit unsigned values with an ori to
7259 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
7262 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
7264 /* 32 bit values require an lui. */
7265 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7266 if ((ep
->X_add_number
& 0xffff) != 0)
7267 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
7272 /* The value is larger than 32 bits. */
7274 if (!dbl
|| HAVE_32BIT_GPRS
)
7278 sprintf_vma (value
, ep
->X_add_number
);
7279 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7280 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7284 if (ep
->X_op
!= O_big
)
7287 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
7288 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
7289 hi32
.X_add_number
&= 0xffffffff;
7291 lo32
.X_add_number
&= 0xffffffff;
7295 gas_assert (ep
->X_add_number
> 2);
7296 if (ep
->X_add_number
== 3)
7297 generic_bignum
[3] = 0;
7298 else if (ep
->X_add_number
> 4)
7299 as_bad (_("Number larger than 64 bits"));
7300 lo32
.X_op
= O_constant
;
7301 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
7302 hi32
.X_op
= O_constant
;
7303 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
7306 if (hi32
.X_add_number
== 0)
7311 unsigned long hi
, lo
;
7313 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
7315 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
7317 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7320 if (lo32
.X_add_number
& 0x80000000)
7322 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7323 if (lo32
.X_add_number
& 0xffff)
7324 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
7329 /* Check for 16bit shifted constant. We know that hi32 is
7330 non-zero, so start the mask on the first bit of the hi32
7335 unsigned long himask
, lomask
;
7339 himask
= 0xffff >> (32 - shift
);
7340 lomask
= (0xffff << shift
) & 0xffffffff;
7344 himask
= 0xffff << (shift
- 32);
7347 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
7348 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
7352 tmp
.X_op
= O_constant
;
7354 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
7355 | (lo32
.X_add_number
>> shift
));
7357 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
7358 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
7359 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
7360 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
7365 while (shift
<= (64 - 16));
7367 /* Find the bit number of the lowest one bit, and store the
7368 shifted value in hi/lo. */
7369 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
7370 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
7374 while ((lo
& 1) == 0)
7379 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
7385 while ((hi
& 1) == 0)
7394 /* Optimize if the shifted value is a (power of 2) - 1. */
7395 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
7396 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
7398 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
7403 /* This instruction will set the register to be all
7405 tmp
.X_op
= O_constant
;
7406 tmp
.X_add_number
= (offsetT
) -1;
7407 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7411 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
7412 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
7414 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
7415 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
7420 /* Sign extend hi32 before calling load_register, because we can
7421 generally get better code when we load a sign extended value. */
7422 if ((hi32
.X_add_number
& 0x80000000) != 0)
7423 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
7424 load_register (reg
, &hi32
, 0);
7427 if ((lo32
.X_add_number
& 0xffff0000) == 0)
7431 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
7439 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
7441 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7442 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
7448 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
7452 mid16
.X_add_number
>>= 16;
7453 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
7454 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7457 if ((lo32
.X_add_number
& 0xffff) != 0)
7458 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
7462 load_delay_nop (void)
7464 if (!gpr_interlocks
)
7465 macro_build (NULL
, "nop", "");
7468 /* Load an address into a register. */
7471 load_address (int reg
, expressionS
*ep
, int *used_at
)
7473 if (ep
->X_op
!= O_constant
7474 && ep
->X_op
!= O_symbol
)
7476 as_bad (_("expression too complex"));
7477 ep
->X_op
= O_constant
;
7480 if (ep
->X_op
== O_constant
)
7482 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
7486 if (mips_pic
== NO_PIC
)
7488 /* If this is a reference to a GP relative symbol, we want
7489 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
7491 lui $reg,<sym> (BFD_RELOC_HI16_S)
7492 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7493 If we have an addend, we always use the latter form.
7495 With 64bit address space and a usable $at we want
7496 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7497 lui $at,<sym> (BFD_RELOC_HI16_S)
7498 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7499 daddiu $at,<sym> (BFD_RELOC_LO16)
7503 If $at is already in use, we use a path which is suboptimal
7504 on superscalar processors.
7505 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7506 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7508 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7510 daddiu $reg,<sym> (BFD_RELOC_LO16)
7512 For GP relative symbols in 64bit address space we can use
7513 the same sequence as in 32bit address space. */
7514 if (HAVE_64BIT_SYMBOLS
)
7516 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7517 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7519 relax_start (ep
->X_add_symbol
);
7520 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7521 mips_gp_register
, BFD_RELOC_GPREL16
);
7525 if (*used_at
== 0 && mips_opts
.at
)
7527 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7528 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
7529 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7530 BFD_RELOC_MIPS_HIGHER
);
7531 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
7532 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
7533 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
7538 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7539 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7540 BFD_RELOC_MIPS_HIGHER
);
7541 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7542 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
7543 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7544 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
7547 if (mips_relax
.sequence
)
7552 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7553 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7555 relax_start (ep
->X_add_symbol
);
7556 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7557 mips_gp_register
, BFD_RELOC_GPREL16
);
7560 macro_build_lui (ep
, reg
);
7561 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
7562 reg
, reg
, BFD_RELOC_LO16
);
7563 if (mips_relax
.sequence
)
7567 else if (!mips_big_got
)
7571 /* If this is a reference to an external symbol, we want
7572 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7574 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7576 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7577 If there is a constant, it must be added in after.
7579 If we have NewABI, we want
7580 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7581 unless we're referencing a global symbol with a non-zero
7582 offset, in which case cst must be added separately. */
7585 if (ep
->X_add_number
)
7587 ex
.X_add_number
= ep
->X_add_number
;
7588 ep
->X_add_number
= 0;
7589 relax_start (ep
->X_add_symbol
);
7590 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7591 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7592 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7593 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7594 ex
.X_op
= O_constant
;
7595 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7596 reg
, reg
, BFD_RELOC_LO16
);
7597 ep
->X_add_number
= ex
.X_add_number
;
7600 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7601 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7602 if (mips_relax
.sequence
)
7607 ex
.X_add_number
= ep
->X_add_number
;
7608 ep
->X_add_number
= 0;
7609 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7610 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7612 relax_start (ep
->X_add_symbol
);
7614 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7618 if (ex
.X_add_number
!= 0)
7620 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7621 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7622 ex
.X_op
= O_constant
;
7623 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7624 reg
, reg
, BFD_RELOC_LO16
);
7628 else if (mips_big_got
)
7632 /* This is the large GOT case. If this is a reference to an
7633 external symbol, we want
7634 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7636 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
7638 Otherwise, for a reference to a local symbol in old ABI, we want
7639 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7641 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7642 If there is a constant, it must be added in after.
7644 In the NewABI, for local symbols, with or without offsets, we want:
7645 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7646 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7650 ex
.X_add_number
= ep
->X_add_number
;
7651 ep
->X_add_number
= 0;
7652 relax_start (ep
->X_add_symbol
);
7653 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7654 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7655 reg
, reg
, mips_gp_register
);
7656 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7657 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7658 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7659 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7660 else if (ex
.X_add_number
)
7662 ex
.X_op
= O_constant
;
7663 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7667 ep
->X_add_number
= ex
.X_add_number
;
7669 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7670 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7671 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7672 BFD_RELOC_MIPS_GOT_OFST
);
7677 ex
.X_add_number
= ep
->X_add_number
;
7678 ep
->X_add_number
= 0;
7679 relax_start (ep
->X_add_symbol
);
7680 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7681 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7682 reg
, reg
, mips_gp_register
);
7683 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7684 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7686 if (reg_needs_delay (mips_gp_register
))
7688 /* We need a nop before loading from $gp. This special
7689 check is required because the lui which starts the main
7690 instruction stream does not refer to $gp, and so will not
7691 insert the nop which may be required. */
7692 macro_build (NULL
, "nop", "");
7694 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7695 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7697 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7701 if (ex
.X_add_number
!= 0)
7703 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7704 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7705 ex
.X_op
= O_constant
;
7706 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7714 if (!mips_opts
.at
&& *used_at
== 1)
7715 as_bad (_("Macro used $at after \".set noat\""));
7718 /* Move the contents of register SOURCE into register DEST. */
7721 move_register (int dest
, int source
)
7723 /* Prefer to use a 16-bit microMIPS instruction unless the previous
7724 instruction specifically requires a 32-bit one. */
7725 if (mips_opts
.micromips
7726 && !mips_opts
.insn32
7727 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7728 macro_build (NULL
, "move", "mp,mj", dest
, source
);
7730 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
7734 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
7735 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
7736 The two alternatives are:
7738 Global symbol Local sybmol
7739 ------------- ------------
7740 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
7742 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
7744 load_got_offset emits the first instruction and add_got_offset
7745 emits the second for a 16-bit offset or add_got_offset_hilo emits
7746 a sequence to add a 32-bit offset using a scratch register. */
7749 load_got_offset (int dest
, expressionS
*local
)
7754 global
.X_add_number
= 0;
7756 relax_start (local
->X_add_symbol
);
7757 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
7758 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7760 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
7761 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7766 add_got_offset (int dest
, expressionS
*local
)
7770 global
.X_op
= O_constant
;
7771 global
.X_op_symbol
= NULL
;
7772 global
.X_add_symbol
= NULL
;
7773 global
.X_add_number
= local
->X_add_number
;
7775 relax_start (local
->X_add_symbol
);
7776 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
7777 dest
, dest
, BFD_RELOC_LO16
);
7779 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
7784 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
7787 int hold_mips_optimize
;
7789 global
.X_op
= O_constant
;
7790 global
.X_op_symbol
= NULL
;
7791 global
.X_add_symbol
= NULL
;
7792 global
.X_add_number
= local
->X_add_number
;
7794 relax_start (local
->X_add_symbol
);
7795 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
7797 /* Set mips_optimize around the lui instruction to avoid
7798 inserting an unnecessary nop after the lw. */
7799 hold_mips_optimize
= mips_optimize
;
7801 macro_build_lui (&global
, tmp
);
7802 mips_optimize
= hold_mips_optimize
;
7803 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
7806 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
7809 /* Emit a sequence of instructions to emulate a branch likely operation.
7810 BR is an ordinary branch corresponding to one to be emulated. BRNEG
7811 is its complementing branch with the original condition negated.
7812 CALL is set if the original branch specified the link operation.
7813 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
7815 Code like this is produced in the noreorder mode:
7820 delay slot (executed only if branch taken)
7828 delay slot (executed only if branch taken)
7831 In the reorder mode the delay slot would be filled with a nop anyway,
7832 so code produced is simply:
7837 This function is used when producing code for the microMIPS ASE that
7838 does not implement branch likely instructions in hardware. */
7841 macro_build_branch_likely (const char *br
, const char *brneg
,
7842 int call
, expressionS
*ep
, const char *fmt
,
7843 unsigned int sreg
, unsigned int treg
)
7845 int noreorder
= mips_opts
.noreorder
;
7848 gas_assert (mips_opts
.micromips
);
7852 micromips_label_expr (&expr1
);
7853 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
7854 macro_build (NULL
, "nop", "");
7855 macro_build (ep
, call
? "bal" : "b", "p");
7857 /* Set to true so that append_insn adds a label. */
7858 emit_branch_likely_macro
= TRUE
;
7862 macro_build (ep
, br
, fmt
, sreg
, treg
);
7863 macro_build (NULL
, "nop", "");
7868 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
7869 the condition code tested. EP specifies the branch target. */
7872 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
7899 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
7902 /* Emit a two-argument branch macro specified by TYPE, using SREG as
7903 the register tested. EP specifies the branch target. */
7906 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
7908 const char *brneg
= NULL
;
7918 br
= mips_opts
.micromips
? "bgez" : "bgezl";
7922 gas_assert (mips_opts
.micromips
);
7923 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
7931 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
7938 br
= mips_opts
.micromips
? "blez" : "blezl";
7945 br
= mips_opts
.micromips
? "bltz" : "bltzl";
7949 gas_assert (mips_opts
.micromips
);
7950 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
7957 if (mips_opts
.micromips
&& brneg
)
7958 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
7960 macro_build (ep
, br
, "s,p", sreg
);
7963 /* Emit a three-argument branch macro specified by TYPE, using SREG and
7964 TREG as the registers tested. EP specifies the branch target. */
7967 macro_build_branch_rsrt (int type
, expressionS
*ep
,
7968 unsigned int sreg
, unsigned int treg
)
7970 const char *brneg
= NULL
;
7982 br
= mips_opts
.micromips
? "beq" : "beql";
7991 br
= mips_opts
.micromips
? "bne" : "bnel";
7997 if (mips_opts
.micromips
&& brneg
)
7998 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
8000 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
8003 /* Return the high part that should be loaded in order to make the low
8004 part of VALUE accessible using an offset of OFFBITS bits. */
8007 offset_high_part (offsetT value
, unsigned int offbits
)
8014 bias
= 1 << (offbits
- 1);
8015 low_mask
= bias
* 2 - 1;
8016 return (value
+ bias
) & ~low_mask
;
8019 /* Return true if the value stored in offset_expr and offset_reloc
8020 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8021 amount that the caller wants to add without inducing overflow
8022 and ALIGN is the known alignment of the value in bytes. */
8025 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
8029 /* Accept any relocation operator if overflow isn't a concern. */
8030 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8033 /* These relocations are guaranteed not to overflow in correct links. */
8034 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
8035 || gprel16_reloc_p (*offset_reloc
))
8038 if (offset_expr
.X_op
== O_constant
8039 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
8040 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
8047 * This routine implements the seemingly endless macro or synthesized
8048 * instructions and addressing modes in the mips assembly language. Many
8049 * of these macros are simple and are similar to each other. These could
8050 * probably be handled by some kind of table or grammar approach instead of
8051 * this verbose method. Others are not simple macros but are more like
8052 * optimizing code generation.
8053 * One interesting optimization is when several store macros appear
8054 * consecutively that would load AT with the upper half of the same address.
8055 * The ensuing load upper instructions are ommited. This implies some kind
8056 * of global optimization. We currently only optimize within a single macro.
8057 * For many of the load and store macros if the address is specified as a
8058 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8059 * first load register 'at' with zero and use it as the base register. The
8060 * mips assembler simply uses register $zero. Just one tiny optimization
8064 macro (struct mips_cl_insn
*ip
, char *str
)
8066 unsigned int treg
, sreg
, dreg
, breg
;
8067 unsigned int tempreg
;
8070 expressionS label_expr
;
8085 bfd_boolean large_offset
;
8087 int hold_mips_optimize
;
8090 gas_assert (! mips_opts
.mips16
);
8092 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
8093 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
8094 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
8095 mask
= ip
->insn_mo
->mask
;
8097 label_expr
.X_op
= O_constant
;
8098 label_expr
.X_op_symbol
= NULL
;
8099 label_expr
.X_add_symbol
= NULL
;
8100 label_expr
.X_add_number
= 0;
8102 expr1
.X_op
= O_constant
;
8103 expr1
.X_op_symbol
= NULL
;
8104 expr1
.X_add_symbol
= NULL
;
8105 expr1
.X_add_number
= 1;
8121 if (mips_opts
.micromips
)
8122 micromips_label_expr (&label_expr
);
8124 label_expr
.X_add_number
= 8;
8125 macro_build (&label_expr
, "bgez", "s,p", sreg
);
8127 macro_build (NULL
, "nop", "");
8129 move_register (dreg
, sreg
);
8130 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
8131 if (mips_opts
.micromips
)
8132 micromips_add_label ();
8149 if (!mips_opts
.micromips
)
8151 if (imm_expr
.X_op
== O_constant
8152 && imm_expr
.X_add_number
>= -0x200
8153 && imm_expr
.X_add_number
< 0x200)
8155 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
8164 if (imm_expr
.X_op
== O_constant
8165 && imm_expr
.X_add_number
>= -0x8000
8166 && imm_expr
.X_add_number
< 0x8000)
8168 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
8173 load_register (AT
, &imm_expr
, dbl
);
8174 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
8193 if (imm_expr
.X_op
== O_constant
8194 && imm_expr
.X_add_number
>= 0
8195 && imm_expr
.X_add_number
< 0x10000)
8197 if (mask
!= M_NOR_I
)
8198 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
8201 macro_build (&imm_expr
, "ori", "t,r,i",
8202 treg
, sreg
, BFD_RELOC_LO16
);
8203 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
8209 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8210 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
8214 switch (imm_expr
.X_add_number
)
8217 macro_build (NULL
, "nop", "");
8220 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
8224 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
8225 (int) imm_expr
.X_add_number
);
8228 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
8229 (unsigned long) imm_expr
.X_add_number
);
8238 gas_assert (mips_opts
.micromips
);
8239 macro_build_branch_ccl (mask
, &offset_expr
,
8240 EXTRACT_OPERAND (1, BCC
, *ip
));
8247 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8253 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
8258 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
8265 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
8267 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
8271 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
8272 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8273 &offset_expr
, AT
, ZERO
);
8283 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
8289 /* Check for > max integer. */
8290 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
8293 /* Result is always false. */
8295 macro_build (NULL
, "nop", "");
8297 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
8300 if (imm_expr
.X_op
!= O_constant
)
8301 as_bad (_("Unsupported large constant"));
8302 ++imm_expr
.X_add_number
;
8306 if (mask
== M_BGEL_I
)
8308 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8310 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
8311 &offset_expr
, sreg
);
8314 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8316 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
8317 &offset_expr
, sreg
);
8320 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
8323 /* result is always true */
8324 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
8325 macro_build (&offset_expr
, "b", "p");
8330 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8331 &offset_expr
, AT
, ZERO
);
8340 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8341 &offset_expr
, ZERO
, treg
);
8345 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
8346 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8347 &offset_expr
, AT
, ZERO
);
8356 && imm_expr
.X_op
== O_constant
8357 && imm_expr
.X_add_number
== -1))
8359 if (imm_expr
.X_op
!= O_constant
)
8360 as_bad (_("Unsupported large constant"));
8361 ++imm_expr
.X_add_number
;
8365 if (mask
== M_BGEUL_I
)
8367 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8369 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8370 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8371 &offset_expr
, sreg
, ZERO
);
8376 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8377 &offset_expr
, AT
, ZERO
);
8385 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
8387 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
8391 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
8392 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8393 &offset_expr
, AT
, ZERO
);
8401 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8402 &offset_expr
, sreg
, ZERO
);
8408 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
8409 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8410 &offset_expr
, AT
, ZERO
);
8418 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
8420 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
8424 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
8425 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8426 &offset_expr
, AT
, ZERO
);
8433 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
8435 if (imm_expr
.X_op
!= O_constant
)
8436 as_bad (_("Unsupported large constant"));
8437 ++imm_expr
.X_add_number
;
8441 if (mask
== M_BLTL_I
)
8443 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8444 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
8445 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8446 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
8451 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8452 &offset_expr
, AT
, ZERO
);
8460 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8461 &offset_expr
, sreg
, ZERO
);
8467 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
8468 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8469 &offset_expr
, AT
, ZERO
);
8478 && imm_expr
.X_op
== O_constant
8479 && imm_expr
.X_add_number
== -1))
8481 if (imm_expr
.X_op
!= O_constant
)
8482 as_bad (_("Unsupported large constant"));
8483 ++imm_expr
.X_add_number
;
8487 if (mask
== M_BLTUL_I
)
8489 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8491 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8492 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8493 &offset_expr
, sreg
, ZERO
);
8498 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8499 &offset_expr
, AT
, ZERO
);
8507 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
8509 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
8513 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
8514 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8515 &offset_expr
, AT
, ZERO
);
8525 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8526 &offset_expr
, ZERO
, treg
);
8530 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
8531 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8532 &offset_expr
, AT
, ZERO
);
8538 /* Use unsigned arithmetic. */
8542 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8544 as_bad (_("Unsupported large constant"));
8549 pos
= imm_expr
.X_add_number
;
8550 size
= imm2_expr
.X_add_number
;
8555 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
8558 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8560 report_bad_field (pos
, size
);
8564 if (size
<= 32 && pos
< 32)
8569 else if (size
<= 32)
8579 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
8586 /* Use unsigned arithmetic. */
8590 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8592 as_bad (_("Unsupported large constant"));
8597 pos
= imm_expr
.X_add_number
;
8598 size
= imm2_expr
.X_add_number
;
8603 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
8606 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8608 report_bad_field (pos
, size
);
8612 if (pos
< 32 && (pos
+ size
- 1) < 32)
8627 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
8628 (int) (pos
+ size
- 1));
8644 as_warn (_("Divide by zero."));
8646 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
8648 macro_build (NULL
, "break", BRK_FMT
, 7);
8655 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
8656 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
8660 if (mips_opts
.micromips
)
8661 micromips_label_expr (&label_expr
);
8663 label_expr
.X_add_number
= 8;
8664 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
8665 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
8666 macro_build (NULL
, "break", BRK_FMT
, 7);
8667 if (mips_opts
.micromips
)
8668 micromips_add_label ();
8670 expr1
.X_add_number
= -1;
8672 load_register (AT
, &expr1
, dbl
);
8673 if (mips_opts
.micromips
)
8674 micromips_label_expr (&label_expr
);
8676 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
8677 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
8680 expr1
.X_add_number
= 1;
8681 load_register (AT
, &expr1
, dbl
);
8682 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
8686 expr1
.X_add_number
= 0x80000000;
8687 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
8691 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
8692 /* We want to close the noreorder block as soon as possible, so
8693 that later insns are available for delay slot filling. */
8698 if (mips_opts
.micromips
)
8699 micromips_label_expr (&label_expr
);
8701 label_expr
.X_add_number
= 8;
8702 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
8703 macro_build (NULL
, "nop", "");
8705 /* We want to close the noreorder block as soon as possible, so
8706 that later insns are available for delay slot filling. */
8709 macro_build (NULL
, "break", BRK_FMT
, 6);
8711 if (mips_opts
.micromips
)
8712 micromips_add_label ();
8713 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
8752 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8754 as_warn (_("Divide by zero."));
8756 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
8758 macro_build (NULL
, "break", BRK_FMT
, 7);
8761 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8763 if (strcmp (s2
, "mflo") == 0)
8764 move_register (dreg
, sreg
);
8766 move_register (dreg
, ZERO
);
8769 if (imm_expr
.X_op
== O_constant
8770 && imm_expr
.X_add_number
== -1
8771 && s
[strlen (s
) - 1] != 'u')
8773 if (strcmp (s2
, "mflo") == 0)
8775 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
8778 move_register (dreg
, ZERO
);
8783 load_register (AT
, &imm_expr
, dbl
);
8784 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
8785 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
8807 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
8808 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
8809 /* We want to close the noreorder block as soon as possible, so
8810 that later insns are available for delay slot filling. */
8815 if (mips_opts
.micromips
)
8816 micromips_label_expr (&label_expr
);
8818 label_expr
.X_add_number
= 8;
8819 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
8820 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
8822 /* We want to close the noreorder block as soon as possible, so
8823 that later insns are available for delay slot filling. */
8825 macro_build (NULL
, "break", BRK_FMT
, 7);
8826 if (mips_opts
.micromips
)
8827 micromips_add_label ();
8829 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
8841 /* Load the address of a symbol into a register. If breg is not
8842 zero, we then add a base register to it. */
8844 if (dbl
&& HAVE_32BIT_GPRS
)
8845 as_warn (_("dla used to load 32-bit register"));
8847 if (!dbl
&& HAVE_64BIT_OBJECTS
)
8848 as_warn (_("la used to load 64-bit address"));
8850 if (small_offset_p (0, align
, 16))
8852 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", treg
, breg
,
8853 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8857 if (mips_opts
.at
&& (treg
== breg
))
8867 if (offset_expr
.X_op
!= O_symbol
8868 && offset_expr
.X_op
!= O_constant
)
8870 as_bad (_("Expression too complex"));
8871 offset_expr
.X_op
= O_constant
;
8874 if (offset_expr
.X_op
== O_constant
)
8875 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
8876 else if (mips_pic
== NO_PIC
)
8878 /* If this is a reference to a GP relative symbol, we want
8879 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
8881 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8882 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8883 If we have a constant, we need two instructions anyhow,
8884 so we may as well always use the latter form.
8886 With 64bit address space and a usable $at we want
8887 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8888 lui $at,<sym> (BFD_RELOC_HI16_S)
8889 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8890 daddiu $at,<sym> (BFD_RELOC_LO16)
8892 daddu $tempreg,$tempreg,$at
8894 If $at is already in use, we use a path which is suboptimal
8895 on superscalar processors.
8896 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8897 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8899 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8901 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
8903 For GP relative symbols in 64bit address space we can use
8904 the same sequence as in 32bit address space. */
8905 if (HAVE_64BIT_SYMBOLS
)
8907 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8908 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8910 relax_start (offset_expr
.X_add_symbol
);
8911 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8912 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
8916 if (used_at
== 0 && mips_opts
.at
)
8918 macro_build (&offset_expr
, "lui", LUI_FMT
,
8919 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
8920 macro_build (&offset_expr
, "lui", LUI_FMT
,
8921 AT
, BFD_RELOC_HI16_S
);
8922 macro_build (&offset_expr
, "daddiu", "t,r,j",
8923 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
8924 macro_build (&offset_expr
, "daddiu", "t,r,j",
8925 AT
, AT
, BFD_RELOC_LO16
);
8926 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8927 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8932 macro_build (&offset_expr
, "lui", LUI_FMT
,
8933 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
8934 macro_build (&offset_expr
, "daddiu", "t,r,j",
8935 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
8936 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8937 macro_build (&offset_expr
, "daddiu", "t,r,j",
8938 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
8939 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8940 macro_build (&offset_expr
, "daddiu", "t,r,j",
8941 tempreg
, tempreg
, BFD_RELOC_LO16
);
8944 if (mips_relax
.sequence
)
8949 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8950 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8952 relax_start (offset_expr
.X_add_symbol
);
8953 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8954 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
8957 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8958 as_bad (_("Offset too large"));
8959 macro_build_lui (&offset_expr
, tempreg
);
8960 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8961 tempreg
, tempreg
, BFD_RELOC_LO16
);
8962 if (mips_relax
.sequence
)
8966 else if (!mips_big_got
&& !HAVE_NEWABI
)
8968 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8970 /* If this is a reference to an external symbol, and there
8971 is no constant, we want
8972 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8973 or for lca or if tempreg is PIC_CALL_REG
8974 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8975 For a local symbol, we want
8976 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8978 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8980 If we have a small constant, and this is a reference to
8981 an external symbol, we want
8982 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8984 addiu $tempreg,$tempreg,<constant>
8985 For a local symbol, we want the same instruction
8986 sequence, but we output a BFD_RELOC_LO16 reloc on the
8989 If we have a large constant, and this is a reference to
8990 an external symbol, we want
8991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8992 lui $at,<hiconstant>
8993 addiu $at,$at,<loconstant>
8994 addu $tempreg,$tempreg,$at
8995 For a local symbol, we want the same instruction
8996 sequence, but we output a BFD_RELOC_LO16 reloc on the
9000 if (offset_expr
.X_add_number
== 0)
9002 if (mips_pic
== SVR4_PIC
9004 && (call
|| tempreg
== PIC_CALL_REG
))
9005 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9007 relax_start (offset_expr
.X_add_symbol
);
9008 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9009 lw_reloc_type
, mips_gp_register
);
9012 /* We're going to put in an addu instruction using
9013 tempreg, so we may as well insert the nop right
9018 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9019 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9021 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9022 tempreg
, tempreg
, BFD_RELOC_LO16
);
9024 /* FIXME: If breg == 0, and the next instruction uses
9025 $tempreg, then if this variant case is used an extra
9026 nop will be generated. */
9028 else if (offset_expr
.X_add_number
>= -0x8000
9029 && offset_expr
.X_add_number
< 0x8000)
9031 load_got_offset (tempreg
, &offset_expr
);
9033 add_got_offset (tempreg
, &offset_expr
);
9037 expr1
.X_add_number
= offset_expr
.X_add_number
;
9038 offset_expr
.X_add_number
=
9039 SEXT_16BIT (offset_expr
.X_add_number
);
9040 load_got_offset (tempreg
, &offset_expr
);
9041 offset_expr
.X_add_number
= expr1
.X_add_number
;
9042 /* If we are going to add in a base register, and the
9043 target register and the base register are the same,
9044 then we are using AT as a temporary register. Since
9045 we want to load the constant into AT, we add our
9046 current AT (from the global offset table) and the
9047 register into the register now, and pretend we were
9048 not using a base register. */
9052 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9057 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
9061 else if (!mips_big_got
&& HAVE_NEWABI
)
9063 int add_breg_early
= 0;
9065 /* If this is a reference to an external, and there is no
9066 constant, or local symbol (*), with or without a
9068 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9069 or for lca or if tempreg is PIC_CALL_REG
9070 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9072 If we have a small constant, and this is a reference to
9073 an external symbol, we want
9074 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9075 addiu $tempreg,$tempreg,<constant>
9077 If we have a large constant, and this is a reference to
9078 an external symbol, we want
9079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9080 lui $at,<hiconstant>
9081 addiu $at,$at,<loconstant>
9082 addu $tempreg,$tempreg,$at
9084 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9085 local symbols, even though it introduces an additional
9088 if (offset_expr
.X_add_number
)
9090 expr1
.X_add_number
= offset_expr
.X_add_number
;
9091 offset_expr
.X_add_number
= 0;
9093 relax_start (offset_expr
.X_add_symbol
);
9094 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9095 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9097 if (expr1
.X_add_number
>= -0x8000
9098 && expr1
.X_add_number
< 0x8000)
9100 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9101 tempreg
, tempreg
, BFD_RELOC_LO16
);
9103 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
9105 /* If we are going to add in a base register, and the
9106 target register and the base register are the same,
9107 then we are using AT as a temporary register. Since
9108 we want to load the constant into AT, we add our
9109 current AT (from the global offset table) and the
9110 register into the register now, and pretend we were
9111 not using a base register. */
9116 gas_assert (tempreg
== AT
);
9117 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9123 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9124 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9130 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9133 offset_expr
.X_add_number
= expr1
.X_add_number
;
9135 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9136 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9139 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9140 treg
, tempreg
, breg
);
9146 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
9148 relax_start (offset_expr
.X_add_symbol
);
9149 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9150 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
9152 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9153 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9158 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9159 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9162 else if (mips_big_got
&& !HAVE_NEWABI
)
9165 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
9166 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
9167 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9169 /* This is the large GOT case. If this is a reference to an
9170 external symbol, and there is no constant, we want
9171 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9172 addu $tempreg,$tempreg,$gp
9173 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9174 or for lca or if tempreg is PIC_CALL_REG
9175 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9176 addu $tempreg,$tempreg,$gp
9177 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9178 For a local symbol, we want
9179 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9181 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9183 If we have a small constant, and this is a reference to
9184 an external symbol, we want
9185 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9186 addu $tempreg,$tempreg,$gp
9187 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9189 addiu $tempreg,$tempreg,<constant>
9190 For a local symbol, we want
9191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9193 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
9195 If we have a large constant, and this is a reference to
9196 an external symbol, we want
9197 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9198 addu $tempreg,$tempreg,$gp
9199 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9200 lui $at,<hiconstant>
9201 addiu $at,$at,<loconstant>
9202 addu $tempreg,$tempreg,$at
9203 For a local symbol, we want
9204 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9205 lui $at,<hiconstant>
9206 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
9207 addu $tempreg,$tempreg,$at
9210 expr1
.X_add_number
= offset_expr
.X_add_number
;
9211 offset_expr
.X_add_number
= 0;
9212 relax_start (offset_expr
.X_add_symbol
);
9213 gpdelay
= reg_needs_delay (mips_gp_register
);
9214 if (expr1
.X_add_number
== 0 && breg
== 0
9215 && (call
|| tempreg
== PIC_CALL_REG
))
9217 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
9218 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
9220 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
9221 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9222 tempreg
, tempreg
, mips_gp_register
);
9223 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9224 tempreg
, lw_reloc_type
, tempreg
);
9225 if (expr1
.X_add_number
== 0)
9229 /* We're going to put in an addu instruction using
9230 tempreg, so we may as well insert the nop right
9235 else if (expr1
.X_add_number
>= -0x8000
9236 && expr1
.X_add_number
< 0x8000)
9239 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9240 tempreg
, tempreg
, BFD_RELOC_LO16
);
9244 /* If we are going to add in a base register, and the
9245 target register and the base register are the same,
9246 then we are using AT as a temporary register. Since
9247 we want to load the constant into AT, we add our
9248 current AT (from the global offset table) and the
9249 register into the register now, and pretend we were
9250 not using a base register. */
9255 gas_assert (tempreg
== AT
);
9257 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9262 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9263 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
9267 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
9272 /* This is needed because this instruction uses $gp, but
9273 the first instruction on the main stream does not. */
9274 macro_build (NULL
, "nop", "");
9277 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9278 local_reloc_type
, mips_gp_register
);
9279 if (expr1
.X_add_number
>= -0x8000
9280 && expr1
.X_add_number
< 0x8000)
9283 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9284 tempreg
, tempreg
, BFD_RELOC_LO16
);
9285 /* FIXME: If add_number is 0, and there was no base
9286 register, the external symbol case ended with a load,
9287 so if the symbol turns out to not be external, and
9288 the next instruction uses tempreg, an unnecessary nop
9289 will be inserted. */
9295 /* We must add in the base register now, as in the
9296 external symbol case. */
9297 gas_assert (tempreg
== AT
);
9299 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9302 /* We set breg to 0 because we have arranged to add
9303 it in in both cases. */
9307 macro_build_lui (&expr1
, AT
);
9308 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9309 AT
, AT
, BFD_RELOC_LO16
);
9310 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9311 tempreg
, tempreg
, AT
);
9316 else if (mips_big_got
&& HAVE_NEWABI
)
9318 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
9319 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
9320 int add_breg_early
= 0;
9322 /* This is the large GOT case. If this is a reference to an
9323 external symbol, and there is no constant, we want
9324 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9325 add $tempreg,$tempreg,$gp
9326 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9327 or for lca or if tempreg is PIC_CALL_REG
9328 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9329 add $tempreg,$tempreg,$gp
9330 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9332 If we have a small constant, and this is a reference to
9333 an external symbol, we want
9334 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9335 add $tempreg,$tempreg,$gp
9336 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9337 addi $tempreg,$tempreg,<constant>
9339 If we have a large constant, and this is a reference to
9340 an external symbol, we want
9341 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9342 addu $tempreg,$tempreg,$gp
9343 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9344 lui $at,<hiconstant>
9345 addi $at,$at,<loconstant>
9346 add $tempreg,$tempreg,$at
9348 If we have NewABI, and we know it's a local symbol, we want
9349 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9350 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9351 otherwise we have to resort to GOT_HI16/GOT_LO16. */
9353 relax_start (offset_expr
.X_add_symbol
);
9355 expr1
.X_add_number
= offset_expr
.X_add_number
;
9356 offset_expr
.X_add_number
= 0;
9358 if (expr1
.X_add_number
== 0 && breg
== 0
9359 && (call
|| tempreg
== PIC_CALL_REG
))
9361 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
9362 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
9364 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
9365 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9366 tempreg
, tempreg
, mips_gp_register
);
9367 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9368 tempreg
, lw_reloc_type
, tempreg
);
9370 if (expr1
.X_add_number
== 0)
9372 else if (expr1
.X_add_number
>= -0x8000
9373 && expr1
.X_add_number
< 0x8000)
9375 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9376 tempreg
, tempreg
, BFD_RELOC_LO16
);
9378 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
9380 /* If we are going to add in a base register, and the
9381 target register and the base register are the same,
9382 then we are using AT as a temporary register. Since
9383 we want to load the constant into AT, we add our
9384 current AT (from the global offset table) and the
9385 register into the register now, and pretend we were
9386 not using a base register. */
9391 gas_assert (tempreg
== AT
);
9392 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9398 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9399 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
9404 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9407 offset_expr
.X_add_number
= expr1
.X_add_number
;
9408 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9409 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9410 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9411 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
9414 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9415 treg
, tempreg
, breg
);
9425 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
9429 gas_assert (!mips_opts
.micromips
);
9430 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x01);
9434 gas_assert (!mips_opts
.micromips
);
9435 macro_build (NULL
, "c2", "C", 0x02);
9439 gas_assert (!mips_opts
.micromips
);
9440 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x02);
9444 gas_assert (!mips_opts
.micromips
);
9445 macro_build (NULL
, "c2", "C", 3);
9449 gas_assert (!mips_opts
.micromips
);
9450 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x03);
9454 /* The j instruction may not be used in PIC code, since it
9455 requires an absolute address. We convert it to a b
9457 if (mips_pic
== NO_PIC
)
9458 macro_build (&offset_expr
, "j", "a");
9460 macro_build (&offset_expr
, "b", "p");
9463 /* The jal instructions must be handled as macros because when
9464 generating PIC code they expand to multi-instruction
9465 sequences. Normally they are simple instructions. */
9470 gas_assert (mips_opts
.micromips
);
9471 if (mips_opts
.insn32
)
9473 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9483 if (mips_pic
== NO_PIC
)
9485 s
= jals
? "jalrs" : "jalr";
9486 if (mips_opts
.micromips
9487 && !mips_opts
.insn32
9489 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9490 macro_build (NULL
, s
, "mj", sreg
);
9492 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
9496 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
9497 && mips_cprestore_offset
>= 0);
9499 if (sreg
!= PIC_CALL_REG
)
9500 as_warn (_("MIPS PIC call to register other than $25"));
9502 s
= ((mips_opts
.micromips
9503 && !mips_opts
.insn32
9504 && (!mips_opts
.noreorder
|| cprestore
))
9505 ? "jalrs" : "jalr");
9506 if (mips_opts
.micromips
9507 && !mips_opts
.insn32
9509 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9510 macro_build (NULL
, s
, "mj", sreg
);
9512 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
9513 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
9515 if (mips_cprestore_offset
< 0)
9516 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9519 if (!mips_frame_reg_valid
)
9521 as_warn (_("No .frame pseudo-op used in PIC code"));
9522 /* Quiet this warning. */
9523 mips_frame_reg_valid
= 1;
9525 if (!mips_cprestore_valid
)
9527 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9528 /* Quiet this warning. */
9529 mips_cprestore_valid
= 1;
9531 if (mips_opts
.noreorder
)
9532 macro_build (NULL
, "nop", "");
9533 expr1
.X_add_number
= mips_cprestore_offset
;
9534 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9537 HAVE_64BIT_ADDRESSES
);
9545 gas_assert (mips_opts
.micromips
);
9546 if (mips_opts
.insn32
)
9548 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9554 if (mips_pic
== NO_PIC
)
9555 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
9556 else if (mips_pic
== SVR4_PIC
)
9558 /* If this is a reference to an external symbol, and we are
9559 using a small GOT, we want
9560 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9564 lw $gp,cprestore($sp)
9565 The cprestore value is set using the .cprestore
9566 pseudo-op. If we are using a big GOT, we want
9567 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9569 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9573 lw $gp,cprestore($sp)
9574 If the symbol is not external, we want
9575 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9577 addiu $25,$25,<sym> (BFD_RELOC_LO16)
9580 lw $gp,cprestore($sp)
9582 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9583 sequences above, minus nops, unless the symbol is local,
9584 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9590 relax_start (offset_expr
.X_add_symbol
);
9591 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9592 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9595 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9596 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
9602 relax_start (offset_expr
.X_add_symbol
);
9603 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9604 BFD_RELOC_MIPS_CALL_HI16
);
9605 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9606 PIC_CALL_REG
, mips_gp_register
);
9607 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9608 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9611 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9612 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
9614 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9615 PIC_CALL_REG
, PIC_CALL_REG
,
9616 BFD_RELOC_MIPS_GOT_OFST
);
9620 macro_build_jalr (&offset_expr
, 0);
9624 relax_start (offset_expr
.X_add_symbol
);
9627 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9628 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9637 gpdelay
= reg_needs_delay (mips_gp_register
);
9638 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9639 BFD_RELOC_MIPS_CALL_HI16
);
9640 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9641 PIC_CALL_REG
, mips_gp_register
);
9642 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9643 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9648 macro_build (NULL
, "nop", "");
9650 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9651 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
9654 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9655 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
9657 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
9659 if (mips_cprestore_offset
< 0)
9660 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9663 if (!mips_frame_reg_valid
)
9665 as_warn (_("No .frame pseudo-op used in PIC code"));
9666 /* Quiet this warning. */
9667 mips_frame_reg_valid
= 1;
9669 if (!mips_cprestore_valid
)
9671 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9672 /* Quiet this warning. */
9673 mips_cprestore_valid
= 1;
9675 if (mips_opts
.noreorder
)
9676 macro_build (NULL
, "nop", "");
9677 expr1
.X_add_number
= mips_cprestore_offset
;
9678 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9681 HAVE_64BIT_ADDRESSES
);
9685 else if (mips_pic
== VXWORKS_PIC
)
9686 as_bad (_("Non-PIC jump used in PIC library"));
9764 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
9770 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
9795 gas_assert (!mips_opts
.micromips
);
9798 /* Itbl support may require additional care here. */
9804 /* Itbl support may require additional care here. */
9810 offbits
= (mips_opts
.micromips
? 12 : 16);
9811 /* Itbl support may require additional care here. */
9815 gas_assert (!mips_opts
.micromips
);
9818 /* Itbl support may require additional care here. */
9824 offbits
= (mips_opts
.micromips
? 12 : 16);
9829 offbits
= (mips_opts
.micromips
? 12 : 16);
9834 /* Itbl support may require additional care here. */
9840 offbits
= (mips_opts
.micromips
? 12 : 16);
9841 /* Itbl support may require additional care here. */
9847 /* Itbl support may require additional care here. */
9853 /* Itbl support may require additional care here. */
9859 offbits
= (mips_opts
.micromips
? 12 : 16);
9864 offbits
= (mips_opts
.micromips
? 12 : 16);
9869 offbits
= (mips_opts
.micromips
? 12 : 16);
9874 offbits
= (mips_opts
.micromips
? 12 : 16);
9879 offbits
= (mips_opts
.micromips
? 12 : 16);
9882 gas_assert (mips_opts
.micromips
);
9889 gas_assert (mips_opts
.micromips
);
9896 gas_assert (mips_opts
.micromips
);
9902 gas_assert (mips_opts
.micromips
);
9909 /* We don't want to use $0 as tempreg. */
9910 if (breg
== treg
+ lp
|| treg
+ lp
== ZERO
)
9913 tempreg
= treg
+ lp
;
9929 gas_assert (!mips_opts
.micromips
);
9932 /* Itbl support may require additional care here. */
9938 /* Itbl support may require additional care here. */
9944 offbits
= (mips_opts
.micromips
? 12 : 16);
9945 /* Itbl support may require additional care here. */
9949 gas_assert (!mips_opts
.micromips
);
9952 /* Itbl support may require additional care here. */
9958 offbits
= (mips_opts
.micromips
? 12 : 16);
9963 offbits
= (mips_opts
.micromips
? 12 : 16);
9968 offbits
= (mips_opts
.micromips
? 12 : 16);
9973 offbits
= (mips_opts
.micromips
? 12 : 16);
9977 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
9978 offbits
= (mips_opts
.micromips
? 12 : 16);
9987 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
9988 offbits
= (mips_opts
.micromips
? 12 : 16);
9999 /* Itbl support may require additional care here. */
10004 offbits
= (mips_opts
.micromips
? 12 : 16);
10005 /* Itbl support may require additional care here. */
10011 /* Itbl support may require additional care here. */
10015 gas_assert (!mips_opts
.micromips
);
10018 /* Itbl support may require additional care here. */
10024 offbits
= (mips_opts
.micromips
? 12 : 16);
10029 offbits
= (mips_opts
.micromips
? 12 : 16);
10032 gas_assert (mips_opts
.micromips
);
10038 gas_assert (mips_opts
.micromips
);
10044 gas_assert (mips_opts
.micromips
);
10050 gas_assert (mips_opts
.micromips
);
10058 if (small_offset_p (0, align
, 16))
10060 /* The first case exists for M_LD_AB and M_SD_AB, which are
10061 macros for o32 but which should act like normal instructions
10064 macro_build (&offset_expr
, s
, fmt
, treg
, -1, offset_reloc
[0],
10065 offset_reloc
[1], offset_reloc
[2], breg
);
10066 else if (small_offset_p (0, align
, offbits
))
10069 macro_build (NULL
, s
, fmt
, treg
, breg
);
10071 macro_build (NULL
, s
, fmt
, treg
,
10072 (int) offset_expr
.X_add_number
, breg
);
10078 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10079 tempreg
, breg
, -1, offset_reloc
[0],
10080 offset_reloc
[1], offset_reloc
[2]);
10082 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
10084 macro_build (NULL
, s
, fmt
, treg
, 0, tempreg
);
10092 if (offset_expr
.X_op
!= O_constant
10093 && offset_expr
.X_op
!= O_symbol
)
10095 as_bad (_("Expression too complex"));
10096 offset_expr
.X_op
= O_constant
;
10099 if (HAVE_32BIT_ADDRESSES
10100 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10104 sprintf_vma (value
, offset_expr
.X_add_number
);
10105 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
10108 /* A constant expression in PIC code can be handled just as it
10109 is in non PIC code. */
10110 if (offset_expr
.X_op
== O_constant
)
10112 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
10113 offbits
== 0 ? 16 : offbits
);
10114 offset_expr
.X_add_number
-= expr1
.X_add_number
;
10116 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
10118 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10119 tempreg
, tempreg
, breg
);
10122 if (offset_expr
.X_add_number
!= 0)
10123 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
10124 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
10125 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
10127 else if (offbits
== 16)
10128 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
10130 macro_build (NULL
, s
, fmt
, treg
,
10131 (int) offset_expr
.X_add_number
, tempreg
);
10133 else if (offbits
!= 16)
10135 /* The offset field is too narrow to be used for a low-part
10136 relocation, so load the whole address into the auxillary
10138 load_address (tempreg
, &offset_expr
, &used_at
);
10140 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10141 tempreg
, tempreg
, breg
);
10143 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
10145 macro_build (NULL
, s
, fmt
, treg
, 0, tempreg
);
10147 else if (mips_pic
== NO_PIC
)
10149 /* If this is a reference to a GP relative symbol, and there
10150 is no base register, we want
10151 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10152 Otherwise, if there is no base register, we want
10153 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10154 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10155 If we have a constant, we need two instructions anyhow,
10156 so we always use the latter form.
10158 If we have a base register, and this is a reference to a
10159 GP relative symbol, we want
10160 addu $tempreg,$breg,$gp
10161 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
10163 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10164 addu $tempreg,$tempreg,$breg
10165 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10166 With a constant we always use the latter case.
10168 With 64bit address space and no base register and $at usable,
10170 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10171 lui $at,<sym> (BFD_RELOC_HI16_S)
10172 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10175 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10176 If we have a base register, we want
10177 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10178 lui $at,<sym> (BFD_RELOC_HI16_S)
10179 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10183 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10185 Without $at we can't generate the optimal path for superscalar
10186 processors here since this would require two temporary registers.
10187 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10188 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10190 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10192 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10193 If we have a base register, we want
10194 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10195 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10197 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10199 daddu $tempreg,$tempreg,$breg
10200 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10202 For GP relative symbols in 64bit address space we can use
10203 the same sequence as in 32bit address space. */
10204 if (HAVE_64BIT_SYMBOLS
)
10206 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10207 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10209 relax_start (offset_expr
.X_add_symbol
);
10212 macro_build (&offset_expr
, s
, fmt
, treg
,
10213 BFD_RELOC_GPREL16
, mips_gp_register
);
10217 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10218 tempreg
, breg
, mips_gp_register
);
10219 macro_build (&offset_expr
, s
, fmt
, treg
,
10220 BFD_RELOC_GPREL16
, tempreg
);
10225 if (used_at
== 0 && mips_opts
.at
)
10227 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10228 BFD_RELOC_MIPS_HIGHEST
);
10229 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
10231 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10232 tempreg
, BFD_RELOC_MIPS_HIGHER
);
10234 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
10235 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10236 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10237 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
10243 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10244 BFD_RELOC_MIPS_HIGHEST
);
10245 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10246 tempreg
, BFD_RELOC_MIPS_HIGHER
);
10247 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10248 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10249 tempreg
, BFD_RELOC_HI16_S
);
10250 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10252 macro_build (NULL
, "daddu", "d,v,t",
10253 tempreg
, tempreg
, breg
);
10254 macro_build (&offset_expr
, s
, fmt
, treg
,
10255 BFD_RELOC_LO16
, tempreg
);
10258 if (mips_relax
.sequence
)
10265 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10266 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10268 relax_start (offset_expr
.X_add_symbol
);
10269 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
10273 macro_build_lui (&offset_expr
, tempreg
);
10274 macro_build (&offset_expr
, s
, fmt
, treg
,
10275 BFD_RELOC_LO16
, tempreg
);
10276 if (mips_relax
.sequence
)
10281 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10282 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10284 relax_start (offset_expr
.X_add_symbol
);
10285 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10286 tempreg
, breg
, mips_gp_register
);
10287 macro_build (&offset_expr
, s
, fmt
, treg
,
10288 BFD_RELOC_GPREL16
, tempreg
);
10291 macro_build_lui (&offset_expr
, tempreg
);
10292 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10293 tempreg
, tempreg
, breg
);
10294 macro_build (&offset_expr
, s
, fmt
, treg
,
10295 BFD_RELOC_LO16
, tempreg
);
10296 if (mips_relax
.sequence
)
10300 else if (!mips_big_got
)
10302 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10304 /* If this is a reference to an external symbol, we want
10305 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10307 <op> $treg,0($tempreg)
10309 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10311 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10312 <op> $treg,0($tempreg)
10314 For NewABI, we want
10315 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10316 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
10318 If there is a base register, we add it to $tempreg before
10319 the <op>. If there is a constant, we stick it in the
10320 <op> instruction. We don't handle constants larger than
10321 16 bits, because we have no way to load the upper 16 bits
10322 (actually, we could handle them for the subset of cases
10323 in which we are not using $at). */
10324 gas_assert (offset_expr
.X_op
== O_symbol
);
10327 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10328 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10330 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10331 tempreg
, tempreg
, breg
);
10332 macro_build (&offset_expr
, s
, fmt
, treg
,
10333 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
10336 expr1
.X_add_number
= offset_expr
.X_add_number
;
10337 offset_expr
.X_add_number
= 0;
10338 if (expr1
.X_add_number
< -0x8000
10339 || expr1
.X_add_number
>= 0x8000)
10340 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10341 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10342 lw_reloc_type
, mips_gp_register
);
10344 relax_start (offset_expr
.X_add_symbol
);
10346 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10347 tempreg
, BFD_RELOC_LO16
);
10350 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10351 tempreg
, tempreg
, breg
);
10352 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
10354 else if (mips_big_got
&& !HAVE_NEWABI
)
10358 /* If this is a reference to an external symbol, we want
10359 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10360 addu $tempreg,$tempreg,$gp
10361 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10362 <op> $treg,0($tempreg)
10364 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10366 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10367 <op> $treg,0($tempreg)
10368 If there is a base register, we add it to $tempreg before
10369 the <op>. If there is a constant, we stick it in the
10370 <op> instruction. We don't handle constants larger than
10371 16 bits, because we have no way to load the upper 16 bits
10372 (actually, we could handle them for the subset of cases
10373 in which we are not using $at). */
10374 gas_assert (offset_expr
.X_op
== O_symbol
);
10375 expr1
.X_add_number
= offset_expr
.X_add_number
;
10376 offset_expr
.X_add_number
= 0;
10377 if (expr1
.X_add_number
< -0x8000
10378 || expr1
.X_add_number
>= 0x8000)
10379 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10380 gpdelay
= reg_needs_delay (mips_gp_register
);
10381 relax_start (offset_expr
.X_add_symbol
);
10382 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10383 BFD_RELOC_MIPS_GOT_HI16
);
10384 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
10386 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10387 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
10390 macro_build (NULL
, "nop", "");
10391 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10392 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10394 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10395 tempreg
, BFD_RELOC_LO16
);
10399 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10400 tempreg
, tempreg
, breg
);
10401 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
10403 else if (mips_big_got
&& HAVE_NEWABI
)
10405 /* If this is a reference to an external symbol, we want
10406 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10407 add $tempreg,$tempreg,$gp
10408 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10409 <op> $treg,<ofst>($tempreg)
10410 Otherwise, for local symbols, we want:
10411 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10412 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
10413 gas_assert (offset_expr
.X_op
== O_symbol
);
10414 expr1
.X_add_number
= offset_expr
.X_add_number
;
10415 offset_expr
.X_add_number
= 0;
10416 if (expr1
.X_add_number
< -0x8000
10417 || expr1
.X_add_number
>= 0x8000)
10418 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10419 relax_start (offset_expr
.X_add_symbol
);
10420 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10421 BFD_RELOC_MIPS_GOT_HI16
);
10422 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
10424 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10425 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
10427 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10428 tempreg
, tempreg
, breg
);
10429 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
10432 offset_expr
.X_add_number
= expr1
.X_add_number
;
10433 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10434 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10436 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10437 tempreg
, tempreg
, breg
);
10438 macro_build (&offset_expr
, s
, fmt
, treg
,
10439 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
10448 gas_assert (mips_opts
.micromips
);
10449 gas_assert (mips_opts
.insn32
);
10450 start_noreorder ();
10451 macro_build (NULL
, "jr", "s", RA
);
10452 expr1
.X_add_number
= EXTRACT_OPERAND (1, IMMP
, *ip
) << 2;
10453 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
10458 gas_assert (mips_opts
.micromips
);
10459 gas_assert (mips_opts
.insn32
);
10460 macro_build (NULL
, "jr", "s", sreg
);
10461 if (mips_opts
.noreorder
)
10462 macro_build (NULL
, "nop", "");
10467 load_register (treg
, &imm_expr
, 0);
10471 load_register (treg
, &imm_expr
, 1);
10475 if (imm_expr
.X_op
== O_constant
)
10478 load_register (AT
, &imm_expr
, 0);
10479 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
10484 gas_assert (offset_expr
.X_op
== O_symbol
10485 && strcmp (segment_name (S_GET_SEGMENT
10486 (offset_expr
.X_add_symbol
)),
10488 && offset_expr
.X_add_number
== 0);
10489 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
10490 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
10495 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
10496 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
10497 order 32 bits of the value and the low order 32 bits are either
10498 zero or in OFFSET_EXPR. */
10499 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10501 if (HAVE_64BIT_GPRS
)
10502 load_register (treg
, &imm_expr
, 1);
10507 if (target_big_endian
)
10519 load_register (hreg
, &imm_expr
, 0);
10522 if (offset_expr
.X_op
== O_absent
)
10523 move_register (lreg
, 0);
10526 gas_assert (offset_expr
.X_op
== O_constant
);
10527 load_register (lreg
, &offset_expr
, 0);
10534 /* We know that sym is in the .rdata section. First we get the
10535 upper 16 bits of the address. */
10536 if (mips_pic
== NO_PIC
)
10538 macro_build_lui (&offset_expr
, AT
);
10543 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10544 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10548 /* Now we load the register(s). */
10549 if (HAVE_64BIT_GPRS
)
10552 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
10557 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
10560 /* FIXME: How in the world do we deal with the possible
10562 offset_expr
.X_add_number
+= 4;
10563 macro_build (&offset_expr
, "lw", "t,o(b)",
10564 treg
+ 1, BFD_RELOC_LO16
, AT
);
10570 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10571 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10572 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10573 the value and the low order 32 bits are either zero or in
10575 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10578 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
10579 if (HAVE_64BIT_FPRS
)
10581 gas_assert (HAVE_64BIT_GPRS
);
10582 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
10586 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
10587 if (offset_expr
.X_op
== O_absent
)
10588 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
10591 gas_assert (offset_expr
.X_op
== O_constant
);
10592 load_register (AT
, &offset_expr
, 0);
10593 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
10599 gas_assert (offset_expr
.X_op
== O_symbol
10600 && offset_expr
.X_add_number
== 0);
10601 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
10602 if (strcmp (s
, ".lit8") == 0)
10604 breg
= mips_gp_register
;
10605 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
10606 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10607 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10611 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
10613 if (mips_pic
!= NO_PIC
)
10614 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10615 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10618 /* FIXME: This won't work for a 64 bit address. */
10619 macro_build_lui (&offset_expr
, AT
);
10623 offset_reloc
[0] = BFD_RELOC_LO16
;
10624 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10625 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10632 * The MIPS assembler seems to check for X_add_number not
10633 * being double aligned and generating:
10634 * lui at,%hi(foo+1)
10636 * addiu at,at,%lo(foo+1)
10639 * But, the resulting address is the same after relocation so why
10640 * generate the extra instruction?
10642 /* Itbl support may require additional care here. */
10645 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10654 gas_assert (!mips_opts
.micromips
);
10655 /* Itbl support may require additional care here. */
10658 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10678 if (HAVE_64BIT_GPRS
)
10688 if (HAVE_64BIT_GPRS
)
10696 /* Even on a big endian machine $fn comes before $fn+1. We have
10697 to adjust when loading from memory. We set coproc if we must
10698 load $fn+1 first. */
10699 /* Itbl support may require additional care here. */
10700 if (!target_big_endian
)
10703 if (small_offset_p (0, align
, 16))
10706 if (!small_offset_p (4, align
, 16))
10708 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
10709 -1, offset_reloc
[0], offset_reloc
[1],
10711 expr1
.X_add_number
= 0;
10715 offset_reloc
[0] = BFD_RELOC_LO16
;
10716 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10717 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10719 if (strcmp (s
, "lw") == 0 && treg
== breg
)
10721 ep
->X_add_number
+= 4;
10722 macro_build (ep
, s
, fmt
, treg
+ 1, -1, offset_reloc
[0],
10723 offset_reloc
[1], offset_reloc
[2], breg
);
10724 ep
->X_add_number
-= 4;
10725 macro_build (ep
, s
, fmt
, treg
, -1, offset_reloc
[0],
10726 offset_reloc
[1], offset_reloc
[2], breg
);
10730 macro_build (ep
, s
, fmt
, coproc
? treg
+ 1 : treg
, -1,
10731 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
10733 ep
->X_add_number
+= 4;
10734 macro_build (ep
, s
, fmt
, coproc
? treg
: treg
+ 1, -1,
10735 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
10741 if (offset_expr
.X_op
!= O_symbol
10742 && offset_expr
.X_op
!= O_constant
)
10744 as_bad (_("Expression too complex"));
10745 offset_expr
.X_op
= O_constant
;
10748 if (HAVE_32BIT_ADDRESSES
10749 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10753 sprintf_vma (value
, offset_expr
.X_add_number
);
10754 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
10757 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
10759 /* If this is a reference to a GP relative symbol, we want
10760 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10761 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
10762 If we have a base register, we use this
10764 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
10765 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
10766 If this is not a GP relative symbol, we want
10767 lui $at,<sym> (BFD_RELOC_HI16_S)
10768 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10769 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10770 If there is a base register, we add it to $at after the
10771 lui instruction. If there is a constant, we always use
10773 if (offset_expr
.X_op
== O_symbol
10774 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10775 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10777 relax_start (offset_expr
.X_add_symbol
);
10780 tempreg
= mips_gp_register
;
10784 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10785 AT
, breg
, mips_gp_register
);
10790 /* Itbl support may require additional care here. */
10791 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10792 BFD_RELOC_GPREL16
, tempreg
);
10793 offset_expr
.X_add_number
+= 4;
10795 /* Set mips_optimize to 2 to avoid inserting an
10797 hold_mips_optimize
= mips_optimize
;
10799 /* Itbl support may require additional care here. */
10800 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10801 BFD_RELOC_GPREL16
, tempreg
);
10802 mips_optimize
= hold_mips_optimize
;
10806 offset_expr
.X_add_number
-= 4;
10809 if (offset_high_part (offset_expr
.X_add_number
, 16)
10810 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
10812 load_address (AT
, &offset_expr
, &used_at
);
10813 offset_expr
.X_op
= O_constant
;
10814 offset_expr
.X_add_number
= 0;
10817 macro_build_lui (&offset_expr
, AT
);
10819 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10820 /* Itbl support may require additional care here. */
10821 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10822 BFD_RELOC_LO16
, AT
);
10823 /* FIXME: How do we handle overflow here? */
10824 offset_expr
.X_add_number
+= 4;
10825 /* Itbl support may require additional care here. */
10826 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10827 BFD_RELOC_LO16
, AT
);
10828 if (mips_relax
.sequence
)
10831 else if (!mips_big_got
)
10833 /* If this is a reference to an external symbol, we want
10834 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10837 <op> $treg+1,4($at)
10839 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10841 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10842 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10843 If there is a base register we add it to $at before the
10844 lwc1 instructions. If there is a constant we include it
10845 in the lwc1 instructions. */
10847 expr1
.X_add_number
= offset_expr
.X_add_number
;
10848 if (expr1
.X_add_number
< -0x8000
10849 || expr1
.X_add_number
>= 0x8000 - 4)
10850 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10851 load_got_offset (AT
, &offset_expr
);
10854 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10856 /* Set mips_optimize to 2 to avoid inserting an undesired
10858 hold_mips_optimize
= mips_optimize
;
10861 /* Itbl support may require additional care here. */
10862 relax_start (offset_expr
.X_add_symbol
);
10863 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10864 BFD_RELOC_LO16
, AT
);
10865 expr1
.X_add_number
+= 4;
10866 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
10867 BFD_RELOC_LO16
, AT
);
10869 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10870 BFD_RELOC_LO16
, AT
);
10871 offset_expr
.X_add_number
+= 4;
10872 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10873 BFD_RELOC_LO16
, AT
);
10876 mips_optimize
= hold_mips_optimize
;
10878 else if (mips_big_got
)
10882 /* If this is a reference to an external symbol, we want
10883 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10885 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
10888 <op> $treg+1,4($at)
10890 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10892 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10893 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10894 If there is a base register we add it to $at before the
10895 lwc1 instructions. If there is a constant we include it
10896 in the lwc1 instructions. */
10898 expr1
.X_add_number
= offset_expr
.X_add_number
;
10899 offset_expr
.X_add_number
= 0;
10900 if (expr1
.X_add_number
< -0x8000
10901 || expr1
.X_add_number
>= 0x8000 - 4)
10902 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10903 gpdelay
= reg_needs_delay (mips_gp_register
);
10904 relax_start (offset_expr
.X_add_symbol
);
10905 macro_build (&offset_expr
, "lui", LUI_FMT
,
10906 AT
, BFD_RELOC_MIPS_GOT_HI16
);
10907 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10908 AT
, AT
, mips_gp_register
);
10909 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10910 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
10913 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10914 /* Itbl support may require additional care here. */
10915 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10916 BFD_RELOC_LO16
, AT
);
10917 expr1
.X_add_number
+= 4;
10919 /* Set mips_optimize to 2 to avoid inserting an undesired
10921 hold_mips_optimize
= mips_optimize
;
10923 /* Itbl support may require additional care here. */
10924 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
10925 BFD_RELOC_LO16
, AT
);
10926 mips_optimize
= hold_mips_optimize
;
10927 expr1
.X_add_number
-= 4;
10930 offset_expr
.X_add_number
= expr1
.X_add_number
;
10932 macro_build (NULL
, "nop", "");
10933 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10934 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10937 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10938 /* Itbl support may require additional care here. */
10939 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10940 BFD_RELOC_LO16
, AT
);
10941 offset_expr
.X_add_number
+= 4;
10943 /* Set mips_optimize to 2 to avoid inserting an undesired
10945 hold_mips_optimize
= mips_optimize
;
10947 /* Itbl support may require additional care here. */
10948 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10949 BFD_RELOC_LO16
, AT
);
10950 mips_optimize
= hold_mips_optimize
;
10969 /* New code added to support COPZ instructions.
10970 This code builds table entries out of the macros in mip_opcodes.
10971 R4000 uses interlocks to handle coproc delays.
10972 Other chips (like the R3000) require nops to be inserted for delays.
10974 FIXME: Currently, we require that the user handle delays.
10975 In order to fill delay slots for non-interlocked chips,
10976 we must have a way to specify delays based on the coprocessor.
10977 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
10978 What are the side-effects of the cop instruction?
10979 What cache support might we have and what are its effects?
10980 Both coprocessor & memory require delays. how long???
10981 What registers are read/set/modified?
10983 If an itbl is provided to interpret cop instructions,
10984 this knowledge can be encoded in the itbl spec. */
10998 gas_assert (!mips_opts
.micromips
);
10999 /* For now we just do C (same as Cz). The parameter will be
11000 stored in insn_opcode by mips_ip. */
11001 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11005 move_register (dreg
, sreg
);
11009 gas_assert (mips_opts
.micromips
);
11010 gas_assert (mips_opts
.insn32
);
11011 dreg
= micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
11012 breg
= micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
11013 sreg
= micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
11014 treg
= micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
11015 move_register (dreg
, sreg
);
11016 move_register (breg
, treg
);
11022 if (mips_opts
.arch
== CPU_R5900
)
11024 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
11028 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
11029 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
11036 /* The MIPS assembler some times generates shifts and adds. I'm
11037 not trying to be that fancy. GCC should do this for us
11040 load_register (AT
, &imm_expr
, dbl
);
11041 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
11042 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
11055 start_noreorder ();
11058 load_register (AT
, &imm_expr
, dbl
);
11059 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
11060 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
11061 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
11062 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11064 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
11067 if (mips_opts
.micromips
)
11068 micromips_label_expr (&label_expr
);
11070 label_expr
.X_add_number
= 8;
11071 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
11072 macro_build (NULL
, "nop", "");
11073 macro_build (NULL
, "break", BRK_FMT
, 6);
11074 if (mips_opts
.micromips
)
11075 micromips_add_label ();
11078 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
11091 start_noreorder ();
11094 load_register (AT
, &imm_expr
, dbl
);
11095 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
11096 sreg
, imm
? AT
: treg
);
11097 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11098 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
11100 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
11103 if (mips_opts
.micromips
)
11104 micromips_label_expr (&label_expr
);
11106 label_expr
.X_add_number
= 8;
11107 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
11108 macro_build (NULL
, "nop", "");
11109 macro_build (NULL
, "break", BRK_FMT
, 6);
11110 if (mips_opts
.micromips
)
11111 micromips_add_label ();
11117 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11128 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
11129 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
11133 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
11134 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
11135 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
11136 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11140 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11151 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
11152 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
11156 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
11157 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
11158 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
11159 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11168 if (imm_expr
.X_op
!= O_constant
)
11169 as_bad (_("Improper rotate count"));
11170 rot
= imm_expr
.X_add_number
& 0x3f;
11171 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11173 rot
= (64 - rot
) & 0x3f;
11175 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
11177 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
11182 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
11185 l
= (rot
< 0x20) ? "dsll" : "dsll32";
11186 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
11189 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
11190 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
11191 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11199 if (imm_expr
.X_op
!= O_constant
)
11200 as_bad (_("Improper rotate count"));
11201 rot
= imm_expr
.X_add_number
& 0x1f;
11202 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11204 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
11209 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
11213 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
11214 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
11215 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11220 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11222 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
11226 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
11227 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
11228 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
11229 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11233 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11235 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
11239 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
11240 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
11241 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
11242 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11251 if (imm_expr
.X_op
!= O_constant
)
11252 as_bad (_("Improper rotate count"));
11253 rot
= imm_expr
.X_add_number
& 0x3f;
11254 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11257 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
11259 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
11264 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
11267 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
11268 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
11271 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
11272 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
11273 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11281 if (imm_expr
.X_op
!= O_constant
)
11282 as_bad (_("Improper rotate count"));
11283 rot
= imm_expr
.X_add_number
& 0x1f;
11284 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11286 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
11291 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
11295 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
11296 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
11297 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11303 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
11304 else if (treg
== 0)
11305 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11308 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
11309 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
11314 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
11316 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11321 as_warn (_("Instruction %s: result is always false"),
11322 ip
->insn_mo
->name
);
11323 move_register (dreg
, 0);
11326 if (CPU_HAS_SEQ (mips_opts
.arch
)
11327 && -512 <= imm_expr
.X_add_number
11328 && imm_expr
.X_add_number
< 512)
11330 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
11331 (int) imm_expr
.X_add_number
);
11334 if (imm_expr
.X_op
== O_constant
11335 && imm_expr
.X_add_number
>= 0
11336 && imm_expr
.X_add_number
< 0x10000)
11338 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
11340 else if (imm_expr
.X_op
== O_constant
11341 && imm_expr
.X_add_number
> -0x8000
11342 && imm_expr
.X_add_number
< 0)
11344 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11345 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
11346 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11348 else if (CPU_HAS_SEQ (mips_opts
.arch
))
11351 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11352 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
11357 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11358 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
11361 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
11364 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
11370 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
11371 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11374 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
11376 if (imm_expr
.X_op
== O_constant
11377 && imm_expr
.X_add_number
>= -0x8000
11378 && imm_expr
.X_add_number
< 0x8000)
11380 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
11381 dreg
, sreg
, BFD_RELOC_LO16
);
11385 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11386 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
11390 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11393 case M_SGT
: /* sreg > treg <==> treg < sreg */
11399 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
11402 case M_SGT_I
: /* sreg > I <==> I < sreg */
11409 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11410 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
11413 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
11419 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
11420 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11423 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
11430 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11431 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
11432 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11436 if (imm_expr
.X_op
== O_constant
11437 && imm_expr
.X_add_number
>= -0x8000
11438 && imm_expr
.X_add_number
< 0x8000)
11440 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11444 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11445 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
11449 if (imm_expr
.X_op
== O_constant
11450 && imm_expr
.X_add_number
>= -0x8000
11451 && imm_expr
.X_add_number
< 0x8000)
11453 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
11458 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11459 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
11464 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
11465 else if (treg
== 0)
11466 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
11469 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
11470 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
11475 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
11477 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
11482 as_warn (_("Instruction %s: result is always true"),
11483 ip
->insn_mo
->name
);
11484 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
11485 dreg
, 0, BFD_RELOC_LO16
);
11488 if (CPU_HAS_SEQ (mips_opts
.arch
)
11489 && -512 <= imm_expr
.X_add_number
11490 && imm_expr
.X_add_number
< 512)
11492 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
11493 (int) imm_expr
.X_add_number
);
11496 if (imm_expr
.X_op
== O_constant
11497 && imm_expr
.X_add_number
>= 0
11498 && imm_expr
.X_add_number
< 0x10000)
11500 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
11502 else if (imm_expr
.X_op
== O_constant
11503 && imm_expr
.X_add_number
> -0x8000
11504 && imm_expr
.X_add_number
< 0)
11506 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11507 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
11508 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11510 else if (CPU_HAS_SEQ (mips_opts
.arch
))
11513 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11514 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
11519 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11520 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
11523 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
11538 if (!mips_opts
.micromips
)
11540 if (imm_expr
.X_op
== O_constant
11541 && imm_expr
.X_add_number
> -0x200
11542 && imm_expr
.X_add_number
<= 0x200)
11544 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
11553 if (imm_expr
.X_op
== O_constant
11554 && imm_expr
.X_add_number
> -0x8000
11555 && imm_expr
.X_add_number
<= 0x8000)
11557 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11558 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11563 load_register (AT
, &imm_expr
, dbl
);
11564 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
11586 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11587 macro_build (NULL
, s
, "s,t", sreg
, AT
);
11592 gas_assert (!mips_opts
.micromips
);
11593 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
11595 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
11596 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
11599 * Is the double cfc1 instruction a bug in the mips assembler;
11600 * or is there a reason for it?
11602 start_noreorder ();
11603 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
11604 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
11605 macro_build (NULL
, "nop", "");
11606 expr1
.X_add_number
= 3;
11607 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
11608 expr1
.X_add_number
= 2;
11609 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
11610 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
11611 macro_build (NULL
, "nop", "");
11612 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
11614 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
11615 macro_build (NULL
, "nop", "");
11632 offbits
= (mips_opts
.micromips
? 12 : 16);
11638 offbits
= (mips_opts
.micromips
? 12 : 16);
11650 offbits
= (mips_opts
.micromips
? 12 : 16);
11657 offbits
= (mips_opts
.micromips
? 12 : 16);
11662 large_offset
= !small_offset_p (off
, align
, offbits
);
11664 expr1
.X_add_number
= 0;
11669 if (small_offset_p (0, align
, 16))
11670 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
11671 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11674 load_address (tempreg
, ep
, &used_at
);
11676 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11677 tempreg
, tempreg
, breg
);
11679 offset_reloc
[0] = BFD_RELOC_LO16
;
11680 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11681 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11686 else if (!ust
&& treg
== breg
)
11697 if (!target_big_endian
)
11698 ep
->X_add_number
+= off
;
11700 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
11702 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
11703 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11705 if (!target_big_endian
)
11706 ep
->X_add_number
-= off
;
11708 ep
->X_add_number
+= off
;
11710 macro_build (NULL
, s2
, "t,~(b)",
11711 tempreg
, (int) ep
->X_add_number
, breg
);
11713 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
11714 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11716 /* If necessary, move the result in tempreg to the final destination. */
11717 if (!ust
&& treg
!= tempreg
)
11719 /* Protect second load's delay slot. */
11721 move_register (treg
, tempreg
);
11727 if (target_big_endian
== ust
)
11728 ep
->X_add_number
+= off
;
11729 tempreg
= ust
|| large_offset
? treg
: AT
;
11730 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
11731 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11733 /* For halfword transfers we need a temporary register to shuffle
11734 bytes. Unfortunately for M_USH_A we have none available before
11735 the next store as AT holds the base address. We deal with this
11736 case by clobbering TREG and then restoring it as with ULH. */
11737 tempreg
= ust
== large_offset
? treg
: AT
;
11739 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
11741 if (target_big_endian
== ust
)
11742 ep
->X_add_number
-= off
;
11744 ep
->X_add_number
+= off
;
11745 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
11746 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11748 /* For M_USH_A re-retrieve the LSB. */
11749 if (ust
&& large_offset
)
11751 if (target_big_endian
)
11752 ep
->X_add_number
+= off
;
11754 ep
->X_add_number
-= off
;
11755 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
11756 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
11758 /* For ULH and M_USH_A OR the LSB in. */
11759 if (!ust
|| large_offset
)
11761 tempreg
= !large_offset
? AT
: treg
;
11762 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
11763 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
11768 /* FIXME: Check if this is one of the itbl macros, since they
11769 are added dynamically. */
11770 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
11773 if (!mips_opts
.at
&& used_at
)
11774 as_bad (_("Macro used $at after \".set noat\""));
11777 /* Implement macros in mips16 mode. */
11780 mips16_macro (struct mips_cl_insn
*ip
)
11783 int xreg
, yreg
, zreg
, tmp
;
11786 const char *s
, *s2
, *s3
;
11788 mask
= ip
->insn_mo
->mask
;
11790 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
11791 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
11792 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
11794 expr1
.X_op
= O_constant
;
11795 expr1
.X_op_symbol
= NULL
;
11796 expr1
.X_add_symbol
= NULL
;
11797 expr1
.X_add_number
= 1;
11816 start_noreorder ();
11817 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
11818 expr1
.X_add_number
= 2;
11819 macro_build (&expr1
, "bnez", "x,p", yreg
);
11820 macro_build (NULL
, "break", "6", 7);
11822 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
11823 since that causes an overflow. We should do that as well,
11824 but I don't see how to do the comparisons without a temporary
11827 macro_build (NULL
, s
, "x", zreg
);
11846 start_noreorder ();
11847 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
11848 expr1
.X_add_number
= 2;
11849 macro_build (&expr1
, "bnez", "x,p", yreg
);
11850 macro_build (NULL
, "break", "6", 7);
11852 macro_build (NULL
, s2
, "x", zreg
);
11858 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
11859 macro_build (NULL
, "mflo", "x", zreg
);
11867 if (imm_expr
.X_op
!= O_constant
)
11868 as_bad (_("Unsupported large constant"));
11869 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11870 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
11874 if (imm_expr
.X_op
!= O_constant
)
11875 as_bad (_("Unsupported large constant"));
11876 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11877 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
11881 if (imm_expr
.X_op
!= O_constant
)
11882 as_bad (_("Unsupported large constant"));
11883 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11884 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
11906 goto do_reverse_branch
;
11910 goto do_reverse_branch
;
11922 goto do_reverse_branch
;
11933 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
11934 macro_build (&offset_expr
, s2
, "p");
11961 goto do_addone_branch_i
;
11966 goto do_addone_branch_i
;
11981 goto do_addone_branch_i
;
11987 do_addone_branch_i
:
11988 if (imm_expr
.X_op
!= O_constant
)
11989 as_bad (_("Unsupported large constant"));
11990 ++imm_expr
.X_add_number
;
11993 macro_build (&imm_expr
, s
, s3
, xreg
);
11994 macro_build (&offset_expr
, s2
, "p");
11998 expr1
.X_add_number
= 0;
11999 macro_build (&expr1
, "slti", "x,8", yreg
);
12001 move_register (xreg
, yreg
);
12002 expr1
.X_add_number
= 2;
12003 macro_build (&expr1
, "bteqz", "p");
12004 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
12008 /* Assemble an instruction into its binary format. If the instruction
12009 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12010 associated with "I", "+I" and "A" operands respectively. Otherwise
12011 store the value of the relocatable field (if any) in offset_expr.
12012 In both cases set offset_reloc to the relocation operators applied
12016 mips_ip (char *str
, struct mips_cl_insn
*ip
)
12018 bfd_boolean wrong_delay_slot_insns
= FALSE
;
12019 bfd_boolean need_delay_slot_ok
= TRUE
;
12020 struct mips_opcode
*firstinsn
= NULL
;
12021 const struct mips_opcode
*past
;
12022 struct hash_control
*hash
;
12025 struct mips_opcode
*insn
;
12031 const struct mips_operand
*operand
;
12032 struct mips_arg_info arg
;
12033 struct mips_operand_token
*tokens
;
12034 bfd_boolean optional_reg
;
12038 if (mips_opts
.micromips
)
12040 hash
= micromips_op_hash
;
12041 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
12046 past
= &mips_opcodes
[NUMOPCODES
];
12048 forced_insn_length
= 0;
12051 /* We first try to match an instruction up to a space or to the end. */
12052 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
12055 /* Make a copy of the instruction so that we can fiddle with it. */
12056 name
= alloca (end
+ 1);
12057 memcpy (name
, str
, end
);
12062 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12064 if (insn
!= NULL
|| !mips_opts
.micromips
)
12066 if (forced_insn_length
)
12069 /* See if there's an instruction size override suffix,
12070 either `16' or `32', at the end of the mnemonic proper,
12071 that defines the operation, i.e. before the first `.'
12072 character if any. Strip it and retry. */
12073 dot
= strchr (name
, '.');
12074 opend
= dot
!= NULL
? dot
- name
: end
;
12077 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
12078 forced_insn_length
= 2;
12079 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
12080 forced_insn_length
= 4;
12083 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
12087 insn_error
= _("Unrecognized opcode");
12091 if (strcmp (name
, "li.s") == 0)
12093 else if (strcmp (name
, "li.d") == 0)
12097 tokens
= mips_parse_arguments (str
+ end
, format
);
12101 /* For microMIPS instructions placed in a fixed-length branch delay slot
12102 we make up to two passes over the relevant fragment of the opcode
12103 table. First we try instructions that meet the delay slot's length
12104 requirement. If none matched, then we retry with the remaining ones
12105 and if one matches, then we use it and then issue an appropriate
12106 warning later on. */
12109 bfd_boolean delay_slot_ok
;
12110 bfd_boolean size_ok
;
12112 bfd_boolean more_alts
;
12114 gas_assert (strcmp (insn
->name
, name
) == 0);
12116 ok
= is_opcode_valid (insn
);
12117 size_ok
= is_size_valid (insn
);
12118 delay_slot_ok
= is_delay_slot_valid (insn
);
12119 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
12122 wrong_delay_slot_insns
= TRUE
;
12124 more_alts
= (insn
+ 1 < past
12125 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
12126 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
12128 static char buf
[256];
12135 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
12137 gas_assert (firstinsn
);
12138 need_delay_slot_ok
= FALSE
;
12144 obstack_free (&mips_operand_tokens
, tokens
);
12149 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
12150 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
12151 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12152 else if (mips_opts
.insn32
)
12153 sprintf (buf
, _("Opcode not supported in the `insn32' mode"));
12155 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
12156 8 * forced_insn_length
);
12162 imm_expr
.X_op
= O_absent
;
12163 imm2_expr
.X_op
= O_absent
;
12164 offset_expr
.X_op
= O_absent
;
12165 offset_reloc
[0] = BFD_RELOC_UNUSED
;
12166 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12167 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12169 create_insn (ip
, insn
);
12171 memset (&arg
, 0, sizeof (arg
));
12173 arg
.token
= tokens
;
12175 arg
.last_regno
= ILLEGAL_REG
;
12176 arg
.dest_regno
= ILLEGAL_REG
;
12177 arg
.soft_match
= (more_alts
12178 || (wrong_delay_slot_insns
&& need_delay_slot_ok
));
12179 for (args
= insn
->args
;; ++args
)
12181 if (arg
.token
->type
== OT_END
)
12183 /* Handle unary instructions in which only one operand is given.
12184 The source is then the same as the destination. */
12185 if (arg
.opnum
== 1 && *args
== ',')
12193 arg
.token
= tokens
;
12198 /* Treat elided base registers as $0. */
12199 if (strcmp (args
, "(b)") == 0)
12202 /* Fail the match if there were too few operands. */
12206 /* Successful match. */
12207 if (arg
.dest_regno
== arg
.last_regno
12208 && strncmp (ip
->insn_mo
->name
, "jalr", 4) == 0)
12210 if (arg
.opnum
== 2)
12211 as_bad (_("Source and destination must be different"));
12212 else if (arg
.last_regno
== 31)
12213 as_bad (_("A destination register must be supplied"));
12215 check_completed_insn (&arg
);
12216 obstack_free (&mips_operand_tokens
, tokens
);
12220 /* Fail the match if the line has too many operands. */
12224 /* Handle characters that need to match exactly. */
12225 if (*args
== '(' || *args
== ')' || *args
== ',')
12227 if (match_char (&arg
, *args
))
12232 /* Handle special macro operands. Work out the properties of
12235 arg
.lax_max
= FALSE
;
12236 optional_reg
= FALSE
;
12255 /* If these integer forms come last, there is no other
12256 form of the instruction that could match. Prefer to
12257 give detailed error messages where possible. */
12259 arg
.soft_match
= FALSE
;
12263 /* "+I" is like "I", except that imm2_expr is used. */
12264 if (match_const_int (&arg
, &imm2_expr
.X_add_number
, 0))
12265 imm2_expr
.X_op
= O_constant
;
12267 insn_error
= _("absolute expression required");
12268 if (HAVE_32BIT_GPRS
)
12269 normalize_constant_expr (&imm2_expr
);
12274 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12304 /* If these integer forms come last, there is no other
12305 form of the instruction that could match. Prefer to
12306 give detailed error messages where possible. */
12308 arg
.soft_match
= FALSE
;
12316 /* We have already matched a comma by this point, so the register
12317 is only optional if there is another operand to come. */
12318 gas_assert (arg
.opnum
== 2);
12319 optional_reg
= (args
[1] == ',');
12323 if (match_const_int (&arg
, &imm_expr
.X_add_number
, 0))
12324 imm_expr
.X_op
= O_constant
;
12326 insn_error
= _("absolute expression required");
12327 if (HAVE_32BIT_GPRS
)
12328 normalize_constant_expr (&imm_expr
);
12332 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
12334 /* Assume that the offset has been elided and that what
12335 we saw was a base register. The match will fail later
12336 if that assumption turns out to be wrong. */
12337 offset_expr
.X_op
= O_constant
;
12338 offset_expr
.X_add_number
= 0;
12340 else if (match_expression (&arg
, &offset_expr
, offset_reloc
))
12341 normalize_address_expr (&offset_expr
);
12343 insn_error
= _("absolute expression required");
12347 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12349 insn_error
= _("floating-point expression required");
12353 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12355 insn_error
= _("floating-point expression required");
12359 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12361 insn_error
= _("floating-point expression required");
12365 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12367 insn_error
= _("floating-point expression required");
12370 /* ??? This is the traditional behavior, but is flaky if
12371 there are alternative versions of the same instruction
12372 for different subarchitectures. The next alternative
12373 might not be suitable. */
12375 /* For compatibility with older assemblers, we accept
12376 0x8000-0xffff as signed 16-bit numbers when only
12377 signed numbers are allowed. */
12378 arg
.lax_max
= !more_alts
;
12380 /* Only accept non-constant operands if this is the
12381 final alternative. Later alternatives might include
12382 a macro implementation. */
12383 arg
.allow_nonconst
= !more_alts
;
12387 /* There are no macro implementations for out-of-range values. */
12388 arg
.allow_nonconst
= TRUE
;
12392 /* There should always be a macro implementation. */
12393 arg
.allow_nonconst
= FALSE
;
12397 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12401 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12405 gas_assert (mips_opts
.micromips
);
12412 /* We have already matched a comma by this point,
12413 so the register is only optional if there is another
12414 operand to come. */
12415 gas_assert (arg
.opnum
== 2);
12416 optional_reg
= (args
[2] == ',');
12421 if (!forced_insn_length
)
12422 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12424 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12426 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12432 operand
= (mips_opts
.micromips
12433 ? decode_micromips_operand (args
)
12434 : decode_mips_operand (args
));
12439 && (arg
.token
[0].type
!= OT_REG
12440 || arg
.token
[1].type
== OT_END
))
12442 /* Assume that the register has been elided and is the
12443 same as the first operand. */
12444 arg
.token
= tokens
;
12448 if (!match_operand (&arg
, operand
))
12451 /* Skip prefixes. */
12452 if (*args
== '+' || *args
== 'm')
12457 /* Args don't match. */
12458 insn_error
= _("Illegal operands");
12464 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
12466 gas_assert (firstinsn
);
12467 need_delay_slot_ok
= FALSE
;
12472 obstack_free (&mips_operand_tokens
, tokens
);
12477 /* As for mips_ip, but used when assembling MIPS16 code.
12478 Also set forced_insn_length to the resulting instruction size in
12479 bytes if the user explicitly requested a small or extended instruction. */
12482 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
12486 struct mips_opcode
*insn
;
12487 const struct mips_operand
*operand
;
12488 const struct mips_operand
*ext_operand
;
12489 struct mips_arg_info arg
;
12490 struct mips_operand_token
*tokens
;
12491 bfd_boolean optional_reg
;
12495 forced_insn_length
= 0;
12497 for (s
= str
; ISLOWER (*s
); ++s
)
12509 if (s
[1] == 't' && s
[2] == ' ')
12512 forced_insn_length
= 2;
12516 else if (s
[1] == 'e' && s
[2] == ' ')
12519 forced_insn_length
= 4;
12523 /* Fall through. */
12525 insn_error
= _("unknown opcode");
12529 if (mips_opts
.noautoextend
&& !forced_insn_length
)
12530 forced_insn_length
= 2;
12532 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
12534 insn_error
= _("unrecognized opcode");
12538 tokens
= mips_parse_arguments (s
, 0);
12545 bfd_boolean more_alts
;
12548 gas_assert (strcmp (insn
->name
, str
) == 0);
12550 ok
= is_opcode_valid_16 (insn
);
12551 more_alts
= (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
12552 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
12564 static char buf
[100];
12566 _("Opcode not supported on this processor: %s (%s)"),
12567 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
12568 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12571 obstack_free (&mips_operand_tokens
, tokens
);
12576 create_insn (ip
, insn
);
12577 imm_expr
.X_op
= O_absent
;
12578 imm2_expr
.X_op
= O_absent
;
12579 offset_expr
.X_op
= O_absent
;
12580 offset_reloc
[0] = BFD_RELOC_UNUSED
;
12581 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12582 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12585 memset (&arg
, 0, sizeof (arg
));
12587 arg
.token
= tokens
;
12589 arg
.last_regno
= ILLEGAL_REG
;
12590 arg
.dest_regno
= ILLEGAL_REG
;
12591 arg
.soft_match
= more_alts
;
12593 for (args
= insn
->args
; 1; ++args
)
12597 if (arg
.token
->type
== OT_END
)
12601 /* Handle unary instructions in which only one operand is given.
12602 The source is then the same as the destination. */
12603 if (arg
.opnum
== 1 && *args
== ',')
12608 arg
.token
= tokens
;
12613 /* Fail the match if there were too few operands. */
12617 /* Successful match. Stuff the immediate value in now, if
12619 if (insn
->pinfo
== INSN_MACRO
)
12621 gas_assert (relax_char
== 0);
12622 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
12624 else if (relax_char
12625 && offset_expr
.X_op
== O_constant
12626 && calculate_reloc (*offset_reloc
,
12627 offset_expr
.X_add_number
,
12630 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
12631 forced_insn_length
, &ip
->insn_opcode
);
12632 offset_expr
.X_op
= O_absent
;
12633 *offset_reloc
= BFD_RELOC_UNUSED
;
12635 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
12637 if (forced_insn_length
== 2)
12638 as_bad (_("invalid unextended operand value"));
12639 forced_insn_length
= 4;
12640 ip
->insn_opcode
|= MIPS16_EXTEND
;
12642 else if (relax_char
)
12643 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
12645 check_completed_insn (&arg
);
12646 obstack_free (&mips_operand_tokens
, tokens
);
12650 /* Fail the match if the line has too many operands. */
12654 /* Handle characters that need to match exactly. */
12655 if (*args
== '(' || *args
== ')' || *args
== ',')
12657 if (match_char (&arg
, *args
))
12663 optional_reg
= FALSE
;
12669 optional_reg
= (args
[1] == ',');
12681 if (match_const_int (&arg
, &imm_expr
.X_add_number
, 0))
12682 imm_expr
.X_op
= O_constant
;
12684 insn_error
= _("absolute expression required");
12685 if (HAVE_32BIT_GPRS
)
12686 normalize_constant_expr (&imm_expr
);
12691 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
12692 ip
->insn_opcode
<<= 16;
12696 operand
= decode_mips16_operand (c
, FALSE
);
12700 /* '6' is a special case. It is used for BREAK and SDBBP,
12701 whose operands are only meaningful to the software that decodes
12702 them. This means that there is no architectural reason why
12703 they cannot be prefixed by EXTEND, but in practice,
12704 exception handlers will only look at the instruction
12705 itself. We therefore allow '6' to be extended when
12706 disassembling but not when assembling. */
12707 if (operand
->type
!= OP_PCREL
&& c
!= '6')
12709 ext_operand
= decode_mips16_operand (c
, TRUE
);
12710 if (operand
!= ext_operand
)
12712 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
12714 offset_expr
.X_op
= O_constant
;
12715 offset_expr
.X_add_number
= 0;
12720 /* We need the OT_INTEGER check because some MIPS16
12721 immediate variants are listed before the register ones. */
12722 if (arg
.token
->type
!= OT_INTEGER
12723 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
12726 /* '8' is used for SLTI(U) and has traditionally not
12727 been allowed to take relocation operators. */
12728 if (offset_reloc
[0] != BFD_RELOC_UNUSED
12729 && (ext_operand
->size
!= 16 || c
== '8'))
12738 && (arg
.token
[0].type
!= OT_REG
12739 || arg
.token
[1].type
== OT_END
))
12741 /* Assume that the register has been elided and is the
12742 same as the first operand. */
12743 arg
.token
= tokens
;
12747 if (!match_operand (&arg
, operand
))
12752 /* Args don't match. */
12759 insn_error
= _("illegal operands");
12761 obstack_free (&mips_operand_tokens
, tokens
);
12766 /* This structure holds information we know about a mips16 immediate
12769 struct mips16_immed_operand
12771 /* The type code used in the argument string in the opcode table. */
12773 /* The number of bits in the short form of the opcode. */
12775 /* The number of bits in the extended form of the opcode. */
12777 /* The amount by which the short form is shifted when it is used;
12778 for example, the sw instruction has a shift count of 2. */
12780 /* The amount by which the short form is shifted when it is stored
12781 into the instruction code. */
12783 /* Non-zero if the short form is unsigned. */
12785 /* Non-zero if the extended form is unsigned. */
12787 /* Non-zero if the value is PC relative. */
12791 /* The mips16 immediate operand types. */
12793 static const struct mips16_immed_operand mips16_immed_operands
[] =
12795 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
12796 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
12797 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
12798 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
12799 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
12800 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12801 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12802 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12803 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12804 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
12805 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
12806 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
12807 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
12808 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
12809 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
12810 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
12811 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
12812 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
12813 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
12814 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
12815 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
12818 #define MIPS16_NUM_IMMED \
12819 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
12821 /* Marshal immediate value VAL for an extended MIPS16 instruction.
12822 NBITS is the number of significant bits in VAL. */
12824 static unsigned long
12825 mips16_immed_extend (offsetT val
, unsigned int nbits
)
12830 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
12833 else if (nbits
== 15)
12835 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
12840 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
12843 return (extval
<< 16) | val
;
12846 /* Install immediate value VAL into MIPS16 instruction *INSN,
12847 extending it if necessary. The instruction in *INSN may
12848 already be extended.
12850 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
12851 if none. In the former case, VAL is a 16-bit number with no
12852 defined signedness.
12854 TYPE is the type of the immediate field. USER_INSN_LENGTH
12855 is the length that the user requested, or 0 if none. */
12858 mips16_immed (char *file
, unsigned int line
, int type
,
12859 bfd_reloc_code_real_type reloc
, offsetT val
,
12860 unsigned int user_insn_length
, unsigned long *insn
)
12862 const struct mips16_immed_operand
*op
;
12863 int mintiny
, maxtiny
;
12865 op
= mips16_immed_operands
;
12866 while (op
->type
!= type
)
12869 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12874 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12877 maxtiny
= 1 << op
->nbits
;
12882 maxtiny
= (1 << op
->nbits
) - 1;
12884 if (reloc
!= BFD_RELOC_UNUSED
)
12889 mintiny
= - (1 << (op
->nbits
- 1));
12890 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12891 if (reloc
!= BFD_RELOC_UNUSED
)
12892 val
= SEXT_16BIT (val
);
12895 /* Branch offsets have an implicit 0 in the lowest bit. */
12896 if (type
== 'p' || type
== 'q')
12899 if ((val
& ((1 << op
->shift
) - 1)) != 0
12900 || val
< (mintiny
<< op
->shift
)
12901 || val
> (maxtiny
<< op
->shift
))
12903 /* We need an extended instruction. */
12904 if (user_insn_length
== 2)
12905 as_bad_where (file
, line
, _("invalid unextended operand value"));
12907 *insn
|= MIPS16_EXTEND
;
12909 else if (user_insn_length
== 4)
12911 /* The operand doesn't force an unextended instruction to be extended.
12912 Warn if the user wanted an extended instruction anyway. */
12913 *insn
|= MIPS16_EXTEND
;
12914 as_warn_where (file
, line
,
12915 _("extended operand requested but not required"));
12918 if (mips16_opcode_length (*insn
) == 2)
12922 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
12923 insnval
<<= op
->op_shift
;
12928 long minext
, maxext
;
12930 if (reloc
== BFD_RELOC_UNUSED
)
12935 maxext
= (1 << op
->extbits
) - 1;
12939 minext
= - (1 << (op
->extbits
- 1));
12940 maxext
= (1 << (op
->extbits
- 1)) - 1;
12942 if (val
< minext
|| val
> maxext
)
12943 as_bad_where (file
, line
,
12944 _("operand value out of range for instruction"));
12947 *insn
|= mips16_immed_extend (val
, op
->extbits
);
12951 struct percent_op_match
12954 bfd_reloc_code_real_type reloc
;
12957 static const struct percent_op_match mips_percent_op
[] =
12959 {"%lo", BFD_RELOC_LO16
},
12960 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
12961 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
12962 {"%call16", BFD_RELOC_MIPS_CALL16
},
12963 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
12964 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
12965 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
12966 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
12967 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
12968 {"%got", BFD_RELOC_MIPS_GOT16
},
12969 {"%gp_rel", BFD_RELOC_GPREL16
},
12970 {"%half", BFD_RELOC_16
},
12971 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
12972 {"%higher", BFD_RELOC_MIPS_HIGHER
},
12973 {"%neg", BFD_RELOC_MIPS_SUB
},
12974 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
12975 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
12976 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
12977 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
12978 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
12979 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
12980 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
12981 {"%hi", BFD_RELOC_HI16_S
}
12984 static const struct percent_op_match mips16_percent_op
[] =
12986 {"%lo", BFD_RELOC_MIPS16_LO16
},
12987 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
12988 {"%got", BFD_RELOC_MIPS16_GOT16
},
12989 {"%call16", BFD_RELOC_MIPS16_CALL16
},
12990 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
12991 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
12992 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
12993 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
12994 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
12995 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
12996 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
12997 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13001 /* Return true if *STR points to a relocation operator. When returning true,
13002 move *STR over the operator and store its relocation code in *RELOC.
13003 Leave both *STR and *RELOC alone when returning false. */
13006 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13008 const struct percent_op_match
*percent_op
;
13011 if (mips_opts
.mips16
)
13013 percent_op
= mips16_percent_op
;
13014 limit
= ARRAY_SIZE (mips16_percent_op
);
13018 percent_op
= mips_percent_op
;
13019 limit
= ARRAY_SIZE (mips_percent_op
);
13022 for (i
= 0; i
< limit
; i
++)
13023 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13025 int len
= strlen (percent_op
[i
].str
);
13027 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13030 *str
+= strlen (percent_op
[i
].str
);
13031 *reloc
= percent_op
[i
].reloc
;
13033 /* Check whether the output BFD supports this relocation.
13034 If not, issue an error and fall back on something safe. */
13035 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13037 as_bad (_("relocation %s isn't supported by the current ABI"),
13038 percent_op
[i
].str
);
13039 *reloc
= BFD_RELOC_UNUSED
;
13047 /* Parse string STR as a 16-bit relocatable operand. Store the
13048 expression in *EP and the relocations in the array starting
13049 at RELOC. Return the number of relocation operators used.
13051 On exit, EXPR_END points to the first character after the expression. */
13054 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13057 bfd_reloc_code_real_type reversed_reloc
[3];
13058 size_t reloc_index
, i
;
13059 int crux_depth
, str_depth
;
13062 /* Search for the start of the main expression, recoding relocations
13063 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13064 of the main expression and with CRUX_DEPTH containing the number
13065 of open brackets at that point. */
13072 crux_depth
= str_depth
;
13074 /* Skip over whitespace and brackets, keeping count of the number
13076 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13081 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13082 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13084 my_getExpression (ep
, crux
);
13087 /* Match every open bracket. */
13088 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13092 if (crux_depth
> 0)
13093 as_bad (_("unclosed '('"));
13097 if (reloc_index
!= 0)
13099 prev_reloc_op_frag
= frag_now
;
13100 for (i
= 0; i
< reloc_index
; i
++)
13101 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13104 return reloc_index
;
13108 my_getExpression (expressionS
*ep
, char *str
)
13112 save_in
= input_line_pointer
;
13113 input_line_pointer
= str
;
13115 expr_end
= input_line_pointer
;
13116 input_line_pointer
= save_in
;
13120 md_atof (int type
, char *litP
, int *sizeP
)
13122 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13126 md_number_to_chars (char *buf
, valueT val
, int n
)
13128 if (target_big_endian
)
13129 number_to_chars_bigendian (buf
, val
, n
);
13131 number_to_chars_littleendian (buf
, val
, n
);
13134 static int support_64bit_objects(void)
13136 const char **list
, **l
;
13139 list
= bfd_target_list ();
13140 for (l
= list
; *l
!= NULL
; l
++)
13141 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13142 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13144 yes
= (*l
!= NULL
);
13149 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13150 NEW_VALUE. Warn if another value was already specified. Note:
13151 we have to defer parsing the -march and -mtune arguments in order
13152 to handle 'from-abi' correctly, since the ABI might be specified
13153 in a later argument. */
13156 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13158 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13159 as_warn (_("A different %s was already specified, is now %s"),
13160 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13163 *string_ptr
= new_value
;
13167 md_parse_option (int c
, char *arg
)
13171 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13172 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13174 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13175 c
== mips_ases
[i
].option_on
);
13181 case OPTION_CONSTRUCT_FLOATS
:
13182 mips_disable_float_construction
= 0;
13185 case OPTION_NO_CONSTRUCT_FLOATS
:
13186 mips_disable_float_construction
= 1;
13198 target_big_endian
= 1;
13202 target_big_endian
= 0;
13208 else if (arg
[0] == '0')
13210 else if (arg
[0] == '1')
13220 mips_debug
= atoi (arg
);
13224 file_mips_isa
= ISA_MIPS1
;
13228 file_mips_isa
= ISA_MIPS2
;
13232 file_mips_isa
= ISA_MIPS3
;
13236 file_mips_isa
= ISA_MIPS4
;
13240 file_mips_isa
= ISA_MIPS5
;
13243 case OPTION_MIPS32
:
13244 file_mips_isa
= ISA_MIPS32
;
13247 case OPTION_MIPS32R2
:
13248 file_mips_isa
= ISA_MIPS32R2
;
13251 case OPTION_MIPS64R2
:
13252 file_mips_isa
= ISA_MIPS64R2
;
13255 case OPTION_MIPS64
:
13256 file_mips_isa
= ISA_MIPS64
;
13260 mips_set_option_string (&mips_tune_string
, arg
);
13264 mips_set_option_string (&mips_arch_string
, arg
);
13268 mips_set_option_string (&mips_arch_string
, "4650");
13269 mips_set_option_string (&mips_tune_string
, "4650");
13272 case OPTION_NO_M4650
:
13276 mips_set_option_string (&mips_arch_string
, "4010");
13277 mips_set_option_string (&mips_tune_string
, "4010");
13280 case OPTION_NO_M4010
:
13284 mips_set_option_string (&mips_arch_string
, "4100");
13285 mips_set_option_string (&mips_tune_string
, "4100");
13288 case OPTION_NO_M4100
:
13292 mips_set_option_string (&mips_arch_string
, "3900");
13293 mips_set_option_string (&mips_tune_string
, "3900");
13296 case OPTION_NO_M3900
:
13299 case OPTION_MICROMIPS
:
13300 if (mips_opts
.mips16
== 1)
13302 as_bad (_("-mmicromips cannot be used with -mips16"));
13305 mips_opts
.micromips
= 1;
13306 mips_no_prev_insn ();
13309 case OPTION_NO_MICROMIPS
:
13310 mips_opts
.micromips
= 0;
13311 mips_no_prev_insn ();
13314 case OPTION_MIPS16
:
13315 if (mips_opts
.micromips
== 1)
13317 as_bad (_("-mips16 cannot be used with -micromips"));
13320 mips_opts
.mips16
= 1;
13321 mips_no_prev_insn ();
13324 case OPTION_NO_MIPS16
:
13325 mips_opts
.mips16
= 0;
13326 mips_no_prev_insn ();
13329 case OPTION_FIX_24K
:
13333 case OPTION_NO_FIX_24K
:
13337 case OPTION_FIX_LOONGSON2F_JUMP
:
13338 mips_fix_loongson2f_jump
= TRUE
;
13341 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13342 mips_fix_loongson2f_jump
= FALSE
;
13345 case OPTION_FIX_LOONGSON2F_NOP
:
13346 mips_fix_loongson2f_nop
= TRUE
;
13349 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13350 mips_fix_loongson2f_nop
= FALSE
;
13353 case OPTION_FIX_VR4120
:
13354 mips_fix_vr4120
= 1;
13357 case OPTION_NO_FIX_VR4120
:
13358 mips_fix_vr4120
= 0;
13361 case OPTION_FIX_VR4130
:
13362 mips_fix_vr4130
= 1;
13365 case OPTION_NO_FIX_VR4130
:
13366 mips_fix_vr4130
= 0;
13369 case OPTION_FIX_CN63XXP1
:
13370 mips_fix_cn63xxp1
= TRUE
;
13373 case OPTION_NO_FIX_CN63XXP1
:
13374 mips_fix_cn63xxp1
= FALSE
;
13377 case OPTION_RELAX_BRANCH
:
13378 mips_relax_branch
= 1;
13381 case OPTION_NO_RELAX_BRANCH
:
13382 mips_relax_branch
= 0;
13385 case OPTION_INSN32
:
13386 mips_opts
.insn32
= TRUE
;
13389 case OPTION_NO_INSN32
:
13390 mips_opts
.insn32
= FALSE
;
13393 case OPTION_MSHARED
:
13394 mips_in_shared
= TRUE
;
13397 case OPTION_MNO_SHARED
:
13398 mips_in_shared
= FALSE
;
13401 case OPTION_MSYM32
:
13402 mips_opts
.sym32
= TRUE
;
13405 case OPTION_MNO_SYM32
:
13406 mips_opts
.sym32
= FALSE
;
13409 /* When generating ELF code, we permit -KPIC and -call_shared to
13410 select SVR4_PIC, and -non_shared to select no PIC. This is
13411 intended to be compatible with Irix 5. */
13412 case OPTION_CALL_SHARED
:
13413 mips_pic
= SVR4_PIC
;
13414 mips_abicalls
= TRUE
;
13417 case OPTION_CALL_NONPIC
:
13419 mips_abicalls
= TRUE
;
13422 case OPTION_NON_SHARED
:
13424 mips_abicalls
= FALSE
;
13427 /* The -xgot option tells the assembler to use 32 bit offsets
13428 when accessing the got in SVR4_PIC mode. It is for Irix
13435 g_switch_value
= atoi (arg
);
13439 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13442 mips_abi
= O32_ABI
;
13446 mips_abi
= N32_ABI
;
13450 mips_abi
= N64_ABI
;
13451 if (!support_64bit_objects())
13452 as_fatal (_("No compiled in support for 64 bit object file format"));
13456 file_mips_gp32
= 1;
13460 file_mips_gp32
= 0;
13464 file_mips_fp32
= 1;
13468 file_mips_fp32
= 0;
13471 case OPTION_SINGLE_FLOAT
:
13472 file_mips_single_float
= 1;
13475 case OPTION_DOUBLE_FLOAT
:
13476 file_mips_single_float
= 0;
13479 case OPTION_SOFT_FLOAT
:
13480 file_mips_soft_float
= 1;
13483 case OPTION_HARD_FLOAT
:
13484 file_mips_soft_float
= 0;
13488 if (strcmp (arg
, "32") == 0)
13489 mips_abi
= O32_ABI
;
13490 else if (strcmp (arg
, "o64") == 0)
13491 mips_abi
= O64_ABI
;
13492 else if (strcmp (arg
, "n32") == 0)
13493 mips_abi
= N32_ABI
;
13494 else if (strcmp (arg
, "64") == 0)
13496 mips_abi
= N64_ABI
;
13497 if (! support_64bit_objects())
13498 as_fatal (_("No compiled in support for 64 bit object file "
13501 else if (strcmp (arg
, "eabi") == 0)
13502 mips_abi
= EABI_ABI
;
13505 as_fatal (_("invalid abi -mabi=%s"), arg
);
13510 case OPTION_M7000_HILO_FIX
:
13511 mips_7000_hilo_fix
= TRUE
;
13514 case OPTION_MNO_7000_HILO_FIX
:
13515 mips_7000_hilo_fix
= FALSE
;
13518 case OPTION_MDEBUG
:
13519 mips_flag_mdebug
= TRUE
;
13522 case OPTION_NO_MDEBUG
:
13523 mips_flag_mdebug
= FALSE
;
13527 mips_flag_pdr
= TRUE
;
13530 case OPTION_NO_PDR
:
13531 mips_flag_pdr
= FALSE
;
13534 case OPTION_MVXWORKS_PIC
:
13535 mips_pic
= VXWORKS_PIC
;
13539 if (strcmp (arg
, "2008") == 0)
13540 mips_flag_nan2008
= TRUE
;
13541 else if (strcmp (arg
, "legacy") == 0)
13542 mips_flag_nan2008
= FALSE
;
13545 as_fatal (_("Invalid NaN setting -mnan=%s"), arg
);
13554 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13559 /* Set up globals to generate code for the ISA or processor
13560 described by INFO. */
13563 mips_set_architecture (const struct mips_cpu_info
*info
)
13567 file_mips_arch
= info
->cpu
;
13568 mips_opts
.arch
= info
->cpu
;
13569 mips_opts
.isa
= info
->isa
;
13574 /* Likewise for tuning. */
13577 mips_set_tune (const struct mips_cpu_info
*info
)
13580 mips_tune
= info
->cpu
;
13585 mips_after_parse_args (void)
13587 const struct mips_cpu_info
*arch_info
= 0;
13588 const struct mips_cpu_info
*tune_info
= 0;
13590 /* GP relative stuff not working for PE */
13591 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13593 if (g_switch_seen
&& g_switch_value
!= 0)
13594 as_bad (_("-G not supported in this configuration."));
13595 g_switch_value
= 0;
13598 if (mips_abi
== NO_ABI
)
13599 mips_abi
= MIPS_DEFAULT_ABI
;
13601 /* The following code determines the architecture and register size.
13602 Similar code was added to GCC 3.3 (see override_options() in
13603 config/mips/mips.c). The GAS and GCC code should be kept in sync
13604 as much as possible. */
13606 if (mips_arch_string
!= 0)
13607 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13609 if (file_mips_isa
!= ISA_UNKNOWN
)
13611 /* Handle -mipsN. At this point, file_mips_isa contains the
13612 ISA level specified by -mipsN, while arch_info->isa contains
13613 the -march selection (if any). */
13614 if (arch_info
!= 0)
13616 /* -march takes precedence over -mipsN, since it is more descriptive.
13617 There's no harm in specifying both as long as the ISA levels
13619 if (file_mips_isa
!= arch_info
->isa
)
13620 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13621 mips_cpu_info_from_isa (file_mips_isa
)->name
,
13622 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13625 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
13628 if (arch_info
== 0)
13630 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13631 gas_assert (arch_info
);
13634 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13635 as_bad (_("-march=%s is not compatible with the selected ABI"),
13638 mips_set_architecture (arch_info
);
13640 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13641 if (mips_tune_string
!= 0)
13642 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13644 if (tune_info
== 0)
13645 mips_set_tune (arch_info
);
13647 mips_set_tune (tune_info
);
13649 if (file_mips_gp32
>= 0)
13651 /* The user specified the size of the integer registers. Make sure
13652 it agrees with the ABI and ISA. */
13653 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13654 as_bad (_("-mgp64 used with a 32-bit processor"));
13655 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
13656 as_bad (_("-mgp32 used with a 64-bit ABI"));
13657 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
13658 as_bad (_("-mgp64 used with a 32-bit ABI"));
13662 /* Infer the integer register size from the ABI and processor.
13663 Restrict ourselves to 32-bit registers if that's all the
13664 processor has, or if the ABI cannot handle 64-bit registers. */
13665 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
13666 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
13669 switch (file_mips_fp32
)
13673 /* No user specified float register size.
13674 ??? GAS treats single-float processors as though they had 64-bit
13675 float registers (although it complains when double-precision
13676 instructions are used). As things stand, saying they have 32-bit
13677 registers would lead to spurious "register must be even" messages.
13678 So here we assume float registers are never smaller than the
13680 if (file_mips_gp32
== 0)
13681 /* 64-bit integer registers implies 64-bit float registers. */
13682 file_mips_fp32
= 0;
13683 else if ((mips_opts
.ase
& FP64_ASES
)
13684 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13685 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13686 file_mips_fp32
= 0;
13688 /* 32-bit float registers. */
13689 file_mips_fp32
= 1;
13692 /* The user specified the size of the float registers. Check if it
13693 agrees with the ABI and ISA. */
13695 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13696 as_bad (_("-mfp64 used with a 32-bit fpu"));
13697 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
13698 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
13699 as_warn (_("-mfp64 used with a 32-bit ABI"));
13702 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13703 as_warn (_("-mfp32 used with a 64-bit ABI"));
13707 /* End of GCC-shared inference code. */
13709 /* This flag is set when we have a 64-bit capable CPU but use only
13710 32-bit wide registers. Note that EABI does not use it. */
13711 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
13712 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
13713 || mips_abi
== O32_ABI
))
13714 mips_32bitmode
= 1;
13716 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
13717 as_bad (_("trap exception not supported at ISA 1"));
13719 /* If the selected architecture includes support for ASEs, enable
13720 generation of code for them. */
13721 if (mips_opts
.mips16
== -1)
13722 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
13723 if (mips_opts
.micromips
== -1)
13724 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
13726 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13727 ASEs from being selected implicitly. */
13728 if (file_mips_fp32
== 1)
13729 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
13731 /* If the user didn't explicitly select or deselect a particular ASE,
13732 use the default setting for the CPU. */
13733 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
13735 file_mips_isa
= mips_opts
.isa
;
13736 file_ase
= mips_opts
.ase
;
13737 mips_opts
.gp32
= file_mips_gp32
;
13738 mips_opts
.fp32
= file_mips_fp32
;
13739 mips_opts
.soft_float
= file_mips_soft_float
;
13740 mips_opts
.single_float
= file_mips_single_float
;
13742 mips_check_isa_supports_ases ();
13744 if (mips_flag_mdebug
< 0)
13745 mips_flag_mdebug
= 0;
13749 mips_init_after_args (void)
13751 /* initialize opcodes */
13752 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
13753 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
13757 md_pcrel_from (fixS
*fixP
)
13759 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13760 switch (fixP
->fx_r_type
)
13762 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
13763 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
13764 /* Return the address of the delay slot. */
13767 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
13768 case BFD_RELOC_MICROMIPS_JMP
:
13769 case BFD_RELOC_16_PCREL_S2
:
13770 case BFD_RELOC_MIPS_JMP
:
13771 /* Return the address of the delay slot. */
13774 case BFD_RELOC_32_PCREL
:
13778 /* We have no relocation type for PC relative MIPS16 instructions. */
13779 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
13780 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
13781 _("PC relative MIPS16 instruction references a different section"));
13786 /* This is called before the symbol table is processed. In order to
13787 work with gcc when using mips-tfile, we must keep all local labels.
13788 However, in other cases, we want to discard them. If we were
13789 called with -g, but we didn't see any debugging information, it may
13790 mean that gcc is smuggling debugging information through to
13791 mips-tfile, in which case we must generate all local labels. */
13794 mips_frob_file_before_adjust (void)
13796 #ifndef NO_ECOFF_DEBUGGING
13797 if (ECOFF_DEBUGGING
13799 && ! ecoff_debugging_seen
)
13800 flag_keep_locals
= 1;
13804 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
13805 the corresponding LO16 reloc. This is called before md_apply_fix and
13806 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
13807 relocation operators.
13809 For our purposes, a %lo() expression matches a %got() or %hi()
13812 (a) it refers to the same symbol; and
13813 (b) the offset applied in the %lo() expression is no lower than
13814 the offset applied in the %got() or %hi().
13816 (b) allows us to cope with code like:
13819 lh $4,%lo(foo+2)($4)
13821 ...which is legal on RELA targets, and has a well-defined behaviour
13822 if the user knows that adding 2 to "foo" will not induce a carry to
13825 When several %lo()s match a particular %got() or %hi(), we use the
13826 following rules to distinguish them:
13828 (1) %lo()s with smaller offsets are a better match than %lo()s with
13831 (2) %lo()s with no matching %got() or %hi() are better than those
13832 that already have a matching %got() or %hi().
13834 (3) later %lo()s are better than earlier %lo()s.
13836 These rules are applied in order.
13838 (1) means, among other things, that %lo()s with identical offsets are
13839 chosen if they exist.
13841 (2) means that we won't associate several high-part relocations with
13842 the same low-part relocation unless there's no alternative. Having
13843 several high parts for the same low part is a GNU extension; this rule
13844 allows careful users to avoid it.
13846 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
13847 with the last high-part relocation being at the front of the list.
13848 It therefore makes sense to choose the last matching low-part
13849 relocation, all other things being equal. It's also easier
13850 to code that way. */
13853 mips_frob_file (void)
13855 struct mips_hi_fixup
*l
;
13856 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
13858 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
13860 segment_info_type
*seginfo
;
13861 bfd_boolean matched_lo_p
;
13862 fixS
**hi_pos
, **lo_pos
, **pos
;
13864 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
13866 /* If a GOT16 relocation turns out to be against a global symbol,
13867 there isn't supposed to be a matching LO. Ignore %gots against
13868 constants; we'll report an error for those later. */
13869 if (got16_reloc_p (l
->fixp
->fx_r_type
)
13870 && !(l
->fixp
->fx_addsy
13871 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
13874 /* Check quickly whether the next fixup happens to be a matching %lo. */
13875 if (fixup_has_matching_lo_p (l
->fixp
))
13878 seginfo
= seg_info (l
->seg
);
13880 /* Set HI_POS to the position of this relocation in the chain.
13881 Set LO_POS to the position of the chosen low-part relocation.
13882 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
13883 relocation that matches an immediately-preceding high-part
13887 matched_lo_p
= FALSE
;
13888 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
13890 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
13892 if (*pos
== l
->fixp
)
13895 if ((*pos
)->fx_r_type
== looking_for_rtype
13896 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
13897 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
13899 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
13901 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
13904 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
13905 && fixup_has_matching_lo_p (*pos
));
13908 /* If we found a match, remove the high-part relocation from its
13909 current position and insert it before the low-part relocation.
13910 Make the offsets match so that fixup_has_matching_lo_p()
13913 We don't warn about unmatched high-part relocations since some
13914 versions of gcc have been known to emit dead "lui ...%hi(...)"
13916 if (lo_pos
!= NULL
)
13918 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
13919 if (l
->fixp
->fx_next
!= *lo_pos
)
13921 *hi_pos
= l
->fixp
->fx_next
;
13922 l
->fixp
->fx_next
= *lo_pos
;
13930 mips_force_relocation (fixS
*fixp
)
13932 if (generic_force_reloc (fixp
))
13935 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
13936 so that the linker relaxation can update targets. */
13937 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
13938 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
13939 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
13945 /* Read the instruction associated with RELOC from BUF. */
13947 static unsigned int
13948 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
13950 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
13951 return read_compressed_insn (buf
, 4);
13953 return read_insn (buf
);
13956 /* Write instruction INSN to BUF, given that it has been relocated
13960 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
13961 unsigned long insn
)
13963 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
13964 write_compressed_insn (buf
, insn
, 4);
13966 write_insn (buf
, insn
);
13969 /* Apply a fixup to the object file. */
13972 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13975 unsigned long insn
;
13976 reloc_howto_type
*howto
;
13978 /* We ignore generic BFD relocations we don't know about. */
13979 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
13983 gas_assert (fixP
->fx_size
== 2
13984 || fixP
->fx_size
== 4
13985 || fixP
->fx_r_type
== BFD_RELOC_16
13986 || fixP
->fx_r_type
== BFD_RELOC_64
13987 || fixP
->fx_r_type
== BFD_RELOC_CTOR
13988 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
13989 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
13990 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13991 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
13992 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
13994 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
13996 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
13997 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
13998 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
13999 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
14000 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
14002 /* Don't treat parts of a composite relocation as done. There are two
14005 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14006 should nevertheless be emitted if the first part is.
14008 (2) In normal usage, composite relocations are never assembly-time
14009 constants. The easiest way of dealing with the pathological
14010 exceptions is to generate a relocation against STN_UNDEF and
14011 leave everything up to the linker. */
14012 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14015 switch (fixP
->fx_r_type
)
14017 case BFD_RELOC_MIPS_TLS_GD
:
14018 case BFD_RELOC_MIPS_TLS_LDM
:
14019 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14020 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14021 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14022 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14023 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14024 case BFD_RELOC_MIPS_TLS_TPREL32
:
14025 case BFD_RELOC_MIPS_TLS_TPREL64
:
14026 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14027 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14028 case BFD_RELOC_MICROMIPS_TLS_GD
:
14029 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14030 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14031 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14032 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14033 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14034 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14035 case BFD_RELOC_MIPS16_TLS_GD
:
14036 case BFD_RELOC_MIPS16_TLS_LDM
:
14037 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14038 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14039 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14040 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14041 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14042 if (!fixP
->fx_addsy
)
14044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14045 _("TLS relocation against a constant"));
14048 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14051 case BFD_RELOC_MIPS_JMP
:
14052 case BFD_RELOC_MIPS_SHIFT5
:
14053 case BFD_RELOC_MIPS_SHIFT6
:
14054 case BFD_RELOC_MIPS_GOT_DISP
:
14055 case BFD_RELOC_MIPS_GOT_PAGE
:
14056 case BFD_RELOC_MIPS_GOT_OFST
:
14057 case BFD_RELOC_MIPS_SUB
:
14058 case BFD_RELOC_MIPS_INSERT_A
:
14059 case BFD_RELOC_MIPS_INSERT_B
:
14060 case BFD_RELOC_MIPS_DELETE
:
14061 case BFD_RELOC_MIPS_HIGHEST
:
14062 case BFD_RELOC_MIPS_HIGHER
:
14063 case BFD_RELOC_MIPS_SCN_DISP
:
14064 case BFD_RELOC_MIPS_REL16
:
14065 case BFD_RELOC_MIPS_RELGOT
:
14066 case BFD_RELOC_MIPS_JALR
:
14067 case BFD_RELOC_HI16
:
14068 case BFD_RELOC_HI16_S
:
14069 case BFD_RELOC_LO16
:
14070 case BFD_RELOC_GPREL16
:
14071 case BFD_RELOC_MIPS_LITERAL
:
14072 case BFD_RELOC_MIPS_CALL16
:
14073 case BFD_RELOC_MIPS_GOT16
:
14074 case BFD_RELOC_GPREL32
:
14075 case BFD_RELOC_MIPS_GOT_HI16
:
14076 case BFD_RELOC_MIPS_GOT_LO16
:
14077 case BFD_RELOC_MIPS_CALL_HI16
:
14078 case BFD_RELOC_MIPS_CALL_LO16
:
14079 case BFD_RELOC_MIPS16_GPREL
:
14080 case BFD_RELOC_MIPS16_GOT16
:
14081 case BFD_RELOC_MIPS16_CALL16
:
14082 case BFD_RELOC_MIPS16_HI16
:
14083 case BFD_RELOC_MIPS16_HI16_S
:
14084 case BFD_RELOC_MIPS16_LO16
:
14085 case BFD_RELOC_MIPS16_JMP
:
14086 case BFD_RELOC_MICROMIPS_JMP
:
14087 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14088 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14089 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14090 case BFD_RELOC_MICROMIPS_SUB
:
14091 case BFD_RELOC_MICROMIPS_HIGHEST
:
14092 case BFD_RELOC_MICROMIPS_HIGHER
:
14093 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14094 case BFD_RELOC_MICROMIPS_JALR
:
14095 case BFD_RELOC_MICROMIPS_HI16
:
14096 case BFD_RELOC_MICROMIPS_HI16_S
:
14097 case BFD_RELOC_MICROMIPS_LO16
:
14098 case BFD_RELOC_MICROMIPS_GPREL16
:
14099 case BFD_RELOC_MICROMIPS_LITERAL
:
14100 case BFD_RELOC_MICROMIPS_CALL16
:
14101 case BFD_RELOC_MICROMIPS_GOT16
:
14102 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14103 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14104 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14105 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14106 case BFD_RELOC_MIPS_EH
:
14111 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14113 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14114 if (mips16_reloc_p (fixP
->fx_r_type
))
14115 insn
|= mips16_immed_extend (value
, 16);
14117 insn
|= (value
& 0xffff);
14118 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14121 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14122 _("Unsupported constant in relocation"));
14127 /* This is handled like BFD_RELOC_32, but we output a sign
14128 extended value if we are only 32 bits. */
14131 if (8 <= sizeof (valueT
))
14132 md_number_to_chars (buf
, *valP
, 8);
14137 if ((*valP
& 0x80000000) != 0)
14141 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14142 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14147 case BFD_RELOC_RVA
:
14149 case BFD_RELOC_32_PCREL
:
14151 /* If we are deleting this reloc entry, we must fill in the
14152 value now. This can happen if we have a .word which is not
14153 resolved when it appears but is later defined. */
14155 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14158 case BFD_RELOC_16_PCREL_S2
:
14159 if ((*valP
& 0x3) != 0)
14160 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14161 _("Branch to misaligned address (%lx)"), (long) *valP
);
14163 /* We need to save the bits in the instruction since fixup_segment()
14164 might be deleting the relocation entry (i.e., a branch within
14165 the current segment). */
14166 if (! fixP
->fx_done
)
14169 /* Update old instruction data. */
14170 insn
= read_insn (buf
);
14172 if (*valP
+ 0x20000 <= 0x3ffff)
14174 insn
|= (*valP
>> 2) & 0xffff;
14175 write_insn (buf
, insn
);
14177 else if (mips_pic
== NO_PIC
14179 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14180 && (fixP
->fx_frag
->fr_address
14181 < text_section
->vma
+ bfd_get_section_size (text_section
))
14182 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14183 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14184 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14186 /* The branch offset is too large. If this is an
14187 unconditional branch, and we are not generating PIC code,
14188 we can convert it to an absolute jump instruction. */
14189 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14190 insn
= 0x0c000000; /* jal */
14192 insn
= 0x08000000; /* j */
14193 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14195 fixP
->fx_addsy
= section_symbol (text_section
);
14196 *valP
+= md_pcrel_from (fixP
);
14197 write_insn (buf
, insn
);
14201 /* If we got here, we have branch-relaxation disabled,
14202 and there's nothing we can do to fix this instruction
14203 without turning it into a longer sequence. */
14204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14205 _("Branch out of range"));
14209 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14210 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14211 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14212 /* We adjust the offset back to even. */
14213 if ((*valP
& 0x1) != 0)
14216 if (! fixP
->fx_done
)
14219 /* Should never visit here, because we keep the relocation. */
14223 case BFD_RELOC_VTABLE_INHERIT
:
14226 && !S_IS_DEFINED (fixP
->fx_addsy
)
14227 && !S_IS_WEAK (fixP
->fx_addsy
))
14228 S_SET_WEAK (fixP
->fx_addsy
);
14231 case BFD_RELOC_VTABLE_ENTRY
:
14239 /* Remember value for tc_gen_reloc. */
14240 fixP
->fx_addnumber
= *valP
;
14250 name
= input_line_pointer
;
14251 c
= get_symbol_end ();
14252 p
= (symbolS
*) symbol_find_or_make (name
);
14253 *input_line_pointer
= c
;
14257 /* Align the current frag to a given power of two. If a particular
14258 fill byte should be used, FILL points to an integer that contains
14259 that byte, otherwise FILL is null.
14261 This function used to have the comment:
14263 The MIPS assembler also automatically adjusts any preceding label.
14265 The implementation therefore applied the adjustment to a maximum of
14266 one label. However, other label adjustments are applied to batches
14267 of labels, and adjusting just one caused problems when new labels
14268 were added for the sake of debugging or unwind information.
14269 We therefore adjust all preceding labels (given as LABELS) instead. */
14272 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14274 mips_emit_delays ();
14275 mips_record_compressed_mode ();
14276 if (fill
== NULL
&& subseg_text_p (now_seg
))
14277 frag_align_code (to
, 0);
14279 frag_align (to
, fill
? *fill
: 0, 0);
14280 record_alignment (now_seg
, to
);
14281 mips_move_labels (labels
, FALSE
);
14284 /* Align to a given power of two. .align 0 turns off the automatic
14285 alignment used by the data creating pseudo-ops. */
14288 s_align (int x ATTRIBUTE_UNUSED
)
14290 int temp
, fill_value
, *fill_ptr
;
14291 long max_alignment
= 28;
14293 /* o Note that the assembler pulls down any immediately preceding label
14294 to the aligned address.
14295 o It's not documented but auto alignment is reinstated by
14296 a .align pseudo instruction.
14297 o Note also that after auto alignment is turned off the mips assembler
14298 issues an error on attempt to assemble an improperly aligned data item.
14301 temp
= get_absolute_expression ();
14302 if (temp
> max_alignment
)
14303 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
14306 as_warn (_("Alignment negative: 0 assumed."));
14309 if (*input_line_pointer
== ',')
14311 ++input_line_pointer
;
14312 fill_value
= get_absolute_expression ();
14313 fill_ptr
= &fill_value
;
14319 segment_info_type
*si
= seg_info (now_seg
);
14320 struct insn_label_list
*l
= si
->label_list
;
14321 /* Auto alignment should be switched on by next section change. */
14323 mips_align (temp
, fill_ptr
, l
);
14330 demand_empty_rest_of_line ();
14334 s_change_sec (int sec
)
14338 /* The ELF backend needs to know that we are changing sections, so
14339 that .previous works correctly. We could do something like check
14340 for an obj_section_change_hook macro, but that might be confusing
14341 as it would not be appropriate to use it in the section changing
14342 functions in read.c, since obj-elf.c intercepts those. FIXME:
14343 This should be cleaner, somehow. */
14344 obj_elf_section_change_hook ();
14346 mips_emit_delays ();
14357 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14358 demand_empty_rest_of_line ();
14362 seg
= subseg_new (RDATA_SECTION_NAME
,
14363 (subsegT
) get_absolute_expression ());
14364 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14365 | SEC_READONLY
| SEC_RELOC
14367 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14368 record_alignment (seg
, 4);
14369 demand_empty_rest_of_line ();
14373 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14374 bfd_set_section_flags (stdoutput
, seg
,
14375 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14376 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14377 record_alignment (seg
, 4);
14378 demand_empty_rest_of_line ();
14382 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14383 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14384 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14385 record_alignment (seg
, 4);
14386 demand_empty_rest_of_line ();
14394 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14396 char *section_name
;
14401 int section_entry_size
;
14402 int section_alignment
;
14404 section_name
= input_line_pointer
;
14405 c
= get_symbol_end ();
14407 next_c
= *(input_line_pointer
+ 1);
14409 /* Do we have .section Name<,"flags">? */
14410 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14412 /* just after name is now '\0'. */
14413 *input_line_pointer
= c
;
14414 input_line_pointer
= section_name
;
14415 obj_elf_section (ignore
);
14418 input_line_pointer
++;
14420 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14422 section_type
= get_absolute_expression ();
14425 if (*input_line_pointer
++ == ',')
14426 section_flag
= get_absolute_expression ();
14429 if (*input_line_pointer
++ == ',')
14430 section_entry_size
= get_absolute_expression ();
14432 section_entry_size
= 0;
14433 if (*input_line_pointer
++ == ',')
14434 section_alignment
= get_absolute_expression ();
14436 section_alignment
= 0;
14437 /* FIXME: really ignore? */
14438 (void) section_alignment
;
14440 section_name
= xstrdup (section_name
);
14442 /* When using the generic form of .section (as implemented by obj-elf.c),
14443 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14444 traditionally had to fall back on the more common @progbits instead.
14446 There's nothing really harmful in this, since bfd will correct
14447 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14448 means that, for backwards compatibility, the special_section entries
14449 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14451 Even so, we shouldn't force users of the MIPS .section syntax to
14452 incorrectly label the sections as SHT_PROGBITS. The best compromise
14453 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14454 generic type-checking code. */
14455 if (section_type
== SHT_MIPS_DWARF
)
14456 section_type
= SHT_PROGBITS
;
14458 obj_elf_change_section (section_name
, section_type
, section_flag
,
14459 section_entry_size
, 0, 0, 0);
14461 if (now_seg
->name
!= section_name
)
14462 free (section_name
);
14466 mips_enable_auto_align (void)
14472 s_cons (int log_size
)
14474 segment_info_type
*si
= seg_info (now_seg
);
14475 struct insn_label_list
*l
= si
->label_list
;
14477 mips_emit_delays ();
14478 if (log_size
> 0 && auto_align
)
14479 mips_align (log_size
, 0, l
);
14480 cons (1 << log_size
);
14481 mips_clear_insn_labels ();
14485 s_float_cons (int type
)
14487 segment_info_type
*si
= seg_info (now_seg
);
14488 struct insn_label_list
*l
= si
->label_list
;
14490 mips_emit_delays ();
14495 mips_align (3, 0, l
);
14497 mips_align (2, 0, l
);
14501 mips_clear_insn_labels ();
14504 /* Handle .globl. We need to override it because on Irix 5 you are
14507 where foo is an undefined symbol, to mean that foo should be
14508 considered to be the address of a function. */
14511 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14520 name
= input_line_pointer
;
14521 c
= get_symbol_end ();
14522 symbolP
= symbol_find_or_make (name
);
14523 S_SET_EXTERNAL (symbolP
);
14525 *input_line_pointer
= c
;
14526 SKIP_WHITESPACE ();
14528 /* On Irix 5, every global symbol that is not explicitly labelled as
14529 being a function is apparently labelled as being an object. */
14532 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14533 && (*input_line_pointer
!= ','))
14538 secname
= input_line_pointer
;
14539 c
= get_symbol_end ();
14540 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14542 as_bad (_("%s: no such section"), secname
);
14543 *input_line_pointer
= c
;
14545 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14546 flag
= BSF_FUNCTION
;
14549 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14551 c
= *input_line_pointer
;
14554 input_line_pointer
++;
14555 SKIP_WHITESPACE ();
14556 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14562 demand_empty_rest_of_line ();
14566 s_option (int x ATTRIBUTE_UNUSED
)
14571 opt
= input_line_pointer
;
14572 c
= get_symbol_end ();
14576 /* FIXME: What does this mean? */
14578 else if (strncmp (opt
, "pic", 3) == 0)
14582 i
= atoi (opt
+ 3);
14587 mips_pic
= SVR4_PIC
;
14588 mips_abicalls
= TRUE
;
14591 as_bad (_(".option pic%d not supported"), i
);
14593 if (mips_pic
== SVR4_PIC
)
14595 if (g_switch_seen
&& g_switch_value
!= 0)
14596 as_warn (_("-G may not be used with SVR4 PIC code"));
14597 g_switch_value
= 0;
14598 bfd_set_gp_size (stdoutput
, 0);
14602 as_warn (_("Unrecognized option \"%s\""), opt
);
14604 *input_line_pointer
= c
;
14605 demand_empty_rest_of_line ();
14608 /* This structure is used to hold a stack of .set values. */
14610 struct mips_option_stack
14612 struct mips_option_stack
*next
;
14613 struct mips_set_options options
;
14616 static struct mips_option_stack
*mips_opts_stack
;
14618 /* Handle the .set pseudo-op. */
14621 s_mipsset (int x ATTRIBUTE_UNUSED
)
14623 char *name
= input_line_pointer
, ch
;
14624 const struct mips_ase
*ase
;
14626 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14627 ++input_line_pointer
;
14628 ch
= *input_line_pointer
;
14629 *input_line_pointer
= '\0';
14631 if (strcmp (name
, "reorder") == 0)
14633 if (mips_opts
.noreorder
)
14636 else if (strcmp (name
, "noreorder") == 0)
14638 if (!mips_opts
.noreorder
)
14639 start_noreorder ();
14641 else if (strncmp (name
, "at=", 3) == 0)
14643 char *s
= name
+ 3;
14645 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
14646 as_bad (_("Unrecognized register name `%s'"), s
);
14648 else if (strcmp (name
, "at") == 0)
14650 mips_opts
.at
= ATREG
;
14652 else if (strcmp (name
, "noat") == 0)
14654 mips_opts
.at
= ZERO
;
14656 else if (strcmp (name
, "macro") == 0)
14658 mips_opts
.warn_about_macros
= 0;
14660 else if (strcmp (name
, "nomacro") == 0)
14662 if (mips_opts
.noreorder
== 0)
14663 as_bad (_("`noreorder' must be set before `nomacro'"));
14664 mips_opts
.warn_about_macros
= 1;
14666 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
14668 mips_opts
.nomove
= 0;
14670 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
14672 mips_opts
.nomove
= 1;
14674 else if (strcmp (name
, "bopt") == 0)
14676 mips_opts
.nobopt
= 0;
14678 else if (strcmp (name
, "nobopt") == 0)
14680 mips_opts
.nobopt
= 1;
14682 else if (strcmp (name
, "gp=default") == 0)
14683 mips_opts
.gp32
= file_mips_gp32
;
14684 else if (strcmp (name
, "gp=32") == 0)
14685 mips_opts
.gp32
= 1;
14686 else if (strcmp (name
, "gp=64") == 0)
14688 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14689 as_warn (_("%s isa does not support 64-bit registers"),
14690 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14691 mips_opts
.gp32
= 0;
14693 else if (strcmp (name
, "fp=default") == 0)
14694 mips_opts
.fp32
= file_mips_fp32
;
14695 else if (strcmp (name
, "fp=32") == 0)
14696 mips_opts
.fp32
= 1;
14697 else if (strcmp (name
, "fp=64") == 0)
14699 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14700 as_warn (_("%s isa does not support 64-bit floating point registers"),
14701 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14702 mips_opts
.fp32
= 0;
14704 else if (strcmp (name
, "softfloat") == 0)
14705 mips_opts
.soft_float
= 1;
14706 else if (strcmp (name
, "hardfloat") == 0)
14707 mips_opts
.soft_float
= 0;
14708 else if (strcmp (name
, "singlefloat") == 0)
14709 mips_opts
.single_float
= 1;
14710 else if (strcmp (name
, "doublefloat") == 0)
14711 mips_opts
.single_float
= 0;
14712 else if (strcmp (name
, "mips16") == 0
14713 || strcmp (name
, "MIPS-16") == 0)
14715 if (mips_opts
.micromips
== 1)
14716 as_fatal (_("`mips16' cannot be used with `micromips'"));
14717 mips_opts
.mips16
= 1;
14719 else if (strcmp (name
, "nomips16") == 0
14720 || strcmp (name
, "noMIPS-16") == 0)
14721 mips_opts
.mips16
= 0;
14722 else if (strcmp (name
, "micromips") == 0)
14724 if (mips_opts
.mips16
== 1)
14725 as_fatal (_("`micromips' cannot be used with `mips16'"));
14726 mips_opts
.micromips
= 1;
14728 else if (strcmp (name
, "nomicromips") == 0)
14729 mips_opts
.micromips
= 0;
14730 else if (name
[0] == 'n'
14732 && (ase
= mips_lookup_ase (name
+ 2)))
14733 mips_set_ase (ase
, FALSE
);
14734 else if ((ase
= mips_lookup_ase (name
)))
14735 mips_set_ase (ase
, TRUE
);
14736 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
14740 /* Permit the user to change the ISA and architecture on the fly.
14741 Needless to say, misuse can cause serious problems. */
14742 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
14745 mips_opts
.isa
= file_mips_isa
;
14746 mips_opts
.arch
= file_mips_arch
;
14748 else if (strncmp (name
, "arch=", 5) == 0)
14750 const struct mips_cpu_info
*p
;
14752 p
= mips_parse_cpu("internal use", name
+ 5);
14754 as_bad (_("unknown architecture %s"), name
+ 5);
14757 mips_opts
.arch
= p
->cpu
;
14758 mips_opts
.isa
= p
->isa
;
14761 else if (strncmp (name
, "mips", 4) == 0)
14763 const struct mips_cpu_info
*p
;
14765 p
= mips_parse_cpu("internal use", name
);
14767 as_bad (_("unknown ISA level %s"), name
+ 4);
14770 mips_opts
.arch
= p
->cpu
;
14771 mips_opts
.isa
= p
->isa
;
14775 as_bad (_("unknown ISA or architecture %s"), name
);
14777 switch (mips_opts
.isa
)
14785 mips_opts
.gp32
= 1;
14786 mips_opts
.fp32
= 1;
14793 mips_opts
.gp32
= 0;
14794 if (mips_opts
.arch
== CPU_R5900
)
14796 mips_opts
.fp32
= 1;
14800 mips_opts
.fp32
= 0;
14804 as_bad (_("unknown ISA level %s"), name
+ 4);
14809 mips_opts
.gp32
= file_mips_gp32
;
14810 mips_opts
.fp32
= file_mips_fp32
;
14813 else if (strcmp (name
, "autoextend") == 0)
14814 mips_opts
.noautoextend
= 0;
14815 else if (strcmp (name
, "noautoextend") == 0)
14816 mips_opts
.noautoextend
= 1;
14817 else if (strcmp (name
, "insn32") == 0)
14818 mips_opts
.insn32
= TRUE
;
14819 else if (strcmp (name
, "noinsn32") == 0)
14820 mips_opts
.insn32
= FALSE
;
14821 else if (strcmp (name
, "push") == 0)
14823 struct mips_option_stack
*s
;
14825 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
14826 s
->next
= mips_opts_stack
;
14827 s
->options
= mips_opts
;
14828 mips_opts_stack
= s
;
14830 else if (strcmp (name
, "pop") == 0)
14832 struct mips_option_stack
*s
;
14834 s
= mips_opts_stack
;
14836 as_bad (_(".set pop with no .set push"));
14839 /* If we're changing the reorder mode we need to handle
14840 delay slots correctly. */
14841 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
14842 start_noreorder ();
14843 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
14846 mips_opts
= s
->options
;
14847 mips_opts_stack
= s
->next
;
14851 else if (strcmp (name
, "sym32") == 0)
14852 mips_opts
.sym32
= TRUE
;
14853 else if (strcmp (name
, "nosym32") == 0)
14854 mips_opts
.sym32
= FALSE
;
14855 else if (strchr (name
, ','))
14857 /* Generic ".set" directive; use the generic handler. */
14858 *input_line_pointer
= ch
;
14859 input_line_pointer
= name
;
14865 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
14867 mips_check_isa_supports_ases ();
14868 *input_line_pointer
= ch
;
14869 demand_empty_rest_of_line ();
14872 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
14873 .option pic2. It means to generate SVR4 PIC calls. */
14876 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
14878 mips_pic
= SVR4_PIC
;
14879 mips_abicalls
= TRUE
;
14881 if (g_switch_seen
&& g_switch_value
!= 0)
14882 as_warn (_("-G may not be used with SVR4 PIC code"));
14883 g_switch_value
= 0;
14885 bfd_set_gp_size (stdoutput
, 0);
14886 demand_empty_rest_of_line ();
14889 /* Handle the .cpload pseudo-op. This is used when generating SVR4
14890 PIC code. It sets the $gp register for the function based on the
14891 function address, which is in the register named in the argument.
14892 This uses a relocation against _gp_disp, which is handled specially
14893 by the linker. The result is:
14894 lui $gp,%hi(_gp_disp)
14895 addiu $gp,$gp,%lo(_gp_disp)
14896 addu $gp,$gp,.cpload argument
14897 The .cpload argument is normally $25 == $t9.
14899 The -mno-shared option changes this to:
14900 lui $gp,%hi(__gnu_local_gp)
14901 addiu $gp,$gp,%lo(__gnu_local_gp)
14902 and the argument is ignored. This saves an instruction, but the
14903 resulting code is not position independent; it uses an absolute
14904 address for __gnu_local_gp. Thus code assembled with -mno-shared
14905 can go into an ordinary executable, but not into a shared library. */
14908 s_cpload (int ignore ATTRIBUTE_UNUSED
)
14914 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
14915 .cpload is ignored. */
14916 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
14922 if (mips_opts
.mips16
)
14924 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
14925 ignore_rest_of_line ();
14929 /* .cpload should be in a .set noreorder section. */
14930 if (mips_opts
.noreorder
== 0)
14931 as_warn (_(".cpload not in noreorder section"));
14933 reg
= tc_get_register (0);
14935 /* If we need to produce a 64-bit address, we are better off using
14936 the default instruction sequence. */
14937 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
14939 ex
.X_op
= O_symbol
;
14940 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
14942 ex
.X_op_symbol
= NULL
;
14943 ex
.X_add_number
= 0;
14945 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
14946 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
14948 mips_mark_labels ();
14949 mips_assembling_insn
= TRUE
;
14952 macro_build_lui (&ex
, mips_gp_register
);
14953 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
14954 mips_gp_register
, BFD_RELOC_LO16
);
14956 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
14957 mips_gp_register
, reg
);
14960 mips_assembling_insn
= FALSE
;
14961 demand_empty_rest_of_line ();
14964 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
14965 .cpsetup $reg1, offset|$reg2, label
14967 If offset is given, this results in:
14968 sd $gp, offset($sp)
14969 lui $gp, %hi(%neg(%gp_rel(label)))
14970 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14971 daddu $gp, $gp, $reg1
14973 If $reg2 is given, this results in:
14974 daddu $reg2, $gp, $0
14975 lui $gp, %hi(%neg(%gp_rel(label)))
14976 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14977 daddu $gp, $gp, $reg1
14978 $reg1 is normally $25 == $t9.
14980 The -mno-shared option replaces the last three instructions with
14982 addiu $gp,$gp,%lo(_gp) */
14985 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
14987 expressionS ex_off
;
14988 expressionS ex_sym
;
14991 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
14992 We also need NewABI support. */
14993 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
14999 if (mips_opts
.mips16
)
15001 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15002 ignore_rest_of_line ();
15006 reg1
= tc_get_register (0);
15007 SKIP_WHITESPACE ();
15008 if (*input_line_pointer
!= ',')
15010 as_bad (_("missing argument separator ',' for .cpsetup"));
15014 ++input_line_pointer
;
15015 SKIP_WHITESPACE ();
15016 if (*input_line_pointer
== '$')
15018 mips_cpreturn_register
= tc_get_register (0);
15019 mips_cpreturn_offset
= -1;
15023 mips_cpreturn_offset
= get_absolute_expression ();
15024 mips_cpreturn_register
= -1;
15026 SKIP_WHITESPACE ();
15027 if (*input_line_pointer
!= ',')
15029 as_bad (_("missing argument separator ',' for .cpsetup"));
15033 ++input_line_pointer
;
15034 SKIP_WHITESPACE ();
15035 expression (&ex_sym
);
15037 mips_mark_labels ();
15038 mips_assembling_insn
= TRUE
;
15041 if (mips_cpreturn_register
== -1)
15043 ex_off
.X_op
= O_constant
;
15044 ex_off
.X_add_symbol
= NULL
;
15045 ex_off
.X_op_symbol
= NULL
;
15046 ex_off
.X_add_number
= mips_cpreturn_offset
;
15048 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15049 BFD_RELOC_LO16
, SP
);
15052 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15053 mips_gp_register
, 0);
15055 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15057 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15058 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15061 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15062 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15063 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15065 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15066 mips_gp_register
, reg1
);
15072 ex
.X_op
= O_symbol
;
15073 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15074 ex
.X_op_symbol
= NULL
;
15075 ex
.X_add_number
= 0;
15077 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15078 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15080 macro_build_lui (&ex
, mips_gp_register
);
15081 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15082 mips_gp_register
, BFD_RELOC_LO16
);
15087 mips_assembling_insn
= FALSE
;
15088 demand_empty_rest_of_line ();
15092 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15094 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15095 .cplocal is ignored. */
15096 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15102 if (mips_opts
.mips16
)
15104 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15105 ignore_rest_of_line ();
15109 mips_gp_register
= tc_get_register (0);
15110 demand_empty_rest_of_line ();
15113 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15114 offset from $sp. The offset is remembered, and after making a PIC
15115 call $gp is restored from that location. */
15118 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15122 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15123 .cprestore is ignored. */
15124 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15130 if (mips_opts
.mips16
)
15132 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15133 ignore_rest_of_line ();
15137 mips_cprestore_offset
= get_absolute_expression ();
15138 mips_cprestore_valid
= 1;
15140 ex
.X_op
= O_constant
;
15141 ex
.X_add_symbol
= NULL
;
15142 ex
.X_op_symbol
= NULL
;
15143 ex
.X_add_number
= mips_cprestore_offset
;
15145 mips_mark_labels ();
15146 mips_assembling_insn
= TRUE
;
15149 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15150 SP
, HAVE_64BIT_ADDRESSES
);
15153 mips_assembling_insn
= FALSE
;
15154 demand_empty_rest_of_line ();
15157 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15158 was given in the preceding .cpsetup, it results in:
15159 ld $gp, offset($sp)
15161 If a register $reg2 was given there, it results in:
15162 daddu $gp, $reg2, $0 */
15165 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15169 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15170 We also need NewABI support. */
15171 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15177 if (mips_opts
.mips16
)
15179 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15180 ignore_rest_of_line ();
15184 mips_mark_labels ();
15185 mips_assembling_insn
= TRUE
;
15188 if (mips_cpreturn_register
== -1)
15190 ex
.X_op
= O_constant
;
15191 ex
.X_add_symbol
= NULL
;
15192 ex
.X_op_symbol
= NULL
;
15193 ex
.X_add_number
= mips_cpreturn_offset
;
15195 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15198 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15199 mips_cpreturn_register
, 0);
15202 mips_assembling_insn
= FALSE
;
15203 demand_empty_rest_of_line ();
15206 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15207 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15208 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15209 debug information or MIPS16 TLS. */
15212 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15213 bfd_reloc_code_real_type rtype
)
15220 if (ex
.X_op
!= O_symbol
)
15222 as_bad (_("Unsupported use of %s"), dirstr
);
15223 ignore_rest_of_line ();
15226 p
= frag_more (bytes
);
15227 md_number_to_chars (p
, 0, bytes
);
15228 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15229 demand_empty_rest_of_line ();
15230 mips_clear_insn_labels ();
15233 /* Handle .dtprelword. */
15236 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15238 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15241 /* Handle .dtpreldword. */
15244 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15246 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15249 /* Handle .tprelword. */
15252 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15254 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15257 /* Handle .tpreldword. */
15260 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15262 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15265 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15266 code. It sets the offset to use in gp_rel relocations. */
15269 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15271 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15272 We also need NewABI support. */
15273 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15279 mips_gprel_offset
= get_absolute_expression ();
15281 demand_empty_rest_of_line ();
15284 /* Handle the .gpword pseudo-op. This is used when generating PIC
15285 code. It generates a 32 bit GP relative reloc. */
15288 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15290 segment_info_type
*si
;
15291 struct insn_label_list
*l
;
15295 /* When not generating PIC code, this is treated as .word. */
15296 if (mips_pic
!= SVR4_PIC
)
15302 si
= seg_info (now_seg
);
15303 l
= si
->label_list
;
15304 mips_emit_delays ();
15306 mips_align (2, 0, l
);
15309 mips_clear_insn_labels ();
15311 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15313 as_bad (_("Unsupported use of .gpword"));
15314 ignore_rest_of_line ();
15318 md_number_to_chars (p
, 0, 4);
15319 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15320 BFD_RELOC_GPREL32
);
15322 demand_empty_rest_of_line ();
15326 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15328 segment_info_type
*si
;
15329 struct insn_label_list
*l
;
15333 /* When not generating PIC code, this is treated as .dword. */
15334 if (mips_pic
!= SVR4_PIC
)
15340 si
= seg_info (now_seg
);
15341 l
= si
->label_list
;
15342 mips_emit_delays ();
15344 mips_align (3, 0, l
);
15347 mips_clear_insn_labels ();
15349 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15351 as_bad (_("Unsupported use of .gpdword"));
15352 ignore_rest_of_line ();
15356 md_number_to_chars (p
, 0, 8);
15357 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15358 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15360 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15361 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15362 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15364 demand_empty_rest_of_line ();
15367 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15368 tables. It generates a R_MIPS_EH reloc. */
15371 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15376 mips_emit_delays ();
15379 mips_clear_insn_labels ();
15381 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15383 as_bad (_("Unsupported use of .ehword"));
15384 ignore_rest_of_line ();
15388 md_number_to_chars (p
, 0, 4);
15389 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15390 BFD_RELOC_MIPS_EH
);
15392 demand_empty_rest_of_line ();
15395 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15396 tables in SVR4 PIC code. */
15399 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15403 /* This is ignored when not generating SVR4 PIC code. */
15404 if (mips_pic
!= SVR4_PIC
)
15410 mips_mark_labels ();
15411 mips_assembling_insn
= TRUE
;
15413 /* Add $gp to the register named as an argument. */
15415 reg
= tc_get_register (0);
15416 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15419 mips_assembling_insn
= FALSE
;
15420 demand_empty_rest_of_line ();
15423 /* Handle the .insn pseudo-op. This marks instruction labels in
15424 mips16/micromips mode. This permits the linker to handle them specially,
15425 such as generating jalx instructions when needed. We also make
15426 them odd for the duration of the assembly, in order to generate the
15427 right sort of code. We will make them even in the adjust_symtab
15428 routine, while leaving them marked. This is convenient for the
15429 debugger and the disassembler. The linker knows to make them odd
15433 s_insn (int ignore ATTRIBUTE_UNUSED
)
15435 mips_mark_labels ();
15437 demand_empty_rest_of_line ();
15440 /* Handle the .nan pseudo-op. */
15443 s_nan (int ignore ATTRIBUTE_UNUSED
)
15445 static const char str_legacy
[] = "legacy";
15446 static const char str_2008
[] = "2008";
15449 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15451 if (i
== sizeof (str_2008
) - 1
15452 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15453 mips_flag_nan2008
= TRUE
;
15454 else if (i
== sizeof (str_legacy
) - 1
15455 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15456 mips_flag_nan2008
= FALSE
;
15458 as_bad (_("Bad .nan directive"));
15460 input_line_pointer
+= i
;
15461 demand_empty_rest_of_line ();
15464 /* Handle a .stab[snd] directive. Ideally these directives would be
15465 implemented in a transparent way, so that removing them would not
15466 have any effect on the generated instructions. However, s_stab
15467 internally changes the section, so in practice we need to decide
15468 now whether the preceding label marks compressed code. We do not
15469 support changing the compression mode of a label after a .stab*
15470 directive, such as in:
15476 so the current mode wins. */
15479 s_mips_stab (int type
)
15481 mips_mark_labels ();
15485 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15488 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15495 name
= input_line_pointer
;
15496 c
= get_symbol_end ();
15497 symbolP
= symbol_find_or_make (name
);
15498 S_SET_WEAK (symbolP
);
15499 *input_line_pointer
= c
;
15501 SKIP_WHITESPACE ();
15503 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15505 if (S_IS_DEFINED (symbolP
))
15507 as_bad (_("ignoring attempt to redefine symbol %s"),
15508 S_GET_NAME (symbolP
));
15509 ignore_rest_of_line ();
15513 if (*input_line_pointer
== ',')
15515 ++input_line_pointer
;
15516 SKIP_WHITESPACE ();
15520 if (exp
.X_op
!= O_symbol
)
15522 as_bad (_("bad .weakext directive"));
15523 ignore_rest_of_line ();
15526 symbol_set_value_expression (symbolP
, &exp
);
15529 demand_empty_rest_of_line ();
15532 /* Parse a register string into a number. Called from the ECOFF code
15533 to parse .frame. The argument is non-zero if this is the frame
15534 register, so that we can record it in mips_frame_reg. */
15537 tc_get_register (int frame
)
15541 SKIP_WHITESPACE ();
15542 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15546 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15547 mips_frame_reg_valid
= 1;
15548 mips_cprestore_valid
= 0;
15554 md_section_align (asection
*seg
, valueT addr
)
15556 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15558 /* We don't need to align ELF sections to the full alignment.
15559 However, Irix 5 may prefer that we align them at least to a 16
15560 byte boundary. We don't bother to align the sections if we
15561 are targeted for an embedded system. */
15562 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15567 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15570 /* Utility routine, called from above as well. If called while the
15571 input file is still being read, it's only an approximation. (For
15572 example, a symbol may later become defined which appeared to be
15573 undefined earlier.) */
15576 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15581 if (g_switch_value
> 0)
15583 const char *symname
;
15586 /* Find out whether this symbol can be referenced off the $gp
15587 register. It can be if it is smaller than the -G size or if
15588 it is in the .sdata or .sbss section. Certain symbols can
15589 not be referenced off the $gp, although it appears as though
15591 symname
= S_GET_NAME (sym
);
15592 if (symname
!= (const char *) NULL
15593 && (strcmp (symname
, "eprol") == 0
15594 || strcmp (symname
, "etext") == 0
15595 || strcmp (symname
, "_gp") == 0
15596 || strcmp (symname
, "edata") == 0
15597 || strcmp (symname
, "_fbss") == 0
15598 || strcmp (symname
, "_fdata") == 0
15599 || strcmp (symname
, "_ftext") == 0
15600 || strcmp (symname
, "end") == 0
15601 || strcmp (symname
, "_gp_disp") == 0))
15603 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15605 #ifndef NO_ECOFF_DEBUGGING
15606 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15607 && (symbol_get_obj (sym
)->ecoff_extern_size
15608 <= g_switch_value
))
15610 /* We must defer this decision until after the whole
15611 file has been read, since there might be a .extern
15612 after the first use of this symbol. */
15613 || (before_relaxing
15614 #ifndef NO_ECOFF_DEBUGGING
15615 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15617 && S_GET_VALUE (sym
) == 0)
15618 || (S_GET_VALUE (sym
) != 0
15619 && S_GET_VALUE (sym
) <= g_switch_value
)))
15623 const char *segname
;
15625 segname
= segment_name (S_GET_SEGMENT (sym
));
15626 gas_assert (strcmp (segname
, ".lit8") != 0
15627 && strcmp (segname
, ".lit4") != 0);
15628 change
= (strcmp (segname
, ".sdata") != 0
15629 && strcmp (segname
, ".sbss") != 0
15630 && strncmp (segname
, ".sdata.", 7) != 0
15631 && strncmp (segname
, ".sbss.", 6) != 0
15632 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
15633 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
15638 /* We are not optimizing for the $gp register. */
15643 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15646 pic_need_relax (symbolS
*sym
, asection
*segtype
)
15650 /* Handle the case of a symbol equated to another symbol. */
15651 while (symbol_equated_reloc_p (sym
))
15655 /* It's possible to get a loop here in a badly written program. */
15656 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
15662 if (symbol_section_p (sym
))
15665 symsec
= S_GET_SEGMENT (sym
);
15667 /* This must duplicate the test in adjust_reloc_syms. */
15668 return (!bfd_is_und_section (symsec
)
15669 && !bfd_is_abs_section (symsec
)
15670 && !bfd_is_com_section (symsec
)
15671 && !s_is_linkonce (sym
, segtype
)
15672 /* A global or weak symbol is treated as external. */
15673 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
15677 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15678 extended opcode. SEC is the section the frag is in. */
15681 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
15684 const struct mips16_immed_operand
*op
;
15686 int mintiny
, maxtiny
;
15690 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
15692 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
15695 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
15696 op
= mips16_immed_operands
;
15697 while (op
->type
!= type
)
15700 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
15705 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
15708 maxtiny
= 1 << op
->nbits
;
15713 maxtiny
= (1 << op
->nbits
) - 1;
15718 mintiny
= - (1 << (op
->nbits
- 1));
15719 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
15722 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
15723 val
= S_GET_VALUE (fragp
->fr_symbol
);
15724 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
15730 /* We won't have the section when we are called from
15731 mips_relax_frag. However, we will always have been called
15732 from md_estimate_size_before_relax first. If this is a
15733 branch to a different section, we mark it as such. If SEC is
15734 NULL, and the frag is not marked, then it must be a branch to
15735 the same section. */
15738 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
15743 /* Must have been called from md_estimate_size_before_relax. */
15746 fragp
->fr_subtype
=
15747 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15749 /* FIXME: We should support this, and let the linker
15750 catch branches and loads that are out of range. */
15751 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
15752 _("unsupported PC relative reference to different section"));
15756 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
15757 /* Assume non-extended on the first relaxation pass.
15758 The address we have calculated will be bogus if this is
15759 a forward branch to another frag, as the forward frag
15760 will have fr_address == 0. */
15764 /* In this case, we know for sure that the symbol fragment is in
15765 the same section. If the relax_marker of the symbol fragment
15766 differs from the relax_marker of this fragment, we have not
15767 yet adjusted the symbol fragment fr_address. We want to add
15768 in STRETCH in order to get a better estimate of the address.
15769 This particularly matters because of the shift bits. */
15771 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
15775 /* Adjust stretch for any alignment frag. Note that if have
15776 been expanding the earlier code, the symbol may be
15777 defined in what appears to be an earlier frag. FIXME:
15778 This doesn't handle the fr_subtype field, which specifies
15779 a maximum number of bytes to skip when doing an
15781 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
15783 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
15786 stretch
= - ((- stretch
)
15787 & ~ ((1 << (int) f
->fr_offset
) - 1));
15789 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
15798 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
15800 /* The base address rules are complicated. The base address of
15801 a branch is the following instruction. The base address of a
15802 PC relative load or add is the instruction itself, but if it
15803 is in a delay slot (in which case it can not be extended) use
15804 the address of the instruction whose delay slot it is in. */
15805 if (type
== 'p' || type
== 'q')
15809 /* If we are currently assuming that this frag should be
15810 extended, then, the current address is two bytes
15812 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
15815 /* Ignore the low bit in the target, since it will be set
15816 for a text label. */
15817 if ((val
& 1) != 0)
15820 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
15822 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
15825 val
-= addr
& ~ ((1 << op
->shift
) - 1);
15827 /* Branch offsets have an implicit 0 in the lowest bit. */
15828 if (type
== 'p' || type
== 'q')
15831 /* If any of the shifted bits are set, we must use an extended
15832 opcode. If the address depends on the size of this
15833 instruction, this can lead to a loop, so we arrange to always
15834 use an extended opcode. We only check this when we are in
15835 the main relaxation loop, when SEC is NULL. */
15836 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
15838 fragp
->fr_subtype
=
15839 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15843 /* If we are about to mark a frag as extended because the value
15844 is precisely maxtiny + 1, then there is a chance of an
15845 infinite loop as in the following code:
15850 In this case when the la is extended, foo is 0x3fc bytes
15851 away, so the la can be shrunk, but then foo is 0x400 away, so
15852 the la must be extended. To avoid this loop, we mark the
15853 frag as extended if it was small, and is about to become
15854 extended with a value of maxtiny + 1. */
15855 if (val
== ((maxtiny
+ 1) << op
->shift
)
15856 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
15859 fragp
->fr_subtype
=
15860 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15864 else if (symsec
!= absolute_section
&& sec
!= NULL
)
15865 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
15867 if ((val
& ((1 << op
->shift
) - 1)) != 0
15868 || val
< (mintiny
<< op
->shift
)
15869 || val
> (maxtiny
<< op
->shift
))
15875 /* Compute the length of a branch sequence, and adjust the
15876 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
15877 worst-case length is computed, with UPDATE being used to indicate
15878 whether an unconditional (-1), branch-likely (+1) or regular (0)
15879 branch is to be computed. */
15881 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
15883 bfd_boolean toofar
;
15887 && S_IS_DEFINED (fragp
->fr_symbol
)
15888 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
15893 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
15895 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
15899 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
15902 /* If the symbol is not defined or it's in a different segment,
15903 assume the user knows what's going on and emit a short
15909 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
15911 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
15912 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
15913 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
15914 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
15920 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
15923 if (mips_pic
!= NO_PIC
)
15925 /* Additional space for PIC loading of target address. */
15927 if (mips_opts
.isa
== ISA_MIPS1
)
15928 /* Additional space for $at-stabilizing nop. */
15932 /* If branch is conditional. */
15933 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
15940 /* Compute the length of a branch sequence, and adjust the
15941 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
15942 worst-case length is computed, with UPDATE being used to indicate
15943 whether an unconditional (-1), or regular (0) branch is to be
15947 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
15949 bfd_boolean toofar
;
15953 && S_IS_DEFINED (fragp
->fr_symbol
)
15954 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
15959 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
15960 /* Ignore the low bit in the target, since it will be set
15961 for a text label. */
15962 if ((val
& 1) != 0)
15965 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
15969 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
15972 /* If the symbol is not defined or it's in a different segment,
15973 assume the user knows what's going on and emit a short
15979 if (fragp
&& update
15980 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
15981 fragp
->fr_subtype
= (toofar
15982 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
15983 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
15988 bfd_boolean compact_known
= fragp
!= NULL
;
15989 bfd_boolean compact
= FALSE
;
15990 bfd_boolean uncond
;
15993 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
15995 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
15997 uncond
= update
< 0;
15999 /* If label is out of range, we turn branch <br>:
16001 <br> label # 4 bytes
16007 nop # 2 bytes if compact && !PIC
16010 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16013 /* If assembling PIC code, we further turn:
16019 lw/ld at, %got(label)(gp) # 4 bytes
16020 d/addiu at, %lo(label) # 4 bytes
16023 if (mips_pic
!= NO_PIC
)
16026 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16028 <brneg> 0f # 4 bytes
16029 nop # 2 bytes if !compact
16032 length
+= (compact_known
&& compact
) ? 4 : 6;
16038 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16039 bit accordingly. */
16042 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16044 bfd_boolean toofar
;
16047 && S_IS_DEFINED (fragp
->fr_symbol
)
16048 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16054 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16055 /* Ignore the low bit in the target, since it will be set
16056 for a text label. */
16057 if ((val
& 1) != 0)
16060 /* Assume this is a 2-byte branch. */
16061 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16063 /* We try to avoid the infinite loop by not adding 2 more bytes for
16068 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16070 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16071 else if (type
== 'E')
16072 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16077 /* If the symbol is not defined or it's in a different segment,
16078 we emit a normal 32-bit branch. */
16081 if (fragp
&& update
16082 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16084 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16085 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16093 /* Estimate the size of a frag before relaxing. Unless this is the
16094 mips16, we are not really relaxing here, and the final size is
16095 encoded in the subtype information. For the mips16, we have to
16096 decide whether we are using an extended opcode or not. */
16099 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16103 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16106 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16108 return fragp
->fr_var
;
16111 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16112 /* We don't want to modify the EXTENDED bit here; it might get us
16113 into infinite loops. We change it only in mips_relax_frag(). */
16114 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16116 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16120 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16121 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16122 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16123 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16124 fragp
->fr_var
= length
;
16129 if (mips_pic
== NO_PIC
)
16130 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16131 else if (mips_pic
== SVR4_PIC
)
16132 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16133 else if (mips_pic
== VXWORKS_PIC
)
16134 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16141 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16142 return -RELAX_FIRST (fragp
->fr_subtype
);
16145 return -RELAX_SECOND (fragp
->fr_subtype
);
16148 /* This is called to see whether a reloc against a defined symbol
16149 should be converted into a reloc against a section. */
16152 mips_fix_adjustable (fixS
*fixp
)
16154 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16155 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16158 if (fixp
->fx_addsy
== NULL
)
16161 /* If symbol SYM is in a mergeable section, relocations of the form
16162 SYM + 0 can usually be made section-relative. The mergeable data
16163 is then identified by the section offset rather than by the symbol.
16165 However, if we're generating REL LO16 relocations, the offset is split
16166 between the LO16 and parterning high part relocation. The linker will
16167 need to recalculate the complete offset in order to correctly identify
16170 The linker has traditionally not looked for the parterning high part
16171 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16172 placed anywhere. Rather than break backwards compatibility by changing
16173 this, it seems better not to force the issue, and instead keep the
16174 original symbol. This will work with either linker behavior. */
16175 if ((lo16_reloc_p (fixp
->fx_r_type
)
16176 || reloc_needs_lo_p (fixp
->fx_r_type
))
16177 && HAVE_IN_PLACE_ADDENDS
16178 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16181 /* There is no place to store an in-place offset for JALR relocations.
16182 Likewise an in-range offset of limited PC-relative relocations may
16183 overflow the in-place relocatable field if recalculated against the
16184 start address of the symbol's containing section. */
16185 if (HAVE_IN_PLACE_ADDENDS
16186 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16187 || jalr_reloc_p (fixp
->fx_r_type
)))
16190 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16191 to a floating-point stub. The same is true for non-R_MIPS16_26
16192 relocations against MIPS16 functions; in this case, the stub becomes
16193 the function's canonical address.
16195 Floating-point stubs are stored in unique .mips16.call.* or
16196 .mips16.fn.* sections. If a stub T for function F is in section S,
16197 the first relocation in section S must be against F; this is how the
16198 linker determines the target function. All relocations that might
16199 resolve to T must also be against F. We therefore have the following
16200 restrictions, which are given in an intentionally-redundant way:
16202 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16205 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16206 if that stub might be used.
16208 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16211 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16212 that stub might be used.
16214 There is a further restriction:
16216 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16217 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16218 targets with in-place addends; the relocation field cannot
16219 encode the low bit.
16221 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16222 against a MIPS16 symbol. We deal with (5) by by not reducing any
16223 such relocations on REL targets.
16225 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16226 relocation against some symbol R, no relocation against R may be
16227 reduced. (Note that this deals with (2) as well as (1) because
16228 relocations against global symbols will never be reduced on ELF
16229 targets.) This approach is a little simpler than trying to detect
16230 stub sections, and gives the "all or nothing" per-symbol consistency
16231 that we have for MIPS16 symbols. */
16232 if (fixp
->fx_subsy
== NULL
16233 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16234 || *symbol_get_tc (fixp
->fx_addsy
)
16235 || (HAVE_IN_PLACE_ADDENDS
16236 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16237 && jmp_reloc_p (fixp
->fx_r_type
))))
16243 /* Translate internal representation of relocation info to BFD target
16247 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16249 static arelent
*retval
[4];
16251 bfd_reloc_code_real_type code
;
16253 memset (retval
, 0, sizeof(retval
));
16254 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16255 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16256 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16257 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16259 if (fixp
->fx_pcrel
)
16261 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16262 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16263 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16264 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16265 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16267 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16268 Relocations want only the symbol offset. */
16269 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16272 reloc
->addend
= fixp
->fx_addnumber
;
16274 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16275 entry to be used in the relocation's section offset. */
16276 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16278 reloc
->address
= reloc
->addend
;
16282 code
= fixp
->fx_r_type
;
16284 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16285 if (reloc
->howto
== NULL
)
16287 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16288 _("Can not represent %s relocation in this object file format"),
16289 bfd_get_reloc_code_name (code
));
16296 /* Relax a machine dependent frag. This returns the amount by which
16297 the current size of the frag should change. */
16300 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16302 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16304 offsetT old_var
= fragp
->fr_var
;
16306 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16308 return fragp
->fr_var
- old_var
;
16311 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16313 offsetT old_var
= fragp
->fr_var
;
16314 offsetT new_var
= 4;
16316 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16317 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16318 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16319 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16320 fragp
->fr_var
= new_var
;
16322 return new_var
- old_var
;
16325 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16328 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16330 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16332 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16337 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16339 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16346 /* Convert a machine dependent frag. */
16349 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16351 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16354 unsigned long insn
;
16358 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16359 insn
= read_insn (buf
);
16361 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16363 /* We generate a fixup instead of applying it right now
16364 because, if there are linker relaxations, we're going to
16365 need the relocations. */
16366 exp
.X_op
= O_symbol
;
16367 exp
.X_add_symbol
= fragp
->fr_symbol
;
16368 exp
.X_add_number
= fragp
->fr_offset
;
16370 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16371 BFD_RELOC_16_PCREL_S2
);
16372 fixp
->fx_file
= fragp
->fr_file
;
16373 fixp
->fx_line
= fragp
->fr_line
;
16375 buf
= write_insn (buf
, insn
);
16381 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16382 _("Relaxed out-of-range branch into a jump"));
16384 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16387 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16389 /* Reverse the branch. */
16390 switch ((insn
>> 28) & 0xf)
16393 /* bc[0-3][tf]l? instructions can have the condition
16394 reversed by tweaking a single TF bit, and their
16395 opcodes all have 0x4???????. */
16396 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16397 insn
^= 0x00010000;
16401 /* bltz 0x04000000 bgez 0x04010000
16402 bltzal 0x04100000 bgezal 0x04110000 */
16403 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16404 insn
^= 0x00010000;
16408 /* beq 0x10000000 bne 0x14000000
16409 blez 0x18000000 bgtz 0x1c000000 */
16410 insn
^= 0x04000000;
16418 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16420 /* Clear the and-link bit. */
16421 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16423 /* bltzal 0x04100000 bgezal 0x04110000
16424 bltzall 0x04120000 bgezall 0x04130000 */
16425 insn
&= ~0x00100000;
16428 /* Branch over the branch (if the branch was likely) or the
16429 full jump (not likely case). Compute the offset from the
16430 current instruction to branch to. */
16431 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16435 /* How many bytes in instructions we've already emitted? */
16436 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16437 /* How many bytes in instructions from here to the end? */
16438 i
= fragp
->fr_var
- i
;
16440 /* Convert to instruction count. */
16442 /* Branch counts from the next instruction. */
16445 /* Branch over the jump. */
16446 buf
= write_insn (buf
, insn
);
16449 buf
= write_insn (buf
, 0);
16451 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16453 /* beql $0, $0, 2f */
16455 /* Compute the PC offset from the current instruction to
16456 the end of the variable frag. */
16457 /* How many bytes in instructions we've already emitted? */
16458 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16459 /* How many bytes in instructions from here to the end? */
16460 i
= fragp
->fr_var
- i
;
16461 /* Convert to instruction count. */
16463 /* Don't decrement i, because we want to branch over the
16467 buf
= write_insn (buf
, insn
);
16468 buf
= write_insn (buf
, 0);
16472 if (mips_pic
== NO_PIC
)
16475 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16476 ? 0x0c000000 : 0x08000000);
16477 exp
.X_op
= O_symbol
;
16478 exp
.X_add_symbol
= fragp
->fr_symbol
;
16479 exp
.X_add_number
= fragp
->fr_offset
;
16481 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16482 FALSE
, BFD_RELOC_MIPS_JMP
);
16483 fixp
->fx_file
= fragp
->fr_file
;
16484 fixp
->fx_line
= fragp
->fr_line
;
16486 buf
= write_insn (buf
, insn
);
16490 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16492 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16493 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16494 insn
|= at
<< OP_SH_RT
;
16495 exp
.X_op
= O_symbol
;
16496 exp
.X_add_symbol
= fragp
->fr_symbol
;
16497 exp
.X_add_number
= fragp
->fr_offset
;
16499 if (fragp
->fr_offset
)
16501 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16502 exp
.X_add_number
= 0;
16505 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16506 FALSE
, BFD_RELOC_MIPS_GOT16
);
16507 fixp
->fx_file
= fragp
->fr_file
;
16508 fixp
->fx_line
= fragp
->fr_line
;
16510 buf
= write_insn (buf
, insn
);
16512 if (mips_opts
.isa
== ISA_MIPS1
)
16514 buf
= write_insn (buf
, 0);
16516 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16517 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16518 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16520 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16521 FALSE
, BFD_RELOC_LO16
);
16522 fixp
->fx_file
= fragp
->fr_file
;
16523 fixp
->fx_line
= fragp
->fr_line
;
16525 buf
= write_insn (buf
, insn
);
16528 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16532 insn
|= at
<< OP_SH_RS
;
16534 buf
= write_insn (buf
, insn
);
16538 fragp
->fr_fix
+= fragp
->fr_var
;
16539 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16543 /* Relax microMIPS branches. */
16544 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16546 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16547 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16548 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16549 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16550 bfd_boolean short_ds
;
16551 unsigned long insn
;
16555 exp
.X_op
= O_symbol
;
16556 exp
.X_add_symbol
= fragp
->fr_symbol
;
16557 exp
.X_add_number
= fragp
->fr_offset
;
16559 fragp
->fr_fix
+= fragp
->fr_var
;
16561 /* Handle 16-bit branches that fit or are forced to fit. */
16562 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16564 /* We generate a fixup instead of applying it right now,
16565 because if there is linker relaxation, we're going to
16566 need the relocations. */
16568 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16569 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16570 else if (type
== 'E')
16571 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16572 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16576 fixp
->fx_file
= fragp
->fr_file
;
16577 fixp
->fx_line
= fragp
->fr_line
;
16579 /* These relocations can have an addend that won't fit in
16581 fixp
->fx_no_overflow
= 1;
16586 /* Handle 32-bit branches that fit or are forced to fit. */
16587 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16588 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16590 /* We generate a fixup instead of applying it right now,
16591 because if there is linker relaxation, we're going to
16592 need the relocations. */
16593 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16594 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16595 fixp
->fx_file
= fragp
->fr_file
;
16596 fixp
->fx_line
= fragp
->fr_line
;
16602 /* Relax 16-bit branches to 32-bit branches. */
16605 insn
= read_compressed_insn (buf
, 2);
16607 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16608 insn
= 0x94000000; /* beq */
16609 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16611 unsigned long regno
;
16613 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16614 regno
= micromips_to_32_reg_d_map
[regno
];
16615 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16616 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16621 /* Nothing else to do, just write it out. */
16622 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16623 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16625 buf
= write_compressed_insn (buf
, insn
, 4);
16626 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16631 insn
= read_compressed_insn (buf
, 4);
16633 /* Relax 32-bit branches to a sequence of instructions. */
16634 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16635 _("Relaxed out-of-range branch into a jump"));
16637 /* Set the short-delay-slot bit. */
16638 short_ds
= al
&& (insn
& 0x02000000) != 0;
16640 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16644 /* Reverse the branch. */
16645 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16646 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16647 insn
^= 0x20000000;
16648 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
16649 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
16650 || (insn
& 0xffe00000) == 0x40800000 /* blez */
16651 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
16652 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
16653 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
16654 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
16655 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
16656 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
16657 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
16658 insn
^= 0x00400000;
16659 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
16660 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
16661 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
16662 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
16663 insn
^= 0x00200000;
16669 /* Clear the and-link and short-delay-slot bits. */
16670 gas_assert ((insn
& 0xfda00000) == 0x40200000);
16672 /* bltzal 0x40200000 bgezal 0x40600000 */
16673 /* bltzals 0x42200000 bgezals 0x42600000 */
16674 insn
&= ~0x02200000;
16677 /* Make a label at the end for use with the branch. */
16678 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
16679 micromips_label_inc ();
16680 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
16683 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
16684 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16685 fixp
->fx_file
= fragp
->fr_file
;
16686 fixp
->fx_line
= fragp
->fr_line
;
16688 /* Branch over the jump. */
16689 buf
= write_compressed_insn (buf
, insn
, 4);
16692 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16695 if (mips_pic
== NO_PIC
)
16697 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
16699 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16700 insn
= al
? jal
: 0xd4000000;
16702 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16703 BFD_RELOC_MICROMIPS_JMP
);
16704 fixp
->fx_file
= fragp
->fr_file
;
16705 fixp
->fx_line
= fragp
->fr_line
;
16707 buf
= write_compressed_insn (buf
, insn
, 4);
16710 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16714 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
16715 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
16716 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
16718 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16719 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
16720 insn
|= at
<< MICROMIPSOP_SH_RT
;
16722 if (exp
.X_add_number
)
16724 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16725 exp
.X_add_number
= 0;
16728 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16729 BFD_RELOC_MICROMIPS_GOT16
);
16730 fixp
->fx_file
= fragp
->fr_file
;
16731 fixp
->fx_line
= fragp
->fr_line
;
16733 buf
= write_compressed_insn (buf
, insn
, 4);
16735 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16736 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
16737 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
16739 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16740 BFD_RELOC_MICROMIPS_LO16
);
16741 fixp
->fx_file
= fragp
->fr_file
;
16742 fixp
->fx_line
= fragp
->fr_line
;
16744 buf
= write_compressed_insn (buf
, insn
, 4);
16746 /* jr/jrc/jalr/jalrs $at */
16747 insn
= al
? jalr
: jr
;
16748 insn
|= at
<< MICROMIPSOP_SH_MJ
;
16750 buf
= write_compressed_insn (buf
, insn
, 2);
16753 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16757 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16760 const struct mips16_immed_operand
*op
;
16763 unsigned int user_length
, length
;
16764 unsigned long insn
;
16767 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16768 op
= mips16_immed_operands
;
16769 while (op
->type
!= type
)
16772 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
16773 val
= resolve_symbol_value (fragp
->fr_symbol
);
16778 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16780 /* The rules for the base address of a PC relative reloc are
16781 complicated; see mips16_extended_frag. */
16782 if (type
== 'p' || type
== 'q')
16787 /* Ignore the low bit in the target, since it will be
16788 set for a text label. */
16789 if ((val
& 1) != 0)
16792 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16794 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16797 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
16800 /* Make sure the section winds up with the alignment we have
16803 record_alignment (asec
, op
->shift
);
16807 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
16808 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
16809 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16810 _("extended instruction in delay slot"));
16812 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16814 insn
= read_compressed_insn (buf
, 2);
16816 insn
|= MIPS16_EXTEND
;
16818 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16820 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16825 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
16826 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
16828 length
= (ext
? 4 : 2);
16829 gas_assert (mips16_opcode_length (insn
) == length
);
16830 write_compressed_insn (buf
, insn
, length
);
16831 fragp
->fr_fix
+= length
;
16835 relax_substateT subtype
= fragp
->fr_subtype
;
16836 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
16837 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
16841 first
= RELAX_FIRST (subtype
);
16842 second
= RELAX_SECOND (subtype
);
16843 fixp
= (fixS
*) fragp
->fr_opcode
;
16845 /* If the delay slot chosen does not match the size of the instruction,
16846 then emit a warning. */
16847 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
16848 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
16853 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
16854 | RELAX_DELAY_SLOT_SIZE_FIRST
16855 | RELAX_DELAY_SLOT_SIZE_SECOND
);
16856 msg
= macro_warning (s
);
16858 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
16862 /* Possibly emit a warning if we've chosen the longer option. */
16863 if (use_second
== second_longer
)
16869 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
16870 msg
= macro_warning (s
);
16872 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
16876 /* Go through all the fixups for the first sequence. Disable them
16877 (by marking them as done) if we're going to use the second
16878 sequence instead. */
16880 && fixp
->fx_frag
== fragp
16881 && fixp
->fx_where
< fragp
->fr_fix
- second
)
16883 if (subtype
& RELAX_USE_SECOND
)
16885 fixp
= fixp
->fx_next
;
16888 /* Go through the fixups for the second sequence. Disable them if
16889 we're going to use the first sequence, otherwise adjust their
16890 addresses to account for the relaxation. */
16891 while (fixp
&& fixp
->fx_frag
== fragp
)
16893 if (subtype
& RELAX_USE_SECOND
)
16894 fixp
->fx_where
-= first
;
16897 fixp
= fixp
->fx_next
;
16900 /* Now modify the frag contents. */
16901 if (subtype
& RELAX_USE_SECOND
)
16905 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
16906 memmove (start
, start
+ first
, second
);
16907 fragp
->fr_fix
-= first
;
16910 fragp
->fr_fix
-= second
;
16914 /* This function is called after the relocs have been generated.
16915 We've been storing mips16 text labels as odd. Here we convert them
16916 back to even for the convenience of the debugger. */
16919 mips_frob_file_after_relocs (void)
16922 unsigned int count
, i
;
16924 syms
= bfd_get_outsymbols (stdoutput
);
16925 count
= bfd_get_symcount (stdoutput
);
16926 for (i
= 0; i
< count
; i
++, syms
++)
16927 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
16928 && ((*syms
)->value
& 1) != 0)
16930 (*syms
)->value
&= ~1;
16931 /* If the symbol has an odd size, it was probably computed
16932 incorrectly, so adjust that as well. */
16933 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
16934 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
16938 /* This function is called whenever a label is defined, including fake
16939 labels instantiated off the dot special symbol. It is used when
16940 handling branch delays; if a branch has a label, we assume we cannot
16941 move it. This also bumps the value of the symbol by 1 in compressed
16945 mips_record_label (symbolS
*sym
)
16947 segment_info_type
*si
= seg_info (now_seg
);
16948 struct insn_label_list
*l
;
16950 if (free_insn_labels
== NULL
)
16951 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
16954 l
= free_insn_labels
;
16955 free_insn_labels
= l
->next
;
16959 l
->next
= si
->label_list
;
16960 si
->label_list
= l
;
16963 /* This function is called as tc_frob_label() whenever a label is defined
16964 and adds a DWARF-2 record we only want for true labels. */
16967 mips_define_label (symbolS
*sym
)
16969 mips_record_label (sym
);
16970 dwarf2_emit_label (sym
);
16973 /* This function is called by tc_new_dot_label whenever a new dot symbol
16977 mips_add_dot_label (symbolS
*sym
)
16979 mips_record_label (sym
);
16980 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
16981 mips_compressed_mark_label (sym
);
16984 /* Some special processing for a MIPS ELF file. */
16987 mips_elf_final_processing (void)
16989 /* Write out the register information. */
16990 if (mips_abi
!= N64_ABI
)
16994 s
.ri_gprmask
= mips_gprmask
;
16995 s
.ri_cprmask
[0] = mips_cprmask
[0];
16996 s
.ri_cprmask
[1] = mips_cprmask
[1];
16997 s
.ri_cprmask
[2] = mips_cprmask
[2];
16998 s
.ri_cprmask
[3] = mips_cprmask
[3];
16999 /* The gp_value field is set by the MIPS ELF backend. */
17001 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17002 ((Elf32_External_RegInfo
*)
17003 mips_regmask_frag
));
17007 Elf64_Internal_RegInfo s
;
17009 s
.ri_gprmask
= mips_gprmask
;
17011 s
.ri_cprmask
[0] = mips_cprmask
[0];
17012 s
.ri_cprmask
[1] = mips_cprmask
[1];
17013 s
.ri_cprmask
[2] = mips_cprmask
[2];
17014 s
.ri_cprmask
[3] = mips_cprmask
[3];
17015 /* The gp_value field is set by the MIPS ELF backend. */
17017 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17018 ((Elf64_External_RegInfo
*)
17019 mips_regmask_frag
));
17022 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17023 sort of BFD interface for this. */
17024 if (mips_any_noreorder
)
17025 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17026 if (mips_pic
!= NO_PIC
)
17028 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17029 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17032 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17034 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17035 defined at present; this might need to change in future. */
17036 if (file_ase_mips16
)
17037 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17038 if (file_ase_micromips
)
17039 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17040 if (file_ase
& ASE_MDMX
)
17041 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17043 /* Set the MIPS ELF ABI flags. */
17044 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17045 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17046 else if (mips_abi
== O64_ABI
)
17047 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17048 else if (mips_abi
== EABI_ABI
)
17050 if (!file_mips_gp32
)
17051 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17053 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17055 else if (mips_abi
== N32_ABI
)
17056 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17058 /* Nothing to do for N64_ABI. */
17060 if (mips_32bitmode
)
17061 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17063 if (mips_flag_nan2008
)
17064 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17066 #if 0 /* XXX FIXME */
17067 /* 32 bit code with 64 bit FP registers. */
17068 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
17069 elf_elfheader (stdoutput
)->e_flags
|= ???;
17073 typedef struct proc
{
17075 symbolS
*func_end_sym
;
17076 unsigned long reg_mask
;
17077 unsigned long reg_offset
;
17078 unsigned long fpreg_mask
;
17079 unsigned long fpreg_offset
;
17080 unsigned long frame_offset
;
17081 unsigned long frame_reg
;
17082 unsigned long pc_reg
;
17085 static procS cur_proc
;
17086 static procS
*cur_proc_ptr
;
17087 static int numprocs
;
17089 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17090 as "2", and a normal nop as "0". */
17092 #define NOP_OPCODE_MIPS 0
17093 #define NOP_OPCODE_MIPS16 1
17094 #define NOP_OPCODE_MICROMIPS 2
17097 mips_nop_opcode (void)
17099 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17100 return NOP_OPCODE_MICROMIPS
;
17101 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17102 return NOP_OPCODE_MIPS16
;
17104 return NOP_OPCODE_MIPS
;
17107 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17108 32-bit microMIPS NOPs here (if applicable). */
17111 mips_handle_align (fragS
*fragp
)
17115 int bytes
, size
, excess
;
17118 if (fragp
->fr_type
!= rs_align_code
)
17121 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17123 switch (nop_opcode
)
17125 case NOP_OPCODE_MICROMIPS
:
17126 opcode
= micromips_nop32_insn
.insn_opcode
;
17129 case NOP_OPCODE_MIPS16
:
17130 opcode
= mips16_nop_insn
.insn_opcode
;
17133 case NOP_OPCODE_MIPS
:
17135 opcode
= nop_insn
.insn_opcode
;
17140 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17141 excess
= bytes
% size
;
17143 /* Handle the leading part if we're not inserting a whole number of
17144 instructions, and make it the end of the fixed part of the frag.
17145 Try to fit in a short microMIPS NOP if applicable and possible,
17146 and use zeroes otherwise. */
17147 gas_assert (excess
< 4);
17148 fragp
->fr_fix
+= excess
;
17153 /* Fall through. */
17155 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17157 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17161 /* Fall through. */
17164 /* Fall through. */
17169 md_number_to_chars (p
, opcode
, size
);
17170 fragp
->fr_var
= size
;
17174 md_obj_begin (void)
17181 /* Check for premature end, nesting errors, etc. */
17183 as_warn (_("missing .end at end of assembly"));
17192 if (*input_line_pointer
== '-')
17194 ++input_line_pointer
;
17197 if (!ISDIGIT (*input_line_pointer
))
17198 as_bad (_("expected simple number"));
17199 if (input_line_pointer
[0] == '0')
17201 if (input_line_pointer
[1] == 'x')
17203 input_line_pointer
+= 2;
17204 while (ISXDIGIT (*input_line_pointer
))
17207 val
|= hex_value (*input_line_pointer
++);
17209 return negative
? -val
: val
;
17213 ++input_line_pointer
;
17214 while (ISDIGIT (*input_line_pointer
))
17217 val
|= *input_line_pointer
++ - '0';
17219 return negative
? -val
: val
;
17222 if (!ISDIGIT (*input_line_pointer
))
17224 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17225 *input_line_pointer
, *input_line_pointer
);
17226 as_warn (_("invalid number"));
17229 while (ISDIGIT (*input_line_pointer
))
17232 val
+= *input_line_pointer
++ - '0';
17234 return negative
? -val
: val
;
17237 /* The .file directive; just like the usual .file directive, but there
17238 is an initial number which is the ECOFF file index. In the non-ECOFF
17239 case .file implies DWARF-2. */
17242 s_mips_file (int x ATTRIBUTE_UNUSED
)
17244 static int first_file_directive
= 0;
17246 if (ECOFF_DEBUGGING
)
17255 filename
= dwarf2_directive_file (0);
17257 /* Versions of GCC up to 3.1 start files with a ".file"
17258 directive even for stabs output. Make sure that this
17259 ".file" is handled. Note that you need a version of GCC
17260 after 3.1 in order to support DWARF-2 on MIPS. */
17261 if (filename
!= NULL
&& ! first_file_directive
)
17263 (void) new_logical_line (filename
, -1);
17264 s_app_file_string (filename
, 0);
17266 first_file_directive
= 1;
17270 /* The .loc directive, implying DWARF-2. */
17273 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17275 if (!ECOFF_DEBUGGING
)
17276 dwarf2_directive_loc (0);
17279 /* The .end directive. */
17282 s_mips_end (int x ATTRIBUTE_UNUSED
)
17286 /* Following functions need their own .frame and .cprestore directives. */
17287 mips_frame_reg_valid
= 0;
17288 mips_cprestore_valid
= 0;
17290 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17293 demand_empty_rest_of_line ();
17298 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17299 as_warn (_(".end not in text section"));
17303 as_warn (_(".end directive without a preceding .ent directive."));
17304 demand_empty_rest_of_line ();
17310 gas_assert (S_GET_NAME (p
));
17311 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17312 as_warn (_(".end symbol does not match .ent symbol."));
17314 if (debug_type
== DEBUG_STABS
)
17315 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17319 as_warn (_(".end directive missing or unknown symbol"));
17321 /* Create an expression to calculate the size of the function. */
17322 if (p
&& cur_proc_ptr
)
17324 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17325 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17328 exp
->X_op
= O_subtract
;
17329 exp
->X_add_symbol
= symbol_temp_new_now ();
17330 exp
->X_op_symbol
= p
;
17331 exp
->X_add_number
= 0;
17333 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17336 /* Generate a .pdr section. */
17337 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17339 segT saved_seg
= now_seg
;
17340 subsegT saved_subseg
= now_subseg
;
17344 #ifdef md_flush_pending_output
17345 md_flush_pending_output ();
17348 gas_assert (pdr_seg
);
17349 subseg_set (pdr_seg
, 0);
17351 /* Write the symbol. */
17352 exp
.X_op
= O_symbol
;
17353 exp
.X_add_symbol
= p
;
17354 exp
.X_add_number
= 0;
17355 emit_expr (&exp
, 4);
17357 fragp
= frag_more (7 * 4);
17359 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17360 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17361 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17362 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17363 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17364 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17365 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17367 subseg_set (saved_seg
, saved_subseg
);
17370 cur_proc_ptr
= NULL
;
17373 /* The .aent and .ent directives. */
17376 s_mips_ent (int aent
)
17380 symbolP
= get_symbol ();
17381 if (*input_line_pointer
== ',')
17382 ++input_line_pointer
;
17383 SKIP_WHITESPACE ();
17384 if (ISDIGIT (*input_line_pointer
)
17385 || *input_line_pointer
== '-')
17388 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17389 as_warn (_(".ent or .aent not in text section."));
17391 if (!aent
&& cur_proc_ptr
)
17392 as_warn (_("missing .end"));
17396 /* This function needs its own .frame and .cprestore directives. */
17397 mips_frame_reg_valid
= 0;
17398 mips_cprestore_valid
= 0;
17400 cur_proc_ptr
= &cur_proc
;
17401 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17403 cur_proc_ptr
->func_sym
= symbolP
;
17407 if (debug_type
== DEBUG_STABS
)
17408 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17409 S_GET_NAME (symbolP
));
17412 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17414 demand_empty_rest_of_line ();
17417 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17418 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17419 s_mips_frame is used so that we can set the PDR information correctly.
17420 We can't use the ecoff routines because they make reference to the ecoff
17421 symbol table (in the mdebug section). */
17424 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17426 if (ECOFF_DEBUGGING
)
17432 if (cur_proc_ptr
== (procS
*) NULL
)
17434 as_warn (_(".frame outside of .ent"));
17435 demand_empty_rest_of_line ();
17439 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17441 SKIP_WHITESPACE ();
17442 if (*input_line_pointer
++ != ','
17443 || get_absolute_expression_and_terminator (&val
) != ',')
17445 as_warn (_("Bad .frame directive"));
17446 --input_line_pointer
;
17447 demand_empty_rest_of_line ();
17451 cur_proc_ptr
->frame_offset
= val
;
17452 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17454 demand_empty_rest_of_line ();
17458 /* The .fmask and .mask directives. If the mdebug section is present
17459 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17460 embedded targets, s_mips_mask is used so that we can set the PDR
17461 information correctly. We can't use the ecoff routines because they
17462 make reference to the ecoff symbol table (in the mdebug section). */
17465 s_mips_mask (int reg_type
)
17467 if (ECOFF_DEBUGGING
)
17468 s_ignore (reg_type
);
17473 if (cur_proc_ptr
== (procS
*) NULL
)
17475 as_warn (_(".mask/.fmask outside of .ent"));
17476 demand_empty_rest_of_line ();
17480 if (get_absolute_expression_and_terminator (&mask
) != ',')
17482 as_warn (_("Bad .mask/.fmask directive"));
17483 --input_line_pointer
;
17484 demand_empty_rest_of_line ();
17488 off
= get_absolute_expression ();
17490 if (reg_type
== 'F')
17492 cur_proc_ptr
->fpreg_mask
= mask
;
17493 cur_proc_ptr
->fpreg_offset
= off
;
17497 cur_proc_ptr
->reg_mask
= mask
;
17498 cur_proc_ptr
->reg_offset
= off
;
17501 demand_empty_rest_of_line ();
17505 /* A table describing all the processors gas knows about. Names are
17506 matched in the order listed.
17508 To ease comparison, please keep this table in the same order as
17509 gcc's mips_cpu_info_table[]. */
17510 static const struct mips_cpu_info mips_cpu_info_table
[] =
17512 /* Entries for generic ISAs */
17513 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17514 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17515 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17516 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17517 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17518 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17519 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17520 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17521 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17524 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17525 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17526 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17529 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17532 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17533 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17534 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17535 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17536 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17537 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17538 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17539 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17540 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17541 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17542 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17543 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17544 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17545 /* ST Microelectronics Loongson 2E and 2F cores */
17546 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17547 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17550 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17551 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17552 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17553 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17554 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17555 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17556 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17557 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17558 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17559 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17560 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17561 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17562 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17563 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17564 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17567 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17568 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17569 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17570 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17572 /* MIPS 32 Release 2 */
17573 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17574 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17575 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17576 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17577 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17578 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17579 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17580 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17581 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17582 ISA_MIPS32R2
, CPU_MIPS32R2
},
17583 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17584 ISA_MIPS32R2
, CPU_MIPS32R2
},
17585 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17586 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17587 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17588 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17589 /* Deprecated forms of the above. */
17590 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17591 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17592 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17593 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17594 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17595 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17596 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17597 /* Deprecated forms of the above. */
17598 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17599 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17600 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17601 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17602 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17603 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17604 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17605 /* Deprecated forms of the above. */
17606 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17607 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17608 /* 34Kn is a 34kc without DSP. */
17609 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17610 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17611 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17612 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17613 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17614 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17615 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17616 /* Deprecated forms of the above. */
17617 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17618 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17619 /* 1004K cores are multiprocessor versions of the 34K. */
17620 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17621 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17622 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17623 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17626 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17627 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17628 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17629 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17631 /* Broadcom SB-1 CPU core */
17632 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17633 /* Broadcom SB-1A CPU core */
17634 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17636 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
17638 /* MIPS 64 Release 2 */
17640 /* Cavium Networks Octeon CPU core */
17641 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
17642 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
17643 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
17646 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
17649 XLP is mostly like XLR, with the prominent exception that it is
17650 MIPS64R2 rather than MIPS64. */
17651 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
17654 { NULL
, 0, 0, 0, 0 }
17658 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17659 with a final "000" replaced by "k". Ignore case.
17661 Note: this function is shared between GCC and GAS. */
17664 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
17666 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
17667 given
++, canonical
++;
17669 return ((*given
== 0 && *canonical
== 0)
17670 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
17674 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17675 CPU name. We've traditionally allowed a lot of variation here.
17677 Note: this function is shared between GCC and GAS. */
17680 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
17682 /* First see if the name matches exactly, or with a final "000"
17683 turned into "k". */
17684 if (mips_strict_matching_cpu_name_p (canonical
, given
))
17687 /* If not, try comparing based on numerical designation alone.
17688 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17689 if (TOLOWER (*given
) == 'r')
17691 if (!ISDIGIT (*given
))
17694 /* Skip over some well-known prefixes in the canonical name,
17695 hoping to find a number there too. */
17696 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
17698 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
17700 else if (TOLOWER (canonical
[0]) == 'r')
17703 return mips_strict_matching_cpu_name_p (canonical
, given
);
17707 /* Parse an option that takes the name of a processor as its argument.
17708 OPTION is the name of the option and CPU_STRING is the argument.
17709 Return the corresponding processor enumeration if the CPU_STRING is
17710 recognized, otherwise report an error and return null.
17712 A similar function exists in GCC. */
17714 static const struct mips_cpu_info
*
17715 mips_parse_cpu (const char *option
, const char *cpu_string
)
17717 const struct mips_cpu_info
*p
;
17719 /* 'from-abi' selects the most compatible architecture for the given
17720 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17721 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17722 version. Look first at the -mgp options, if given, otherwise base
17723 the choice on MIPS_DEFAULT_64BIT.
17725 Treat NO_ABI like the EABIs. One reason to do this is that the
17726 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17727 architecture. This code picks MIPS I for 'mips' and MIPS III for
17728 'mips64', just as we did in the days before 'from-abi'. */
17729 if (strcasecmp (cpu_string
, "from-abi") == 0)
17731 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
17732 return mips_cpu_info_from_isa (ISA_MIPS1
);
17734 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
17735 return mips_cpu_info_from_isa (ISA_MIPS3
);
17737 if (file_mips_gp32
>= 0)
17738 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
17740 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17745 /* 'default' has traditionally been a no-op. Probably not very useful. */
17746 if (strcasecmp (cpu_string
, "default") == 0)
17749 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
17750 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
17753 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
17757 /* Return the canonical processor information for ISA (a member of the
17758 ISA_MIPS* enumeration). */
17760 static const struct mips_cpu_info
*
17761 mips_cpu_info_from_isa (int isa
)
17765 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17766 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
17767 && isa
== mips_cpu_info_table
[i
].isa
)
17768 return (&mips_cpu_info_table
[i
]);
17773 static const struct mips_cpu_info
*
17774 mips_cpu_info_from_arch (int arch
)
17778 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17779 if (arch
== mips_cpu_info_table
[i
].cpu
)
17780 return (&mips_cpu_info_table
[i
]);
17786 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
17790 fprintf (stream
, "%24s", "");
17795 fprintf (stream
, ", ");
17799 if (*col_p
+ strlen (string
) > 72)
17801 fprintf (stream
, "\n%24s", "");
17805 fprintf (stream
, "%s", string
);
17806 *col_p
+= strlen (string
);
17812 md_show_usage (FILE *stream
)
17817 fprintf (stream
, _("\
17819 -EB generate big endian output\n\
17820 -EL generate little endian output\n\
17821 -g, -g2 do not remove unneeded NOPs or swap branches\n\
17822 -G NUM allow referencing objects up to NUM bytes\n\
17823 implicitly with the gp register [default 8]\n"));
17824 fprintf (stream
, _("\
17825 -mips1 generate MIPS ISA I instructions\n\
17826 -mips2 generate MIPS ISA II instructions\n\
17827 -mips3 generate MIPS ISA III instructions\n\
17828 -mips4 generate MIPS ISA IV instructions\n\
17829 -mips5 generate MIPS ISA V instructions\n\
17830 -mips32 generate MIPS32 ISA instructions\n\
17831 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
17832 -mips64 generate MIPS64 ISA instructions\n\
17833 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
17834 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
17838 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17839 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
17840 show (stream
, "from-abi", &column
, &first
);
17841 fputc ('\n', stream
);
17843 fprintf (stream
, _("\
17844 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
17845 -no-mCPU don't generate code specific to CPU.\n\
17846 For -mCPU and -no-mCPU, CPU must be one of:\n"));
17850 show (stream
, "3900", &column
, &first
);
17851 show (stream
, "4010", &column
, &first
);
17852 show (stream
, "4100", &column
, &first
);
17853 show (stream
, "4650", &column
, &first
);
17854 fputc ('\n', stream
);
17856 fprintf (stream
, _("\
17857 -mips16 generate mips16 instructions\n\
17858 -no-mips16 do not generate mips16 instructions\n"));
17859 fprintf (stream
, _("\
17860 -mmicromips generate microMIPS instructions\n\
17861 -mno-micromips do not generate microMIPS instructions\n"));
17862 fprintf (stream
, _("\
17863 -msmartmips generate smartmips instructions\n\
17864 -mno-smartmips do not generate smartmips instructions\n"));
17865 fprintf (stream
, _("\
17866 -mdsp generate DSP instructions\n\
17867 -mno-dsp do not generate DSP instructions\n"));
17868 fprintf (stream
, _("\
17869 -mdspr2 generate DSP R2 instructions\n\
17870 -mno-dspr2 do not generate DSP R2 instructions\n"));
17871 fprintf (stream
, _("\
17872 -mmt generate MT instructions\n\
17873 -mno-mt do not generate MT instructions\n"));
17874 fprintf (stream
, _("\
17875 -mmcu generate MCU instructions\n\
17876 -mno-mcu do not generate MCU instructions\n"));
17877 fprintf (stream
, _("\
17878 -mvirt generate Virtualization instructions\n\
17879 -mno-virt do not generate Virtualization instructions\n"));
17880 fprintf (stream
, _("\
17881 -minsn32 only generate 32-bit microMIPS instructions\n\
17882 -mno-insn32 generate all microMIPS instructions\n"));
17883 fprintf (stream
, _("\
17884 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
17885 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
17886 -mfix-vr4120 work around certain VR4120 errata\n\
17887 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
17888 -mfix-24k insert a nop after ERET and DERET instructions\n\
17889 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
17890 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
17891 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
17892 -msym32 assume all symbols have 32-bit values\n\
17893 -O0 remove unneeded NOPs, do not swap branches\n\
17894 -O remove unneeded NOPs and swap branches\n\
17895 --trap, --no-break trap exception on div by 0 and mult overflow\n\
17896 --break, --no-trap break exception on div by 0 and mult overflow\n"));
17897 fprintf (stream
, _("\
17898 -mhard-float allow floating-point instructions\n\
17899 -msoft-float do not allow floating-point instructions\n\
17900 -msingle-float only allow 32-bit floating-point operations\n\
17901 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
17902 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
17903 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
17904 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
17908 show (stream
, "legacy", &column
, &first
);
17909 show (stream
, "2008", &column
, &first
);
17911 fputc ('\n', stream
);
17913 fprintf (stream
, _("\
17914 -KPIC, -call_shared generate SVR4 position independent code\n\
17915 -call_nonpic generate non-PIC code that can operate with DSOs\n\
17916 -mvxworks-pic generate VxWorks position independent code\n\
17917 -non_shared do not generate code that can operate with DSOs\n\
17918 -xgot assume a 32 bit GOT\n\
17919 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
17920 -mshared, -mno-shared disable/enable .cpload optimization for\n\
17921 position dependent (non shared) code\n\
17922 -mabi=ABI create ABI conformant object file for:\n"));
17926 show (stream
, "32", &column
, &first
);
17927 show (stream
, "o64", &column
, &first
);
17928 show (stream
, "n32", &column
, &first
);
17929 show (stream
, "64", &column
, &first
);
17930 show (stream
, "eabi", &column
, &first
);
17932 fputc ('\n', stream
);
17934 fprintf (stream
, _("\
17935 -32 create o32 ABI object file (default)\n\
17936 -n32 create n32 ABI object file\n\
17937 -64 create 64 ABI object file\n"));
17942 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
17944 if (HAVE_64BIT_SYMBOLS
)
17945 return dwarf2_format_64bit_irix
;
17947 return dwarf2_format_32bit
;
17952 mips_dwarf2_addr_size (void)
17954 if (HAVE_64BIT_OBJECTS
)
17960 /* Standard calling conventions leave the CFA at SP on entry. */
17962 mips_cfi_frame_initial_instructions (void)
17964 cfi_add_CFA_def_cfa_register (SP
);
17968 tc_mips_regname_to_dw2regnum (char *regname
)
17970 unsigned int regnum
= -1;
17973 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))