1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros
;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32
= -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32
= -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts
=
194 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask
;
201 unsigned long mips_cprmask
[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa
= ISA_UNKNOWN
;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16
;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d
;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx
;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch
= CPU_UNKNOWN
;
220 static const char *mips_arch_string
;
221 static const struct mips_cpu_info
*mips_arch_info
;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune
= CPU_UNKNOWN
;
226 static const char *mips_tune_string
;
227 static const struct mips_cpu_info
*mips_tune_info
;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode
= 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
289 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
291 /* Return true if the given CPU supports the MIPS3D ASE. */
292 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
295 /* Return true if the given CPU supports the MDMX ASE. */
296 #define CPU_HAS_MDMX(cpu) (false \
299 /* Whether the processor uses hardware interlocks to protect
300 reads from the HI and LO registers, and thus does not
301 require nops to be inserted. */
303 #define hilo_interlocks (mips_arch == CPU_R4010 \
304 || mips_arch == CPU_SB1 \
307 /* Whether the processor uses hardware interlocks to protect reads
308 from the GPRs, and thus does not require nops to be inserted. */
309 #define gpr_interlocks \
310 (mips_opts.isa != ISA_MIPS1 \
311 || mips_arch == CPU_R3900)
313 /* As with other "interlocks" this is used by hardware that has FP
314 (co-processor) interlocks. */
315 /* Itbl support may require additional care here. */
316 #define cop_interlocks (mips_arch == CPU_R4300 \
317 || mips_arch == CPU_SB1 \
320 /* Is this a mfhi or mflo instruction? */
321 #define MF_HILO_INSN(PINFO) \
322 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
324 /* MIPS PIC level. */
326 enum mips_pic_level mips_pic
;
328 /* Warn about all NOPS that the assembler generates. */
329 static int warn_nops
= 0;
331 /* 1 if we should generate 32 bit offsets from the $gp register in
332 SVR4_PIC mode. Currently has no meaning in other modes. */
333 static int mips_big_got
= 0;
335 /* 1 if trap instructions should used for overflow rather than break
337 static int mips_trap
= 0;
339 /* 1 if double width floating point constants should not be constructed
340 by assembling two single width halves into two single width floating
341 point registers which just happen to alias the double width destination
342 register. On some architectures this aliasing can be disabled by a bit
343 in the status register, and the setting of this bit cannot be determined
344 automatically at assemble time. */
345 static int mips_disable_float_construction
;
347 /* Non-zero if any .set noreorder directives were used. */
349 static int mips_any_noreorder
;
351 /* Non-zero if nops should be inserted when the register referenced in
352 an mfhi/mflo instruction is read in the next two instructions. */
353 static int mips_7000_hilo_fix
;
355 /* The size of the small data section. */
356 static unsigned int g_switch_value
= 8;
357 /* Whether the -G option was used. */
358 static int g_switch_seen
= 0;
363 /* If we can determine in advance that GP optimization won't be
364 possible, we can skip the relaxation stuff that tries to produce
365 GP-relative references. This makes delay slot optimization work
368 This function can only provide a guess, but it seems to work for
369 gcc output. It needs to guess right for gcc, otherwise gcc
370 will put what it thinks is a GP-relative instruction in a branch
373 I don't know if a fix is needed for the SVR4_PIC mode. I've only
374 fixed it for the non-PIC mode. KR 95/04/07 */
375 static int nopic_need_relax
PARAMS ((symbolS
*, int));
377 /* handle of the OPCODE hash table */
378 static struct hash_control
*op_hash
= NULL
;
380 /* The opcode hash table we use for the mips16. */
381 static struct hash_control
*mips16_op_hash
= NULL
;
383 /* This array holds the chars that always start a comment. If the
384 pre-processor is disabled, these aren't very useful */
385 const char comment_chars
[] = "#";
387 /* This array holds the chars that only start a comment at the beginning of
388 a line. If the line seems to have the form '# 123 filename'
389 .line and .file directives will appear in the pre-processed output */
390 /* Note that input_file.c hand checks for '#' at the beginning of the
391 first line of the input file. This is because the compiler outputs
392 #NO_APP at the beginning of its output. */
393 /* Also note that C style comments are always supported. */
394 const char line_comment_chars
[] = "#";
396 /* This array holds machine specific line separator characters. */
397 const char line_separator_chars
[] = ";";
399 /* Chars that can be used to separate mant from exp in floating point nums */
400 const char EXP_CHARS
[] = "eE";
402 /* Chars that mean this number is a floating point constant */
405 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
407 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
408 changed in read.c . Ideally it shouldn't have to know about it at all,
409 but nothing is ideal around here.
412 static char *insn_error
;
414 static int auto_align
= 1;
416 /* When outputting SVR4 PIC code, the assembler needs to know the
417 offset in the stack frame from which to restore the $gp register.
418 This is set by the .cprestore pseudo-op, and saved in this
420 static offsetT mips_cprestore_offset
= -1;
422 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
423 more optimizations, it can use a register value instead of a memory-saved
424 offset and even an other register than $gp as global pointer. */
425 static offsetT mips_cpreturn_offset
= -1;
426 static int mips_cpreturn_register
= -1;
427 static int mips_gp_register
= GP
;
428 static int mips_gprel_offset
= 0;
430 /* Whether mips_cprestore_offset has been set in the current function
431 (or whether it has already been warned about, if not). */
432 static int mips_cprestore_valid
= 0;
434 /* This is the register which holds the stack frame, as set by the
435 .frame pseudo-op. This is needed to implement .cprestore. */
436 static int mips_frame_reg
= SP
;
438 /* Whether mips_frame_reg has been set in the current function
439 (or whether it has already been warned about, if not). */
440 static int mips_frame_reg_valid
= 0;
442 /* To output NOP instructions correctly, we need to keep information
443 about the previous two instructions. */
445 /* Whether we are optimizing. The default value of 2 means to remove
446 unneeded NOPs and swap branch instructions when possible. A value
447 of 1 means to not swap branches. A value of 0 means to always
449 static int mips_optimize
= 2;
451 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
452 equivalent to seeing no -g option at all. */
453 static int mips_debug
= 0;
455 /* The previous instruction. */
456 static struct mips_cl_insn prev_insn
;
458 /* The instruction before prev_insn. */
459 static struct mips_cl_insn prev_prev_insn
;
461 /* If we don't want information for prev_insn or prev_prev_insn, we
462 point the insn_mo field at this dummy integer. */
463 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
465 /* Non-zero if prev_insn is valid. */
466 static int prev_insn_valid
;
468 /* The frag for the previous instruction. */
469 static struct frag
*prev_insn_frag
;
471 /* The offset into prev_insn_frag for the previous instruction. */
472 static long prev_insn_where
;
474 /* The reloc type for the previous instruction, if any. */
475 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
477 /* The reloc for the previous instruction, if any. */
478 static fixS
*prev_insn_fixp
[3];
480 /* Non-zero if the previous instruction was in a delay slot. */
481 static int prev_insn_is_delay_slot
;
483 /* Non-zero if the previous instruction was in a .set noreorder. */
484 static int prev_insn_unreordered
;
486 /* Non-zero if the previous instruction uses an extend opcode (if
488 static int prev_insn_extended
;
490 /* Non-zero if the previous previous instruction was in a .set
492 static int prev_prev_insn_unreordered
;
494 /* If this is set, it points to a frag holding nop instructions which
495 were inserted before the start of a noreorder section. If those
496 nops turn out to be unnecessary, the size of the frag can be
498 static fragS
*prev_nop_frag
;
500 /* The number of nop instructions we created in prev_nop_frag. */
501 static int prev_nop_frag_holds
;
503 /* The number of nop instructions that we know we need in
505 static int prev_nop_frag_required
;
507 /* The number of instructions we've seen since prev_nop_frag. */
508 static int prev_nop_frag_since
;
510 /* For ECOFF and ELF, relocations against symbols are done in two
511 parts, with a HI relocation and a LO relocation. Each relocation
512 has only 16 bits of space to store an addend. This means that in
513 order for the linker to handle carries correctly, it must be able
514 to locate both the HI and the LO relocation. This means that the
515 relocations must appear in order in the relocation table.
517 In order to implement this, we keep track of each unmatched HI
518 relocation. We then sort them so that they immediately precede the
519 corresponding LO relocation. */
524 struct mips_hi_fixup
*next
;
527 /* The section this fixup is in. */
531 /* The list of unmatched HI relocs. */
533 static struct mips_hi_fixup
*mips_hi_fixup_list
;
535 /* Map normal MIPS register numbers to mips16 register numbers. */
537 #define X ILLEGAL_REG
538 static const int mips32_to_16_reg_map
[] =
540 X
, X
, 2, 3, 4, 5, 6, 7,
541 X
, X
, X
, X
, X
, X
, X
, X
,
542 0, 1, X
, X
, X
, X
, X
, X
,
543 X
, X
, X
, X
, X
, X
, X
, X
547 /* Map mips16 register numbers to normal MIPS register numbers. */
549 static const unsigned int mips16_to_32_reg_map
[] =
551 16, 17, 2, 3, 4, 5, 6, 7
554 /* Since the MIPS does not have multiple forms of PC relative
555 instructions, we do not have to do relaxing as is done on other
556 platforms. However, we do have to handle GP relative addressing
557 correctly, which turns out to be a similar problem.
559 Every macro that refers to a symbol can occur in (at least) two
560 forms, one with GP relative addressing and one without. For
561 example, loading a global variable into a register generally uses
562 a macro instruction like this:
564 If i can be addressed off the GP register (this is true if it is in
565 the .sbss or .sdata section, or if it is known to be smaller than
566 the -G argument) this will generate the following instruction:
568 This instruction will use a GPREL reloc. If i can not be addressed
569 off the GP register, the following instruction sequence will be used:
572 In this case the first instruction will have a HI16 reloc, and the
573 second reloc will have a LO16 reloc. Both relocs will be against
576 The issue here is that we may not know whether i is GP addressable
577 until after we see the instruction that uses it. Therefore, we
578 want to be able to choose the final instruction sequence only at
579 the end of the assembly. This is similar to the way other
580 platforms choose the size of a PC relative instruction only at the
583 When generating position independent code we do not use GP
584 addressing in quite the same way, but the issue still arises as
585 external symbols and local symbols must be handled differently.
587 We handle these issues by actually generating both possible
588 instruction sequences. The longer one is put in a frag_var with
589 type rs_machine_dependent. We encode what to do with the frag in
590 the subtype field. We encode (1) the number of existing bytes to
591 replace, (2) the number of new bytes to use, (3) the offset from
592 the start of the existing bytes to the first reloc we must generate
593 (that is, the offset is applied from the start of the existing
594 bytes after they are replaced by the new bytes, if any), (4) the
595 offset from the start of the existing bytes to the second reloc,
596 (5) whether a third reloc is needed (the third reloc is always four
597 bytes after the second reloc), and (6) whether to warn if this
598 variant is used (this is sometimes needed if .set nomacro or .set
599 noat is in effect). All these numbers are reasonably small.
601 Generating two instruction sequences must be handled carefully to
602 ensure that delay slots are handled correctly. Fortunately, there
603 are a limited number of cases. When the second instruction
604 sequence is generated, append_insn is directed to maintain the
605 existing delay slot information, so it continues to apply to any
606 code after the second instruction sequence. This means that the
607 second instruction sequence must not impose any requirements not
608 required by the first instruction sequence.
610 These variant frags are then handled in functions called by the
611 machine independent code. md_estimate_size_before_relax returns
612 the final size of the frag. md_convert_frag sets up the final form
613 of the frag. tc_gen_reloc adjust the first reloc and adds a second
615 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
619 | (((reloc1) + 64) << 9) \
620 | (((reloc2) + 64) << 2) \
621 | ((reloc3) ? (1 << 1) : 0) \
623 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
624 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
625 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
626 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
627 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
628 #define RELAX_WARN(i) ((i) & 1)
630 /* For mips16 code, we use an entirely different form of relaxation.
631 mips16 supports two versions of most instructions which take
632 immediate values: a small one which takes some small value, and a
633 larger one which takes a 16 bit value. Since branches also follow
634 this pattern, relaxing these values is required.
636 We can assemble both mips16 and normal MIPS code in a single
637 object. Therefore, we need to support this type of relaxation at
638 the same time that we support the relaxation described above. We
639 use the high bit of the subtype field to distinguish these cases.
641 The information we store for this type of relaxation is the
642 argument code found in the opcode file for this relocation, whether
643 the user explicitly requested a small or extended form, and whether
644 the relocation is in a jump or jal delay slot. That tells us the
645 size of the value, and how it should be stored. We also store
646 whether the fragment is considered to be extended or not. We also
647 store whether this is known to be a branch to a different section,
648 whether we have tried to relax this frag yet, and whether we have
649 ever extended a PC relative fragment because of a shift count. */
650 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
653 | ((small) ? 0x100 : 0) \
654 | ((ext) ? 0x200 : 0) \
655 | ((dslot) ? 0x400 : 0) \
656 | ((jal_dslot) ? 0x800 : 0))
657 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
658 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
659 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
660 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
661 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
662 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
663 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
664 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
665 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
666 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
667 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
668 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
670 /* Is the given value a sign-extended 32-bit value? */
671 #define IS_SEXT_32BIT_NUM(x) \
672 (((x) &~ (offsetT) 0x7fffffff) == 0 \
673 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
675 /* Is the given value a sign-extended 16-bit value? */
676 #define IS_SEXT_16BIT_NUM(x) \
677 (((x) &~ (offsetT) 0x7fff) == 0 \
678 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
681 /* Prototypes for static functions. */
684 #define internalError() \
685 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
687 #define internalError() as_fatal (_("MIPS internal Error"));
690 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
692 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
693 unsigned int reg
, enum mips_regclass
class));
694 static int reg_needs_delay
PARAMS ((unsigned int));
695 static void mips16_mark_labels
PARAMS ((void));
696 static void append_insn
PARAMS ((char *place
,
697 struct mips_cl_insn
* ip
,
699 bfd_reloc_code_real_type
*r
,
701 static void mips_no_prev_insn
PARAMS ((int));
702 static void mips_emit_delays
PARAMS ((boolean
));
704 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
705 const char *name
, const char *fmt
,
708 static void macro_build ();
710 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
711 const char *, const char *,
713 static void macro_build_jalr
PARAMS ((int, expressionS
*));
714 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
715 expressionS
* ep
, int regnum
));
716 static void macro_build_ldst_constoffset
PARAMS ((char *place
, int *counter
,
717 expressionS
* ep
, const char *op
,
718 int valreg
, int breg
));
719 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
720 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
722 static void load_register
PARAMS ((int *, int, expressionS
*, int));
723 static void load_address
PARAMS ((int *, int, expressionS
*, int *));
724 static void move_register
PARAMS ((int *, int, int));
725 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
726 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
727 #ifdef LOSING_COMPILER
728 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
730 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
731 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
732 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
733 boolean
, boolean
, unsigned long *,
734 boolean
*, unsigned short *));
735 static int my_getPercentOp
PARAMS ((char **, unsigned int *, int *));
736 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
737 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
738 static void my_getExpression
PARAMS ((expressionS
*, char *));
740 static int support_64bit_objects
PARAMS((void));
742 static void mips_set_option_string
PARAMS ((const char **, const char *));
743 static symbolS
*get_symbol
PARAMS ((void));
744 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
745 static void s_align
PARAMS ((int));
746 static void s_change_sec
PARAMS ((int));
747 static void s_change_section
PARAMS ((int));
748 static void s_cons
PARAMS ((int));
749 static void s_float_cons
PARAMS ((int));
750 static void s_mips_globl
PARAMS ((int));
751 static void s_option
PARAMS ((int));
752 static void s_mipsset
PARAMS ((int));
753 static void s_abicalls
PARAMS ((int));
754 static void s_cpload
PARAMS ((int));
755 static void s_cpsetup
PARAMS ((int));
756 static void s_cplocal
PARAMS ((int));
757 static void s_cprestore
PARAMS ((int));
758 static void s_cpreturn
PARAMS ((int));
759 static void s_gpvalue
PARAMS ((int));
760 static void s_gpword
PARAMS ((int));
761 static void s_cpadd
PARAMS ((int));
762 static void s_insn
PARAMS ((int));
763 static void md_obj_begin
PARAMS ((void));
764 static void md_obj_end
PARAMS ((void));
765 static long get_number
PARAMS ((void));
766 static void s_mips_ent
PARAMS ((int));
767 static void s_mips_end
PARAMS ((int));
768 static void s_mips_frame
PARAMS ((int));
769 static void s_mips_mask
PARAMS ((int));
770 static void s_mips_stab
PARAMS ((int));
771 static void s_mips_weakext
PARAMS ((int));
772 static void s_mips_file
PARAMS ((int));
773 static void s_mips_loc
PARAMS ((int));
774 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
775 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
776 static void show
PARAMS ((FILE *, const char *, int *, int *));
778 static int mips_need_elf_addend_fixup
PARAMS ((fixS
*));
781 /* Return values of my_getSmallExpression(). */
788 /* Direct relocation creation by %percent_op(). */
807 /* Table and functions used to map between CPU/ISA names, and
808 ISA levels, and CPU numbers. */
812 const char *name
; /* CPU or ISA name. */
813 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
814 int isa
; /* ISA level. */
815 int cpu
; /* CPU number (default CPU if ISA). */
818 static void mips_set_architecture
PARAMS ((const struct mips_cpu_info
*));
819 static void mips_set_tune
PARAMS ((const struct mips_cpu_info
*));
820 static boolean mips_strict_matching_cpu_name_p
PARAMS ((const char *,
822 static boolean mips_matching_cpu_name_p
PARAMS ((const char *, const char *));
823 static const struct mips_cpu_info
*mips_parse_cpu
PARAMS ((const char *,
825 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
829 The following pseudo-ops from the Kane and Heinrich MIPS book
830 should be defined here, but are currently unsupported: .alias,
831 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
833 The following pseudo-ops from the Kane and Heinrich MIPS book are
834 specific to the type of debugging information being generated, and
835 should be defined by the object format: .aent, .begin, .bend,
836 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
839 The following pseudo-ops from the Kane and Heinrich MIPS book are
840 not MIPS CPU specific, but are also not specific to the object file
841 format. This file is probably the best place to define them, but
842 they are not currently supported: .asm0, .endr, .lab, .repeat,
845 static const pseudo_typeS mips_pseudo_table
[] =
847 /* MIPS specific pseudo-ops. */
848 {"option", s_option
, 0},
849 {"set", s_mipsset
, 0},
850 {"rdata", s_change_sec
, 'r'},
851 {"sdata", s_change_sec
, 's'},
852 {"livereg", s_ignore
, 0},
853 {"abicalls", s_abicalls
, 0},
854 {"cpload", s_cpload
, 0},
855 {"cpsetup", s_cpsetup
, 0},
856 {"cplocal", s_cplocal
, 0},
857 {"cprestore", s_cprestore
, 0},
858 {"cpreturn", s_cpreturn
, 0},
859 {"gpvalue", s_gpvalue
, 0},
860 {"gpword", s_gpword
, 0},
861 {"cpadd", s_cpadd
, 0},
864 /* Relatively generic pseudo-ops that happen to be used on MIPS
866 {"asciiz", stringer
, 1},
867 {"bss", s_change_sec
, 'b'},
870 {"dword", s_cons
, 3},
871 {"weakext", s_mips_weakext
, 0},
873 /* These pseudo-ops are defined in read.c, but must be overridden
874 here for one reason or another. */
875 {"align", s_align
, 0},
877 {"data", s_change_sec
, 'd'},
878 {"double", s_float_cons
, 'd'},
879 {"float", s_float_cons
, 'f'},
880 {"globl", s_mips_globl
, 0},
881 {"global", s_mips_globl
, 0},
882 {"hword", s_cons
, 1},
887 {"section", s_change_section
, 0},
888 {"short", s_cons
, 1},
889 {"single", s_float_cons
, 'f'},
890 {"stabn", s_mips_stab
, 'n'},
891 {"text", s_change_sec
, 't'},
894 { "extern", ecoff_directive_extern
, 0},
899 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
901 /* These pseudo-ops should be defined by the object file format.
902 However, a.out doesn't support them, so we have versions here. */
903 {"aent", s_mips_ent
, 1},
904 {"bgnb", s_ignore
, 0},
905 {"end", s_mips_end
, 0},
906 {"endb", s_ignore
, 0},
907 {"ent", s_mips_ent
, 0},
908 {"file", s_mips_file
, 0},
909 {"fmask", s_mips_mask
, 'F'},
910 {"frame", s_mips_frame
, 0},
911 {"loc", s_mips_loc
, 0},
912 {"mask", s_mips_mask
, 'R'},
913 {"verstamp", s_ignore
, 0},
917 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
922 pop_insert (mips_pseudo_table
);
923 if (! ECOFF_DEBUGGING
)
924 pop_insert (mips_nonecoff_pseudo_table
);
927 /* Symbols labelling the current insn. */
929 struct insn_label_list
931 struct insn_label_list
*next
;
935 static struct insn_label_list
*insn_labels
;
936 static struct insn_label_list
*free_insn_labels
;
938 static void mips_clear_insn_labels
PARAMS ((void));
941 mips_clear_insn_labels ()
943 register struct insn_label_list
**pl
;
945 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
951 static char *expr_end
;
953 /* Expressions which appear in instructions. These are set by
956 static expressionS imm_expr
;
957 static expressionS offset_expr
;
959 /* Relocs associated with imm_expr and offset_expr. */
961 static bfd_reloc_code_real_type imm_reloc
[3]
962 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
963 static bfd_reloc_code_real_type offset_reloc
[3]
964 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
966 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
968 static boolean imm_unmatched_hi
;
970 /* These are set by mips16_ip if an explicit extension is used. */
972 static boolean mips16_small
, mips16_ext
;
975 /* The pdr segment for per procedure frame/regmask info. Not used for
981 /* The default target format to use. */
984 mips_target_format ()
986 switch (OUTPUT_FLAVOR
)
988 case bfd_target_aout_flavour
:
989 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
990 case bfd_target_ecoff_flavour
:
991 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
992 case bfd_target_coff_flavour
:
994 case bfd_target_elf_flavour
:
996 /* This is traditional mips. */
997 return (target_big_endian
998 ? (HAVE_64BIT_OBJECTS
999 ? "elf64-tradbigmips"
1001 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1002 : (HAVE_64BIT_OBJECTS
1003 ? "elf64-tradlittlemips"
1005 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1007 return (target_big_endian
1008 ? (HAVE_64BIT_OBJECTS
1011 ? "elf32-nbigmips" : "elf32-bigmips"))
1012 : (HAVE_64BIT_OBJECTS
1013 ? "elf64-littlemips"
1015 ? "elf32-nlittlemips" : "elf32-littlemips")));
1023 /* This function is called once, at assembler startup time. It should
1024 set up all the tables, etc. that the MD part of the assembler will need. */
1029 register const char *retval
= NULL
;
1033 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1034 as_warn (_("Could not set architecture and machine"));
1036 op_hash
= hash_new ();
1038 for (i
= 0; i
< NUMOPCODES
;)
1040 const char *name
= mips_opcodes
[i
].name
;
1042 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1045 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1046 mips_opcodes
[i
].name
, retval
);
1047 /* Probably a memory allocation problem? Give up now. */
1048 as_fatal (_("Broken assembler. No assembly attempted."));
1052 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1054 if (!validate_mips_insn (&mips_opcodes
[i
]))
1059 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1062 mips16_op_hash
= hash_new ();
1065 while (i
< bfd_mips16_num_opcodes
)
1067 const char *name
= mips16_opcodes
[i
].name
;
1069 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1071 as_fatal (_("internal: can't hash `%s': %s"),
1072 mips16_opcodes
[i
].name
, retval
);
1075 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1076 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1077 != mips16_opcodes
[i
].match
))
1079 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1080 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1085 while (i
< bfd_mips16_num_opcodes
1086 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1090 as_fatal (_("Broken assembler. No assembly attempted."));
1092 /* We add all the general register names to the symbol table. This
1093 helps us detect invalid uses of them. */
1094 for (i
= 0; i
< 32; i
++)
1098 sprintf (buf
, "$%d", i
);
1099 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1100 &zero_address_frag
));
1102 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1103 &zero_address_frag
));
1104 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1105 &zero_address_frag
));
1106 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1107 &zero_address_frag
));
1108 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1109 &zero_address_frag
));
1110 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1111 &zero_address_frag
));
1112 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1113 &zero_address_frag
));
1114 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1115 &zero_address_frag
));
1116 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1117 &zero_address_frag
));
1118 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1119 &zero_address_frag
));
1121 mips_no_prev_insn (false);
1124 mips_cprmask
[0] = 0;
1125 mips_cprmask
[1] = 0;
1126 mips_cprmask
[2] = 0;
1127 mips_cprmask
[3] = 0;
1129 /* set the default alignment for the text section (2**2) */
1130 record_alignment (text_section
, 2);
1132 if (USE_GLOBAL_POINTER_OPT
)
1133 bfd_set_gp_size (stdoutput
, g_switch_value
);
1135 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1137 /* On a native system, sections must be aligned to 16 byte
1138 boundaries. When configured for an embedded ELF target, we
1140 if (strcmp (TARGET_OS
, "elf") != 0)
1142 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1143 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1144 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1147 /* Create a .reginfo section for register masks and a .mdebug
1148 section for debugging information. */
1156 subseg
= now_subseg
;
1158 /* The ABI says this section should be loaded so that the
1159 running program can access it. However, we don't load it
1160 if we are configured for an embedded target */
1161 flags
= SEC_READONLY
| SEC_DATA
;
1162 if (strcmp (TARGET_OS
, "elf") != 0)
1163 flags
|= SEC_ALLOC
| SEC_LOAD
;
1165 if (mips_abi
!= N64_ABI
)
1167 sec
= subseg_new (".reginfo", (subsegT
) 0);
1169 bfd_set_section_flags (stdoutput
, sec
, flags
);
1170 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1173 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1178 /* The 64-bit ABI uses a .MIPS.options section rather than
1179 .reginfo section. */
1180 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1181 bfd_set_section_flags (stdoutput
, sec
, flags
);
1182 bfd_set_section_alignment (stdoutput
, sec
, 3);
1185 /* Set up the option header. */
1187 Elf_Internal_Options opthdr
;
1190 opthdr
.kind
= ODK_REGINFO
;
1191 opthdr
.size
= (sizeof (Elf_External_Options
)
1192 + sizeof (Elf64_External_RegInfo
));
1195 f
= frag_more (sizeof (Elf_External_Options
));
1196 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1197 (Elf_External_Options
*) f
);
1199 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1204 if (ECOFF_DEBUGGING
)
1206 sec
= subseg_new (".mdebug", (subsegT
) 0);
1207 (void) bfd_set_section_flags (stdoutput
, sec
,
1208 SEC_HAS_CONTENTS
| SEC_READONLY
);
1209 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1212 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1214 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1215 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1216 SEC_READONLY
| SEC_RELOC
1218 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1222 subseg_set (seg
, subseg
);
1226 if (! ECOFF_DEBUGGING
)
1233 if (! ECOFF_DEBUGGING
)
1241 struct mips_cl_insn insn
;
1242 bfd_reloc_code_real_type unused_reloc
[3]
1243 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1245 imm_expr
.X_op
= O_absent
;
1246 imm_unmatched_hi
= false;
1247 offset_expr
.X_op
= O_absent
;
1248 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1249 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1250 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1251 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1252 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1253 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1255 if (mips_opts
.mips16
)
1256 mips16_ip (str
, &insn
);
1259 mips_ip (str
, &insn
);
1260 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1261 str
, insn
.insn_opcode
));
1266 as_bad ("%s `%s'", insn_error
, str
);
1270 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1272 if (mips_opts
.mips16
)
1273 mips16_macro (&insn
);
1279 if (imm_expr
.X_op
!= O_absent
)
1280 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1281 else if (offset_expr
.X_op
!= O_absent
)
1282 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1284 append_insn (NULL
, &insn
, NULL
, unused_reloc
, false);
1288 /* See whether instruction IP reads register REG. CLASS is the type
1292 insn_uses_reg (ip
, reg
, class)
1293 struct mips_cl_insn
*ip
;
1295 enum mips_regclass
class;
1297 if (class == MIPS16_REG
)
1299 assert (mips_opts
.mips16
);
1300 reg
= mips16_to_32_reg_map
[reg
];
1301 class = MIPS_GR_REG
;
1304 /* Don't report on general register ZERO, since it never changes. */
1305 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1308 if (class == MIPS_FP_REG
)
1310 assert (! mips_opts
.mips16
);
1311 /* If we are called with either $f0 or $f1, we must check $f0.
1312 This is not optimal, because it will introduce an unnecessary
1313 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1314 need to distinguish reading both $f0 and $f1 or just one of
1315 them. Note that we don't have to check the other way,
1316 because there is no instruction that sets both $f0 and $f1
1317 and requires a delay. */
1318 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1319 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1320 == (reg
&~ (unsigned) 1)))
1322 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1323 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1324 == (reg
&~ (unsigned) 1)))
1327 else if (! mips_opts
.mips16
)
1329 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1330 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1332 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1333 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1338 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1339 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1340 & MIPS16OP_MASK_RX
)]
1343 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1344 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1345 & MIPS16OP_MASK_RY
)]
1348 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1349 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1350 & MIPS16OP_MASK_MOVE32Z
)]
1353 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1355 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1357 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1359 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1360 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1361 & MIPS16OP_MASK_REGR32
) == reg
)
1368 /* This function returns true if modifying a register requires a
1372 reg_needs_delay (reg
)
1375 unsigned long prev_pinfo
;
1377 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1378 if (! mips_opts
.noreorder
1379 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1380 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1381 || (! gpr_interlocks
1382 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1384 /* A load from a coprocessor or from memory. All load
1385 delays delay the use of general register rt for one
1386 instruction on the r3000. The r6000 and r4000 use
1388 /* Itbl support may require additional care here. */
1389 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1390 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1397 /* Mark instruction labels in mips16 mode. This permits the linker to
1398 handle them specially, such as generating jalx instructions when
1399 needed. We also make them odd for the duration of the assembly, in
1400 order to generate the right sort of code. We will make them even
1401 in the adjust_symtab routine, while leaving them marked. This is
1402 convenient for the debugger and the disassembler. The linker knows
1403 to make them odd again. */
1406 mips16_mark_labels ()
1408 if (mips_opts
.mips16
)
1410 struct insn_label_list
*l
;
1413 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1416 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1417 S_SET_OTHER (l
->label
, STO_MIPS16
);
1419 val
= S_GET_VALUE (l
->label
);
1421 S_SET_VALUE (l
->label
, val
+ 1);
1426 /* Output an instruction. PLACE is where to put the instruction; if
1427 it is NULL, this uses frag_more to get room. IP is the instruction
1428 information. ADDRESS_EXPR is an operand of the instruction to be
1429 used with RELOC_TYPE. */
1432 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1434 struct mips_cl_insn
*ip
;
1435 expressionS
*address_expr
;
1436 bfd_reloc_code_real_type
*reloc_type
;
1437 boolean unmatched_hi
;
1439 register unsigned long prev_pinfo
, pinfo
;
1444 /* Mark instruction labels in mips16 mode. */
1445 mips16_mark_labels ();
1447 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1448 pinfo
= ip
->insn_mo
->pinfo
;
1450 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1454 /* If the previous insn required any delay slots, see if we need
1455 to insert a NOP or two. There are eight kinds of possible
1456 hazards, of which an instruction can have at most one type.
1457 (1) a load from memory delay
1458 (2) a load from a coprocessor delay
1459 (3) an unconditional branch delay
1460 (4) a conditional branch delay
1461 (5) a move to coprocessor register delay
1462 (6) a load coprocessor register from memory delay
1463 (7) a coprocessor condition code delay
1464 (8) a HI/LO special register delay
1466 There are a lot of optimizations we could do that we don't.
1467 In particular, we do not, in general, reorder instructions.
1468 If you use gcc with optimization, it will reorder
1469 instructions and generally do much more optimization then we
1470 do here; repeating all that work in the assembler would only
1471 benefit hand written assembly code, and does not seem worth
1474 /* This is how a NOP is emitted. */
1475 #define emit_nop() \
1477 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1478 : md_number_to_chars (frag_more (4), 0, 4))
1480 /* The previous insn might require a delay slot, depending upon
1481 the contents of the current insn. */
1482 if (! mips_opts
.mips16
1483 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1484 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1485 && ! cop_interlocks
)
1486 || (! gpr_interlocks
1487 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1489 /* A load from a coprocessor or from memory. All load
1490 delays delay the use of general register rt for one
1491 instruction on the r3000. The r6000 and r4000 use
1493 /* Itbl support may require additional care here. */
1494 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1495 if (mips_optimize
== 0
1496 || insn_uses_reg (ip
,
1497 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1502 else if (! mips_opts
.mips16
1503 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1504 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1505 && ! cop_interlocks
)
1506 || (mips_opts
.isa
== ISA_MIPS1
1507 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1509 /* A generic coprocessor delay. The previous instruction
1510 modified a coprocessor general or control register. If
1511 it modified a control register, we need to avoid any
1512 coprocessor instruction (this is probably not always
1513 required, but it sometimes is). If it modified a general
1514 register, we avoid using that register.
1516 On the r6000 and r4000 loading a coprocessor register
1517 from memory is interlocked, and does not require a delay.
1519 This case is not handled very well. There is no special
1520 knowledge of CP0 handling, and the coprocessors other
1521 than the floating point unit are not distinguished at
1523 /* Itbl support may require additional care here. FIXME!
1524 Need to modify this to include knowledge about
1525 user specified delays! */
1526 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1528 if (mips_optimize
== 0
1529 || insn_uses_reg (ip
,
1530 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1535 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1537 if (mips_optimize
== 0
1538 || insn_uses_reg (ip
,
1539 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1546 /* We don't know exactly what the previous instruction
1547 does. If the current instruction uses a coprocessor
1548 register, we must insert a NOP. If previous
1549 instruction may set the condition codes, and the
1550 current instruction uses them, we must insert two
1552 /* Itbl support may require additional care here. */
1553 if (mips_optimize
== 0
1554 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1555 && (pinfo
& INSN_READ_COND_CODE
)))
1557 else if (pinfo
& INSN_COP
)
1561 else if (! mips_opts
.mips16
1562 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1563 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1564 && ! cop_interlocks
)
1566 /* The previous instruction sets the coprocessor condition
1567 codes, but does not require a general coprocessor delay
1568 (this means it is a floating point comparison
1569 instruction). If this instruction uses the condition
1570 codes, we need to insert a single NOP. */
1571 /* Itbl support may require additional care here. */
1572 if (mips_optimize
== 0
1573 || (pinfo
& INSN_READ_COND_CODE
))
1577 /* If we're fixing up mfhi/mflo for the r7000 and the
1578 previous insn was an mfhi/mflo and the current insn
1579 reads the register that the mfhi/mflo wrote to, then
1582 else if (mips_7000_hilo_fix
1583 && MF_HILO_INSN (prev_pinfo
)
1584 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1591 /* If we're fixing up mfhi/mflo for the r7000 and the
1592 2nd previous insn was an mfhi/mflo and the current insn
1593 reads the register that the mfhi/mflo wrote to, then
1596 else if (mips_7000_hilo_fix
1597 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1598 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1606 else if (prev_pinfo
& INSN_READ_LO
)
1608 /* The previous instruction reads the LO register; if the
1609 current instruction writes to the LO register, we must
1610 insert two NOPS. Some newer processors have interlocks.
1611 Also the tx39's multiply instructions can be exectuted
1612 immediatly after a read from HI/LO (without the delay),
1613 though the tx39's divide insns still do require the
1615 if (! (hilo_interlocks
1616 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1617 && (mips_optimize
== 0
1618 || (pinfo
& INSN_WRITE_LO
)))
1620 /* Most mips16 branch insns don't have a delay slot.
1621 If a read from LO is immediately followed by a branch
1622 to a write to LO we have a read followed by a write
1623 less than 2 insns away. We assume the target of
1624 a branch might be a write to LO, and insert a nop
1625 between a read and an immediately following branch. */
1626 else if (mips_opts
.mips16
1627 && (mips_optimize
== 0
1628 || (pinfo
& MIPS16_INSN_BRANCH
)))
1631 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1633 /* The previous instruction reads the HI register; if the
1634 current instruction writes to the HI register, we must
1635 insert a NOP. Some newer processors have interlocks.
1636 Also the note tx39's multiply above. */
1637 if (! (hilo_interlocks
1638 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1639 && (mips_optimize
== 0
1640 || (pinfo
& INSN_WRITE_HI
)))
1642 /* Most mips16 branch insns don't have a delay slot.
1643 If a read from HI is immediately followed by a branch
1644 to a write to HI we have a read followed by a write
1645 less than 2 insns away. We assume the target of
1646 a branch might be a write to HI, and insert a nop
1647 between a read and an immediately following branch. */
1648 else if (mips_opts
.mips16
1649 && (mips_optimize
== 0
1650 || (pinfo
& MIPS16_INSN_BRANCH
)))
1654 /* If the previous instruction was in a noreorder section, then
1655 we don't want to insert the nop after all. */
1656 /* Itbl support may require additional care here. */
1657 if (prev_insn_unreordered
)
1660 /* There are two cases which require two intervening
1661 instructions: 1) setting the condition codes using a move to
1662 coprocessor instruction which requires a general coprocessor
1663 delay and then reading the condition codes 2) reading the HI
1664 or LO register and then writing to it (except on processors
1665 which have interlocks). If we are not already emitting a NOP
1666 instruction, we must check for these cases compared to the
1667 instruction previous to the previous instruction. */
1668 if ((! mips_opts
.mips16
1669 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1670 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1671 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1672 && (pinfo
& INSN_READ_COND_CODE
)
1673 && ! cop_interlocks
)
1674 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1675 && (pinfo
& INSN_WRITE_LO
)
1676 && ! (hilo_interlocks
1677 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1678 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1679 && (pinfo
& INSN_WRITE_HI
)
1680 && ! (hilo_interlocks
1681 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1686 if (prev_prev_insn_unreordered
)
1689 if (prev_prev_nop
&& nops
== 0)
1692 /* If we are being given a nop instruction, don't bother with
1693 one of the nops we would otherwise output. This will only
1694 happen when a nop instruction is used with mips_optimize set
1697 && ! mips_opts
.noreorder
1698 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1701 /* Now emit the right number of NOP instructions. */
1702 if (nops
> 0 && ! mips_opts
.noreorder
)
1705 unsigned long old_frag_offset
;
1707 struct insn_label_list
*l
;
1709 old_frag
= frag_now
;
1710 old_frag_offset
= frag_now_fix ();
1712 for (i
= 0; i
< nops
; i
++)
1717 listing_prev_line ();
1718 /* We may be at the start of a variant frag. In case we
1719 are, make sure there is enough space for the frag
1720 after the frags created by listing_prev_line. The
1721 argument to frag_grow here must be at least as large
1722 as the argument to all other calls to frag_grow in
1723 this file. We don't have to worry about being in the
1724 middle of a variant frag, because the variants insert
1725 all needed nop instructions themselves. */
1729 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1733 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1734 symbol_set_frag (l
->label
, frag_now
);
1735 val
= (valueT
) frag_now_fix ();
1736 /* mips16 text labels are stored as odd. */
1737 if (mips_opts
.mips16
)
1739 S_SET_VALUE (l
->label
, val
);
1742 #ifndef NO_ECOFF_DEBUGGING
1743 if (ECOFF_DEBUGGING
)
1744 ecoff_fix_loc (old_frag
, old_frag_offset
);
1747 else if (prev_nop_frag
!= NULL
)
1749 /* We have a frag holding nops we may be able to remove. If
1750 we don't need any nops, we can decrease the size of
1751 prev_nop_frag by the size of one instruction. If we do
1752 need some nops, we count them in prev_nops_required. */
1753 if (prev_nop_frag_since
== 0)
1757 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1758 --prev_nop_frag_holds
;
1761 prev_nop_frag_required
+= nops
;
1765 if (prev_prev_nop
== 0)
1767 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1768 --prev_nop_frag_holds
;
1771 ++prev_nop_frag_required
;
1774 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1775 prev_nop_frag
= NULL
;
1777 ++prev_nop_frag_since
;
1779 /* Sanity check: by the time we reach the second instruction
1780 after prev_nop_frag, we should have used up all the nops
1781 one way or another. */
1782 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1786 if (*reloc_type
> BFD_RELOC_UNUSED
)
1788 /* We need to set up a variant frag. */
1789 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1790 f
= frag_var (rs_machine_dependent
, 4, 0,
1791 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1792 mips16_small
, mips16_ext
,
1794 & INSN_UNCOND_BRANCH_DELAY
),
1795 (*prev_insn_reloc_type
1796 == BFD_RELOC_MIPS16_JMP
)),
1797 make_expr_symbol (address_expr
), 0, NULL
);
1799 else if (place
!= NULL
)
1801 else if (mips_opts
.mips16
1803 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1805 /* Make sure there is enough room to swap this instruction with
1806 a following jump instruction. */
1812 if (mips_opts
.mips16
1813 && mips_opts
.noreorder
1814 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1815 as_warn (_("extended instruction in delay slot"));
1820 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
1821 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
1823 if (address_expr
->X_op
== O_constant
)
1827 switch (*reloc_type
)
1830 ip
->insn_opcode
|= address_expr
->X_add_number
;
1833 case BFD_RELOC_MIPS_HIGHEST
:
1834 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
1836 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1839 case BFD_RELOC_MIPS_HIGHER
:
1840 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
1841 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1844 case BFD_RELOC_HI16_S
:
1845 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
1849 case BFD_RELOC_HI16
:
1850 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
1853 case BFD_RELOC_LO16
:
1854 case BFD_RELOC_MIPS_GOT_DISP
:
1855 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1858 case BFD_RELOC_MIPS_JMP
:
1859 if ((address_expr
->X_add_number
& 3) != 0)
1860 as_bad (_("jump to misaligned address (0x%lx)"),
1861 (unsigned long) address_expr
->X_add_number
);
1862 if (address_expr
->X_add_number
& ~0xfffffff)
1863 as_bad (_("jump address range overflow (0x%lx)"),
1864 (unsigned long) address_expr
->X_add_number
);
1865 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1868 case BFD_RELOC_MIPS16_JMP
:
1869 if ((address_expr
->X_add_number
& 3) != 0)
1870 as_bad (_("jump to misaligned address (0x%lx)"),
1871 (unsigned long) address_expr
->X_add_number
);
1872 if (address_expr
->X_add_number
& ~0xfffffff)
1873 as_bad (_("jump address range overflow (0x%lx)"),
1874 (unsigned long) address_expr
->X_add_number
);
1876 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1877 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1878 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1881 case BFD_RELOC_16_PCREL
:
1882 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1885 case BFD_RELOC_16_PCREL_S2
:
1895 /* Don't generate a reloc if we are writing into a variant frag. */
1898 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1900 (*reloc_type
== BFD_RELOC_16_PCREL
1901 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
1904 /* These relocations can have an addend that won't fit in
1905 4 octets for 64bit assembly. */
1906 if (HAVE_64BIT_GPRS
&&
1907 (*reloc_type
== BFD_RELOC_16
1908 || *reloc_type
== BFD_RELOC_32
1909 || *reloc_type
== BFD_RELOC_MIPS_JMP
1910 || *reloc_type
== BFD_RELOC_HI16_S
1911 || *reloc_type
== BFD_RELOC_LO16
1912 || *reloc_type
== BFD_RELOC_GPREL16
1913 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
1914 || *reloc_type
== BFD_RELOC_GPREL32
1915 || *reloc_type
== BFD_RELOC_64
1916 || *reloc_type
== BFD_RELOC_CTOR
1917 || *reloc_type
== BFD_RELOC_MIPS_SUB
1918 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
1919 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
1920 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
1921 || *reloc_type
== BFD_RELOC_MIPS_REL16
1922 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
1923 fixp
[0]->fx_no_overflow
= 1;
1927 struct mips_hi_fixup
*hi_fixup
;
1929 assert (*reloc_type
== BFD_RELOC_HI16_S
);
1930 hi_fixup
= ((struct mips_hi_fixup
*)
1931 xmalloc (sizeof (struct mips_hi_fixup
)));
1932 hi_fixup
->fixp
= fixp
[0];
1933 hi_fixup
->seg
= now_seg
;
1934 hi_fixup
->next
= mips_hi_fixup_list
;
1935 mips_hi_fixup_list
= hi_fixup
;
1938 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
1940 /* FIXME: This symbol can be one of
1941 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
1942 address_expr
->X_op
= O_absent
;
1943 address_expr
->X_add_symbol
= 0;
1944 address_expr
->X_add_number
= 0;
1946 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
1947 4, address_expr
, false,
1950 /* These relocations can have an addend that won't fit in
1951 4 octets for 64bit assembly. */
1952 if (HAVE_64BIT_GPRS
&&
1953 (*reloc_type
== BFD_RELOC_16
1954 || *reloc_type
== BFD_RELOC_32
1955 || *reloc_type
== BFD_RELOC_MIPS_JMP
1956 || *reloc_type
== BFD_RELOC_HI16_S
1957 || *reloc_type
== BFD_RELOC_LO16
1958 || *reloc_type
== BFD_RELOC_GPREL16
1959 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
1960 || *reloc_type
== BFD_RELOC_GPREL32
1961 || *reloc_type
== BFD_RELOC_64
1962 || *reloc_type
== BFD_RELOC_CTOR
1963 || *reloc_type
== BFD_RELOC_MIPS_SUB
1964 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
1965 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
1966 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
1967 || *reloc_type
== BFD_RELOC_MIPS_REL16
1968 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
1969 fixp
[1]->fx_no_overflow
= 1;
1971 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
1973 address_expr
->X_op
= O_absent
;
1974 address_expr
->X_add_symbol
= 0;
1975 address_expr
->X_add_number
= 0;
1977 fixp
[2] = fix_new_exp (frag_now
,
1978 f
- frag_now
->fr_literal
, 4,
1979 address_expr
, false,
1982 /* These relocations can have an addend that won't fit in
1983 4 octets for 64bit assembly. */
1984 if (HAVE_64BIT_GPRS
&&
1985 (*reloc_type
== BFD_RELOC_16
1986 || *reloc_type
== BFD_RELOC_32
1987 || *reloc_type
== BFD_RELOC_MIPS_JMP
1988 || *reloc_type
== BFD_RELOC_HI16_S
1989 || *reloc_type
== BFD_RELOC_LO16
1990 || *reloc_type
== BFD_RELOC_GPREL16
1991 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
1992 || *reloc_type
== BFD_RELOC_GPREL32
1993 || *reloc_type
== BFD_RELOC_64
1994 || *reloc_type
== BFD_RELOC_CTOR
1995 || *reloc_type
== BFD_RELOC_MIPS_SUB
1996 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
1997 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
1998 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
1999 || *reloc_type
== BFD_RELOC_MIPS_REL16
2000 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2001 fixp
[2]->fx_no_overflow
= 1;
2008 if (! mips_opts
.mips16
)
2010 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2012 dwarf2_emit_insn (4);
2015 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2017 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2018 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2020 dwarf2_emit_insn (4);
2027 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2030 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2032 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2036 /* Update the register mask information. */
2037 if (! mips_opts
.mips16
)
2039 if (pinfo
& INSN_WRITE_GPR_D
)
2040 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2041 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2042 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2043 if (pinfo
& INSN_READ_GPR_S
)
2044 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2045 if (pinfo
& INSN_WRITE_GPR_31
)
2046 mips_gprmask
|= 1 << RA
;
2047 if (pinfo
& INSN_WRITE_FPR_D
)
2048 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2049 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2050 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2051 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2052 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2053 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2054 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2055 if (pinfo
& INSN_COP
)
2057 /* We don't keep enough information to sort these cases out.
2058 The itbl support does keep this information however, although
2059 we currently don't support itbl fprmats as part of the cop
2060 instruction. May want to add this support in the future. */
2062 /* Never set the bit for $0, which is always zero. */
2063 mips_gprmask
&= ~1 << 0;
2067 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2068 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2069 & MIPS16OP_MASK_RX
);
2070 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2071 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2072 & MIPS16OP_MASK_RY
);
2073 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2074 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2075 & MIPS16OP_MASK_RZ
);
2076 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2077 mips_gprmask
|= 1 << TREG
;
2078 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2079 mips_gprmask
|= 1 << SP
;
2080 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2081 mips_gprmask
|= 1 << RA
;
2082 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2083 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2084 if (pinfo
& MIPS16_INSN_READ_Z
)
2085 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2086 & MIPS16OP_MASK_MOVE32Z
);
2087 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2088 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2089 & MIPS16OP_MASK_REGR32
);
2092 if (place
== NULL
&& ! mips_opts
.noreorder
)
2094 /* Filling the branch delay slot is more complex. We try to
2095 switch the branch with the previous instruction, which we can
2096 do if the previous instruction does not set up a condition
2097 that the branch tests and if the branch is not itself the
2098 target of any branch. */
2099 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2100 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2102 if (mips_optimize
< 2
2103 /* If we have seen .set volatile or .set nomove, don't
2105 || mips_opts
.nomove
!= 0
2106 /* If we had to emit any NOP instructions, then we
2107 already know we can not swap. */
2109 /* If we don't even know the previous insn, we can not
2111 || ! prev_insn_valid
2112 /* If the previous insn is already in a branch delay
2113 slot, then we can not swap. */
2114 || prev_insn_is_delay_slot
2115 /* If the previous previous insn was in a .set
2116 noreorder, we can't swap. Actually, the MIPS
2117 assembler will swap in this situation. However, gcc
2118 configured -with-gnu-as will generate code like
2124 in which we can not swap the bne and INSN. If gcc is
2125 not configured -with-gnu-as, it does not output the
2126 .set pseudo-ops. We don't have to check
2127 prev_insn_unreordered, because prev_insn_valid will
2128 be 0 in that case. We don't want to use
2129 prev_prev_insn_valid, because we do want to be able
2130 to swap at the start of a function. */
2131 || prev_prev_insn_unreordered
2132 /* If the branch is itself the target of a branch, we
2133 can not swap. We cheat on this; all we check for is
2134 whether there is a label on this instruction. If
2135 there are any branches to anything other than a
2136 label, users must use .set noreorder. */
2137 || insn_labels
!= NULL
2138 /* If the previous instruction is in a variant frag, we
2139 can not do the swap. This does not apply to the
2140 mips16, which uses variant frags for different
2142 || (! mips_opts
.mips16
2143 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2144 /* If the branch reads the condition codes, we don't
2145 even try to swap, because in the sequence
2150 we can not swap, and I don't feel like handling that
2152 || (! mips_opts
.mips16
2153 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2154 && (pinfo
& INSN_READ_COND_CODE
))
2155 /* We can not swap with an instruction that requires a
2156 delay slot, becase the target of the branch might
2157 interfere with that instruction. */
2158 || (! mips_opts
.mips16
2159 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2161 /* Itbl support may require additional care here. */
2162 & (INSN_LOAD_COPROC_DELAY
2163 | INSN_COPROC_MOVE_DELAY
2164 | INSN_WRITE_COND_CODE
)))
2165 || (! (hilo_interlocks
2166 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2170 || (! mips_opts
.mips16
2172 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2173 || (! mips_opts
.mips16
2174 && mips_opts
.isa
== ISA_MIPS1
2175 /* Itbl support may require additional care here. */
2176 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2177 /* We can not swap with a branch instruction. */
2179 & (INSN_UNCOND_BRANCH_DELAY
2180 | INSN_COND_BRANCH_DELAY
2181 | INSN_COND_BRANCH_LIKELY
))
2182 /* We do not swap with a trap instruction, since it
2183 complicates trap handlers to have the trap
2184 instruction be in a delay slot. */
2185 || (prev_pinfo
& INSN_TRAP
)
2186 /* If the branch reads a register that the previous
2187 instruction sets, we can not swap. */
2188 || (! mips_opts
.mips16
2189 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2190 && insn_uses_reg (ip
,
2191 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2194 || (! mips_opts
.mips16
2195 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2196 && insn_uses_reg (ip
,
2197 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2200 || (mips_opts
.mips16
2201 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2202 && insn_uses_reg (ip
,
2203 ((prev_insn
.insn_opcode
2205 & MIPS16OP_MASK_RX
),
2207 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2208 && insn_uses_reg (ip
,
2209 ((prev_insn
.insn_opcode
2211 & MIPS16OP_MASK_RY
),
2213 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2214 && insn_uses_reg (ip
,
2215 ((prev_insn
.insn_opcode
2217 & MIPS16OP_MASK_RZ
),
2219 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2220 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2221 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2222 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2223 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2224 && insn_uses_reg (ip
,
2225 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2228 /* If the branch writes a register that the previous
2229 instruction sets, we can not swap (we know that
2230 branches write only to RD or to $31). */
2231 || (! mips_opts
.mips16
2232 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2233 && (((pinfo
& INSN_WRITE_GPR_D
)
2234 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2235 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2236 || ((pinfo
& INSN_WRITE_GPR_31
)
2237 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2240 || (! mips_opts
.mips16
2241 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2242 && (((pinfo
& INSN_WRITE_GPR_D
)
2243 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2244 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2245 || ((pinfo
& INSN_WRITE_GPR_31
)
2246 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2249 || (mips_opts
.mips16
2250 && (pinfo
& MIPS16_INSN_WRITE_31
)
2251 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2252 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2253 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2255 /* If the branch writes a register that the previous
2256 instruction reads, we can not swap (we know that
2257 branches only write to RD or to $31). */
2258 || (! mips_opts
.mips16
2259 && (pinfo
& INSN_WRITE_GPR_D
)
2260 && insn_uses_reg (&prev_insn
,
2261 ((ip
->insn_opcode
>> OP_SH_RD
)
2264 || (! mips_opts
.mips16
2265 && (pinfo
& INSN_WRITE_GPR_31
)
2266 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2267 || (mips_opts
.mips16
2268 && (pinfo
& MIPS16_INSN_WRITE_31
)
2269 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2270 /* If we are generating embedded PIC code, the branch
2271 might be expanded into a sequence which uses $at, so
2272 we can't swap with an instruction which reads it. */
2273 || (mips_pic
== EMBEDDED_PIC
2274 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2275 /* If the previous previous instruction has a load
2276 delay, and sets a register that the branch reads, we
2278 || (! mips_opts
.mips16
2279 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2280 /* Itbl support may require additional care here. */
2281 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2282 || (! gpr_interlocks
2283 && (prev_prev_insn
.insn_mo
->pinfo
2284 & INSN_LOAD_MEMORY_DELAY
)))
2285 && insn_uses_reg (ip
,
2286 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2289 /* If one instruction sets a condition code and the
2290 other one uses a condition code, we can not swap. */
2291 || ((pinfo
& INSN_READ_COND_CODE
)
2292 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2293 || ((pinfo
& INSN_WRITE_COND_CODE
)
2294 && (prev_pinfo
& INSN_READ_COND_CODE
))
2295 /* If the previous instruction uses the PC, we can not
2297 || (mips_opts
.mips16
2298 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2299 /* If the previous instruction was extended, we can not
2301 || (mips_opts
.mips16
&& prev_insn_extended
)
2302 /* If the previous instruction had a fixup in mips16
2303 mode, we can not swap. This normally means that the
2304 previous instruction was a 4 byte branch anyhow. */
2305 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2306 /* If the previous instruction is a sync, sync.l, or
2307 sync.p, we can not swap. */
2308 || (prev_pinfo
& INSN_SYNC
))
2310 /* We could do even better for unconditional branches to
2311 portions of this object file; we could pick up the
2312 instruction at the destination, put it in the delay
2313 slot, and bump the destination address. */
2315 /* Update the previous insn information. */
2316 prev_prev_insn
= *ip
;
2317 prev_insn
.insn_mo
= &dummy_opcode
;
2321 /* It looks like we can actually do the swap. */
2322 if (! mips_opts
.mips16
)
2327 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2328 memcpy (temp
, prev_f
, 4);
2329 memcpy (prev_f
, f
, 4);
2330 memcpy (f
, temp
, 4);
2331 if (prev_insn_fixp
[0])
2333 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2334 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2336 if (prev_insn_fixp
[1])
2338 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2339 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2341 if (prev_insn_fixp
[2])
2343 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2344 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2348 fixp
[0]->fx_frag
= prev_insn_frag
;
2349 fixp
[0]->fx_where
= prev_insn_where
;
2353 fixp
[1]->fx_frag
= prev_insn_frag
;
2354 fixp
[1]->fx_where
= prev_insn_where
;
2358 fixp
[2]->fx_frag
= prev_insn_frag
;
2359 fixp
[2]->fx_where
= prev_insn_where
;
2367 assert (prev_insn_fixp
[0] == NULL
);
2368 assert (prev_insn_fixp
[1] == NULL
);
2369 assert (prev_insn_fixp
[2] == NULL
);
2370 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2371 memcpy (temp
, prev_f
, 2);
2372 memcpy (prev_f
, f
, 2);
2373 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2375 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2376 memcpy (f
, temp
, 2);
2380 memcpy (f
, f
+ 2, 2);
2381 memcpy (f
+ 2, temp
, 2);
2385 fixp
[0]->fx_frag
= prev_insn_frag
;
2386 fixp
[0]->fx_where
= prev_insn_where
;
2390 fixp
[1]->fx_frag
= prev_insn_frag
;
2391 fixp
[1]->fx_where
= prev_insn_where
;
2395 fixp
[2]->fx_frag
= prev_insn_frag
;
2396 fixp
[2]->fx_where
= prev_insn_where
;
2400 /* Update the previous insn information; leave prev_insn
2402 prev_prev_insn
= *ip
;
2404 prev_insn_is_delay_slot
= 1;
2406 /* If that was an unconditional branch, forget the previous
2407 insn information. */
2408 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2410 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2411 prev_insn
.insn_mo
= &dummy_opcode
;
2414 prev_insn_fixp
[0] = NULL
;
2415 prev_insn_fixp
[1] = NULL
;
2416 prev_insn_fixp
[2] = NULL
;
2417 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2418 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2419 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2420 prev_insn_extended
= 0;
2422 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2424 /* We don't yet optimize a branch likely. What we should do
2425 is look at the target, copy the instruction found there
2426 into the delay slot, and increment the branch to jump to
2427 the next instruction. */
2429 /* Update the previous insn information. */
2430 prev_prev_insn
= *ip
;
2431 prev_insn
.insn_mo
= &dummy_opcode
;
2432 prev_insn_fixp
[0] = NULL
;
2433 prev_insn_fixp
[1] = NULL
;
2434 prev_insn_fixp
[2] = NULL
;
2435 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2436 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2437 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2438 prev_insn_extended
= 0;
2442 /* Update the previous insn information. */
2444 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2446 prev_prev_insn
= prev_insn
;
2449 /* Any time we see a branch, we always fill the delay slot
2450 immediately; since this insn is not a branch, we know it
2451 is not in a delay slot. */
2452 prev_insn_is_delay_slot
= 0;
2454 prev_insn_fixp
[0] = fixp
[0];
2455 prev_insn_fixp
[1] = fixp
[1];
2456 prev_insn_fixp
[2] = fixp
[2];
2457 prev_insn_reloc_type
[0] = reloc_type
[0];
2458 prev_insn_reloc_type
[1] = reloc_type
[1];
2459 prev_insn_reloc_type
[2] = reloc_type
[2];
2460 if (mips_opts
.mips16
)
2461 prev_insn_extended
= (ip
->use_extend
2462 || *reloc_type
> BFD_RELOC_UNUSED
);
2465 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2466 prev_insn_unreordered
= 0;
2467 prev_insn_frag
= frag_now
;
2468 prev_insn_where
= f
- frag_now
->fr_literal
;
2469 prev_insn_valid
= 1;
2471 else if (place
== NULL
)
2473 /* We need to record a bit of information even when we are not
2474 reordering, in order to determine the base address for mips16
2475 PC relative relocs. */
2476 prev_prev_insn
= prev_insn
;
2478 prev_insn_reloc_type
[0] = reloc_type
[0];
2479 prev_insn_reloc_type
[1] = reloc_type
[1];
2480 prev_insn_reloc_type
[2] = reloc_type
[2];
2481 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2482 prev_insn_unreordered
= 1;
2485 /* We just output an insn, so the next one doesn't have a label. */
2486 mips_clear_insn_labels ();
2488 /* We must ensure that a fixup associated with an unmatched %hi
2489 reloc does not become a variant frag. Otherwise, the
2490 rearrangement of %hi relocs in frob_file may confuse
2494 frag_wane (frag_now
);
2499 /* This function forgets that there was any previous instruction or
2500 label. If PRESERVE is non-zero, it remembers enough information to
2501 know whether nops are needed before a noreorder section. */
2504 mips_no_prev_insn (preserve
)
2509 prev_insn
.insn_mo
= &dummy_opcode
;
2510 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2511 prev_nop_frag
= NULL
;
2512 prev_nop_frag_holds
= 0;
2513 prev_nop_frag_required
= 0;
2514 prev_nop_frag_since
= 0;
2516 prev_insn_valid
= 0;
2517 prev_insn_is_delay_slot
= 0;
2518 prev_insn_unreordered
= 0;
2519 prev_insn_extended
= 0;
2520 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2521 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2522 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2523 prev_prev_insn_unreordered
= 0;
2524 mips_clear_insn_labels ();
2527 /* This function must be called whenever we turn on noreorder or emit
2528 something other than instructions. It inserts any NOPS which might
2529 be needed by the previous instruction, and clears the information
2530 kept for the previous instructions. The INSNS parameter is true if
2531 instructions are to follow. */
2534 mips_emit_delays (insns
)
2537 if (! mips_opts
.noreorder
)
2542 if ((! mips_opts
.mips16
2543 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2544 && (! cop_interlocks
2545 && (prev_insn
.insn_mo
->pinfo
2546 & (INSN_LOAD_COPROC_DELAY
2547 | INSN_COPROC_MOVE_DELAY
2548 | INSN_WRITE_COND_CODE
))))
2549 || (! hilo_interlocks
2550 && (prev_insn
.insn_mo
->pinfo
2553 || (! mips_opts
.mips16
2555 && (prev_insn
.insn_mo
->pinfo
2556 & INSN_LOAD_MEMORY_DELAY
))
2557 || (! mips_opts
.mips16
2558 && mips_opts
.isa
== ISA_MIPS1
2559 && (prev_insn
.insn_mo
->pinfo
2560 & INSN_COPROC_MEMORY_DELAY
)))
2562 /* Itbl support may require additional care here. */
2564 if ((! mips_opts
.mips16
2565 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2566 && (! cop_interlocks
2567 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2568 || (! hilo_interlocks
2569 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2570 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2573 if (prev_insn_unreordered
)
2576 else if ((! mips_opts
.mips16
2577 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2578 && (! cop_interlocks
2579 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2580 || (! hilo_interlocks
2581 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2582 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2584 /* Itbl support may require additional care here. */
2585 if (! prev_prev_insn_unreordered
)
2591 struct insn_label_list
*l
;
2595 /* Record the frag which holds the nop instructions, so
2596 that we can remove them if we don't need them. */
2597 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2598 prev_nop_frag
= frag_now
;
2599 prev_nop_frag_holds
= nops
;
2600 prev_nop_frag_required
= 0;
2601 prev_nop_frag_since
= 0;
2604 for (; nops
> 0; --nops
)
2609 /* Move on to a new frag, so that it is safe to simply
2610 decrease the size of prev_nop_frag. */
2611 frag_wane (frag_now
);
2615 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2619 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2620 symbol_set_frag (l
->label
, frag_now
);
2621 val
= (valueT
) frag_now_fix ();
2622 /* mips16 text labels are stored as odd. */
2623 if (mips_opts
.mips16
)
2625 S_SET_VALUE (l
->label
, val
);
2630 /* Mark instruction labels in mips16 mode. */
2632 mips16_mark_labels ();
2634 mips_no_prev_insn (insns
);
2637 /* Build an instruction created by a macro expansion. This is passed
2638 a pointer to the count of instructions created so far, an
2639 expression, the name of the instruction to build, an operand format
2640 string, and corresponding arguments. */
2644 macro_build (char *place
,
2652 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2661 struct mips_cl_insn insn
;
2662 bfd_reloc_code_real_type r
[3];
2666 va_start (args
, fmt
);
2672 * If the macro is about to expand into a second instruction,
2673 * print a warning if needed. We need to pass ip as a parameter
2674 * to generate a better warning message here...
2676 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2677 as_warn (_("Macro instruction expanded into multiple instructions"));
2680 * If the macro is about to expand into a second instruction,
2681 * and it is in a delay slot, print a warning.
2685 && mips_opts
.noreorder
2686 && (prev_prev_insn
.insn_mo
->pinfo
2687 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2688 | INSN_COND_BRANCH_LIKELY
)) != 0)
2689 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2692 ++*counter
; /* bump instruction counter */
2694 if (mips_opts
.mips16
)
2696 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2701 r
[0] = BFD_RELOC_UNUSED
;
2702 r
[1] = BFD_RELOC_UNUSED
;
2703 r
[2] = BFD_RELOC_UNUSED
;
2704 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2705 assert (insn
.insn_mo
);
2706 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2708 /* Search until we get a match for NAME. */
2711 /* It is assumed here that macros will never generate
2712 MDMX or MIPS-3D instructions. */
2713 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2714 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2715 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2717 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2719 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2723 assert (insn
.insn_mo
->name
);
2724 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2727 insn
.insn_opcode
= insn
.insn_mo
->match
;
2743 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2747 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2752 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2757 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2762 int tmp
= va_arg (args
, int);
2764 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2765 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2771 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2778 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2782 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2786 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2790 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2794 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2801 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2807 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2808 assert (*r
== BFD_RELOC_GPREL16
2809 || *r
== BFD_RELOC_MIPS_LITERAL
2810 || *r
== BFD_RELOC_MIPS_HIGHER
2811 || *r
== BFD_RELOC_HI16_S
2812 || *r
== BFD_RELOC_LO16
2813 || *r
== BFD_RELOC_MIPS_GOT16
2814 || *r
== BFD_RELOC_MIPS_CALL16
2815 || *r
== BFD_RELOC_MIPS_GOT_DISP
2816 || *r
== BFD_RELOC_MIPS_GOT_PAGE
2817 || *r
== BFD_RELOC_MIPS_GOT_OFST
2818 || *r
== BFD_RELOC_MIPS_GOT_LO16
2819 || *r
== BFD_RELOC_MIPS_CALL_LO16
2820 || (ep
->X_op
== O_subtract
2821 && *r
== BFD_RELOC_PCREL_LO16
));
2825 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2827 && (ep
->X_op
== O_constant
2828 || (ep
->X_op
== O_symbol
2829 && (*r
== BFD_RELOC_MIPS_HIGHEST
2830 || *r
== BFD_RELOC_HI16_S
2831 || *r
== BFD_RELOC_HI16
2832 || *r
== BFD_RELOC_GPREL16
2833 || *r
== BFD_RELOC_MIPS_GOT_HI16
2834 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
2835 || (ep
->X_op
== O_subtract
2836 && *r
== BFD_RELOC_PCREL_HI16_S
)));
2840 assert (ep
!= NULL
);
2842 * This allows macro() to pass an immediate expression for
2843 * creating short branches without creating a symbol.
2844 * Note that the expression still might come from the assembly
2845 * input, in which case the value is not checked for range nor
2846 * is a relocation entry generated (yuck).
2848 if (ep
->X_op
== O_constant
)
2850 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2854 if (mips_pic
== EMBEDDED_PIC
)
2855 *r
= BFD_RELOC_16_PCREL_S2
;
2857 *r
= BFD_RELOC_16_PCREL
;
2861 assert (ep
!= NULL
);
2862 *r
= BFD_RELOC_MIPS_JMP
;
2866 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2875 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2877 append_insn (place
, &insn
, ep
, r
, false);
2881 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2883 int *counter ATTRIBUTE_UNUSED
;
2889 struct mips_cl_insn insn
;
2890 bfd_reloc_code_real_type r
[3]
2891 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2893 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2894 assert (insn
.insn_mo
);
2895 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2897 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2898 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2901 assert (insn
.insn_mo
->name
);
2902 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2905 insn
.insn_opcode
= insn
.insn_mo
->match
;
2906 insn
.use_extend
= false;
2925 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2930 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2934 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2938 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2948 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2955 regno
= va_arg (args
, int);
2956 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2957 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2978 assert (ep
!= NULL
);
2980 if (ep
->X_op
!= O_constant
)
2981 *r
= (int) BFD_RELOC_UNUSED
+ c
;
2984 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, false, false,
2985 false, &insn
.insn_opcode
, &insn
.use_extend
,
2988 *r
= BFD_RELOC_UNUSED
;
2994 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3001 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3003 append_insn (place
, &insn
, ep
, r
, false);
3007 * Generate a "jalr" instruction with a relocation hint to the called
3008 * function. This occurs in NewABI PIC code.
3011 macro_build_jalr (icnt
, ep
)
3022 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3025 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3026 0, ep
, false, BFD_RELOC_MIPS_JALR
);
3030 * Generate a "lui" instruction.
3033 macro_build_lui (place
, counter
, ep
, regnum
)
3039 expressionS high_expr
;
3040 struct mips_cl_insn insn
;
3041 bfd_reloc_code_real_type r
[3]
3042 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3043 const char *name
= "lui";
3044 const char *fmt
= "t,u";
3046 assert (! mips_opts
.mips16
);
3052 high_expr
.X_op
= O_constant
;
3053 high_expr
.X_add_number
= ep
->X_add_number
;
3056 if (high_expr
.X_op
== O_constant
)
3058 /* we can compute the instruction now without a relocation entry */
3059 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3061 *r
= BFD_RELOC_UNUSED
;
3063 else if (! HAVE_NEWABI
)
3065 assert (ep
->X_op
== O_symbol
);
3066 /* _gp_disp is a special case, used from s_cpload. */
3067 assert (mips_pic
== NO_PIC
3068 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3069 *r
= BFD_RELOC_HI16_S
;
3073 * If the macro is about to expand into a second instruction,
3074 * print a warning if needed. We need to pass ip as a parameter
3075 * to generate a better warning message here...
3077 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3078 as_warn (_("Macro instruction expanded into multiple instructions"));
3081 ++*counter
; /* bump instruction counter */
3083 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3084 assert (insn
.insn_mo
);
3085 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3086 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3088 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3089 if (*r
== BFD_RELOC_UNUSED
)
3091 insn
.insn_opcode
|= high_expr
.X_add_number
;
3092 append_insn (place
, &insn
, NULL
, r
, false);
3095 append_insn (place
, &insn
, &high_expr
, r
, false);
3098 /* Generate a sequence of instructions to do a load or store from a constant
3099 offset off of a base register (breg) into/from a target register (treg),
3100 using AT if necessary. */
3102 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3109 assert (ep
->X_op
== O_constant
);
3111 /* Right now, this routine can only handle signed 32-bit contants. */
3112 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3113 as_warn (_("operand overflow"));
3115 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3117 /* Signed 16-bit offset will fit in the op. Easy! */
3118 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3119 (int) BFD_RELOC_LO16
, breg
);
3123 /* 32-bit offset, need multiple instructions and AT, like:
3124 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3125 addu $tempreg,$tempreg,$breg
3126 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3127 to handle the complete offset. */
3128 macro_build_lui (place
, counter
, ep
, AT
);
3131 macro_build (place
, counter
, (expressionS
*) NULL
,
3132 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3133 "d,v,t", AT
, AT
, breg
);
3136 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3137 (int) BFD_RELOC_LO16
, AT
);
3140 as_warn (_("Macro used $at after \".set noat\""));
3145 * Generates code to set the $at register to true (one)
3146 * if reg is less than the immediate expression.
3149 set_at (counter
, reg
, unsignedp
)
3154 if (imm_expr
.X_op
== O_constant
3155 && imm_expr
.X_add_number
>= -0x8000
3156 && imm_expr
.X_add_number
< 0x8000)
3157 macro_build ((char *) NULL
, counter
, &imm_expr
,
3158 unsignedp
? "sltiu" : "slti",
3159 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3162 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3163 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3164 unsignedp
? "sltu" : "slt",
3165 "d,v,t", AT
, reg
, AT
);
3169 /* Warn if an expression is not a constant. */
3172 check_absolute_expr (ip
, ex
)
3173 struct mips_cl_insn
*ip
;
3176 if (ex
->X_op
== O_big
)
3177 as_bad (_("unsupported large constant"));
3178 else if (ex
->X_op
!= O_constant
)
3179 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3182 /* Count the leading zeroes by performing a binary chop. This is a
3183 bulky bit of source, but performance is a LOT better for the
3184 majority of values than a simple loop to count the bits:
3185 for (lcnt = 0; (lcnt < 32); lcnt++)
3186 if ((v) & (1 << (31 - lcnt)))
3188 However it is not code size friendly, and the gain will drop a bit
3189 on certain cached systems.
3191 #define COUNT_TOP_ZEROES(v) \
3192 (((v) & ~0xffff) == 0 \
3193 ? ((v) & ~0xff) == 0 \
3194 ? ((v) & ~0xf) == 0 \
3195 ? ((v) & ~0x3) == 0 \
3196 ? ((v) & ~0x1) == 0 \
3201 : ((v) & ~0x7) == 0 \
3204 : ((v) & ~0x3f) == 0 \
3205 ? ((v) & ~0x1f) == 0 \
3208 : ((v) & ~0x7f) == 0 \
3211 : ((v) & ~0xfff) == 0 \
3212 ? ((v) & ~0x3ff) == 0 \
3213 ? ((v) & ~0x1ff) == 0 \
3216 : ((v) & ~0x7ff) == 0 \
3219 : ((v) & ~0x3fff) == 0 \
3220 ? ((v) & ~0x1fff) == 0 \
3223 : ((v) & ~0x7fff) == 0 \
3226 : ((v) & ~0xffffff) == 0 \
3227 ? ((v) & ~0xfffff) == 0 \
3228 ? ((v) & ~0x3ffff) == 0 \
3229 ? ((v) & ~0x1ffff) == 0 \
3232 : ((v) & ~0x7ffff) == 0 \
3235 : ((v) & ~0x3fffff) == 0 \
3236 ? ((v) & ~0x1fffff) == 0 \
3239 : ((v) & ~0x7fffff) == 0 \
3242 : ((v) & ~0xfffffff) == 0 \
3243 ? ((v) & ~0x3ffffff) == 0 \
3244 ? ((v) & ~0x1ffffff) == 0 \
3247 : ((v) & ~0x7ffffff) == 0 \
3250 : ((v) & ~0x3fffffff) == 0 \
3251 ? ((v) & ~0x1fffffff) == 0 \
3254 : ((v) & ~0x7fffffff) == 0 \
3259 * This routine generates the least number of instructions neccessary to load
3260 * an absolute expression value into a register.
3263 load_register (counter
, reg
, ep
, dbl
)
3270 expressionS hi32
, lo32
;
3272 if (ep
->X_op
!= O_big
)
3274 assert (ep
->X_op
== O_constant
);
3275 if (ep
->X_add_number
< 0x8000
3276 && (ep
->X_add_number
>= 0
3277 || (ep
->X_add_number
>= -0x8000
3280 || sizeof (ep
->X_add_number
) > 4))))
3282 /* We can handle 16 bit signed values with an addiu to
3283 $zero. No need to ever use daddiu here, since $zero and
3284 the result are always correct in 32 bit mode. */
3285 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3286 (int) BFD_RELOC_LO16
);
3289 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3291 /* We can handle 16 bit unsigned values with an ori to
3293 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3294 (int) BFD_RELOC_LO16
);
3297 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3300 || sizeof (ep
->X_add_number
) > 4
3301 || (ep
->X_add_number
& 0x80000000) == 0))
3302 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3303 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3306 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3307 == ~ (offsetT
) 0xffffffff)))
3309 /* 32 bit values require an lui. */
3310 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3311 (int) BFD_RELOC_HI16
);
3312 if ((ep
->X_add_number
& 0xffff) != 0)
3313 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3314 (int) BFD_RELOC_LO16
);
3319 /* The value is larger than 32 bits. */
3321 if (HAVE_32BIT_GPRS
)
3323 as_bad (_("Number (0x%lx) larger than 32 bits"),
3324 (unsigned long) ep
->X_add_number
);
3325 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3326 (int) BFD_RELOC_LO16
);
3330 if (ep
->X_op
!= O_big
)
3333 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3334 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3335 hi32
.X_add_number
&= 0xffffffff;
3337 lo32
.X_add_number
&= 0xffffffff;
3341 assert (ep
->X_add_number
> 2);
3342 if (ep
->X_add_number
== 3)
3343 generic_bignum
[3] = 0;
3344 else if (ep
->X_add_number
> 4)
3345 as_bad (_("Number larger than 64 bits"));
3346 lo32
.X_op
= O_constant
;
3347 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3348 hi32
.X_op
= O_constant
;
3349 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3352 if (hi32
.X_add_number
== 0)
3357 unsigned long hi
, lo
;
3359 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3361 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3363 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3364 reg
, 0, (int) BFD_RELOC_LO16
);
3367 if (lo32
.X_add_number
& 0x80000000)
3369 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3370 (int) BFD_RELOC_HI16
);
3371 if (lo32
.X_add_number
& 0xffff)
3372 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3373 reg
, reg
, (int) BFD_RELOC_LO16
);
3378 /* Check for 16bit shifted constant. We know that hi32 is
3379 non-zero, so start the mask on the first bit of the hi32
3384 unsigned long himask
, lomask
;
3388 himask
= 0xffff >> (32 - shift
);
3389 lomask
= (0xffff << shift
) & 0xffffffff;
3393 himask
= 0xffff << (shift
- 32);
3396 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3397 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3401 tmp
.X_op
= O_constant
;
3403 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3404 | (lo32
.X_add_number
>> shift
));
3406 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3407 macro_build ((char *) NULL
, counter
, &tmp
,
3408 "ori", "t,r,i", reg
, 0,
3409 (int) BFD_RELOC_LO16
);
3410 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3411 (shift
>= 32) ? "dsll32" : "dsll",
3413 (shift
>= 32) ? shift
- 32 : shift
);
3418 while (shift
<= (64 - 16));
3420 /* Find the bit number of the lowest one bit, and store the
3421 shifted value in hi/lo. */
3422 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3423 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3427 while ((lo
& 1) == 0)
3432 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3438 while ((hi
& 1) == 0)
3447 /* Optimize if the shifted value is a (power of 2) - 1. */
3448 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3449 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3451 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3456 /* This instruction will set the register to be all
3458 tmp
.X_op
= O_constant
;
3459 tmp
.X_add_number
= (offsetT
) -1;
3460 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3461 reg
, 0, (int) BFD_RELOC_LO16
);
3465 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3466 (bit
>= 32) ? "dsll32" : "dsll",
3468 (bit
>= 32) ? bit
- 32 : bit
);
3470 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3471 (shift
>= 32) ? "dsrl32" : "dsrl",
3473 (shift
>= 32) ? shift
- 32 : shift
);
3478 /* Sign extend hi32 before calling load_register, because we can
3479 generally get better code when we load a sign extended value. */
3480 if ((hi32
.X_add_number
& 0x80000000) != 0)
3481 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3482 load_register (counter
, reg
, &hi32
, 0);
3485 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3489 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3490 "dsll32", "d,w,<", reg
, freg
, 0);
3498 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3500 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3501 (int) BFD_RELOC_HI16
);
3502 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3503 "dsrl32", "d,w,<", reg
, reg
, 0);
3509 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3510 "d,w,<", reg
, freg
, 16);
3514 mid16
.X_add_number
>>= 16;
3515 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3516 freg
, (int) BFD_RELOC_LO16
);
3517 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3518 "d,w,<", reg
, reg
, 16);
3521 if ((lo32
.X_add_number
& 0xffff) != 0)
3522 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3523 (int) BFD_RELOC_LO16
);
3526 /* Load an address into a register. */
3529 load_address (counter
, reg
, ep
, used_at
)
3537 if (ep
->X_op
!= O_constant
3538 && ep
->X_op
!= O_symbol
)
3540 as_bad (_("expression too complex"));
3541 ep
->X_op
= O_constant
;
3544 if (ep
->X_op
== O_constant
)
3546 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3550 if (mips_pic
== NO_PIC
)
3552 /* If this is a reference to a GP relative symbol, we want
3553 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3555 lui $reg,<sym> (BFD_RELOC_HI16_S)
3556 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3557 If we have an addend, we always use the latter form.
3559 With 64bit address space and a usable $at we want
3560 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3561 lui $at,<sym> (BFD_RELOC_HI16_S)
3562 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3563 daddiu $at,<sym> (BFD_RELOC_LO16)
3567 If $at is already in use, we use an path which is suboptimal
3568 on superscalar processors.
3569 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3570 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3572 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3574 daddiu $reg,<sym> (BFD_RELOC_LO16)
3576 if (HAVE_64BIT_ADDRESSES
)
3578 /* We don't do GP optimization for now because RELAX_ENCODE can't
3579 hold the data for such large chunks. */
3581 if (*used_at
== 0 && ! mips_opts
.noat
)
3583 macro_build (p
, counter
, ep
, "lui", "t,u",
3584 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3585 macro_build (p
, counter
, ep
, "lui", "t,u",
3586 AT
, (int) BFD_RELOC_HI16_S
);
3587 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3588 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3589 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3590 AT
, AT
, (int) BFD_RELOC_LO16
);
3591 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3592 "d,w,<", reg
, reg
, 0);
3593 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3594 "d,v,t", reg
, reg
, AT
);
3599 macro_build (p
, counter
, ep
, "lui", "t,u",
3600 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3601 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3602 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3603 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3604 "d,w,<", reg
, reg
, 16);
3605 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3606 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3607 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3608 "d,w,<", reg
, reg
, 16);
3609 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3610 reg
, reg
, (int) BFD_RELOC_LO16
);
3615 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3616 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3619 macro_build ((char *) NULL
, counter
, ep
,
3620 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3621 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3622 p
= frag_var (rs_machine_dependent
, 8, 0,
3623 RELAX_ENCODE (4, 8, 0, 4, 0,
3624 mips_opts
.warn_about_macros
),
3625 ep
->X_add_symbol
, 0, NULL
);
3627 macro_build_lui (p
, counter
, ep
, reg
);
3630 macro_build (p
, counter
, ep
,
3631 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3632 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3635 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3639 /* If this is a reference to an external symbol, we want
3640 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3642 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3644 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3645 If we have NewABI, we want
3646 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3647 If there is a constant, it must be added in after. */
3648 ex
.X_add_number
= ep
->X_add_number
;
3649 ep
->X_add_number
= 0;
3653 macro_build ((char *) NULL
, counter
, ep
,
3654 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3655 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3659 macro_build ((char *) NULL
, counter
, ep
,
3660 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3661 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3662 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3663 p
= frag_var (rs_machine_dependent
, 4, 0,
3664 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3665 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3666 macro_build (p
, counter
, ep
,
3667 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3668 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3671 if (ex
.X_add_number
!= 0)
3673 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3674 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3675 ex
.X_op
= O_constant
;
3676 macro_build ((char *) NULL
, counter
, &ex
,
3677 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3678 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3681 else if (mips_pic
== SVR4_PIC
)
3686 /* This is the large GOT case. If this is a reference to an
3687 external symbol, we want
3688 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3690 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3691 Otherwise, for a reference to a local symbol, we want
3692 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3694 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3695 If we have NewABI, we want
3696 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3697 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3698 If there is a constant, it must be added in after. */
3699 ex
.X_add_number
= ep
->X_add_number
;
3700 ep
->X_add_number
= 0;
3703 macro_build ((char *) NULL
, counter
, ep
,
3704 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3705 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3706 macro_build (p
, counter
, ep
,
3707 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3708 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
3712 if (reg_needs_delay (mips_gp_register
))
3717 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3718 (int) BFD_RELOC_MIPS_GOT_HI16
);
3719 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3720 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
3721 reg
, mips_gp_register
);
3722 macro_build ((char *) NULL
, counter
, ep
,
3723 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3724 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3725 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3726 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3727 mips_opts
.warn_about_macros
),
3728 ep
->X_add_symbol
, 0, NULL
);
3731 /* We need a nop before loading from $gp. This special
3732 check is required because the lui which starts the main
3733 instruction stream does not refer to $gp, and so will not
3734 insert the nop which may be required. */
3735 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3738 macro_build (p
, counter
, ep
,
3739 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3740 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3742 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3744 macro_build (p
, counter
, ep
,
3745 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3746 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3749 if (ex
.X_add_number
!= 0)
3751 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3752 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3753 ex
.X_op
= O_constant
;
3754 macro_build ((char *) NULL
, counter
, &ex
,
3755 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3756 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3759 else if (mips_pic
== EMBEDDED_PIC
)
3762 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3764 macro_build ((char *) NULL
, counter
, ep
,
3765 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3766 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3772 /* Move the contents of register SOURCE into register DEST. */
3775 move_register (counter
, dest
, source
)
3780 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3781 HAVE_32BIT_GPRS
? "addu" : "daddu",
3782 "d,v,t", dest
, source
, 0);
3787 * This routine implements the seemingly endless macro or synthesized
3788 * instructions and addressing modes in the mips assembly language. Many
3789 * of these macros are simple and are similar to each other. These could
3790 * probably be handled by some kind of table or grammer aproach instead of
3791 * this verbose method. Others are not simple macros but are more like
3792 * optimizing code generation.
3793 * One interesting optimization is when several store macros appear
3794 * consecutivly that would load AT with the upper half of the same address.
3795 * The ensuing load upper instructions are ommited. This implies some kind
3796 * of global optimization. We currently only optimize within a single macro.
3797 * For many of the load and store macros if the address is specified as a
3798 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3799 * first load register 'at' with zero and use it as the base register. The
3800 * mips assembler simply uses register $zero. Just one tiny optimization
3805 struct mips_cl_insn
*ip
;
3807 register int treg
, sreg
, dreg
, breg
;
3823 bfd_reloc_code_real_type r
;
3824 int hold_mips_optimize
;
3826 assert (! mips_opts
.mips16
);
3828 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3829 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3830 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3831 mask
= ip
->insn_mo
->mask
;
3833 expr1
.X_op
= O_constant
;
3834 expr1
.X_op_symbol
= NULL
;
3835 expr1
.X_add_symbol
= NULL
;
3836 expr1
.X_add_number
= 1;
3848 mips_emit_delays (true);
3849 ++mips_opts
.noreorder
;
3850 mips_any_noreorder
= 1;
3852 expr1
.X_add_number
= 8;
3853 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3855 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
3858 move_register (&icnt
, dreg
, sreg
);
3859 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3860 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3862 --mips_opts
.noreorder
;
3883 if (imm_expr
.X_op
== O_constant
3884 && imm_expr
.X_add_number
>= -0x8000
3885 && imm_expr
.X_add_number
< 0x8000)
3887 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3888 (int) BFD_RELOC_LO16
);
3891 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3892 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
3912 if (imm_expr
.X_op
== O_constant
3913 && imm_expr
.X_add_number
>= 0
3914 && imm_expr
.X_add_number
< 0x10000)
3916 if (mask
!= M_NOR_I
)
3917 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3918 sreg
, (int) BFD_RELOC_LO16
);
3921 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3922 treg
, sreg
, (int) BFD_RELOC_LO16
);
3923 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
3924 "d,v,t", treg
, treg
, 0);
3929 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3930 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
3948 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3950 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3954 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3955 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3963 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3964 likely
? "bgezl" : "bgez", "s,p", sreg
);
3969 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3970 likely
? "blezl" : "blez", "s,p", treg
);
3973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
3975 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3976 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3982 /* check for > max integer */
3983 maxnum
= 0x7fffffff;
3984 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3991 if (imm_expr
.X_op
== O_constant
3992 && imm_expr
.X_add_number
>= maxnum
3993 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3996 /* result is always false */
4000 as_warn (_("Branch %s is always false (nop)"),
4002 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4008 as_warn (_("Branch likely %s is always false"),
4010 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4015 if (imm_expr
.X_op
!= O_constant
)
4016 as_bad (_("Unsupported large constant"));
4017 ++imm_expr
.X_add_number
;
4021 if (mask
== M_BGEL_I
)
4023 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4025 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4026 likely
? "bgezl" : "bgez", "s,p", sreg
);
4029 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4031 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4032 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4035 maxnum
= 0x7fffffff;
4036 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4043 maxnum
= - maxnum
- 1;
4044 if (imm_expr
.X_op
== O_constant
4045 && imm_expr
.X_add_number
<= maxnum
4046 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4049 /* result is always true */
4050 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4051 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4054 set_at (&icnt
, sreg
, 0);
4055 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4056 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4066 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4067 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4071 "d,v,t", AT
, sreg
, treg
);
4072 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4073 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4081 && imm_expr
.X_op
== O_constant
4082 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4084 if (imm_expr
.X_op
!= O_constant
)
4085 as_bad (_("Unsupported large constant"));
4086 ++imm_expr
.X_add_number
;
4090 if (mask
== M_BGEUL_I
)
4092 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4094 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4096 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4097 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4100 set_at (&icnt
, sreg
, 1);
4101 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4102 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4110 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4111 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4116 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4117 likely
? "bltzl" : "bltz", "s,p", treg
);
4120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4122 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4123 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4131 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4132 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4137 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4138 "d,v,t", AT
, treg
, sreg
);
4139 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4140 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4148 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4149 likely
? "blezl" : "blez", "s,p", sreg
);
4154 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4155 likely
? "bgezl" : "bgez", "s,p", treg
);
4158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4161 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4167 maxnum
= 0x7fffffff;
4168 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4175 if (imm_expr
.X_op
== O_constant
4176 && imm_expr
.X_add_number
>= maxnum
4177 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4179 if (imm_expr
.X_op
!= O_constant
)
4180 as_bad (_("Unsupported large constant"));
4181 ++imm_expr
.X_add_number
;
4185 if (mask
== M_BLTL_I
)
4187 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4189 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4190 likely
? "bltzl" : "bltz", "s,p", sreg
);
4193 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4195 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4196 likely
? "blezl" : "blez", "s,p", sreg
);
4199 set_at (&icnt
, sreg
, 0);
4200 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4201 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4209 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4210 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4215 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4216 "d,v,t", AT
, treg
, sreg
);
4217 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4218 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4226 && imm_expr
.X_op
== O_constant
4227 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4229 if (imm_expr
.X_op
!= O_constant
)
4230 as_bad (_("Unsupported large constant"));
4231 ++imm_expr
.X_add_number
;
4235 if (mask
== M_BLTUL_I
)
4237 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4239 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4241 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4242 likely
? "beql" : "beq",
4246 set_at (&icnt
, sreg
, 1);
4247 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4248 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4256 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4257 likely
? "bltzl" : "bltz", "s,p", sreg
);
4262 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4263 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4266 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4268 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4269 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4279 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4280 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4283 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4286 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4287 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4302 as_warn (_("Divide by zero."));
4304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4307 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4312 mips_emit_delays (true);
4313 ++mips_opts
.noreorder
;
4314 mips_any_noreorder
= 1;
4317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4318 "s,t,q", treg
, 0, 7);
4319 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4320 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4324 expr1
.X_add_number
= 8;
4325 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4326 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4327 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4331 expr1
.X_add_number
= -1;
4332 macro_build ((char *) NULL
, &icnt
, &expr1
,
4333 dbl
? "daddiu" : "addiu",
4334 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4335 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4336 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4339 expr1
.X_add_number
= 1;
4340 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4341 (int) BFD_RELOC_LO16
);
4342 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4343 "d,w,<", AT
, AT
, 31);
4347 expr1
.X_add_number
= 0x80000000;
4348 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4349 (int) BFD_RELOC_HI16
);
4353 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4354 "s,t,q", sreg
, AT
, 6);
4355 /* We want to close the noreorder block as soon as possible, so
4356 that later insns are available for delay slot filling. */
4357 --mips_opts
.noreorder
;
4361 expr1
.X_add_number
= 8;
4362 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4363 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4366 /* We want to close the noreorder block as soon as possible, so
4367 that later insns are available for delay slot filling. */
4368 --mips_opts
.noreorder
;
4370 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4373 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4412 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4414 as_warn (_("Divide by zero."));
4416 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4419 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4423 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4425 if (strcmp (s2
, "mflo") == 0)
4426 move_register (&icnt
, dreg
, sreg
);
4428 move_register (&icnt
, dreg
, 0);
4431 if (imm_expr
.X_op
== O_constant
4432 && imm_expr
.X_add_number
== -1
4433 && s
[strlen (s
) - 1] != 'u')
4435 if (strcmp (s2
, "mflo") == 0)
4437 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4438 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4441 move_register (&icnt
, dreg
, 0);
4445 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4446 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4448 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4467 mips_emit_delays (true);
4468 ++mips_opts
.noreorder
;
4469 mips_any_noreorder
= 1;
4472 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4473 "s,t,q", treg
, 0, 7);
4474 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4476 /* We want to close the noreorder block as soon as possible, so
4477 that later insns are available for delay slot filling. */
4478 --mips_opts
.noreorder
;
4482 expr1
.X_add_number
= 8;
4483 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4484 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4487 /* We want to close the noreorder block as soon as possible, so
4488 that later insns are available for delay slot filling. */
4489 --mips_opts
.noreorder
;
4490 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4493 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4499 /* Load the address of a symbol into a register. If breg is not
4500 zero, we then add a base register to it. */
4502 if (dbl
&& HAVE_32BIT_GPRS
)
4503 as_warn (_("dla used to load 32-bit register"));
4505 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4506 as_warn (_("la used to load 64-bit address"));
4508 if (offset_expr
.X_op
== O_constant
4509 && offset_expr
.X_add_number
>= -0x8000
4510 && offset_expr
.X_add_number
< 0x8000)
4512 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4513 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4514 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4529 /* When generating embedded PIC code, we permit expressions of
4532 la $treg,foo-bar($breg)
4533 where bar is an address in the current section. These are used
4534 when getting the addresses of functions. We don't permit
4535 X_add_number to be non-zero, because if the symbol is
4536 external the relaxing code needs to know that any addend is
4537 purely the offset to X_op_symbol. */
4538 if (mips_pic
== EMBEDDED_PIC
4539 && offset_expr
.X_op
== O_subtract
4540 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4541 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4542 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4544 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4547 && (offset_expr
.X_add_number
== 0
4548 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4554 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4555 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4559 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4560 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4561 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4562 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4563 "d,v,t", tempreg
, tempreg
, breg
);
4565 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4566 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4567 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4573 if (offset_expr
.X_op
!= O_symbol
4574 && offset_expr
.X_op
!= O_constant
)
4576 as_bad (_("expression too complex"));
4577 offset_expr
.X_op
= O_constant
;
4580 if (offset_expr
.X_op
== O_constant
)
4581 load_register (&icnt
, tempreg
, &offset_expr
,
4582 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4583 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4584 : HAVE_64BIT_ADDRESSES
));
4585 else if (mips_pic
== NO_PIC
)
4587 /* If this is a reference to a GP relative symbol, we want
4588 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4590 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4591 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4592 If we have a constant, we need two instructions anyhow,
4593 so we may as well always use the latter form.
4595 With 64bit address space and a usable $at we want
4596 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4597 lui $at,<sym> (BFD_RELOC_HI16_S)
4598 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4599 daddiu $at,<sym> (BFD_RELOC_LO16)
4601 daddu $tempreg,$tempreg,$at
4603 If $at is already in use, we use an path which is suboptimal
4604 on superscalar processors.
4605 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4606 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4608 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4610 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4613 if (HAVE_64BIT_ADDRESSES
)
4615 /* We don't do GP optimization for now because RELAX_ENCODE can't
4616 hold the data for such large chunks. */
4618 if (used_at
== 0 && ! mips_opts
.noat
)
4620 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4621 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4622 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4623 AT
, (int) BFD_RELOC_HI16_S
);
4624 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4625 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4626 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4627 AT
, AT
, (int) BFD_RELOC_LO16
);
4628 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4629 "d,w,<", tempreg
, tempreg
, 0);
4630 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
4631 "d,v,t", tempreg
, tempreg
, AT
);
4636 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4637 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4638 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4639 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4640 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4641 tempreg
, tempreg
, 16);
4642 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4643 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4644 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4645 tempreg
, tempreg
, 16);
4646 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4647 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4652 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4653 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4656 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4657 "t,r,j", tempreg
, mips_gp_register
,
4658 (int) BFD_RELOC_GPREL16
);
4659 p
= frag_var (rs_machine_dependent
, 8, 0,
4660 RELAX_ENCODE (4, 8, 0, 4, 0,
4661 mips_opts
.warn_about_macros
),
4662 offset_expr
.X_add_symbol
, 0, NULL
);
4664 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4667 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4668 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4671 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4673 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4675 /* If this is a reference to an external symbol, and there
4676 is no constant, we want
4677 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4678 or if tempreg is PIC_CALL_REG
4679 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4680 For a local symbol, we want
4681 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4683 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4685 If we have a small constant, and this is a reference to
4686 an external symbol, we want
4687 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4689 addiu $tempreg,$tempreg,<constant>
4690 For a local symbol, we want the same instruction
4691 sequence, but we output a BFD_RELOC_LO16 reloc on the
4694 If we have a large constant, and this is a reference to
4695 an external symbol, we want
4696 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4697 lui $at,<hiconstant>
4698 addiu $at,$at,<loconstant>
4699 addu $tempreg,$tempreg,$at
4700 For a local symbol, we want the same instruction
4701 sequence, but we output a BFD_RELOC_LO16 reloc on the
4704 For NewABI, we want for local or external data addresses
4705 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4706 For a local function symbol, we want
4707 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4709 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4712 expr1
.X_add_number
= offset_expr
.X_add_number
;
4713 offset_expr
.X_add_number
= 0;
4715 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4716 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4717 else if (HAVE_NEWABI
)
4718 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
4719 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4720 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4721 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
4722 if (expr1
.X_add_number
== 0)
4731 /* We're going to put in an addu instruction using
4732 tempreg, so we may as well insert the nop right
4734 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4738 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4739 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4741 ? mips_opts
.warn_about_macros
4743 offset_expr
.X_add_symbol
, 0, NULL
);
4746 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4749 macro_build (p
, &icnt
, &expr1
,
4750 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4751 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4752 /* FIXME: If breg == 0, and the next instruction uses
4753 $tempreg, then if this variant case is used an extra
4754 nop will be generated. */
4756 else if (expr1
.X_add_number
>= -0x8000
4757 && expr1
.X_add_number
< 0x8000)
4759 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4761 macro_build ((char *) NULL
, &icnt
, &expr1
,
4762 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4763 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4764 frag_var (rs_machine_dependent
, 0, 0,
4765 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4766 offset_expr
.X_add_symbol
, 0, NULL
);
4772 /* If we are going to add in a base register, and the
4773 target register and the base register are the same,
4774 then we are using AT as a temporary register. Since
4775 we want to load the constant into AT, we add our
4776 current AT (from the global offset table) and the
4777 register into the register now, and pretend we were
4778 not using a base register. */
4783 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4785 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4786 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4787 "d,v,t", treg
, AT
, breg
);
4793 /* Set mips_optimize around the lui instruction to avoid
4794 inserting an unnecessary nop after the lw. */
4795 hold_mips_optimize
= mips_optimize
;
4797 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4798 mips_optimize
= hold_mips_optimize
;
4800 macro_build ((char *) NULL
, &icnt
, &expr1
,
4801 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4802 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4804 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4805 "d,v,t", tempreg
, tempreg
, AT
);
4806 frag_var (rs_machine_dependent
, 0, 0,
4807 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4808 offset_expr
.X_add_symbol
, 0, NULL
);
4812 else if (mips_pic
== SVR4_PIC
)
4816 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4817 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4818 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4820 /* This is the large GOT case. If this is a reference to an
4821 external symbol, and there is no constant, we want
4822 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4823 addu $tempreg,$tempreg,$gp
4824 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4825 or if tempreg is PIC_CALL_REG
4826 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4827 addu $tempreg,$tempreg,$gp
4828 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4829 For a local symbol, we want
4830 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4832 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4834 If we have a small constant, and this is a reference to
4835 an external symbol, we want
4836 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4837 addu $tempreg,$tempreg,$gp
4838 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4840 addiu $tempreg,$tempreg,<constant>
4841 For a local symbol, we want
4842 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4844 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4846 If we have a large constant, and this is a reference to
4847 an external symbol, we want
4848 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4849 addu $tempreg,$tempreg,$gp
4850 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4851 lui $at,<hiconstant>
4852 addiu $at,$at,<loconstant>
4853 addu $tempreg,$tempreg,$at
4854 For a local symbol, we want
4855 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4856 lui $at,<hiconstant>
4857 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4858 addu $tempreg,$tempreg,$at
4860 For NewABI, we want for local data addresses
4861 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4864 expr1
.X_add_number
= offset_expr
.X_add_number
;
4865 offset_expr
.X_add_number
= 0;
4867 if (reg_needs_delay (mips_gp_register
))
4871 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4873 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4874 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4876 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4877 tempreg
, lui_reloc_type
);
4878 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4879 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4880 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
4881 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4882 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4883 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4884 if (expr1
.X_add_number
== 0)
4892 /* We're going to put in an addu instruction using
4893 tempreg, so we may as well insert the nop right
4895 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4900 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4901 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4904 ? mips_opts
.warn_about_macros
4906 offset_expr
.X_add_symbol
, 0, NULL
);
4908 else if (expr1
.X_add_number
>= -0x8000
4909 && expr1
.X_add_number
< 0x8000)
4911 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4913 macro_build ((char *) NULL
, &icnt
, &expr1
,
4914 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4915 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4917 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4918 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4920 ? mips_opts
.warn_about_macros
4922 offset_expr
.X_add_symbol
, 0, NULL
);
4928 /* If we are going to add in a base register, and the
4929 target register and the base register are the same,
4930 then we are using AT as a temporary register. Since
4931 we want to load the constant into AT, we add our
4932 current AT (from the global offset table) and the
4933 register into the register now, and pretend we were
4934 not using a base register. */
4942 assert (tempreg
== AT
);
4943 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4945 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4946 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4947 "d,v,t", treg
, AT
, breg
);
4952 /* Set mips_optimize around the lui instruction to avoid
4953 inserting an unnecessary nop after the lw. */
4954 hold_mips_optimize
= mips_optimize
;
4956 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4957 mips_optimize
= hold_mips_optimize
;
4959 macro_build ((char *) NULL
, &icnt
, &expr1
,
4960 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4961 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4962 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4963 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4964 "d,v,t", dreg
, dreg
, AT
);
4966 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4967 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4970 ? mips_opts
.warn_about_macros
4972 offset_expr
.X_add_symbol
, 0, NULL
);
4979 /* This is needed because this instruction uses $gp, but
4980 the first instruction on the main stream does not. */
4981 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4986 local_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
4987 macro_build (p
, &icnt
, &offset_expr
,
4988 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4993 if (expr1
.X_add_number
== 0 && HAVE_NEWABI
)
4995 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
4998 if (expr1
.X_add_number
>= -0x8000
4999 && expr1
.X_add_number
< 0x8000)
5001 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5003 macro_build (p
, &icnt
, &expr1
,
5004 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5005 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5006 /* FIXME: If add_number is 0, and there was no base
5007 register, the external symbol case ended with a load,
5008 so if the symbol turns out to not be external, and
5009 the next instruction uses tempreg, an unnecessary nop
5010 will be inserted. */
5016 /* We must add in the base register now, as in the
5017 external symbol case. */
5018 assert (tempreg
== AT
);
5019 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5021 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5022 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5023 "d,v,t", treg
, AT
, breg
);
5026 /* We set breg to 0 because we have arranged to add
5027 it in in both cases. */
5031 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5033 macro_build (p
, &icnt
, &expr1
,
5034 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5035 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5037 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5038 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5039 "d,v,t", tempreg
, tempreg
, AT
);
5043 else if (mips_pic
== EMBEDDED_PIC
)
5046 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5048 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5049 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5050 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5059 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5060 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5062 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5064 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5065 "d,v,t", treg
, tempreg
, breg
);
5074 /* The j instruction may not be used in PIC code, since it
5075 requires an absolute address. We convert it to a b
5077 if (mips_pic
== NO_PIC
)
5078 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5080 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5083 /* The jal instructions must be handled as macros because when
5084 generating PIC code they expand to multi-instruction
5085 sequences. Normally they are simple instructions. */
5090 if (mips_pic
== NO_PIC
5091 || mips_pic
== EMBEDDED_PIC
)
5092 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5094 else if (mips_pic
== SVR4_PIC
)
5096 if (sreg
!= PIC_CALL_REG
)
5097 as_warn (_("MIPS PIC call to register other than $25"));
5099 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5103 if (mips_cprestore_offset
< 0)
5104 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5107 if (! mips_frame_reg_valid
)
5109 as_warn (_("No .frame pseudo-op used in PIC code"));
5110 /* Quiet this warning. */
5111 mips_frame_reg_valid
= 1;
5113 if (! mips_cprestore_valid
)
5115 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5116 /* Quiet this warning. */
5117 mips_cprestore_valid
= 1;
5119 expr1
.X_add_number
= mips_cprestore_offset
;
5120 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5121 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5122 mips_gp_register
, mips_frame_reg
);
5132 if (mips_pic
== NO_PIC
)
5133 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5134 else if (mips_pic
== SVR4_PIC
)
5138 /* If this is a reference to an external symbol, and we are
5139 using a small GOT, we want
5140 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5144 lw $gp,cprestore($sp)
5145 The cprestore value is set using the .cprestore
5146 pseudo-op. If we are using a big GOT, we want
5147 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5149 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5153 lw $gp,cprestore($sp)
5154 If the symbol is not external, we want
5155 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5157 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5160 lw $gp,cprestore($sp)
5162 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5163 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5167 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5168 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5169 "t,o(b)", PIC_CALL_REG
,
5170 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5171 macro_build_jalr (icnt
, &offset_expr
);
5178 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5179 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5180 "t,o(b)", PIC_CALL_REG
,
5181 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5182 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5184 p
= frag_var (rs_machine_dependent
, 4, 0,
5185 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5186 offset_expr
.X_add_symbol
, 0, NULL
);
5192 if (reg_needs_delay (mips_gp_register
))
5196 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5197 "t,u", PIC_CALL_REG
,
5198 (int) BFD_RELOC_MIPS_CALL_HI16
);
5199 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5200 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5201 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5203 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5204 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5205 "t,o(b)", PIC_CALL_REG
,
5206 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5207 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5209 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5210 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5212 offset_expr
.X_add_symbol
, 0, NULL
);
5215 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5218 macro_build (p
, &icnt
, &offset_expr
,
5219 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5220 "t,o(b)", PIC_CALL_REG
,
5221 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5223 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5226 macro_build (p
, &icnt
, &offset_expr
,
5227 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5228 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5229 (int) BFD_RELOC_LO16
);
5230 macro_build_jalr (icnt
, &offset_expr
);
5232 if (mips_cprestore_offset
< 0)
5233 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5236 if (! mips_frame_reg_valid
)
5238 as_warn (_("No .frame pseudo-op used in PIC code"));
5239 /* Quiet this warning. */
5240 mips_frame_reg_valid
= 1;
5242 if (! mips_cprestore_valid
)
5244 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5245 /* Quiet this warning. */
5246 mips_cprestore_valid
= 1;
5248 if (mips_opts
.noreorder
)
5249 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5251 expr1
.X_add_number
= mips_cprestore_offset
;
5252 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5253 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5254 mips_gp_register
, mips_frame_reg
);
5258 else if (mips_pic
== EMBEDDED_PIC
)
5260 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5261 /* The linker may expand the call to a longer sequence which
5262 uses $at, so we must break rather than return. */
5287 /* Itbl support may require additional care here. */
5292 /* Itbl support may require additional care here. */
5297 /* Itbl support may require additional care here. */
5302 /* Itbl support may require additional care here. */
5314 if (mips_arch
== CPU_R4650
)
5316 as_bad (_("opcode not supported on this processor"));
5320 /* Itbl support may require additional care here. */
5325 /* Itbl support may require additional care here. */
5330 /* Itbl support may require additional care here. */
5350 if (breg
== treg
|| coproc
|| lr
)
5372 /* Itbl support may require additional care here. */
5377 /* Itbl support may require additional care here. */
5382 /* Itbl support may require additional care here. */
5387 /* Itbl support may require additional care here. */
5403 if (mips_arch
== CPU_R4650
)
5405 as_bad (_("opcode not supported on this processor"));
5410 /* Itbl support may require additional care here. */
5414 /* Itbl support may require additional care here. */
5419 /* Itbl support may require additional care here. */
5431 /* Itbl support may require additional care here. */
5432 if (mask
== M_LWC1_AB
5433 || mask
== M_SWC1_AB
5434 || mask
== M_LDC1_AB
5435 || mask
== M_SDC1_AB
5444 /* For embedded PIC, we allow loads where the offset is calculated
5445 by subtracting a symbol in the current segment from an unknown
5446 symbol, relative to a base register, e.g.:
5447 <op> $treg, <sym>-<localsym>($breg)
5448 This is used by the compiler for switch statements. */
5449 if (mips_pic
== EMBEDDED_PIC
5450 && offset_expr
.X_op
== O_subtract
5451 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5452 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5453 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5455 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5459 && (offset_expr
.X_add_number
== 0
5460 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5462 /* For this case, we output the instructions:
5463 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5464 addiu $tempreg,$tempreg,$breg
5465 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5466 If the relocation would fit entirely in 16 bits, it would be
5468 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5469 instead, but that seems quite difficult. */
5470 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5471 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5472 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5473 ((bfd_arch_bits_per_address (stdoutput
) == 32
5474 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5475 ? "addu" : "daddu"),
5476 "d,v,t", tempreg
, tempreg
, breg
);
5477 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5478 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5484 if (offset_expr
.X_op
!= O_constant
5485 && offset_expr
.X_op
!= O_symbol
)
5487 as_bad (_("expression too complex"));
5488 offset_expr
.X_op
= O_constant
;
5491 /* A constant expression in PIC code can be handled just as it
5492 is in non PIC code. */
5493 if (mips_pic
== NO_PIC
5494 || offset_expr
.X_op
== O_constant
)
5498 /* If this is a reference to a GP relative symbol, and there
5499 is no base register, we want
5500 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5501 Otherwise, if there is no base register, we want
5502 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5503 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5504 If we have a constant, we need two instructions anyhow,
5505 so we always use the latter form.
5507 If we have a base register, and this is a reference to a
5508 GP relative symbol, we want
5509 addu $tempreg,$breg,$gp
5510 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5512 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5513 addu $tempreg,$tempreg,$breg
5514 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5515 With a constant we always use the latter case.
5517 With 64bit address space and no base register and $at usable,
5519 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5520 lui $at,<sym> (BFD_RELOC_HI16_S)
5521 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5524 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5525 If we have a base register, we want
5526 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5527 lui $at,<sym> (BFD_RELOC_HI16_S)
5528 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5532 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5534 Without $at we can't generate the optimal path for superscalar
5535 processors here since this would require two temporary registers.
5536 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5537 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5539 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5541 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5542 If we have a base register, we want
5543 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5544 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5546 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5548 daddu $tempreg,$tempreg,$breg
5549 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5551 If we have 64-bit addresses, as an optimization, for
5552 addresses which are 32-bit constants (e.g. kseg0/kseg1
5553 addresses) we fall back to the 32-bit address generation
5554 mechanism since it is more efficient. Note that due to
5555 the signed offset used by memory operations, the 32-bit
5556 range is shifted down by 32768 here. This code should
5557 probably attempt to generate 64-bit constants more
5558 efficiently in general.
5560 if (HAVE_64BIT_ADDRESSES
5561 && !(offset_expr
.X_op
== O_constant
5562 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5566 /* We don't do GP optimization for now because RELAX_ENCODE can't
5567 hold the data for such large chunks. */
5569 if (used_at
== 0 && ! mips_opts
.noat
)
5571 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5572 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5573 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5574 AT
, (int) BFD_RELOC_HI16_S
);
5575 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5576 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5578 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5579 "d,v,t", AT
, AT
, breg
);
5580 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5581 "d,w,<", tempreg
, tempreg
, 0);
5582 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5583 "d,v,t", tempreg
, tempreg
, AT
);
5584 macro_build (p
, &icnt
, &offset_expr
, s
,
5585 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5590 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5591 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5592 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5593 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5594 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5595 "d,w,<", tempreg
, tempreg
, 16);
5596 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5597 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5598 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5599 "d,w,<", tempreg
, tempreg
, 16);
5601 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5602 "d,v,t", tempreg
, tempreg
, breg
);
5603 macro_build (p
, &icnt
, &offset_expr
, s
,
5604 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5612 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5613 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5618 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5619 treg
, (int) BFD_RELOC_GPREL16
,
5621 p
= frag_var (rs_machine_dependent
, 8, 0,
5622 RELAX_ENCODE (4, 8, 0, 4, 0,
5623 (mips_opts
.warn_about_macros
5625 && mips_opts
.noat
))),
5626 offset_expr
.X_add_symbol
, 0, NULL
);
5629 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5632 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5633 (int) BFD_RELOC_LO16
, tempreg
);
5637 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5638 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5643 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5644 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5645 "d,v,t", tempreg
, breg
, mips_gp_register
);
5646 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5647 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5648 p
= frag_var (rs_machine_dependent
, 12, 0,
5649 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5650 offset_expr
.X_add_symbol
, 0, NULL
);
5652 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5655 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5656 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5657 "d,v,t", tempreg
, tempreg
, breg
);
5660 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5661 (int) BFD_RELOC_LO16
, tempreg
);
5664 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5667 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5669 /* If this is a reference to an external symbol, we want
5670 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5672 <op> $treg,0($tempreg)
5674 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5676 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5677 <op> $treg,0($tempreg)
5678 If we have NewABI, we want
5679 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5680 If there is a base register, we add it to $tempreg before
5681 the <op>. If there is a constant, we stick it in the
5682 <op> instruction. We don't handle constants larger than
5683 16 bits, because we have no way to load the upper 16 bits
5684 (actually, we could handle them for the subset of cases
5685 in which we are not using $at). */
5686 assert (offset_expr
.X_op
== O_symbol
);
5687 expr1
.X_add_number
= offset_expr
.X_add_number
;
5688 offset_expr
.X_add_number
= 0;
5690 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5691 if (expr1
.X_add_number
< -0x8000
5692 || expr1
.X_add_number
>= 0x8000)
5693 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5695 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5696 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
5697 (int) lw_reloc_type
, mips_gp_register
);
5698 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5699 p
= frag_var (rs_machine_dependent
, 4, 0,
5700 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5701 offset_expr
.X_add_symbol
, 0, NULL
);
5702 macro_build (p
, &icnt
, &offset_expr
,
5703 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5704 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5706 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5707 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5708 "d,v,t", tempreg
, tempreg
, breg
);
5709 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5710 (int) BFD_RELOC_LO16
, tempreg
);
5712 else if (mips_pic
== SVR4_PIC
)
5717 /* If this is a reference to an external symbol, we want
5718 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5719 addu $tempreg,$tempreg,$gp
5720 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5721 <op> $treg,0($tempreg)
5723 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5725 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5726 <op> $treg,0($tempreg)
5727 If there is a base register, we add it to $tempreg before
5728 the <op>. If there is a constant, we stick it in the
5729 <op> instruction. We don't handle constants larger than
5730 16 bits, because we have no way to load the upper 16 bits
5731 (actually, we could handle them for the subset of cases
5732 in which we are not using $at).
5735 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5736 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5737 <op> $treg,0($tempreg)
5739 assert (offset_expr
.X_op
== O_symbol
);
5740 expr1
.X_add_number
= offset_expr
.X_add_number
;
5741 offset_expr
.X_add_number
= 0;
5742 if (expr1
.X_add_number
< -0x8000
5743 || expr1
.X_add_number
>= 0x8000)
5744 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5747 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5748 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5749 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
5751 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5752 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5753 "t,r,j", tempreg
, tempreg
,
5754 BFD_RELOC_MIPS_GOT_OFST
);
5756 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5757 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5758 "d,v,t", tempreg
, tempreg
, breg
);
5759 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5760 (int) BFD_RELOC_LO16
, tempreg
);
5767 if (reg_needs_delay (mips_gp_register
))
5772 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5773 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5774 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5775 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5776 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5777 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5778 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5779 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5781 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5782 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5783 offset_expr
.X_add_symbol
, 0, NULL
);
5786 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5789 macro_build (p
, &icnt
, &offset_expr
,
5790 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5791 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
5794 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5796 macro_build (p
, &icnt
, &offset_expr
,
5797 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5798 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5800 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5801 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5802 "d,v,t", tempreg
, tempreg
, breg
);
5803 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5804 (int) BFD_RELOC_LO16
, tempreg
);
5806 else if (mips_pic
== EMBEDDED_PIC
)
5808 /* If there is no base register, we want
5809 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5810 If there is a base register, we want
5811 addu $tempreg,$breg,$gp
5812 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5814 assert (offset_expr
.X_op
== O_symbol
);
5817 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5818 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
5823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5824 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5825 "d,v,t", tempreg
, breg
, mips_gp_register
);
5826 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5827 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5840 load_register (&icnt
, treg
, &imm_expr
, 0);
5844 load_register (&icnt
, treg
, &imm_expr
, 1);
5848 if (imm_expr
.X_op
== O_constant
)
5850 load_register (&icnt
, AT
, &imm_expr
, 0);
5851 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5852 "mtc1", "t,G", AT
, treg
);
5857 assert (offset_expr
.X_op
== O_symbol
5858 && strcmp (segment_name (S_GET_SEGMENT
5859 (offset_expr
.X_add_symbol
)),
5861 && offset_expr
.X_add_number
== 0);
5862 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5863 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
5868 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5869 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5870 order 32 bits of the value and the low order 32 bits are either
5871 zero or in OFFSET_EXPR. */
5872 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5874 if (HAVE_64BIT_GPRS
)
5875 load_register (&icnt
, treg
, &imm_expr
, 1);
5880 if (target_big_endian
)
5892 load_register (&icnt
, hreg
, &imm_expr
, 0);
5895 if (offset_expr
.X_op
== O_absent
)
5896 move_register (&icnt
, lreg
, 0);
5899 assert (offset_expr
.X_op
== O_constant
);
5900 load_register (&icnt
, lreg
, &offset_expr
, 0);
5907 /* We know that sym is in the .rdata section. First we get the
5908 upper 16 bits of the address. */
5909 if (mips_pic
== NO_PIC
)
5911 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
5913 else if (mips_pic
== SVR4_PIC
)
5915 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5916 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5917 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
5920 else if (mips_pic
== EMBEDDED_PIC
)
5922 /* For embedded PIC we pick up the entire address off $gp in
5923 a single instruction. */
5924 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5925 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
5926 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5927 offset_expr
.X_op
= O_constant
;
5928 offset_expr
.X_add_number
= 0;
5933 /* Now we load the register(s). */
5934 if (HAVE_64BIT_GPRS
)
5935 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5936 treg
, (int) BFD_RELOC_LO16
, AT
);
5939 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5940 treg
, (int) BFD_RELOC_LO16
, AT
);
5943 /* FIXME: How in the world do we deal with the possible
5945 offset_expr
.X_add_number
+= 4;
5946 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5947 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5951 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5952 does not become a variant frag. */
5953 frag_wane (frag_now
);
5959 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5960 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5961 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5962 the value and the low order 32 bits are either zero or in
5964 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5966 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5967 if (HAVE_64BIT_FPRS
)
5969 assert (HAVE_64BIT_GPRS
);
5970 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5971 "dmtc1", "t,S", AT
, treg
);
5975 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5976 "mtc1", "t,G", AT
, treg
+ 1);
5977 if (offset_expr
.X_op
== O_absent
)
5978 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5979 "mtc1", "t,G", 0, treg
);
5982 assert (offset_expr
.X_op
== O_constant
);
5983 load_register (&icnt
, AT
, &offset_expr
, 0);
5984 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5985 "mtc1", "t,G", AT
, treg
);
5991 assert (offset_expr
.X_op
== O_symbol
5992 && offset_expr
.X_add_number
== 0);
5993 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5994 if (strcmp (s
, ".lit8") == 0)
5996 if (mips_opts
.isa
!= ISA_MIPS1
)
5998 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5999 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6003 breg
= mips_gp_register
;
6004 r
= BFD_RELOC_MIPS_LITERAL
;
6009 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6010 if (mips_pic
== SVR4_PIC
)
6011 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6012 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6013 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6017 /* FIXME: This won't work for a 64 bit address. */
6018 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6021 if (mips_opts
.isa
!= ISA_MIPS1
)
6023 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6024 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6026 /* To avoid confusion in tc_gen_reloc, we must ensure
6027 that this does not become a variant frag. */
6028 frag_wane (frag_now
);
6039 if (mips_arch
== CPU_R4650
)
6041 as_bad (_("opcode not supported on this processor"));
6044 /* Even on a big endian machine $fn comes before $fn+1. We have
6045 to adjust when loading from memory. */
6048 assert (mips_opts
.isa
== ISA_MIPS1
);
6049 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6050 target_big_endian
? treg
+ 1 : treg
,
6052 /* FIXME: A possible overflow which I don't know how to deal
6054 offset_expr
.X_add_number
+= 4;
6055 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6056 target_big_endian
? treg
: treg
+ 1,
6059 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6060 does not become a variant frag. */
6061 frag_wane (frag_now
);
6070 * The MIPS assembler seems to check for X_add_number not
6071 * being double aligned and generating:
6074 * addiu at,at,%lo(foo+1)
6077 * But, the resulting address is the same after relocation so why
6078 * generate the extra instruction?
6080 if (mips_arch
== CPU_R4650
)
6082 as_bad (_("opcode not supported on this processor"));
6085 /* Itbl support may require additional care here. */
6087 if (mips_opts
.isa
!= ISA_MIPS1
)
6098 if (mips_arch
== CPU_R4650
)
6100 as_bad (_("opcode not supported on this processor"));
6104 if (mips_opts
.isa
!= ISA_MIPS1
)
6112 /* Itbl support may require additional care here. */
6117 if (HAVE_64BIT_GPRS
)
6128 if (HAVE_64BIT_GPRS
)
6138 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6139 loads for the case of doing a pair of loads to simulate an 'ld'.
6140 This is not currently done by the compiler, and assembly coders
6141 writing embedded-pic code can cope. */
6143 if (offset_expr
.X_op
!= O_symbol
6144 && offset_expr
.X_op
!= O_constant
)
6146 as_bad (_("expression too complex"));
6147 offset_expr
.X_op
= O_constant
;
6150 /* Even on a big endian machine $fn comes before $fn+1. We have
6151 to adjust when loading from memory. We set coproc if we must
6152 load $fn+1 first. */
6153 /* Itbl support may require additional care here. */
6154 if (! target_big_endian
)
6157 if (mips_pic
== NO_PIC
6158 || offset_expr
.X_op
== O_constant
)
6162 /* If this is a reference to a GP relative symbol, we want
6163 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6164 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6165 If we have a base register, we use this
6167 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6168 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6169 If this is not a GP relative symbol, we want
6170 lui $at,<sym> (BFD_RELOC_HI16_S)
6171 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6172 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6173 If there is a base register, we add it to $at after the
6174 lui instruction. If there is a constant, we always use
6176 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6177 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6189 tempreg
= mips_gp_register
;
6196 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6197 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6198 "d,v,t", AT
, breg
, mips_gp_register
);
6204 /* Itbl support may require additional care here. */
6205 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6206 coproc
? treg
+ 1 : treg
,
6207 (int) BFD_RELOC_GPREL16
, tempreg
);
6208 offset_expr
.X_add_number
+= 4;
6210 /* Set mips_optimize to 2 to avoid inserting an
6212 hold_mips_optimize
= mips_optimize
;
6214 /* Itbl support may require additional care here. */
6215 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6216 coproc
? treg
: treg
+ 1,
6217 (int) BFD_RELOC_GPREL16
, tempreg
);
6218 mips_optimize
= hold_mips_optimize
;
6220 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6221 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6222 used_at
&& mips_opts
.noat
),
6223 offset_expr
.X_add_symbol
, 0, NULL
);
6225 /* We just generated two relocs. When tc_gen_reloc
6226 handles this case, it will skip the first reloc and
6227 handle the second. The second reloc already has an
6228 extra addend of 4, which we added above. We must
6229 subtract it out, and then subtract another 4 to make
6230 the first reloc come out right. The second reloc
6231 will come out right because we are going to add 4 to
6232 offset_expr when we build its instruction below.
6234 If we have a symbol, then we don't want to include
6235 the offset, because it will wind up being included
6236 when we generate the reloc. */
6238 if (offset_expr
.X_op
== O_constant
)
6239 offset_expr
.X_add_number
-= 8;
6242 offset_expr
.X_add_number
= -4;
6243 offset_expr
.X_op
= O_constant
;
6246 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6251 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6252 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6253 "d,v,t", AT
, breg
, AT
);
6257 /* Itbl support may require additional care here. */
6258 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6259 coproc
? treg
+ 1 : treg
,
6260 (int) BFD_RELOC_LO16
, AT
);
6263 /* FIXME: How do we handle overflow here? */
6264 offset_expr
.X_add_number
+= 4;
6265 /* Itbl support may require additional care here. */
6266 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6267 coproc
? treg
: treg
+ 1,
6268 (int) BFD_RELOC_LO16
, AT
);
6270 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6274 /* If this is a reference to an external symbol, we want
6275 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6280 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6282 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6283 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6284 If there is a base register we add it to $at before the
6285 lwc1 instructions. If there is a constant we include it
6286 in the lwc1 instructions. */
6288 expr1
.X_add_number
= offset_expr
.X_add_number
;
6289 offset_expr
.X_add_number
= 0;
6290 if (expr1
.X_add_number
< -0x8000
6291 || expr1
.X_add_number
>= 0x8000 - 4)
6292 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6297 frag_grow (24 + off
);
6298 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6299 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
6300 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6303 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6304 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6305 "d,v,t", AT
, breg
, AT
);
6306 /* Itbl support may require additional care here. */
6307 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6308 coproc
? treg
+ 1 : treg
,
6309 (int) BFD_RELOC_LO16
, AT
);
6310 expr1
.X_add_number
+= 4;
6312 /* Set mips_optimize to 2 to avoid inserting an undesired
6314 hold_mips_optimize
= mips_optimize
;
6316 /* Itbl support may require additional care here. */
6317 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6318 coproc
? treg
: treg
+ 1,
6319 (int) BFD_RELOC_LO16
, AT
);
6320 mips_optimize
= hold_mips_optimize
;
6322 (void) frag_var (rs_machine_dependent
, 0, 0,
6323 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6324 offset_expr
.X_add_symbol
, 0, NULL
);
6326 else if (mips_pic
== SVR4_PIC
)
6331 /* If this is a reference to an external symbol, we want
6332 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6334 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6339 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6341 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6342 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6343 If there is a base register we add it to $at before the
6344 lwc1 instructions. If there is a constant we include it
6345 in the lwc1 instructions. */
6347 expr1
.X_add_number
= offset_expr
.X_add_number
;
6348 offset_expr
.X_add_number
= 0;
6349 if (expr1
.X_add_number
< -0x8000
6350 || expr1
.X_add_number
>= 0x8000 - 4)
6351 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6352 if (reg_needs_delay (mips_gp_register
))
6361 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6362 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6363 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6364 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6365 "d,v,t", AT
, AT
, mips_gp_register
);
6366 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6367 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6368 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6369 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6371 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6372 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6373 "d,v,t", AT
, breg
, AT
);
6374 /* Itbl support may require additional care here. */
6375 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6376 coproc
? treg
+ 1 : treg
,
6377 (int) BFD_RELOC_LO16
, AT
);
6378 expr1
.X_add_number
+= 4;
6380 /* Set mips_optimize to 2 to avoid inserting an undesired
6382 hold_mips_optimize
= mips_optimize
;
6384 /* Itbl support may require additional care here. */
6385 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6386 coproc
? treg
: treg
+ 1,
6387 (int) BFD_RELOC_LO16
, AT
);
6388 mips_optimize
= hold_mips_optimize
;
6389 expr1
.X_add_number
-= 4;
6391 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6392 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6393 8 + gpdel
+ off
, 1, 0),
6394 offset_expr
.X_add_symbol
, 0, NULL
);
6397 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6400 macro_build (p
, &icnt
, &offset_expr
,
6401 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6402 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6405 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6409 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6410 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6411 "d,v,t", AT
, breg
, AT
);
6414 /* Itbl support may require additional care here. */
6415 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6416 coproc
? treg
+ 1 : treg
,
6417 (int) BFD_RELOC_LO16
, AT
);
6419 expr1
.X_add_number
+= 4;
6421 /* Set mips_optimize to 2 to avoid inserting an undesired
6423 hold_mips_optimize
= mips_optimize
;
6425 /* Itbl support may require additional care here. */
6426 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6427 coproc
? treg
: treg
+ 1,
6428 (int) BFD_RELOC_LO16
, AT
);
6429 mips_optimize
= hold_mips_optimize
;
6431 else if (mips_pic
== EMBEDDED_PIC
)
6433 /* If there is no base register, we use
6434 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6435 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6436 If we have a base register, we use
6438 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6439 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6443 tempreg
= mips_gp_register
;
6448 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6449 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6450 "d,v,t", AT
, breg
, mips_gp_register
);
6455 /* Itbl support may require additional care here. */
6456 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6457 coproc
? treg
+ 1 : treg
,
6458 (int) BFD_RELOC_GPREL16
, tempreg
);
6459 offset_expr
.X_add_number
+= 4;
6460 /* Itbl support may require additional care here. */
6461 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6462 coproc
? treg
: treg
+ 1,
6463 (int) BFD_RELOC_GPREL16
, tempreg
);
6479 assert (HAVE_32BIT_ADDRESSES
);
6480 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6481 (int) BFD_RELOC_LO16
, breg
);
6482 offset_expr
.X_add_number
+= 4;
6483 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6484 (int) BFD_RELOC_LO16
, breg
);
6487 /* New code added to support COPZ instructions.
6488 This code builds table entries out of the macros in mip_opcodes.
6489 R4000 uses interlocks to handle coproc delays.
6490 Other chips (like the R3000) require nops to be inserted for delays.
6492 FIXME: Currently, we require that the user handle delays.
6493 In order to fill delay slots for non-interlocked chips,
6494 we must have a way to specify delays based on the coprocessor.
6495 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6496 What are the side-effects of the cop instruction?
6497 What cache support might we have and what are its effects?
6498 Both coprocessor & memory require delays. how long???
6499 What registers are read/set/modified?
6501 If an itbl is provided to interpret cop instructions,
6502 this knowledge can be encoded in the itbl spec. */
6516 /* For now we just do C (same as Cz). The parameter will be
6517 stored in insn_opcode by mips_ip. */
6518 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6523 move_register (&icnt
, dreg
, sreg
);
6526 #ifdef LOSING_COMPILER
6528 /* Try and see if this is a new itbl instruction.
6529 This code builds table entries out of the macros in mip_opcodes.
6530 FIXME: For now we just assemble the expression and pass it's
6531 value along as a 32-bit immediate.
6532 We may want to have the assembler assemble this value,
6533 so that we gain the assembler's knowledge of delay slots,
6535 Would it be more efficient to use mask (id) here? */
6536 if (itbl_have_entries
6537 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6539 s
= ip
->insn_mo
->name
;
6541 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6542 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6549 as_warn (_("Macro used $at after \".set noat\""));
6554 struct mips_cl_insn
*ip
;
6556 register int treg
, sreg
, dreg
, breg
;
6572 bfd_reloc_code_real_type r
;
6575 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6576 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6577 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6578 mask
= ip
->insn_mo
->mask
;
6580 expr1
.X_op
= O_constant
;
6581 expr1
.X_op_symbol
= NULL
;
6582 expr1
.X_add_symbol
= NULL
;
6583 expr1
.X_add_number
= 1;
6587 #endif /* LOSING_COMPILER */
6592 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6593 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6594 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6601 /* The MIPS assembler some times generates shifts and adds. I'm
6602 not trying to be that fancy. GCC should do this for us
6604 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6605 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6606 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6607 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6621 mips_emit_delays (true);
6622 ++mips_opts
.noreorder
;
6623 mips_any_noreorder
= 1;
6625 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6626 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6627 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6628 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6630 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6631 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6632 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6635 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6636 "s,t,q", dreg
, AT
, 6);
6639 expr1
.X_add_number
= 8;
6640 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6642 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6644 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6647 --mips_opts
.noreorder
;
6648 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6661 mips_emit_delays (true);
6662 ++mips_opts
.noreorder
;
6663 mips_any_noreorder
= 1;
6665 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6666 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6667 dbl
? "dmultu" : "multu",
6668 "s,t", sreg
, imm
? AT
: treg
);
6669 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6674 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6678 expr1
.X_add_number
= 8;
6679 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6680 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6682 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6685 --mips_opts
.noreorder
;
6689 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6690 "d,v,t", AT
, 0, treg
);
6691 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6692 "d,t,s", AT
, sreg
, AT
);
6693 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6694 "d,t,s", dreg
, sreg
, treg
);
6695 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6696 "d,v,t", dreg
, dreg
, AT
);
6700 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6701 "d,v,t", AT
, 0, treg
);
6702 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6703 "d,t,s", AT
, sreg
, AT
);
6704 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6705 "d,t,s", dreg
, sreg
, treg
);
6706 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6707 "d,v,t", dreg
, dreg
, AT
);
6714 if (imm_expr
.X_op
!= O_constant
)
6715 as_bad (_("rotate count too large"));
6716 rot
= imm_expr
.X_add_number
& 0x3f;
6718 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
6719 "d,w,<", dreg
, sreg
, 0);
6724 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6725 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6727 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6728 "d,w,<", AT
, sreg
, rot
);
6729 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6730 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6731 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6732 "d,v,t", dreg
, dreg
, AT
);
6741 if (imm_expr
.X_op
!= O_constant
)
6742 as_bad (_("rotate count too large"));
6743 rot
= imm_expr
.X_add_number
& 0x1f;
6745 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6746 "d,w,<", dreg
, sreg
, 0);
6749 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6750 "d,w,<", AT
, sreg
, rot
);
6751 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6752 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6753 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6754 "d,v,t", dreg
, dreg
, AT
);
6760 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6761 "d,v,t", AT
, 0, treg
);
6762 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6763 "d,t,s", AT
, sreg
, AT
);
6764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6765 "d,t,s", dreg
, sreg
, treg
);
6766 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6767 "d,v,t", dreg
, dreg
, AT
);
6771 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6772 "d,v,t", AT
, 0, treg
);
6773 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6774 "d,t,s", AT
, sreg
, AT
);
6775 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6776 "d,t,s", dreg
, sreg
, treg
);
6777 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6778 "d,v,t", dreg
, dreg
, AT
);
6785 if (imm_expr
.X_op
!= O_constant
)
6786 as_bad (_("rotate count too large"));
6787 rot
= imm_expr
.X_add_number
& 0x3f;
6789 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
6790 "d,w,<", dreg
, sreg
, 0);
6795 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6796 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6798 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6799 "d,w,<", AT
, sreg
, rot
);
6800 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6801 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6802 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6803 "d,v,t", dreg
, dreg
, AT
);
6812 if (imm_expr
.X_op
!= O_constant
)
6813 as_bad (_("rotate count too large"));
6814 rot
= imm_expr
.X_add_number
& 0x1f;
6816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6817 "d,w,<", dreg
, sreg
, 0);
6820 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6821 "d,w,<", AT
, sreg
, rot
);
6822 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6823 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6824 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6825 "d,v,t", dreg
, dreg
, AT
);
6831 if (mips_arch
== CPU_R4650
)
6833 as_bad (_("opcode not supported on this processor"));
6836 assert (mips_opts
.isa
== ISA_MIPS1
);
6837 /* Even on a big endian machine $fn comes before $fn+1. We have
6838 to adjust when storing to memory. */
6839 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6840 target_big_endian
? treg
+ 1 : treg
,
6841 (int) BFD_RELOC_LO16
, breg
);
6842 offset_expr
.X_add_number
+= 4;
6843 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6844 target_big_endian
? treg
: treg
+ 1,
6845 (int) BFD_RELOC_LO16
, breg
);
6850 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6851 treg
, (int) BFD_RELOC_LO16
);
6853 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6854 sreg
, (int) BFD_RELOC_LO16
);
6857 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6858 "d,v,t", dreg
, sreg
, treg
);
6859 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6860 dreg
, (int) BFD_RELOC_LO16
);
6865 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6867 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6868 sreg
, (int) BFD_RELOC_LO16
);
6873 as_warn (_("Instruction %s: result is always false"),
6875 move_register (&icnt
, dreg
, 0);
6878 if (imm_expr
.X_op
== O_constant
6879 && imm_expr
.X_add_number
>= 0
6880 && imm_expr
.X_add_number
< 0x10000)
6882 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6883 sreg
, (int) BFD_RELOC_LO16
);
6886 else if (imm_expr
.X_op
== O_constant
6887 && imm_expr
.X_add_number
> -0x8000
6888 && imm_expr
.X_add_number
< 0)
6890 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6891 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6892 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6893 "t,r,j", dreg
, sreg
,
6894 (int) BFD_RELOC_LO16
);
6899 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6900 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6901 "d,v,t", dreg
, sreg
, AT
);
6904 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6905 (int) BFD_RELOC_LO16
);
6910 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6916 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6918 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6919 (int) BFD_RELOC_LO16
);
6922 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6924 if (imm_expr
.X_op
== O_constant
6925 && imm_expr
.X_add_number
>= -0x8000
6926 && imm_expr
.X_add_number
< 0x8000)
6928 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6929 mask
== M_SGE_I
? "slti" : "sltiu",
6930 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6935 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6936 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6937 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
6941 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6942 (int) BFD_RELOC_LO16
);
6947 case M_SGT
: /* sreg > treg <==> treg < sreg */
6953 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6957 case M_SGT_I
: /* sreg > I <==> I < sreg */
6963 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6964 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6968 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6974 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6976 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6977 (int) BFD_RELOC_LO16
);
6980 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6986 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6987 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6989 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6990 (int) BFD_RELOC_LO16
);
6994 if (imm_expr
.X_op
== O_constant
6995 && imm_expr
.X_add_number
>= -0x8000
6996 && imm_expr
.X_add_number
< 0x8000)
6998 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6999 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7002 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7003 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7008 if (imm_expr
.X_op
== O_constant
7009 && imm_expr
.X_add_number
>= -0x8000
7010 && imm_expr
.X_add_number
< 0x8000)
7012 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7013 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7016 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7017 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7018 "d,v,t", dreg
, sreg
, AT
);
7023 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7024 "d,v,t", dreg
, 0, treg
);
7026 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7027 "d,v,t", dreg
, 0, sreg
);
7030 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7031 "d,v,t", dreg
, sreg
, treg
);
7032 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7033 "d,v,t", dreg
, 0, dreg
);
7038 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7040 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7041 "d,v,t", dreg
, 0, sreg
);
7046 as_warn (_("Instruction %s: result is always true"),
7048 macro_build ((char *) NULL
, &icnt
, &expr1
,
7049 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7050 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7053 if (imm_expr
.X_op
== O_constant
7054 && imm_expr
.X_add_number
>= 0
7055 && imm_expr
.X_add_number
< 0x10000)
7057 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7058 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7061 else if (imm_expr
.X_op
== O_constant
7062 && imm_expr
.X_add_number
> -0x8000
7063 && imm_expr
.X_add_number
< 0)
7065 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7066 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7067 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7068 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7073 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7074 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7075 "d,v,t", dreg
, sreg
, AT
);
7078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7079 "d,v,t", dreg
, 0, dreg
);
7087 if (imm_expr
.X_op
== O_constant
7088 && imm_expr
.X_add_number
> -0x8000
7089 && imm_expr
.X_add_number
<= 0x8000)
7091 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7092 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7093 dbl
? "daddi" : "addi",
7094 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7097 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7098 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7099 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7105 if (imm_expr
.X_op
== O_constant
7106 && imm_expr
.X_add_number
> -0x8000
7107 && imm_expr
.X_add_number
<= 0x8000)
7109 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7110 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7111 dbl
? "daddiu" : "addiu",
7112 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7115 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7116 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7117 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7138 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7145 assert (mips_opts
.isa
== ISA_MIPS1
);
7146 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7147 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7150 * Is the double cfc1 instruction a bug in the mips assembler;
7151 * or is there a reason for it?
7153 mips_emit_delays (true);
7154 ++mips_opts
.noreorder
;
7155 mips_any_noreorder
= 1;
7156 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7160 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7161 expr1
.X_add_number
= 3;
7162 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7163 (int) BFD_RELOC_LO16
);
7164 expr1
.X_add_number
= 2;
7165 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7166 (int) BFD_RELOC_LO16
);
7167 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7169 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7170 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7171 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7172 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7174 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7175 --mips_opts
.noreorder
;
7184 if (offset_expr
.X_add_number
>= 0x7fff)
7185 as_bad (_("operand overflow"));
7186 /* avoid load delay */
7187 if (! target_big_endian
)
7188 ++offset_expr
.X_add_number
;
7189 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7190 (int) BFD_RELOC_LO16
, breg
);
7191 if (! target_big_endian
)
7192 --offset_expr
.X_add_number
;
7194 ++offset_expr
.X_add_number
;
7195 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7196 (int) BFD_RELOC_LO16
, breg
);
7197 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7199 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7213 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7214 as_bad (_("operand overflow"));
7215 if (! target_big_endian
)
7216 offset_expr
.X_add_number
+= off
;
7217 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7218 (int) BFD_RELOC_LO16
, breg
);
7219 if (! target_big_endian
)
7220 offset_expr
.X_add_number
-= off
;
7222 offset_expr
.X_add_number
+= off
;
7223 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7224 (int) BFD_RELOC_LO16
, breg
);
7238 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7240 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7241 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7242 "d,v,t", AT
, AT
, breg
);
7243 if (! target_big_endian
)
7244 expr1
.X_add_number
= off
;
7246 expr1
.X_add_number
= 0;
7247 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7248 (int) BFD_RELOC_LO16
, AT
);
7249 if (! target_big_endian
)
7250 expr1
.X_add_number
= 0;
7252 expr1
.X_add_number
= off
;
7253 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7254 (int) BFD_RELOC_LO16
, AT
);
7260 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7262 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7263 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7264 "d,v,t", AT
, AT
, breg
);
7265 if (target_big_endian
)
7266 expr1
.X_add_number
= 0;
7267 macro_build ((char *) NULL
, &icnt
, &expr1
,
7268 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7269 (int) BFD_RELOC_LO16
, AT
);
7270 if (target_big_endian
)
7271 expr1
.X_add_number
= 1;
7273 expr1
.X_add_number
= 0;
7274 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7275 (int) BFD_RELOC_LO16
, AT
);
7276 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7278 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7283 if (offset_expr
.X_add_number
>= 0x7fff)
7284 as_bad (_("operand overflow"));
7285 if (target_big_endian
)
7286 ++offset_expr
.X_add_number
;
7287 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7288 (int) BFD_RELOC_LO16
, breg
);
7289 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7291 if (target_big_endian
)
7292 --offset_expr
.X_add_number
;
7294 ++offset_expr
.X_add_number
;
7295 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7296 (int) BFD_RELOC_LO16
, breg
);
7309 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7310 as_bad (_("operand overflow"));
7311 if (! target_big_endian
)
7312 offset_expr
.X_add_number
+= off
;
7313 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7314 (int) BFD_RELOC_LO16
, breg
);
7315 if (! target_big_endian
)
7316 offset_expr
.X_add_number
-= off
;
7318 offset_expr
.X_add_number
+= off
;
7319 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7320 (int) BFD_RELOC_LO16
, breg
);
7334 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7337 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7338 "d,v,t", AT
, AT
, breg
);
7339 if (! target_big_endian
)
7340 expr1
.X_add_number
= off
;
7342 expr1
.X_add_number
= 0;
7343 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7344 (int) BFD_RELOC_LO16
, AT
);
7345 if (! target_big_endian
)
7346 expr1
.X_add_number
= 0;
7348 expr1
.X_add_number
= off
;
7349 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7350 (int) BFD_RELOC_LO16
, AT
);
7355 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7357 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7358 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7359 "d,v,t", AT
, AT
, breg
);
7360 if (! target_big_endian
)
7361 expr1
.X_add_number
= 0;
7362 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7363 (int) BFD_RELOC_LO16
, AT
);
7364 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7366 if (! target_big_endian
)
7367 expr1
.X_add_number
= 1;
7369 expr1
.X_add_number
= 0;
7370 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7371 (int) BFD_RELOC_LO16
, AT
);
7372 if (! target_big_endian
)
7373 expr1
.X_add_number
= 0;
7375 expr1
.X_add_number
= 1;
7376 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7377 (int) BFD_RELOC_LO16
, AT
);
7378 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7380 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7385 /* FIXME: Check if this is one of the itbl macros, since they
7386 are added dynamically. */
7387 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7391 as_warn (_("Macro used $at after \".set noat\""));
7394 /* Implement macros in mips16 mode. */
7398 struct mips_cl_insn
*ip
;
7401 int xreg
, yreg
, zreg
, tmp
;
7405 const char *s
, *s2
, *s3
;
7407 mask
= ip
->insn_mo
->mask
;
7409 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7410 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7411 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7415 expr1
.X_op
= O_constant
;
7416 expr1
.X_op_symbol
= NULL
;
7417 expr1
.X_add_symbol
= NULL
;
7418 expr1
.X_add_number
= 1;
7437 mips_emit_delays (true);
7438 ++mips_opts
.noreorder
;
7439 mips_any_noreorder
= 1;
7440 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7441 dbl
? "ddiv" : "div",
7442 "0,x,y", xreg
, yreg
);
7443 expr1
.X_add_number
= 2;
7444 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7445 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7448 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7449 since that causes an overflow. We should do that as well,
7450 but I don't see how to do the comparisons without a temporary
7452 --mips_opts
.noreorder
;
7453 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7472 mips_emit_delays (true);
7473 ++mips_opts
.noreorder
;
7474 mips_any_noreorder
= 1;
7475 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7477 expr1
.X_add_number
= 2;
7478 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7479 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7481 --mips_opts
.noreorder
;
7482 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7489 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7490 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7499 if (imm_expr
.X_op
!= O_constant
)
7500 as_bad (_("Unsupported large constant"));
7501 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7502 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7503 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7507 if (imm_expr
.X_op
!= O_constant
)
7508 as_bad (_("Unsupported large constant"));
7509 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7510 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7515 if (imm_expr
.X_op
!= O_constant
)
7516 as_bad (_("Unsupported large constant"));
7517 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7518 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7541 goto do_reverse_branch
;
7545 goto do_reverse_branch
;
7557 goto do_reverse_branch
;
7568 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7570 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7597 goto do_addone_branch_i
;
7602 goto do_addone_branch_i
;
7617 goto do_addone_branch_i
;
7624 if (imm_expr
.X_op
!= O_constant
)
7625 as_bad (_("Unsupported large constant"));
7626 ++imm_expr
.X_add_number
;
7629 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7630 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7634 expr1
.X_add_number
= 0;
7635 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7637 move_register (&icnt
, xreg
, yreg
);
7638 expr1
.X_add_number
= 2;
7639 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7640 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7641 "neg", "x,w", xreg
, xreg
);
7645 /* For consistency checking, verify that all bits are specified either
7646 by the match/mask part of the instruction definition, or by the
7649 validate_mips_insn (opc
)
7650 const struct mips_opcode
*opc
;
7652 const char *p
= opc
->args
;
7654 unsigned long used_bits
= opc
->mask
;
7656 if ((used_bits
& opc
->match
) != opc
->match
)
7658 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7659 opc
->name
, opc
->args
);
7662 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7669 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7670 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7672 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7673 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7674 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7675 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7677 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7678 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7680 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7682 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7683 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7684 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7685 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7686 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7687 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7688 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7689 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7690 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7691 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7692 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7693 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7694 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7695 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7696 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7697 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7698 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7700 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7701 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7702 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7703 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7705 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7706 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7707 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7708 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7709 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7710 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7711 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7712 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7713 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7716 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7717 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7718 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7720 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7721 c
, opc
->name
, opc
->args
);
7725 if (used_bits
!= 0xffffffff)
7727 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7728 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7734 /* This routine assembles an instruction into its binary format. As a
7735 side effect, it sets one of the global variables imm_reloc or
7736 offset_reloc to the type of relocation to do if one of the operands
7737 is an address expression. */
7742 struct mips_cl_insn
*ip
;
7747 struct mips_opcode
*insn
;
7750 unsigned int lastregno
= 0;
7756 /* If the instruction contains a '.', we first try to match an instruction
7757 including the '.'. Then we try again without the '.'. */
7759 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7762 /* If we stopped on whitespace, then replace the whitespace with null for
7763 the call to hash_find. Save the character we replaced just in case we
7764 have to re-parse the instruction. */
7771 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7773 /* If we didn't find the instruction in the opcode table, try again, but
7774 this time with just the instruction up to, but not including the
7778 /* Restore the character we overwrite above (if any). */
7782 /* Scan up to the first '.' or whitespace. */
7784 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7788 /* If we did not find a '.', then we can quit now. */
7791 insn_error
= "unrecognized opcode";
7795 /* Lookup the instruction in the hash table. */
7797 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7799 insn_error
= "unrecognized opcode";
7809 assert (strcmp (insn
->name
, str
) == 0);
7811 if (OPCODE_IS_MEMBER (insn
,
7813 | (file_ase_mips16
? INSN_MIPS16
: 0)
7814 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7815 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7821 if (insn
->pinfo
!= INSN_MACRO
)
7823 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7829 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7830 && strcmp (insn
->name
, insn
[1].name
) == 0)
7839 static char buf
[100];
7840 if (mips_arch_info
->is_isa
)
7842 _("opcode not supported at this ISA level (%s)"),
7843 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7846 _("opcode not supported on this processor: %s (%s)"),
7847 mips_arch_info
->name
,
7848 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7858 ip
->insn_opcode
= insn
->match
;
7860 for (args
= insn
->args
;; ++args
)
7864 s
+= strspn (s
, " \t");
7868 case '\0': /* end of args */
7881 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7885 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7889 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7893 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7899 /* Handle optional base register.
7900 Either the base register is omitted or
7901 we must have a left paren. */
7902 /* This is dependent on the next operand specifier
7903 is a base register specification. */
7904 assert (args
[1] == 'b' || args
[1] == '5'
7905 || args
[1] == '-' || args
[1] == '4');
7909 case ')': /* these must match exactly */
7914 case '<': /* must be at least one digit */
7916 * According to the manual, if the shift amount is greater
7917 * than 31 or less than 0, then the shift amount should be
7918 * mod 32. In reality the mips assembler issues an error.
7919 * We issue a warning and mask out all but the low 5 bits.
7921 my_getExpression (&imm_expr
, s
);
7922 check_absolute_expr (ip
, &imm_expr
);
7923 if ((unsigned long) imm_expr
.X_add_number
> 31)
7925 as_warn (_("Improper shift amount (%lu)"),
7926 (unsigned long) imm_expr
.X_add_number
);
7927 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7929 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7930 imm_expr
.X_op
= O_absent
;
7934 case '>': /* shift amount minus 32 */
7935 my_getExpression (&imm_expr
, s
);
7936 check_absolute_expr (ip
, &imm_expr
);
7937 if ((unsigned long) imm_expr
.X_add_number
< 32
7938 || (unsigned long) imm_expr
.X_add_number
> 63)
7940 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7941 imm_expr
.X_op
= O_absent
;
7945 case 'k': /* cache code */
7946 case 'h': /* prefx code */
7947 my_getExpression (&imm_expr
, s
);
7948 check_absolute_expr (ip
, &imm_expr
);
7949 if ((unsigned long) imm_expr
.X_add_number
> 31)
7951 as_warn (_("Invalid value for `%s' (%lu)"),
7953 (unsigned long) imm_expr
.X_add_number
);
7954 imm_expr
.X_add_number
&= 0x1f;
7957 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7959 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7960 imm_expr
.X_op
= O_absent
;
7964 case 'c': /* break code */
7965 my_getExpression (&imm_expr
, s
);
7966 check_absolute_expr (ip
, &imm_expr
);
7967 if ((unsigned long) imm_expr
.X_add_number
> 1023)
7969 as_warn (_("Illegal break code (%lu)"),
7970 (unsigned long) imm_expr
.X_add_number
);
7971 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7973 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7974 imm_expr
.X_op
= O_absent
;
7978 case 'q': /* lower break code */
7979 my_getExpression (&imm_expr
, s
);
7980 check_absolute_expr (ip
, &imm_expr
);
7981 if ((unsigned long) imm_expr
.X_add_number
> 1023)
7983 as_warn (_("Illegal lower break code (%lu)"),
7984 (unsigned long) imm_expr
.X_add_number
);
7985 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7987 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7988 imm_expr
.X_op
= O_absent
;
7992 case 'B': /* 20-bit syscall/break code. */
7993 my_getExpression (&imm_expr
, s
);
7994 check_absolute_expr (ip
, &imm_expr
);
7995 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7996 as_warn (_("Illegal 20-bit code (%lu)"),
7997 (unsigned long) imm_expr
.X_add_number
);
7998 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7999 imm_expr
.X_op
= O_absent
;
8003 case 'C': /* Coprocessor code */
8004 my_getExpression (&imm_expr
, s
);
8005 check_absolute_expr (ip
, &imm_expr
);
8006 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8008 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8009 (unsigned long) imm_expr
.X_add_number
);
8010 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8012 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8013 imm_expr
.X_op
= O_absent
;
8017 case 'J': /* 19-bit wait code. */
8018 my_getExpression (&imm_expr
, s
);
8019 check_absolute_expr (ip
, &imm_expr
);
8020 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8021 as_warn (_("Illegal 19-bit code (%lu)"),
8022 (unsigned long) imm_expr
.X_add_number
);
8023 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8024 imm_expr
.X_op
= O_absent
;
8028 case 'P': /* Performance register */
8029 my_getExpression (&imm_expr
, s
);
8030 check_absolute_expr (ip
, &imm_expr
);
8031 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8033 as_warn (_("Invalid performance register (%lu)"),
8034 (unsigned long) imm_expr
.X_add_number
);
8035 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8037 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8038 imm_expr
.X_op
= O_absent
;
8042 case 'b': /* base register */
8043 case 'd': /* destination register */
8044 case 's': /* source register */
8045 case 't': /* target register */
8046 case 'r': /* both target and source */
8047 case 'v': /* both dest and source */
8048 case 'w': /* both dest and target */
8049 case 'E': /* coprocessor target register */
8050 case 'G': /* coprocessor destination register */
8051 case 'x': /* ignore register name */
8052 case 'z': /* must be zero register */
8053 case 'U': /* destination register (clo/clz). */
8068 while (ISDIGIT (*s
));
8070 as_bad (_("Invalid register number (%d)"), regno
);
8072 else if (*args
== 'E' || *args
== 'G')
8076 if (s
[1] == 'r' && s
[2] == 'a')
8081 else if (s
[1] == 'f' && s
[2] == 'p')
8086 else if (s
[1] == 's' && s
[2] == 'p')
8091 else if (s
[1] == 'g' && s
[2] == 'p')
8096 else if (s
[1] == 'a' && s
[2] == 't')
8101 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8106 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8111 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8116 else if (itbl_have_entries
)
8121 p
= s
+ 1; /* advance past '$' */
8122 n
= itbl_get_field (&p
); /* n is name */
8124 /* See if this is a register defined in an
8126 if (itbl_get_reg_val (n
, &r
))
8128 /* Get_field advances to the start of
8129 the next field, so we need to back
8130 rack to the end of the last field. */
8134 s
= strchr (s
, '\0');
8147 as_warn (_("Used $at without \".set noat\""));
8153 if (c
== 'r' || c
== 'v' || c
== 'w')
8160 /* 'z' only matches $0. */
8161 if (c
== 'z' && regno
!= 0)
8164 /* Now that we have assembled one operand, we use the args string
8165 * to figure out where it goes in the instruction. */
8172 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8176 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8179 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8180 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8185 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8188 /* This case exists because on the r3000 trunc
8189 expands into a macro which requires a gp
8190 register. On the r6000 or r4000 it is
8191 assembled into a single instruction which
8192 ignores the register. Thus the insn version
8193 is MIPS_ISA2 and uses 'x', and the macro
8194 version is MIPS_ISA1 and uses 't'. */
8197 /* This case is for the div instruction, which
8198 acts differently if the destination argument
8199 is $0. This only matches $0, and is checked
8200 outside the switch. */
8203 /* Itbl operand; not yet implemented. FIXME ?? */
8205 /* What about all other operands like 'i', which
8206 can be specified in the opcode table? */
8216 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8219 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8224 case 'O': /* MDMX alignment immediate constant. */
8225 my_getExpression (&imm_expr
, s
);
8226 check_absolute_expr (ip
, &imm_expr
);
8227 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8229 as_warn ("Improper align amount (%ld), using low bits",
8230 (long) imm_expr
.X_add_number
);
8231 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8233 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8234 imm_expr
.X_op
= O_absent
;
8238 case 'Q': /* MDMX vector, element sel, or const. */
8241 /* MDMX Immediate. */
8242 my_getExpression (&imm_expr
, s
);
8243 check_absolute_expr (ip
, &imm_expr
);
8244 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8246 as_warn (_("Invalid MDMX Immediate (%ld)"),
8247 (long) imm_expr
.X_add_number
);
8248 imm_expr
.X_add_number
&= OP_MASK_FT
;
8250 imm_expr
.X_add_number
&= OP_MASK_FT
;
8251 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8252 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8254 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8255 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8256 imm_expr
.X_op
= O_absent
;
8260 /* Not MDMX Immediate. Fall through. */
8261 case 'X': /* MDMX destination register. */
8262 case 'Y': /* MDMX source register. */
8263 case 'Z': /* MDMX target register. */
8265 case 'D': /* floating point destination register */
8266 case 'S': /* floating point source register */
8267 case 'T': /* floating point target register */
8268 case 'R': /* floating point source register */
8272 /* Accept $fN for FP and MDMX register numbers, and in
8273 addition accept $vN for MDMX register numbers. */
8274 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8275 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8286 while (ISDIGIT (*s
));
8289 as_bad (_("Invalid float register number (%d)"), regno
);
8291 if ((regno
& 1) != 0
8293 && ! (strcmp (str
, "mtc1") == 0
8294 || strcmp (str
, "mfc1") == 0
8295 || strcmp (str
, "lwc1") == 0
8296 || strcmp (str
, "swc1") == 0
8297 || strcmp (str
, "l.s") == 0
8298 || strcmp (str
, "s.s") == 0))
8299 as_warn (_("Float register should be even, was %d"),
8307 if (c
== 'V' || c
== 'W')
8318 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8323 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8326 /* This is like 'Z', but also needs to fix the MDMX
8327 vector/scalar select bits. Note that the
8328 scalar immediate case is handled above. */
8331 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8332 int max_el
= (is_qh
? 3 : 7);
8334 my_getExpression(&imm_expr
, s
);
8335 check_absolute_expr (ip
, &imm_expr
);
8337 if (imm_expr
.X_add_number
> max_el
)
8338 as_bad(_("Bad element selector %ld"),
8339 (long) imm_expr
.X_add_number
);
8340 imm_expr
.X_add_number
&= max_el
;
8341 ip
->insn_opcode
|= (imm_expr
.X_add_number
8345 as_warn(_("Expecting ']' found '%s'"), s
);
8351 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8352 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8355 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8362 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8365 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8375 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8378 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8384 my_getExpression (&imm_expr
, s
);
8385 if (imm_expr
.X_op
!= O_big
8386 && imm_expr
.X_op
!= O_constant
)
8387 insn_error
= _("absolute expression required");
8392 my_getExpression (&offset_expr
, s
);
8393 *imm_reloc
= BFD_RELOC_32
;
8406 unsigned char temp
[8];
8408 unsigned int length
;
8413 /* These only appear as the last operand in an
8414 instruction, and every instruction that accepts
8415 them in any variant accepts them in all variants.
8416 This means we don't have to worry about backing out
8417 any changes if the instruction does not match.
8419 The difference between them is the size of the
8420 floating point constant and where it goes. For 'F'
8421 and 'L' the constant is 64 bits; for 'f' and 'l' it
8422 is 32 bits. Where the constant is placed is based
8423 on how the MIPS assembler does things:
8426 f -- immediate value
8429 The .lit4 and .lit8 sections are only used if
8430 permitted by the -G argument.
8432 When generating embedded PIC code, we use the
8433 .lit8 section but not the .lit4 section (we can do
8434 .lit4 inline easily; we need to put .lit8
8435 somewhere in the data segment, and using .lit8
8436 permits the linker to eventually combine identical
8439 The code below needs to know whether the target register
8440 is 32 or 64 bits wide. It relies on the fact 'f' and
8441 'F' are used with GPR-based instructions and 'l' and
8442 'L' are used with FPR-based instructions. */
8444 f64
= *args
== 'F' || *args
== 'L';
8445 using_gprs
= *args
== 'F' || *args
== 'f';
8447 save_in
= input_line_pointer
;
8448 input_line_pointer
= s
;
8449 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8451 s
= input_line_pointer
;
8452 input_line_pointer
= save_in
;
8453 if (err
!= NULL
&& *err
!= '\0')
8455 as_bad (_("Bad floating point constant: %s"), err
);
8456 memset (temp
, '\0', sizeof temp
);
8457 length
= f64
? 8 : 4;
8460 assert (length
== (unsigned) (f64
? 8 : 4));
8464 && (! USE_GLOBAL_POINTER_OPT
8465 || mips_pic
== EMBEDDED_PIC
8466 || g_switch_value
< 4
8467 || (temp
[0] == 0 && temp
[1] == 0)
8468 || (temp
[2] == 0 && temp
[3] == 0))))
8470 imm_expr
.X_op
= O_constant
;
8471 if (! target_big_endian
)
8472 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8474 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8477 && ! mips_disable_float_construction
8478 /* Constants can only be constructed in GPRs and
8479 copied to FPRs if the GPRs are at least as wide
8480 as the FPRs. Force the constant into memory if
8481 we are using 64-bit FPRs but the GPRs are only
8484 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8485 && ((temp
[0] == 0 && temp
[1] == 0)
8486 || (temp
[2] == 0 && temp
[3] == 0))
8487 && ((temp
[4] == 0 && temp
[5] == 0)
8488 || (temp
[6] == 0 && temp
[7] == 0)))
8490 /* The value is simple enough to load with a couple of
8491 instructions. If using 32-bit registers, set
8492 imm_expr to the high order 32 bits and offset_expr to
8493 the low order 32 bits. Otherwise, set imm_expr to
8494 the entire 64 bit constant. */
8495 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8497 imm_expr
.X_op
= O_constant
;
8498 offset_expr
.X_op
= O_constant
;
8499 if (! target_big_endian
)
8501 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8502 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8506 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8507 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8509 if (offset_expr
.X_add_number
== 0)
8510 offset_expr
.X_op
= O_absent
;
8512 else if (sizeof (imm_expr
.X_add_number
) > 4)
8514 imm_expr
.X_op
= O_constant
;
8515 if (! target_big_endian
)
8516 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8518 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8522 imm_expr
.X_op
= O_big
;
8523 imm_expr
.X_add_number
= 4;
8524 if (! target_big_endian
)
8526 generic_bignum
[0] = bfd_getl16 (temp
);
8527 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8528 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8529 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8533 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8534 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8535 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8536 generic_bignum
[3] = bfd_getb16 (temp
);
8542 const char *newname
;
8545 /* Switch to the right section. */
8547 subseg
= now_subseg
;
8550 default: /* unused default case avoids warnings. */
8552 newname
= RDATA_SECTION_NAME
;
8553 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8554 || mips_pic
== EMBEDDED_PIC
)
8558 if (mips_pic
== EMBEDDED_PIC
)
8561 newname
= RDATA_SECTION_NAME
;
8564 assert (!USE_GLOBAL_POINTER_OPT
8565 || g_switch_value
>= 4);
8569 new_seg
= subseg_new (newname
, (subsegT
) 0);
8570 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8571 bfd_set_section_flags (stdoutput
, new_seg
,
8576 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8577 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8578 && strcmp (TARGET_OS
, "elf") != 0)
8579 record_alignment (new_seg
, 4);
8581 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8583 as_bad (_("Can't use floating point insn in this section"));
8585 /* Set the argument to the current address in the
8587 offset_expr
.X_op
= O_symbol
;
8588 offset_expr
.X_add_symbol
=
8589 symbol_new ("L0\001", now_seg
,
8590 (valueT
) frag_now_fix (), frag_now
);
8591 offset_expr
.X_add_number
= 0;
8593 /* Put the floating point number into the section. */
8594 p
= frag_more ((int) length
);
8595 memcpy (p
, temp
, length
);
8597 /* Switch back to the original section. */
8598 subseg_set (seg
, subseg
);
8603 case 'i': /* 16 bit unsigned immediate */
8604 case 'j': /* 16 bit signed immediate */
8605 *imm_reloc
= BFD_RELOC_LO16
;
8606 c
= my_getSmallExpression (&imm_expr
, s
);
8613 *imm_reloc
= BFD_RELOC_HI16_S
;
8614 imm_unmatched_hi
= true;
8617 else if (c
== S_EX_HIGHEST
)
8618 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8619 else if (c
== S_EX_HIGHER
)
8620 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8621 else if (c
== S_EX_GP_REL
)
8623 /* This occurs in NewABI only. */
8624 c
= my_getSmallExpression (&imm_expr
, s
);
8626 as_bad (_("bad composition of relocations"));
8629 c
= my_getSmallExpression (&imm_expr
, s
);
8631 as_bad (_("bad composition of relocations"));
8634 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8635 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8636 imm_reloc
[2] = BFD_RELOC_LO16
;
8642 *imm_reloc
= BFD_RELOC_HI16
;
8644 else if (imm_expr
.X_op
== O_constant
)
8645 imm_expr
.X_add_number
&= 0xffff;
8649 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8650 || ((imm_expr
.X_add_number
< 0
8651 || imm_expr
.X_add_number
>= 0x10000)
8652 && imm_expr
.X_op
== O_constant
))
8654 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8655 !strcmp (insn
->name
, insn
[1].name
))
8657 if (imm_expr
.X_op
== O_constant
8658 || imm_expr
.X_op
== O_big
)
8659 as_bad (_("16 bit expression not in range 0..65535"));
8667 /* The upper bound should be 0x8000, but
8668 unfortunately the MIPS assembler accepts numbers
8669 from 0x8000 to 0xffff and sign extends them, and
8670 we want to be compatible. We only permit this
8671 extended range for an instruction which does not
8672 provide any further alternates, since those
8673 alternates may handle other cases. People should
8674 use the numbers they mean, rather than relying on
8675 a mysterious sign extension. */
8676 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8677 strcmp (insn
->name
, insn
[1].name
) == 0);
8682 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8683 || ((imm_expr
.X_add_number
< -0x8000
8684 || imm_expr
.X_add_number
>= max
)
8685 && imm_expr
.X_op
== O_constant
)
8687 && imm_expr
.X_add_number
< 0
8689 && imm_expr
.X_unsigned
8690 && sizeof (imm_expr
.X_add_number
) <= 4))
8694 if (imm_expr
.X_op
== O_constant
8695 || imm_expr
.X_op
== O_big
)
8696 as_bad (_("16 bit expression not in range -32768..32767"));
8702 case 'o': /* 16 bit offset */
8703 c
= my_getSmallExpression (&offset_expr
, s
);
8705 /* If this value won't fit into a 16 bit offset, then go
8706 find a macro that will generate the 32 bit offset
8709 && (offset_expr
.X_op
!= O_constant
8710 || offset_expr
.X_add_number
>= 0x8000
8711 || offset_expr
.X_add_number
< -0x8000))
8716 if (offset_expr
.X_op
!= O_constant
)
8718 offset_expr
.X_add_number
=
8719 (offset_expr
.X_add_number
>> 16) & 0xffff;
8721 *offset_reloc
= BFD_RELOC_LO16
;
8725 case 'p': /* pc relative offset */
8726 if (mips_pic
== EMBEDDED_PIC
)
8727 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8729 *offset_reloc
= BFD_RELOC_16_PCREL
;
8730 my_getExpression (&offset_expr
, s
);
8734 case 'u': /* upper 16 bits */
8735 c
= my_getSmallExpression (&imm_expr
, s
);
8736 *imm_reloc
= BFD_RELOC_LO16
;
8743 *imm_reloc
= BFD_RELOC_HI16_S
;
8744 imm_unmatched_hi
= true;
8747 else if (c
== S_EX_HIGHEST
)
8748 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8749 else if (c
== S_EX_GP_REL
)
8751 /* This occurs in NewABI only. */
8752 c
= my_getSmallExpression (&imm_expr
, s
);
8754 as_bad (_("bad composition of relocations"));
8757 c
= my_getSmallExpression (&imm_expr
, s
);
8759 as_bad (_("bad composition of relocations"));
8762 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8763 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8764 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8770 *imm_reloc
= BFD_RELOC_HI16
;
8772 else if (imm_expr
.X_op
== O_constant
)
8773 imm_expr
.X_add_number
&= 0xffff;
8775 else if (imm_expr
.X_op
== O_constant
8776 && (imm_expr
.X_add_number
< 0
8777 || imm_expr
.X_add_number
>= 0x10000))
8778 as_bad (_("lui expression not in range 0..65535"));
8782 case 'a': /* 26 bit address */
8783 my_getExpression (&offset_expr
, s
);
8785 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8788 case 'N': /* 3 bit branch condition code */
8789 case 'M': /* 3 bit compare condition code */
8790 if (strncmp (s
, "$fcc", 4) != 0)
8800 while (ISDIGIT (*s
));
8802 as_bad (_("invalid condition code register $fcc%d"), regno
);
8804 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8806 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8810 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8821 while (ISDIGIT (*s
));
8824 c
= 8; /* Invalid sel value. */
8827 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8828 ip
->insn_opcode
|= c
;
8832 as_bad (_("bad char = '%c'\n"), *args
);
8837 /* Args don't match. */
8838 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8839 !strcmp (insn
->name
, insn
[1].name
))
8843 insn_error
= _("illegal operands");
8848 insn_error
= _("illegal operands");
8853 /* This routine assembles an instruction into its binary format when
8854 assembling for the mips16. As a side effect, it sets one of the
8855 global variables imm_reloc or offset_reloc to the type of
8856 relocation to do if one of the operands is an address expression.
8857 It also sets mips16_small and mips16_ext if the user explicitly
8858 requested a small or extended instruction. */
8863 struct mips_cl_insn
*ip
;
8867 struct mips_opcode
*insn
;
8870 unsigned int lastregno
= 0;
8875 mips16_small
= false;
8878 for (s
= str
; ISLOWER (*s
); ++s
)
8890 if (s
[1] == 't' && s
[2] == ' ')
8893 mips16_small
= true;
8897 else if (s
[1] == 'e' && s
[2] == ' ')
8906 insn_error
= _("unknown opcode");
8910 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8911 mips16_small
= true;
8913 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8915 insn_error
= _("unrecognized opcode");
8922 assert (strcmp (insn
->name
, str
) == 0);
8925 ip
->insn_opcode
= insn
->match
;
8926 ip
->use_extend
= false;
8927 imm_expr
.X_op
= O_absent
;
8928 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8929 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8930 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8931 offset_expr
.X_op
= O_absent
;
8932 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8933 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8934 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8935 for (args
= insn
->args
; 1; ++args
)
8942 /* In this switch statement we call break if we did not find
8943 a match, continue if we did find a match, or return if we
8952 /* Stuff the immediate value in now, if we can. */
8953 if (imm_expr
.X_op
== O_constant
8954 && *imm_reloc
> BFD_RELOC_UNUSED
8955 && insn
->pinfo
!= INSN_MACRO
)
8957 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
8958 imm_expr
.X_add_number
, true, mips16_small
,
8959 mips16_ext
, &ip
->insn_opcode
,
8960 &ip
->use_extend
, &ip
->extend
);
8961 imm_expr
.X_op
= O_absent
;
8962 *imm_reloc
= BFD_RELOC_UNUSED
;
8976 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8979 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8995 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8997 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9024 while (ISDIGIT (*s
));
9027 as_bad (_("invalid register number (%d)"), regno
);
9033 if (s
[1] == 'r' && s
[2] == 'a')
9038 else if (s
[1] == 'f' && s
[2] == 'p')
9043 else if (s
[1] == 's' && s
[2] == 'p')
9048 else if (s
[1] == 'g' && s
[2] == 'p')
9053 else if (s
[1] == 'a' && s
[2] == 't')
9058 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9063 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9068 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9081 if (c
== 'v' || c
== 'w')
9083 regno
= mips16_to_32_reg_map
[lastregno
];
9097 regno
= mips32_to_16_reg_map
[regno
];
9102 regno
= ILLEGAL_REG
;
9107 regno
= ILLEGAL_REG
;
9112 regno
= ILLEGAL_REG
;
9117 if (regno
== AT
&& ! mips_opts
.noat
)
9118 as_warn (_("used $at without \".set noat\""));
9125 if (regno
== ILLEGAL_REG
)
9132 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9136 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9139 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9142 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9148 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9151 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9152 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9162 if (strncmp (s
, "$pc", 3) == 0)
9186 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9188 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9189 and generate the appropriate reloc. If the text
9190 inside %gprel is not a symbol name with an
9191 optional offset, then we generate a normal reloc
9192 and will probably fail later. */
9193 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9194 if (imm_expr
.X_op
== O_symbol
)
9197 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9199 ip
->use_extend
= true;
9206 /* Just pick up a normal expression. */
9207 my_getExpression (&imm_expr
, s
);
9210 if (imm_expr
.X_op
== O_register
)
9212 /* What we thought was an expression turned out to
9215 if (s
[0] == '(' && args
[1] == '(')
9217 /* It looks like the expression was omitted
9218 before a register indirection, which means
9219 that the expression is implicitly zero. We
9220 still set up imm_expr, so that we handle
9221 explicit extensions correctly. */
9222 imm_expr
.X_op
= O_constant
;
9223 imm_expr
.X_add_number
= 0;
9224 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9231 /* We need to relax this instruction. */
9232 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9241 /* We use offset_reloc rather than imm_reloc for the PC
9242 relative operands. This lets macros with both
9243 immediate and address operands work correctly. */
9244 my_getExpression (&offset_expr
, s
);
9246 if (offset_expr
.X_op
== O_register
)
9249 /* We need to relax this instruction. */
9250 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9254 case '6': /* break code */
9255 my_getExpression (&imm_expr
, s
);
9256 check_absolute_expr (ip
, &imm_expr
);
9257 if ((unsigned long) imm_expr
.X_add_number
> 63)
9259 as_warn (_("Invalid value for `%s' (%lu)"),
9261 (unsigned long) imm_expr
.X_add_number
);
9262 imm_expr
.X_add_number
&= 0x3f;
9264 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9265 imm_expr
.X_op
= O_absent
;
9269 case 'a': /* 26 bit address */
9270 my_getExpression (&offset_expr
, s
);
9272 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9273 ip
->insn_opcode
<<= 16;
9276 case 'l': /* register list for entry macro */
9277 case 'L': /* register list for exit macro */
9287 int freg
, reg1
, reg2
;
9289 while (*s
== ' ' || *s
== ',')
9293 as_bad (_("can't parse register list"));
9305 while (ISDIGIT (*s
))
9327 as_bad (_("invalid register list"));
9332 while (ISDIGIT (*s
))
9339 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9344 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9349 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9350 mask
|= (reg2
- 3) << 3;
9351 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9352 mask
|= (reg2
- 15) << 1;
9353 else if (reg1
== RA
&& reg2
== RA
)
9357 as_bad (_("invalid register list"));
9361 /* The mask is filled in in the opcode table for the
9362 benefit of the disassembler. We remove it before
9363 applying the actual mask. */
9364 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9365 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9369 case 'e': /* extend code */
9370 my_getExpression (&imm_expr
, s
);
9371 check_absolute_expr (ip
, &imm_expr
);
9372 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9374 as_warn (_("Invalid value for `%s' (%lu)"),
9376 (unsigned long) imm_expr
.X_add_number
);
9377 imm_expr
.X_add_number
&= 0x7ff;
9379 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9380 imm_expr
.X_op
= O_absent
;
9390 /* Args don't match. */
9391 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9392 strcmp (insn
->name
, insn
[1].name
) == 0)
9399 insn_error
= _("illegal operands");
9405 /* This structure holds information we know about a mips16 immediate
9408 struct mips16_immed_operand
9410 /* The type code used in the argument string in the opcode table. */
9412 /* The number of bits in the short form of the opcode. */
9414 /* The number of bits in the extended form of the opcode. */
9416 /* The amount by which the short form is shifted when it is used;
9417 for example, the sw instruction has a shift count of 2. */
9419 /* The amount by which the short form is shifted when it is stored
9420 into the instruction code. */
9422 /* Non-zero if the short form is unsigned. */
9424 /* Non-zero if the extended form is unsigned. */
9426 /* Non-zero if the value is PC relative. */
9430 /* The mips16 immediate operand types. */
9432 static const struct mips16_immed_operand mips16_immed_operands
[] =
9434 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9435 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9436 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9437 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9438 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9439 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9440 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9441 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9442 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9443 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9444 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9445 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9446 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9447 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9448 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9449 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9450 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9451 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9452 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9453 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9454 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9457 #define MIPS16_NUM_IMMED \
9458 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9460 /* Handle a mips16 instruction with an immediate value. This or's the
9461 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9462 whether an extended value is needed; if one is needed, it sets
9463 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9464 If SMALL is true, an unextended opcode was explicitly requested.
9465 If EXT is true, an extended opcode was explicitly requested. If
9466 WARN is true, warn if EXT does not match reality. */
9469 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9478 unsigned long *insn
;
9479 boolean
*use_extend
;
9480 unsigned short *extend
;
9482 register const struct mips16_immed_operand
*op
;
9483 int mintiny
, maxtiny
;
9486 op
= mips16_immed_operands
;
9487 while (op
->type
!= type
)
9490 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9495 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9498 maxtiny
= 1 << op
->nbits
;
9503 maxtiny
= (1 << op
->nbits
) - 1;
9508 mintiny
= - (1 << (op
->nbits
- 1));
9509 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9512 /* Branch offsets have an implicit 0 in the lowest bit. */
9513 if (type
== 'p' || type
== 'q')
9516 if ((val
& ((1 << op
->shift
) - 1)) != 0
9517 || val
< (mintiny
<< op
->shift
)
9518 || val
> (maxtiny
<< op
->shift
))
9523 if (warn
&& ext
&& ! needext
)
9524 as_warn_where (file
, line
,
9525 _("extended operand requested but not required"));
9526 if (small
&& needext
)
9527 as_bad_where (file
, line
, _("invalid unextended operand value"));
9529 if (small
|| (! ext
&& ! needext
))
9533 *use_extend
= false;
9534 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9535 insnval
<<= op
->op_shift
;
9540 long minext
, maxext
;
9546 maxext
= (1 << op
->extbits
) - 1;
9550 minext
= - (1 << (op
->extbits
- 1));
9551 maxext
= (1 << (op
->extbits
- 1)) - 1;
9553 if (val
< minext
|| val
> maxext
)
9554 as_bad_where (file
, line
,
9555 _("operand value out of range for instruction"));
9558 if (op
->extbits
== 16)
9560 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9563 else if (op
->extbits
== 15)
9565 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9570 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9574 *extend
= (unsigned short) extval
;
9579 static struct percent_op_match
9582 const enum small_ex_type type
;
9587 {"%call_hi", S_EX_CALL_HI
},
9588 {"%call_lo", S_EX_CALL_LO
},
9589 {"%call16", S_EX_CALL16
},
9590 {"%got_disp", S_EX_GOT_DISP
},
9591 {"%got_page", S_EX_GOT_PAGE
},
9592 {"%got_ofst", S_EX_GOT_OFST
},
9593 {"%got_hi", S_EX_GOT_HI
},
9594 {"%got_lo", S_EX_GOT_LO
},
9596 {"%gp_rel", S_EX_GP_REL
},
9597 {"%half", S_EX_HALF
},
9598 {"%highest", S_EX_HIGHEST
},
9599 {"%higher", S_EX_HIGHER
},
9605 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9606 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9607 can be nested, this is handled by blanking the innermost, parsing the
9608 rest by subsequent calls. */
9611 my_getSmallParser (str
, len
, nestlevel
)
9617 *str
+= strspn (*str
, " \t");
9618 /* Check for expression in parentheses. */
9621 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9624 /* Check for base register. */
9628 && (e
= b
+ strcspn (b
, ") \t"))
9629 && e
- b
> 1 && e
- b
< 4)
9632 && ((b
[1] == 'f' && b
[2] == 'p')
9633 || (b
[1] == 's' && b
[2] == 'p')
9634 || (b
[1] == 'g' && b
[2] == 'p')
9635 || (b
[1] == 'a' && b
[2] == 't')
9637 && ISDIGIT (b
[2]))))
9638 || (ISDIGIT (b
[1])))
9640 *len
= strcspn (*str
, ")") + 1;
9641 return S_EX_REGISTER
;
9645 /* Check for percent_op (in parentheses). */
9646 else if (b
[0] == '%')
9649 return my_getPercentOp (str
, len
, nestlevel
);
9652 /* Some other expression in the parentheses, which can contain
9653 parentheses itself. Attempt to find the matching one. */
9659 for (s
= *str
+ 1; *s
&& pcnt
; s
++, (*len
)++)
9668 /* Check for percent_op (outside of parentheses). */
9669 else if (*str
[0] == '%')
9670 return my_getPercentOp (str
, len
, nestlevel
);
9672 /* Any other expression. */
9677 my_getPercentOp (str
, len
, nestlevel
)
9682 char *tmp
= *str
+ 1;
9685 while (ISALPHA (*tmp
) || *tmp
== '_')
9687 *tmp
= TOLOWER (*tmp
);
9690 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9692 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9696 int type
= percent_op
[i
].type
;
9698 /* Only %hi and %lo are allowed for OldABI. */
9699 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9702 *len
= strlen (percent_op
[i
].str
);
9711 my_getSmallExpression (ep
, str
)
9715 static char *oldstr
= NULL
;
9721 /* Don't update oldstr if the last call had nested percent_op's. We need
9722 it to parse the outer ones later. */
9729 c
= my_getSmallParser (&str
, &len
, &nestlevel
);
9730 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9733 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9737 /* A percent_op was encountered. Don't try to get an expression if
9738 it is already blanked out. */
9739 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9743 /* Let my_getExpression() stop at the closing parenthesis. */
9744 save
= *(str
+ len
);
9745 *(str
+ len
) = '\0';
9746 my_getExpression (ep
, str
);
9747 *(str
+ len
) = save
;
9751 /* Blank out including the % sign and the proper matching
9754 char *s
= strrchr (oldstr
, '%');
9757 for (end
= strchr (s
, '(') + 1; *end
&& pcnt
; end
++)
9761 else if (*end
== ')')
9765 memset (s
, ' ', end
- s
);
9769 expr_end
= str
+ len
;
9773 else if (c
== S_EX_NONE
)
9775 my_getExpression (ep
, str
);
9777 else if (c
== S_EX_REGISTER
)
9779 ep
->X_op
= O_constant
;
9781 ep
->X_add_symbol
= NULL
;
9782 ep
->X_op_symbol
= NULL
;
9783 ep
->X_add_number
= 0;
9787 as_fatal (_("internal error"));
9791 /* All percent_op's have been handled. */
9798 my_getExpression (ep
, str
)
9805 save_in
= input_line_pointer
;
9806 input_line_pointer
= str
;
9808 expr_end
= input_line_pointer
;
9809 input_line_pointer
= save_in
;
9811 /* If we are in mips16 mode, and this is an expression based on `.',
9812 then we bump the value of the symbol by 1 since that is how other
9813 text symbols are handled. We don't bother to handle complex
9814 expressions, just `.' plus or minus a constant. */
9815 if (mips_opts
.mips16
9816 && ep
->X_op
== O_symbol
9817 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9818 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9819 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9820 && symbol_constant_p (ep
->X_add_symbol
)
9821 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9822 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9825 /* Turn a string in input_line_pointer into a floating point constant
9826 of type TYPE, and store the appropriate bytes in *LITP. The number
9827 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9828 returned, or NULL on OK. */
9831 md_atof (type
, litP
, sizeP
)
9837 LITTLENUM_TYPE words
[4];
9853 return _("bad call to md_atof");
9856 t
= atof_ieee (input_line_pointer
, type
, words
);
9858 input_line_pointer
= t
;
9862 if (! target_big_endian
)
9864 for (i
= prec
- 1; i
>= 0; i
--)
9866 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9872 for (i
= 0; i
< prec
; i
++)
9874 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9883 md_number_to_chars (buf
, val
, n
)
9888 if (target_big_endian
)
9889 number_to_chars_bigendian (buf
, val
, n
);
9891 number_to_chars_littleendian (buf
, val
, n
);
9895 static int support_64bit_objects(void)
9897 const char **list
, **l
;
9899 list
= bfd_target_list ();
9900 for (l
= list
; *l
!= NULL
; l
++)
9902 /* This is traditional mips */
9903 if (strcmp (*l
, "elf64-tradbigmips") == 0
9904 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9906 if (strcmp (*l
, "elf64-bigmips") == 0
9907 || strcmp (*l
, "elf64-littlemips") == 0)
9911 return (*l
!= NULL
);
9913 #endif /* OBJ_ELF */
9915 const char *md_shortopts
= "nO::g::G:";
9917 struct option md_longopts
[] =
9919 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9920 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9921 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9922 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9923 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9924 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9925 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9926 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9927 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9928 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9929 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9930 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9931 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9932 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9933 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9934 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9935 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9936 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9937 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9938 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9939 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9940 {"break", no_argument
, NULL
, OPTION_BREAK
},
9941 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9942 #define OPTION_EB (OPTION_MD_BASE + 11)
9943 {"EB", no_argument
, NULL
, OPTION_EB
},
9944 #define OPTION_EL (OPTION_MD_BASE + 12)
9945 {"EL", no_argument
, NULL
, OPTION_EL
},
9946 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9947 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9948 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9949 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9950 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9951 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9952 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
9953 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9954 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9955 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9956 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9957 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9958 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9959 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9960 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9961 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9962 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9963 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9964 {"march", required_argument
, NULL
, OPTION_MARCH
},
9965 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9966 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9967 #define OPTION_FP64 (OPTION_MD_BASE + 23)
9968 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
9969 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9970 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9971 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9972 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9973 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9974 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9975 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9976 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9977 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9978 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9979 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9980 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9981 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9982 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9983 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9984 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9985 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9986 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9987 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9988 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9989 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9990 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9991 #define OPTION_MDMX (OPTION_MD_BASE + 35)
9992 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
9993 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
9994 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
9996 #define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
9997 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9998 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9999 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10000 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10001 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10002 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10003 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10004 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10005 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10006 #define OPTION_32 (OPTION_ELF_BASE + 4)
10007 {"32", no_argument
, NULL
, OPTION_32
},
10008 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10009 {"n32", no_argument
, NULL
, OPTION_N32
},
10010 #define OPTION_64 (OPTION_ELF_BASE + 6)
10011 {"64", no_argument
, NULL
, OPTION_64
},
10012 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10013 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10014 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10015 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10016 #endif /* OBJ_ELF */
10017 {NULL
, no_argument
, NULL
, 0}
10019 size_t md_longopts_size
= sizeof (md_longopts
);
10021 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10022 NEW_VALUE. Warn if another value was already specified. Note:
10023 we have to defer parsing the -march and -mtune arguments in order
10024 to handle 'from-abi' correctly, since the ABI might be specified
10025 in a later argument. */
10028 mips_set_option_string (string_ptr
, new_value
)
10029 const char **string_ptr
, *new_value
;
10031 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10032 as_warn (_("A different %s was already specified, is now %s"),
10033 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10036 *string_ptr
= new_value
;
10040 md_parse_option (c
, arg
)
10046 case OPTION_CONSTRUCT_FLOATS
:
10047 mips_disable_float_construction
= 0;
10050 case OPTION_NO_CONSTRUCT_FLOATS
:
10051 mips_disable_float_construction
= 1;
10063 target_big_endian
= 1;
10067 target_big_endian
= 0;
10075 if (arg
&& arg
[1] == '0')
10085 mips_debug
= atoi (arg
);
10086 /* When the MIPS assembler sees -g or -g2, it does not do
10087 optimizations which limit full symbolic debugging. We take
10088 that to be equivalent to -O0. */
10089 if (mips_debug
== 2)
10094 file_mips_isa
= ISA_MIPS1
;
10098 file_mips_isa
= ISA_MIPS2
;
10102 file_mips_isa
= ISA_MIPS3
;
10106 file_mips_isa
= ISA_MIPS4
;
10110 file_mips_isa
= ISA_MIPS5
;
10113 case OPTION_MIPS32
:
10114 file_mips_isa
= ISA_MIPS32
;
10117 case OPTION_MIPS64
:
10118 file_mips_isa
= ISA_MIPS64
;
10122 mips_set_option_string (&mips_tune_string
, arg
);
10126 mips_set_option_string (&mips_arch_string
, arg
);
10130 mips_set_option_string (&mips_arch_string
, "4650");
10131 mips_set_option_string (&mips_tune_string
, "4650");
10134 case OPTION_NO_M4650
:
10138 mips_set_option_string (&mips_arch_string
, "4010");
10139 mips_set_option_string (&mips_tune_string
, "4010");
10142 case OPTION_NO_M4010
:
10146 mips_set_option_string (&mips_arch_string
, "4100");
10147 mips_set_option_string (&mips_tune_string
, "4100");
10150 case OPTION_NO_M4100
:
10154 mips_set_option_string (&mips_arch_string
, "3900");
10155 mips_set_option_string (&mips_tune_string
, "3900");
10158 case OPTION_NO_M3900
:
10162 mips_opts
.ase_mdmx
= 1;
10165 case OPTION_NO_MDMX
:
10166 mips_opts
.ase_mdmx
= 0;
10169 case OPTION_MIPS16
:
10170 mips_opts
.mips16
= 1;
10171 mips_no_prev_insn (false);
10174 case OPTION_NO_MIPS16
:
10175 mips_opts
.mips16
= 0;
10176 mips_no_prev_insn (false);
10179 case OPTION_MIPS3D
:
10180 mips_opts
.ase_mips3d
= 1;
10183 case OPTION_NO_MIPS3D
:
10184 mips_opts
.ase_mips3d
= 0;
10187 case OPTION_MEMBEDDED_PIC
:
10188 mips_pic
= EMBEDDED_PIC
;
10189 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10191 as_bad (_("-G may not be used with embedded PIC code"));
10194 g_switch_value
= 0x7fffffff;
10198 /* When generating ELF code, we permit -KPIC and -call_shared to
10199 select SVR4_PIC, and -non_shared to select no PIC. This is
10200 intended to be compatible with Irix 5. */
10201 case OPTION_CALL_SHARED
:
10202 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10204 as_bad (_("-call_shared is supported only for ELF format"));
10207 mips_pic
= SVR4_PIC
;
10208 if (g_switch_seen
&& g_switch_value
!= 0)
10210 as_bad (_("-G may not be used with SVR4 PIC code"));
10213 g_switch_value
= 0;
10216 case OPTION_NON_SHARED
:
10217 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10219 as_bad (_("-non_shared is supported only for ELF format"));
10225 /* The -xgot option tells the assembler to use 32 offsets when
10226 accessing the got in SVR4_PIC mode. It is for Irix
10231 #endif /* OBJ_ELF */
10234 if (! USE_GLOBAL_POINTER_OPT
)
10236 as_bad (_("-G is not supported for this configuration"));
10239 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10241 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10245 g_switch_value
= atoi (arg
);
10250 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10253 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10255 as_bad (_("-32 is supported for ELF format only"));
10258 mips_abi
= O32_ABI
;
10262 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10264 as_bad (_("-n32 is supported for ELF format only"));
10267 mips_abi
= N32_ABI
;
10271 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10273 as_bad (_("-64 is supported for ELF format only"));
10276 mips_abi
= N64_ABI
;
10277 if (! support_64bit_objects())
10278 as_fatal (_("No compiled in support for 64 bit object file format"));
10280 #endif /* OBJ_ELF */
10283 file_mips_gp32
= 1;
10287 file_mips_gp32
= 0;
10291 file_mips_fp32
= 1;
10295 file_mips_fp32
= 0;
10300 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10302 as_bad (_("-mabi is supported for ELF format only"));
10305 if (strcmp (arg
, "32") == 0)
10306 mips_abi
= O32_ABI
;
10307 else if (strcmp (arg
, "o64") == 0)
10308 mips_abi
= O64_ABI
;
10309 else if (strcmp (arg
, "n32") == 0)
10310 mips_abi
= N32_ABI
;
10311 else if (strcmp (arg
, "64") == 0)
10313 mips_abi
= N64_ABI
;
10314 if (! support_64bit_objects())
10315 as_fatal (_("No compiled in support for 64 bit object file "
10318 else if (strcmp (arg
, "eabi") == 0)
10319 mips_abi
= EABI_ABI
;
10322 as_fatal (_("invalid abi -mabi=%s"), arg
);
10326 #endif /* OBJ_ELF */
10328 case OPTION_M7000_HILO_FIX
:
10329 mips_7000_hilo_fix
= true;
10332 case OPTION_MNO_7000_HILO_FIX
:
10333 mips_7000_hilo_fix
= false;
10337 case OPTION_MDEBUG
:
10338 mips_flag_mdebug
= true;
10341 case OPTION_NO_MDEBUG
:
10342 mips_flag_mdebug
= false;
10344 #endif /* OBJ_ELF */
10353 /* Set up globals to generate code for the ISA or processor
10354 described by INFO. */
10357 mips_set_architecture (info
)
10358 const struct mips_cpu_info
*info
;
10362 mips_arch_info
= info
;
10363 mips_arch
= info
->cpu
;
10364 mips_opts
.isa
= info
->isa
;
10369 /* Likewise for tuning. */
10372 mips_set_tune (info
)
10373 const struct mips_cpu_info
*info
;
10377 mips_tune_info
= info
;
10378 mips_tune
= info
->cpu
;
10384 mips_after_parse_args ()
10386 /* GP relative stuff not working for PE */
10387 if (strncmp (TARGET_OS
, "pe", 2) == 0
10388 && g_switch_value
!= 0)
10391 as_bad (_("-G not supported in this configuration."));
10392 g_switch_value
= 0;
10395 /* The following code determines the architecture and register size.
10396 Similar code was added to GCC 3.3 (see override_options() in
10397 config/mips/mips.c). The GAS and GCC code should be kept in sync
10398 as much as possible. */
10400 if (mips_arch_string
!= 0)
10401 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
10403 if (mips_tune_string
!= 0)
10404 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
10406 if (file_mips_isa
!= ISA_UNKNOWN
)
10408 /* Handle -mipsN. At this point, file_mips_isa contains the
10409 ISA level specified by -mipsN, while mips_opts.isa contains
10410 the -march selection (if any). */
10411 if (mips_arch_info
!= 0)
10413 /* -march takes precedence over -mipsN, since it is more descriptive.
10414 There's no harm in specifying both as long as the ISA levels
10416 if (file_mips_isa
!= mips_opts
.isa
)
10417 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10418 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10419 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10422 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa
));
10425 if (mips_arch_info
== 0)
10426 mips_set_architecture (mips_parse_cpu ("default CPU",
10427 MIPS_CPU_STRING_DEFAULT
));
10429 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10430 as_bad ("-march=%s is not compatible with the selected ABI",
10431 mips_arch_info
->name
);
10433 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10434 if (mips_tune_info
== 0)
10435 mips_set_tune (mips_arch_info
);
10437 if (file_mips_gp32
>= 0)
10439 /* The user specified the size of the integer registers. Make sure
10440 it agrees with the ABI and ISA. */
10441 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10442 as_bad (_("-mgp64 used with a 32-bit processor"));
10443 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10444 as_bad (_("-mgp32 used with a 64-bit ABI"));
10445 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10446 as_bad (_("-mgp64 used with a 32-bit ABI"));
10450 /* Infer the integer register size from the ABI and processor.
10451 Restrict ourselves to 32-bit registers if that's all the
10452 processor has, or if the ABI cannot handle 64-bit registers. */
10453 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10454 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10457 /* ??? GAS treats single-float processors as though they had 64-bit
10458 float registers (although it complains when double-precision
10459 instructions are used). As things stand, saying they have 32-bit
10460 registers would lead to spurious "register must be even" messages.
10461 So here we assume float registers are always the same size as
10462 integer ones, unless the user says otherwise. */
10463 if (file_mips_fp32
< 0)
10464 file_mips_fp32
= file_mips_gp32
;
10466 /* End of GCC-shared inference code. */
10468 /* ??? When do we want this flag to be set? Who uses it? */
10469 if (file_mips_gp32
== 1
10470 && mips_abi
== NO_ABI
10471 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10472 mips_32bitmode
= 1;
10474 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10475 as_bad (_("trap exception not supported at ISA 1"));
10477 /* If the selected architecture includes support for ASEs, enable
10478 generation of code for them. */
10479 if (mips_opts
.mips16
== -1)
10480 mips_opts
.mips16
= (CPU_HAS_MIPS16 (mips_arch
)) ? 1 : 0;
10481 if (mips_opts
.ase_mips3d
== -1)
10482 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (mips_arch
)) ? 1 : 0;
10483 if (mips_opts
.ase_mdmx
== -1)
10484 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (mips_arch
)) ? 1 : 0;
10486 file_mips_isa
= mips_opts
.isa
;
10487 file_ase_mips16
= mips_opts
.mips16
;
10488 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10489 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10490 mips_opts
.gp32
= file_mips_gp32
;
10491 mips_opts
.fp32
= file_mips_fp32
;
10493 if (mips_flag_mdebug
< 0)
10495 #ifdef OBJ_MAYBE_ECOFF
10496 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10497 mips_flag_mdebug
= 1;
10499 #endif /* OBJ_MAYBE_ECOFF */
10500 mips_flag_mdebug
= 0;
10505 mips_init_after_args ()
10507 /* initialize opcodes */
10508 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10509 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10513 md_pcrel_from (fixP
)
10516 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10517 && fixP
->fx_addsy
!= (symbolS
*) NULL
10518 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10520 /* This makes a branch to an undefined symbol be a branch to the
10521 current location. */
10522 if (mips_pic
== EMBEDDED_PIC
)
10528 /* Return the address of the delay slot. */
10529 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10532 /* This is called before the symbol table is processed. In order to
10533 work with gcc when using mips-tfile, we must keep all local labels.
10534 However, in other cases, we want to discard them. If we were
10535 called with -g, but we didn't see any debugging information, it may
10536 mean that gcc is smuggling debugging information through to
10537 mips-tfile, in which case we must generate all local labels. */
10540 mips_frob_file_before_adjust ()
10542 #ifndef NO_ECOFF_DEBUGGING
10543 if (ECOFF_DEBUGGING
10545 && ! ecoff_debugging_seen
)
10546 flag_keep_locals
= 1;
10550 /* Sort any unmatched HI16_S relocs so that they immediately precede
10551 the corresponding LO reloc. This is called before md_apply_fix3 and
10552 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10553 explicit use of the %hi modifier. */
10558 struct mips_hi_fixup
*l
;
10560 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10562 segment_info_type
*seginfo
;
10565 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10567 /* Check quickly whether the next fixup happens to be a matching
10569 if (l
->fixp
->fx_next
!= NULL
10570 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10571 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10572 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10575 /* Look through the fixups for this segment for a matching %lo.
10576 When we find one, move the %hi just in front of it. We do
10577 this in two passes. In the first pass, we try to find a
10578 unique %lo. In the second pass, we permit multiple %hi
10579 relocs for a single %lo (this is a GNU extension). */
10580 seginfo
= seg_info (l
->seg
);
10581 for (pass
= 0; pass
< 2; pass
++)
10586 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10588 /* Check whether this is a %lo fixup which matches l->fixp. */
10589 if (f
->fx_r_type
== BFD_RELOC_LO16
10590 && f
->fx_addsy
== l
->fixp
->fx_addsy
10591 && f
->fx_offset
== l
->fixp
->fx_offset
10594 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10595 || prev
->fx_addsy
!= f
->fx_addsy
10596 || prev
->fx_offset
!= f
->fx_offset
))
10600 /* Move l->fixp before f. */
10601 for (pf
= &seginfo
->fix_root
;
10603 pf
= &(*pf
)->fx_next
)
10604 assert (*pf
!= NULL
);
10606 *pf
= l
->fixp
->fx_next
;
10608 l
->fixp
->fx_next
= f
;
10610 seginfo
->fix_root
= l
->fixp
;
10612 prev
->fx_next
= l
->fixp
;
10623 #if 0 /* GCC code motion plus incomplete dead code elimination
10624 can leave a %hi without a %lo. */
10626 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10627 _("Unmatched %%hi reloc"));
10633 /* When generating embedded PIC code we need to use a special
10634 relocation to represent the difference of two symbols in the .text
10635 section (switch tables use a difference of this sort). See
10636 include/coff/mips.h for details. This macro checks whether this
10637 fixup requires the special reloc. */
10638 #define SWITCH_TABLE(fixp) \
10639 ((fixp)->fx_r_type == BFD_RELOC_32 \
10640 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10641 && (fixp)->fx_addsy != NULL \
10642 && (fixp)->fx_subsy != NULL \
10643 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10644 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10646 /* When generating embedded PIC code we must keep all PC relative
10647 relocations, in case the linker has to relax a call. We also need
10648 to keep relocations for switch table entries.
10650 We may have combined relocations without symbols in the N32/N64 ABI.
10651 We have to prevent gas from dropping them. */
10654 mips_force_relocation (fixp
)
10657 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10658 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
10659 || S_FORCE_RELOC (fixp
->fx_addsy
))
10663 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10664 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10665 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10666 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10669 return (mips_pic
== EMBEDDED_PIC
10671 || SWITCH_TABLE (fixp
)
10672 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10673 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10678 mips_need_elf_addend_fixup (fixP
)
10681 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
10683 if (mips_pic
== EMBEDDED_PIC
10684 && S_IS_WEAK (fixP
->fx_addsy
))
10686 if (mips_pic
!= EMBEDDED_PIC
10687 && (S_IS_WEAK (fixP
->fx_addsy
)
10688 || S_IS_EXTERNAL (fixP
->fx_addsy
))
10689 && !S_IS_COMMON (fixP
->fx_addsy
))
10691 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10692 && (((bfd_get_section_flags (stdoutput
,
10693 S_GET_SEGMENT (fixP
->fx_addsy
))
10694 & SEC_LINK_ONCE
) != 0)
10695 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10697 sizeof (".gnu.linkonce") - 1)))
10703 /* Apply a fixup to the object file. */
10706 md_apply_fix3 (fixP
, valP
, seg
)
10709 segT seg ATTRIBUTE_UNUSED
;
10714 static int previous_fx_r_type
= 0;
10716 /* FIXME: Maybe just return for all reloc types not listed below?
10717 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
10718 if (fixP
->fx_r_type
== BFD_RELOC_8
)
10721 assert (fixP
->fx_size
== 4
10722 || fixP
->fx_r_type
== BFD_RELOC_16
10723 || fixP
->fx_r_type
== BFD_RELOC_32
10724 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10725 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10726 || fixP
->fx_r_type
== BFD_RELOC_LO16
10727 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10728 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10729 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10730 || fixP
->fx_r_type
== BFD_RELOC_64
10731 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10732 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10733 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10734 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10735 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10736 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10737 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10738 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10739 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
10740 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JALR
);
10744 /* If we aren't adjusting this fixup to be against the section
10745 symbol, we need to adjust the value. */
10747 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10749 if (mips_need_elf_addend_fixup (fixP
))
10751 reloc_howto_type
*howto
;
10752 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10756 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10757 if (value
!= 0 && howto
->partial_inplace
&& ! fixP
->fx_pcrel
)
10759 /* In this case, the bfd_install_relocation routine will
10760 incorrectly add the symbol value back in. We just want
10761 the addend to appear in the object file. */
10764 /* Make sure the addend is still non-zero. If it became zero
10765 after the last operation, set it to a spurious value and
10766 subtract the same value from the object file's contents. */
10771 /* The in-place addends for LO16 relocations are signed;
10772 leave the matching HI16 in-place addends as zero. */
10773 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10775 bfd_vma contents
, mask
, field
;
10777 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10780 target_big_endian
);
10782 /* MASK has bits set where the relocation should go.
10783 FIELD is -value, shifted into the appropriate place
10784 for this relocation. */
10785 mask
= 1 << (howto
->bitsize
- 1);
10786 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10787 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10789 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10790 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10792 target_big_endian
);
10798 /* This code was generated using trial and error and so is
10799 fragile and not trustworthy. If you change it, you should
10800 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10801 they still pass. */
10802 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10804 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10806 /* BFD's REL handling, for MIPS, is _very_ weird.
10807 This gives the right results, but it can't possibly
10808 be the way things are supposed to work. */
10809 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10810 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10811 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10812 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10817 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
10819 /* We are not done if this is a composite relocation to set up gp. */
10820 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
10821 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10822 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
10823 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
10824 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
10826 previous_fx_r_type
= fixP
->fx_r_type
;
10828 switch (fixP
->fx_r_type
)
10830 case BFD_RELOC_MIPS_JMP
:
10831 case BFD_RELOC_MIPS_SHIFT5
:
10832 case BFD_RELOC_MIPS_SHIFT6
:
10833 case BFD_RELOC_MIPS_GOT_DISP
:
10834 case BFD_RELOC_MIPS_GOT_PAGE
:
10835 case BFD_RELOC_MIPS_GOT_OFST
:
10836 case BFD_RELOC_MIPS_SUB
:
10837 case BFD_RELOC_MIPS_INSERT_A
:
10838 case BFD_RELOC_MIPS_INSERT_B
:
10839 case BFD_RELOC_MIPS_DELETE
:
10840 case BFD_RELOC_MIPS_HIGHEST
:
10841 case BFD_RELOC_MIPS_HIGHER
:
10842 case BFD_RELOC_MIPS_SCN_DISP
:
10843 case BFD_RELOC_MIPS_REL16
:
10844 case BFD_RELOC_MIPS_RELGOT
:
10845 case BFD_RELOC_MIPS_JALR
:
10846 case BFD_RELOC_HI16
:
10847 case BFD_RELOC_HI16_S
:
10848 case BFD_RELOC_GPREL16
:
10849 case BFD_RELOC_MIPS_LITERAL
:
10850 case BFD_RELOC_MIPS_CALL16
:
10851 case BFD_RELOC_MIPS_GOT16
:
10852 case BFD_RELOC_GPREL32
:
10853 case BFD_RELOC_MIPS_GOT_HI16
:
10854 case BFD_RELOC_MIPS_GOT_LO16
:
10855 case BFD_RELOC_MIPS_CALL_HI16
:
10856 case BFD_RELOC_MIPS_CALL_LO16
:
10857 case BFD_RELOC_MIPS16_GPREL
:
10858 if (fixP
->fx_pcrel
)
10859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10860 _("Invalid PC relative reloc"));
10861 /* Nothing needed to do. The value comes from the reloc entry */
10864 case BFD_RELOC_MIPS16_JMP
:
10865 /* We currently always generate a reloc against a symbol, which
10866 means that we don't want an addend even if the symbol is
10868 fixP
->fx_addnumber
= 0;
10871 case BFD_RELOC_PCREL_HI16_S
:
10872 /* The addend for this is tricky if it is internal, so we just
10873 do everything here rather than in bfd_install_relocation. */
10874 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10879 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10881 /* For an external symbol adjust by the address to make it
10882 pcrel_offset. We use the address of the RELLO reloc
10883 which follows this one. */
10884 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10885 + fixP
->fx_next
->fx_where
);
10887 value
= ((value
+ 0x8000) >> 16) & 0xffff;
10888 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10889 if (target_big_endian
)
10891 md_number_to_chars ((char *) buf
, value
, 2);
10894 case BFD_RELOC_PCREL_LO16
:
10895 /* The addend for this is tricky if it is internal, so we just
10896 do everything here rather than in bfd_install_relocation. */
10897 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10902 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10903 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10904 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10905 if (target_big_endian
)
10907 md_number_to_chars ((char *) buf
, value
, 2);
10911 /* This is handled like BFD_RELOC_32, but we output a sign
10912 extended value if we are only 32 bits. */
10914 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10916 if (8 <= sizeof (valueT
))
10917 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10924 w1
= w2
= fixP
->fx_where
;
10925 if (target_big_endian
)
10929 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10930 if ((value
& 0x80000000) != 0)
10934 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10939 case BFD_RELOC_RVA
:
10941 /* If we are deleting this reloc entry, we must fill in the
10942 value now. This can happen if we have a .word which is not
10943 resolved when it appears but is later defined. We also need
10944 to fill in the value if this is an embedded PIC switch table
10947 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10948 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10953 /* If we are deleting this reloc entry, we must fill in the
10955 assert (fixP
->fx_size
== 2);
10957 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10961 case BFD_RELOC_LO16
:
10962 /* When handling an embedded PIC switch statement, we can wind
10963 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10966 if (value
+ 0x8000 > 0xffff)
10967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10968 _("relocation overflow"));
10969 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10970 if (target_big_endian
)
10972 md_number_to_chars ((char *) buf
, value
, 2);
10976 case BFD_RELOC_16_PCREL_S2
:
10977 if ((value
& 0x3) != 0)
10978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10979 _("Branch to odd address (%lx)"), (long) value
);
10981 /* Fall through. */
10983 case BFD_RELOC_16_PCREL
:
10985 * We need to save the bits in the instruction since fixup_segment()
10986 * might be deleting the relocation entry (i.e., a branch within
10987 * the current segment).
10989 if (!fixP
->fx_done
&& value
!= 0)
10991 /* If 'value' is zero, the remaining reloc code won't actually
10992 do the store, so it must be done here. This is probably
10993 a bug somewhere. */
10995 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
10996 || fixP
->fx_addsy
== NULL
/* ??? */
10997 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
10998 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11000 value
= (offsetT
) value
>> 2;
11002 /* update old instruction data */
11003 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
11004 if (target_big_endian
)
11005 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11007 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11009 if (value
+ 0x8000 <= 0xffff)
11010 insn
|= value
& 0xffff;
11013 /* The branch offset is too large. If this is an
11014 unconditional branch, and we are not generating PIC code,
11015 we can convert it to an absolute jump instruction. */
11016 if (mips_pic
== NO_PIC
11018 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11019 && (fixP
->fx_frag
->fr_address
11020 < text_section
->vma
+ text_section
->_raw_size
)
11021 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11022 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11023 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11025 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11026 insn
= 0x0c000000; /* jal */
11028 insn
= 0x08000000; /* j */
11029 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11031 fixP
->fx_addsy
= section_symbol (text_section
);
11032 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
11036 /* FIXME. It would be possible in principle to handle
11037 conditional branches which overflow. They could be
11038 transformed into a branch around a jump. This would
11039 require setting up variant frags for each different
11040 branch type. The native MIPS assembler attempts to
11041 handle these cases, but it appears to do it
11043 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11044 _("Branch out of range"));
11048 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11051 case BFD_RELOC_VTABLE_INHERIT
:
11054 && !S_IS_DEFINED (fixP
->fx_addsy
)
11055 && !S_IS_WEAK (fixP
->fx_addsy
))
11056 S_SET_WEAK (fixP
->fx_addsy
);
11059 case BFD_RELOC_VTABLE_ENTRY
:
11073 const struct mips_opcode
*p
;
11074 int treg
, sreg
, dreg
, shamt
;
11079 for (i
= 0; i
< NUMOPCODES
; ++i
)
11081 p
= &mips_opcodes
[i
];
11082 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11084 printf ("%08lx %s\t", oc
, p
->name
);
11085 treg
= (oc
>> 16) & 0x1f;
11086 sreg
= (oc
>> 21) & 0x1f;
11087 dreg
= (oc
>> 11) & 0x1f;
11088 shamt
= (oc
>> 6) & 0x1f;
11090 for (args
= p
->args
;; ++args
)
11101 printf ("%c", *args
);
11105 assert (treg
== sreg
);
11106 printf ("$%d,$%d", treg
, sreg
);
11111 printf ("$%d", dreg
);
11116 printf ("$%d", treg
);
11120 printf ("0x%x", treg
);
11125 printf ("$%d", sreg
);
11129 printf ("0x%08lx", oc
& 0x1ffffff);
11136 printf ("%d", imm
);
11141 printf ("$%d", shamt
);
11152 printf (_("%08lx UNDEFINED\n"), oc
);
11163 name
= input_line_pointer
;
11164 c
= get_symbol_end ();
11165 p
= (symbolS
*) symbol_find_or_make (name
);
11166 *input_line_pointer
= c
;
11170 /* Align the current frag to a given power of two. The MIPS assembler
11171 also automatically adjusts any preceding label. */
11174 mips_align (to
, fill
, label
)
11179 mips_emit_delays (false);
11180 frag_align (to
, fill
, 0);
11181 record_alignment (now_seg
, to
);
11184 assert (S_GET_SEGMENT (label
) == now_seg
);
11185 symbol_set_frag (label
, frag_now
);
11186 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11190 /* Align to a given power of two. .align 0 turns off the automatic
11191 alignment used by the data creating pseudo-ops. */
11195 int x ATTRIBUTE_UNUSED
;
11198 register long temp_fill
;
11199 long max_alignment
= 15;
11203 o Note that the assembler pulls down any immediately preceeding label
11204 to the aligned address.
11205 o It's not documented but auto alignment is reinstated by
11206 a .align pseudo instruction.
11207 o Note also that after auto alignment is turned off the mips assembler
11208 issues an error on attempt to assemble an improperly aligned data item.
11213 temp
= get_absolute_expression ();
11214 if (temp
> max_alignment
)
11215 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11218 as_warn (_("Alignment negative: 0 assumed."));
11221 if (*input_line_pointer
== ',')
11223 ++input_line_pointer
;
11224 temp_fill
= get_absolute_expression ();
11231 mips_align (temp
, (int) temp_fill
,
11232 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11239 demand_empty_rest_of_line ();
11243 mips_flush_pending_output ()
11245 mips_emit_delays (false);
11246 mips_clear_insn_labels ();
11255 /* When generating embedded PIC code, we only use the .text, .lit8,
11256 .sdata and .sbss sections. We change the .data and .rdata
11257 pseudo-ops to use .sdata. */
11258 if (mips_pic
== EMBEDDED_PIC
11259 && (sec
== 'd' || sec
== 'r'))
11263 /* The ELF backend needs to know that we are changing sections, so
11264 that .previous works correctly. We could do something like check
11265 for an obj_section_change_hook macro, but that might be confusing
11266 as it would not be appropriate to use it in the section changing
11267 functions in read.c, since obj-elf.c intercepts those. FIXME:
11268 This should be cleaner, somehow. */
11269 obj_elf_section_change_hook ();
11272 mips_emit_delays (false);
11282 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11283 demand_empty_rest_of_line ();
11287 if (USE_GLOBAL_POINTER_OPT
)
11289 seg
= subseg_new (RDATA_SECTION_NAME
,
11290 (subsegT
) get_absolute_expression ());
11291 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11293 bfd_set_section_flags (stdoutput
, seg
,
11299 if (strcmp (TARGET_OS
, "elf") != 0)
11300 record_alignment (seg
, 4);
11302 demand_empty_rest_of_line ();
11306 as_bad (_("No read only data section in this object file format"));
11307 demand_empty_rest_of_line ();
11313 if (USE_GLOBAL_POINTER_OPT
)
11315 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11316 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11318 bfd_set_section_flags (stdoutput
, seg
,
11319 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11321 if (strcmp (TARGET_OS
, "elf") != 0)
11322 record_alignment (seg
, 4);
11324 demand_empty_rest_of_line ();
11329 as_bad (_("Global pointers not supported; recompile -G 0"));
11330 demand_empty_rest_of_line ();
11339 s_change_section (ignore
)
11340 int ignore ATTRIBUTE_UNUSED
;
11343 char *section_name
;
11348 int section_entry_size
;
11349 int section_alignment
;
11351 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11354 section_name
= input_line_pointer
;
11355 c
= get_symbol_end ();
11356 next_c
= *(input_line_pointer
+ 1);
11358 /* Do we have .section Name<,"flags">? */
11359 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11361 /* just after name is now '\0'. */
11362 *input_line_pointer
= c
;
11363 input_line_pointer
= section_name
;
11364 obj_elf_section (ignore
);
11367 input_line_pointer
++;
11369 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11371 section_type
= get_absolute_expression ();
11374 if (*input_line_pointer
++ == ',')
11375 section_flag
= get_absolute_expression ();
11378 if (*input_line_pointer
++ == ',')
11379 section_entry_size
= get_absolute_expression ();
11381 section_entry_size
= 0;
11382 if (*input_line_pointer
++ == ',')
11383 section_alignment
= get_absolute_expression ();
11385 section_alignment
= 0;
11387 obj_elf_change_section (section_name
, section_type
, section_flag
,
11388 section_entry_size
, 0, 0, 0);
11389 #endif /* OBJ_ELF */
11393 mips_enable_auto_align ()
11404 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11405 mips_emit_delays (false);
11406 if (log_size
> 0 && auto_align
)
11407 mips_align (log_size
, 0, label
);
11408 mips_clear_insn_labels ();
11409 cons (1 << log_size
);
11413 s_float_cons (type
)
11418 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11420 mips_emit_delays (false);
11425 mips_align (3, 0, label
);
11427 mips_align (2, 0, label
);
11430 mips_clear_insn_labels ();
11435 /* Handle .globl. We need to override it because on Irix 5 you are
11438 where foo is an undefined symbol, to mean that foo should be
11439 considered to be the address of a function. */
11443 int x ATTRIBUTE_UNUSED
;
11450 name
= input_line_pointer
;
11451 c
= get_symbol_end ();
11452 symbolP
= symbol_find_or_make (name
);
11453 *input_line_pointer
= c
;
11454 SKIP_WHITESPACE ();
11456 /* On Irix 5, every global symbol that is not explicitly labelled as
11457 being a function is apparently labelled as being an object. */
11460 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11465 secname
= input_line_pointer
;
11466 c
= get_symbol_end ();
11467 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11469 as_bad (_("%s: no such section"), secname
);
11470 *input_line_pointer
= c
;
11472 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11473 flag
= BSF_FUNCTION
;
11476 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11478 S_SET_EXTERNAL (symbolP
);
11479 demand_empty_rest_of_line ();
11484 int x ATTRIBUTE_UNUSED
;
11489 opt
= input_line_pointer
;
11490 c
= get_symbol_end ();
11494 /* FIXME: What does this mean? */
11496 else if (strncmp (opt
, "pic", 3) == 0)
11500 i
= atoi (opt
+ 3);
11504 mips_pic
= SVR4_PIC
;
11506 as_bad (_(".option pic%d not supported"), i
);
11508 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11510 if (g_switch_seen
&& g_switch_value
!= 0)
11511 as_warn (_("-G may not be used with SVR4 PIC code"));
11512 g_switch_value
= 0;
11513 bfd_set_gp_size (stdoutput
, 0);
11517 as_warn (_("Unrecognized option \"%s\""), opt
);
11519 *input_line_pointer
= c
;
11520 demand_empty_rest_of_line ();
11523 /* This structure is used to hold a stack of .set values. */
11525 struct mips_option_stack
11527 struct mips_option_stack
*next
;
11528 struct mips_set_options options
;
11531 static struct mips_option_stack
*mips_opts_stack
;
11533 /* Handle the .set pseudo-op. */
11537 int x ATTRIBUTE_UNUSED
;
11539 char *name
= input_line_pointer
, ch
;
11541 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11542 ++input_line_pointer
;
11543 ch
= *input_line_pointer
;
11544 *input_line_pointer
= '\0';
11546 if (strcmp (name
, "reorder") == 0)
11548 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11550 /* If we still have pending nops, we can discard them. The
11551 usual nop handling will insert any that are still
11553 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11554 * (mips_opts
.mips16
? 2 : 4));
11555 prev_nop_frag
= NULL
;
11557 mips_opts
.noreorder
= 0;
11559 else if (strcmp (name
, "noreorder") == 0)
11561 mips_emit_delays (true);
11562 mips_opts
.noreorder
= 1;
11563 mips_any_noreorder
= 1;
11565 else if (strcmp (name
, "at") == 0)
11567 mips_opts
.noat
= 0;
11569 else if (strcmp (name
, "noat") == 0)
11571 mips_opts
.noat
= 1;
11573 else if (strcmp (name
, "macro") == 0)
11575 mips_opts
.warn_about_macros
= 0;
11577 else if (strcmp (name
, "nomacro") == 0)
11579 if (mips_opts
.noreorder
== 0)
11580 as_bad (_("`noreorder' must be set before `nomacro'"));
11581 mips_opts
.warn_about_macros
= 1;
11583 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11585 mips_opts
.nomove
= 0;
11587 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11589 mips_opts
.nomove
= 1;
11591 else if (strcmp (name
, "bopt") == 0)
11593 mips_opts
.nobopt
= 0;
11595 else if (strcmp (name
, "nobopt") == 0)
11597 mips_opts
.nobopt
= 1;
11599 else if (strcmp (name
, "mips16") == 0
11600 || strcmp (name
, "MIPS-16") == 0)
11601 mips_opts
.mips16
= 1;
11602 else if (strcmp (name
, "nomips16") == 0
11603 || strcmp (name
, "noMIPS-16") == 0)
11604 mips_opts
.mips16
= 0;
11605 else if (strcmp (name
, "mips3d") == 0)
11606 mips_opts
.ase_mips3d
= 1;
11607 else if (strcmp (name
, "nomips3d") == 0)
11608 mips_opts
.ase_mips3d
= 0;
11609 else if (strcmp (name
, "mdmx") == 0)
11610 mips_opts
.ase_mdmx
= 1;
11611 else if (strcmp (name
, "nomdmx") == 0)
11612 mips_opts
.ase_mdmx
= 0;
11613 else if (strncmp (name
, "mips", 4) == 0)
11617 /* Permit the user to change the ISA on the fly. Needless to
11618 say, misuse can cause serious problems. */
11619 isa
= atoi (name
+ 4);
11623 mips_opts
.gp32
= file_mips_gp32
;
11624 mips_opts
.fp32
= file_mips_fp32
;
11629 mips_opts
.gp32
= 1;
11630 mips_opts
.fp32
= 1;
11636 mips_opts
.gp32
= 0;
11637 mips_opts
.fp32
= 0;
11640 as_bad (_("unknown ISA level %s"), name
+ 4);
11646 case 0: mips_opts
.isa
= file_mips_isa
; break;
11647 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11648 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11649 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11650 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11651 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11652 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11653 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11654 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11657 else if (strcmp (name
, "autoextend") == 0)
11658 mips_opts
.noautoextend
= 0;
11659 else if (strcmp (name
, "noautoextend") == 0)
11660 mips_opts
.noautoextend
= 1;
11661 else if (strcmp (name
, "push") == 0)
11663 struct mips_option_stack
*s
;
11665 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11666 s
->next
= mips_opts_stack
;
11667 s
->options
= mips_opts
;
11668 mips_opts_stack
= s
;
11670 else if (strcmp (name
, "pop") == 0)
11672 struct mips_option_stack
*s
;
11674 s
= mips_opts_stack
;
11676 as_bad (_(".set pop with no .set push"));
11679 /* If we're changing the reorder mode we need to handle
11680 delay slots correctly. */
11681 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11682 mips_emit_delays (true);
11683 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11685 if (prev_nop_frag
!= NULL
)
11687 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11688 * (mips_opts
.mips16
? 2 : 4));
11689 prev_nop_frag
= NULL
;
11693 mips_opts
= s
->options
;
11694 mips_opts_stack
= s
->next
;
11700 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11702 *input_line_pointer
= ch
;
11703 demand_empty_rest_of_line ();
11706 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11707 .option pic2. It means to generate SVR4 PIC calls. */
11710 s_abicalls (ignore
)
11711 int ignore ATTRIBUTE_UNUSED
;
11713 mips_pic
= SVR4_PIC
;
11714 if (USE_GLOBAL_POINTER_OPT
)
11716 if (g_switch_seen
&& g_switch_value
!= 0)
11717 as_warn (_("-G may not be used with SVR4 PIC code"));
11718 g_switch_value
= 0;
11720 bfd_set_gp_size (stdoutput
, 0);
11721 demand_empty_rest_of_line ();
11724 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11725 PIC code. It sets the $gp register for the function based on the
11726 function address, which is in the register named in the argument.
11727 This uses a relocation against _gp_disp, which is handled specially
11728 by the linker. The result is:
11729 lui $gp,%hi(_gp_disp)
11730 addiu $gp,$gp,%lo(_gp_disp)
11731 addu $gp,$gp,.cpload argument
11732 The .cpload argument is normally $25 == $t9. */
11736 int ignore ATTRIBUTE_UNUSED
;
11741 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11742 .cpload is ignored. */
11743 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11749 /* .cpload should be in a .set noreorder section. */
11750 if (mips_opts
.noreorder
== 0)
11751 as_warn (_(".cpload not in noreorder section"));
11753 ex
.X_op
= O_symbol
;
11754 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11755 ex
.X_op_symbol
= NULL
;
11756 ex
.X_add_number
= 0;
11758 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11759 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11761 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
11762 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
11763 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
11765 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11766 mips_gp_register
, mips_gp_register
, tc_get_register (0));
11768 demand_empty_rest_of_line ();
11771 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11772 .cpsetup $reg1, offset|$reg2, label
11774 If offset is given, this results in:
11775 sd $gp, offset($sp)
11776 lui $gp, %hi(%neg(%gp_rel(label)))
11777 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11778 daddu $gp, $gp, $reg1
11780 If $reg2 is given, this results in:
11781 daddu $reg2, $gp, $0
11782 lui $gp, %hi(%neg(%gp_rel(label)))
11783 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11784 daddu $gp, $gp, $reg1
11785 $reg1 is normally $25 == $t9. */
11788 int ignore ATTRIBUTE_UNUSED
;
11790 expressionS ex_off
;
11791 expressionS ex_sym
;
11796 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11797 We also need NewABI support. */
11798 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11804 reg1
= tc_get_register (0);
11805 SKIP_WHITESPACE ();
11806 if (*input_line_pointer
!= ',')
11808 as_bad (_("missing argument separator ',' for .cpsetup"));
11812 ++input_line_pointer
;
11813 SKIP_WHITESPACE ();
11814 if (*input_line_pointer
== '$')
11816 mips_cpreturn_register
= tc_get_register (0);
11817 mips_cpreturn_offset
= -1;
11821 mips_cpreturn_offset
= get_absolute_expression ();
11822 mips_cpreturn_register
= -1;
11824 SKIP_WHITESPACE ();
11825 if (*input_line_pointer
!= ',')
11827 as_bad (_("missing argument separator ',' for .cpsetup"));
11831 ++input_line_pointer
;
11832 SKIP_WHITESPACE ();
11833 expression (&ex_sym
);
11835 if (mips_cpreturn_register
== -1)
11837 ex_off
.X_op
= O_constant
;
11838 ex_off
.X_add_symbol
= NULL
;
11839 ex_off
.X_op_symbol
= NULL
;
11840 ex_off
.X_add_number
= mips_cpreturn_offset
;
11842 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11843 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11846 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11847 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
11849 /* Ensure there's room for the next two instructions, so that `f'
11850 doesn't end up with an address in the wrong frag. */
11853 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
11854 (int) BFD_RELOC_GPREL16
);
11855 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11856 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11857 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11858 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
11861 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
11862 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
11863 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11864 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11865 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11866 0, NULL
, 0, 0, BFD_RELOC_LO16
);
11868 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11869 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
11870 mips_gp_register
, mips_gp_register
, reg1
);
11872 demand_empty_rest_of_line ();
11877 int ignore ATTRIBUTE_UNUSED
;
11879 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11880 .cplocal is ignored. */
11881 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11887 mips_gp_register
= tc_get_register (0);
11888 demand_empty_rest_of_line ();
11891 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11892 offset from $sp. The offset is remembered, and after making a PIC
11893 call $gp is restored from that location. */
11896 s_cprestore (ignore
)
11897 int ignore ATTRIBUTE_UNUSED
;
11902 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11903 .cprestore is ignored. */
11904 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11910 mips_cprestore_offset
= get_absolute_expression ();
11911 mips_cprestore_valid
= 1;
11913 ex
.X_op
= O_constant
;
11914 ex
.X_add_symbol
= NULL
;
11915 ex
.X_op_symbol
= NULL
;
11916 ex
.X_add_number
= mips_cprestore_offset
;
11918 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
,
11919 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
11920 mips_gp_register
, SP
);
11922 demand_empty_rest_of_line ();
11925 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11926 was given in the preceeding .gpsetup, it results in:
11927 ld $gp, offset($sp)
11929 If a register $reg2 was given there, it results in:
11930 daddiu $gp, $gp, $reg2
11933 s_cpreturn (ignore
)
11934 int ignore ATTRIBUTE_UNUSED
;
11939 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11940 We also need NewABI support. */
11941 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11947 if (mips_cpreturn_register
== -1)
11949 ex
.X_op
= O_constant
;
11950 ex
.X_add_symbol
= NULL
;
11951 ex
.X_op_symbol
= NULL
;
11952 ex
.X_add_number
= mips_cpreturn_offset
;
11954 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
11955 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11958 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11959 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
11961 demand_empty_rest_of_line ();
11964 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11965 code. It sets the offset to use in gp_rel relocations. */
11969 int ignore ATTRIBUTE_UNUSED
;
11971 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11972 We also need NewABI support. */
11973 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11979 mips_gprel_offset
= get_absolute_expression ();
11981 demand_empty_rest_of_line ();
11984 /* Handle the .gpword pseudo-op. This is used when generating PIC
11985 code. It generates a 32 bit GP relative reloc. */
11989 int ignore ATTRIBUTE_UNUSED
;
11995 /* When not generating PIC code, this is treated as .word. */
11996 if (mips_pic
!= SVR4_PIC
)
12002 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12003 mips_emit_delays (true);
12005 mips_align (2, 0, label
);
12006 mips_clear_insn_labels ();
12010 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12012 as_bad (_("Unsupported use of .gpword"));
12013 ignore_rest_of_line ();
12017 md_number_to_chars (p
, (valueT
) 0, 4);
12018 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
12019 BFD_RELOC_GPREL32
);
12021 demand_empty_rest_of_line ();
12024 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12025 tables in SVR4 PIC code. */
12029 int ignore ATTRIBUTE_UNUSED
;
12034 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
12036 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12042 /* Add $gp to the register named as an argument. */
12043 reg
= tc_get_register (0);
12044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12045 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
12046 "d,v,t", reg
, reg
, mips_gp_register
);
12048 demand_empty_rest_of_line ();
12051 /* Handle the .insn pseudo-op. This marks instruction labels in
12052 mips16 mode. This permits the linker to handle them specially,
12053 such as generating jalx instructions when needed. We also make
12054 them odd for the duration of the assembly, in order to generate the
12055 right sort of code. We will make them even in the adjust_symtab
12056 routine, while leaving them marked. This is convenient for the
12057 debugger and the disassembler. The linker knows to make them odd
12062 int ignore ATTRIBUTE_UNUSED
;
12064 mips16_mark_labels ();
12066 demand_empty_rest_of_line ();
12069 /* Handle a .stabn directive. We need these in order to mark a label
12070 as being a mips16 text label correctly. Sometimes the compiler
12071 will emit a label, followed by a .stabn, and then switch sections.
12072 If the label and .stabn are in mips16 mode, then the label is
12073 really a mips16 text label. */
12080 mips16_mark_labels ();
12085 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12089 s_mips_weakext (ignore
)
12090 int ignore ATTRIBUTE_UNUSED
;
12097 name
= input_line_pointer
;
12098 c
= get_symbol_end ();
12099 symbolP
= symbol_find_or_make (name
);
12100 S_SET_WEAK (symbolP
);
12101 *input_line_pointer
= c
;
12103 SKIP_WHITESPACE ();
12105 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12107 if (S_IS_DEFINED (symbolP
))
12109 as_bad ("ignoring attempt to redefine symbol %s",
12110 S_GET_NAME (symbolP
));
12111 ignore_rest_of_line ();
12115 if (*input_line_pointer
== ',')
12117 ++input_line_pointer
;
12118 SKIP_WHITESPACE ();
12122 if (exp
.X_op
!= O_symbol
)
12124 as_bad ("bad .weakext directive");
12125 ignore_rest_of_line ();
12128 symbol_set_value_expression (symbolP
, &exp
);
12131 demand_empty_rest_of_line ();
12134 /* Parse a register string into a number. Called from the ECOFF code
12135 to parse .frame. The argument is non-zero if this is the frame
12136 register, so that we can record it in mips_frame_reg. */
12139 tc_get_register (frame
)
12144 SKIP_WHITESPACE ();
12145 if (*input_line_pointer
++ != '$')
12147 as_warn (_("expected `$'"));
12150 else if (ISDIGIT (*input_line_pointer
))
12152 reg
= get_absolute_expression ();
12153 if (reg
< 0 || reg
>= 32)
12155 as_warn (_("Bad register number"));
12161 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12164 input_line_pointer
+= 2;
12166 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12169 input_line_pointer
+= 2;
12171 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12174 input_line_pointer
+= 2;
12176 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12179 input_line_pointer
+= 2;
12181 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12184 input_line_pointer
+= 2;
12186 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12189 input_line_pointer
+= 3;
12191 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12194 input_line_pointer
+= 3;
12196 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12199 input_line_pointer
+= 4;
12203 as_warn (_("Unrecognized register name"));
12205 while (ISALNUM(*input_line_pointer
))
12206 input_line_pointer
++;
12211 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12212 mips_frame_reg_valid
= 1;
12213 mips_cprestore_valid
= 0;
12219 md_section_align (seg
, addr
)
12223 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12226 /* We don't need to align ELF sections to the full alignment.
12227 However, Irix 5 may prefer that we align them at least to a 16
12228 byte boundary. We don't bother to align the sections if we are
12229 targeted for an embedded system. */
12230 if (strcmp (TARGET_OS
, "elf") == 0)
12236 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12239 /* Utility routine, called from above as well. If called while the
12240 input file is still being read, it's only an approximation. (For
12241 example, a symbol may later become defined which appeared to be
12242 undefined earlier.) */
12245 nopic_need_relax (sym
, before_relaxing
)
12247 int before_relaxing
;
12252 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12254 const char *symname
;
12257 /* Find out whether this symbol can be referenced off the $gp
12258 register. It can be if it is smaller than the -G size or if
12259 it is in the .sdata or .sbss section. Certain symbols can
12260 not be referenced off the $gp, although it appears as though
12262 symname
= S_GET_NAME (sym
);
12263 if (symname
!= (const char *) NULL
12264 && (strcmp (symname
, "eprol") == 0
12265 || strcmp (symname
, "etext") == 0
12266 || strcmp (symname
, "_gp") == 0
12267 || strcmp (symname
, "edata") == 0
12268 || strcmp (symname
, "_fbss") == 0
12269 || strcmp (symname
, "_fdata") == 0
12270 || strcmp (symname
, "_ftext") == 0
12271 || strcmp (symname
, "end") == 0
12272 || strcmp (symname
, "_gp_disp") == 0))
12274 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12276 #ifndef NO_ECOFF_DEBUGGING
12277 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12278 && (symbol_get_obj (sym
)->ecoff_extern_size
12279 <= g_switch_value
))
12281 /* We must defer this decision until after the whole
12282 file has been read, since there might be a .extern
12283 after the first use of this symbol. */
12284 || (before_relaxing
12285 #ifndef NO_ECOFF_DEBUGGING
12286 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12288 && S_GET_VALUE (sym
) == 0)
12289 || (S_GET_VALUE (sym
) != 0
12290 && S_GET_VALUE (sym
) <= g_switch_value
)))
12294 const char *segname
;
12296 segname
= segment_name (S_GET_SEGMENT (sym
));
12297 assert (strcmp (segname
, ".lit8") != 0
12298 && strcmp (segname
, ".lit4") != 0);
12299 change
= (strcmp (segname
, ".sdata") != 0
12300 && strcmp (segname
, ".sbss") != 0
12301 && strncmp (segname
, ".sdata.", 7) != 0
12302 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12307 /* We are not optimizing for the $gp register. */
12311 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12312 extended opcode. SEC is the section the frag is in. */
12315 mips16_extended_frag (fragp
, sec
, stretch
)
12321 register const struct mips16_immed_operand
*op
;
12323 int mintiny
, maxtiny
;
12327 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12329 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12332 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12333 op
= mips16_immed_operands
;
12334 while (op
->type
!= type
)
12337 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12342 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12345 maxtiny
= 1 << op
->nbits
;
12350 maxtiny
= (1 << op
->nbits
) - 1;
12355 mintiny
= - (1 << (op
->nbits
- 1));
12356 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12359 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12360 val
= S_GET_VALUE (fragp
->fr_symbol
);
12361 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12367 /* We won't have the section when we are called from
12368 mips_relax_frag. However, we will always have been called
12369 from md_estimate_size_before_relax first. If this is a
12370 branch to a different section, we mark it as such. If SEC is
12371 NULL, and the frag is not marked, then it must be a branch to
12372 the same section. */
12375 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12380 /* Must have been called from md_estimate_size_before_relax. */
12383 fragp
->fr_subtype
=
12384 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12386 /* FIXME: We should support this, and let the linker
12387 catch branches and loads that are out of range. */
12388 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12389 _("unsupported PC relative reference to different section"));
12393 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12394 /* Assume non-extended on the first relaxation pass.
12395 The address we have calculated will be bogus if this is
12396 a forward branch to another frag, as the forward frag
12397 will have fr_address == 0. */
12401 /* In this case, we know for sure that the symbol fragment is in
12402 the same section. If the relax_marker of the symbol fragment
12403 differs from the relax_marker of this fragment, we have not
12404 yet adjusted the symbol fragment fr_address. We want to add
12405 in STRETCH in order to get a better estimate of the address.
12406 This particularly matters because of the shift bits. */
12408 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12412 /* Adjust stretch for any alignment frag. Note that if have
12413 been expanding the earlier code, the symbol may be
12414 defined in what appears to be an earlier frag. FIXME:
12415 This doesn't handle the fr_subtype field, which specifies
12416 a maximum number of bytes to skip when doing an
12418 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12420 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12423 stretch
= - ((- stretch
)
12424 & ~ ((1 << (int) f
->fr_offset
) - 1));
12426 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12435 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12437 /* The base address rules are complicated. The base address of
12438 a branch is the following instruction. The base address of a
12439 PC relative load or add is the instruction itself, but if it
12440 is in a delay slot (in which case it can not be extended) use
12441 the address of the instruction whose delay slot it is in. */
12442 if (type
== 'p' || type
== 'q')
12446 /* If we are currently assuming that this frag should be
12447 extended, then, the current address is two bytes
12449 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12452 /* Ignore the low bit in the target, since it will be set
12453 for a text label. */
12454 if ((val
& 1) != 0)
12457 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12459 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12462 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12464 /* Branch offsets have an implicit 0 in the lowest bit. */
12465 if (type
== 'p' || type
== 'q')
12468 /* If any of the shifted bits are set, we must use an extended
12469 opcode. If the address depends on the size of this
12470 instruction, this can lead to a loop, so we arrange to always
12471 use an extended opcode. We only check this when we are in
12472 the main relaxation loop, when SEC is NULL. */
12473 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12475 fragp
->fr_subtype
=
12476 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12480 /* If we are about to mark a frag as extended because the value
12481 is precisely maxtiny + 1, then there is a chance of an
12482 infinite loop as in the following code:
12487 In this case when the la is extended, foo is 0x3fc bytes
12488 away, so the la can be shrunk, but then foo is 0x400 away, so
12489 the la must be extended. To avoid this loop, we mark the
12490 frag as extended if it was small, and is about to become
12491 extended with a value of maxtiny + 1. */
12492 if (val
== ((maxtiny
+ 1) << op
->shift
)
12493 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12496 fragp
->fr_subtype
=
12497 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12501 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12502 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12504 if ((val
& ((1 << op
->shift
) - 1)) != 0
12505 || val
< (mintiny
<< op
->shift
)
12506 || val
> (maxtiny
<< op
->shift
))
12512 /* Estimate the size of a frag before relaxing. Unless this is the
12513 mips16, we are not really relaxing here, and the final size is
12514 encoded in the subtype information. For the mips16, we have to
12515 decide whether we are using an extended opcode or not. */
12518 md_estimate_size_before_relax (fragp
, segtype
)
12523 boolean linkonce
= false;
12525 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12526 /* We don't want to modify the EXTENDED bit here; it might get us
12527 into infinite loops. We change it only in mips_relax_frag(). */
12528 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12530 if (mips_pic
== NO_PIC
)
12532 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12534 else if (mips_pic
== SVR4_PIC
)
12539 sym
= fragp
->fr_symbol
;
12541 /* Handle the case of a symbol equated to another symbol. */
12542 while (symbol_equated_reloc_p (sym
))
12546 /* It's possible to get a loop here in a badly written
12548 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12554 symsec
= S_GET_SEGMENT (sym
);
12556 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12557 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12559 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12563 /* The GNU toolchain uses an extension for ELF: a section
12564 beginning with the magic string .gnu.linkonce is a linkonce
12566 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12567 sizeof ".gnu.linkonce" - 1) == 0)
12571 /* This must duplicate the test in adjust_reloc_syms. */
12572 change
= (symsec
!= &bfd_und_section
12573 && symsec
!= &bfd_abs_section
12574 && ! bfd_is_com_section (symsec
)
12577 /* A global or weak symbol is treated as external. */
12578 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12579 || (! S_IS_WEAK (sym
)
12580 && (! S_IS_EXTERNAL (sym
)
12581 || mips_pic
== EMBEDDED_PIC
)))
12590 /* Record the offset to the first reloc in the fr_opcode field.
12591 This lets md_convert_frag and tc_gen_reloc know that the code
12592 must be expanded. */
12593 fragp
->fr_opcode
= (fragp
->fr_literal
12595 - RELAX_OLD (fragp
->fr_subtype
)
12596 + RELAX_RELOC1 (fragp
->fr_subtype
));
12597 /* FIXME: This really needs as_warn_where. */
12598 if (RELAX_WARN (fragp
->fr_subtype
))
12599 as_warn (_("AT used after \".set noat\" or macro used after "
12600 "\".set nomacro\""));
12602 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
12608 /* This is called to see whether a reloc against a defined symbol
12609 should be converted into a reloc against a section. Don't adjust
12610 MIPS16 jump relocations, so we don't have to worry about the format
12611 of the offset in the .o file. Don't adjust relocations against
12612 mips16 symbols, so that the linker can find them if it needs to set
12616 mips_fix_adjustable (fixp
)
12619 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12622 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12623 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12626 if (fixp
->fx_addsy
== NULL
)
12630 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12631 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12632 && fixp
->fx_subsy
== NULL
)
12639 /* Translate internal representation of relocation info to BFD target
12643 tc_gen_reloc (section
, fixp
)
12644 asection
*section ATTRIBUTE_UNUSED
;
12647 static arelent
*retval
[4];
12649 bfd_reloc_code_real_type code
;
12651 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12654 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12655 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12656 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12658 if (mips_pic
== EMBEDDED_PIC
12659 && SWITCH_TABLE (fixp
))
12661 /* For a switch table entry we use a special reloc. The addend
12662 is actually the difference between the reloc address and the
12664 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12665 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12666 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12667 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12669 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12671 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12672 reloc
->addend
= fixp
->fx_addnumber
;
12675 /* We use a special addend for an internal RELLO reloc. */
12676 if (symbol_section_p (fixp
->fx_addsy
))
12677 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12679 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12682 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12684 assert (fixp
->fx_next
!= NULL
12685 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12687 /* The reloc is relative to the RELLO; adjust the addend
12689 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12690 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
12693 /* We use a special addend for an internal RELHI reloc. */
12694 if (symbol_section_p (fixp
->fx_addsy
))
12695 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12696 + fixp
->fx_next
->fx_where
12697 - S_GET_VALUE (fixp
->fx_subsy
));
12699 reloc
->addend
= (fixp
->fx_addnumber
12700 + fixp
->fx_next
->fx_frag
->fr_address
12701 + fixp
->fx_next
->fx_where
);
12704 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12705 reloc
->addend
= fixp
->fx_addnumber
;
12708 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12709 /* A gruesome hack which is a result of the gruesome gas reloc
12711 reloc
->addend
= reloc
->address
;
12713 reloc
->addend
= -reloc
->address
;
12716 /* If this is a variant frag, we may need to adjust the existing
12717 reloc and generate a new one. */
12718 if (fixp
->fx_frag
->fr_opcode
!= NULL
12719 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12721 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12722 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12723 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12724 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12725 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12726 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12731 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12733 /* If this is not the last reloc in this frag, then we have two
12734 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12735 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12736 the second one handle all of them. */
12737 if (fixp
->fx_next
!= NULL
12738 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12740 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12741 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
12742 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12743 && (fixp
->fx_next
->fx_r_type
12744 == BFD_RELOC_MIPS_GOT_LO16
))
12745 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12746 && (fixp
->fx_next
->fx_r_type
12747 == BFD_RELOC_MIPS_CALL_LO16
)));
12752 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12753 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12754 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12756 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12757 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12758 reloc2
->address
= (reloc
->address
12759 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12760 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12761 reloc2
->addend
= fixp
->fx_addnumber
;
12762 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12763 assert (reloc2
->howto
!= NULL
);
12765 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12769 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12772 reloc3
->address
+= 4;
12775 if (mips_pic
== NO_PIC
)
12777 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
12778 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12780 else if (mips_pic
== SVR4_PIC
)
12782 switch (fixp
->fx_r_type
)
12786 case BFD_RELOC_MIPS_GOT16
:
12788 case BFD_RELOC_MIPS_GOT_LO16
:
12789 case BFD_RELOC_MIPS_CALL_LO16
:
12790 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12792 case BFD_RELOC_MIPS_CALL16
:
12795 /* BFD_RELOC_MIPS_GOT16;*/
12796 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
12797 reloc2
->howto
= bfd_reloc_type_lookup
12798 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
12801 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12808 /* newabi uses R_MIPS_GOT_DISP for local symbols */
12809 if (HAVE_NEWABI
&& BFD_RELOC_MIPS_GOT_LO16
)
12811 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
12816 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12817 entry to be used in the relocation's section offset. */
12818 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12820 reloc
->address
= reloc
->addend
;
12824 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12825 fixup_segment converted a non-PC relative reloc into a PC
12826 relative reloc. In such a case, we need to convert the reloc
12828 code
= fixp
->fx_r_type
;
12829 if (fixp
->fx_pcrel
)
12834 code
= BFD_RELOC_8_PCREL
;
12837 code
= BFD_RELOC_16_PCREL
;
12840 code
= BFD_RELOC_32_PCREL
;
12843 code
= BFD_RELOC_64_PCREL
;
12845 case BFD_RELOC_8_PCREL
:
12846 case BFD_RELOC_16_PCREL
:
12847 case BFD_RELOC_32_PCREL
:
12848 case BFD_RELOC_64_PCREL
:
12849 case BFD_RELOC_16_PCREL_S2
:
12850 case BFD_RELOC_PCREL_HI16_S
:
12851 case BFD_RELOC_PCREL_LO16
:
12854 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12855 _("Cannot make %s relocation PC relative"),
12856 bfd_get_reloc_code_name (code
));
12861 /* md_apply_fix3 has a double-subtraction hack to get
12862 bfd_install_relocation to behave nicely. GPREL relocations are
12863 handled correctly without this hack, so undo it here. We can't
12864 stop md_apply_fix3 from subtracting twice in the first place since
12865 the fake addend is required for variant frags above. */
12866 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
12867 && (code
== BFD_RELOC_GPREL16
|| code
== BFD_RELOC_MIPS16_GPREL
)
12868 && reloc
->addend
!= 0
12869 && mips_need_elf_addend_fixup (fixp
))
12870 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
12873 /* To support a PC relative reloc when generating embedded PIC code
12874 for ECOFF, we use a Cygnus extension. We check for that here to
12875 make sure that we don't let such a reloc escape normally. */
12876 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12877 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12878 && code
== BFD_RELOC_16_PCREL_S2
12879 && mips_pic
!= EMBEDDED_PIC
)
12880 reloc
->howto
= NULL
;
12882 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12884 if (reloc
->howto
== NULL
)
12886 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12887 _("Can not represent %s relocation in this object file format"),
12888 bfd_get_reloc_code_name (code
));
12895 /* Relax a machine dependent frag. This returns the amount by which
12896 the current size of the frag should change. */
12899 mips_relax_frag (fragp
, stretch
)
12903 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12906 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12908 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12910 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12915 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12917 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12924 /* Convert a machine dependent frag. */
12927 md_convert_frag (abfd
, asec
, fragp
)
12928 bfd
*abfd ATTRIBUTE_UNUSED
;
12935 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12938 register const struct mips16_immed_operand
*op
;
12939 boolean small
, ext
;
12942 unsigned long insn
;
12943 boolean use_extend
;
12944 unsigned short extend
;
12946 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12947 op
= mips16_immed_operands
;
12948 while (op
->type
!= type
)
12951 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12962 resolve_symbol_value (fragp
->fr_symbol
);
12963 val
= S_GET_VALUE (fragp
->fr_symbol
);
12968 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12970 /* The rules for the base address of a PC relative reloc are
12971 complicated; see mips16_extended_frag. */
12972 if (type
== 'p' || type
== 'q')
12977 /* Ignore the low bit in the target, since it will be
12978 set for a text label. */
12979 if ((val
& 1) != 0)
12982 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12984 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12987 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12990 /* Make sure the section winds up with the alignment we have
12993 record_alignment (asec
, op
->shift
);
12997 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
12998 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
12999 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13000 _("extended instruction in delay slot"));
13002 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13004 if (target_big_endian
)
13005 insn
= bfd_getb16 (buf
);
13007 insn
= bfd_getl16 (buf
);
13009 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13010 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13011 small
, ext
, &insn
, &use_extend
, &extend
);
13015 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13016 fragp
->fr_fix
+= 2;
13020 md_number_to_chars ((char *) buf
, insn
, 2);
13021 fragp
->fr_fix
+= 2;
13026 if (fragp
->fr_opcode
== NULL
)
13029 old
= RELAX_OLD (fragp
->fr_subtype
);
13030 new = RELAX_NEW (fragp
->fr_subtype
);
13031 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
13034 memcpy (fixptr
- old
, fixptr
, new);
13036 fragp
->fr_fix
+= new - old
;
13042 /* This function is called after the relocs have been generated.
13043 We've been storing mips16 text labels as odd. Here we convert them
13044 back to even for the convenience of the debugger. */
13047 mips_frob_file_after_relocs ()
13050 unsigned int count
, i
;
13052 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13055 syms
= bfd_get_outsymbols (stdoutput
);
13056 count
= bfd_get_symcount (stdoutput
);
13057 for (i
= 0; i
< count
; i
++, syms
++)
13059 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13060 && ((*syms
)->value
& 1) != 0)
13062 (*syms
)->value
&= ~1;
13063 /* If the symbol has an odd size, it was probably computed
13064 incorrectly, so adjust that as well. */
13065 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13066 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13073 /* This function is called whenever a label is defined. It is used
13074 when handling branch delays; if a branch has a label, we assume we
13075 can not move it. */
13078 mips_define_label (sym
)
13081 struct insn_label_list
*l
;
13083 if (free_insn_labels
== NULL
)
13084 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13087 l
= free_insn_labels
;
13088 free_insn_labels
= l
->next
;
13092 l
->next
= insn_labels
;
13096 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13098 /* Some special processing for a MIPS ELF file. */
13101 mips_elf_final_processing ()
13103 /* Write out the register information. */
13104 if (mips_abi
!= N64_ABI
)
13108 s
.ri_gprmask
= mips_gprmask
;
13109 s
.ri_cprmask
[0] = mips_cprmask
[0];
13110 s
.ri_cprmask
[1] = mips_cprmask
[1];
13111 s
.ri_cprmask
[2] = mips_cprmask
[2];
13112 s
.ri_cprmask
[3] = mips_cprmask
[3];
13113 /* The gp_value field is set by the MIPS ELF backend. */
13115 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13116 ((Elf32_External_RegInfo
*)
13117 mips_regmask_frag
));
13121 Elf64_Internal_RegInfo s
;
13123 s
.ri_gprmask
= mips_gprmask
;
13125 s
.ri_cprmask
[0] = mips_cprmask
[0];
13126 s
.ri_cprmask
[1] = mips_cprmask
[1];
13127 s
.ri_cprmask
[2] = mips_cprmask
[2];
13128 s
.ri_cprmask
[3] = mips_cprmask
[3];
13129 /* The gp_value field is set by the MIPS ELF backend. */
13131 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13132 ((Elf64_External_RegInfo
*)
13133 mips_regmask_frag
));
13136 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13137 sort of BFD interface for this. */
13138 if (mips_any_noreorder
)
13139 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13140 if (mips_pic
!= NO_PIC
)
13141 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13143 /* Set MIPS ELF flags for ASEs. */
13144 if (file_ase_mips16
)
13145 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13146 #if 0 /* XXX FIXME */
13147 if (file_ase_mips3d
)
13148 elf_elfheader (stdoutput
)->e_flags
|= ???;
13151 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13153 /* Set the MIPS ELF ABI flags. */
13154 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13155 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13156 else if (mips_abi
== O64_ABI
)
13157 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13158 else if (mips_abi
== EABI_ABI
)
13160 if (!file_mips_gp32
)
13161 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13163 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13165 else if (mips_abi
== N32_ABI
)
13166 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13168 /* Nothing to do for N64_ABI. */
13170 if (mips_32bitmode
)
13171 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13174 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13176 typedef struct proc
{
13178 unsigned long reg_mask
;
13179 unsigned long reg_offset
;
13180 unsigned long fpreg_mask
;
13181 unsigned long fpreg_offset
;
13182 unsigned long frame_offset
;
13183 unsigned long frame_reg
;
13184 unsigned long pc_reg
;
13187 static procS cur_proc
;
13188 static procS
*cur_proc_ptr
;
13189 static int numprocs
;
13191 /* Fill in an rs_align_code fragment. */
13194 mips_handle_align (fragp
)
13197 if (fragp
->fr_type
!= rs_align_code
)
13200 if (mips_opts
.mips16
)
13202 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13203 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13208 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13209 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13217 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13221 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13232 /* check for premature end, nesting errors, etc */
13234 as_warn (_("missing .end at end of assembly"));
13243 if (*input_line_pointer
== '-')
13245 ++input_line_pointer
;
13248 if (!ISDIGIT (*input_line_pointer
))
13249 as_bad (_("expected simple number"));
13250 if (input_line_pointer
[0] == '0')
13252 if (input_line_pointer
[1] == 'x')
13254 input_line_pointer
+= 2;
13255 while (ISXDIGIT (*input_line_pointer
))
13258 val
|= hex_value (*input_line_pointer
++);
13260 return negative
? -val
: val
;
13264 ++input_line_pointer
;
13265 while (ISDIGIT (*input_line_pointer
))
13268 val
|= *input_line_pointer
++ - '0';
13270 return negative
? -val
: val
;
13273 if (!ISDIGIT (*input_line_pointer
))
13275 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13276 *input_line_pointer
, *input_line_pointer
);
13277 as_warn (_("invalid number"));
13280 while (ISDIGIT (*input_line_pointer
))
13283 val
+= *input_line_pointer
++ - '0';
13285 return negative
? -val
: val
;
13288 /* The .file directive; just like the usual .file directive, but there
13289 is an initial number which is the ECOFF file index. In the non-ECOFF
13290 case .file implies DWARF-2. */
13294 int x ATTRIBUTE_UNUSED
;
13296 static int first_file_directive
= 0;
13298 if (ECOFF_DEBUGGING
)
13307 filename
= dwarf2_directive_file (0);
13309 /* Versions of GCC up to 3.1 start files with a ".file"
13310 directive even for stabs output. Make sure that this
13311 ".file" is handled. Note that you need a version of GCC
13312 after 3.1 in order to support DWARF-2 on MIPS. */
13313 if (filename
!= NULL
&& ! first_file_directive
)
13315 (void) new_logical_line (filename
, -1);
13316 s_app_file_string (filename
);
13318 first_file_directive
= 1;
13322 /* The .loc directive, implying DWARF-2. */
13326 int x ATTRIBUTE_UNUSED
;
13328 if (!ECOFF_DEBUGGING
)
13329 dwarf2_directive_loc (0);
13332 /* The .end directive. */
13336 int x ATTRIBUTE_UNUSED
;
13341 /* Following functions need their own .frame and .cprestore directives. */
13342 mips_frame_reg_valid
= 0;
13343 mips_cprestore_valid
= 0;
13345 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13348 demand_empty_rest_of_line ();
13353 #ifdef BFD_ASSEMBLER
13354 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13359 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13366 as_warn (_(".end not in text section"));
13370 as_warn (_(".end directive without a preceding .ent directive."));
13371 demand_empty_rest_of_line ();
13377 assert (S_GET_NAME (p
));
13378 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13379 as_warn (_(".end symbol does not match .ent symbol."));
13381 if (debug_type
== DEBUG_STABS
)
13382 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13386 as_warn (_(".end directive missing or unknown symbol"));
13389 /* Generate a .pdr section. */
13390 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13392 segT saved_seg
= now_seg
;
13393 subsegT saved_subseg
= now_subseg
;
13398 dot
= frag_now_fix ();
13400 #ifdef md_flush_pending_output
13401 md_flush_pending_output ();
13405 subseg_set (pdr_seg
, 0);
13407 /* Write the symbol. */
13408 exp
.X_op
= O_symbol
;
13409 exp
.X_add_symbol
= p
;
13410 exp
.X_add_number
= 0;
13411 emit_expr (&exp
, 4);
13413 fragp
= frag_more (7 * 4);
13415 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
13416 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
13417 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
13418 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
13419 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
13420 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
13421 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
13423 subseg_set (saved_seg
, saved_subseg
);
13425 #endif /* OBJ_ELF */
13427 cur_proc_ptr
= NULL
;
13430 /* The .aent and .ent directives. */
13439 symbolP
= get_symbol ();
13440 if (*input_line_pointer
== ',')
13441 ++input_line_pointer
;
13442 SKIP_WHITESPACE ();
13443 if (ISDIGIT (*input_line_pointer
)
13444 || *input_line_pointer
== '-')
13447 #ifdef BFD_ASSEMBLER
13448 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13453 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13460 as_warn (_(".ent or .aent not in text section."));
13462 if (!aent
&& cur_proc_ptr
)
13463 as_warn (_("missing .end"));
13467 /* This function needs its own .frame and .cprestore directives. */
13468 mips_frame_reg_valid
= 0;
13469 mips_cprestore_valid
= 0;
13471 cur_proc_ptr
= &cur_proc
;
13472 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13474 cur_proc_ptr
->isym
= symbolP
;
13476 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13480 if (debug_type
== DEBUG_STABS
)
13481 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13482 S_GET_NAME (symbolP
));
13485 demand_empty_rest_of_line ();
13488 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13489 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13490 s_mips_frame is used so that we can set the PDR information correctly.
13491 We can't use the ecoff routines because they make reference to the ecoff
13492 symbol table (in the mdebug section). */
13495 s_mips_frame (ignore
)
13496 int ignore ATTRIBUTE_UNUSED
;
13499 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13503 if (cur_proc_ptr
== (procS
*) NULL
)
13505 as_warn (_(".frame outside of .ent"));
13506 demand_empty_rest_of_line ();
13510 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13512 SKIP_WHITESPACE ();
13513 if (*input_line_pointer
++ != ','
13514 || get_absolute_expression_and_terminator (&val
) != ',')
13516 as_warn (_("Bad .frame directive"));
13517 --input_line_pointer
;
13518 demand_empty_rest_of_line ();
13522 cur_proc_ptr
->frame_offset
= val
;
13523 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13525 demand_empty_rest_of_line ();
13528 #endif /* OBJ_ELF */
13532 /* The .fmask and .mask directives. If the mdebug section is present
13533 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13534 embedded targets, s_mips_mask is used so that we can set the PDR
13535 information correctly. We can't use the ecoff routines because they
13536 make reference to the ecoff symbol table (in the mdebug section). */
13539 s_mips_mask (reg_type
)
13543 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13547 if (cur_proc_ptr
== (procS
*) NULL
)
13549 as_warn (_(".mask/.fmask outside of .ent"));
13550 demand_empty_rest_of_line ();
13554 if (get_absolute_expression_and_terminator (&mask
) != ',')
13556 as_warn (_("Bad .mask/.fmask directive"));
13557 --input_line_pointer
;
13558 demand_empty_rest_of_line ();
13562 off
= get_absolute_expression ();
13564 if (reg_type
== 'F')
13566 cur_proc_ptr
->fpreg_mask
= mask
;
13567 cur_proc_ptr
->fpreg_offset
= off
;
13571 cur_proc_ptr
->reg_mask
= mask
;
13572 cur_proc_ptr
->reg_offset
= off
;
13575 demand_empty_rest_of_line ();
13578 #endif /* OBJ_ELF */
13579 s_ignore (reg_type
);
13582 /* The .loc directive. */
13593 assert (now_seg
== text_section
);
13595 lineno
= get_number ();
13596 addroff
= frag_now_fix ();
13598 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13599 S_SET_TYPE (symbolP
, N_SLINE
);
13600 S_SET_OTHER (symbolP
, 0);
13601 S_SET_DESC (symbolP
, lineno
);
13602 symbolP
->sy_segment
= now_seg
;
13606 /* A table describing all the processors gas knows about. Names are
13607 matched in the order listed.
13609 To ease comparison, please keep this table in the same order as
13610 gcc's mips_cpu_info_table[]. */
13611 static const struct mips_cpu_info mips_cpu_info_table
[] =
13613 /* Entries for generic ISAs */
13614 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13615 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13616 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13617 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13618 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13619 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13620 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13623 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13624 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13625 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13628 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13631 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13632 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13633 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13634 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13635 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13636 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13637 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13638 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13639 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13642 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13643 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13644 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13645 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13646 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13647 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13648 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13649 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13650 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13651 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
13654 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
13655 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13656 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13659 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13660 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13662 /* Broadcom SB-1 CPU core */
13663 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13670 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13671 with a final "000" replaced by "k". Ignore case.
13673 Note: this function is shared between GCC and GAS. */
13676 mips_strict_matching_cpu_name_p (canonical
, given
)
13677 const char *canonical
, *given
;
13679 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13680 given
++, canonical
++;
13682 return ((*given
== 0 && *canonical
== 0)
13683 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13687 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13688 CPU name. We've traditionally allowed a lot of variation here.
13690 Note: this function is shared between GCC and GAS. */
13693 mips_matching_cpu_name_p (canonical
, given
)
13694 const char *canonical
, *given
;
13696 /* First see if the name matches exactly, or with a final "000"
13697 turned into "k". */
13698 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13701 /* If not, try comparing based on numerical designation alone.
13702 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13703 if (TOLOWER (*given
) == 'r')
13705 if (!ISDIGIT (*given
))
13708 /* Skip over some well-known prefixes in the canonical name,
13709 hoping to find a number there too. */
13710 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13712 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13714 else if (TOLOWER (canonical
[0]) == 'r')
13717 return mips_strict_matching_cpu_name_p (canonical
, given
);
13721 /* Parse an option that takes the name of a processor as its argument.
13722 OPTION is the name of the option and CPU_STRING is the argument.
13723 Return the corresponding processor enumeration if the CPU_STRING is
13724 recognized, otherwise report an error and return null.
13726 A similar function exists in GCC. */
13728 static const struct mips_cpu_info
*
13729 mips_parse_cpu (option
, cpu_string
)
13730 const char *option
, *cpu_string
;
13732 const struct mips_cpu_info
*p
;
13734 /* 'from-abi' selects the most compatible architecture for the given
13735 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13736 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13737 version. Look first at the -mgp options, if given, otherwise base
13738 the choice on MIPS_DEFAULT_64BIT.
13740 Treat NO_ABI like the EABIs. One reason to do this is that the
13741 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13742 architecture. This code picks MIPS I for 'mips' and MIPS III for
13743 'mips64', just as we did in the days before 'from-abi'. */
13744 if (strcasecmp (cpu_string
, "from-abi") == 0)
13746 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13747 return mips_cpu_info_from_isa (ISA_MIPS1
);
13749 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13750 return mips_cpu_info_from_isa (ISA_MIPS3
);
13752 if (file_mips_gp32
>= 0)
13753 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13755 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13760 /* 'default' has traditionally been a no-op. Probably not very useful. */
13761 if (strcasecmp (cpu_string
, "default") == 0)
13764 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13765 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13768 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13772 /* Return the canonical processor information for ISA (a member of the
13773 ISA_MIPS* enumeration). */
13775 static const struct mips_cpu_info
*
13776 mips_cpu_info_from_isa (isa
)
13781 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13782 if (mips_cpu_info_table
[i
].is_isa
13783 && isa
== mips_cpu_info_table
[i
].isa
)
13784 return (&mips_cpu_info_table
[i
]);
13790 show (stream
, string
, col_p
, first_p
)
13792 const char *string
;
13798 fprintf (stream
, "%24s", "");
13803 fprintf (stream
, ", ");
13807 if (*col_p
+ strlen (string
) > 72)
13809 fprintf (stream
, "\n%24s", "");
13813 fprintf (stream
, "%s", string
);
13814 *col_p
+= strlen (string
);
13820 md_show_usage (stream
)
13826 fprintf (stream
, _("\
13828 -membedded-pic generate embedded position independent code\n\
13829 -EB generate big endian output\n\
13830 -EL generate little endian output\n\
13831 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13832 -G NUM allow referencing objects up to NUM bytes\n\
13833 implicitly with the gp register [default 8]\n"));
13834 fprintf (stream
, _("\
13835 -mips1 generate MIPS ISA I instructions\n\
13836 -mips2 generate MIPS ISA II instructions\n\
13837 -mips3 generate MIPS ISA III instructions\n\
13838 -mips4 generate MIPS ISA IV instructions\n\
13839 -mips5 generate MIPS ISA V instructions\n\
13840 -mips32 generate MIPS32 ISA instructions\n\
13841 -mips64 generate MIPS64 ISA instructions\n\
13842 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13846 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13847 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13848 show (stream
, "from-abi", &column
, &first
);
13849 fputc ('\n', stream
);
13851 fprintf (stream
, _("\
13852 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13853 -no-mCPU don't generate code specific to CPU.\n\
13854 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13858 show (stream
, "3900", &column
, &first
);
13859 show (stream
, "4010", &column
, &first
);
13860 show (stream
, "4100", &column
, &first
);
13861 show (stream
, "4650", &column
, &first
);
13862 fputc ('\n', stream
);
13864 fprintf (stream
, _("\
13865 -mips16 generate mips16 instructions\n\
13866 -no-mips16 do not generate mips16 instructions\n"));
13867 fprintf (stream
, _("\
13868 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13869 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13870 -O0 remove unneeded NOPs, do not swap branches\n\
13871 -O remove unneeded NOPs and swap branches\n\
13872 -n warn about NOPs generated from macros\n\
13873 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13874 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13875 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13877 fprintf (stream
, _("\
13878 -KPIC, -call_shared generate SVR4 position independent code\n\
13879 -non_shared do not generate position independent code\n\
13880 -xgot assume a 32 bit GOT\n\
13881 -mabi=ABI create ABI conformant object file for:\n"));
13885 show (stream
, "32", &column
, &first
);
13886 show (stream
, "o64", &column
, &first
);
13887 show (stream
, "n32", &column
, &first
);
13888 show (stream
, "64", &column
, &first
);
13889 show (stream
, "eabi", &column
, &first
);
13891 fputc ('\n', stream
);
13893 fprintf (stream
, _("\
13894 -32 create o32 ABI object file (default)\n\
13895 -n32 create n32 ABI object file\n\
13896 -64 create 64 ABI object file\n"));