1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode
;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p
: 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p
: 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p
: 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p
: 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p
: 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi
= NO_ABI
;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls
= FALSE
;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared
= TRUE
;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). These are set to -1
212 if they have not been initialized. Changed by `.set <asename>', by
213 command line options, and based on the default architecture. */
221 /* Whether we are assembling for the mips16 processor. 0 if we are
222 not, 1 if we are, and -1 if the value has not been initialized.
223 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
224 -nomips16 command line options, and the default CPU. */
226 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
227 1 if we are, and -1 if the value has not been initialized. Changed
228 by `.set micromips' and `.set nomicromips', and the -mmicromips
229 and -mno-micromips command line options, and the default CPU. */
231 /* Non-zero if we should not reorder instructions. Changed by `.set
232 reorder' and `.set noreorder'. */
234 /* Non-zero if we should not permit the register designated "assembler
235 temporary" to be used in instructions. The value is the register
236 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
237 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
239 /* Non-zero if we should warn when a macro instruction expands into
240 more than one machine instruction. Changed by `.set nomacro' and
242 int warn_about_macros
;
243 /* Non-zero if we should not move instructions. Changed by `.set
244 move', `.set volatile', `.set nomove', and `.set novolatile'. */
246 /* Non-zero if we should not optimize branches by moving the target
247 of the branch into the delay slot. Actually, we don't perform
248 this optimization anyhow. Changed by `.set bopt' and `.set
251 /* Non-zero if we should not autoextend mips16 instructions.
252 Changed by `.set autoextend' and `.set noautoextend'. */
254 /* Restrict general purpose registers and floating point registers
255 to 32 bit. This is initially determined when -mgp32 or -mfp32
256 is passed but can changed if the assembler code uses .set mipsN. */
259 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
260 command line option, and the default CPU. */
262 /* True if ".set sym32" is in effect. */
264 /* True if floating-point operations are not allowed. Changed by .set
265 softfloat or .set hardfloat, by command line options -msoft-float or
266 -mhard-float. The default is false. */
267 bfd_boolean soft_float
;
269 /* True if only single-precision floating-point operations are allowed.
270 Changed by .set singlefloat or .set doublefloat, command-line options
271 -msingle-float or -mdouble-float. The default is false. */
272 bfd_boolean single_float
;
275 /* This is the struct we use to hold the current set of options. Note
276 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
277 -1 to indicate that they have not been initialized. */
279 /* True if -mgp32 was passed. */
280 static int file_mips_gp32
= -1;
282 /* True if -mfp32 was passed. */
283 static int file_mips_fp32
= -1;
285 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
286 static int file_mips_soft_float
= 0;
288 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
289 static int file_mips_single_float
= 0;
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
294 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
295 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
296 /* at */ ATREG
, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
297 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
298 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
301 /* These variables are filled in with the masks of registers used.
302 The object format code reads them and puts them in the appropriate
304 unsigned long mips_gprmask
;
305 unsigned long mips_cprmask
[4];
307 /* MIPS ISA we are using for this output file. */
308 static int file_mips_isa
= ISA_UNKNOWN
;
310 /* True if any MIPS16 code was produced. */
311 static int file_ase_mips16
;
313 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
314 || mips_opts.isa == ISA_MIPS32R2 \
315 || mips_opts.isa == ISA_MIPS64 \
316 || mips_opts.isa == ISA_MIPS64R2)
318 /* True if any microMIPS code was produced. */
319 static int file_ase_micromips
;
321 /* True if we want to create R_MIPS_JALR for jalr $25. */
323 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
325 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328 #define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
333 /* True if -mips3d was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mips3d
;
337 /* True if -mdmx was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mdmx
;
341 /* True if -msmartmips was passed or implied by arguments passed on the
342 command line (e.g., by -march). */
343 static int file_ase_smartmips
;
345 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
346 || mips_opts.isa == ISA_MIPS32R2)
348 /* True if -mdsp was passed or implied by arguments passed on the
349 command line (e.g., by -march). */
350 static int file_ase_dsp
;
352 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
353 || mips_opts.isa == ISA_MIPS64R2 \
354 || mips_opts.micromips)
356 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
358 /* True if -mdspr2 was passed or implied by arguments passed on the
359 command line (e.g., by -march). */
360 static int file_ase_dspr2
;
362 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
363 || mips_opts.isa == ISA_MIPS64R2 \
364 || mips_opts.micromips)
366 /* True if -mmt was passed or implied by arguments passed on the
367 command line (e.g., by -march). */
368 static int file_ase_mt
;
370 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
371 || mips_opts.isa == ISA_MIPS64R2)
373 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
374 || mips_opts.isa == ISA_MIPS64R2 \
375 || mips_opts.micromips)
377 /* The argument of the -march= flag. The architecture we are assembling. */
378 static int file_mips_arch
= CPU_UNKNOWN
;
379 static const char *mips_arch_string
;
381 /* The argument of the -mtune= flag. The architecture for which we
383 static int mips_tune
= CPU_UNKNOWN
;
384 static const char *mips_tune_string
;
386 /* True when generating 32-bit code for a 64-bit processor. */
387 static int mips_32bitmode
= 0;
389 /* True if the given ABI requires 32-bit registers. */
390 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
392 /* Likewise 64-bit registers. */
393 #define ABI_NEEDS_64BIT_REGS(ABI) \
395 || (ABI) == N64_ABI \
398 /* Return true if ISA supports 64 bit wide gp registers. */
399 #define ISA_HAS_64BIT_REGS(ISA) \
400 ((ISA) == ISA_MIPS3 \
401 || (ISA) == ISA_MIPS4 \
402 || (ISA) == ISA_MIPS5 \
403 || (ISA) == ISA_MIPS64 \
404 || (ISA) == ISA_MIPS64R2)
406 /* Return true if ISA supports 64 bit wide float registers. */
407 #define ISA_HAS_64BIT_FPRS(ISA) \
408 ((ISA) == ISA_MIPS3 \
409 || (ISA) == ISA_MIPS4 \
410 || (ISA) == ISA_MIPS5 \
411 || (ISA) == ISA_MIPS32R2 \
412 || (ISA) == ISA_MIPS64 \
413 || (ISA) == ISA_MIPS64R2)
415 /* Return true if ISA supports 64-bit right rotate (dror et al.)
417 #define ISA_HAS_DROR(ISA) \
418 ((ISA) == ISA_MIPS64R2 \
419 || (mips_opts.micromips \
420 && ISA_HAS_64BIT_REGS (ISA)) \
423 /* Return true if ISA supports 32-bit right rotate (ror et al.)
425 #define ISA_HAS_ROR(ISA) \
426 ((ISA) == ISA_MIPS32R2 \
427 || (ISA) == ISA_MIPS64R2 \
428 || mips_opts.ase_smartmips \
429 || mips_opts.micromips \
432 /* Return true if ISA supports single-precision floats in odd registers. */
433 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
434 ((ISA) == ISA_MIPS32 \
435 || (ISA) == ISA_MIPS32R2 \
436 || (ISA) == ISA_MIPS64 \
437 || (ISA) == ISA_MIPS64R2)
439 /* Return true if ISA supports move to/from high part of a 64-bit
440 floating-point register. */
441 #define ISA_HAS_MXHC1(ISA) \
442 ((ISA) == ISA_MIPS32R2 \
443 || (ISA) == ISA_MIPS64R2)
445 #define HAVE_32BIT_GPRS \
446 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
448 #define HAVE_32BIT_FPRS \
449 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
451 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
452 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
454 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
456 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
458 /* True if relocations are stored in-place. */
459 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
461 /* The ABI-derived address size. */
462 #define HAVE_64BIT_ADDRESSES \
463 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
464 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
466 /* The size of symbolic constants (i.e., expressions of the form
467 "SYMBOL" or "SYMBOL + OFFSET"). */
468 #define HAVE_32BIT_SYMBOLS \
469 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
470 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
472 /* Addresses are loaded in different ways, depending on the address size
473 in use. The n32 ABI Documentation also mandates the use of additions
474 with overflow checking, but existing implementations don't follow it. */
475 #define ADDRESS_ADD_INSN \
476 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
478 #define ADDRESS_ADDI_INSN \
479 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
481 #define ADDRESS_LOAD_INSN \
482 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
484 #define ADDRESS_STORE_INSN \
485 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
487 /* Return true if the given CPU supports the MIPS16 ASE. */
488 #define CPU_HAS_MIPS16(cpu) \
489 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
490 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
492 /* Return true if the given CPU supports the microMIPS ASE. */
493 #define CPU_HAS_MICROMIPS(cpu) 0
495 /* True if CPU has a dror instruction. */
496 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
498 /* True if CPU has a ror instruction. */
499 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
501 /* True if CPU is in the Octeon family */
502 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
504 /* True if CPU has seq/sne and seqi/snei instructions. */
505 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
507 /* True, if CPU has support for ldc1 and sdc1. */
508 #define CPU_HAS_LDC1_SDC1(CPU) \
509 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
511 /* True if mflo and mfhi can be immediately followed by instructions
512 which write to the HI and LO registers.
514 According to MIPS specifications, MIPS ISAs I, II, and III need
515 (at least) two instructions between the reads of HI/LO and
516 instructions which write them, and later ISAs do not. Contradicting
517 the MIPS specifications, some MIPS IV processor user manuals (e.g.
518 the UM for the NEC Vr5000) document needing the instructions between
519 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
520 MIPS64 and later ISAs to have the interlocks, plus any specific
521 earlier-ISA CPUs for which CPU documentation declares that the
522 instructions are really interlocked. */
523 #define hilo_interlocks \
524 (mips_opts.isa == ISA_MIPS32 \
525 || mips_opts.isa == ISA_MIPS32R2 \
526 || mips_opts.isa == ISA_MIPS64 \
527 || mips_opts.isa == ISA_MIPS64R2 \
528 || mips_opts.arch == CPU_R4010 \
529 || mips_opts.arch == CPU_R5900 \
530 || mips_opts.arch == CPU_R10000 \
531 || mips_opts.arch == CPU_R12000 \
532 || mips_opts.arch == CPU_R14000 \
533 || mips_opts.arch == CPU_R16000 \
534 || mips_opts.arch == CPU_RM7000 \
535 || mips_opts.arch == CPU_VR5500 \
536 || mips_opts.micromips \
539 /* Whether the processor uses hardware interlocks to protect reads
540 from the GPRs after they are loaded from memory, and thus does not
541 require nops to be inserted. This applies to instructions marked
542 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
543 level I and microMIPS mode instructions are always interlocked. */
544 #define gpr_interlocks \
545 (mips_opts.isa != ISA_MIPS1 \
546 || mips_opts.arch == CPU_R3900 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.micromips \
551 /* Whether the processor uses hardware interlocks to avoid delays
552 required by coprocessor instructions, and thus does not require
553 nops to be inserted. This applies to instructions marked
554 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
555 between instructions marked INSN_WRITE_COND_CODE and ones marked
556 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
557 levels I, II, and III and microMIPS mode instructions are always
559 /* Itbl support may require additional care here. */
560 #define cop_interlocks \
561 ((mips_opts.isa != ISA_MIPS1 \
562 && mips_opts.isa != ISA_MIPS2 \
563 && mips_opts.isa != ISA_MIPS3) \
564 || mips_opts.arch == CPU_R4300 \
565 || mips_opts.micromips \
568 /* Whether the processor uses hardware interlocks to protect reads
569 from coprocessor registers after they are loaded from memory, and
570 thus does not require nops to be inserted. This applies to
571 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
572 requires at MIPS ISA level I and microMIPS mode instructions are
573 always interlocked. */
574 #define cop_mem_interlocks \
575 (mips_opts.isa != ISA_MIPS1 \
576 || mips_opts.micromips \
579 /* Is this a mfhi or mflo instruction? */
580 #define MF_HILO_INSN(PINFO) \
581 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
583 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
584 has been selected. This implies, in particular, that addresses of text
585 labels have their LSB set. */
586 #define HAVE_CODE_COMPRESSION \
587 ((mips_opts.mips16 | mips_opts.micromips) != 0)
589 /* MIPS PIC level. */
591 enum mips_pic_level mips_pic
;
593 /* 1 if we should generate 32 bit offsets from the $gp register in
594 SVR4_PIC mode. Currently has no meaning in other modes. */
595 static int mips_big_got
= 0;
597 /* 1 if trap instructions should used for overflow rather than break
599 static int mips_trap
= 0;
601 /* 1 if double width floating point constants should not be constructed
602 by assembling two single width halves into two single width floating
603 point registers which just happen to alias the double width destination
604 register. On some architectures this aliasing can be disabled by a bit
605 in the status register, and the setting of this bit cannot be determined
606 automatically at assemble time. */
607 static int mips_disable_float_construction
;
609 /* Non-zero if any .set noreorder directives were used. */
611 static int mips_any_noreorder
;
613 /* Non-zero if nops should be inserted when the register referenced in
614 an mfhi/mflo instruction is read in the next two instructions. */
615 static int mips_7000_hilo_fix
;
617 /* The size of objects in the small data section. */
618 static unsigned int g_switch_value
= 8;
619 /* Whether the -G option was used. */
620 static int g_switch_seen
= 0;
625 /* If we can determine in advance that GP optimization won't be
626 possible, we can skip the relaxation stuff that tries to produce
627 GP-relative references. This makes delay slot optimization work
630 This function can only provide a guess, but it seems to work for
631 gcc output. It needs to guess right for gcc, otherwise gcc
632 will put what it thinks is a GP-relative instruction in a branch
635 I don't know if a fix is needed for the SVR4_PIC mode. I've only
636 fixed it for the non-PIC mode. KR 95/04/07 */
637 static int nopic_need_relax (symbolS
*, int);
639 /* handle of the OPCODE hash table */
640 static struct hash_control
*op_hash
= NULL
;
642 /* The opcode hash table we use for the mips16. */
643 static struct hash_control
*mips16_op_hash
= NULL
;
645 /* The opcode hash table we use for the microMIPS ASE. */
646 static struct hash_control
*micromips_op_hash
= NULL
;
648 /* This array holds the chars that always start a comment. If the
649 pre-processor is disabled, these aren't very useful */
650 const char comment_chars
[] = "#";
652 /* This array holds the chars that only start a comment at the beginning of
653 a line. If the line seems to have the form '# 123 filename'
654 .line and .file directives will appear in the pre-processed output */
655 /* Note that input_file.c hand checks for '#' at the beginning of the
656 first line of the input file. This is because the compiler outputs
657 #NO_APP at the beginning of its output. */
658 /* Also note that C style comments are always supported. */
659 const char line_comment_chars
[] = "#";
661 /* This array holds machine specific line separator characters. */
662 const char line_separator_chars
[] = ";";
664 /* Chars that can be used to separate mant from exp in floating point nums */
665 const char EXP_CHARS
[] = "eE";
667 /* Chars that mean this number is a floating point constant */
670 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
672 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
673 changed in read.c . Ideally it shouldn't have to know about it at all,
674 but nothing is ideal around here.
677 static char *insn_error
;
679 static int auto_align
= 1;
681 /* When outputting SVR4 PIC code, the assembler needs to know the
682 offset in the stack frame from which to restore the $gp register.
683 This is set by the .cprestore pseudo-op, and saved in this
685 static offsetT mips_cprestore_offset
= -1;
687 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
688 more optimizations, it can use a register value instead of a memory-saved
689 offset and even an other register than $gp as global pointer. */
690 static offsetT mips_cpreturn_offset
= -1;
691 static int mips_cpreturn_register
= -1;
692 static int mips_gp_register
= GP
;
693 static int mips_gprel_offset
= 0;
695 /* Whether mips_cprestore_offset has been set in the current function
696 (or whether it has already been warned about, if not). */
697 static int mips_cprestore_valid
= 0;
699 /* This is the register which holds the stack frame, as set by the
700 .frame pseudo-op. This is needed to implement .cprestore. */
701 static int mips_frame_reg
= SP
;
703 /* Whether mips_frame_reg has been set in the current function
704 (or whether it has already been warned about, if not). */
705 static int mips_frame_reg_valid
= 0;
707 /* To output NOP instructions correctly, we need to keep information
708 about the previous two instructions. */
710 /* Whether we are optimizing. The default value of 2 means to remove
711 unneeded NOPs and swap branch instructions when possible. A value
712 of 1 means to not swap branches. A value of 0 means to always
714 static int mips_optimize
= 2;
716 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
717 equivalent to seeing no -g option at all. */
718 static int mips_debug
= 0;
720 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
721 #define MAX_VR4130_NOPS 4
723 /* The maximum number of NOPs needed to fill delay slots. */
724 #define MAX_DELAY_NOPS 2
726 /* The maximum number of NOPs needed for any purpose. */
729 /* A list of previous instructions, with index 0 being the most recent.
730 We need to look back MAX_NOPS instructions when filling delay slots
731 or working around processor errata. We need to look back one
732 instruction further if we're thinking about using history[0] to
733 fill a branch delay slot. */
734 static struct mips_cl_insn history
[1 + MAX_NOPS
];
736 /* Nop instructions used by emit_nop. */
737 static struct mips_cl_insn nop_insn
;
738 static struct mips_cl_insn mips16_nop_insn
;
739 static struct mips_cl_insn micromips_nop16_insn
;
740 static struct mips_cl_insn micromips_nop32_insn
;
742 /* The appropriate nop for the current mode. */
743 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
744 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
746 /* The size of NOP_INSN in bytes. */
747 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
749 /* If this is set, it points to a frag holding nop instructions which
750 were inserted before the start of a noreorder section. If those
751 nops turn out to be unnecessary, the size of the frag can be
753 static fragS
*prev_nop_frag
;
755 /* The number of nop instructions we created in prev_nop_frag. */
756 static int prev_nop_frag_holds
;
758 /* The number of nop instructions that we know we need in
760 static int prev_nop_frag_required
;
762 /* The number of instructions we've seen since prev_nop_frag. */
763 static int prev_nop_frag_since
;
765 /* For ECOFF and ELF, relocations against symbols are done in two
766 parts, with a HI relocation and a LO relocation. Each relocation
767 has only 16 bits of space to store an addend. This means that in
768 order for the linker to handle carries correctly, it must be able
769 to locate both the HI and the LO relocation. This means that the
770 relocations must appear in order in the relocation table.
772 In order to implement this, we keep track of each unmatched HI
773 relocation. We then sort them so that they immediately precede the
774 corresponding LO relocation. */
779 struct mips_hi_fixup
*next
;
782 /* The section this fixup is in. */
786 /* The list of unmatched HI relocs. */
788 static struct mips_hi_fixup
*mips_hi_fixup_list
;
790 /* The frag containing the last explicit relocation operator.
791 Null if explicit relocations have not been used. */
793 static fragS
*prev_reloc_op_frag
;
795 /* Map normal MIPS register numbers to mips16 register numbers. */
797 #define X ILLEGAL_REG
798 static const int mips32_to_16_reg_map
[] =
800 X
, X
, 2, 3, 4, 5, 6, 7,
801 X
, X
, X
, X
, X
, X
, X
, X
,
802 0, 1, X
, X
, X
, X
, X
, X
,
803 X
, X
, X
, X
, X
, X
, X
, X
807 /* Map mips16 register numbers to normal MIPS register numbers. */
809 static const unsigned int mips16_to_32_reg_map
[] =
811 16, 17, 2, 3, 4, 5, 6, 7
814 /* Map normal MIPS register numbers to microMIPS register numbers. */
816 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
817 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
818 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
819 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
820 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
821 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
822 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
824 #define X ILLEGAL_REG
825 /* reg type h: 4, 5, 6. */
826 static const int mips32_to_micromips_reg_h_map
[] =
828 X
, X
, X
, X
, 4, 5, 6, X
,
829 X
, X
, X
, X
, X
, X
, X
, X
,
830 X
, X
, X
, X
, X
, X
, X
, X
,
831 X
, X
, X
, X
, X
, X
, X
, X
834 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
835 static const int mips32_to_micromips_reg_m_map
[] =
837 0, X
, 2, 3, X
, X
, X
, X
,
838 X
, X
, X
, X
, X
, X
, X
, X
,
839 4, 1, 5, 6, 7, X
, X
, X
,
840 X
, X
, X
, X
, X
, X
, X
, X
843 /* reg type q: 0, 2-7. 17. */
844 static const int mips32_to_micromips_reg_q_map
[] =
846 0, X
, 2, 3, 4, 5, 6, 7,
847 X
, X
, X
, X
, X
, X
, X
, X
,
848 X
, 1, X
, X
, X
, X
, X
, X
,
849 X
, X
, X
, X
, X
, X
, X
, X
852 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
855 /* Map microMIPS register numbers to normal MIPS register numbers. */
857 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
858 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
859 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
860 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
861 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
862 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
864 /* The microMIPS registers with type h. */
865 static const unsigned int micromips_to_32_reg_h_map
[] =
867 5, 5, 6, 4, 4, 4, 4, 4
870 /* The microMIPS registers with type i. */
871 static const unsigned int micromips_to_32_reg_i_map
[] =
873 6, 7, 7, 21, 22, 5, 6, 7
876 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
878 /* The microMIPS registers with type m. */
879 static const unsigned int micromips_to_32_reg_m_map
[] =
881 0, 17, 2, 3, 16, 18, 19, 20
884 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
886 /* The microMIPS registers with type q. */
887 static const unsigned int micromips_to_32_reg_q_map
[] =
889 0, 17, 2, 3, 4, 5, 6, 7
892 /* microMIPS imm type B. */
893 static const int micromips_imm_b_map
[] =
895 1, 4, 8, 12, 16, 20, 24, -1
898 /* microMIPS imm type C. */
899 static const int micromips_imm_c_map
[] =
901 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
904 /* Classifies the kind of instructions we're interested in when
905 implementing -mfix-vr4120. */
906 enum fix_vr4120_class
914 NUM_FIX_VR4120_CLASSES
917 /* ...likewise -mfix-loongson2f-jump. */
918 static bfd_boolean mips_fix_loongson2f_jump
;
920 /* ...likewise -mfix-loongson2f-nop. */
921 static bfd_boolean mips_fix_loongson2f_nop
;
923 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
924 static bfd_boolean mips_fix_loongson2f
;
926 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
927 there must be at least one other instruction between an instruction
928 of type X and an instruction of type Y. */
929 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
931 /* True if -mfix-vr4120 is in force. */
932 static int mips_fix_vr4120
;
934 /* ...likewise -mfix-vr4130. */
935 static int mips_fix_vr4130
;
937 /* ...likewise -mfix-24k. */
938 static int mips_fix_24k
;
940 /* ...likewise -mfix-cn63xxp1 */
941 static bfd_boolean mips_fix_cn63xxp1
;
943 /* We don't relax branches by default, since this causes us to expand
944 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
945 fail to compute the offset before expanding the macro to the most
946 efficient expansion. */
948 static int mips_relax_branch
;
950 /* The expansion of many macros depends on the type of symbol that
951 they refer to. For example, when generating position-dependent code,
952 a macro that refers to a symbol may have two different expansions,
953 one which uses GP-relative addresses and one which uses absolute
954 addresses. When generating SVR4-style PIC, a macro may have
955 different expansions for local and global symbols.
957 We handle these situations by generating both sequences and putting
958 them in variant frags. In position-dependent code, the first sequence
959 will be the GP-relative one and the second sequence will be the
960 absolute one. In SVR4 PIC, the first sequence will be for global
961 symbols and the second will be for local symbols.
963 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
964 SECOND are the lengths of the two sequences in bytes. These fields
965 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
966 the subtype has the following flags:
969 Set if it has been decided that we should use the second
970 sequence instead of the first.
973 Set in the first variant frag if the macro's second implementation
974 is longer than its first. This refers to the macro as a whole,
975 not an individual relaxation.
978 Set in the first variant frag if the macro appeared in a .set nomacro
979 block and if one alternative requires a warning but the other does not.
982 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
985 RELAX_DELAY_SLOT_16BIT
986 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
989 RELAX_DELAY_SLOT_SIZE_FIRST
990 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
991 the macro is of the wrong size for the branch delay slot.
993 RELAX_DELAY_SLOT_SIZE_SECOND
994 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
995 the macro is of the wrong size for the branch delay slot.
997 The frag's "opcode" points to the first fixup for relaxable code.
999 Relaxable macros are generated using a sequence such as:
1001 relax_start (SYMBOL);
1002 ... generate first expansion ...
1004 ... generate second expansion ...
1007 The code and fixups for the unwanted alternative are discarded
1008 by md_convert_frag. */
1009 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1011 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1012 #define RELAX_SECOND(X) ((X) & 0xff)
1013 #define RELAX_USE_SECOND 0x10000
1014 #define RELAX_SECOND_LONGER 0x20000
1015 #define RELAX_NOMACRO 0x40000
1016 #define RELAX_DELAY_SLOT 0x80000
1017 #define RELAX_DELAY_SLOT_16BIT 0x100000
1018 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1019 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1021 /* Branch without likely bit. If label is out of range, we turn:
1023 beq reg1, reg2, label
1033 with the following opcode replacements:
1040 bltzal <-> bgezal (with jal label instead of j label)
1042 Even though keeping the delay slot instruction in the delay slot of
1043 the branch would be more efficient, it would be very tricky to do
1044 correctly, because we'd have to introduce a variable frag *after*
1045 the delay slot instruction, and expand that instead. Let's do it
1046 the easy way for now, even if the branch-not-taken case now costs
1047 one additional instruction. Out-of-range branches are not supposed
1048 to be common, anyway.
1050 Branch likely. If label is out of range, we turn:
1052 beql reg1, reg2, label
1053 delay slot (annulled if branch not taken)
1062 delay slot (executed only if branch taken)
1065 It would be possible to generate a shorter sequence by losing the
1066 likely bit, generating something like:
1071 delay slot (executed only if branch taken)
1083 bltzall -> bgezal (with jal label instead of j label)
1084 bgezall -> bltzal (ditto)
1087 but it's not clear that it would actually improve performance. */
1088 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1089 ((relax_substateT) \
1092 | ((toofar) ? 0x20 : 0) \
1093 | ((link) ? 0x40 : 0) \
1094 | ((likely) ? 0x80 : 0) \
1095 | ((uncond) ? 0x100 : 0)))
1096 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1097 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1098 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1099 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1100 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1101 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1103 /* For mips16 code, we use an entirely different form of relaxation.
1104 mips16 supports two versions of most instructions which take
1105 immediate values: a small one which takes some small value, and a
1106 larger one which takes a 16 bit value. Since branches also follow
1107 this pattern, relaxing these values is required.
1109 We can assemble both mips16 and normal MIPS code in a single
1110 object. Therefore, we need to support this type of relaxation at
1111 the same time that we support the relaxation described above. We
1112 use the high bit of the subtype field to distinguish these cases.
1114 The information we store for this type of relaxation is the
1115 argument code found in the opcode file for this relocation, whether
1116 the user explicitly requested a small or extended form, and whether
1117 the relocation is in a jump or jal delay slot. That tells us the
1118 size of the value, and how it should be stored. We also store
1119 whether the fragment is considered to be extended or not. We also
1120 store whether this is known to be a branch to a different section,
1121 whether we have tried to relax this frag yet, and whether we have
1122 ever extended a PC relative fragment because of a shift count. */
1123 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1126 | ((small) ? 0x100 : 0) \
1127 | ((ext) ? 0x200 : 0) \
1128 | ((dslot) ? 0x400 : 0) \
1129 | ((jal_dslot) ? 0x800 : 0))
1130 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1131 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1132 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1133 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1134 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1135 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1136 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1137 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1138 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1139 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1140 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1141 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1143 /* For microMIPS code, we use relaxation similar to one we use for
1144 MIPS16 code. Some instructions that take immediate values support
1145 two encodings: a small one which takes some small value, and a
1146 larger one which takes a 16 bit value. As some branches also follow
1147 this pattern, relaxing these values is required.
1149 We can assemble both microMIPS and normal MIPS code in a single
1150 object. Therefore, we need to support this type of relaxation at
1151 the same time that we support the relaxation described above. We
1152 use one of the high bits of the subtype field to distinguish these
1155 The information we store for this type of relaxation is the argument
1156 code found in the opcode file for this relocation, the register
1157 selected as the assembler temporary, whether the branch is
1158 unconditional, whether it is compact, whether it stores the link
1159 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1160 branches to a sequence of instructions is enabled, and whether the
1161 displacement of a branch is too large to fit as an immediate argument
1162 of a 16-bit and a 32-bit branch, respectively. */
1163 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1164 relax32, toofar16, toofar32) \
1167 | (((at) & 0x1f) << 8) \
1168 | ((uncond) ? 0x2000 : 0) \
1169 | ((compact) ? 0x4000 : 0) \
1170 | ((link) ? 0x8000 : 0) \
1171 | ((relax32) ? 0x10000 : 0) \
1172 | ((toofar16) ? 0x20000 : 0) \
1173 | ((toofar32) ? 0x40000 : 0))
1174 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1175 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1176 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1177 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1178 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1179 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1180 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1182 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1185 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1186 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1187 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1189 /* Sign-extend 16-bit value X. */
1190 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1192 /* Is the given value a sign-extended 32-bit value? */
1193 #define IS_SEXT_32BIT_NUM(x) \
1194 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1195 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1197 /* Is the given value a sign-extended 16-bit value? */
1198 #define IS_SEXT_16BIT_NUM(x) \
1199 (((x) &~ (offsetT) 0x7fff) == 0 \
1200 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1202 /* Is the given value a sign-extended 12-bit value? */
1203 #define IS_SEXT_12BIT_NUM(x) \
1204 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1206 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1207 #define IS_ZEXT_32BIT_NUM(x) \
1208 (((x) &~ (offsetT) 0xffffffff) == 0 \
1209 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1211 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1212 VALUE << SHIFT. VALUE is evaluated exactly once. */
1213 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1214 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1215 | (((VALUE) & (MASK)) << (SHIFT)))
1217 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1219 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1220 (((STRUCT) >> (SHIFT)) & (MASK))
1222 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1223 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1225 include/opcode/mips.h specifies operand fields using the macros
1226 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1227 with "MIPS16OP" instead of "OP". */
1228 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1231 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1232 OP_MASK_##FIELD, OP_SH_##FIELD); \
1234 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1235 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1237 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1238 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1239 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1241 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1242 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1244 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1245 : EXTRACT_BITS ((INSN).insn_opcode, \
1246 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1247 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1248 EXTRACT_BITS ((INSN).insn_opcode, \
1249 MIPS16OP_MASK_##FIELD, \
1250 MIPS16OP_SH_##FIELD)
1252 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1253 #define MIPS16_EXTEND (0xf000U << 16)
1255 /* Whether or not we are emitting a branch-likely macro. */
1256 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1258 /* Global variables used when generating relaxable macros. See the
1259 comment above RELAX_ENCODE for more details about how relaxation
1262 /* 0 if we're not emitting a relaxable macro.
1263 1 if we're emitting the first of the two relaxation alternatives.
1264 2 if we're emitting the second alternative. */
1267 /* The first relaxable fixup in the current frag. (In other words,
1268 the first fixup that refers to relaxable code.) */
1271 /* sizes[0] says how many bytes of the first alternative are stored in
1272 the current frag. Likewise sizes[1] for the second alternative. */
1273 unsigned int sizes
[2];
1275 /* The symbol on which the choice of sequence depends. */
1279 /* Global variables used to decide whether a macro needs a warning. */
1281 /* True if the macro is in a branch delay slot. */
1282 bfd_boolean delay_slot_p
;
1284 /* Set to the length in bytes required if the macro is in a delay slot
1285 that requires a specific length of instruction, otherwise zero. */
1286 unsigned int delay_slot_length
;
1288 /* For relaxable macros, sizes[0] is the length of the first alternative
1289 in bytes and sizes[1] is the length of the second alternative.
1290 For non-relaxable macros, both elements give the length of the
1292 unsigned int sizes
[2];
1294 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1295 instruction of the first alternative in bytes and first_insn_sizes[1]
1296 is the length of the first instruction of the second alternative.
1297 For non-relaxable macros, both elements give the length of the first
1298 instruction in bytes.
1300 Set to zero if we haven't yet seen the first instruction. */
1301 unsigned int first_insn_sizes
[2];
1303 /* For relaxable macros, insns[0] is the number of instructions for the
1304 first alternative and insns[1] is the number of instructions for the
1307 For non-relaxable macros, both elements give the number of
1308 instructions for the macro. */
1309 unsigned int insns
[2];
1311 /* The first variant frag for this macro. */
1313 } mips_macro_warning
;
1315 /* Prototypes for static functions. */
1317 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1319 static void append_insn
1320 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1321 bfd_boolean expansionp
);
1322 static void mips_no_prev_insn (void);
1323 static void macro_build (expressionS
*, const char *, const char *, ...);
1324 static void mips16_macro_build
1325 (expressionS
*, const char *, const char *, va_list *);
1326 static void load_register (int, expressionS
*, int);
1327 static void macro_start (void);
1328 static void macro_end (void);
1329 static void macro (struct mips_cl_insn
* ip
);
1330 static void mips16_macro (struct mips_cl_insn
* ip
);
1331 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1332 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1333 static void mips16_immed
1334 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1335 unsigned int, unsigned long *);
1336 static size_t my_getSmallExpression
1337 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1338 static void my_getExpression (expressionS
*, char *);
1339 static void s_align (int);
1340 static void s_change_sec (int);
1341 static void s_change_section (int);
1342 static void s_cons (int);
1343 static void s_float_cons (int);
1344 static void s_mips_globl (int);
1345 static void s_option (int);
1346 static void s_mipsset (int);
1347 static void s_abicalls (int);
1348 static void s_cpload (int);
1349 static void s_cpsetup (int);
1350 static void s_cplocal (int);
1351 static void s_cprestore (int);
1352 static void s_cpreturn (int);
1353 static void s_dtprelword (int);
1354 static void s_dtpreldword (int);
1355 static void s_tprelword (int);
1356 static void s_tpreldword (int);
1357 static void s_gpvalue (int);
1358 static void s_gpword (int);
1359 static void s_gpdword (int);
1360 static void s_cpadd (int);
1361 static void s_insn (int);
1362 static void md_obj_begin (void);
1363 static void md_obj_end (void);
1364 static void s_mips_ent (int);
1365 static void s_mips_end (int);
1366 static void s_mips_frame (int);
1367 static void s_mips_mask (int reg_type
);
1368 static void s_mips_stab (int);
1369 static void s_mips_weakext (int);
1370 static void s_mips_file (int);
1371 static void s_mips_loc (int);
1372 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1373 static int relaxed_branch_length (fragS
*, asection
*, int);
1374 static int validate_mips_insn (const struct mips_opcode
*);
1375 static int validate_micromips_insn (const struct mips_opcode
*);
1376 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1377 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1379 /* Table and functions used to map between CPU/ISA names, and
1380 ISA levels, and CPU numbers. */
1382 struct mips_cpu_info
1384 const char *name
; /* CPU or ISA name. */
1385 int flags
; /* ASEs available, or ISA flag. */
1386 int isa
; /* ISA level. */
1387 int cpu
; /* CPU number (default CPU if ISA). */
1390 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1391 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1392 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1393 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1394 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1395 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1396 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1397 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1399 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1400 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1401 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1405 The following pseudo-ops from the Kane and Heinrich MIPS book
1406 should be defined here, but are currently unsupported: .alias,
1407 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1409 The following pseudo-ops from the Kane and Heinrich MIPS book are
1410 specific to the type of debugging information being generated, and
1411 should be defined by the object format: .aent, .begin, .bend,
1412 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1415 The following pseudo-ops from the Kane and Heinrich MIPS book are
1416 not MIPS CPU specific, but are also not specific to the object file
1417 format. This file is probably the best place to define them, but
1418 they are not currently supported: .asm0, .endr, .lab, .struct. */
1420 static const pseudo_typeS mips_pseudo_table
[] =
1422 /* MIPS specific pseudo-ops. */
1423 {"option", s_option
, 0},
1424 {"set", s_mipsset
, 0},
1425 {"rdata", s_change_sec
, 'r'},
1426 {"sdata", s_change_sec
, 's'},
1427 {"livereg", s_ignore
, 0},
1428 {"abicalls", s_abicalls
, 0},
1429 {"cpload", s_cpload
, 0},
1430 {"cpsetup", s_cpsetup
, 0},
1431 {"cplocal", s_cplocal
, 0},
1432 {"cprestore", s_cprestore
, 0},
1433 {"cpreturn", s_cpreturn
, 0},
1434 {"dtprelword", s_dtprelword
, 0},
1435 {"dtpreldword", s_dtpreldword
, 0},
1436 {"tprelword", s_tprelword
, 0},
1437 {"tpreldword", s_tpreldword
, 0},
1438 {"gpvalue", s_gpvalue
, 0},
1439 {"gpword", s_gpword
, 0},
1440 {"gpdword", s_gpdword
, 0},
1441 {"cpadd", s_cpadd
, 0},
1442 {"insn", s_insn
, 0},
1444 /* Relatively generic pseudo-ops that happen to be used on MIPS
1446 {"asciiz", stringer
, 8 + 1},
1447 {"bss", s_change_sec
, 'b'},
1449 {"half", s_cons
, 1},
1450 {"dword", s_cons
, 3},
1451 {"weakext", s_mips_weakext
, 0},
1452 {"origin", s_org
, 0},
1453 {"repeat", s_rept
, 0},
1455 /* For MIPS this is non-standard, but we define it for consistency. */
1456 {"sbss", s_change_sec
, 'B'},
1458 /* These pseudo-ops are defined in read.c, but must be overridden
1459 here for one reason or another. */
1460 {"align", s_align
, 0},
1461 {"byte", s_cons
, 0},
1462 {"data", s_change_sec
, 'd'},
1463 {"double", s_float_cons
, 'd'},
1464 {"float", s_float_cons
, 'f'},
1465 {"globl", s_mips_globl
, 0},
1466 {"global", s_mips_globl
, 0},
1467 {"hword", s_cons
, 1},
1469 {"long", s_cons
, 2},
1470 {"octa", s_cons
, 4},
1471 {"quad", s_cons
, 3},
1472 {"section", s_change_section
, 0},
1473 {"short", s_cons
, 1},
1474 {"single", s_float_cons
, 'f'},
1475 {"stabd", s_mips_stab
, 'd'},
1476 {"stabn", s_mips_stab
, 'n'},
1477 {"stabs", s_mips_stab
, 's'},
1478 {"text", s_change_sec
, 't'},
1479 {"word", s_cons
, 2},
1481 { "extern", ecoff_directive_extern
, 0},
1486 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1488 /* These pseudo-ops should be defined by the object file format.
1489 However, a.out doesn't support them, so we have versions here. */
1490 {"aent", s_mips_ent
, 1},
1491 {"bgnb", s_ignore
, 0},
1492 {"end", s_mips_end
, 0},
1493 {"endb", s_ignore
, 0},
1494 {"ent", s_mips_ent
, 0},
1495 {"file", s_mips_file
, 0},
1496 {"fmask", s_mips_mask
, 'F'},
1497 {"frame", s_mips_frame
, 0},
1498 {"loc", s_mips_loc
, 0},
1499 {"mask", s_mips_mask
, 'R'},
1500 {"verstamp", s_ignore
, 0},
1504 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1505 purpose of the `.dc.a' internal pseudo-op. */
1508 mips_address_bytes (void)
1510 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1513 extern void pop_insert (const pseudo_typeS
*);
1516 mips_pop_insert (void)
1518 pop_insert (mips_pseudo_table
);
1519 if (! ECOFF_DEBUGGING
)
1520 pop_insert (mips_nonecoff_pseudo_table
);
1523 /* Symbols labelling the current insn. */
1525 struct insn_label_list
1527 struct insn_label_list
*next
;
1531 static struct insn_label_list
*free_insn_labels
;
1532 #define label_list tc_segment_info_data.labels
1534 static void mips_clear_insn_labels (void);
1535 static void mips_mark_labels (void);
1536 static void mips_compressed_mark_labels (void);
1539 mips_clear_insn_labels (void)
1541 register struct insn_label_list
**pl
;
1542 segment_info_type
*si
;
1546 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1549 si
= seg_info (now_seg
);
1550 *pl
= si
->label_list
;
1551 si
->label_list
= NULL
;
1555 /* Mark instruction labels in MIPS16/microMIPS mode. */
1558 mips_mark_labels (void)
1560 if (HAVE_CODE_COMPRESSION
)
1561 mips_compressed_mark_labels ();
1564 static char *expr_end
;
1566 /* Expressions which appear in instructions. These are set by
1569 static expressionS imm_expr
;
1570 static expressionS imm2_expr
;
1571 static expressionS offset_expr
;
1573 /* Relocs associated with imm_expr and offset_expr. */
1575 static bfd_reloc_code_real_type imm_reloc
[3]
1576 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1577 static bfd_reloc_code_real_type offset_reloc
[3]
1578 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1580 /* This is set to the resulting size of the instruction to be produced
1581 by mips16_ip if an explicit extension is used or by mips_ip if an
1582 explicit size is supplied. */
1584 static unsigned int forced_insn_length
;
1586 /* True if we are assembling an instruction. All dot symbols defined during
1587 this time should be treated as code labels. */
1589 static bfd_boolean mips_assembling_insn
;
1592 /* The pdr segment for per procedure frame/regmask info. Not used for
1595 static segT pdr_seg
;
1598 /* The default target format to use. */
1600 #if defined (TE_FreeBSD)
1601 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1602 #elif defined (TE_TMIPS)
1603 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1605 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1609 mips_target_format (void)
1611 switch (OUTPUT_FLAVOR
)
1613 case bfd_target_ecoff_flavour
:
1614 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1615 case bfd_target_coff_flavour
:
1617 case bfd_target_elf_flavour
:
1619 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1620 return (target_big_endian
1621 ? "elf32-bigmips-vxworks"
1622 : "elf32-littlemips-vxworks");
1624 return (target_big_endian
1625 ? (HAVE_64BIT_OBJECTS
1626 ? ELF_TARGET ("elf64-", "big")
1628 ? ELF_TARGET ("elf32-n", "big")
1629 : ELF_TARGET ("elf32-", "big")))
1630 : (HAVE_64BIT_OBJECTS
1631 ? ELF_TARGET ("elf64-", "little")
1633 ? ELF_TARGET ("elf32-n", "little")
1634 : ELF_TARGET ("elf32-", "little"))));
1641 /* Return the length of a microMIPS instruction in bytes. If bits of
1642 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1643 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1644 major opcode) will require further modifications to the opcode
1647 static inline unsigned int
1648 micromips_insn_length (const struct mips_opcode
*mo
)
1650 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1653 /* Return the length of MIPS16 instruction OPCODE. */
1655 static inline unsigned int
1656 mips16_opcode_length (unsigned long opcode
)
1658 return (opcode
>> 16) == 0 ? 2 : 4;
1661 /* Return the length of instruction INSN. */
1663 static inline unsigned int
1664 insn_length (const struct mips_cl_insn
*insn
)
1666 if (mips_opts
.micromips
)
1667 return micromips_insn_length (insn
->insn_mo
);
1668 else if (mips_opts
.mips16
)
1669 return mips16_opcode_length (insn
->insn_opcode
);
1674 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1677 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1682 insn
->insn_opcode
= mo
->match
;
1685 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1686 insn
->fixp
[i
] = NULL
;
1687 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1688 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1689 insn
->mips16_absolute_jump_p
= 0;
1690 insn
->complete_p
= 0;
1691 insn
->cleared_p
= 0;
1694 /* Record the current MIPS16/microMIPS mode in now_seg. */
1697 mips_record_compressed_mode (void)
1699 segment_info_type
*si
;
1701 si
= seg_info (now_seg
);
1702 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1703 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1704 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1705 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1708 /* Read a standard MIPS instruction from BUF. */
1710 static unsigned long
1711 read_insn (char *buf
)
1713 if (target_big_endian
)
1714 return bfd_getb32 ((bfd_byte
*) buf
);
1716 return bfd_getl32 ((bfd_byte
*) buf
);
1719 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1723 write_insn (char *buf
, unsigned int insn
)
1725 md_number_to_chars (buf
, insn
, 4);
1729 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1730 has length LENGTH. */
1732 static unsigned long
1733 read_compressed_insn (char *buf
, unsigned int length
)
1739 for (i
= 0; i
< length
; i
+= 2)
1742 if (target_big_endian
)
1743 insn
|= bfd_getb16 ((char *) buf
);
1745 insn
|= bfd_getl16 ((char *) buf
);
1751 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1752 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1755 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
1759 for (i
= 0; i
< length
; i
+= 2)
1760 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
1761 return buf
+ length
;
1764 /* Install INSN at the location specified by its "frag" and "where" fields. */
1767 install_insn (const struct mips_cl_insn
*insn
)
1769 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1770 if (HAVE_CODE_COMPRESSION
)
1771 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
1773 write_insn (f
, insn
->insn_opcode
);
1774 mips_record_compressed_mode ();
1777 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1778 and install the opcode in the new location. */
1781 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1786 insn
->where
= where
;
1787 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1788 if (insn
->fixp
[i
] != NULL
)
1790 insn
->fixp
[i
]->fx_frag
= frag
;
1791 insn
->fixp
[i
]->fx_where
= where
;
1793 install_insn (insn
);
1796 /* Add INSN to the end of the output. */
1799 add_fixed_insn (struct mips_cl_insn
*insn
)
1801 char *f
= frag_more (insn_length (insn
));
1802 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1805 /* Start a variant frag and move INSN to the start of the variant part,
1806 marking it as fixed. The other arguments are as for frag_var. */
1809 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1810 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1812 frag_grow (max_chars
);
1813 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1815 frag_var (rs_machine_dependent
, max_chars
, var
,
1816 subtype
, symbol
, offset
, NULL
);
1819 /* Insert N copies of INSN into the history buffer, starting at
1820 position FIRST. Neither FIRST nor N need to be clipped. */
1823 insert_into_history (unsigned int first
, unsigned int n
,
1824 const struct mips_cl_insn
*insn
)
1826 if (mips_relax
.sequence
!= 2)
1830 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1832 history
[i
] = history
[i
- n
];
1838 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1839 the idea is to make it obvious at a glance that each errata is
1843 init_vr4120_conflicts (void)
1845 #define CONFLICT(FIRST, SECOND) \
1846 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1848 /* Errata 21 - [D]DIV[U] after [D]MACC */
1849 CONFLICT (MACC
, DIV
);
1850 CONFLICT (DMACC
, DIV
);
1852 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1853 CONFLICT (DMULT
, DMULT
);
1854 CONFLICT (DMULT
, DMACC
);
1855 CONFLICT (DMACC
, DMULT
);
1856 CONFLICT (DMACC
, DMACC
);
1858 /* Errata 24 - MT{LO,HI} after [D]MACC */
1859 CONFLICT (MACC
, MTHILO
);
1860 CONFLICT (DMACC
, MTHILO
);
1862 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1863 instruction is executed immediately after a MACC or DMACC
1864 instruction, the result of [either instruction] is incorrect." */
1865 CONFLICT (MACC
, MULT
);
1866 CONFLICT (MACC
, DMULT
);
1867 CONFLICT (DMACC
, MULT
);
1868 CONFLICT (DMACC
, DMULT
);
1870 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1871 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1872 DDIV or DDIVU instruction, the result of the MACC or
1873 DMACC instruction is incorrect.". */
1874 CONFLICT (DMULT
, MACC
);
1875 CONFLICT (DMULT
, DMACC
);
1876 CONFLICT (DIV
, MACC
);
1877 CONFLICT (DIV
, DMACC
);
1887 #define RTYPE_MASK 0x1ff00
1888 #define RTYPE_NUM 0x00100
1889 #define RTYPE_FPU 0x00200
1890 #define RTYPE_FCC 0x00400
1891 #define RTYPE_VEC 0x00800
1892 #define RTYPE_GP 0x01000
1893 #define RTYPE_CP0 0x02000
1894 #define RTYPE_PC 0x04000
1895 #define RTYPE_ACC 0x08000
1896 #define RTYPE_CCC 0x10000
1897 #define RNUM_MASK 0x000ff
1898 #define RWARN 0x80000
1900 #define GENERIC_REGISTER_NUMBERS \
1901 {"$0", RTYPE_NUM | 0}, \
1902 {"$1", RTYPE_NUM | 1}, \
1903 {"$2", RTYPE_NUM | 2}, \
1904 {"$3", RTYPE_NUM | 3}, \
1905 {"$4", RTYPE_NUM | 4}, \
1906 {"$5", RTYPE_NUM | 5}, \
1907 {"$6", RTYPE_NUM | 6}, \
1908 {"$7", RTYPE_NUM | 7}, \
1909 {"$8", RTYPE_NUM | 8}, \
1910 {"$9", RTYPE_NUM | 9}, \
1911 {"$10", RTYPE_NUM | 10}, \
1912 {"$11", RTYPE_NUM | 11}, \
1913 {"$12", RTYPE_NUM | 12}, \
1914 {"$13", RTYPE_NUM | 13}, \
1915 {"$14", RTYPE_NUM | 14}, \
1916 {"$15", RTYPE_NUM | 15}, \
1917 {"$16", RTYPE_NUM | 16}, \
1918 {"$17", RTYPE_NUM | 17}, \
1919 {"$18", RTYPE_NUM | 18}, \
1920 {"$19", RTYPE_NUM | 19}, \
1921 {"$20", RTYPE_NUM | 20}, \
1922 {"$21", RTYPE_NUM | 21}, \
1923 {"$22", RTYPE_NUM | 22}, \
1924 {"$23", RTYPE_NUM | 23}, \
1925 {"$24", RTYPE_NUM | 24}, \
1926 {"$25", RTYPE_NUM | 25}, \
1927 {"$26", RTYPE_NUM | 26}, \
1928 {"$27", RTYPE_NUM | 27}, \
1929 {"$28", RTYPE_NUM | 28}, \
1930 {"$29", RTYPE_NUM | 29}, \
1931 {"$30", RTYPE_NUM | 30}, \
1932 {"$31", RTYPE_NUM | 31}
1934 #define FPU_REGISTER_NAMES \
1935 {"$f0", RTYPE_FPU | 0}, \
1936 {"$f1", RTYPE_FPU | 1}, \
1937 {"$f2", RTYPE_FPU | 2}, \
1938 {"$f3", RTYPE_FPU | 3}, \
1939 {"$f4", RTYPE_FPU | 4}, \
1940 {"$f5", RTYPE_FPU | 5}, \
1941 {"$f6", RTYPE_FPU | 6}, \
1942 {"$f7", RTYPE_FPU | 7}, \
1943 {"$f8", RTYPE_FPU | 8}, \
1944 {"$f9", RTYPE_FPU | 9}, \
1945 {"$f10", RTYPE_FPU | 10}, \
1946 {"$f11", RTYPE_FPU | 11}, \
1947 {"$f12", RTYPE_FPU | 12}, \
1948 {"$f13", RTYPE_FPU | 13}, \
1949 {"$f14", RTYPE_FPU | 14}, \
1950 {"$f15", RTYPE_FPU | 15}, \
1951 {"$f16", RTYPE_FPU | 16}, \
1952 {"$f17", RTYPE_FPU | 17}, \
1953 {"$f18", RTYPE_FPU | 18}, \
1954 {"$f19", RTYPE_FPU | 19}, \
1955 {"$f20", RTYPE_FPU | 20}, \
1956 {"$f21", RTYPE_FPU | 21}, \
1957 {"$f22", RTYPE_FPU | 22}, \
1958 {"$f23", RTYPE_FPU | 23}, \
1959 {"$f24", RTYPE_FPU | 24}, \
1960 {"$f25", RTYPE_FPU | 25}, \
1961 {"$f26", RTYPE_FPU | 26}, \
1962 {"$f27", RTYPE_FPU | 27}, \
1963 {"$f28", RTYPE_FPU | 28}, \
1964 {"$f29", RTYPE_FPU | 29}, \
1965 {"$f30", RTYPE_FPU | 30}, \
1966 {"$f31", RTYPE_FPU | 31}
1968 #define FPU_CONDITION_CODE_NAMES \
1969 {"$fcc0", RTYPE_FCC | 0}, \
1970 {"$fcc1", RTYPE_FCC | 1}, \
1971 {"$fcc2", RTYPE_FCC | 2}, \
1972 {"$fcc3", RTYPE_FCC | 3}, \
1973 {"$fcc4", RTYPE_FCC | 4}, \
1974 {"$fcc5", RTYPE_FCC | 5}, \
1975 {"$fcc6", RTYPE_FCC | 6}, \
1976 {"$fcc7", RTYPE_FCC | 7}
1978 #define COPROC_CONDITION_CODE_NAMES \
1979 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1980 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1981 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1982 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1983 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1984 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1985 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1986 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1988 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1989 {"$a4", RTYPE_GP | 8}, \
1990 {"$a5", RTYPE_GP | 9}, \
1991 {"$a6", RTYPE_GP | 10}, \
1992 {"$a7", RTYPE_GP | 11}, \
1993 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1994 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1995 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1996 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1997 {"$t0", RTYPE_GP | 12}, \
1998 {"$t1", RTYPE_GP | 13}, \
1999 {"$t2", RTYPE_GP | 14}, \
2000 {"$t3", RTYPE_GP | 15}
2002 #define O32_SYMBOLIC_REGISTER_NAMES \
2003 {"$t0", RTYPE_GP | 8}, \
2004 {"$t1", RTYPE_GP | 9}, \
2005 {"$t2", RTYPE_GP | 10}, \
2006 {"$t3", RTYPE_GP | 11}, \
2007 {"$t4", RTYPE_GP | 12}, \
2008 {"$t5", RTYPE_GP | 13}, \
2009 {"$t6", RTYPE_GP | 14}, \
2010 {"$t7", RTYPE_GP | 15}, \
2011 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2012 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2013 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2014 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2016 /* Remaining symbolic register names */
2017 #define SYMBOLIC_REGISTER_NAMES \
2018 {"$zero", RTYPE_GP | 0}, \
2019 {"$at", RTYPE_GP | 1}, \
2020 {"$AT", RTYPE_GP | 1}, \
2021 {"$v0", RTYPE_GP | 2}, \
2022 {"$v1", RTYPE_GP | 3}, \
2023 {"$a0", RTYPE_GP | 4}, \
2024 {"$a1", RTYPE_GP | 5}, \
2025 {"$a2", RTYPE_GP | 6}, \
2026 {"$a3", RTYPE_GP | 7}, \
2027 {"$s0", RTYPE_GP | 16}, \
2028 {"$s1", RTYPE_GP | 17}, \
2029 {"$s2", RTYPE_GP | 18}, \
2030 {"$s3", RTYPE_GP | 19}, \
2031 {"$s4", RTYPE_GP | 20}, \
2032 {"$s5", RTYPE_GP | 21}, \
2033 {"$s6", RTYPE_GP | 22}, \
2034 {"$s7", RTYPE_GP | 23}, \
2035 {"$t8", RTYPE_GP | 24}, \
2036 {"$t9", RTYPE_GP | 25}, \
2037 {"$k0", RTYPE_GP | 26}, \
2038 {"$kt0", RTYPE_GP | 26}, \
2039 {"$k1", RTYPE_GP | 27}, \
2040 {"$kt1", RTYPE_GP | 27}, \
2041 {"$gp", RTYPE_GP | 28}, \
2042 {"$sp", RTYPE_GP | 29}, \
2043 {"$s8", RTYPE_GP | 30}, \
2044 {"$fp", RTYPE_GP | 30}, \
2045 {"$ra", RTYPE_GP | 31}
2047 #define MIPS16_SPECIAL_REGISTER_NAMES \
2048 {"$pc", RTYPE_PC | 0}
2050 #define MDMX_VECTOR_REGISTER_NAMES \
2051 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2052 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2053 {"$v2", RTYPE_VEC | 2}, \
2054 {"$v3", RTYPE_VEC | 3}, \
2055 {"$v4", RTYPE_VEC | 4}, \
2056 {"$v5", RTYPE_VEC | 5}, \
2057 {"$v6", RTYPE_VEC | 6}, \
2058 {"$v7", RTYPE_VEC | 7}, \
2059 {"$v8", RTYPE_VEC | 8}, \
2060 {"$v9", RTYPE_VEC | 9}, \
2061 {"$v10", RTYPE_VEC | 10}, \
2062 {"$v11", RTYPE_VEC | 11}, \
2063 {"$v12", RTYPE_VEC | 12}, \
2064 {"$v13", RTYPE_VEC | 13}, \
2065 {"$v14", RTYPE_VEC | 14}, \
2066 {"$v15", RTYPE_VEC | 15}, \
2067 {"$v16", RTYPE_VEC | 16}, \
2068 {"$v17", RTYPE_VEC | 17}, \
2069 {"$v18", RTYPE_VEC | 18}, \
2070 {"$v19", RTYPE_VEC | 19}, \
2071 {"$v20", RTYPE_VEC | 20}, \
2072 {"$v21", RTYPE_VEC | 21}, \
2073 {"$v22", RTYPE_VEC | 22}, \
2074 {"$v23", RTYPE_VEC | 23}, \
2075 {"$v24", RTYPE_VEC | 24}, \
2076 {"$v25", RTYPE_VEC | 25}, \
2077 {"$v26", RTYPE_VEC | 26}, \
2078 {"$v27", RTYPE_VEC | 27}, \
2079 {"$v28", RTYPE_VEC | 28}, \
2080 {"$v29", RTYPE_VEC | 29}, \
2081 {"$v30", RTYPE_VEC | 30}, \
2082 {"$v31", RTYPE_VEC | 31}
2084 #define MIPS_DSP_ACCUMULATOR_NAMES \
2085 {"$ac0", RTYPE_ACC | 0}, \
2086 {"$ac1", RTYPE_ACC | 1}, \
2087 {"$ac2", RTYPE_ACC | 2}, \
2088 {"$ac3", RTYPE_ACC | 3}
2090 static const struct regname reg_names
[] = {
2091 GENERIC_REGISTER_NUMBERS
,
2093 FPU_CONDITION_CODE_NAMES
,
2094 COPROC_CONDITION_CODE_NAMES
,
2096 /* The $txx registers depends on the abi,
2097 these will be added later into the symbol table from
2098 one of the tables below once mips_abi is set after
2099 parsing of arguments from the command line. */
2100 SYMBOLIC_REGISTER_NAMES
,
2102 MIPS16_SPECIAL_REGISTER_NAMES
,
2103 MDMX_VECTOR_REGISTER_NAMES
,
2104 MIPS_DSP_ACCUMULATOR_NAMES
,
2108 static const struct regname reg_names_o32
[] = {
2109 O32_SYMBOLIC_REGISTER_NAMES
,
2113 static const struct regname reg_names_n32n64
[] = {
2114 N32N64_SYMBOLIC_REGISTER_NAMES
,
2118 /* Check if S points at a valid register specifier according to TYPES.
2119 If so, then return 1, advance S to consume the specifier and store
2120 the register's number in REGNOP, otherwise return 0. */
2123 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2130 /* Find end of name. */
2132 if (is_name_beginner (*e
))
2134 while (is_part_of_name (*e
))
2137 /* Terminate name. */
2141 /* Look for a register symbol. */
2142 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2144 int r
= S_GET_VALUE (symbolP
);
2146 reg
= r
& RNUM_MASK
;
2147 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2148 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2149 reg
= (r
& RNUM_MASK
) - 2;
2151 /* Else see if this is a register defined in an itbl entry. */
2152 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2159 if (itbl_get_reg_val (n
, &r
))
2160 reg
= r
& RNUM_MASK
;
2163 /* Advance to next token if a register was recognised. */
2166 else if (types
& RWARN
)
2167 as_warn (_("Unrecognized register name `%s'"), *s
);
2175 /* Check if S points at a valid register list according to TYPES.
2176 If so, then return 1, advance S to consume the list and store
2177 the registers present on the list as a bitmask of ones in REGLISTP,
2178 otherwise return 0. A valid list comprises a comma-separated
2179 enumeration of valid single registers and/or dash-separated
2180 contiguous register ranges as determined by their numbers.
2182 As a special exception if one of s0-s7 registers is specified as
2183 the range's lower delimiter and s8 (fp) is its upper one, then no
2184 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2185 are selected; they have to be listed separately if needed. */
2188 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2190 unsigned int reglist
= 0;
2191 unsigned int lastregno
;
2192 bfd_boolean ok
= TRUE
;
2193 unsigned int regmask
;
2194 char *s_endlist
= *s
;
2198 while (reg_lookup (s
, types
, ®no
))
2204 ok
= reg_lookup (s
, types
, &lastregno
);
2205 if (ok
&& lastregno
< regno
)
2211 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2216 regmask
= 1 << lastregno
;
2217 regmask
= (regmask
<< 1) - 1;
2218 regmask
^= (1 << regno
) - 1;
2232 *reglistp
= reglist
;
2233 return ok
&& reglist
!= 0;
2236 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2237 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2240 is_opcode_valid (const struct mips_opcode
*mo
)
2242 int isa
= mips_opts
.isa
;
2245 if (mips_opts
.ase_mdmx
)
2247 if (mips_opts
.ase_dsp
)
2249 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2251 if (mips_opts
.ase_dspr2
)
2253 if (mips_opts
.ase_mt
)
2255 if (mips_opts
.ase_mips3d
)
2257 if (mips_opts
.ase_smartmips
)
2258 isa
|= INSN_SMARTMIPS
;
2259 if (mips_opts
.ase_mcu
)
2262 if (!opcode_is_member (mo
, isa
, mips_opts
.arch
))
2265 /* Check whether the instruction or macro requires single-precision or
2266 double-precision floating-point support. Note that this information is
2267 stored differently in the opcode table for insns and macros. */
2268 if (mo
->pinfo
== INSN_MACRO
)
2270 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2271 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2275 fp_s
= mo
->pinfo
& FP_S
;
2276 fp_d
= mo
->pinfo
& FP_D
;
2279 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2282 if (fp_s
&& mips_opts
.soft_float
)
2288 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2289 selected ISA and architecture. */
2292 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2294 return opcode_is_member (mo
, mips_opts
.isa
, mips_opts
.arch
);
2297 /* Return TRUE if the size of the microMIPS opcode MO matches one
2298 explicitly requested. Always TRUE in the standard MIPS mode. */
2301 is_size_valid (const struct mips_opcode
*mo
)
2303 if (!mips_opts
.micromips
)
2306 if (!forced_insn_length
)
2308 if (mo
->pinfo
== INSN_MACRO
)
2310 return forced_insn_length
== micromips_insn_length (mo
);
2313 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2314 of the preceding instruction. Always TRUE in the standard MIPS mode.
2316 We don't accept macros in 16-bit delay slots to avoid a case where
2317 a macro expansion fails because it relies on a preceding 32-bit real
2318 instruction to have matched and does not handle the operands correctly.
2319 The only macros that may expand to 16-bit instructions are JAL that
2320 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2321 and BGT (that likewise cannot be placed in a delay slot) that decay to
2322 a NOP. In all these cases the macros precede any corresponding real
2323 instruction definitions in the opcode table, so they will match in the
2324 second pass where the size of the delay slot is ignored and therefore
2325 produce correct code. */
2328 is_delay_slot_valid (const struct mips_opcode
*mo
)
2330 if (!mips_opts
.micromips
)
2333 if (mo
->pinfo
== INSN_MACRO
)
2334 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2335 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2336 && micromips_insn_length (mo
) != 4)
2338 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2339 && micromips_insn_length (mo
) != 2)
2345 /* This function is called once, at assembler startup time. It should set up
2346 all the tables, etc. that the MD part of the assembler will need. */
2351 const char *retval
= NULL
;
2355 if (mips_pic
!= NO_PIC
)
2357 if (g_switch_seen
&& g_switch_value
!= 0)
2358 as_bad (_("-G may not be used in position-independent code"));
2362 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2363 as_warn (_("Could not set architecture and machine"));
2365 op_hash
= hash_new ();
2367 for (i
= 0; i
< NUMOPCODES
;)
2369 const char *name
= mips_opcodes
[i
].name
;
2371 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2374 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2375 mips_opcodes
[i
].name
, retval
);
2376 /* Probably a memory allocation problem? Give up now. */
2377 as_fatal (_("Broken assembler. No assembly attempted."));
2381 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2383 if (!validate_mips_insn (&mips_opcodes
[i
]))
2385 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2387 create_insn (&nop_insn
, mips_opcodes
+ i
);
2388 if (mips_fix_loongson2f_nop
)
2389 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2390 nop_insn
.fixed_p
= 1;
2395 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2398 mips16_op_hash
= hash_new ();
2401 while (i
< bfd_mips16_num_opcodes
)
2403 const char *name
= mips16_opcodes
[i
].name
;
2405 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2407 as_fatal (_("internal: can't hash `%s': %s"),
2408 mips16_opcodes
[i
].name
, retval
);
2411 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2412 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2413 != mips16_opcodes
[i
].match
))
2415 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2416 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2419 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2421 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2422 mips16_nop_insn
.fixed_p
= 1;
2426 while (i
< bfd_mips16_num_opcodes
2427 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2430 micromips_op_hash
= hash_new ();
2433 while (i
< bfd_micromips_num_opcodes
)
2435 const char *name
= micromips_opcodes
[i
].name
;
2437 retval
= hash_insert (micromips_op_hash
, name
,
2438 (void *) µmips_opcodes
[i
]);
2440 as_fatal (_("internal: can't hash `%s': %s"),
2441 micromips_opcodes
[i
].name
, retval
);
2443 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2445 struct mips_cl_insn
*micromips_nop_insn
;
2447 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2450 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2451 micromips_nop_insn
= µmips_nop16_insn
;
2452 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2453 micromips_nop_insn
= µmips_nop32_insn
;
2457 if (micromips_nop_insn
->insn_mo
== NULL
2458 && strcmp (name
, "nop") == 0)
2460 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2461 micromips_nop_insn
->fixed_p
= 1;
2464 while (++i
< bfd_micromips_num_opcodes
2465 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2469 as_fatal (_("Broken assembler. No assembly attempted."));
2471 /* We add all the general register names to the symbol table. This
2472 helps us detect invalid uses of them. */
2473 for (i
= 0; reg_names
[i
].name
; i
++)
2474 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2475 reg_names
[i
].num
, /* & RNUM_MASK, */
2476 &zero_address_frag
));
2478 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2479 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2480 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2481 &zero_address_frag
));
2483 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2484 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2485 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2486 &zero_address_frag
));
2488 mips_no_prev_insn ();
2491 mips_cprmask
[0] = 0;
2492 mips_cprmask
[1] = 0;
2493 mips_cprmask
[2] = 0;
2494 mips_cprmask
[3] = 0;
2496 /* set the default alignment for the text section (2**2) */
2497 record_alignment (text_section
, 2);
2499 bfd_set_gp_size (stdoutput
, g_switch_value
);
2504 /* On a native system other than VxWorks, sections must be aligned
2505 to 16 byte boundaries. When configured for an embedded ELF
2506 target, we don't bother. */
2507 if (strncmp (TARGET_OS
, "elf", 3) != 0
2508 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2510 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2511 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2512 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2515 /* Create a .reginfo section for register masks and a .mdebug
2516 section for debugging information. */
2524 subseg
= now_subseg
;
2526 /* The ABI says this section should be loaded so that the
2527 running program can access it. However, we don't load it
2528 if we are configured for an embedded target */
2529 flags
= SEC_READONLY
| SEC_DATA
;
2530 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2531 flags
|= SEC_ALLOC
| SEC_LOAD
;
2533 if (mips_abi
!= N64_ABI
)
2535 sec
= subseg_new (".reginfo", (subsegT
) 0);
2537 bfd_set_section_flags (stdoutput
, sec
, flags
);
2538 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2540 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2544 /* The 64-bit ABI uses a .MIPS.options section rather than
2545 .reginfo section. */
2546 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2547 bfd_set_section_flags (stdoutput
, sec
, flags
);
2548 bfd_set_section_alignment (stdoutput
, sec
, 3);
2550 /* Set up the option header. */
2552 Elf_Internal_Options opthdr
;
2555 opthdr
.kind
= ODK_REGINFO
;
2556 opthdr
.size
= (sizeof (Elf_External_Options
)
2557 + sizeof (Elf64_External_RegInfo
));
2560 f
= frag_more (sizeof (Elf_External_Options
));
2561 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2562 (Elf_External_Options
*) f
);
2564 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2568 if (ECOFF_DEBUGGING
)
2570 sec
= subseg_new (".mdebug", (subsegT
) 0);
2571 (void) bfd_set_section_flags (stdoutput
, sec
,
2572 SEC_HAS_CONTENTS
| SEC_READONLY
);
2573 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2575 else if (mips_flag_pdr
)
2577 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2578 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2579 SEC_READONLY
| SEC_RELOC
2581 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2584 subseg_set (seg
, subseg
);
2587 #endif /* OBJ_ELF */
2589 if (! ECOFF_DEBUGGING
)
2592 if (mips_fix_vr4120
)
2593 init_vr4120_conflicts ();
2599 mips_emit_delays ();
2600 if (! ECOFF_DEBUGGING
)
2605 md_assemble (char *str
)
2607 struct mips_cl_insn insn
;
2608 bfd_reloc_code_real_type unused_reloc
[3]
2609 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2611 imm_expr
.X_op
= O_absent
;
2612 imm2_expr
.X_op
= O_absent
;
2613 offset_expr
.X_op
= O_absent
;
2614 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2615 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2616 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2617 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2618 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2619 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2621 mips_mark_labels ();
2622 mips_assembling_insn
= TRUE
;
2624 if (mips_opts
.mips16
)
2625 mips16_ip (str
, &insn
);
2628 mips_ip (str
, &insn
);
2629 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2630 str
, insn
.insn_opcode
));
2634 as_bad ("%s `%s'", insn_error
, str
);
2635 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2638 if (mips_opts
.mips16
)
2639 mips16_macro (&insn
);
2646 if (imm_expr
.X_op
!= O_absent
)
2647 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2648 else if (offset_expr
.X_op
!= O_absent
)
2649 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2651 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2654 mips_assembling_insn
= FALSE
;
2657 /* Convenience functions for abstracting away the differences between
2658 MIPS16 and non-MIPS16 relocations. */
2660 static inline bfd_boolean
2661 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2665 case BFD_RELOC_MIPS16_JMP
:
2666 case BFD_RELOC_MIPS16_GPREL
:
2667 case BFD_RELOC_MIPS16_GOT16
:
2668 case BFD_RELOC_MIPS16_CALL16
:
2669 case BFD_RELOC_MIPS16_HI16_S
:
2670 case BFD_RELOC_MIPS16_HI16
:
2671 case BFD_RELOC_MIPS16_LO16
:
2679 static inline bfd_boolean
2680 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2684 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2685 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2686 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2687 case BFD_RELOC_MICROMIPS_GPREL16
:
2688 case BFD_RELOC_MICROMIPS_JMP
:
2689 case BFD_RELOC_MICROMIPS_HI16
:
2690 case BFD_RELOC_MICROMIPS_HI16_S
:
2691 case BFD_RELOC_MICROMIPS_LO16
:
2692 case BFD_RELOC_MICROMIPS_LITERAL
:
2693 case BFD_RELOC_MICROMIPS_GOT16
:
2694 case BFD_RELOC_MICROMIPS_CALL16
:
2695 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2696 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2697 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2698 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2699 case BFD_RELOC_MICROMIPS_SUB
:
2700 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2701 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2702 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2703 case BFD_RELOC_MICROMIPS_HIGHEST
:
2704 case BFD_RELOC_MICROMIPS_HIGHER
:
2705 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2706 case BFD_RELOC_MICROMIPS_JALR
:
2714 static inline bfd_boolean
2715 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2717 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2720 static inline bfd_boolean
2721 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2723 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2724 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2727 static inline bfd_boolean
2728 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2730 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2731 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2734 static inline bfd_boolean
2735 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2737 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2738 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2741 static inline bfd_boolean
2742 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2744 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2747 /* Return true if RELOC is a PC-relative relocation that does not have
2748 full address range. */
2750 static inline bfd_boolean
2751 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
2755 case BFD_RELOC_16_PCREL_S2
:
2756 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2757 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2758 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2761 case BFD_RELOC_32_PCREL
:
2762 return HAVE_64BIT_ADDRESSES
;
2769 /* Return true if the given relocation might need a matching %lo().
2770 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2771 need a matching %lo() when applied to local symbols. */
2773 static inline bfd_boolean
2774 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2776 return (HAVE_IN_PLACE_ADDENDS
2777 && (hi16_reloc_p (reloc
)
2778 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2779 all GOT16 relocations evaluate to "G". */
2780 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2783 /* Return the type of %lo() reloc needed by RELOC, given that
2784 reloc_needs_lo_p. */
2786 static inline bfd_reloc_code_real_type
2787 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2789 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2790 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2794 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2797 static inline bfd_boolean
2798 fixup_has_matching_lo_p (fixS
*fixp
)
2800 return (fixp
->fx_next
!= NULL
2801 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2802 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2803 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2806 /* This function returns true if modifying a register requires a
2810 reg_needs_delay (unsigned int reg
)
2812 unsigned long prev_pinfo
;
2814 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2815 if (! mips_opts
.noreorder
2816 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2817 && ! gpr_interlocks
)
2818 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2819 && ! cop_interlocks
)))
2821 /* A load from a coprocessor or from memory. All load delays
2822 delay the use of general register rt for one instruction. */
2823 /* Itbl support may require additional care here. */
2824 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2825 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2832 /* Move all labels in LABELS to the current insertion point. TEXT_P
2833 says whether the labels refer to text or data. */
2836 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
2838 struct insn_label_list
*l
;
2841 for (l
= labels
; l
!= NULL
; l
= l
->next
)
2843 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2844 symbol_set_frag (l
->label
, frag_now
);
2845 val
= (valueT
) frag_now_fix ();
2846 /* MIPS16/microMIPS text labels are stored as odd. */
2847 if (text_p
&& HAVE_CODE_COMPRESSION
)
2849 S_SET_VALUE (l
->label
, val
);
2853 /* Move all labels in insn_labels to the current insertion point
2854 and treat them as text labels. */
2857 mips_move_text_labels (void)
2859 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
2863 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2865 bfd_boolean linkonce
= FALSE
;
2866 segT symseg
= S_GET_SEGMENT (sym
);
2868 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2870 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2873 /* The GNU toolchain uses an extension for ELF: a section
2874 beginning with the magic string .gnu.linkonce is a
2875 linkonce section. */
2876 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2877 sizeof ".gnu.linkonce" - 1) == 0)
2884 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2885 linker to handle them specially, such as generating jalx instructions
2886 when needed. We also make them odd for the duration of the assembly,
2887 in order to generate the right sort of code. We will make them even
2888 in the adjust_symtab routine, while leaving them marked. This is
2889 convenient for the debugger and the disassembler. The linker knows
2890 to make them odd again. */
2893 mips_compressed_mark_label (symbolS
*label
)
2895 gas_assert (HAVE_CODE_COMPRESSION
);
2897 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2900 if (mips_opts
.mips16
)
2901 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2903 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2906 if ((S_GET_VALUE (label
) & 1) == 0
2907 /* Don't adjust the address if the label is global or weak, or
2908 in a link-once section, since we'll be emitting symbol reloc
2909 references to it which will be patched up by the linker, and
2910 the final value of the symbol may or may not be MIPS16/microMIPS. */
2911 && !S_IS_WEAK (label
)
2912 && !S_IS_EXTERNAL (label
)
2913 && !s_is_linkonce (label
, now_seg
))
2914 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2917 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2920 mips_compressed_mark_labels (void)
2922 struct insn_label_list
*l
;
2924 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
2925 mips_compressed_mark_label (l
->label
);
2928 /* End the current frag. Make it a variant frag and record the
2932 relax_close_frag (void)
2934 mips_macro_warning
.first_frag
= frag_now
;
2935 frag_var (rs_machine_dependent
, 0, 0,
2936 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2937 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2939 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2940 mips_relax
.first_fixup
= 0;
2943 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2944 See the comment above RELAX_ENCODE for more details. */
2947 relax_start (symbolS
*symbol
)
2949 gas_assert (mips_relax
.sequence
== 0);
2950 mips_relax
.sequence
= 1;
2951 mips_relax
.symbol
= symbol
;
2954 /* Start generating the second version of a relaxable sequence.
2955 See the comment above RELAX_ENCODE for more details. */
2960 gas_assert (mips_relax
.sequence
== 1);
2961 mips_relax
.sequence
= 2;
2964 /* End the current relaxable sequence. */
2969 gas_assert (mips_relax
.sequence
== 2);
2970 relax_close_frag ();
2971 mips_relax
.sequence
= 0;
2974 /* Return true if IP is a delayed branch or jump. */
2976 static inline bfd_boolean
2977 delayed_branch_p (const struct mips_cl_insn
*ip
)
2979 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2980 | INSN_COND_BRANCH_DELAY
2981 | INSN_COND_BRANCH_LIKELY
)) != 0;
2984 /* Return true if IP is a compact branch or jump. */
2986 static inline bfd_boolean
2987 compact_branch_p (const struct mips_cl_insn
*ip
)
2989 if (mips_opts
.mips16
)
2990 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2991 | MIPS16_INSN_COND_BRANCH
)) != 0;
2993 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
2994 | INSN2_COND_BRANCH
)) != 0;
2997 /* Return true if IP is an unconditional branch or jump. */
2999 static inline bfd_boolean
3000 uncond_branch_p (const struct mips_cl_insn
*ip
)
3002 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3003 || (mips_opts
.mips16
3004 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3005 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3008 /* Return true if IP is a branch-likely instruction. */
3010 static inline bfd_boolean
3011 branch_likely_p (const struct mips_cl_insn
*ip
)
3013 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3016 /* Return the type of nop that should be used to fill the delay slot
3017 of delayed branch IP. */
3019 static struct mips_cl_insn
*
3020 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3022 if (mips_opts
.micromips
3023 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3024 return µmips_nop32_insn
;
3028 /* Return the mask of core registers that IP reads or writes. */
3031 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3033 unsigned long pinfo2
;
3037 pinfo2
= ip
->insn_mo
->pinfo2
;
3038 if (mips_opts
.micromips
)
3040 if (pinfo2
& INSN2_MOD_GPR_MD
)
3041 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3042 if (pinfo2
& INSN2_MOD_GPR_MF
)
3043 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3044 if (pinfo2
& INSN2_MOD_SP
)
3050 /* Return the mask of core registers that IP reads. */
3053 gpr_read_mask (const struct mips_cl_insn
*ip
)
3055 unsigned long pinfo
, pinfo2
;
3058 mask
= gpr_mod_mask (ip
);
3059 pinfo
= ip
->insn_mo
->pinfo
;
3060 pinfo2
= ip
->insn_mo
->pinfo2
;
3061 if (mips_opts
.mips16
)
3063 if (pinfo
& MIPS16_INSN_READ_X
)
3064 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3065 if (pinfo
& MIPS16_INSN_READ_Y
)
3066 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3067 if (pinfo
& MIPS16_INSN_READ_T
)
3069 if (pinfo
& MIPS16_INSN_READ_SP
)
3071 if (pinfo
& MIPS16_INSN_READ_31
)
3073 if (pinfo
& MIPS16_INSN_READ_Z
)
3074 mask
|= 1 << (mips16_to_32_reg_map
3075 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3076 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3077 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3081 if (pinfo2
& INSN2_READ_GPR_D
)
3082 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3083 if (pinfo
& INSN_READ_GPR_T
)
3084 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3085 if (pinfo
& INSN_READ_GPR_S
)
3086 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3087 if (pinfo2
& INSN2_READ_GP
)
3089 if (pinfo2
& INSN2_READ_GPR_31
)
3091 if (pinfo2
& INSN2_READ_GPR_Z
)
3092 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3094 if (mips_opts
.micromips
)
3096 if (pinfo2
& INSN2_READ_GPR_MC
)
3097 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3098 if (pinfo2
& INSN2_READ_GPR_ME
)
3099 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3100 if (pinfo2
& INSN2_READ_GPR_MG
)
3101 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3102 if (pinfo2
& INSN2_READ_GPR_MJ
)
3103 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3104 if (pinfo2
& INSN2_READ_GPR_MMN
)
3106 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3107 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3109 if (pinfo2
& INSN2_READ_GPR_MP
)
3110 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3111 if (pinfo2
& INSN2_READ_GPR_MQ
)
3112 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3114 /* Don't include register 0. */
3118 /* Return the mask of core registers that IP writes. */
3121 gpr_write_mask (const struct mips_cl_insn
*ip
)
3123 unsigned long pinfo
, pinfo2
;
3126 mask
= gpr_mod_mask (ip
);
3127 pinfo
= ip
->insn_mo
->pinfo
;
3128 pinfo2
= ip
->insn_mo
->pinfo2
;
3129 if (mips_opts
.mips16
)
3131 if (pinfo
& MIPS16_INSN_WRITE_X
)
3132 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3133 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3134 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3135 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3136 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3137 if (pinfo
& MIPS16_INSN_WRITE_T
)
3139 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3141 if (pinfo
& MIPS16_INSN_WRITE_31
)
3143 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3144 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3148 if (pinfo
& INSN_WRITE_GPR_D
)
3149 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3150 if (pinfo
& INSN_WRITE_GPR_T
)
3151 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3152 if (pinfo
& INSN_WRITE_GPR_S
)
3153 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3154 if (pinfo
& INSN_WRITE_GPR_31
)
3156 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3157 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3159 if (mips_opts
.micromips
)
3161 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3162 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3163 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3165 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3166 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3168 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3169 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3170 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3171 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3173 /* Don't include register 0. */
3177 /* Return the mask of floating-point registers that IP reads. */
3180 fpr_read_mask (const struct mips_cl_insn
*ip
)
3182 unsigned long pinfo
, pinfo2
;
3186 pinfo
= ip
->insn_mo
->pinfo
;
3187 pinfo2
= ip
->insn_mo
->pinfo2
;
3188 if (!mips_opts
.mips16
)
3190 if (pinfo2
& INSN2_READ_FPR_D
)
3191 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3192 if (pinfo
& INSN_READ_FPR_S
)
3193 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3194 if (pinfo
& INSN_READ_FPR_T
)
3195 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3196 if (pinfo
& INSN_READ_FPR_R
)
3197 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3198 if (pinfo2
& INSN2_READ_FPR_Z
)
3199 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3201 /* Conservatively treat all operands to an FP_D instruction are doubles.
3202 (This is overly pessimistic for things like cvt.d.s.) */
3203 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3208 /* Return the mask of floating-point registers that IP writes. */
3211 fpr_write_mask (const struct mips_cl_insn
*ip
)
3213 unsigned long pinfo
, pinfo2
;
3217 pinfo
= ip
->insn_mo
->pinfo
;
3218 pinfo2
= ip
->insn_mo
->pinfo2
;
3219 if (!mips_opts
.mips16
)
3221 if (pinfo
& INSN_WRITE_FPR_D
)
3222 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3223 if (pinfo
& INSN_WRITE_FPR_S
)
3224 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3225 if (pinfo
& INSN_WRITE_FPR_T
)
3226 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3227 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3228 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3230 /* Conservatively treat all operands to an FP_D instruction are doubles.
3231 (This is overly pessimistic for things like cvt.s.d.) */
3232 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3237 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3238 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3239 by VR4120 errata. */
3242 classify_vr4120_insn (const char *name
)
3244 if (strncmp (name
, "macc", 4) == 0)
3245 return FIX_VR4120_MACC
;
3246 if (strncmp (name
, "dmacc", 5) == 0)
3247 return FIX_VR4120_DMACC
;
3248 if (strncmp (name
, "mult", 4) == 0)
3249 return FIX_VR4120_MULT
;
3250 if (strncmp (name
, "dmult", 5) == 0)
3251 return FIX_VR4120_DMULT
;
3252 if (strstr (name
, "div"))
3253 return FIX_VR4120_DIV
;
3254 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3255 return FIX_VR4120_MTHILO
;
3256 return NUM_FIX_VR4120_CLASSES
;
3259 #define INSN_ERET 0x42000018
3260 #define INSN_DERET 0x4200001f
3262 /* Return the number of instructions that must separate INSN1 and INSN2,
3263 where INSN1 is the earlier instruction. Return the worst-case value
3264 for any INSN2 if INSN2 is null. */
3267 insns_between (const struct mips_cl_insn
*insn1
,
3268 const struct mips_cl_insn
*insn2
)
3270 unsigned long pinfo1
, pinfo2
;
3273 /* This function needs to know which pinfo flags are set for INSN2
3274 and which registers INSN2 uses. The former is stored in PINFO2 and
3275 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3276 will have every flag set and INSN2_USES_GPR will always return true. */
3277 pinfo1
= insn1
->insn_mo
->pinfo
;
3278 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3280 #define INSN2_USES_GPR(REG) \
3281 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3283 /* For most targets, write-after-read dependencies on the HI and LO
3284 registers must be separated by at least two instructions. */
3285 if (!hilo_interlocks
)
3287 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3289 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3293 /* If we're working around r7000 errata, there must be two instructions
3294 between an mfhi or mflo and any instruction that uses the result. */
3295 if (mips_7000_hilo_fix
3296 && !mips_opts
.micromips
3297 && MF_HILO_INSN (pinfo1
)
3298 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3301 /* If we're working around 24K errata, one instruction is required
3302 if an ERET or DERET is followed by a branch instruction. */
3303 if (mips_fix_24k
&& !mips_opts
.micromips
)
3305 if (insn1
->insn_opcode
== INSN_ERET
3306 || insn1
->insn_opcode
== INSN_DERET
)
3309 || insn2
->insn_opcode
== INSN_ERET
3310 || insn2
->insn_opcode
== INSN_DERET
3311 || delayed_branch_p (insn2
))
3316 /* If working around VR4120 errata, check for combinations that need
3317 a single intervening instruction. */
3318 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3320 unsigned int class1
, class2
;
3322 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3323 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3327 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3328 if (vr4120_conflicts
[class1
] & (1 << class2
))
3333 if (!HAVE_CODE_COMPRESSION
)
3335 /* Check for GPR or coprocessor load delays. All such delays
3336 are on the RT register. */
3337 /* Itbl support may require additional care here. */
3338 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3339 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3341 know (pinfo1
& INSN_WRITE_GPR_T
);
3342 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3346 /* Check for generic coprocessor hazards.
3348 This case is not handled very well. There is no special
3349 knowledge of CP0 handling, and the coprocessors other than
3350 the floating point unit are not distinguished at all. */
3351 /* Itbl support may require additional care here. FIXME!
3352 Need to modify this to include knowledge about
3353 user specified delays! */
3354 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3355 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3357 /* Handle cases where INSN1 writes to a known general coprocessor
3358 register. There must be a one instruction delay before INSN2
3359 if INSN2 reads that register, otherwise no delay is needed. */
3360 mask
= fpr_write_mask (insn1
);
3363 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3368 /* Read-after-write dependencies on the control registers
3369 require a two-instruction gap. */
3370 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3371 && (pinfo2
& INSN_READ_COND_CODE
))
3374 /* We don't know exactly what INSN1 does. If INSN2 is
3375 also a coprocessor instruction, assume there must be
3376 a one instruction gap. */
3377 if (pinfo2
& INSN_COP
)
3382 /* Check for read-after-write dependencies on the coprocessor
3383 control registers in cases where INSN1 does not need a general
3384 coprocessor delay. This means that INSN1 is a floating point
3385 comparison instruction. */
3386 /* Itbl support may require additional care here. */
3387 else if (!cop_interlocks
3388 && (pinfo1
& INSN_WRITE_COND_CODE
)
3389 && (pinfo2
& INSN_READ_COND_CODE
))
3393 #undef INSN2_USES_GPR
3398 /* Return the number of nops that would be needed to work around the
3399 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3400 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3401 that are contained within the first IGNORE instructions of HIST. */
3404 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3405 const struct mips_cl_insn
*insn
)
3410 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3411 are not affected by the errata. */
3413 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3414 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3415 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3418 /* Search for the first MFLO or MFHI. */
3419 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3420 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3422 /* Extract the destination register. */
3423 mask
= gpr_write_mask (&hist
[i
]);
3425 /* No nops are needed if INSN reads that register. */
3426 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3429 /* ...or if any of the intervening instructions do. */
3430 for (j
= 0; j
< i
; j
++)
3431 if (gpr_read_mask (&hist
[j
]) & mask
)
3435 return MAX_VR4130_NOPS
- i
;
3440 #define BASE_REG_EQ(INSN1, INSN2) \
3441 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3442 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3444 /* Return the minimum alignment for this store instruction. */
3447 fix_24k_align_to (const struct mips_opcode
*mo
)
3449 if (strcmp (mo
->name
, "sh") == 0)
3452 if (strcmp (mo
->name
, "swc1") == 0
3453 || strcmp (mo
->name
, "swc2") == 0
3454 || strcmp (mo
->name
, "sw") == 0
3455 || strcmp (mo
->name
, "sc") == 0
3456 || strcmp (mo
->name
, "s.s") == 0)
3459 if (strcmp (mo
->name
, "sdc1") == 0
3460 || strcmp (mo
->name
, "sdc2") == 0
3461 || strcmp (mo
->name
, "s.d") == 0)
3468 struct fix_24k_store_info
3470 /* Immediate offset, if any, for this store instruction. */
3472 /* Alignment required by this store instruction. */
3474 /* True for register offsets. */
3475 int register_offset
;
3478 /* Comparison function used by qsort. */
3481 fix_24k_sort (const void *a
, const void *b
)
3483 const struct fix_24k_store_info
*pos1
= a
;
3484 const struct fix_24k_store_info
*pos2
= b
;
3486 return (pos1
->off
- pos2
->off
);
3489 /* INSN is a store instruction. Try to record the store information
3490 in STINFO. Return false if the information isn't known. */
3493 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3494 const struct mips_cl_insn
*insn
)
3496 /* The instruction must have a known offset. */
3497 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3500 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3501 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3505 /* Return the number of nops that would be needed to work around the 24k
3506 "lost data on stores during refill" errata if instruction INSN
3507 immediately followed the 2 instructions described by HIST.
3508 Ignore hazards that are contained within the first IGNORE
3509 instructions of HIST.
3511 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3512 for the data cache refills and store data. The following describes
3513 the scenario where the store data could be lost.
3515 * A data cache miss, due to either a load or a store, causing fill
3516 data to be supplied by the memory subsystem
3517 * The first three doublewords of fill data are returned and written
3519 * A sequence of four stores occurs in consecutive cycles around the
3520 final doubleword of the fill:
3524 * Zero, One or more instructions
3527 The four stores A-D must be to different doublewords of the line that
3528 is being filled. The fourth instruction in the sequence above permits
3529 the fill of the final doubleword to be transferred from the FSB into
3530 the cache. In the sequence above, the stores may be either integer
3531 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3532 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3533 different doublewords on the line. If the floating point unit is
3534 running in 1:2 mode, it is not possible to create the sequence above
3535 using only floating point store instructions.
3537 In this case, the cache line being filled is incorrectly marked
3538 invalid, thereby losing the data from any store to the line that
3539 occurs between the original miss and the completion of the five
3540 cycle sequence shown above.
3542 The workarounds are:
3544 * Run the data cache in write-through mode.
3545 * Insert a non-store instruction between
3546 Store A and Store B or Store B and Store C. */
3549 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3550 const struct mips_cl_insn
*insn
)
3552 struct fix_24k_store_info pos
[3];
3553 int align
, i
, base_offset
;
3558 /* If the previous instruction wasn't a store, there's nothing to
3560 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3563 /* If the instructions after the previous one are unknown, we have
3564 to assume the worst. */
3568 /* Check whether we are dealing with three consecutive stores. */
3569 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3570 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3573 /* If we don't know the relationship between the store addresses,
3574 assume the worst. */
3575 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3576 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3579 if (!fix_24k_record_store_info (&pos
[0], insn
)
3580 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3581 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3584 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3586 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3587 X bytes and such that the base register + X is known to be aligned
3590 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3594 align
= pos
[0].align_to
;
3595 base_offset
= pos
[0].off
;
3596 for (i
= 1; i
< 3; i
++)
3597 if (align
< pos
[i
].align_to
)
3599 align
= pos
[i
].align_to
;
3600 base_offset
= pos
[i
].off
;
3602 for (i
= 0; i
< 3; i
++)
3603 pos
[i
].off
-= base_offset
;
3606 pos
[0].off
&= ~align
+ 1;
3607 pos
[1].off
&= ~align
+ 1;
3608 pos
[2].off
&= ~align
+ 1;
3610 /* If any two stores write to the same chunk, they also write to the
3611 same doubleword. The offsets are still sorted at this point. */
3612 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3615 /* A range of at least 9 bytes is needed for the stores to be in
3616 non-overlapping doublewords. */
3617 if (pos
[2].off
- pos
[0].off
<= 8)
3620 if (pos
[2].off
- pos
[1].off
>= 24
3621 || pos
[1].off
- pos
[0].off
>= 24
3622 || pos
[2].off
- pos
[0].off
>= 32)
3628 /* Return the number of nops that would be needed if instruction INSN
3629 immediately followed the MAX_NOPS instructions given by HIST,
3630 where HIST[0] is the most recent instruction. Ignore hazards
3631 between INSN and the first IGNORE instructions in HIST.
3633 If INSN is null, return the worse-case number of nops for any
3637 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3638 const struct mips_cl_insn
*insn
)
3640 int i
, nops
, tmp_nops
;
3643 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3645 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3646 if (tmp_nops
> nops
)
3650 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3652 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3653 if (tmp_nops
> nops
)
3657 if (mips_fix_24k
&& !mips_opts
.micromips
)
3659 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3660 if (tmp_nops
> nops
)
3667 /* The variable arguments provide NUM_INSNS extra instructions that
3668 might be added to HIST. Return the largest number of nops that
3669 would be needed after the extended sequence, ignoring hazards
3670 in the first IGNORE instructions. */
3673 nops_for_sequence (int num_insns
, int ignore
,
3674 const struct mips_cl_insn
*hist
, ...)
3677 struct mips_cl_insn buffer
[MAX_NOPS
];
3678 struct mips_cl_insn
*cursor
;
3681 va_start (args
, hist
);
3682 cursor
= buffer
+ num_insns
;
3683 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3684 while (cursor
> buffer
)
3685 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3687 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3692 /* Like nops_for_insn, but if INSN is a branch, take into account the
3693 worst-case delay for the branch target. */
3696 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3697 const struct mips_cl_insn
*insn
)
3701 nops
= nops_for_insn (ignore
, hist
, insn
);
3702 if (delayed_branch_p (insn
))
3704 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3705 hist
, insn
, get_delay_slot_nop (insn
));
3706 if (tmp_nops
> nops
)
3709 else if (compact_branch_p (insn
))
3711 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3712 if (tmp_nops
> nops
)
3718 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3721 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3723 gas_assert (!HAVE_CODE_COMPRESSION
);
3724 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3725 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3728 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3729 jr target pc &= 'hffff_ffff_cfff_ffff. */
3732 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3734 gas_assert (!HAVE_CODE_COMPRESSION
);
3735 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3736 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3737 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3745 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3746 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3749 ep
.X_op
= O_constant
;
3750 ep
.X_add_number
= 0xcfff0000;
3751 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3752 ep
.X_add_number
= 0xffff;
3753 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3754 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3759 fix_loongson2f (struct mips_cl_insn
* ip
)
3761 if (mips_fix_loongson2f_nop
)
3762 fix_loongson2f_nop (ip
);
3764 if (mips_fix_loongson2f_jump
)
3765 fix_loongson2f_jump (ip
);
3768 /* IP is a branch that has a delay slot, and we need to fill it
3769 automatically. Return true if we can do that by swapping IP
3770 with the previous instruction.
3771 ADDRESS_EXPR is an operand of the instruction to be used with
3775 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3776 bfd_reloc_code_real_type
*reloc_type
)
3778 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3779 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3781 /* -O2 and above is required for this optimization. */
3782 if (mips_optimize
< 2)
3785 /* If we have seen .set volatile or .set nomove, don't optimize. */
3786 if (mips_opts
.nomove
)
3789 /* We can't swap if the previous instruction's position is fixed. */
3790 if (history
[0].fixed_p
)
3793 /* If the previous previous insn was in a .set noreorder, we can't
3794 swap. Actually, the MIPS assembler will swap in this situation.
3795 However, gcc configured -with-gnu-as will generate code like
3803 in which we can not swap the bne and INSN. If gcc is not configured
3804 -with-gnu-as, it does not output the .set pseudo-ops. */
3805 if (history
[1].noreorder_p
)
3808 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3809 This means that the previous instruction was a 4-byte one anyhow. */
3810 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3813 /* If the branch is itself the target of a branch, we can not swap.
3814 We cheat on this; all we check for is whether there is a label on
3815 this instruction. If there are any branches to anything other than
3816 a label, users must use .set noreorder. */
3817 if (seg_info (now_seg
)->label_list
)
3820 /* If the previous instruction is in a variant frag other than this
3821 branch's one, we cannot do the swap. This does not apply to
3822 MIPS16 code, which uses variant frags for different purposes. */
3823 if (!mips_opts
.mips16
3825 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3828 /* We do not swap with instructions that cannot architecturally
3829 be placed in a branch delay slot, such as SYNC or ERET. We
3830 also refrain from swapping with a trap instruction, since it
3831 complicates trap handlers to have the trap instruction be in
3833 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3834 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3837 /* Check for conflicts between the branch and the instructions
3838 before the candidate delay slot. */
3839 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3842 /* Check for conflicts between the swapped sequence and the
3843 target of the branch. */
3844 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3847 /* If the branch reads a register that the previous
3848 instruction sets, we can not swap. */
3849 gpr_read
= gpr_read_mask (ip
);
3850 prev_gpr_write
= gpr_write_mask (&history
[0]);
3851 if (gpr_read
& prev_gpr_write
)
3854 /* If the branch writes a register that the previous
3855 instruction sets, we can not swap. */
3856 gpr_write
= gpr_write_mask (ip
);
3857 if (gpr_write
& prev_gpr_write
)
3860 /* If the branch writes a register that the previous
3861 instruction reads, we can not swap. */
3862 prev_gpr_read
= gpr_read_mask (&history
[0]);
3863 if (gpr_write
& prev_gpr_read
)
3866 /* If one instruction sets a condition code and the
3867 other one uses a condition code, we can not swap. */
3868 pinfo
= ip
->insn_mo
->pinfo
;
3869 if ((pinfo
& INSN_READ_COND_CODE
)
3870 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3872 if ((pinfo
& INSN_WRITE_COND_CODE
)
3873 && (prev_pinfo
& INSN_READ_COND_CODE
))
3876 /* If the previous instruction uses the PC, we can not swap. */
3877 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3878 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3880 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3883 /* If the previous instruction has an incorrect size for a fixed
3884 branch delay slot in microMIPS mode, we cannot swap. */
3885 pinfo2
= ip
->insn_mo
->pinfo2
;
3886 if (mips_opts
.micromips
3887 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3888 && insn_length (history
) != 2)
3890 if (mips_opts
.micromips
3891 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3892 && insn_length (history
) != 4)
3895 /* On R5900 short loops need to be fixed by inserting a nop in
3896 the branch delay slots.
3897 A short loop can be terminated too early. */
3898 if (mips_opts
.arch
== CPU_R5900
3899 /* Check if instruction has a parameter, ignore "j $31". */
3900 && (address_expr
!= NULL
)
3901 /* Parameter must be 16 bit. */
3902 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
3903 /* Branch to same segment. */
3904 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
3905 /* Branch to same code fragment. */
3906 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
3907 /* Can only calculate branch offset if value is known. */
3908 && symbol_constant_p(address_expr
->X_add_symbol
)
3909 /* Check if branch is really conditional. */
3910 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
3911 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
3912 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
3915 /* Check if loop is shorter than 6 instructions including
3916 branch and delay slot. */
3917 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
3924 /* When the loop includes branches or jumps,
3925 it is not a short loop. */
3926 for (i
= 0; i
< (distance
/ 4); i
++)
3928 if ((history
[i
].cleared_p
)
3929 || delayed_branch_p(&history
[i
]))
3937 /* Insert nop after branch to fix short loop. */
3946 /* Decide how we should add IP to the instruction stream.
3947 ADDRESS_EXPR is an operand of the instruction to be used with
3950 static enum append_method
3951 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3952 bfd_reloc_code_real_type
*reloc_type
)
3954 unsigned long pinfo
;
3956 /* The relaxed version of a macro sequence must be inherently
3958 if (mips_relax
.sequence
== 2)
3961 /* We must not dabble with instructions in a ".set norerorder" block. */
3962 if (mips_opts
.noreorder
)
3965 /* Otherwise, it's our responsibility to fill branch delay slots. */
3966 if (delayed_branch_p (ip
))
3968 if (!branch_likely_p (ip
)
3969 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
3972 pinfo
= ip
->insn_mo
->pinfo
;
3973 if (mips_opts
.mips16
3974 && ISA_SUPPORTS_MIPS16E
3975 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
3976 return APPEND_ADD_COMPACT
;
3978 return APPEND_ADD_WITH_NOP
;
3984 /* IP is a MIPS16 instruction whose opcode we have just changed.
3985 Point IP->insn_mo to the new opcode's definition. */
3988 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
3990 const struct mips_opcode
*mo
, *end
;
3992 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
3993 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
3994 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
4002 /* For microMIPS macros, we need to generate a local number label
4003 as the target of branches. */
4004 #define MICROMIPS_LABEL_CHAR '\037'
4005 static unsigned long micromips_target_label
;
4006 static char micromips_target_name
[32];
4009 micromips_label_name (void)
4011 char *p
= micromips_target_name
;
4012 char symbol_name_temporary
[24];
4020 l
= micromips_target_label
;
4021 #ifdef LOCAL_LABEL_PREFIX
4022 *p
++ = LOCAL_LABEL_PREFIX
;
4025 *p
++ = MICROMIPS_LABEL_CHAR
;
4028 symbol_name_temporary
[i
++] = l
% 10 + '0';
4033 *p
++ = symbol_name_temporary
[--i
];
4036 return micromips_target_name
;
4040 micromips_label_expr (expressionS
*label_expr
)
4042 label_expr
->X_op
= O_symbol
;
4043 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
4044 label_expr
->X_add_number
= 0;
4048 micromips_label_inc (void)
4050 micromips_target_label
++;
4051 *micromips_target_name
= '\0';
4055 micromips_add_label (void)
4059 s
= colon (micromips_label_name ());
4060 micromips_label_inc ();
4061 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4063 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
4069 /* If assembling microMIPS code, then return the microMIPS reloc
4070 corresponding to the requested one if any. Otherwise return
4071 the reloc unchanged. */
4073 static bfd_reloc_code_real_type
4074 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
4076 static const bfd_reloc_code_real_type relocs
[][2] =
4078 /* Keep sorted incrementally by the left-hand key. */
4079 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
4080 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
4081 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
4082 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
4083 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
4084 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
4085 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
4086 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
4087 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
4088 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
4089 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
4090 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
4091 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
4092 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
4093 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
4094 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
4095 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
4096 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
4097 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4098 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4099 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4100 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4101 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4102 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4103 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4104 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4105 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4107 bfd_reloc_code_real_type r
;
4110 if (!mips_opts
.micromips
)
4112 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4118 return relocs
[i
][1];
4123 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4124 Return true on success, storing the resolved value in RESULT. */
4127 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
4132 case BFD_RELOC_MIPS_HIGHEST
:
4133 case BFD_RELOC_MICROMIPS_HIGHEST
:
4134 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
4137 case BFD_RELOC_MIPS_HIGHER
:
4138 case BFD_RELOC_MICROMIPS_HIGHER
:
4139 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
4142 case BFD_RELOC_HI16_S
:
4143 case BFD_RELOC_MICROMIPS_HI16_S
:
4144 case BFD_RELOC_MIPS16_HI16_S
:
4145 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
4148 case BFD_RELOC_HI16
:
4149 case BFD_RELOC_MICROMIPS_HI16
:
4150 case BFD_RELOC_MIPS16_HI16
:
4151 *result
= (operand
>> 16) & 0xffff;
4154 case BFD_RELOC_LO16
:
4155 case BFD_RELOC_MICROMIPS_LO16
:
4156 case BFD_RELOC_MIPS16_LO16
:
4157 *result
= operand
& 0xffff;
4160 case BFD_RELOC_UNUSED
:
4169 /* Output an instruction. IP is the instruction information.
4170 ADDRESS_EXPR is an operand of the instruction to be used with
4171 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4172 a macro expansion. */
4175 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4176 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4178 unsigned long prev_pinfo2
, pinfo
;
4179 bfd_boolean relaxed_branch
= FALSE
;
4180 enum append_method method
;
4181 bfd_boolean relax32
;
4184 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4185 fix_loongson2f (ip
);
4187 file_ase_mips16
|= mips_opts
.mips16
;
4188 file_ase_micromips
|= mips_opts
.micromips
;
4190 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4191 pinfo
= ip
->insn_mo
->pinfo
;
4193 if (mips_opts
.micromips
4195 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4196 && micromips_insn_length (ip
->insn_mo
) != 2)
4197 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4198 && micromips_insn_length (ip
->insn_mo
) != 4)))
4199 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4200 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4202 if (address_expr
== NULL
)
4204 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
4205 && reloc_type
[1] == BFD_RELOC_UNUSED
4206 && reloc_type
[2] == BFD_RELOC_UNUSED
4207 && address_expr
->X_op
== O_constant
)
4209 switch (*reloc_type
)
4211 case BFD_RELOC_MIPS_JMP
:
4215 shift
= mips_opts
.micromips
? 1 : 2;
4216 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4217 as_bad (_("jump to misaligned address (0x%lx)"),
4218 (unsigned long) address_expr
->X_add_number
);
4219 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4225 case BFD_RELOC_MIPS16_JMP
:
4226 if ((address_expr
->X_add_number
& 3) != 0)
4227 as_bad (_("jump to misaligned address (0x%lx)"),
4228 (unsigned long) address_expr
->X_add_number
);
4230 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4231 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4232 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4236 case BFD_RELOC_16_PCREL_S2
:
4240 shift
= mips_opts
.micromips
? 1 : 2;
4241 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4242 as_bad (_("branch to misaligned address (0x%lx)"),
4243 (unsigned long) address_expr
->X_add_number
);
4244 if (!mips_relax_branch
)
4246 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4247 & ~((1 << (shift
+ 16)) - 1))
4248 as_bad (_("branch address range overflow (0x%lx)"),
4249 (unsigned long) address_expr
->X_add_number
);
4250 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4260 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
4263 ip
->insn_opcode
|= value
& 0xffff;
4271 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4273 /* There are a lot of optimizations we could do that we don't.
4274 In particular, we do not, in general, reorder instructions.
4275 If you use gcc with optimization, it will reorder
4276 instructions and generally do much more optimization then we
4277 do here; repeating all that work in the assembler would only
4278 benefit hand written assembly code, and does not seem worth
4280 int nops
= (mips_optimize
== 0
4281 ? nops_for_insn (0, history
, NULL
)
4282 : nops_for_insn_or_target (0, history
, ip
));
4286 unsigned long old_frag_offset
;
4289 old_frag
= frag_now
;
4290 old_frag_offset
= frag_now_fix ();
4292 for (i
= 0; i
< nops
; i
++)
4293 add_fixed_insn (NOP_INSN
);
4294 insert_into_history (0, nops
, NOP_INSN
);
4298 listing_prev_line ();
4299 /* We may be at the start of a variant frag. In case we
4300 are, make sure there is enough space for the frag
4301 after the frags created by listing_prev_line. The
4302 argument to frag_grow here must be at least as large
4303 as the argument to all other calls to frag_grow in
4304 this file. We don't have to worry about being in the
4305 middle of a variant frag, because the variants insert
4306 all needed nop instructions themselves. */
4310 mips_move_text_labels ();
4312 #ifndef NO_ECOFF_DEBUGGING
4313 if (ECOFF_DEBUGGING
)
4314 ecoff_fix_loc (old_frag
, old_frag_offset
);
4318 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4322 /* Work out how many nops in prev_nop_frag are needed by IP,
4323 ignoring hazards generated by the first prev_nop_frag_since
4325 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4326 gas_assert (nops
<= prev_nop_frag_holds
);
4328 /* Enforce NOPS as a minimum. */
4329 if (nops
> prev_nop_frag_required
)
4330 prev_nop_frag_required
= nops
;
4332 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4334 /* Settle for the current number of nops. Update the history
4335 accordingly (for the benefit of any future .set reorder code). */
4336 prev_nop_frag
= NULL
;
4337 insert_into_history (prev_nop_frag_since
,
4338 prev_nop_frag_holds
, NOP_INSN
);
4342 /* Allow this instruction to replace one of the nops that was
4343 tentatively added to prev_nop_frag. */
4344 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4345 prev_nop_frag_holds
--;
4346 prev_nop_frag_since
++;
4350 method
= get_append_method (ip
, address_expr
, reloc_type
);
4351 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4354 /* The value passed to dwarf2_emit_insn is the distance between
4355 the beginning of the current instruction and the address that
4356 should be recorded in the debug tables. This is normally the
4359 For MIPS16/microMIPS debug info we want to use ISA-encoded
4360 addresses, so we use -1 for an address higher by one than the
4363 If the instruction produced is a branch that we will swap with
4364 the preceding instruction, then we add the displacement by which
4365 the branch will be moved backwards. This is more appropriate
4366 and for MIPS16/microMIPS code also prevents a debugger from
4367 placing a breakpoint in the middle of the branch (and corrupting
4368 code if software breakpoints are used). */
4369 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION
? -1 : 0) + branch_disp
);
4372 relax32
= (mips_relax_branch
4373 /* Don't try branch relaxation within .set nomacro, or within
4374 .set noat if we use $at for PIC computations. If it turns
4375 out that the branch was out-of-range, we'll get an error. */
4376 && !mips_opts
.warn_about_macros
4377 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4378 /* Don't relax BPOSGE32/64 as they have no complementing
4380 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
)));
4382 if (!HAVE_CODE_COMPRESSION
4385 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4386 && delayed_branch_p (ip
))
4388 relaxed_branch
= TRUE
;
4389 add_relaxed_insn (ip
, (relaxed_branch_length
4391 uncond_branch_p (ip
) ? -1
4392 : branch_likely_p (ip
) ? 1
4396 uncond_branch_p (ip
),
4397 branch_likely_p (ip
),
4398 pinfo
& INSN_WRITE_GPR_31
,
4400 address_expr
->X_add_symbol
,
4401 address_expr
->X_add_number
);
4402 *reloc_type
= BFD_RELOC_UNUSED
;
4404 else if (mips_opts
.micromips
4406 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4407 || *reloc_type
> BFD_RELOC_UNUSED
)
4408 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4409 /* Don't try branch relaxation when users specify
4410 16-bit/32-bit instructions. */
4411 && !forced_insn_length
)
4413 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4414 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4415 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4416 int compact
= compact_branch_p (ip
);
4417 int al
= pinfo
& INSN_WRITE_GPR_31
;
4420 gas_assert (address_expr
!= NULL
);
4421 gas_assert (!mips_relax
.sequence
);
4423 relaxed_branch
= TRUE
;
4424 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4425 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4426 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4428 address_expr
->X_add_symbol
,
4429 address_expr
->X_add_number
);
4430 *reloc_type
= BFD_RELOC_UNUSED
;
4432 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4434 /* We need to set up a variant frag. */
4435 gas_assert (address_expr
!= NULL
);
4436 add_relaxed_insn (ip
, 4, 0,
4438 (*reloc_type
- BFD_RELOC_UNUSED
,
4439 forced_insn_length
== 2, forced_insn_length
== 4,
4440 delayed_branch_p (&history
[0]),
4441 history
[0].mips16_absolute_jump_p
),
4442 make_expr_symbol (address_expr
), 0);
4444 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4446 if (!delayed_branch_p (ip
))
4447 /* Make sure there is enough room to swap this instruction with
4448 a following jump instruction. */
4450 add_fixed_insn (ip
);
4454 if (mips_opts
.mips16
4455 && mips_opts
.noreorder
4456 && delayed_branch_p (&history
[0]))
4457 as_warn (_("extended instruction in delay slot"));
4459 if (mips_relax
.sequence
)
4461 /* If we've reached the end of this frag, turn it into a variant
4462 frag and record the information for the instructions we've
4464 if (frag_room () < 4)
4465 relax_close_frag ();
4466 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4469 if (mips_relax
.sequence
!= 2)
4471 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4472 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4473 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4474 mips_macro_warning
.insns
[0]++;
4476 if (mips_relax
.sequence
!= 1)
4478 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4479 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4480 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4481 mips_macro_warning
.insns
[1]++;
4484 if (mips_opts
.mips16
)
4487 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4489 add_fixed_insn (ip
);
4492 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4494 bfd_reloc_code_real_type final_type
[3];
4495 reloc_howto_type
*howto0
;
4496 reloc_howto_type
*howto
;
4499 /* Perform any necessary conversion to microMIPS relocations
4500 and find out how many relocations there actually are. */
4501 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4502 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4504 /* In a compound relocation, it is the final (outermost)
4505 operator that determines the relocated field. */
4506 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4510 /* To reproduce this failure try assembling gas/testsuites/
4511 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4513 as_bad (_("Unsupported MIPS relocation number %d"),
4515 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4519 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4520 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4521 bfd_get_reloc_size (howto
),
4523 howto0
&& howto0
->pc_relative
,
4526 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4527 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4528 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4530 /* These relocations can have an addend that won't fit in
4531 4 octets for 64bit assembly. */
4533 && ! howto
->partial_inplace
4534 && (reloc_type
[0] == BFD_RELOC_16
4535 || reloc_type
[0] == BFD_RELOC_32
4536 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4537 || reloc_type
[0] == BFD_RELOC_GPREL16
4538 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4539 || reloc_type
[0] == BFD_RELOC_GPREL32
4540 || reloc_type
[0] == BFD_RELOC_64
4541 || reloc_type
[0] == BFD_RELOC_CTOR
4542 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4543 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4544 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4545 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4546 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4547 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4548 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4549 || hi16_reloc_p (reloc_type
[0])
4550 || lo16_reloc_p (reloc_type
[0])))
4551 ip
->fixp
[0]->fx_no_overflow
= 1;
4553 /* These relocations can have an addend that won't fit in 2 octets. */
4554 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4555 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
4556 ip
->fixp
[0]->fx_no_overflow
= 1;
4558 if (mips_relax
.sequence
)
4560 if (mips_relax
.first_fixup
== 0)
4561 mips_relax
.first_fixup
= ip
->fixp
[0];
4563 else if (reloc_needs_lo_p (*reloc_type
))
4565 struct mips_hi_fixup
*hi_fixup
;
4567 /* Reuse the last entry if it already has a matching %lo. */
4568 hi_fixup
= mips_hi_fixup_list
;
4570 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4572 hi_fixup
= ((struct mips_hi_fixup
*)
4573 xmalloc (sizeof (struct mips_hi_fixup
)));
4574 hi_fixup
->next
= mips_hi_fixup_list
;
4575 mips_hi_fixup_list
= hi_fixup
;
4577 hi_fixup
->fixp
= ip
->fixp
[0];
4578 hi_fixup
->seg
= now_seg
;
4581 /* Add fixups for the second and third relocations, if given.
4582 Note that the ABI allows the second relocation to be
4583 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4584 moment we only use RSS_UNDEF, but we could add support
4585 for the others if it ever becomes necessary. */
4586 for (i
= 1; i
< 3; i
++)
4587 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4589 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4590 ip
->fixp
[0]->fx_size
, NULL
, 0,
4591 FALSE
, final_type
[i
]);
4593 /* Use fx_tcbit to mark compound relocs. */
4594 ip
->fixp
[0]->fx_tcbit
= 1;
4595 ip
->fixp
[i
]->fx_tcbit
= 1;
4600 /* Update the register mask information. */
4601 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4602 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4607 insert_into_history (0, 1, ip
);
4610 case APPEND_ADD_WITH_NOP
:
4612 struct mips_cl_insn
*nop
;
4614 insert_into_history (0, 1, ip
);
4615 nop
= get_delay_slot_nop (ip
);
4616 add_fixed_insn (nop
);
4617 insert_into_history (0, 1, nop
);
4618 if (mips_relax
.sequence
)
4619 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4623 case APPEND_ADD_COMPACT
:
4624 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4625 gas_assert (mips_opts
.mips16
);
4626 ip
->insn_opcode
|= 0x0080;
4627 find_altered_mips16_opcode (ip
);
4629 insert_into_history (0, 1, ip
);
4634 struct mips_cl_insn delay
= history
[0];
4635 if (mips_opts
.mips16
)
4637 know (delay
.frag
== ip
->frag
);
4638 move_insn (ip
, delay
.frag
, delay
.where
);
4639 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4641 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4643 /* Add the delay slot instruction to the end of the
4644 current frag and shrink the fixed part of the
4645 original frag. If the branch occupies the tail of
4646 the latter, move it backwards to cover the gap. */
4647 delay
.frag
->fr_fix
-= branch_disp
;
4648 if (delay
.frag
== ip
->frag
)
4649 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4650 add_fixed_insn (&delay
);
4654 move_insn (&delay
, ip
->frag
,
4655 ip
->where
- branch_disp
+ insn_length (ip
));
4656 move_insn (ip
, history
[0].frag
, history
[0].where
);
4660 insert_into_history (0, 1, &delay
);
4665 /* If we have just completed an unconditional branch, clear the history. */
4666 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4667 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4671 mips_no_prev_insn ();
4673 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4674 history
[i
].cleared_p
= 1;
4677 /* We need to emit a label at the end of branch-likely macros. */
4678 if (emit_branch_likely_macro
)
4680 emit_branch_likely_macro
= FALSE
;
4681 micromips_add_label ();
4684 /* We just output an insn, so the next one doesn't have a label. */
4685 mips_clear_insn_labels ();
4688 /* Forget that there was any previous instruction or label.
4689 When BRANCH is true, the branch history is also flushed. */
4692 mips_no_prev_insn (void)
4694 prev_nop_frag
= NULL
;
4695 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4696 mips_clear_insn_labels ();
4699 /* This function must be called before we emit something other than
4700 instructions. It is like mips_no_prev_insn except that it inserts
4701 any NOPS that might be needed by previous instructions. */
4704 mips_emit_delays (void)
4706 if (! mips_opts
.noreorder
)
4708 int nops
= nops_for_insn (0, history
, NULL
);
4712 add_fixed_insn (NOP_INSN
);
4713 mips_move_text_labels ();
4716 mips_no_prev_insn ();
4719 /* Start a (possibly nested) noreorder block. */
4722 start_noreorder (void)
4724 if (mips_opts
.noreorder
== 0)
4729 /* None of the instructions before the .set noreorder can be moved. */
4730 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4731 history
[i
].fixed_p
= 1;
4733 /* Insert any nops that might be needed between the .set noreorder
4734 block and the previous instructions. We will later remove any
4735 nops that turn out not to be needed. */
4736 nops
= nops_for_insn (0, history
, NULL
);
4739 if (mips_optimize
!= 0)
4741 /* Record the frag which holds the nop instructions, so
4742 that we can remove them if we don't need them. */
4743 frag_grow (nops
* NOP_INSN_SIZE
);
4744 prev_nop_frag
= frag_now
;
4745 prev_nop_frag_holds
= nops
;
4746 prev_nop_frag_required
= 0;
4747 prev_nop_frag_since
= 0;
4750 for (; nops
> 0; --nops
)
4751 add_fixed_insn (NOP_INSN
);
4753 /* Move on to a new frag, so that it is safe to simply
4754 decrease the size of prev_nop_frag. */
4755 frag_wane (frag_now
);
4757 mips_move_text_labels ();
4759 mips_mark_labels ();
4760 mips_clear_insn_labels ();
4762 mips_opts
.noreorder
++;
4763 mips_any_noreorder
= 1;
4766 /* End a nested noreorder block. */
4769 end_noreorder (void)
4771 mips_opts
.noreorder
--;
4772 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4774 /* Commit to inserting prev_nop_frag_required nops and go back to
4775 handling nop insertion the .set reorder way. */
4776 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4778 insert_into_history (prev_nop_frag_since
,
4779 prev_nop_frag_required
, NOP_INSN
);
4780 prev_nop_frag
= NULL
;
4784 /* Set up global variables for the start of a new macro. */
4789 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4790 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4791 sizeof (mips_macro_warning
.first_insn_sizes
));
4792 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4793 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4794 && delayed_branch_p (&history
[0]));
4795 switch (history
[0].insn_mo
->pinfo2
4796 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4798 case INSN2_BRANCH_DELAY_32BIT
:
4799 mips_macro_warning
.delay_slot_length
= 4;
4801 case INSN2_BRANCH_DELAY_16BIT
:
4802 mips_macro_warning
.delay_slot_length
= 2;
4805 mips_macro_warning
.delay_slot_length
= 0;
4808 mips_macro_warning
.first_frag
= NULL
;
4811 /* Given that a macro is longer than one instruction or of the wrong size,
4812 return the appropriate warning for it. Return null if no warning is
4813 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4814 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4815 and RELAX_NOMACRO. */
4818 macro_warning (relax_substateT subtype
)
4820 if (subtype
& RELAX_DELAY_SLOT
)
4821 return _("Macro instruction expanded into multiple instructions"
4822 " in a branch delay slot");
4823 else if (subtype
& RELAX_NOMACRO
)
4824 return _("Macro instruction expanded into multiple instructions");
4825 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4826 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4827 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4828 ? _("Macro instruction expanded into a wrong size instruction"
4829 " in a 16-bit branch delay slot")
4830 : _("Macro instruction expanded into a wrong size instruction"
4831 " in a 32-bit branch delay slot"));
4836 /* Finish up a macro. Emit warnings as appropriate. */
4841 /* Relaxation warning flags. */
4842 relax_substateT subtype
= 0;
4844 /* Check delay slot size requirements. */
4845 if (mips_macro_warning
.delay_slot_length
== 2)
4846 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4847 if (mips_macro_warning
.delay_slot_length
!= 0)
4849 if (mips_macro_warning
.delay_slot_length
4850 != mips_macro_warning
.first_insn_sizes
[0])
4851 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4852 if (mips_macro_warning
.delay_slot_length
4853 != mips_macro_warning
.first_insn_sizes
[1])
4854 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4857 /* Check instruction count requirements. */
4858 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4860 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4861 subtype
|= RELAX_SECOND_LONGER
;
4862 if (mips_opts
.warn_about_macros
)
4863 subtype
|= RELAX_NOMACRO
;
4864 if (mips_macro_warning
.delay_slot_p
)
4865 subtype
|= RELAX_DELAY_SLOT
;
4868 /* If both alternatives fail to fill a delay slot correctly,
4869 emit the warning now. */
4870 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4871 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4876 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4877 | RELAX_DELAY_SLOT_SIZE_FIRST
4878 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4879 msg
= macro_warning (s
);
4881 as_warn ("%s", msg
);
4885 /* If both implementations are longer than 1 instruction, then emit the
4887 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4892 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4893 msg
= macro_warning (s
);
4895 as_warn ("%s", msg
);
4899 /* If any flags still set, then one implementation might need a warning
4900 and the other either will need one of a different kind or none at all.
4901 Pass any remaining flags over to relaxation. */
4902 if (mips_macro_warning
.first_frag
!= NULL
)
4903 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4906 /* Instruction operand formats used in macros that vary between
4907 standard MIPS and microMIPS code. */
4909 static const char * const brk_fmt
[2] = { "c", "mF" };
4910 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4911 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4912 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4913 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4914 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4915 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4916 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4918 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4919 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4920 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4921 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4922 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4923 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4924 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4925 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4927 /* Read a macro's relocation codes from *ARGS and store them in *R.
4928 The first argument in *ARGS will be either the code for a single
4929 relocation or -1 followed by the three codes that make up a
4930 composite relocation. */
4933 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4937 next
= va_arg (*args
, int);
4939 r
[0] = (bfd_reloc_code_real_type
) next
;
4941 for (i
= 0; i
< 3; i
++)
4942 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4945 /* Build an instruction created by a macro expansion. This is passed
4946 a pointer to the count of instructions created so far, an
4947 expression, the name of the instruction to build, an operand format
4948 string, and corresponding arguments. */
4951 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4953 const struct mips_opcode
*mo
= NULL
;
4954 bfd_reloc_code_real_type r
[3];
4955 const struct mips_opcode
*amo
;
4956 struct hash_control
*hash
;
4957 struct mips_cl_insn insn
;
4960 va_start (args
, fmt
);
4962 if (mips_opts
.mips16
)
4964 mips16_macro_build (ep
, name
, fmt
, &args
);
4969 r
[0] = BFD_RELOC_UNUSED
;
4970 r
[1] = BFD_RELOC_UNUSED
;
4971 r
[2] = BFD_RELOC_UNUSED
;
4972 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
4973 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
4975 gas_assert (strcmp (name
, amo
->name
) == 0);
4979 /* Search until we get a match for NAME. It is assumed here that
4980 macros will never generate MDMX, MIPS-3D, or MT instructions.
4981 We try to match an instruction that fulfils the branch delay
4982 slot instruction length requirement (if any) of the previous
4983 instruction. While doing this we record the first instruction
4984 seen that matches all the other conditions and use it anyway
4985 if the requirement cannot be met; we will issue an appropriate
4986 warning later on. */
4987 if (strcmp (fmt
, amo
->args
) == 0
4988 && amo
->pinfo
!= INSN_MACRO
4989 && is_opcode_valid (amo
)
4990 && is_size_valid (amo
))
4992 if (is_delay_slot_valid (amo
))
5002 gas_assert (amo
->name
);
5004 while (strcmp (name
, amo
->name
) == 0);
5007 create_insn (&insn
, mo
);
5025 INSERT_OPERAND (mips_opts
.micromips
,
5026 EXTLSB
, insn
, va_arg (args
, int));
5031 /* Note that in the macro case, these arguments are already
5032 in MSB form. (When handling the instruction in the
5033 non-macro case, these arguments are sizes from which
5034 MSB values must be calculated.) */
5035 INSERT_OPERAND (mips_opts
.micromips
,
5036 INSMSB
, insn
, va_arg (args
, int));
5042 /* Note that in the macro case, these arguments are already
5043 in MSBD form. (When handling the instruction in the
5044 non-macro case, these arguments are sizes from which
5045 MSBD values must be calculated.) */
5046 INSERT_OPERAND (mips_opts
.micromips
,
5047 EXTMSBD
, insn
, va_arg (args
, int));
5051 gas_assert (!mips_opts
.micromips
);
5052 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
5061 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
5065 gas_assert (mips_opts
.micromips
);
5069 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
5073 gas_assert (!mips_opts
.micromips
);
5074 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
5078 gas_assert (!mips_opts
.micromips
);
5080 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
5084 if (mips_opts
.micromips
)
5085 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
5087 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
5091 gas_assert (!mips_opts
.micromips
);
5093 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
5097 gas_assert (!mips_opts
.micromips
);
5099 int tmp
= va_arg (args
, int);
5101 INSERT_OPERAND (0, RT
, insn
, tmp
);
5102 INSERT_OPERAND (0, RD
, insn
, tmp
);
5108 gas_assert (!mips_opts
.micromips
);
5109 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
5116 INSERT_OPERAND (mips_opts
.micromips
,
5117 SHAMT
, insn
, va_arg (args
, int));
5121 gas_assert (!mips_opts
.micromips
);
5122 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
5126 gas_assert (!mips_opts
.micromips
);
5127 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
5131 gas_assert (!mips_opts
.micromips
);
5132 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5136 gas_assert (!mips_opts
.micromips
);
5137 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5144 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5149 macro_read_relocs (&args
, r
);
5150 gas_assert (*r
== BFD_RELOC_GPREL16
5151 || *r
== BFD_RELOC_MIPS_HIGHER
5152 || *r
== BFD_RELOC_HI16_S
5153 || *r
== BFD_RELOC_LO16
5154 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5158 macro_read_relocs (&args
, r
);
5162 macro_read_relocs (&args
, r
);
5163 gas_assert (ep
!= NULL
5164 && (ep
->X_op
== O_constant
5165 || (ep
->X_op
== O_symbol
5166 && (*r
== BFD_RELOC_MIPS_HIGHEST
5167 || *r
== BFD_RELOC_HI16_S
5168 || *r
== BFD_RELOC_HI16
5169 || *r
== BFD_RELOC_GPREL16
5170 || *r
== BFD_RELOC_MIPS_GOT_HI16
5171 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5175 gas_assert (ep
!= NULL
);
5178 * This allows macro() to pass an immediate expression for
5179 * creating short branches without creating a symbol.
5181 * We don't allow branch relaxation for these branches, as
5182 * they should only appear in ".set nomacro" anyway.
5184 if (ep
->X_op
== O_constant
)
5186 /* For microMIPS we always use relocations for branches.
5187 So we should not resolve immediate values. */
5188 gas_assert (!mips_opts
.micromips
);
5190 if ((ep
->X_add_number
& 3) != 0)
5191 as_bad (_("branch to misaligned address (0x%lx)"),
5192 (unsigned long) ep
->X_add_number
);
5193 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5194 as_bad (_("branch address range overflow (0x%lx)"),
5195 (unsigned long) ep
->X_add_number
);
5196 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5200 *r
= BFD_RELOC_16_PCREL_S2
;
5204 gas_assert (ep
!= NULL
);
5205 *r
= BFD_RELOC_MIPS_JMP
;
5209 gas_assert (!mips_opts
.micromips
);
5210 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5214 INSERT_OPERAND (mips_opts
.micromips
,
5215 CACHE
, insn
, va_arg (args
, unsigned long));
5219 gas_assert (mips_opts
.micromips
);
5220 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5224 gas_assert (mips_opts
.micromips
);
5225 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5229 INSERT_OPERAND (mips_opts
.micromips
,
5230 3BITPOS
, insn
, va_arg (args
, unsigned int));
5234 INSERT_OPERAND (mips_opts
.micromips
,
5235 OFFSET12
, insn
, va_arg (args
, unsigned long));
5239 gas_assert (mips_opts
.micromips
);
5240 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5243 case 'm': /* Opcode extension character. */
5244 gas_assert (mips_opts
.micromips
);
5248 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5252 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5256 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5270 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5272 append_insn (&insn
, ep
, r
, TRUE
);
5276 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5279 struct mips_opcode
*mo
;
5280 struct mips_cl_insn insn
;
5281 bfd_reloc_code_real_type r
[3]
5282 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5284 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5286 gas_assert (strcmp (name
, mo
->name
) == 0);
5288 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5291 gas_assert (mo
->name
);
5292 gas_assert (strcmp (name
, mo
->name
) == 0);
5295 create_insn (&insn
, mo
);
5313 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5318 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5322 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5326 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5336 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5343 regno
= va_arg (*args
, int);
5344 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5345 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5368 gas_assert (ep
!= NULL
);
5370 if (ep
->X_op
!= O_constant
)
5371 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5372 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
5374 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
5376 *r
= BFD_RELOC_UNUSED
;
5382 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5389 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5391 append_insn (&insn
, ep
, r
, TRUE
);
5395 * Sign-extend 32-bit mode constants that have bit 31 set and all
5396 * higher bits unset.
5399 normalize_constant_expr (expressionS
*ex
)
5401 if (ex
->X_op
== O_constant
5402 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5403 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5408 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5409 * all higher bits unset.
5412 normalize_address_expr (expressionS
*ex
)
5414 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5415 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5416 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5417 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5422 * Generate a "jalr" instruction with a relocation hint to the called
5423 * function. This occurs in NewABI PIC code.
5426 macro_build_jalr (expressionS
*ep
, int cprestore
)
5428 static const bfd_reloc_code_real_type jalr_relocs
[2]
5429 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5430 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5434 if (MIPS_JALR_HINT_P (ep
))
5439 if (mips_opts
.micromips
)
5441 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5442 if (MIPS_JALR_HINT_P (ep
)
5443 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5444 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5446 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5449 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5450 if (MIPS_JALR_HINT_P (ep
))
5451 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5455 * Generate a "lui" instruction.
5458 macro_build_lui (expressionS
*ep
, int regnum
)
5460 gas_assert (! mips_opts
.mips16
);
5462 if (ep
->X_op
!= O_constant
)
5464 gas_assert (ep
->X_op
== O_symbol
);
5465 /* _gp_disp is a special case, used from s_cpload.
5466 __gnu_local_gp is used if mips_no_shared. */
5467 gas_assert (mips_pic
== NO_PIC
5469 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5470 || (! mips_in_shared
5471 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5472 "__gnu_local_gp") == 0));
5475 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5478 /* Generate a sequence of instructions to do a load or store from a constant
5479 offset off of a base register (breg) into/from a target register (treg),
5480 using AT if necessary. */
5482 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5483 int treg
, int breg
, int dbl
)
5485 gas_assert (ep
->X_op
== O_constant
);
5487 /* Sign-extending 32-bit constants makes their handling easier. */
5489 normalize_constant_expr (ep
);
5491 /* Right now, this routine can only handle signed 32-bit constants. */
5492 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5493 as_warn (_("operand overflow"));
5495 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5497 /* Signed 16-bit offset will fit in the op. Easy! */
5498 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5502 /* 32-bit offset, need multiple instructions and AT, like:
5503 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5504 addu $tempreg,$tempreg,$breg
5505 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5506 to handle the complete offset. */
5507 macro_build_lui (ep
, AT
);
5508 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5509 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5512 as_bad (_("Macro used $at after \".set noat\""));
5517 * Generates code to set the $at register to true (one)
5518 * if reg is less than the immediate expression.
5521 set_at (int reg
, int unsignedp
)
5523 if (imm_expr
.X_op
== O_constant
5524 && imm_expr
.X_add_number
>= -0x8000
5525 && imm_expr
.X_add_number
< 0x8000)
5526 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5527 AT
, reg
, BFD_RELOC_LO16
);
5530 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5531 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5535 /* Warn if an expression is not a constant. */
5538 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5540 if (ex
->X_op
== O_big
)
5541 as_bad (_("unsupported large constant"));
5542 else if (ex
->X_op
!= O_constant
)
5543 as_bad (_("Instruction %s requires absolute expression"),
5546 if (HAVE_32BIT_GPRS
)
5547 normalize_constant_expr (ex
);
5550 /* Count the leading zeroes by performing a binary chop. This is a
5551 bulky bit of source, but performance is a LOT better for the
5552 majority of values than a simple loop to count the bits:
5553 for (lcnt = 0; (lcnt < 32); lcnt++)
5554 if ((v) & (1 << (31 - lcnt)))
5556 However it is not code size friendly, and the gain will drop a bit
5557 on certain cached systems.
5559 #define COUNT_TOP_ZEROES(v) \
5560 (((v) & ~0xffff) == 0 \
5561 ? ((v) & ~0xff) == 0 \
5562 ? ((v) & ~0xf) == 0 \
5563 ? ((v) & ~0x3) == 0 \
5564 ? ((v) & ~0x1) == 0 \
5569 : ((v) & ~0x7) == 0 \
5572 : ((v) & ~0x3f) == 0 \
5573 ? ((v) & ~0x1f) == 0 \
5576 : ((v) & ~0x7f) == 0 \
5579 : ((v) & ~0xfff) == 0 \
5580 ? ((v) & ~0x3ff) == 0 \
5581 ? ((v) & ~0x1ff) == 0 \
5584 : ((v) & ~0x7ff) == 0 \
5587 : ((v) & ~0x3fff) == 0 \
5588 ? ((v) & ~0x1fff) == 0 \
5591 : ((v) & ~0x7fff) == 0 \
5594 : ((v) & ~0xffffff) == 0 \
5595 ? ((v) & ~0xfffff) == 0 \
5596 ? ((v) & ~0x3ffff) == 0 \
5597 ? ((v) & ~0x1ffff) == 0 \
5600 : ((v) & ~0x7ffff) == 0 \
5603 : ((v) & ~0x3fffff) == 0 \
5604 ? ((v) & ~0x1fffff) == 0 \
5607 : ((v) & ~0x7fffff) == 0 \
5610 : ((v) & ~0xfffffff) == 0 \
5611 ? ((v) & ~0x3ffffff) == 0 \
5612 ? ((v) & ~0x1ffffff) == 0 \
5615 : ((v) & ~0x7ffffff) == 0 \
5618 : ((v) & ~0x3fffffff) == 0 \
5619 ? ((v) & ~0x1fffffff) == 0 \
5622 : ((v) & ~0x7fffffff) == 0 \
5627 * This routine generates the least number of instructions necessary to load
5628 * an absolute expression value into a register.
5631 load_register (int reg
, expressionS
*ep
, int dbl
)
5634 expressionS hi32
, lo32
;
5636 if (ep
->X_op
!= O_big
)
5638 gas_assert (ep
->X_op
== O_constant
);
5640 /* Sign-extending 32-bit constants makes their handling easier. */
5642 normalize_constant_expr (ep
);
5644 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5646 /* We can handle 16 bit signed values with an addiu to
5647 $zero. No need to ever use daddiu here, since $zero and
5648 the result are always correct in 32 bit mode. */
5649 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5652 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5654 /* We can handle 16 bit unsigned values with an ori to
5656 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5659 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5661 /* 32 bit values require an lui. */
5662 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5663 if ((ep
->X_add_number
& 0xffff) != 0)
5664 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5669 /* The value is larger than 32 bits. */
5671 if (!dbl
|| HAVE_32BIT_GPRS
)
5675 sprintf_vma (value
, ep
->X_add_number
);
5676 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5677 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5681 if (ep
->X_op
!= O_big
)
5684 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5685 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5686 hi32
.X_add_number
&= 0xffffffff;
5688 lo32
.X_add_number
&= 0xffffffff;
5692 gas_assert (ep
->X_add_number
> 2);
5693 if (ep
->X_add_number
== 3)
5694 generic_bignum
[3] = 0;
5695 else if (ep
->X_add_number
> 4)
5696 as_bad (_("Number larger than 64 bits"));
5697 lo32
.X_op
= O_constant
;
5698 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5699 hi32
.X_op
= O_constant
;
5700 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5703 if (hi32
.X_add_number
== 0)
5708 unsigned long hi
, lo
;
5710 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5712 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5714 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5717 if (lo32
.X_add_number
& 0x80000000)
5719 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5720 if (lo32
.X_add_number
& 0xffff)
5721 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5726 /* Check for 16bit shifted constant. We know that hi32 is
5727 non-zero, so start the mask on the first bit of the hi32
5732 unsigned long himask
, lomask
;
5736 himask
= 0xffff >> (32 - shift
);
5737 lomask
= (0xffff << shift
) & 0xffffffff;
5741 himask
= 0xffff << (shift
- 32);
5744 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5745 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5749 tmp
.X_op
= O_constant
;
5751 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5752 | (lo32
.X_add_number
>> shift
));
5754 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5755 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5756 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5757 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5762 while (shift
<= (64 - 16));
5764 /* Find the bit number of the lowest one bit, and store the
5765 shifted value in hi/lo. */
5766 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5767 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5771 while ((lo
& 1) == 0)
5776 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5782 while ((hi
& 1) == 0)
5791 /* Optimize if the shifted value is a (power of 2) - 1. */
5792 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5793 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5795 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5800 /* This instruction will set the register to be all
5802 tmp
.X_op
= O_constant
;
5803 tmp
.X_add_number
= (offsetT
) -1;
5804 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5808 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5809 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5811 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5812 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5817 /* Sign extend hi32 before calling load_register, because we can
5818 generally get better code when we load a sign extended value. */
5819 if ((hi32
.X_add_number
& 0x80000000) != 0)
5820 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5821 load_register (reg
, &hi32
, 0);
5824 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5828 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5836 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5838 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5839 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5845 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5849 mid16
.X_add_number
>>= 16;
5850 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5851 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5854 if ((lo32
.X_add_number
& 0xffff) != 0)
5855 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5859 load_delay_nop (void)
5861 if (!gpr_interlocks
)
5862 macro_build (NULL
, "nop", "");
5865 /* Load an address into a register. */
5868 load_address (int reg
, expressionS
*ep
, int *used_at
)
5870 if (ep
->X_op
!= O_constant
5871 && ep
->X_op
!= O_symbol
)
5873 as_bad (_("expression too complex"));
5874 ep
->X_op
= O_constant
;
5877 if (ep
->X_op
== O_constant
)
5879 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5883 if (mips_pic
== NO_PIC
)
5885 /* If this is a reference to a GP relative symbol, we want
5886 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5888 lui $reg,<sym> (BFD_RELOC_HI16_S)
5889 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5890 If we have an addend, we always use the latter form.
5892 With 64bit address space and a usable $at we want
5893 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5894 lui $at,<sym> (BFD_RELOC_HI16_S)
5895 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5896 daddiu $at,<sym> (BFD_RELOC_LO16)
5900 If $at is already in use, we use a path which is suboptimal
5901 on superscalar processors.
5902 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5903 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5905 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5907 daddiu $reg,<sym> (BFD_RELOC_LO16)
5909 For GP relative symbols in 64bit address space we can use
5910 the same sequence as in 32bit address space. */
5911 if (HAVE_64BIT_SYMBOLS
)
5913 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5914 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5916 relax_start (ep
->X_add_symbol
);
5917 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5918 mips_gp_register
, BFD_RELOC_GPREL16
);
5922 if (*used_at
== 0 && mips_opts
.at
)
5924 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5925 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5926 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5927 BFD_RELOC_MIPS_HIGHER
);
5928 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5929 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5930 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5935 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5936 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5937 BFD_RELOC_MIPS_HIGHER
);
5938 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5939 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5940 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5941 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5944 if (mips_relax
.sequence
)
5949 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5950 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5952 relax_start (ep
->X_add_symbol
);
5953 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5954 mips_gp_register
, BFD_RELOC_GPREL16
);
5957 macro_build_lui (ep
, reg
);
5958 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
5959 reg
, reg
, BFD_RELOC_LO16
);
5960 if (mips_relax
.sequence
)
5964 else if (!mips_big_got
)
5968 /* If this is a reference to an external symbol, we want
5969 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5971 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5973 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5974 If there is a constant, it must be added in after.
5976 If we have NewABI, we want
5977 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5978 unless we're referencing a global symbol with a non-zero
5979 offset, in which case cst must be added separately. */
5982 if (ep
->X_add_number
)
5984 ex
.X_add_number
= ep
->X_add_number
;
5985 ep
->X_add_number
= 0;
5986 relax_start (ep
->X_add_symbol
);
5987 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5988 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5989 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5990 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5991 ex
.X_op
= O_constant
;
5992 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5993 reg
, reg
, BFD_RELOC_LO16
);
5994 ep
->X_add_number
= ex
.X_add_number
;
5997 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5998 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5999 if (mips_relax
.sequence
)
6004 ex
.X_add_number
= ep
->X_add_number
;
6005 ep
->X_add_number
= 0;
6006 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6007 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6009 relax_start (ep
->X_add_symbol
);
6011 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6015 if (ex
.X_add_number
!= 0)
6017 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6018 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6019 ex
.X_op
= O_constant
;
6020 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6021 reg
, reg
, BFD_RELOC_LO16
);
6025 else if (mips_big_got
)
6029 /* This is the large GOT case. If this is a reference to an
6030 external symbol, we want
6031 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6033 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6035 Otherwise, for a reference to a local symbol in old ABI, we want
6036 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6038 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6039 If there is a constant, it must be added in after.
6041 In the NewABI, for local symbols, with or without offsets, we want:
6042 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6043 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6047 ex
.X_add_number
= ep
->X_add_number
;
6048 ep
->X_add_number
= 0;
6049 relax_start (ep
->X_add_symbol
);
6050 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6051 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6052 reg
, reg
, mips_gp_register
);
6053 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6054 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6055 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6056 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6057 else if (ex
.X_add_number
)
6059 ex
.X_op
= O_constant
;
6060 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6064 ep
->X_add_number
= ex
.X_add_number
;
6066 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6067 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6068 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6069 BFD_RELOC_MIPS_GOT_OFST
);
6074 ex
.X_add_number
= ep
->X_add_number
;
6075 ep
->X_add_number
= 0;
6076 relax_start (ep
->X_add_symbol
);
6077 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6078 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6079 reg
, reg
, mips_gp_register
);
6080 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6081 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6083 if (reg_needs_delay (mips_gp_register
))
6085 /* We need a nop before loading from $gp. This special
6086 check is required because the lui which starts the main
6087 instruction stream does not refer to $gp, and so will not
6088 insert the nop which may be required. */
6089 macro_build (NULL
, "nop", "");
6091 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6092 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6094 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6098 if (ex
.X_add_number
!= 0)
6100 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6101 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6102 ex
.X_op
= O_constant
;
6103 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6111 if (!mips_opts
.at
&& *used_at
== 1)
6112 as_bad (_("Macro used $at after \".set noat\""));
6115 /* Move the contents of register SOURCE into register DEST. */
6118 move_register (int dest
, int source
)
6120 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6121 instruction specifically requires a 32-bit one. */
6122 if (mips_opts
.micromips
6123 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6124 macro_build (NULL
, "move", "mp,mj", dest
, source
);
6126 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
6130 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6131 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6132 The two alternatives are:
6134 Global symbol Local sybmol
6135 ------------- ------------
6136 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6138 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6140 load_got_offset emits the first instruction and add_got_offset
6141 emits the second for a 16-bit offset or add_got_offset_hilo emits
6142 a sequence to add a 32-bit offset using a scratch register. */
6145 load_got_offset (int dest
, expressionS
*local
)
6150 global
.X_add_number
= 0;
6152 relax_start (local
->X_add_symbol
);
6153 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6154 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6156 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6157 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6162 add_got_offset (int dest
, expressionS
*local
)
6166 global
.X_op
= O_constant
;
6167 global
.X_op_symbol
= NULL
;
6168 global
.X_add_symbol
= NULL
;
6169 global
.X_add_number
= local
->X_add_number
;
6171 relax_start (local
->X_add_symbol
);
6172 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6173 dest
, dest
, BFD_RELOC_LO16
);
6175 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6180 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6183 int hold_mips_optimize
;
6185 global
.X_op
= O_constant
;
6186 global
.X_op_symbol
= NULL
;
6187 global
.X_add_symbol
= NULL
;
6188 global
.X_add_number
= local
->X_add_number
;
6190 relax_start (local
->X_add_symbol
);
6191 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6193 /* Set mips_optimize around the lui instruction to avoid
6194 inserting an unnecessary nop after the lw. */
6195 hold_mips_optimize
= mips_optimize
;
6197 macro_build_lui (&global
, tmp
);
6198 mips_optimize
= hold_mips_optimize
;
6199 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6202 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6205 /* Emit a sequence of instructions to emulate a branch likely operation.
6206 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6207 is its complementing branch with the original condition negated.
6208 CALL is set if the original branch specified the link operation.
6209 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6211 Code like this is produced in the noreorder mode:
6216 delay slot (executed only if branch taken)
6224 delay slot (executed only if branch taken)
6227 In the reorder mode the delay slot would be filled with a nop anyway,
6228 so code produced is simply:
6233 This function is used when producing code for the microMIPS ASE that
6234 does not implement branch likely instructions in hardware. */
6237 macro_build_branch_likely (const char *br
, const char *brneg
,
6238 int call
, expressionS
*ep
, const char *fmt
,
6239 unsigned int sreg
, unsigned int treg
)
6241 int noreorder
= mips_opts
.noreorder
;
6244 gas_assert (mips_opts
.micromips
);
6248 micromips_label_expr (&expr1
);
6249 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6250 macro_build (NULL
, "nop", "");
6251 macro_build (ep
, call
? "bal" : "b", "p");
6253 /* Set to true so that append_insn adds a label. */
6254 emit_branch_likely_macro
= TRUE
;
6258 macro_build (ep
, br
, fmt
, sreg
, treg
);
6259 macro_build (NULL
, "nop", "");
6264 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6265 the condition code tested. EP specifies the branch target. */
6268 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6295 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6298 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6299 the register tested. EP specifies the branch target. */
6302 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6304 const char *brneg
= NULL
;
6314 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6318 gas_assert (mips_opts
.micromips
);
6327 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6334 br
= mips_opts
.micromips
? "blez" : "blezl";
6341 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6345 gas_assert (mips_opts
.micromips
);
6353 if (mips_opts
.micromips
&& brneg
)
6354 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6356 macro_build (ep
, br
, "s,p", sreg
);
6359 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6360 TREG as the registers tested. EP specifies the branch target. */
6363 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6364 unsigned int sreg
, unsigned int treg
)
6366 const char *brneg
= NULL
;
6378 br
= mips_opts
.micromips
? "beq" : "beql";
6387 br
= mips_opts
.micromips
? "bne" : "bnel";
6393 if (mips_opts
.micromips
&& brneg
)
6394 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6396 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6401 * This routine implements the seemingly endless macro or synthesized
6402 * instructions and addressing modes in the mips assembly language. Many
6403 * of these macros are simple and are similar to each other. These could
6404 * probably be handled by some kind of table or grammar approach instead of
6405 * this verbose method. Others are not simple macros but are more like
6406 * optimizing code generation.
6407 * One interesting optimization is when several store macros appear
6408 * consecutively that would load AT with the upper half of the same address.
6409 * The ensuing load upper instructions are ommited. This implies some kind
6410 * of global optimization. We currently only optimize within a single macro.
6411 * For many of the load and store macros if the address is specified as a
6412 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6413 * first load register 'at' with zero and use it as the base register. The
6414 * mips assembler simply uses register $zero. Just one tiny optimization
6418 macro (struct mips_cl_insn
*ip
)
6420 unsigned int treg
, sreg
, dreg
, breg
;
6421 unsigned int tempreg
;
6424 expressionS label_expr
;
6443 bfd_reloc_code_real_type r
;
6444 int hold_mips_optimize
;
6446 gas_assert (! mips_opts
.mips16
);
6448 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6449 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6450 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6451 mask
= ip
->insn_mo
->mask
;
6453 label_expr
.X_op
= O_constant
;
6454 label_expr
.X_op_symbol
= NULL
;
6455 label_expr
.X_add_symbol
= NULL
;
6456 label_expr
.X_add_number
= 0;
6458 expr1
.X_op
= O_constant
;
6459 expr1
.X_op_symbol
= NULL
;
6460 expr1
.X_add_symbol
= NULL
;
6461 expr1
.X_add_number
= 1;
6476 if (mips_opts
.micromips
)
6477 micromips_label_expr (&label_expr
);
6479 label_expr
.X_add_number
= 8;
6480 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6482 macro_build (NULL
, "nop", "");
6484 move_register (dreg
, sreg
);
6485 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6486 if (mips_opts
.micromips
)
6487 micromips_add_label ();
6504 if (!mips_opts
.micromips
)
6506 if (imm_expr
.X_op
== O_constant
6507 && imm_expr
.X_add_number
>= -0x200
6508 && imm_expr
.X_add_number
< 0x200)
6510 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6519 if (imm_expr
.X_op
== O_constant
6520 && imm_expr
.X_add_number
>= -0x8000
6521 && imm_expr
.X_add_number
< 0x8000)
6523 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6528 load_register (AT
, &imm_expr
, dbl
);
6529 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6548 if (imm_expr
.X_op
== O_constant
6549 && imm_expr
.X_add_number
>= 0
6550 && imm_expr
.X_add_number
< 0x10000)
6552 if (mask
!= M_NOR_I
)
6553 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6556 macro_build (&imm_expr
, "ori", "t,r,i",
6557 treg
, sreg
, BFD_RELOC_LO16
);
6558 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6564 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6565 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6569 switch (imm_expr
.X_add_number
)
6572 macro_build (NULL
, "nop", "");
6575 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6579 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6580 (int) imm_expr
.X_add_number
);
6583 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6584 (unsigned long) imm_expr
.X_add_number
);
6593 gas_assert (mips_opts
.micromips
);
6594 macro_build_branch_ccl (mask
, &offset_expr
,
6595 EXTRACT_OPERAND (1, BCC
, *ip
));
6602 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6608 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6613 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6620 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6622 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6626 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6627 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6628 &offset_expr
, AT
, ZERO
);
6638 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6644 /* Check for > max integer. */
6645 maxnum
= 0x7fffffff;
6646 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6653 if (imm_expr
.X_op
== O_constant
6654 && imm_expr
.X_add_number
>= maxnum
6655 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6658 /* Result is always false. */
6660 macro_build (NULL
, "nop", "");
6662 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6665 if (imm_expr
.X_op
!= O_constant
)
6666 as_bad (_("Unsupported large constant"));
6667 ++imm_expr
.X_add_number
;
6671 if (mask
== M_BGEL_I
)
6673 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6675 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6676 &offset_expr
, sreg
);
6679 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6681 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6682 &offset_expr
, sreg
);
6685 maxnum
= 0x7fffffff;
6686 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6693 maxnum
= - maxnum
- 1;
6694 if (imm_expr
.X_op
== O_constant
6695 && imm_expr
.X_add_number
<= maxnum
6696 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6699 /* result is always true */
6700 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6701 macro_build (&offset_expr
, "b", "p");
6706 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6707 &offset_expr
, AT
, ZERO
);
6716 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6717 &offset_expr
, ZERO
, treg
);
6721 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6722 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6723 &offset_expr
, AT
, ZERO
);
6732 && imm_expr
.X_op
== O_constant
6733 && imm_expr
.X_add_number
== -1))
6735 if (imm_expr
.X_op
!= O_constant
)
6736 as_bad (_("Unsupported large constant"));
6737 ++imm_expr
.X_add_number
;
6741 if (mask
== M_BGEUL_I
)
6743 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6745 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6746 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6747 &offset_expr
, sreg
, ZERO
);
6752 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6753 &offset_expr
, AT
, ZERO
);
6761 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6763 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6767 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6768 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6769 &offset_expr
, AT
, ZERO
);
6777 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6778 &offset_expr
, sreg
, ZERO
);
6784 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6785 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6786 &offset_expr
, AT
, ZERO
);
6794 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6796 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6800 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6801 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6802 &offset_expr
, AT
, ZERO
);
6809 maxnum
= 0x7fffffff;
6810 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6817 if (imm_expr
.X_op
== O_constant
6818 && imm_expr
.X_add_number
>= maxnum
6819 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6821 if (imm_expr
.X_op
!= O_constant
)
6822 as_bad (_("Unsupported large constant"));
6823 ++imm_expr
.X_add_number
;
6827 if (mask
== M_BLTL_I
)
6829 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6830 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6831 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6832 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6837 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6838 &offset_expr
, AT
, ZERO
);
6846 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6847 &offset_expr
, sreg
, ZERO
);
6853 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6854 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6855 &offset_expr
, AT
, ZERO
);
6864 && imm_expr
.X_op
== O_constant
6865 && imm_expr
.X_add_number
== -1))
6867 if (imm_expr
.X_op
!= O_constant
)
6868 as_bad (_("Unsupported large constant"));
6869 ++imm_expr
.X_add_number
;
6873 if (mask
== M_BLTUL_I
)
6875 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6877 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6878 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6879 &offset_expr
, sreg
, ZERO
);
6884 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6885 &offset_expr
, AT
, ZERO
);
6893 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6895 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6899 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6900 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6901 &offset_expr
, AT
, ZERO
);
6911 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6912 &offset_expr
, ZERO
, treg
);
6916 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6917 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6918 &offset_expr
, AT
, ZERO
);
6924 /* Use unsigned arithmetic. */
6928 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6930 as_bad (_("Unsupported large constant"));
6935 pos
= imm_expr
.X_add_number
;
6936 size
= imm2_expr
.X_add_number
;
6941 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6944 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6946 as_bad (_("Improper extract size (%lu, position %lu)"),
6947 (unsigned long) size
, (unsigned long) pos
);
6951 if (size
<= 32 && pos
< 32)
6956 else if (size
<= 32)
6966 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6973 /* Use unsigned arithmetic. */
6977 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6979 as_bad (_("Unsupported large constant"));
6984 pos
= imm_expr
.X_add_number
;
6985 size
= imm2_expr
.X_add_number
;
6990 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6993 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6995 as_bad (_("Improper insert size (%lu, position %lu)"),
6996 (unsigned long) size
, (unsigned long) pos
);
7000 if (pos
< 32 && (pos
+ size
- 1) < 32)
7015 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7016 (int) (pos
+ size
- 1));
7032 as_warn (_("Divide by zero."));
7034 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7036 macro_build (NULL
, "break", BRK_FMT
, 7);
7043 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7044 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7048 if (mips_opts
.micromips
)
7049 micromips_label_expr (&label_expr
);
7051 label_expr
.X_add_number
= 8;
7052 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7053 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7054 macro_build (NULL
, "break", BRK_FMT
, 7);
7055 if (mips_opts
.micromips
)
7056 micromips_add_label ();
7058 expr1
.X_add_number
= -1;
7060 load_register (AT
, &expr1
, dbl
);
7061 if (mips_opts
.micromips
)
7062 micromips_label_expr (&label_expr
);
7064 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
7065 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
7068 expr1
.X_add_number
= 1;
7069 load_register (AT
, &expr1
, dbl
);
7070 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
7074 expr1
.X_add_number
= 0x80000000;
7075 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
7079 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
7080 /* We want to close the noreorder block as soon as possible, so
7081 that later insns are available for delay slot filling. */
7086 if (mips_opts
.micromips
)
7087 micromips_label_expr (&label_expr
);
7089 label_expr
.X_add_number
= 8;
7090 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
7091 macro_build (NULL
, "nop", "");
7093 /* We want to close the noreorder block as soon as possible, so
7094 that later insns are available for delay slot filling. */
7097 macro_build (NULL
, "break", BRK_FMT
, 6);
7099 if (mips_opts
.micromips
)
7100 micromips_add_label ();
7101 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7140 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7142 as_warn (_("Divide by zero."));
7144 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7146 macro_build (NULL
, "break", BRK_FMT
, 7);
7149 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7151 if (strcmp (s2
, "mflo") == 0)
7152 move_register (dreg
, sreg
);
7154 move_register (dreg
, ZERO
);
7157 if (imm_expr
.X_op
== O_constant
7158 && imm_expr
.X_add_number
== -1
7159 && s
[strlen (s
) - 1] != 'u')
7161 if (strcmp (s2
, "mflo") == 0)
7163 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7166 move_register (dreg
, ZERO
);
7171 load_register (AT
, &imm_expr
, dbl
);
7172 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7173 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7195 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7196 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7197 /* We want to close the noreorder block as soon as possible, so
7198 that later insns are available for delay slot filling. */
7203 if (mips_opts
.micromips
)
7204 micromips_label_expr (&label_expr
);
7206 label_expr
.X_add_number
= 8;
7207 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7208 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7210 /* We want to close the noreorder block as soon as possible, so
7211 that later insns are available for delay slot filling. */
7213 macro_build (NULL
, "break", BRK_FMT
, 7);
7214 if (mips_opts
.micromips
)
7215 micromips_add_label ();
7217 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7229 /* Load the address of a symbol into a register. If breg is not
7230 zero, we then add a base register to it. */
7232 if (dbl
&& HAVE_32BIT_GPRS
)
7233 as_warn (_("dla used to load 32-bit register"));
7235 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7236 as_warn (_("la used to load 64-bit address"));
7238 if (offset_expr
.X_op
== O_constant
7239 && offset_expr
.X_add_number
>= -0x8000
7240 && offset_expr
.X_add_number
< 0x8000)
7242 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7243 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7247 if (mips_opts
.at
&& (treg
== breg
))
7257 if (offset_expr
.X_op
!= O_symbol
7258 && offset_expr
.X_op
!= O_constant
)
7260 as_bad (_("Expression too complex"));
7261 offset_expr
.X_op
= O_constant
;
7264 if (offset_expr
.X_op
== O_constant
)
7265 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7266 else if (mips_pic
== NO_PIC
)
7268 /* If this is a reference to a GP relative symbol, we want
7269 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7271 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7272 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7273 If we have a constant, we need two instructions anyhow,
7274 so we may as well always use the latter form.
7276 With 64bit address space and a usable $at we want
7277 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7278 lui $at,<sym> (BFD_RELOC_HI16_S)
7279 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7280 daddiu $at,<sym> (BFD_RELOC_LO16)
7282 daddu $tempreg,$tempreg,$at
7284 If $at is already in use, we use a path which is suboptimal
7285 on superscalar processors.
7286 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7287 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7289 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7291 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7293 For GP relative symbols in 64bit address space we can use
7294 the same sequence as in 32bit address space. */
7295 if (HAVE_64BIT_SYMBOLS
)
7297 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7298 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7300 relax_start (offset_expr
.X_add_symbol
);
7301 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7302 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7306 if (used_at
== 0 && mips_opts
.at
)
7308 macro_build (&offset_expr
, "lui", LUI_FMT
,
7309 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7310 macro_build (&offset_expr
, "lui", LUI_FMT
,
7311 AT
, BFD_RELOC_HI16_S
);
7312 macro_build (&offset_expr
, "daddiu", "t,r,j",
7313 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7314 macro_build (&offset_expr
, "daddiu", "t,r,j",
7315 AT
, AT
, BFD_RELOC_LO16
);
7316 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7317 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7322 macro_build (&offset_expr
, "lui", LUI_FMT
,
7323 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7324 macro_build (&offset_expr
, "daddiu", "t,r,j",
7325 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7326 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7327 macro_build (&offset_expr
, "daddiu", "t,r,j",
7328 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7329 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7330 macro_build (&offset_expr
, "daddiu", "t,r,j",
7331 tempreg
, tempreg
, BFD_RELOC_LO16
);
7334 if (mips_relax
.sequence
)
7339 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7340 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7342 relax_start (offset_expr
.X_add_symbol
);
7343 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7344 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7347 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7348 as_bad (_("Offset too large"));
7349 macro_build_lui (&offset_expr
, tempreg
);
7350 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7351 tempreg
, tempreg
, BFD_RELOC_LO16
);
7352 if (mips_relax
.sequence
)
7356 else if (!mips_big_got
&& !HAVE_NEWABI
)
7358 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7360 /* If this is a reference to an external symbol, and there
7361 is no constant, we want
7362 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7363 or for lca or if tempreg is PIC_CALL_REG
7364 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7365 For a local symbol, we want
7366 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7368 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7370 If we have a small constant, and this is a reference to
7371 an external symbol, we want
7372 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7374 addiu $tempreg,$tempreg,<constant>
7375 For a local symbol, we want the same instruction
7376 sequence, but we output a BFD_RELOC_LO16 reloc on the
7379 If we have a large constant, and this is a reference to
7380 an external symbol, we want
7381 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7382 lui $at,<hiconstant>
7383 addiu $at,$at,<loconstant>
7384 addu $tempreg,$tempreg,$at
7385 For a local symbol, we want the same instruction
7386 sequence, but we output a BFD_RELOC_LO16 reloc on the
7390 if (offset_expr
.X_add_number
== 0)
7392 if (mips_pic
== SVR4_PIC
7394 && (call
|| tempreg
== PIC_CALL_REG
))
7395 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7397 relax_start (offset_expr
.X_add_symbol
);
7398 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7399 lw_reloc_type
, mips_gp_register
);
7402 /* We're going to put in an addu instruction using
7403 tempreg, so we may as well insert the nop right
7408 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7409 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7411 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7412 tempreg
, tempreg
, BFD_RELOC_LO16
);
7414 /* FIXME: If breg == 0, and the next instruction uses
7415 $tempreg, then if this variant case is used an extra
7416 nop will be generated. */
7418 else if (offset_expr
.X_add_number
>= -0x8000
7419 && offset_expr
.X_add_number
< 0x8000)
7421 load_got_offset (tempreg
, &offset_expr
);
7423 add_got_offset (tempreg
, &offset_expr
);
7427 expr1
.X_add_number
= offset_expr
.X_add_number
;
7428 offset_expr
.X_add_number
=
7429 SEXT_16BIT (offset_expr
.X_add_number
);
7430 load_got_offset (tempreg
, &offset_expr
);
7431 offset_expr
.X_add_number
= expr1
.X_add_number
;
7432 /* If we are going to add in a base register, and the
7433 target register and the base register are the same,
7434 then we are using AT as a temporary register. Since
7435 we want to load the constant into AT, we add our
7436 current AT (from the global offset table) and the
7437 register into the register now, and pretend we were
7438 not using a base register. */
7442 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7447 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7451 else if (!mips_big_got
&& HAVE_NEWABI
)
7453 int add_breg_early
= 0;
7455 /* If this is a reference to an external, and there is no
7456 constant, or local symbol (*), with or without a
7458 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7459 or for lca or if tempreg is PIC_CALL_REG
7460 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7462 If we have a small constant, and this is a reference to
7463 an external symbol, we want
7464 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7465 addiu $tempreg,$tempreg,<constant>
7467 If we have a large constant, and this is a reference to
7468 an external symbol, we want
7469 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7470 lui $at,<hiconstant>
7471 addiu $at,$at,<loconstant>
7472 addu $tempreg,$tempreg,$at
7474 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7475 local symbols, even though it introduces an additional
7478 if (offset_expr
.X_add_number
)
7480 expr1
.X_add_number
= offset_expr
.X_add_number
;
7481 offset_expr
.X_add_number
= 0;
7483 relax_start (offset_expr
.X_add_symbol
);
7484 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7485 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7487 if (expr1
.X_add_number
>= -0x8000
7488 && expr1
.X_add_number
< 0x8000)
7490 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7491 tempreg
, tempreg
, BFD_RELOC_LO16
);
7493 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7495 /* If we are going to add in a base register, and the
7496 target register and the base register are the same,
7497 then we are using AT as a temporary register. Since
7498 we want to load the constant into AT, we add our
7499 current AT (from the global offset table) and the
7500 register into the register now, and pretend we were
7501 not using a base register. */
7506 gas_assert (tempreg
== AT
);
7507 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7513 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7514 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7520 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7523 offset_expr
.X_add_number
= expr1
.X_add_number
;
7525 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7526 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7529 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7530 treg
, tempreg
, breg
);
7536 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7538 relax_start (offset_expr
.X_add_symbol
);
7539 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7540 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7542 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7543 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7548 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7549 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7552 else if (mips_big_got
&& !HAVE_NEWABI
)
7555 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7556 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7557 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7559 /* This is the large GOT case. If this is a reference to an
7560 external symbol, and there is no constant, we want
7561 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7562 addu $tempreg,$tempreg,$gp
7563 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7564 or for lca or if tempreg is PIC_CALL_REG
7565 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7566 addu $tempreg,$tempreg,$gp
7567 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7568 For a local symbol, we want
7569 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7571 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7573 If we have a small constant, and this is a reference to
7574 an external symbol, we want
7575 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7576 addu $tempreg,$tempreg,$gp
7577 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7579 addiu $tempreg,$tempreg,<constant>
7580 For a local symbol, we want
7581 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7583 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7585 If we have a large constant, and this is a reference to
7586 an external symbol, we want
7587 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7588 addu $tempreg,$tempreg,$gp
7589 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7590 lui $at,<hiconstant>
7591 addiu $at,$at,<loconstant>
7592 addu $tempreg,$tempreg,$at
7593 For a local symbol, we want
7594 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7595 lui $at,<hiconstant>
7596 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7597 addu $tempreg,$tempreg,$at
7600 expr1
.X_add_number
= offset_expr
.X_add_number
;
7601 offset_expr
.X_add_number
= 0;
7602 relax_start (offset_expr
.X_add_symbol
);
7603 gpdelay
= reg_needs_delay (mips_gp_register
);
7604 if (expr1
.X_add_number
== 0 && breg
== 0
7605 && (call
|| tempreg
== PIC_CALL_REG
))
7607 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7608 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7610 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7611 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7612 tempreg
, tempreg
, mips_gp_register
);
7613 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7614 tempreg
, lw_reloc_type
, tempreg
);
7615 if (expr1
.X_add_number
== 0)
7619 /* We're going to put in an addu instruction using
7620 tempreg, so we may as well insert the nop right
7625 else if (expr1
.X_add_number
>= -0x8000
7626 && expr1
.X_add_number
< 0x8000)
7629 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7630 tempreg
, tempreg
, BFD_RELOC_LO16
);
7634 /* If we are going to add in a base register, and the
7635 target register and the base register are the same,
7636 then we are using AT as a temporary register. Since
7637 we want to load the constant into AT, we add our
7638 current AT (from the global offset table) and the
7639 register into the register now, and pretend we were
7640 not using a base register. */
7645 gas_assert (tempreg
== AT
);
7647 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7652 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7653 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7657 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
7662 /* This is needed because this instruction uses $gp, but
7663 the first instruction on the main stream does not. */
7664 macro_build (NULL
, "nop", "");
7667 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7668 local_reloc_type
, mips_gp_register
);
7669 if (expr1
.X_add_number
>= -0x8000
7670 && expr1
.X_add_number
< 0x8000)
7673 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7674 tempreg
, tempreg
, BFD_RELOC_LO16
);
7675 /* FIXME: If add_number is 0, and there was no base
7676 register, the external symbol case ended with a load,
7677 so if the symbol turns out to not be external, and
7678 the next instruction uses tempreg, an unnecessary nop
7679 will be inserted. */
7685 /* We must add in the base register now, as in the
7686 external symbol case. */
7687 gas_assert (tempreg
== AT
);
7689 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7692 /* We set breg to 0 because we have arranged to add
7693 it in in both cases. */
7697 macro_build_lui (&expr1
, AT
);
7698 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7699 AT
, AT
, BFD_RELOC_LO16
);
7700 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7701 tempreg
, tempreg
, AT
);
7706 else if (mips_big_got
&& HAVE_NEWABI
)
7708 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7709 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7710 int add_breg_early
= 0;
7712 /* This is the large GOT case. If this is a reference to an
7713 external symbol, and there is no constant, we want
7714 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7715 add $tempreg,$tempreg,$gp
7716 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7717 or for lca or if tempreg is PIC_CALL_REG
7718 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7719 add $tempreg,$tempreg,$gp
7720 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7722 If we have a small constant, and this is a reference to
7723 an external symbol, we want
7724 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7725 add $tempreg,$tempreg,$gp
7726 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7727 addi $tempreg,$tempreg,<constant>
7729 If we have a large constant, and this is a reference to
7730 an external symbol, we want
7731 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7732 addu $tempreg,$tempreg,$gp
7733 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7734 lui $at,<hiconstant>
7735 addi $at,$at,<loconstant>
7736 add $tempreg,$tempreg,$at
7738 If we have NewABI, and we know it's a local symbol, we want
7739 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7740 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7741 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7743 relax_start (offset_expr
.X_add_symbol
);
7745 expr1
.X_add_number
= offset_expr
.X_add_number
;
7746 offset_expr
.X_add_number
= 0;
7748 if (expr1
.X_add_number
== 0 && breg
== 0
7749 && (call
|| tempreg
== PIC_CALL_REG
))
7751 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7752 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7754 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7755 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7756 tempreg
, tempreg
, mips_gp_register
);
7757 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7758 tempreg
, lw_reloc_type
, tempreg
);
7760 if (expr1
.X_add_number
== 0)
7762 else if (expr1
.X_add_number
>= -0x8000
7763 && expr1
.X_add_number
< 0x8000)
7765 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7766 tempreg
, tempreg
, BFD_RELOC_LO16
);
7768 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7770 /* If we are going to add in a base register, and the
7771 target register and the base register are the same,
7772 then we are using AT as a temporary register. Since
7773 we want to load the constant into AT, we add our
7774 current AT (from the global offset table) and the
7775 register into the register now, and pretend we were
7776 not using a base register. */
7781 gas_assert (tempreg
== AT
);
7782 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7788 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7789 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7794 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7797 offset_expr
.X_add_number
= expr1
.X_add_number
;
7798 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7799 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7800 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7801 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7804 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7805 treg
, tempreg
, breg
);
7815 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7819 gas_assert (!mips_opts
.micromips
);
7821 unsigned long temp
= (treg
<< 16) | (0x01);
7822 macro_build (NULL
, "c2", "C", temp
);
7827 gas_assert (!mips_opts
.micromips
);
7829 unsigned long temp
= (0x02);
7830 macro_build (NULL
, "c2", "C", temp
);
7835 gas_assert (!mips_opts
.micromips
);
7837 unsigned long temp
= (treg
<< 16) | (0x02);
7838 macro_build (NULL
, "c2", "C", temp
);
7843 gas_assert (!mips_opts
.micromips
);
7844 macro_build (NULL
, "c2", "C", 3);
7848 gas_assert (!mips_opts
.micromips
);
7850 unsigned long temp
= (treg
<< 16) | 0x03;
7851 macro_build (NULL
, "c2", "C", temp
);
7856 /* The j instruction may not be used in PIC code, since it
7857 requires an absolute address. We convert it to a b
7859 if (mips_pic
== NO_PIC
)
7860 macro_build (&offset_expr
, "j", "a");
7862 macro_build (&offset_expr
, "b", "p");
7865 /* The jal instructions must be handled as macros because when
7866 generating PIC code they expand to multi-instruction
7867 sequences. Normally they are simple instructions. */
7872 gas_assert (mips_opts
.micromips
);
7880 if (mips_pic
== NO_PIC
)
7882 s
= jals
? "jalrs" : "jalr";
7883 if (mips_opts
.micromips
7885 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7886 macro_build (NULL
, s
, "mj", sreg
);
7888 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7892 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7893 && mips_cprestore_offset
>= 0);
7895 if (sreg
!= PIC_CALL_REG
)
7896 as_warn (_("MIPS PIC call to register other than $25"));
7898 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7899 ? "jalrs" : "jalr");
7900 if (mips_opts
.micromips
7902 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7903 macro_build (NULL
, s
, "mj", sreg
);
7905 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7906 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7908 if (mips_cprestore_offset
< 0)
7909 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7912 if (!mips_frame_reg_valid
)
7914 as_warn (_("No .frame pseudo-op used in PIC code"));
7915 /* Quiet this warning. */
7916 mips_frame_reg_valid
= 1;
7918 if (!mips_cprestore_valid
)
7920 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7921 /* Quiet this warning. */
7922 mips_cprestore_valid
= 1;
7924 if (mips_opts
.noreorder
)
7925 macro_build (NULL
, "nop", "");
7926 expr1
.X_add_number
= mips_cprestore_offset
;
7927 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7930 HAVE_64BIT_ADDRESSES
);
7938 gas_assert (mips_opts
.micromips
);
7942 if (mips_pic
== NO_PIC
)
7943 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7944 else if (mips_pic
== SVR4_PIC
)
7946 /* If this is a reference to an external symbol, and we are
7947 using a small GOT, we want
7948 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7952 lw $gp,cprestore($sp)
7953 The cprestore value is set using the .cprestore
7954 pseudo-op. If we are using a big GOT, we want
7955 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7957 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7961 lw $gp,cprestore($sp)
7962 If the symbol is not external, we want
7963 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7965 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7968 lw $gp,cprestore($sp)
7970 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7971 sequences above, minus nops, unless the symbol is local,
7972 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7978 relax_start (offset_expr
.X_add_symbol
);
7979 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7980 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7983 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7984 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
7990 relax_start (offset_expr
.X_add_symbol
);
7991 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7992 BFD_RELOC_MIPS_CALL_HI16
);
7993 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7994 PIC_CALL_REG
, mips_gp_register
);
7995 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7996 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7999 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8000 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
8002 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8003 PIC_CALL_REG
, PIC_CALL_REG
,
8004 BFD_RELOC_MIPS_GOT_OFST
);
8008 macro_build_jalr (&offset_expr
, 0);
8012 relax_start (offset_expr
.X_add_symbol
);
8015 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8016 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8025 gpdelay
= reg_needs_delay (mips_gp_register
);
8026 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8027 BFD_RELOC_MIPS_CALL_HI16
);
8028 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8029 PIC_CALL_REG
, mips_gp_register
);
8030 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8031 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8036 macro_build (NULL
, "nop", "");
8038 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8039 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
8042 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8043 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
8045 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
8047 if (mips_cprestore_offset
< 0)
8048 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8051 if (!mips_frame_reg_valid
)
8053 as_warn (_("No .frame pseudo-op used in PIC code"));
8054 /* Quiet this warning. */
8055 mips_frame_reg_valid
= 1;
8057 if (!mips_cprestore_valid
)
8059 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8060 /* Quiet this warning. */
8061 mips_cprestore_valid
= 1;
8063 if (mips_opts
.noreorder
)
8064 macro_build (NULL
, "nop", "");
8065 expr1
.X_add_number
= mips_cprestore_offset
;
8066 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8069 HAVE_64BIT_ADDRESSES
);
8073 else if (mips_pic
== VXWORKS_PIC
)
8074 as_bad (_("Non-PIC jump used in PIC library"));
8084 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8092 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8123 gas_assert (!mips_opts
.micromips
);
8126 /* Itbl support may require additional care here. */
8133 /* Itbl support may require additional care here. */
8141 off12
= mips_opts
.micromips
;
8142 /* Itbl support may require additional care here. */
8147 gas_assert (!mips_opts
.micromips
);
8150 /* Itbl support may require additional care here. */
8158 off12
= mips_opts
.micromips
;
8165 off12
= mips_opts
.micromips
;
8171 /* Itbl support may require additional care here. */
8179 off12
= mips_opts
.micromips
;
8180 /* Itbl support may require additional care here. */
8187 /* Itbl support may require additional care here. */
8195 off12
= mips_opts
.micromips
;
8202 off12
= mips_opts
.micromips
;
8209 off12
= mips_opts
.micromips
;
8216 off12
= mips_opts
.micromips
;
8223 off12
= mips_opts
.micromips
;
8228 gas_assert (mips_opts
.micromips
);
8237 gas_assert (mips_opts
.micromips
);
8246 gas_assert (mips_opts
.micromips
);
8254 gas_assert (mips_opts
.micromips
);
8261 if (breg
== treg
+ lp
)
8264 tempreg
= treg
+ lp
;
8284 gas_assert (!mips_opts
.micromips
);
8287 /* Itbl support may require additional care here. */
8294 /* Itbl support may require additional care here. */
8302 off12
= mips_opts
.micromips
;
8303 /* Itbl support may require additional care here. */
8308 gas_assert (!mips_opts
.micromips
);
8311 /* Itbl support may require additional care here. */
8319 off12
= mips_opts
.micromips
;
8326 off12
= mips_opts
.micromips
;
8333 off12
= mips_opts
.micromips
;
8340 off12
= mips_opts
.micromips
;
8346 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8347 off12
= mips_opts
.micromips
;
8353 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8354 off12
= mips_opts
.micromips
;
8361 /* Itbl support may require additional care here. */
8368 off12
= mips_opts
.micromips
;
8369 /* Itbl support may require additional care here. */
8374 gas_assert (!mips_opts
.micromips
);
8377 /* Itbl support may require additional care here. */
8385 off12
= mips_opts
.micromips
;
8392 off12
= mips_opts
.micromips
;
8397 gas_assert (mips_opts
.micromips
);
8405 gas_assert (mips_opts
.micromips
);
8413 gas_assert (mips_opts
.micromips
);
8421 gas_assert (mips_opts
.micromips
);
8430 if (offset_expr
.X_op
!= O_constant
8431 && offset_expr
.X_op
!= O_symbol
)
8433 as_bad (_("Expression too complex"));
8434 offset_expr
.X_op
= O_constant
;
8437 if (HAVE_32BIT_ADDRESSES
8438 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8442 sprintf_vma (value
, offset_expr
.X_add_number
);
8443 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8446 /* A constant expression in PIC code can be handled just as it
8447 is in non PIC code. */
8448 if (offset_expr
.X_op
== O_constant
)
8452 expr1
.X_add_number
= offset_expr
.X_add_number
;
8453 normalize_address_expr (&expr1
);
8454 if (!off12
&& !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8456 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8457 & ~(bfd_vma
) 0xffff);
8460 else if (off12
&& !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8462 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8463 & ~(bfd_vma
) 0xfff);
8468 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8470 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8471 tempreg
, tempreg
, breg
);
8476 if (offset_expr
.X_add_number
== 0)
8479 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8480 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8481 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8484 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8486 macro_build (NULL
, s
, fmt
,
8487 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8489 else if (off12
|| off0
)
8491 /* A 12-bit or 0-bit offset field is too narrow to be used
8492 for a low-part relocation, so load the whole address into
8493 the auxillary register. In the case of "A(b)" addresses,
8494 we first load absolute address "A" into the register and
8495 then add base register "b". In the case of "o(b)" addresses,
8496 we simply need to add 16-bit offset "o" to base register "b", and
8497 offset_reloc already contains the relocations associated
8501 load_address (tempreg
, &offset_expr
, &used_at
);
8503 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8504 tempreg
, tempreg
, breg
);
8507 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8509 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8510 expr1
.X_add_number
= 0;
8512 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8514 macro_build (NULL
, s
, fmt
,
8515 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8517 else if (mips_pic
== NO_PIC
)
8519 /* If this is a reference to a GP relative symbol, and there
8520 is no base register, we want
8521 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8522 Otherwise, if there is no base register, we want
8523 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8524 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8525 If we have a constant, we need two instructions anyhow,
8526 so we always use the latter form.
8528 If we have a base register, and this is a reference to a
8529 GP relative symbol, we want
8530 addu $tempreg,$breg,$gp
8531 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8533 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8534 addu $tempreg,$tempreg,$breg
8535 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8536 With a constant we always use the latter case.
8538 With 64bit address space and no base register and $at usable,
8540 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8541 lui $at,<sym> (BFD_RELOC_HI16_S)
8542 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8545 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8546 If we have a base register, we want
8547 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8548 lui $at,<sym> (BFD_RELOC_HI16_S)
8549 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8553 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8555 Without $at we can't generate the optimal path for superscalar
8556 processors here since this would require two temporary registers.
8557 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8558 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8560 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8562 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8563 If we have a base register, we want
8564 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8565 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8567 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8569 daddu $tempreg,$tempreg,$breg
8570 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8572 For GP relative symbols in 64bit address space we can use
8573 the same sequence as in 32bit address space. */
8574 if (HAVE_64BIT_SYMBOLS
)
8576 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8577 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8579 relax_start (offset_expr
.X_add_symbol
);
8582 macro_build (&offset_expr
, s
, fmt
, treg
,
8583 BFD_RELOC_GPREL16
, mips_gp_register
);
8587 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8588 tempreg
, breg
, mips_gp_register
);
8589 macro_build (&offset_expr
, s
, fmt
, treg
,
8590 BFD_RELOC_GPREL16
, tempreg
);
8595 if (used_at
== 0 && mips_opts
.at
)
8597 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8598 BFD_RELOC_MIPS_HIGHEST
);
8599 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8601 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8602 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8604 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8605 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8606 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8607 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8613 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8614 BFD_RELOC_MIPS_HIGHEST
);
8615 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8616 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8617 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8618 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8619 tempreg
, BFD_RELOC_HI16_S
);
8620 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8622 macro_build (NULL
, "daddu", "d,v,t",
8623 tempreg
, tempreg
, breg
);
8624 macro_build (&offset_expr
, s
, fmt
, treg
,
8625 BFD_RELOC_LO16
, tempreg
);
8628 if (mips_relax
.sequence
)
8635 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8636 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8638 relax_start (offset_expr
.X_add_symbol
);
8639 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8643 macro_build_lui (&offset_expr
, tempreg
);
8644 macro_build (&offset_expr
, s
, fmt
, treg
,
8645 BFD_RELOC_LO16
, tempreg
);
8646 if (mips_relax
.sequence
)
8651 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8652 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8654 relax_start (offset_expr
.X_add_symbol
);
8655 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8656 tempreg
, breg
, mips_gp_register
);
8657 macro_build (&offset_expr
, s
, fmt
, treg
,
8658 BFD_RELOC_GPREL16
, tempreg
);
8661 macro_build_lui (&offset_expr
, tempreg
);
8662 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8663 tempreg
, tempreg
, breg
);
8664 macro_build (&offset_expr
, s
, fmt
, treg
,
8665 BFD_RELOC_LO16
, tempreg
);
8666 if (mips_relax
.sequence
)
8670 else if (!mips_big_got
)
8672 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8674 /* If this is a reference to an external symbol, we want
8675 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8677 <op> $treg,0($tempreg)
8679 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8681 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8682 <op> $treg,0($tempreg)
8685 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8686 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8688 If there is a base register, we add it to $tempreg before
8689 the <op>. If there is a constant, we stick it in the
8690 <op> instruction. We don't handle constants larger than
8691 16 bits, because we have no way to load the upper 16 bits
8692 (actually, we could handle them for the subset of cases
8693 in which we are not using $at). */
8694 gas_assert (offset_expr
.X_op
== O_symbol
);
8697 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8698 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8700 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8701 tempreg
, tempreg
, breg
);
8702 macro_build (&offset_expr
, s
, fmt
, treg
,
8703 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8706 expr1
.X_add_number
= offset_expr
.X_add_number
;
8707 offset_expr
.X_add_number
= 0;
8708 if (expr1
.X_add_number
< -0x8000
8709 || expr1
.X_add_number
>= 0x8000)
8710 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8711 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8712 lw_reloc_type
, mips_gp_register
);
8714 relax_start (offset_expr
.X_add_symbol
);
8716 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8717 tempreg
, BFD_RELOC_LO16
);
8720 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8721 tempreg
, tempreg
, breg
);
8722 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8724 else if (mips_big_got
&& !HAVE_NEWABI
)
8728 /* If this is a reference to an external symbol, we want
8729 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8730 addu $tempreg,$tempreg,$gp
8731 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8732 <op> $treg,0($tempreg)
8734 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8736 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8737 <op> $treg,0($tempreg)
8738 If there is a base register, we add it to $tempreg before
8739 the <op>. If there is a constant, we stick it in the
8740 <op> instruction. We don't handle constants larger than
8741 16 bits, because we have no way to load the upper 16 bits
8742 (actually, we could handle them for the subset of cases
8743 in which we are not using $at). */
8744 gas_assert (offset_expr
.X_op
== O_symbol
);
8745 expr1
.X_add_number
= offset_expr
.X_add_number
;
8746 offset_expr
.X_add_number
= 0;
8747 if (expr1
.X_add_number
< -0x8000
8748 || expr1
.X_add_number
>= 0x8000)
8749 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8750 gpdelay
= reg_needs_delay (mips_gp_register
);
8751 relax_start (offset_expr
.X_add_symbol
);
8752 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8753 BFD_RELOC_MIPS_GOT_HI16
);
8754 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8756 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8757 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8760 macro_build (NULL
, "nop", "");
8761 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8762 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8764 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8765 tempreg
, BFD_RELOC_LO16
);
8769 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8770 tempreg
, tempreg
, breg
);
8771 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8773 else if (mips_big_got
&& HAVE_NEWABI
)
8775 /* If this is a reference to an external symbol, we want
8776 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8777 add $tempreg,$tempreg,$gp
8778 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8779 <op> $treg,<ofst>($tempreg)
8780 Otherwise, for local symbols, we want:
8781 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8782 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8783 gas_assert (offset_expr
.X_op
== O_symbol
);
8784 expr1
.X_add_number
= offset_expr
.X_add_number
;
8785 offset_expr
.X_add_number
= 0;
8786 if (expr1
.X_add_number
< -0x8000
8787 || expr1
.X_add_number
>= 0x8000)
8788 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8789 relax_start (offset_expr
.X_add_symbol
);
8790 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8791 BFD_RELOC_MIPS_GOT_HI16
);
8792 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8794 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8795 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8797 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8798 tempreg
, tempreg
, breg
);
8799 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8802 offset_expr
.X_add_number
= expr1
.X_add_number
;
8803 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8804 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8806 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8807 tempreg
, tempreg
, breg
);
8808 macro_build (&offset_expr
, s
, fmt
, treg
,
8809 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8819 load_register (treg
, &imm_expr
, 0);
8823 load_register (treg
, &imm_expr
, 1);
8827 if (imm_expr
.X_op
== O_constant
)
8830 load_register (AT
, &imm_expr
, 0);
8831 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8836 gas_assert (offset_expr
.X_op
== O_symbol
8837 && strcmp (segment_name (S_GET_SEGMENT
8838 (offset_expr
.X_add_symbol
)),
8840 && offset_expr
.X_add_number
== 0);
8841 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
8842 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8847 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8848 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8849 order 32 bits of the value and the low order 32 bits are either
8850 zero or in OFFSET_EXPR. */
8851 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8853 if (HAVE_64BIT_GPRS
)
8854 load_register (treg
, &imm_expr
, 1);
8859 if (target_big_endian
)
8871 load_register (hreg
, &imm_expr
, 0);
8874 if (offset_expr
.X_op
== O_absent
)
8875 move_register (lreg
, 0);
8878 gas_assert (offset_expr
.X_op
== O_constant
);
8879 load_register (lreg
, &offset_expr
, 0);
8886 /* We know that sym is in the .rdata section. First we get the
8887 upper 16 bits of the address. */
8888 if (mips_pic
== NO_PIC
)
8890 macro_build_lui (&offset_expr
, AT
);
8895 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8896 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8900 /* Now we load the register(s). */
8901 if (HAVE_64BIT_GPRS
)
8904 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8909 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8912 /* FIXME: How in the world do we deal with the possible
8914 offset_expr
.X_add_number
+= 4;
8915 macro_build (&offset_expr
, "lw", "t,o(b)",
8916 treg
+ 1, BFD_RELOC_LO16
, AT
);
8922 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8923 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8924 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8925 the value and the low order 32 bits are either zero or in
8927 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8930 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
8931 if (HAVE_64BIT_FPRS
)
8933 gas_assert (HAVE_64BIT_GPRS
);
8934 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
8938 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
8939 if (offset_expr
.X_op
== O_absent
)
8940 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
8943 gas_assert (offset_expr
.X_op
== O_constant
);
8944 load_register (AT
, &offset_expr
, 0);
8945 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8951 gas_assert (offset_expr
.X_op
== O_symbol
8952 && offset_expr
.X_add_number
== 0);
8953 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
8954 if (strcmp (s
, ".lit8") == 0)
8956 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
8958 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
8959 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8962 breg
= mips_gp_register
;
8963 r
= BFD_RELOC_MIPS_LITERAL
;
8968 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
8970 if (mips_pic
!= NO_PIC
)
8971 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8972 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8975 /* FIXME: This won't work for a 64 bit address. */
8976 macro_build_lui (&offset_expr
, AT
);
8979 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
8981 macro_build (&offset_expr
, "ldc1", "T,o(b)",
8982 treg
, BFD_RELOC_LO16
, AT
);
8991 /* Even on a big endian machine $fn comes before $fn+1. We have
8992 to adjust when loading from memory. */
8995 gas_assert (!mips_opts
.micromips
);
8996 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
8997 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8998 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
8999 /* FIXME: A possible overflow which I don't know how to deal
9001 offset_expr
.X_add_number
+= 4;
9002 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9003 target_big_endian
? treg
: treg
+ 1, r
, breg
);
9007 gas_assert (!mips_opts
.micromips
);
9008 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9009 /* Even on a big endian machine $fn comes before $fn+1. We have
9010 to adjust when storing to memory. */
9011 macro_build (&offset_expr
, "swc1", "T,o(b)",
9012 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
9013 offset_expr
.X_add_number
+= 4;
9014 macro_build (&offset_expr
, "swc1", "T,o(b)",
9015 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
9019 gas_assert (!mips_opts
.micromips
);
9021 * The MIPS assembler seems to check for X_add_number not
9022 * being double aligned and generating:
9025 * addiu at,at,%lo(foo+1)
9028 * But, the resulting address is the same after relocation so why
9029 * generate the extra instruction?
9031 /* Itbl support may require additional care here. */
9034 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9043 gas_assert (!mips_opts
.micromips
);
9044 /* Itbl support may require additional care here. */
9047 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9067 if (HAVE_64BIT_GPRS
)
9077 if (HAVE_64BIT_GPRS
)
9085 if (offset_expr
.X_op
!= O_symbol
9086 && offset_expr
.X_op
!= O_constant
)
9088 as_bad (_("Expression too complex"));
9089 offset_expr
.X_op
= O_constant
;
9092 if (HAVE_32BIT_ADDRESSES
9093 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9097 sprintf_vma (value
, offset_expr
.X_add_number
);
9098 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9101 /* Even on a big endian machine $fn comes before $fn+1. We have
9102 to adjust when loading from memory. We set coproc if we must
9103 load $fn+1 first. */
9104 /* Itbl support may require additional care here. */
9105 if (!target_big_endian
)
9108 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
9110 /* If this is a reference to a GP relative symbol, we want
9111 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9112 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9113 If we have a base register, we use this
9115 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9116 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9117 If this is not a GP relative symbol, we want
9118 lui $at,<sym> (BFD_RELOC_HI16_S)
9119 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9120 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9121 If there is a base register, we add it to $at after the
9122 lui instruction. If there is a constant, we always use
9124 if (offset_expr
.X_op
== O_symbol
9125 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9126 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9128 relax_start (offset_expr
.X_add_symbol
);
9131 tempreg
= mips_gp_register
;
9135 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9136 AT
, breg
, mips_gp_register
);
9141 /* Itbl support may require additional care here. */
9142 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9143 BFD_RELOC_GPREL16
, tempreg
);
9144 offset_expr
.X_add_number
+= 4;
9146 /* Set mips_optimize to 2 to avoid inserting an
9148 hold_mips_optimize
= mips_optimize
;
9150 /* Itbl support may require additional care here. */
9151 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9152 BFD_RELOC_GPREL16
, tempreg
);
9153 mips_optimize
= hold_mips_optimize
;
9157 offset_expr
.X_add_number
-= 4;
9160 macro_build_lui (&offset_expr
, AT
);
9162 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9163 /* Itbl support may require additional care here. */
9164 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9165 BFD_RELOC_LO16
, AT
);
9166 /* FIXME: How do we handle overflow here? */
9167 offset_expr
.X_add_number
+= 4;
9168 /* Itbl support may require additional care here. */
9169 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9170 BFD_RELOC_LO16
, AT
);
9171 if (mips_relax
.sequence
)
9174 else if (!mips_big_got
)
9176 /* If this is a reference to an external symbol, we want
9177 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9182 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9184 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9185 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9186 If there is a base register we add it to $at before the
9187 lwc1 instructions. If there is a constant we include it
9188 in the lwc1 instructions. */
9190 expr1
.X_add_number
= offset_expr
.X_add_number
;
9191 if (expr1
.X_add_number
< -0x8000
9192 || expr1
.X_add_number
>= 0x8000 - 4)
9193 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9194 load_got_offset (AT
, &offset_expr
);
9197 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9199 /* Set mips_optimize to 2 to avoid inserting an undesired
9201 hold_mips_optimize
= mips_optimize
;
9204 /* Itbl support may require additional care here. */
9205 relax_start (offset_expr
.X_add_symbol
);
9206 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9207 BFD_RELOC_LO16
, AT
);
9208 expr1
.X_add_number
+= 4;
9209 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9210 BFD_RELOC_LO16
, AT
);
9212 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9213 BFD_RELOC_LO16
, AT
);
9214 offset_expr
.X_add_number
+= 4;
9215 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9216 BFD_RELOC_LO16
, AT
);
9219 mips_optimize
= hold_mips_optimize
;
9221 else if (mips_big_got
)
9225 /* If this is a reference to an external symbol, we want
9226 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9228 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9233 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9235 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9236 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9237 If there is a base register we add it to $at before the
9238 lwc1 instructions. If there is a constant we include it
9239 in the lwc1 instructions. */
9241 expr1
.X_add_number
= offset_expr
.X_add_number
;
9242 offset_expr
.X_add_number
= 0;
9243 if (expr1
.X_add_number
< -0x8000
9244 || expr1
.X_add_number
>= 0x8000 - 4)
9245 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9246 gpdelay
= reg_needs_delay (mips_gp_register
);
9247 relax_start (offset_expr
.X_add_symbol
);
9248 macro_build (&offset_expr
, "lui", LUI_FMT
,
9249 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9250 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9251 AT
, AT
, mips_gp_register
);
9252 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9253 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9256 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9257 /* Itbl support may require additional care here. */
9258 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9259 BFD_RELOC_LO16
, AT
);
9260 expr1
.X_add_number
+= 4;
9262 /* Set mips_optimize to 2 to avoid inserting an undesired
9264 hold_mips_optimize
= mips_optimize
;
9266 /* Itbl support may require additional care here. */
9267 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9268 BFD_RELOC_LO16
, AT
);
9269 mips_optimize
= hold_mips_optimize
;
9270 expr1
.X_add_number
-= 4;
9273 offset_expr
.X_add_number
= expr1
.X_add_number
;
9275 macro_build (NULL
, "nop", "");
9276 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9277 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9280 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9281 /* Itbl support may require additional care here. */
9282 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9283 BFD_RELOC_LO16
, AT
);
9284 offset_expr
.X_add_number
+= 4;
9286 /* Set mips_optimize to 2 to avoid inserting an undesired
9288 hold_mips_optimize
= mips_optimize
;
9290 /* Itbl support may require additional care here. */
9291 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9292 BFD_RELOC_LO16
, AT
);
9293 mips_optimize
= hold_mips_optimize
;
9302 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9305 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9307 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9308 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9310 if (!HAVE_64BIT_GPRS
)
9312 offset_expr
.X_add_number
+= 4;
9313 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9314 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9335 /* New code added to support COPZ instructions.
9336 This code builds table entries out of the macros in mip_opcodes.
9337 R4000 uses interlocks to handle coproc delays.
9338 Other chips (like the R3000) require nops to be inserted for delays.
9340 FIXME: Currently, we require that the user handle delays.
9341 In order to fill delay slots for non-interlocked chips,
9342 we must have a way to specify delays based on the coprocessor.
9343 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9344 What are the side-effects of the cop instruction?
9345 What cache support might we have and what are its effects?
9346 Both coprocessor & memory require delays. how long???
9347 What registers are read/set/modified?
9349 If an itbl is provided to interpret cop instructions,
9350 this knowledge can be encoded in the itbl spec. */
9364 gas_assert (!mips_opts
.micromips
);
9365 /* For now we just do C (same as Cz). The parameter will be
9366 stored in insn_opcode by mips_ip. */
9367 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9371 move_register (dreg
, sreg
);
9377 if (mips_opts
.arch
== CPU_R5900
)
9379 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
9383 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9384 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9391 /* The MIPS assembler some times generates shifts and adds. I'm
9392 not trying to be that fancy. GCC should do this for us
9395 load_register (AT
, &imm_expr
, dbl
);
9396 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9397 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9413 load_register (AT
, &imm_expr
, dbl
);
9414 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9415 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9416 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9417 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9419 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9422 if (mips_opts
.micromips
)
9423 micromips_label_expr (&label_expr
);
9425 label_expr
.X_add_number
= 8;
9426 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9427 macro_build (NULL
, "nop", "");
9428 macro_build (NULL
, "break", BRK_FMT
, 6);
9429 if (mips_opts
.micromips
)
9430 micromips_add_label ();
9433 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9449 load_register (AT
, &imm_expr
, dbl
);
9450 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9451 sreg
, imm
? AT
: treg
);
9452 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9453 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9455 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9458 if (mips_opts
.micromips
)
9459 micromips_label_expr (&label_expr
);
9461 label_expr
.X_add_number
= 8;
9462 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9463 macro_build (NULL
, "nop", "");
9464 macro_build (NULL
, "break", BRK_FMT
, 6);
9465 if (mips_opts
.micromips
)
9466 micromips_add_label ();
9472 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9483 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9484 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9488 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9489 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9490 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9491 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9495 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9506 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9507 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9511 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9512 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9513 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9514 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9523 if (imm_expr
.X_op
!= O_constant
)
9524 as_bad (_("Improper rotate count"));
9525 rot
= imm_expr
.X_add_number
& 0x3f;
9526 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9528 rot
= (64 - rot
) & 0x3f;
9530 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9532 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9537 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9540 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9541 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9544 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9545 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9546 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9554 if (imm_expr
.X_op
!= O_constant
)
9555 as_bad (_("Improper rotate count"));
9556 rot
= imm_expr
.X_add_number
& 0x1f;
9557 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9559 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9564 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9568 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9569 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9570 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9575 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9577 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9581 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9582 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9583 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9584 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9588 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9590 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9594 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9595 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9596 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9597 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9606 if (imm_expr
.X_op
!= O_constant
)
9607 as_bad (_("Improper rotate count"));
9608 rot
= imm_expr
.X_add_number
& 0x3f;
9609 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9612 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9614 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9619 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9622 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9623 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9626 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9627 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9628 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9636 if (imm_expr
.X_op
!= O_constant
)
9637 as_bad (_("Improper rotate count"));
9638 rot
= imm_expr
.X_add_number
& 0x1f;
9639 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9641 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9646 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9650 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9651 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9652 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9658 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9660 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9663 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9664 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9669 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9671 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9676 as_warn (_("Instruction %s: result is always false"),
9678 move_register (dreg
, 0);
9681 if (CPU_HAS_SEQ (mips_opts
.arch
)
9682 && -512 <= imm_expr
.X_add_number
9683 && imm_expr
.X_add_number
< 512)
9685 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9686 (int) imm_expr
.X_add_number
);
9689 if (imm_expr
.X_op
== O_constant
9690 && imm_expr
.X_add_number
>= 0
9691 && imm_expr
.X_add_number
< 0x10000)
9693 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9695 else if (imm_expr
.X_op
== O_constant
9696 && imm_expr
.X_add_number
> -0x8000
9697 && imm_expr
.X_add_number
< 0)
9699 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9700 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9701 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9703 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9706 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9707 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9712 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9713 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9716 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9719 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9725 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9726 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9729 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9731 if (imm_expr
.X_op
== O_constant
9732 && imm_expr
.X_add_number
>= -0x8000
9733 && imm_expr
.X_add_number
< 0x8000)
9735 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9736 dreg
, sreg
, BFD_RELOC_LO16
);
9740 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9741 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9745 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9748 case M_SGT
: /* sreg > treg <==> treg < sreg */
9754 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9757 case M_SGT_I
: /* sreg > I <==> I < sreg */
9764 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9765 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9768 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9774 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9775 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9778 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9785 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9786 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9787 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9791 if (imm_expr
.X_op
== O_constant
9792 && imm_expr
.X_add_number
>= -0x8000
9793 && imm_expr
.X_add_number
< 0x8000)
9795 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9799 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9800 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9804 if (imm_expr
.X_op
== O_constant
9805 && imm_expr
.X_add_number
>= -0x8000
9806 && imm_expr
.X_add_number
< 0x8000)
9808 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9813 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9814 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9819 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9821 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9824 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9825 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9830 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9832 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9837 as_warn (_("Instruction %s: result is always true"),
9839 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
9840 dreg
, 0, BFD_RELOC_LO16
);
9843 if (CPU_HAS_SEQ (mips_opts
.arch
)
9844 && -512 <= imm_expr
.X_add_number
9845 && imm_expr
.X_add_number
< 512)
9847 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
9848 (int) imm_expr
.X_add_number
);
9851 if (imm_expr
.X_op
== O_constant
9852 && imm_expr
.X_add_number
>= 0
9853 && imm_expr
.X_add_number
< 0x10000)
9855 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9857 else if (imm_expr
.X_op
== O_constant
9858 && imm_expr
.X_add_number
> -0x8000
9859 && imm_expr
.X_add_number
< 0)
9861 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9862 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9863 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9865 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9868 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9869 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
9874 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9875 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9878 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9893 if (!mips_opts
.micromips
)
9895 if (imm_expr
.X_op
== O_constant
9896 && imm_expr
.X_add_number
> -0x200
9897 && imm_expr
.X_add_number
<= 0x200)
9899 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
9908 if (imm_expr
.X_op
== O_constant
9909 && imm_expr
.X_add_number
> -0x8000
9910 && imm_expr
.X_add_number
<= 0x8000)
9912 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9913 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9918 load_register (AT
, &imm_expr
, dbl
);
9919 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
9941 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9942 macro_build (NULL
, s
, "s,t", sreg
, AT
);
9947 gas_assert (!mips_opts
.micromips
);
9948 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
9950 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
9951 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
9954 * Is the double cfc1 instruction a bug in the mips assembler;
9955 * or is there a reason for it?
9958 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9959 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9960 macro_build (NULL
, "nop", "");
9961 expr1
.X_add_number
= 3;
9962 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
9963 expr1
.X_add_number
= 2;
9964 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
9965 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
9966 macro_build (NULL
, "nop", "");
9967 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
9969 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
9970 macro_build (NULL
, "nop", "");
9993 off12
= mips_opts
.micromips
;
10001 off12
= mips_opts
.micromips
;
10017 off12
= mips_opts
.micromips
;
10026 off12
= mips_opts
.micromips
;
10031 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
10032 as_bad (_("Operand overflow"));
10035 expr1
.X_add_number
= 0;
10040 load_address (tempreg
, ep
, &used_at
);
10042 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10043 tempreg
, tempreg
, breg
);
10049 && (offset_expr
.X_op
!= O_constant
10050 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
10051 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
10055 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
10056 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10061 else if (!ust
&& treg
== breg
)
10072 if (!target_big_endian
)
10073 ep
->X_add_number
+= off
;
10075 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10077 macro_build (NULL
, s
, "t,~(b)",
10078 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10080 if (!target_big_endian
)
10081 ep
->X_add_number
-= off
;
10083 ep
->X_add_number
+= off
;
10085 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10087 macro_build (NULL
, s2
, "t,~(b)",
10088 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10090 /* If necessary, move the result in tempreg to the final destination. */
10091 if (!ust
&& treg
!= tempreg
)
10093 /* Protect second load's delay slot. */
10095 move_register (treg
, tempreg
);
10101 if (target_big_endian
== ust
)
10102 ep
->X_add_number
+= off
;
10103 tempreg
= ust
|| ab
? treg
: AT
;
10104 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10106 /* For halfword transfers we need a temporary register to shuffle
10107 bytes. Unfortunately for M_USH_A we have none available before
10108 the next store as AT holds the base address. We deal with this
10109 case by clobbering TREG and then restoring it as with ULH. */
10110 tempreg
= ust
== ab
? treg
: AT
;
10112 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
10114 if (target_big_endian
== ust
)
10115 ep
->X_add_number
-= off
;
10117 ep
->X_add_number
+= off
;
10118 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10120 /* For M_USH_A re-retrieve the LSB. */
10123 if (target_big_endian
)
10124 ep
->X_add_number
+= off
;
10126 ep
->X_add_number
-= off
;
10127 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
10129 /* For ULH and M_USH_A OR the LSB in. */
10132 tempreg
= !ab
? AT
: treg
;
10133 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
10134 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
10139 /* FIXME: Check if this is one of the itbl macros, since they
10140 are added dynamically. */
10141 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
10144 if (!mips_opts
.at
&& used_at
)
10145 as_bad (_("Macro used $at after \".set noat\""));
10148 /* Implement macros in mips16 mode. */
10151 mips16_macro (struct mips_cl_insn
*ip
)
10154 int xreg
, yreg
, zreg
, tmp
;
10157 const char *s
, *s2
, *s3
;
10159 mask
= ip
->insn_mo
->mask
;
10161 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10162 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10163 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10165 expr1
.X_op
= O_constant
;
10166 expr1
.X_op_symbol
= NULL
;
10167 expr1
.X_add_symbol
= NULL
;
10168 expr1
.X_add_number
= 1;
10187 start_noreorder ();
10188 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10189 expr1
.X_add_number
= 2;
10190 macro_build (&expr1
, "bnez", "x,p", yreg
);
10191 macro_build (NULL
, "break", "6", 7);
10193 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10194 since that causes an overflow. We should do that as well,
10195 but I don't see how to do the comparisons without a temporary
10198 macro_build (NULL
, s
, "x", zreg
);
10217 start_noreorder ();
10218 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10219 expr1
.X_add_number
= 2;
10220 macro_build (&expr1
, "bnez", "x,p", yreg
);
10221 macro_build (NULL
, "break", "6", 7);
10223 macro_build (NULL
, s2
, "x", zreg
);
10229 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10230 macro_build (NULL
, "mflo", "x", zreg
);
10238 if (imm_expr
.X_op
!= O_constant
)
10239 as_bad (_("Unsupported large constant"));
10240 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10241 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10245 if (imm_expr
.X_op
!= O_constant
)
10246 as_bad (_("Unsupported large constant"));
10247 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10248 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10252 if (imm_expr
.X_op
!= O_constant
)
10253 as_bad (_("Unsupported large constant"));
10254 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10255 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10277 goto do_reverse_branch
;
10281 goto do_reverse_branch
;
10293 goto do_reverse_branch
;
10304 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10305 macro_build (&offset_expr
, s2
, "p");
10332 goto do_addone_branch_i
;
10337 goto do_addone_branch_i
;
10352 goto do_addone_branch_i
;
10358 do_addone_branch_i
:
10359 if (imm_expr
.X_op
!= O_constant
)
10360 as_bad (_("Unsupported large constant"));
10361 ++imm_expr
.X_add_number
;
10364 macro_build (&imm_expr
, s
, s3
, xreg
);
10365 macro_build (&offset_expr
, s2
, "p");
10369 expr1
.X_add_number
= 0;
10370 macro_build (&expr1
, "slti", "x,8", yreg
);
10372 move_register (xreg
, yreg
);
10373 expr1
.X_add_number
= 2;
10374 macro_build (&expr1
, "bteqz", "p");
10375 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10379 /* For consistency checking, verify that all bits are specified either
10380 by the match/mask part of the instruction definition, or by the
10383 validate_mips_insn (const struct mips_opcode
*opc
)
10385 const char *p
= opc
->args
;
10387 unsigned long used_bits
= opc
->mask
;
10389 if ((used_bits
& opc
->match
) != opc
->match
)
10391 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10392 opc
->name
, opc
->args
);
10395 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10405 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10406 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10407 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10408 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10409 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10410 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10411 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10412 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10413 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10414 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10415 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10416 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10417 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10419 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10420 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10421 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10422 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10423 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10424 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10425 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10426 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10427 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10428 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10429 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10430 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10431 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10432 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10433 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10436 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10437 c
, opc
->name
, opc
->args
);
10441 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10442 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10444 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10445 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10446 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10447 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10449 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10450 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10452 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10453 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10455 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10456 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10457 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10458 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10459 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10460 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10461 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10462 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10463 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10464 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10465 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10466 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10467 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10468 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10469 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10470 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10471 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10473 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10474 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10475 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10476 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10478 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10479 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10480 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10481 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10482 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10483 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10484 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10485 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10486 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10489 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10490 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10491 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10492 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10493 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10496 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10497 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10498 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10499 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10500 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10501 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10502 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10503 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10504 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10505 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10506 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10507 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10508 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10509 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10510 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10511 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10512 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10513 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10514 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10515 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10517 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10518 c
, opc
->name
, opc
->args
);
10522 if (used_bits
!= 0xffffffff)
10524 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10525 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10531 /* For consistency checking, verify that the length implied matches the
10532 major opcode and that all bits are specified either by the match/mask
10533 part of the instruction definition, or by the operand list. */
10536 validate_micromips_insn (const struct mips_opcode
*opc
)
10538 unsigned long match
= opc
->match
;
10539 unsigned long mask
= opc
->mask
;
10540 const char *p
= opc
->args
;
10541 unsigned long insn_bits
;
10542 unsigned long used_bits
;
10543 unsigned long major
;
10544 unsigned int length
;
10548 if ((mask
& match
) != match
)
10550 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10551 opc
->name
, opc
->args
);
10554 length
= micromips_insn_length (opc
);
10555 if (length
!= 2 && length
!= 4)
10557 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10558 "%s %s"), length
, opc
->name
, opc
->args
);
10561 major
= match
>> (10 + 8 * (length
- 2));
10562 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10563 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10565 as_bad (_("Internal error: bad microMIPS opcode "
10566 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10570 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10571 insn_bits
= 1 << 4 * length
;
10572 insn_bits
<<= 4 * length
;
10575 #define USE_BITS(field) \
10576 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10587 case 'A': USE_BITS (EXTLSB
); break;
10588 case 'B': USE_BITS (INSMSB
); break;
10589 case 'C': USE_BITS (EXTMSBD
); break;
10590 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10591 case 'E': USE_BITS (EXTLSB
); break;
10592 case 'F': USE_BITS (INSMSB
); break;
10593 case 'G': USE_BITS (EXTMSBD
); break;
10594 case 'H': USE_BITS (EXTMSBD
); break;
10596 as_bad (_("Internal error: bad mips opcode "
10597 "(unknown extension operand type `%c%c'): %s %s"),
10598 e
, c
, opc
->name
, opc
->args
);
10606 case 'A': USE_BITS (IMMA
); break;
10607 case 'B': USE_BITS (IMMB
); break;
10608 case 'C': USE_BITS (IMMC
); break;
10609 case 'D': USE_BITS (IMMD
); break;
10610 case 'E': USE_BITS (IMME
); break;
10611 case 'F': USE_BITS (IMMF
); break;
10612 case 'G': USE_BITS (IMMG
); break;
10613 case 'H': USE_BITS (IMMH
); break;
10614 case 'I': USE_BITS (IMMI
); break;
10615 case 'J': USE_BITS (IMMJ
); break;
10616 case 'L': USE_BITS (IMML
); break;
10617 case 'M': USE_BITS (IMMM
); break;
10618 case 'N': USE_BITS (IMMN
); break;
10619 case 'O': USE_BITS (IMMO
); break;
10620 case 'P': USE_BITS (IMMP
); break;
10621 case 'Q': USE_BITS (IMMQ
); break;
10622 case 'U': USE_BITS (IMMU
); break;
10623 case 'W': USE_BITS (IMMW
); break;
10624 case 'X': USE_BITS (IMMX
); break;
10625 case 'Y': USE_BITS (IMMY
); break;
10628 case 'b': USE_BITS (MB
); break;
10629 case 'c': USE_BITS (MC
); break;
10630 case 'd': USE_BITS (MD
); break;
10631 case 'e': USE_BITS (ME
); break;
10632 case 'f': USE_BITS (MF
); break;
10633 case 'g': USE_BITS (MG
); break;
10634 case 'h': USE_BITS (MH
); break;
10635 case 'i': USE_BITS (MI
); break;
10636 case 'j': USE_BITS (MJ
); break;
10637 case 'l': USE_BITS (ML
); break;
10638 case 'm': USE_BITS (MM
); break;
10639 case 'n': USE_BITS (MN
); break;
10640 case 'p': USE_BITS (MP
); break;
10641 case 'q': USE_BITS (MQ
); break;
10649 as_bad (_("Internal error: bad mips opcode "
10650 "(unknown extension operand type `%c%c'): %s %s"),
10651 e
, c
, opc
->name
, opc
->args
);
10655 case '.': USE_BITS (OFFSET10
); break;
10656 case '1': USE_BITS (STYPE
); break;
10657 case '2': USE_BITS (BP
); break;
10658 case '3': USE_BITS (SA3
); break;
10659 case '4': USE_BITS (SA4
); break;
10660 case '5': USE_BITS (IMM8
); break;
10661 case '6': USE_BITS (RS
); break;
10662 case '7': USE_BITS (DSPACC
); break;
10663 case '8': USE_BITS (WRDSP
); break;
10664 case '0': USE_BITS (DSPSFT
); break;
10665 case '<': USE_BITS (SHAMT
); break;
10666 case '>': USE_BITS (SHAMT
); break;
10667 case '@': USE_BITS (IMM10
); break;
10668 case 'B': USE_BITS (CODE10
); break;
10669 case 'C': USE_BITS (COPZ
); break;
10670 case 'D': USE_BITS (FD
); break;
10671 case 'E': USE_BITS (RT
); break;
10672 case 'G': USE_BITS (RS
); break;
10673 case 'H': USE_BITS (SEL
); break;
10674 case 'K': USE_BITS (RS
); break;
10675 case 'M': USE_BITS (CCC
); break;
10676 case 'N': USE_BITS (BCC
); break;
10677 case 'R': USE_BITS (FR
); break;
10678 case 'S': USE_BITS (FS
); break;
10679 case 'T': USE_BITS (FT
); break;
10680 case 'V': USE_BITS (FS
); break;
10681 case '\\': USE_BITS (3BITPOS
); break;
10682 case '^': USE_BITS (RD
); break;
10683 case 'a': USE_BITS (TARGET
); break;
10684 case 'b': USE_BITS (RS
); break;
10685 case 'c': USE_BITS (CODE
); break;
10686 case 'd': USE_BITS (RD
); break;
10687 case 'h': USE_BITS (PREFX
); break;
10688 case 'i': USE_BITS (IMMEDIATE
); break;
10689 case 'j': USE_BITS (DELTA
); break;
10690 case 'k': USE_BITS (CACHE
); break;
10691 case 'n': USE_BITS (RT
); break;
10692 case 'o': USE_BITS (DELTA
); break;
10693 case 'p': USE_BITS (DELTA
); break;
10694 case 'q': USE_BITS (CODE2
); break;
10695 case 'r': USE_BITS (RS
); break;
10696 case 's': USE_BITS (RS
); break;
10697 case 't': USE_BITS (RT
); break;
10698 case 'u': USE_BITS (IMMEDIATE
); break;
10699 case 'v': USE_BITS (RS
); break;
10700 case 'w': USE_BITS (RT
); break;
10701 case 'y': USE_BITS (RS3
); break;
10703 case '|': USE_BITS (TRAP
); break;
10704 case '~': USE_BITS (OFFSET12
); break;
10706 as_bad (_("Internal error: bad microMIPS opcode "
10707 "(unknown operand type `%c'): %s %s"),
10708 c
, opc
->name
, opc
->args
);
10712 if (used_bits
!= insn_bits
)
10714 if (~used_bits
& insn_bits
)
10715 as_bad (_("Internal error: bad microMIPS opcode "
10716 "(bits 0x%lx undefined): %s %s"),
10717 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10718 if (used_bits
& ~insn_bits
)
10719 as_bad (_("Internal error: bad microMIPS opcode "
10720 "(bits 0x%lx defined): %s %s"),
10721 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10727 /* UDI immediates. */
10728 struct mips_immed
{
10730 unsigned int shift
;
10731 unsigned long mask
;
10735 static const struct mips_immed mips_immed
[] = {
10736 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10737 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10738 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10739 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10743 /* Check whether an odd floating-point register is allowed. */
10745 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10747 const char *s
= insn
->name
;
10749 if (insn
->pinfo
== INSN_MACRO
)
10750 /* Let a macro pass, we'll catch it later when it is expanded. */
10753 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || (mips_opts
.arch
== CPU_R5900
))
10755 /* Allow odd registers for single-precision ops. */
10756 switch (insn
->pinfo
& (FP_S
| FP_D
))
10760 return 1; /* both single precision - ok */
10762 return 0; /* both double precision - fail */
10767 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10768 s
= strchr (insn
->name
, '.');
10770 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10771 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10774 /* Single-precision coprocessor loads and moves are OK too. */
10775 if ((insn
->pinfo
& FP_S
)
10776 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10777 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10783 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10784 taking bits from BIT up. */
10786 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10788 return (ep
->X_op
== O_constant
10789 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10790 && ep
->X_add_number
>= min
<< bit
10791 && ep
->X_add_number
< max
<< bit
);
10794 /* This routine assembles an instruction into its binary format. As a
10795 side effect, it sets one of the global variables imm_reloc or
10796 offset_reloc to the type of relocation to do if one of the operands
10797 is an address expression. */
10800 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10802 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10803 bfd_boolean need_delay_slot_ok
= TRUE
;
10804 struct mips_opcode
*firstinsn
= NULL
;
10805 const struct mips_opcode
*past
;
10806 struct hash_control
*hash
;
10810 struct mips_opcode
*insn
;
10812 unsigned int regno
;
10813 unsigned int lastregno
;
10814 unsigned int destregno
= 0;
10815 unsigned int lastpos
= 0;
10816 unsigned int limlo
, limhi
;
10819 offsetT min_range
, max_range
;
10823 unsigned int rtype
;
10829 if (mips_opts
.micromips
)
10831 hash
= micromips_op_hash
;
10832 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10837 past
= &mips_opcodes
[NUMOPCODES
];
10839 forced_insn_length
= 0;
10842 /* We first try to match an instruction up to a space or to the end. */
10843 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10846 /* Make a copy of the instruction so that we can fiddle with it. */
10847 name
= alloca (end
+ 1);
10848 memcpy (name
, str
, end
);
10853 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10855 if (insn
!= NULL
|| !mips_opts
.micromips
)
10857 if (forced_insn_length
)
10860 /* See if there's an instruction size override suffix,
10861 either `16' or `32', at the end of the mnemonic proper,
10862 that defines the operation, i.e. before the first `.'
10863 character if any. Strip it and retry. */
10864 dot
= strchr (name
, '.');
10865 opend
= dot
!= NULL
? dot
- name
: end
;
10868 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10869 forced_insn_length
= 2;
10870 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
10871 forced_insn_length
= 4;
10874 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
10878 insn_error
= _("Unrecognized opcode");
10882 /* For microMIPS instructions placed in a fixed-length branch delay slot
10883 we make up to two passes over the relevant fragment of the opcode
10884 table. First we try instructions that meet the delay slot's length
10885 requirement. If none matched, then we retry with the remaining ones
10886 and if one matches, then we use it and then issue an appropriate
10887 warning later on. */
10888 argsStart
= s
= str
+ end
;
10891 bfd_boolean delay_slot_ok
;
10892 bfd_boolean size_ok
;
10895 gas_assert (strcmp (insn
->name
, name
) == 0);
10897 ok
= is_opcode_valid (insn
);
10898 size_ok
= is_size_valid (insn
);
10899 delay_slot_ok
= is_delay_slot_valid (insn
);
10900 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
10903 wrong_delay_slot_insns
= TRUE
;
10905 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
10907 static char buf
[256];
10909 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
10914 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
10916 gas_assert (firstinsn
);
10917 need_delay_slot_ok
= FALSE
;
10927 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
10928 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10929 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10931 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
10932 8 * forced_insn_length
);
10938 create_insn (ip
, insn
);
10941 lastregno
= 0xffffffff;
10942 for (args
= insn
->args
;; ++args
)
10946 s
+= strspn (s
, " \t");
10950 case '\0': /* end of args */
10956 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10957 code) or 14 (for microMIPS code). */
10958 my_getExpression (&imm_expr
, s
);
10959 check_absolute_expr (ip
, &imm_expr
);
10960 if ((unsigned long) imm_expr
.X_add_number
!= 1
10961 && (unsigned long) imm_expr
.X_add_number
!= 3)
10963 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10964 (unsigned long) imm_expr
.X_add_number
);
10966 INSERT_OPERAND (mips_opts
.micromips
,
10967 BP
, *ip
, imm_expr
.X_add_number
);
10968 imm_expr
.X_op
= O_absent
;
10973 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10974 code) or 21 (for microMIPS code). */
10976 unsigned long mask
= (mips_opts
.micromips
10977 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
10979 my_getExpression (&imm_expr
, s
);
10980 check_absolute_expr (ip
, &imm_expr
);
10981 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10982 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10983 mask
, (unsigned long) imm_expr
.X_add_number
);
10984 INSERT_OPERAND (mips_opts
.micromips
,
10985 SA3
, *ip
, imm_expr
.X_add_number
);
10986 imm_expr
.X_op
= O_absent
;
10992 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10993 code) or 21 (for microMIPS code). */
10995 unsigned long mask
= (mips_opts
.micromips
10996 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
10998 my_getExpression (&imm_expr
, s
);
10999 check_absolute_expr (ip
, &imm_expr
);
11000 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11001 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11002 mask
, (unsigned long) imm_expr
.X_add_number
);
11003 INSERT_OPERAND (mips_opts
.micromips
,
11004 SA4
, *ip
, imm_expr
.X_add_number
);
11005 imm_expr
.X_op
= O_absent
;
11011 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
11012 code) or 16 (for microMIPS code). */
11014 unsigned long mask
= (mips_opts
.micromips
11015 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
11017 my_getExpression (&imm_expr
, s
);
11018 check_absolute_expr (ip
, &imm_expr
);
11019 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11020 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11021 mask
, (unsigned long) imm_expr
.X_add_number
);
11022 INSERT_OPERAND (mips_opts
.micromips
,
11023 IMM8
, *ip
, imm_expr
.X_add_number
);
11024 imm_expr
.X_op
= O_absent
;
11030 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11031 code) or 21 (for microMIPS code). */
11033 unsigned long mask
= (mips_opts
.micromips
11034 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
11036 my_getExpression (&imm_expr
, s
);
11037 check_absolute_expr (ip
, &imm_expr
);
11038 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11039 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11040 mask
, (unsigned long) imm_expr
.X_add_number
);
11041 INSERT_OPERAND (mips_opts
.micromips
,
11042 RS
, *ip
, imm_expr
.X_add_number
);
11043 imm_expr
.X_op
= O_absent
;
11048 case '7': /* Four DSP accumulators in bits 11,12. */
11049 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11050 && s
[3] >= '0' && s
[3] <= '3')
11052 regno
= s
[3] - '0';
11054 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
11058 as_bad (_("Invalid dsp acc register"));
11062 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11063 code) or 14 (for microMIPS code). */
11065 unsigned long mask
= (mips_opts
.micromips
11066 ? MICROMIPSOP_MASK_WRDSP
11069 my_getExpression (&imm_expr
, s
);
11070 check_absolute_expr (ip
, &imm_expr
);
11071 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11072 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11073 mask
, (unsigned long) imm_expr
.X_add_number
);
11074 INSERT_OPERAND (mips_opts
.micromips
,
11075 WRDSP
, *ip
, imm_expr
.X_add_number
);
11076 imm_expr
.X_op
= O_absent
;
11081 case '9': /* Four DSP accumulators in bits 21,22. */
11082 gas_assert (!mips_opts
.micromips
);
11083 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11084 && s
[3] >= '0' && s
[3] <= '3')
11086 regno
= s
[3] - '0';
11088 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
11092 as_bad (_("Invalid dsp acc register"));
11096 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11097 code) or 20 (for microMIPS code). */
11099 long mask
= (mips_opts
.micromips
11100 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
11102 my_getExpression (&imm_expr
, s
);
11103 check_absolute_expr (ip
, &imm_expr
);
11104 min_range
= -((mask
+ 1) >> 1);
11105 max_range
= ((mask
+ 1) >> 1) - 1;
11106 if (imm_expr
.X_add_number
< min_range
11107 || imm_expr
.X_add_number
> max_range
)
11108 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11109 (long) min_range
, (long) max_range
,
11110 (long) imm_expr
.X_add_number
);
11111 INSERT_OPERAND (mips_opts
.micromips
,
11112 DSPSFT
, *ip
, imm_expr
.X_add_number
);
11113 imm_expr
.X_op
= O_absent
;
11118 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11119 gas_assert (!mips_opts
.micromips
);
11120 my_getExpression (&imm_expr
, s
);
11121 check_absolute_expr (ip
, &imm_expr
);
11122 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
11124 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11126 (unsigned long) imm_expr
.X_add_number
);
11128 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
11129 imm_expr
.X_op
= O_absent
;
11133 case ':': /* DSP 7-bit signed immediate in bit 19. */
11134 gas_assert (!mips_opts
.micromips
);
11135 my_getExpression (&imm_expr
, s
);
11136 check_absolute_expr (ip
, &imm_expr
);
11137 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11138 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11139 if (imm_expr
.X_add_number
< min_range
||
11140 imm_expr
.X_add_number
> max_range
)
11142 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11143 (long) min_range
, (long) max_range
,
11144 (long) imm_expr
.X_add_number
);
11146 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11147 imm_expr
.X_op
= O_absent
;
11151 case '@': /* DSP 10-bit signed immediate in bit 16. */
11153 long mask
= (mips_opts
.micromips
11154 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11156 my_getExpression (&imm_expr
, s
);
11157 check_absolute_expr (ip
, &imm_expr
);
11158 min_range
= -((mask
+ 1) >> 1);
11159 max_range
= ((mask
+ 1) >> 1) - 1;
11160 if (imm_expr
.X_add_number
< min_range
11161 || imm_expr
.X_add_number
> max_range
)
11162 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11163 (long) min_range
, (long) max_range
,
11164 (long) imm_expr
.X_add_number
);
11165 INSERT_OPERAND (mips_opts
.micromips
,
11166 IMM10
, *ip
, imm_expr
.X_add_number
);
11167 imm_expr
.X_op
= O_absent
;
11172 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11173 gas_assert (mips_opts
.micromips
);
11174 my_getExpression (&imm_expr
, s
);
11175 check_absolute_expr (ip
, &imm_expr
);
11176 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11177 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11178 MICROMIPSOP_MASK_RD
,
11179 (unsigned long) imm_expr
.X_add_number
);
11180 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11181 imm_expr
.X_op
= O_absent
;
11185 case '!': /* MT usermode flag bit. */
11186 gas_assert (!mips_opts
.micromips
);
11187 my_getExpression (&imm_expr
, s
);
11188 check_absolute_expr (ip
, &imm_expr
);
11189 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11190 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11191 (unsigned long) imm_expr
.X_add_number
);
11192 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11193 imm_expr
.X_op
= O_absent
;
11197 case '$': /* MT load high flag bit. */
11198 gas_assert (!mips_opts
.micromips
);
11199 my_getExpression (&imm_expr
, s
);
11200 check_absolute_expr (ip
, &imm_expr
);
11201 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11202 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11203 (unsigned long) imm_expr
.X_add_number
);
11204 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11205 imm_expr
.X_op
= O_absent
;
11209 case '*': /* Four DSP accumulators in bits 18,19. */
11210 gas_assert (!mips_opts
.micromips
);
11211 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11212 s
[3] >= '0' && s
[3] <= '3')
11214 regno
= s
[3] - '0';
11216 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11220 as_bad (_("Invalid dsp/smartmips acc register"));
11223 case '&': /* Four DSP accumulators in bits 13,14. */
11224 gas_assert (!mips_opts
.micromips
);
11225 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11226 s
[3] >= '0' && s
[3] <= '3')
11228 regno
= s
[3] - '0';
11230 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11234 as_bad (_("Invalid dsp/smartmips acc register"));
11237 case '\\': /* 3-bit bit position. */
11239 unsigned long mask
= (mips_opts
.micromips
11240 ? MICROMIPSOP_MASK_3BITPOS
11241 : OP_MASK_3BITPOS
);
11243 my_getExpression (&imm_expr
, s
);
11244 check_absolute_expr (ip
, &imm_expr
);
11245 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11246 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11248 mask
, (unsigned long) imm_expr
.X_add_number
);
11249 INSERT_OPERAND (mips_opts
.micromips
,
11250 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11251 imm_expr
.X_op
= O_absent
;
11265 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11269 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11273 gas_assert (!mips_opts
.micromips
);
11274 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11278 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11284 /* Handle optional base register.
11285 Either the base register is omitted or
11286 we must have a left paren. */
11287 /* This is dependent on the next operand specifier
11288 is a base register specification. */
11289 gas_assert (args
[1] == 'b'
11290 || (mips_opts
.micromips
11292 && (args
[2] == 'l' || args
[2] == 'n'
11293 || args
[2] == 's' || args
[2] == 'a')));
11294 if (*s
== '\0' && args
[1] == 'b')
11296 /* Fall through. */
11298 case ')': /* These must match exactly. */
11303 case '[': /* These must match exactly. */
11305 gas_assert (!mips_opts
.micromips
);
11310 case '+': /* Opcode extension character. */
11313 case '1': /* UDI immediates. */
11317 gas_assert (!mips_opts
.micromips
);
11319 const struct mips_immed
*imm
= mips_immed
;
11321 while (imm
->type
&& imm
->type
!= *args
)
11325 my_getExpression (&imm_expr
, s
);
11326 check_absolute_expr (ip
, &imm_expr
);
11327 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11329 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11330 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11331 (unsigned long) imm_expr
.X_add_number
,
11332 (unsigned long) imm_expr
.X_add_number
);
11333 imm_expr
.X_add_number
&= imm
->mask
;
11335 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11337 imm_expr
.X_op
= O_absent
;
11342 case 'A': /* ins/ext position, becomes LSB. */
11351 my_getExpression (&imm_expr
, s
);
11352 check_absolute_expr (ip
, &imm_expr
);
11353 if ((unsigned long) imm_expr
.X_add_number
< limlo
11354 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11356 as_bad (_("Improper position (%lu)"),
11357 (unsigned long) imm_expr
.X_add_number
);
11358 imm_expr
.X_add_number
= limlo
;
11360 lastpos
= imm_expr
.X_add_number
;
11361 INSERT_OPERAND (mips_opts
.micromips
,
11362 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11363 imm_expr
.X_op
= O_absent
;
11367 case 'B': /* ins size, becomes MSB. */
11376 my_getExpression (&imm_expr
, s
);
11377 check_absolute_expr (ip
, &imm_expr
);
11378 /* Check for negative input so that small negative numbers
11379 will not succeed incorrectly. The checks against
11380 (pos+size) transitively check "size" itself,
11381 assuming that "pos" is reasonable. */
11382 if ((long) imm_expr
.X_add_number
< 0
11383 || ((unsigned long) imm_expr
.X_add_number
11385 || ((unsigned long) imm_expr
.X_add_number
11386 + lastpos
) > limhi
)
11388 as_bad (_("Improper insert size (%lu, position %lu)"),
11389 (unsigned long) imm_expr
.X_add_number
,
11390 (unsigned long) lastpos
);
11391 imm_expr
.X_add_number
= limlo
- lastpos
;
11393 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11394 lastpos
+ imm_expr
.X_add_number
- 1);
11395 imm_expr
.X_op
= O_absent
;
11399 case 'C': /* ext size, becomes MSBD. */
11415 my_getExpression (&imm_expr
, s
);
11416 check_absolute_expr (ip
, &imm_expr
);
11417 /* The checks against (pos+size) don't transitively check
11418 "size" itself, assuming that "pos" is reasonable.
11419 We also need to check the lower bound of "size". */
11420 if ((long) imm_expr
.X_add_number
< sizelo
11421 || ((unsigned long) imm_expr
.X_add_number
11423 || ((unsigned long) imm_expr
.X_add_number
11424 + lastpos
) > limhi
)
11426 as_bad (_("Improper extract size (%lu, position %lu)"),
11427 (unsigned long) imm_expr
.X_add_number
,
11428 (unsigned long) lastpos
);
11429 imm_expr
.X_add_number
= limlo
- lastpos
;
11431 INSERT_OPERAND (mips_opts
.micromips
,
11432 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11433 imm_expr
.X_op
= O_absent
;
11438 /* +D is for disassembly only; never match. */
11442 /* "+I" is like "I", except that imm2_expr is used. */
11443 my_getExpression (&imm2_expr
, s
);
11444 if (imm2_expr
.X_op
!= O_big
11445 && imm2_expr
.X_op
!= O_constant
)
11446 insn_error
= _("absolute expression required");
11447 if (HAVE_32BIT_GPRS
)
11448 normalize_constant_expr (&imm2_expr
);
11452 case 'T': /* Coprocessor register. */
11453 gas_assert (!mips_opts
.micromips
);
11454 /* +T is for disassembly only; never match. */
11457 case 't': /* Coprocessor register number. */
11458 gas_assert (!mips_opts
.micromips
);
11459 if (s
[0] == '$' && ISDIGIT (s
[1]))
11469 while (ISDIGIT (*s
));
11471 as_bad (_("Invalid register number (%d)"), regno
);
11474 INSERT_OPERAND (0, RT
, *ip
, regno
);
11479 as_bad (_("Invalid coprocessor 0 register number"));
11483 /* bbit[01] and bbit[01]32 bit index. Give error if index
11484 is not in the valid range. */
11485 gas_assert (!mips_opts
.micromips
);
11486 my_getExpression (&imm_expr
, s
);
11487 check_absolute_expr (ip
, &imm_expr
);
11488 if ((unsigned) imm_expr
.X_add_number
> 31)
11490 as_bad (_("Improper bit index (%lu)"),
11491 (unsigned long) imm_expr
.X_add_number
);
11492 imm_expr
.X_add_number
= 0;
11494 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11495 imm_expr
.X_op
= O_absent
;
11500 /* bbit[01] bit index when bbit is used but we generate
11501 bbit[01]32 because the index is over 32. Move to the
11502 next candidate if index is not in the valid range. */
11503 gas_assert (!mips_opts
.micromips
);
11504 my_getExpression (&imm_expr
, s
);
11505 check_absolute_expr (ip
, &imm_expr
);
11506 if ((unsigned) imm_expr
.X_add_number
< 32
11507 || (unsigned) imm_expr
.X_add_number
> 63)
11509 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11510 imm_expr
.X_op
= O_absent
;
11515 /* cins, cins32, exts and exts32 position field. Give error
11516 if it's not in the valid range. */
11517 gas_assert (!mips_opts
.micromips
);
11518 my_getExpression (&imm_expr
, s
);
11519 check_absolute_expr (ip
, &imm_expr
);
11520 if ((unsigned) imm_expr
.X_add_number
> 31)
11522 as_bad (_("Improper position (%lu)"),
11523 (unsigned long) imm_expr
.X_add_number
);
11524 imm_expr
.X_add_number
= 0;
11526 /* Make the pos explicit to simplify +S. */
11527 lastpos
= imm_expr
.X_add_number
+ 32;
11528 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11529 imm_expr
.X_op
= O_absent
;
11534 /* cins, cins32, exts and exts32 position field. Move to
11535 the next candidate if it's not in the valid range. */
11536 gas_assert (!mips_opts
.micromips
);
11537 my_getExpression (&imm_expr
, s
);
11538 check_absolute_expr (ip
, &imm_expr
);
11539 if ((unsigned) imm_expr
.X_add_number
< 32
11540 || (unsigned) imm_expr
.X_add_number
> 63)
11542 lastpos
= imm_expr
.X_add_number
;
11543 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11544 imm_expr
.X_op
= O_absent
;
11549 /* cins and exts length-minus-one field. */
11550 gas_assert (!mips_opts
.micromips
);
11551 my_getExpression (&imm_expr
, s
);
11552 check_absolute_expr (ip
, &imm_expr
);
11553 if ((unsigned long) imm_expr
.X_add_number
> 31)
11555 as_bad (_("Improper size (%lu)"),
11556 (unsigned long) imm_expr
.X_add_number
);
11557 imm_expr
.X_add_number
= 0;
11559 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11560 imm_expr
.X_op
= O_absent
;
11565 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11566 length-minus-one field. */
11567 gas_assert (!mips_opts
.micromips
);
11568 my_getExpression (&imm_expr
, s
);
11569 check_absolute_expr (ip
, &imm_expr
);
11570 if ((long) imm_expr
.X_add_number
< 0
11571 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11573 as_bad (_("Improper size (%lu)"),
11574 (unsigned long) imm_expr
.X_add_number
);
11575 imm_expr
.X_add_number
= 0;
11577 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11578 imm_expr
.X_op
= O_absent
;
11583 /* seqi/snei immediate field. */
11584 gas_assert (!mips_opts
.micromips
);
11585 my_getExpression (&imm_expr
, s
);
11586 check_absolute_expr (ip
, &imm_expr
);
11587 if ((long) imm_expr
.X_add_number
< -512
11588 || (long) imm_expr
.X_add_number
>= 512)
11590 as_bad (_("Improper immediate (%ld)"),
11591 (long) imm_expr
.X_add_number
);
11592 imm_expr
.X_add_number
= 0;
11594 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11595 imm_expr
.X_op
= O_absent
;
11599 case 'a': /* 8-bit signed offset in bit 6 */
11600 gas_assert (!mips_opts
.micromips
);
11601 my_getExpression (&imm_expr
, s
);
11602 check_absolute_expr (ip
, &imm_expr
);
11603 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11604 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11605 if (imm_expr
.X_add_number
< min_range
11606 || imm_expr
.X_add_number
> max_range
)
11608 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11609 (long) min_range
, (long) max_range
,
11610 (long) imm_expr
.X_add_number
);
11612 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11613 imm_expr
.X_op
= O_absent
;
11617 case 'b': /* 8-bit signed offset in bit 3 */
11618 gas_assert (!mips_opts
.micromips
);
11619 my_getExpression (&imm_expr
, s
);
11620 check_absolute_expr (ip
, &imm_expr
);
11621 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11622 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11623 if (imm_expr
.X_add_number
< min_range
11624 || imm_expr
.X_add_number
> max_range
)
11626 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11627 (long) min_range
, (long) max_range
,
11628 (long) imm_expr
.X_add_number
);
11630 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11631 imm_expr
.X_op
= O_absent
;
11635 case 'c': /* 9-bit signed offset in bit 6 */
11636 gas_assert (!mips_opts
.micromips
);
11637 my_getExpression (&imm_expr
, s
);
11638 check_absolute_expr (ip
, &imm_expr
);
11639 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11640 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11641 /* We check the offset range before adjusted. */
11644 if (imm_expr
.X_add_number
< min_range
11645 || imm_expr
.X_add_number
> max_range
)
11647 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11648 (long) min_range
, (long) max_range
,
11649 (long) imm_expr
.X_add_number
);
11651 if (imm_expr
.X_add_number
& 0xf)
11653 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11654 (long) imm_expr
.X_add_number
);
11656 /* Right shift 4 bits to adjust the offset operand. */
11657 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11658 imm_expr
.X_add_number
>> 4);
11659 imm_expr
.X_op
= O_absent
;
11664 gas_assert (!mips_opts
.micromips
);
11665 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11667 if (regno
== AT
&& mips_opts
.at
)
11669 if (mips_opts
.at
== ATREG
)
11670 as_warn (_("used $at without \".set noat\""));
11672 as_warn (_("used $%u with \".set at=$%u\""),
11673 regno
, mips_opts
.at
);
11675 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11679 gas_assert (!mips_opts
.micromips
);
11680 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11682 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11686 as_bad (_("Internal error: bad %s opcode "
11687 "(unknown extension operand type `+%c'): %s %s"),
11688 mips_opts
.micromips
? "microMIPS" : "MIPS",
11689 *args
, insn
->name
, insn
->args
);
11690 /* Further processing is fruitless. */
11695 case '.': /* 10-bit offset. */
11696 gas_assert (mips_opts
.micromips
);
11697 case '~': /* 12-bit offset. */
11699 int shift
= *args
== '.' ? 9 : 11;
11702 /* Check whether there is only a single bracketed expression
11703 left. If so, it must be the base register and the
11704 constant must be zero. */
11705 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11708 /* If this value won't fit into the offset, then go find
11709 a macro that will generate a 16- or 32-bit offset code
11711 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11712 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11713 || imm_expr
.X_add_number
>= 1 << shift
11714 || imm_expr
.X_add_number
< -1 << shift
))
11717 imm_expr
.X_op
= O_absent
;
11721 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11723 INSERT_OPERAND (mips_opts
.micromips
,
11724 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11725 imm_expr
.X_op
= O_absent
;
11730 case '<': /* must be at least one digit */
11732 * According to the manual, if the shift amount is greater
11733 * than 31 or less than 0, then the shift amount should be
11734 * mod 32. In reality the mips assembler issues an error.
11735 * We issue a warning and mask out all but the low 5 bits.
11737 my_getExpression (&imm_expr
, s
);
11738 check_absolute_expr (ip
, &imm_expr
);
11739 if ((unsigned long) imm_expr
.X_add_number
> 31)
11740 as_warn (_("Improper shift amount (%lu)"),
11741 (unsigned long) imm_expr
.X_add_number
);
11742 INSERT_OPERAND (mips_opts
.micromips
,
11743 SHAMT
, *ip
, imm_expr
.X_add_number
);
11744 imm_expr
.X_op
= O_absent
;
11748 case '>': /* shift amount minus 32 */
11749 my_getExpression (&imm_expr
, s
);
11750 check_absolute_expr (ip
, &imm_expr
);
11751 if ((unsigned long) imm_expr
.X_add_number
< 32
11752 || (unsigned long) imm_expr
.X_add_number
> 63)
11754 INSERT_OPERAND (mips_opts
.micromips
,
11755 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11756 imm_expr
.X_op
= O_absent
;
11760 case 'k': /* CACHE code. */
11761 case 'h': /* PREFX code. */
11762 case '1': /* SYNC type. */
11763 my_getExpression (&imm_expr
, s
);
11764 check_absolute_expr (ip
, &imm_expr
);
11765 if ((unsigned long) imm_expr
.X_add_number
> 31)
11766 as_warn (_("Invalid value for `%s' (%lu)"),
11768 (unsigned long) imm_expr
.X_add_number
);
11772 if (mips_fix_cn63xxp1
11773 && !mips_opts
.micromips
11774 && strcmp ("pref", insn
->name
) == 0)
11775 switch (imm_expr
.X_add_number
)
11784 case 31: /* These are ok. */
11787 default: /* The rest must be changed to 28. */
11788 imm_expr
.X_add_number
= 28;
11791 INSERT_OPERAND (mips_opts
.micromips
,
11792 CACHE
, *ip
, imm_expr
.X_add_number
);
11795 INSERT_OPERAND (mips_opts
.micromips
,
11796 PREFX
, *ip
, imm_expr
.X_add_number
);
11799 INSERT_OPERAND (mips_opts
.micromips
,
11800 STYPE
, *ip
, imm_expr
.X_add_number
);
11803 imm_expr
.X_op
= O_absent
;
11807 case 'c': /* BREAK code. */
11809 unsigned long mask
= (mips_opts
.micromips
11810 ? MICROMIPSOP_MASK_CODE
11813 my_getExpression (&imm_expr
, s
);
11814 check_absolute_expr (ip
, &imm_expr
);
11815 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11816 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11818 mask
, (unsigned long) imm_expr
.X_add_number
);
11819 INSERT_OPERAND (mips_opts
.micromips
,
11820 CODE
, *ip
, imm_expr
.X_add_number
);
11821 imm_expr
.X_op
= O_absent
;
11826 case 'q': /* Lower BREAK code. */
11828 unsigned long mask
= (mips_opts
.micromips
11829 ? MICROMIPSOP_MASK_CODE2
11832 my_getExpression (&imm_expr
, s
);
11833 check_absolute_expr (ip
, &imm_expr
);
11834 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11835 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11837 mask
, (unsigned long) imm_expr
.X_add_number
);
11838 INSERT_OPERAND (mips_opts
.micromips
,
11839 CODE2
, *ip
, imm_expr
.X_add_number
);
11840 imm_expr
.X_op
= O_absent
;
11845 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11847 unsigned long mask
= (mips_opts
.micromips
11848 ? MICROMIPSOP_MASK_CODE10
11851 my_getExpression (&imm_expr
, s
);
11852 check_absolute_expr (ip
, &imm_expr
);
11853 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11854 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11856 mask
, (unsigned long) imm_expr
.X_add_number
);
11857 if (mips_opts
.micromips
)
11858 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
11860 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
11861 imm_expr
.X_op
= O_absent
;
11866 case 'C': /* 25- or 23-bit coprocessor code. */
11868 unsigned long mask
= (mips_opts
.micromips
11869 ? MICROMIPSOP_MASK_COPZ
11872 my_getExpression (&imm_expr
, s
);
11873 check_absolute_expr (ip
, &imm_expr
);
11874 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11875 as_warn (_("Coproccesor code > %u bits (%lu)"),
11876 mips_opts
.micromips
? 23U : 25U,
11877 (unsigned long) imm_expr
.X_add_number
);
11878 INSERT_OPERAND (mips_opts
.micromips
,
11879 COPZ
, *ip
, imm_expr
.X_add_number
);
11880 imm_expr
.X_op
= O_absent
;
11885 case 'J': /* 19-bit WAIT code. */
11886 gas_assert (!mips_opts
.micromips
);
11887 my_getExpression (&imm_expr
, s
);
11888 check_absolute_expr (ip
, &imm_expr
);
11889 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
11891 as_warn (_("Illegal 19-bit code (%lu)"),
11892 (unsigned long) imm_expr
.X_add_number
);
11893 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
11895 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
11896 imm_expr
.X_op
= O_absent
;
11900 case 'P': /* Performance register. */
11901 gas_assert (!mips_opts
.micromips
);
11902 my_getExpression (&imm_expr
, s
);
11903 check_absolute_expr (ip
, &imm_expr
);
11904 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
11905 as_warn (_("Invalid performance register (%lu)"),
11906 (unsigned long) imm_expr
.X_add_number
);
11907 if (imm_expr
.X_add_number
!= 0 && mips_opts
.arch
== CPU_R5900
11908 && (!strcmp(insn
->name
,"mfps") || !strcmp(insn
->name
,"mtps")))
11909 as_warn (_("Invalid performance register (%lu)"),
11910 (unsigned long) imm_expr
.X_add_number
);
11911 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
11912 imm_expr
.X_op
= O_absent
;
11916 case 'G': /* Coprocessor destination register. */
11918 unsigned long opcode
= ip
->insn_opcode
;
11919 unsigned long mask
;
11920 unsigned int types
;
11923 if (mips_opts
.micromips
)
11925 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
11926 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
11927 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
11931 case 0x000000fc: /* mfc0 */
11932 case 0x000002fc: /* mtc0 */
11933 case 0x580000fc: /* dmfc0 */
11934 case 0x580002fc: /* dmtc0 */
11944 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
11945 cop0
= opcode
== OP_OP_COP0
;
11947 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
11948 ok
= reg_lookup (&s
, types
, ®no
);
11949 if (mips_opts
.micromips
)
11950 INSERT_OPERAND (1, RS
, *ip
, regno
);
11952 INSERT_OPERAND (0, RD
, *ip
, regno
);
11961 case 'y': /* ALNV.PS source register. */
11962 gas_assert (mips_opts
.micromips
);
11964 case 'x': /* Ignore register name. */
11965 case 'U': /* Destination register (CLO/CLZ). */
11966 case 'g': /* Coprocessor destination register. */
11967 gas_assert (!mips_opts
.micromips
);
11968 case 'b': /* Base register. */
11969 case 'd': /* Destination register. */
11970 case 's': /* Source register. */
11971 case 't': /* Target register. */
11972 case 'r': /* Both target and source. */
11973 case 'v': /* Both dest and source. */
11974 case 'w': /* Both dest and target. */
11975 case 'E': /* Coprocessor target register. */
11976 case 'K': /* RDHWR destination register. */
11977 case 'z': /* Must be zero register. */
11980 if (*args
== 'E' || *args
== 'K')
11981 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
11984 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
11985 if (regno
== AT
&& mips_opts
.at
)
11987 if (mips_opts
.at
== ATREG
)
11988 as_warn (_("Used $at without \".set noat\""));
11990 as_warn (_("Used $%u with \".set at=$%u\""),
11991 regno
, mips_opts
.at
);
12001 if (c
== 'r' || c
== 'v' || c
== 'w')
12008 /* 'z' only matches $0. */
12009 if (c
== 'z' && regno
!= 0)
12012 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12014 if (regno
== lastregno
)
12017 = _("Source and destination must be different");
12020 if (regno
== 31 && lastregno
== 0xffffffff)
12023 = _("A destination register must be supplied");
12027 /* Now that we have assembled one operand, we use the args
12028 string to figure out where it goes in the instruction. */
12035 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
12039 if (mips_opts
.micromips
)
12040 INSERT_OPERAND (1, RS
, *ip
, regno
);
12042 INSERT_OPERAND (0, RD
, *ip
, regno
);
12047 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
12051 gas_assert (!mips_opts
.micromips
);
12052 INSERT_OPERAND (0, RD
, *ip
, regno
);
12053 INSERT_OPERAND (0, RT
, *ip
, regno
);
12059 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
12063 gas_assert (mips_opts
.micromips
);
12064 INSERT_OPERAND (1, RS3
, *ip
, regno
);
12068 /* This case exists because on the r3000 trunc
12069 expands into a macro which requires a gp
12070 register. On the r6000 or r4000 it is
12071 assembled into a single instruction which
12072 ignores the register. Thus the insn version
12073 is MIPS_ISA2 and uses 'x', and the macro
12074 version is MIPS_ISA1 and uses 't'. */
12078 /* This case is for the div instruction, which
12079 acts differently if the destination argument
12080 is $0. This only matches $0, and is checked
12081 outside the switch. */
12091 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12095 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12100 case 'O': /* MDMX alignment immediate constant. */
12101 gas_assert (!mips_opts
.micromips
);
12102 my_getExpression (&imm_expr
, s
);
12103 check_absolute_expr (ip
, &imm_expr
);
12104 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
12105 as_warn (_("Improper align amount (%ld), using low bits"),
12106 (long) imm_expr
.X_add_number
);
12107 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
12108 imm_expr
.X_op
= O_absent
;
12112 case 'Q': /* MDMX vector, element sel, or const. */
12115 /* MDMX Immediate. */
12116 gas_assert (!mips_opts
.micromips
);
12117 my_getExpression (&imm_expr
, s
);
12118 check_absolute_expr (ip
, &imm_expr
);
12119 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
12120 as_warn (_("Invalid MDMX Immediate (%ld)"),
12121 (long) imm_expr
.X_add_number
);
12122 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
12123 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12124 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
12126 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
12127 imm_expr
.X_op
= O_absent
;
12131 /* Not MDMX Immediate. Fall through. */
12132 case 'X': /* MDMX destination register. */
12133 case 'Y': /* MDMX source register. */
12134 case 'Z': /* MDMX target register. */
12137 gas_assert (!mips_opts
.micromips
);
12138 case 'D': /* Floating point destination register. */
12139 case 'S': /* Floating point source register. */
12140 case 'T': /* Floating point target register. */
12141 case 'R': /* Floating point source register. */
12145 || (mips_opts
.ase_mdmx
12146 && (ip
->insn_mo
->pinfo
& FP_D
)
12147 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12148 | INSN_COPROC_MEMORY_DELAY
12149 | INSN_LOAD_COPROC_DELAY
12150 | INSN_LOAD_MEMORY_DELAY
12151 | INSN_STORE_MEMORY
))))
12152 rtype
|= RTYPE_VEC
;
12154 if (reg_lookup (&s
, rtype
, ®no
))
12156 if ((regno
& 1) != 0
12158 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12159 as_warn (_("Float register should be even, was %d"),
12167 if (c
== 'V' || c
== 'W')
12178 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12184 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12188 /* This is like 'Z', but also needs to fix the MDMX
12189 vector/scalar select bits. Note that the
12190 scalar immediate case is handled above. */
12193 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12194 int max_el
= (is_qh
? 3 : 7);
12196 my_getExpression(&imm_expr
, s
);
12197 check_absolute_expr (ip
, &imm_expr
);
12199 if (imm_expr
.X_add_number
> max_el
)
12200 as_bad (_("Bad element selector %ld"),
12201 (long) imm_expr
.X_add_number
);
12202 imm_expr
.X_add_number
&= max_el
;
12203 ip
->insn_opcode
|= (imm_expr
.X_add_number
12206 imm_expr
.X_op
= O_absent
;
12208 as_warn (_("Expecting ']' found '%s'"), s
);
12214 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12215 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12218 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12221 /* Fall through. */
12225 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12229 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12239 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12243 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12249 my_getExpression (&imm_expr
, s
);
12250 if (imm_expr
.X_op
!= O_big
12251 && imm_expr
.X_op
!= O_constant
)
12252 insn_error
= _("absolute expression required");
12253 if (HAVE_32BIT_GPRS
)
12254 normalize_constant_expr (&imm_expr
);
12259 my_getExpression (&offset_expr
, s
);
12260 normalize_address_expr (&offset_expr
);
12261 *imm_reloc
= BFD_RELOC_32
;
12274 unsigned char temp
[8];
12276 unsigned int length
;
12281 /* These only appear as the last operand in an
12282 instruction, and every instruction that accepts
12283 them in any variant accepts them in all variants.
12284 This means we don't have to worry about backing out
12285 any changes if the instruction does not match.
12287 The difference between them is the size of the
12288 floating point constant and where it goes. For 'F'
12289 and 'L' the constant is 64 bits; for 'f' and 'l' it
12290 is 32 bits. Where the constant is placed is based
12291 on how the MIPS assembler does things:
12294 f -- immediate value
12297 The .lit4 and .lit8 sections are only used if
12298 permitted by the -G argument.
12300 The code below needs to know whether the target register
12301 is 32 or 64 bits wide. It relies on the fact 'f' and
12302 'F' are used with GPR-based instructions and 'l' and
12303 'L' are used with FPR-based instructions. */
12305 f64
= *args
== 'F' || *args
== 'L';
12306 using_gprs
= *args
== 'F' || *args
== 'f';
12308 save_in
= input_line_pointer
;
12309 input_line_pointer
= s
;
12310 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12312 s
= input_line_pointer
;
12313 input_line_pointer
= save_in
;
12314 if (err
!= NULL
&& *err
!= '\0')
12316 as_bad (_("Bad floating point constant: %s"), err
);
12317 memset (temp
, '\0', sizeof temp
);
12318 length
= f64
? 8 : 4;
12321 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12325 && (g_switch_value
< 4
12326 || (temp
[0] == 0 && temp
[1] == 0)
12327 || (temp
[2] == 0 && temp
[3] == 0))))
12329 imm_expr
.X_op
= O_constant
;
12330 if (!target_big_endian
)
12331 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12333 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12335 else if (length
> 4
12336 && !mips_disable_float_construction
12337 /* Constants can only be constructed in GPRs and
12338 copied to FPRs if the GPRs are at least as wide
12339 as the FPRs. Force the constant into memory if
12340 we are using 64-bit FPRs but the GPRs are only
12343 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12344 && ((temp
[0] == 0 && temp
[1] == 0)
12345 || (temp
[2] == 0 && temp
[3] == 0))
12346 && ((temp
[4] == 0 && temp
[5] == 0)
12347 || (temp
[6] == 0 && temp
[7] == 0)))
12349 /* The value is simple enough to load with a couple of
12350 instructions. If using 32-bit registers, set
12351 imm_expr to the high order 32 bits and offset_expr to
12352 the low order 32 bits. Otherwise, set imm_expr to
12353 the entire 64 bit constant. */
12354 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12356 imm_expr
.X_op
= O_constant
;
12357 offset_expr
.X_op
= O_constant
;
12358 if (!target_big_endian
)
12360 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12361 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12365 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12366 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12368 if (offset_expr
.X_add_number
== 0)
12369 offset_expr
.X_op
= O_absent
;
12371 else if (sizeof (imm_expr
.X_add_number
) > 4)
12373 imm_expr
.X_op
= O_constant
;
12374 if (!target_big_endian
)
12375 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12377 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12381 imm_expr
.X_op
= O_big
;
12382 imm_expr
.X_add_number
= 4;
12383 if (!target_big_endian
)
12385 generic_bignum
[0] = bfd_getl16 (temp
);
12386 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12387 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12388 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12392 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12393 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12394 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12395 generic_bignum
[3] = bfd_getb16 (temp
);
12401 const char *newname
;
12404 /* Switch to the right section. */
12406 subseg
= now_subseg
;
12409 default: /* unused default case avoids warnings. */
12411 newname
= RDATA_SECTION_NAME
;
12412 if (g_switch_value
>= 8)
12416 newname
= RDATA_SECTION_NAME
;
12419 gas_assert (g_switch_value
>= 4);
12423 new_seg
= subseg_new (newname
, (subsegT
) 0);
12425 bfd_set_section_flags (stdoutput
, new_seg
,
12430 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12431 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12432 record_alignment (new_seg
, 4);
12434 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12435 if (seg
== now_seg
)
12436 as_bad (_("Can't use floating point insn in this section"));
12438 /* Set the argument to the current address in the
12440 offset_expr
.X_op
= O_symbol
;
12441 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12442 offset_expr
.X_add_number
= 0;
12444 /* Put the floating point number into the section. */
12445 p
= frag_more ((int) length
);
12446 memcpy (p
, temp
, length
);
12448 /* Switch back to the original section. */
12449 subseg_set (seg
, subseg
);
12454 case 'i': /* 16-bit unsigned immediate. */
12455 case 'j': /* 16-bit signed immediate. */
12456 *imm_reloc
= BFD_RELOC_LO16
;
12457 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12460 offsetT minval
, maxval
;
12462 more
= (insn
+ 1 < past
12463 && strcmp (insn
->name
, insn
[1].name
) == 0);
12465 /* If the expression was written as an unsigned number,
12466 only treat it as signed if there are no more
12470 && sizeof (imm_expr
.X_add_number
) <= 4
12471 && imm_expr
.X_op
== O_constant
12472 && imm_expr
.X_add_number
< 0
12473 && imm_expr
.X_unsigned
12474 && HAVE_64BIT_GPRS
)
12477 /* For compatibility with older assemblers, we accept
12478 0x8000-0xffff as signed 16-bit numbers when only
12479 signed numbers are allowed. */
12481 minval
= 0, maxval
= 0xffff;
12483 minval
= -0x8000, maxval
= 0x7fff;
12485 minval
= -0x8000, maxval
= 0xffff;
12487 if (imm_expr
.X_op
!= O_constant
12488 || imm_expr
.X_add_number
< minval
12489 || imm_expr
.X_add_number
> maxval
)
12493 if (imm_expr
.X_op
== O_constant
12494 || imm_expr
.X_op
== O_big
)
12495 as_bad (_("Expression out of range"));
12501 case 'o': /* 16-bit offset. */
12502 offset_reloc
[0] = BFD_RELOC_LO16
;
12503 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12504 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12506 /* Check whether there is only a single bracketed expression
12507 left. If so, it must be the base register and the
12508 constant must be zero. */
12509 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12511 offset_expr
.X_op
= O_constant
;
12512 offset_expr
.X_add_number
= 0;
12516 /* If this value won't fit into a 16 bit offset, then go
12517 find a macro that will generate the 32 bit offset
12519 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12520 && (offset_expr
.X_op
!= O_constant
12521 || offset_expr
.X_add_number
>= 0x8000
12522 || offset_expr
.X_add_number
< -0x8000))
12528 case 'p': /* PC-relative offset. */
12529 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12530 my_getExpression (&offset_expr
, s
);
12534 case 'u': /* Upper 16 bits. */
12535 *imm_reloc
= BFD_RELOC_LO16
;
12536 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12537 && imm_expr
.X_op
== O_constant
12538 && (imm_expr
.X_add_number
< 0
12539 || imm_expr
.X_add_number
>= 0x10000))
12540 as_bad (_("lui expression (%lu) not in range 0..65535"),
12541 (unsigned long) imm_expr
.X_add_number
);
12545 case 'a': /* 26-bit address. */
12546 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12547 my_getExpression (&offset_expr
, s
);
12551 case 'N': /* 3-bit branch condition code. */
12552 case 'M': /* 3-bit compare condition code. */
12554 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12555 rtype
|= RTYPE_FCC
;
12556 if (!reg_lookup (&s
, rtype
, ®no
))
12558 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12559 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12560 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12561 && (regno
& 1) != 0)
12562 as_warn (_("Condition code register should be even for %s, "
12565 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12566 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12567 && (regno
& 3) != 0)
12568 as_warn (_("Condition code register should be 0 or 4 for %s, "
12572 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12574 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12578 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12589 while (ISDIGIT (*s
));
12592 c
= 8; /* Invalid sel value. */
12595 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12596 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12600 gas_assert (!mips_opts
.micromips
);
12601 /* Must be at least one digit. */
12602 my_getExpression (&imm_expr
, s
);
12603 check_absolute_expr (ip
, &imm_expr
);
12605 if ((unsigned long) imm_expr
.X_add_number
12606 > (unsigned long) OP_MASK_VECBYTE
)
12608 as_bad (_("bad byte vector index (%ld)"),
12609 (long) imm_expr
.X_add_number
);
12610 imm_expr
.X_add_number
= 0;
12613 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12614 imm_expr
.X_op
= O_absent
;
12619 gas_assert (!mips_opts
.micromips
);
12620 my_getExpression (&imm_expr
, s
);
12621 check_absolute_expr (ip
, &imm_expr
);
12623 if ((unsigned long) imm_expr
.X_add_number
12624 > (unsigned long) OP_MASK_VECALIGN
)
12626 as_bad (_("bad byte vector index (%ld)"),
12627 (long) imm_expr
.X_add_number
);
12628 imm_expr
.X_add_number
= 0;
12631 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12632 imm_expr
.X_op
= O_absent
;
12636 case 'm': /* Opcode extension character. */
12637 gas_assert (mips_opts
.micromips
);
12642 if (strncmp (s
, "$pc", 3) == 0)
12670 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12671 if (regno
== AT
&& mips_opts
.at
)
12673 if (mips_opts
.at
== ATREG
)
12674 as_warn (_("Used $at without \".set noat\""));
12676 as_warn (_("Used $%u with \".set at=$%u\""),
12677 regno
, mips_opts
.at
);
12683 gas_assert (args
[1] == ',');
12689 gas_assert (args
[1] == ',');
12691 continue; /* Nothing to do. */
12697 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12699 if (regno
== lastregno
)
12702 = _("Source and destination must be different");
12705 if (regno
== 31 && lastregno
== 0xffffffff)
12708 = _("A destination register must be supplied");
12719 gas_assert (args
[1] == ',');
12726 gas_assert (args
[1] == ',');
12729 continue; /* Nothing to do. */
12733 /* Make sure regno is the same as lastregno. */
12734 if (c
== 't' && regno
!= lastregno
)
12737 /* Make sure regno is the same as destregno. */
12738 if (c
== 'x' && regno
!= destregno
)
12741 /* We need to save regno, before regno maps to the
12742 microMIPS register encoding. */
12752 regno
= ILLEGAL_REG
;
12756 regno
= mips32_to_micromips_reg_b_map
[regno
];
12760 regno
= mips32_to_micromips_reg_c_map
[regno
];
12764 regno
= mips32_to_micromips_reg_d_map
[regno
];
12768 regno
= mips32_to_micromips_reg_e_map
[regno
];
12772 regno
= mips32_to_micromips_reg_f_map
[regno
];
12776 regno
= mips32_to_micromips_reg_g_map
[regno
];
12780 regno
= mips32_to_micromips_reg_h_map
[regno
];
12784 switch (EXTRACT_OPERAND (1, MI
, *ip
))
12789 else if (regno
== 22)
12791 else if (regno
== 5)
12793 else if (regno
== 6)
12795 else if (regno
== 7)
12798 regno
= ILLEGAL_REG
;
12804 else if (regno
== 7)
12807 regno
= ILLEGAL_REG
;
12814 regno
= ILLEGAL_REG
;
12818 regno
= ILLEGAL_REG
;
12824 regno
= mips32_to_micromips_reg_l_map
[regno
];
12828 regno
= mips32_to_micromips_reg_m_map
[regno
];
12832 regno
= mips32_to_micromips_reg_n_map
[regno
];
12836 regno
= mips32_to_micromips_reg_q_map
[regno
];
12841 regno
= ILLEGAL_REG
;
12846 regno
= ILLEGAL_REG
;
12851 regno
= ILLEGAL_REG
;
12854 case 'j': /* Do nothing. */
12864 if (regno
== ILLEGAL_REG
)
12870 INSERT_OPERAND (1, MB
, *ip
, regno
);
12874 INSERT_OPERAND (1, MC
, *ip
, regno
);
12878 INSERT_OPERAND (1, MD
, *ip
, regno
);
12882 INSERT_OPERAND (1, ME
, *ip
, regno
);
12886 INSERT_OPERAND (1, MF
, *ip
, regno
);
12890 INSERT_OPERAND (1, MG
, *ip
, regno
);
12894 INSERT_OPERAND (1, MH
, *ip
, regno
);
12898 INSERT_OPERAND (1, MI
, *ip
, regno
);
12902 INSERT_OPERAND (1, MJ
, *ip
, regno
);
12906 INSERT_OPERAND (1, ML
, *ip
, regno
);
12910 INSERT_OPERAND (1, MM
, *ip
, regno
);
12914 INSERT_OPERAND (1, MN
, *ip
, regno
);
12918 INSERT_OPERAND (1, MP
, *ip
, regno
);
12922 INSERT_OPERAND (1, MQ
, *ip
, regno
);
12925 case 'a': /* Do nothing. */
12926 case 's': /* Do nothing. */
12927 case 't': /* Do nothing. */
12928 case 'x': /* Do nothing. */
12929 case 'y': /* Do nothing. */
12930 case 'z': /* Do nothing. */
12940 bfd_reloc_code_real_type r
[3];
12944 /* Check whether there is only a single bracketed
12945 expression left. If so, it must be the base register
12946 and the constant must be zero. */
12947 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12949 INSERT_OPERAND (1, IMMA
, *ip
, 0);
12953 if (my_getSmallExpression (&ep
, r
, s
) > 0
12954 || !expr_const_in_range (&ep
, -64, 64, 2))
12957 imm
= ep
.X_add_number
>> 2;
12958 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
12965 bfd_reloc_code_real_type r
[3];
12969 if (my_getSmallExpression (&ep
, r
, s
) > 0
12970 || ep
.X_op
!= O_constant
)
12973 for (imm
= 0; imm
< 8; imm
++)
12974 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
12979 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
12986 bfd_reloc_code_real_type r
[3];
12990 if (my_getSmallExpression (&ep
, r
, s
) > 0
12991 || ep
.X_op
!= O_constant
)
12994 for (imm
= 0; imm
< 16; imm
++)
12995 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
13000 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
13005 case 'D': /* pc relative offset */
13006 case 'E': /* pc relative offset */
13007 my_getExpression (&offset_expr
, s
);
13008 if (offset_expr
.X_op
== O_register
)
13011 if (!forced_insn_length
)
13012 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13014 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
13016 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
13022 bfd_reloc_code_real_type r
[3];
13026 if (my_getSmallExpression (&ep
, r
, s
) > 0
13027 || !expr_const_in_range (&ep
, 0, 16, 0))
13030 imm
= ep
.X_add_number
;
13031 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
13038 bfd_reloc_code_real_type r
[3];
13042 /* Check whether there is only a single bracketed
13043 expression left. If so, it must be the base register
13044 and the constant must be zero. */
13045 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13047 INSERT_OPERAND (1, IMMG
, *ip
, 0);
13051 if (my_getSmallExpression (&ep
, r
, s
) > 0
13052 || !expr_const_in_range (&ep
, -1, 15, 0))
13055 imm
= ep
.X_add_number
& 15;
13056 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
13063 bfd_reloc_code_real_type r
[3];
13067 /* Check whether there is only a single bracketed
13068 expression left. If so, it must be the base register
13069 and the constant must be zero. */
13070 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13072 INSERT_OPERAND (1, IMMH
, *ip
, 0);
13076 if (my_getSmallExpression (&ep
, r
, s
) > 0
13077 || !expr_const_in_range (&ep
, 0, 16, 1))
13080 imm
= ep
.X_add_number
>> 1;
13081 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
13088 bfd_reloc_code_real_type r
[3];
13092 if (my_getSmallExpression (&ep
, r
, s
) > 0
13093 || !expr_const_in_range (&ep
, -1, 127, 0))
13096 imm
= ep
.X_add_number
& 127;
13097 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
13104 bfd_reloc_code_real_type r
[3];
13108 /* Check whether there is only a single bracketed
13109 expression left. If so, it must be the base register
13110 and the constant must be zero. */
13111 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13113 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
13117 if (my_getSmallExpression (&ep
, r
, s
) > 0
13118 || !expr_const_in_range (&ep
, 0, 16, 2))
13121 imm
= ep
.X_add_number
>> 2;
13122 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
13129 bfd_reloc_code_real_type r
[3];
13133 /* Check whether there is only a single bracketed
13134 expression left. If so, it must be the base register
13135 and the constant must be zero. */
13136 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13138 INSERT_OPERAND (1, IMML
, *ip
, 0);
13142 if (my_getSmallExpression (&ep
, r
, s
) > 0
13143 || !expr_const_in_range (&ep
, 0, 16, 0))
13146 imm
= ep
.X_add_number
;
13147 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13154 bfd_reloc_code_real_type r
[3];
13158 if (my_getSmallExpression (&ep
, r
, s
) > 0
13159 || !expr_const_in_range (&ep
, 1, 9, 0))
13162 imm
= ep
.X_add_number
& 7;
13163 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13168 case 'N': /* Register list for lwm and swm. */
13170 /* A comma-separated list of registers and/or
13171 dash-separated contiguous ranges including
13172 both ra and a set of one or more registers
13173 starting at s0 up to s3 which have to be
13180 and any permutations of these. */
13181 unsigned int reglist
;
13184 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13187 if ((reglist
& 0xfff1ffff) != 0x80010000)
13190 reglist
= (reglist
>> 17) & 7;
13192 if ((reglist
& -reglist
) != reglist
)
13195 imm
= ffs (reglist
) - 1;
13196 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13200 case 'O': /* sdbbp 4-bit code. */
13202 bfd_reloc_code_real_type r
[3];
13206 if (my_getSmallExpression (&ep
, r
, s
) > 0
13207 || !expr_const_in_range (&ep
, 0, 16, 0))
13210 imm
= ep
.X_add_number
;
13211 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13218 bfd_reloc_code_real_type r
[3];
13222 if (my_getSmallExpression (&ep
, r
, s
) > 0
13223 || !expr_const_in_range (&ep
, 0, 32, 2))
13226 imm
= ep
.X_add_number
>> 2;
13227 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13234 bfd_reloc_code_real_type r
[3];
13238 if (my_getSmallExpression (&ep
, r
, s
) > 0
13239 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13242 imm
= ep
.X_add_number
>> 2;
13243 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13250 bfd_reloc_code_real_type r
[3];
13254 /* Check whether there is only a single bracketed
13255 expression left. If so, it must be the base register
13256 and the constant must be zero. */
13257 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13259 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13263 if (my_getSmallExpression (&ep
, r
, s
) > 0
13264 || !expr_const_in_range (&ep
, 0, 32, 2))
13267 imm
= ep
.X_add_number
>> 2;
13268 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13275 bfd_reloc_code_real_type r
[3];
13279 if (my_getSmallExpression (&ep
, r
, s
) > 0
13280 || !expr_const_in_range (&ep
, 0, 64, 2))
13283 imm
= ep
.X_add_number
>> 2;
13284 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13291 bfd_reloc_code_real_type r
[3];
13295 if (my_getSmallExpression (&ep
, r
, s
) > 0
13296 || !expr_const_in_range (&ep
, -8, 8, 0))
13299 imm
= ep
.X_add_number
;
13300 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13307 bfd_reloc_code_real_type r
[3];
13311 if (my_getSmallExpression (&ep
, r
, s
) > 0
13312 || expr_const_in_range (&ep
, -2, 2, 2)
13313 || !expr_const_in_range (&ep
, -258, 258, 2))
13316 imm
= ep
.X_add_number
>> 2;
13317 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13318 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13325 bfd_reloc_code_real_type r
[3];
13328 if (my_getSmallExpression (&ep
, r
, s
) > 0
13329 || !expr_const_in_range (&ep
, 0, 1, 0))
13336 as_bad (_("Internal error: bad microMIPS opcode "
13337 "(unknown extension operand type `m%c'): %s %s"),
13338 *args
, insn
->name
, insn
->args
);
13339 /* Further processing is fruitless. */
13344 case 'n': /* Register list for 32-bit lwm and swm. */
13345 gas_assert (mips_opts
.micromips
);
13347 /* A comma-separated list of registers and/or
13348 dash-separated contiguous ranges including
13349 at least one of ra and a set of one or more
13350 registers starting at s0 up to s7 and then
13351 s8 which have to be consecutive, e.g.:
13359 and any permutations of these. */
13360 unsigned int reglist
;
13364 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13367 if ((reglist
& 0x3f00ffff) != 0)
13370 ra
= (reglist
>> 27) & 0x10;
13371 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13373 if ((reglist
& -reglist
) != reglist
)
13376 imm
= (ffs (reglist
) - 1) | ra
;
13377 INSERT_OPERAND (1, RT
, *ip
, imm
);
13378 imm_expr
.X_op
= O_absent
;
13382 case '|': /* 4-bit trap code. */
13383 gas_assert (mips_opts
.micromips
);
13384 my_getExpression (&imm_expr
, s
);
13385 check_absolute_expr (ip
, &imm_expr
);
13386 if ((unsigned long) imm_expr
.X_add_number
13387 > MICROMIPSOP_MASK_TRAP
)
13388 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13389 (unsigned long) imm_expr
.X_add_number
,
13390 ip
->insn_mo
->name
);
13391 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13392 imm_expr
.X_op
= O_absent
;
13397 as_bad (_("Bad char = '%c'\n"), *args
);
13402 /* Args don't match. */
13404 insn_error
= _("Illegal operands");
13405 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13410 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13412 gas_assert (firstinsn
);
13413 need_delay_slot_ok
= FALSE
;
13422 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13424 /* This routine assembles an instruction into its binary format when
13425 assembling for the mips16. As a side effect, it sets one of the
13426 global variables imm_reloc or offset_reloc to the type of relocation
13427 to do if one of the operands is an address expression. It also sets
13428 forced_insn_length to the resulting instruction size in bytes if the
13429 user explicitly requested a small or extended instruction. */
13432 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13436 struct mips_opcode
*insn
;
13438 unsigned int regno
;
13439 unsigned int lastregno
= 0;
13445 forced_insn_length
= 0;
13447 for (s
= str
; ISLOWER (*s
); ++s
)
13459 if (s
[1] == 't' && s
[2] == ' ')
13462 forced_insn_length
= 2;
13466 else if (s
[1] == 'e' && s
[2] == ' ')
13469 forced_insn_length
= 4;
13473 /* Fall through. */
13475 insn_error
= _("unknown opcode");
13479 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13480 forced_insn_length
= 2;
13482 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13484 insn_error
= _("unrecognized opcode");
13493 gas_assert (strcmp (insn
->name
, str
) == 0);
13495 ok
= is_opcode_valid_16 (insn
);
13498 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13499 && strcmp (insn
->name
, insn
[1].name
) == 0)
13508 static char buf
[100];
13510 _("Opcode not supported on this processor: %s (%s)"),
13511 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13512 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13519 create_insn (ip
, insn
);
13520 imm_expr
.X_op
= O_absent
;
13521 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13522 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13523 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13524 imm2_expr
.X_op
= O_absent
;
13525 offset_expr
.X_op
= O_absent
;
13526 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13527 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13528 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13529 for (args
= insn
->args
; 1; ++args
)
13536 /* In this switch statement we call break if we did not find
13537 a match, continue if we did find a match, or return if we
13548 /* Stuff the immediate value in now, if we can. */
13549 if (imm_expr
.X_op
== O_constant
13550 && *imm_reloc
> BFD_RELOC_UNUSED
13551 && insn
->pinfo
!= INSN_MACRO
13552 && calculate_reloc (*offset_reloc
,
13553 imm_expr
.X_add_number
, &value
))
13555 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13556 *offset_reloc
, value
, forced_insn_length
,
13558 imm_expr
.X_op
= O_absent
;
13559 *imm_reloc
= BFD_RELOC_UNUSED
;
13560 *offset_reloc
= BFD_RELOC_UNUSED
;
13574 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13577 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13593 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13595 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13599 /* Fall through. */
13610 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13612 if (c
== 'v' || c
== 'w')
13615 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13617 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13628 if (c
== 'v' || c
== 'w')
13630 regno
= mips16_to_32_reg_map
[lastregno
];
13644 regno
= mips32_to_16_reg_map
[regno
];
13649 regno
= ILLEGAL_REG
;
13654 regno
= ILLEGAL_REG
;
13659 regno
= ILLEGAL_REG
;
13664 if (regno
== AT
&& mips_opts
.at
)
13666 if (mips_opts
.at
== ATREG
)
13667 as_warn (_("used $at without \".set noat\""));
13669 as_warn (_("used $%u with \".set at=$%u\""),
13670 regno
, mips_opts
.at
);
13678 if (regno
== ILLEGAL_REG
)
13685 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13689 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13692 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13695 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13701 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13704 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13705 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13715 if (strncmp (s
, "$pc", 3) == 0)
13732 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13735 if (imm_expr
.X_op
!= O_constant
)
13737 forced_insn_length
= 4;
13738 ip
->insn_opcode
|= MIPS16_EXTEND
;
13742 /* We need to relax this instruction. */
13743 *offset_reloc
= *imm_reloc
;
13744 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13749 *imm_reloc
= BFD_RELOC_UNUSED
;
13750 /* Fall through. */
13757 my_getExpression (&imm_expr
, s
);
13758 if (imm_expr
.X_op
== O_register
)
13760 /* What we thought was an expression turned out to
13763 if (s
[0] == '(' && args
[1] == '(')
13765 /* It looks like the expression was omitted
13766 before a register indirection, which means
13767 that the expression is implicitly zero. We
13768 still set up imm_expr, so that we handle
13769 explicit extensions correctly. */
13770 imm_expr
.X_op
= O_constant
;
13771 imm_expr
.X_add_number
= 0;
13772 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13779 /* We need to relax this instruction. */
13780 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13789 /* We use offset_reloc rather than imm_reloc for the PC
13790 relative operands. This lets macros with both
13791 immediate and address operands work correctly. */
13792 my_getExpression (&offset_expr
, s
);
13794 if (offset_expr
.X_op
== O_register
)
13797 /* We need to relax this instruction. */
13798 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13802 case '6': /* break code */
13803 my_getExpression (&imm_expr
, s
);
13804 check_absolute_expr (ip
, &imm_expr
);
13805 if ((unsigned long) imm_expr
.X_add_number
> 63)
13806 as_warn (_("Invalid value for `%s' (%lu)"),
13808 (unsigned long) imm_expr
.X_add_number
);
13809 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13810 imm_expr
.X_op
= O_absent
;
13814 case 'a': /* 26 bit address */
13815 my_getExpression (&offset_expr
, s
);
13817 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13818 ip
->insn_opcode
<<= 16;
13821 case 'l': /* register list for entry macro */
13822 case 'L': /* register list for exit macro */
13832 unsigned int freg
, reg1
, reg2
;
13834 while (*s
== ' ' || *s
== ',')
13836 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13838 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13842 as_bad (_("can't parse register list"));
13852 if (!reg_lookup (&s
, freg
? RTYPE_FPU
13853 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
13855 as_bad (_("invalid register list"));
13859 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
13861 mask
&= ~ (7 << 3);
13864 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
13866 mask
&= ~ (7 << 3);
13869 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
13870 mask
|= (reg2
- 3) << 3;
13871 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
13872 mask
|= (reg2
- 15) << 1;
13873 else if (reg1
== RA
&& reg2
== RA
)
13877 as_bad (_("invalid register list"));
13881 /* The mask is filled in in the opcode table for the
13882 benefit of the disassembler. We remove it before
13883 applying the actual mask. */
13884 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
13885 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
13889 case 'm': /* Register list for save insn. */
13890 case 'M': /* Register list for restore insn. */
13892 int opcode
= ip
->insn_opcode
;
13893 int framesz
= 0, seen_framesz
= 0;
13894 int nargs
= 0, statics
= 0, sregs
= 0;
13898 unsigned int reg1
, reg2
;
13900 SKIP_SPACE_TABS (s
);
13903 SKIP_SPACE_TABS (s
);
13905 my_getExpression (&imm_expr
, s
);
13906 if (imm_expr
.X_op
== O_constant
)
13908 /* Handle the frame size. */
13911 as_bad (_("more than one frame size in list"));
13915 framesz
= imm_expr
.X_add_number
;
13916 imm_expr
.X_op
= O_absent
;
13921 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13923 as_bad (_("can't parse register list"));
13935 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
13938 as_bad (_("can't parse register list"));
13943 while (reg1
<= reg2
)
13945 if (reg1
>= 4 && reg1
<= 7)
13949 nargs
|= 1 << (reg1
- 4);
13951 /* statics $a0-$a3 */
13952 statics
|= 1 << (reg1
- 4);
13954 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
13957 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
13959 else if (reg1
== 31)
13961 /* Add $ra to insn. */
13966 as_bad (_("unexpected register in list"));
13974 /* Encode args/statics combination. */
13975 if (nargs
& statics
)
13976 as_bad (_("arg/static registers overlap"));
13977 else if (nargs
== 0xf)
13978 /* All $a0-$a3 are args. */
13979 opcode
|= MIPS16_ALL_ARGS
<< 16;
13980 else if (statics
== 0xf)
13981 /* All $a0-$a3 are statics. */
13982 opcode
|= MIPS16_ALL_STATICS
<< 16;
13985 int narg
= 0, nstat
= 0;
13987 /* Count arg registers. */
13988 while (nargs
& 0x1)
13994 as_bad (_("invalid arg register list"));
13996 /* Count static registers. */
13997 while (statics
& 0x8)
13999 statics
= (statics
<< 1) & 0xf;
14003 as_bad (_("invalid static register list"));
14005 /* Encode args/statics. */
14006 opcode
|= ((narg
<< 2) | nstat
) << 16;
14009 /* Encode $s0/$s1. */
14010 if (sregs
& (1 << 0)) /* $s0 */
14012 if (sregs
& (1 << 1)) /* $s1 */
14018 /* Count regs $s2-$s8. */
14026 as_bad (_("invalid static register list"));
14027 /* Encode $s2-$s8. */
14028 opcode
|= nsreg
<< 24;
14031 /* Encode frame size. */
14033 as_bad (_("missing frame size"));
14034 else if ((framesz
& 7) != 0 || framesz
< 0
14035 || framesz
> 0xff * 8)
14036 as_bad (_("invalid frame size"));
14037 else if (framesz
!= 128 || (opcode
>> 16) != 0)
14040 opcode
|= (((framesz
& 0xf0) << 16)
14041 | (framesz
& 0x0f));
14044 /* Finally build the instruction. */
14045 if ((opcode
>> 16) != 0 || framesz
== 0)
14046 opcode
|= MIPS16_EXTEND
;
14047 ip
->insn_opcode
= opcode
;
14051 case 'e': /* extend code */
14052 my_getExpression (&imm_expr
, s
);
14053 check_absolute_expr (ip
, &imm_expr
);
14054 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
14056 as_warn (_("Invalid value for `%s' (%lu)"),
14058 (unsigned long) imm_expr
.X_add_number
);
14059 imm_expr
.X_add_number
&= 0x7ff;
14061 ip
->insn_opcode
|= imm_expr
.X_add_number
;
14062 imm_expr
.X_op
= O_absent
;
14072 /* Args don't match. */
14073 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
14074 strcmp (insn
->name
, insn
[1].name
) == 0)
14081 insn_error
= _("illegal operands");
14087 /* This structure holds information we know about a mips16 immediate
14090 struct mips16_immed_operand
14092 /* The type code used in the argument string in the opcode table. */
14094 /* The number of bits in the short form of the opcode. */
14096 /* The number of bits in the extended form of the opcode. */
14098 /* The amount by which the short form is shifted when it is used;
14099 for example, the sw instruction has a shift count of 2. */
14101 /* The amount by which the short form is shifted when it is stored
14102 into the instruction code. */
14104 /* Non-zero if the short form is unsigned. */
14106 /* Non-zero if the extended form is unsigned. */
14108 /* Non-zero if the value is PC relative. */
14112 /* The mips16 immediate operand types. */
14114 static const struct mips16_immed_operand mips16_immed_operands
[] =
14116 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14117 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14118 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14119 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14120 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
14121 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14122 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14123 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14124 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14125 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
14126 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14127 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14128 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14129 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
14130 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14131 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14132 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14133 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14134 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
14135 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
14136 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
14139 #define MIPS16_NUM_IMMED \
14140 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14142 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14143 NBITS is the number of significant bits in VAL. */
14145 static unsigned long
14146 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14151 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14154 else if (nbits
== 15)
14156 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14161 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14164 return (extval
<< 16) | val
;
14167 /* Install immediate value VAL into MIPS16 instruction *INSN,
14168 extending it if necessary. The instruction in *INSN may
14169 already be extended.
14171 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14172 if none. In the former case, VAL is a 16-bit number with no
14173 defined signedness.
14175 TYPE is the type of the immediate field. USER_INSN_LENGTH
14176 is the length that the user requested, or 0 if none. */
14179 mips16_immed (char *file
, unsigned int line
, int type
,
14180 bfd_reloc_code_real_type reloc
, offsetT val
,
14181 unsigned int user_insn_length
, unsigned long *insn
)
14183 const struct mips16_immed_operand
*op
;
14184 int mintiny
, maxtiny
;
14186 op
= mips16_immed_operands
;
14187 while (op
->type
!= type
)
14190 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14195 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14198 maxtiny
= 1 << op
->nbits
;
14203 maxtiny
= (1 << op
->nbits
) - 1;
14205 if (reloc
!= BFD_RELOC_UNUSED
)
14210 mintiny
= - (1 << (op
->nbits
- 1));
14211 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14212 if (reloc
!= BFD_RELOC_UNUSED
)
14213 val
= SEXT_16BIT (val
);
14216 /* Branch offsets have an implicit 0 in the lowest bit. */
14217 if (type
== 'p' || type
== 'q')
14220 if ((val
& ((1 << op
->shift
) - 1)) != 0
14221 || val
< (mintiny
<< op
->shift
)
14222 || val
> (maxtiny
<< op
->shift
))
14224 /* We need an extended instruction. */
14225 if (user_insn_length
== 2)
14226 as_bad_where (file
, line
, _("invalid unextended operand value"));
14228 *insn
|= MIPS16_EXTEND
;
14230 else if (user_insn_length
== 4)
14232 /* The operand doesn't force an unextended instruction to be extended.
14233 Warn if the user wanted an extended instruction anyway. */
14234 *insn
|= MIPS16_EXTEND
;
14235 as_warn_where (file
, line
,
14236 _("extended operand requested but not required"));
14239 if (mips16_opcode_length (*insn
) == 2)
14243 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14244 insnval
<<= op
->op_shift
;
14249 long minext
, maxext
;
14251 if (reloc
== BFD_RELOC_UNUSED
)
14256 maxext
= (1 << op
->extbits
) - 1;
14260 minext
= - (1 << (op
->extbits
- 1));
14261 maxext
= (1 << (op
->extbits
- 1)) - 1;
14263 if (val
< minext
|| val
> maxext
)
14264 as_bad_where (file
, line
,
14265 _("operand value out of range for instruction"));
14268 *insn
|= mips16_immed_extend (val
, op
->extbits
);
14272 struct percent_op_match
14275 bfd_reloc_code_real_type reloc
;
14278 static const struct percent_op_match mips_percent_op
[] =
14280 {"%lo", BFD_RELOC_LO16
},
14282 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14283 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14284 {"%call16", BFD_RELOC_MIPS_CALL16
},
14285 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14286 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14287 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14288 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14289 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14290 {"%got", BFD_RELOC_MIPS_GOT16
},
14291 {"%gp_rel", BFD_RELOC_GPREL16
},
14292 {"%half", BFD_RELOC_16
},
14293 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14294 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14295 {"%neg", BFD_RELOC_MIPS_SUB
},
14296 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14297 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14298 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14299 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14300 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14301 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14302 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14304 {"%hi", BFD_RELOC_HI16_S
}
14307 static const struct percent_op_match mips16_percent_op
[] =
14309 {"%lo", BFD_RELOC_MIPS16_LO16
},
14310 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14311 {"%got", BFD_RELOC_MIPS16_GOT16
},
14312 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14313 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14314 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14315 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14316 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14317 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14318 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14319 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14320 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14324 /* Return true if *STR points to a relocation operator. When returning true,
14325 move *STR over the operator and store its relocation code in *RELOC.
14326 Leave both *STR and *RELOC alone when returning false. */
14329 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14331 const struct percent_op_match
*percent_op
;
14334 if (mips_opts
.mips16
)
14336 percent_op
= mips16_percent_op
;
14337 limit
= ARRAY_SIZE (mips16_percent_op
);
14341 percent_op
= mips_percent_op
;
14342 limit
= ARRAY_SIZE (mips_percent_op
);
14345 for (i
= 0; i
< limit
; i
++)
14346 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14348 int len
= strlen (percent_op
[i
].str
);
14350 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14353 *str
+= strlen (percent_op
[i
].str
);
14354 *reloc
= percent_op
[i
].reloc
;
14356 /* Check whether the output BFD supports this relocation.
14357 If not, issue an error and fall back on something safe. */
14358 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14360 as_bad (_("relocation %s isn't supported by the current ABI"),
14361 percent_op
[i
].str
);
14362 *reloc
= BFD_RELOC_UNUSED
;
14370 /* Parse string STR as a 16-bit relocatable operand. Store the
14371 expression in *EP and the relocations in the array starting
14372 at RELOC. Return the number of relocation operators used.
14374 On exit, EXPR_END points to the first character after the expression. */
14377 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14380 bfd_reloc_code_real_type reversed_reloc
[3];
14381 size_t reloc_index
, i
;
14382 int crux_depth
, str_depth
;
14385 /* Search for the start of the main expression, recoding relocations
14386 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14387 of the main expression and with CRUX_DEPTH containing the number
14388 of open brackets at that point. */
14395 crux_depth
= str_depth
;
14397 /* Skip over whitespace and brackets, keeping count of the number
14399 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14404 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14405 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14407 my_getExpression (ep
, crux
);
14410 /* Match every open bracket. */
14411 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14415 if (crux_depth
> 0)
14416 as_bad (_("unclosed '('"));
14420 if (reloc_index
!= 0)
14422 prev_reloc_op_frag
= frag_now
;
14423 for (i
= 0; i
< reloc_index
; i
++)
14424 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14427 return reloc_index
;
14431 my_getExpression (expressionS
*ep
, char *str
)
14435 save_in
= input_line_pointer
;
14436 input_line_pointer
= str
;
14438 expr_end
= input_line_pointer
;
14439 input_line_pointer
= save_in
;
14443 md_atof (int type
, char *litP
, int *sizeP
)
14445 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14449 md_number_to_chars (char *buf
, valueT val
, int n
)
14451 if (target_big_endian
)
14452 number_to_chars_bigendian (buf
, val
, n
);
14454 number_to_chars_littleendian (buf
, val
, n
);
14458 static int support_64bit_objects(void)
14460 const char **list
, **l
;
14463 list
= bfd_target_list ();
14464 for (l
= list
; *l
!= NULL
; l
++)
14465 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14466 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14468 yes
= (*l
!= NULL
);
14472 #endif /* OBJ_ELF */
14474 const char *md_shortopts
= "O::g::G:";
14478 OPTION_MARCH
= OPTION_MD_BASE
,
14500 OPTION_NO_SMARTMIPS
,
14504 OPTION_NO_MICROMIPS
,
14507 OPTION_COMPAT_ARCH_BASE
,
14516 OPTION_M7000_HILO_FIX
,
14517 OPTION_MNO_7000_HILO_FIX
,
14520 OPTION_FIX_LOONGSON2F_JUMP
,
14521 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14522 OPTION_FIX_LOONGSON2F_NOP
,
14523 OPTION_NO_FIX_LOONGSON2F_NOP
,
14525 OPTION_NO_FIX_VR4120
,
14527 OPTION_NO_FIX_VR4130
,
14528 OPTION_FIX_CN63XXP1
,
14529 OPTION_NO_FIX_CN63XXP1
,
14536 OPTION_CONSTRUCT_FLOATS
,
14537 OPTION_NO_CONSTRUCT_FLOATS
,
14540 OPTION_RELAX_BRANCH
,
14541 OPTION_NO_RELAX_BRANCH
,
14548 OPTION_SINGLE_FLOAT
,
14549 OPTION_DOUBLE_FLOAT
,
14552 OPTION_CALL_SHARED
,
14553 OPTION_CALL_NONPIC
,
14563 OPTION_MVXWORKS_PIC
,
14564 #endif /* OBJ_ELF */
14568 struct option md_longopts
[] =
14570 /* Options which specify architecture. */
14571 {"march", required_argument
, NULL
, OPTION_MARCH
},
14572 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14573 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14574 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14575 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14576 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14577 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14578 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14579 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14580 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14581 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14582 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14584 /* Options which specify Application Specific Extensions (ASEs). */
14585 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14586 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14587 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14588 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14589 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14590 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14591 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14592 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14593 {"mmt", no_argument
, NULL
, OPTION_MT
},
14594 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14595 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14596 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14597 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14598 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14599 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14600 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14601 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
14602 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
14604 /* Old-style architecture options. Don't add more of these. */
14605 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14606 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14607 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14608 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14609 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14610 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14611 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14612 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14614 /* Options which enable bug fixes. */
14615 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14616 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14617 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14618 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14619 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14620 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14621 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14622 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14623 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14624 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14625 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14626 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14627 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14628 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14629 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14631 /* Miscellaneous options. */
14632 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14633 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14634 {"break", no_argument
, NULL
, OPTION_BREAK
},
14635 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14636 {"EB", no_argument
, NULL
, OPTION_EB
},
14637 {"EL", no_argument
, NULL
, OPTION_EL
},
14638 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14639 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14640 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14641 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14642 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14643 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14644 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14645 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14646 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14647 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14648 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14649 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14650 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14651 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14652 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14653 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14655 /* Strictly speaking this next option is ELF specific,
14656 but we allow it for other ports as well in order to
14657 make testing easier. */
14658 {"32", no_argument
, NULL
, OPTION_32
},
14660 /* ELF-specific options. */
14662 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14663 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14664 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14665 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14666 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14667 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14668 {"n32", no_argument
, NULL
, OPTION_N32
},
14669 {"64", no_argument
, NULL
, OPTION_64
},
14670 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14671 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14672 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14673 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14674 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14675 #endif /* OBJ_ELF */
14677 {NULL
, no_argument
, NULL
, 0}
14679 size_t md_longopts_size
= sizeof (md_longopts
);
14681 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14682 NEW_VALUE. Warn if another value was already specified. Note:
14683 we have to defer parsing the -march and -mtune arguments in order
14684 to handle 'from-abi' correctly, since the ABI might be specified
14685 in a later argument. */
14688 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14690 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14691 as_warn (_("A different %s was already specified, is now %s"),
14692 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14695 *string_ptr
= new_value
;
14699 md_parse_option (int c
, char *arg
)
14703 case OPTION_CONSTRUCT_FLOATS
:
14704 mips_disable_float_construction
= 0;
14707 case OPTION_NO_CONSTRUCT_FLOATS
:
14708 mips_disable_float_construction
= 1;
14720 target_big_endian
= 1;
14724 target_big_endian
= 0;
14730 else if (arg
[0] == '0')
14732 else if (arg
[0] == '1')
14742 mips_debug
= atoi (arg
);
14746 file_mips_isa
= ISA_MIPS1
;
14750 file_mips_isa
= ISA_MIPS2
;
14754 file_mips_isa
= ISA_MIPS3
;
14758 file_mips_isa
= ISA_MIPS4
;
14762 file_mips_isa
= ISA_MIPS5
;
14765 case OPTION_MIPS32
:
14766 file_mips_isa
= ISA_MIPS32
;
14769 case OPTION_MIPS32R2
:
14770 file_mips_isa
= ISA_MIPS32R2
;
14773 case OPTION_MIPS64R2
:
14774 file_mips_isa
= ISA_MIPS64R2
;
14777 case OPTION_MIPS64
:
14778 file_mips_isa
= ISA_MIPS64
;
14782 mips_set_option_string (&mips_tune_string
, arg
);
14786 mips_set_option_string (&mips_arch_string
, arg
);
14790 mips_set_option_string (&mips_arch_string
, "4650");
14791 mips_set_option_string (&mips_tune_string
, "4650");
14794 case OPTION_NO_M4650
:
14798 mips_set_option_string (&mips_arch_string
, "4010");
14799 mips_set_option_string (&mips_tune_string
, "4010");
14802 case OPTION_NO_M4010
:
14806 mips_set_option_string (&mips_arch_string
, "4100");
14807 mips_set_option_string (&mips_tune_string
, "4100");
14810 case OPTION_NO_M4100
:
14814 mips_set_option_string (&mips_arch_string
, "3900");
14815 mips_set_option_string (&mips_tune_string
, "3900");
14818 case OPTION_NO_M3900
:
14822 mips_opts
.ase_mdmx
= 1;
14825 case OPTION_NO_MDMX
:
14826 mips_opts
.ase_mdmx
= 0;
14830 mips_opts
.ase_dsp
= 1;
14831 mips_opts
.ase_dspr2
= 0;
14834 case OPTION_NO_DSP
:
14835 mips_opts
.ase_dsp
= 0;
14836 mips_opts
.ase_dspr2
= 0;
14840 mips_opts
.ase_dspr2
= 1;
14841 mips_opts
.ase_dsp
= 1;
14844 case OPTION_NO_DSPR2
:
14845 mips_opts
.ase_dspr2
= 0;
14846 mips_opts
.ase_dsp
= 0;
14850 mips_opts
.ase_mt
= 1;
14854 mips_opts
.ase_mt
= 0;
14858 mips_opts
.ase_mcu
= 1;
14861 case OPTION_NO_MCU
:
14862 mips_opts
.ase_mcu
= 0;
14865 case OPTION_MICROMIPS
:
14866 if (mips_opts
.mips16
== 1)
14868 as_bad (_("-mmicromips cannot be used with -mips16"));
14871 mips_opts
.micromips
= 1;
14872 mips_no_prev_insn ();
14875 case OPTION_NO_MICROMIPS
:
14876 mips_opts
.micromips
= 0;
14877 mips_no_prev_insn ();
14880 case OPTION_MIPS16
:
14881 if (mips_opts
.micromips
== 1)
14883 as_bad (_("-mips16 cannot be used with -micromips"));
14886 mips_opts
.mips16
= 1;
14887 mips_no_prev_insn ();
14890 case OPTION_NO_MIPS16
:
14891 mips_opts
.mips16
= 0;
14892 mips_no_prev_insn ();
14895 case OPTION_MIPS3D
:
14896 mips_opts
.ase_mips3d
= 1;
14899 case OPTION_NO_MIPS3D
:
14900 mips_opts
.ase_mips3d
= 0;
14903 case OPTION_SMARTMIPS
:
14904 mips_opts
.ase_smartmips
= 1;
14907 case OPTION_NO_SMARTMIPS
:
14908 mips_opts
.ase_smartmips
= 0;
14911 case OPTION_FIX_24K
:
14915 case OPTION_NO_FIX_24K
:
14919 case OPTION_FIX_LOONGSON2F_JUMP
:
14920 mips_fix_loongson2f_jump
= TRUE
;
14923 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14924 mips_fix_loongson2f_jump
= FALSE
;
14927 case OPTION_FIX_LOONGSON2F_NOP
:
14928 mips_fix_loongson2f_nop
= TRUE
;
14931 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14932 mips_fix_loongson2f_nop
= FALSE
;
14935 case OPTION_FIX_VR4120
:
14936 mips_fix_vr4120
= 1;
14939 case OPTION_NO_FIX_VR4120
:
14940 mips_fix_vr4120
= 0;
14943 case OPTION_FIX_VR4130
:
14944 mips_fix_vr4130
= 1;
14947 case OPTION_NO_FIX_VR4130
:
14948 mips_fix_vr4130
= 0;
14951 case OPTION_FIX_CN63XXP1
:
14952 mips_fix_cn63xxp1
= TRUE
;
14955 case OPTION_NO_FIX_CN63XXP1
:
14956 mips_fix_cn63xxp1
= FALSE
;
14959 case OPTION_RELAX_BRANCH
:
14960 mips_relax_branch
= 1;
14963 case OPTION_NO_RELAX_BRANCH
:
14964 mips_relax_branch
= 0;
14967 case OPTION_MSHARED
:
14968 mips_in_shared
= TRUE
;
14971 case OPTION_MNO_SHARED
:
14972 mips_in_shared
= FALSE
;
14975 case OPTION_MSYM32
:
14976 mips_opts
.sym32
= TRUE
;
14979 case OPTION_MNO_SYM32
:
14980 mips_opts
.sym32
= FALSE
;
14984 /* When generating ELF code, we permit -KPIC and -call_shared to
14985 select SVR4_PIC, and -non_shared to select no PIC. This is
14986 intended to be compatible with Irix 5. */
14987 case OPTION_CALL_SHARED
:
14990 as_bad (_("-call_shared is supported only for ELF format"));
14993 mips_pic
= SVR4_PIC
;
14994 mips_abicalls
= TRUE
;
14997 case OPTION_CALL_NONPIC
:
15000 as_bad (_("-call_nonpic is supported only for ELF format"));
15004 mips_abicalls
= TRUE
;
15007 case OPTION_NON_SHARED
:
15010 as_bad (_("-non_shared is supported only for ELF format"));
15014 mips_abicalls
= FALSE
;
15017 /* The -xgot option tells the assembler to use 32 bit offsets
15018 when accessing the got in SVR4_PIC mode. It is for Irix
15023 #endif /* OBJ_ELF */
15026 g_switch_value
= atoi (arg
);
15030 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15034 mips_abi
= O32_ABI
;
15035 /* We silently ignore -32 for non-ELF targets. This greatly
15036 simplifies the construction of the MIPS GAS test cases. */
15043 as_bad (_("-n32 is supported for ELF format only"));
15046 mips_abi
= N32_ABI
;
15052 as_bad (_("-64 is supported for ELF format only"));
15055 mips_abi
= N64_ABI
;
15056 if (!support_64bit_objects())
15057 as_fatal (_("No compiled in support for 64 bit object file format"));
15059 #endif /* OBJ_ELF */
15062 file_mips_gp32
= 1;
15066 file_mips_gp32
= 0;
15070 file_mips_fp32
= 1;
15074 file_mips_fp32
= 0;
15077 case OPTION_SINGLE_FLOAT
:
15078 file_mips_single_float
= 1;
15081 case OPTION_DOUBLE_FLOAT
:
15082 file_mips_single_float
= 0;
15085 case OPTION_SOFT_FLOAT
:
15086 file_mips_soft_float
= 1;
15089 case OPTION_HARD_FLOAT
:
15090 file_mips_soft_float
= 0;
15097 as_bad (_("-mabi is supported for ELF format only"));
15100 if (strcmp (arg
, "32") == 0)
15101 mips_abi
= O32_ABI
;
15102 else if (strcmp (arg
, "o64") == 0)
15103 mips_abi
= O64_ABI
;
15104 else if (strcmp (arg
, "n32") == 0)
15105 mips_abi
= N32_ABI
;
15106 else if (strcmp (arg
, "64") == 0)
15108 mips_abi
= N64_ABI
;
15109 if (! support_64bit_objects())
15110 as_fatal (_("No compiled in support for 64 bit object file "
15113 else if (strcmp (arg
, "eabi") == 0)
15114 mips_abi
= EABI_ABI
;
15117 as_fatal (_("invalid abi -mabi=%s"), arg
);
15121 #endif /* OBJ_ELF */
15123 case OPTION_M7000_HILO_FIX
:
15124 mips_7000_hilo_fix
= TRUE
;
15127 case OPTION_MNO_7000_HILO_FIX
:
15128 mips_7000_hilo_fix
= FALSE
;
15132 case OPTION_MDEBUG
:
15133 mips_flag_mdebug
= TRUE
;
15136 case OPTION_NO_MDEBUG
:
15137 mips_flag_mdebug
= FALSE
;
15141 mips_flag_pdr
= TRUE
;
15144 case OPTION_NO_PDR
:
15145 mips_flag_pdr
= FALSE
;
15148 case OPTION_MVXWORKS_PIC
:
15149 mips_pic
= VXWORKS_PIC
;
15151 #endif /* OBJ_ELF */
15157 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15162 /* Set up globals to generate code for the ISA or processor
15163 described by INFO. */
15166 mips_set_architecture (const struct mips_cpu_info
*info
)
15170 file_mips_arch
= info
->cpu
;
15171 mips_opts
.arch
= info
->cpu
;
15172 mips_opts
.isa
= info
->isa
;
15177 /* Likewise for tuning. */
15180 mips_set_tune (const struct mips_cpu_info
*info
)
15183 mips_tune
= info
->cpu
;
15188 mips_after_parse_args (void)
15190 const struct mips_cpu_info
*arch_info
= 0;
15191 const struct mips_cpu_info
*tune_info
= 0;
15193 /* GP relative stuff not working for PE */
15194 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15196 if (g_switch_seen
&& g_switch_value
!= 0)
15197 as_bad (_("-G not supported in this configuration."));
15198 g_switch_value
= 0;
15201 if (mips_abi
== NO_ABI
)
15202 mips_abi
= MIPS_DEFAULT_ABI
;
15204 /* The following code determines the architecture and register size.
15205 Similar code was added to GCC 3.3 (see override_options() in
15206 config/mips/mips.c). The GAS and GCC code should be kept in sync
15207 as much as possible. */
15209 if (mips_arch_string
!= 0)
15210 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15212 if (file_mips_isa
!= ISA_UNKNOWN
)
15214 /* Handle -mipsN. At this point, file_mips_isa contains the
15215 ISA level specified by -mipsN, while arch_info->isa contains
15216 the -march selection (if any). */
15217 if (arch_info
!= 0)
15219 /* -march takes precedence over -mipsN, since it is more descriptive.
15220 There's no harm in specifying both as long as the ISA levels
15222 if (file_mips_isa
!= arch_info
->isa
)
15223 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15224 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15225 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15228 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15231 if (arch_info
== 0)
15233 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15234 gas_assert (arch_info
);
15237 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15238 as_bad (_("-march=%s is not compatible with the selected ABI"),
15241 mips_set_architecture (arch_info
);
15243 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15244 if (mips_tune_string
!= 0)
15245 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15247 if (tune_info
== 0)
15248 mips_set_tune (arch_info
);
15250 mips_set_tune (tune_info
);
15252 if (file_mips_gp32
>= 0)
15254 /* The user specified the size of the integer registers. Make sure
15255 it agrees with the ABI and ISA. */
15256 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15257 as_bad (_("-mgp64 used with a 32-bit processor"));
15258 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15259 as_bad (_("-mgp32 used with a 64-bit ABI"));
15260 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15261 as_bad (_("-mgp64 used with a 32-bit ABI"));
15265 /* Infer the integer register size from the ABI and processor.
15266 Restrict ourselves to 32-bit registers if that's all the
15267 processor has, or if the ABI cannot handle 64-bit registers. */
15268 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15269 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15272 switch (file_mips_fp32
)
15276 /* No user specified float register size.
15277 ??? GAS treats single-float processors as though they had 64-bit
15278 float registers (although it complains when double-precision
15279 instructions are used). As things stand, saying they have 32-bit
15280 registers would lead to spurious "register must be even" messages.
15281 So here we assume float registers are never smaller than the
15283 if (file_mips_gp32
== 0)
15284 /* 64-bit integer registers implies 64-bit float registers. */
15285 file_mips_fp32
= 0;
15286 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
15287 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15288 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15289 file_mips_fp32
= 0;
15291 /* 32-bit float registers. */
15292 file_mips_fp32
= 1;
15295 /* The user specified the size of the float registers. Check if it
15296 agrees with the ABI and ISA. */
15298 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15299 as_bad (_("-mfp64 used with a 32-bit fpu"));
15300 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15301 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15302 as_warn (_("-mfp64 used with a 32-bit ABI"));
15305 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15306 as_warn (_("-mfp32 used with a 64-bit ABI"));
15310 /* End of GCC-shared inference code. */
15312 /* This flag is set when we have a 64-bit capable CPU but use only
15313 32-bit wide registers. Note that EABI does not use it. */
15314 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15315 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15316 || mips_abi
== O32_ABI
))
15317 mips_32bitmode
= 1;
15319 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15320 as_bad (_("trap exception not supported at ISA 1"));
15322 /* If the selected architecture includes support for ASEs, enable
15323 generation of code for them. */
15324 if (mips_opts
.mips16
== -1)
15325 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15326 if (mips_opts
.micromips
== -1)
15327 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15328 if (mips_opts
.ase_mips3d
== -1)
15329 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
15330 && file_mips_fp32
== 0) ? 1 : 0;
15331 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
15332 as_bad (_("-mfp32 used with -mips3d"));
15334 if (mips_opts
.ase_mdmx
== -1)
15335 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
15336 && file_mips_fp32
== 0) ? 1 : 0;
15337 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
15338 as_bad (_("-mfp32 used with -mdmx"));
15340 if (mips_opts
.ase_smartmips
== -1)
15341 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15342 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15343 as_warn (_("%s ISA does not support SmartMIPS"),
15344 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15346 if (mips_opts
.ase_dsp
== -1)
15347 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15348 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15349 as_warn (_("%s ISA does not support DSP ASE"),
15350 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15352 if (mips_opts
.ase_dspr2
== -1)
15354 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15355 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15357 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15358 as_warn (_("%s ISA does not support DSP R2 ASE"),
15359 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15361 if (mips_opts
.ase_mt
== -1)
15362 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15363 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15364 as_warn (_("%s ISA does not support MT ASE"),
15365 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15367 if (mips_opts
.ase_mcu
== -1)
15368 mips_opts
.ase_mcu
= (arch_info
->flags
& MIPS_CPU_ASE_MCU
) ? 1 : 0;
15369 if (mips_opts
.ase_mcu
&& !ISA_SUPPORTS_MCU_ASE
)
15370 as_warn (_("%s ISA does not support MCU ASE"),
15371 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15373 file_mips_isa
= mips_opts
.isa
;
15374 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15375 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15376 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15377 file_ase_dsp
= mips_opts
.ase_dsp
;
15378 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15379 file_ase_mt
= mips_opts
.ase_mt
;
15380 mips_opts
.gp32
= file_mips_gp32
;
15381 mips_opts
.fp32
= file_mips_fp32
;
15382 mips_opts
.soft_float
= file_mips_soft_float
;
15383 mips_opts
.single_float
= file_mips_single_float
;
15385 if (mips_flag_mdebug
< 0)
15387 #ifdef OBJ_MAYBE_ECOFF
15388 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15389 mips_flag_mdebug
= 1;
15391 #endif /* OBJ_MAYBE_ECOFF */
15392 mips_flag_mdebug
= 0;
15397 mips_init_after_args (void)
15399 /* initialize opcodes */
15400 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15401 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15405 md_pcrel_from (fixS
*fixP
)
15407 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15408 switch (fixP
->fx_r_type
)
15410 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15411 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15412 /* Return the address of the delay slot. */
15415 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15416 case BFD_RELOC_MICROMIPS_JMP
:
15417 case BFD_RELOC_16_PCREL_S2
:
15418 case BFD_RELOC_MIPS_JMP
:
15419 /* Return the address of the delay slot. */
15422 case BFD_RELOC_32_PCREL
:
15426 /* We have no relocation type for PC relative MIPS16 instructions. */
15427 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15429 _("PC relative MIPS16 instruction references a different section"));
15434 /* This is called before the symbol table is processed. In order to
15435 work with gcc when using mips-tfile, we must keep all local labels.
15436 However, in other cases, we want to discard them. If we were
15437 called with -g, but we didn't see any debugging information, it may
15438 mean that gcc is smuggling debugging information through to
15439 mips-tfile, in which case we must generate all local labels. */
15442 mips_frob_file_before_adjust (void)
15444 #ifndef NO_ECOFF_DEBUGGING
15445 if (ECOFF_DEBUGGING
15447 && ! ecoff_debugging_seen
)
15448 flag_keep_locals
= 1;
15452 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15453 the corresponding LO16 reloc. This is called before md_apply_fix and
15454 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15455 relocation operators.
15457 For our purposes, a %lo() expression matches a %got() or %hi()
15460 (a) it refers to the same symbol; and
15461 (b) the offset applied in the %lo() expression is no lower than
15462 the offset applied in the %got() or %hi().
15464 (b) allows us to cope with code like:
15467 lh $4,%lo(foo+2)($4)
15469 ...which is legal on RELA targets, and has a well-defined behaviour
15470 if the user knows that adding 2 to "foo" will not induce a carry to
15473 When several %lo()s match a particular %got() or %hi(), we use the
15474 following rules to distinguish them:
15476 (1) %lo()s with smaller offsets are a better match than %lo()s with
15479 (2) %lo()s with no matching %got() or %hi() are better than those
15480 that already have a matching %got() or %hi().
15482 (3) later %lo()s are better than earlier %lo()s.
15484 These rules are applied in order.
15486 (1) means, among other things, that %lo()s with identical offsets are
15487 chosen if they exist.
15489 (2) means that we won't associate several high-part relocations with
15490 the same low-part relocation unless there's no alternative. Having
15491 several high parts for the same low part is a GNU extension; this rule
15492 allows careful users to avoid it.
15494 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15495 with the last high-part relocation being at the front of the list.
15496 It therefore makes sense to choose the last matching low-part
15497 relocation, all other things being equal. It's also easier
15498 to code that way. */
15501 mips_frob_file (void)
15503 struct mips_hi_fixup
*l
;
15504 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15506 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15508 segment_info_type
*seginfo
;
15509 bfd_boolean matched_lo_p
;
15510 fixS
**hi_pos
, **lo_pos
, **pos
;
15512 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15514 /* If a GOT16 relocation turns out to be against a global symbol,
15515 there isn't supposed to be a matching LO. Ignore %gots against
15516 constants; we'll report an error for those later. */
15517 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15518 && !(l
->fixp
->fx_addsy
15519 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15522 /* Check quickly whether the next fixup happens to be a matching %lo. */
15523 if (fixup_has_matching_lo_p (l
->fixp
))
15526 seginfo
= seg_info (l
->seg
);
15528 /* Set HI_POS to the position of this relocation in the chain.
15529 Set LO_POS to the position of the chosen low-part relocation.
15530 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15531 relocation that matches an immediately-preceding high-part
15535 matched_lo_p
= FALSE
;
15536 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15538 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15540 if (*pos
== l
->fixp
)
15543 if ((*pos
)->fx_r_type
== looking_for_rtype
15544 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15545 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15547 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15549 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15552 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15553 && fixup_has_matching_lo_p (*pos
));
15556 /* If we found a match, remove the high-part relocation from its
15557 current position and insert it before the low-part relocation.
15558 Make the offsets match so that fixup_has_matching_lo_p()
15561 We don't warn about unmatched high-part relocations since some
15562 versions of gcc have been known to emit dead "lui ...%hi(...)"
15564 if (lo_pos
!= NULL
)
15566 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15567 if (l
->fixp
->fx_next
!= *lo_pos
)
15569 *hi_pos
= l
->fixp
->fx_next
;
15570 l
->fixp
->fx_next
= *lo_pos
;
15578 mips_force_relocation (fixS
*fixp
)
15580 if (generic_force_reloc (fixp
))
15583 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15584 so that the linker relaxation can update targets. */
15585 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15586 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15587 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15593 /* Read the instruction associated with RELOC from BUF. */
15595 static unsigned int
15596 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15598 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15599 return read_compressed_insn (buf
, 4);
15601 return read_insn (buf
);
15604 /* Write instruction INSN to BUF, given that it has been relocated
15608 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15609 unsigned long insn
)
15611 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15612 write_compressed_insn (buf
, insn
, 4);
15614 write_insn (buf
, insn
);
15617 /* Apply a fixup to the object file. */
15620 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15623 unsigned long insn
;
15624 reloc_howto_type
*howto
;
15626 /* We ignore generic BFD relocations we don't know about. */
15627 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15631 gas_assert (fixP
->fx_size
== 2
15632 || fixP
->fx_size
== 4
15633 || fixP
->fx_r_type
== BFD_RELOC_16
15634 || fixP
->fx_r_type
== BFD_RELOC_64
15635 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15636 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15637 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15638 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15639 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15640 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15642 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15644 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15645 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15646 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15647 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
15648 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
15650 /* Don't treat parts of a composite relocation as done. There are two
15653 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15654 should nevertheless be emitted if the first part is.
15656 (2) In normal usage, composite relocations are never assembly-time
15657 constants. The easiest way of dealing with the pathological
15658 exceptions is to generate a relocation against STN_UNDEF and
15659 leave everything up to the linker. */
15660 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15663 switch (fixP
->fx_r_type
)
15665 case BFD_RELOC_MIPS_TLS_GD
:
15666 case BFD_RELOC_MIPS_TLS_LDM
:
15667 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15668 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15669 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15670 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15671 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15672 case BFD_RELOC_MIPS_TLS_TPREL32
:
15673 case BFD_RELOC_MIPS_TLS_TPREL64
:
15674 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15675 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15676 case BFD_RELOC_MICROMIPS_TLS_GD
:
15677 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15678 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15679 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15680 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15681 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15682 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15683 case BFD_RELOC_MIPS16_TLS_GD
:
15684 case BFD_RELOC_MIPS16_TLS_LDM
:
15685 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15686 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15687 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15688 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15689 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15690 if (!fixP
->fx_addsy
)
15692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15693 _("TLS relocation against a constant"));
15696 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15699 case BFD_RELOC_MIPS_JMP
:
15700 case BFD_RELOC_MIPS_SHIFT5
:
15701 case BFD_RELOC_MIPS_SHIFT6
:
15702 case BFD_RELOC_MIPS_GOT_DISP
:
15703 case BFD_RELOC_MIPS_GOT_PAGE
:
15704 case BFD_RELOC_MIPS_GOT_OFST
:
15705 case BFD_RELOC_MIPS_SUB
:
15706 case BFD_RELOC_MIPS_INSERT_A
:
15707 case BFD_RELOC_MIPS_INSERT_B
:
15708 case BFD_RELOC_MIPS_DELETE
:
15709 case BFD_RELOC_MIPS_HIGHEST
:
15710 case BFD_RELOC_MIPS_HIGHER
:
15711 case BFD_RELOC_MIPS_SCN_DISP
:
15712 case BFD_RELOC_MIPS_REL16
:
15713 case BFD_RELOC_MIPS_RELGOT
:
15714 case BFD_RELOC_MIPS_JALR
:
15715 case BFD_RELOC_HI16
:
15716 case BFD_RELOC_HI16_S
:
15717 case BFD_RELOC_LO16
:
15718 case BFD_RELOC_GPREL16
:
15719 case BFD_RELOC_MIPS_LITERAL
:
15720 case BFD_RELOC_MIPS_CALL16
:
15721 case BFD_RELOC_MIPS_GOT16
:
15722 case BFD_RELOC_GPREL32
:
15723 case BFD_RELOC_MIPS_GOT_HI16
:
15724 case BFD_RELOC_MIPS_GOT_LO16
:
15725 case BFD_RELOC_MIPS_CALL_HI16
:
15726 case BFD_RELOC_MIPS_CALL_LO16
:
15727 case BFD_RELOC_MIPS16_GPREL
:
15728 case BFD_RELOC_MIPS16_GOT16
:
15729 case BFD_RELOC_MIPS16_CALL16
:
15730 case BFD_RELOC_MIPS16_HI16
:
15731 case BFD_RELOC_MIPS16_HI16_S
:
15732 case BFD_RELOC_MIPS16_LO16
:
15733 case BFD_RELOC_MIPS16_JMP
:
15734 case BFD_RELOC_MICROMIPS_JMP
:
15735 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15736 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15737 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15738 case BFD_RELOC_MICROMIPS_SUB
:
15739 case BFD_RELOC_MICROMIPS_HIGHEST
:
15740 case BFD_RELOC_MICROMIPS_HIGHER
:
15741 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15742 case BFD_RELOC_MICROMIPS_JALR
:
15743 case BFD_RELOC_MICROMIPS_HI16
:
15744 case BFD_RELOC_MICROMIPS_HI16_S
:
15745 case BFD_RELOC_MICROMIPS_LO16
:
15746 case BFD_RELOC_MICROMIPS_GPREL16
:
15747 case BFD_RELOC_MICROMIPS_LITERAL
:
15748 case BFD_RELOC_MICROMIPS_CALL16
:
15749 case BFD_RELOC_MICROMIPS_GOT16
:
15750 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15751 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15752 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15753 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15758 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15760 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15761 if (mips16_reloc_p (fixP
->fx_r_type
))
15762 insn
|= mips16_immed_extend (value
, 16);
15764 insn
|= (value
& 0xffff);
15765 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15769 _("Unsupported constant in relocation"));
15774 /* This is handled like BFD_RELOC_32, but we output a sign
15775 extended value if we are only 32 bits. */
15778 if (8 <= sizeof (valueT
))
15779 md_number_to_chars (buf
, *valP
, 8);
15784 if ((*valP
& 0x80000000) != 0)
15788 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15789 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15794 case BFD_RELOC_RVA
:
15796 case BFD_RELOC_32_PCREL
:
15798 /* If we are deleting this reloc entry, we must fill in the
15799 value now. This can happen if we have a .word which is not
15800 resolved when it appears but is later defined. */
15802 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15805 case BFD_RELOC_16_PCREL_S2
:
15806 if ((*valP
& 0x3) != 0)
15807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15808 _("Branch to misaligned address (%lx)"), (long) *valP
);
15810 /* We need to save the bits in the instruction since fixup_segment()
15811 might be deleting the relocation entry (i.e., a branch within
15812 the current segment). */
15813 if (! fixP
->fx_done
)
15816 /* Update old instruction data. */
15817 insn
= read_insn (buf
);
15819 if (*valP
+ 0x20000 <= 0x3ffff)
15821 insn
|= (*valP
>> 2) & 0xffff;
15822 write_insn (buf
, insn
);
15824 else if (mips_pic
== NO_PIC
15826 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15827 && (fixP
->fx_frag
->fr_address
15828 < text_section
->vma
+ bfd_get_section_size (text_section
))
15829 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15830 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15831 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15833 /* The branch offset is too large. If this is an
15834 unconditional branch, and we are not generating PIC code,
15835 we can convert it to an absolute jump instruction. */
15836 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15837 insn
= 0x0c000000; /* jal */
15839 insn
= 0x08000000; /* j */
15840 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15842 fixP
->fx_addsy
= section_symbol (text_section
);
15843 *valP
+= md_pcrel_from (fixP
);
15844 write_insn (buf
, insn
);
15848 /* If we got here, we have branch-relaxation disabled,
15849 and there's nothing we can do to fix this instruction
15850 without turning it into a longer sequence. */
15851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15852 _("Branch out of range"));
15856 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15857 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15858 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15859 /* We adjust the offset back to even. */
15860 if ((*valP
& 0x1) != 0)
15863 if (! fixP
->fx_done
)
15866 /* Should never visit here, because we keep the relocation. */
15870 case BFD_RELOC_VTABLE_INHERIT
:
15873 && !S_IS_DEFINED (fixP
->fx_addsy
)
15874 && !S_IS_WEAK (fixP
->fx_addsy
))
15875 S_SET_WEAK (fixP
->fx_addsy
);
15878 case BFD_RELOC_VTABLE_ENTRY
:
15886 /* Remember value for tc_gen_reloc. */
15887 fixP
->fx_addnumber
= *valP
;
15897 name
= input_line_pointer
;
15898 c
= get_symbol_end ();
15899 p
= (symbolS
*) symbol_find_or_make (name
);
15900 *input_line_pointer
= c
;
15904 /* Align the current frag to a given power of two. If a particular
15905 fill byte should be used, FILL points to an integer that contains
15906 that byte, otherwise FILL is null.
15908 This function used to have the comment:
15910 The MIPS assembler also automatically adjusts any preceding label.
15912 The implementation therefore applied the adjustment to a maximum of
15913 one label. However, other label adjustments are applied to batches
15914 of labels, and adjusting just one caused problems when new labels
15915 were added for the sake of debugging or unwind information.
15916 We therefore adjust all preceding labels (given as LABELS) instead. */
15919 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15921 mips_emit_delays ();
15922 mips_record_compressed_mode ();
15923 if (fill
== NULL
&& subseg_text_p (now_seg
))
15924 frag_align_code (to
, 0);
15926 frag_align (to
, fill
? *fill
: 0, 0);
15927 record_alignment (now_seg
, to
);
15928 mips_move_labels (labels
, FALSE
);
15931 /* Align to a given power of two. .align 0 turns off the automatic
15932 alignment used by the data creating pseudo-ops. */
15935 s_align (int x ATTRIBUTE_UNUSED
)
15937 int temp
, fill_value
, *fill_ptr
;
15938 long max_alignment
= 28;
15940 /* o Note that the assembler pulls down any immediately preceding label
15941 to the aligned address.
15942 o It's not documented but auto alignment is reinstated by
15943 a .align pseudo instruction.
15944 o Note also that after auto alignment is turned off the mips assembler
15945 issues an error on attempt to assemble an improperly aligned data item.
15948 temp
= get_absolute_expression ();
15949 if (temp
> max_alignment
)
15950 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
15953 as_warn (_("Alignment negative: 0 assumed."));
15956 if (*input_line_pointer
== ',')
15958 ++input_line_pointer
;
15959 fill_value
= get_absolute_expression ();
15960 fill_ptr
= &fill_value
;
15966 segment_info_type
*si
= seg_info (now_seg
);
15967 struct insn_label_list
*l
= si
->label_list
;
15968 /* Auto alignment should be switched on by next section change. */
15970 mips_align (temp
, fill_ptr
, l
);
15977 demand_empty_rest_of_line ();
15981 s_change_sec (int sec
)
15986 /* The ELF backend needs to know that we are changing sections, so
15987 that .previous works correctly. We could do something like check
15988 for an obj_section_change_hook macro, but that might be confusing
15989 as it would not be appropriate to use it in the section changing
15990 functions in read.c, since obj-elf.c intercepts those. FIXME:
15991 This should be cleaner, somehow. */
15993 obj_elf_section_change_hook ();
15996 mips_emit_delays ();
16007 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16008 demand_empty_rest_of_line ();
16012 seg
= subseg_new (RDATA_SECTION_NAME
,
16013 (subsegT
) get_absolute_expression ());
16016 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16017 | SEC_READONLY
| SEC_RELOC
16019 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16020 record_alignment (seg
, 4);
16022 demand_empty_rest_of_line ();
16026 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16029 bfd_set_section_flags (stdoutput
, seg
,
16030 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16031 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16032 record_alignment (seg
, 4);
16034 demand_empty_rest_of_line ();
16038 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16041 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16042 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16043 record_alignment (seg
, 4);
16045 demand_empty_rest_of_line ();
16053 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16056 char *section_name
;
16061 int section_entry_size
;
16062 int section_alignment
;
16067 section_name
= input_line_pointer
;
16068 c
= get_symbol_end ();
16070 next_c
= *(input_line_pointer
+ 1);
16072 /* Do we have .section Name<,"flags">? */
16073 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16075 /* just after name is now '\0'. */
16076 *input_line_pointer
= c
;
16077 input_line_pointer
= section_name
;
16078 obj_elf_section (ignore
);
16081 input_line_pointer
++;
16083 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16085 section_type
= get_absolute_expression ();
16088 if (*input_line_pointer
++ == ',')
16089 section_flag
= get_absolute_expression ();
16092 if (*input_line_pointer
++ == ',')
16093 section_entry_size
= get_absolute_expression ();
16095 section_entry_size
= 0;
16096 if (*input_line_pointer
++ == ',')
16097 section_alignment
= get_absolute_expression ();
16099 section_alignment
= 0;
16100 /* FIXME: really ignore? */
16101 (void) section_alignment
;
16103 section_name
= xstrdup (section_name
);
16105 /* When using the generic form of .section (as implemented by obj-elf.c),
16106 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16107 traditionally had to fall back on the more common @progbits instead.
16109 There's nothing really harmful in this, since bfd will correct
16110 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16111 means that, for backwards compatibility, the special_section entries
16112 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16114 Even so, we shouldn't force users of the MIPS .section syntax to
16115 incorrectly label the sections as SHT_PROGBITS. The best compromise
16116 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16117 generic type-checking code. */
16118 if (section_type
== SHT_MIPS_DWARF
)
16119 section_type
= SHT_PROGBITS
;
16121 obj_elf_change_section (section_name
, section_type
, section_flag
,
16122 section_entry_size
, 0, 0, 0);
16124 if (now_seg
->name
!= section_name
)
16125 free (section_name
);
16126 #endif /* OBJ_ELF */
16130 mips_enable_auto_align (void)
16136 s_cons (int log_size
)
16138 segment_info_type
*si
= seg_info (now_seg
);
16139 struct insn_label_list
*l
= si
->label_list
;
16141 mips_emit_delays ();
16142 if (log_size
> 0 && auto_align
)
16143 mips_align (log_size
, 0, l
);
16144 cons (1 << log_size
);
16145 mips_clear_insn_labels ();
16149 s_float_cons (int type
)
16151 segment_info_type
*si
= seg_info (now_seg
);
16152 struct insn_label_list
*l
= si
->label_list
;
16154 mips_emit_delays ();
16159 mips_align (3, 0, l
);
16161 mips_align (2, 0, l
);
16165 mips_clear_insn_labels ();
16168 /* Handle .globl. We need to override it because on Irix 5 you are
16171 where foo is an undefined symbol, to mean that foo should be
16172 considered to be the address of a function. */
16175 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16184 name
= input_line_pointer
;
16185 c
= get_symbol_end ();
16186 symbolP
= symbol_find_or_make (name
);
16187 S_SET_EXTERNAL (symbolP
);
16189 *input_line_pointer
= c
;
16190 SKIP_WHITESPACE ();
16192 /* On Irix 5, every global symbol that is not explicitly labelled as
16193 being a function is apparently labelled as being an object. */
16196 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16197 && (*input_line_pointer
!= ','))
16202 secname
= input_line_pointer
;
16203 c
= get_symbol_end ();
16204 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16206 as_bad (_("%s: no such section"), secname
);
16207 *input_line_pointer
= c
;
16209 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16210 flag
= BSF_FUNCTION
;
16213 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16215 c
= *input_line_pointer
;
16218 input_line_pointer
++;
16219 SKIP_WHITESPACE ();
16220 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16226 demand_empty_rest_of_line ();
16230 s_option (int x ATTRIBUTE_UNUSED
)
16235 opt
= input_line_pointer
;
16236 c
= get_symbol_end ();
16240 /* FIXME: What does this mean? */
16242 else if (strncmp (opt
, "pic", 3) == 0)
16246 i
= atoi (opt
+ 3);
16251 mips_pic
= SVR4_PIC
;
16252 mips_abicalls
= TRUE
;
16255 as_bad (_(".option pic%d not supported"), i
);
16257 if (mips_pic
== SVR4_PIC
)
16259 if (g_switch_seen
&& g_switch_value
!= 0)
16260 as_warn (_("-G may not be used with SVR4 PIC code"));
16261 g_switch_value
= 0;
16262 bfd_set_gp_size (stdoutput
, 0);
16266 as_warn (_("Unrecognized option \"%s\""), opt
);
16268 *input_line_pointer
= c
;
16269 demand_empty_rest_of_line ();
16272 /* This structure is used to hold a stack of .set values. */
16274 struct mips_option_stack
16276 struct mips_option_stack
*next
;
16277 struct mips_set_options options
;
16280 static struct mips_option_stack
*mips_opts_stack
;
16282 /* Handle the .set pseudo-op. */
16285 s_mipsset (int x ATTRIBUTE_UNUSED
)
16287 char *name
= input_line_pointer
, ch
;
16289 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16290 ++input_line_pointer
;
16291 ch
= *input_line_pointer
;
16292 *input_line_pointer
= '\0';
16294 if (strcmp (name
, "reorder") == 0)
16296 if (mips_opts
.noreorder
)
16299 else if (strcmp (name
, "noreorder") == 0)
16301 if (!mips_opts
.noreorder
)
16302 start_noreorder ();
16304 else if (strncmp (name
, "at=", 3) == 0)
16306 char *s
= name
+ 3;
16308 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16309 as_bad (_("Unrecognized register name `%s'"), s
);
16311 else if (strcmp (name
, "at") == 0)
16313 mips_opts
.at
= ATREG
;
16315 else if (strcmp (name
, "noat") == 0)
16317 mips_opts
.at
= ZERO
;
16319 else if (strcmp (name
, "macro") == 0)
16321 mips_opts
.warn_about_macros
= 0;
16323 else if (strcmp (name
, "nomacro") == 0)
16325 if (mips_opts
.noreorder
== 0)
16326 as_bad (_("`noreorder' must be set before `nomacro'"));
16327 mips_opts
.warn_about_macros
= 1;
16329 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16331 mips_opts
.nomove
= 0;
16333 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16335 mips_opts
.nomove
= 1;
16337 else if (strcmp (name
, "bopt") == 0)
16339 mips_opts
.nobopt
= 0;
16341 else if (strcmp (name
, "nobopt") == 0)
16343 mips_opts
.nobopt
= 1;
16345 else if (strcmp (name
, "gp=default") == 0)
16346 mips_opts
.gp32
= file_mips_gp32
;
16347 else if (strcmp (name
, "gp=32") == 0)
16348 mips_opts
.gp32
= 1;
16349 else if (strcmp (name
, "gp=64") == 0)
16351 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16352 as_warn (_("%s isa does not support 64-bit registers"),
16353 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16354 mips_opts
.gp32
= 0;
16356 else if (strcmp (name
, "fp=default") == 0)
16357 mips_opts
.fp32
= file_mips_fp32
;
16358 else if (strcmp (name
, "fp=32") == 0)
16359 mips_opts
.fp32
= 1;
16360 else if (strcmp (name
, "fp=64") == 0)
16362 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16363 as_warn (_("%s isa does not support 64-bit floating point registers"),
16364 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16365 mips_opts
.fp32
= 0;
16367 else if (strcmp (name
, "softfloat") == 0)
16368 mips_opts
.soft_float
= 1;
16369 else if (strcmp (name
, "hardfloat") == 0)
16370 mips_opts
.soft_float
= 0;
16371 else if (strcmp (name
, "singlefloat") == 0)
16372 mips_opts
.single_float
= 1;
16373 else if (strcmp (name
, "doublefloat") == 0)
16374 mips_opts
.single_float
= 0;
16375 else if (strcmp (name
, "mips16") == 0
16376 || strcmp (name
, "MIPS-16") == 0)
16378 if (mips_opts
.micromips
== 1)
16379 as_fatal (_("`mips16' cannot be used with `micromips'"));
16380 mips_opts
.mips16
= 1;
16382 else if (strcmp (name
, "nomips16") == 0
16383 || strcmp (name
, "noMIPS-16") == 0)
16384 mips_opts
.mips16
= 0;
16385 else if (strcmp (name
, "micromips") == 0)
16387 if (mips_opts
.mips16
== 1)
16388 as_fatal (_("`micromips' cannot be used with `mips16'"));
16389 mips_opts
.micromips
= 1;
16391 else if (strcmp (name
, "nomicromips") == 0)
16392 mips_opts
.micromips
= 0;
16393 else if (strcmp (name
, "smartmips") == 0)
16395 if (!ISA_SUPPORTS_SMARTMIPS
)
16396 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16397 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16398 mips_opts
.ase_smartmips
= 1;
16400 else if (strcmp (name
, "nosmartmips") == 0)
16401 mips_opts
.ase_smartmips
= 0;
16402 else if (strcmp (name
, "mips3d") == 0)
16403 mips_opts
.ase_mips3d
= 1;
16404 else if (strcmp (name
, "nomips3d") == 0)
16405 mips_opts
.ase_mips3d
= 0;
16406 else if (strcmp (name
, "mdmx") == 0)
16407 mips_opts
.ase_mdmx
= 1;
16408 else if (strcmp (name
, "nomdmx") == 0)
16409 mips_opts
.ase_mdmx
= 0;
16410 else if (strcmp (name
, "dsp") == 0)
16412 if (!ISA_SUPPORTS_DSP_ASE
)
16413 as_warn (_("%s ISA does not support DSP ASE"),
16414 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16415 mips_opts
.ase_dsp
= 1;
16416 mips_opts
.ase_dspr2
= 0;
16418 else if (strcmp (name
, "nodsp") == 0)
16420 mips_opts
.ase_dsp
= 0;
16421 mips_opts
.ase_dspr2
= 0;
16423 else if (strcmp (name
, "dspr2") == 0)
16425 if (!ISA_SUPPORTS_DSPR2_ASE
)
16426 as_warn (_("%s ISA does not support DSP R2 ASE"),
16427 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16428 mips_opts
.ase_dspr2
= 1;
16429 mips_opts
.ase_dsp
= 1;
16431 else if (strcmp (name
, "nodspr2") == 0)
16433 mips_opts
.ase_dspr2
= 0;
16434 mips_opts
.ase_dsp
= 0;
16436 else if (strcmp (name
, "mt") == 0)
16438 if (!ISA_SUPPORTS_MT_ASE
)
16439 as_warn (_("%s ISA does not support MT ASE"),
16440 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16441 mips_opts
.ase_mt
= 1;
16443 else if (strcmp (name
, "nomt") == 0)
16444 mips_opts
.ase_mt
= 0;
16445 else if (strcmp (name
, "mcu") == 0)
16446 mips_opts
.ase_mcu
= 1;
16447 else if (strcmp (name
, "nomcu") == 0)
16448 mips_opts
.ase_mcu
= 0;
16449 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16453 /* Permit the user to change the ISA and architecture on the fly.
16454 Needless to say, misuse can cause serious problems. */
16455 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16458 mips_opts
.isa
= file_mips_isa
;
16459 mips_opts
.arch
= file_mips_arch
;
16461 else if (strncmp (name
, "arch=", 5) == 0)
16463 const struct mips_cpu_info
*p
;
16465 p
= mips_parse_cpu("internal use", name
+ 5);
16467 as_bad (_("unknown architecture %s"), name
+ 5);
16470 mips_opts
.arch
= p
->cpu
;
16471 mips_opts
.isa
= p
->isa
;
16474 else if (strncmp (name
, "mips", 4) == 0)
16476 const struct mips_cpu_info
*p
;
16478 p
= mips_parse_cpu("internal use", name
);
16480 as_bad (_("unknown ISA level %s"), name
+ 4);
16483 mips_opts
.arch
= p
->cpu
;
16484 mips_opts
.isa
= p
->isa
;
16488 as_bad (_("unknown ISA or architecture %s"), name
);
16490 switch (mips_opts
.isa
)
16498 mips_opts
.gp32
= 1;
16499 mips_opts
.fp32
= 1;
16506 mips_opts
.gp32
= 0;
16507 if (mips_opts
.arch
== CPU_R5900
)
16509 mips_opts
.fp32
= 1;
16513 mips_opts
.fp32
= 0;
16517 as_bad (_("unknown ISA level %s"), name
+ 4);
16522 mips_opts
.gp32
= file_mips_gp32
;
16523 mips_opts
.fp32
= file_mips_fp32
;
16526 else if (strcmp (name
, "autoextend") == 0)
16527 mips_opts
.noautoextend
= 0;
16528 else if (strcmp (name
, "noautoextend") == 0)
16529 mips_opts
.noautoextend
= 1;
16530 else if (strcmp (name
, "push") == 0)
16532 struct mips_option_stack
*s
;
16534 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16535 s
->next
= mips_opts_stack
;
16536 s
->options
= mips_opts
;
16537 mips_opts_stack
= s
;
16539 else if (strcmp (name
, "pop") == 0)
16541 struct mips_option_stack
*s
;
16543 s
= mips_opts_stack
;
16545 as_bad (_(".set pop with no .set push"));
16548 /* If we're changing the reorder mode we need to handle
16549 delay slots correctly. */
16550 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16551 start_noreorder ();
16552 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16555 mips_opts
= s
->options
;
16556 mips_opts_stack
= s
->next
;
16560 else if (strcmp (name
, "sym32") == 0)
16561 mips_opts
.sym32
= TRUE
;
16562 else if (strcmp (name
, "nosym32") == 0)
16563 mips_opts
.sym32
= FALSE
;
16564 else if (strchr (name
, ','))
16566 /* Generic ".set" directive; use the generic handler. */
16567 *input_line_pointer
= ch
;
16568 input_line_pointer
= name
;
16574 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16576 *input_line_pointer
= ch
;
16577 demand_empty_rest_of_line ();
16580 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16581 .option pic2. It means to generate SVR4 PIC calls. */
16584 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16586 mips_pic
= SVR4_PIC
;
16587 mips_abicalls
= TRUE
;
16589 if (g_switch_seen
&& g_switch_value
!= 0)
16590 as_warn (_("-G may not be used with SVR4 PIC code"));
16591 g_switch_value
= 0;
16593 bfd_set_gp_size (stdoutput
, 0);
16594 demand_empty_rest_of_line ();
16597 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16598 PIC code. It sets the $gp register for the function based on the
16599 function address, which is in the register named in the argument.
16600 This uses a relocation against _gp_disp, which is handled specially
16601 by the linker. The result is:
16602 lui $gp,%hi(_gp_disp)
16603 addiu $gp,$gp,%lo(_gp_disp)
16604 addu $gp,$gp,.cpload argument
16605 The .cpload argument is normally $25 == $t9.
16607 The -mno-shared option changes this to:
16608 lui $gp,%hi(__gnu_local_gp)
16609 addiu $gp,$gp,%lo(__gnu_local_gp)
16610 and the argument is ignored. This saves an instruction, but the
16611 resulting code is not position independent; it uses an absolute
16612 address for __gnu_local_gp. Thus code assembled with -mno-shared
16613 can go into an ordinary executable, but not into a shared library. */
16616 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16622 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16623 .cpload is ignored. */
16624 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16630 if (mips_opts
.mips16
)
16632 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16633 ignore_rest_of_line ();
16637 /* .cpload should be in a .set noreorder section. */
16638 if (mips_opts
.noreorder
== 0)
16639 as_warn (_(".cpload not in noreorder section"));
16641 reg
= tc_get_register (0);
16643 /* If we need to produce a 64-bit address, we are better off using
16644 the default instruction sequence. */
16645 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16647 ex
.X_op
= O_symbol
;
16648 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16650 ex
.X_op_symbol
= NULL
;
16651 ex
.X_add_number
= 0;
16653 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16654 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16656 mips_mark_labels ();
16657 mips_assembling_insn
= TRUE
;
16660 macro_build_lui (&ex
, mips_gp_register
);
16661 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16662 mips_gp_register
, BFD_RELOC_LO16
);
16664 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16665 mips_gp_register
, reg
);
16668 mips_assembling_insn
= FALSE
;
16669 demand_empty_rest_of_line ();
16672 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16673 .cpsetup $reg1, offset|$reg2, label
16675 If offset is given, this results in:
16676 sd $gp, offset($sp)
16677 lui $gp, %hi(%neg(%gp_rel(label)))
16678 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16679 daddu $gp, $gp, $reg1
16681 If $reg2 is given, this results in:
16682 daddu $reg2, $gp, $0
16683 lui $gp, %hi(%neg(%gp_rel(label)))
16684 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16685 daddu $gp, $gp, $reg1
16686 $reg1 is normally $25 == $t9.
16688 The -mno-shared option replaces the last three instructions with
16690 addiu $gp,$gp,%lo(_gp) */
16693 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16695 expressionS ex_off
;
16696 expressionS ex_sym
;
16699 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16700 We also need NewABI support. */
16701 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16707 if (mips_opts
.mips16
)
16709 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16710 ignore_rest_of_line ();
16714 reg1
= tc_get_register (0);
16715 SKIP_WHITESPACE ();
16716 if (*input_line_pointer
!= ',')
16718 as_bad (_("missing argument separator ',' for .cpsetup"));
16722 ++input_line_pointer
;
16723 SKIP_WHITESPACE ();
16724 if (*input_line_pointer
== '$')
16726 mips_cpreturn_register
= tc_get_register (0);
16727 mips_cpreturn_offset
= -1;
16731 mips_cpreturn_offset
= get_absolute_expression ();
16732 mips_cpreturn_register
= -1;
16734 SKIP_WHITESPACE ();
16735 if (*input_line_pointer
!= ',')
16737 as_bad (_("missing argument separator ',' for .cpsetup"));
16741 ++input_line_pointer
;
16742 SKIP_WHITESPACE ();
16743 expression (&ex_sym
);
16745 mips_mark_labels ();
16746 mips_assembling_insn
= TRUE
;
16749 if (mips_cpreturn_register
== -1)
16751 ex_off
.X_op
= O_constant
;
16752 ex_off
.X_add_symbol
= NULL
;
16753 ex_off
.X_op_symbol
= NULL
;
16754 ex_off
.X_add_number
= mips_cpreturn_offset
;
16756 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16757 BFD_RELOC_LO16
, SP
);
16760 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16761 mips_gp_register
, 0);
16763 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16765 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16766 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16769 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16770 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16771 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16773 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16774 mips_gp_register
, reg1
);
16780 ex
.X_op
= O_symbol
;
16781 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16782 ex
.X_op_symbol
= NULL
;
16783 ex
.X_add_number
= 0;
16785 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16786 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16788 macro_build_lui (&ex
, mips_gp_register
);
16789 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16790 mips_gp_register
, BFD_RELOC_LO16
);
16795 mips_assembling_insn
= FALSE
;
16796 demand_empty_rest_of_line ();
16800 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16802 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16803 .cplocal is ignored. */
16804 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16810 if (mips_opts
.mips16
)
16812 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16813 ignore_rest_of_line ();
16817 mips_gp_register
= tc_get_register (0);
16818 demand_empty_rest_of_line ();
16821 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16822 offset from $sp. The offset is remembered, and after making a PIC
16823 call $gp is restored from that location. */
16826 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16830 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16831 .cprestore is ignored. */
16832 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16838 if (mips_opts
.mips16
)
16840 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16841 ignore_rest_of_line ();
16845 mips_cprestore_offset
= get_absolute_expression ();
16846 mips_cprestore_valid
= 1;
16848 ex
.X_op
= O_constant
;
16849 ex
.X_add_symbol
= NULL
;
16850 ex
.X_op_symbol
= NULL
;
16851 ex
.X_add_number
= mips_cprestore_offset
;
16853 mips_mark_labels ();
16854 mips_assembling_insn
= TRUE
;
16857 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16858 SP
, HAVE_64BIT_ADDRESSES
);
16861 mips_assembling_insn
= FALSE
;
16862 demand_empty_rest_of_line ();
16865 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16866 was given in the preceding .cpsetup, it results in:
16867 ld $gp, offset($sp)
16869 If a register $reg2 was given there, it results in:
16870 daddu $gp, $reg2, $0 */
16873 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16877 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16878 We also need NewABI support. */
16879 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16885 if (mips_opts
.mips16
)
16887 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16888 ignore_rest_of_line ();
16892 mips_mark_labels ();
16893 mips_assembling_insn
= TRUE
;
16896 if (mips_cpreturn_register
== -1)
16898 ex
.X_op
= O_constant
;
16899 ex
.X_add_symbol
= NULL
;
16900 ex
.X_op_symbol
= NULL
;
16901 ex
.X_add_number
= mips_cpreturn_offset
;
16903 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16906 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16907 mips_cpreturn_register
, 0);
16910 mips_assembling_insn
= FALSE
;
16911 demand_empty_rest_of_line ();
16914 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16915 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16916 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16917 debug information or MIPS16 TLS. */
16920 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16921 bfd_reloc_code_real_type rtype
)
16928 if (ex
.X_op
!= O_symbol
)
16930 as_bad (_("Unsupported use of %s"), dirstr
);
16931 ignore_rest_of_line ();
16934 p
= frag_more (bytes
);
16935 md_number_to_chars (p
, 0, bytes
);
16936 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16937 demand_empty_rest_of_line ();
16938 mips_clear_insn_labels ();
16941 /* Handle .dtprelword. */
16944 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16946 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16949 /* Handle .dtpreldword. */
16952 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16954 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16957 /* Handle .tprelword. */
16960 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16962 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16965 /* Handle .tpreldword. */
16968 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16970 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16973 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16974 code. It sets the offset to use in gp_rel relocations. */
16977 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16979 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16980 We also need NewABI support. */
16981 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16987 mips_gprel_offset
= get_absolute_expression ();
16989 demand_empty_rest_of_line ();
16992 /* Handle the .gpword pseudo-op. This is used when generating PIC
16993 code. It generates a 32 bit GP relative reloc. */
16996 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16998 segment_info_type
*si
;
16999 struct insn_label_list
*l
;
17003 /* When not generating PIC code, this is treated as .word. */
17004 if (mips_pic
!= SVR4_PIC
)
17010 si
= seg_info (now_seg
);
17011 l
= si
->label_list
;
17012 mips_emit_delays ();
17014 mips_align (2, 0, l
);
17017 mips_clear_insn_labels ();
17019 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17021 as_bad (_("Unsupported use of .gpword"));
17022 ignore_rest_of_line ();
17026 md_number_to_chars (p
, 0, 4);
17027 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17028 BFD_RELOC_GPREL32
);
17030 demand_empty_rest_of_line ();
17034 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17036 segment_info_type
*si
;
17037 struct insn_label_list
*l
;
17041 /* When not generating PIC code, this is treated as .dword. */
17042 if (mips_pic
!= SVR4_PIC
)
17048 si
= seg_info (now_seg
);
17049 l
= si
->label_list
;
17050 mips_emit_delays ();
17052 mips_align (3, 0, l
);
17055 mips_clear_insn_labels ();
17057 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17059 as_bad (_("Unsupported use of .gpdword"));
17060 ignore_rest_of_line ();
17064 md_number_to_chars (p
, 0, 8);
17065 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17066 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17068 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17069 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17070 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17072 demand_empty_rest_of_line ();
17075 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17076 tables in SVR4 PIC code. */
17079 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17083 /* This is ignored when not generating SVR4 PIC code. */
17084 if (mips_pic
!= SVR4_PIC
)
17090 mips_mark_labels ();
17091 mips_assembling_insn
= TRUE
;
17093 /* Add $gp to the register named as an argument. */
17095 reg
= tc_get_register (0);
17096 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17099 mips_assembling_insn
= FALSE
;
17100 demand_empty_rest_of_line ();
17103 /* Handle the .insn pseudo-op. This marks instruction labels in
17104 mips16/micromips mode. This permits the linker to handle them specially,
17105 such as generating jalx instructions when needed. We also make
17106 them odd for the duration of the assembly, in order to generate the
17107 right sort of code. We will make them even in the adjust_symtab
17108 routine, while leaving them marked. This is convenient for the
17109 debugger and the disassembler. The linker knows to make them odd
17113 s_insn (int ignore ATTRIBUTE_UNUSED
)
17115 mips_mark_labels ();
17117 demand_empty_rest_of_line ();
17120 /* Handle a .stab[snd] directive. Ideally these directives would be
17121 implemented in a transparent way, so that removing them would not
17122 have any effect on the generated instructions. However, s_stab
17123 internally changes the section, so in practice we need to decide
17124 now whether the preceding label marks compressed code. We do not
17125 support changing the compression mode of a label after a .stab*
17126 directive, such as in:
17132 so the current mode wins. */
17135 s_mips_stab (int type
)
17137 mips_mark_labels ();
17141 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17144 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17151 name
= input_line_pointer
;
17152 c
= get_symbol_end ();
17153 symbolP
= symbol_find_or_make (name
);
17154 S_SET_WEAK (symbolP
);
17155 *input_line_pointer
= c
;
17157 SKIP_WHITESPACE ();
17159 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17161 if (S_IS_DEFINED (symbolP
))
17163 as_bad (_("ignoring attempt to redefine symbol %s"),
17164 S_GET_NAME (symbolP
));
17165 ignore_rest_of_line ();
17169 if (*input_line_pointer
== ',')
17171 ++input_line_pointer
;
17172 SKIP_WHITESPACE ();
17176 if (exp
.X_op
!= O_symbol
)
17178 as_bad (_("bad .weakext directive"));
17179 ignore_rest_of_line ();
17182 symbol_set_value_expression (symbolP
, &exp
);
17185 demand_empty_rest_of_line ();
17188 /* Parse a register string into a number. Called from the ECOFF code
17189 to parse .frame. The argument is non-zero if this is the frame
17190 register, so that we can record it in mips_frame_reg. */
17193 tc_get_register (int frame
)
17197 SKIP_WHITESPACE ();
17198 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17202 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17203 mips_frame_reg_valid
= 1;
17204 mips_cprestore_valid
= 0;
17210 md_section_align (asection
*seg
, valueT addr
)
17212 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17216 /* We don't need to align ELF sections to the full alignment.
17217 However, Irix 5 may prefer that we align them at least to a 16
17218 byte boundary. We don't bother to align the sections if we
17219 are targeted for an embedded system. */
17220 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17226 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17229 /* Utility routine, called from above as well. If called while the
17230 input file is still being read, it's only an approximation. (For
17231 example, a symbol may later become defined which appeared to be
17232 undefined earlier.) */
17235 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17240 if (g_switch_value
> 0)
17242 const char *symname
;
17245 /* Find out whether this symbol can be referenced off the $gp
17246 register. It can be if it is smaller than the -G size or if
17247 it is in the .sdata or .sbss section. Certain symbols can
17248 not be referenced off the $gp, although it appears as though
17250 symname
= S_GET_NAME (sym
);
17251 if (symname
!= (const char *) NULL
17252 && (strcmp (symname
, "eprol") == 0
17253 || strcmp (symname
, "etext") == 0
17254 || strcmp (symname
, "_gp") == 0
17255 || strcmp (symname
, "edata") == 0
17256 || strcmp (symname
, "_fbss") == 0
17257 || strcmp (symname
, "_fdata") == 0
17258 || strcmp (symname
, "_ftext") == 0
17259 || strcmp (symname
, "end") == 0
17260 || strcmp (symname
, "_gp_disp") == 0))
17262 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17264 #ifndef NO_ECOFF_DEBUGGING
17265 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17266 && (symbol_get_obj (sym
)->ecoff_extern_size
17267 <= g_switch_value
))
17269 /* We must defer this decision until after the whole
17270 file has been read, since there might be a .extern
17271 after the first use of this symbol. */
17272 || (before_relaxing
17273 #ifndef NO_ECOFF_DEBUGGING
17274 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17276 && S_GET_VALUE (sym
) == 0)
17277 || (S_GET_VALUE (sym
) != 0
17278 && S_GET_VALUE (sym
) <= g_switch_value
)))
17282 const char *segname
;
17284 segname
= segment_name (S_GET_SEGMENT (sym
));
17285 gas_assert (strcmp (segname
, ".lit8") != 0
17286 && strcmp (segname
, ".lit4") != 0);
17287 change
= (strcmp (segname
, ".sdata") != 0
17288 && strcmp (segname
, ".sbss") != 0
17289 && strncmp (segname
, ".sdata.", 7) != 0
17290 && strncmp (segname
, ".sbss.", 6) != 0
17291 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17292 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17297 /* We are not optimizing for the $gp register. */
17302 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17305 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17309 /* Handle the case of a symbol equated to another symbol. */
17310 while (symbol_equated_reloc_p (sym
))
17314 /* It's possible to get a loop here in a badly written program. */
17315 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17321 if (symbol_section_p (sym
))
17324 symsec
= S_GET_SEGMENT (sym
);
17326 /* This must duplicate the test in adjust_reloc_syms. */
17327 return (!bfd_is_und_section (symsec
)
17328 && !bfd_is_abs_section (symsec
)
17329 && !bfd_is_com_section (symsec
)
17330 && !s_is_linkonce (sym
, segtype
)
17332 /* A global or weak symbol is treated as external. */
17333 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17339 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17340 extended opcode. SEC is the section the frag is in. */
17343 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17346 const struct mips16_immed_operand
*op
;
17348 int mintiny
, maxtiny
;
17352 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17354 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17357 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17358 op
= mips16_immed_operands
;
17359 while (op
->type
!= type
)
17362 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17367 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17370 maxtiny
= 1 << op
->nbits
;
17375 maxtiny
= (1 << op
->nbits
) - 1;
17380 mintiny
= - (1 << (op
->nbits
- 1));
17381 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17384 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17385 val
= S_GET_VALUE (fragp
->fr_symbol
);
17386 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17392 /* We won't have the section when we are called from
17393 mips_relax_frag. However, we will always have been called
17394 from md_estimate_size_before_relax first. If this is a
17395 branch to a different section, we mark it as such. If SEC is
17396 NULL, and the frag is not marked, then it must be a branch to
17397 the same section. */
17400 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17405 /* Must have been called from md_estimate_size_before_relax. */
17408 fragp
->fr_subtype
=
17409 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17411 /* FIXME: We should support this, and let the linker
17412 catch branches and loads that are out of range. */
17413 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17414 _("unsupported PC relative reference to different section"));
17418 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17419 /* Assume non-extended on the first relaxation pass.
17420 The address we have calculated will be bogus if this is
17421 a forward branch to another frag, as the forward frag
17422 will have fr_address == 0. */
17426 /* In this case, we know for sure that the symbol fragment is in
17427 the same section. If the relax_marker of the symbol fragment
17428 differs from the relax_marker of this fragment, we have not
17429 yet adjusted the symbol fragment fr_address. We want to add
17430 in STRETCH in order to get a better estimate of the address.
17431 This particularly matters because of the shift bits. */
17433 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17437 /* Adjust stretch for any alignment frag. Note that if have
17438 been expanding the earlier code, the symbol may be
17439 defined in what appears to be an earlier frag. FIXME:
17440 This doesn't handle the fr_subtype field, which specifies
17441 a maximum number of bytes to skip when doing an
17443 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17445 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17448 stretch
= - ((- stretch
)
17449 & ~ ((1 << (int) f
->fr_offset
) - 1));
17451 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17460 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17462 /* The base address rules are complicated. The base address of
17463 a branch is the following instruction. The base address of a
17464 PC relative load or add is the instruction itself, but if it
17465 is in a delay slot (in which case it can not be extended) use
17466 the address of the instruction whose delay slot it is in. */
17467 if (type
== 'p' || type
== 'q')
17471 /* If we are currently assuming that this frag should be
17472 extended, then, the current address is two bytes
17474 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17477 /* Ignore the low bit in the target, since it will be set
17478 for a text label. */
17479 if ((val
& 1) != 0)
17482 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17484 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17487 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17489 /* Branch offsets have an implicit 0 in the lowest bit. */
17490 if (type
== 'p' || type
== 'q')
17493 /* If any of the shifted bits are set, we must use an extended
17494 opcode. If the address depends on the size of this
17495 instruction, this can lead to a loop, so we arrange to always
17496 use an extended opcode. We only check this when we are in
17497 the main relaxation loop, when SEC is NULL. */
17498 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17500 fragp
->fr_subtype
=
17501 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17505 /* If we are about to mark a frag as extended because the value
17506 is precisely maxtiny + 1, then there is a chance of an
17507 infinite loop as in the following code:
17512 In this case when the la is extended, foo is 0x3fc bytes
17513 away, so the la can be shrunk, but then foo is 0x400 away, so
17514 the la must be extended. To avoid this loop, we mark the
17515 frag as extended if it was small, and is about to become
17516 extended with a value of maxtiny + 1. */
17517 if (val
== ((maxtiny
+ 1) << op
->shift
)
17518 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17521 fragp
->fr_subtype
=
17522 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17526 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17527 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17529 if ((val
& ((1 << op
->shift
) - 1)) != 0
17530 || val
< (mintiny
<< op
->shift
)
17531 || val
> (maxtiny
<< op
->shift
))
17537 /* Compute the length of a branch sequence, and adjust the
17538 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17539 worst-case length is computed, with UPDATE being used to indicate
17540 whether an unconditional (-1), branch-likely (+1) or regular (0)
17541 branch is to be computed. */
17543 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17545 bfd_boolean toofar
;
17549 && S_IS_DEFINED (fragp
->fr_symbol
)
17550 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17555 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17557 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17561 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17564 /* If the symbol is not defined or it's in a different segment,
17565 assume the user knows what's going on and emit a short
17571 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17573 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17574 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17575 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17576 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17582 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17585 if (mips_pic
!= NO_PIC
)
17587 /* Additional space for PIC loading of target address. */
17589 if (mips_opts
.isa
== ISA_MIPS1
)
17590 /* Additional space for $at-stabilizing nop. */
17594 /* If branch is conditional. */
17595 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17602 /* Compute the length of a branch sequence, and adjust the
17603 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17604 worst-case length is computed, with UPDATE being used to indicate
17605 whether an unconditional (-1), or regular (0) branch is to be
17609 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17611 bfd_boolean toofar
;
17615 && S_IS_DEFINED (fragp
->fr_symbol
)
17616 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17621 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17622 /* Ignore the low bit in the target, since it will be set
17623 for a text label. */
17624 if ((val
& 1) != 0)
17627 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17631 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17634 /* If the symbol is not defined or it's in a different segment,
17635 assume the user knows what's going on and emit a short
17641 if (fragp
&& update
17642 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17643 fragp
->fr_subtype
= (toofar
17644 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17645 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17650 bfd_boolean compact_known
= fragp
!= NULL
;
17651 bfd_boolean compact
= FALSE
;
17652 bfd_boolean uncond
;
17655 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17657 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17659 uncond
= update
< 0;
17661 /* If label is out of range, we turn branch <br>:
17663 <br> label # 4 bytes
17669 nop # 2 bytes if compact && !PIC
17672 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17675 /* If assembling PIC code, we further turn:
17681 lw/ld at, %got(label)(gp) # 4 bytes
17682 d/addiu at, %lo(label) # 4 bytes
17685 if (mips_pic
!= NO_PIC
)
17688 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17690 <brneg> 0f # 4 bytes
17691 nop # 2 bytes if !compact
17694 length
+= (compact_known
&& compact
) ? 4 : 6;
17700 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17701 bit accordingly. */
17704 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17706 bfd_boolean toofar
;
17709 && S_IS_DEFINED (fragp
->fr_symbol
)
17710 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17716 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17717 /* Ignore the low bit in the target, since it will be set
17718 for a text label. */
17719 if ((val
& 1) != 0)
17722 /* Assume this is a 2-byte branch. */
17723 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17725 /* We try to avoid the infinite loop by not adding 2 more bytes for
17730 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17732 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17733 else if (type
== 'E')
17734 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17739 /* If the symbol is not defined or it's in a different segment,
17740 we emit a normal 32-bit branch. */
17743 if (fragp
&& update
17744 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17746 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17747 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17755 /* Estimate the size of a frag before relaxing. Unless this is the
17756 mips16, we are not really relaxing here, and the final size is
17757 encoded in the subtype information. For the mips16, we have to
17758 decide whether we are using an extended opcode or not. */
17761 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17765 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17768 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17770 return fragp
->fr_var
;
17773 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17774 /* We don't want to modify the EXTENDED bit here; it might get us
17775 into infinite loops. We change it only in mips_relax_frag(). */
17776 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17778 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17782 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17783 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17784 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17785 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17786 fragp
->fr_var
= length
;
17791 if (mips_pic
== NO_PIC
)
17792 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17793 else if (mips_pic
== SVR4_PIC
)
17794 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17795 else if (mips_pic
== VXWORKS_PIC
)
17796 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17803 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17804 return -RELAX_FIRST (fragp
->fr_subtype
);
17807 return -RELAX_SECOND (fragp
->fr_subtype
);
17810 /* This is called to see whether a reloc against a defined symbol
17811 should be converted into a reloc against a section. */
17814 mips_fix_adjustable (fixS
*fixp
)
17816 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17817 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17820 if (fixp
->fx_addsy
== NULL
)
17823 /* If symbol SYM is in a mergeable section, relocations of the form
17824 SYM + 0 can usually be made section-relative. The mergeable data
17825 is then identified by the section offset rather than by the symbol.
17827 However, if we're generating REL LO16 relocations, the offset is split
17828 between the LO16 and parterning high part relocation. The linker will
17829 need to recalculate the complete offset in order to correctly identify
17832 The linker has traditionally not looked for the parterning high part
17833 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17834 placed anywhere. Rather than break backwards compatibility by changing
17835 this, it seems better not to force the issue, and instead keep the
17836 original symbol. This will work with either linker behavior. */
17837 if ((lo16_reloc_p (fixp
->fx_r_type
)
17838 || reloc_needs_lo_p (fixp
->fx_r_type
))
17839 && HAVE_IN_PLACE_ADDENDS
17840 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17843 /* There is no place to store an in-place offset for JALR relocations.
17844 Likewise an in-range offset of limited PC-relative relocations may
17845 overflow the in-place relocatable field if recalculated against the
17846 start address of the symbol's containing section. */
17847 if (HAVE_IN_PLACE_ADDENDS
17848 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17849 || jalr_reloc_p (fixp
->fx_r_type
)))
17853 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17854 to a floating-point stub. The same is true for non-R_MIPS16_26
17855 relocations against MIPS16 functions; in this case, the stub becomes
17856 the function's canonical address.
17858 Floating-point stubs are stored in unique .mips16.call.* or
17859 .mips16.fn.* sections. If a stub T for function F is in section S,
17860 the first relocation in section S must be against F; this is how the
17861 linker determines the target function. All relocations that might
17862 resolve to T must also be against F. We therefore have the following
17863 restrictions, which are given in an intentionally-redundant way:
17865 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17868 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17869 if that stub might be used.
17871 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17874 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17875 that stub might be used.
17877 There is a further restriction:
17879 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17880 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17881 targets with in-place addends; the relocation field cannot
17882 encode the low bit.
17884 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17885 against a MIPS16 symbol. We deal with (5) by by not reducing any
17886 such relocations on REL targets.
17888 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17889 relocation against some symbol R, no relocation against R may be
17890 reduced. (Note that this deals with (2) as well as (1) because
17891 relocations against global symbols will never be reduced on ELF
17892 targets.) This approach is a little simpler than trying to detect
17893 stub sections, and gives the "all or nothing" per-symbol consistency
17894 that we have for MIPS16 symbols. */
17896 && fixp
->fx_subsy
== NULL
17897 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17898 || *symbol_get_tc (fixp
->fx_addsy
)
17899 || (HAVE_IN_PLACE_ADDENDS
17900 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17901 && jmp_reloc_p (fixp
->fx_r_type
))))
17908 /* Translate internal representation of relocation info to BFD target
17912 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17914 static arelent
*retval
[4];
17916 bfd_reloc_code_real_type code
;
17918 memset (retval
, 0, sizeof(retval
));
17919 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17920 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17921 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17922 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17924 if (fixp
->fx_pcrel
)
17926 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17927 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17928 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17929 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17930 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
17932 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17933 Relocations want only the symbol offset. */
17934 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17937 /* A gruesome hack which is a result of the gruesome gas
17938 reloc handling. What's worse, for COFF (as opposed to
17939 ECOFF), we might need yet another copy of reloc->address.
17940 See bfd_install_relocation. */
17941 reloc
->addend
+= reloc
->address
;
17945 reloc
->addend
= fixp
->fx_addnumber
;
17947 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17948 entry to be used in the relocation's section offset. */
17949 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17951 reloc
->address
= reloc
->addend
;
17955 code
= fixp
->fx_r_type
;
17957 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17958 if (reloc
->howto
== NULL
)
17960 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17961 _("Can not represent %s relocation in this object file format"),
17962 bfd_get_reloc_code_name (code
));
17969 /* Relax a machine dependent frag. This returns the amount by which
17970 the current size of the frag should change. */
17973 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17975 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17977 offsetT old_var
= fragp
->fr_var
;
17979 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17981 return fragp
->fr_var
- old_var
;
17984 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17986 offsetT old_var
= fragp
->fr_var
;
17987 offsetT new_var
= 4;
17989 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17990 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17991 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17992 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17993 fragp
->fr_var
= new_var
;
17995 return new_var
- old_var
;
17998 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18001 if (mips16_extended_frag (fragp
, NULL
, stretch
))
18003 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18005 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18010 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18012 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18019 /* Convert a machine dependent frag. */
18022 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18024 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18027 unsigned long insn
;
18031 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18032 insn
= read_insn (buf
);
18034 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18036 /* We generate a fixup instead of applying it right now
18037 because, if there are linker relaxations, we're going to
18038 need the relocations. */
18039 exp
.X_op
= O_symbol
;
18040 exp
.X_add_symbol
= fragp
->fr_symbol
;
18041 exp
.X_add_number
= fragp
->fr_offset
;
18043 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18044 BFD_RELOC_16_PCREL_S2
);
18045 fixp
->fx_file
= fragp
->fr_file
;
18046 fixp
->fx_line
= fragp
->fr_line
;
18048 buf
= write_insn (buf
, insn
);
18054 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18055 _("Relaxed out-of-range branch into a jump"));
18057 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18060 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18062 /* Reverse the branch. */
18063 switch ((insn
>> 28) & 0xf)
18066 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
18067 have the condition reversed by tweaking a single
18068 bit, and their opcodes all have 0x4???????. */
18069 gas_assert ((insn
& 0xf1000000) == 0x41000000);
18070 insn
^= 0x00010000;
18074 /* bltz 0x04000000 bgez 0x04010000
18075 bltzal 0x04100000 bgezal 0x04110000 */
18076 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18077 insn
^= 0x00010000;
18081 /* beq 0x10000000 bne 0x14000000
18082 blez 0x18000000 bgtz 0x1c000000 */
18083 insn
^= 0x04000000;
18091 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18093 /* Clear the and-link bit. */
18094 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18096 /* bltzal 0x04100000 bgezal 0x04110000
18097 bltzall 0x04120000 bgezall 0x04130000 */
18098 insn
&= ~0x00100000;
18101 /* Branch over the branch (if the branch was likely) or the
18102 full jump (not likely case). Compute the offset from the
18103 current instruction to branch to. */
18104 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18108 /* How many bytes in instructions we've already emitted? */
18109 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18110 /* How many bytes in instructions from here to the end? */
18111 i
= fragp
->fr_var
- i
;
18113 /* Convert to instruction count. */
18115 /* Branch counts from the next instruction. */
18118 /* Branch over the jump. */
18119 buf
= write_insn (buf
, insn
);
18122 buf
= write_insn (buf
, 0);
18124 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18126 /* beql $0, $0, 2f */
18128 /* Compute the PC offset from the current instruction to
18129 the end of the variable frag. */
18130 /* How many bytes in instructions we've already emitted? */
18131 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18132 /* How many bytes in instructions from here to the end? */
18133 i
= fragp
->fr_var
- i
;
18134 /* Convert to instruction count. */
18136 /* Don't decrement i, because we want to branch over the
18140 buf
= write_insn (buf
, insn
);
18141 buf
= write_insn (buf
, 0);
18145 if (mips_pic
== NO_PIC
)
18148 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18149 ? 0x0c000000 : 0x08000000);
18150 exp
.X_op
= O_symbol
;
18151 exp
.X_add_symbol
= fragp
->fr_symbol
;
18152 exp
.X_add_number
= fragp
->fr_offset
;
18154 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18155 FALSE
, BFD_RELOC_MIPS_JMP
);
18156 fixp
->fx_file
= fragp
->fr_file
;
18157 fixp
->fx_line
= fragp
->fr_line
;
18159 buf
= write_insn (buf
, insn
);
18163 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18165 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18166 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18167 insn
|= at
<< OP_SH_RT
;
18168 exp
.X_op
= O_symbol
;
18169 exp
.X_add_symbol
= fragp
->fr_symbol
;
18170 exp
.X_add_number
= fragp
->fr_offset
;
18172 if (fragp
->fr_offset
)
18174 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18175 exp
.X_add_number
= 0;
18178 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18179 FALSE
, BFD_RELOC_MIPS_GOT16
);
18180 fixp
->fx_file
= fragp
->fr_file
;
18181 fixp
->fx_line
= fragp
->fr_line
;
18183 buf
= write_insn (buf
, insn
);
18185 if (mips_opts
.isa
== ISA_MIPS1
)
18187 buf
= write_insn (buf
, 0);
18189 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18190 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18191 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18193 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18194 FALSE
, BFD_RELOC_LO16
);
18195 fixp
->fx_file
= fragp
->fr_file
;
18196 fixp
->fx_line
= fragp
->fr_line
;
18198 buf
= write_insn (buf
, insn
);
18201 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18205 insn
|= at
<< OP_SH_RS
;
18207 buf
= write_insn (buf
, insn
);
18211 fragp
->fr_fix
+= fragp
->fr_var
;
18212 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18216 /* Relax microMIPS branches. */
18217 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18219 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18220 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18221 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18222 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18223 bfd_boolean short_ds
;
18224 unsigned long insn
;
18228 exp
.X_op
= O_symbol
;
18229 exp
.X_add_symbol
= fragp
->fr_symbol
;
18230 exp
.X_add_number
= fragp
->fr_offset
;
18232 fragp
->fr_fix
+= fragp
->fr_var
;
18234 /* Handle 16-bit branches that fit or are forced to fit. */
18235 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18237 /* We generate a fixup instead of applying it right now,
18238 because if there is linker relaxation, we're going to
18239 need the relocations. */
18241 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18242 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18243 else if (type
== 'E')
18244 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18245 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18249 fixp
->fx_file
= fragp
->fr_file
;
18250 fixp
->fx_line
= fragp
->fr_line
;
18252 /* These relocations can have an addend that won't fit in
18254 fixp
->fx_no_overflow
= 1;
18259 /* Handle 32-bit branches that fit or are forced to fit. */
18260 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18261 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18263 /* We generate a fixup instead of applying it right now,
18264 because if there is linker relaxation, we're going to
18265 need the relocations. */
18266 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18267 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18268 fixp
->fx_file
= fragp
->fr_file
;
18269 fixp
->fx_line
= fragp
->fr_line
;
18275 /* Relax 16-bit branches to 32-bit branches. */
18278 insn
= read_compressed_insn (buf
, 2);
18280 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18281 insn
= 0x94000000; /* beq */
18282 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18284 unsigned long regno
;
18286 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18287 regno
= micromips_to_32_reg_d_map
[regno
];
18288 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18289 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18294 /* Nothing else to do, just write it out. */
18295 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18296 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18298 buf
= write_compressed_insn (buf
, insn
, 4);
18299 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18304 insn
= read_compressed_insn (buf
, 4);
18306 /* Relax 32-bit branches to a sequence of instructions. */
18307 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18308 _("Relaxed out-of-range branch into a jump"));
18310 /* Set the short-delay-slot bit. */
18311 short_ds
= al
&& (insn
& 0x02000000) != 0;
18313 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18317 /* Reverse the branch. */
18318 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18319 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18320 insn
^= 0x20000000;
18321 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18322 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18323 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18324 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18325 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18326 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18327 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18328 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18329 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18330 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18331 insn
^= 0x00400000;
18332 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18333 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18334 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18335 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18336 insn
^= 0x00200000;
18342 /* Clear the and-link and short-delay-slot bits. */
18343 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18345 /* bltzal 0x40200000 bgezal 0x40600000 */
18346 /* bltzals 0x42200000 bgezals 0x42600000 */
18347 insn
&= ~0x02200000;
18350 /* Make a label at the end for use with the branch. */
18351 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18352 micromips_label_inc ();
18353 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18355 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18359 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18360 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18361 fixp
->fx_file
= fragp
->fr_file
;
18362 fixp
->fx_line
= fragp
->fr_line
;
18364 /* Branch over the jump. */
18365 buf
= write_compressed_insn (buf
, insn
, 4);
18368 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18371 if (mips_pic
== NO_PIC
)
18373 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18375 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18376 insn
= al
? jal
: 0xd4000000;
18378 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18379 BFD_RELOC_MICROMIPS_JMP
);
18380 fixp
->fx_file
= fragp
->fr_file
;
18381 fixp
->fx_line
= fragp
->fr_line
;
18383 buf
= write_compressed_insn (buf
, insn
, 4);
18386 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18390 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18391 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18392 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18394 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18395 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18396 insn
|= at
<< MICROMIPSOP_SH_RT
;
18398 if (exp
.X_add_number
)
18400 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18401 exp
.X_add_number
= 0;
18404 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18405 BFD_RELOC_MICROMIPS_GOT16
);
18406 fixp
->fx_file
= fragp
->fr_file
;
18407 fixp
->fx_line
= fragp
->fr_line
;
18409 buf
= write_compressed_insn (buf
, insn
, 4);
18411 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18412 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18413 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18415 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18416 BFD_RELOC_MICROMIPS_LO16
);
18417 fixp
->fx_file
= fragp
->fr_file
;
18418 fixp
->fx_line
= fragp
->fr_line
;
18420 buf
= write_compressed_insn (buf
, insn
, 4);
18422 /* jr/jrc/jalr/jalrs $at */
18423 insn
= al
? jalr
: jr
;
18424 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18426 buf
= write_compressed_insn (buf
, insn
, 2);
18429 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18433 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18436 const struct mips16_immed_operand
*op
;
18439 unsigned int user_length
, length
;
18440 unsigned long insn
;
18443 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18444 op
= mips16_immed_operands
;
18445 while (op
->type
!= type
)
18448 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18449 val
= resolve_symbol_value (fragp
->fr_symbol
);
18454 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18456 /* The rules for the base address of a PC relative reloc are
18457 complicated; see mips16_extended_frag. */
18458 if (type
== 'p' || type
== 'q')
18463 /* Ignore the low bit in the target, since it will be
18464 set for a text label. */
18465 if ((val
& 1) != 0)
18468 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18470 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18473 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18476 /* Make sure the section winds up with the alignment we have
18479 record_alignment (asec
, op
->shift
);
18483 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18484 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18485 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18486 _("extended instruction in delay slot"));
18488 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18490 insn
= read_compressed_insn (buf
, 2);
18492 insn
|= MIPS16_EXTEND
;
18494 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18496 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18501 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18502 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18504 length
= (ext
? 4 : 2);
18505 gas_assert (mips16_opcode_length (insn
) == length
);
18506 write_compressed_insn (buf
, insn
, length
);
18507 fragp
->fr_fix
+= length
;
18511 relax_substateT subtype
= fragp
->fr_subtype
;
18512 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18513 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18517 first
= RELAX_FIRST (subtype
);
18518 second
= RELAX_SECOND (subtype
);
18519 fixp
= (fixS
*) fragp
->fr_opcode
;
18521 /* If the delay slot chosen does not match the size of the instruction,
18522 then emit a warning. */
18523 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18524 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18529 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18530 | RELAX_DELAY_SLOT_SIZE_FIRST
18531 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18532 msg
= macro_warning (s
);
18534 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18538 /* Possibly emit a warning if we've chosen the longer option. */
18539 if (use_second
== second_longer
)
18545 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18546 msg
= macro_warning (s
);
18548 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18552 /* Go through all the fixups for the first sequence. Disable them
18553 (by marking them as done) if we're going to use the second
18554 sequence instead. */
18556 && fixp
->fx_frag
== fragp
18557 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18559 if (subtype
& RELAX_USE_SECOND
)
18561 fixp
= fixp
->fx_next
;
18564 /* Go through the fixups for the second sequence. Disable them if
18565 we're going to use the first sequence, otherwise adjust their
18566 addresses to account for the relaxation. */
18567 while (fixp
&& fixp
->fx_frag
== fragp
)
18569 if (subtype
& RELAX_USE_SECOND
)
18570 fixp
->fx_where
-= first
;
18573 fixp
= fixp
->fx_next
;
18576 /* Now modify the frag contents. */
18577 if (subtype
& RELAX_USE_SECOND
)
18581 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18582 memmove (start
, start
+ first
, second
);
18583 fragp
->fr_fix
-= first
;
18586 fragp
->fr_fix
-= second
;
18592 /* This function is called after the relocs have been generated.
18593 We've been storing mips16 text labels as odd. Here we convert them
18594 back to even for the convenience of the debugger. */
18597 mips_frob_file_after_relocs (void)
18600 unsigned int count
, i
;
18605 syms
= bfd_get_outsymbols (stdoutput
);
18606 count
= bfd_get_symcount (stdoutput
);
18607 for (i
= 0; i
< count
; i
++, syms
++)
18608 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18609 && ((*syms
)->value
& 1) != 0)
18611 (*syms
)->value
&= ~1;
18612 /* If the symbol has an odd size, it was probably computed
18613 incorrectly, so adjust that as well. */
18614 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18615 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18621 /* This function is called whenever a label is defined, including fake
18622 labels instantiated off the dot special symbol. It is used when
18623 handling branch delays; if a branch has a label, we assume we cannot
18624 move it. This also bumps the value of the symbol by 1 in compressed
18628 mips_record_label (symbolS
*sym
)
18630 segment_info_type
*si
= seg_info (now_seg
);
18631 struct insn_label_list
*l
;
18633 if (free_insn_labels
== NULL
)
18634 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18637 l
= free_insn_labels
;
18638 free_insn_labels
= l
->next
;
18642 l
->next
= si
->label_list
;
18643 si
->label_list
= l
;
18646 /* This function is called as tc_frob_label() whenever a label is defined
18647 and adds a DWARF-2 record we only want for true labels. */
18650 mips_define_label (symbolS
*sym
)
18652 mips_record_label (sym
);
18654 dwarf2_emit_label (sym
);
18658 /* This function is called by tc_new_dot_label whenever a new dot symbol
18662 mips_add_dot_label (symbolS
*sym
)
18664 mips_record_label (sym
);
18665 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18666 mips_compressed_mark_label (sym
);
18669 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18671 /* Some special processing for a MIPS ELF file. */
18674 mips_elf_final_processing (void)
18676 /* Write out the register information. */
18677 if (mips_abi
!= N64_ABI
)
18681 s
.ri_gprmask
= mips_gprmask
;
18682 s
.ri_cprmask
[0] = mips_cprmask
[0];
18683 s
.ri_cprmask
[1] = mips_cprmask
[1];
18684 s
.ri_cprmask
[2] = mips_cprmask
[2];
18685 s
.ri_cprmask
[3] = mips_cprmask
[3];
18686 /* The gp_value field is set by the MIPS ELF backend. */
18688 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18689 ((Elf32_External_RegInfo
*)
18690 mips_regmask_frag
));
18694 Elf64_Internal_RegInfo s
;
18696 s
.ri_gprmask
= mips_gprmask
;
18698 s
.ri_cprmask
[0] = mips_cprmask
[0];
18699 s
.ri_cprmask
[1] = mips_cprmask
[1];
18700 s
.ri_cprmask
[2] = mips_cprmask
[2];
18701 s
.ri_cprmask
[3] = mips_cprmask
[3];
18702 /* The gp_value field is set by the MIPS ELF backend. */
18704 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18705 ((Elf64_External_RegInfo
*)
18706 mips_regmask_frag
));
18709 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18710 sort of BFD interface for this. */
18711 if (mips_any_noreorder
)
18712 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18713 if (mips_pic
!= NO_PIC
)
18715 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18716 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18719 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18721 /* Set MIPS ELF flags for ASEs. */
18722 /* We may need to define a new flag for DSP ASE, and set this flag when
18723 file_ase_dsp is true. */
18724 /* Same for DSP R2. */
18725 /* We may need to define a new flag for MT ASE, and set this flag when
18726 file_ase_mt is true. */
18727 if (file_ase_mips16
)
18728 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18729 if (file_ase_micromips
)
18730 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18731 #if 0 /* XXX FIXME */
18732 if (file_ase_mips3d
)
18733 elf_elfheader (stdoutput
)->e_flags
|= ???;
18736 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18738 /* Set the MIPS ELF ABI flags. */
18739 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18740 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18741 else if (mips_abi
== O64_ABI
)
18742 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18743 else if (mips_abi
== EABI_ABI
)
18745 if (!file_mips_gp32
)
18746 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18748 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18750 else if (mips_abi
== N32_ABI
)
18751 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18753 /* Nothing to do for N64_ABI. */
18755 if (mips_32bitmode
)
18756 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18758 #if 0 /* XXX FIXME */
18759 /* 32 bit code with 64 bit FP registers. */
18760 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18761 elf_elfheader (stdoutput
)->e_flags
|= ???;
18765 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18767 typedef struct proc
{
18769 symbolS
*func_end_sym
;
18770 unsigned long reg_mask
;
18771 unsigned long reg_offset
;
18772 unsigned long fpreg_mask
;
18773 unsigned long fpreg_offset
;
18774 unsigned long frame_offset
;
18775 unsigned long frame_reg
;
18776 unsigned long pc_reg
;
18779 static procS cur_proc
;
18780 static procS
*cur_proc_ptr
;
18781 static int numprocs
;
18783 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18784 as "2", and a normal nop as "0". */
18786 #define NOP_OPCODE_MIPS 0
18787 #define NOP_OPCODE_MIPS16 1
18788 #define NOP_OPCODE_MICROMIPS 2
18791 mips_nop_opcode (void)
18793 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18794 return NOP_OPCODE_MICROMIPS
;
18795 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18796 return NOP_OPCODE_MIPS16
;
18798 return NOP_OPCODE_MIPS
;
18801 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18802 32-bit microMIPS NOPs here (if applicable). */
18805 mips_handle_align (fragS
*fragp
)
18809 int bytes
, size
, excess
;
18812 if (fragp
->fr_type
!= rs_align_code
)
18815 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18817 switch (nop_opcode
)
18819 case NOP_OPCODE_MICROMIPS
:
18820 opcode
= micromips_nop32_insn
.insn_opcode
;
18823 case NOP_OPCODE_MIPS16
:
18824 opcode
= mips16_nop_insn
.insn_opcode
;
18827 case NOP_OPCODE_MIPS
:
18829 opcode
= nop_insn
.insn_opcode
;
18834 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18835 excess
= bytes
% size
;
18837 /* Handle the leading part if we're not inserting a whole number of
18838 instructions, and make it the end of the fixed part of the frag.
18839 Try to fit in a short microMIPS NOP if applicable and possible,
18840 and use zeroes otherwise. */
18841 gas_assert (excess
< 4);
18842 fragp
->fr_fix
+= excess
;
18847 /* Fall through. */
18849 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
18851 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18855 /* Fall through. */
18858 /* Fall through. */
18863 md_number_to_chars (p
, opcode
, size
);
18864 fragp
->fr_var
= size
;
18868 md_obj_begin (void)
18875 /* Check for premature end, nesting errors, etc. */
18877 as_warn (_("missing .end at end of assembly"));
18886 if (*input_line_pointer
== '-')
18888 ++input_line_pointer
;
18891 if (!ISDIGIT (*input_line_pointer
))
18892 as_bad (_("expected simple number"));
18893 if (input_line_pointer
[0] == '0')
18895 if (input_line_pointer
[1] == 'x')
18897 input_line_pointer
+= 2;
18898 while (ISXDIGIT (*input_line_pointer
))
18901 val
|= hex_value (*input_line_pointer
++);
18903 return negative
? -val
: val
;
18907 ++input_line_pointer
;
18908 while (ISDIGIT (*input_line_pointer
))
18911 val
|= *input_line_pointer
++ - '0';
18913 return negative
? -val
: val
;
18916 if (!ISDIGIT (*input_line_pointer
))
18918 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18919 *input_line_pointer
, *input_line_pointer
);
18920 as_warn (_("invalid number"));
18923 while (ISDIGIT (*input_line_pointer
))
18926 val
+= *input_line_pointer
++ - '0';
18928 return negative
? -val
: val
;
18931 /* The .file directive; just like the usual .file directive, but there
18932 is an initial number which is the ECOFF file index. In the non-ECOFF
18933 case .file implies DWARF-2. */
18936 s_mips_file (int x ATTRIBUTE_UNUSED
)
18938 static int first_file_directive
= 0;
18940 if (ECOFF_DEBUGGING
)
18949 filename
= dwarf2_directive_file (0);
18951 /* Versions of GCC up to 3.1 start files with a ".file"
18952 directive even for stabs output. Make sure that this
18953 ".file" is handled. Note that you need a version of GCC
18954 after 3.1 in order to support DWARF-2 on MIPS. */
18955 if (filename
!= NULL
&& ! first_file_directive
)
18957 (void) new_logical_line (filename
, -1);
18958 s_app_file_string (filename
, 0);
18960 first_file_directive
= 1;
18964 /* The .loc directive, implying DWARF-2. */
18967 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18969 if (!ECOFF_DEBUGGING
)
18970 dwarf2_directive_loc (0);
18973 /* The .end directive. */
18976 s_mips_end (int x ATTRIBUTE_UNUSED
)
18980 /* Following functions need their own .frame and .cprestore directives. */
18981 mips_frame_reg_valid
= 0;
18982 mips_cprestore_valid
= 0;
18984 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18987 demand_empty_rest_of_line ();
18992 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18993 as_warn (_(".end not in text section"));
18997 as_warn (_(".end directive without a preceding .ent directive."));
18998 demand_empty_rest_of_line ();
19004 gas_assert (S_GET_NAME (p
));
19005 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19006 as_warn (_(".end symbol does not match .ent symbol."));
19008 if (debug_type
== DEBUG_STABS
)
19009 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19013 as_warn (_(".end directive missing or unknown symbol"));
19016 /* Create an expression to calculate the size of the function. */
19017 if (p
&& cur_proc_ptr
)
19019 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19020 expressionS
*exp
= xmalloc (sizeof (expressionS
));
19023 exp
->X_op
= O_subtract
;
19024 exp
->X_add_symbol
= symbol_temp_new_now ();
19025 exp
->X_op_symbol
= p
;
19026 exp
->X_add_number
= 0;
19028 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19031 /* Generate a .pdr section. */
19032 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
19034 segT saved_seg
= now_seg
;
19035 subsegT saved_subseg
= now_subseg
;
19039 #ifdef md_flush_pending_output
19040 md_flush_pending_output ();
19043 gas_assert (pdr_seg
);
19044 subseg_set (pdr_seg
, 0);
19046 /* Write the symbol. */
19047 exp
.X_op
= O_symbol
;
19048 exp
.X_add_symbol
= p
;
19049 exp
.X_add_number
= 0;
19050 emit_expr (&exp
, 4);
19052 fragp
= frag_more (7 * 4);
19054 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19055 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19056 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19057 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19058 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19059 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19060 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19062 subseg_set (saved_seg
, saved_subseg
);
19064 #endif /* OBJ_ELF */
19066 cur_proc_ptr
= NULL
;
19069 /* The .aent and .ent directives. */
19072 s_mips_ent (int aent
)
19076 symbolP
= get_symbol ();
19077 if (*input_line_pointer
== ',')
19078 ++input_line_pointer
;
19079 SKIP_WHITESPACE ();
19080 if (ISDIGIT (*input_line_pointer
)
19081 || *input_line_pointer
== '-')
19084 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19085 as_warn (_(".ent or .aent not in text section."));
19087 if (!aent
&& cur_proc_ptr
)
19088 as_warn (_("missing .end"));
19092 /* This function needs its own .frame and .cprestore directives. */
19093 mips_frame_reg_valid
= 0;
19094 mips_cprestore_valid
= 0;
19096 cur_proc_ptr
= &cur_proc
;
19097 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19099 cur_proc_ptr
->func_sym
= symbolP
;
19103 if (debug_type
== DEBUG_STABS
)
19104 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19105 S_GET_NAME (symbolP
));
19108 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19110 demand_empty_rest_of_line ();
19113 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19114 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19115 s_mips_frame is used so that we can set the PDR information correctly.
19116 We can't use the ecoff routines because they make reference to the ecoff
19117 symbol table (in the mdebug section). */
19120 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19123 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19127 if (cur_proc_ptr
== (procS
*) NULL
)
19129 as_warn (_(".frame outside of .ent"));
19130 demand_empty_rest_of_line ();
19134 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19136 SKIP_WHITESPACE ();
19137 if (*input_line_pointer
++ != ','
19138 || get_absolute_expression_and_terminator (&val
) != ',')
19140 as_warn (_("Bad .frame directive"));
19141 --input_line_pointer
;
19142 demand_empty_rest_of_line ();
19146 cur_proc_ptr
->frame_offset
= val
;
19147 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19149 demand_empty_rest_of_line ();
19152 #endif /* OBJ_ELF */
19156 /* The .fmask and .mask directives. If the mdebug section is present
19157 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19158 embedded targets, s_mips_mask is used so that we can set the PDR
19159 information correctly. We can't use the ecoff routines because they
19160 make reference to the ecoff symbol table (in the mdebug section). */
19163 s_mips_mask (int reg_type
)
19166 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19170 if (cur_proc_ptr
== (procS
*) NULL
)
19172 as_warn (_(".mask/.fmask outside of .ent"));
19173 demand_empty_rest_of_line ();
19177 if (get_absolute_expression_and_terminator (&mask
) != ',')
19179 as_warn (_("Bad .mask/.fmask directive"));
19180 --input_line_pointer
;
19181 demand_empty_rest_of_line ();
19185 off
= get_absolute_expression ();
19187 if (reg_type
== 'F')
19189 cur_proc_ptr
->fpreg_mask
= mask
;
19190 cur_proc_ptr
->fpreg_offset
= off
;
19194 cur_proc_ptr
->reg_mask
= mask
;
19195 cur_proc_ptr
->reg_offset
= off
;
19198 demand_empty_rest_of_line ();
19201 #endif /* OBJ_ELF */
19202 s_ignore (reg_type
);
19205 /* A table describing all the processors gas knows about. Names are
19206 matched in the order listed.
19208 To ease comparison, please keep this table in the same order as
19209 gcc's mips_cpu_info_table[]. */
19210 static const struct mips_cpu_info mips_cpu_info_table
[] =
19212 /* Entries for generic ISAs */
19213 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
19214 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
19215 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
19216 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
19217 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
19218 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
19219 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19220 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
19221 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
19224 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
19225 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
19226 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
19229 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
19232 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
19233 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
19234 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
19235 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
19236 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
19237 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
19238 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
19239 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
19240 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
19241 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
19242 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
19243 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
19244 { "r5900", 0, ISA_MIPS3
, CPU_R5900
},
19245 /* ST Microelectronics Loongson 2E and 2F cores */
19246 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19247 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19250 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
19251 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
19252 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
19253 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
19254 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
19255 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
19256 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
19257 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
19258 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
19259 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
19260 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
19261 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
19262 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
19263 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
19264 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
19267 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
19268 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
19269 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
19270 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19272 /* MIPS 32 Release 2 */
19273 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19274 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19275 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19276 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19277 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19278 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19279 { "m14k", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19280 { "m14kc", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19281 { "m14ke", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19282 ISA_MIPS32R2
, CPU_MIPS32R2
},
19283 { "m14kec", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19284 ISA_MIPS32R2
, CPU_MIPS32R2
},
19285 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19286 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19287 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19288 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19289 /* Deprecated forms of the above. */
19290 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19291 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19292 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19293 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19294 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19295 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19296 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19297 /* Deprecated forms of the above. */
19298 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19299 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19300 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19301 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19302 ISA_MIPS32R2
, CPU_MIPS32R2
},
19303 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19304 ISA_MIPS32R2
, CPU_MIPS32R2
},
19305 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19306 ISA_MIPS32R2
, CPU_MIPS32R2
},
19307 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19308 ISA_MIPS32R2
, CPU_MIPS32R2
},
19309 /* Deprecated forms of the above. */
19310 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19311 ISA_MIPS32R2
, CPU_MIPS32R2
},
19312 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19313 ISA_MIPS32R2
, CPU_MIPS32R2
},
19314 /* 34Kn is a 34kc without DSP. */
19315 { "34kn", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19316 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19317 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19318 ISA_MIPS32R2
, CPU_MIPS32R2
},
19319 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19320 ISA_MIPS32R2
, CPU_MIPS32R2
},
19321 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19322 ISA_MIPS32R2
, CPU_MIPS32R2
},
19323 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19324 ISA_MIPS32R2
, CPU_MIPS32R2
},
19325 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19326 ISA_MIPS32R2
, CPU_MIPS32R2
},
19327 /* Deprecated forms of the above. */
19328 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19329 ISA_MIPS32R2
, CPU_MIPS32R2
},
19330 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19331 ISA_MIPS32R2
, CPU_MIPS32R2
},
19332 /* 1004K cores are multiprocessor versions of the 34K. */
19333 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19334 ISA_MIPS32R2
, CPU_MIPS32R2
},
19335 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19336 ISA_MIPS32R2
, CPU_MIPS32R2
},
19337 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19338 ISA_MIPS32R2
, CPU_MIPS32R2
},
19339 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19340 ISA_MIPS32R2
, CPU_MIPS32R2
},
19343 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
19344 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
19345 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19346 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19348 /* Broadcom SB-1 CPU core */
19349 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19350 ISA_MIPS64
, CPU_SB1
},
19351 /* Broadcom SB-1A CPU core */
19352 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19353 ISA_MIPS64
, CPU_SB1
},
19355 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19357 /* MIPS 64 Release 2 */
19359 /* Cavium Networks Octeon CPU core */
19360 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
19361 { "octeon+", 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19362 { "octeon2", 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19365 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
19368 XLP is mostly like XLR, with the prominent exception that it is
19369 MIPS64R2 rather than MIPS64. */
19370 { "xlp", 0, ISA_MIPS64R2
, CPU_XLR
},
19377 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19378 with a final "000" replaced by "k". Ignore case.
19380 Note: this function is shared between GCC and GAS. */
19383 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19385 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19386 given
++, canonical
++;
19388 return ((*given
== 0 && *canonical
== 0)
19389 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19393 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19394 CPU name. We've traditionally allowed a lot of variation here.
19396 Note: this function is shared between GCC and GAS. */
19399 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19401 /* First see if the name matches exactly, or with a final "000"
19402 turned into "k". */
19403 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19406 /* If not, try comparing based on numerical designation alone.
19407 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19408 if (TOLOWER (*given
) == 'r')
19410 if (!ISDIGIT (*given
))
19413 /* Skip over some well-known prefixes in the canonical name,
19414 hoping to find a number there too. */
19415 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19417 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19419 else if (TOLOWER (canonical
[0]) == 'r')
19422 return mips_strict_matching_cpu_name_p (canonical
, given
);
19426 /* Parse an option that takes the name of a processor as its argument.
19427 OPTION is the name of the option and CPU_STRING is the argument.
19428 Return the corresponding processor enumeration if the CPU_STRING is
19429 recognized, otherwise report an error and return null.
19431 A similar function exists in GCC. */
19433 static const struct mips_cpu_info
*
19434 mips_parse_cpu (const char *option
, const char *cpu_string
)
19436 const struct mips_cpu_info
*p
;
19438 /* 'from-abi' selects the most compatible architecture for the given
19439 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19440 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19441 version. Look first at the -mgp options, if given, otherwise base
19442 the choice on MIPS_DEFAULT_64BIT.
19444 Treat NO_ABI like the EABIs. One reason to do this is that the
19445 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19446 architecture. This code picks MIPS I for 'mips' and MIPS III for
19447 'mips64', just as we did in the days before 'from-abi'. */
19448 if (strcasecmp (cpu_string
, "from-abi") == 0)
19450 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19451 return mips_cpu_info_from_isa (ISA_MIPS1
);
19453 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19454 return mips_cpu_info_from_isa (ISA_MIPS3
);
19456 if (file_mips_gp32
>= 0)
19457 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19459 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19464 /* 'default' has traditionally been a no-op. Probably not very useful. */
19465 if (strcasecmp (cpu_string
, "default") == 0)
19468 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19469 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19472 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19476 /* Return the canonical processor information for ISA (a member of the
19477 ISA_MIPS* enumeration). */
19479 static const struct mips_cpu_info
*
19480 mips_cpu_info_from_isa (int isa
)
19484 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19485 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19486 && isa
== mips_cpu_info_table
[i
].isa
)
19487 return (&mips_cpu_info_table
[i
]);
19492 static const struct mips_cpu_info
*
19493 mips_cpu_info_from_arch (int arch
)
19497 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19498 if (arch
== mips_cpu_info_table
[i
].cpu
)
19499 return (&mips_cpu_info_table
[i
]);
19505 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19509 fprintf (stream
, "%24s", "");
19514 fprintf (stream
, ", ");
19518 if (*col_p
+ strlen (string
) > 72)
19520 fprintf (stream
, "\n%24s", "");
19524 fprintf (stream
, "%s", string
);
19525 *col_p
+= strlen (string
);
19531 md_show_usage (FILE *stream
)
19536 fprintf (stream
, _("\
19538 -EB generate big endian output\n\
19539 -EL generate little endian output\n\
19540 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19541 -G NUM allow referencing objects up to NUM bytes\n\
19542 implicitly with the gp register [default 8]\n"));
19543 fprintf (stream
, _("\
19544 -mips1 generate MIPS ISA I instructions\n\
19545 -mips2 generate MIPS ISA II instructions\n\
19546 -mips3 generate MIPS ISA III instructions\n\
19547 -mips4 generate MIPS ISA IV instructions\n\
19548 -mips5 generate MIPS ISA V instructions\n\
19549 -mips32 generate MIPS32 ISA instructions\n\
19550 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19551 -mips64 generate MIPS64 ISA instructions\n\
19552 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19553 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19557 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19558 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19559 show (stream
, "from-abi", &column
, &first
);
19560 fputc ('\n', stream
);
19562 fprintf (stream
, _("\
19563 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19564 -no-mCPU don't generate code specific to CPU.\n\
19565 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19569 show (stream
, "3900", &column
, &first
);
19570 show (stream
, "4010", &column
, &first
);
19571 show (stream
, "4100", &column
, &first
);
19572 show (stream
, "4650", &column
, &first
);
19573 fputc ('\n', stream
);
19575 fprintf (stream
, _("\
19576 -mips16 generate mips16 instructions\n\
19577 -no-mips16 do not generate mips16 instructions\n"));
19578 fprintf (stream
, _("\
19579 -mmicromips generate microMIPS instructions\n\
19580 -mno-micromips do not generate microMIPS instructions\n"));
19581 fprintf (stream
, _("\
19582 -msmartmips generate smartmips instructions\n\
19583 -mno-smartmips do not generate smartmips instructions\n"));
19584 fprintf (stream
, _("\
19585 -mdsp generate DSP instructions\n\
19586 -mno-dsp do not generate DSP instructions\n"));
19587 fprintf (stream
, _("\
19588 -mdspr2 generate DSP R2 instructions\n\
19589 -mno-dspr2 do not generate DSP R2 instructions\n"));
19590 fprintf (stream
, _("\
19591 -mmt generate MT instructions\n\
19592 -mno-mt do not generate MT instructions\n"));
19593 fprintf (stream
, _("\
19594 -mmcu generate MCU instructions\n\
19595 -mno-mcu do not generate MCU instructions\n"));
19596 fprintf (stream
, _("\
19597 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19598 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19599 -mfix-vr4120 work around certain VR4120 errata\n\
19600 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19601 -mfix-24k insert a nop after ERET and DERET instructions\n\
19602 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19603 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19604 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19605 -msym32 assume all symbols have 32-bit values\n\
19606 -O0 remove unneeded NOPs, do not swap branches\n\
19607 -O remove unneeded NOPs and swap branches\n\
19608 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19609 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19610 fprintf (stream
, _("\
19611 -mhard-float allow floating-point instructions\n\
19612 -msoft-float do not allow floating-point instructions\n\
19613 -msingle-float only allow 32-bit floating-point operations\n\
19614 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19615 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19618 fprintf (stream
, _("\
19619 -KPIC, -call_shared generate SVR4 position independent code\n\
19620 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19621 -mvxworks-pic generate VxWorks position independent code\n\
19622 -non_shared do not generate code that can operate with DSOs\n\
19623 -xgot assume a 32 bit GOT\n\
19624 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19625 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19626 position dependent (non shared) code\n\
19627 -mabi=ABI create ABI conformant object file for:\n"));
19631 show (stream
, "32", &column
, &first
);
19632 show (stream
, "o64", &column
, &first
);
19633 show (stream
, "n32", &column
, &first
);
19634 show (stream
, "64", &column
, &first
);
19635 show (stream
, "eabi", &column
, &first
);
19637 fputc ('\n', stream
);
19639 fprintf (stream
, _("\
19640 -32 create o32 ABI object file (default)\n\
19641 -n32 create n32 ABI object file\n\
19642 -64 create 64 ABI object file\n"));
19648 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19650 if (HAVE_64BIT_SYMBOLS
)
19651 return dwarf2_format_64bit_irix
;
19653 return dwarf2_format_32bit
;
19658 mips_dwarf2_addr_size (void)
19660 if (HAVE_64BIT_OBJECTS
)
19666 /* Standard calling conventions leave the CFA at SP on entry. */
19668 mips_cfi_frame_initial_instructions (void)
19670 cfi_add_CFA_def_cfa_register (SP
);
19674 tc_mips_regname_to_dw2regnum (char *regname
)
19676 unsigned int regnum
= -1;
19679 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))