1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32
= -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32
= -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float
= 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float
= 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008
= FALSE
;
281 static struct mips_set_options mips_opts
=
283 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
287 /* soft_float */ FALSE
, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase
;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit
;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch
= CPU_UNKNOWN
;
331 static const char *mips_arch_string
;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune
= CPU_UNKNOWN
;
336 static const char *mips_tune_string
;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode
= 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic
;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got
= 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap
= 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction
;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder
;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix
;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value
= 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen
= 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS
*, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control
*op_hash
= NULL
;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control
*mips16_op_hash
= NULL
;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control
*micromips_op_hash
= NULL
;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars
[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars
[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars
[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS
[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 static char *insn_error
;
635 static int auto_align
= 1;
637 /* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
641 static offsetT mips_cprestore_offset
= -1;
643 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
644 more optimizations, it can use a register value instead of a memory-saved
645 offset and even an other register than $gp as global pointer. */
646 static offsetT mips_cpreturn_offset
= -1;
647 static int mips_cpreturn_register
= -1;
648 static int mips_gp_register
= GP
;
649 static int mips_gprel_offset
= 0;
651 /* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_cprestore_valid
= 0;
655 /* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657 static int mips_frame_reg
= SP
;
659 /* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661 static int mips_frame_reg_valid
= 0;
663 /* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
666 /* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
670 static int mips_optimize
= 2;
672 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674 static int mips_debug
= 0;
676 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677 #define MAX_VR4130_NOPS 4
679 /* The maximum number of NOPs needed to fill delay slots. */
680 #define MAX_DELAY_NOPS 2
682 /* The maximum number of NOPs needed for any purpose. */
685 /* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690 static struct mips_cl_insn history
[1 + MAX_NOPS
];
692 /* Arrays of operands for each instruction. */
693 #define MAX_OPERANDS 6
694 struct mips_operand_array
{
695 const struct mips_operand
*operand
[MAX_OPERANDS
];
697 static struct mips_operand_array
*mips_operands
;
698 static struct mips_operand_array
*mips16_operands
;
699 static struct mips_operand_array
*micromips_operands
;
701 /* Nop instructions used by emit_nop. */
702 static struct mips_cl_insn nop_insn
;
703 static struct mips_cl_insn mips16_nop_insn
;
704 static struct mips_cl_insn micromips_nop16_insn
;
705 static struct mips_cl_insn micromips_nop32_insn
;
707 /* The appropriate nop for the current mode. */
708 #define NOP_INSN (mips_opts.mips16 \
710 : (mips_opts.micromips \
711 ? (mips_opts.insn32 \
712 ? µmips_nop32_insn \
713 : µmips_nop16_insn) \
716 /* The size of NOP_INSN in bytes. */
717 #define NOP_INSN_SIZE ((mips_opts.mips16 \
718 || (mips_opts.micromips && !mips_opts.insn32)) \
721 /* If this is set, it points to a frag holding nop instructions which
722 were inserted before the start of a noreorder section. If those
723 nops turn out to be unnecessary, the size of the frag can be
725 static fragS
*prev_nop_frag
;
727 /* The number of nop instructions we created in prev_nop_frag. */
728 static int prev_nop_frag_holds
;
730 /* The number of nop instructions that we know we need in
732 static int prev_nop_frag_required
;
734 /* The number of instructions we've seen since prev_nop_frag. */
735 static int prev_nop_frag_since
;
737 /* Relocations against symbols are sometimes done in two parts, with a HI
738 relocation and a LO relocation. Each relocation has only 16 bits of
739 space to store an addend. This means that in order for the linker to
740 handle carries correctly, it must be able to locate both the HI and
741 the LO relocation. This means that the relocations must appear in
742 order in the relocation table.
744 In order to implement this, we keep track of each unmatched HI
745 relocation. We then sort them so that they immediately precede the
746 corresponding LO relocation. */
751 struct mips_hi_fixup
*next
;
754 /* The section this fixup is in. */
758 /* The list of unmatched HI relocs. */
760 static struct mips_hi_fixup
*mips_hi_fixup_list
;
762 /* The frag containing the last explicit relocation operator.
763 Null if explicit relocations have not been used. */
765 static fragS
*prev_reloc_op_frag
;
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map
[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map microMIPS register numbers to normal MIPS register numbers. */
776 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
778 /* The microMIPS registers with type h. */
779 static const unsigned int micromips_to_32_reg_h_map1
[] =
781 5, 5, 6, 4, 4, 4, 4, 4
783 static const unsigned int micromips_to_32_reg_h_map2
[] =
785 6, 7, 7, 21, 22, 5, 6, 7
788 /* The microMIPS registers with type m. */
789 static const unsigned int micromips_to_32_reg_m_map
[] =
791 0, 17, 2, 3, 16, 18, 19, 20
794 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
796 /* Classifies the kind of instructions we're interested in when
797 implementing -mfix-vr4120. */
798 enum fix_vr4120_class
806 NUM_FIX_VR4120_CLASSES
809 /* ...likewise -mfix-loongson2f-jump. */
810 static bfd_boolean mips_fix_loongson2f_jump
;
812 /* ...likewise -mfix-loongson2f-nop. */
813 static bfd_boolean mips_fix_loongson2f_nop
;
815 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
816 static bfd_boolean mips_fix_loongson2f
;
818 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
819 there must be at least one other instruction between an instruction
820 of type X and an instruction of type Y. */
821 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
823 /* True if -mfix-vr4120 is in force. */
824 static int mips_fix_vr4120
;
826 /* ...likewise -mfix-vr4130. */
827 static int mips_fix_vr4130
;
829 /* ...likewise -mfix-24k. */
830 static int mips_fix_24k
;
832 /* ...likewise -mfix-cn63xxp1 */
833 static bfd_boolean mips_fix_cn63xxp1
;
835 /* We don't relax branches by default, since this causes us to expand
836 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
837 fail to compute the offset before expanding the macro to the most
838 efficient expansion. */
840 static int mips_relax_branch
;
842 /* The expansion of many macros depends on the type of symbol that
843 they refer to. For example, when generating position-dependent code,
844 a macro that refers to a symbol may have two different expansions,
845 one which uses GP-relative addresses and one which uses absolute
846 addresses. When generating SVR4-style PIC, a macro may have
847 different expansions for local and global symbols.
849 We handle these situations by generating both sequences and putting
850 them in variant frags. In position-dependent code, the first sequence
851 will be the GP-relative one and the second sequence will be the
852 absolute one. In SVR4 PIC, the first sequence will be for global
853 symbols and the second will be for local symbols.
855 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
856 SECOND are the lengths of the two sequences in bytes. These fields
857 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
858 the subtype has the following flags:
861 Set if it has been decided that we should use the second
862 sequence instead of the first.
865 Set in the first variant frag if the macro's second implementation
866 is longer than its first. This refers to the macro as a whole,
867 not an individual relaxation.
870 Set in the first variant frag if the macro appeared in a .set nomacro
871 block and if one alternative requires a warning but the other does not.
874 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
877 RELAX_DELAY_SLOT_16BIT
878 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
881 RELAX_DELAY_SLOT_SIZE_FIRST
882 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
883 the macro is of the wrong size for the branch delay slot.
885 RELAX_DELAY_SLOT_SIZE_SECOND
886 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
887 the macro is of the wrong size for the branch delay slot.
889 The frag's "opcode" points to the first fixup for relaxable code.
891 Relaxable macros are generated using a sequence such as:
893 relax_start (SYMBOL);
894 ... generate first expansion ...
896 ... generate second expansion ...
899 The code and fixups for the unwanted alternative are discarded
900 by md_convert_frag. */
901 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
903 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
904 #define RELAX_SECOND(X) ((X) & 0xff)
905 #define RELAX_USE_SECOND 0x10000
906 #define RELAX_SECOND_LONGER 0x20000
907 #define RELAX_NOMACRO 0x40000
908 #define RELAX_DELAY_SLOT 0x80000
909 #define RELAX_DELAY_SLOT_16BIT 0x100000
910 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
911 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
913 /* Branch without likely bit. If label is out of range, we turn:
915 beq reg1, reg2, label
925 with the following opcode replacements:
932 bltzal <-> bgezal (with jal label instead of j label)
934 Even though keeping the delay slot instruction in the delay slot of
935 the branch would be more efficient, it would be very tricky to do
936 correctly, because we'd have to introduce a variable frag *after*
937 the delay slot instruction, and expand that instead. Let's do it
938 the easy way for now, even if the branch-not-taken case now costs
939 one additional instruction. Out-of-range branches are not supposed
940 to be common, anyway.
942 Branch likely. If label is out of range, we turn:
944 beql reg1, reg2, label
945 delay slot (annulled if branch not taken)
954 delay slot (executed only if branch taken)
957 It would be possible to generate a shorter sequence by losing the
958 likely bit, generating something like:
963 delay slot (executed only if branch taken)
975 bltzall -> bgezal (with jal label instead of j label)
976 bgezall -> bltzal (ditto)
979 but it's not clear that it would actually improve performance. */
980 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
984 | ((toofar) ? 0x20 : 0) \
985 | ((link) ? 0x40 : 0) \
986 | ((likely) ? 0x80 : 0) \
987 | ((uncond) ? 0x100 : 0)))
988 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
989 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
990 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
991 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
992 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
993 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
995 /* For mips16 code, we use an entirely different form of relaxation.
996 mips16 supports two versions of most instructions which take
997 immediate values: a small one which takes some small value, and a
998 larger one which takes a 16 bit value. Since branches also follow
999 this pattern, relaxing these values is required.
1001 We can assemble both mips16 and normal MIPS code in a single
1002 object. Therefore, we need to support this type of relaxation at
1003 the same time that we support the relaxation described above. We
1004 use the high bit of the subtype field to distinguish these cases.
1006 The information we store for this type of relaxation is the
1007 argument code found in the opcode file for this relocation, whether
1008 the user explicitly requested a small or extended form, and whether
1009 the relocation is in a jump or jal delay slot. That tells us the
1010 size of the value, and how it should be stored. We also store
1011 whether the fragment is considered to be extended or not. We also
1012 store whether this is known to be a branch to a different section,
1013 whether we have tried to relax this frag yet, and whether we have
1014 ever extended a PC relative fragment because of a shift count. */
1015 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1018 | ((small) ? 0x100 : 0) \
1019 | ((ext) ? 0x200 : 0) \
1020 | ((dslot) ? 0x400 : 0) \
1021 | ((jal_dslot) ? 0x800 : 0))
1022 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1023 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1024 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1025 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1026 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1027 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1028 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1029 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1030 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1031 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1032 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1033 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1035 /* For microMIPS code, we use relaxation similar to one we use for
1036 MIPS16 code. Some instructions that take immediate values support
1037 two encodings: a small one which takes some small value, and a
1038 larger one which takes a 16 bit value. As some branches also follow
1039 this pattern, relaxing these values is required.
1041 We can assemble both microMIPS and normal MIPS code in a single
1042 object. Therefore, we need to support this type of relaxation at
1043 the same time that we support the relaxation described above. We
1044 use one of the high bits of the subtype field to distinguish these
1047 The information we store for this type of relaxation is the argument
1048 code found in the opcode file for this relocation, the register
1049 selected as the assembler temporary, whether the branch is
1050 unconditional, whether it is compact, whether it stores the link
1051 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1052 branches to a sequence of instructions is enabled, and whether the
1053 displacement of a branch is too large to fit as an immediate argument
1054 of a 16-bit and a 32-bit branch, respectively. */
1055 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1056 relax32, toofar16, toofar32) \
1059 | (((at) & 0x1f) << 8) \
1060 | ((uncond) ? 0x2000 : 0) \
1061 | ((compact) ? 0x4000 : 0) \
1062 | ((link) ? 0x8000 : 0) \
1063 | ((relax32) ? 0x10000 : 0) \
1064 | ((toofar16) ? 0x20000 : 0) \
1065 | ((toofar32) ? 0x40000 : 0))
1066 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1067 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1068 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1069 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1070 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1071 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1072 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1074 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1075 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1076 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1077 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1078 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1079 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1081 /* Sign-extend 16-bit value X. */
1082 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1084 /* Is the given value a sign-extended 32-bit value? */
1085 #define IS_SEXT_32BIT_NUM(x) \
1086 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1087 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1089 /* Is the given value a sign-extended 16-bit value? */
1090 #define IS_SEXT_16BIT_NUM(x) \
1091 (((x) &~ (offsetT) 0x7fff) == 0 \
1092 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1094 /* Is the given value a sign-extended 12-bit value? */
1095 #define IS_SEXT_12BIT_NUM(x) \
1096 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1098 /* Is the given value a sign-extended 9-bit value? */
1099 #define IS_SEXT_9BIT_NUM(x) \
1100 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1102 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1103 #define IS_ZEXT_32BIT_NUM(x) \
1104 (((x) &~ (offsetT) 0xffffffff) == 0 \
1105 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1107 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1109 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1110 (((STRUCT) >> (SHIFT)) & (MASK))
1112 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1113 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1115 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1116 : EXTRACT_BITS ((INSN).insn_opcode, \
1117 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1118 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1119 EXTRACT_BITS ((INSN).insn_opcode, \
1120 MIPS16OP_MASK_##FIELD, \
1121 MIPS16OP_SH_##FIELD)
1123 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1124 #define MIPS16_EXTEND (0xf000U << 16)
1126 /* Whether or not we are emitting a branch-likely macro. */
1127 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1129 /* Global variables used when generating relaxable macros. See the
1130 comment above RELAX_ENCODE for more details about how relaxation
1133 /* 0 if we're not emitting a relaxable macro.
1134 1 if we're emitting the first of the two relaxation alternatives.
1135 2 if we're emitting the second alternative. */
1138 /* The first relaxable fixup in the current frag. (In other words,
1139 the first fixup that refers to relaxable code.) */
1142 /* sizes[0] says how many bytes of the first alternative are stored in
1143 the current frag. Likewise sizes[1] for the second alternative. */
1144 unsigned int sizes
[2];
1146 /* The symbol on which the choice of sequence depends. */
1150 /* Global variables used to decide whether a macro needs a warning. */
1152 /* True if the macro is in a branch delay slot. */
1153 bfd_boolean delay_slot_p
;
1155 /* Set to the length in bytes required if the macro is in a delay slot
1156 that requires a specific length of instruction, otherwise zero. */
1157 unsigned int delay_slot_length
;
1159 /* For relaxable macros, sizes[0] is the length of the first alternative
1160 in bytes and sizes[1] is the length of the second alternative.
1161 For non-relaxable macros, both elements give the length of the
1163 unsigned int sizes
[2];
1165 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1166 instruction of the first alternative in bytes and first_insn_sizes[1]
1167 is the length of the first instruction of the second alternative.
1168 For non-relaxable macros, both elements give the length of the first
1169 instruction in bytes.
1171 Set to zero if we haven't yet seen the first instruction. */
1172 unsigned int first_insn_sizes
[2];
1174 /* For relaxable macros, insns[0] is the number of instructions for the
1175 first alternative and insns[1] is the number of instructions for the
1178 For non-relaxable macros, both elements give the number of
1179 instructions for the macro. */
1180 unsigned int insns
[2];
1182 /* The first variant frag for this macro. */
1184 } mips_macro_warning
;
1186 /* Prototypes for static functions. */
1188 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1190 static void append_insn
1191 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1192 bfd_boolean expansionp
);
1193 static void mips_no_prev_insn (void);
1194 static void macro_build (expressionS
*, const char *, const char *, ...);
1195 static void mips16_macro_build
1196 (expressionS
*, const char *, const char *, va_list *);
1197 static void load_register (int, expressionS
*, int);
1198 static void macro_start (void);
1199 static void macro_end (void);
1200 static void macro (struct mips_cl_insn
*ip
, char *str
);
1201 static void mips16_macro (struct mips_cl_insn
* ip
);
1202 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1203 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1204 static void mips16_immed
1205 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1206 unsigned int, unsigned long *);
1207 static size_t my_getSmallExpression
1208 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1209 static void my_getExpression (expressionS
*, char *);
1210 static void s_align (int);
1211 static void s_change_sec (int);
1212 static void s_change_section (int);
1213 static void s_cons (int);
1214 static void s_float_cons (int);
1215 static void s_mips_globl (int);
1216 static void s_option (int);
1217 static void s_mipsset (int);
1218 static void s_abicalls (int);
1219 static void s_cpload (int);
1220 static void s_cpsetup (int);
1221 static void s_cplocal (int);
1222 static void s_cprestore (int);
1223 static void s_cpreturn (int);
1224 static void s_dtprelword (int);
1225 static void s_dtpreldword (int);
1226 static void s_tprelword (int);
1227 static void s_tpreldword (int);
1228 static void s_gpvalue (int);
1229 static void s_gpword (int);
1230 static void s_gpdword (int);
1231 static void s_ehword (int);
1232 static void s_cpadd (int);
1233 static void s_insn (int);
1234 static void s_nan (int);
1235 static void md_obj_begin (void);
1236 static void md_obj_end (void);
1237 static void s_mips_ent (int);
1238 static void s_mips_end (int);
1239 static void s_mips_frame (int);
1240 static void s_mips_mask (int reg_type
);
1241 static void s_mips_stab (int);
1242 static void s_mips_weakext (int);
1243 static void s_mips_file (int);
1244 static void s_mips_loc (int);
1245 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1246 static int relaxed_branch_length (fragS
*, asection
*, int);
1247 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1248 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1250 /* Table and functions used to map between CPU/ISA names, and
1251 ISA levels, and CPU numbers. */
1253 struct mips_cpu_info
1255 const char *name
; /* CPU or ISA name. */
1256 int flags
; /* MIPS_CPU_* flags. */
1257 int ase
; /* Set of ASEs implemented by the CPU. */
1258 int isa
; /* ISA level. */
1259 int cpu
; /* CPU number (default CPU if ISA). */
1262 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1264 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1265 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1266 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1268 /* Command-line options. */
1269 const char *md_shortopts
= "O::g::G:";
1273 OPTION_MARCH
= OPTION_MD_BASE
,
1297 OPTION_NO_SMARTMIPS
,
1303 OPTION_NO_MICROMIPS
,
1306 OPTION_COMPAT_ARCH_BASE
,
1315 OPTION_M7000_HILO_FIX
,
1316 OPTION_MNO_7000_HILO_FIX
,
1319 OPTION_FIX_LOONGSON2F_JUMP
,
1320 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1321 OPTION_FIX_LOONGSON2F_NOP
,
1322 OPTION_NO_FIX_LOONGSON2F_NOP
,
1324 OPTION_NO_FIX_VR4120
,
1326 OPTION_NO_FIX_VR4130
,
1327 OPTION_FIX_CN63XXP1
,
1328 OPTION_NO_FIX_CN63XXP1
,
1335 OPTION_CONSTRUCT_FLOATS
,
1336 OPTION_NO_CONSTRUCT_FLOATS
,
1339 OPTION_RELAX_BRANCH
,
1340 OPTION_NO_RELAX_BRANCH
,
1349 OPTION_SINGLE_FLOAT
,
1350 OPTION_DOUBLE_FLOAT
,
1363 OPTION_MVXWORKS_PIC
,
1368 struct option md_longopts
[] =
1370 /* Options which specify architecture. */
1371 {"march", required_argument
, NULL
, OPTION_MARCH
},
1372 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1373 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1374 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1375 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1376 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1377 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1378 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1379 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1380 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1381 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1382 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1384 /* Options which specify Application Specific Extensions (ASEs). */
1385 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1386 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1387 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1388 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1389 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1390 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1391 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1392 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1393 {"mmt", no_argument
, NULL
, OPTION_MT
},
1394 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1395 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1396 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1397 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1398 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1399 {"meva", no_argument
, NULL
, OPTION_EVA
},
1400 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1401 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1402 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1403 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1404 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1405 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1406 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1408 /* Old-style architecture options. Don't add more of these. */
1409 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1410 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1411 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1412 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1413 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1414 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1415 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1416 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1418 /* Options which enable bug fixes. */
1419 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1420 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1421 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1422 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1423 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1424 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1425 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1426 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1427 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1428 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1429 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1430 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1431 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1432 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1433 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1435 /* Miscellaneous options. */
1436 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1437 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1438 {"break", no_argument
, NULL
, OPTION_BREAK
},
1439 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1440 {"EB", no_argument
, NULL
, OPTION_EB
},
1441 {"EL", no_argument
, NULL
, OPTION_EL
},
1442 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1443 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1444 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1445 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1446 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1447 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1448 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1449 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1450 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1451 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1452 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1453 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1454 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1455 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1456 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1457 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1458 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1459 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1461 /* Strictly speaking this next option is ELF specific,
1462 but we allow it for other ports as well in order to
1463 make testing easier. */
1464 {"32", no_argument
, NULL
, OPTION_32
},
1466 /* ELF-specific options. */
1467 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1468 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1469 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1470 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1471 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1472 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1473 {"n32", no_argument
, NULL
, OPTION_N32
},
1474 {"64", no_argument
, NULL
, OPTION_64
},
1475 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1476 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1477 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1478 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1479 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1480 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1482 {NULL
, no_argument
, NULL
, 0}
1484 size_t md_longopts_size
= sizeof (md_longopts
);
1486 /* Information about either an Application Specific Extension or an
1487 optional architecture feature that, for simplicity, we treat in the
1488 same way as an ASE. */
1491 /* The name of the ASE, used in both the command-line and .set options. */
1494 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1495 and 64-bit architectures, the flags here refer to the subset that
1496 is available on both. */
1499 /* The ASE_* flag used for instructions that are available on 64-bit
1500 architectures but that are not included in FLAGS. */
1501 unsigned int flags64
;
1503 /* The command-line options that turn the ASE on and off. */
1507 /* The minimum required architecture revisions for MIPS32, MIPS64,
1508 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1511 int micromips32_rev
;
1512 int micromips64_rev
;
1515 /* A table of all supported ASEs. */
1516 static const struct mips_ase mips_ases
[] = {
1517 { "dsp", ASE_DSP
, ASE_DSP64
,
1518 OPTION_DSP
, OPTION_NO_DSP
,
1521 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1522 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1525 { "eva", ASE_EVA
, 0,
1526 OPTION_EVA
, OPTION_NO_EVA
,
1529 { "mcu", ASE_MCU
, 0,
1530 OPTION_MCU
, OPTION_NO_MCU
,
1533 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1534 { "mdmx", ASE_MDMX
, 0,
1535 OPTION_MDMX
, OPTION_NO_MDMX
,
1538 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1539 { "mips3d", ASE_MIPS3D
, 0,
1540 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1544 OPTION_MT
, OPTION_NO_MT
,
1547 { "smartmips", ASE_SMARTMIPS
, 0,
1548 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1551 { "virt", ASE_VIRT
, ASE_VIRT64
,
1552 OPTION_VIRT
, OPTION_NO_VIRT
,
1556 /* The set of ASEs that require -mfp64. */
1557 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1559 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1560 static const unsigned int mips_ase_groups
[] = {
1566 The following pseudo-ops from the Kane and Heinrich MIPS book
1567 should be defined here, but are currently unsupported: .alias,
1568 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1570 The following pseudo-ops from the Kane and Heinrich MIPS book are
1571 specific to the type of debugging information being generated, and
1572 should be defined by the object format: .aent, .begin, .bend,
1573 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1576 The following pseudo-ops from the Kane and Heinrich MIPS book are
1577 not MIPS CPU specific, but are also not specific to the object file
1578 format. This file is probably the best place to define them, but
1579 they are not currently supported: .asm0, .endr, .lab, .struct. */
1581 static const pseudo_typeS mips_pseudo_table
[] =
1583 /* MIPS specific pseudo-ops. */
1584 {"option", s_option
, 0},
1585 {"set", s_mipsset
, 0},
1586 {"rdata", s_change_sec
, 'r'},
1587 {"sdata", s_change_sec
, 's'},
1588 {"livereg", s_ignore
, 0},
1589 {"abicalls", s_abicalls
, 0},
1590 {"cpload", s_cpload
, 0},
1591 {"cpsetup", s_cpsetup
, 0},
1592 {"cplocal", s_cplocal
, 0},
1593 {"cprestore", s_cprestore
, 0},
1594 {"cpreturn", s_cpreturn
, 0},
1595 {"dtprelword", s_dtprelword
, 0},
1596 {"dtpreldword", s_dtpreldword
, 0},
1597 {"tprelword", s_tprelword
, 0},
1598 {"tpreldword", s_tpreldword
, 0},
1599 {"gpvalue", s_gpvalue
, 0},
1600 {"gpword", s_gpword
, 0},
1601 {"gpdword", s_gpdword
, 0},
1602 {"ehword", s_ehword
, 0},
1603 {"cpadd", s_cpadd
, 0},
1604 {"insn", s_insn
, 0},
1607 /* Relatively generic pseudo-ops that happen to be used on MIPS
1609 {"asciiz", stringer
, 8 + 1},
1610 {"bss", s_change_sec
, 'b'},
1612 {"half", s_cons
, 1},
1613 {"dword", s_cons
, 3},
1614 {"weakext", s_mips_weakext
, 0},
1615 {"origin", s_org
, 0},
1616 {"repeat", s_rept
, 0},
1618 /* For MIPS this is non-standard, but we define it for consistency. */
1619 {"sbss", s_change_sec
, 'B'},
1621 /* These pseudo-ops are defined in read.c, but must be overridden
1622 here for one reason or another. */
1623 {"align", s_align
, 0},
1624 {"byte", s_cons
, 0},
1625 {"data", s_change_sec
, 'd'},
1626 {"double", s_float_cons
, 'd'},
1627 {"float", s_float_cons
, 'f'},
1628 {"globl", s_mips_globl
, 0},
1629 {"global", s_mips_globl
, 0},
1630 {"hword", s_cons
, 1},
1632 {"long", s_cons
, 2},
1633 {"octa", s_cons
, 4},
1634 {"quad", s_cons
, 3},
1635 {"section", s_change_section
, 0},
1636 {"short", s_cons
, 1},
1637 {"single", s_float_cons
, 'f'},
1638 {"stabd", s_mips_stab
, 'd'},
1639 {"stabn", s_mips_stab
, 'n'},
1640 {"stabs", s_mips_stab
, 's'},
1641 {"text", s_change_sec
, 't'},
1642 {"word", s_cons
, 2},
1644 { "extern", ecoff_directive_extern
, 0},
1649 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1651 /* These pseudo-ops should be defined by the object file format.
1652 However, a.out doesn't support them, so we have versions here. */
1653 {"aent", s_mips_ent
, 1},
1654 {"bgnb", s_ignore
, 0},
1655 {"end", s_mips_end
, 0},
1656 {"endb", s_ignore
, 0},
1657 {"ent", s_mips_ent
, 0},
1658 {"file", s_mips_file
, 0},
1659 {"fmask", s_mips_mask
, 'F'},
1660 {"frame", s_mips_frame
, 0},
1661 {"loc", s_mips_loc
, 0},
1662 {"mask", s_mips_mask
, 'R'},
1663 {"verstamp", s_ignore
, 0},
1667 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1668 purpose of the `.dc.a' internal pseudo-op. */
1671 mips_address_bytes (void)
1673 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1676 extern void pop_insert (const pseudo_typeS
*);
1679 mips_pop_insert (void)
1681 pop_insert (mips_pseudo_table
);
1682 if (! ECOFF_DEBUGGING
)
1683 pop_insert (mips_nonecoff_pseudo_table
);
1686 /* Symbols labelling the current insn. */
1688 struct insn_label_list
1690 struct insn_label_list
*next
;
1694 static struct insn_label_list
*free_insn_labels
;
1695 #define label_list tc_segment_info_data.labels
1697 static void mips_clear_insn_labels (void);
1698 static void mips_mark_labels (void);
1699 static void mips_compressed_mark_labels (void);
1702 mips_clear_insn_labels (void)
1704 register struct insn_label_list
**pl
;
1705 segment_info_type
*si
;
1709 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1712 si
= seg_info (now_seg
);
1713 *pl
= si
->label_list
;
1714 si
->label_list
= NULL
;
1718 /* Mark instruction labels in MIPS16/microMIPS mode. */
1721 mips_mark_labels (void)
1723 if (HAVE_CODE_COMPRESSION
)
1724 mips_compressed_mark_labels ();
1727 static char *expr_end
;
1729 /* Expressions which appear in macro instructions. These are set by
1730 mips_ip and read by macro. */
1732 static expressionS imm_expr
;
1733 static expressionS imm2_expr
;
1735 /* The relocatable field in an instruction and the relocs associated
1736 with it. These variables are used for instructions like LUI and
1737 JAL as well as true offsets. They are also used for address
1738 operands in macros. */
1740 static expressionS offset_expr
;
1741 static bfd_reloc_code_real_type offset_reloc
[3]
1742 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1744 /* This is set to the resulting size of the instruction to be produced
1745 by mips16_ip if an explicit extension is used or by mips_ip if an
1746 explicit size is supplied. */
1748 static unsigned int forced_insn_length
;
1750 /* True if we are assembling an instruction. All dot symbols defined during
1751 this time should be treated as code labels. */
1753 static bfd_boolean mips_assembling_insn
;
1755 /* The pdr segment for per procedure frame/regmask info. Not used for
1758 static segT pdr_seg
;
1760 /* The default target format to use. */
1762 #if defined (TE_FreeBSD)
1763 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1764 #elif defined (TE_TMIPS)
1765 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1767 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1771 mips_target_format (void)
1773 switch (OUTPUT_FLAVOR
)
1775 case bfd_target_elf_flavour
:
1777 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1778 return (target_big_endian
1779 ? "elf32-bigmips-vxworks"
1780 : "elf32-littlemips-vxworks");
1782 return (target_big_endian
1783 ? (HAVE_64BIT_OBJECTS
1784 ? ELF_TARGET ("elf64-", "big")
1786 ? ELF_TARGET ("elf32-n", "big")
1787 : ELF_TARGET ("elf32-", "big")))
1788 : (HAVE_64BIT_OBJECTS
1789 ? ELF_TARGET ("elf64-", "little")
1791 ? ELF_TARGET ("elf32-n", "little")
1792 : ELF_TARGET ("elf32-", "little"))));
1799 /* Return the ISA revision that is currently in use, or 0 if we are
1800 generating code for MIPS V or below. */
1805 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1808 /* microMIPS implies revision 2 or above. */
1809 if (mips_opts
.micromips
)
1812 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1818 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1821 mips_ase_mask (unsigned int flags
)
1825 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1826 if (flags
& mips_ase_groups
[i
])
1827 flags
|= mips_ase_groups
[i
];
1831 /* Check whether the current ISA supports ASE. Issue a warning if
1835 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1839 static unsigned int warned_isa
;
1840 static unsigned int warned_fp32
;
1842 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1843 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1845 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1846 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1847 && (warned_isa
& ase
->flags
) != ase
->flags
)
1849 warned_isa
|= ase
->flags
;
1850 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1851 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1853 as_warn (_("The %d-bit %s architecture does not support the"
1854 " `%s' extension"), size
, base
, ase
->name
);
1856 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1857 ase
->name
, base
, size
, min_rev
);
1859 if ((ase
->flags
& FP64_ASES
)
1861 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1863 warned_fp32
|= ase
->flags
;
1864 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1868 /* Check all enabled ASEs to see whether they are supported by the
1869 chosen architecture. */
1872 mips_check_isa_supports_ases (void)
1874 unsigned int i
, mask
;
1876 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1878 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1879 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1880 mips_check_isa_supports_ase (&mips_ases
[i
]);
1884 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1885 that were affected. */
1888 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1892 mask
= mips_ase_mask (ase
->flags
);
1893 mips_opts
.ase
&= ~mask
;
1895 mips_opts
.ase
|= ase
->flags
;
1899 /* Return the ASE called NAME, or null if none. */
1901 static const struct mips_ase
*
1902 mips_lookup_ase (const char *name
)
1906 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1907 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1908 return &mips_ases
[i
];
1912 /* Return the length of a microMIPS instruction in bytes. If bits of
1913 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1914 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1915 major opcode) will require further modifications to the opcode
1918 static inline unsigned int
1919 micromips_insn_length (const struct mips_opcode
*mo
)
1921 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1924 /* Return the length of MIPS16 instruction OPCODE. */
1926 static inline unsigned int
1927 mips16_opcode_length (unsigned long opcode
)
1929 return (opcode
>> 16) == 0 ? 2 : 4;
1932 /* Return the length of instruction INSN. */
1934 static inline unsigned int
1935 insn_length (const struct mips_cl_insn
*insn
)
1937 if (mips_opts
.micromips
)
1938 return micromips_insn_length (insn
->insn_mo
);
1939 else if (mips_opts
.mips16
)
1940 return mips16_opcode_length (insn
->insn_opcode
);
1945 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1948 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1953 insn
->insn_opcode
= mo
->match
;
1956 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1957 insn
->fixp
[i
] = NULL
;
1958 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1959 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1960 insn
->mips16_absolute_jump_p
= 0;
1961 insn
->complete_p
= 0;
1962 insn
->cleared_p
= 0;
1965 /* Get a list of all the operands in INSN. */
1967 static const struct mips_operand_array
*
1968 insn_operands (const struct mips_cl_insn
*insn
)
1970 if (insn
->insn_mo
>= &mips_opcodes
[0]
1971 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
1972 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
1974 if (insn
->insn_mo
>= &mips16_opcodes
[0]
1975 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
1976 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
1978 if (insn
->insn_mo
>= µmips_opcodes
[0]
1979 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
1980 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
1985 /* Get a description of operand OPNO of INSN. */
1987 static const struct mips_operand
*
1988 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
1990 const struct mips_operand_array
*operands
;
1992 operands
= insn_operands (insn
);
1993 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
1995 return operands
->operand
[opno
];
1998 /* Install UVAL as the value of OPERAND in INSN. */
2001 insn_insert_operand (struct mips_cl_insn
*insn
,
2002 const struct mips_operand
*operand
, unsigned int uval
)
2004 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2007 /* Extract the value of OPERAND from INSN. */
2009 static inline unsigned
2010 insn_extract_operand (const struct mips_cl_insn
*insn
,
2011 const struct mips_operand
*operand
)
2013 return mips_extract_operand (operand
, insn
->insn_opcode
);
2016 /* Record the current MIPS16/microMIPS mode in now_seg. */
2019 mips_record_compressed_mode (void)
2021 segment_info_type
*si
;
2023 si
= seg_info (now_seg
);
2024 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2025 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2026 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2027 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2030 /* Read a standard MIPS instruction from BUF. */
2032 static unsigned long
2033 read_insn (char *buf
)
2035 if (target_big_endian
)
2036 return bfd_getb32 ((bfd_byte
*) buf
);
2038 return bfd_getl32 ((bfd_byte
*) buf
);
2041 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2045 write_insn (char *buf
, unsigned int insn
)
2047 md_number_to_chars (buf
, insn
, 4);
2051 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2052 has length LENGTH. */
2054 static unsigned long
2055 read_compressed_insn (char *buf
, unsigned int length
)
2061 for (i
= 0; i
< length
; i
+= 2)
2064 if (target_big_endian
)
2065 insn
|= bfd_getb16 ((char *) buf
);
2067 insn
|= bfd_getl16 ((char *) buf
);
2073 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2074 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2077 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2081 for (i
= 0; i
< length
; i
+= 2)
2082 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2083 return buf
+ length
;
2086 /* Install INSN at the location specified by its "frag" and "where" fields. */
2089 install_insn (const struct mips_cl_insn
*insn
)
2091 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2092 if (HAVE_CODE_COMPRESSION
)
2093 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2095 write_insn (f
, insn
->insn_opcode
);
2096 mips_record_compressed_mode ();
2099 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2100 and install the opcode in the new location. */
2103 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2108 insn
->where
= where
;
2109 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2110 if (insn
->fixp
[i
] != NULL
)
2112 insn
->fixp
[i
]->fx_frag
= frag
;
2113 insn
->fixp
[i
]->fx_where
= where
;
2115 install_insn (insn
);
2118 /* Add INSN to the end of the output. */
2121 add_fixed_insn (struct mips_cl_insn
*insn
)
2123 char *f
= frag_more (insn_length (insn
));
2124 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2127 /* Start a variant frag and move INSN to the start of the variant part,
2128 marking it as fixed. The other arguments are as for frag_var. */
2131 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2132 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2134 frag_grow (max_chars
);
2135 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2137 frag_var (rs_machine_dependent
, max_chars
, var
,
2138 subtype
, symbol
, offset
, NULL
);
2141 /* Insert N copies of INSN into the history buffer, starting at
2142 position FIRST. Neither FIRST nor N need to be clipped. */
2145 insert_into_history (unsigned int first
, unsigned int n
,
2146 const struct mips_cl_insn
*insn
)
2148 if (mips_relax
.sequence
!= 2)
2152 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2154 history
[i
] = history
[i
- n
];
2160 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2161 the idea is to make it obvious at a glance that each errata is
2165 init_vr4120_conflicts (void)
2167 #define CONFLICT(FIRST, SECOND) \
2168 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2170 /* Errata 21 - [D]DIV[U] after [D]MACC */
2171 CONFLICT (MACC
, DIV
);
2172 CONFLICT (DMACC
, DIV
);
2174 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2175 CONFLICT (DMULT
, DMULT
);
2176 CONFLICT (DMULT
, DMACC
);
2177 CONFLICT (DMACC
, DMULT
);
2178 CONFLICT (DMACC
, DMACC
);
2180 /* Errata 24 - MT{LO,HI} after [D]MACC */
2181 CONFLICT (MACC
, MTHILO
);
2182 CONFLICT (DMACC
, MTHILO
);
2184 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2185 instruction is executed immediately after a MACC or DMACC
2186 instruction, the result of [either instruction] is incorrect." */
2187 CONFLICT (MACC
, MULT
);
2188 CONFLICT (MACC
, DMULT
);
2189 CONFLICT (DMACC
, MULT
);
2190 CONFLICT (DMACC
, DMULT
);
2192 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2193 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2194 DDIV or DDIVU instruction, the result of the MACC or
2195 DMACC instruction is incorrect.". */
2196 CONFLICT (DMULT
, MACC
);
2197 CONFLICT (DMULT
, DMACC
);
2198 CONFLICT (DIV
, MACC
);
2199 CONFLICT (DIV
, DMACC
);
2209 #define RNUM_MASK 0x00000ff
2210 #define RTYPE_MASK 0x0efff00
2211 #define RTYPE_NUM 0x0000100
2212 #define RTYPE_FPU 0x0000200
2213 #define RTYPE_FCC 0x0000400
2214 #define RTYPE_VEC 0x0000800
2215 #define RTYPE_GP 0x0001000
2216 #define RTYPE_CP0 0x0002000
2217 #define RTYPE_PC 0x0004000
2218 #define RTYPE_ACC 0x0008000
2219 #define RTYPE_CCC 0x0010000
2220 #define RTYPE_VI 0x0020000
2221 #define RTYPE_VF 0x0040000
2222 #define RTYPE_R5900_I 0x0080000
2223 #define RTYPE_R5900_Q 0x0100000
2224 #define RTYPE_R5900_R 0x0200000
2225 #define RTYPE_R5900_ACC 0x0400000
2226 #define RWARN 0x8000000
2228 #define GENERIC_REGISTER_NUMBERS \
2229 {"$0", RTYPE_NUM | 0}, \
2230 {"$1", RTYPE_NUM | 1}, \
2231 {"$2", RTYPE_NUM | 2}, \
2232 {"$3", RTYPE_NUM | 3}, \
2233 {"$4", RTYPE_NUM | 4}, \
2234 {"$5", RTYPE_NUM | 5}, \
2235 {"$6", RTYPE_NUM | 6}, \
2236 {"$7", RTYPE_NUM | 7}, \
2237 {"$8", RTYPE_NUM | 8}, \
2238 {"$9", RTYPE_NUM | 9}, \
2239 {"$10", RTYPE_NUM | 10}, \
2240 {"$11", RTYPE_NUM | 11}, \
2241 {"$12", RTYPE_NUM | 12}, \
2242 {"$13", RTYPE_NUM | 13}, \
2243 {"$14", RTYPE_NUM | 14}, \
2244 {"$15", RTYPE_NUM | 15}, \
2245 {"$16", RTYPE_NUM | 16}, \
2246 {"$17", RTYPE_NUM | 17}, \
2247 {"$18", RTYPE_NUM | 18}, \
2248 {"$19", RTYPE_NUM | 19}, \
2249 {"$20", RTYPE_NUM | 20}, \
2250 {"$21", RTYPE_NUM | 21}, \
2251 {"$22", RTYPE_NUM | 22}, \
2252 {"$23", RTYPE_NUM | 23}, \
2253 {"$24", RTYPE_NUM | 24}, \
2254 {"$25", RTYPE_NUM | 25}, \
2255 {"$26", RTYPE_NUM | 26}, \
2256 {"$27", RTYPE_NUM | 27}, \
2257 {"$28", RTYPE_NUM | 28}, \
2258 {"$29", RTYPE_NUM | 29}, \
2259 {"$30", RTYPE_NUM | 30}, \
2260 {"$31", RTYPE_NUM | 31}
2262 #define FPU_REGISTER_NAMES \
2263 {"$f0", RTYPE_FPU | 0}, \
2264 {"$f1", RTYPE_FPU | 1}, \
2265 {"$f2", RTYPE_FPU | 2}, \
2266 {"$f3", RTYPE_FPU | 3}, \
2267 {"$f4", RTYPE_FPU | 4}, \
2268 {"$f5", RTYPE_FPU | 5}, \
2269 {"$f6", RTYPE_FPU | 6}, \
2270 {"$f7", RTYPE_FPU | 7}, \
2271 {"$f8", RTYPE_FPU | 8}, \
2272 {"$f9", RTYPE_FPU | 9}, \
2273 {"$f10", RTYPE_FPU | 10}, \
2274 {"$f11", RTYPE_FPU | 11}, \
2275 {"$f12", RTYPE_FPU | 12}, \
2276 {"$f13", RTYPE_FPU | 13}, \
2277 {"$f14", RTYPE_FPU | 14}, \
2278 {"$f15", RTYPE_FPU | 15}, \
2279 {"$f16", RTYPE_FPU | 16}, \
2280 {"$f17", RTYPE_FPU | 17}, \
2281 {"$f18", RTYPE_FPU | 18}, \
2282 {"$f19", RTYPE_FPU | 19}, \
2283 {"$f20", RTYPE_FPU | 20}, \
2284 {"$f21", RTYPE_FPU | 21}, \
2285 {"$f22", RTYPE_FPU | 22}, \
2286 {"$f23", RTYPE_FPU | 23}, \
2287 {"$f24", RTYPE_FPU | 24}, \
2288 {"$f25", RTYPE_FPU | 25}, \
2289 {"$f26", RTYPE_FPU | 26}, \
2290 {"$f27", RTYPE_FPU | 27}, \
2291 {"$f28", RTYPE_FPU | 28}, \
2292 {"$f29", RTYPE_FPU | 29}, \
2293 {"$f30", RTYPE_FPU | 30}, \
2294 {"$f31", RTYPE_FPU | 31}
2296 #define FPU_CONDITION_CODE_NAMES \
2297 {"$fcc0", RTYPE_FCC | 0}, \
2298 {"$fcc1", RTYPE_FCC | 1}, \
2299 {"$fcc2", RTYPE_FCC | 2}, \
2300 {"$fcc3", RTYPE_FCC | 3}, \
2301 {"$fcc4", RTYPE_FCC | 4}, \
2302 {"$fcc5", RTYPE_FCC | 5}, \
2303 {"$fcc6", RTYPE_FCC | 6}, \
2304 {"$fcc7", RTYPE_FCC | 7}
2306 #define COPROC_CONDITION_CODE_NAMES \
2307 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2308 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2309 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2310 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2311 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2312 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2313 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2314 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2316 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2317 {"$a4", RTYPE_GP | 8}, \
2318 {"$a5", RTYPE_GP | 9}, \
2319 {"$a6", RTYPE_GP | 10}, \
2320 {"$a7", RTYPE_GP | 11}, \
2321 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2322 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2323 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2324 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2325 {"$t0", RTYPE_GP | 12}, \
2326 {"$t1", RTYPE_GP | 13}, \
2327 {"$t2", RTYPE_GP | 14}, \
2328 {"$t3", RTYPE_GP | 15}
2330 #define O32_SYMBOLIC_REGISTER_NAMES \
2331 {"$t0", RTYPE_GP | 8}, \
2332 {"$t1", RTYPE_GP | 9}, \
2333 {"$t2", RTYPE_GP | 10}, \
2334 {"$t3", RTYPE_GP | 11}, \
2335 {"$t4", RTYPE_GP | 12}, \
2336 {"$t5", RTYPE_GP | 13}, \
2337 {"$t6", RTYPE_GP | 14}, \
2338 {"$t7", RTYPE_GP | 15}, \
2339 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2340 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2341 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2342 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2344 /* Remaining symbolic register names */
2345 #define SYMBOLIC_REGISTER_NAMES \
2346 {"$zero", RTYPE_GP | 0}, \
2347 {"$at", RTYPE_GP | 1}, \
2348 {"$AT", RTYPE_GP | 1}, \
2349 {"$v0", RTYPE_GP | 2}, \
2350 {"$v1", RTYPE_GP | 3}, \
2351 {"$a0", RTYPE_GP | 4}, \
2352 {"$a1", RTYPE_GP | 5}, \
2353 {"$a2", RTYPE_GP | 6}, \
2354 {"$a3", RTYPE_GP | 7}, \
2355 {"$s0", RTYPE_GP | 16}, \
2356 {"$s1", RTYPE_GP | 17}, \
2357 {"$s2", RTYPE_GP | 18}, \
2358 {"$s3", RTYPE_GP | 19}, \
2359 {"$s4", RTYPE_GP | 20}, \
2360 {"$s5", RTYPE_GP | 21}, \
2361 {"$s6", RTYPE_GP | 22}, \
2362 {"$s7", RTYPE_GP | 23}, \
2363 {"$t8", RTYPE_GP | 24}, \
2364 {"$t9", RTYPE_GP | 25}, \
2365 {"$k0", RTYPE_GP | 26}, \
2366 {"$kt0", RTYPE_GP | 26}, \
2367 {"$k1", RTYPE_GP | 27}, \
2368 {"$kt1", RTYPE_GP | 27}, \
2369 {"$gp", RTYPE_GP | 28}, \
2370 {"$sp", RTYPE_GP | 29}, \
2371 {"$s8", RTYPE_GP | 30}, \
2372 {"$fp", RTYPE_GP | 30}, \
2373 {"$ra", RTYPE_GP | 31}
2375 #define MIPS16_SPECIAL_REGISTER_NAMES \
2376 {"$pc", RTYPE_PC | 0}
2378 #define MDMX_VECTOR_REGISTER_NAMES \
2379 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2380 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2381 {"$v2", RTYPE_VEC | 2}, \
2382 {"$v3", RTYPE_VEC | 3}, \
2383 {"$v4", RTYPE_VEC | 4}, \
2384 {"$v5", RTYPE_VEC | 5}, \
2385 {"$v6", RTYPE_VEC | 6}, \
2386 {"$v7", RTYPE_VEC | 7}, \
2387 {"$v8", RTYPE_VEC | 8}, \
2388 {"$v9", RTYPE_VEC | 9}, \
2389 {"$v10", RTYPE_VEC | 10}, \
2390 {"$v11", RTYPE_VEC | 11}, \
2391 {"$v12", RTYPE_VEC | 12}, \
2392 {"$v13", RTYPE_VEC | 13}, \
2393 {"$v14", RTYPE_VEC | 14}, \
2394 {"$v15", RTYPE_VEC | 15}, \
2395 {"$v16", RTYPE_VEC | 16}, \
2396 {"$v17", RTYPE_VEC | 17}, \
2397 {"$v18", RTYPE_VEC | 18}, \
2398 {"$v19", RTYPE_VEC | 19}, \
2399 {"$v20", RTYPE_VEC | 20}, \
2400 {"$v21", RTYPE_VEC | 21}, \
2401 {"$v22", RTYPE_VEC | 22}, \
2402 {"$v23", RTYPE_VEC | 23}, \
2403 {"$v24", RTYPE_VEC | 24}, \
2404 {"$v25", RTYPE_VEC | 25}, \
2405 {"$v26", RTYPE_VEC | 26}, \
2406 {"$v27", RTYPE_VEC | 27}, \
2407 {"$v28", RTYPE_VEC | 28}, \
2408 {"$v29", RTYPE_VEC | 29}, \
2409 {"$v30", RTYPE_VEC | 30}, \
2410 {"$v31", RTYPE_VEC | 31}
2412 #define R5900_I_NAMES \
2413 {"$I", RTYPE_R5900_I | 0}
2415 #define R5900_Q_NAMES \
2416 {"$Q", RTYPE_R5900_Q | 0}
2418 #define R5900_R_NAMES \
2419 {"$R", RTYPE_R5900_R | 0}
2421 #define R5900_ACC_NAMES \
2422 {"$ACC", RTYPE_R5900_ACC | 0 }
2424 #define MIPS_DSP_ACCUMULATOR_NAMES \
2425 {"$ac0", RTYPE_ACC | 0}, \
2426 {"$ac1", RTYPE_ACC | 1}, \
2427 {"$ac2", RTYPE_ACC | 2}, \
2428 {"$ac3", RTYPE_ACC | 3}
2430 static const struct regname reg_names
[] = {
2431 GENERIC_REGISTER_NUMBERS
,
2433 FPU_CONDITION_CODE_NAMES
,
2434 COPROC_CONDITION_CODE_NAMES
,
2436 /* The $txx registers depends on the abi,
2437 these will be added later into the symbol table from
2438 one of the tables below once mips_abi is set after
2439 parsing of arguments from the command line. */
2440 SYMBOLIC_REGISTER_NAMES
,
2442 MIPS16_SPECIAL_REGISTER_NAMES
,
2443 MDMX_VECTOR_REGISTER_NAMES
,
2448 MIPS_DSP_ACCUMULATOR_NAMES
,
2452 static const struct regname reg_names_o32
[] = {
2453 O32_SYMBOLIC_REGISTER_NAMES
,
2457 static const struct regname reg_names_n32n64
[] = {
2458 N32N64_SYMBOLIC_REGISTER_NAMES
,
2462 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2463 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2464 of these register symbols, return the associated vector register,
2465 otherwise return SYMVAL itself. */
2468 mips_prefer_vec_regno (unsigned int symval
)
2470 if ((symval
& -2) == (RTYPE_GP
| 2))
2471 return RTYPE_VEC
| (symval
& 1);
2475 /* Return true if string [S, E) is a valid register name, storing its
2476 symbol value in *SYMVAL_PTR if so. */
2479 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2484 /* Terminate name. */
2488 /* Look up the name. */
2489 symbol
= symbol_find (s
);
2492 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2495 *symval_ptr
= S_GET_VALUE (symbol
);
2499 /* Return true if the string at *SPTR is a valid register name. Allow it
2500 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2503 When returning true, move *SPTR past the register, store the
2504 register's symbol value in *SYMVAL_PTR and the channel mask in
2505 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2506 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2507 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2510 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2511 unsigned int *channels_ptr
)
2515 unsigned int channels
, symval
, bit
;
2517 /* Find end of name. */
2519 if (is_name_beginner (*e
))
2521 while (is_part_of_name (*e
))
2525 if (!mips_parse_register_1 (s
, e
, &symval
))
2530 /* Eat characters from the end of the string that are valid
2531 channel suffixes. The preceding register must be $ACC or
2532 end with a digit, so there is no ambiguity. */
2535 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2536 if (m
> s
&& m
[-1] == *q
)
2543 || !mips_parse_register_1 (s
, m
, &symval
)
2544 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2549 *symval_ptr
= symval
;
2551 *channels_ptr
= channels
;
2555 /* Check if SPTR points at a valid register specifier according to TYPES.
2556 If so, then return 1, advance S to consume the specifier and store
2557 the register's number in REGNOP, otherwise return 0. */
2560 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2564 if (mips_parse_register (s
, ®no
, NULL
))
2566 if (types
& RTYPE_VEC
)
2567 regno
= mips_prefer_vec_regno (regno
);
2576 as_warn (_("Unrecognized register name `%s'"), *s
);
2581 return regno
<= RNUM_MASK
;
2584 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2585 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2588 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2593 for (i
= 0; i
< 4; i
++)
2594 if (*s
== "xyzw"[i
])
2596 *channels
|= 1 << (3 - i
);
2602 /* Token types for parsed operand lists. */
2603 enum mips_operand_token_type
{
2604 /* A plain register, e.g. $f2. */
2607 /* A 4-bit XYZW channel mask. */
2610 /* An element of a vector, e.g. $v0[1]. */
2613 /* A continuous range of registers, e.g. $s0-$s4. */
2616 /* A (possibly relocated) expression. */
2619 /* A floating-point value. */
2622 /* A single character. This can be '(', ')' or ',', but '(' only appears
2626 /* A doubled character, either "--" or "++". */
2629 /* The end of the operand list. */
2633 /* A parsed operand token. */
2634 struct mips_operand_token
2636 /* The type of token. */
2637 enum mips_operand_token_type type
;
2640 /* The register symbol value for an OT_REG. */
2643 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2644 unsigned int channels
;
2646 /* The register symbol value and index for an OT_REG_ELEMENT. */
2652 /* The two register symbol values involved in an OT_REG_RANGE. */
2654 unsigned int regno1
;
2655 unsigned int regno2
;
2658 /* The value of an OT_INTEGER. The value is represented as an
2659 expression and the relocation operators that were applied to
2660 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2661 relocation operators were used. */
2664 bfd_reloc_code_real_type relocs
[3];
2667 /* The binary data for an OT_FLOAT constant, and the number of bytes
2670 unsigned char data
[8];
2674 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2679 /* An obstack used to construct lists of mips_operand_tokens. */
2680 static struct obstack mips_operand_tokens
;
2682 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2685 mips_add_token (struct mips_operand_token
*token
,
2686 enum mips_operand_token_type type
)
2689 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2692 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2693 and OT_REG tokens for them if so, and return a pointer to the first
2694 unconsumed character. Return null otherwise. */
2697 mips_parse_base_start (char *s
)
2699 struct mips_operand_token token
;
2700 unsigned int regno
, channels
;
2701 bfd_boolean decrement_p
;
2707 SKIP_SPACE_TABS (s
);
2709 /* Only match "--" as part of a base expression. In other contexts "--X"
2710 is a double negative. */
2711 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2715 SKIP_SPACE_TABS (s
);
2718 /* Allow a channel specifier because that leads to better error messages
2719 than treating something like "$vf0x++" as an expression. */
2720 if (!mips_parse_register (&s
, ®no
, &channels
))
2724 mips_add_token (&token
, OT_CHAR
);
2729 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2732 token
.u
.regno
= regno
;
2733 mips_add_token (&token
, OT_REG
);
2737 token
.u
.channels
= channels
;
2738 mips_add_token (&token
, OT_CHANNELS
);
2741 /* For consistency, only match "++" as part of base expressions too. */
2742 SKIP_SPACE_TABS (s
);
2743 if (s
[0] == '+' && s
[1] == '+')
2747 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2753 /* Parse one or more tokens from S. Return a pointer to the first
2754 unconsumed character on success. Return null if an error was found
2755 and store the error text in insn_error. FLOAT_FORMAT is as for
2756 mips_parse_arguments. */
2759 mips_parse_argument_token (char *s
, char float_format
)
2761 char *end
, *save_in
, *err
;
2762 unsigned int regno1
, regno2
, channels
;
2763 struct mips_operand_token token
;
2765 /* First look for "($reg", since we want to treat that as an
2766 OT_CHAR and OT_REG rather than an expression. */
2767 end
= mips_parse_base_start (s
);
2771 /* Handle other characters that end up as OT_CHARs. */
2772 if (*s
== ')' || *s
== ',')
2775 mips_add_token (&token
, OT_CHAR
);
2780 /* Handle tokens that start with a register. */
2781 if (mips_parse_register (&s
, ®no1
, &channels
))
2785 /* A register and a VU0 channel suffix. */
2786 token
.u
.regno
= regno1
;
2787 mips_add_token (&token
, OT_REG
);
2789 token
.u
.channels
= channels
;
2790 mips_add_token (&token
, OT_CHANNELS
);
2794 SKIP_SPACE_TABS (s
);
2797 /* A register range. */
2799 SKIP_SPACE_TABS (s
);
2800 if (!mips_parse_register (&s
, ®no2
, NULL
))
2802 insn_error
= _("Invalid register range");
2806 token
.u
.reg_range
.regno1
= regno1
;
2807 token
.u
.reg_range
.regno2
= regno2
;
2808 mips_add_token (&token
, OT_REG_RANGE
);
2813 /* A vector element. */
2814 expressionS element
;
2817 SKIP_SPACE_TABS (s
);
2818 my_getExpression (&element
, s
);
2819 if (element
.X_op
!= O_constant
)
2821 insn_error
= _("Vector element must be constant");
2825 SKIP_SPACE_TABS (s
);
2828 insn_error
= _("Missing `]'");
2833 token
.u
.reg_element
.regno
= regno1
;
2834 token
.u
.reg_element
.index
= element
.X_add_number
;
2835 mips_add_token (&token
, OT_REG_ELEMENT
);
2839 /* Looks like just a plain register. */
2840 token
.u
.regno
= regno1
;
2841 mips_add_token (&token
, OT_REG
);
2847 /* First try to treat expressions as floats. */
2848 save_in
= input_line_pointer
;
2849 input_line_pointer
= s
;
2850 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
2851 &token
.u
.flt
.length
);
2852 end
= input_line_pointer
;
2853 input_line_pointer
= save_in
;
2861 mips_add_token (&token
, OT_FLOAT
);
2866 /* Treat everything else as an integer expression. */
2867 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
2868 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
2869 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
2870 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
2872 mips_add_token (&token
, OT_INTEGER
);
2876 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
2877 if expressions should be treated as 32-bit floating-point constants,
2878 'd' if they should be treated as 64-bit floating-point constants,
2879 or 0 if they should be treated as integer expressions (the usual case).
2881 Return a list of tokens on success, otherwise return 0. The caller
2882 must obstack_free the list after use. */
2884 static struct mips_operand_token
*
2885 mips_parse_arguments (char *s
, char float_format
)
2887 struct mips_operand_token token
;
2889 SKIP_SPACE_TABS (s
);
2892 s
= mips_parse_argument_token (s
, float_format
);
2895 obstack_free (&mips_operand_tokens
,
2896 obstack_finish (&mips_operand_tokens
));
2899 SKIP_SPACE_TABS (s
);
2901 mips_add_token (&token
, OT_END
);
2902 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
2905 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2906 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2909 is_opcode_valid (const struct mips_opcode
*mo
)
2911 int isa
= mips_opts
.isa
;
2912 int ase
= mips_opts
.ase
;
2916 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2917 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2918 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
2919 ase
|= mips_ases
[i
].flags64
;
2921 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2924 /* Check whether the instruction or macro requires single-precision or
2925 double-precision floating-point support. Note that this information is
2926 stored differently in the opcode table for insns and macros. */
2927 if (mo
->pinfo
== INSN_MACRO
)
2929 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2930 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2934 fp_s
= mo
->pinfo
& FP_S
;
2935 fp_d
= mo
->pinfo
& FP_D
;
2938 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2941 if (fp_s
&& mips_opts
.soft_float
)
2947 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2948 selected ISA and architecture. */
2951 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2953 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2956 /* Return TRUE if the size of the microMIPS opcode MO matches one
2957 explicitly requested. Always TRUE in the standard MIPS mode. */
2960 is_size_valid (const struct mips_opcode
*mo
)
2962 if (!mips_opts
.micromips
)
2965 if (mips_opts
.insn32
)
2967 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
2969 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
2972 if (!forced_insn_length
)
2974 if (mo
->pinfo
== INSN_MACRO
)
2976 return forced_insn_length
== micromips_insn_length (mo
);
2979 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2980 of the preceding instruction. Always TRUE in the standard MIPS mode.
2982 We don't accept macros in 16-bit delay slots to avoid a case where
2983 a macro expansion fails because it relies on a preceding 32-bit real
2984 instruction to have matched and does not handle the operands correctly.
2985 The only macros that may expand to 16-bit instructions are JAL that
2986 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2987 and BGT (that likewise cannot be placed in a delay slot) that decay to
2988 a NOP. In all these cases the macros precede any corresponding real
2989 instruction definitions in the opcode table, so they will match in the
2990 second pass where the size of the delay slot is ignored and therefore
2991 produce correct code. */
2994 is_delay_slot_valid (const struct mips_opcode
*mo
)
2996 if (!mips_opts
.micromips
)
2999 if (mo
->pinfo
== INSN_MACRO
)
3000 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3001 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3002 && micromips_insn_length (mo
) != 4)
3004 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3005 && micromips_insn_length (mo
) != 2)
3011 /* For consistency checking, verify that all bits of OPCODE are specified
3012 either by the match/mask part of the instruction definition, or by the
3013 operand list. Also build up a list of operands in OPERANDS.
3015 INSN_BITS says which bits of the instruction are significant.
3016 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3017 provides the mips_operand description of each operand. DECODE_OPERAND
3018 is null for MIPS16 instructions. */
3021 validate_mips_insn (const struct mips_opcode
*opcode
,
3022 unsigned long insn_bits
,
3023 const struct mips_operand
*(*decode_operand
) (const char *),
3024 struct mips_operand_array
*operands
)
3027 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3028 const struct mips_operand
*operand
;
3030 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3031 if ((mask
& opcode
->match
) != opcode
->match
)
3033 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3034 opcode
->name
, opcode
->args
);
3039 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3040 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3041 for (s
= opcode
->args
; *s
; ++s
)
3054 if (!decode_operand
)
3055 operand
= decode_mips16_operand (*s
, FALSE
);
3057 operand
= decode_operand (s
);
3058 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3060 as_bad (_("internal: unknown operand type: %s %s"),
3061 opcode
->name
, opcode
->args
);
3064 gas_assert (opno
< MAX_OPERANDS
);
3065 operands
->operand
[opno
] = operand
;
3066 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3068 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3069 if (operand
->type
== OP_MDMX_IMM_REG
)
3070 /* Bit 5 is the format selector (OB vs QH). The opcode table
3071 has separate entries for each format. */
3072 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3073 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3074 used_bits
&= ~(mask
& 0x700);
3076 /* Skip prefix characters. */
3077 if (decode_operand
&& (*s
== '+' || *s
== 'm'))
3082 doubled
= used_bits
& mask
& insn_bits
;
3085 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3086 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3090 undefined
= ~used_bits
& insn_bits
;
3091 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3093 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3094 undefined
, opcode
->name
, opcode
->args
);
3097 used_bits
&= ~insn_bits
;
3100 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3101 used_bits
, opcode
->name
, opcode
->args
);
3107 /* The MIPS16 version of validate_mips_insn. */
3110 validate_mips16_insn (const struct mips_opcode
*opcode
,
3111 struct mips_operand_array
*operands
)
3113 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3115 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3116 instruction. Use TMP to describe the full instruction. */
3117 struct mips_opcode tmp
;
3122 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3124 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3127 /* The microMIPS version of validate_mips_insn. */
3130 validate_micromips_insn (const struct mips_opcode
*opc
,
3131 struct mips_operand_array
*operands
)
3133 unsigned long insn_bits
;
3134 unsigned long major
;
3135 unsigned int length
;
3137 if (opc
->pinfo
== INSN_MACRO
)
3138 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3141 length
= micromips_insn_length (opc
);
3142 if (length
!= 2 && length
!= 4)
3144 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3145 "%s %s"), length
, opc
->name
, opc
->args
);
3148 major
= opc
->match
>> (10 + 8 * (length
- 2));
3149 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3150 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3152 as_bad (_("Internal error: bad microMIPS opcode "
3153 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3157 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3158 insn_bits
= 1 << 4 * length
;
3159 insn_bits
<<= 4 * length
;
3161 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3165 /* This function is called once, at assembler startup time. It should set up
3166 all the tables, etc. that the MD part of the assembler will need. */
3171 const char *retval
= NULL
;
3175 if (mips_pic
!= NO_PIC
)
3177 if (g_switch_seen
&& g_switch_value
!= 0)
3178 as_bad (_("-G may not be used in position-independent code"));
3182 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
3183 as_warn (_("Could not set architecture and machine"));
3185 op_hash
= hash_new ();
3187 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3188 for (i
= 0; i
< NUMOPCODES
;)
3190 const char *name
= mips_opcodes
[i
].name
;
3192 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3195 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3196 mips_opcodes
[i
].name
, retval
);
3197 /* Probably a memory allocation problem? Give up now. */
3198 as_fatal (_("Broken assembler. No assembly attempted."));
3202 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3203 decode_mips_operand
, &mips_operands
[i
]))
3205 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3207 create_insn (&nop_insn
, mips_opcodes
+ i
);
3208 if (mips_fix_loongson2f_nop
)
3209 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3210 nop_insn
.fixed_p
= 1;
3214 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3217 mips16_op_hash
= hash_new ();
3218 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3219 bfd_mips16_num_opcodes
);
3222 while (i
< bfd_mips16_num_opcodes
)
3224 const char *name
= mips16_opcodes
[i
].name
;
3226 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3228 as_fatal (_("internal: can't hash `%s': %s"),
3229 mips16_opcodes
[i
].name
, retval
);
3232 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3234 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3236 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3237 mips16_nop_insn
.fixed_p
= 1;
3241 while (i
< bfd_mips16_num_opcodes
3242 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3245 micromips_op_hash
= hash_new ();
3246 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3247 bfd_micromips_num_opcodes
);
3250 while (i
< bfd_micromips_num_opcodes
)
3252 const char *name
= micromips_opcodes
[i
].name
;
3254 retval
= hash_insert (micromips_op_hash
, name
,
3255 (void *) µmips_opcodes
[i
]);
3257 as_fatal (_("internal: can't hash `%s': %s"),
3258 micromips_opcodes
[i
].name
, retval
);
3261 struct mips_cl_insn
*micromips_nop_insn
;
3263 if (!validate_micromips_insn (µmips_opcodes
[i
],
3264 µmips_operands
[i
]))
3267 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3269 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3270 micromips_nop_insn
= µmips_nop16_insn
;
3271 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3272 micromips_nop_insn
= µmips_nop32_insn
;
3276 if (micromips_nop_insn
->insn_mo
== NULL
3277 && strcmp (name
, "nop") == 0)
3279 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3280 micromips_nop_insn
->fixed_p
= 1;
3284 while (++i
< bfd_micromips_num_opcodes
3285 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3289 as_fatal (_("Broken assembler. No assembly attempted."));
3291 /* We add all the general register names to the symbol table. This
3292 helps us detect invalid uses of them. */
3293 for (i
= 0; reg_names
[i
].name
; i
++)
3294 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3295 reg_names
[i
].num
, /* & RNUM_MASK, */
3296 &zero_address_frag
));
3298 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3299 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3300 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3301 &zero_address_frag
));
3303 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3304 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3305 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3306 &zero_address_frag
));
3308 for (i
= 0; i
< 32; i
++)
3312 /* R5900 VU0 floating-point register. */
3313 regname
[sizeof (rename
) - 1] = 0;
3314 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3315 symbol_table_insert (symbol_new (regname
, reg_section
,
3316 RTYPE_VF
| i
, &zero_address_frag
));
3318 /* R5900 VU0 integer register. */
3319 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3320 symbol_table_insert (symbol_new (regname
, reg_section
,
3321 RTYPE_VI
| i
, &zero_address_frag
));
3325 obstack_init (&mips_operand_tokens
);
3327 mips_no_prev_insn ();
3330 mips_cprmask
[0] = 0;
3331 mips_cprmask
[1] = 0;
3332 mips_cprmask
[2] = 0;
3333 mips_cprmask
[3] = 0;
3335 /* set the default alignment for the text section (2**2) */
3336 record_alignment (text_section
, 2);
3338 bfd_set_gp_size (stdoutput
, g_switch_value
);
3340 /* On a native system other than VxWorks, sections must be aligned
3341 to 16 byte boundaries. When configured for an embedded ELF
3342 target, we don't bother. */
3343 if (strncmp (TARGET_OS
, "elf", 3) != 0
3344 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3346 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3347 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3348 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3351 /* Create a .reginfo section for register masks and a .mdebug
3352 section for debugging information. */
3360 subseg
= now_subseg
;
3362 /* The ABI says this section should be loaded so that the
3363 running program can access it. However, we don't load it
3364 if we are configured for an embedded target */
3365 flags
= SEC_READONLY
| SEC_DATA
;
3366 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3367 flags
|= SEC_ALLOC
| SEC_LOAD
;
3369 if (mips_abi
!= N64_ABI
)
3371 sec
= subseg_new (".reginfo", (subsegT
) 0);
3373 bfd_set_section_flags (stdoutput
, sec
, flags
);
3374 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3376 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3380 /* The 64-bit ABI uses a .MIPS.options section rather than
3381 .reginfo section. */
3382 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3383 bfd_set_section_flags (stdoutput
, sec
, flags
);
3384 bfd_set_section_alignment (stdoutput
, sec
, 3);
3386 /* Set up the option header. */
3388 Elf_Internal_Options opthdr
;
3391 opthdr
.kind
= ODK_REGINFO
;
3392 opthdr
.size
= (sizeof (Elf_External_Options
)
3393 + sizeof (Elf64_External_RegInfo
));
3396 f
= frag_more (sizeof (Elf_External_Options
));
3397 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3398 (Elf_External_Options
*) f
);
3400 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3404 if (ECOFF_DEBUGGING
)
3406 sec
= subseg_new (".mdebug", (subsegT
) 0);
3407 (void) bfd_set_section_flags (stdoutput
, sec
,
3408 SEC_HAS_CONTENTS
| SEC_READONLY
);
3409 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3411 else if (mips_flag_pdr
)
3413 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3414 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3415 SEC_READONLY
| SEC_RELOC
3417 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3420 subseg_set (seg
, subseg
);
3423 if (! ECOFF_DEBUGGING
)
3426 if (mips_fix_vr4120
)
3427 init_vr4120_conflicts ();
3433 mips_emit_delays ();
3434 if (! ECOFF_DEBUGGING
)
3439 md_assemble (char *str
)
3441 struct mips_cl_insn insn
;
3442 bfd_reloc_code_real_type unused_reloc
[3]
3443 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3445 imm_expr
.X_op
= O_absent
;
3446 imm2_expr
.X_op
= O_absent
;
3447 offset_expr
.X_op
= O_absent
;
3448 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3449 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3450 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3452 mips_mark_labels ();
3453 mips_assembling_insn
= TRUE
;
3455 if (mips_opts
.mips16
)
3456 mips16_ip (str
, &insn
);
3459 mips_ip (str
, &insn
);
3460 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3461 str
, insn
.insn_opcode
));
3465 as_bad ("%s `%s'", insn_error
, str
);
3466 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3469 if (mips_opts
.mips16
)
3470 mips16_macro (&insn
);
3477 if (offset_expr
.X_op
!= O_absent
)
3478 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3480 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3483 mips_assembling_insn
= FALSE
;
3486 /* Convenience functions for abstracting away the differences between
3487 MIPS16 and non-MIPS16 relocations. */
3489 static inline bfd_boolean
3490 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3494 case BFD_RELOC_MIPS16_JMP
:
3495 case BFD_RELOC_MIPS16_GPREL
:
3496 case BFD_RELOC_MIPS16_GOT16
:
3497 case BFD_RELOC_MIPS16_CALL16
:
3498 case BFD_RELOC_MIPS16_HI16_S
:
3499 case BFD_RELOC_MIPS16_HI16
:
3500 case BFD_RELOC_MIPS16_LO16
:
3508 static inline bfd_boolean
3509 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3513 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3514 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3515 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3516 case BFD_RELOC_MICROMIPS_GPREL16
:
3517 case BFD_RELOC_MICROMIPS_JMP
:
3518 case BFD_RELOC_MICROMIPS_HI16
:
3519 case BFD_RELOC_MICROMIPS_HI16_S
:
3520 case BFD_RELOC_MICROMIPS_LO16
:
3521 case BFD_RELOC_MICROMIPS_LITERAL
:
3522 case BFD_RELOC_MICROMIPS_GOT16
:
3523 case BFD_RELOC_MICROMIPS_CALL16
:
3524 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3525 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3526 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3527 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3528 case BFD_RELOC_MICROMIPS_SUB
:
3529 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3530 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3531 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3532 case BFD_RELOC_MICROMIPS_HIGHEST
:
3533 case BFD_RELOC_MICROMIPS_HIGHER
:
3534 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3535 case BFD_RELOC_MICROMIPS_JALR
:
3543 static inline bfd_boolean
3544 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3546 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3549 static inline bfd_boolean
3550 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3552 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3553 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3556 static inline bfd_boolean
3557 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3559 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3560 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3563 static inline bfd_boolean
3564 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3566 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3567 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3570 static inline bfd_boolean
3571 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3573 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3576 static inline bfd_boolean
3577 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3579 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3580 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3583 /* Return true if RELOC is a PC-relative relocation that does not have
3584 full address range. */
3586 static inline bfd_boolean
3587 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3591 case BFD_RELOC_16_PCREL_S2
:
3592 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3593 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3594 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3597 case BFD_RELOC_32_PCREL
:
3598 return HAVE_64BIT_ADDRESSES
;
3605 /* Return true if the given relocation might need a matching %lo().
3606 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3607 need a matching %lo() when applied to local symbols. */
3609 static inline bfd_boolean
3610 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3612 return (HAVE_IN_PLACE_ADDENDS
3613 && (hi16_reloc_p (reloc
)
3614 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3615 all GOT16 relocations evaluate to "G". */
3616 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3619 /* Return the type of %lo() reloc needed by RELOC, given that
3620 reloc_needs_lo_p. */
3622 static inline bfd_reloc_code_real_type
3623 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3625 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3626 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3630 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3633 static inline bfd_boolean
3634 fixup_has_matching_lo_p (fixS
*fixp
)
3636 return (fixp
->fx_next
!= NULL
3637 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3638 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3639 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3642 /* Move all labels in LABELS to the current insertion point. TEXT_P
3643 says whether the labels refer to text or data. */
3646 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3648 struct insn_label_list
*l
;
3651 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3653 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3654 symbol_set_frag (l
->label
, frag_now
);
3655 val
= (valueT
) frag_now_fix ();
3656 /* MIPS16/microMIPS text labels are stored as odd. */
3657 if (text_p
&& HAVE_CODE_COMPRESSION
)
3659 S_SET_VALUE (l
->label
, val
);
3663 /* Move all labels in insn_labels to the current insertion point
3664 and treat them as text labels. */
3667 mips_move_text_labels (void)
3669 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3673 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3675 bfd_boolean linkonce
= FALSE
;
3676 segT symseg
= S_GET_SEGMENT (sym
);
3678 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3680 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3682 /* The GNU toolchain uses an extension for ELF: a section
3683 beginning with the magic string .gnu.linkonce is a
3684 linkonce section. */
3685 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3686 sizeof ".gnu.linkonce" - 1) == 0)
3692 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3693 linker to handle them specially, such as generating jalx instructions
3694 when needed. We also make them odd for the duration of the assembly,
3695 in order to generate the right sort of code. We will make them even
3696 in the adjust_symtab routine, while leaving them marked. This is
3697 convenient for the debugger and the disassembler. The linker knows
3698 to make them odd again. */
3701 mips_compressed_mark_label (symbolS
*label
)
3703 gas_assert (HAVE_CODE_COMPRESSION
);
3705 if (mips_opts
.mips16
)
3706 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3708 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3709 if ((S_GET_VALUE (label
) & 1) == 0
3710 /* Don't adjust the address if the label is global or weak, or
3711 in a link-once section, since we'll be emitting symbol reloc
3712 references to it which will be patched up by the linker, and
3713 the final value of the symbol may or may not be MIPS16/microMIPS. */
3714 && !S_IS_WEAK (label
)
3715 && !S_IS_EXTERNAL (label
)
3716 && !s_is_linkonce (label
, now_seg
))
3717 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3720 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3723 mips_compressed_mark_labels (void)
3725 struct insn_label_list
*l
;
3727 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3728 mips_compressed_mark_label (l
->label
);
3731 /* End the current frag. Make it a variant frag and record the
3735 relax_close_frag (void)
3737 mips_macro_warning
.first_frag
= frag_now
;
3738 frag_var (rs_machine_dependent
, 0, 0,
3739 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3740 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3742 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3743 mips_relax
.first_fixup
= 0;
3746 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3747 See the comment above RELAX_ENCODE for more details. */
3750 relax_start (symbolS
*symbol
)
3752 gas_assert (mips_relax
.sequence
== 0);
3753 mips_relax
.sequence
= 1;
3754 mips_relax
.symbol
= symbol
;
3757 /* Start generating the second version of a relaxable sequence.
3758 See the comment above RELAX_ENCODE for more details. */
3763 gas_assert (mips_relax
.sequence
== 1);
3764 mips_relax
.sequence
= 2;
3767 /* End the current relaxable sequence. */
3772 gas_assert (mips_relax
.sequence
== 2);
3773 relax_close_frag ();
3774 mips_relax
.sequence
= 0;
3777 /* Return true if IP is a delayed branch or jump. */
3779 static inline bfd_boolean
3780 delayed_branch_p (const struct mips_cl_insn
*ip
)
3782 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3783 | INSN_COND_BRANCH_DELAY
3784 | INSN_COND_BRANCH_LIKELY
)) != 0;
3787 /* Return true if IP is a compact branch or jump. */
3789 static inline bfd_boolean
3790 compact_branch_p (const struct mips_cl_insn
*ip
)
3792 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3793 | INSN2_COND_BRANCH
)) != 0;
3796 /* Return true if IP is an unconditional branch or jump. */
3798 static inline bfd_boolean
3799 uncond_branch_p (const struct mips_cl_insn
*ip
)
3801 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3802 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
3805 /* Return true if IP is a branch-likely instruction. */
3807 static inline bfd_boolean
3808 branch_likely_p (const struct mips_cl_insn
*ip
)
3810 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3813 /* Return the type of nop that should be used to fill the delay slot
3814 of delayed branch IP. */
3816 static struct mips_cl_insn
*
3817 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3819 if (mips_opts
.micromips
3820 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3821 return µmips_nop32_insn
;
3825 /* Return a mask that has bit N set if OPCODE reads the register(s)
3829 insn_read_mask (const struct mips_opcode
*opcode
)
3831 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
3834 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3838 insn_write_mask (const struct mips_opcode
*opcode
)
3840 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
3843 /* Return a mask of the registers specified by operand OPERAND of INSN.
3844 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3848 operand_reg_mask (const struct mips_cl_insn
*insn
,
3849 const struct mips_operand
*operand
,
3850 unsigned int type_mask
)
3852 unsigned int uval
, vsel
;
3854 switch (operand
->type
)
3861 case OP_ADDIUSP_INT
:
3862 case OP_ENTRY_EXIT_LIST
:
3863 case OP_REPEAT_DEST_REG
:
3864 case OP_REPEAT_PREV_REG
:
3867 case OP_VU0_MATCH_SUFFIX
:
3871 case OP_OPTIONAL_REG
:
3873 const struct mips_reg_operand
*reg_op
;
3875 reg_op
= (const struct mips_reg_operand
*) operand
;
3876 if (!(type_mask
& (1 << reg_op
->reg_type
)))
3878 uval
= insn_extract_operand (insn
, operand
);
3879 return 1 << mips_decode_reg_operand (reg_op
, uval
);
3884 const struct mips_reg_pair_operand
*pair_op
;
3886 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
3887 if (!(type_mask
& (1 << pair_op
->reg_type
)))
3889 uval
= insn_extract_operand (insn
, operand
);
3890 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
3893 case OP_CLO_CLZ_DEST
:
3894 if (!(type_mask
& (1 << OP_REG_GP
)))
3896 uval
= insn_extract_operand (insn
, operand
);
3897 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
3899 case OP_LWM_SWM_LIST
:
3902 case OP_SAVE_RESTORE_LIST
:
3905 case OP_MDMX_IMM_REG
:
3906 if (!(type_mask
& (1 << OP_REG_VEC
)))
3908 uval
= insn_extract_operand (insn
, operand
);
3910 if ((vsel
& 0x18) == 0x18)
3912 return 1 << (uval
& 31);
3917 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
3918 where bit N of OPNO_MASK is set if operand N should be included.
3919 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3923 insn_reg_mask (const struct mips_cl_insn
*insn
,
3924 unsigned int type_mask
, unsigned int opno_mask
)
3926 unsigned int opno
, reg_mask
;
3930 while (opno_mask
!= 0)
3933 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
3940 /* Return the mask of core registers that IP reads. */
3943 gpr_read_mask (const struct mips_cl_insn
*ip
)
3945 unsigned long pinfo
, pinfo2
;
3948 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
3949 pinfo
= ip
->insn_mo
->pinfo
;
3950 pinfo2
= ip
->insn_mo
->pinfo2
;
3951 if (pinfo
& INSN_UDI
)
3953 /* UDI instructions have traditionally been assumed to read RS
3955 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3956 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3958 if (pinfo
& INSN_READ_GPR_24
)
3960 if (pinfo2
& INSN2_READ_GPR_16
)
3962 if (pinfo2
& INSN2_READ_SP
)
3964 if (pinfo2
& INSN2_READ_GPR_31
)
3966 /* Don't include register 0. */
3970 /* Return the mask of core registers that IP writes. */
3973 gpr_write_mask (const struct mips_cl_insn
*ip
)
3975 unsigned long pinfo
, pinfo2
;
3978 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
3979 pinfo
= ip
->insn_mo
->pinfo
;
3980 pinfo2
= ip
->insn_mo
->pinfo2
;
3981 if (pinfo
& INSN_WRITE_GPR_24
)
3983 if (pinfo
& INSN_WRITE_GPR_31
)
3985 if (pinfo
& INSN_UDI
)
3986 /* UDI instructions have traditionally been assumed to write to RD. */
3987 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3988 if (pinfo2
& INSN2_WRITE_SP
)
3990 /* Don't include register 0. */
3994 /* Return the mask of floating-point registers that IP reads. */
3997 fpr_read_mask (const struct mips_cl_insn
*ip
)
3999 unsigned long pinfo
;
4002 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
4003 insn_read_mask (ip
->insn_mo
));
4004 pinfo
= ip
->insn_mo
->pinfo
;
4005 /* Conservatively treat all operands to an FP_D instruction are doubles.
4006 (This is overly pessimistic for things like cvt.d.s.) */
4007 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4012 /* Return the mask of floating-point registers that IP writes. */
4015 fpr_write_mask (const struct mips_cl_insn
*ip
)
4017 unsigned long pinfo
;
4020 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
4021 insn_write_mask (ip
->insn_mo
));
4022 pinfo
= ip
->insn_mo
->pinfo
;
4023 /* Conservatively treat all operands to an FP_D instruction are doubles.
4024 (This is overly pessimistic for things like cvt.s.d.) */
4025 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4030 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4031 Check whether that is allowed. */
4034 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4036 const char *s
= insn
->name
;
4038 if (insn
->pinfo
== INSN_MACRO
)
4039 /* Let a macro pass, we'll catch it later when it is expanded. */
4042 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
4044 /* Allow odd registers for single-precision ops. */
4045 switch (insn
->pinfo
& (FP_S
| FP_D
))
4056 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4057 s
= strchr (insn
->name
, '.');
4058 if (s
!= NULL
&& opnum
== 2)
4059 s
= strchr (s
+ 1, '.');
4060 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
4063 /* Single-precision coprocessor loads and moves are OK too. */
4064 if ((insn
->pinfo
& FP_S
)
4065 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
4066 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
4072 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
4073 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
4074 this operand is normally printed in hex or decimal. */
4077 report_bad_range (struct mips_cl_insn
*insn
, int argnum
,
4078 offsetT val
, int min_val
, int max_val
,
4079 bfd_boolean print_hex
)
4081 if (print_hex
&& val
>= 0)
4082 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4084 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4086 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4088 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4090 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
4092 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4095 /* Report an invalid combination of position and size operands for a bitfield
4096 operation. POS and SIZE are the values that were given. */
4099 report_bad_field (offsetT pos
, offsetT size
)
4101 as_bad (_("Invalid field specification (position %ld, size %ld)"),
4102 (unsigned long) pos
, (unsigned long) size
);
4105 /* Information about an instruction argument that we're trying to match. */
4106 struct mips_arg_info
4108 /* The instruction so far. */
4109 struct mips_cl_insn
*insn
;
4111 /* The first unconsumed operand token. */
4112 struct mips_operand_token
*token
;
4114 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4117 /* The 1-based argument number, for error reporting. This does not
4118 count elided optional registers, etc.. */
4121 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4122 unsigned int last_regno
;
4124 /* If the first operand was an OP_REG, this is the register that it
4125 specified, otherwise it is ILLEGAL_REG. */
4126 unsigned int dest_regno
;
4128 /* The value of the last OP_INT operand. Only used for OP_MSB,
4129 where it gives the lsb position. */
4130 unsigned int last_op_int
;
4132 /* If true, match routines should silently reject invalid arguments.
4133 If false, match routines can accept invalid arguments as long as
4134 they report an appropriate error. They still have the option of
4135 silently rejecting arguments, in which case a generic "Invalid operands"
4136 style of error will be used instead. */
4137 bfd_boolean soft_match
;
4139 /* If true, the OP_INT match routine should treat plain symbolic operands
4140 as if a relocation operator like %lo(...) had been used. This is only
4141 ever true if the operand can be relocated. */
4142 bfd_boolean allow_nonconst
;
4144 /* When true, the OP_INT match routine should allow unsigned N-bit
4145 arguments to be used where a signed N-bit operand is expected. */
4146 bfd_boolean lax_max
;
4148 /* True if a reference to the current AT register was seen. */
4149 bfd_boolean seen_at
;
4152 /* Try to match an OT_CHAR token for character CH. Consume the token
4153 and return true on success, otherwise return false. */
4156 match_char (struct mips_arg_info
*arg
, char ch
)
4158 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4168 /* Try to get an expression from the next tokens in ARG. Consume the
4169 tokens and return true on success, storing the expression value in
4170 VALUE and relocation types in R. */
4173 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4174 bfd_reloc_code_real_type
*r
)
4176 if (arg
->token
->type
== OT_INTEGER
)
4178 *value
= arg
->token
->u
.integer
.value
;
4179 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4184 /* Error-reporting is more consistent if we treat registers as O_register
4185 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
4186 then handled in the same way. */
4187 if (arg
->token
->type
== OT_REG
)
4189 value
->X_add_number
= arg
->token
->u
.regno
;
4192 else if (arg
->token
[0].type
== OT_CHAR
4193 && arg
->token
[0].u
.ch
== '('
4194 && arg
->token
[1].type
== OT_REG
4195 && arg
->token
[2].type
== OT_CHAR
4196 && arg
->token
[2].u
.ch
== ')')
4198 value
->X_add_number
= arg
->token
[1].u
.regno
;
4204 value
->X_op
= O_register
;
4205 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4209 /* Try to get a constant expression from the next tokens in ARG. Consume
4210 the tokens and return return true on success, storing the constant value
4211 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4215 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
, offsetT fallback
)
4218 bfd_reloc_code_real_type r
[3];
4220 if (!match_expression (arg
, &ex
, r
))
4223 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4224 *value
= ex
.X_add_number
;
4227 if (arg
->soft_match
)
4229 as_bad (_("Operand %d of `%s' must be constant"),
4230 arg
->argnum
, arg
->insn
->insn_mo
->name
);
4236 /* Return the RTYPE_* flags for a register operand of type TYPE that
4237 appears in instruction OPCODE. */
4240 convert_reg_type (const struct mips_opcode
*opcode
,
4241 enum mips_reg_operand_type type
)
4246 return RTYPE_NUM
| RTYPE_GP
;
4249 /* Allow vector register names for MDMX if the instruction is a 64-bit
4250 FPR load, store or move (including moves to and from GPRs). */
4251 if ((mips_opts
.ase
& ASE_MDMX
)
4252 && (opcode
->pinfo
& FP_D
)
4253 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4254 | INSN_COPROC_MEMORY_DELAY
4255 | INSN_LOAD_COPROC_DELAY
4256 | INSN_LOAD_MEMORY_DELAY
4257 | INSN_STORE_MEMORY
)))
4258 return RTYPE_FPU
| RTYPE_VEC
;
4262 if (opcode
->pinfo
& (FP_D
| FP_S
))
4263 return RTYPE_CCC
| RTYPE_FCC
;
4267 if (opcode
->membership
& INSN_5400
)
4269 return RTYPE_FPU
| RTYPE_VEC
;
4275 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4276 return RTYPE_NUM
| RTYPE_CP0
;
4283 return RTYPE_NUM
| RTYPE_VI
;
4286 return RTYPE_NUM
| RTYPE_VF
;
4288 case OP_REG_R5900_I
:
4289 return RTYPE_R5900_I
;
4291 case OP_REG_R5900_Q
:
4292 return RTYPE_R5900_Q
;
4294 case OP_REG_R5900_R
:
4295 return RTYPE_R5900_R
;
4297 case OP_REG_R5900_ACC
:
4298 return RTYPE_R5900_ACC
;
4303 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4306 check_regno (struct mips_arg_info
*arg
,
4307 enum mips_reg_operand_type type
, unsigned int regno
)
4309 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4310 arg
->seen_at
= TRUE
;
4312 if (type
== OP_REG_FP
4315 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4316 as_warn (_("Float register should be even, was %d"), regno
);
4318 if (type
== OP_REG_CCC
)
4323 name
= arg
->insn
->insn_mo
->name
;
4324 length
= strlen (name
);
4325 if ((regno
& 1) != 0
4326 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4327 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4328 as_warn (_("Condition code register should be even for %s, was %d"),
4331 if ((regno
& 3) != 0
4332 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4333 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4338 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4339 a register of type TYPE. Return true on success, storing the register
4340 number in *REGNO and warning about any dubious uses. */
4343 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4344 unsigned int symval
, unsigned int *regno
)
4346 if (type
== OP_REG_VEC
)
4347 symval
= mips_prefer_vec_regno (symval
);
4348 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4351 *regno
= symval
& RNUM_MASK
;
4352 check_regno (arg
, type
, *regno
);
4356 /* Try to interpret the next token in ARG as a register of type TYPE.
4357 Consume the token and return true on success, storing the register
4358 number in *REGNO. Return false on failure. */
4361 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4362 unsigned int *regno
)
4364 if (arg
->token
->type
== OT_REG
4365 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4373 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4374 Consume the token and return true on success, storing the register numbers
4375 in *REGNO1 and *REGNO2. Return false on failure. */
4378 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4379 unsigned int *regno1
, unsigned int *regno2
)
4381 if (match_reg (arg
, type
, regno1
))
4386 if (arg
->token
->type
== OT_REG_RANGE
4387 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4388 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4389 && *regno1
<= *regno2
)
4397 /* OP_INT matcher. */
4400 match_int_operand (struct mips_arg_info
*arg
,
4401 const struct mips_operand
*operand_base
)
4403 const struct mips_int_operand
*operand
;
4405 int min_val
, max_val
, factor
;
4407 bfd_boolean print_hex
;
4409 operand
= (const struct mips_int_operand
*) operand_base
;
4410 factor
= 1 << operand
->shift
;
4411 min_val
= mips_int_operand_min (operand
);
4412 max_val
= mips_int_operand_max (operand
);
4414 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
4416 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4417 /* Assume we have an elided offset. The later match will fail
4418 if this turns out to be wrong. */
4420 else if (operand_base
->lsb
== 0
4421 && operand_base
->size
== 16
4422 && operand
->shift
== 0
4423 && operand
->bias
== 0
4424 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4426 /* The operand can be relocated. */
4427 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4430 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4431 /* Relocation operators were used. Accept the arguent and
4432 leave the relocation value in offset_expr and offset_relocs
4433 for the caller to process. */
4436 if (offset_expr
.X_op
!= O_constant
)
4438 /* If non-constant operands are allowed then leave them for
4439 the caller to process, otherwise fail the match. */
4440 if (!arg
->allow_nonconst
)
4442 offset_reloc
[0] = BFD_RELOC_LO16
;
4446 /* Clear the global state; we're going to install the operand
4448 sval
= offset_expr
.X_add_number
;
4449 offset_expr
.X_op
= O_absent
;
4453 if (!match_const_int (arg
, &sval
, min_val
))
4457 arg
->last_op_int
= sval
;
4459 /* Check the range. If there's a problem, record the lowest acceptable
4460 value in arg->last_op_int in order to prevent an unhelpful error
4463 Bit counts have traditionally been printed in hex by the disassembler
4464 but printed as decimal in error messages. Only resort to hex if
4465 the operand is bigger than 6 bits. */
4466 print_hex
= operand
->print_hex
&& operand_base
->size
> 6;
4467 if (sval
< min_val
|| sval
> max_val
)
4469 if (arg
->soft_match
)
4471 report_bad_range (arg
->insn
, arg
->argnum
, sval
, min_val
, max_val
,
4473 arg
->last_op_int
= min_val
;
4475 else if (sval
% factor
)
4477 if (arg
->soft_match
)
4479 as_bad (print_hex
&& sval
>= 0
4480 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4481 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4482 arg
->argnum
, arg
->insn
->insn_mo
->name
, factor
,
4483 (unsigned long) sval
);
4484 arg
->last_op_int
= min_val
;
4487 uval
= (unsigned int) sval
>> operand
->shift
;
4488 uval
-= operand
->bias
;
4490 /* Handle -mfix-cn63xxp1. */
4492 && mips_fix_cn63xxp1
4493 && !mips_opts
.micromips
4494 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4509 /* The rest must be changed to 28. */
4514 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4518 /* OP_MAPPED_INT matcher. */
4521 match_mapped_int_operand (struct mips_arg_info
*arg
,
4522 const struct mips_operand
*operand_base
)
4524 const struct mips_mapped_int_operand
*operand
;
4525 unsigned int uval
, num_vals
;
4528 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4529 if (!match_const_int (arg
, &sval
, operand
->int_map
[0]))
4532 num_vals
= 1 << operand_base
->size
;
4533 for (uval
= 0; uval
< num_vals
; uval
++)
4534 if (operand
->int_map
[uval
] == sval
)
4536 if (uval
== num_vals
)
4539 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4543 /* OP_MSB matcher. */
4546 match_msb_operand (struct mips_arg_info
*arg
,
4547 const struct mips_operand
*operand_base
)
4549 const struct mips_msb_operand
*operand
;
4550 int min_val
, max_val
, max_high
;
4551 offsetT size
, sval
, high
;
4553 operand
= (const struct mips_msb_operand
*) operand_base
;
4554 min_val
= operand
->bias
;
4555 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4556 max_high
= operand
->opsize
;
4558 if (!match_const_int (arg
, &size
, 1))
4561 high
= size
+ arg
->last_op_int
;
4562 sval
= operand
->add_lsb
? high
: size
;
4564 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4566 if (arg
->soft_match
)
4568 report_bad_field (arg
->last_op_int
, size
);
4571 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4575 /* OP_REG matcher. */
4578 match_reg_operand (struct mips_arg_info
*arg
,
4579 const struct mips_operand
*operand_base
)
4581 const struct mips_reg_operand
*operand
;
4582 unsigned int regno
, uval
, num_vals
;
4584 operand
= (const struct mips_reg_operand
*) operand_base
;
4585 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4588 if (operand
->reg_map
)
4590 num_vals
= 1 << operand
->root
.size
;
4591 for (uval
= 0; uval
< num_vals
; uval
++)
4592 if (operand
->reg_map
[uval
] == regno
)
4594 if (num_vals
== uval
)
4600 arg
->last_regno
= regno
;
4601 if (arg
->opnum
== 1)
4602 arg
->dest_regno
= regno
;
4603 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4607 /* OP_REG_PAIR matcher. */
4610 match_reg_pair_operand (struct mips_arg_info
*arg
,
4611 const struct mips_operand
*operand_base
)
4613 const struct mips_reg_pair_operand
*operand
;
4614 unsigned int regno1
, regno2
, uval
, num_vals
;
4616 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4617 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4618 || !match_char (arg
, ',')
4619 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4622 num_vals
= 1 << operand_base
->size
;
4623 for (uval
= 0; uval
< num_vals
; uval
++)
4624 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4626 if (uval
== num_vals
)
4629 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4633 /* OP_PCREL matcher. The caller chooses the relocation type. */
4636 match_pcrel_operand (struct mips_arg_info
*arg
)
4638 bfd_reloc_code_real_type r
[3];
4640 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4643 /* OP_PERF_REG matcher. */
4646 match_perf_reg_operand (struct mips_arg_info
*arg
,
4647 const struct mips_operand
*operand
)
4651 if (!match_const_int (arg
, &sval
, 0))
4656 || (mips_opts
.arch
== CPU_R5900
4657 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4658 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4660 if (arg
->soft_match
)
4662 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval
);
4665 insn_insert_operand (arg
->insn
, operand
, sval
);
4669 /* OP_ADDIUSP matcher. */
4672 match_addiusp_operand (struct mips_arg_info
*arg
,
4673 const struct mips_operand
*operand
)
4678 if (!match_const_int (arg
, &sval
, -256))
4685 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4688 uval
= (unsigned int) sval
;
4689 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4690 insn_insert_operand (arg
->insn
, operand
, uval
);
4694 /* OP_CLO_CLZ_DEST matcher. */
4697 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4698 const struct mips_operand
*operand
)
4702 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4705 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4709 /* OP_LWM_SWM_LIST matcher. */
4712 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4713 const struct mips_operand
*operand
)
4715 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4716 struct mips_arg_info reset
;
4719 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4723 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4728 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4731 while (match_char (arg
, ',')
4732 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4735 if (operand
->size
== 2)
4737 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4743 and any permutations of these. */
4744 if ((reglist
& 0xfff1ffff) != 0x80010000)
4747 sregs
= (reglist
>> 17) & 7;
4752 /* The list must include at least one of ra and s0-sN,
4753 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4754 which are $23 and $30 respectively.) E.g.:
4762 and any permutations of these. */
4763 if ((reglist
& 0x3f00ffff) != 0)
4766 ra
= (reglist
>> 27) & 0x10;
4767 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4770 if ((sregs
& -sregs
) != sregs
)
4773 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4777 /* OP_ENTRY_EXIT_LIST matcher. */
4780 match_entry_exit_operand (struct mips_arg_info
*arg
,
4781 const struct mips_operand
*operand
)
4784 bfd_boolean is_exit
;
4786 /* The format is the same for both ENTRY and EXIT, but the constraints
4788 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4789 mask
= (is_exit
? 7 << 3 : 0);
4792 unsigned int regno1
, regno2
;
4793 bfd_boolean is_freg
;
4795 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4797 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4802 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4805 mask
|= (5 + regno2
) << 3;
4807 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4808 mask
|= (regno2
- 3) << 3;
4809 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4810 mask
|= (regno2
- 15) << 1;
4811 else if (regno1
== RA
&& regno2
== RA
)
4816 while (match_char (arg
, ','));
4818 insn_insert_operand (arg
->insn
, operand
, mask
);
4822 /* OP_SAVE_RESTORE_LIST matcher. */
4825 match_save_restore_list_operand (struct mips_arg_info
*arg
)
4827 unsigned int opcode
, args
, statics
, sregs
;
4828 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
4833 opcode
= arg
->insn
->insn_opcode
;
4835 num_frame_sizes
= 0;
4841 unsigned int regno1
, regno2
;
4843 if (arg
->token
->type
== OT_INTEGER
)
4845 /* Handle the frame size. */
4846 if (!match_const_int (arg
, &frame_size
, 0))
4848 num_frame_sizes
+= 1;
4852 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4855 while (regno1
<= regno2
)
4857 if (regno1
>= 4 && regno1
<= 7)
4859 if (num_frame_sizes
== 0)
4861 args
|= 1 << (regno1
- 4);
4863 /* statics $a0-$a3 */
4864 statics
|= 1 << (regno1
- 4);
4866 else if (regno1
>= 16 && regno1
<= 23)
4868 sregs
|= 1 << (regno1
- 16);
4869 else if (regno1
== 30)
4872 else if (regno1
== 31)
4873 /* Add $ra to insn. */
4883 while (match_char (arg
, ','));
4885 /* Encode args/statics combination. */
4888 else if (args
== 0xf)
4889 /* All $a0-$a3 are args. */
4890 opcode
|= MIPS16_ALL_ARGS
<< 16;
4891 else if (statics
== 0xf)
4892 /* All $a0-$a3 are statics. */
4893 opcode
|= MIPS16_ALL_STATICS
<< 16;
4896 /* Count arg registers. */
4906 /* Count static registers. */
4908 while (statics
& 0x8)
4910 statics
= (statics
<< 1) & 0xf;
4916 /* Encode args/statics. */
4917 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
4920 /* Encode $s0/$s1. */
4921 if (sregs
& (1 << 0)) /* $s0 */
4923 if (sregs
& (1 << 1)) /* $s1 */
4927 /* Encode $s2-$s8. */
4936 opcode
|= num_sregs
<< 24;
4938 /* Encode frame size. */
4939 if (num_frame_sizes
== 0)
4940 error
= _("Missing frame size");
4941 else if (num_frame_sizes
> 1)
4942 error
= _("Frame size specified twice");
4943 else if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
4944 error
= _("Invalid frame size");
4945 else if (frame_size
!= 128 || (opcode
>> 16) != 0)
4948 opcode
|= (((frame_size
& 0xf0) << 16)
4949 | (frame_size
& 0x0f));
4954 if (arg
->soft_match
)
4956 as_bad ("%s", error
);
4959 /* Finally build the instruction. */
4960 if ((opcode
>> 16) != 0 || frame_size
== 0)
4961 opcode
|= MIPS16_EXTEND
;
4962 arg
->insn
->insn_opcode
= opcode
;
4966 /* OP_MDMX_IMM_REG matcher. */
4969 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
4970 const struct mips_operand
*operand
)
4972 unsigned int regno
, uval
;
4974 const struct mips_opcode
*opcode
;
4976 /* The mips_opcode records whether this is an octobyte or quadhalf
4977 instruction. Start out with that bit in place. */
4978 opcode
= arg
->insn
->insn_mo
;
4979 uval
= mips_extract_operand (operand
, opcode
->match
);
4980 is_qh
= (uval
!= 0);
4982 if (arg
->token
->type
== OT_REG
|| arg
->token
->type
== OT_REG_ELEMENT
)
4984 if ((opcode
->membership
& INSN_5400
)
4985 && strcmp (opcode
->name
, "rzu.ob") == 0)
4987 if (arg
->soft_match
)
4989 as_bad (_("Operand %d of `%s' must be an immediate"),
4990 arg
->argnum
, opcode
->name
);
4993 /* Check whether this is a vector register or a broadcast of
4994 a single element. */
4995 if (arg
->token
->type
== OT_REG_ELEMENT
)
4997 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.reg_element
.regno
,
5000 if (arg
->token
->u
.reg_element
.index
> (is_qh
? 3 : 7))
5002 if (arg
->soft_match
)
5004 as_bad (_("Invalid element selector"));
5007 uval
|= arg
->token
->u
.reg_element
.index
<< (is_qh
? 2 : 1) << 5;
5011 /* A full vector. */
5012 if ((opcode
->membership
& INSN_5400
)
5013 && (strcmp (opcode
->name
, "sll.ob") == 0
5014 || strcmp (opcode
->name
, "srl.ob") == 0))
5016 if (arg
->soft_match
)
5018 as_bad (_("Operand %d of `%s' must be scalar"),
5019 arg
->argnum
, opcode
->name
);
5022 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5025 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5027 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5036 if (!match_const_int (arg
, &sval
, 0))
5038 if (sval
< 0 || sval
> 31)
5040 if (arg
->soft_match
)
5042 report_bad_range (arg
->insn
, arg
->argnum
, sval
, 0, 31, FALSE
);
5044 uval
|= (sval
& 31);
5046 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5048 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5050 insn_insert_operand (arg
->insn
, operand
, uval
);
5054 /* OP_PC matcher. */
5057 match_pc_operand (struct mips_arg_info
*arg
)
5059 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5067 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5068 register that we need to match. */
5071 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5075 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5078 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5079 the length of the value in bytes (4 for float, 8 for double) and
5080 USING_GPRS says whether the destination is a GPR rather than an FPR.
5082 Return the constant in IMM and OFFSET as follows:
5084 - If the constant should be loaded via memory, set IMM to O_absent and
5085 OFFSET to the memory address.
5087 - Otherwise, if the constant should be loaded into two 32-bit registers,
5088 set IMM to the O_constant to load into the high register and OFFSET
5089 to the corresponding value for the low register.
5091 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5093 These constants only appear as the last operand in an instruction,
5094 and every instruction that accepts them in any variant accepts them
5095 in all variants. This means we don't have to worry about backing out
5096 any changes if the instruction does not match. We just match
5097 unconditionally and report an error if the constant is invalid. */
5100 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5101 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5106 const char *newname
;
5107 unsigned char *data
;
5109 /* Where the constant is placed is based on how the MIPS assembler
5112 length == 4 && using_gprs -- immediate value only
5113 length == 8 && using_gprs -- .rdata or immediate value
5114 length == 4 && !using_gprs -- .lit4 or immediate value
5115 length == 8 && !using_gprs -- .lit8 or immediate value
5117 The .lit4 and .lit8 sections are only used if permitted by the
5119 if (arg
->token
->type
!= OT_FLOAT
)
5122 gas_assert (arg
->token
->u
.flt
.length
== length
);
5123 data
= arg
->token
->u
.flt
.data
;
5126 /* Handle 32-bit constants for which an immediate value is best. */
5129 || g_switch_value
< 4
5130 || (data
[0] == 0 && data
[1] == 0)
5131 || (data
[2] == 0 && data
[3] == 0)))
5133 imm
->X_op
= O_constant
;
5134 if (!target_big_endian
)
5135 imm
->X_add_number
= bfd_getl32 (data
);
5137 imm
->X_add_number
= bfd_getb32 (data
);
5138 offset
->X_op
= O_absent
;
5142 /* Handle 64-bit constants for which an immediate value is best. */
5144 && !mips_disable_float_construction
5145 /* Constants can only be constructed in GPRs and copied
5146 to FPRs if the GPRs are at least as wide as the FPRs.
5147 Force the constant into memory if we are using 64-bit FPRs
5148 but the GPRs are only 32 bits wide. */
5149 /* ??? No longer true with the addition of MTHC1, but this
5150 is legacy code... */
5151 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
5152 && ((data
[0] == 0 && data
[1] == 0)
5153 || (data
[2] == 0 && data
[3] == 0))
5154 && ((data
[4] == 0 && data
[5] == 0)
5155 || (data
[6] == 0 && data
[7] == 0)))
5157 /* The value is simple enough to load with a couple of instructions.
5158 If using 32-bit registers, set IMM to the high order 32 bits and
5159 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5161 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
5163 imm
->X_op
= O_constant
;
5164 offset
->X_op
= O_constant
;
5165 if (!target_big_endian
)
5167 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5168 offset
->X_add_number
= bfd_getl32 (data
);
5172 imm
->X_add_number
= bfd_getb32 (data
);
5173 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5175 if (offset
->X_add_number
== 0)
5176 offset
->X_op
= O_absent
;
5180 imm
->X_op
= O_constant
;
5181 if (!target_big_endian
)
5182 imm
->X_add_number
= bfd_getl64 (data
);
5184 imm
->X_add_number
= bfd_getb64 (data
);
5185 offset
->X_op
= O_absent
;
5190 /* Switch to the right section. */
5192 subseg
= now_subseg
;
5195 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5200 if (using_gprs
|| g_switch_value
< 8)
5201 newname
= RDATA_SECTION_NAME
;
5206 new_seg
= subseg_new (newname
, (subsegT
) 0);
5207 bfd_set_section_flags (stdoutput
, new_seg
,
5208 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5209 frag_align (length
== 4 ? 2 : 3, 0, 0);
5210 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5211 record_alignment (new_seg
, 4);
5213 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5215 as_bad (_("Can't use floating point insn in this section"));
5217 /* Set the argument to the current address in the section. */
5218 imm
->X_op
= O_absent
;
5219 offset
->X_op
= O_symbol
;
5220 offset
->X_add_symbol
= symbol_temp_new_now ();
5221 offset
->X_add_number
= 0;
5223 /* Put the floating point number into the section. */
5224 p
= frag_more (length
);
5225 memcpy (p
, data
, length
);
5227 /* Switch back to the original section. */
5228 subseg_set (seg
, subseg
);
5232 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5236 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5237 const struct mips_operand
*operand
,
5238 bfd_boolean match_p
)
5242 /* The operand can be an XYZW mask or a single 2-bit channel index
5243 (with X being 0). */
5244 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5246 /* The suffix can be omitted when it is already part of the opcode. */
5247 if (arg
->token
->type
!= OT_CHANNELS
)
5250 uval
= arg
->token
->u
.channels
;
5251 if (operand
->size
== 2)
5253 /* Check that a single bit is set and convert it into a 2-bit index. */
5254 if ((uval
& -uval
) != uval
)
5256 uval
= 4 - ffs (uval
);
5259 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5264 insn_insert_operand (arg
->insn
, operand
, uval
);
5268 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5269 of the argument text if the match is successful, otherwise return null. */
5272 match_operand (struct mips_arg_info
*arg
,
5273 const struct mips_operand
*operand
)
5275 switch (operand
->type
)
5278 return match_int_operand (arg
, operand
);
5281 return match_mapped_int_operand (arg
, operand
);
5284 return match_msb_operand (arg
, operand
);
5287 case OP_OPTIONAL_REG
:
5288 return match_reg_operand (arg
, operand
);
5291 return match_reg_pair_operand (arg
, operand
);
5294 return match_pcrel_operand (arg
);
5297 return match_perf_reg_operand (arg
, operand
);
5299 case OP_ADDIUSP_INT
:
5300 return match_addiusp_operand (arg
, operand
);
5302 case OP_CLO_CLZ_DEST
:
5303 return match_clo_clz_dest_operand (arg
, operand
);
5305 case OP_LWM_SWM_LIST
:
5306 return match_lwm_swm_list_operand (arg
, operand
);
5308 case OP_ENTRY_EXIT_LIST
:
5309 return match_entry_exit_operand (arg
, operand
);
5311 case OP_SAVE_RESTORE_LIST
:
5312 return match_save_restore_list_operand (arg
);
5314 case OP_MDMX_IMM_REG
:
5315 return match_mdmx_imm_reg_operand (arg
, operand
);
5317 case OP_REPEAT_DEST_REG
:
5318 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5320 case OP_REPEAT_PREV_REG
:
5321 return match_tied_reg_operand (arg
, arg
->last_regno
);
5324 return match_pc_operand (arg
);
5327 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5329 case OP_VU0_MATCH_SUFFIX
:
5330 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5335 /* ARG is the state after successfully matching an instruction.
5336 Issue any queued-up warnings. */
5339 check_completed_insn (struct mips_arg_info
*arg
)
5344 as_warn (_("Used $at without \".set noat\""));
5346 as_warn (_("Used $%u with \".set at=$%u\""), AT
, AT
);
5350 /* Return true if modifying general-purpose register REG needs a delay. */
5353 reg_needs_delay (unsigned int reg
)
5355 unsigned long prev_pinfo
;
5357 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5358 if (!mips_opts
.noreorder
5359 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
) && !gpr_interlocks
)
5360 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5361 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5367 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5368 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5369 by VR4120 errata. */
5372 classify_vr4120_insn (const char *name
)
5374 if (strncmp (name
, "macc", 4) == 0)
5375 return FIX_VR4120_MACC
;
5376 if (strncmp (name
, "dmacc", 5) == 0)
5377 return FIX_VR4120_DMACC
;
5378 if (strncmp (name
, "mult", 4) == 0)
5379 return FIX_VR4120_MULT
;
5380 if (strncmp (name
, "dmult", 5) == 0)
5381 return FIX_VR4120_DMULT
;
5382 if (strstr (name
, "div"))
5383 return FIX_VR4120_DIV
;
5384 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5385 return FIX_VR4120_MTHILO
;
5386 return NUM_FIX_VR4120_CLASSES
;
5389 #define INSN_ERET 0x42000018
5390 #define INSN_DERET 0x4200001f
5392 /* Return the number of instructions that must separate INSN1 and INSN2,
5393 where INSN1 is the earlier instruction. Return the worst-case value
5394 for any INSN2 if INSN2 is null. */
5397 insns_between (const struct mips_cl_insn
*insn1
,
5398 const struct mips_cl_insn
*insn2
)
5400 unsigned long pinfo1
, pinfo2
;
5403 /* If INFO2 is null, pessimistically assume that all flags are set for
5404 the second instruction. */
5405 pinfo1
= insn1
->insn_mo
->pinfo
;
5406 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5408 /* For most targets, write-after-read dependencies on the HI and LO
5409 registers must be separated by at least two instructions. */
5410 if (!hilo_interlocks
)
5412 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5414 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5418 /* If we're working around r7000 errata, there must be two instructions
5419 between an mfhi or mflo and any instruction that uses the result. */
5420 if (mips_7000_hilo_fix
5421 && !mips_opts
.micromips
5422 && MF_HILO_INSN (pinfo1
)
5423 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5426 /* If we're working around 24K errata, one instruction is required
5427 if an ERET or DERET is followed by a branch instruction. */
5428 if (mips_fix_24k
&& !mips_opts
.micromips
)
5430 if (insn1
->insn_opcode
== INSN_ERET
5431 || insn1
->insn_opcode
== INSN_DERET
)
5434 || insn2
->insn_opcode
== INSN_ERET
5435 || insn2
->insn_opcode
== INSN_DERET
5436 || delayed_branch_p (insn2
))
5441 /* If working around VR4120 errata, check for combinations that need
5442 a single intervening instruction. */
5443 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5445 unsigned int class1
, class2
;
5447 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5448 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5452 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5453 if (vr4120_conflicts
[class1
] & (1 << class2
))
5458 if (!HAVE_CODE_COMPRESSION
)
5460 /* Check for GPR or coprocessor load delays. All such delays
5461 are on the RT register. */
5462 /* Itbl support may require additional care here. */
5463 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
5464 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5466 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5470 /* Check for generic coprocessor hazards.
5472 This case is not handled very well. There is no special
5473 knowledge of CP0 handling, and the coprocessors other than
5474 the floating point unit are not distinguished at all. */
5475 /* Itbl support may require additional care here. FIXME!
5476 Need to modify this to include knowledge about
5477 user specified delays! */
5478 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5479 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5481 /* Handle cases where INSN1 writes to a known general coprocessor
5482 register. There must be a one instruction delay before INSN2
5483 if INSN2 reads that register, otherwise no delay is needed. */
5484 mask
= fpr_write_mask (insn1
);
5487 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5492 /* Read-after-write dependencies on the control registers
5493 require a two-instruction gap. */
5494 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5495 && (pinfo2
& INSN_READ_COND_CODE
))
5498 /* We don't know exactly what INSN1 does. If INSN2 is
5499 also a coprocessor instruction, assume there must be
5500 a one instruction gap. */
5501 if (pinfo2
& INSN_COP
)
5506 /* Check for read-after-write dependencies on the coprocessor
5507 control registers in cases where INSN1 does not need a general
5508 coprocessor delay. This means that INSN1 is a floating point
5509 comparison instruction. */
5510 /* Itbl support may require additional care here. */
5511 else if (!cop_interlocks
5512 && (pinfo1
& INSN_WRITE_COND_CODE
)
5513 && (pinfo2
& INSN_READ_COND_CODE
))
5520 /* Return the number of nops that would be needed to work around the
5521 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5522 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5523 that are contained within the first IGNORE instructions of HIST. */
5526 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5527 const struct mips_cl_insn
*insn
)
5532 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5533 are not affected by the errata. */
5535 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5536 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5537 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5540 /* Search for the first MFLO or MFHI. */
5541 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5542 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5544 /* Extract the destination register. */
5545 mask
= gpr_write_mask (&hist
[i
]);
5547 /* No nops are needed if INSN reads that register. */
5548 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5551 /* ...or if any of the intervening instructions do. */
5552 for (j
= 0; j
< i
; j
++)
5553 if (gpr_read_mask (&hist
[j
]) & mask
)
5557 return MAX_VR4130_NOPS
- i
;
5562 #define BASE_REG_EQ(INSN1, INSN2) \
5563 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5564 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5566 /* Return the minimum alignment for this store instruction. */
5569 fix_24k_align_to (const struct mips_opcode
*mo
)
5571 if (strcmp (mo
->name
, "sh") == 0)
5574 if (strcmp (mo
->name
, "swc1") == 0
5575 || strcmp (mo
->name
, "swc2") == 0
5576 || strcmp (mo
->name
, "sw") == 0
5577 || strcmp (mo
->name
, "sc") == 0
5578 || strcmp (mo
->name
, "s.s") == 0)
5581 if (strcmp (mo
->name
, "sdc1") == 0
5582 || strcmp (mo
->name
, "sdc2") == 0
5583 || strcmp (mo
->name
, "s.d") == 0)
5590 struct fix_24k_store_info
5592 /* Immediate offset, if any, for this store instruction. */
5594 /* Alignment required by this store instruction. */
5596 /* True for register offsets. */
5597 int register_offset
;
5600 /* Comparison function used by qsort. */
5603 fix_24k_sort (const void *a
, const void *b
)
5605 const struct fix_24k_store_info
*pos1
= a
;
5606 const struct fix_24k_store_info
*pos2
= b
;
5608 return (pos1
->off
- pos2
->off
);
5611 /* INSN is a store instruction. Try to record the store information
5612 in STINFO. Return false if the information isn't known. */
5615 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5616 const struct mips_cl_insn
*insn
)
5618 /* The instruction must have a known offset. */
5619 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5622 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5623 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5627 /* Return the number of nops that would be needed to work around the 24k
5628 "lost data on stores during refill" errata if instruction INSN
5629 immediately followed the 2 instructions described by HIST.
5630 Ignore hazards that are contained within the first IGNORE
5631 instructions of HIST.
5633 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5634 for the data cache refills and store data. The following describes
5635 the scenario where the store data could be lost.
5637 * A data cache miss, due to either a load or a store, causing fill
5638 data to be supplied by the memory subsystem
5639 * The first three doublewords of fill data are returned and written
5641 * A sequence of four stores occurs in consecutive cycles around the
5642 final doubleword of the fill:
5646 * Zero, One or more instructions
5649 The four stores A-D must be to different doublewords of the line that
5650 is being filled. The fourth instruction in the sequence above permits
5651 the fill of the final doubleword to be transferred from the FSB into
5652 the cache. In the sequence above, the stores may be either integer
5653 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5654 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5655 different doublewords on the line. If the floating point unit is
5656 running in 1:2 mode, it is not possible to create the sequence above
5657 using only floating point store instructions.
5659 In this case, the cache line being filled is incorrectly marked
5660 invalid, thereby losing the data from any store to the line that
5661 occurs between the original miss and the completion of the five
5662 cycle sequence shown above.
5664 The workarounds are:
5666 * Run the data cache in write-through mode.
5667 * Insert a non-store instruction between
5668 Store A and Store B or Store B and Store C. */
5671 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5672 const struct mips_cl_insn
*insn
)
5674 struct fix_24k_store_info pos
[3];
5675 int align
, i
, base_offset
;
5680 /* If the previous instruction wasn't a store, there's nothing to
5682 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5685 /* If the instructions after the previous one are unknown, we have
5686 to assume the worst. */
5690 /* Check whether we are dealing with three consecutive stores. */
5691 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5692 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5695 /* If we don't know the relationship between the store addresses,
5696 assume the worst. */
5697 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5698 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5701 if (!fix_24k_record_store_info (&pos
[0], insn
)
5702 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5703 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5706 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5708 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5709 X bytes and such that the base register + X is known to be aligned
5712 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5716 align
= pos
[0].align_to
;
5717 base_offset
= pos
[0].off
;
5718 for (i
= 1; i
< 3; i
++)
5719 if (align
< pos
[i
].align_to
)
5721 align
= pos
[i
].align_to
;
5722 base_offset
= pos
[i
].off
;
5724 for (i
= 0; i
< 3; i
++)
5725 pos
[i
].off
-= base_offset
;
5728 pos
[0].off
&= ~align
+ 1;
5729 pos
[1].off
&= ~align
+ 1;
5730 pos
[2].off
&= ~align
+ 1;
5732 /* If any two stores write to the same chunk, they also write to the
5733 same doubleword. The offsets are still sorted at this point. */
5734 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5737 /* A range of at least 9 bytes is needed for the stores to be in
5738 non-overlapping doublewords. */
5739 if (pos
[2].off
- pos
[0].off
<= 8)
5742 if (pos
[2].off
- pos
[1].off
>= 24
5743 || pos
[1].off
- pos
[0].off
>= 24
5744 || pos
[2].off
- pos
[0].off
>= 32)
5750 /* Return the number of nops that would be needed if instruction INSN
5751 immediately followed the MAX_NOPS instructions given by HIST,
5752 where HIST[0] is the most recent instruction. Ignore hazards
5753 between INSN and the first IGNORE instructions in HIST.
5755 If INSN is null, return the worse-case number of nops for any
5759 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
5760 const struct mips_cl_insn
*insn
)
5762 int i
, nops
, tmp_nops
;
5765 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
5767 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
5768 if (tmp_nops
> nops
)
5772 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
5774 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
5775 if (tmp_nops
> nops
)
5779 if (mips_fix_24k
&& !mips_opts
.micromips
)
5781 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
5782 if (tmp_nops
> nops
)
5789 /* The variable arguments provide NUM_INSNS extra instructions that
5790 might be added to HIST. Return the largest number of nops that
5791 would be needed after the extended sequence, ignoring hazards
5792 in the first IGNORE instructions. */
5795 nops_for_sequence (int num_insns
, int ignore
,
5796 const struct mips_cl_insn
*hist
, ...)
5799 struct mips_cl_insn buffer
[MAX_NOPS
];
5800 struct mips_cl_insn
*cursor
;
5803 va_start (args
, hist
);
5804 cursor
= buffer
+ num_insns
;
5805 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
5806 while (cursor
> buffer
)
5807 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
5809 nops
= nops_for_insn (ignore
, buffer
, NULL
);
5814 /* Like nops_for_insn, but if INSN is a branch, take into account the
5815 worst-case delay for the branch target. */
5818 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
5819 const struct mips_cl_insn
*insn
)
5823 nops
= nops_for_insn (ignore
, hist
, insn
);
5824 if (delayed_branch_p (insn
))
5826 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
5827 hist
, insn
, get_delay_slot_nop (insn
));
5828 if (tmp_nops
> nops
)
5831 else if (compact_branch_p (insn
))
5833 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
5834 if (tmp_nops
> nops
)
5840 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5843 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
5845 gas_assert (!HAVE_CODE_COMPRESSION
);
5846 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
5847 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
5850 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5851 jr target pc &= 'hffff_ffff_cfff_ffff. */
5854 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
5856 gas_assert (!HAVE_CODE_COMPRESSION
);
5857 if (strcmp (ip
->insn_mo
->name
, "j") == 0
5858 || strcmp (ip
->insn_mo
->name
, "jr") == 0
5859 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
5867 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
5868 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
5871 ep
.X_op
= O_constant
;
5872 ep
.X_add_number
= 0xcfff0000;
5873 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
5874 ep
.X_add_number
= 0xffff;
5875 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
5876 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
5881 fix_loongson2f (struct mips_cl_insn
* ip
)
5883 if (mips_fix_loongson2f_nop
)
5884 fix_loongson2f_nop (ip
);
5886 if (mips_fix_loongson2f_jump
)
5887 fix_loongson2f_jump (ip
);
5890 /* IP is a branch that has a delay slot, and we need to fill it
5891 automatically. Return true if we can do that by swapping IP
5892 with the previous instruction.
5893 ADDRESS_EXPR is an operand of the instruction to be used with
5897 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5898 bfd_reloc_code_real_type
*reloc_type
)
5900 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
5901 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
5903 /* -O2 and above is required for this optimization. */
5904 if (mips_optimize
< 2)
5907 /* If we have seen .set volatile or .set nomove, don't optimize. */
5908 if (mips_opts
.nomove
)
5911 /* We can't swap if the previous instruction's position is fixed. */
5912 if (history
[0].fixed_p
)
5915 /* If the previous previous insn was in a .set noreorder, we can't
5916 swap. Actually, the MIPS assembler will swap in this situation.
5917 However, gcc configured -with-gnu-as will generate code like
5925 in which we can not swap the bne and INSN. If gcc is not configured
5926 -with-gnu-as, it does not output the .set pseudo-ops. */
5927 if (history
[1].noreorder_p
)
5930 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5931 This means that the previous instruction was a 4-byte one anyhow. */
5932 if (mips_opts
.mips16
&& history
[0].fixp
[0])
5935 /* If the branch is itself the target of a branch, we can not swap.
5936 We cheat on this; all we check for is whether there is a label on
5937 this instruction. If there are any branches to anything other than
5938 a label, users must use .set noreorder. */
5939 if (seg_info (now_seg
)->label_list
)
5942 /* If the previous instruction is in a variant frag other than this
5943 branch's one, we cannot do the swap. This does not apply to
5944 MIPS16 code, which uses variant frags for different purposes. */
5945 if (!mips_opts
.mips16
5947 && history
[0].frag
->fr_type
== rs_machine_dependent
)
5950 /* We do not swap with instructions that cannot architecturally
5951 be placed in a branch delay slot, such as SYNC or ERET. We
5952 also refrain from swapping with a trap instruction, since it
5953 complicates trap handlers to have the trap instruction be in
5955 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5956 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
5959 /* Check for conflicts between the branch and the instructions
5960 before the candidate delay slot. */
5961 if (nops_for_insn (0, history
+ 1, ip
) > 0)
5964 /* Check for conflicts between the swapped sequence and the
5965 target of the branch. */
5966 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
5969 /* If the branch reads a register that the previous
5970 instruction sets, we can not swap. */
5971 gpr_read
= gpr_read_mask (ip
);
5972 prev_gpr_write
= gpr_write_mask (&history
[0]);
5973 if (gpr_read
& prev_gpr_write
)
5976 /* If the branch writes a register that the previous
5977 instruction sets, we can not swap. */
5978 gpr_write
= gpr_write_mask (ip
);
5979 if (gpr_write
& prev_gpr_write
)
5982 /* If the branch writes a register that the previous
5983 instruction reads, we can not swap. */
5984 prev_gpr_read
= gpr_read_mask (&history
[0]);
5985 if (gpr_write
& prev_gpr_read
)
5988 /* If one instruction sets a condition code and the
5989 other one uses a condition code, we can not swap. */
5990 pinfo
= ip
->insn_mo
->pinfo
;
5991 if ((pinfo
& INSN_READ_COND_CODE
)
5992 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
5994 if ((pinfo
& INSN_WRITE_COND_CODE
)
5995 && (prev_pinfo
& INSN_READ_COND_CODE
))
5998 /* If the previous instruction uses the PC, we can not swap. */
5999 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6000 if (prev_pinfo2
& INSN2_READ_PC
)
6003 /* If the previous instruction has an incorrect size for a fixed
6004 branch delay slot in microMIPS mode, we cannot swap. */
6005 pinfo2
= ip
->insn_mo
->pinfo2
;
6006 if (mips_opts
.micromips
6007 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6008 && insn_length (history
) != 2)
6010 if (mips_opts
.micromips
6011 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6012 && insn_length (history
) != 4)
6015 /* On R5900 short loops need to be fixed by inserting a nop in
6016 the branch delay slots.
6017 A short loop can be terminated too early. */
6018 if (mips_opts
.arch
== CPU_R5900
6019 /* Check if instruction has a parameter, ignore "j $31". */
6020 && (address_expr
!= NULL
)
6021 /* Parameter must be 16 bit. */
6022 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6023 /* Branch to same segment. */
6024 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6025 /* Branch to same code fragment. */
6026 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6027 /* Can only calculate branch offset if value is known. */
6028 && symbol_constant_p(address_expr
->X_add_symbol
)
6029 /* Check if branch is really conditional. */
6030 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6031 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6032 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6035 /* Check if loop is shorter than 6 instructions including
6036 branch and delay slot. */
6037 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6044 /* When the loop includes branches or jumps,
6045 it is not a short loop. */
6046 for (i
= 0; i
< (distance
/ 4); i
++)
6048 if ((history
[i
].cleared_p
)
6049 || delayed_branch_p(&history
[i
]))
6057 /* Insert nop after branch to fix short loop. */
6066 /* Decide how we should add IP to the instruction stream.
6067 ADDRESS_EXPR is an operand of the instruction to be used with
6070 static enum append_method
6071 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6072 bfd_reloc_code_real_type
*reloc_type
)
6074 /* The relaxed version of a macro sequence must be inherently
6076 if (mips_relax
.sequence
== 2)
6079 /* We must not dabble with instructions in a ".set norerorder" block. */
6080 if (mips_opts
.noreorder
)
6083 /* Otherwise, it's our responsibility to fill branch delay slots. */
6084 if (delayed_branch_p (ip
))
6086 if (!branch_likely_p (ip
)
6087 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6090 if (mips_opts
.mips16
6091 && ISA_SUPPORTS_MIPS16E
6092 && gpr_read_mask (ip
) != 0)
6093 return APPEND_ADD_COMPACT
;
6095 return APPEND_ADD_WITH_NOP
;
6101 /* IP is a MIPS16 instruction whose opcode we have just changed.
6102 Point IP->insn_mo to the new opcode's definition. */
6105 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6107 const struct mips_opcode
*mo
, *end
;
6109 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6110 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6111 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6119 /* For microMIPS macros, we need to generate a local number label
6120 as the target of branches. */
6121 #define MICROMIPS_LABEL_CHAR '\037'
6122 static unsigned long micromips_target_label
;
6123 static char micromips_target_name
[32];
6126 micromips_label_name (void)
6128 char *p
= micromips_target_name
;
6129 char symbol_name_temporary
[24];
6137 l
= micromips_target_label
;
6138 #ifdef LOCAL_LABEL_PREFIX
6139 *p
++ = LOCAL_LABEL_PREFIX
;
6142 *p
++ = MICROMIPS_LABEL_CHAR
;
6145 symbol_name_temporary
[i
++] = l
% 10 + '0';
6150 *p
++ = symbol_name_temporary
[--i
];
6153 return micromips_target_name
;
6157 micromips_label_expr (expressionS
*label_expr
)
6159 label_expr
->X_op
= O_symbol
;
6160 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6161 label_expr
->X_add_number
= 0;
6165 micromips_label_inc (void)
6167 micromips_target_label
++;
6168 *micromips_target_name
= '\0';
6172 micromips_add_label (void)
6176 s
= colon (micromips_label_name ());
6177 micromips_label_inc ();
6178 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6181 /* If assembling microMIPS code, then return the microMIPS reloc
6182 corresponding to the requested one if any. Otherwise return
6183 the reloc unchanged. */
6185 static bfd_reloc_code_real_type
6186 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6188 static const bfd_reloc_code_real_type relocs
[][2] =
6190 /* Keep sorted incrementally by the left-hand key. */
6191 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6192 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6193 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6194 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6195 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6196 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6197 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6198 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6199 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6200 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6201 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6202 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6203 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6204 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6205 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6206 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6207 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6208 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6209 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6210 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6211 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6212 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6213 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6214 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6215 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6216 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6217 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6219 bfd_reloc_code_real_type r
;
6222 if (!mips_opts
.micromips
)
6224 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6230 return relocs
[i
][1];
6235 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6236 Return true on success, storing the resolved value in RESULT. */
6239 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6244 case BFD_RELOC_MIPS_HIGHEST
:
6245 case BFD_RELOC_MICROMIPS_HIGHEST
:
6246 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6249 case BFD_RELOC_MIPS_HIGHER
:
6250 case BFD_RELOC_MICROMIPS_HIGHER
:
6251 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6254 case BFD_RELOC_HI16_S
:
6255 case BFD_RELOC_MICROMIPS_HI16_S
:
6256 case BFD_RELOC_MIPS16_HI16_S
:
6257 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6260 case BFD_RELOC_HI16
:
6261 case BFD_RELOC_MICROMIPS_HI16
:
6262 case BFD_RELOC_MIPS16_HI16
:
6263 *result
= (operand
>> 16) & 0xffff;
6266 case BFD_RELOC_LO16
:
6267 case BFD_RELOC_MICROMIPS_LO16
:
6268 case BFD_RELOC_MIPS16_LO16
:
6269 *result
= operand
& 0xffff;
6272 case BFD_RELOC_UNUSED
:
6281 /* Output an instruction. IP is the instruction information.
6282 ADDRESS_EXPR is an operand of the instruction to be used with
6283 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6284 a macro expansion. */
6287 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6288 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6290 unsigned long prev_pinfo2
, pinfo
;
6291 bfd_boolean relaxed_branch
= FALSE
;
6292 enum append_method method
;
6293 bfd_boolean relax32
;
6296 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6297 fix_loongson2f (ip
);
6299 file_ase_mips16
|= mips_opts
.mips16
;
6300 file_ase_micromips
|= mips_opts
.micromips
;
6302 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6303 pinfo
= ip
->insn_mo
->pinfo
;
6305 if (mips_opts
.micromips
6307 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6308 && micromips_insn_length (ip
->insn_mo
) != 2)
6309 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6310 && micromips_insn_length (ip
->insn_mo
) != 4)))
6311 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6312 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6314 if (address_expr
== NULL
)
6316 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6317 && reloc_type
[1] == BFD_RELOC_UNUSED
6318 && reloc_type
[2] == BFD_RELOC_UNUSED
6319 && address_expr
->X_op
== O_constant
)
6321 switch (*reloc_type
)
6323 case BFD_RELOC_MIPS_JMP
:
6327 shift
= mips_opts
.micromips
? 1 : 2;
6328 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6329 as_bad (_("jump to misaligned address (0x%lx)"),
6330 (unsigned long) address_expr
->X_add_number
);
6331 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6337 case BFD_RELOC_MIPS16_JMP
:
6338 if ((address_expr
->X_add_number
& 3) != 0)
6339 as_bad (_("jump to misaligned address (0x%lx)"),
6340 (unsigned long) address_expr
->X_add_number
);
6342 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6343 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6344 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6348 case BFD_RELOC_16_PCREL_S2
:
6352 shift
= mips_opts
.micromips
? 1 : 2;
6353 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6354 as_bad (_("branch to misaligned address (0x%lx)"),
6355 (unsigned long) address_expr
->X_add_number
);
6356 if (!mips_relax_branch
)
6358 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6359 & ~((1 << (shift
+ 16)) - 1))
6360 as_bad (_("branch address range overflow (0x%lx)"),
6361 (unsigned long) address_expr
->X_add_number
);
6362 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6372 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6375 ip
->insn_opcode
|= value
& 0xffff;
6383 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6385 /* There are a lot of optimizations we could do that we don't.
6386 In particular, we do not, in general, reorder instructions.
6387 If you use gcc with optimization, it will reorder
6388 instructions and generally do much more optimization then we
6389 do here; repeating all that work in the assembler would only
6390 benefit hand written assembly code, and does not seem worth
6392 int nops
= (mips_optimize
== 0
6393 ? nops_for_insn (0, history
, NULL
)
6394 : nops_for_insn_or_target (0, history
, ip
));
6398 unsigned long old_frag_offset
;
6401 old_frag
= frag_now
;
6402 old_frag_offset
= frag_now_fix ();
6404 for (i
= 0; i
< nops
; i
++)
6405 add_fixed_insn (NOP_INSN
);
6406 insert_into_history (0, nops
, NOP_INSN
);
6410 listing_prev_line ();
6411 /* We may be at the start of a variant frag. In case we
6412 are, make sure there is enough space for the frag
6413 after the frags created by listing_prev_line. The
6414 argument to frag_grow here must be at least as large
6415 as the argument to all other calls to frag_grow in
6416 this file. We don't have to worry about being in the
6417 middle of a variant frag, because the variants insert
6418 all needed nop instructions themselves. */
6422 mips_move_text_labels ();
6424 #ifndef NO_ECOFF_DEBUGGING
6425 if (ECOFF_DEBUGGING
)
6426 ecoff_fix_loc (old_frag
, old_frag_offset
);
6430 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6434 /* Work out how many nops in prev_nop_frag are needed by IP,
6435 ignoring hazards generated by the first prev_nop_frag_since
6437 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6438 gas_assert (nops
<= prev_nop_frag_holds
);
6440 /* Enforce NOPS as a minimum. */
6441 if (nops
> prev_nop_frag_required
)
6442 prev_nop_frag_required
= nops
;
6444 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6446 /* Settle for the current number of nops. Update the history
6447 accordingly (for the benefit of any future .set reorder code). */
6448 prev_nop_frag
= NULL
;
6449 insert_into_history (prev_nop_frag_since
,
6450 prev_nop_frag_holds
, NOP_INSN
);
6454 /* Allow this instruction to replace one of the nops that was
6455 tentatively added to prev_nop_frag. */
6456 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6457 prev_nop_frag_holds
--;
6458 prev_nop_frag_since
++;
6462 method
= get_append_method (ip
, address_expr
, reloc_type
);
6463 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6465 dwarf2_emit_insn (0);
6466 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6467 so "move" the instruction address accordingly.
6469 Also, it doesn't seem appropriate for the assembler to reorder .loc
6470 entries. If this instruction is a branch that we are going to swap
6471 with the previous instruction, the two instructions should be
6472 treated as a unit, and the debug information for both instructions
6473 should refer to the start of the branch sequence. Using the
6474 current position is certainly wrong when swapping a 32-bit branch
6475 and a 16-bit delay slot, since the current position would then be
6476 in the middle of a branch. */
6477 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6479 relax32
= (mips_relax_branch
6480 /* Don't try branch relaxation within .set nomacro, or within
6481 .set noat if we use $at for PIC computations. If it turns
6482 out that the branch was out-of-range, we'll get an error. */
6483 && !mips_opts
.warn_about_macros
6484 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6485 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6486 as they have no complementing branches. */
6487 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6489 if (!HAVE_CODE_COMPRESSION
6492 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6493 && delayed_branch_p (ip
))
6495 relaxed_branch
= TRUE
;
6496 add_relaxed_insn (ip
, (relaxed_branch_length
6498 uncond_branch_p (ip
) ? -1
6499 : branch_likely_p (ip
) ? 1
6503 uncond_branch_p (ip
),
6504 branch_likely_p (ip
),
6505 pinfo
& INSN_WRITE_GPR_31
,
6507 address_expr
->X_add_symbol
,
6508 address_expr
->X_add_number
);
6509 *reloc_type
= BFD_RELOC_UNUSED
;
6511 else if (mips_opts
.micromips
6513 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6514 || *reloc_type
> BFD_RELOC_UNUSED
)
6515 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6516 /* Don't try branch relaxation when users specify
6517 16-bit/32-bit instructions. */
6518 && !forced_insn_length
)
6520 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6521 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6522 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6523 int compact
= compact_branch_p (ip
);
6524 int al
= pinfo
& INSN_WRITE_GPR_31
;
6527 gas_assert (address_expr
!= NULL
);
6528 gas_assert (!mips_relax
.sequence
);
6530 relaxed_branch
= TRUE
;
6531 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6532 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6533 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6535 address_expr
->X_add_symbol
,
6536 address_expr
->X_add_number
);
6537 *reloc_type
= BFD_RELOC_UNUSED
;
6539 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6541 /* We need to set up a variant frag. */
6542 gas_assert (address_expr
!= NULL
);
6543 add_relaxed_insn (ip
, 4, 0,
6545 (*reloc_type
- BFD_RELOC_UNUSED
,
6546 forced_insn_length
== 2, forced_insn_length
== 4,
6547 delayed_branch_p (&history
[0]),
6548 history
[0].mips16_absolute_jump_p
),
6549 make_expr_symbol (address_expr
), 0);
6551 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6553 if (!delayed_branch_p (ip
))
6554 /* Make sure there is enough room to swap this instruction with
6555 a following jump instruction. */
6557 add_fixed_insn (ip
);
6561 if (mips_opts
.mips16
6562 && mips_opts
.noreorder
6563 && delayed_branch_p (&history
[0]))
6564 as_warn (_("extended instruction in delay slot"));
6566 if (mips_relax
.sequence
)
6568 /* If we've reached the end of this frag, turn it into a variant
6569 frag and record the information for the instructions we've
6571 if (frag_room () < 4)
6572 relax_close_frag ();
6573 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6576 if (mips_relax
.sequence
!= 2)
6578 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6579 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6580 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6581 mips_macro_warning
.insns
[0]++;
6583 if (mips_relax
.sequence
!= 1)
6585 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6586 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6587 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6588 mips_macro_warning
.insns
[1]++;
6591 if (mips_opts
.mips16
)
6594 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6596 add_fixed_insn (ip
);
6599 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6601 bfd_reloc_code_real_type final_type
[3];
6602 reloc_howto_type
*howto0
;
6603 reloc_howto_type
*howto
;
6606 /* Perform any necessary conversion to microMIPS relocations
6607 and find out how many relocations there actually are. */
6608 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6609 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6611 /* In a compound relocation, it is the final (outermost)
6612 operator that determines the relocated field. */
6613 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6618 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6619 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6620 bfd_get_reloc_size (howto
),
6622 howto0
&& howto0
->pc_relative
,
6625 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6626 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6627 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6629 /* These relocations can have an addend that won't fit in
6630 4 octets for 64bit assembly. */
6632 && ! howto
->partial_inplace
6633 && (reloc_type
[0] == BFD_RELOC_16
6634 || reloc_type
[0] == BFD_RELOC_32
6635 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6636 || reloc_type
[0] == BFD_RELOC_GPREL16
6637 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6638 || reloc_type
[0] == BFD_RELOC_GPREL32
6639 || reloc_type
[0] == BFD_RELOC_64
6640 || reloc_type
[0] == BFD_RELOC_CTOR
6641 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6642 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6643 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6644 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6645 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6646 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6647 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6648 || hi16_reloc_p (reloc_type
[0])
6649 || lo16_reloc_p (reloc_type
[0])))
6650 ip
->fixp
[0]->fx_no_overflow
= 1;
6652 /* These relocations can have an addend that won't fit in 2 octets. */
6653 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6654 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6655 ip
->fixp
[0]->fx_no_overflow
= 1;
6657 if (mips_relax
.sequence
)
6659 if (mips_relax
.first_fixup
== 0)
6660 mips_relax
.first_fixup
= ip
->fixp
[0];
6662 else if (reloc_needs_lo_p (*reloc_type
))
6664 struct mips_hi_fixup
*hi_fixup
;
6666 /* Reuse the last entry if it already has a matching %lo. */
6667 hi_fixup
= mips_hi_fixup_list
;
6669 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6671 hi_fixup
= ((struct mips_hi_fixup
*)
6672 xmalloc (sizeof (struct mips_hi_fixup
)));
6673 hi_fixup
->next
= mips_hi_fixup_list
;
6674 mips_hi_fixup_list
= hi_fixup
;
6676 hi_fixup
->fixp
= ip
->fixp
[0];
6677 hi_fixup
->seg
= now_seg
;
6680 /* Add fixups for the second and third relocations, if given.
6681 Note that the ABI allows the second relocation to be
6682 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6683 moment we only use RSS_UNDEF, but we could add support
6684 for the others if it ever becomes necessary. */
6685 for (i
= 1; i
< 3; i
++)
6686 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6688 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6689 ip
->fixp
[0]->fx_size
, NULL
, 0,
6690 FALSE
, final_type
[i
]);
6692 /* Use fx_tcbit to mark compound relocs. */
6693 ip
->fixp
[0]->fx_tcbit
= 1;
6694 ip
->fixp
[i
]->fx_tcbit
= 1;
6699 /* Update the register mask information. */
6700 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6701 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6706 insert_into_history (0, 1, ip
);
6709 case APPEND_ADD_WITH_NOP
:
6711 struct mips_cl_insn
*nop
;
6713 insert_into_history (0, 1, ip
);
6714 nop
= get_delay_slot_nop (ip
);
6715 add_fixed_insn (nop
);
6716 insert_into_history (0, 1, nop
);
6717 if (mips_relax
.sequence
)
6718 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6722 case APPEND_ADD_COMPACT
:
6723 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6724 gas_assert (mips_opts
.mips16
);
6725 ip
->insn_opcode
|= 0x0080;
6726 find_altered_mips16_opcode (ip
);
6728 insert_into_history (0, 1, ip
);
6733 struct mips_cl_insn delay
= history
[0];
6734 if (mips_opts
.mips16
)
6736 know (delay
.frag
== ip
->frag
);
6737 move_insn (ip
, delay
.frag
, delay
.where
);
6738 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6740 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6742 /* Add the delay slot instruction to the end of the
6743 current frag and shrink the fixed part of the
6744 original frag. If the branch occupies the tail of
6745 the latter, move it backwards to cover the gap. */
6746 delay
.frag
->fr_fix
-= branch_disp
;
6747 if (delay
.frag
== ip
->frag
)
6748 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6749 add_fixed_insn (&delay
);
6753 move_insn (&delay
, ip
->frag
,
6754 ip
->where
- branch_disp
+ insn_length (ip
));
6755 move_insn (ip
, history
[0].frag
, history
[0].where
);
6759 insert_into_history (0, 1, &delay
);
6764 /* If we have just completed an unconditional branch, clear the history. */
6765 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
6766 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
6770 mips_no_prev_insn ();
6772 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6773 history
[i
].cleared_p
= 1;
6776 /* We need to emit a label at the end of branch-likely macros. */
6777 if (emit_branch_likely_macro
)
6779 emit_branch_likely_macro
= FALSE
;
6780 micromips_add_label ();
6783 /* We just output an insn, so the next one doesn't have a label. */
6784 mips_clear_insn_labels ();
6787 /* Forget that there was any previous instruction or label.
6788 When BRANCH is true, the branch history is also flushed. */
6791 mips_no_prev_insn (void)
6793 prev_nop_frag
= NULL
;
6794 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
6795 mips_clear_insn_labels ();
6798 /* This function must be called before we emit something other than
6799 instructions. It is like mips_no_prev_insn except that it inserts
6800 any NOPS that might be needed by previous instructions. */
6803 mips_emit_delays (void)
6805 if (! mips_opts
.noreorder
)
6807 int nops
= nops_for_insn (0, history
, NULL
);
6811 add_fixed_insn (NOP_INSN
);
6812 mips_move_text_labels ();
6815 mips_no_prev_insn ();
6818 /* Start a (possibly nested) noreorder block. */
6821 start_noreorder (void)
6823 if (mips_opts
.noreorder
== 0)
6828 /* None of the instructions before the .set noreorder can be moved. */
6829 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6830 history
[i
].fixed_p
= 1;
6832 /* Insert any nops that might be needed between the .set noreorder
6833 block and the previous instructions. We will later remove any
6834 nops that turn out not to be needed. */
6835 nops
= nops_for_insn (0, history
, NULL
);
6838 if (mips_optimize
!= 0)
6840 /* Record the frag which holds the nop instructions, so
6841 that we can remove them if we don't need them. */
6842 frag_grow (nops
* NOP_INSN_SIZE
);
6843 prev_nop_frag
= frag_now
;
6844 prev_nop_frag_holds
= nops
;
6845 prev_nop_frag_required
= 0;
6846 prev_nop_frag_since
= 0;
6849 for (; nops
> 0; --nops
)
6850 add_fixed_insn (NOP_INSN
);
6852 /* Move on to a new frag, so that it is safe to simply
6853 decrease the size of prev_nop_frag. */
6854 frag_wane (frag_now
);
6856 mips_move_text_labels ();
6858 mips_mark_labels ();
6859 mips_clear_insn_labels ();
6861 mips_opts
.noreorder
++;
6862 mips_any_noreorder
= 1;
6865 /* End a nested noreorder block. */
6868 end_noreorder (void)
6870 mips_opts
.noreorder
--;
6871 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
6873 /* Commit to inserting prev_nop_frag_required nops and go back to
6874 handling nop insertion the .set reorder way. */
6875 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
6877 insert_into_history (prev_nop_frag_since
,
6878 prev_nop_frag_required
, NOP_INSN
);
6879 prev_nop_frag
= NULL
;
6883 /* Set up global variables for the start of a new macro. */
6888 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
6889 memset (&mips_macro_warning
.first_insn_sizes
, 0,
6890 sizeof (mips_macro_warning
.first_insn_sizes
));
6891 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
6892 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
6893 && delayed_branch_p (&history
[0]));
6894 switch (history
[0].insn_mo
->pinfo2
6895 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
6897 case INSN2_BRANCH_DELAY_32BIT
:
6898 mips_macro_warning
.delay_slot_length
= 4;
6900 case INSN2_BRANCH_DELAY_16BIT
:
6901 mips_macro_warning
.delay_slot_length
= 2;
6904 mips_macro_warning
.delay_slot_length
= 0;
6907 mips_macro_warning
.first_frag
= NULL
;
6910 /* Given that a macro is longer than one instruction or of the wrong size,
6911 return the appropriate warning for it. Return null if no warning is
6912 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6913 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6914 and RELAX_NOMACRO. */
6917 macro_warning (relax_substateT subtype
)
6919 if (subtype
& RELAX_DELAY_SLOT
)
6920 return _("Macro instruction expanded into multiple instructions"
6921 " in a branch delay slot");
6922 else if (subtype
& RELAX_NOMACRO
)
6923 return _("Macro instruction expanded into multiple instructions");
6924 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
6925 | RELAX_DELAY_SLOT_SIZE_SECOND
))
6926 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
6927 ? _("Macro instruction expanded into a wrong size instruction"
6928 " in a 16-bit branch delay slot")
6929 : _("Macro instruction expanded into a wrong size instruction"
6930 " in a 32-bit branch delay slot"));
6935 /* Finish up a macro. Emit warnings as appropriate. */
6940 /* Relaxation warning flags. */
6941 relax_substateT subtype
= 0;
6943 /* Check delay slot size requirements. */
6944 if (mips_macro_warning
.delay_slot_length
== 2)
6945 subtype
|= RELAX_DELAY_SLOT_16BIT
;
6946 if (mips_macro_warning
.delay_slot_length
!= 0)
6948 if (mips_macro_warning
.delay_slot_length
6949 != mips_macro_warning
.first_insn_sizes
[0])
6950 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
6951 if (mips_macro_warning
.delay_slot_length
6952 != mips_macro_warning
.first_insn_sizes
[1])
6953 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
6956 /* Check instruction count requirements. */
6957 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
6959 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
6960 subtype
|= RELAX_SECOND_LONGER
;
6961 if (mips_opts
.warn_about_macros
)
6962 subtype
|= RELAX_NOMACRO
;
6963 if (mips_macro_warning
.delay_slot_p
)
6964 subtype
|= RELAX_DELAY_SLOT
;
6967 /* If both alternatives fail to fill a delay slot correctly,
6968 emit the warning now. */
6969 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
6970 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
6975 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
6976 | RELAX_DELAY_SLOT_SIZE_FIRST
6977 | RELAX_DELAY_SLOT_SIZE_SECOND
);
6978 msg
= macro_warning (s
);
6980 as_warn ("%s", msg
);
6984 /* If both implementations are longer than 1 instruction, then emit the
6986 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
6991 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
6992 msg
= macro_warning (s
);
6994 as_warn ("%s", msg
);
6998 /* If any flags still set, then one implementation might need a warning
6999 and the other either will need one of a different kind or none at all.
7000 Pass any remaining flags over to relaxation. */
7001 if (mips_macro_warning
.first_frag
!= NULL
)
7002 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
7005 /* Instruction operand formats used in macros that vary between
7006 standard MIPS and microMIPS code. */
7008 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
7009 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
7010 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
7011 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
7012 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
7013 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
7014 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
7015 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
7017 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7018 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7019 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7020 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7021 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7022 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7023 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7024 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7026 /* Read a macro's relocation codes from *ARGS and store them in *R.
7027 The first argument in *ARGS will be either the code for a single
7028 relocation or -1 followed by the three codes that make up a
7029 composite relocation. */
7032 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
7036 next
= va_arg (*args
, int);
7038 r
[0] = (bfd_reloc_code_real_type
) next
;
7041 for (i
= 0; i
< 3; i
++)
7042 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
7043 /* This function is only used for 16-bit relocation fields.
7044 To make the macro code simpler, treat an unrelocated value
7045 in the same way as BFD_RELOC_LO16. */
7046 if (r
[0] == BFD_RELOC_UNUSED
)
7047 r
[0] = BFD_RELOC_LO16
;
7051 /* Build an instruction created by a macro expansion. This is passed
7052 a pointer to the count of instructions created so far, an
7053 expression, the name of the instruction to build, an operand format
7054 string, and corresponding arguments. */
7057 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
7059 const struct mips_opcode
*mo
= NULL
;
7060 bfd_reloc_code_real_type r
[3];
7061 const struct mips_opcode
*amo
;
7062 const struct mips_operand
*operand
;
7063 struct hash_control
*hash
;
7064 struct mips_cl_insn insn
;
7068 va_start (args
, fmt
);
7070 if (mips_opts
.mips16
)
7072 mips16_macro_build (ep
, name
, fmt
, &args
);
7077 r
[0] = BFD_RELOC_UNUSED
;
7078 r
[1] = BFD_RELOC_UNUSED
;
7079 r
[2] = BFD_RELOC_UNUSED
;
7080 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
7081 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
7083 gas_assert (strcmp (name
, amo
->name
) == 0);
7087 /* Search until we get a match for NAME. It is assumed here that
7088 macros will never generate MDMX, MIPS-3D, or MT instructions.
7089 We try to match an instruction that fulfils the branch delay
7090 slot instruction length requirement (if any) of the previous
7091 instruction. While doing this we record the first instruction
7092 seen that matches all the other conditions and use it anyway
7093 if the requirement cannot be met; we will issue an appropriate
7094 warning later on. */
7095 if (strcmp (fmt
, amo
->args
) == 0
7096 && amo
->pinfo
!= INSN_MACRO
7097 && is_opcode_valid (amo
)
7098 && is_size_valid (amo
))
7100 if (is_delay_slot_valid (amo
))
7110 gas_assert (amo
->name
);
7112 while (strcmp (name
, amo
->name
) == 0);
7115 create_insn (&insn
, mo
);
7128 macro_read_relocs (&args
, r
);
7129 gas_assert (*r
== BFD_RELOC_GPREL16
7130 || *r
== BFD_RELOC_MIPS_HIGHER
7131 || *r
== BFD_RELOC_HI16_S
7132 || *r
== BFD_RELOC_LO16
7133 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
7137 macro_read_relocs (&args
, r
);
7141 macro_read_relocs (&args
, r
);
7142 gas_assert (ep
!= NULL
7143 && (ep
->X_op
== O_constant
7144 || (ep
->X_op
== O_symbol
7145 && (*r
== BFD_RELOC_MIPS_HIGHEST
7146 || *r
== BFD_RELOC_HI16_S
7147 || *r
== BFD_RELOC_HI16
7148 || *r
== BFD_RELOC_GPREL16
7149 || *r
== BFD_RELOC_MIPS_GOT_HI16
7150 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
7154 gas_assert (ep
!= NULL
);
7157 * This allows macro() to pass an immediate expression for
7158 * creating short branches without creating a symbol.
7160 * We don't allow branch relaxation for these branches, as
7161 * they should only appear in ".set nomacro" anyway.
7163 if (ep
->X_op
== O_constant
)
7165 /* For microMIPS we always use relocations for branches.
7166 So we should not resolve immediate values. */
7167 gas_assert (!mips_opts
.micromips
);
7169 if ((ep
->X_add_number
& 3) != 0)
7170 as_bad (_("branch to misaligned address (0x%lx)"),
7171 (unsigned long) ep
->X_add_number
);
7172 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
7173 as_bad (_("branch address range overflow (0x%lx)"),
7174 (unsigned long) ep
->X_add_number
);
7175 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
7179 *r
= BFD_RELOC_16_PCREL_S2
;
7183 gas_assert (ep
!= NULL
);
7184 *r
= BFD_RELOC_MIPS_JMP
;
7188 operand
= (mips_opts
.micromips
7189 ? decode_micromips_operand (fmt
)
7190 : decode_mips_operand (fmt
));
7194 uval
= va_arg (args
, int);
7195 if (operand
->type
== OP_CLO_CLZ_DEST
)
7196 uval
|= (uval
<< 5);
7197 insn_insert_operand (&insn
, operand
, uval
);
7199 if (*fmt
== '+' || *fmt
== 'm')
7205 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7207 append_insn (&insn
, ep
, r
, TRUE
);
7211 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
7214 struct mips_opcode
*mo
;
7215 struct mips_cl_insn insn
;
7216 const struct mips_operand
*operand
;
7217 bfd_reloc_code_real_type r
[3]
7218 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
7220 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
7222 gas_assert (strcmp (name
, mo
->name
) == 0);
7224 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
7227 gas_assert (mo
->name
);
7228 gas_assert (strcmp (name
, mo
->name
) == 0);
7231 create_insn (&insn
, mo
);
7269 gas_assert (ep
!= NULL
);
7271 if (ep
->X_op
!= O_constant
)
7272 *r
= (int) BFD_RELOC_UNUSED
+ c
;
7273 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
7275 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
7277 *r
= BFD_RELOC_UNUSED
;
7283 operand
= decode_mips16_operand (c
, FALSE
);
7287 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
7292 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7294 append_insn (&insn
, ep
, r
, TRUE
);
7298 * Sign-extend 32-bit mode constants that have bit 31 set and all
7299 * higher bits unset.
7302 normalize_constant_expr (expressionS
*ex
)
7304 if (ex
->X_op
== O_constant
7305 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7306 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7311 * Sign-extend 32-bit mode address offsets that have bit 31 set and
7312 * all higher bits unset.
7315 normalize_address_expr (expressionS
*ex
)
7317 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7318 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7319 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7320 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7325 * Generate a "jalr" instruction with a relocation hint to the called
7326 * function. This occurs in NewABI PIC code.
7329 macro_build_jalr (expressionS
*ep
, int cprestore
)
7331 static const bfd_reloc_code_real_type jalr_relocs
[2]
7332 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
7333 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
7337 if (MIPS_JALR_HINT_P (ep
))
7342 if (mips_opts
.micromips
)
7344 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
7345 ? "jalr" : "jalrs");
7346 if (MIPS_JALR_HINT_P (ep
)
7348 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7349 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
7351 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
7354 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
7355 if (MIPS_JALR_HINT_P (ep
))
7356 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
7360 * Generate a "lui" instruction.
7363 macro_build_lui (expressionS
*ep
, int regnum
)
7365 gas_assert (! mips_opts
.mips16
);
7367 if (ep
->X_op
!= O_constant
)
7369 gas_assert (ep
->X_op
== O_symbol
);
7370 /* _gp_disp is a special case, used from s_cpload.
7371 __gnu_local_gp is used if mips_no_shared. */
7372 gas_assert (mips_pic
== NO_PIC
7374 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
7375 || (! mips_in_shared
7376 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
7377 "__gnu_local_gp") == 0));
7380 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
7383 /* Generate a sequence of instructions to do a load or store from a constant
7384 offset off of a base register (breg) into/from a target register (treg),
7385 using AT if necessary. */
7387 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
7388 int treg
, int breg
, int dbl
)
7390 gas_assert (ep
->X_op
== O_constant
);
7392 /* Sign-extending 32-bit constants makes their handling easier. */
7394 normalize_constant_expr (ep
);
7396 /* Right now, this routine can only handle signed 32-bit constants. */
7397 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
7398 as_warn (_("operand overflow"));
7400 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
7402 /* Signed 16-bit offset will fit in the op. Easy! */
7403 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7407 /* 32-bit offset, need multiple instructions and AT, like:
7408 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7409 addu $tempreg,$tempreg,$breg
7410 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7411 to handle the complete offset. */
7412 macro_build_lui (ep
, AT
);
7413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7414 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7417 as_bad (_("Macro used $at after \".set noat\""));
7422 * Generates code to set the $at register to true (one)
7423 * if reg is less than the immediate expression.
7426 set_at (int reg
, int unsignedp
)
7428 if (imm_expr
.X_op
== O_constant
7429 && imm_expr
.X_add_number
>= -0x8000
7430 && imm_expr
.X_add_number
< 0x8000)
7431 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
7432 AT
, reg
, BFD_RELOC_LO16
);
7435 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7436 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
7440 /* Count the leading zeroes by performing a binary chop. This is a
7441 bulky bit of source, but performance is a LOT better for the
7442 majority of values than a simple loop to count the bits:
7443 for (lcnt = 0; (lcnt < 32); lcnt++)
7444 if ((v) & (1 << (31 - lcnt)))
7446 However it is not code size friendly, and the gain will drop a bit
7447 on certain cached systems.
7449 #define COUNT_TOP_ZEROES(v) \
7450 (((v) & ~0xffff) == 0 \
7451 ? ((v) & ~0xff) == 0 \
7452 ? ((v) & ~0xf) == 0 \
7453 ? ((v) & ~0x3) == 0 \
7454 ? ((v) & ~0x1) == 0 \
7459 : ((v) & ~0x7) == 0 \
7462 : ((v) & ~0x3f) == 0 \
7463 ? ((v) & ~0x1f) == 0 \
7466 : ((v) & ~0x7f) == 0 \
7469 : ((v) & ~0xfff) == 0 \
7470 ? ((v) & ~0x3ff) == 0 \
7471 ? ((v) & ~0x1ff) == 0 \
7474 : ((v) & ~0x7ff) == 0 \
7477 : ((v) & ~0x3fff) == 0 \
7478 ? ((v) & ~0x1fff) == 0 \
7481 : ((v) & ~0x7fff) == 0 \
7484 : ((v) & ~0xffffff) == 0 \
7485 ? ((v) & ~0xfffff) == 0 \
7486 ? ((v) & ~0x3ffff) == 0 \
7487 ? ((v) & ~0x1ffff) == 0 \
7490 : ((v) & ~0x7ffff) == 0 \
7493 : ((v) & ~0x3fffff) == 0 \
7494 ? ((v) & ~0x1fffff) == 0 \
7497 : ((v) & ~0x7fffff) == 0 \
7500 : ((v) & ~0xfffffff) == 0 \
7501 ? ((v) & ~0x3ffffff) == 0 \
7502 ? ((v) & ~0x1ffffff) == 0 \
7505 : ((v) & ~0x7ffffff) == 0 \
7508 : ((v) & ~0x3fffffff) == 0 \
7509 ? ((v) & ~0x1fffffff) == 0 \
7512 : ((v) & ~0x7fffffff) == 0 \
7517 * This routine generates the least number of instructions necessary to load
7518 * an absolute expression value into a register.
7521 load_register (int reg
, expressionS
*ep
, int dbl
)
7524 expressionS hi32
, lo32
;
7526 if (ep
->X_op
!= O_big
)
7528 gas_assert (ep
->X_op
== O_constant
);
7530 /* Sign-extending 32-bit constants makes their handling easier. */
7532 normalize_constant_expr (ep
);
7534 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
7536 /* We can handle 16 bit signed values with an addiu to
7537 $zero. No need to ever use daddiu here, since $zero and
7538 the result are always correct in 32 bit mode. */
7539 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7542 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
7544 /* We can handle 16 bit unsigned values with an ori to
7546 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
7549 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
7551 /* 32 bit values require an lui. */
7552 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7553 if ((ep
->X_add_number
& 0xffff) != 0)
7554 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
7559 /* The value is larger than 32 bits. */
7561 if (!dbl
|| HAVE_32BIT_GPRS
)
7565 sprintf_vma (value
, ep
->X_add_number
);
7566 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7567 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7571 if (ep
->X_op
!= O_big
)
7574 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
7575 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
7576 hi32
.X_add_number
&= 0xffffffff;
7578 lo32
.X_add_number
&= 0xffffffff;
7582 gas_assert (ep
->X_add_number
> 2);
7583 if (ep
->X_add_number
== 3)
7584 generic_bignum
[3] = 0;
7585 else if (ep
->X_add_number
> 4)
7586 as_bad (_("Number larger than 64 bits"));
7587 lo32
.X_op
= O_constant
;
7588 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
7589 hi32
.X_op
= O_constant
;
7590 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
7593 if (hi32
.X_add_number
== 0)
7598 unsigned long hi
, lo
;
7600 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
7602 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
7604 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7607 if (lo32
.X_add_number
& 0x80000000)
7609 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7610 if (lo32
.X_add_number
& 0xffff)
7611 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
7616 /* Check for 16bit shifted constant. We know that hi32 is
7617 non-zero, so start the mask on the first bit of the hi32
7622 unsigned long himask
, lomask
;
7626 himask
= 0xffff >> (32 - shift
);
7627 lomask
= (0xffff << shift
) & 0xffffffff;
7631 himask
= 0xffff << (shift
- 32);
7634 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
7635 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
7639 tmp
.X_op
= O_constant
;
7641 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
7642 | (lo32
.X_add_number
>> shift
));
7644 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
7645 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
7646 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
7647 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
7652 while (shift
<= (64 - 16));
7654 /* Find the bit number of the lowest one bit, and store the
7655 shifted value in hi/lo. */
7656 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
7657 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
7661 while ((lo
& 1) == 0)
7666 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
7672 while ((hi
& 1) == 0)
7681 /* Optimize if the shifted value is a (power of 2) - 1. */
7682 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
7683 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
7685 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
7690 /* This instruction will set the register to be all
7692 tmp
.X_op
= O_constant
;
7693 tmp
.X_add_number
= (offsetT
) -1;
7694 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7698 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
7699 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
7701 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
7702 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
7707 /* Sign extend hi32 before calling load_register, because we can
7708 generally get better code when we load a sign extended value. */
7709 if ((hi32
.X_add_number
& 0x80000000) != 0)
7710 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
7711 load_register (reg
, &hi32
, 0);
7714 if ((lo32
.X_add_number
& 0xffff0000) == 0)
7718 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
7726 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
7728 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7729 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
7735 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
7739 mid16
.X_add_number
>>= 16;
7740 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
7741 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7744 if ((lo32
.X_add_number
& 0xffff) != 0)
7745 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
7749 load_delay_nop (void)
7751 if (!gpr_interlocks
)
7752 macro_build (NULL
, "nop", "");
7755 /* Load an address into a register. */
7758 load_address (int reg
, expressionS
*ep
, int *used_at
)
7760 if (ep
->X_op
!= O_constant
7761 && ep
->X_op
!= O_symbol
)
7763 as_bad (_("expression too complex"));
7764 ep
->X_op
= O_constant
;
7767 if (ep
->X_op
== O_constant
)
7769 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
7773 if (mips_pic
== NO_PIC
)
7775 /* If this is a reference to a GP relative symbol, we want
7776 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
7778 lui $reg,<sym> (BFD_RELOC_HI16_S)
7779 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7780 If we have an addend, we always use the latter form.
7782 With 64bit address space and a usable $at we want
7783 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7784 lui $at,<sym> (BFD_RELOC_HI16_S)
7785 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7786 daddiu $at,<sym> (BFD_RELOC_LO16)
7790 If $at is already in use, we use a path which is suboptimal
7791 on superscalar processors.
7792 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7793 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7795 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7797 daddiu $reg,<sym> (BFD_RELOC_LO16)
7799 For GP relative symbols in 64bit address space we can use
7800 the same sequence as in 32bit address space. */
7801 if (HAVE_64BIT_SYMBOLS
)
7803 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7804 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7806 relax_start (ep
->X_add_symbol
);
7807 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7808 mips_gp_register
, BFD_RELOC_GPREL16
);
7812 if (*used_at
== 0 && mips_opts
.at
)
7814 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7815 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
7816 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7817 BFD_RELOC_MIPS_HIGHER
);
7818 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
7819 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
7820 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
7825 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7826 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7827 BFD_RELOC_MIPS_HIGHER
);
7828 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7829 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
7830 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7831 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
7834 if (mips_relax
.sequence
)
7839 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7840 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7842 relax_start (ep
->X_add_symbol
);
7843 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7844 mips_gp_register
, BFD_RELOC_GPREL16
);
7847 macro_build_lui (ep
, reg
);
7848 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
7849 reg
, reg
, BFD_RELOC_LO16
);
7850 if (mips_relax
.sequence
)
7854 else if (!mips_big_got
)
7858 /* If this is a reference to an external symbol, we want
7859 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7861 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7863 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7864 If there is a constant, it must be added in after.
7866 If we have NewABI, we want
7867 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7868 unless we're referencing a global symbol with a non-zero
7869 offset, in which case cst must be added separately. */
7872 if (ep
->X_add_number
)
7874 ex
.X_add_number
= ep
->X_add_number
;
7875 ep
->X_add_number
= 0;
7876 relax_start (ep
->X_add_symbol
);
7877 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7878 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7879 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7880 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7881 ex
.X_op
= O_constant
;
7882 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7883 reg
, reg
, BFD_RELOC_LO16
);
7884 ep
->X_add_number
= ex
.X_add_number
;
7887 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7888 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7889 if (mips_relax
.sequence
)
7894 ex
.X_add_number
= ep
->X_add_number
;
7895 ep
->X_add_number
= 0;
7896 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7897 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7899 relax_start (ep
->X_add_symbol
);
7901 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7905 if (ex
.X_add_number
!= 0)
7907 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7908 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7909 ex
.X_op
= O_constant
;
7910 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7911 reg
, reg
, BFD_RELOC_LO16
);
7915 else if (mips_big_got
)
7919 /* This is the large GOT case. If this is a reference to an
7920 external symbol, we want
7921 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7923 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
7925 Otherwise, for a reference to a local symbol in old ABI, we want
7926 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7928 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7929 If there is a constant, it must be added in after.
7931 In the NewABI, for local symbols, with or without offsets, we want:
7932 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7933 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7937 ex
.X_add_number
= ep
->X_add_number
;
7938 ep
->X_add_number
= 0;
7939 relax_start (ep
->X_add_symbol
);
7940 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7941 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7942 reg
, reg
, mips_gp_register
);
7943 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7944 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7945 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7946 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7947 else if (ex
.X_add_number
)
7949 ex
.X_op
= O_constant
;
7950 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7954 ep
->X_add_number
= ex
.X_add_number
;
7956 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7957 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7958 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7959 BFD_RELOC_MIPS_GOT_OFST
);
7964 ex
.X_add_number
= ep
->X_add_number
;
7965 ep
->X_add_number
= 0;
7966 relax_start (ep
->X_add_symbol
);
7967 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7968 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7969 reg
, reg
, mips_gp_register
);
7970 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7971 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7973 if (reg_needs_delay (mips_gp_register
))
7975 /* We need a nop before loading from $gp. This special
7976 check is required because the lui which starts the main
7977 instruction stream does not refer to $gp, and so will not
7978 insert the nop which may be required. */
7979 macro_build (NULL
, "nop", "");
7981 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7982 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7984 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7988 if (ex
.X_add_number
!= 0)
7990 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7991 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7992 ex
.X_op
= O_constant
;
7993 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8001 if (!mips_opts
.at
&& *used_at
== 1)
8002 as_bad (_("Macro used $at after \".set noat\""));
8005 /* Move the contents of register SOURCE into register DEST. */
8008 move_register (int dest
, int source
)
8010 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8011 instruction specifically requires a 32-bit one. */
8012 if (mips_opts
.micromips
8013 && !mips_opts
.insn32
8014 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8015 macro_build (NULL
, "move", "mp,mj", dest
, source
);
8017 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
8021 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8022 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8023 The two alternatives are:
8025 Global symbol Local sybmol
8026 ------------- ------------
8027 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8029 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8031 load_got_offset emits the first instruction and add_got_offset
8032 emits the second for a 16-bit offset or add_got_offset_hilo emits
8033 a sequence to add a 32-bit offset using a scratch register. */
8036 load_got_offset (int dest
, expressionS
*local
)
8041 global
.X_add_number
= 0;
8043 relax_start (local
->X_add_symbol
);
8044 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8045 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8047 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8048 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8053 add_got_offset (int dest
, expressionS
*local
)
8057 global
.X_op
= O_constant
;
8058 global
.X_op_symbol
= NULL
;
8059 global
.X_add_symbol
= NULL
;
8060 global
.X_add_number
= local
->X_add_number
;
8062 relax_start (local
->X_add_symbol
);
8063 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
8064 dest
, dest
, BFD_RELOC_LO16
);
8066 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
8071 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
8074 int hold_mips_optimize
;
8076 global
.X_op
= O_constant
;
8077 global
.X_op_symbol
= NULL
;
8078 global
.X_add_symbol
= NULL
;
8079 global
.X_add_number
= local
->X_add_number
;
8081 relax_start (local
->X_add_symbol
);
8082 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
8084 /* Set mips_optimize around the lui instruction to avoid
8085 inserting an unnecessary nop after the lw. */
8086 hold_mips_optimize
= mips_optimize
;
8088 macro_build_lui (&global
, tmp
);
8089 mips_optimize
= hold_mips_optimize
;
8090 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
8093 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
8096 /* Emit a sequence of instructions to emulate a branch likely operation.
8097 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8098 is its complementing branch with the original condition negated.
8099 CALL is set if the original branch specified the link operation.
8100 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8102 Code like this is produced in the noreorder mode:
8107 delay slot (executed only if branch taken)
8115 delay slot (executed only if branch taken)
8118 In the reorder mode the delay slot would be filled with a nop anyway,
8119 so code produced is simply:
8124 This function is used when producing code for the microMIPS ASE that
8125 does not implement branch likely instructions in hardware. */
8128 macro_build_branch_likely (const char *br
, const char *brneg
,
8129 int call
, expressionS
*ep
, const char *fmt
,
8130 unsigned int sreg
, unsigned int treg
)
8132 int noreorder
= mips_opts
.noreorder
;
8135 gas_assert (mips_opts
.micromips
);
8139 micromips_label_expr (&expr1
);
8140 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
8141 macro_build (NULL
, "nop", "");
8142 macro_build (ep
, call
? "bal" : "b", "p");
8144 /* Set to true so that append_insn adds a label. */
8145 emit_branch_likely_macro
= TRUE
;
8149 macro_build (ep
, br
, fmt
, sreg
, treg
);
8150 macro_build (NULL
, "nop", "");
8155 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8156 the condition code tested. EP specifies the branch target. */
8159 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
8186 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
8189 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8190 the register tested. EP specifies the branch target. */
8193 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
8195 const char *brneg
= NULL
;
8205 br
= mips_opts
.micromips
? "bgez" : "bgezl";
8209 gas_assert (mips_opts
.micromips
);
8210 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
8218 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
8225 br
= mips_opts
.micromips
? "blez" : "blezl";
8232 br
= mips_opts
.micromips
? "bltz" : "bltzl";
8236 gas_assert (mips_opts
.micromips
);
8237 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
8244 if (mips_opts
.micromips
&& brneg
)
8245 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
8247 macro_build (ep
, br
, "s,p", sreg
);
8250 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8251 TREG as the registers tested. EP specifies the branch target. */
8254 macro_build_branch_rsrt (int type
, expressionS
*ep
,
8255 unsigned int sreg
, unsigned int treg
)
8257 const char *brneg
= NULL
;
8269 br
= mips_opts
.micromips
? "beq" : "beql";
8278 br
= mips_opts
.micromips
? "bne" : "bnel";
8284 if (mips_opts
.micromips
&& brneg
)
8285 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
8287 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
8290 /* Return the high part that should be loaded in order to make the low
8291 part of VALUE accessible using an offset of OFFBITS bits. */
8294 offset_high_part (offsetT value
, unsigned int offbits
)
8301 bias
= 1 << (offbits
- 1);
8302 low_mask
= bias
* 2 - 1;
8303 return (value
+ bias
) & ~low_mask
;
8306 /* Return true if the value stored in offset_expr and offset_reloc
8307 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8308 amount that the caller wants to add without inducing overflow
8309 and ALIGN is the known alignment of the value in bytes. */
8312 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
8316 /* Accept any relocation operator if overflow isn't a concern. */
8317 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8320 /* These relocations are guaranteed not to overflow in correct links. */
8321 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
8322 || gprel16_reloc_p (*offset_reloc
))
8325 if (offset_expr
.X_op
== O_constant
8326 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
8327 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
8334 * This routine implements the seemingly endless macro or synthesized
8335 * instructions and addressing modes in the mips assembly language. Many
8336 * of these macros are simple and are similar to each other. These could
8337 * probably be handled by some kind of table or grammar approach instead of
8338 * this verbose method. Others are not simple macros but are more like
8339 * optimizing code generation.
8340 * One interesting optimization is when several store macros appear
8341 * consecutively that would load AT with the upper half of the same address.
8342 * The ensuing load upper instructions are ommited. This implies some kind
8343 * of global optimization. We currently only optimize within a single macro.
8344 * For many of the load and store macros if the address is specified as a
8345 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8346 * first load register 'at' with zero and use it as the base register. The
8347 * mips assembler simply uses register $zero. Just one tiny optimization
8351 macro (struct mips_cl_insn
*ip
, char *str
)
8353 const struct mips_operand_array
*operands
;
8354 unsigned int breg
, i
;
8355 unsigned int tempreg
;
8358 expressionS label_expr
;
8373 bfd_boolean large_offset
;
8375 int hold_mips_optimize
;
8377 unsigned int op
[MAX_OPERANDS
];
8379 gas_assert (! mips_opts
.mips16
);
8381 operands
= insn_operands (ip
);
8382 for (i
= 0; i
< MAX_OPERANDS
; i
++)
8383 if (operands
->operand
[i
])
8384 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
8388 mask
= ip
->insn_mo
->mask
;
8390 label_expr
.X_op
= O_constant
;
8391 label_expr
.X_op_symbol
= NULL
;
8392 label_expr
.X_add_symbol
= NULL
;
8393 label_expr
.X_add_number
= 0;
8395 expr1
.X_op
= O_constant
;
8396 expr1
.X_op_symbol
= NULL
;
8397 expr1
.X_add_symbol
= NULL
;
8398 expr1
.X_add_number
= 1;
8414 if (mips_opts
.micromips
)
8415 micromips_label_expr (&label_expr
);
8417 label_expr
.X_add_number
= 8;
8418 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
8420 macro_build (NULL
, "nop", "");
8422 move_register (op
[0], op
[1]);
8423 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
8424 if (mips_opts
.micromips
)
8425 micromips_add_label ();
8442 if (!mips_opts
.micromips
)
8444 if (imm_expr
.X_op
== O_constant
8445 && imm_expr
.X_add_number
>= -0x200
8446 && imm_expr
.X_add_number
< 0x200)
8448 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1], imm_expr
.X_add_number
);
8457 if (imm_expr
.X_op
== O_constant
8458 && imm_expr
.X_add_number
>= -0x8000
8459 && imm_expr
.X_add_number
< 0x8000)
8461 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
8466 load_register (AT
, &imm_expr
, dbl
);
8467 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
8486 if (imm_expr
.X_op
== O_constant
8487 && imm_expr
.X_add_number
>= 0
8488 && imm_expr
.X_add_number
< 0x10000)
8490 if (mask
!= M_NOR_I
)
8491 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
8494 macro_build (&imm_expr
, "ori", "t,r,i",
8495 op
[0], op
[1], BFD_RELOC_LO16
);
8496 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
8502 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8503 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
8507 switch (imm_expr
.X_add_number
)
8510 macro_build (NULL
, "nop", "");
8513 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
8517 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
8518 (int) imm_expr
.X_add_number
);
8521 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
8522 (unsigned long) imm_expr
.X_add_number
);
8531 gas_assert (mips_opts
.micromips
);
8532 macro_build_branch_ccl (mask
, &offset_expr
,
8533 EXTRACT_OPERAND (1, BCC
, *ip
));
8540 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8546 load_register (op
[1], &imm_expr
, HAVE_64BIT_GPRS
);
8551 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
8558 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
8559 else if (op
[0] == 0)
8560 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
8564 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
8565 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8566 &offset_expr
, AT
, ZERO
);
8576 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
8582 /* Check for > max integer. */
8583 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
8586 /* Result is always false. */
8588 macro_build (NULL
, "nop", "");
8590 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
8593 if (imm_expr
.X_op
!= O_constant
)
8594 as_bad (_("Unsupported large constant"));
8595 ++imm_expr
.X_add_number
;
8599 if (mask
== M_BGEL_I
)
8601 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8603 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
8604 &offset_expr
, op
[0]);
8607 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8609 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
8610 &offset_expr
, op
[0]);
8613 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
8616 /* result is always true */
8617 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
8618 macro_build (&offset_expr
, "b", "p");
8623 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8624 &offset_expr
, AT
, ZERO
);
8632 else if (op
[0] == 0)
8633 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8634 &offset_expr
, ZERO
, op
[1]);
8638 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
8639 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8640 &offset_expr
, AT
, ZERO
);
8649 && imm_expr
.X_op
== O_constant
8650 && imm_expr
.X_add_number
== -1))
8652 if (imm_expr
.X_op
!= O_constant
)
8653 as_bad (_("Unsupported large constant"));
8654 ++imm_expr
.X_add_number
;
8658 if (mask
== M_BGEUL_I
)
8660 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8662 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8663 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8664 &offset_expr
, op
[0], ZERO
);
8669 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8670 &offset_expr
, AT
, ZERO
);
8678 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
8679 else if (op
[0] == 0)
8680 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
8684 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
8685 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8686 &offset_expr
, AT
, ZERO
);
8694 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8695 &offset_expr
, op
[0], ZERO
);
8696 else if (op
[0] == 0)
8701 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
8702 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8703 &offset_expr
, AT
, ZERO
);
8711 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
8712 else if (op
[0] == 0)
8713 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
8717 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
8718 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8719 &offset_expr
, AT
, ZERO
);
8726 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
8728 if (imm_expr
.X_op
!= O_constant
)
8729 as_bad (_("Unsupported large constant"));
8730 ++imm_expr
.X_add_number
;
8734 if (mask
== M_BLTL_I
)
8736 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8737 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
8738 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8739 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
8744 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8745 &offset_expr
, AT
, ZERO
);
8753 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8754 &offset_expr
, op
[0], ZERO
);
8755 else if (op
[0] == 0)
8760 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
8761 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8762 &offset_expr
, AT
, ZERO
);
8771 && imm_expr
.X_op
== O_constant
8772 && imm_expr
.X_add_number
== -1))
8774 if (imm_expr
.X_op
!= O_constant
)
8775 as_bad (_("Unsupported large constant"));
8776 ++imm_expr
.X_add_number
;
8780 if (mask
== M_BLTUL_I
)
8782 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8784 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8785 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8786 &offset_expr
, op
[0], ZERO
);
8791 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8792 &offset_expr
, AT
, ZERO
);
8800 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
8801 else if (op
[0] == 0)
8802 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
8806 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
8807 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8808 &offset_expr
, AT
, ZERO
);
8817 else if (op
[0] == 0)
8818 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8819 &offset_expr
, ZERO
, op
[1]);
8823 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
8824 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8825 &offset_expr
, AT
, ZERO
);
8831 /* Use unsigned arithmetic. */
8835 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8837 as_bad (_("Unsupported large constant"));
8842 pos
= imm_expr
.X_add_number
;
8843 size
= imm2_expr
.X_add_number
;
8848 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
8851 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8853 report_bad_field (pos
, size
);
8857 if (size
<= 32 && pos
< 32)
8862 else if (size
<= 32)
8872 macro_build ((expressionS
*) NULL
, s
, fmt
, op
[0], op
[1], (int) pos
,
8879 /* Use unsigned arithmetic. */
8883 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8885 as_bad (_("Unsupported large constant"));
8890 pos
= imm_expr
.X_add_number
;
8891 size
= imm2_expr
.X_add_number
;
8896 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
8899 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8901 report_bad_field (pos
, size
);
8905 if (pos
< 32 && (pos
+ size
- 1) < 32)
8920 macro_build ((expressionS
*) NULL
, s
, fmt
, op
[0], op
[1], (int) pos
,
8921 (int) (pos
+ size
- 1));
8937 as_warn (_("Divide by zero."));
8939 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
8941 macro_build (NULL
, "break", BRK_FMT
, 7);
8948 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
8949 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
8953 if (mips_opts
.micromips
)
8954 micromips_label_expr (&label_expr
);
8956 label_expr
.X_add_number
= 8;
8957 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
8958 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
8959 macro_build (NULL
, "break", BRK_FMT
, 7);
8960 if (mips_opts
.micromips
)
8961 micromips_add_label ();
8963 expr1
.X_add_number
= -1;
8965 load_register (AT
, &expr1
, dbl
);
8966 if (mips_opts
.micromips
)
8967 micromips_label_expr (&label_expr
);
8969 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
8970 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
8973 expr1
.X_add_number
= 1;
8974 load_register (AT
, &expr1
, dbl
);
8975 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
8979 expr1
.X_add_number
= 0x80000000;
8980 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
8984 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
8985 /* We want to close the noreorder block as soon as possible, so
8986 that later insns are available for delay slot filling. */
8991 if (mips_opts
.micromips
)
8992 micromips_label_expr (&label_expr
);
8994 label_expr
.X_add_number
= 8;
8995 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
8996 macro_build (NULL
, "nop", "");
8998 /* We want to close the noreorder block as soon as possible, so
8999 that later insns are available for delay slot filling. */
9002 macro_build (NULL
, "break", BRK_FMT
, 6);
9004 if (mips_opts
.micromips
)
9005 micromips_add_label ();
9006 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
9045 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9047 as_warn (_("Divide by zero."));
9049 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9051 macro_build (NULL
, "break", BRK_FMT
, 7);
9054 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9056 if (strcmp (s2
, "mflo") == 0)
9057 move_register (op
[0], op
[1]);
9059 move_register (op
[0], ZERO
);
9062 if (imm_expr
.X_op
== O_constant
9063 && imm_expr
.X_add_number
== -1
9064 && s
[strlen (s
) - 1] != 'u')
9066 if (strcmp (s2
, "mflo") == 0)
9067 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
9069 move_register (op
[0], ZERO
);
9074 load_register (AT
, &imm_expr
, dbl
);
9075 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
9076 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9098 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9099 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9100 /* We want to close the noreorder block as soon as possible, so
9101 that later insns are available for delay slot filling. */
9106 if (mips_opts
.micromips
)
9107 micromips_label_expr (&label_expr
);
9109 label_expr
.X_add_number
= 8;
9110 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9111 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9113 /* We want to close the noreorder block as soon as possible, so
9114 that later insns are available for delay slot filling. */
9116 macro_build (NULL
, "break", BRK_FMT
, 7);
9117 if (mips_opts
.micromips
)
9118 micromips_add_label ();
9120 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9132 /* Load the address of a symbol into a register. If breg is not
9133 zero, we then add a base register to it. */
9136 if (dbl
&& HAVE_32BIT_GPRS
)
9137 as_warn (_("dla used to load 32-bit register"));
9139 if (!dbl
&& HAVE_64BIT_OBJECTS
)
9140 as_warn (_("la used to load 64-bit address"));
9142 if (small_offset_p (0, align
, 16))
9144 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
9145 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9149 if (mips_opts
.at
&& (op
[0] == breg
))
9157 if (offset_expr
.X_op
!= O_symbol
9158 && offset_expr
.X_op
!= O_constant
)
9160 as_bad (_("Expression too complex"));
9161 offset_expr
.X_op
= O_constant
;
9164 if (offset_expr
.X_op
== O_constant
)
9165 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
9166 else if (mips_pic
== NO_PIC
)
9168 /* If this is a reference to a GP relative symbol, we want
9169 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9171 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9172 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9173 If we have a constant, we need two instructions anyhow,
9174 so we may as well always use the latter form.
9176 With 64bit address space and a usable $at we want
9177 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9178 lui $at,<sym> (BFD_RELOC_HI16_S)
9179 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9180 daddiu $at,<sym> (BFD_RELOC_LO16)
9182 daddu $tempreg,$tempreg,$at
9184 If $at is already in use, we use a path which is suboptimal
9185 on superscalar processors.
9186 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9187 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9189 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9191 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9193 For GP relative symbols in 64bit address space we can use
9194 the same sequence as in 32bit address space. */
9195 if (HAVE_64BIT_SYMBOLS
)
9197 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9198 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9200 relax_start (offset_expr
.X_add_symbol
);
9201 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9202 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9206 if (used_at
== 0 && mips_opts
.at
)
9208 macro_build (&offset_expr
, "lui", LUI_FMT
,
9209 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9210 macro_build (&offset_expr
, "lui", LUI_FMT
,
9211 AT
, BFD_RELOC_HI16_S
);
9212 macro_build (&offset_expr
, "daddiu", "t,r,j",
9213 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9214 macro_build (&offset_expr
, "daddiu", "t,r,j",
9215 AT
, AT
, BFD_RELOC_LO16
);
9216 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9217 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9222 macro_build (&offset_expr
, "lui", LUI_FMT
,
9223 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9224 macro_build (&offset_expr
, "daddiu", "t,r,j",
9225 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9226 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9227 macro_build (&offset_expr
, "daddiu", "t,r,j",
9228 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
9229 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9230 macro_build (&offset_expr
, "daddiu", "t,r,j",
9231 tempreg
, tempreg
, BFD_RELOC_LO16
);
9234 if (mips_relax
.sequence
)
9239 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9240 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9242 relax_start (offset_expr
.X_add_symbol
);
9243 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9244 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9247 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9248 as_bad (_("Offset too large"));
9249 macro_build_lui (&offset_expr
, tempreg
);
9250 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9251 tempreg
, tempreg
, BFD_RELOC_LO16
);
9252 if (mips_relax
.sequence
)
9256 else if (!mips_big_got
&& !HAVE_NEWABI
)
9258 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9260 /* If this is a reference to an external symbol, and there
9261 is no constant, we want
9262 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9263 or for lca or if tempreg is PIC_CALL_REG
9264 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9265 For a local symbol, we want
9266 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9268 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9270 If we have a small constant, and this is a reference to
9271 an external symbol, we want
9272 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9274 addiu $tempreg,$tempreg,<constant>
9275 For a local symbol, we want the same instruction
9276 sequence, but we output a BFD_RELOC_LO16 reloc on the
9279 If we have a large constant, and this is a reference to
9280 an external symbol, we want
9281 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9282 lui $at,<hiconstant>
9283 addiu $at,$at,<loconstant>
9284 addu $tempreg,$tempreg,$at
9285 For a local symbol, we want the same instruction
9286 sequence, but we output a BFD_RELOC_LO16 reloc on the
9290 if (offset_expr
.X_add_number
== 0)
9292 if (mips_pic
== SVR4_PIC
9294 && (call
|| tempreg
== PIC_CALL_REG
))
9295 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9297 relax_start (offset_expr
.X_add_symbol
);
9298 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9299 lw_reloc_type
, mips_gp_register
);
9302 /* We're going to put in an addu instruction using
9303 tempreg, so we may as well insert the nop right
9308 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9309 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9311 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9312 tempreg
, tempreg
, BFD_RELOC_LO16
);
9314 /* FIXME: If breg == 0, and the next instruction uses
9315 $tempreg, then if this variant case is used an extra
9316 nop will be generated. */
9318 else if (offset_expr
.X_add_number
>= -0x8000
9319 && offset_expr
.X_add_number
< 0x8000)
9321 load_got_offset (tempreg
, &offset_expr
);
9323 add_got_offset (tempreg
, &offset_expr
);
9327 expr1
.X_add_number
= offset_expr
.X_add_number
;
9328 offset_expr
.X_add_number
=
9329 SEXT_16BIT (offset_expr
.X_add_number
);
9330 load_got_offset (tempreg
, &offset_expr
);
9331 offset_expr
.X_add_number
= expr1
.X_add_number
;
9332 /* If we are going to add in a base register, and the
9333 target register and the base register are the same,
9334 then we are using AT as a temporary register. Since
9335 we want to load the constant into AT, we add our
9336 current AT (from the global offset table) and the
9337 register into the register now, and pretend we were
9338 not using a base register. */
9342 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9347 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
9351 else if (!mips_big_got
&& HAVE_NEWABI
)
9353 int add_breg_early
= 0;
9355 /* If this is a reference to an external, and there is no
9356 constant, or local symbol (*), with or without a
9358 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9359 or for lca or if tempreg is PIC_CALL_REG
9360 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9362 If we have a small constant, and this is a reference to
9363 an external symbol, we want
9364 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9365 addiu $tempreg,$tempreg,<constant>
9367 If we have a large constant, and this is a reference to
9368 an external symbol, we want
9369 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9370 lui $at,<hiconstant>
9371 addiu $at,$at,<loconstant>
9372 addu $tempreg,$tempreg,$at
9374 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9375 local symbols, even though it introduces an additional
9378 if (offset_expr
.X_add_number
)
9380 expr1
.X_add_number
= offset_expr
.X_add_number
;
9381 offset_expr
.X_add_number
= 0;
9383 relax_start (offset_expr
.X_add_symbol
);
9384 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9385 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9387 if (expr1
.X_add_number
>= -0x8000
9388 && expr1
.X_add_number
< 0x8000)
9390 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9391 tempreg
, tempreg
, BFD_RELOC_LO16
);
9393 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
9397 /* If we are going to add in a base register, and the
9398 target register and the base register are the same,
9399 then we are using AT as a temporary register. Since
9400 we want to load the constant into AT, we add our
9401 current AT (from the global offset table) and the
9402 register into the register now, and pretend we were
9403 not using a base register. */
9408 gas_assert (tempreg
== AT
);
9409 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9415 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9416 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9422 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9425 offset_expr
.X_add_number
= expr1
.X_add_number
;
9427 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9428 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9431 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9432 op
[0], tempreg
, breg
);
9438 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
9440 relax_start (offset_expr
.X_add_symbol
);
9441 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9442 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
9444 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9445 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9450 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9451 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9454 else if (mips_big_got
&& !HAVE_NEWABI
)
9457 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
9458 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
9459 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9461 /* This is the large GOT case. If this is a reference to an
9462 external symbol, and there is no constant, we want
9463 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9464 addu $tempreg,$tempreg,$gp
9465 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9466 or for lca or if tempreg is PIC_CALL_REG
9467 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9468 addu $tempreg,$tempreg,$gp
9469 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9470 For a local symbol, we want
9471 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9473 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9475 If we have a small constant, and this is a reference to
9476 an external symbol, we want
9477 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9478 addu $tempreg,$tempreg,$gp
9479 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9481 addiu $tempreg,$tempreg,<constant>
9482 For a local symbol, we want
9483 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9485 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
9487 If we have a large constant, and this is a reference to
9488 an external symbol, we want
9489 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9490 addu $tempreg,$tempreg,$gp
9491 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9492 lui $at,<hiconstant>
9493 addiu $at,$at,<loconstant>
9494 addu $tempreg,$tempreg,$at
9495 For a local symbol, we want
9496 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9497 lui $at,<hiconstant>
9498 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
9499 addu $tempreg,$tempreg,$at
9502 expr1
.X_add_number
= offset_expr
.X_add_number
;
9503 offset_expr
.X_add_number
= 0;
9504 relax_start (offset_expr
.X_add_symbol
);
9505 gpdelay
= reg_needs_delay (mips_gp_register
);
9506 if (expr1
.X_add_number
== 0 && breg
== 0
9507 && (call
|| tempreg
== PIC_CALL_REG
))
9509 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
9510 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
9512 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
9513 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9514 tempreg
, tempreg
, mips_gp_register
);
9515 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9516 tempreg
, lw_reloc_type
, tempreg
);
9517 if (expr1
.X_add_number
== 0)
9521 /* We're going to put in an addu instruction using
9522 tempreg, so we may as well insert the nop right
9527 else if (expr1
.X_add_number
>= -0x8000
9528 && expr1
.X_add_number
< 0x8000)
9531 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9532 tempreg
, tempreg
, BFD_RELOC_LO16
);
9538 /* If we are going to add in a base register, and the
9539 target register and the base register are the same,
9540 then we are using AT as a temporary register. Since
9541 we want to load the constant into AT, we add our
9542 current AT (from the global offset table) and the
9543 register into the register now, and pretend we were
9544 not using a base register. */
9549 gas_assert (tempreg
== AT
);
9551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9556 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9557 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
9561 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
9566 /* This is needed because this instruction uses $gp, but
9567 the first instruction on the main stream does not. */
9568 macro_build (NULL
, "nop", "");
9571 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9572 local_reloc_type
, mips_gp_register
);
9573 if (expr1
.X_add_number
>= -0x8000
9574 && expr1
.X_add_number
< 0x8000)
9577 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9578 tempreg
, tempreg
, BFD_RELOC_LO16
);
9579 /* FIXME: If add_number is 0, and there was no base
9580 register, the external symbol case ended with a load,
9581 so if the symbol turns out to not be external, and
9582 the next instruction uses tempreg, an unnecessary nop
9583 will be inserted. */
9589 /* We must add in the base register now, as in the
9590 external symbol case. */
9591 gas_assert (tempreg
== AT
);
9593 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9596 /* We set breg to 0 because we have arranged to add
9597 it in in both cases. */
9601 macro_build_lui (&expr1
, AT
);
9602 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9603 AT
, AT
, BFD_RELOC_LO16
);
9604 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9605 tempreg
, tempreg
, AT
);
9610 else if (mips_big_got
&& HAVE_NEWABI
)
9612 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
9613 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
9614 int add_breg_early
= 0;
9616 /* This is the large GOT case. If this is a reference to an
9617 external symbol, and there is no constant, we want
9618 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9619 add $tempreg,$tempreg,$gp
9620 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9621 or for lca or if tempreg is PIC_CALL_REG
9622 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9623 add $tempreg,$tempreg,$gp
9624 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9626 If we have a small constant, and this is a reference to
9627 an external symbol, we want
9628 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9629 add $tempreg,$tempreg,$gp
9630 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9631 addi $tempreg,$tempreg,<constant>
9633 If we have a large constant, and this is a reference to
9634 an external symbol, we want
9635 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9636 addu $tempreg,$tempreg,$gp
9637 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9638 lui $at,<hiconstant>
9639 addi $at,$at,<loconstant>
9640 add $tempreg,$tempreg,$at
9642 If we have NewABI, and we know it's a local symbol, we want
9643 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9644 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9645 otherwise we have to resort to GOT_HI16/GOT_LO16. */
9647 relax_start (offset_expr
.X_add_symbol
);
9649 expr1
.X_add_number
= offset_expr
.X_add_number
;
9650 offset_expr
.X_add_number
= 0;
9652 if (expr1
.X_add_number
== 0 && breg
== 0
9653 && (call
|| tempreg
== PIC_CALL_REG
))
9655 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
9656 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
9658 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
9659 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9660 tempreg
, tempreg
, mips_gp_register
);
9661 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9662 tempreg
, lw_reloc_type
, tempreg
);
9664 if (expr1
.X_add_number
== 0)
9666 else if (expr1
.X_add_number
>= -0x8000
9667 && expr1
.X_add_number
< 0x8000)
9669 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9670 tempreg
, tempreg
, BFD_RELOC_LO16
);
9672 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
9676 /* If we are going to add in a base register, and the
9677 target register and the base register are the same,
9678 then we are using AT as a temporary register. Since
9679 we want to load the constant into AT, we add our
9680 current AT (from the global offset table) and the
9681 register into the register now, and pretend we were
9682 not using a base register. */
9687 gas_assert (tempreg
== AT
);
9688 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9694 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9695 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
9700 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9703 offset_expr
.X_add_number
= expr1
.X_add_number
;
9704 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9705 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9706 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9707 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
9710 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9711 op
[0], tempreg
, breg
);
9721 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
9725 gas_assert (!mips_opts
.micromips
);
9726 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
9730 gas_assert (!mips_opts
.micromips
);
9731 macro_build (NULL
, "c2", "C", 0x02);
9735 gas_assert (!mips_opts
.micromips
);
9736 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
9740 gas_assert (!mips_opts
.micromips
);
9741 macro_build (NULL
, "c2", "C", 3);
9745 gas_assert (!mips_opts
.micromips
);
9746 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
9750 /* The j instruction may not be used in PIC code, since it
9751 requires an absolute address. We convert it to a b
9753 if (mips_pic
== NO_PIC
)
9754 macro_build (&offset_expr
, "j", "a");
9756 macro_build (&offset_expr
, "b", "p");
9759 /* The jal instructions must be handled as macros because when
9760 generating PIC code they expand to multi-instruction
9761 sequences. Normally they are simple instructions. */
9767 gas_assert (mips_opts
.micromips
);
9768 if (mips_opts
.insn32
)
9770 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9781 if (mips_pic
== NO_PIC
)
9783 s
= jals
? "jalrs" : "jalr";
9784 if (mips_opts
.micromips
9785 && !mips_opts
.insn32
9787 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9788 macro_build (NULL
, s
, "mj", op
[1]);
9790 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
9794 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
9795 && mips_cprestore_offset
>= 0);
9797 if (op
[1] != PIC_CALL_REG
)
9798 as_warn (_("MIPS PIC call to register other than $25"));
9800 s
= ((mips_opts
.micromips
9801 && !mips_opts
.insn32
9802 && (!mips_opts
.noreorder
|| cprestore
))
9803 ? "jalrs" : "jalr");
9804 if (mips_opts
.micromips
9805 && !mips_opts
.insn32
9807 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9808 macro_build (NULL
, s
, "mj", op
[1]);
9810 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
9811 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
9813 if (mips_cprestore_offset
< 0)
9814 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9817 if (!mips_frame_reg_valid
)
9819 as_warn (_("No .frame pseudo-op used in PIC code"));
9820 /* Quiet this warning. */
9821 mips_frame_reg_valid
= 1;
9823 if (!mips_cprestore_valid
)
9825 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9826 /* Quiet this warning. */
9827 mips_cprestore_valid
= 1;
9829 if (mips_opts
.noreorder
)
9830 macro_build (NULL
, "nop", "");
9831 expr1
.X_add_number
= mips_cprestore_offset
;
9832 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9835 HAVE_64BIT_ADDRESSES
);
9843 gas_assert (mips_opts
.micromips
);
9844 if (mips_opts
.insn32
)
9846 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9852 if (mips_pic
== NO_PIC
)
9853 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
9854 else if (mips_pic
== SVR4_PIC
)
9856 /* If this is a reference to an external symbol, and we are
9857 using a small GOT, we want
9858 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9862 lw $gp,cprestore($sp)
9863 The cprestore value is set using the .cprestore
9864 pseudo-op. If we are using a big GOT, we want
9865 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9867 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9871 lw $gp,cprestore($sp)
9872 If the symbol is not external, we want
9873 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9875 addiu $25,$25,<sym> (BFD_RELOC_LO16)
9878 lw $gp,cprestore($sp)
9880 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9881 sequences above, minus nops, unless the symbol is local,
9882 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9888 relax_start (offset_expr
.X_add_symbol
);
9889 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9890 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9893 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9894 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
9900 relax_start (offset_expr
.X_add_symbol
);
9901 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9902 BFD_RELOC_MIPS_CALL_HI16
);
9903 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9904 PIC_CALL_REG
, mips_gp_register
);
9905 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9906 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9909 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9910 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
9912 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9913 PIC_CALL_REG
, PIC_CALL_REG
,
9914 BFD_RELOC_MIPS_GOT_OFST
);
9918 macro_build_jalr (&offset_expr
, 0);
9922 relax_start (offset_expr
.X_add_symbol
);
9925 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9926 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9935 gpdelay
= reg_needs_delay (mips_gp_register
);
9936 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9937 BFD_RELOC_MIPS_CALL_HI16
);
9938 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9939 PIC_CALL_REG
, mips_gp_register
);
9940 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9941 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9946 macro_build (NULL
, "nop", "");
9948 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9949 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
9952 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9953 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
9955 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
9957 if (mips_cprestore_offset
< 0)
9958 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9961 if (!mips_frame_reg_valid
)
9963 as_warn (_("No .frame pseudo-op used in PIC code"));
9964 /* Quiet this warning. */
9965 mips_frame_reg_valid
= 1;
9967 if (!mips_cprestore_valid
)
9969 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9970 /* Quiet this warning. */
9971 mips_cprestore_valid
= 1;
9973 if (mips_opts
.noreorder
)
9974 macro_build (NULL
, "nop", "");
9975 expr1
.X_add_number
= mips_cprestore_offset
;
9976 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9979 HAVE_64BIT_ADDRESSES
);
9983 else if (mips_pic
== VXWORKS_PIC
)
9984 as_bad (_("Non-PIC jump used in PIC library"));
10091 gas_assert (!mips_opts
.micromips
);
10094 /* Itbl support may require additional care here. */
10100 /* Itbl support may require additional care here. */
10106 offbits
= (mips_opts
.micromips
? 12 : 16);
10107 /* Itbl support may require additional care here. */
10111 gas_assert (!mips_opts
.micromips
);
10114 /* Itbl support may require additional care here. */
10120 offbits
= (mips_opts
.micromips
? 12 : 16);
10125 offbits
= (mips_opts
.micromips
? 12 : 16);
10130 /* Itbl support may require additional care here. */
10136 offbits
= (mips_opts
.micromips
? 12 : 16);
10137 /* Itbl support may require additional care here. */
10143 /* Itbl support may require additional care here. */
10149 /* Itbl support may require additional care here. */
10155 offbits
= (mips_opts
.micromips
? 12 : 16);
10160 offbits
= (mips_opts
.micromips
? 12 : 16);
10165 offbits
= (mips_opts
.micromips
? 12 : 16);
10170 offbits
= (mips_opts
.micromips
? 12 : 16);
10175 offbits
= (mips_opts
.micromips
? 12 : 16);
10178 gas_assert (mips_opts
.micromips
);
10185 gas_assert (mips_opts
.micromips
);
10192 gas_assert (mips_opts
.micromips
);
10198 gas_assert (mips_opts
.micromips
);
10205 /* We don't want to use $0 as tempreg. */
10206 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
10209 tempreg
= op
[0] + lp
;
10225 gas_assert (!mips_opts
.micromips
);
10228 /* Itbl support may require additional care here. */
10234 /* Itbl support may require additional care here. */
10240 offbits
= (mips_opts
.micromips
? 12 : 16);
10241 /* Itbl support may require additional care here. */
10245 gas_assert (!mips_opts
.micromips
);
10248 /* Itbl support may require additional care here. */
10254 offbits
= (mips_opts
.micromips
? 12 : 16);
10259 offbits
= (mips_opts
.micromips
? 12 : 16);
10264 offbits
= (mips_opts
.micromips
? 12 : 16);
10269 offbits
= (mips_opts
.micromips
? 12 : 16);
10273 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
10274 offbits
= (mips_opts
.micromips
? 12 : 16);
10283 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
10284 offbits
= (mips_opts
.micromips
? 12 : 16);
10295 /* Itbl support may require additional care here. */
10300 offbits
= (mips_opts
.micromips
? 12 : 16);
10301 /* Itbl support may require additional care here. */
10307 /* Itbl support may require additional care here. */
10311 gas_assert (!mips_opts
.micromips
);
10314 /* Itbl support may require additional care here. */
10320 offbits
= (mips_opts
.micromips
? 12 : 16);
10325 offbits
= (mips_opts
.micromips
? 12 : 16);
10328 gas_assert (mips_opts
.micromips
);
10334 gas_assert (mips_opts
.micromips
);
10340 gas_assert (mips_opts
.micromips
);
10346 gas_assert (mips_opts
.micromips
);
10355 if (small_offset_p (0, align
, 16))
10357 /* The first case exists for M_LD_AB and M_SD_AB, which are
10358 macros for o32 but which should act like normal instructions
10361 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
10362 offset_reloc
[1], offset_reloc
[2], breg
);
10363 else if (small_offset_p (0, align
, offbits
))
10366 macro_build (NULL
, s
, fmt
, op
[0], breg
);
10368 macro_build (NULL
, s
, fmt
, op
[0],
10369 (int) offset_expr
.X_add_number
, breg
);
10375 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10376 tempreg
, breg
, -1, offset_reloc
[0],
10377 offset_reloc
[1], offset_reloc
[2]);
10379 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
10381 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
10389 if (offset_expr
.X_op
!= O_constant
10390 && offset_expr
.X_op
!= O_symbol
)
10392 as_bad (_("Expression too complex"));
10393 offset_expr
.X_op
= O_constant
;
10396 if (HAVE_32BIT_ADDRESSES
10397 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10401 sprintf_vma (value
, offset_expr
.X_add_number
);
10402 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
10405 /* A constant expression in PIC code can be handled just as it
10406 is in non PIC code. */
10407 if (offset_expr
.X_op
== O_constant
)
10409 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
10410 offbits
== 0 ? 16 : offbits
);
10411 offset_expr
.X_add_number
-= expr1
.X_add_number
;
10413 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
10415 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10416 tempreg
, tempreg
, breg
);
10419 if (offset_expr
.X_add_number
!= 0)
10420 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
10421 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
10422 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
10424 else if (offbits
== 16)
10425 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
10427 macro_build (NULL
, s
, fmt
, op
[0],
10428 (int) offset_expr
.X_add_number
, tempreg
);
10430 else if (offbits
!= 16)
10432 /* The offset field is too narrow to be used for a low-part
10433 relocation, so load the whole address into the auxillary
10435 load_address (tempreg
, &offset_expr
, &used_at
);
10437 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10438 tempreg
, tempreg
, breg
);
10440 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
10442 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
10444 else if (mips_pic
== NO_PIC
)
10446 /* If this is a reference to a GP relative symbol, and there
10447 is no base register, we want
10448 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
10449 Otherwise, if there is no base register, we want
10450 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10451 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10452 If we have a constant, we need two instructions anyhow,
10453 so we always use the latter form.
10455 If we have a base register, and this is a reference to a
10456 GP relative symbol, we want
10457 addu $tempreg,$breg,$gp
10458 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
10460 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10461 addu $tempreg,$tempreg,$breg
10462 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10463 With a constant we always use the latter case.
10465 With 64bit address space and no base register and $at usable,
10467 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10468 lui $at,<sym> (BFD_RELOC_HI16_S)
10469 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10472 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10473 If we have a base register, we want
10474 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10475 lui $at,<sym> (BFD_RELOC_HI16_S)
10476 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10480 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10482 Without $at we can't generate the optimal path for superscalar
10483 processors here since this would require two temporary registers.
10484 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10485 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10487 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10489 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10490 If we have a base register, we want
10491 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10492 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10494 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10496 daddu $tempreg,$tempreg,$breg
10497 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10499 For GP relative symbols in 64bit address space we can use
10500 the same sequence as in 32bit address space. */
10501 if (HAVE_64BIT_SYMBOLS
)
10503 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10504 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10506 relax_start (offset_expr
.X_add_symbol
);
10509 macro_build (&offset_expr
, s
, fmt
, op
[0],
10510 BFD_RELOC_GPREL16
, mips_gp_register
);
10514 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10515 tempreg
, breg
, mips_gp_register
);
10516 macro_build (&offset_expr
, s
, fmt
, op
[0],
10517 BFD_RELOC_GPREL16
, tempreg
);
10522 if (used_at
== 0 && mips_opts
.at
)
10524 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10525 BFD_RELOC_MIPS_HIGHEST
);
10526 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
10528 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10529 tempreg
, BFD_RELOC_MIPS_HIGHER
);
10531 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
10532 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10533 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10534 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
10540 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10541 BFD_RELOC_MIPS_HIGHEST
);
10542 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10543 tempreg
, BFD_RELOC_MIPS_HIGHER
);
10544 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10545 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10546 tempreg
, BFD_RELOC_HI16_S
);
10547 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10549 macro_build (NULL
, "daddu", "d,v,t",
10550 tempreg
, tempreg
, breg
);
10551 macro_build (&offset_expr
, s
, fmt
, op
[0],
10552 BFD_RELOC_LO16
, tempreg
);
10555 if (mips_relax
.sequence
)
10562 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10563 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10565 relax_start (offset_expr
.X_add_symbol
);
10566 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
10570 macro_build_lui (&offset_expr
, tempreg
);
10571 macro_build (&offset_expr
, s
, fmt
, op
[0],
10572 BFD_RELOC_LO16
, tempreg
);
10573 if (mips_relax
.sequence
)
10578 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10579 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10581 relax_start (offset_expr
.X_add_symbol
);
10582 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10583 tempreg
, breg
, mips_gp_register
);
10584 macro_build (&offset_expr
, s
, fmt
, op
[0],
10585 BFD_RELOC_GPREL16
, tempreg
);
10588 macro_build_lui (&offset_expr
, tempreg
);
10589 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10590 tempreg
, tempreg
, breg
);
10591 macro_build (&offset_expr
, s
, fmt
, op
[0],
10592 BFD_RELOC_LO16
, tempreg
);
10593 if (mips_relax
.sequence
)
10597 else if (!mips_big_got
)
10599 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10601 /* If this is a reference to an external symbol, we want
10602 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10604 <op> op[0],0($tempreg)
10606 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10608 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10609 <op> op[0],0($tempreg)
10611 For NewABI, we want
10612 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10613 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
10615 If there is a base register, we add it to $tempreg before
10616 the <op>. If there is a constant, we stick it in the
10617 <op> instruction. We don't handle constants larger than
10618 16 bits, because we have no way to load the upper 16 bits
10619 (actually, we could handle them for the subset of cases
10620 in which we are not using $at). */
10621 gas_assert (offset_expr
.X_op
== O_symbol
);
10624 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10625 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10627 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10628 tempreg
, tempreg
, breg
);
10629 macro_build (&offset_expr
, s
, fmt
, op
[0],
10630 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
10633 expr1
.X_add_number
= offset_expr
.X_add_number
;
10634 offset_expr
.X_add_number
= 0;
10635 if (expr1
.X_add_number
< -0x8000
10636 || expr1
.X_add_number
>= 0x8000)
10637 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10638 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10639 lw_reloc_type
, mips_gp_register
);
10641 relax_start (offset_expr
.X_add_symbol
);
10643 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10644 tempreg
, BFD_RELOC_LO16
);
10647 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10648 tempreg
, tempreg
, breg
);
10649 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
10651 else if (mips_big_got
&& !HAVE_NEWABI
)
10655 /* If this is a reference to an external symbol, we want
10656 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10657 addu $tempreg,$tempreg,$gp
10658 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10659 <op> op[0],0($tempreg)
10661 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10663 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10664 <op> op[0],0($tempreg)
10665 If there is a base register, we add it to $tempreg before
10666 the <op>. If there is a constant, we stick it in the
10667 <op> instruction. We don't handle constants larger than
10668 16 bits, because we have no way to load the upper 16 bits
10669 (actually, we could handle them for the subset of cases
10670 in which we are not using $at). */
10671 gas_assert (offset_expr
.X_op
== O_symbol
);
10672 expr1
.X_add_number
= offset_expr
.X_add_number
;
10673 offset_expr
.X_add_number
= 0;
10674 if (expr1
.X_add_number
< -0x8000
10675 || expr1
.X_add_number
>= 0x8000)
10676 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10677 gpdelay
= reg_needs_delay (mips_gp_register
);
10678 relax_start (offset_expr
.X_add_symbol
);
10679 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10680 BFD_RELOC_MIPS_GOT_HI16
);
10681 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
10683 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10684 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
10687 macro_build (NULL
, "nop", "");
10688 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10689 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10691 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10692 tempreg
, BFD_RELOC_LO16
);
10696 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10697 tempreg
, tempreg
, breg
);
10698 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
10700 else if (mips_big_got
&& HAVE_NEWABI
)
10702 /* If this is a reference to an external symbol, we want
10703 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10704 add $tempreg,$tempreg,$gp
10705 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10706 <op> op[0],<ofst>($tempreg)
10707 Otherwise, for local symbols, we want:
10708 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10709 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
10710 gas_assert (offset_expr
.X_op
== O_symbol
);
10711 expr1
.X_add_number
= offset_expr
.X_add_number
;
10712 offset_expr
.X_add_number
= 0;
10713 if (expr1
.X_add_number
< -0x8000
10714 || expr1
.X_add_number
>= 0x8000)
10715 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10716 relax_start (offset_expr
.X_add_symbol
);
10717 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10718 BFD_RELOC_MIPS_GOT_HI16
);
10719 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
10721 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10722 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
10724 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10725 tempreg
, tempreg
, breg
);
10726 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
10729 offset_expr
.X_add_number
= expr1
.X_add_number
;
10730 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10731 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10733 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10734 tempreg
, tempreg
, breg
);
10735 macro_build (&offset_expr
, s
, fmt
, op
[0],
10736 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
10745 gas_assert (mips_opts
.micromips
);
10746 gas_assert (mips_opts
.insn32
);
10747 start_noreorder ();
10748 macro_build (NULL
, "jr", "s", RA
);
10749 expr1
.X_add_number
= op
[0] << 2;
10750 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
10755 gas_assert (mips_opts
.micromips
);
10756 gas_assert (mips_opts
.insn32
);
10757 macro_build (NULL
, "jr", "s", op
[0]);
10758 if (mips_opts
.noreorder
)
10759 macro_build (NULL
, "nop", "");
10764 load_register (op
[0], &imm_expr
, 0);
10768 load_register (op
[0], &imm_expr
, 1);
10772 if (imm_expr
.X_op
== O_constant
)
10775 load_register (AT
, &imm_expr
, 0);
10776 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
10781 gas_assert (offset_expr
.X_op
== O_symbol
10782 && strcmp (segment_name (S_GET_SEGMENT
10783 (offset_expr
.X_add_symbol
)),
10785 && offset_expr
.X_add_number
== 0);
10786 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
10787 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
10792 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
10793 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
10794 order 32 bits of the value and the low order 32 bits are either
10795 zero or in OFFSET_EXPR. */
10796 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10798 if (HAVE_64BIT_GPRS
)
10799 load_register (op
[0], &imm_expr
, 1);
10804 if (target_big_endian
)
10816 load_register (hreg
, &imm_expr
, 0);
10819 if (offset_expr
.X_op
== O_absent
)
10820 move_register (lreg
, 0);
10823 gas_assert (offset_expr
.X_op
== O_constant
);
10824 load_register (lreg
, &offset_expr
, 0);
10831 /* We know that sym is in the .rdata section. First we get the
10832 upper 16 bits of the address. */
10833 if (mips_pic
== NO_PIC
)
10835 macro_build_lui (&offset_expr
, AT
);
10840 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10841 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10845 /* Now we load the register(s). */
10846 if (HAVE_64BIT_GPRS
)
10849 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
10850 BFD_RELOC_LO16
, AT
);
10855 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
10856 BFD_RELOC_LO16
, AT
);
10859 /* FIXME: How in the world do we deal with the possible
10861 offset_expr
.X_add_number
+= 4;
10862 macro_build (&offset_expr
, "lw", "t,o(b)",
10863 op
[0] + 1, BFD_RELOC_LO16
, AT
);
10869 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10870 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10871 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10872 the value and the low order 32 bits are either zero or in
10874 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10877 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
10878 if (HAVE_64BIT_FPRS
)
10880 gas_assert (HAVE_64BIT_GPRS
);
10881 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
10885 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
10886 if (offset_expr
.X_op
== O_absent
)
10887 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
10890 gas_assert (offset_expr
.X_op
== O_constant
);
10891 load_register (AT
, &offset_expr
, 0);
10892 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
10898 gas_assert (offset_expr
.X_op
== O_symbol
10899 && offset_expr
.X_add_number
== 0);
10900 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
10901 if (strcmp (s
, ".lit8") == 0)
10903 op
[2] = mips_gp_register
;
10904 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
10905 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10906 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10910 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
10912 if (mips_pic
!= NO_PIC
)
10913 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10914 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10917 /* FIXME: This won't work for a 64 bit address. */
10918 macro_build_lui (&offset_expr
, AT
);
10922 offset_reloc
[0] = BFD_RELOC_LO16
;
10923 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10924 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10931 * The MIPS assembler seems to check for X_add_number not
10932 * being double aligned and generating:
10933 * lui at,%hi(foo+1)
10935 * addiu at,at,%lo(foo+1)
10938 * But, the resulting address is the same after relocation so why
10939 * generate the extra instruction?
10941 /* Itbl support may require additional care here. */
10944 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10953 gas_assert (!mips_opts
.micromips
);
10954 /* Itbl support may require additional care here. */
10957 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10977 if (HAVE_64BIT_GPRS
)
10987 if (HAVE_64BIT_GPRS
)
10995 /* Even on a big endian machine $fn comes before $fn+1. We have
10996 to adjust when loading from memory. We set coproc if we must
10997 load $fn+1 first. */
10998 /* Itbl support may require additional care here. */
10999 if (!target_big_endian
)
11003 if (small_offset_p (0, align
, 16))
11006 if (!small_offset_p (4, align
, 16))
11008 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
11009 -1, offset_reloc
[0], offset_reloc
[1],
11011 expr1
.X_add_number
= 0;
11015 offset_reloc
[0] = BFD_RELOC_LO16
;
11016 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11017 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11019 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
11021 ep
->X_add_number
+= 4;
11022 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
11023 offset_reloc
[1], offset_reloc
[2], breg
);
11024 ep
->X_add_number
-= 4;
11025 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11026 offset_reloc
[1], offset_reloc
[2], breg
);
11030 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
11031 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11033 ep
->X_add_number
+= 4;
11034 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
11035 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11041 if (offset_expr
.X_op
!= O_symbol
11042 && offset_expr
.X_op
!= O_constant
)
11044 as_bad (_("Expression too complex"));
11045 offset_expr
.X_op
= O_constant
;
11048 if (HAVE_32BIT_ADDRESSES
11049 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11053 sprintf_vma (value
, offset_expr
.X_add_number
);
11054 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
11057 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
11059 /* If this is a reference to a GP relative symbol, we want
11060 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11061 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11062 If we have a base register, we use this
11064 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11065 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11066 If this is not a GP relative symbol, we want
11067 lui $at,<sym> (BFD_RELOC_HI16_S)
11068 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11069 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11070 If there is a base register, we add it to $at after the
11071 lui instruction. If there is a constant, we always use
11073 if (offset_expr
.X_op
== O_symbol
11074 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11075 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11077 relax_start (offset_expr
.X_add_symbol
);
11080 tempreg
= mips_gp_register
;
11084 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11085 AT
, breg
, mips_gp_register
);
11090 /* Itbl support may require additional care here. */
11091 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11092 BFD_RELOC_GPREL16
, tempreg
);
11093 offset_expr
.X_add_number
+= 4;
11095 /* Set mips_optimize to 2 to avoid inserting an
11097 hold_mips_optimize
= mips_optimize
;
11099 /* Itbl support may require additional care here. */
11100 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11101 BFD_RELOC_GPREL16
, tempreg
);
11102 mips_optimize
= hold_mips_optimize
;
11106 offset_expr
.X_add_number
-= 4;
11109 if (offset_high_part (offset_expr
.X_add_number
, 16)
11110 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
11112 load_address (AT
, &offset_expr
, &used_at
);
11113 offset_expr
.X_op
= O_constant
;
11114 offset_expr
.X_add_number
= 0;
11117 macro_build_lui (&offset_expr
, AT
);
11119 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11120 /* Itbl support may require additional care here. */
11121 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11122 BFD_RELOC_LO16
, AT
);
11123 /* FIXME: How do we handle overflow here? */
11124 offset_expr
.X_add_number
+= 4;
11125 /* Itbl support may require additional care here. */
11126 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11127 BFD_RELOC_LO16
, AT
);
11128 if (mips_relax
.sequence
)
11131 else if (!mips_big_got
)
11133 /* If this is a reference to an external symbol, we want
11134 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11137 <op> op[0]+1,4($at)
11139 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11141 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11142 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11143 If there is a base register we add it to $at before the
11144 lwc1 instructions. If there is a constant we include it
11145 in the lwc1 instructions. */
11147 expr1
.X_add_number
= offset_expr
.X_add_number
;
11148 if (expr1
.X_add_number
< -0x8000
11149 || expr1
.X_add_number
>= 0x8000 - 4)
11150 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11151 load_got_offset (AT
, &offset_expr
);
11154 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11156 /* Set mips_optimize to 2 to avoid inserting an undesired
11158 hold_mips_optimize
= mips_optimize
;
11161 /* Itbl support may require additional care here. */
11162 relax_start (offset_expr
.X_add_symbol
);
11163 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11164 BFD_RELOC_LO16
, AT
);
11165 expr1
.X_add_number
+= 4;
11166 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11167 BFD_RELOC_LO16
, AT
);
11169 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11170 BFD_RELOC_LO16
, AT
);
11171 offset_expr
.X_add_number
+= 4;
11172 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11173 BFD_RELOC_LO16
, AT
);
11176 mips_optimize
= hold_mips_optimize
;
11178 else if (mips_big_got
)
11182 /* If this is a reference to an external symbol, we want
11183 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11185 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11188 <op> op[0]+1,4($at)
11190 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11192 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11193 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11194 If there is a base register we add it to $at before the
11195 lwc1 instructions. If there is a constant we include it
11196 in the lwc1 instructions. */
11198 expr1
.X_add_number
= offset_expr
.X_add_number
;
11199 offset_expr
.X_add_number
= 0;
11200 if (expr1
.X_add_number
< -0x8000
11201 || expr1
.X_add_number
>= 0x8000 - 4)
11202 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11203 gpdelay
= reg_needs_delay (mips_gp_register
);
11204 relax_start (offset_expr
.X_add_symbol
);
11205 macro_build (&offset_expr
, "lui", LUI_FMT
,
11206 AT
, BFD_RELOC_MIPS_GOT_HI16
);
11207 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11208 AT
, AT
, mips_gp_register
);
11209 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11210 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
11213 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11214 /* Itbl support may require additional care here. */
11215 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11216 BFD_RELOC_LO16
, AT
);
11217 expr1
.X_add_number
+= 4;
11219 /* Set mips_optimize to 2 to avoid inserting an undesired
11221 hold_mips_optimize
= mips_optimize
;
11223 /* Itbl support may require additional care here. */
11224 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11225 BFD_RELOC_LO16
, AT
);
11226 mips_optimize
= hold_mips_optimize
;
11227 expr1
.X_add_number
-= 4;
11230 offset_expr
.X_add_number
= expr1
.X_add_number
;
11232 macro_build (NULL
, "nop", "");
11233 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11234 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11237 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11238 /* Itbl support may require additional care here. */
11239 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11240 BFD_RELOC_LO16
, AT
);
11241 offset_expr
.X_add_number
+= 4;
11243 /* Set mips_optimize to 2 to avoid inserting an undesired
11245 hold_mips_optimize
= mips_optimize
;
11247 /* Itbl support may require additional care here. */
11248 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11249 BFD_RELOC_LO16
, AT
);
11250 mips_optimize
= hold_mips_optimize
;
11269 /* New code added to support COPZ instructions.
11270 This code builds table entries out of the macros in mip_opcodes.
11271 R4000 uses interlocks to handle coproc delays.
11272 Other chips (like the R3000) require nops to be inserted for delays.
11274 FIXME: Currently, we require that the user handle delays.
11275 In order to fill delay slots for non-interlocked chips,
11276 we must have a way to specify delays based on the coprocessor.
11277 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11278 What are the side-effects of the cop instruction?
11279 What cache support might we have and what are its effects?
11280 Both coprocessor & memory require delays. how long???
11281 What registers are read/set/modified?
11283 If an itbl is provided to interpret cop instructions,
11284 this knowledge can be encoded in the itbl spec. */
11298 gas_assert (!mips_opts
.micromips
);
11299 /* For now we just do C (same as Cz). The parameter will be
11300 stored in insn_opcode by mips_ip. */
11301 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11305 move_register (op
[0], op
[1]);
11309 gas_assert (mips_opts
.micromips
);
11310 gas_assert (mips_opts
.insn32
);
11311 move_register (micromips_to_32_reg_h_map1
[op
[0]],
11312 micromips_to_32_reg_m_map
[op
[1]]);
11313 move_register (micromips_to_32_reg_h_map2
[op
[0]],
11314 micromips_to_32_reg_n_map
[op
[2]]);
11320 if (mips_opts
.arch
== CPU_R5900
)
11321 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
11325 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
11326 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11333 /* The MIPS assembler some times generates shifts and adds. I'm
11334 not trying to be that fancy. GCC should do this for us
11337 load_register (AT
, &imm_expr
, dbl
);
11338 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
11339 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11352 start_noreorder ();
11355 load_register (AT
, &imm_expr
, dbl
);
11356 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
11357 op
[1], imm
? AT
: op
[2]);
11358 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11359 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
11360 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11362 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
11365 if (mips_opts
.micromips
)
11366 micromips_label_expr (&label_expr
);
11368 label_expr
.X_add_number
= 8;
11369 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
11370 macro_build (NULL
, "nop", "");
11371 macro_build (NULL
, "break", BRK_FMT
, 6);
11372 if (mips_opts
.micromips
)
11373 micromips_add_label ();
11376 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11389 start_noreorder ();
11392 load_register (AT
, &imm_expr
, dbl
);
11393 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
11394 op
[1], imm
? AT
: op
[2]);
11395 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11396 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11398 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
11401 if (mips_opts
.micromips
)
11402 micromips_label_expr (&label_expr
);
11404 label_expr
.X_add_number
= 8;
11405 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
11406 macro_build (NULL
, "nop", "");
11407 macro_build (NULL
, "break", BRK_FMT
, 6);
11408 if (mips_opts
.micromips
)
11409 micromips_add_label ();
11415 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11417 if (op
[0] == op
[1])
11424 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
11425 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
11429 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
11430 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
11431 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
11432 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11436 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11438 if (op
[0] == op
[1])
11445 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
11446 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
11450 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
11451 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
11452 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
11453 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11462 if (imm_expr
.X_op
!= O_constant
)
11463 as_bad (_("Improper rotate count"));
11464 rot
= imm_expr
.X_add_number
& 0x3f;
11465 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11467 rot
= (64 - rot
) & 0x3f;
11469 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
11471 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
11476 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
11479 l
= (rot
< 0x20) ? "dsll" : "dsll32";
11480 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
11483 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
11484 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
11485 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11493 if (imm_expr
.X_op
!= O_constant
)
11494 as_bad (_("Improper rotate count"));
11495 rot
= imm_expr
.X_add_number
& 0x1f;
11496 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11498 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
11499 (32 - rot
) & 0x1f);
11504 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
11508 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
11509 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
11510 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11515 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11517 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
11521 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
11522 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
11523 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
11524 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11528 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11530 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
11534 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
11535 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
11536 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
11537 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11546 if (imm_expr
.X_op
!= O_constant
)
11547 as_bad (_("Improper rotate count"));
11548 rot
= imm_expr
.X_add_number
& 0x3f;
11549 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11552 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
11554 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
11559 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
11562 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
11563 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
11566 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
11567 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
11568 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11576 if (imm_expr
.X_op
!= O_constant
)
11577 as_bad (_("Improper rotate count"));
11578 rot
= imm_expr
.X_add_number
& 0x1f;
11579 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11581 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
11586 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
11590 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
11591 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
11592 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11598 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
11599 else if (op
[2] == 0)
11600 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
11603 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
11604 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
11609 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
11611 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
11616 as_warn (_("Instruction %s: result is always false"),
11617 ip
->insn_mo
->name
);
11618 move_register (op
[0], 0);
11621 if (CPU_HAS_SEQ (mips_opts
.arch
)
11622 && -512 <= imm_expr
.X_add_number
11623 && imm_expr
.X_add_number
< 512)
11625 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
11626 (int) imm_expr
.X_add_number
);
11629 if (imm_expr
.X_op
== O_constant
11630 && imm_expr
.X_add_number
>= 0
11631 && imm_expr
.X_add_number
< 0x10000)
11632 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
11633 else if (imm_expr
.X_op
== O_constant
11634 && imm_expr
.X_add_number
> -0x8000
11635 && imm_expr
.X_add_number
< 0)
11637 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11638 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
11639 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
11641 else if (CPU_HAS_SEQ (mips_opts
.arch
))
11644 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11645 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
11650 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11651 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
11654 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
11657 case M_SGE
: /* X >= Y <==> not (X < Y) */
11663 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
11664 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
11667 case M_SGE_I
: /* X >= I <==> not (X < I) */
11669 if (imm_expr
.X_op
== O_constant
11670 && imm_expr
.X_add_number
>= -0x8000
11671 && imm_expr
.X_add_number
< 0x8000)
11672 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
11673 op
[0], op
[1], BFD_RELOC_LO16
);
11676 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11677 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
11681 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
11684 case M_SGT
: /* X > Y <==> Y < X */
11690 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
11693 case M_SGT_I
: /* X > I <==> I < X */
11700 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11701 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
11704 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
11710 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
11711 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
11714 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
11721 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11722 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
11723 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
11727 if (imm_expr
.X_op
== O_constant
11728 && imm_expr
.X_add_number
>= -0x8000
11729 && imm_expr
.X_add_number
< 0x8000)
11731 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
11736 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11737 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
11741 if (imm_expr
.X_op
== O_constant
11742 && imm_expr
.X_add_number
>= -0x8000
11743 && imm_expr
.X_add_number
< 0x8000)
11745 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
11750 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11751 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
11756 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
11757 else if (op
[2] == 0)
11758 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
11761 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
11762 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
11767 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
11769 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
11774 as_warn (_("Instruction %s: result is always true"),
11775 ip
->insn_mo
->name
);
11776 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
11777 op
[0], 0, BFD_RELOC_LO16
);
11780 if (CPU_HAS_SEQ (mips_opts
.arch
)
11781 && -512 <= imm_expr
.X_add_number
11782 && imm_expr
.X_add_number
< 512)
11784 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
11785 (int) imm_expr
.X_add_number
);
11788 if (imm_expr
.X_op
== O_constant
11789 && imm_expr
.X_add_number
>= 0
11790 && imm_expr
.X_add_number
< 0x10000)
11792 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
11795 else if (imm_expr
.X_op
== O_constant
11796 && imm_expr
.X_add_number
> -0x8000
11797 && imm_expr
.X_add_number
< 0)
11799 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11800 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
11801 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
11803 else if (CPU_HAS_SEQ (mips_opts
.arch
))
11806 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11807 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
11812 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11813 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
11816 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
11831 if (!mips_opts
.micromips
)
11833 if (imm_expr
.X_op
== O_constant
11834 && imm_expr
.X_add_number
> -0x200
11835 && imm_expr
.X_add_number
<= 0x200)
11837 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1], -imm_expr
.X_add_number
);
11846 if (imm_expr
.X_op
== O_constant
11847 && imm_expr
.X_add_number
> -0x8000
11848 && imm_expr
.X_add_number
<= 0x8000)
11850 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11851 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
11856 load_register (AT
, &imm_expr
, dbl
);
11857 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
11879 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11880 macro_build (NULL
, s
, "s,t", op
[0], AT
);
11885 gas_assert (!mips_opts
.micromips
);
11886 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
11890 * Is the double cfc1 instruction a bug in the mips assembler;
11891 * or is there a reason for it?
11893 start_noreorder ();
11894 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
11895 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
11896 macro_build (NULL
, "nop", "");
11897 expr1
.X_add_number
= 3;
11898 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
11899 expr1
.X_add_number
= 2;
11900 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
11901 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
11902 macro_build (NULL
, "nop", "");
11903 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
11905 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
11906 macro_build (NULL
, "nop", "");
11923 offbits
= (mips_opts
.micromips
? 12 : 16);
11929 offbits
= (mips_opts
.micromips
? 12 : 16);
11941 offbits
= (mips_opts
.micromips
? 12 : 16);
11948 offbits
= (mips_opts
.micromips
? 12 : 16);
11954 large_offset
= !small_offset_p (off
, align
, offbits
);
11956 expr1
.X_add_number
= 0;
11961 if (small_offset_p (0, align
, 16))
11962 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
11963 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11966 load_address (tempreg
, ep
, &used_at
);
11968 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11969 tempreg
, tempreg
, breg
);
11971 offset_reloc
[0] = BFD_RELOC_LO16
;
11972 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11973 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11978 else if (!ust
&& op
[0] == breg
)
11989 if (!target_big_endian
)
11990 ep
->X_add_number
+= off
;
11992 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
11994 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
11995 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11997 if (!target_big_endian
)
11998 ep
->X_add_number
-= off
;
12000 ep
->X_add_number
+= off
;
12002 macro_build (NULL
, s2
, "t,~(b)",
12003 tempreg
, (int) ep
->X_add_number
, breg
);
12005 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12006 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12008 /* If necessary, move the result in tempreg to the final destination. */
12009 if (!ust
&& op
[0] != tempreg
)
12011 /* Protect second load's delay slot. */
12013 move_register (op
[0], tempreg
);
12019 if (target_big_endian
== ust
)
12020 ep
->X_add_number
+= off
;
12021 tempreg
= ust
|| large_offset
? op
[0] : AT
;
12022 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12023 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12025 /* For halfword transfers we need a temporary register to shuffle
12026 bytes. Unfortunately for M_USH_A we have none available before
12027 the next store as AT holds the base address. We deal with this
12028 case by clobbering TREG and then restoring it as with ULH. */
12029 tempreg
= ust
== large_offset
? op
[0] : AT
;
12031 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
12033 if (target_big_endian
== ust
)
12034 ep
->X_add_number
-= off
;
12036 ep
->X_add_number
+= off
;
12037 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12038 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12040 /* For M_USH_A re-retrieve the LSB. */
12041 if (ust
&& large_offset
)
12043 if (target_big_endian
)
12044 ep
->X_add_number
+= off
;
12046 ep
->X_add_number
-= off
;
12047 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
12048 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
12050 /* For ULH and M_USH_A OR the LSB in. */
12051 if (!ust
|| large_offset
)
12053 tempreg
= !large_offset
? AT
: op
[0];
12054 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
12055 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12060 /* FIXME: Check if this is one of the itbl macros, since they
12061 are added dynamically. */
12062 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
12065 if (!mips_opts
.at
&& used_at
)
12066 as_bad (_("Macro used $at after \".set noat\""));
12069 /* Implement macros in mips16 mode. */
12072 mips16_macro (struct mips_cl_insn
*ip
)
12074 const struct mips_operand_array
*operands
;
12079 const char *s
, *s2
, *s3
;
12080 unsigned int op
[MAX_OPERANDS
];
12083 mask
= ip
->insn_mo
->mask
;
12085 operands
= insn_operands (ip
);
12086 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12087 if (operands
->operand
[i
])
12088 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
12092 expr1
.X_op
= O_constant
;
12093 expr1
.X_op_symbol
= NULL
;
12094 expr1
.X_add_symbol
= NULL
;
12095 expr1
.X_add_number
= 1;
12114 start_noreorder ();
12115 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
12116 expr1
.X_add_number
= 2;
12117 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12118 macro_build (NULL
, "break", "6", 7);
12120 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12121 since that causes an overflow. We should do that as well,
12122 but I don't see how to do the comparisons without a temporary
12125 macro_build (NULL
, s
, "x", op
[0]);
12144 start_noreorder ();
12145 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
12146 expr1
.X_add_number
= 2;
12147 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12148 macro_build (NULL
, "break", "6", 7);
12150 macro_build (NULL
, s2
, "x", op
[0]);
12156 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
12157 macro_build (NULL
, "mflo", "x", op
[0]);
12165 if (imm_expr
.X_op
!= O_constant
)
12166 as_bad (_("Unsupported large constant"));
12167 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12168 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
12172 if (imm_expr
.X_op
!= O_constant
)
12173 as_bad (_("Unsupported large constant"));
12174 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12175 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
12179 if (imm_expr
.X_op
!= O_constant
)
12180 as_bad (_("Unsupported large constant"));
12181 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12182 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
12204 goto do_reverse_branch
;
12208 goto do_reverse_branch
;
12220 goto do_reverse_branch
;
12231 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
12232 macro_build (&offset_expr
, s2
, "p");
12259 goto do_addone_branch_i
;
12264 goto do_addone_branch_i
;
12279 goto do_addone_branch_i
;
12285 do_addone_branch_i
:
12286 if (imm_expr
.X_op
!= O_constant
)
12287 as_bad (_("Unsupported large constant"));
12288 ++imm_expr
.X_add_number
;
12291 macro_build (&imm_expr
, s
, s3
, op
[0]);
12292 macro_build (&offset_expr
, s2
, "p");
12296 expr1
.X_add_number
= 0;
12297 macro_build (&expr1
, "slti", "x,8", op
[1]);
12298 if (op
[0] != op
[1])
12299 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
12300 expr1
.X_add_number
= 2;
12301 macro_build (&expr1
, "bteqz", "p");
12302 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
12307 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12308 opcode bits in *OPCODE_EXTRA. */
12310 static struct mips_opcode
*
12311 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
12312 ssize_t length
, unsigned int *opcode_extra
)
12314 char *name
, *dot
, *p
;
12315 unsigned int mask
, suffix
;
12317 struct mips_opcode
*insn
;
12319 /* Make a copy of the instruction so that we can fiddle with it. */
12320 name
= alloca (length
+ 1);
12321 memcpy (name
, start
, length
);
12322 name
[length
] = '\0';
12324 /* Look up the instruction as-is. */
12325 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12329 dot
= strchr (name
, '.');
12332 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12333 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
12334 if (*p
== 0 && mask
!= 0)
12337 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12339 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
12341 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
12347 if (mips_opts
.micromips
)
12349 /* See if there's an instruction size override suffix,
12350 either `16' or `32', at the end of the mnemonic proper,
12351 that defines the operation, i.e. before the first `.'
12352 character if any. Strip it and retry. */
12353 opend
= dot
!= NULL
? dot
- name
: length
;
12354 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
12356 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
12362 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
12363 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12366 forced_insn_length
= suffix
;
12375 /* Assemble an instruction into its binary format. If the instruction
12376 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12377 associated with "I", "+I" and "A" operands respectively. Otherwise
12378 store the value of the relocatable field (if any) in offset_expr.
12379 In both cases set offset_reloc to the relocation operators applied
12383 mips_ip (char *str
, struct mips_cl_insn
*ip
)
12385 bfd_boolean wrong_delay_slot_insns
= FALSE
;
12386 bfd_boolean need_delay_slot_ok
= TRUE
;
12387 struct mips_opcode
*firstinsn
= NULL
;
12388 const struct mips_opcode
*past
;
12389 struct hash_control
*hash
;
12392 struct mips_opcode
*first
, *insn
;
12395 const struct mips_operand
*operand
;
12396 struct mips_arg_info arg
;
12397 struct mips_operand_token
*tokens
;
12398 unsigned int opcode_extra
;
12402 if (mips_opts
.micromips
)
12404 hash
= micromips_op_hash
;
12405 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
12410 past
= &mips_opcodes
[NUMOPCODES
];
12412 forced_insn_length
= 0;
12416 /* We first try to match an instruction up to a space or to the end. */
12417 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
12420 first
= insn
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
12423 insn_error
= _("Unrecognized opcode");
12426 /* When no opcode suffix is specified, assume ".xyzw". */
12427 if ((insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
12428 opcode_extra
= 0xf << mips_vu0_channel_mask
.lsb
;
12430 if (strcmp (insn
->name
, "li.s") == 0)
12432 else if (strcmp (insn
->name
, "li.d") == 0)
12436 tokens
= mips_parse_arguments (str
+ end
, format
);
12440 /* For microMIPS instructions placed in a fixed-length branch delay slot
12441 we make up to two passes over the relevant fragment of the opcode
12442 table. First we try instructions that meet the delay slot's length
12443 requirement. If none matched, then we retry with the remaining ones
12444 and if one matches, then we use it and then issue an appropriate
12445 warning later on. */
12448 bfd_boolean delay_slot_ok
;
12449 bfd_boolean size_ok
;
12451 bfd_boolean more_alts
;
12453 gas_assert (strcmp (insn
->name
, first
->name
) == 0);
12455 ok
= is_opcode_valid (insn
);
12456 size_ok
= is_size_valid (insn
);
12457 delay_slot_ok
= is_delay_slot_valid (insn
);
12458 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
12461 wrong_delay_slot_insns
= TRUE
;
12463 more_alts
= (insn
+ 1 < past
12464 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
12465 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
12467 static char buf
[256];
12474 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
12476 gas_assert (firstinsn
);
12477 need_delay_slot_ok
= FALSE
;
12483 obstack_free (&mips_operand_tokens
, tokens
);
12488 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
12489 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
12490 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12491 else if (mips_opts
.insn32
)
12492 sprintf (buf
, _("Opcode not supported in the `insn32' mode"));
12494 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
12495 8 * forced_insn_length
);
12501 imm_expr
.X_op
= O_absent
;
12502 imm2_expr
.X_op
= O_absent
;
12503 offset_expr
.X_op
= O_absent
;
12504 offset_reloc
[0] = BFD_RELOC_UNUSED
;
12505 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12506 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12508 create_insn (ip
, insn
);
12509 ip
->insn_opcode
|= opcode_extra
;
12511 memset (&arg
, 0, sizeof (arg
));
12513 arg
.token
= tokens
;
12515 arg
.last_regno
= ILLEGAL_REG
;
12516 arg
.dest_regno
= ILLEGAL_REG
;
12517 arg
.soft_match
= (more_alts
12518 || (wrong_delay_slot_insns
&& need_delay_slot_ok
));
12519 for (args
= insn
->args
;; ++args
)
12521 if (arg
.token
->type
== OT_END
)
12523 /* Handle unary instructions in which only one operand is given.
12524 The source is then the same as the destination. */
12525 if (arg
.opnum
== 1 && *args
== ',')
12527 operand
= (mips_opts
.micromips
12528 ? decode_micromips_operand (args
+ 1)
12529 : decode_mips_operand (args
+ 1));
12530 if (operand
&& mips_optional_operand_p (operand
))
12532 arg
.token
= tokens
;
12538 /* Treat elided base registers as $0. */
12539 if (strcmp (args
, "(b)") == 0)
12542 if (args
[0] == '+')
12547 /* The register suffix is optional. */
12552 /* Fail the match if there were too few operands. */
12556 /* Successful match. */
12557 if (arg
.dest_regno
== arg
.last_regno
12558 && strncmp (ip
->insn_mo
->name
, "jalr", 4) == 0)
12560 if (arg
.opnum
== 2)
12561 as_bad (_("Source and destination must be different"));
12562 else if (arg
.last_regno
== 31)
12563 as_bad (_("A destination register must be supplied"));
12565 check_completed_insn (&arg
);
12566 obstack_free (&mips_operand_tokens
, tokens
);
12570 /* Fail the match if the line has too many operands. */
12574 /* Handle characters that need to match exactly. */
12575 if (*args
== '(' || *args
== ')' || *args
== ',')
12577 if (match_char (&arg
, *args
))
12584 if (arg
.token
->type
== OT_DOUBLE_CHAR
12585 && arg
.token
->u
.ch
== *args
)
12593 /* Handle special macro operands. Work out the properties of
12596 arg
.lax_max
= FALSE
;
12615 /* If these integer forms come last, there is no other
12616 form of the instruction that could match. Prefer to
12617 give detailed error messages where possible. */
12619 arg
.soft_match
= FALSE
;
12623 /* "+I" is like "I", except that imm2_expr is used. */
12624 if (match_const_int (&arg
, &imm2_expr
.X_add_number
, 0))
12625 imm2_expr
.X_op
= O_constant
;
12627 insn_error
= _("absolute expression required");
12628 if (HAVE_32BIT_GPRS
)
12629 normalize_constant_expr (&imm2_expr
);
12634 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12664 /* If these integer forms come last, there is no other
12665 form of the instruction that could match. Prefer to
12666 give detailed error messages where possible. */
12668 arg
.soft_match
= FALSE
;
12672 if (match_const_int (&arg
, &imm_expr
.X_add_number
, 0))
12673 imm_expr
.X_op
= O_constant
;
12675 insn_error
= _("absolute expression required");
12676 if (HAVE_32BIT_GPRS
)
12677 normalize_constant_expr (&imm_expr
);
12681 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
12683 /* Assume that the offset has been elided and that what
12684 we saw was a base register. The match will fail later
12685 if that assumption turns out to be wrong. */
12686 offset_expr
.X_op
= O_constant
;
12687 offset_expr
.X_add_number
= 0;
12689 else if (match_expression (&arg
, &offset_expr
, offset_reloc
))
12690 normalize_address_expr (&offset_expr
);
12692 insn_error
= _("absolute expression required");
12696 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12698 insn_error
= _("floating-point expression required");
12702 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12704 insn_error
= _("floating-point expression required");
12708 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12710 insn_error
= _("floating-point expression required");
12714 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12716 insn_error
= _("floating-point expression required");
12719 /* ??? This is the traditional behavior, but is flaky if
12720 there are alternative versions of the same instruction
12721 for different subarchitectures. The next alternative
12722 might not be suitable. */
12724 /* For compatibility with older assemblers, we accept
12725 0x8000-0xffff as signed 16-bit numbers when only
12726 signed numbers are allowed. */
12727 arg
.lax_max
= !more_alts
;
12729 /* Only accept non-constant operands if this is the
12730 final alternative. Later alternatives might include
12731 a macro implementation. */
12732 arg
.allow_nonconst
= !more_alts
;
12736 /* There are no macro implementations for out-of-range values. */
12737 arg
.allow_nonconst
= TRUE
;
12741 /* There should always be a macro implementation. */
12742 arg
.allow_nonconst
= FALSE
;
12746 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12750 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12754 gas_assert (mips_opts
.micromips
);
12760 if (!forced_insn_length
)
12761 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12763 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12765 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12771 operand
= (mips_opts
.micromips
12772 ? decode_micromips_operand (args
)
12773 : decode_mips_operand (args
));
12777 /* Skip prefixes. */
12778 if (*args
== '+' || *args
== 'm')
12781 if (mips_optional_operand_p (operand
)
12783 && (arg
.token
[0].type
!= OT_REG
12784 || arg
.token
[1].type
== OT_END
))
12786 /* Assume that the register has been elided and is the
12787 same as the first operand. */
12788 arg
.token
= tokens
;
12792 if (!match_operand (&arg
, operand
))
12797 /* Args don't match. */
12798 insn_error
= _("Illegal operands");
12804 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
12806 gas_assert (firstinsn
);
12807 need_delay_slot_ok
= FALSE
;
12812 obstack_free (&mips_operand_tokens
, tokens
);
12817 /* As for mips_ip, but used when assembling MIPS16 code.
12818 Also set forced_insn_length to the resulting instruction size in
12819 bytes if the user explicitly requested a small or extended instruction. */
12822 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
12826 struct mips_opcode
*insn
;
12827 const struct mips_operand
*operand
;
12828 const struct mips_operand
*ext_operand
;
12829 struct mips_arg_info arg
;
12830 struct mips_operand_token
*tokens
;
12834 forced_insn_length
= 0;
12836 for (s
= str
; ISLOWER (*s
); ++s
)
12848 if (s
[1] == 't' && s
[2] == ' ')
12851 forced_insn_length
= 2;
12855 else if (s
[1] == 'e' && s
[2] == ' ')
12858 forced_insn_length
= 4;
12862 /* Fall through. */
12864 insn_error
= _("unknown opcode");
12868 if (mips_opts
.noautoextend
&& !forced_insn_length
)
12869 forced_insn_length
= 2;
12871 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
12873 insn_error
= _("unrecognized opcode");
12877 tokens
= mips_parse_arguments (s
, 0);
12884 bfd_boolean more_alts
;
12887 gas_assert (strcmp (insn
->name
, str
) == 0);
12889 ok
= is_opcode_valid_16 (insn
);
12890 more_alts
= (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
12891 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
12903 static char buf
[100];
12905 _("Opcode not supported on this processor: %s (%s)"),
12906 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
12907 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12910 obstack_free (&mips_operand_tokens
, tokens
);
12915 create_insn (ip
, insn
);
12916 imm_expr
.X_op
= O_absent
;
12917 imm2_expr
.X_op
= O_absent
;
12918 offset_expr
.X_op
= O_absent
;
12919 offset_reloc
[0] = BFD_RELOC_UNUSED
;
12920 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12921 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12924 memset (&arg
, 0, sizeof (arg
));
12926 arg
.token
= tokens
;
12928 arg
.last_regno
= ILLEGAL_REG
;
12929 arg
.dest_regno
= ILLEGAL_REG
;
12930 arg
.soft_match
= more_alts
;
12932 for (args
= insn
->args
; 1; ++args
)
12936 if (arg
.token
->type
== OT_END
)
12940 /* Handle unary instructions in which only one operand is given.
12941 The source is then the same as the destination. */
12942 if (arg
.opnum
== 1 && *args
== ',')
12944 operand
= decode_mips16_operand (args
[1], FALSE
);
12945 if (operand
&& mips_optional_operand_p (operand
))
12947 arg
.token
= tokens
;
12953 /* Fail the match if there were too few operands. */
12957 /* Successful match. Stuff the immediate value in now, if
12959 if (insn
->pinfo
== INSN_MACRO
)
12961 gas_assert (relax_char
== 0 || relax_char
== 'p');
12962 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
12964 else if (relax_char
12965 && offset_expr
.X_op
== O_constant
12966 && calculate_reloc (*offset_reloc
,
12967 offset_expr
.X_add_number
,
12970 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
12971 forced_insn_length
, &ip
->insn_opcode
);
12972 offset_expr
.X_op
= O_absent
;
12973 *offset_reloc
= BFD_RELOC_UNUSED
;
12975 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
12977 if (forced_insn_length
== 2)
12978 as_bad (_("invalid unextended operand value"));
12979 forced_insn_length
= 4;
12980 ip
->insn_opcode
|= MIPS16_EXTEND
;
12982 else if (relax_char
)
12983 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
12985 check_completed_insn (&arg
);
12986 obstack_free (&mips_operand_tokens
, tokens
);
12990 /* Fail the match if the line has too many operands. */
12994 /* Handle characters that need to match exactly. */
12995 if (*args
== '(' || *args
== ')' || *args
== ',')
12997 if (match_char (&arg
, *args
))
13015 if (match_const_int (&arg
, &imm_expr
.X_add_number
, 0))
13016 imm_expr
.X_op
= O_constant
;
13018 insn_error
= _("absolute expression required");
13019 if (HAVE_32BIT_GPRS
)
13020 normalize_constant_expr (&imm_expr
);
13025 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13026 ip
->insn_opcode
<<= 16;
13030 operand
= decode_mips16_operand (c
, FALSE
);
13034 /* '6' is a special case. It is used for BREAK and SDBBP,
13035 whose operands are only meaningful to the software that decodes
13036 them. This means that there is no architectural reason why
13037 they cannot be prefixed by EXTEND, but in practice,
13038 exception handlers will only look at the instruction
13039 itself. We therefore allow '6' to be extended when
13040 disassembling but not when assembling. */
13041 if (operand
->type
!= OP_PCREL
&& c
!= '6')
13043 ext_operand
= decode_mips16_operand (c
, TRUE
);
13044 if (operand
!= ext_operand
)
13046 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
13048 offset_expr
.X_op
= O_constant
;
13049 offset_expr
.X_add_number
= 0;
13054 /* We need the OT_INTEGER check because some MIPS16
13055 immediate variants are listed before the register ones. */
13056 if (arg
.token
->type
!= OT_INTEGER
13057 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
13060 /* '8' is used for SLTI(U) and has traditionally not
13061 been allowed to take relocation operators. */
13062 if (offset_reloc
[0] != BFD_RELOC_UNUSED
13063 && (ext_operand
->size
!= 16 || c
== '8'))
13071 if (mips_optional_operand_p (operand
)
13073 && (arg
.token
[0].type
!= OT_REG
13074 || arg
.token
[1].type
== OT_END
))
13076 /* Assume that the register has been elided and is the
13077 same as the first operand. */
13078 arg
.token
= tokens
;
13082 if (!match_operand (&arg
, operand
))
13087 /* Args don't match. */
13094 insn_error
= _("illegal operands");
13096 obstack_free (&mips_operand_tokens
, tokens
);
13101 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13102 NBITS is the number of significant bits in VAL. */
13104 static unsigned long
13105 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13110 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13113 else if (nbits
== 15)
13115 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13120 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13123 return (extval
<< 16) | val
;
13126 /* Like decode_mips16_operand, but require the operand to be defined and
13127 require it to be an integer. */
13129 static const struct mips_int_operand
*
13130 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13132 const struct mips_operand
*operand
;
13134 operand
= decode_mips16_operand (type
, extended_p
);
13135 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13137 return (const struct mips_int_operand
*) operand
;
13140 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13143 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13144 bfd_reloc_code_real_type reloc
, offsetT sval
)
13146 int min_val
, max_val
;
13148 min_val
= mips_int_operand_min (operand
);
13149 max_val
= mips_int_operand_max (operand
);
13150 if (reloc
!= BFD_RELOC_UNUSED
)
13153 sval
= SEXT_16BIT (sval
);
13158 return (sval
>= min_val
13160 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13163 /* Install immediate value VAL into MIPS16 instruction *INSN,
13164 extending it if necessary. The instruction in *INSN may
13165 already be extended.
13167 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13168 if none. In the former case, VAL is a 16-bit number with no
13169 defined signedness.
13171 TYPE is the type of the immediate field. USER_INSN_LENGTH
13172 is the length that the user requested, or 0 if none. */
13175 mips16_immed (char *file
, unsigned int line
, int type
,
13176 bfd_reloc_code_real_type reloc
, offsetT val
,
13177 unsigned int user_insn_length
, unsigned long *insn
)
13179 const struct mips_int_operand
*operand
;
13180 unsigned int uval
, length
;
13182 operand
= mips16_immed_operand (type
, FALSE
);
13183 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13185 /* We need an extended instruction. */
13186 if (user_insn_length
== 2)
13187 as_bad_where (file
, line
, _("invalid unextended operand value"));
13189 *insn
|= MIPS16_EXTEND
;
13191 else if (user_insn_length
== 4)
13193 /* The operand doesn't force an unextended instruction to be extended.
13194 Warn if the user wanted an extended instruction anyway. */
13195 *insn
|= MIPS16_EXTEND
;
13196 as_warn_where (file
, line
,
13197 _("extended operand requested but not required"));
13200 length
= mips16_opcode_length (*insn
);
13203 operand
= mips16_immed_operand (type
, TRUE
);
13204 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13205 as_bad_where (file
, line
,
13206 _("operand value out of range for instruction"));
13208 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13210 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13212 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13215 struct percent_op_match
13218 bfd_reloc_code_real_type reloc
;
13221 static const struct percent_op_match mips_percent_op
[] =
13223 {"%lo", BFD_RELOC_LO16
},
13224 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13225 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13226 {"%call16", BFD_RELOC_MIPS_CALL16
},
13227 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13228 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13229 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13230 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13231 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13232 {"%got", BFD_RELOC_MIPS_GOT16
},
13233 {"%gp_rel", BFD_RELOC_GPREL16
},
13234 {"%half", BFD_RELOC_16
},
13235 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13236 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13237 {"%neg", BFD_RELOC_MIPS_SUB
},
13238 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13239 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13240 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13241 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13242 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13243 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13244 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13245 {"%hi", BFD_RELOC_HI16_S
}
13248 static const struct percent_op_match mips16_percent_op
[] =
13250 {"%lo", BFD_RELOC_MIPS16_LO16
},
13251 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13252 {"%got", BFD_RELOC_MIPS16_GOT16
},
13253 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13254 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13255 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13256 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13257 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13258 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13259 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13260 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13261 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13265 /* Return true if *STR points to a relocation operator. When returning true,
13266 move *STR over the operator and store its relocation code in *RELOC.
13267 Leave both *STR and *RELOC alone when returning false. */
13270 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13272 const struct percent_op_match
*percent_op
;
13275 if (mips_opts
.mips16
)
13277 percent_op
= mips16_percent_op
;
13278 limit
= ARRAY_SIZE (mips16_percent_op
);
13282 percent_op
= mips_percent_op
;
13283 limit
= ARRAY_SIZE (mips_percent_op
);
13286 for (i
= 0; i
< limit
; i
++)
13287 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13289 int len
= strlen (percent_op
[i
].str
);
13291 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13294 *str
+= strlen (percent_op
[i
].str
);
13295 *reloc
= percent_op
[i
].reloc
;
13297 /* Check whether the output BFD supports this relocation.
13298 If not, issue an error and fall back on something safe. */
13299 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13301 as_bad (_("relocation %s isn't supported by the current ABI"),
13302 percent_op
[i
].str
);
13303 *reloc
= BFD_RELOC_UNUSED
;
13311 /* Parse string STR as a 16-bit relocatable operand. Store the
13312 expression in *EP and the relocations in the array starting
13313 at RELOC. Return the number of relocation operators used.
13315 On exit, EXPR_END points to the first character after the expression. */
13318 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13321 bfd_reloc_code_real_type reversed_reloc
[3];
13322 size_t reloc_index
, i
;
13323 int crux_depth
, str_depth
;
13326 /* Search for the start of the main expression, recoding relocations
13327 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13328 of the main expression and with CRUX_DEPTH containing the number
13329 of open brackets at that point. */
13336 crux_depth
= str_depth
;
13338 /* Skip over whitespace and brackets, keeping count of the number
13340 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13345 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13346 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13348 my_getExpression (ep
, crux
);
13351 /* Match every open bracket. */
13352 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13356 if (crux_depth
> 0)
13357 as_bad (_("unclosed '('"));
13361 if (reloc_index
!= 0)
13363 prev_reloc_op_frag
= frag_now
;
13364 for (i
= 0; i
< reloc_index
; i
++)
13365 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13368 return reloc_index
;
13372 my_getExpression (expressionS
*ep
, char *str
)
13376 save_in
= input_line_pointer
;
13377 input_line_pointer
= str
;
13379 expr_end
= input_line_pointer
;
13380 input_line_pointer
= save_in
;
13384 md_atof (int type
, char *litP
, int *sizeP
)
13386 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13390 md_number_to_chars (char *buf
, valueT val
, int n
)
13392 if (target_big_endian
)
13393 number_to_chars_bigendian (buf
, val
, n
);
13395 number_to_chars_littleendian (buf
, val
, n
);
13398 static int support_64bit_objects(void)
13400 const char **list
, **l
;
13403 list
= bfd_target_list ();
13404 for (l
= list
; *l
!= NULL
; l
++)
13405 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13406 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13408 yes
= (*l
!= NULL
);
13413 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13414 NEW_VALUE. Warn if another value was already specified. Note:
13415 we have to defer parsing the -march and -mtune arguments in order
13416 to handle 'from-abi' correctly, since the ABI might be specified
13417 in a later argument. */
13420 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13422 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13423 as_warn (_("A different %s was already specified, is now %s"),
13424 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13427 *string_ptr
= new_value
;
13431 md_parse_option (int c
, char *arg
)
13435 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13436 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13438 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13439 c
== mips_ases
[i
].option_on
);
13445 case OPTION_CONSTRUCT_FLOATS
:
13446 mips_disable_float_construction
= 0;
13449 case OPTION_NO_CONSTRUCT_FLOATS
:
13450 mips_disable_float_construction
= 1;
13462 target_big_endian
= 1;
13466 target_big_endian
= 0;
13472 else if (arg
[0] == '0')
13474 else if (arg
[0] == '1')
13484 mips_debug
= atoi (arg
);
13488 file_mips_isa
= ISA_MIPS1
;
13492 file_mips_isa
= ISA_MIPS2
;
13496 file_mips_isa
= ISA_MIPS3
;
13500 file_mips_isa
= ISA_MIPS4
;
13504 file_mips_isa
= ISA_MIPS5
;
13507 case OPTION_MIPS32
:
13508 file_mips_isa
= ISA_MIPS32
;
13511 case OPTION_MIPS32R2
:
13512 file_mips_isa
= ISA_MIPS32R2
;
13515 case OPTION_MIPS64R2
:
13516 file_mips_isa
= ISA_MIPS64R2
;
13519 case OPTION_MIPS64
:
13520 file_mips_isa
= ISA_MIPS64
;
13524 mips_set_option_string (&mips_tune_string
, arg
);
13528 mips_set_option_string (&mips_arch_string
, arg
);
13532 mips_set_option_string (&mips_arch_string
, "4650");
13533 mips_set_option_string (&mips_tune_string
, "4650");
13536 case OPTION_NO_M4650
:
13540 mips_set_option_string (&mips_arch_string
, "4010");
13541 mips_set_option_string (&mips_tune_string
, "4010");
13544 case OPTION_NO_M4010
:
13548 mips_set_option_string (&mips_arch_string
, "4100");
13549 mips_set_option_string (&mips_tune_string
, "4100");
13552 case OPTION_NO_M4100
:
13556 mips_set_option_string (&mips_arch_string
, "3900");
13557 mips_set_option_string (&mips_tune_string
, "3900");
13560 case OPTION_NO_M3900
:
13563 case OPTION_MICROMIPS
:
13564 if (mips_opts
.mips16
== 1)
13566 as_bad (_("-mmicromips cannot be used with -mips16"));
13569 mips_opts
.micromips
= 1;
13570 mips_no_prev_insn ();
13573 case OPTION_NO_MICROMIPS
:
13574 mips_opts
.micromips
= 0;
13575 mips_no_prev_insn ();
13578 case OPTION_MIPS16
:
13579 if (mips_opts
.micromips
== 1)
13581 as_bad (_("-mips16 cannot be used with -micromips"));
13584 mips_opts
.mips16
= 1;
13585 mips_no_prev_insn ();
13588 case OPTION_NO_MIPS16
:
13589 mips_opts
.mips16
= 0;
13590 mips_no_prev_insn ();
13593 case OPTION_FIX_24K
:
13597 case OPTION_NO_FIX_24K
:
13601 case OPTION_FIX_LOONGSON2F_JUMP
:
13602 mips_fix_loongson2f_jump
= TRUE
;
13605 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13606 mips_fix_loongson2f_jump
= FALSE
;
13609 case OPTION_FIX_LOONGSON2F_NOP
:
13610 mips_fix_loongson2f_nop
= TRUE
;
13613 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13614 mips_fix_loongson2f_nop
= FALSE
;
13617 case OPTION_FIX_VR4120
:
13618 mips_fix_vr4120
= 1;
13621 case OPTION_NO_FIX_VR4120
:
13622 mips_fix_vr4120
= 0;
13625 case OPTION_FIX_VR4130
:
13626 mips_fix_vr4130
= 1;
13629 case OPTION_NO_FIX_VR4130
:
13630 mips_fix_vr4130
= 0;
13633 case OPTION_FIX_CN63XXP1
:
13634 mips_fix_cn63xxp1
= TRUE
;
13637 case OPTION_NO_FIX_CN63XXP1
:
13638 mips_fix_cn63xxp1
= FALSE
;
13641 case OPTION_RELAX_BRANCH
:
13642 mips_relax_branch
= 1;
13645 case OPTION_NO_RELAX_BRANCH
:
13646 mips_relax_branch
= 0;
13649 case OPTION_INSN32
:
13650 mips_opts
.insn32
= TRUE
;
13653 case OPTION_NO_INSN32
:
13654 mips_opts
.insn32
= FALSE
;
13657 case OPTION_MSHARED
:
13658 mips_in_shared
= TRUE
;
13661 case OPTION_MNO_SHARED
:
13662 mips_in_shared
= FALSE
;
13665 case OPTION_MSYM32
:
13666 mips_opts
.sym32
= TRUE
;
13669 case OPTION_MNO_SYM32
:
13670 mips_opts
.sym32
= FALSE
;
13673 /* When generating ELF code, we permit -KPIC and -call_shared to
13674 select SVR4_PIC, and -non_shared to select no PIC. This is
13675 intended to be compatible with Irix 5. */
13676 case OPTION_CALL_SHARED
:
13677 mips_pic
= SVR4_PIC
;
13678 mips_abicalls
= TRUE
;
13681 case OPTION_CALL_NONPIC
:
13683 mips_abicalls
= TRUE
;
13686 case OPTION_NON_SHARED
:
13688 mips_abicalls
= FALSE
;
13691 /* The -xgot option tells the assembler to use 32 bit offsets
13692 when accessing the got in SVR4_PIC mode. It is for Irix
13699 g_switch_value
= atoi (arg
);
13703 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13706 mips_abi
= O32_ABI
;
13710 mips_abi
= N32_ABI
;
13714 mips_abi
= N64_ABI
;
13715 if (!support_64bit_objects())
13716 as_fatal (_("No compiled in support for 64 bit object file format"));
13720 file_mips_gp32
= 1;
13724 file_mips_gp32
= 0;
13728 file_mips_fp32
= 1;
13732 file_mips_fp32
= 0;
13735 case OPTION_SINGLE_FLOAT
:
13736 file_mips_single_float
= 1;
13739 case OPTION_DOUBLE_FLOAT
:
13740 file_mips_single_float
= 0;
13743 case OPTION_SOFT_FLOAT
:
13744 file_mips_soft_float
= 1;
13747 case OPTION_HARD_FLOAT
:
13748 file_mips_soft_float
= 0;
13752 if (strcmp (arg
, "32") == 0)
13753 mips_abi
= O32_ABI
;
13754 else if (strcmp (arg
, "o64") == 0)
13755 mips_abi
= O64_ABI
;
13756 else if (strcmp (arg
, "n32") == 0)
13757 mips_abi
= N32_ABI
;
13758 else if (strcmp (arg
, "64") == 0)
13760 mips_abi
= N64_ABI
;
13761 if (! support_64bit_objects())
13762 as_fatal (_("No compiled in support for 64 bit object file "
13765 else if (strcmp (arg
, "eabi") == 0)
13766 mips_abi
= EABI_ABI
;
13769 as_fatal (_("invalid abi -mabi=%s"), arg
);
13774 case OPTION_M7000_HILO_FIX
:
13775 mips_7000_hilo_fix
= TRUE
;
13778 case OPTION_MNO_7000_HILO_FIX
:
13779 mips_7000_hilo_fix
= FALSE
;
13782 case OPTION_MDEBUG
:
13783 mips_flag_mdebug
= TRUE
;
13786 case OPTION_NO_MDEBUG
:
13787 mips_flag_mdebug
= FALSE
;
13791 mips_flag_pdr
= TRUE
;
13794 case OPTION_NO_PDR
:
13795 mips_flag_pdr
= FALSE
;
13798 case OPTION_MVXWORKS_PIC
:
13799 mips_pic
= VXWORKS_PIC
;
13803 if (strcmp (arg
, "2008") == 0)
13804 mips_flag_nan2008
= TRUE
;
13805 else if (strcmp (arg
, "legacy") == 0)
13806 mips_flag_nan2008
= FALSE
;
13809 as_fatal (_("Invalid NaN setting -mnan=%s"), arg
);
13818 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13823 /* Set up globals to generate code for the ISA or processor
13824 described by INFO. */
13827 mips_set_architecture (const struct mips_cpu_info
*info
)
13831 file_mips_arch
= info
->cpu
;
13832 mips_opts
.arch
= info
->cpu
;
13833 mips_opts
.isa
= info
->isa
;
13838 /* Likewise for tuning. */
13841 mips_set_tune (const struct mips_cpu_info
*info
)
13844 mips_tune
= info
->cpu
;
13849 mips_after_parse_args (void)
13851 const struct mips_cpu_info
*arch_info
= 0;
13852 const struct mips_cpu_info
*tune_info
= 0;
13854 /* GP relative stuff not working for PE */
13855 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13857 if (g_switch_seen
&& g_switch_value
!= 0)
13858 as_bad (_("-G not supported in this configuration."));
13859 g_switch_value
= 0;
13862 if (mips_abi
== NO_ABI
)
13863 mips_abi
= MIPS_DEFAULT_ABI
;
13865 /* The following code determines the architecture and register size.
13866 Similar code was added to GCC 3.3 (see override_options() in
13867 config/mips/mips.c). The GAS and GCC code should be kept in sync
13868 as much as possible. */
13870 if (mips_arch_string
!= 0)
13871 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13873 if (file_mips_isa
!= ISA_UNKNOWN
)
13875 /* Handle -mipsN. At this point, file_mips_isa contains the
13876 ISA level specified by -mipsN, while arch_info->isa contains
13877 the -march selection (if any). */
13878 if (arch_info
!= 0)
13880 /* -march takes precedence over -mipsN, since it is more descriptive.
13881 There's no harm in specifying both as long as the ISA levels
13883 if (file_mips_isa
!= arch_info
->isa
)
13884 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13885 mips_cpu_info_from_isa (file_mips_isa
)->name
,
13886 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13889 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
13892 if (arch_info
== 0)
13894 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13895 gas_assert (arch_info
);
13898 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13899 as_bad (_("-march=%s is not compatible with the selected ABI"),
13902 mips_set_architecture (arch_info
);
13904 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13905 if (mips_tune_string
!= 0)
13906 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13908 if (tune_info
== 0)
13909 mips_set_tune (arch_info
);
13911 mips_set_tune (tune_info
);
13913 if (file_mips_gp32
>= 0)
13915 /* The user specified the size of the integer registers. Make sure
13916 it agrees with the ABI and ISA. */
13917 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13918 as_bad (_("-mgp64 used with a 32-bit processor"));
13919 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
13920 as_bad (_("-mgp32 used with a 64-bit ABI"));
13921 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
13922 as_bad (_("-mgp64 used with a 32-bit ABI"));
13926 /* Infer the integer register size from the ABI and processor.
13927 Restrict ourselves to 32-bit registers if that's all the
13928 processor has, or if the ABI cannot handle 64-bit registers. */
13929 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
13930 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
13933 switch (file_mips_fp32
)
13937 /* No user specified float register size.
13938 ??? GAS treats single-float processors as though they had 64-bit
13939 float registers (although it complains when double-precision
13940 instructions are used). As things stand, saying they have 32-bit
13941 registers would lead to spurious "register must be even" messages.
13942 So here we assume float registers are never smaller than the
13944 if (file_mips_gp32
== 0)
13945 /* 64-bit integer registers implies 64-bit float registers. */
13946 file_mips_fp32
= 0;
13947 else if ((mips_opts
.ase
& FP64_ASES
)
13948 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13949 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13950 file_mips_fp32
= 0;
13952 /* 32-bit float registers. */
13953 file_mips_fp32
= 1;
13956 /* The user specified the size of the float registers. Check if it
13957 agrees with the ABI and ISA. */
13959 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13960 as_bad (_("-mfp64 used with a 32-bit fpu"));
13961 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
13962 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
13963 as_warn (_("-mfp64 used with a 32-bit ABI"));
13966 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13967 as_warn (_("-mfp32 used with a 64-bit ABI"));
13971 /* End of GCC-shared inference code. */
13973 /* This flag is set when we have a 64-bit capable CPU but use only
13974 32-bit wide registers. Note that EABI does not use it. */
13975 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
13976 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
13977 || mips_abi
== O32_ABI
))
13978 mips_32bitmode
= 1;
13980 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
13981 as_bad (_("trap exception not supported at ISA 1"));
13983 /* If the selected architecture includes support for ASEs, enable
13984 generation of code for them. */
13985 if (mips_opts
.mips16
== -1)
13986 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
13987 if (mips_opts
.micromips
== -1)
13988 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
13990 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13991 ASEs from being selected implicitly. */
13992 if (file_mips_fp32
== 1)
13993 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
13995 /* If the user didn't explicitly select or deselect a particular ASE,
13996 use the default setting for the CPU. */
13997 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
13999 file_mips_isa
= mips_opts
.isa
;
14000 file_ase
= mips_opts
.ase
;
14001 mips_opts
.gp32
= file_mips_gp32
;
14002 mips_opts
.fp32
= file_mips_fp32
;
14003 mips_opts
.soft_float
= file_mips_soft_float
;
14004 mips_opts
.single_float
= file_mips_single_float
;
14006 mips_check_isa_supports_ases ();
14008 if (mips_flag_mdebug
< 0)
14009 mips_flag_mdebug
= 0;
14013 mips_init_after_args (void)
14015 /* initialize opcodes */
14016 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14017 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14021 md_pcrel_from (fixS
*fixP
)
14023 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14024 switch (fixP
->fx_r_type
)
14026 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14027 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14028 /* Return the address of the delay slot. */
14031 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14032 case BFD_RELOC_MICROMIPS_JMP
:
14033 case BFD_RELOC_16_PCREL_S2
:
14034 case BFD_RELOC_MIPS_JMP
:
14035 /* Return the address of the delay slot. */
14038 case BFD_RELOC_32_PCREL
:
14042 /* We have no relocation type for PC relative MIPS16 instructions. */
14043 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
14044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14045 _("PC relative MIPS16 instruction references a different section"));
14050 /* This is called before the symbol table is processed. In order to
14051 work with gcc when using mips-tfile, we must keep all local labels.
14052 However, in other cases, we want to discard them. If we were
14053 called with -g, but we didn't see any debugging information, it may
14054 mean that gcc is smuggling debugging information through to
14055 mips-tfile, in which case we must generate all local labels. */
14058 mips_frob_file_before_adjust (void)
14060 #ifndef NO_ECOFF_DEBUGGING
14061 if (ECOFF_DEBUGGING
14063 && ! ecoff_debugging_seen
)
14064 flag_keep_locals
= 1;
14068 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14069 the corresponding LO16 reloc. This is called before md_apply_fix and
14070 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14071 relocation operators.
14073 For our purposes, a %lo() expression matches a %got() or %hi()
14076 (a) it refers to the same symbol; and
14077 (b) the offset applied in the %lo() expression is no lower than
14078 the offset applied in the %got() or %hi().
14080 (b) allows us to cope with code like:
14083 lh $4,%lo(foo+2)($4)
14085 ...which is legal on RELA targets, and has a well-defined behaviour
14086 if the user knows that adding 2 to "foo" will not induce a carry to
14089 When several %lo()s match a particular %got() or %hi(), we use the
14090 following rules to distinguish them:
14092 (1) %lo()s with smaller offsets are a better match than %lo()s with
14095 (2) %lo()s with no matching %got() or %hi() are better than those
14096 that already have a matching %got() or %hi().
14098 (3) later %lo()s are better than earlier %lo()s.
14100 These rules are applied in order.
14102 (1) means, among other things, that %lo()s with identical offsets are
14103 chosen if they exist.
14105 (2) means that we won't associate several high-part relocations with
14106 the same low-part relocation unless there's no alternative. Having
14107 several high parts for the same low part is a GNU extension; this rule
14108 allows careful users to avoid it.
14110 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14111 with the last high-part relocation being at the front of the list.
14112 It therefore makes sense to choose the last matching low-part
14113 relocation, all other things being equal. It's also easier
14114 to code that way. */
14117 mips_frob_file (void)
14119 struct mips_hi_fixup
*l
;
14120 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14122 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14124 segment_info_type
*seginfo
;
14125 bfd_boolean matched_lo_p
;
14126 fixS
**hi_pos
, **lo_pos
, **pos
;
14128 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14130 /* If a GOT16 relocation turns out to be against a global symbol,
14131 there isn't supposed to be a matching LO. Ignore %gots against
14132 constants; we'll report an error for those later. */
14133 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14134 && !(l
->fixp
->fx_addsy
14135 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14138 /* Check quickly whether the next fixup happens to be a matching %lo. */
14139 if (fixup_has_matching_lo_p (l
->fixp
))
14142 seginfo
= seg_info (l
->seg
);
14144 /* Set HI_POS to the position of this relocation in the chain.
14145 Set LO_POS to the position of the chosen low-part relocation.
14146 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14147 relocation that matches an immediately-preceding high-part
14151 matched_lo_p
= FALSE
;
14152 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14154 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14156 if (*pos
== l
->fixp
)
14159 if ((*pos
)->fx_r_type
== looking_for_rtype
14160 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14161 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14163 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14165 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14168 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14169 && fixup_has_matching_lo_p (*pos
));
14172 /* If we found a match, remove the high-part relocation from its
14173 current position and insert it before the low-part relocation.
14174 Make the offsets match so that fixup_has_matching_lo_p()
14177 We don't warn about unmatched high-part relocations since some
14178 versions of gcc have been known to emit dead "lui ...%hi(...)"
14180 if (lo_pos
!= NULL
)
14182 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14183 if (l
->fixp
->fx_next
!= *lo_pos
)
14185 *hi_pos
= l
->fixp
->fx_next
;
14186 l
->fixp
->fx_next
= *lo_pos
;
14194 mips_force_relocation (fixS
*fixp
)
14196 if (generic_force_reloc (fixp
))
14199 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14200 so that the linker relaxation can update targets. */
14201 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14202 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14203 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14209 /* Read the instruction associated with RELOC from BUF. */
14211 static unsigned int
14212 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14214 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14215 return read_compressed_insn (buf
, 4);
14217 return read_insn (buf
);
14220 /* Write instruction INSN to BUF, given that it has been relocated
14224 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14225 unsigned long insn
)
14227 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14228 write_compressed_insn (buf
, insn
, 4);
14230 write_insn (buf
, insn
);
14233 /* Apply a fixup to the object file. */
14236 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14239 unsigned long insn
;
14240 reloc_howto_type
*howto
;
14242 /* We ignore generic BFD relocations we don't know about. */
14243 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14247 gas_assert (fixP
->fx_size
== 2
14248 || fixP
->fx_size
== 4
14249 || fixP
->fx_r_type
== BFD_RELOC_16
14250 || fixP
->fx_r_type
== BFD_RELOC_64
14251 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14252 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14253 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14254 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14255 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14256 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14258 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14260 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14261 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14262 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14263 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
14264 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
14266 /* Don't treat parts of a composite relocation as done. There are two
14269 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14270 should nevertheless be emitted if the first part is.
14272 (2) In normal usage, composite relocations are never assembly-time
14273 constants. The easiest way of dealing with the pathological
14274 exceptions is to generate a relocation against STN_UNDEF and
14275 leave everything up to the linker. */
14276 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14279 switch (fixP
->fx_r_type
)
14281 case BFD_RELOC_MIPS_TLS_GD
:
14282 case BFD_RELOC_MIPS_TLS_LDM
:
14283 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14284 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14285 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14286 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14287 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14288 case BFD_RELOC_MIPS_TLS_TPREL32
:
14289 case BFD_RELOC_MIPS_TLS_TPREL64
:
14290 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14291 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14292 case BFD_RELOC_MICROMIPS_TLS_GD
:
14293 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14294 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14295 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14296 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14297 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14298 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14299 case BFD_RELOC_MIPS16_TLS_GD
:
14300 case BFD_RELOC_MIPS16_TLS_LDM
:
14301 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14302 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14303 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14304 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14305 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14306 if (!fixP
->fx_addsy
)
14308 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14309 _("TLS relocation against a constant"));
14312 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14315 case BFD_RELOC_MIPS_JMP
:
14316 case BFD_RELOC_MIPS_SHIFT5
:
14317 case BFD_RELOC_MIPS_SHIFT6
:
14318 case BFD_RELOC_MIPS_GOT_DISP
:
14319 case BFD_RELOC_MIPS_GOT_PAGE
:
14320 case BFD_RELOC_MIPS_GOT_OFST
:
14321 case BFD_RELOC_MIPS_SUB
:
14322 case BFD_RELOC_MIPS_INSERT_A
:
14323 case BFD_RELOC_MIPS_INSERT_B
:
14324 case BFD_RELOC_MIPS_DELETE
:
14325 case BFD_RELOC_MIPS_HIGHEST
:
14326 case BFD_RELOC_MIPS_HIGHER
:
14327 case BFD_RELOC_MIPS_SCN_DISP
:
14328 case BFD_RELOC_MIPS_REL16
:
14329 case BFD_RELOC_MIPS_RELGOT
:
14330 case BFD_RELOC_MIPS_JALR
:
14331 case BFD_RELOC_HI16
:
14332 case BFD_RELOC_HI16_S
:
14333 case BFD_RELOC_LO16
:
14334 case BFD_RELOC_GPREL16
:
14335 case BFD_RELOC_MIPS_LITERAL
:
14336 case BFD_RELOC_MIPS_CALL16
:
14337 case BFD_RELOC_MIPS_GOT16
:
14338 case BFD_RELOC_GPREL32
:
14339 case BFD_RELOC_MIPS_GOT_HI16
:
14340 case BFD_RELOC_MIPS_GOT_LO16
:
14341 case BFD_RELOC_MIPS_CALL_HI16
:
14342 case BFD_RELOC_MIPS_CALL_LO16
:
14343 case BFD_RELOC_MIPS16_GPREL
:
14344 case BFD_RELOC_MIPS16_GOT16
:
14345 case BFD_RELOC_MIPS16_CALL16
:
14346 case BFD_RELOC_MIPS16_HI16
:
14347 case BFD_RELOC_MIPS16_HI16_S
:
14348 case BFD_RELOC_MIPS16_LO16
:
14349 case BFD_RELOC_MIPS16_JMP
:
14350 case BFD_RELOC_MICROMIPS_JMP
:
14351 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14352 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14353 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14354 case BFD_RELOC_MICROMIPS_SUB
:
14355 case BFD_RELOC_MICROMIPS_HIGHEST
:
14356 case BFD_RELOC_MICROMIPS_HIGHER
:
14357 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14358 case BFD_RELOC_MICROMIPS_JALR
:
14359 case BFD_RELOC_MICROMIPS_HI16
:
14360 case BFD_RELOC_MICROMIPS_HI16_S
:
14361 case BFD_RELOC_MICROMIPS_LO16
:
14362 case BFD_RELOC_MICROMIPS_GPREL16
:
14363 case BFD_RELOC_MICROMIPS_LITERAL
:
14364 case BFD_RELOC_MICROMIPS_CALL16
:
14365 case BFD_RELOC_MICROMIPS_GOT16
:
14366 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14367 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14368 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14369 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14370 case BFD_RELOC_MIPS_EH
:
14375 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14377 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14378 if (mips16_reloc_p (fixP
->fx_r_type
))
14379 insn
|= mips16_immed_extend (value
, 16);
14381 insn
|= (value
& 0xffff);
14382 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14386 _("Unsupported constant in relocation"));
14391 /* This is handled like BFD_RELOC_32, but we output a sign
14392 extended value if we are only 32 bits. */
14395 if (8 <= sizeof (valueT
))
14396 md_number_to_chars (buf
, *valP
, 8);
14401 if ((*valP
& 0x80000000) != 0)
14405 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14406 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14411 case BFD_RELOC_RVA
:
14413 case BFD_RELOC_32_PCREL
:
14415 /* If we are deleting this reloc entry, we must fill in the
14416 value now. This can happen if we have a .word which is not
14417 resolved when it appears but is later defined. */
14419 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14422 case BFD_RELOC_16_PCREL_S2
:
14423 if ((*valP
& 0x3) != 0)
14424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14425 _("Branch to misaligned address (%lx)"), (long) *valP
);
14427 /* We need to save the bits in the instruction since fixup_segment()
14428 might be deleting the relocation entry (i.e., a branch within
14429 the current segment). */
14430 if (! fixP
->fx_done
)
14433 /* Update old instruction data. */
14434 insn
= read_insn (buf
);
14436 if (*valP
+ 0x20000 <= 0x3ffff)
14438 insn
|= (*valP
>> 2) & 0xffff;
14439 write_insn (buf
, insn
);
14441 else if (mips_pic
== NO_PIC
14443 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14444 && (fixP
->fx_frag
->fr_address
14445 < text_section
->vma
+ bfd_get_section_size (text_section
))
14446 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14447 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14448 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14450 /* The branch offset is too large. If this is an
14451 unconditional branch, and we are not generating PIC code,
14452 we can convert it to an absolute jump instruction. */
14453 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14454 insn
= 0x0c000000; /* jal */
14456 insn
= 0x08000000; /* j */
14457 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14459 fixP
->fx_addsy
= section_symbol (text_section
);
14460 *valP
+= md_pcrel_from (fixP
);
14461 write_insn (buf
, insn
);
14465 /* If we got here, we have branch-relaxation disabled,
14466 and there's nothing we can do to fix this instruction
14467 without turning it into a longer sequence. */
14468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14469 _("Branch out of range"));
14473 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14474 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14475 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14476 /* We adjust the offset back to even. */
14477 if ((*valP
& 0x1) != 0)
14480 if (! fixP
->fx_done
)
14483 /* Should never visit here, because we keep the relocation. */
14487 case BFD_RELOC_VTABLE_INHERIT
:
14490 && !S_IS_DEFINED (fixP
->fx_addsy
)
14491 && !S_IS_WEAK (fixP
->fx_addsy
))
14492 S_SET_WEAK (fixP
->fx_addsy
);
14495 case BFD_RELOC_VTABLE_ENTRY
:
14503 /* Remember value for tc_gen_reloc. */
14504 fixP
->fx_addnumber
= *valP
;
14514 name
= input_line_pointer
;
14515 c
= get_symbol_end ();
14516 p
= (symbolS
*) symbol_find_or_make (name
);
14517 *input_line_pointer
= c
;
14521 /* Align the current frag to a given power of two. If a particular
14522 fill byte should be used, FILL points to an integer that contains
14523 that byte, otherwise FILL is null.
14525 This function used to have the comment:
14527 The MIPS assembler also automatically adjusts any preceding label.
14529 The implementation therefore applied the adjustment to a maximum of
14530 one label. However, other label adjustments are applied to batches
14531 of labels, and adjusting just one caused problems when new labels
14532 were added for the sake of debugging or unwind information.
14533 We therefore adjust all preceding labels (given as LABELS) instead. */
14536 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14538 mips_emit_delays ();
14539 mips_record_compressed_mode ();
14540 if (fill
== NULL
&& subseg_text_p (now_seg
))
14541 frag_align_code (to
, 0);
14543 frag_align (to
, fill
? *fill
: 0, 0);
14544 record_alignment (now_seg
, to
);
14545 mips_move_labels (labels
, FALSE
);
14548 /* Align to a given power of two. .align 0 turns off the automatic
14549 alignment used by the data creating pseudo-ops. */
14552 s_align (int x ATTRIBUTE_UNUSED
)
14554 int temp
, fill_value
, *fill_ptr
;
14555 long max_alignment
= 28;
14557 /* o Note that the assembler pulls down any immediately preceding label
14558 to the aligned address.
14559 o It's not documented but auto alignment is reinstated by
14560 a .align pseudo instruction.
14561 o Note also that after auto alignment is turned off the mips assembler
14562 issues an error on attempt to assemble an improperly aligned data item.
14565 temp
= get_absolute_expression ();
14566 if (temp
> max_alignment
)
14567 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
14570 as_warn (_("Alignment negative: 0 assumed."));
14573 if (*input_line_pointer
== ',')
14575 ++input_line_pointer
;
14576 fill_value
= get_absolute_expression ();
14577 fill_ptr
= &fill_value
;
14583 segment_info_type
*si
= seg_info (now_seg
);
14584 struct insn_label_list
*l
= si
->label_list
;
14585 /* Auto alignment should be switched on by next section change. */
14587 mips_align (temp
, fill_ptr
, l
);
14594 demand_empty_rest_of_line ();
14598 s_change_sec (int sec
)
14602 /* The ELF backend needs to know that we are changing sections, so
14603 that .previous works correctly. We could do something like check
14604 for an obj_section_change_hook macro, but that might be confusing
14605 as it would not be appropriate to use it in the section changing
14606 functions in read.c, since obj-elf.c intercepts those. FIXME:
14607 This should be cleaner, somehow. */
14608 obj_elf_section_change_hook ();
14610 mips_emit_delays ();
14621 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14622 demand_empty_rest_of_line ();
14626 seg
= subseg_new (RDATA_SECTION_NAME
,
14627 (subsegT
) get_absolute_expression ());
14628 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14629 | SEC_READONLY
| SEC_RELOC
14631 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14632 record_alignment (seg
, 4);
14633 demand_empty_rest_of_line ();
14637 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14638 bfd_set_section_flags (stdoutput
, seg
,
14639 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14640 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14641 record_alignment (seg
, 4);
14642 demand_empty_rest_of_line ();
14646 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14647 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14648 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14649 record_alignment (seg
, 4);
14650 demand_empty_rest_of_line ();
14658 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14660 char *section_name
;
14665 int section_entry_size
;
14666 int section_alignment
;
14668 section_name
= input_line_pointer
;
14669 c
= get_symbol_end ();
14671 next_c
= *(input_line_pointer
+ 1);
14673 /* Do we have .section Name<,"flags">? */
14674 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14676 /* just after name is now '\0'. */
14677 *input_line_pointer
= c
;
14678 input_line_pointer
= section_name
;
14679 obj_elf_section (ignore
);
14682 input_line_pointer
++;
14684 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14686 section_type
= get_absolute_expression ();
14689 if (*input_line_pointer
++ == ',')
14690 section_flag
= get_absolute_expression ();
14693 if (*input_line_pointer
++ == ',')
14694 section_entry_size
= get_absolute_expression ();
14696 section_entry_size
= 0;
14697 if (*input_line_pointer
++ == ',')
14698 section_alignment
= get_absolute_expression ();
14700 section_alignment
= 0;
14701 /* FIXME: really ignore? */
14702 (void) section_alignment
;
14704 section_name
= xstrdup (section_name
);
14706 /* When using the generic form of .section (as implemented by obj-elf.c),
14707 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14708 traditionally had to fall back on the more common @progbits instead.
14710 There's nothing really harmful in this, since bfd will correct
14711 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14712 means that, for backwards compatibility, the special_section entries
14713 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14715 Even so, we shouldn't force users of the MIPS .section syntax to
14716 incorrectly label the sections as SHT_PROGBITS. The best compromise
14717 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14718 generic type-checking code. */
14719 if (section_type
== SHT_MIPS_DWARF
)
14720 section_type
= SHT_PROGBITS
;
14722 obj_elf_change_section (section_name
, section_type
, section_flag
,
14723 section_entry_size
, 0, 0, 0);
14725 if (now_seg
->name
!= section_name
)
14726 free (section_name
);
14730 mips_enable_auto_align (void)
14736 s_cons (int log_size
)
14738 segment_info_type
*si
= seg_info (now_seg
);
14739 struct insn_label_list
*l
= si
->label_list
;
14741 mips_emit_delays ();
14742 if (log_size
> 0 && auto_align
)
14743 mips_align (log_size
, 0, l
);
14744 cons (1 << log_size
);
14745 mips_clear_insn_labels ();
14749 s_float_cons (int type
)
14751 segment_info_type
*si
= seg_info (now_seg
);
14752 struct insn_label_list
*l
= si
->label_list
;
14754 mips_emit_delays ();
14759 mips_align (3, 0, l
);
14761 mips_align (2, 0, l
);
14765 mips_clear_insn_labels ();
14768 /* Handle .globl. We need to override it because on Irix 5 you are
14771 where foo is an undefined symbol, to mean that foo should be
14772 considered to be the address of a function. */
14775 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14784 name
= input_line_pointer
;
14785 c
= get_symbol_end ();
14786 symbolP
= symbol_find_or_make (name
);
14787 S_SET_EXTERNAL (symbolP
);
14789 *input_line_pointer
= c
;
14790 SKIP_WHITESPACE ();
14792 /* On Irix 5, every global symbol that is not explicitly labelled as
14793 being a function is apparently labelled as being an object. */
14796 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14797 && (*input_line_pointer
!= ','))
14802 secname
= input_line_pointer
;
14803 c
= get_symbol_end ();
14804 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14806 as_bad (_("%s: no such section"), secname
);
14807 *input_line_pointer
= c
;
14809 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14810 flag
= BSF_FUNCTION
;
14813 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14815 c
= *input_line_pointer
;
14818 input_line_pointer
++;
14819 SKIP_WHITESPACE ();
14820 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14826 demand_empty_rest_of_line ();
14830 s_option (int x ATTRIBUTE_UNUSED
)
14835 opt
= input_line_pointer
;
14836 c
= get_symbol_end ();
14840 /* FIXME: What does this mean? */
14842 else if (strncmp (opt
, "pic", 3) == 0)
14846 i
= atoi (opt
+ 3);
14851 mips_pic
= SVR4_PIC
;
14852 mips_abicalls
= TRUE
;
14855 as_bad (_(".option pic%d not supported"), i
);
14857 if (mips_pic
== SVR4_PIC
)
14859 if (g_switch_seen
&& g_switch_value
!= 0)
14860 as_warn (_("-G may not be used with SVR4 PIC code"));
14861 g_switch_value
= 0;
14862 bfd_set_gp_size (stdoutput
, 0);
14866 as_warn (_("Unrecognized option \"%s\""), opt
);
14868 *input_line_pointer
= c
;
14869 demand_empty_rest_of_line ();
14872 /* This structure is used to hold a stack of .set values. */
14874 struct mips_option_stack
14876 struct mips_option_stack
*next
;
14877 struct mips_set_options options
;
14880 static struct mips_option_stack
*mips_opts_stack
;
14882 /* Handle the .set pseudo-op. */
14885 s_mipsset (int x ATTRIBUTE_UNUSED
)
14887 char *name
= input_line_pointer
, ch
;
14888 const struct mips_ase
*ase
;
14890 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14891 ++input_line_pointer
;
14892 ch
= *input_line_pointer
;
14893 *input_line_pointer
= '\0';
14895 if (strcmp (name
, "reorder") == 0)
14897 if (mips_opts
.noreorder
)
14900 else if (strcmp (name
, "noreorder") == 0)
14902 if (!mips_opts
.noreorder
)
14903 start_noreorder ();
14905 else if (strncmp (name
, "at=", 3) == 0)
14907 char *s
= name
+ 3;
14909 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
14910 as_bad (_("Unrecognized register name `%s'"), s
);
14912 else if (strcmp (name
, "at") == 0)
14914 mips_opts
.at
= ATREG
;
14916 else if (strcmp (name
, "noat") == 0)
14918 mips_opts
.at
= ZERO
;
14920 else if (strcmp (name
, "macro") == 0)
14922 mips_opts
.warn_about_macros
= 0;
14924 else if (strcmp (name
, "nomacro") == 0)
14926 if (mips_opts
.noreorder
== 0)
14927 as_bad (_("`noreorder' must be set before `nomacro'"));
14928 mips_opts
.warn_about_macros
= 1;
14930 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
14932 mips_opts
.nomove
= 0;
14934 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
14936 mips_opts
.nomove
= 1;
14938 else if (strcmp (name
, "bopt") == 0)
14940 mips_opts
.nobopt
= 0;
14942 else if (strcmp (name
, "nobopt") == 0)
14944 mips_opts
.nobopt
= 1;
14946 else if (strcmp (name
, "gp=default") == 0)
14947 mips_opts
.gp32
= file_mips_gp32
;
14948 else if (strcmp (name
, "gp=32") == 0)
14949 mips_opts
.gp32
= 1;
14950 else if (strcmp (name
, "gp=64") == 0)
14952 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14953 as_warn (_("%s isa does not support 64-bit registers"),
14954 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14955 mips_opts
.gp32
= 0;
14957 else if (strcmp (name
, "fp=default") == 0)
14958 mips_opts
.fp32
= file_mips_fp32
;
14959 else if (strcmp (name
, "fp=32") == 0)
14960 mips_opts
.fp32
= 1;
14961 else if (strcmp (name
, "fp=64") == 0)
14963 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14964 as_warn (_("%s isa does not support 64-bit floating point registers"),
14965 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14966 mips_opts
.fp32
= 0;
14968 else if (strcmp (name
, "softfloat") == 0)
14969 mips_opts
.soft_float
= 1;
14970 else if (strcmp (name
, "hardfloat") == 0)
14971 mips_opts
.soft_float
= 0;
14972 else if (strcmp (name
, "singlefloat") == 0)
14973 mips_opts
.single_float
= 1;
14974 else if (strcmp (name
, "doublefloat") == 0)
14975 mips_opts
.single_float
= 0;
14976 else if (strcmp (name
, "mips16") == 0
14977 || strcmp (name
, "MIPS-16") == 0)
14979 if (mips_opts
.micromips
== 1)
14980 as_fatal (_("`mips16' cannot be used with `micromips'"));
14981 mips_opts
.mips16
= 1;
14983 else if (strcmp (name
, "nomips16") == 0
14984 || strcmp (name
, "noMIPS-16") == 0)
14985 mips_opts
.mips16
= 0;
14986 else if (strcmp (name
, "micromips") == 0)
14988 if (mips_opts
.mips16
== 1)
14989 as_fatal (_("`micromips' cannot be used with `mips16'"));
14990 mips_opts
.micromips
= 1;
14992 else if (strcmp (name
, "nomicromips") == 0)
14993 mips_opts
.micromips
= 0;
14994 else if (name
[0] == 'n'
14996 && (ase
= mips_lookup_ase (name
+ 2)))
14997 mips_set_ase (ase
, FALSE
);
14998 else if ((ase
= mips_lookup_ase (name
)))
14999 mips_set_ase (ase
, TRUE
);
15000 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15004 /* Permit the user to change the ISA and architecture on the fly.
15005 Needless to say, misuse can cause serious problems. */
15006 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15009 mips_opts
.isa
= file_mips_isa
;
15010 mips_opts
.arch
= file_mips_arch
;
15012 else if (strncmp (name
, "arch=", 5) == 0)
15014 const struct mips_cpu_info
*p
;
15016 p
= mips_parse_cpu("internal use", name
+ 5);
15018 as_bad (_("unknown architecture %s"), name
+ 5);
15021 mips_opts
.arch
= p
->cpu
;
15022 mips_opts
.isa
= p
->isa
;
15025 else if (strncmp (name
, "mips", 4) == 0)
15027 const struct mips_cpu_info
*p
;
15029 p
= mips_parse_cpu("internal use", name
);
15031 as_bad (_("unknown ISA level %s"), name
+ 4);
15034 mips_opts
.arch
= p
->cpu
;
15035 mips_opts
.isa
= p
->isa
;
15039 as_bad (_("unknown ISA or architecture %s"), name
);
15041 switch (mips_opts
.isa
)
15049 mips_opts
.gp32
= 1;
15050 mips_opts
.fp32
= 1;
15057 mips_opts
.gp32
= 0;
15058 if (mips_opts
.arch
== CPU_R5900
)
15060 mips_opts
.fp32
= 1;
15064 mips_opts
.fp32
= 0;
15068 as_bad (_("unknown ISA level %s"), name
+ 4);
15073 mips_opts
.gp32
= file_mips_gp32
;
15074 mips_opts
.fp32
= file_mips_fp32
;
15077 else if (strcmp (name
, "autoextend") == 0)
15078 mips_opts
.noautoextend
= 0;
15079 else if (strcmp (name
, "noautoextend") == 0)
15080 mips_opts
.noautoextend
= 1;
15081 else if (strcmp (name
, "insn32") == 0)
15082 mips_opts
.insn32
= TRUE
;
15083 else if (strcmp (name
, "noinsn32") == 0)
15084 mips_opts
.insn32
= FALSE
;
15085 else if (strcmp (name
, "push") == 0)
15087 struct mips_option_stack
*s
;
15089 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15090 s
->next
= mips_opts_stack
;
15091 s
->options
= mips_opts
;
15092 mips_opts_stack
= s
;
15094 else if (strcmp (name
, "pop") == 0)
15096 struct mips_option_stack
*s
;
15098 s
= mips_opts_stack
;
15100 as_bad (_(".set pop with no .set push"));
15103 /* If we're changing the reorder mode we need to handle
15104 delay slots correctly. */
15105 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15106 start_noreorder ();
15107 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15110 mips_opts
= s
->options
;
15111 mips_opts_stack
= s
->next
;
15115 else if (strcmp (name
, "sym32") == 0)
15116 mips_opts
.sym32
= TRUE
;
15117 else if (strcmp (name
, "nosym32") == 0)
15118 mips_opts
.sym32
= FALSE
;
15119 else if (strchr (name
, ','))
15121 /* Generic ".set" directive; use the generic handler. */
15122 *input_line_pointer
= ch
;
15123 input_line_pointer
= name
;
15129 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
15131 mips_check_isa_supports_ases ();
15132 *input_line_pointer
= ch
;
15133 demand_empty_rest_of_line ();
15136 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15137 .option pic2. It means to generate SVR4 PIC calls. */
15140 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15142 mips_pic
= SVR4_PIC
;
15143 mips_abicalls
= TRUE
;
15145 if (g_switch_seen
&& g_switch_value
!= 0)
15146 as_warn (_("-G may not be used with SVR4 PIC code"));
15147 g_switch_value
= 0;
15149 bfd_set_gp_size (stdoutput
, 0);
15150 demand_empty_rest_of_line ();
15153 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15154 PIC code. It sets the $gp register for the function based on the
15155 function address, which is in the register named in the argument.
15156 This uses a relocation against _gp_disp, which is handled specially
15157 by the linker. The result is:
15158 lui $gp,%hi(_gp_disp)
15159 addiu $gp,$gp,%lo(_gp_disp)
15160 addu $gp,$gp,.cpload argument
15161 The .cpload argument is normally $25 == $t9.
15163 The -mno-shared option changes this to:
15164 lui $gp,%hi(__gnu_local_gp)
15165 addiu $gp,$gp,%lo(__gnu_local_gp)
15166 and the argument is ignored. This saves an instruction, but the
15167 resulting code is not position independent; it uses an absolute
15168 address for __gnu_local_gp. Thus code assembled with -mno-shared
15169 can go into an ordinary executable, but not into a shared library. */
15172 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15178 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15179 .cpload is ignored. */
15180 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15186 if (mips_opts
.mips16
)
15188 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15189 ignore_rest_of_line ();
15193 /* .cpload should be in a .set noreorder section. */
15194 if (mips_opts
.noreorder
== 0)
15195 as_warn (_(".cpload not in noreorder section"));
15197 reg
= tc_get_register (0);
15199 /* If we need to produce a 64-bit address, we are better off using
15200 the default instruction sequence. */
15201 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15203 ex
.X_op
= O_symbol
;
15204 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15206 ex
.X_op_symbol
= NULL
;
15207 ex
.X_add_number
= 0;
15209 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15210 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15212 mips_mark_labels ();
15213 mips_assembling_insn
= TRUE
;
15216 macro_build_lui (&ex
, mips_gp_register
);
15217 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15218 mips_gp_register
, BFD_RELOC_LO16
);
15220 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15221 mips_gp_register
, reg
);
15224 mips_assembling_insn
= FALSE
;
15225 demand_empty_rest_of_line ();
15228 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15229 .cpsetup $reg1, offset|$reg2, label
15231 If offset is given, this results in:
15232 sd $gp, offset($sp)
15233 lui $gp, %hi(%neg(%gp_rel(label)))
15234 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15235 daddu $gp, $gp, $reg1
15237 If $reg2 is given, this results in:
15238 daddu $reg2, $gp, $0
15239 lui $gp, %hi(%neg(%gp_rel(label)))
15240 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15241 daddu $gp, $gp, $reg1
15242 $reg1 is normally $25 == $t9.
15244 The -mno-shared option replaces the last three instructions with
15246 addiu $gp,$gp,%lo(_gp) */
15249 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15251 expressionS ex_off
;
15252 expressionS ex_sym
;
15255 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15256 We also need NewABI support. */
15257 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15263 if (mips_opts
.mips16
)
15265 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15266 ignore_rest_of_line ();
15270 reg1
= tc_get_register (0);
15271 SKIP_WHITESPACE ();
15272 if (*input_line_pointer
!= ',')
15274 as_bad (_("missing argument separator ',' for .cpsetup"));
15278 ++input_line_pointer
;
15279 SKIP_WHITESPACE ();
15280 if (*input_line_pointer
== '$')
15282 mips_cpreturn_register
= tc_get_register (0);
15283 mips_cpreturn_offset
= -1;
15287 mips_cpreturn_offset
= get_absolute_expression ();
15288 mips_cpreturn_register
= -1;
15290 SKIP_WHITESPACE ();
15291 if (*input_line_pointer
!= ',')
15293 as_bad (_("missing argument separator ',' for .cpsetup"));
15297 ++input_line_pointer
;
15298 SKIP_WHITESPACE ();
15299 expression (&ex_sym
);
15301 mips_mark_labels ();
15302 mips_assembling_insn
= TRUE
;
15305 if (mips_cpreturn_register
== -1)
15307 ex_off
.X_op
= O_constant
;
15308 ex_off
.X_add_symbol
= NULL
;
15309 ex_off
.X_op_symbol
= NULL
;
15310 ex_off
.X_add_number
= mips_cpreturn_offset
;
15312 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15313 BFD_RELOC_LO16
, SP
);
15316 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15317 mips_gp_register
, 0);
15319 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15321 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15322 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15325 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15326 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15327 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15329 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15330 mips_gp_register
, reg1
);
15336 ex
.X_op
= O_symbol
;
15337 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15338 ex
.X_op_symbol
= NULL
;
15339 ex
.X_add_number
= 0;
15341 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15342 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15344 macro_build_lui (&ex
, mips_gp_register
);
15345 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15346 mips_gp_register
, BFD_RELOC_LO16
);
15351 mips_assembling_insn
= FALSE
;
15352 demand_empty_rest_of_line ();
15356 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15358 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15359 .cplocal is ignored. */
15360 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15366 if (mips_opts
.mips16
)
15368 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15369 ignore_rest_of_line ();
15373 mips_gp_register
= tc_get_register (0);
15374 demand_empty_rest_of_line ();
15377 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15378 offset from $sp. The offset is remembered, and after making a PIC
15379 call $gp is restored from that location. */
15382 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15386 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15387 .cprestore is ignored. */
15388 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15394 if (mips_opts
.mips16
)
15396 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15397 ignore_rest_of_line ();
15401 mips_cprestore_offset
= get_absolute_expression ();
15402 mips_cprestore_valid
= 1;
15404 ex
.X_op
= O_constant
;
15405 ex
.X_add_symbol
= NULL
;
15406 ex
.X_op_symbol
= NULL
;
15407 ex
.X_add_number
= mips_cprestore_offset
;
15409 mips_mark_labels ();
15410 mips_assembling_insn
= TRUE
;
15413 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15414 SP
, HAVE_64BIT_ADDRESSES
);
15417 mips_assembling_insn
= FALSE
;
15418 demand_empty_rest_of_line ();
15421 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15422 was given in the preceding .cpsetup, it results in:
15423 ld $gp, offset($sp)
15425 If a register $reg2 was given there, it results in:
15426 daddu $gp, $reg2, $0 */
15429 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15433 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15434 We also need NewABI support. */
15435 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15441 if (mips_opts
.mips16
)
15443 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15444 ignore_rest_of_line ();
15448 mips_mark_labels ();
15449 mips_assembling_insn
= TRUE
;
15452 if (mips_cpreturn_register
== -1)
15454 ex
.X_op
= O_constant
;
15455 ex
.X_add_symbol
= NULL
;
15456 ex
.X_op_symbol
= NULL
;
15457 ex
.X_add_number
= mips_cpreturn_offset
;
15459 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15462 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15463 mips_cpreturn_register
, 0);
15466 mips_assembling_insn
= FALSE
;
15467 demand_empty_rest_of_line ();
15470 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15471 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15472 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15473 debug information or MIPS16 TLS. */
15476 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15477 bfd_reloc_code_real_type rtype
)
15484 if (ex
.X_op
!= O_symbol
)
15486 as_bad (_("Unsupported use of %s"), dirstr
);
15487 ignore_rest_of_line ();
15490 p
= frag_more (bytes
);
15491 md_number_to_chars (p
, 0, bytes
);
15492 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15493 demand_empty_rest_of_line ();
15494 mips_clear_insn_labels ();
15497 /* Handle .dtprelword. */
15500 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15502 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15505 /* Handle .dtpreldword. */
15508 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15510 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15513 /* Handle .tprelword. */
15516 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15518 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15521 /* Handle .tpreldword. */
15524 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15526 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15529 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15530 code. It sets the offset to use in gp_rel relocations. */
15533 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15535 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15536 We also need NewABI support. */
15537 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15543 mips_gprel_offset
= get_absolute_expression ();
15545 demand_empty_rest_of_line ();
15548 /* Handle the .gpword pseudo-op. This is used when generating PIC
15549 code. It generates a 32 bit GP relative reloc. */
15552 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15554 segment_info_type
*si
;
15555 struct insn_label_list
*l
;
15559 /* When not generating PIC code, this is treated as .word. */
15560 if (mips_pic
!= SVR4_PIC
)
15566 si
= seg_info (now_seg
);
15567 l
= si
->label_list
;
15568 mips_emit_delays ();
15570 mips_align (2, 0, l
);
15573 mips_clear_insn_labels ();
15575 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15577 as_bad (_("Unsupported use of .gpword"));
15578 ignore_rest_of_line ();
15582 md_number_to_chars (p
, 0, 4);
15583 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15584 BFD_RELOC_GPREL32
);
15586 demand_empty_rest_of_line ();
15590 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15592 segment_info_type
*si
;
15593 struct insn_label_list
*l
;
15597 /* When not generating PIC code, this is treated as .dword. */
15598 if (mips_pic
!= SVR4_PIC
)
15604 si
= seg_info (now_seg
);
15605 l
= si
->label_list
;
15606 mips_emit_delays ();
15608 mips_align (3, 0, l
);
15611 mips_clear_insn_labels ();
15613 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15615 as_bad (_("Unsupported use of .gpdword"));
15616 ignore_rest_of_line ();
15620 md_number_to_chars (p
, 0, 8);
15621 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15622 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15624 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15625 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15626 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15628 demand_empty_rest_of_line ();
15631 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15632 tables. It generates a R_MIPS_EH reloc. */
15635 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15640 mips_emit_delays ();
15643 mips_clear_insn_labels ();
15645 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15647 as_bad (_("Unsupported use of .ehword"));
15648 ignore_rest_of_line ();
15652 md_number_to_chars (p
, 0, 4);
15653 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15654 BFD_RELOC_MIPS_EH
);
15656 demand_empty_rest_of_line ();
15659 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15660 tables in SVR4 PIC code. */
15663 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15667 /* This is ignored when not generating SVR4 PIC code. */
15668 if (mips_pic
!= SVR4_PIC
)
15674 mips_mark_labels ();
15675 mips_assembling_insn
= TRUE
;
15677 /* Add $gp to the register named as an argument. */
15679 reg
= tc_get_register (0);
15680 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15683 mips_assembling_insn
= FALSE
;
15684 demand_empty_rest_of_line ();
15687 /* Handle the .insn pseudo-op. This marks instruction labels in
15688 mips16/micromips mode. This permits the linker to handle them specially,
15689 such as generating jalx instructions when needed. We also make
15690 them odd for the duration of the assembly, in order to generate the
15691 right sort of code. We will make them even in the adjust_symtab
15692 routine, while leaving them marked. This is convenient for the
15693 debugger and the disassembler. The linker knows to make them odd
15697 s_insn (int ignore ATTRIBUTE_UNUSED
)
15699 mips_mark_labels ();
15701 demand_empty_rest_of_line ();
15704 /* Handle the .nan pseudo-op. */
15707 s_nan (int ignore ATTRIBUTE_UNUSED
)
15709 static const char str_legacy
[] = "legacy";
15710 static const char str_2008
[] = "2008";
15713 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15715 if (i
== sizeof (str_2008
) - 1
15716 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15717 mips_flag_nan2008
= TRUE
;
15718 else if (i
== sizeof (str_legacy
) - 1
15719 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15720 mips_flag_nan2008
= FALSE
;
15722 as_bad (_("Bad .nan directive"));
15724 input_line_pointer
+= i
;
15725 demand_empty_rest_of_line ();
15728 /* Handle a .stab[snd] directive. Ideally these directives would be
15729 implemented in a transparent way, so that removing them would not
15730 have any effect on the generated instructions. However, s_stab
15731 internally changes the section, so in practice we need to decide
15732 now whether the preceding label marks compressed code. We do not
15733 support changing the compression mode of a label after a .stab*
15734 directive, such as in:
15740 so the current mode wins. */
15743 s_mips_stab (int type
)
15745 mips_mark_labels ();
15749 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15752 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15759 name
= input_line_pointer
;
15760 c
= get_symbol_end ();
15761 symbolP
= symbol_find_or_make (name
);
15762 S_SET_WEAK (symbolP
);
15763 *input_line_pointer
= c
;
15765 SKIP_WHITESPACE ();
15767 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15769 if (S_IS_DEFINED (symbolP
))
15771 as_bad (_("ignoring attempt to redefine symbol %s"),
15772 S_GET_NAME (symbolP
));
15773 ignore_rest_of_line ();
15777 if (*input_line_pointer
== ',')
15779 ++input_line_pointer
;
15780 SKIP_WHITESPACE ();
15784 if (exp
.X_op
!= O_symbol
)
15786 as_bad (_("bad .weakext directive"));
15787 ignore_rest_of_line ();
15790 symbol_set_value_expression (symbolP
, &exp
);
15793 demand_empty_rest_of_line ();
15796 /* Parse a register string into a number. Called from the ECOFF code
15797 to parse .frame. The argument is non-zero if this is the frame
15798 register, so that we can record it in mips_frame_reg. */
15801 tc_get_register (int frame
)
15805 SKIP_WHITESPACE ();
15806 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15810 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15811 mips_frame_reg_valid
= 1;
15812 mips_cprestore_valid
= 0;
15818 md_section_align (asection
*seg
, valueT addr
)
15820 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15822 /* We don't need to align ELF sections to the full alignment.
15823 However, Irix 5 may prefer that we align them at least to a 16
15824 byte boundary. We don't bother to align the sections if we
15825 are targeted for an embedded system. */
15826 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15831 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15834 /* Utility routine, called from above as well. If called while the
15835 input file is still being read, it's only an approximation. (For
15836 example, a symbol may later become defined which appeared to be
15837 undefined earlier.) */
15840 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15845 if (g_switch_value
> 0)
15847 const char *symname
;
15850 /* Find out whether this symbol can be referenced off the $gp
15851 register. It can be if it is smaller than the -G size or if
15852 it is in the .sdata or .sbss section. Certain symbols can
15853 not be referenced off the $gp, although it appears as though
15855 symname
= S_GET_NAME (sym
);
15856 if (symname
!= (const char *) NULL
15857 && (strcmp (symname
, "eprol") == 0
15858 || strcmp (symname
, "etext") == 0
15859 || strcmp (symname
, "_gp") == 0
15860 || strcmp (symname
, "edata") == 0
15861 || strcmp (symname
, "_fbss") == 0
15862 || strcmp (symname
, "_fdata") == 0
15863 || strcmp (symname
, "_ftext") == 0
15864 || strcmp (symname
, "end") == 0
15865 || strcmp (symname
, "_gp_disp") == 0))
15867 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15869 #ifndef NO_ECOFF_DEBUGGING
15870 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15871 && (symbol_get_obj (sym
)->ecoff_extern_size
15872 <= g_switch_value
))
15874 /* We must defer this decision until after the whole
15875 file has been read, since there might be a .extern
15876 after the first use of this symbol. */
15877 || (before_relaxing
15878 #ifndef NO_ECOFF_DEBUGGING
15879 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15881 && S_GET_VALUE (sym
) == 0)
15882 || (S_GET_VALUE (sym
) != 0
15883 && S_GET_VALUE (sym
) <= g_switch_value
)))
15887 const char *segname
;
15889 segname
= segment_name (S_GET_SEGMENT (sym
));
15890 gas_assert (strcmp (segname
, ".lit8") != 0
15891 && strcmp (segname
, ".lit4") != 0);
15892 change
= (strcmp (segname
, ".sdata") != 0
15893 && strcmp (segname
, ".sbss") != 0
15894 && strncmp (segname
, ".sdata.", 7) != 0
15895 && strncmp (segname
, ".sbss.", 6) != 0
15896 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
15897 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
15902 /* We are not optimizing for the $gp register. */
15907 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15910 pic_need_relax (symbolS
*sym
, asection
*segtype
)
15914 /* Handle the case of a symbol equated to another symbol. */
15915 while (symbol_equated_reloc_p (sym
))
15919 /* It's possible to get a loop here in a badly written program. */
15920 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
15926 if (symbol_section_p (sym
))
15929 symsec
= S_GET_SEGMENT (sym
);
15931 /* This must duplicate the test in adjust_reloc_syms. */
15932 return (!bfd_is_und_section (symsec
)
15933 && !bfd_is_abs_section (symsec
)
15934 && !bfd_is_com_section (symsec
)
15935 && !s_is_linkonce (sym
, segtype
)
15936 /* A global or weak symbol is treated as external. */
15937 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
15941 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15942 extended opcode. SEC is the section the frag is in. */
15945 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
15948 const struct mips_int_operand
*operand
;
15953 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
15955 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
15958 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
15959 operand
= mips16_immed_operand (type
, FALSE
);
15961 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
15962 val
= S_GET_VALUE (fragp
->fr_symbol
);
15963 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
15965 if (operand
->root
.type
== OP_PCREL
)
15967 const struct mips_pcrel_operand
*pcrel_op
;
15971 /* We won't have the section when we are called from
15972 mips_relax_frag. However, we will always have been called
15973 from md_estimate_size_before_relax first. If this is a
15974 branch to a different section, we mark it as such. If SEC is
15975 NULL, and the frag is not marked, then it must be a branch to
15976 the same section. */
15977 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
15980 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
15985 /* Must have been called from md_estimate_size_before_relax. */
15988 fragp
->fr_subtype
=
15989 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15991 /* FIXME: We should support this, and let the linker
15992 catch branches and loads that are out of range. */
15993 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
15994 _("unsupported PC relative reference to different section"));
15998 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
15999 /* Assume non-extended on the first relaxation pass.
16000 The address we have calculated will be bogus if this is
16001 a forward branch to another frag, as the forward frag
16002 will have fr_address == 0. */
16006 /* In this case, we know for sure that the symbol fragment is in
16007 the same section. If the relax_marker of the symbol fragment
16008 differs from the relax_marker of this fragment, we have not
16009 yet adjusted the symbol fragment fr_address. We want to add
16010 in STRETCH in order to get a better estimate of the address.
16011 This particularly matters because of the shift bits. */
16013 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16017 /* Adjust stretch for any alignment frag. Note that if have
16018 been expanding the earlier code, the symbol may be
16019 defined in what appears to be an earlier frag. FIXME:
16020 This doesn't handle the fr_subtype field, which specifies
16021 a maximum number of bytes to skip when doing an
16023 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16025 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16028 stretch
= - ((- stretch
)
16029 & ~ ((1 << (int) f
->fr_offset
) - 1));
16031 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16040 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16042 /* The base address rules are complicated. The base address of
16043 a branch is the following instruction. The base address of a
16044 PC relative load or add is the instruction itself, but if it
16045 is in a delay slot (in which case it can not be extended) use
16046 the address of the instruction whose delay slot it is in. */
16047 if (pcrel_op
->include_isa_bit
)
16051 /* If we are currently assuming that this frag should be
16052 extended, then, the current address is two bytes
16054 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16057 /* Ignore the low bit in the target, since it will be set
16058 for a text label. */
16061 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16063 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16066 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16068 /* If any of the shifted bits are set, we must use an extended
16069 opcode. If the address depends on the size of this
16070 instruction, this can lead to a loop, so we arrange to always
16071 use an extended opcode. We only check this when we are in
16072 the main relaxation loop, when SEC is NULL. */
16073 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16075 fragp
->fr_subtype
=
16076 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16080 /* If we are about to mark a frag as extended because the value
16081 is precisely the next value above maxtiny, then there is a
16082 chance of an infinite loop as in the following code:
16087 In this case when the la is extended, foo is 0x3fc bytes
16088 away, so the la can be shrunk, but then foo is 0x400 away, so
16089 the la must be extended. To avoid this loop, we mark the
16090 frag as extended if it was small, and is about to become
16091 extended with the next value above maxtiny. */
16092 maxtiny
= mips_int_operand_max (operand
);
16093 if (val
== maxtiny
+ (1 << operand
->shift
)
16094 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16097 fragp
->fr_subtype
=
16098 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16102 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16103 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16105 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16108 /* Compute the length of a branch sequence, and adjust the
16109 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16110 worst-case length is computed, with UPDATE being used to indicate
16111 whether an unconditional (-1), branch-likely (+1) or regular (0)
16112 branch is to be computed. */
16114 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16116 bfd_boolean toofar
;
16120 && S_IS_DEFINED (fragp
->fr_symbol
)
16121 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16126 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16128 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16132 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16135 /* If the symbol is not defined or it's in a different segment,
16136 assume the user knows what's going on and emit a short
16142 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16144 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16145 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16146 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16147 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16153 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16156 if (mips_pic
!= NO_PIC
)
16158 /* Additional space for PIC loading of target address. */
16160 if (mips_opts
.isa
== ISA_MIPS1
)
16161 /* Additional space for $at-stabilizing nop. */
16165 /* If branch is conditional. */
16166 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16173 /* Compute the length of a branch sequence, and adjust the
16174 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16175 worst-case length is computed, with UPDATE being used to indicate
16176 whether an unconditional (-1), or regular (0) branch is to be
16180 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16182 bfd_boolean toofar
;
16186 && S_IS_DEFINED (fragp
->fr_symbol
)
16187 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16192 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16193 /* Ignore the low bit in the target, since it will be set
16194 for a text label. */
16195 if ((val
& 1) != 0)
16198 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16202 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16205 /* If the symbol is not defined or it's in a different segment,
16206 assume the user knows what's going on and emit a short
16212 if (fragp
&& update
16213 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16214 fragp
->fr_subtype
= (toofar
16215 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16216 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16221 bfd_boolean compact_known
= fragp
!= NULL
;
16222 bfd_boolean compact
= FALSE
;
16223 bfd_boolean uncond
;
16226 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16228 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16230 uncond
= update
< 0;
16232 /* If label is out of range, we turn branch <br>:
16234 <br> label # 4 bytes
16240 nop # 2 bytes if compact && !PIC
16243 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16246 /* If assembling PIC code, we further turn:
16252 lw/ld at, %got(label)(gp) # 4 bytes
16253 d/addiu at, %lo(label) # 4 bytes
16256 if (mips_pic
!= NO_PIC
)
16259 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16261 <brneg> 0f # 4 bytes
16262 nop # 2 bytes if !compact
16265 length
+= (compact_known
&& compact
) ? 4 : 6;
16271 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16272 bit accordingly. */
16275 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16277 bfd_boolean toofar
;
16280 && S_IS_DEFINED (fragp
->fr_symbol
)
16281 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16287 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16288 /* Ignore the low bit in the target, since it will be set
16289 for a text label. */
16290 if ((val
& 1) != 0)
16293 /* Assume this is a 2-byte branch. */
16294 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16296 /* We try to avoid the infinite loop by not adding 2 more bytes for
16301 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16303 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16304 else if (type
== 'E')
16305 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16310 /* If the symbol is not defined or it's in a different segment,
16311 we emit a normal 32-bit branch. */
16314 if (fragp
&& update
16315 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16317 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16318 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16326 /* Estimate the size of a frag before relaxing. Unless this is the
16327 mips16, we are not really relaxing here, and the final size is
16328 encoded in the subtype information. For the mips16, we have to
16329 decide whether we are using an extended opcode or not. */
16332 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16336 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16339 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16341 return fragp
->fr_var
;
16344 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16345 /* We don't want to modify the EXTENDED bit here; it might get us
16346 into infinite loops. We change it only in mips_relax_frag(). */
16347 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16349 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16353 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16354 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16355 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16356 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16357 fragp
->fr_var
= length
;
16362 if (mips_pic
== NO_PIC
)
16363 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16364 else if (mips_pic
== SVR4_PIC
)
16365 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16366 else if (mips_pic
== VXWORKS_PIC
)
16367 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16374 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16375 return -RELAX_FIRST (fragp
->fr_subtype
);
16378 return -RELAX_SECOND (fragp
->fr_subtype
);
16381 /* This is called to see whether a reloc against a defined symbol
16382 should be converted into a reloc against a section. */
16385 mips_fix_adjustable (fixS
*fixp
)
16387 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16388 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16391 if (fixp
->fx_addsy
== NULL
)
16394 /* If symbol SYM is in a mergeable section, relocations of the form
16395 SYM + 0 can usually be made section-relative. The mergeable data
16396 is then identified by the section offset rather than by the symbol.
16398 However, if we're generating REL LO16 relocations, the offset is split
16399 between the LO16 and parterning high part relocation. The linker will
16400 need to recalculate the complete offset in order to correctly identify
16403 The linker has traditionally not looked for the parterning high part
16404 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16405 placed anywhere. Rather than break backwards compatibility by changing
16406 this, it seems better not to force the issue, and instead keep the
16407 original symbol. This will work with either linker behavior. */
16408 if ((lo16_reloc_p (fixp
->fx_r_type
)
16409 || reloc_needs_lo_p (fixp
->fx_r_type
))
16410 && HAVE_IN_PLACE_ADDENDS
16411 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16414 /* There is no place to store an in-place offset for JALR relocations.
16415 Likewise an in-range offset of limited PC-relative relocations may
16416 overflow the in-place relocatable field if recalculated against the
16417 start address of the symbol's containing section. */
16418 if (HAVE_IN_PLACE_ADDENDS
16419 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16420 || jalr_reloc_p (fixp
->fx_r_type
)))
16423 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16424 to a floating-point stub. The same is true for non-R_MIPS16_26
16425 relocations against MIPS16 functions; in this case, the stub becomes
16426 the function's canonical address.
16428 Floating-point stubs are stored in unique .mips16.call.* or
16429 .mips16.fn.* sections. If a stub T for function F is in section S,
16430 the first relocation in section S must be against F; this is how the
16431 linker determines the target function. All relocations that might
16432 resolve to T must also be against F. We therefore have the following
16433 restrictions, which are given in an intentionally-redundant way:
16435 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16438 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16439 if that stub might be used.
16441 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16444 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16445 that stub might be used.
16447 There is a further restriction:
16449 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16450 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16451 targets with in-place addends; the relocation field cannot
16452 encode the low bit.
16454 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16455 against a MIPS16 symbol. We deal with (5) by by not reducing any
16456 such relocations on REL targets.
16458 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16459 relocation against some symbol R, no relocation against R may be
16460 reduced. (Note that this deals with (2) as well as (1) because
16461 relocations against global symbols will never be reduced on ELF
16462 targets.) This approach is a little simpler than trying to detect
16463 stub sections, and gives the "all or nothing" per-symbol consistency
16464 that we have for MIPS16 symbols. */
16465 if (fixp
->fx_subsy
== NULL
16466 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16467 || *symbol_get_tc (fixp
->fx_addsy
)
16468 || (HAVE_IN_PLACE_ADDENDS
16469 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16470 && jmp_reloc_p (fixp
->fx_r_type
))))
16476 /* Translate internal representation of relocation info to BFD target
16480 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16482 static arelent
*retval
[4];
16484 bfd_reloc_code_real_type code
;
16486 memset (retval
, 0, sizeof(retval
));
16487 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16488 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16489 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16490 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16492 if (fixp
->fx_pcrel
)
16494 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16495 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16496 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16497 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16498 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16500 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16501 Relocations want only the symbol offset. */
16502 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16505 reloc
->addend
= fixp
->fx_addnumber
;
16507 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16508 entry to be used in the relocation's section offset. */
16509 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16511 reloc
->address
= reloc
->addend
;
16515 code
= fixp
->fx_r_type
;
16517 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16518 if (reloc
->howto
== NULL
)
16520 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16521 _("Can not represent %s relocation in this object file format"),
16522 bfd_get_reloc_code_name (code
));
16529 /* Relax a machine dependent frag. This returns the amount by which
16530 the current size of the frag should change. */
16533 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16535 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16537 offsetT old_var
= fragp
->fr_var
;
16539 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16541 return fragp
->fr_var
- old_var
;
16544 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16546 offsetT old_var
= fragp
->fr_var
;
16547 offsetT new_var
= 4;
16549 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16550 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16551 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16552 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16553 fragp
->fr_var
= new_var
;
16555 return new_var
- old_var
;
16558 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16561 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16563 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16565 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16570 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16572 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16579 /* Convert a machine dependent frag. */
16582 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16584 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16587 unsigned long insn
;
16591 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16592 insn
= read_insn (buf
);
16594 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16596 /* We generate a fixup instead of applying it right now
16597 because, if there are linker relaxations, we're going to
16598 need the relocations. */
16599 exp
.X_op
= O_symbol
;
16600 exp
.X_add_symbol
= fragp
->fr_symbol
;
16601 exp
.X_add_number
= fragp
->fr_offset
;
16603 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16604 BFD_RELOC_16_PCREL_S2
);
16605 fixp
->fx_file
= fragp
->fr_file
;
16606 fixp
->fx_line
= fragp
->fr_line
;
16608 buf
= write_insn (buf
, insn
);
16614 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16615 _("Relaxed out-of-range branch into a jump"));
16617 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16620 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16622 /* Reverse the branch. */
16623 switch ((insn
>> 28) & 0xf)
16626 /* bc[0-3][tf]l? instructions can have the condition
16627 reversed by tweaking a single TF bit, and their
16628 opcodes all have 0x4???????. */
16629 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16630 insn
^= 0x00010000;
16634 /* bltz 0x04000000 bgez 0x04010000
16635 bltzal 0x04100000 bgezal 0x04110000 */
16636 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16637 insn
^= 0x00010000;
16641 /* beq 0x10000000 bne 0x14000000
16642 blez 0x18000000 bgtz 0x1c000000 */
16643 insn
^= 0x04000000;
16651 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16653 /* Clear the and-link bit. */
16654 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16656 /* bltzal 0x04100000 bgezal 0x04110000
16657 bltzall 0x04120000 bgezall 0x04130000 */
16658 insn
&= ~0x00100000;
16661 /* Branch over the branch (if the branch was likely) or the
16662 full jump (not likely case). Compute the offset from the
16663 current instruction to branch to. */
16664 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16668 /* How many bytes in instructions we've already emitted? */
16669 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16670 /* How many bytes in instructions from here to the end? */
16671 i
= fragp
->fr_var
- i
;
16673 /* Convert to instruction count. */
16675 /* Branch counts from the next instruction. */
16678 /* Branch over the jump. */
16679 buf
= write_insn (buf
, insn
);
16682 buf
= write_insn (buf
, 0);
16684 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16686 /* beql $0, $0, 2f */
16688 /* Compute the PC offset from the current instruction to
16689 the end of the variable frag. */
16690 /* How many bytes in instructions we've already emitted? */
16691 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16692 /* How many bytes in instructions from here to the end? */
16693 i
= fragp
->fr_var
- i
;
16694 /* Convert to instruction count. */
16696 /* Don't decrement i, because we want to branch over the
16700 buf
= write_insn (buf
, insn
);
16701 buf
= write_insn (buf
, 0);
16705 if (mips_pic
== NO_PIC
)
16708 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16709 ? 0x0c000000 : 0x08000000);
16710 exp
.X_op
= O_symbol
;
16711 exp
.X_add_symbol
= fragp
->fr_symbol
;
16712 exp
.X_add_number
= fragp
->fr_offset
;
16714 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16715 FALSE
, BFD_RELOC_MIPS_JMP
);
16716 fixp
->fx_file
= fragp
->fr_file
;
16717 fixp
->fx_line
= fragp
->fr_line
;
16719 buf
= write_insn (buf
, insn
);
16723 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16725 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16726 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16727 insn
|= at
<< OP_SH_RT
;
16728 exp
.X_op
= O_symbol
;
16729 exp
.X_add_symbol
= fragp
->fr_symbol
;
16730 exp
.X_add_number
= fragp
->fr_offset
;
16732 if (fragp
->fr_offset
)
16734 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16735 exp
.X_add_number
= 0;
16738 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16739 FALSE
, BFD_RELOC_MIPS_GOT16
);
16740 fixp
->fx_file
= fragp
->fr_file
;
16741 fixp
->fx_line
= fragp
->fr_line
;
16743 buf
= write_insn (buf
, insn
);
16745 if (mips_opts
.isa
== ISA_MIPS1
)
16747 buf
= write_insn (buf
, 0);
16749 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16750 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16751 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16753 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16754 FALSE
, BFD_RELOC_LO16
);
16755 fixp
->fx_file
= fragp
->fr_file
;
16756 fixp
->fx_line
= fragp
->fr_line
;
16758 buf
= write_insn (buf
, insn
);
16761 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16765 insn
|= at
<< OP_SH_RS
;
16767 buf
= write_insn (buf
, insn
);
16771 fragp
->fr_fix
+= fragp
->fr_var
;
16772 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16776 /* Relax microMIPS branches. */
16777 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16779 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16780 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16781 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16782 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16783 bfd_boolean short_ds
;
16784 unsigned long insn
;
16788 exp
.X_op
= O_symbol
;
16789 exp
.X_add_symbol
= fragp
->fr_symbol
;
16790 exp
.X_add_number
= fragp
->fr_offset
;
16792 fragp
->fr_fix
+= fragp
->fr_var
;
16794 /* Handle 16-bit branches that fit or are forced to fit. */
16795 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16797 /* We generate a fixup instead of applying it right now,
16798 because if there is linker relaxation, we're going to
16799 need the relocations. */
16801 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16802 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16803 else if (type
== 'E')
16804 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16805 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16809 fixp
->fx_file
= fragp
->fr_file
;
16810 fixp
->fx_line
= fragp
->fr_line
;
16812 /* These relocations can have an addend that won't fit in
16814 fixp
->fx_no_overflow
= 1;
16819 /* Handle 32-bit branches that fit or are forced to fit. */
16820 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16821 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16823 /* We generate a fixup instead of applying it right now,
16824 because if there is linker relaxation, we're going to
16825 need the relocations. */
16826 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16827 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16828 fixp
->fx_file
= fragp
->fr_file
;
16829 fixp
->fx_line
= fragp
->fr_line
;
16835 /* Relax 16-bit branches to 32-bit branches. */
16838 insn
= read_compressed_insn (buf
, 2);
16840 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16841 insn
= 0x94000000; /* beq */
16842 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16844 unsigned long regno
;
16846 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16847 regno
= micromips_to_32_reg_d_map
[regno
];
16848 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16849 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16854 /* Nothing else to do, just write it out. */
16855 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16856 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16858 buf
= write_compressed_insn (buf
, insn
, 4);
16859 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16864 insn
= read_compressed_insn (buf
, 4);
16866 /* Relax 32-bit branches to a sequence of instructions. */
16867 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16868 _("Relaxed out-of-range branch into a jump"));
16870 /* Set the short-delay-slot bit. */
16871 short_ds
= al
&& (insn
& 0x02000000) != 0;
16873 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16877 /* Reverse the branch. */
16878 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16879 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16880 insn
^= 0x20000000;
16881 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
16882 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
16883 || (insn
& 0xffe00000) == 0x40800000 /* blez */
16884 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
16885 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
16886 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
16887 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
16888 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
16889 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
16890 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
16891 insn
^= 0x00400000;
16892 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
16893 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
16894 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
16895 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
16896 insn
^= 0x00200000;
16902 /* Clear the and-link and short-delay-slot bits. */
16903 gas_assert ((insn
& 0xfda00000) == 0x40200000);
16905 /* bltzal 0x40200000 bgezal 0x40600000 */
16906 /* bltzals 0x42200000 bgezals 0x42600000 */
16907 insn
&= ~0x02200000;
16910 /* Make a label at the end for use with the branch. */
16911 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
16912 micromips_label_inc ();
16913 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
16916 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
16917 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16918 fixp
->fx_file
= fragp
->fr_file
;
16919 fixp
->fx_line
= fragp
->fr_line
;
16921 /* Branch over the jump. */
16922 buf
= write_compressed_insn (buf
, insn
, 4);
16925 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16928 if (mips_pic
== NO_PIC
)
16930 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
16932 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16933 insn
= al
? jal
: 0xd4000000;
16935 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16936 BFD_RELOC_MICROMIPS_JMP
);
16937 fixp
->fx_file
= fragp
->fr_file
;
16938 fixp
->fx_line
= fragp
->fr_line
;
16940 buf
= write_compressed_insn (buf
, insn
, 4);
16943 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16947 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
16948 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
16949 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
16951 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16952 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
16953 insn
|= at
<< MICROMIPSOP_SH_RT
;
16955 if (exp
.X_add_number
)
16957 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16958 exp
.X_add_number
= 0;
16961 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16962 BFD_RELOC_MICROMIPS_GOT16
);
16963 fixp
->fx_file
= fragp
->fr_file
;
16964 fixp
->fx_line
= fragp
->fr_line
;
16966 buf
= write_compressed_insn (buf
, insn
, 4);
16968 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16969 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
16970 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
16972 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16973 BFD_RELOC_MICROMIPS_LO16
);
16974 fixp
->fx_file
= fragp
->fr_file
;
16975 fixp
->fx_line
= fragp
->fr_line
;
16977 buf
= write_compressed_insn (buf
, insn
, 4);
16979 /* jr/jrc/jalr/jalrs $at */
16980 insn
= al
? jalr
: jr
;
16981 insn
|= at
<< MICROMIPSOP_SH_MJ
;
16983 buf
= write_compressed_insn (buf
, insn
, 2);
16986 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16990 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16993 const struct mips_int_operand
*operand
;
16996 unsigned int user_length
, length
;
16997 unsigned long insn
;
17000 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17001 operand
= mips16_immed_operand (type
, FALSE
);
17003 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17004 val
= resolve_symbol_value (fragp
->fr_symbol
);
17005 if (operand
->root
.type
== OP_PCREL
)
17007 const struct mips_pcrel_operand
*pcrel_op
;
17010 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17011 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17013 /* The rules for the base address of a PC relative reloc are
17014 complicated; see mips16_extended_frag. */
17015 if (pcrel_op
->include_isa_bit
)
17020 /* Ignore the low bit in the target, since it will be
17021 set for a text label. */
17024 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17026 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17029 addr
&= -(1 << pcrel_op
->align_log2
);
17032 /* Make sure the section winds up with the alignment we have
17034 if (operand
->shift
> 0)
17035 record_alignment (asec
, operand
->shift
);
17039 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17040 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17041 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17042 _("extended instruction in delay slot"));
17044 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17046 insn
= read_compressed_insn (buf
, 2);
17048 insn
|= MIPS16_EXTEND
;
17050 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17052 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17057 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17058 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17060 length
= (ext
? 4 : 2);
17061 gas_assert (mips16_opcode_length (insn
) == length
);
17062 write_compressed_insn (buf
, insn
, length
);
17063 fragp
->fr_fix
+= length
;
17067 relax_substateT subtype
= fragp
->fr_subtype
;
17068 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17069 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17073 first
= RELAX_FIRST (subtype
);
17074 second
= RELAX_SECOND (subtype
);
17075 fixp
= (fixS
*) fragp
->fr_opcode
;
17077 /* If the delay slot chosen does not match the size of the instruction,
17078 then emit a warning. */
17079 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17080 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17085 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17086 | RELAX_DELAY_SLOT_SIZE_FIRST
17087 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17088 msg
= macro_warning (s
);
17090 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17094 /* Possibly emit a warning if we've chosen the longer option. */
17095 if (use_second
== second_longer
)
17101 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17102 msg
= macro_warning (s
);
17104 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17108 /* Go through all the fixups for the first sequence. Disable them
17109 (by marking them as done) if we're going to use the second
17110 sequence instead. */
17112 && fixp
->fx_frag
== fragp
17113 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17115 if (subtype
& RELAX_USE_SECOND
)
17117 fixp
= fixp
->fx_next
;
17120 /* Go through the fixups for the second sequence. Disable them if
17121 we're going to use the first sequence, otherwise adjust their
17122 addresses to account for the relaxation. */
17123 while (fixp
&& fixp
->fx_frag
== fragp
)
17125 if (subtype
& RELAX_USE_SECOND
)
17126 fixp
->fx_where
-= first
;
17129 fixp
= fixp
->fx_next
;
17132 /* Now modify the frag contents. */
17133 if (subtype
& RELAX_USE_SECOND
)
17137 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17138 memmove (start
, start
+ first
, second
);
17139 fragp
->fr_fix
-= first
;
17142 fragp
->fr_fix
-= second
;
17146 /* This function is called after the relocs have been generated.
17147 We've been storing mips16 text labels as odd. Here we convert them
17148 back to even for the convenience of the debugger. */
17151 mips_frob_file_after_relocs (void)
17154 unsigned int count
, i
;
17156 syms
= bfd_get_outsymbols (stdoutput
);
17157 count
= bfd_get_symcount (stdoutput
);
17158 for (i
= 0; i
< count
; i
++, syms
++)
17159 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17160 && ((*syms
)->value
& 1) != 0)
17162 (*syms
)->value
&= ~1;
17163 /* If the symbol has an odd size, it was probably computed
17164 incorrectly, so adjust that as well. */
17165 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17166 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17170 /* This function is called whenever a label is defined, including fake
17171 labels instantiated off the dot special symbol. It is used when
17172 handling branch delays; if a branch has a label, we assume we cannot
17173 move it. This also bumps the value of the symbol by 1 in compressed
17177 mips_record_label (symbolS
*sym
)
17179 segment_info_type
*si
= seg_info (now_seg
);
17180 struct insn_label_list
*l
;
17182 if (free_insn_labels
== NULL
)
17183 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17186 l
= free_insn_labels
;
17187 free_insn_labels
= l
->next
;
17191 l
->next
= si
->label_list
;
17192 si
->label_list
= l
;
17195 /* This function is called as tc_frob_label() whenever a label is defined
17196 and adds a DWARF-2 record we only want for true labels. */
17199 mips_define_label (symbolS
*sym
)
17201 mips_record_label (sym
);
17202 dwarf2_emit_label (sym
);
17205 /* This function is called by tc_new_dot_label whenever a new dot symbol
17209 mips_add_dot_label (symbolS
*sym
)
17211 mips_record_label (sym
);
17212 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17213 mips_compressed_mark_label (sym
);
17216 /* Some special processing for a MIPS ELF file. */
17219 mips_elf_final_processing (void)
17221 /* Write out the register information. */
17222 if (mips_abi
!= N64_ABI
)
17226 s
.ri_gprmask
= mips_gprmask
;
17227 s
.ri_cprmask
[0] = mips_cprmask
[0];
17228 s
.ri_cprmask
[1] = mips_cprmask
[1];
17229 s
.ri_cprmask
[2] = mips_cprmask
[2];
17230 s
.ri_cprmask
[3] = mips_cprmask
[3];
17231 /* The gp_value field is set by the MIPS ELF backend. */
17233 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17234 ((Elf32_External_RegInfo
*)
17235 mips_regmask_frag
));
17239 Elf64_Internal_RegInfo s
;
17241 s
.ri_gprmask
= mips_gprmask
;
17243 s
.ri_cprmask
[0] = mips_cprmask
[0];
17244 s
.ri_cprmask
[1] = mips_cprmask
[1];
17245 s
.ri_cprmask
[2] = mips_cprmask
[2];
17246 s
.ri_cprmask
[3] = mips_cprmask
[3];
17247 /* The gp_value field is set by the MIPS ELF backend. */
17249 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17250 ((Elf64_External_RegInfo
*)
17251 mips_regmask_frag
));
17254 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17255 sort of BFD interface for this. */
17256 if (mips_any_noreorder
)
17257 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17258 if (mips_pic
!= NO_PIC
)
17260 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17261 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17264 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17266 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17267 defined at present; this might need to change in future. */
17268 if (file_ase_mips16
)
17269 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17270 if (file_ase_micromips
)
17271 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17272 if (file_ase
& ASE_MDMX
)
17273 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17275 /* Set the MIPS ELF ABI flags. */
17276 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17277 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17278 else if (mips_abi
== O64_ABI
)
17279 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17280 else if (mips_abi
== EABI_ABI
)
17282 if (!file_mips_gp32
)
17283 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17285 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17287 else if (mips_abi
== N32_ABI
)
17288 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17290 /* Nothing to do for N64_ABI. */
17292 if (mips_32bitmode
)
17293 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17295 if (mips_flag_nan2008
)
17296 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17298 #if 0 /* XXX FIXME */
17299 /* 32 bit code with 64 bit FP registers. */
17300 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
17301 elf_elfheader (stdoutput
)->e_flags
|= ???;
17305 typedef struct proc
{
17307 symbolS
*func_end_sym
;
17308 unsigned long reg_mask
;
17309 unsigned long reg_offset
;
17310 unsigned long fpreg_mask
;
17311 unsigned long fpreg_offset
;
17312 unsigned long frame_offset
;
17313 unsigned long frame_reg
;
17314 unsigned long pc_reg
;
17317 static procS cur_proc
;
17318 static procS
*cur_proc_ptr
;
17319 static int numprocs
;
17321 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17322 as "2", and a normal nop as "0". */
17324 #define NOP_OPCODE_MIPS 0
17325 #define NOP_OPCODE_MIPS16 1
17326 #define NOP_OPCODE_MICROMIPS 2
17329 mips_nop_opcode (void)
17331 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17332 return NOP_OPCODE_MICROMIPS
;
17333 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17334 return NOP_OPCODE_MIPS16
;
17336 return NOP_OPCODE_MIPS
;
17339 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17340 32-bit microMIPS NOPs here (if applicable). */
17343 mips_handle_align (fragS
*fragp
)
17347 int bytes
, size
, excess
;
17350 if (fragp
->fr_type
!= rs_align_code
)
17353 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17355 switch (nop_opcode
)
17357 case NOP_OPCODE_MICROMIPS
:
17358 opcode
= micromips_nop32_insn
.insn_opcode
;
17361 case NOP_OPCODE_MIPS16
:
17362 opcode
= mips16_nop_insn
.insn_opcode
;
17365 case NOP_OPCODE_MIPS
:
17367 opcode
= nop_insn
.insn_opcode
;
17372 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17373 excess
= bytes
% size
;
17375 /* Handle the leading part if we're not inserting a whole number of
17376 instructions, and make it the end of the fixed part of the frag.
17377 Try to fit in a short microMIPS NOP if applicable and possible,
17378 and use zeroes otherwise. */
17379 gas_assert (excess
< 4);
17380 fragp
->fr_fix
+= excess
;
17385 /* Fall through. */
17387 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17389 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17393 /* Fall through. */
17396 /* Fall through. */
17401 md_number_to_chars (p
, opcode
, size
);
17402 fragp
->fr_var
= size
;
17406 md_obj_begin (void)
17413 /* Check for premature end, nesting errors, etc. */
17415 as_warn (_("missing .end at end of assembly"));
17424 if (*input_line_pointer
== '-')
17426 ++input_line_pointer
;
17429 if (!ISDIGIT (*input_line_pointer
))
17430 as_bad (_("expected simple number"));
17431 if (input_line_pointer
[0] == '0')
17433 if (input_line_pointer
[1] == 'x')
17435 input_line_pointer
+= 2;
17436 while (ISXDIGIT (*input_line_pointer
))
17439 val
|= hex_value (*input_line_pointer
++);
17441 return negative
? -val
: val
;
17445 ++input_line_pointer
;
17446 while (ISDIGIT (*input_line_pointer
))
17449 val
|= *input_line_pointer
++ - '0';
17451 return negative
? -val
: val
;
17454 if (!ISDIGIT (*input_line_pointer
))
17456 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17457 *input_line_pointer
, *input_line_pointer
);
17458 as_warn (_("invalid number"));
17461 while (ISDIGIT (*input_line_pointer
))
17464 val
+= *input_line_pointer
++ - '0';
17466 return negative
? -val
: val
;
17469 /* The .file directive; just like the usual .file directive, but there
17470 is an initial number which is the ECOFF file index. In the non-ECOFF
17471 case .file implies DWARF-2. */
17474 s_mips_file (int x ATTRIBUTE_UNUSED
)
17476 static int first_file_directive
= 0;
17478 if (ECOFF_DEBUGGING
)
17487 filename
= dwarf2_directive_file (0);
17489 /* Versions of GCC up to 3.1 start files with a ".file"
17490 directive even for stabs output. Make sure that this
17491 ".file" is handled. Note that you need a version of GCC
17492 after 3.1 in order to support DWARF-2 on MIPS. */
17493 if (filename
!= NULL
&& ! first_file_directive
)
17495 (void) new_logical_line (filename
, -1);
17496 s_app_file_string (filename
, 0);
17498 first_file_directive
= 1;
17502 /* The .loc directive, implying DWARF-2. */
17505 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17507 if (!ECOFF_DEBUGGING
)
17508 dwarf2_directive_loc (0);
17511 /* The .end directive. */
17514 s_mips_end (int x ATTRIBUTE_UNUSED
)
17518 /* Following functions need their own .frame and .cprestore directives. */
17519 mips_frame_reg_valid
= 0;
17520 mips_cprestore_valid
= 0;
17522 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17525 demand_empty_rest_of_line ();
17530 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17531 as_warn (_(".end not in text section"));
17535 as_warn (_(".end directive without a preceding .ent directive."));
17536 demand_empty_rest_of_line ();
17542 gas_assert (S_GET_NAME (p
));
17543 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17544 as_warn (_(".end symbol does not match .ent symbol."));
17546 if (debug_type
== DEBUG_STABS
)
17547 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17551 as_warn (_(".end directive missing or unknown symbol"));
17553 /* Create an expression to calculate the size of the function. */
17554 if (p
&& cur_proc_ptr
)
17556 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17557 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17560 exp
->X_op
= O_subtract
;
17561 exp
->X_add_symbol
= symbol_temp_new_now ();
17562 exp
->X_op_symbol
= p
;
17563 exp
->X_add_number
= 0;
17565 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17568 /* Generate a .pdr section. */
17569 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17571 segT saved_seg
= now_seg
;
17572 subsegT saved_subseg
= now_subseg
;
17576 #ifdef md_flush_pending_output
17577 md_flush_pending_output ();
17580 gas_assert (pdr_seg
);
17581 subseg_set (pdr_seg
, 0);
17583 /* Write the symbol. */
17584 exp
.X_op
= O_symbol
;
17585 exp
.X_add_symbol
= p
;
17586 exp
.X_add_number
= 0;
17587 emit_expr (&exp
, 4);
17589 fragp
= frag_more (7 * 4);
17591 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17592 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17593 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17594 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17595 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17596 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17597 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17599 subseg_set (saved_seg
, saved_subseg
);
17602 cur_proc_ptr
= NULL
;
17605 /* The .aent and .ent directives. */
17608 s_mips_ent (int aent
)
17612 symbolP
= get_symbol ();
17613 if (*input_line_pointer
== ',')
17614 ++input_line_pointer
;
17615 SKIP_WHITESPACE ();
17616 if (ISDIGIT (*input_line_pointer
)
17617 || *input_line_pointer
== '-')
17620 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17621 as_warn (_(".ent or .aent not in text section."));
17623 if (!aent
&& cur_proc_ptr
)
17624 as_warn (_("missing .end"));
17628 /* This function needs its own .frame and .cprestore directives. */
17629 mips_frame_reg_valid
= 0;
17630 mips_cprestore_valid
= 0;
17632 cur_proc_ptr
= &cur_proc
;
17633 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17635 cur_proc_ptr
->func_sym
= symbolP
;
17639 if (debug_type
== DEBUG_STABS
)
17640 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17641 S_GET_NAME (symbolP
));
17644 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17646 demand_empty_rest_of_line ();
17649 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17650 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17651 s_mips_frame is used so that we can set the PDR information correctly.
17652 We can't use the ecoff routines because they make reference to the ecoff
17653 symbol table (in the mdebug section). */
17656 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17658 if (ECOFF_DEBUGGING
)
17664 if (cur_proc_ptr
== (procS
*) NULL
)
17666 as_warn (_(".frame outside of .ent"));
17667 demand_empty_rest_of_line ();
17671 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17673 SKIP_WHITESPACE ();
17674 if (*input_line_pointer
++ != ','
17675 || get_absolute_expression_and_terminator (&val
) != ',')
17677 as_warn (_("Bad .frame directive"));
17678 --input_line_pointer
;
17679 demand_empty_rest_of_line ();
17683 cur_proc_ptr
->frame_offset
= val
;
17684 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17686 demand_empty_rest_of_line ();
17690 /* The .fmask and .mask directives. If the mdebug section is present
17691 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17692 embedded targets, s_mips_mask is used so that we can set the PDR
17693 information correctly. We can't use the ecoff routines because they
17694 make reference to the ecoff symbol table (in the mdebug section). */
17697 s_mips_mask (int reg_type
)
17699 if (ECOFF_DEBUGGING
)
17700 s_ignore (reg_type
);
17705 if (cur_proc_ptr
== (procS
*) NULL
)
17707 as_warn (_(".mask/.fmask outside of .ent"));
17708 demand_empty_rest_of_line ();
17712 if (get_absolute_expression_and_terminator (&mask
) != ',')
17714 as_warn (_("Bad .mask/.fmask directive"));
17715 --input_line_pointer
;
17716 demand_empty_rest_of_line ();
17720 off
= get_absolute_expression ();
17722 if (reg_type
== 'F')
17724 cur_proc_ptr
->fpreg_mask
= mask
;
17725 cur_proc_ptr
->fpreg_offset
= off
;
17729 cur_proc_ptr
->reg_mask
= mask
;
17730 cur_proc_ptr
->reg_offset
= off
;
17733 demand_empty_rest_of_line ();
17737 /* A table describing all the processors gas knows about. Names are
17738 matched in the order listed.
17740 To ease comparison, please keep this table in the same order as
17741 gcc's mips_cpu_info_table[]. */
17742 static const struct mips_cpu_info mips_cpu_info_table
[] =
17744 /* Entries for generic ISAs */
17745 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17746 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17747 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17748 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17749 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17750 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17751 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17752 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17753 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17756 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17757 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17758 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17761 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17764 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17765 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17766 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17767 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17768 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17769 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17770 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17771 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17772 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17773 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17774 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17775 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17776 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17777 /* ST Microelectronics Loongson 2E and 2F cores */
17778 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17779 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17782 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17783 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17784 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17785 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17786 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17787 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17788 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17789 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17790 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17791 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17792 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17793 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17794 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17795 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17796 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17799 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17800 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17801 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17802 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17804 /* MIPS 32 Release 2 */
17805 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17806 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17807 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17808 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17809 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17810 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17811 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17812 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17813 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17814 ISA_MIPS32R2
, CPU_MIPS32R2
},
17815 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17816 ISA_MIPS32R2
, CPU_MIPS32R2
},
17817 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17818 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17819 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17820 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17821 /* Deprecated forms of the above. */
17822 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17823 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17824 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17825 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17826 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17827 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17828 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17829 /* Deprecated forms of the above. */
17830 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17831 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17832 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17833 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17834 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17835 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17836 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17837 /* Deprecated forms of the above. */
17838 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17839 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17840 /* 34Kn is a 34kc without DSP. */
17841 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17842 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17843 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17844 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17845 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17846 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17847 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17848 /* Deprecated forms of the above. */
17849 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17850 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17851 /* 1004K cores are multiprocessor versions of the 34K. */
17852 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17853 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17854 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17855 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17858 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17859 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17860 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17861 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17863 /* Broadcom SB-1 CPU core */
17864 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17865 /* Broadcom SB-1A CPU core */
17866 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17868 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
17870 /* MIPS 64 Release 2 */
17872 /* Cavium Networks Octeon CPU core */
17873 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
17874 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
17875 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
17878 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
17881 XLP is mostly like XLR, with the prominent exception that it is
17882 MIPS64R2 rather than MIPS64. */
17883 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
17886 { NULL
, 0, 0, 0, 0 }
17890 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17891 with a final "000" replaced by "k". Ignore case.
17893 Note: this function is shared between GCC and GAS. */
17896 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
17898 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
17899 given
++, canonical
++;
17901 return ((*given
== 0 && *canonical
== 0)
17902 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
17906 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17907 CPU name. We've traditionally allowed a lot of variation here.
17909 Note: this function is shared between GCC and GAS. */
17912 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
17914 /* First see if the name matches exactly, or with a final "000"
17915 turned into "k". */
17916 if (mips_strict_matching_cpu_name_p (canonical
, given
))
17919 /* If not, try comparing based on numerical designation alone.
17920 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17921 if (TOLOWER (*given
) == 'r')
17923 if (!ISDIGIT (*given
))
17926 /* Skip over some well-known prefixes in the canonical name,
17927 hoping to find a number there too. */
17928 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
17930 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
17932 else if (TOLOWER (canonical
[0]) == 'r')
17935 return mips_strict_matching_cpu_name_p (canonical
, given
);
17939 /* Parse an option that takes the name of a processor as its argument.
17940 OPTION is the name of the option and CPU_STRING is the argument.
17941 Return the corresponding processor enumeration if the CPU_STRING is
17942 recognized, otherwise report an error and return null.
17944 A similar function exists in GCC. */
17946 static const struct mips_cpu_info
*
17947 mips_parse_cpu (const char *option
, const char *cpu_string
)
17949 const struct mips_cpu_info
*p
;
17951 /* 'from-abi' selects the most compatible architecture for the given
17952 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17953 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17954 version. Look first at the -mgp options, if given, otherwise base
17955 the choice on MIPS_DEFAULT_64BIT.
17957 Treat NO_ABI like the EABIs. One reason to do this is that the
17958 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17959 architecture. This code picks MIPS I for 'mips' and MIPS III for
17960 'mips64', just as we did in the days before 'from-abi'. */
17961 if (strcasecmp (cpu_string
, "from-abi") == 0)
17963 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
17964 return mips_cpu_info_from_isa (ISA_MIPS1
);
17966 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
17967 return mips_cpu_info_from_isa (ISA_MIPS3
);
17969 if (file_mips_gp32
>= 0)
17970 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
17972 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17977 /* 'default' has traditionally been a no-op. Probably not very useful. */
17978 if (strcasecmp (cpu_string
, "default") == 0)
17981 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
17982 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
17985 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
17989 /* Return the canonical processor information for ISA (a member of the
17990 ISA_MIPS* enumeration). */
17992 static const struct mips_cpu_info
*
17993 mips_cpu_info_from_isa (int isa
)
17997 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17998 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
17999 && isa
== mips_cpu_info_table
[i
].isa
)
18000 return (&mips_cpu_info_table
[i
]);
18005 static const struct mips_cpu_info
*
18006 mips_cpu_info_from_arch (int arch
)
18010 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18011 if (arch
== mips_cpu_info_table
[i
].cpu
)
18012 return (&mips_cpu_info_table
[i
]);
18018 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18022 fprintf (stream
, "%24s", "");
18027 fprintf (stream
, ", ");
18031 if (*col_p
+ strlen (string
) > 72)
18033 fprintf (stream
, "\n%24s", "");
18037 fprintf (stream
, "%s", string
);
18038 *col_p
+= strlen (string
);
18044 md_show_usage (FILE *stream
)
18049 fprintf (stream
, _("\
18051 -EB generate big endian output\n\
18052 -EL generate little endian output\n\
18053 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18054 -G NUM allow referencing objects up to NUM bytes\n\
18055 implicitly with the gp register [default 8]\n"));
18056 fprintf (stream
, _("\
18057 -mips1 generate MIPS ISA I instructions\n\
18058 -mips2 generate MIPS ISA II instructions\n\
18059 -mips3 generate MIPS ISA III instructions\n\
18060 -mips4 generate MIPS ISA IV instructions\n\
18061 -mips5 generate MIPS ISA V instructions\n\
18062 -mips32 generate MIPS32 ISA instructions\n\
18063 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18064 -mips64 generate MIPS64 ISA instructions\n\
18065 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18066 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18070 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18071 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18072 show (stream
, "from-abi", &column
, &first
);
18073 fputc ('\n', stream
);
18075 fprintf (stream
, _("\
18076 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18077 -no-mCPU don't generate code specific to CPU.\n\
18078 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18082 show (stream
, "3900", &column
, &first
);
18083 show (stream
, "4010", &column
, &first
);
18084 show (stream
, "4100", &column
, &first
);
18085 show (stream
, "4650", &column
, &first
);
18086 fputc ('\n', stream
);
18088 fprintf (stream
, _("\
18089 -mips16 generate mips16 instructions\n\
18090 -no-mips16 do not generate mips16 instructions\n"));
18091 fprintf (stream
, _("\
18092 -mmicromips generate microMIPS instructions\n\
18093 -mno-micromips do not generate microMIPS instructions\n"));
18094 fprintf (stream
, _("\
18095 -msmartmips generate smartmips instructions\n\
18096 -mno-smartmips do not generate smartmips instructions\n"));
18097 fprintf (stream
, _("\
18098 -mdsp generate DSP instructions\n\
18099 -mno-dsp do not generate DSP instructions\n"));
18100 fprintf (stream
, _("\
18101 -mdspr2 generate DSP R2 instructions\n\
18102 -mno-dspr2 do not generate DSP R2 instructions\n"));
18103 fprintf (stream
, _("\
18104 -mmt generate MT instructions\n\
18105 -mno-mt do not generate MT instructions\n"));
18106 fprintf (stream
, _("\
18107 -mmcu generate MCU instructions\n\
18108 -mno-mcu do not generate MCU instructions\n"));
18109 fprintf (stream
, _("\
18110 -mvirt generate Virtualization instructions\n\
18111 -mno-virt do not generate Virtualization instructions\n"));
18112 fprintf (stream
, _("\
18113 -minsn32 only generate 32-bit microMIPS instructions\n\
18114 -mno-insn32 generate all microMIPS instructions\n"));
18115 fprintf (stream
, _("\
18116 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18117 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18118 -mfix-vr4120 work around certain VR4120 errata\n\
18119 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18120 -mfix-24k insert a nop after ERET and DERET instructions\n\
18121 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18122 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18123 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18124 -msym32 assume all symbols have 32-bit values\n\
18125 -O0 remove unneeded NOPs, do not swap branches\n\
18126 -O remove unneeded NOPs and swap branches\n\
18127 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18128 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18129 fprintf (stream
, _("\
18130 -mhard-float allow floating-point instructions\n\
18131 -msoft-float do not allow floating-point instructions\n\
18132 -msingle-float only allow 32-bit floating-point operations\n\
18133 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18134 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18135 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18136 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18140 show (stream
, "legacy", &column
, &first
);
18141 show (stream
, "2008", &column
, &first
);
18143 fputc ('\n', stream
);
18145 fprintf (stream
, _("\
18146 -KPIC, -call_shared generate SVR4 position independent code\n\
18147 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18148 -mvxworks-pic generate VxWorks position independent code\n\
18149 -non_shared do not generate code that can operate with DSOs\n\
18150 -xgot assume a 32 bit GOT\n\
18151 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18152 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18153 position dependent (non shared) code\n\
18154 -mabi=ABI create ABI conformant object file for:\n"));
18158 show (stream
, "32", &column
, &first
);
18159 show (stream
, "o64", &column
, &first
);
18160 show (stream
, "n32", &column
, &first
);
18161 show (stream
, "64", &column
, &first
);
18162 show (stream
, "eabi", &column
, &first
);
18164 fputc ('\n', stream
);
18166 fprintf (stream
, _("\
18167 -32 create o32 ABI object file (default)\n\
18168 -n32 create n32 ABI object file\n\
18169 -64 create 64 ABI object file\n"));
18174 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18176 if (HAVE_64BIT_SYMBOLS
)
18177 return dwarf2_format_64bit_irix
;
18179 return dwarf2_format_32bit
;
18184 mips_dwarf2_addr_size (void)
18186 if (HAVE_64BIT_OBJECTS
)
18192 /* Standard calling conventions leave the CFA at SP on entry. */
18194 mips_cfi_frame_initial_instructions (void)
18196 cfi_add_CFA_def_cfa_register (SP
);
18200 tc_mips_regname_to_dw2regnum (char *regname
)
18202 unsigned int regnum
= -1;
18205 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))