1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* True if this is a mips16 instruction and if we want the extended
150 bfd_boolean use_extend
;
152 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
153 unsigned short extend
;
155 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
156 a copy of INSN_MO->match with the operands filled in. */
157 unsigned long insn_opcode
;
159 /* The frag that contains the instruction. */
162 /* The offset into FRAG of the first instruction byte. */
165 /* The relocs associated with the instruction, if any. */
168 /* True if this entry cannot be moved from its current position. */
169 unsigned int fixed_p
: 1;
171 /* True if this instruction occurred in a .set noreorder block. */
172 unsigned int noreorder_p
: 1;
174 /* True for mips16 instructions that jump to an absolute address. */
175 unsigned int mips16_absolute_jump_p
: 1;
177 /* True if this instruction is complete. */
178 unsigned int complete_p
: 1;
181 /* The ABI to use. */
192 /* MIPS ABI we are using for this output file. */
193 static enum mips_abi_level mips_abi
= NO_ABI
;
195 /* Whether or not we have code that can call pic code. */
196 int mips_abicalls
= FALSE
;
198 /* Whether or not we have code which can be put into a shared
200 static bfd_boolean mips_in_shared
= TRUE
;
202 /* This is the set of options which may be modified by the .set
203 pseudo-op. We use a struct so that .set push and .set pop are more
206 struct mips_set_options
208 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
209 if it has not been initialized. Changed by `.set mipsN', and the
210 -mipsN command line option, and the default CPU. */
212 /* Enabled Application Specific Extensions (ASEs). These are set to -1
213 if they have not been initialized. Changed by `.set <asename>', by
214 command line options, and based on the default architecture. */
222 /* Whether we are assembling for the mips16 processor. 0 if we are
223 not, 1 if we are, and -1 if the value has not been initialized.
224 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
225 -nomips16 command line options, and the default CPU. */
227 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
228 1 if we are, and -1 if the value has not been initialized. Changed
229 by `.set micromips' and `.set nomicromips', and the -mmicromips
230 and -mno-micromips command line options, and the default CPU. */
232 /* Non-zero if we should not reorder instructions. Changed by `.set
233 reorder' and `.set noreorder'. */
235 /* Non-zero if we should not permit the register designated "assembler
236 temporary" to be used in instructions. The value is the register
237 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
238 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
240 /* Non-zero if we should warn when a macro instruction expands into
241 more than one machine instruction. Changed by `.set nomacro' and
243 int warn_about_macros
;
244 /* Non-zero if we should not move instructions. Changed by `.set
245 move', `.set volatile', `.set nomove', and `.set novolatile'. */
247 /* Non-zero if we should not optimize branches by moving the target
248 of the branch into the delay slot. Actually, we don't perform
249 this optimization anyhow. Changed by `.set bopt' and `.set
252 /* Non-zero if we should not autoextend mips16 instructions.
253 Changed by `.set autoextend' and `.set noautoextend'. */
255 /* Restrict general purpose registers and floating point registers
256 to 32 bit. This is initially determined when -mgp32 or -mfp32
257 is passed but can changed if the assembler code uses .set mipsN. */
260 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
261 command line option, and the default CPU. */
263 /* True if ".set sym32" is in effect. */
265 /* True if floating-point operations are not allowed. Changed by .set
266 softfloat or .set hardfloat, by command line options -msoft-float or
267 -mhard-float. The default is false. */
268 bfd_boolean soft_float
;
270 /* True if only single-precision floating-point operations are allowed.
271 Changed by .set singlefloat or .set doublefloat, command-line options
272 -msingle-float or -mdouble-float. The default is false. */
273 bfd_boolean single_float
;
276 /* This is the struct we use to hold the current set of options. Note
277 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
278 -1 to indicate that they have not been initialized. */
280 /* True if -mgp32 was passed. */
281 static int file_mips_gp32
= -1;
283 /* True if -mfp32 was passed. */
284 static int file_mips_fp32
= -1;
286 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
287 static int file_mips_soft_float
= 0;
289 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
290 static int file_mips_single_float
= 0;
292 static struct mips_set_options mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
295 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
296 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
297 /* at */ ATREG
, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
298 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
299 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
302 /* These variables are filled in with the masks of registers used.
303 The object format code reads them and puts them in the appropriate
305 unsigned long mips_gprmask
;
306 unsigned long mips_cprmask
[4];
308 /* MIPS ISA we are using for this output file. */
309 static int file_mips_isa
= ISA_UNKNOWN
;
311 /* True if any MIPS16 code was produced. */
312 static int file_ase_mips16
;
314 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
315 || mips_opts.isa == ISA_MIPS32R2 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2)
319 /* True if any microMIPS code was produced. */
320 static int file_ase_micromips
;
322 /* True if we want to create R_MIPS_JALR for jalr $25. */
324 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
326 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
327 because there's no place for any addend, the only acceptable
328 expression is a bare symbol. */
329 #define MIPS_JALR_HINT_P(EXPR) \
330 (!HAVE_IN_PLACE_ADDENDS \
331 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
334 /* True if -mips3d was passed or implied by arguments passed on the
335 command line (e.g., by -march). */
336 static int file_ase_mips3d
;
338 /* True if -mdmx was passed or implied by arguments passed on the
339 command line (e.g., by -march). */
340 static int file_ase_mdmx
;
342 /* True if -msmartmips was passed or implied by arguments passed on the
343 command line (e.g., by -march). */
344 static int file_ase_smartmips
;
346 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
347 || mips_opts.isa == ISA_MIPS32R2)
349 /* True if -mdsp was passed or implied by arguments passed on the
350 command line (e.g., by -march). */
351 static int file_ase_dsp
;
353 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
354 || mips_opts.isa == ISA_MIPS64R2)
356 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
358 /* True if -mdspr2 was passed or implied by arguments passed on the
359 command line (e.g., by -march). */
360 static int file_ase_dspr2
;
362 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
363 || mips_opts.isa == ISA_MIPS64R2)
365 /* True if -mmt was passed or implied by arguments passed on the
366 command line (e.g., by -march). */
367 static int file_ase_mt
;
369 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
370 || mips_opts.isa == ISA_MIPS64R2)
372 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
373 || mips_opts.isa == ISA_MIPS64R2 \
374 || mips_opts.micromips)
376 /* The argument of the -march= flag. The architecture we are assembling. */
377 static int file_mips_arch
= CPU_UNKNOWN
;
378 static const char *mips_arch_string
;
380 /* The argument of the -mtune= flag. The architecture for which we
382 static int mips_tune
= CPU_UNKNOWN
;
383 static const char *mips_tune_string
;
385 /* True when generating 32-bit code for a 64-bit processor. */
386 static int mips_32bitmode
= 0;
388 /* True if the given ABI requires 32-bit registers. */
389 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
391 /* Likewise 64-bit registers. */
392 #define ABI_NEEDS_64BIT_REGS(ABI) \
394 || (ABI) == N64_ABI \
397 /* Return true if ISA supports 64 bit wide gp registers. */
398 #define ISA_HAS_64BIT_REGS(ISA) \
399 ((ISA) == ISA_MIPS3 \
400 || (ISA) == ISA_MIPS4 \
401 || (ISA) == ISA_MIPS5 \
402 || (ISA) == ISA_MIPS64 \
403 || (ISA) == ISA_MIPS64R2)
405 /* Return true if ISA supports 64 bit wide float registers. */
406 #define ISA_HAS_64BIT_FPRS(ISA) \
407 ((ISA) == ISA_MIPS3 \
408 || (ISA) == ISA_MIPS4 \
409 || (ISA) == ISA_MIPS5 \
410 || (ISA) == ISA_MIPS32R2 \
411 || (ISA) == ISA_MIPS64 \
412 || (ISA) == ISA_MIPS64R2)
414 /* Return true if ISA supports 64-bit right rotate (dror et al.)
416 #define ISA_HAS_DROR(ISA) \
417 ((ISA) == ISA_MIPS64R2 \
418 || (mips_opts.micromips \
419 && ISA_HAS_64BIT_REGS (ISA)) \
422 /* Return true if ISA supports 32-bit right rotate (ror et al.)
424 #define ISA_HAS_ROR(ISA) \
425 ((ISA) == ISA_MIPS32R2 \
426 || (ISA) == ISA_MIPS64R2 \
427 || mips_opts.ase_smartmips \
428 || mips_opts.micromips \
431 /* Return true if ISA supports single-precision floats in odd registers. */
432 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
433 ((ISA) == ISA_MIPS32 \
434 || (ISA) == ISA_MIPS32R2 \
435 || (ISA) == ISA_MIPS64 \
436 || (ISA) == ISA_MIPS64R2)
438 /* Return true if ISA supports move to/from high part of a 64-bit
439 floating-point register. */
440 #define ISA_HAS_MXHC1(ISA) \
441 ((ISA) == ISA_MIPS32R2 \
442 || (ISA) == ISA_MIPS64R2)
444 #define HAVE_32BIT_GPRS \
445 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
447 #define HAVE_32BIT_FPRS \
448 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
450 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
451 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
453 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
455 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
457 /* True if relocations are stored in-place. */
458 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
460 /* The ABI-derived address size. */
461 #define HAVE_64BIT_ADDRESSES \
462 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
463 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
465 /* The size of symbolic constants (i.e., expressions of the form
466 "SYMBOL" or "SYMBOL + OFFSET"). */
467 #define HAVE_32BIT_SYMBOLS \
468 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
469 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
471 /* Addresses are loaded in different ways, depending on the address size
472 in use. The n32 ABI Documentation also mandates the use of additions
473 with overflow checking, but existing implementations don't follow it. */
474 #define ADDRESS_ADD_INSN \
475 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
477 #define ADDRESS_ADDI_INSN \
478 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
480 #define ADDRESS_LOAD_INSN \
481 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
483 #define ADDRESS_STORE_INSN \
484 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
486 /* Return true if the given CPU supports the MIPS16 ASE. */
487 #define CPU_HAS_MIPS16(cpu) \
488 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
489 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
491 /* Return true if the given CPU supports the microMIPS ASE. */
492 #define CPU_HAS_MICROMIPS(cpu) 0
494 /* True if CPU has a dror instruction. */
495 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
497 /* True if CPU has a ror instruction. */
498 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
500 /* True if CPU is in the Octeon family */
501 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
503 /* True if CPU has seq/sne and seqi/snei instructions. */
504 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
506 /* True if CPU does not implement the all the coprocessor insns. For these
507 CPUs only those COP insns are accepted that are explicitly marked to be
508 available on the CPU. ISA membership for COP insns is ignored. */
509 #define NO_ISA_COP(CPU) (CPU_IS_OCTEON (CPU))
511 /* True if mflo and mfhi can be immediately followed by instructions
512 which write to the HI and LO registers.
514 According to MIPS specifications, MIPS ISAs I, II, and III need
515 (at least) two instructions between the reads of HI/LO and
516 instructions which write them, and later ISAs do not. Contradicting
517 the MIPS specifications, some MIPS IV processor user manuals (e.g.
518 the UM for the NEC Vr5000) document needing the instructions between
519 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
520 MIPS64 and later ISAs to have the interlocks, plus any specific
521 earlier-ISA CPUs for which CPU documentation declares that the
522 instructions are really interlocked. */
523 #define hilo_interlocks \
524 (mips_opts.isa == ISA_MIPS32 \
525 || mips_opts.isa == ISA_MIPS32R2 \
526 || mips_opts.isa == ISA_MIPS64 \
527 || mips_opts.isa == ISA_MIPS64R2 \
528 || mips_opts.arch == CPU_R4010 \
529 || mips_opts.arch == CPU_R10000 \
530 || mips_opts.arch == CPU_R12000 \
531 || mips_opts.arch == CPU_R14000 \
532 || mips_opts.arch == CPU_R16000 \
533 || mips_opts.arch == CPU_RM7000 \
534 || mips_opts.arch == CPU_VR5500 \
535 || mips_opts.micromips \
538 /* Whether the processor uses hardware interlocks to protect reads
539 from the GPRs after they are loaded from memory, and thus does not
540 require nops to be inserted. This applies to instructions marked
541 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
542 level I and microMIPS mode instructions are always interlocked. */
543 #define gpr_interlocks \
544 (mips_opts.isa != ISA_MIPS1 \
545 || mips_opts.arch == CPU_R3900 \
546 || mips_opts.micromips \
549 /* Whether the processor uses hardware interlocks to avoid delays
550 required by coprocessor instructions, and thus does not require
551 nops to be inserted. This applies to instructions marked
552 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
553 between instructions marked INSN_WRITE_COND_CODE and ones marked
554 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
555 levels I, II, and III and microMIPS mode instructions are always
557 /* Itbl support may require additional care here. */
558 #define cop_interlocks \
559 ((mips_opts.isa != ISA_MIPS1 \
560 && mips_opts.isa != ISA_MIPS2 \
561 && mips_opts.isa != ISA_MIPS3) \
562 || mips_opts.arch == CPU_R4300 \
563 || mips_opts.micromips \
566 /* Whether the processor uses hardware interlocks to protect reads
567 from coprocessor registers after they are loaded from memory, and
568 thus does not require nops to be inserted. This applies to
569 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
570 requires at MIPS ISA level I and microMIPS mode instructions are
571 always interlocked. */
572 #define cop_mem_interlocks \
573 (mips_opts.isa != ISA_MIPS1 \
574 || mips_opts.micromips \
577 /* Is this a mfhi or mflo instruction? */
578 #define MF_HILO_INSN(PINFO) \
579 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
581 /* Returns true for a (non floating-point) coprocessor instruction. Reading
582 or writing the condition code is only possible on the coprocessors and
583 these insns are not marked with INSN_COP. Thus for these insns use the
584 condition-code flags. */
585 #define COP_INSN(PINFO) \
586 (PINFO != INSN_MACRO \
587 && ((PINFO) & (FP_S | FP_D)) == 0 \
588 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
590 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
591 has been selected. This implies, in particular, that addresses of text
592 labels have their LSB set. */
593 #define HAVE_CODE_COMPRESSION \
594 ((mips_opts.mips16 | mips_opts.micromips) != 0)
596 /* MIPS PIC level. */
598 enum mips_pic_level mips_pic
;
600 /* 1 if we should generate 32 bit offsets from the $gp register in
601 SVR4_PIC mode. Currently has no meaning in other modes. */
602 static int mips_big_got
= 0;
604 /* 1 if trap instructions should used for overflow rather than break
606 static int mips_trap
= 0;
608 /* 1 if double width floating point constants should not be constructed
609 by assembling two single width halves into two single width floating
610 point registers which just happen to alias the double width destination
611 register. On some architectures this aliasing can be disabled by a bit
612 in the status register, and the setting of this bit cannot be determined
613 automatically at assemble time. */
614 static int mips_disable_float_construction
;
616 /* Non-zero if any .set noreorder directives were used. */
618 static int mips_any_noreorder
;
620 /* Non-zero if nops should be inserted when the register referenced in
621 an mfhi/mflo instruction is read in the next two instructions. */
622 static int mips_7000_hilo_fix
;
624 /* The size of objects in the small data section. */
625 static unsigned int g_switch_value
= 8;
626 /* Whether the -G option was used. */
627 static int g_switch_seen
= 0;
632 /* If we can determine in advance that GP optimization won't be
633 possible, we can skip the relaxation stuff that tries to produce
634 GP-relative references. This makes delay slot optimization work
637 This function can only provide a guess, but it seems to work for
638 gcc output. It needs to guess right for gcc, otherwise gcc
639 will put what it thinks is a GP-relative instruction in a branch
642 I don't know if a fix is needed for the SVR4_PIC mode. I've only
643 fixed it for the non-PIC mode. KR 95/04/07 */
644 static int nopic_need_relax (symbolS
*, int);
646 /* handle of the OPCODE hash table */
647 static struct hash_control
*op_hash
= NULL
;
649 /* The opcode hash table we use for the mips16. */
650 static struct hash_control
*mips16_op_hash
= NULL
;
652 /* The opcode hash table we use for the microMIPS ASE. */
653 static struct hash_control
*micromips_op_hash
= NULL
;
655 /* This array holds the chars that always start a comment. If the
656 pre-processor is disabled, these aren't very useful */
657 const char comment_chars
[] = "#";
659 /* This array holds the chars that only start a comment at the beginning of
660 a line. If the line seems to have the form '# 123 filename'
661 .line and .file directives will appear in the pre-processed output */
662 /* Note that input_file.c hand checks for '#' at the beginning of the
663 first line of the input file. This is because the compiler outputs
664 #NO_APP at the beginning of its output. */
665 /* Also note that C style comments are always supported. */
666 const char line_comment_chars
[] = "#";
668 /* This array holds machine specific line separator characters. */
669 const char line_separator_chars
[] = ";";
671 /* Chars that can be used to separate mant from exp in floating point nums */
672 const char EXP_CHARS
[] = "eE";
674 /* Chars that mean this number is a floating point constant */
677 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
679 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
680 changed in read.c . Ideally it shouldn't have to know about it at all,
681 but nothing is ideal around here.
684 static char *insn_error
;
686 static int auto_align
= 1;
688 /* When outputting SVR4 PIC code, the assembler needs to know the
689 offset in the stack frame from which to restore the $gp register.
690 This is set by the .cprestore pseudo-op, and saved in this
692 static offsetT mips_cprestore_offset
= -1;
694 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
695 more optimizations, it can use a register value instead of a memory-saved
696 offset and even an other register than $gp as global pointer. */
697 static offsetT mips_cpreturn_offset
= -1;
698 static int mips_cpreturn_register
= -1;
699 static int mips_gp_register
= GP
;
700 static int mips_gprel_offset
= 0;
702 /* Whether mips_cprestore_offset has been set in the current function
703 (or whether it has already been warned about, if not). */
704 static int mips_cprestore_valid
= 0;
706 /* This is the register which holds the stack frame, as set by the
707 .frame pseudo-op. This is needed to implement .cprestore. */
708 static int mips_frame_reg
= SP
;
710 /* Whether mips_frame_reg has been set in the current function
711 (or whether it has already been warned about, if not). */
712 static int mips_frame_reg_valid
= 0;
714 /* To output NOP instructions correctly, we need to keep information
715 about the previous two instructions. */
717 /* Whether we are optimizing. The default value of 2 means to remove
718 unneeded NOPs and swap branch instructions when possible. A value
719 of 1 means to not swap branches. A value of 0 means to always
721 static int mips_optimize
= 2;
723 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
724 equivalent to seeing no -g option at all. */
725 static int mips_debug
= 0;
727 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
728 #define MAX_VR4130_NOPS 4
730 /* The maximum number of NOPs needed to fill delay slots. */
731 #define MAX_DELAY_NOPS 2
733 /* The maximum number of NOPs needed for any purpose. */
736 /* A list of previous instructions, with index 0 being the most recent.
737 We need to look back MAX_NOPS instructions when filling delay slots
738 or working around processor errata. We need to look back one
739 instruction further if we're thinking about using history[0] to
740 fill a branch delay slot. */
741 static struct mips_cl_insn history
[1 + MAX_NOPS
];
743 /* Nop instructions used by emit_nop. */
744 static struct mips_cl_insn nop_insn
;
745 static struct mips_cl_insn mips16_nop_insn
;
746 static struct mips_cl_insn micromips_nop16_insn
;
747 static struct mips_cl_insn micromips_nop32_insn
;
749 /* The appropriate nop for the current mode. */
750 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
751 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
753 /* The size of NOP_INSN in bytes. */
754 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
756 /* If this is set, it points to a frag holding nop instructions which
757 were inserted before the start of a noreorder section. If those
758 nops turn out to be unnecessary, the size of the frag can be
760 static fragS
*prev_nop_frag
;
762 /* The number of nop instructions we created in prev_nop_frag. */
763 static int prev_nop_frag_holds
;
765 /* The number of nop instructions that we know we need in
767 static int prev_nop_frag_required
;
769 /* The number of instructions we've seen since prev_nop_frag. */
770 static int prev_nop_frag_since
;
772 /* For ECOFF and ELF, relocations against symbols are done in two
773 parts, with a HI relocation and a LO relocation. Each relocation
774 has only 16 bits of space to store an addend. This means that in
775 order for the linker to handle carries correctly, it must be able
776 to locate both the HI and the LO relocation. This means that the
777 relocations must appear in order in the relocation table.
779 In order to implement this, we keep track of each unmatched HI
780 relocation. We then sort them so that they immediately precede the
781 corresponding LO relocation. */
786 struct mips_hi_fixup
*next
;
789 /* The section this fixup is in. */
793 /* The list of unmatched HI relocs. */
795 static struct mips_hi_fixup
*mips_hi_fixup_list
;
797 /* The frag containing the last explicit relocation operator.
798 Null if explicit relocations have not been used. */
800 static fragS
*prev_reloc_op_frag
;
802 /* Map normal MIPS register numbers to mips16 register numbers. */
804 #define X ILLEGAL_REG
805 static const int mips32_to_16_reg_map
[] =
807 X
, X
, 2, 3, 4, 5, 6, 7,
808 X
, X
, X
, X
, X
, X
, X
, X
,
809 0, 1, X
, X
, X
, X
, X
, X
,
810 X
, X
, X
, X
, X
, X
, X
, X
814 /* Map mips16 register numbers to normal MIPS register numbers. */
816 static const unsigned int mips16_to_32_reg_map
[] =
818 16, 17, 2, 3, 4, 5, 6, 7
821 /* Map normal MIPS register numbers to microMIPS register numbers. */
823 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
824 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
825 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
826 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
827 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
828 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
829 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
831 #define X ILLEGAL_REG
832 /* reg type h: 4, 5, 6. */
833 static const int mips32_to_micromips_reg_h_map
[] =
835 X
, X
, X
, X
, 4, 5, 6, X
,
836 X
, X
, X
, X
, X
, X
, X
, X
,
837 X
, X
, X
, X
, X
, X
, X
, X
,
838 X
, X
, X
, X
, X
, X
, X
, X
841 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
842 static const int mips32_to_micromips_reg_m_map
[] =
844 0, X
, 2, 3, X
, X
, X
, X
,
845 X
, X
, X
, X
, X
, X
, X
, X
,
846 4, 1, 5, 6, 7, X
, X
, X
,
847 X
, X
, X
, X
, X
, X
, X
, X
850 /* reg type q: 0, 2-7. 17. */
851 static const int mips32_to_micromips_reg_q_map
[] =
853 0, X
, 2, 3, 4, 5, 6, 7,
854 X
, X
, X
, X
, X
, X
, X
, X
,
855 X
, 1, X
, X
, X
, X
, X
, X
,
856 X
, X
, X
, X
, X
, X
, X
, X
859 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
862 /* Map microMIPS register numbers to normal MIPS register numbers. */
864 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
865 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
866 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
867 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
868 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
869 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
871 /* The microMIPS registers with type h. */
872 static const unsigned int micromips_to_32_reg_h_map
[] =
874 5, 5, 6, 4, 4, 4, 4, 4
877 /* The microMIPS registers with type i. */
878 static const unsigned int micromips_to_32_reg_i_map
[] =
880 6, 7, 7, 21, 22, 5, 6, 7
883 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
885 /* The microMIPS registers with type m. */
886 static const unsigned int micromips_to_32_reg_m_map
[] =
888 0, 17, 2, 3, 16, 18, 19, 20
891 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
893 /* The microMIPS registers with type q. */
894 static const unsigned int micromips_to_32_reg_q_map
[] =
896 0, 17, 2, 3, 4, 5, 6, 7
899 /* microMIPS imm type B. */
900 static const int micromips_imm_b_map
[] =
902 1, 4, 8, 12, 16, 20, 24, -1
905 /* microMIPS imm type C. */
906 static const int micromips_imm_c_map
[] =
908 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
911 /* Classifies the kind of instructions we're interested in when
912 implementing -mfix-vr4120. */
913 enum fix_vr4120_class
921 NUM_FIX_VR4120_CLASSES
924 /* ...likewise -mfix-loongson2f-jump. */
925 static bfd_boolean mips_fix_loongson2f_jump
;
927 /* ...likewise -mfix-loongson2f-nop. */
928 static bfd_boolean mips_fix_loongson2f_nop
;
930 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
931 static bfd_boolean mips_fix_loongson2f
;
933 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
934 there must be at least one other instruction between an instruction
935 of type X and an instruction of type Y. */
936 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
938 /* True if -mfix-vr4120 is in force. */
939 static int mips_fix_vr4120
;
941 /* ...likewise -mfix-vr4130. */
942 static int mips_fix_vr4130
;
944 /* ...likewise -mfix-24k. */
945 static int mips_fix_24k
;
947 /* ...likewise -mfix-cn63xxp1 */
948 static bfd_boolean mips_fix_cn63xxp1
;
950 /* We don't relax branches by default, since this causes us to expand
951 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
952 fail to compute the offset before expanding the macro to the most
953 efficient expansion. */
955 static int mips_relax_branch
;
957 /* The expansion of many macros depends on the type of symbol that
958 they refer to. For example, when generating position-dependent code,
959 a macro that refers to a symbol may have two different expansions,
960 one which uses GP-relative addresses and one which uses absolute
961 addresses. When generating SVR4-style PIC, a macro may have
962 different expansions for local and global symbols.
964 We handle these situations by generating both sequences and putting
965 them in variant frags. In position-dependent code, the first sequence
966 will be the GP-relative one and the second sequence will be the
967 absolute one. In SVR4 PIC, the first sequence will be for global
968 symbols and the second will be for local symbols.
970 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
971 SECOND are the lengths of the two sequences in bytes. These fields
972 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
973 the subtype has the following flags:
976 Set if it has been decided that we should use the second
977 sequence instead of the first.
980 Set in the first variant frag if the macro's second implementation
981 is longer than its first. This refers to the macro as a whole,
982 not an individual relaxation.
985 Set in the first variant frag if the macro appeared in a .set nomacro
986 block and if one alternative requires a warning but the other does not.
989 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
992 RELAX_DELAY_SLOT_16BIT
993 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
996 RELAX_DELAY_SLOT_SIZE_FIRST
997 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
998 the macro is of the wrong size for the branch delay slot.
1000 RELAX_DELAY_SLOT_SIZE_SECOND
1001 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1002 the macro is of the wrong size for the branch delay slot.
1004 The frag's "opcode" points to the first fixup for relaxable code.
1006 Relaxable macros are generated using a sequence such as:
1008 relax_start (SYMBOL);
1009 ... generate first expansion ...
1011 ... generate second expansion ...
1014 The code and fixups for the unwanted alternative are discarded
1015 by md_convert_frag. */
1016 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1018 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1019 #define RELAX_SECOND(X) ((X) & 0xff)
1020 #define RELAX_USE_SECOND 0x10000
1021 #define RELAX_SECOND_LONGER 0x20000
1022 #define RELAX_NOMACRO 0x40000
1023 #define RELAX_DELAY_SLOT 0x80000
1024 #define RELAX_DELAY_SLOT_16BIT 0x100000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1096 ((relax_substateT) \
1099 | ((toofar) ? 0x20 : 0) \
1100 | ((link) ? 0x40 : 0) \
1101 | ((likely) ? 0x80 : 0) \
1102 | ((uncond) ? 0x100 : 0)))
1103 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1104 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1105 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1106 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1107 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1108 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1110 /* For mips16 code, we use an entirely different form of relaxation.
1111 mips16 supports two versions of most instructions which take
1112 immediate values: a small one which takes some small value, and a
1113 larger one which takes a 16 bit value. Since branches also follow
1114 this pattern, relaxing these values is required.
1116 We can assemble both mips16 and normal MIPS code in a single
1117 object. Therefore, we need to support this type of relaxation at
1118 the same time that we support the relaxation described above. We
1119 use the high bit of the subtype field to distinguish these cases.
1121 The information we store for this type of relaxation is the
1122 argument code found in the opcode file for this relocation, whether
1123 the user explicitly requested a small or extended form, and whether
1124 the relocation is in a jump or jal delay slot. That tells us the
1125 size of the value, and how it should be stored. We also store
1126 whether the fragment is considered to be extended or not. We also
1127 store whether this is known to be a branch to a different section,
1128 whether we have tried to relax this frag yet, and whether we have
1129 ever extended a PC relative fragment because of a shift count. */
1130 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1133 | ((small) ? 0x100 : 0) \
1134 | ((ext) ? 0x200 : 0) \
1135 | ((dslot) ? 0x400 : 0) \
1136 | ((jal_dslot) ? 0x800 : 0))
1137 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1138 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1139 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1140 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1141 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1142 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1143 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1144 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1145 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1146 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1147 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1148 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1150 /* For microMIPS code, we use relaxation similar to one we use for
1151 MIPS16 code. Some instructions that take immediate values support
1152 two encodings: a small one which takes some small value, and a
1153 larger one which takes a 16 bit value. As some branches also follow
1154 this pattern, relaxing these values is required.
1156 We can assemble both microMIPS and normal MIPS code in a single
1157 object. Therefore, we need to support this type of relaxation at
1158 the same time that we support the relaxation described above. We
1159 use one of the high bits of the subtype field to distinguish these
1162 The information we store for this type of relaxation is the argument
1163 code found in the opcode file for this relocation, the register
1164 selected as the assembler temporary, whether the branch is
1165 unconditional, whether it is compact, whether it stores the link
1166 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1167 branches to a sequence of instructions is enabled, and whether the
1168 displacement of a branch is too large to fit as an immediate argument
1169 of a 16-bit and a 32-bit branch, respectively. */
1170 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1171 relax32, toofar16, toofar32) \
1174 | (((at) & 0x1f) << 8) \
1175 | ((uncond) ? 0x2000 : 0) \
1176 | ((compact) ? 0x4000 : 0) \
1177 | ((link) ? 0x8000 : 0) \
1178 | ((relax32) ? 0x10000 : 0) \
1179 | ((toofar16) ? 0x20000 : 0) \
1180 | ((toofar32) ? 0x40000 : 0))
1181 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1182 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1183 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1184 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1185 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1186 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1187 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1189 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1190 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1191 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1192 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1193 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1194 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1196 /* Is the given value a sign-extended 32-bit value? */
1197 #define IS_SEXT_32BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1199 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1201 /* Is the given value a sign-extended 16-bit value? */
1202 #define IS_SEXT_16BIT_NUM(x) \
1203 (((x) &~ (offsetT) 0x7fff) == 0 \
1204 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1206 /* Is the given value a sign-extended 12-bit value? */
1207 #define IS_SEXT_12BIT_NUM(x) \
1208 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1210 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1211 #define IS_ZEXT_32BIT_NUM(x) \
1212 (((x) &~ (offsetT) 0xffffffff) == 0 \
1213 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1215 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1216 VALUE << SHIFT. VALUE is evaluated exactly once. */
1217 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1218 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1219 | (((VALUE) & (MASK)) << (SHIFT)))
1221 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1223 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1224 (((STRUCT) >> (SHIFT)) & (MASK))
1226 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1227 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1229 include/opcode/mips.h specifies operand fields using the macros
1230 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1231 with "MIPS16OP" instead of "OP". */
1232 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1235 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1236 OP_MASK_##FIELD, OP_SH_##FIELD); \
1238 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1239 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1241 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1242 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1243 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1245 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1246 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1248 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1249 : EXTRACT_BITS ((INSN).insn_opcode, \
1250 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1251 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1252 EXTRACT_BITS ((INSN).insn_opcode, \
1253 MIPS16OP_MASK_##FIELD, \
1254 MIPS16OP_SH_##FIELD)
1256 /* Whether or not we are emitting a branch-likely macro. */
1257 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1259 /* Global variables used when generating relaxable macros. See the
1260 comment above RELAX_ENCODE for more details about how relaxation
1263 /* 0 if we're not emitting a relaxable macro.
1264 1 if we're emitting the first of the two relaxation alternatives.
1265 2 if we're emitting the second alternative. */
1268 /* The first relaxable fixup in the current frag. (In other words,
1269 the first fixup that refers to relaxable code.) */
1272 /* sizes[0] says how many bytes of the first alternative are stored in
1273 the current frag. Likewise sizes[1] for the second alternative. */
1274 unsigned int sizes
[2];
1276 /* The symbol on which the choice of sequence depends. */
1280 /* Global variables used to decide whether a macro needs a warning. */
1282 /* True if the macro is in a branch delay slot. */
1283 bfd_boolean delay_slot_p
;
1285 /* Set to the length in bytes required if the macro is in a delay slot
1286 that requires a specific length of instruction, otherwise zero. */
1287 unsigned int delay_slot_length
;
1289 /* For relaxable macros, sizes[0] is the length of the first alternative
1290 in bytes and sizes[1] is the length of the second alternative.
1291 For non-relaxable macros, both elements give the length of the
1293 unsigned int sizes
[2];
1295 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1296 instruction of the first alternative in bytes and first_insn_sizes[1]
1297 is the length of the first instruction of the second alternative.
1298 For non-relaxable macros, both elements give the length of the first
1299 instruction in bytes.
1301 Set to zero if we haven't yet seen the first instruction. */
1302 unsigned int first_insn_sizes
[2];
1304 /* For relaxable macros, insns[0] is the number of instructions for the
1305 first alternative and insns[1] is the number of instructions for the
1308 For non-relaxable macros, both elements give the number of
1309 instructions for the macro. */
1310 unsigned int insns
[2];
1312 /* The first variant frag for this macro. */
1314 } mips_macro_warning
;
1316 /* Prototypes for static functions. */
1318 #define internalError() \
1319 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1321 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1323 static void append_insn
1324 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1325 bfd_boolean expansionp
);
1326 static void mips_no_prev_insn (void);
1327 static void macro_build (expressionS
*, const char *, const char *, ...);
1328 static void mips16_macro_build
1329 (expressionS
*, const char *, const char *, va_list *);
1330 static void load_register (int, expressionS
*, int);
1331 static void macro_start (void);
1332 static void macro_end (void);
1333 static void macro (struct mips_cl_insn
* ip
);
1334 static void mips16_macro (struct mips_cl_insn
* ip
);
1335 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1336 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1337 static void mips16_immed
1338 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1339 unsigned long *, bfd_boolean
*, unsigned short *);
1340 static size_t my_getSmallExpression
1341 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1342 static void my_getExpression (expressionS
*, char *);
1343 static void s_align (int);
1344 static void s_change_sec (int);
1345 static void s_change_section (int);
1346 static void s_cons (int);
1347 static void s_float_cons (int);
1348 static void s_mips_globl (int);
1349 static void s_option (int);
1350 static void s_mipsset (int);
1351 static void s_abicalls (int);
1352 static void s_cpload (int);
1353 static void s_cpsetup (int);
1354 static void s_cplocal (int);
1355 static void s_cprestore (int);
1356 static void s_cpreturn (int);
1357 static void s_dtprelword (int);
1358 static void s_dtpreldword (int);
1359 static void s_tprelword (int);
1360 static void s_tpreldword (int);
1361 static void s_gpvalue (int);
1362 static void s_gpword (int);
1363 static void s_gpdword (int);
1364 static void s_cpadd (int);
1365 static void s_insn (int);
1366 static void md_obj_begin (void);
1367 static void md_obj_end (void);
1368 static void s_mips_ent (int);
1369 static void s_mips_end (int);
1370 static void s_mips_frame (int);
1371 static void s_mips_mask (int reg_type
);
1372 static void s_mips_stab (int);
1373 static void s_mips_weakext (int);
1374 static void s_mips_file (int);
1375 static void s_mips_loc (int);
1376 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1377 static int relaxed_branch_length (fragS
*, asection
*, int);
1378 static int validate_mips_insn (const struct mips_opcode
*);
1379 static int validate_micromips_insn (const struct mips_opcode
*);
1380 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1381 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1383 /* Table and functions used to map between CPU/ISA names, and
1384 ISA levels, and CPU numbers. */
1386 struct mips_cpu_info
1388 const char *name
; /* CPU or ISA name. */
1389 int flags
; /* ASEs available, or ISA flag. */
1390 int isa
; /* ISA level. */
1391 int cpu
; /* CPU number (default CPU if ISA). */
1394 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1395 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1396 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1397 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1398 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1399 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1400 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1401 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1403 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1404 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1405 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1409 The following pseudo-ops from the Kane and Heinrich MIPS book
1410 should be defined here, but are currently unsupported: .alias,
1411 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1413 The following pseudo-ops from the Kane and Heinrich MIPS book are
1414 specific to the type of debugging information being generated, and
1415 should be defined by the object format: .aent, .begin, .bend,
1416 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1419 The following pseudo-ops from the Kane and Heinrich MIPS book are
1420 not MIPS CPU specific, but are also not specific to the object file
1421 format. This file is probably the best place to define them, but
1422 they are not currently supported: .asm0, .endr, .lab, .struct. */
1424 static const pseudo_typeS mips_pseudo_table
[] =
1426 /* MIPS specific pseudo-ops. */
1427 {"option", s_option
, 0},
1428 {"set", s_mipsset
, 0},
1429 {"rdata", s_change_sec
, 'r'},
1430 {"sdata", s_change_sec
, 's'},
1431 {"livereg", s_ignore
, 0},
1432 {"abicalls", s_abicalls
, 0},
1433 {"cpload", s_cpload
, 0},
1434 {"cpsetup", s_cpsetup
, 0},
1435 {"cplocal", s_cplocal
, 0},
1436 {"cprestore", s_cprestore
, 0},
1437 {"cpreturn", s_cpreturn
, 0},
1438 {"dtprelword", s_dtprelword
, 0},
1439 {"dtpreldword", s_dtpreldword
, 0},
1440 {"tprelword", s_tprelword
, 0},
1441 {"tpreldword", s_tpreldword
, 0},
1442 {"gpvalue", s_gpvalue
, 0},
1443 {"gpword", s_gpword
, 0},
1444 {"gpdword", s_gpdword
, 0},
1445 {"cpadd", s_cpadd
, 0},
1446 {"insn", s_insn
, 0},
1448 /* Relatively generic pseudo-ops that happen to be used on MIPS
1450 {"asciiz", stringer
, 8 + 1},
1451 {"bss", s_change_sec
, 'b'},
1453 {"half", s_cons
, 1},
1454 {"dword", s_cons
, 3},
1455 {"weakext", s_mips_weakext
, 0},
1456 {"origin", s_org
, 0},
1457 {"repeat", s_rept
, 0},
1459 /* For MIPS this is non-standard, but we define it for consistency. */
1460 {"sbss", s_change_sec
, 'B'},
1462 /* These pseudo-ops are defined in read.c, but must be overridden
1463 here for one reason or another. */
1464 {"align", s_align
, 0},
1465 {"byte", s_cons
, 0},
1466 {"data", s_change_sec
, 'd'},
1467 {"double", s_float_cons
, 'd'},
1468 {"float", s_float_cons
, 'f'},
1469 {"globl", s_mips_globl
, 0},
1470 {"global", s_mips_globl
, 0},
1471 {"hword", s_cons
, 1},
1473 {"long", s_cons
, 2},
1474 {"octa", s_cons
, 4},
1475 {"quad", s_cons
, 3},
1476 {"section", s_change_section
, 0},
1477 {"short", s_cons
, 1},
1478 {"single", s_float_cons
, 'f'},
1479 {"stabn", s_mips_stab
, 'n'},
1480 {"text", s_change_sec
, 't'},
1481 {"word", s_cons
, 2},
1483 { "extern", ecoff_directive_extern
, 0},
1488 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1490 /* These pseudo-ops should be defined by the object file format.
1491 However, a.out doesn't support them, so we have versions here. */
1492 {"aent", s_mips_ent
, 1},
1493 {"bgnb", s_ignore
, 0},
1494 {"end", s_mips_end
, 0},
1495 {"endb", s_ignore
, 0},
1496 {"ent", s_mips_ent
, 0},
1497 {"file", s_mips_file
, 0},
1498 {"fmask", s_mips_mask
, 'F'},
1499 {"frame", s_mips_frame
, 0},
1500 {"loc", s_mips_loc
, 0},
1501 {"mask", s_mips_mask
, 'R'},
1502 {"verstamp", s_ignore
, 0},
1506 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1507 purpose of the `.dc.a' internal pseudo-op. */
1510 mips_address_bytes (void)
1512 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1515 extern void pop_insert (const pseudo_typeS
*);
1518 mips_pop_insert (void)
1520 pop_insert (mips_pseudo_table
);
1521 if (! ECOFF_DEBUGGING
)
1522 pop_insert (mips_nonecoff_pseudo_table
);
1525 /* Symbols labelling the current insn. */
1527 struct insn_label_list
1529 struct insn_label_list
*next
;
1533 static struct insn_label_list
*free_insn_labels
;
1534 #define label_list tc_segment_info_data.labels
1536 static void mips_clear_insn_labels (void);
1537 static void mips_mark_labels (void);
1538 static void mips_compressed_mark_labels (void);
1541 mips_clear_insn_labels (void)
1543 register struct insn_label_list
**pl
;
1544 segment_info_type
*si
;
1548 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1551 si
= seg_info (now_seg
);
1552 *pl
= si
->label_list
;
1553 si
->label_list
= NULL
;
1557 /* Mark instruction labels in MIPS16/microMIPS mode. */
1560 mips_mark_labels (void)
1562 if (HAVE_CODE_COMPRESSION
)
1563 mips_compressed_mark_labels ();
1566 static char *expr_end
;
1568 /* Expressions which appear in instructions. These are set by
1571 static expressionS imm_expr
;
1572 static expressionS imm2_expr
;
1573 static expressionS offset_expr
;
1575 /* Relocs associated with imm_expr and offset_expr. */
1577 static bfd_reloc_code_real_type imm_reloc
[3]
1578 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1579 static bfd_reloc_code_real_type offset_reloc
[3]
1580 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1582 /* This is set to the resulting size of the instruction to be produced
1583 by mips16_ip if an explicit extension is used or by mips_ip if an
1584 explicit size is supplied. */
1586 static unsigned int forced_insn_length
;
1589 /* The pdr segment for per procedure frame/regmask info. Not used for
1592 static segT pdr_seg
;
1595 /* The default target format to use. */
1597 #if defined (TE_FreeBSD)
1598 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1599 #elif defined (TE_TMIPS)
1600 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1602 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1606 mips_target_format (void)
1608 switch (OUTPUT_FLAVOR
)
1610 case bfd_target_ecoff_flavour
:
1611 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1612 case bfd_target_coff_flavour
:
1614 case bfd_target_elf_flavour
:
1616 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1617 return (target_big_endian
1618 ? "elf32-bigmips-vxworks"
1619 : "elf32-littlemips-vxworks");
1621 return (target_big_endian
1622 ? (HAVE_64BIT_OBJECTS
1623 ? ELF_TARGET ("elf64-", "big")
1625 ? ELF_TARGET ("elf32-n", "big")
1626 : ELF_TARGET ("elf32-", "big")))
1627 : (HAVE_64BIT_OBJECTS
1628 ? ELF_TARGET ("elf64-", "little")
1630 ? ELF_TARGET ("elf32-n", "little")
1631 : ELF_TARGET ("elf32-", "little"))));
1638 /* Return the length of a microMIPS instruction in bytes. If bits of
1639 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1640 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1641 major opcode) will require further modifications to the opcode
1644 static inline unsigned int
1645 micromips_insn_length (const struct mips_opcode
*mo
)
1647 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1650 /* Return the length of instruction INSN. */
1652 static inline unsigned int
1653 insn_length (const struct mips_cl_insn
*insn
)
1655 if (mips_opts
.micromips
)
1656 return micromips_insn_length (insn
->insn_mo
);
1657 else if (mips_opts
.mips16
)
1658 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1663 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1666 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1671 insn
->use_extend
= FALSE
;
1673 insn
->insn_opcode
= mo
->match
;
1676 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1677 insn
->fixp
[i
] = NULL
;
1678 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1679 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1680 insn
->mips16_absolute_jump_p
= 0;
1681 insn
->complete_p
= 0;
1684 /* Record the current MIPS16/microMIPS mode in now_seg. */
1687 mips_record_compressed_mode (void)
1689 segment_info_type
*si
;
1691 si
= seg_info (now_seg
);
1692 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1693 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1694 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1695 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1698 /* Install INSN at the location specified by its "frag" and "where" fields. */
1701 install_insn (const struct mips_cl_insn
*insn
)
1703 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1704 if (!HAVE_CODE_COMPRESSION
)
1705 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1706 else if (mips_opts
.micromips
)
1708 unsigned int length
= insn_length (insn
);
1710 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1711 else if (length
== 4)
1713 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1715 md_number_to_chars (f
, insn
->insn_opcode
& 0xffff, 2);
1718 as_bad (_("48-bit microMIPS instructions are not supported"));
1720 else if (insn
->mips16_absolute_jump_p
)
1722 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1723 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1727 if (insn
->use_extend
)
1729 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1732 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1734 mips_record_compressed_mode ();
1737 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1738 and install the opcode in the new location. */
1741 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1746 insn
->where
= where
;
1747 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1748 if (insn
->fixp
[i
] != NULL
)
1750 insn
->fixp
[i
]->fx_frag
= frag
;
1751 insn
->fixp
[i
]->fx_where
= where
;
1753 install_insn (insn
);
1756 /* Add INSN to the end of the output. */
1759 add_fixed_insn (struct mips_cl_insn
*insn
)
1761 char *f
= frag_more (insn_length (insn
));
1762 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1765 /* Start a variant frag and move INSN to the start of the variant part,
1766 marking it as fixed. The other arguments are as for frag_var. */
1769 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1770 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1772 frag_grow (max_chars
);
1773 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1775 frag_var (rs_machine_dependent
, max_chars
, var
,
1776 subtype
, symbol
, offset
, NULL
);
1779 /* Insert N copies of INSN into the history buffer, starting at
1780 position FIRST. Neither FIRST nor N need to be clipped. */
1783 insert_into_history (unsigned int first
, unsigned int n
,
1784 const struct mips_cl_insn
*insn
)
1786 if (mips_relax
.sequence
!= 2)
1790 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1792 history
[i
] = history
[i
- n
];
1798 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1799 the idea is to make it obvious at a glance that each errata is
1803 init_vr4120_conflicts (void)
1805 #define CONFLICT(FIRST, SECOND) \
1806 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1808 /* Errata 21 - [D]DIV[U] after [D]MACC */
1809 CONFLICT (MACC
, DIV
);
1810 CONFLICT (DMACC
, DIV
);
1812 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1813 CONFLICT (DMULT
, DMULT
);
1814 CONFLICT (DMULT
, DMACC
);
1815 CONFLICT (DMACC
, DMULT
);
1816 CONFLICT (DMACC
, DMACC
);
1818 /* Errata 24 - MT{LO,HI} after [D]MACC */
1819 CONFLICT (MACC
, MTHILO
);
1820 CONFLICT (DMACC
, MTHILO
);
1822 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1823 instruction is executed immediately after a MACC or DMACC
1824 instruction, the result of [either instruction] is incorrect." */
1825 CONFLICT (MACC
, MULT
);
1826 CONFLICT (MACC
, DMULT
);
1827 CONFLICT (DMACC
, MULT
);
1828 CONFLICT (DMACC
, DMULT
);
1830 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1831 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1832 DDIV or DDIVU instruction, the result of the MACC or
1833 DMACC instruction is incorrect.". */
1834 CONFLICT (DMULT
, MACC
);
1835 CONFLICT (DMULT
, DMACC
);
1836 CONFLICT (DIV
, MACC
);
1837 CONFLICT (DIV
, DMACC
);
1847 #define RTYPE_MASK 0x1ff00
1848 #define RTYPE_NUM 0x00100
1849 #define RTYPE_FPU 0x00200
1850 #define RTYPE_FCC 0x00400
1851 #define RTYPE_VEC 0x00800
1852 #define RTYPE_GP 0x01000
1853 #define RTYPE_CP0 0x02000
1854 #define RTYPE_PC 0x04000
1855 #define RTYPE_ACC 0x08000
1856 #define RTYPE_CCC 0x10000
1857 #define RNUM_MASK 0x000ff
1858 #define RWARN 0x80000
1860 #define GENERIC_REGISTER_NUMBERS \
1861 {"$0", RTYPE_NUM | 0}, \
1862 {"$1", RTYPE_NUM | 1}, \
1863 {"$2", RTYPE_NUM | 2}, \
1864 {"$3", RTYPE_NUM | 3}, \
1865 {"$4", RTYPE_NUM | 4}, \
1866 {"$5", RTYPE_NUM | 5}, \
1867 {"$6", RTYPE_NUM | 6}, \
1868 {"$7", RTYPE_NUM | 7}, \
1869 {"$8", RTYPE_NUM | 8}, \
1870 {"$9", RTYPE_NUM | 9}, \
1871 {"$10", RTYPE_NUM | 10}, \
1872 {"$11", RTYPE_NUM | 11}, \
1873 {"$12", RTYPE_NUM | 12}, \
1874 {"$13", RTYPE_NUM | 13}, \
1875 {"$14", RTYPE_NUM | 14}, \
1876 {"$15", RTYPE_NUM | 15}, \
1877 {"$16", RTYPE_NUM | 16}, \
1878 {"$17", RTYPE_NUM | 17}, \
1879 {"$18", RTYPE_NUM | 18}, \
1880 {"$19", RTYPE_NUM | 19}, \
1881 {"$20", RTYPE_NUM | 20}, \
1882 {"$21", RTYPE_NUM | 21}, \
1883 {"$22", RTYPE_NUM | 22}, \
1884 {"$23", RTYPE_NUM | 23}, \
1885 {"$24", RTYPE_NUM | 24}, \
1886 {"$25", RTYPE_NUM | 25}, \
1887 {"$26", RTYPE_NUM | 26}, \
1888 {"$27", RTYPE_NUM | 27}, \
1889 {"$28", RTYPE_NUM | 28}, \
1890 {"$29", RTYPE_NUM | 29}, \
1891 {"$30", RTYPE_NUM | 30}, \
1892 {"$31", RTYPE_NUM | 31}
1894 #define FPU_REGISTER_NAMES \
1895 {"$f0", RTYPE_FPU | 0}, \
1896 {"$f1", RTYPE_FPU | 1}, \
1897 {"$f2", RTYPE_FPU | 2}, \
1898 {"$f3", RTYPE_FPU | 3}, \
1899 {"$f4", RTYPE_FPU | 4}, \
1900 {"$f5", RTYPE_FPU | 5}, \
1901 {"$f6", RTYPE_FPU | 6}, \
1902 {"$f7", RTYPE_FPU | 7}, \
1903 {"$f8", RTYPE_FPU | 8}, \
1904 {"$f9", RTYPE_FPU | 9}, \
1905 {"$f10", RTYPE_FPU | 10}, \
1906 {"$f11", RTYPE_FPU | 11}, \
1907 {"$f12", RTYPE_FPU | 12}, \
1908 {"$f13", RTYPE_FPU | 13}, \
1909 {"$f14", RTYPE_FPU | 14}, \
1910 {"$f15", RTYPE_FPU | 15}, \
1911 {"$f16", RTYPE_FPU | 16}, \
1912 {"$f17", RTYPE_FPU | 17}, \
1913 {"$f18", RTYPE_FPU | 18}, \
1914 {"$f19", RTYPE_FPU | 19}, \
1915 {"$f20", RTYPE_FPU | 20}, \
1916 {"$f21", RTYPE_FPU | 21}, \
1917 {"$f22", RTYPE_FPU | 22}, \
1918 {"$f23", RTYPE_FPU | 23}, \
1919 {"$f24", RTYPE_FPU | 24}, \
1920 {"$f25", RTYPE_FPU | 25}, \
1921 {"$f26", RTYPE_FPU | 26}, \
1922 {"$f27", RTYPE_FPU | 27}, \
1923 {"$f28", RTYPE_FPU | 28}, \
1924 {"$f29", RTYPE_FPU | 29}, \
1925 {"$f30", RTYPE_FPU | 30}, \
1926 {"$f31", RTYPE_FPU | 31}
1928 #define FPU_CONDITION_CODE_NAMES \
1929 {"$fcc0", RTYPE_FCC | 0}, \
1930 {"$fcc1", RTYPE_FCC | 1}, \
1931 {"$fcc2", RTYPE_FCC | 2}, \
1932 {"$fcc3", RTYPE_FCC | 3}, \
1933 {"$fcc4", RTYPE_FCC | 4}, \
1934 {"$fcc5", RTYPE_FCC | 5}, \
1935 {"$fcc6", RTYPE_FCC | 6}, \
1936 {"$fcc7", RTYPE_FCC | 7}
1938 #define COPROC_CONDITION_CODE_NAMES \
1939 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1940 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1941 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1942 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1943 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1944 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1945 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1946 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1948 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1949 {"$a4", RTYPE_GP | 8}, \
1950 {"$a5", RTYPE_GP | 9}, \
1951 {"$a6", RTYPE_GP | 10}, \
1952 {"$a7", RTYPE_GP | 11}, \
1953 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1954 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1955 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1956 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1957 {"$t0", RTYPE_GP | 12}, \
1958 {"$t1", RTYPE_GP | 13}, \
1959 {"$t2", RTYPE_GP | 14}, \
1960 {"$t3", RTYPE_GP | 15}
1962 #define O32_SYMBOLIC_REGISTER_NAMES \
1963 {"$t0", RTYPE_GP | 8}, \
1964 {"$t1", RTYPE_GP | 9}, \
1965 {"$t2", RTYPE_GP | 10}, \
1966 {"$t3", RTYPE_GP | 11}, \
1967 {"$t4", RTYPE_GP | 12}, \
1968 {"$t5", RTYPE_GP | 13}, \
1969 {"$t6", RTYPE_GP | 14}, \
1970 {"$t7", RTYPE_GP | 15}, \
1971 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1972 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1973 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1974 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1976 /* Remaining symbolic register names */
1977 #define SYMBOLIC_REGISTER_NAMES \
1978 {"$zero", RTYPE_GP | 0}, \
1979 {"$at", RTYPE_GP | 1}, \
1980 {"$AT", RTYPE_GP | 1}, \
1981 {"$v0", RTYPE_GP | 2}, \
1982 {"$v1", RTYPE_GP | 3}, \
1983 {"$a0", RTYPE_GP | 4}, \
1984 {"$a1", RTYPE_GP | 5}, \
1985 {"$a2", RTYPE_GP | 6}, \
1986 {"$a3", RTYPE_GP | 7}, \
1987 {"$s0", RTYPE_GP | 16}, \
1988 {"$s1", RTYPE_GP | 17}, \
1989 {"$s2", RTYPE_GP | 18}, \
1990 {"$s3", RTYPE_GP | 19}, \
1991 {"$s4", RTYPE_GP | 20}, \
1992 {"$s5", RTYPE_GP | 21}, \
1993 {"$s6", RTYPE_GP | 22}, \
1994 {"$s7", RTYPE_GP | 23}, \
1995 {"$t8", RTYPE_GP | 24}, \
1996 {"$t9", RTYPE_GP | 25}, \
1997 {"$k0", RTYPE_GP | 26}, \
1998 {"$kt0", RTYPE_GP | 26}, \
1999 {"$k1", RTYPE_GP | 27}, \
2000 {"$kt1", RTYPE_GP | 27}, \
2001 {"$gp", RTYPE_GP | 28}, \
2002 {"$sp", RTYPE_GP | 29}, \
2003 {"$s8", RTYPE_GP | 30}, \
2004 {"$fp", RTYPE_GP | 30}, \
2005 {"$ra", RTYPE_GP | 31}
2007 #define MIPS16_SPECIAL_REGISTER_NAMES \
2008 {"$pc", RTYPE_PC | 0}
2010 #define MDMX_VECTOR_REGISTER_NAMES \
2011 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2012 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2013 {"$v2", RTYPE_VEC | 2}, \
2014 {"$v3", RTYPE_VEC | 3}, \
2015 {"$v4", RTYPE_VEC | 4}, \
2016 {"$v5", RTYPE_VEC | 5}, \
2017 {"$v6", RTYPE_VEC | 6}, \
2018 {"$v7", RTYPE_VEC | 7}, \
2019 {"$v8", RTYPE_VEC | 8}, \
2020 {"$v9", RTYPE_VEC | 9}, \
2021 {"$v10", RTYPE_VEC | 10}, \
2022 {"$v11", RTYPE_VEC | 11}, \
2023 {"$v12", RTYPE_VEC | 12}, \
2024 {"$v13", RTYPE_VEC | 13}, \
2025 {"$v14", RTYPE_VEC | 14}, \
2026 {"$v15", RTYPE_VEC | 15}, \
2027 {"$v16", RTYPE_VEC | 16}, \
2028 {"$v17", RTYPE_VEC | 17}, \
2029 {"$v18", RTYPE_VEC | 18}, \
2030 {"$v19", RTYPE_VEC | 19}, \
2031 {"$v20", RTYPE_VEC | 20}, \
2032 {"$v21", RTYPE_VEC | 21}, \
2033 {"$v22", RTYPE_VEC | 22}, \
2034 {"$v23", RTYPE_VEC | 23}, \
2035 {"$v24", RTYPE_VEC | 24}, \
2036 {"$v25", RTYPE_VEC | 25}, \
2037 {"$v26", RTYPE_VEC | 26}, \
2038 {"$v27", RTYPE_VEC | 27}, \
2039 {"$v28", RTYPE_VEC | 28}, \
2040 {"$v29", RTYPE_VEC | 29}, \
2041 {"$v30", RTYPE_VEC | 30}, \
2042 {"$v31", RTYPE_VEC | 31}
2044 #define MIPS_DSP_ACCUMULATOR_NAMES \
2045 {"$ac0", RTYPE_ACC | 0}, \
2046 {"$ac1", RTYPE_ACC | 1}, \
2047 {"$ac2", RTYPE_ACC | 2}, \
2048 {"$ac3", RTYPE_ACC | 3}
2050 static const struct regname reg_names
[] = {
2051 GENERIC_REGISTER_NUMBERS
,
2053 FPU_CONDITION_CODE_NAMES
,
2054 COPROC_CONDITION_CODE_NAMES
,
2056 /* The $txx registers depends on the abi,
2057 these will be added later into the symbol table from
2058 one of the tables below once mips_abi is set after
2059 parsing of arguments from the command line. */
2060 SYMBOLIC_REGISTER_NAMES
,
2062 MIPS16_SPECIAL_REGISTER_NAMES
,
2063 MDMX_VECTOR_REGISTER_NAMES
,
2064 MIPS_DSP_ACCUMULATOR_NAMES
,
2068 static const struct regname reg_names_o32
[] = {
2069 O32_SYMBOLIC_REGISTER_NAMES
,
2073 static const struct regname reg_names_n32n64
[] = {
2074 N32N64_SYMBOLIC_REGISTER_NAMES
,
2078 /* Check if S points at a valid register specifier according to TYPES.
2079 If so, then return 1, advance S to consume the specifier and store
2080 the register's number in REGNOP, otherwise return 0. */
2083 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2090 /* Find end of name. */
2092 if (is_name_beginner (*e
))
2094 while (is_part_of_name (*e
))
2097 /* Terminate name. */
2101 /* Look for a register symbol. */
2102 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2104 int r
= S_GET_VALUE (symbolP
);
2106 reg
= r
& RNUM_MASK
;
2107 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2108 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2109 reg
= (r
& RNUM_MASK
) - 2;
2111 /* Else see if this is a register defined in an itbl entry. */
2112 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2119 if (itbl_get_reg_val (n
, &r
))
2120 reg
= r
& RNUM_MASK
;
2123 /* Advance to next token if a register was recognised. */
2126 else if (types
& RWARN
)
2127 as_warn (_("Unrecognized register name `%s'"), *s
);
2135 /* Check if S points at a valid register list according to TYPES.
2136 If so, then return 1, advance S to consume the list and store
2137 the registers present on the list as a bitmask of ones in REGLISTP,
2138 otherwise return 0. A valid list comprises a comma-separated
2139 enumeration of valid single registers and/or dash-separated
2140 contiguous register ranges as determined by their numbers.
2142 As a special exception if one of s0-s7 registers is specified as
2143 the range's lower delimiter and s8 (fp) is its upper one, then no
2144 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2145 are selected; they have to be listed separately if needed. */
2148 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2150 unsigned int reglist
= 0;
2151 unsigned int lastregno
;
2152 bfd_boolean ok
= TRUE
;
2153 unsigned int regmask
;
2154 char *s_endlist
= *s
;
2158 while (reg_lookup (s
, types
, ®no
))
2164 ok
= reg_lookup (s
, types
, &lastregno
);
2165 if (ok
&& lastregno
< regno
)
2171 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2176 regmask
= 1 << lastregno
;
2177 regmask
= (regmask
<< 1) - 1;
2178 regmask
^= (1 << regno
) - 1;
2192 *reglistp
= reglist
;
2193 return ok
&& reglist
!= 0;
2196 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2197 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2200 is_opcode_valid (const struct mips_opcode
*mo
)
2202 int isa
= mips_opts
.isa
;
2205 if (mips_opts
.ase_mdmx
)
2207 if (mips_opts
.ase_dsp
)
2209 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2211 if (mips_opts
.ase_dspr2
)
2213 if (mips_opts
.ase_mt
)
2215 if (mips_opts
.ase_mips3d
)
2217 if (mips_opts
.ase_smartmips
)
2218 isa
|= INSN_SMARTMIPS
;
2219 if (mips_opts
.ase_mcu
)
2222 /* Don't accept instructions based on the ISA if the CPU does not implement
2223 all the coprocessor insns. */
2224 if (NO_ISA_COP (mips_opts
.arch
)
2225 && COP_INSN (mo
->pinfo
))
2228 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
2231 /* Check whether the instruction or macro requires single-precision or
2232 double-precision floating-point support. Note that this information is
2233 stored differently in the opcode table for insns and macros. */
2234 if (mo
->pinfo
== INSN_MACRO
)
2236 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2237 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2241 fp_s
= mo
->pinfo
& FP_S
;
2242 fp_d
= mo
->pinfo
& FP_D
;
2245 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2248 if (fp_s
&& mips_opts
.soft_float
)
2254 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2255 selected ISA and architecture. */
2258 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2260 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
2263 /* Return TRUE if the size of the microMIPS opcode MO matches one
2264 explicitly requested. Always TRUE in the standard MIPS mode. */
2267 is_size_valid (const struct mips_opcode
*mo
)
2269 if (!mips_opts
.micromips
)
2272 if (!forced_insn_length
)
2274 if (mo
->pinfo
== INSN_MACRO
)
2276 return forced_insn_length
== micromips_insn_length (mo
);
2279 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2280 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2283 is_delay_slot_valid (const struct mips_opcode
*mo
)
2285 if (!mips_opts
.micromips
)
2288 if (mo
->pinfo
== INSN_MACRO
)
2290 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2291 && micromips_insn_length (mo
) != 4)
2293 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2294 && micromips_insn_length (mo
) != 2)
2300 /* This function is called once, at assembler startup time. It should set up
2301 all the tables, etc. that the MD part of the assembler will need. */
2306 const char *retval
= NULL
;
2310 if (mips_pic
!= NO_PIC
)
2312 if (g_switch_seen
&& g_switch_value
!= 0)
2313 as_bad (_("-G may not be used in position-independent code"));
2317 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2318 as_warn (_("Could not set architecture and machine"));
2320 op_hash
= hash_new ();
2322 for (i
= 0; i
< NUMOPCODES
;)
2324 const char *name
= mips_opcodes
[i
].name
;
2326 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2329 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2330 mips_opcodes
[i
].name
, retval
);
2331 /* Probably a memory allocation problem? Give up now. */
2332 as_fatal (_("Broken assembler. No assembly attempted."));
2336 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2338 if (!validate_mips_insn (&mips_opcodes
[i
]))
2340 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2342 create_insn (&nop_insn
, mips_opcodes
+ i
);
2343 if (mips_fix_loongson2f_nop
)
2344 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2345 nop_insn
.fixed_p
= 1;
2350 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2353 mips16_op_hash
= hash_new ();
2356 while (i
< bfd_mips16_num_opcodes
)
2358 const char *name
= mips16_opcodes
[i
].name
;
2360 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2362 as_fatal (_("internal: can't hash `%s': %s"),
2363 mips16_opcodes
[i
].name
, retval
);
2366 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2367 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2368 != mips16_opcodes
[i
].match
))
2370 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2371 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2374 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2376 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2377 mips16_nop_insn
.fixed_p
= 1;
2381 while (i
< bfd_mips16_num_opcodes
2382 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2385 micromips_op_hash
= hash_new ();
2388 while (i
< bfd_micromips_num_opcodes
)
2390 const char *name
= micromips_opcodes
[i
].name
;
2392 retval
= hash_insert (micromips_op_hash
, name
,
2393 (void *) µmips_opcodes
[i
]);
2395 as_fatal (_("internal: can't hash `%s': %s"),
2396 micromips_opcodes
[i
].name
, retval
);
2398 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2400 struct mips_cl_insn
*micromips_nop_insn
;
2402 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2405 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2406 micromips_nop_insn
= µmips_nop16_insn
;
2407 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2408 micromips_nop_insn
= µmips_nop32_insn
;
2412 if (micromips_nop_insn
->insn_mo
== NULL
2413 && strcmp (name
, "nop") == 0)
2415 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2416 micromips_nop_insn
->fixed_p
= 1;
2419 while (++i
< bfd_micromips_num_opcodes
2420 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2424 as_fatal (_("Broken assembler. No assembly attempted."));
2426 /* We add all the general register names to the symbol table. This
2427 helps us detect invalid uses of them. */
2428 for (i
= 0; reg_names
[i
].name
; i
++)
2429 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2430 reg_names
[i
].num
, /* & RNUM_MASK, */
2431 &zero_address_frag
));
2433 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2434 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2435 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2436 &zero_address_frag
));
2438 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2439 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2440 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2441 &zero_address_frag
));
2443 mips_no_prev_insn ();
2446 mips_cprmask
[0] = 0;
2447 mips_cprmask
[1] = 0;
2448 mips_cprmask
[2] = 0;
2449 mips_cprmask
[3] = 0;
2451 /* set the default alignment for the text section (2**2) */
2452 record_alignment (text_section
, 2);
2454 bfd_set_gp_size (stdoutput
, g_switch_value
);
2459 /* On a native system other than VxWorks, sections must be aligned
2460 to 16 byte boundaries. When configured for an embedded ELF
2461 target, we don't bother. */
2462 if (strncmp (TARGET_OS
, "elf", 3) != 0
2463 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2465 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2466 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2467 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2470 /* Create a .reginfo section for register masks and a .mdebug
2471 section for debugging information. */
2479 subseg
= now_subseg
;
2481 /* The ABI says this section should be loaded so that the
2482 running program can access it. However, we don't load it
2483 if we are configured for an embedded target */
2484 flags
= SEC_READONLY
| SEC_DATA
;
2485 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2486 flags
|= SEC_ALLOC
| SEC_LOAD
;
2488 if (mips_abi
!= N64_ABI
)
2490 sec
= subseg_new (".reginfo", (subsegT
) 0);
2492 bfd_set_section_flags (stdoutput
, sec
, flags
);
2493 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2495 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2499 /* The 64-bit ABI uses a .MIPS.options section rather than
2500 .reginfo section. */
2501 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2502 bfd_set_section_flags (stdoutput
, sec
, flags
);
2503 bfd_set_section_alignment (stdoutput
, sec
, 3);
2505 /* Set up the option header. */
2507 Elf_Internal_Options opthdr
;
2510 opthdr
.kind
= ODK_REGINFO
;
2511 opthdr
.size
= (sizeof (Elf_External_Options
)
2512 + sizeof (Elf64_External_RegInfo
));
2515 f
= frag_more (sizeof (Elf_External_Options
));
2516 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2517 (Elf_External_Options
*) f
);
2519 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2523 if (ECOFF_DEBUGGING
)
2525 sec
= subseg_new (".mdebug", (subsegT
) 0);
2526 (void) bfd_set_section_flags (stdoutput
, sec
,
2527 SEC_HAS_CONTENTS
| SEC_READONLY
);
2528 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2530 else if (mips_flag_pdr
)
2532 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2533 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2534 SEC_READONLY
| SEC_RELOC
2536 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2539 subseg_set (seg
, subseg
);
2542 #endif /* OBJ_ELF */
2544 if (! ECOFF_DEBUGGING
)
2547 if (mips_fix_vr4120
)
2548 init_vr4120_conflicts ();
2554 mips_emit_delays ();
2555 if (! ECOFF_DEBUGGING
)
2560 md_assemble (char *str
)
2562 struct mips_cl_insn insn
;
2563 bfd_reloc_code_real_type unused_reloc
[3]
2564 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2566 imm_expr
.X_op
= O_absent
;
2567 imm2_expr
.X_op
= O_absent
;
2568 offset_expr
.X_op
= O_absent
;
2569 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2570 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2571 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2572 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2573 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2574 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2576 if (mips_opts
.mips16
)
2577 mips16_ip (str
, &insn
);
2580 mips_ip (str
, &insn
);
2581 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2582 str
, insn
.insn_opcode
));
2587 as_bad ("%s `%s'", insn_error
, str
);
2591 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2594 if (mips_opts
.mips16
)
2595 mips16_macro (&insn
);
2602 if (imm_expr
.X_op
!= O_absent
)
2603 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2604 else if (offset_expr
.X_op
!= O_absent
)
2605 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2607 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2611 /* Convenience functions for abstracting away the differences between
2612 MIPS16 and non-MIPS16 relocations. */
2614 static inline bfd_boolean
2615 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2619 case BFD_RELOC_MIPS16_JMP
:
2620 case BFD_RELOC_MIPS16_GPREL
:
2621 case BFD_RELOC_MIPS16_GOT16
:
2622 case BFD_RELOC_MIPS16_CALL16
:
2623 case BFD_RELOC_MIPS16_HI16_S
:
2624 case BFD_RELOC_MIPS16_HI16
:
2625 case BFD_RELOC_MIPS16_LO16
:
2633 static inline bfd_boolean
2634 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2638 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2639 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2640 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2641 case BFD_RELOC_MICROMIPS_GPREL16
:
2642 case BFD_RELOC_MICROMIPS_JMP
:
2643 case BFD_RELOC_MICROMIPS_HI16
:
2644 case BFD_RELOC_MICROMIPS_HI16_S
:
2645 case BFD_RELOC_MICROMIPS_LO16
:
2646 case BFD_RELOC_MICROMIPS_LITERAL
:
2647 case BFD_RELOC_MICROMIPS_GOT16
:
2648 case BFD_RELOC_MICROMIPS_CALL16
:
2649 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2650 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2651 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2652 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2653 case BFD_RELOC_MICROMIPS_SUB
:
2654 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2655 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2656 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2657 case BFD_RELOC_MICROMIPS_HIGHEST
:
2658 case BFD_RELOC_MICROMIPS_HIGHER
:
2659 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2660 case BFD_RELOC_MICROMIPS_JALR
:
2668 static inline bfd_boolean
2669 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2671 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2674 static inline bfd_boolean
2675 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2677 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2678 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2681 static inline bfd_boolean
2682 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2684 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2685 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2688 static inline bfd_boolean
2689 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2691 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2692 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2695 static inline bfd_boolean
2696 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2698 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2701 /* Return true if the given relocation might need a matching %lo().
2702 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2703 need a matching %lo() when applied to local symbols. */
2705 static inline bfd_boolean
2706 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2708 return (HAVE_IN_PLACE_ADDENDS
2709 && (hi16_reloc_p (reloc
)
2710 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2711 all GOT16 relocations evaluate to "G". */
2712 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2715 /* Return the type of %lo() reloc needed by RELOC, given that
2716 reloc_needs_lo_p. */
2718 static inline bfd_reloc_code_real_type
2719 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2721 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2722 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2726 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2729 static inline bfd_boolean
2730 fixup_has_matching_lo_p (fixS
*fixp
)
2732 return (fixp
->fx_next
!= NULL
2733 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2734 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2735 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2738 /* This function returns true if modifying a register requires a
2742 reg_needs_delay (unsigned int reg
)
2744 unsigned long prev_pinfo
;
2746 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2747 if (! mips_opts
.noreorder
2748 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2749 && ! gpr_interlocks
)
2750 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2751 && ! cop_interlocks
)))
2753 /* A load from a coprocessor or from memory. All load delays
2754 delay the use of general register rt for one instruction. */
2755 /* Itbl support may require additional care here. */
2756 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2757 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2764 /* Move all labels in LABELS to the current insertion point. TEXT_P
2765 says whether the labels refer to text or data. */
2768 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
2770 struct insn_label_list
*l
;
2773 for (l
= labels
; l
!= NULL
; l
= l
->next
)
2775 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2776 symbol_set_frag (l
->label
, frag_now
);
2777 val
= (valueT
) frag_now_fix ();
2778 /* MIPS16/microMIPS text labels are stored as odd. */
2779 if (text_p
&& HAVE_CODE_COMPRESSION
)
2781 S_SET_VALUE (l
->label
, val
);
2785 /* Move all labels in insn_labels to the current insertion point
2786 and treat them as text labels. */
2789 mips_move_text_labels (void)
2791 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
2795 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2797 bfd_boolean linkonce
= FALSE
;
2798 segT symseg
= S_GET_SEGMENT (sym
);
2800 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2802 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2805 /* The GNU toolchain uses an extension for ELF: a section
2806 beginning with the magic string .gnu.linkonce is a
2807 linkonce section. */
2808 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2809 sizeof ".gnu.linkonce" - 1) == 0)
2816 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2817 linker to handle them specially, such as generating jalx instructions
2818 when needed. We also make them odd for the duration of the assembly,
2819 in order to generate the right sort of code. We will make them even
2820 in the adjust_symtab routine, while leaving them marked. This is
2821 convenient for the debugger and the disassembler. The linker knows
2822 to make them odd again. */
2825 mips_compressed_mark_labels (void)
2827 segment_info_type
*si
= seg_info (now_seg
);
2828 struct insn_label_list
*l
;
2830 gas_assert (HAVE_CODE_COMPRESSION
);
2832 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2834 symbolS
*label
= l
->label
;
2836 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2839 if (mips_opts
.mips16
)
2840 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2842 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2845 if ((S_GET_VALUE (label
) & 1) == 0
2846 /* Don't adjust the address if the label is global or weak, or
2847 in a link-once section, since we'll be emitting symbol reloc
2848 references to it which will be patched up by the linker, and
2849 the final value of the symbol may or may not be MIPS16/microMIPS. */
2850 && ! S_IS_WEAK (label
)
2851 && ! S_IS_EXTERNAL (label
)
2852 && ! s_is_linkonce (label
, now_seg
))
2853 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2857 /* End the current frag. Make it a variant frag and record the
2861 relax_close_frag (void)
2863 mips_macro_warning
.first_frag
= frag_now
;
2864 frag_var (rs_machine_dependent
, 0, 0,
2865 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2866 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2868 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2869 mips_relax
.first_fixup
= 0;
2872 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2873 See the comment above RELAX_ENCODE for more details. */
2876 relax_start (symbolS
*symbol
)
2878 gas_assert (mips_relax
.sequence
== 0);
2879 mips_relax
.sequence
= 1;
2880 mips_relax
.symbol
= symbol
;
2883 /* Start generating the second version of a relaxable sequence.
2884 See the comment above RELAX_ENCODE for more details. */
2889 gas_assert (mips_relax
.sequence
== 1);
2890 mips_relax
.sequence
= 2;
2893 /* End the current relaxable sequence. */
2898 gas_assert (mips_relax
.sequence
== 2);
2899 relax_close_frag ();
2900 mips_relax
.sequence
= 0;
2903 /* Return true if IP is a delayed branch or jump. */
2905 static inline bfd_boolean
2906 delayed_branch_p (const struct mips_cl_insn
*ip
)
2908 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2909 | INSN_COND_BRANCH_DELAY
2910 | INSN_COND_BRANCH_LIKELY
)) != 0;
2913 /* Return true if IP is a compact branch or jump. */
2915 static inline bfd_boolean
2916 compact_branch_p (const struct mips_cl_insn
*ip
)
2918 if (mips_opts
.mips16
)
2919 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2920 | MIPS16_INSN_COND_BRANCH
)) != 0;
2922 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
2923 | INSN2_COND_BRANCH
)) != 0;
2926 /* Return true if IP is an unconditional branch or jump. */
2928 static inline bfd_boolean
2929 uncond_branch_p (const struct mips_cl_insn
*ip
)
2931 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
2932 || (mips_opts
.mips16
2933 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
2934 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
2937 /* Return true if IP is a branch-likely instruction. */
2939 static inline bfd_boolean
2940 branch_likely_p (const struct mips_cl_insn
*ip
)
2942 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
2945 /* Return the type of nop that should be used to fill the delay slot
2946 of delayed branch IP. */
2948 static struct mips_cl_insn
*
2949 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
2951 if (mips_opts
.micromips
2952 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
2953 return µmips_nop32_insn
;
2957 /* Return the mask of core registers that IP reads or writes. */
2960 gpr_mod_mask (const struct mips_cl_insn
*ip
)
2962 unsigned long pinfo2
;
2966 pinfo2
= ip
->insn_mo
->pinfo2
;
2967 if (mips_opts
.micromips
)
2969 if (pinfo2
& INSN2_MOD_GPR_MD
)
2970 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
2971 if (pinfo2
& INSN2_MOD_GPR_MF
)
2972 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
2973 if (pinfo2
& INSN2_MOD_SP
)
2979 /* Return the mask of core registers that IP reads. */
2982 gpr_read_mask (const struct mips_cl_insn
*ip
)
2984 unsigned long pinfo
, pinfo2
;
2987 mask
= gpr_mod_mask (ip
);
2988 pinfo
= ip
->insn_mo
->pinfo
;
2989 pinfo2
= ip
->insn_mo
->pinfo2
;
2990 if (mips_opts
.mips16
)
2992 if (pinfo
& MIPS16_INSN_READ_X
)
2993 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
2994 if (pinfo
& MIPS16_INSN_READ_Y
)
2995 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
2996 if (pinfo
& MIPS16_INSN_READ_T
)
2998 if (pinfo
& MIPS16_INSN_READ_SP
)
3000 if (pinfo
& MIPS16_INSN_READ_31
)
3002 if (pinfo
& MIPS16_INSN_READ_Z
)
3003 mask
|= 1 << (mips16_to_32_reg_map
3004 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3005 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3006 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3010 if (pinfo2
& INSN2_READ_GPR_D
)
3011 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3012 if (pinfo
& INSN_READ_GPR_T
)
3013 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3014 if (pinfo
& INSN_READ_GPR_S
)
3015 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3016 if (pinfo2
& INSN2_READ_GP
)
3018 if (pinfo2
& INSN2_READ_GPR_31
)
3020 if (pinfo2
& INSN2_READ_GPR_Z
)
3021 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3023 if (mips_opts
.micromips
)
3025 if (pinfo2
& INSN2_READ_GPR_MC
)
3026 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3027 if (pinfo2
& INSN2_READ_GPR_ME
)
3028 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3029 if (pinfo2
& INSN2_READ_GPR_MG
)
3030 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3031 if (pinfo2
& INSN2_READ_GPR_MJ
)
3032 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3033 if (pinfo2
& INSN2_READ_GPR_MMN
)
3035 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3036 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3038 if (pinfo2
& INSN2_READ_GPR_MP
)
3039 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3040 if (pinfo2
& INSN2_READ_GPR_MQ
)
3041 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3043 /* Don't include register 0. */
3047 /* Return the mask of core registers that IP writes. */
3050 gpr_write_mask (const struct mips_cl_insn
*ip
)
3052 unsigned long pinfo
, pinfo2
;
3055 mask
= gpr_mod_mask (ip
);
3056 pinfo
= ip
->insn_mo
->pinfo
;
3057 pinfo2
= ip
->insn_mo
->pinfo2
;
3058 if (mips_opts
.mips16
)
3060 if (pinfo
& MIPS16_INSN_WRITE_X
)
3061 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3062 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3063 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3064 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3065 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3066 if (pinfo
& MIPS16_INSN_WRITE_T
)
3068 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3070 if (pinfo
& MIPS16_INSN_WRITE_31
)
3072 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3073 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3077 if (pinfo
& INSN_WRITE_GPR_D
)
3078 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3079 if (pinfo
& INSN_WRITE_GPR_T
)
3080 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3081 if (pinfo
& INSN_WRITE_GPR_S
)
3082 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3083 if (pinfo
& INSN_WRITE_GPR_31
)
3085 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3086 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3088 if (mips_opts
.micromips
)
3090 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3091 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3092 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3094 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3095 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3097 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3098 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3099 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3100 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3102 /* Don't include register 0. */
3106 /* Return the mask of floating-point registers that IP reads. */
3109 fpr_read_mask (const struct mips_cl_insn
*ip
)
3111 unsigned long pinfo
, pinfo2
;
3115 pinfo
= ip
->insn_mo
->pinfo
;
3116 pinfo2
= ip
->insn_mo
->pinfo2
;
3117 if (!mips_opts
.mips16
)
3119 if (pinfo2
& INSN2_READ_FPR_D
)
3120 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3121 if (pinfo
& INSN_READ_FPR_S
)
3122 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3123 if (pinfo
& INSN_READ_FPR_T
)
3124 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3125 if (pinfo
& INSN_READ_FPR_R
)
3126 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3127 if (pinfo2
& INSN2_READ_FPR_Z
)
3128 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3130 /* Conservatively treat all operands to an FP_D instruction are doubles.
3131 (This is overly pessimistic for things like cvt.d.s.) */
3132 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3137 /* Return the mask of floating-point registers that IP writes. */
3140 fpr_write_mask (const struct mips_cl_insn
*ip
)
3142 unsigned long pinfo
, pinfo2
;
3146 pinfo
= ip
->insn_mo
->pinfo
;
3147 pinfo2
= ip
->insn_mo
->pinfo2
;
3148 if (!mips_opts
.mips16
)
3150 if (pinfo
& INSN_WRITE_FPR_D
)
3151 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3152 if (pinfo
& INSN_WRITE_FPR_S
)
3153 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3154 if (pinfo
& INSN_WRITE_FPR_T
)
3155 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3156 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3157 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3159 /* Conservatively treat all operands to an FP_D instruction are doubles.
3160 (This is overly pessimistic for things like cvt.s.d.) */
3161 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3166 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3167 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3168 by VR4120 errata. */
3171 classify_vr4120_insn (const char *name
)
3173 if (strncmp (name
, "macc", 4) == 0)
3174 return FIX_VR4120_MACC
;
3175 if (strncmp (name
, "dmacc", 5) == 0)
3176 return FIX_VR4120_DMACC
;
3177 if (strncmp (name
, "mult", 4) == 0)
3178 return FIX_VR4120_MULT
;
3179 if (strncmp (name
, "dmult", 5) == 0)
3180 return FIX_VR4120_DMULT
;
3181 if (strstr (name
, "div"))
3182 return FIX_VR4120_DIV
;
3183 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3184 return FIX_VR4120_MTHILO
;
3185 return NUM_FIX_VR4120_CLASSES
;
3188 #define INSN_ERET 0x42000018
3189 #define INSN_DERET 0x4200001f
3191 /* Return the number of instructions that must separate INSN1 and INSN2,
3192 where INSN1 is the earlier instruction. Return the worst-case value
3193 for any INSN2 if INSN2 is null. */
3196 insns_between (const struct mips_cl_insn
*insn1
,
3197 const struct mips_cl_insn
*insn2
)
3199 unsigned long pinfo1
, pinfo2
;
3202 /* This function needs to know which pinfo flags are set for INSN2
3203 and which registers INSN2 uses. The former is stored in PINFO2 and
3204 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3205 will have every flag set and INSN2_USES_GPR will always return true. */
3206 pinfo1
= insn1
->insn_mo
->pinfo
;
3207 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3209 #define INSN2_USES_GPR(REG) \
3210 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3212 /* For most targets, write-after-read dependencies on the HI and LO
3213 registers must be separated by at least two instructions. */
3214 if (!hilo_interlocks
)
3216 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3218 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3222 /* If we're working around r7000 errata, there must be two instructions
3223 between an mfhi or mflo and any instruction that uses the result. */
3224 if (mips_7000_hilo_fix
3225 && !mips_opts
.micromips
3226 && MF_HILO_INSN (pinfo1
)
3227 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3230 /* If we're working around 24K errata, one instruction is required
3231 if an ERET or DERET is followed by a branch instruction. */
3232 if (mips_fix_24k
&& !mips_opts
.micromips
)
3234 if (insn1
->insn_opcode
== INSN_ERET
3235 || insn1
->insn_opcode
== INSN_DERET
)
3238 || insn2
->insn_opcode
== INSN_ERET
3239 || insn2
->insn_opcode
== INSN_DERET
3240 || delayed_branch_p (insn2
))
3245 /* If working around VR4120 errata, check for combinations that need
3246 a single intervening instruction. */
3247 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3249 unsigned int class1
, class2
;
3251 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3252 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3256 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3257 if (vr4120_conflicts
[class1
] & (1 << class2
))
3262 if (!HAVE_CODE_COMPRESSION
)
3264 /* Check for GPR or coprocessor load delays. All such delays
3265 are on the RT register. */
3266 /* Itbl support may require additional care here. */
3267 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3268 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3270 know (pinfo1
& INSN_WRITE_GPR_T
);
3271 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3275 /* Check for generic coprocessor hazards.
3277 This case is not handled very well. There is no special
3278 knowledge of CP0 handling, and the coprocessors other than
3279 the floating point unit are not distinguished at all. */
3280 /* Itbl support may require additional care here. FIXME!
3281 Need to modify this to include knowledge about
3282 user specified delays! */
3283 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3284 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3286 /* Handle cases where INSN1 writes to a known general coprocessor
3287 register. There must be a one instruction delay before INSN2
3288 if INSN2 reads that register, otherwise no delay is needed. */
3289 mask
= fpr_write_mask (insn1
);
3292 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3297 /* Read-after-write dependencies on the control registers
3298 require a two-instruction gap. */
3299 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3300 && (pinfo2
& INSN_READ_COND_CODE
))
3303 /* We don't know exactly what INSN1 does. If INSN2 is
3304 also a coprocessor instruction, assume there must be
3305 a one instruction gap. */
3306 if (pinfo2
& INSN_COP
)
3311 /* Check for read-after-write dependencies on the coprocessor
3312 control registers in cases where INSN1 does not need a general
3313 coprocessor delay. This means that INSN1 is a floating point
3314 comparison instruction. */
3315 /* Itbl support may require additional care here. */
3316 else if (!cop_interlocks
3317 && (pinfo1
& INSN_WRITE_COND_CODE
)
3318 && (pinfo2
& INSN_READ_COND_CODE
))
3322 #undef INSN2_USES_GPR
3327 /* Return the number of nops that would be needed to work around the
3328 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3329 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3330 that are contained within the first IGNORE instructions of HIST. */
3333 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3334 const struct mips_cl_insn
*insn
)
3339 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3340 are not affected by the errata. */
3342 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3343 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3344 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3347 /* Search for the first MFLO or MFHI. */
3348 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3349 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3351 /* Extract the destination register. */
3352 mask
= gpr_write_mask (&hist
[i
]);
3354 /* No nops are needed if INSN reads that register. */
3355 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3358 /* ...or if any of the intervening instructions do. */
3359 for (j
= 0; j
< i
; j
++)
3360 if (gpr_read_mask (&hist
[j
]) & mask
)
3364 return MAX_VR4130_NOPS
- i
;
3369 #define BASE_REG_EQ(INSN1, INSN2) \
3370 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3371 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3373 /* Return the minimum alignment for this store instruction. */
3376 fix_24k_align_to (const struct mips_opcode
*mo
)
3378 if (strcmp (mo
->name
, "sh") == 0)
3381 if (strcmp (mo
->name
, "swc1") == 0
3382 || strcmp (mo
->name
, "swc2") == 0
3383 || strcmp (mo
->name
, "sw") == 0
3384 || strcmp (mo
->name
, "sc") == 0
3385 || strcmp (mo
->name
, "s.s") == 0)
3388 if (strcmp (mo
->name
, "sdc1") == 0
3389 || strcmp (mo
->name
, "sdc2") == 0
3390 || strcmp (mo
->name
, "s.d") == 0)
3397 struct fix_24k_store_info
3399 /* Immediate offset, if any, for this store instruction. */
3401 /* Alignment required by this store instruction. */
3403 /* True for register offsets. */
3404 int register_offset
;
3407 /* Comparison function used by qsort. */
3410 fix_24k_sort (const void *a
, const void *b
)
3412 const struct fix_24k_store_info
*pos1
= a
;
3413 const struct fix_24k_store_info
*pos2
= b
;
3415 return (pos1
->off
- pos2
->off
);
3418 /* INSN is a store instruction. Try to record the store information
3419 in STINFO. Return false if the information isn't known. */
3422 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3423 const struct mips_cl_insn
*insn
)
3425 /* The instruction must have a known offset. */
3426 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3429 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3430 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3434 /* Return the number of nops that would be needed to work around the 24k
3435 "lost data on stores during refill" errata if instruction INSN
3436 immediately followed the 2 instructions described by HIST.
3437 Ignore hazards that are contained within the first IGNORE
3438 instructions of HIST.
3440 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3441 for the data cache refills and store data. The following describes
3442 the scenario where the store data could be lost.
3444 * A data cache miss, due to either a load or a store, causing fill
3445 data to be supplied by the memory subsystem
3446 * The first three doublewords of fill data are returned and written
3448 * A sequence of four stores occurs in consecutive cycles around the
3449 final doubleword of the fill:
3453 * Zero, One or more instructions
3456 The four stores A-D must be to different doublewords of the line that
3457 is being filled. The fourth instruction in the sequence above permits
3458 the fill of the final doubleword to be transferred from the FSB into
3459 the cache. In the sequence above, the stores may be either integer
3460 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3461 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3462 different doublewords on the line. If the floating point unit is
3463 running in 1:2 mode, it is not possible to create the sequence above
3464 using only floating point store instructions.
3466 In this case, the cache line being filled is incorrectly marked
3467 invalid, thereby losing the data from any store to the line that
3468 occurs between the original miss and the completion of the five
3469 cycle sequence shown above.
3471 The workarounds are:
3473 * Run the data cache in write-through mode.
3474 * Insert a non-store instruction between
3475 Store A and Store B or Store B and Store C. */
3478 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3479 const struct mips_cl_insn
*insn
)
3481 struct fix_24k_store_info pos
[3];
3482 int align
, i
, base_offset
;
3487 /* If the previous instruction wasn't a store, there's nothing to
3489 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3492 /* If the instructions after the previous one are unknown, we have
3493 to assume the worst. */
3497 /* Check whether we are dealing with three consecutive stores. */
3498 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3499 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3502 /* If we don't know the relationship between the store addresses,
3503 assume the worst. */
3504 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3505 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3508 if (!fix_24k_record_store_info (&pos
[0], insn
)
3509 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3510 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3513 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3515 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3516 X bytes and such that the base register + X is known to be aligned
3519 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3523 align
= pos
[0].align_to
;
3524 base_offset
= pos
[0].off
;
3525 for (i
= 1; i
< 3; i
++)
3526 if (align
< pos
[i
].align_to
)
3528 align
= pos
[i
].align_to
;
3529 base_offset
= pos
[i
].off
;
3531 for (i
= 0; i
< 3; i
++)
3532 pos
[i
].off
-= base_offset
;
3535 pos
[0].off
&= ~align
+ 1;
3536 pos
[1].off
&= ~align
+ 1;
3537 pos
[2].off
&= ~align
+ 1;
3539 /* If any two stores write to the same chunk, they also write to the
3540 same doubleword. The offsets are still sorted at this point. */
3541 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3544 /* A range of at least 9 bytes is needed for the stores to be in
3545 non-overlapping doublewords. */
3546 if (pos
[2].off
- pos
[0].off
<= 8)
3549 if (pos
[2].off
- pos
[1].off
>= 24
3550 || pos
[1].off
- pos
[0].off
>= 24
3551 || pos
[2].off
- pos
[0].off
>= 32)
3557 /* Return the number of nops that would be needed if instruction INSN
3558 immediately followed the MAX_NOPS instructions given by HIST,
3559 where HIST[0] is the most recent instruction. Ignore hazards
3560 between INSN and the first IGNORE instructions in HIST.
3562 If INSN is null, return the worse-case number of nops for any
3566 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3567 const struct mips_cl_insn
*insn
)
3569 int i
, nops
, tmp_nops
;
3572 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3574 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3575 if (tmp_nops
> nops
)
3579 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3581 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3582 if (tmp_nops
> nops
)
3586 if (mips_fix_24k
&& !mips_opts
.micromips
)
3588 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3589 if (tmp_nops
> nops
)
3596 /* The variable arguments provide NUM_INSNS extra instructions that
3597 might be added to HIST. Return the largest number of nops that
3598 would be needed after the extended sequence, ignoring hazards
3599 in the first IGNORE instructions. */
3602 nops_for_sequence (int num_insns
, int ignore
,
3603 const struct mips_cl_insn
*hist
, ...)
3606 struct mips_cl_insn buffer
[MAX_NOPS
];
3607 struct mips_cl_insn
*cursor
;
3610 va_start (args
, hist
);
3611 cursor
= buffer
+ num_insns
;
3612 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3613 while (cursor
> buffer
)
3614 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3616 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3621 /* Like nops_for_insn, but if INSN is a branch, take into account the
3622 worst-case delay for the branch target. */
3625 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3626 const struct mips_cl_insn
*insn
)
3630 nops
= nops_for_insn (ignore
, hist
, insn
);
3631 if (delayed_branch_p (insn
))
3633 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3634 hist
, insn
, get_delay_slot_nop (insn
));
3635 if (tmp_nops
> nops
)
3638 else if (compact_branch_p (insn
))
3640 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3641 if (tmp_nops
> nops
)
3647 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3650 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3652 gas_assert (!HAVE_CODE_COMPRESSION
);
3653 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3654 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3657 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3658 jr target pc &= 'hffff_ffff_cfff_ffff. */
3661 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3663 gas_assert (!HAVE_CODE_COMPRESSION
);
3664 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3665 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3666 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3674 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3675 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3678 ep
.X_op
= O_constant
;
3679 ep
.X_add_number
= 0xcfff0000;
3680 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3681 ep
.X_add_number
= 0xffff;
3682 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3683 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3688 fix_loongson2f (struct mips_cl_insn
* ip
)
3690 if (mips_fix_loongson2f_nop
)
3691 fix_loongson2f_nop (ip
);
3693 if (mips_fix_loongson2f_jump
)
3694 fix_loongson2f_jump (ip
);
3697 /* IP is a branch that has a delay slot, and we need to fill it
3698 automatically. Return true if we can do that by swapping IP
3699 with the previous instruction. */
3702 can_swap_branch_p (struct mips_cl_insn
*ip
)
3704 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3705 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3707 /* -O2 and above is required for this optimization. */
3708 if (mips_optimize
< 2)
3711 /* If we have seen .set volatile or .set nomove, don't optimize. */
3712 if (mips_opts
.nomove
)
3715 /* We can't swap if the previous instruction's position is fixed. */
3716 if (history
[0].fixed_p
)
3719 /* If the previous previous insn was in a .set noreorder, we can't
3720 swap. Actually, the MIPS assembler will swap in this situation.
3721 However, gcc configured -with-gnu-as will generate code like
3729 in which we can not swap the bne and INSN. If gcc is not configured
3730 -with-gnu-as, it does not output the .set pseudo-ops. */
3731 if (history
[1].noreorder_p
)
3734 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3735 This means that the previous instruction was a 4-byte one anyhow. */
3736 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3739 /* If the branch is itself the target of a branch, we can not swap.
3740 We cheat on this; all we check for is whether there is a label on
3741 this instruction. If there are any branches to anything other than
3742 a label, users must use .set noreorder. */
3743 if (seg_info (now_seg
)->label_list
)
3746 /* If the previous instruction is in a variant frag other than this
3747 branch's one, we cannot do the swap. This does not apply to
3748 MIPS16 code, which uses variant frags for different purposes. */
3749 if (!mips_opts
.mips16
3751 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3754 /* We do not swap with instructions that cannot architecturally
3755 be placed in a branch delay slot, such as SYNC or ERET. We
3756 also refrain from swapping with a trap instruction, since it
3757 complicates trap handlers to have the trap instruction be in
3759 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3760 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3763 /* Check for conflicts between the branch and the instructions
3764 before the candidate delay slot. */
3765 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3768 /* Check for conflicts between the swapped sequence and the
3769 target of the branch. */
3770 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3773 /* If the branch reads a register that the previous
3774 instruction sets, we can not swap. */
3775 gpr_read
= gpr_read_mask (ip
);
3776 prev_gpr_write
= gpr_write_mask (&history
[0]);
3777 if (gpr_read
& prev_gpr_write
)
3780 /* If the branch writes a register that the previous
3781 instruction sets, we can not swap. */
3782 gpr_write
= gpr_write_mask (ip
);
3783 if (gpr_write
& prev_gpr_write
)
3786 /* If the branch writes a register that the previous
3787 instruction reads, we can not swap. */
3788 prev_gpr_read
= gpr_read_mask (&history
[0]);
3789 if (gpr_write
& prev_gpr_read
)
3792 /* If one instruction sets a condition code and the
3793 other one uses a condition code, we can not swap. */
3794 pinfo
= ip
->insn_mo
->pinfo
;
3795 if ((pinfo
& INSN_READ_COND_CODE
)
3796 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3798 if ((pinfo
& INSN_WRITE_COND_CODE
)
3799 && (prev_pinfo
& INSN_READ_COND_CODE
))
3802 /* If the previous instruction uses the PC, we can not swap. */
3803 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3804 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3806 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3809 /* If the previous instruction has an incorrect size for a fixed
3810 branch delay slot in microMIPS mode, we cannot swap. */
3811 pinfo2
= ip
->insn_mo
->pinfo2
;
3812 if (mips_opts
.micromips
3813 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3814 && insn_length (history
) != 2)
3816 if (mips_opts
.micromips
3817 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3818 && insn_length (history
) != 4)
3824 /* Decide how we should add IP to the instruction stream. */
3826 static enum append_method
3827 get_append_method (struct mips_cl_insn
*ip
)
3829 unsigned long pinfo
;
3831 /* The relaxed version of a macro sequence must be inherently
3833 if (mips_relax
.sequence
== 2)
3836 /* We must not dabble with instructions in a ".set norerorder" block. */
3837 if (mips_opts
.noreorder
)
3840 /* Otherwise, it's our responsibility to fill branch delay slots. */
3841 if (delayed_branch_p (ip
))
3843 if (!branch_likely_p (ip
) && can_swap_branch_p (ip
))
3846 pinfo
= ip
->insn_mo
->pinfo
;
3847 if (mips_opts
.mips16
3848 && ISA_SUPPORTS_MIPS16E
3849 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
3850 return APPEND_ADD_COMPACT
;
3852 return APPEND_ADD_WITH_NOP
;
3858 /* IP is a MIPS16 instruction whose opcode we have just changed.
3859 Point IP->insn_mo to the new opcode's definition. */
3862 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
3864 const struct mips_opcode
*mo
, *end
;
3866 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
3867 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
3868 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
3876 /* For microMIPS macros, we need to generate a local number label
3877 as the target of branches. */
3878 #define MICROMIPS_LABEL_CHAR '\037'
3879 static unsigned long micromips_target_label
;
3880 static char micromips_target_name
[32];
3883 micromips_label_name (void)
3885 char *p
= micromips_target_name
;
3886 char symbol_name_temporary
[24];
3894 l
= micromips_target_label
;
3895 #ifdef LOCAL_LABEL_PREFIX
3896 *p
++ = LOCAL_LABEL_PREFIX
;
3899 *p
++ = MICROMIPS_LABEL_CHAR
;
3902 symbol_name_temporary
[i
++] = l
% 10 + '0';
3907 *p
++ = symbol_name_temporary
[--i
];
3910 return micromips_target_name
;
3914 micromips_label_expr (expressionS
*label_expr
)
3916 label_expr
->X_op
= O_symbol
;
3917 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
3918 label_expr
->X_add_number
= 0;
3922 micromips_label_inc (void)
3924 micromips_target_label
++;
3925 *micromips_target_name
= '\0';
3929 micromips_add_label (void)
3933 s
= colon (micromips_label_name ());
3934 micromips_label_inc ();
3935 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3937 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
3943 /* If assembling microMIPS code, then return the microMIPS reloc
3944 corresponding to the requested one if any. Otherwise return
3945 the reloc unchanged. */
3947 static bfd_reloc_code_real_type
3948 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
3950 static const bfd_reloc_code_real_type relocs
[][2] =
3952 /* Keep sorted incrementally by the left-hand key. */
3953 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
3954 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
3955 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
3956 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
3957 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
3958 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
3959 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
3960 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
3961 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
3962 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
3963 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
3964 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
3965 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
3966 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
3967 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
3968 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
3969 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
3970 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
3971 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
3972 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
3973 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
3974 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
3975 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
3976 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
3977 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
3978 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
3979 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
3981 bfd_reloc_code_real_type r
;
3984 if (!mips_opts
.micromips
)
3986 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
3992 return relocs
[i
][1];
3997 /* Output an instruction. IP is the instruction information.
3998 ADDRESS_EXPR is an operand of the instruction to be used with
3999 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4000 a macro expansion. */
4003 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4004 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4006 unsigned long prev_pinfo2
, pinfo
;
4007 bfd_boolean relaxed_branch
= FALSE
;
4008 enum append_method method
;
4009 bfd_boolean relax32
;
4012 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4013 fix_loongson2f (ip
);
4015 mips_mark_labels ();
4017 file_ase_mips16
|= mips_opts
.mips16
;
4018 file_ase_micromips
|= mips_opts
.micromips
;
4020 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4021 pinfo
= ip
->insn_mo
->pinfo
;
4023 if (mips_opts
.micromips
4025 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4026 && micromips_insn_length (ip
->insn_mo
) != 2)
4027 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4028 && micromips_insn_length (ip
->insn_mo
) != 4)))
4029 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4030 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4032 if (address_expr
== NULL
)
4034 else if (*reloc_type
<= BFD_RELOC_UNUSED
4035 && address_expr
->X_op
== O_constant
)
4040 switch (*reloc_type
)
4043 ip
->insn_opcode
|= address_expr
->X_add_number
;
4046 case BFD_RELOC_MIPS_HIGHEST
:
4047 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
4048 ip
->insn_opcode
|= tmp
& 0xffff;
4051 case BFD_RELOC_MIPS_HIGHER
:
4052 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
4053 ip
->insn_opcode
|= tmp
& 0xffff;
4056 case BFD_RELOC_HI16_S
:
4057 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
4058 ip
->insn_opcode
|= tmp
& 0xffff;
4061 case BFD_RELOC_HI16
:
4062 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
4065 case BFD_RELOC_UNUSED
:
4066 case BFD_RELOC_LO16
:
4067 case BFD_RELOC_MIPS_GOT_DISP
:
4068 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
4071 case BFD_RELOC_MIPS_JMP
:
4075 shift
= mips_opts
.micromips
? 1 : 2;
4076 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4077 as_bad (_("jump to misaligned address (0x%lx)"),
4078 (unsigned long) address_expr
->X_add_number
);
4079 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4085 case BFD_RELOC_MIPS16_JMP
:
4086 if ((address_expr
->X_add_number
& 3) != 0)
4087 as_bad (_("jump to misaligned address (0x%lx)"),
4088 (unsigned long) address_expr
->X_add_number
);
4090 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4091 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4092 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4096 case BFD_RELOC_16_PCREL_S2
:
4100 shift
= mips_opts
.micromips
? 1 : 2;
4101 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4102 as_bad (_("branch to misaligned address (0x%lx)"),
4103 (unsigned long) address_expr
->X_add_number
);
4104 if (!mips_relax_branch
)
4106 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4107 & ~((1 << (shift
+ 16)) - 1))
4108 as_bad (_("branch address range overflow (0x%lx)"),
4109 (unsigned long) address_expr
->X_add_number
);
4110 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4122 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4124 /* There are a lot of optimizations we could do that we don't.
4125 In particular, we do not, in general, reorder instructions.
4126 If you use gcc with optimization, it will reorder
4127 instructions and generally do much more optimization then we
4128 do here; repeating all that work in the assembler would only
4129 benefit hand written assembly code, and does not seem worth
4131 int nops
= (mips_optimize
== 0
4132 ? nops_for_insn (0, history
, NULL
)
4133 : nops_for_insn_or_target (0, history
, ip
));
4137 unsigned long old_frag_offset
;
4140 old_frag
= frag_now
;
4141 old_frag_offset
= frag_now_fix ();
4143 for (i
= 0; i
< nops
; i
++)
4144 add_fixed_insn (NOP_INSN
);
4145 insert_into_history (0, nops
, NOP_INSN
);
4149 listing_prev_line ();
4150 /* We may be at the start of a variant frag. In case we
4151 are, make sure there is enough space for the frag
4152 after the frags created by listing_prev_line. The
4153 argument to frag_grow here must be at least as large
4154 as the argument to all other calls to frag_grow in
4155 this file. We don't have to worry about being in the
4156 middle of a variant frag, because the variants insert
4157 all needed nop instructions themselves. */
4161 mips_move_text_labels ();
4163 #ifndef NO_ECOFF_DEBUGGING
4164 if (ECOFF_DEBUGGING
)
4165 ecoff_fix_loc (old_frag
, old_frag_offset
);
4169 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4173 /* Work out how many nops in prev_nop_frag are needed by IP,
4174 ignoring hazards generated by the first prev_nop_frag_since
4176 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4177 gas_assert (nops
<= prev_nop_frag_holds
);
4179 /* Enforce NOPS as a minimum. */
4180 if (nops
> prev_nop_frag_required
)
4181 prev_nop_frag_required
= nops
;
4183 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4185 /* Settle for the current number of nops. Update the history
4186 accordingly (for the benefit of any future .set reorder code). */
4187 prev_nop_frag
= NULL
;
4188 insert_into_history (prev_nop_frag_since
,
4189 prev_nop_frag_holds
, NOP_INSN
);
4193 /* Allow this instruction to replace one of the nops that was
4194 tentatively added to prev_nop_frag. */
4195 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4196 prev_nop_frag_holds
--;
4197 prev_nop_frag_since
++;
4201 method
= get_append_method (ip
);
4202 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4205 /* The value passed to dwarf2_emit_insn is the distance between
4206 the beginning of the current instruction and the address that
4207 should be recorded in the debug tables. This is normally the
4210 For MIPS16/microMIPS debug info we want to use ISA-encoded
4211 addresses, so we use -1 for an address higher by one than the
4214 If the instruction produced is a branch that we will swap with
4215 the preceding instruction, then we add the displacement by which
4216 the branch will be moved backwards. This is more appropriate
4217 and for MIPS16/microMIPS code also prevents a debugger from
4218 placing a breakpoint in the middle of the branch (and corrupting
4219 code if software breakpoints are used). */
4220 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION
? -1 : 0) + branch_disp
);
4223 relax32
= (mips_relax_branch
4224 /* Don't try branch relaxation within .set nomacro, or within
4225 .set noat if we use $at for PIC computations. If it turns
4226 out that the branch was out-of-range, we'll get an error. */
4227 && !mips_opts
.warn_about_macros
4228 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4229 /* Don't relax BPOSGE32/64 as they have no complementing
4231 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
)));
4233 if (!HAVE_CODE_COMPRESSION
4236 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4237 && delayed_branch_p (ip
))
4239 relaxed_branch
= TRUE
;
4240 add_relaxed_insn (ip
, (relaxed_branch_length
4242 uncond_branch_p (ip
) ? -1
4243 : branch_likely_p (ip
) ? 1
4247 uncond_branch_p (ip
),
4248 branch_likely_p (ip
),
4249 pinfo
& INSN_WRITE_GPR_31
,
4251 address_expr
->X_add_symbol
,
4252 address_expr
->X_add_number
);
4253 *reloc_type
= BFD_RELOC_UNUSED
;
4255 else if (mips_opts
.micromips
4257 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4258 || *reloc_type
> BFD_RELOC_UNUSED
)
4259 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4260 /* Don't try branch relaxation when users specify
4261 16-bit/32-bit instructions. */
4262 && !forced_insn_length
)
4264 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4265 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4266 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4267 int compact
= compact_branch_p (ip
);
4268 int al
= pinfo
& INSN_WRITE_GPR_31
;
4271 gas_assert (address_expr
!= NULL
);
4272 gas_assert (!mips_relax
.sequence
);
4274 relaxed_branch
= TRUE
;
4275 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4276 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4277 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4279 address_expr
->X_add_symbol
,
4280 address_expr
->X_add_number
);
4281 *reloc_type
= BFD_RELOC_UNUSED
;
4283 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4285 /* We need to set up a variant frag. */
4286 gas_assert (address_expr
!= NULL
);
4287 add_relaxed_insn (ip
, 4, 0,
4289 (*reloc_type
- BFD_RELOC_UNUSED
,
4290 forced_insn_length
== 2, forced_insn_length
== 4,
4291 delayed_branch_p (&history
[0]),
4292 history
[0].mips16_absolute_jump_p
),
4293 make_expr_symbol (address_expr
), 0);
4295 else if (mips_opts
.mips16
4297 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
4299 if (!delayed_branch_p (ip
))
4300 /* Make sure there is enough room to swap this instruction with
4301 a following jump instruction. */
4303 add_fixed_insn (ip
);
4307 if (mips_opts
.mips16
4308 && mips_opts
.noreorder
4309 && delayed_branch_p (&history
[0]))
4310 as_warn (_("extended instruction in delay slot"));
4312 if (mips_relax
.sequence
)
4314 /* If we've reached the end of this frag, turn it into a variant
4315 frag and record the information for the instructions we've
4317 if (frag_room () < 4)
4318 relax_close_frag ();
4319 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4322 if (mips_relax
.sequence
!= 2)
4324 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4325 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4326 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4327 mips_macro_warning
.insns
[0]++;
4329 if (mips_relax
.sequence
!= 1)
4331 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4332 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4333 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4334 mips_macro_warning
.insns
[1]++;
4337 if (mips_opts
.mips16
)
4340 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4342 add_fixed_insn (ip
);
4345 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4347 bfd_reloc_code_real_type final_type
[3];
4348 reloc_howto_type
*howto0
;
4349 reloc_howto_type
*howto
;
4352 /* Perform any necessary conversion to microMIPS relocations
4353 and find out how many relocations there actually are. */
4354 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4355 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4357 /* In a compound relocation, it is the final (outermost)
4358 operator that determines the relocated field. */
4359 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4363 /* To reproduce this failure try assembling gas/testsuites/
4364 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4366 as_bad (_("Unsupported MIPS relocation number %d"),
4368 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4372 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4373 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4374 bfd_get_reloc_size (howto
),
4376 howto0
&& howto0
->pc_relative
,
4379 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4380 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4381 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4383 /* These relocations can have an addend that won't fit in
4384 4 octets for 64bit assembly. */
4386 && ! howto
->partial_inplace
4387 && (reloc_type
[0] == BFD_RELOC_16
4388 || reloc_type
[0] == BFD_RELOC_32
4389 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4390 || reloc_type
[0] == BFD_RELOC_GPREL16
4391 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4392 || reloc_type
[0] == BFD_RELOC_GPREL32
4393 || reloc_type
[0] == BFD_RELOC_64
4394 || reloc_type
[0] == BFD_RELOC_CTOR
4395 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4396 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4397 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4398 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4399 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4400 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4401 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4402 || hi16_reloc_p (reloc_type
[0])
4403 || lo16_reloc_p (reloc_type
[0])))
4404 ip
->fixp
[0]->fx_no_overflow
= 1;
4406 if (mips_relax
.sequence
)
4408 if (mips_relax
.first_fixup
== 0)
4409 mips_relax
.first_fixup
= ip
->fixp
[0];
4411 else if (reloc_needs_lo_p (*reloc_type
))
4413 struct mips_hi_fixup
*hi_fixup
;
4415 /* Reuse the last entry if it already has a matching %lo. */
4416 hi_fixup
= mips_hi_fixup_list
;
4418 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4420 hi_fixup
= ((struct mips_hi_fixup
*)
4421 xmalloc (sizeof (struct mips_hi_fixup
)));
4422 hi_fixup
->next
= mips_hi_fixup_list
;
4423 mips_hi_fixup_list
= hi_fixup
;
4425 hi_fixup
->fixp
= ip
->fixp
[0];
4426 hi_fixup
->seg
= now_seg
;
4429 /* Add fixups for the second and third relocations, if given.
4430 Note that the ABI allows the second relocation to be
4431 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4432 moment we only use RSS_UNDEF, but we could add support
4433 for the others if it ever becomes necessary. */
4434 for (i
= 1; i
< 3; i
++)
4435 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4437 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4438 ip
->fixp
[0]->fx_size
, NULL
, 0,
4439 FALSE
, final_type
[i
]);
4441 /* Use fx_tcbit to mark compound relocs. */
4442 ip
->fixp
[0]->fx_tcbit
= 1;
4443 ip
->fixp
[i
]->fx_tcbit
= 1;
4448 /* Update the register mask information. */
4449 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4450 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4455 insert_into_history (0, 1, ip
);
4458 case APPEND_ADD_WITH_NOP
:
4460 struct mips_cl_insn
*nop
;
4462 insert_into_history (0, 1, ip
);
4463 nop
= get_delay_slot_nop (ip
);
4464 add_fixed_insn (nop
);
4465 insert_into_history (0, 1, nop
);
4466 if (mips_relax
.sequence
)
4467 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4471 case APPEND_ADD_COMPACT
:
4472 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4473 gas_assert (mips_opts
.mips16
);
4474 ip
->insn_opcode
|= 0x0080;
4475 find_altered_mips16_opcode (ip
);
4477 insert_into_history (0, 1, ip
);
4482 struct mips_cl_insn delay
= history
[0];
4483 if (mips_opts
.mips16
)
4485 know (delay
.frag
== ip
->frag
);
4486 move_insn (ip
, delay
.frag
, delay
.where
);
4487 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4489 else if (relaxed_branch
)
4491 /* Add the delay slot instruction to the end of the
4492 current frag and shrink the fixed part of the
4493 original frag. If the branch occupies the tail of
4494 the latter, move it backwards to cover the gap. */
4495 delay
.frag
->fr_fix
-= branch_disp
;
4496 if (delay
.frag
== ip
->frag
)
4497 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4498 add_fixed_insn (&delay
);
4502 move_insn (&delay
, ip
->frag
,
4503 ip
->where
- branch_disp
+ insn_length (ip
));
4504 move_insn (ip
, history
[0].frag
, history
[0].where
);
4508 insert_into_history (0, 1, &delay
);
4513 /* If we have just completed an unconditional branch, clear the history. */
4514 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4515 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4516 mips_no_prev_insn ();
4518 /* We need to emit a label at the end of branch-likely macros. */
4519 if (emit_branch_likely_macro
)
4521 emit_branch_likely_macro
= FALSE
;
4522 micromips_add_label ();
4525 /* We just output an insn, so the next one doesn't have a label. */
4526 mips_clear_insn_labels ();
4529 /* Forget that there was any previous instruction or label. */
4532 mips_no_prev_insn (void)
4534 prev_nop_frag
= NULL
;
4535 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4536 mips_clear_insn_labels ();
4539 /* This function must be called before we emit something other than
4540 instructions. It is like mips_no_prev_insn except that it inserts
4541 any NOPS that might be needed by previous instructions. */
4544 mips_emit_delays (void)
4546 if (! mips_opts
.noreorder
)
4548 int nops
= nops_for_insn (0, history
, NULL
);
4552 add_fixed_insn (NOP_INSN
);
4553 mips_move_text_labels ();
4556 mips_no_prev_insn ();
4559 /* Start a (possibly nested) noreorder block. */
4562 start_noreorder (void)
4564 if (mips_opts
.noreorder
== 0)
4569 /* None of the instructions before the .set noreorder can be moved. */
4570 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4571 history
[i
].fixed_p
= 1;
4573 /* Insert any nops that might be needed between the .set noreorder
4574 block and the previous instructions. We will later remove any
4575 nops that turn out not to be needed. */
4576 nops
= nops_for_insn (0, history
, NULL
);
4579 if (mips_optimize
!= 0)
4581 /* Record the frag which holds the nop instructions, so
4582 that we can remove them if we don't need them. */
4583 frag_grow (nops
* NOP_INSN_SIZE
);
4584 prev_nop_frag
= frag_now
;
4585 prev_nop_frag_holds
= nops
;
4586 prev_nop_frag_required
= 0;
4587 prev_nop_frag_since
= 0;
4590 for (; nops
> 0; --nops
)
4591 add_fixed_insn (NOP_INSN
);
4593 /* Move on to a new frag, so that it is safe to simply
4594 decrease the size of prev_nop_frag. */
4595 frag_wane (frag_now
);
4597 mips_move_text_labels ();
4599 mips_mark_labels ();
4600 mips_clear_insn_labels ();
4602 mips_opts
.noreorder
++;
4603 mips_any_noreorder
= 1;
4606 /* End a nested noreorder block. */
4609 end_noreorder (void)
4611 mips_opts
.noreorder
--;
4612 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4614 /* Commit to inserting prev_nop_frag_required nops and go back to
4615 handling nop insertion the .set reorder way. */
4616 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4618 insert_into_history (prev_nop_frag_since
,
4619 prev_nop_frag_required
, NOP_INSN
);
4620 prev_nop_frag
= NULL
;
4624 /* Set up global variables for the start of a new macro. */
4629 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4630 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4631 sizeof (mips_macro_warning
.first_insn_sizes
));
4632 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4633 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4634 && delayed_branch_p (&history
[0]));
4635 switch (history
[0].insn_mo
->pinfo2
4636 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4638 case INSN2_BRANCH_DELAY_32BIT
:
4639 mips_macro_warning
.delay_slot_length
= 4;
4641 case INSN2_BRANCH_DELAY_16BIT
:
4642 mips_macro_warning
.delay_slot_length
= 2;
4645 mips_macro_warning
.delay_slot_length
= 0;
4648 mips_macro_warning
.first_frag
= NULL
;
4651 /* Given that a macro is longer than one instruction or of the wrong size,
4652 return the appropriate warning for it. Return null if no warning is
4653 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4654 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4655 and RELAX_NOMACRO. */
4658 macro_warning (relax_substateT subtype
)
4660 if (subtype
& RELAX_DELAY_SLOT
)
4661 return _("Macro instruction expanded into multiple instructions"
4662 " in a branch delay slot");
4663 else if (subtype
& RELAX_NOMACRO
)
4664 return _("Macro instruction expanded into multiple instructions");
4665 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4666 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4667 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4668 ? _("Macro instruction expanded into a wrong size instruction"
4669 " in a 16-bit branch delay slot")
4670 : _("Macro instruction expanded into a wrong size instruction"
4671 " in a 32-bit branch delay slot"));
4676 /* Finish up a macro. Emit warnings as appropriate. */
4681 /* Relaxation warning flags. */
4682 relax_substateT subtype
= 0;
4684 /* Check delay slot size requirements. */
4685 if (mips_macro_warning
.delay_slot_length
== 2)
4686 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4687 if (mips_macro_warning
.delay_slot_length
!= 0)
4689 if (mips_macro_warning
.delay_slot_length
4690 != mips_macro_warning
.first_insn_sizes
[0])
4691 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4692 if (mips_macro_warning
.delay_slot_length
4693 != mips_macro_warning
.first_insn_sizes
[1])
4694 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4697 /* Check instruction count requirements. */
4698 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4700 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4701 subtype
|= RELAX_SECOND_LONGER
;
4702 if (mips_opts
.warn_about_macros
)
4703 subtype
|= RELAX_NOMACRO
;
4704 if (mips_macro_warning
.delay_slot_p
)
4705 subtype
|= RELAX_DELAY_SLOT
;
4708 /* If both alternatives fail to fill a delay slot correctly,
4709 emit the warning now. */
4710 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4711 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4716 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4717 | RELAX_DELAY_SLOT_SIZE_FIRST
4718 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4719 msg
= macro_warning (s
);
4721 as_warn ("%s", msg
);
4725 /* If both implementations are longer than 1 instruction, then emit the
4727 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4732 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4733 msg
= macro_warning (s
);
4735 as_warn ("%s", msg
);
4739 /* If any flags still set, then one implementation might need a warning
4740 and the other either will need one of a different kind or none at all.
4741 Pass any remaining flags over to relaxation. */
4742 if (mips_macro_warning
.first_frag
!= NULL
)
4743 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4746 /* Instruction operand formats used in macros that vary between
4747 standard MIPS and microMIPS code. */
4749 static const char * const brk_fmt
[2] = { "c", "mF" };
4750 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4751 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4752 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4753 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4754 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4755 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4756 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4758 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4759 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4760 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4761 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4762 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4763 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4764 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4765 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4767 /* Read a macro's relocation codes from *ARGS and store them in *R.
4768 The first argument in *ARGS will be either the code for a single
4769 relocation or -1 followed by the three codes that make up a
4770 composite relocation. */
4773 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4777 next
= va_arg (*args
, int);
4779 r
[0] = (bfd_reloc_code_real_type
) next
;
4781 for (i
= 0; i
< 3; i
++)
4782 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4785 /* Build an instruction created by a macro expansion. This is passed
4786 a pointer to the count of instructions created so far, an
4787 expression, the name of the instruction to build, an operand format
4788 string, and corresponding arguments. */
4791 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4793 const struct mips_opcode
*mo
= NULL
;
4794 bfd_reloc_code_real_type r
[3];
4795 const struct mips_opcode
*amo
;
4796 struct hash_control
*hash
;
4797 struct mips_cl_insn insn
;
4800 va_start (args
, fmt
);
4802 if (mips_opts
.mips16
)
4804 mips16_macro_build (ep
, name
, fmt
, &args
);
4809 r
[0] = BFD_RELOC_UNUSED
;
4810 r
[1] = BFD_RELOC_UNUSED
;
4811 r
[2] = BFD_RELOC_UNUSED
;
4812 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
4813 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
4815 gas_assert (strcmp (name
, amo
->name
) == 0);
4819 /* Search until we get a match for NAME. It is assumed here that
4820 macros will never generate MDMX, MIPS-3D, or MT instructions.
4821 We try to match an instruction that fulfils the branch delay
4822 slot instruction length requirement (if any) of the previous
4823 instruction. While doing this we record the first instruction
4824 seen that matches all the other conditions and use it anyway
4825 if the requirement cannot be met; we will issue an appropriate
4826 warning later on. */
4827 if (strcmp (fmt
, amo
->args
) == 0
4828 && amo
->pinfo
!= INSN_MACRO
4829 && is_opcode_valid (amo
)
4830 && is_size_valid (amo
))
4832 if (is_delay_slot_valid (amo
))
4842 gas_assert (amo
->name
);
4844 while (strcmp (name
, amo
->name
) == 0);
4847 create_insn (&insn
, mo
);
4865 INSERT_OPERAND (mips_opts
.micromips
,
4866 EXTLSB
, insn
, va_arg (args
, int));
4871 /* Note that in the macro case, these arguments are already
4872 in MSB form. (When handling the instruction in the
4873 non-macro case, these arguments are sizes from which
4874 MSB values must be calculated.) */
4875 INSERT_OPERAND (mips_opts
.micromips
,
4876 INSMSB
, insn
, va_arg (args
, int));
4882 /* Note that in the macro case, these arguments are already
4883 in MSBD form. (When handling the instruction in the
4884 non-macro case, these arguments are sizes from which
4885 MSBD values must be calculated.) */
4886 INSERT_OPERAND (mips_opts
.micromips
,
4887 EXTMSBD
, insn
, va_arg (args
, int));
4891 gas_assert (!mips_opts
.micromips
);
4892 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
4901 gas_assert (!mips_opts
.micromips
);
4902 INSERT_OPERAND (0, BP
, insn
, va_arg (args
, int));
4906 gas_assert (mips_opts
.micromips
);
4910 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
4914 gas_assert (!mips_opts
.micromips
);
4915 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
4919 gas_assert (!mips_opts
.micromips
);
4921 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
4925 if (mips_opts
.micromips
)
4926 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
4928 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
4932 gas_assert (!mips_opts
.micromips
);
4934 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
4938 gas_assert (!mips_opts
.micromips
);
4940 int tmp
= va_arg (args
, int);
4942 INSERT_OPERAND (0, RT
, insn
, tmp
);
4943 INSERT_OPERAND (0, RD
, insn
, tmp
);
4949 gas_assert (!mips_opts
.micromips
);
4950 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
4957 INSERT_OPERAND (mips_opts
.micromips
,
4958 SHAMT
, insn
, va_arg (args
, int));
4962 gas_assert (!mips_opts
.micromips
);
4963 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
4967 gas_assert (!mips_opts
.micromips
);
4968 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
4972 gas_assert (!mips_opts
.micromips
);
4973 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
4977 gas_assert (!mips_opts
.micromips
);
4978 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
4985 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
4990 macro_read_relocs (&args
, r
);
4991 gas_assert (*r
== BFD_RELOC_GPREL16
4992 || *r
== BFD_RELOC_MIPS_HIGHER
4993 || *r
== BFD_RELOC_HI16_S
4994 || *r
== BFD_RELOC_LO16
4995 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
4999 macro_read_relocs (&args
, r
);
5003 macro_read_relocs (&args
, r
);
5004 gas_assert (ep
!= NULL
5005 && (ep
->X_op
== O_constant
5006 || (ep
->X_op
== O_symbol
5007 && (*r
== BFD_RELOC_MIPS_HIGHEST
5008 || *r
== BFD_RELOC_HI16_S
5009 || *r
== BFD_RELOC_HI16
5010 || *r
== BFD_RELOC_GPREL16
5011 || *r
== BFD_RELOC_MIPS_GOT_HI16
5012 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5016 gas_assert (ep
!= NULL
);
5019 * This allows macro() to pass an immediate expression for
5020 * creating short branches without creating a symbol.
5022 * We don't allow branch relaxation for these branches, as
5023 * they should only appear in ".set nomacro" anyway.
5025 if (ep
->X_op
== O_constant
)
5027 /* For microMIPS we always use relocations for branches.
5028 So we should not resolve immediate values. */
5029 gas_assert (!mips_opts
.micromips
);
5031 if ((ep
->X_add_number
& 3) != 0)
5032 as_bad (_("branch to misaligned address (0x%lx)"),
5033 (unsigned long) ep
->X_add_number
);
5034 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5035 as_bad (_("branch address range overflow (0x%lx)"),
5036 (unsigned long) ep
->X_add_number
);
5037 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5041 *r
= BFD_RELOC_16_PCREL_S2
;
5045 gas_assert (ep
!= NULL
);
5046 *r
= BFD_RELOC_MIPS_JMP
;
5050 gas_assert (!mips_opts
.micromips
);
5051 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5055 INSERT_OPERAND (mips_opts
.micromips
,
5056 CACHE
, insn
, va_arg (args
, unsigned long));
5060 gas_assert (mips_opts
.micromips
);
5061 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5065 gas_assert (mips_opts
.micromips
);
5066 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5070 INSERT_OPERAND (mips_opts
.micromips
,
5071 3BITPOS
, insn
, va_arg (args
, unsigned int));
5075 INSERT_OPERAND (mips_opts
.micromips
,
5076 OFFSET12
, insn
, va_arg (args
, unsigned long));
5080 gas_assert (mips_opts
.micromips
);
5081 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5084 case 'm': /* Opcode extension character. */
5085 gas_assert (mips_opts
.micromips
);
5089 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5093 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5097 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5111 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5113 append_insn (&insn
, ep
, r
, TRUE
);
5117 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5120 struct mips_opcode
*mo
;
5121 struct mips_cl_insn insn
;
5122 bfd_reloc_code_real_type r
[3]
5123 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5125 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5127 gas_assert (strcmp (name
, mo
->name
) == 0);
5129 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5132 gas_assert (mo
->name
);
5133 gas_assert (strcmp (name
, mo
->name
) == 0);
5136 create_insn (&insn
, mo
);
5154 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5159 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5163 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5167 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5177 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5184 regno
= va_arg (*args
, int);
5185 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5186 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5207 gas_assert (ep
!= NULL
);
5209 if (ep
->X_op
!= O_constant
)
5210 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5213 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
5214 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
5217 *r
= BFD_RELOC_UNUSED
;
5223 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5230 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5232 append_insn (&insn
, ep
, r
, TRUE
);
5236 * Sign-extend 32-bit mode constants that have bit 31 set and all
5237 * higher bits unset.
5240 normalize_constant_expr (expressionS
*ex
)
5242 if (ex
->X_op
== O_constant
5243 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5244 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5249 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5250 * all higher bits unset.
5253 normalize_address_expr (expressionS
*ex
)
5255 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5256 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5257 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5258 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5263 * Generate a "jalr" instruction with a relocation hint to the called
5264 * function. This occurs in NewABI PIC code.
5267 macro_build_jalr (expressionS
*ep
, int cprestore
)
5269 static const bfd_reloc_code_real_type jalr_relocs
[2]
5270 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5271 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5275 if (MIPS_JALR_HINT_P (ep
))
5280 if (mips_opts
.micromips
)
5282 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5283 if (MIPS_JALR_HINT_P (ep
))
5284 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5286 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5289 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5290 if (MIPS_JALR_HINT_P (ep
))
5291 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5295 * Generate a "lui" instruction.
5298 macro_build_lui (expressionS
*ep
, int regnum
)
5300 gas_assert (! mips_opts
.mips16
);
5302 if (ep
->X_op
!= O_constant
)
5304 gas_assert (ep
->X_op
== O_symbol
);
5305 /* _gp_disp is a special case, used from s_cpload.
5306 __gnu_local_gp is used if mips_no_shared. */
5307 gas_assert (mips_pic
== NO_PIC
5309 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5310 || (! mips_in_shared
5311 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5312 "__gnu_local_gp") == 0));
5315 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5318 /* Generate a sequence of instructions to do a load or store from a constant
5319 offset off of a base register (breg) into/from a target register (treg),
5320 using AT if necessary. */
5322 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5323 int treg
, int breg
, int dbl
)
5325 gas_assert (ep
->X_op
== O_constant
);
5327 /* Sign-extending 32-bit constants makes their handling easier. */
5329 normalize_constant_expr (ep
);
5331 /* Right now, this routine can only handle signed 32-bit constants. */
5332 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5333 as_warn (_("operand overflow"));
5335 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5337 /* Signed 16-bit offset will fit in the op. Easy! */
5338 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5342 /* 32-bit offset, need multiple instructions and AT, like:
5343 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5344 addu $tempreg,$tempreg,$breg
5345 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5346 to handle the complete offset. */
5347 macro_build_lui (ep
, AT
);
5348 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5349 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5352 as_bad (_("Macro used $at after \".set noat\""));
5357 * Generates code to set the $at register to true (one)
5358 * if reg is less than the immediate expression.
5361 set_at (int reg
, int unsignedp
)
5363 if (imm_expr
.X_op
== O_constant
5364 && imm_expr
.X_add_number
>= -0x8000
5365 && imm_expr
.X_add_number
< 0x8000)
5366 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5367 AT
, reg
, BFD_RELOC_LO16
);
5370 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5371 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5375 /* Warn if an expression is not a constant. */
5378 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5380 if (ex
->X_op
== O_big
)
5381 as_bad (_("unsupported large constant"));
5382 else if (ex
->X_op
!= O_constant
)
5383 as_bad (_("Instruction %s requires absolute expression"),
5386 if (HAVE_32BIT_GPRS
)
5387 normalize_constant_expr (ex
);
5390 /* Count the leading zeroes by performing a binary chop. This is a
5391 bulky bit of source, but performance is a LOT better for the
5392 majority of values than a simple loop to count the bits:
5393 for (lcnt = 0; (lcnt < 32); lcnt++)
5394 if ((v) & (1 << (31 - lcnt)))
5396 However it is not code size friendly, and the gain will drop a bit
5397 on certain cached systems.
5399 #define COUNT_TOP_ZEROES(v) \
5400 (((v) & ~0xffff) == 0 \
5401 ? ((v) & ~0xff) == 0 \
5402 ? ((v) & ~0xf) == 0 \
5403 ? ((v) & ~0x3) == 0 \
5404 ? ((v) & ~0x1) == 0 \
5409 : ((v) & ~0x7) == 0 \
5412 : ((v) & ~0x3f) == 0 \
5413 ? ((v) & ~0x1f) == 0 \
5416 : ((v) & ~0x7f) == 0 \
5419 : ((v) & ~0xfff) == 0 \
5420 ? ((v) & ~0x3ff) == 0 \
5421 ? ((v) & ~0x1ff) == 0 \
5424 : ((v) & ~0x7ff) == 0 \
5427 : ((v) & ~0x3fff) == 0 \
5428 ? ((v) & ~0x1fff) == 0 \
5431 : ((v) & ~0x7fff) == 0 \
5434 : ((v) & ~0xffffff) == 0 \
5435 ? ((v) & ~0xfffff) == 0 \
5436 ? ((v) & ~0x3ffff) == 0 \
5437 ? ((v) & ~0x1ffff) == 0 \
5440 : ((v) & ~0x7ffff) == 0 \
5443 : ((v) & ~0x3fffff) == 0 \
5444 ? ((v) & ~0x1fffff) == 0 \
5447 : ((v) & ~0x7fffff) == 0 \
5450 : ((v) & ~0xfffffff) == 0 \
5451 ? ((v) & ~0x3ffffff) == 0 \
5452 ? ((v) & ~0x1ffffff) == 0 \
5455 : ((v) & ~0x7ffffff) == 0 \
5458 : ((v) & ~0x3fffffff) == 0 \
5459 ? ((v) & ~0x1fffffff) == 0 \
5462 : ((v) & ~0x7fffffff) == 0 \
5467 * This routine generates the least number of instructions necessary to load
5468 * an absolute expression value into a register.
5471 load_register (int reg
, expressionS
*ep
, int dbl
)
5474 expressionS hi32
, lo32
;
5476 if (ep
->X_op
!= O_big
)
5478 gas_assert (ep
->X_op
== O_constant
);
5480 /* Sign-extending 32-bit constants makes their handling easier. */
5482 normalize_constant_expr (ep
);
5484 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5486 /* We can handle 16 bit signed values with an addiu to
5487 $zero. No need to ever use daddiu here, since $zero and
5488 the result are always correct in 32 bit mode. */
5489 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5492 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5494 /* We can handle 16 bit unsigned values with an ori to
5496 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5499 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5501 /* 32 bit values require an lui. */
5502 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5503 if ((ep
->X_add_number
& 0xffff) != 0)
5504 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5509 /* The value is larger than 32 bits. */
5511 if (!dbl
|| HAVE_32BIT_GPRS
)
5515 sprintf_vma (value
, ep
->X_add_number
);
5516 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5517 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5521 if (ep
->X_op
!= O_big
)
5524 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5525 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5526 hi32
.X_add_number
&= 0xffffffff;
5528 lo32
.X_add_number
&= 0xffffffff;
5532 gas_assert (ep
->X_add_number
> 2);
5533 if (ep
->X_add_number
== 3)
5534 generic_bignum
[3] = 0;
5535 else if (ep
->X_add_number
> 4)
5536 as_bad (_("Number larger than 64 bits"));
5537 lo32
.X_op
= O_constant
;
5538 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5539 hi32
.X_op
= O_constant
;
5540 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5543 if (hi32
.X_add_number
== 0)
5548 unsigned long hi
, lo
;
5550 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5552 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5554 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5557 if (lo32
.X_add_number
& 0x80000000)
5559 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5560 if (lo32
.X_add_number
& 0xffff)
5561 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5566 /* Check for 16bit shifted constant. We know that hi32 is
5567 non-zero, so start the mask on the first bit of the hi32
5572 unsigned long himask
, lomask
;
5576 himask
= 0xffff >> (32 - shift
);
5577 lomask
= (0xffff << shift
) & 0xffffffff;
5581 himask
= 0xffff << (shift
- 32);
5584 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5585 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5589 tmp
.X_op
= O_constant
;
5591 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5592 | (lo32
.X_add_number
>> shift
));
5594 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5595 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5596 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5597 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5602 while (shift
<= (64 - 16));
5604 /* Find the bit number of the lowest one bit, and store the
5605 shifted value in hi/lo. */
5606 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5607 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5611 while ((lo
& 1) == 0)
5616 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5622 while ((hi
& 1) == 0)
5631 /* Optimize if the shifted value is a (power of 2) - 1. */
5632 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5633 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5635 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5640 /* This instruction will set the register to be all
5642 tmp
.X_op
= O_constant
;
5643 tmp
.X_add_number
= (offsetT
) -1;
5644 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5648 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5649 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5651 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5652 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5657 /* Sign extend hi32 before calling load_register, because we can
5658 generally get better code when we load a sign extended value. */
5659 if ((hi32
.X_add_number
& 0x80000000) != 0)
5660 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5661 load_register (reg
, &hi32
, 0);
5664 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5668 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5676 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5678 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5679 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5685 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5689 mid16
.X_add_number
>>= 16;
5690 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5691 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5694 if ((lo32
.X_add_number
& 0xffff) != 0)
5695 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5699 load_delay_nop (void)
5701 if (!gpr_interlocks
)
5702 macro_build (NULL
, "nop", "");
5705 /* Load an address into a register. */
5708 load_address (int reg
, expressionS
*ep
, int *used_at
)
5710 if (ep
->X_op
!= O_constant
5711 && ep
->X_op
!= O_symbol
)
5713 as_bad (_("expression too complex"));
5714 ep
->X_op
= O_constant
;
5717 if (ep
->X_op
== O_constant
)
5719 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5723 if (mips_pic
== NO_PIC
)
5725 /* If this is a reference to a GP relative symbol, we want
5726 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5728 lui $reg,<sym> (BFD_RELOC_HI16_S)
5729 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5730 If we have an addend, we always use the latter form.
5732 With 64bit address space and a usable $at we want
5733 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5734 lui $at,<sym> (BFD_RELOC_HI16_S)
5735 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5736 daddiu $at,<sym> (BFD_RELOC_LO16)
5740 If $at is already in use, we use a path which is suboptimal
5741 on superscalar processors.
5742 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5743 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5745 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5747 daddiu $reg,<sym> (BFD_RELOC_LO16)
5749 For GP relative symbols in 64bit address space we can use
5750 the same sequence as in 32bit address space. */
5751 if (HAVE_64BIT_SYMBOLS
)
5753 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5754 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5756 relax_start (ep
->X_add_symbol
);
5757 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5758 mips_gp_register
, BFD_RELOC_GPREL16
);
5762 if (*used_at
== 0 && mips_opts
.at
)
5764 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5765 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5766 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5767 BFD_RELOC_MIPS_HIGHER
);
5768 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5769 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5770 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5775 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5776 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5777 BFD_RELOC_MIPS_HIGHER
);
5778 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5779 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5780 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5781 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5784 if (mips_relax
.sequence
)
5789 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5790 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5792 relax_start (ep
->X_add_symbol
);
5793 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5794 mips_gp_register
, BFD_RELOC_GPREL16
);
5797 macro_build_lui (ep
, reg
);
5798 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
5799 reg
, reg
, BFD_RELOC_LO16
);
5800 if (mips_relax
.sequence
)
5804 else if (!mips_big_got
)
5808 /* If this is a reference to an external symbol, we want
5809 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5811 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5813 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5814 If there is a constant, it must be added in after.
5816 If we have NewABI, we want
5817 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5818 unless we're referencing a global symbol with a non-zero
5819 offset, in which case cst must be added separately. */
5822 if (ep
->X_add_number
)
5824 ex
.X_add_number
= ep
->X_add_number
;
5825 ep
->X_add_number
= 0;
5826 relax_start (ep
->X_add_symbol
);
5827 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5828 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5829 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5830 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5831 ex
.X_op
= O_constant
;
5832 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5833 reg
, reg
, BFD_RELOC_LO16
);
5834 ep
->X_add_number
= ex
.X_add_number
;
5837 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5838 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5839 if (mips_relax
.sequence
)
5844 ex
.X_add_number
= ep
->X_add_number
;
5845 ep
->X_add_number
= 0;
5846 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5847 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5849 relax_start (ep
->X_add_symbol
);
5851 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5855 if (ex
.X_add_number
!= 0)
5857 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5858 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5859 ex
.X_op
= O_constant
;
5860 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5861 reg
, reg
, BFD_RELOC_LO16
);
5865 else if (mips_big_got
)
5869 /* This is the large GOT case. If this is a reference to an
5870 external symbol, we want
5871 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5873 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5875 Otherwise, for a reference to a local symbol in old ABI, we want
5876 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5878 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5879 If there is a constant, it must be added in after.
5881 In the NewABI, for local symbols, with or without offsets, we want:
5882 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5883 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5887 ex
.X_add_number
= ep
->X_add_number
;
5888 ep
->X_add_number
= 0;
5889 relax_start (ep
->X_add_symbol
);
5890 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5891 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5892 reg
, reg
, mips_gp_register
);
5893 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5894 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5895 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5896 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5897 else if (ex
.X_add_number
)
5899 ex
.X_op
= O_constant
;
5900 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5904 ep
->X_add_number
= ex
.X_add_number
;
5906 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5907 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5908 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5909 BFD_RELOC_MIPS_GOT_OFST
);
5914 ex
.X_add_number
= ep
->X_add_number
;
5915 ep
->X_add_number
= 0;
5916 relax_start (ep
->X_add_symbol
);
5917 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5918 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5919 reg
, reg
, mips_gp_register
);
5920 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5921 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5923 if (reg_needs_delay (mips_gp_register
))
5925 /* We need a nop before loading from $gp. This special
5926 check is required because the lui which starts the main
5927 instruction stream does not refer to $gp, and so will not
5928 insert the nop which may be required. */
5929 macro_build (NULL
, "nop", "");
5931 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5932 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5934 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5938 if (ex
.X_add_number
!= 0)
5940 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5941 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5942 ex
.X_op
= O_constant
;
5943 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5951 if (!mips_opts
.at
&& *used_at
== 1)
5952 as_bad (_("Macro used $at after \".set noat\""));
5955 /* Move the contents of register SOURCE into register DEST. */
5958 move_register (int dest
, int source
)
5960 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5961 instruction specifically requires a 32-bit one. */
5962 if (mips_opts
.micromips
5963 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5964 macro_build (NULL
, "move", "mp,mj", dest
, source
);
5966 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
5970 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5971 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5972 The two alternatives are:
5974 Global symbol Local sybmol
5975 ------------- ------------
5976 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5978 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5980 load_got_offset emits the first instruction and add_got_offset
5981 emits the second for a 16-bit offset or add_got_offset_hilo emits
5982 a sequence to add a 32-bit offset using a scratch register. */
5985 load_got_offset (int dest
, expressionS
*local
)
5990 global
.X_add_number
= 0;
5992 relax_start (local
->X_add_symbol
);
5993 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
5994 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5996 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
5997 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6002 add_got_offset (int dest
, expressionS
*local
)
6006 global
.X_op
= O_constant
;
6007 global
.X_op_symbol
= NULL
;
6008 global
.X_add_symbol
= NULL
;
6009 global
.X_add_number
= local
->X_add_number
;
6011 relax_start (local
->X_add_symbol
);
6012 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6013 dest
, dest
, BFD_RELOC_LO16
);
6015 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6020 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6023 int hold_mips_optimize
;
6025 global
.X_op
= O_constant
;
6026 global
.X_op_symbol
= NULL
;
6027 global
.X_add_symbol
= NULL
;
6028 global
.X_add_number
= local
->X_add_number
;
6030 relax_start (local
->X_add_symbol
);
6031 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6033 /* Set mips_optimize around the lui instruction to avoid
6034 inserting an unnecessary nop after the lw. */
6035 hold_mips_optimize
= mips_optimize
;
6037 macro_build_lui (&global
, tmp
);
6038 mips_optimize
= hold_mips_optimize
;
6039 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6042 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6045 /* Emit a sequence of instructions to emulate a branch likely operation.
6046 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6047 is its complementing branch with the original condition negated.
6048 CALL is set if the original branch specified the link operation.
6049 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6051 Code like this is produced in the noreorder mode:
6056 delay slot (executed only if branch taken)
6064 delay slot (executed only if branch taken)
6067 In the reorder mode the delay slot would be filled with a nop anyway,
6068 so code produced is simply:
6073 This function is used when producing code for the microMIPS ASE that
6074 does not implement branch likely instructions in hardware. */
6077 macro_build_branch_likely (const char *br
, const char *brneg
,
6078 int call
, expressionS
*ep
, const char *fmt
,
6079 unsigned int sreg
, unsigned int treg
)
6081 int noreorder
= mips_opts
.noreorder
;
6084 gas_assert (mips_opts
.micromips
);
6088 micromips_label_expr (&expr1
);
6089 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6090 macro_build (NULL
, "nop", "");
6091 macro_build (ep
, call
? "bal" : "b", "p");
6093 /* Set to true so that append_insn adds a label. */
6094 emit_branch_likely_macro
= TRUE
;
6098 macro_build (ep
, br
, fmt
, sreg
, treg
);
6099 macro_build (NULL
, "nop", "");
6104 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6105 the condition code tested. EP specifies the branch target. */
6108 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6135 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6138 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6139 the register tested. EP specifies the branch target. */
6142 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6144 const char *brneg
= NULL
;
6154 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6158 gas_assert (mips_opts
.micromips
);
6167 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6174 br
= mips_opts
.micromips
? "blez" : "blezl";
6181 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6185 gas_assert (mips_opts
.micromips
);
6193 if (mips_opts
.micromips
&& brneg
)
6194 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6196 macro_build (ep
, br
, "s,p", sreg
);
6199 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6200 TREG as the registers tested. EP specifies the branch target. */
6203 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6204 unsigned int sreg
, unsigned int treg
)
6206 const char *brneg
= NULL
;
6218 br
= mips_opts
.micromips
? "beq" : "beql";
6227 br
= mips_opts
.micromips
? "bne" : "bnel";
6233 if (mips_opts
.micromips
&& brneg
)
6234 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6236 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6241 * This routine implements the seemingly endless macro or synthesized
6242 * instructions and addressing modes in the mips assembly language. Many
6243 * of these macros are simple and are similar to each other. These could
6244 * probably be handled by some kind of table or grammar approach instead of
6245 * this verbose method. Others are not simple macros but are more like
6246 * optimizing code generation.
6247 * One interesting optimization is when several store macros appear
6248 * consecutively that would load AT with the upper half of the same address.
6249 * The ensuing load upper instructions are ommited. This implies some kind
6250 * of global optimization. We currently only optimize within a single macro.
6251 * For many of the load and store macros if the address is specified as a
6252 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6253 * first load register 'at' with zero and use it as the base register. The
6254 * mips assembler simply uses register $zero. Just one tiny optimization
6258 macro (struct mips_cl_insn
*ip
)
6260 unsigned int treg
, sreg
, dreg
, breg
;
6261 unsigned int tempreg
;
6264 expressionS label_expr
;
6283 bfd_reloc_code_real_type r
;
6284 int hold_mips_optimize
;
6286 gas_assert (! mips_opts
.mips16
);
6288 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6289 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6290 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6291 mask
= ip
->insn_mo
->mask
;
6293 label_expr
.X_op
= O_constant
;
6294 label_expr
.X_op_symbol
= NULL
;
6295 label_expr
.X_add_symbol
= NULL
;
6296 label_expr
.X_add_number
= 0;
6298 expr1
.X_op
= O_constant
;
6299 expr1
.X_op_symbol
= NULL
;
6300 expr1
.X_add_symbol
= NULL
;
6301 expr1
.X_add_number
= 1;
6316 if (mips_opts
.micromips
)
6317 micromips_label_expr (&label_expr
);
6319 label_expr
.X_add_number
= 8;
6320 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6322 macro_build (NULL
, "nop", "");
6324 move_register (dreg
, sreg
);
6325 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6326 if (mips_opts
.micromips
)
6327 micromips_add_label ();
6344 if (!mips_opts
.micromips
)
6346 if (imm_expr
.X_op
== O_constant
6347 && imm_expr
.X_add_number
>= -0x200
6348 && imm_expr
.X_add_number
< 0x200)
6350 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6359 if (imm_expr
.X_op
== O_constant
6360 && imm_expr
.X_add_number
>= -0x8000
6361 && imm_expr
.X_add_number
< 0x8000)
6363 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6368 load_register (AT
, &imm_expr
, dbl
);
6369 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6388 if (imm_expr
.X_op
== O_constant
6389 && imm_expr
.X_add_number
>= 0
6390 && imm_expr
.X_add_number
< 0x10000)
6392 if (mask
!= M_NOR_I
)
6393 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6396 macro_build (&imm_expr
, "ori", "t,r,i",
6397 treg
, sreg
, BFD_RELOC_LO16
);
6398 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6404 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6405 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6409 switch (imm_expr
.X_add_number
)
6412 macro_build (NULL
, "nop", "");
6415 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6418 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6419 (int) imm_expr
.X_add_number
);
6428 gas_assert (mips_opts
.micromips
);
6429 macro_build_branch_ccl (mask
, &offset_expr
,
6430 EXTRACT_OPERAND (1, BCC
, *ip
));
6437 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6443 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6448 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6455 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6457 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6461 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6462 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6463 &offset_expr
, AT
, ZERO
);
6473 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6479 /* Check for > max integer. */
6480 maxnum
= 0x7fffffff;
6481 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6488 if (imm_expr
.X_op
== O_constant
6489 && imm_expr
.X_add_number
>= maxnum
6490 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6493 /* Result is always false. */
6495 macro_build (NULL
, "nop", "");
6497 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6500 if (imm_expr
.X_op
!= O_constant
)
6501 as_bad (_("Unsupported large constant"));
6502 ++imm_expr
.X_add_number
;
6506 if (mask
== M_BGEL_I
)
6508 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6510 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6511 &offset_expr
, sreg
);
6514 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6516 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6517 &offset_expr
, sreg
);
6520 maxnum
= 0x7fffffff;
6521 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6528 maxnum
= - maxnum
- 1;
6529 if (imm_expr
.X_op
== O_constant
6530 && imm_expr
.X_add_number
<= maxnum
6531 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6534 /* result is always true */
6535 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6536 macro_build (&offset_expr
, "b", "p");
6541 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6542 &offset_expr
, AT
, ZERO
);
6551 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6552 &offset_expr
, ZERO
, treg
);
6556 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6557 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6558 &offset_expr
, AT
, ZERO
);
6567 && imm_expr
.X_op
== O_constant
6568 && imm_expr
.X_add_number
== -1))
6570 if (imm_expr
.X_op
!= O_constant
)
6571 as_bad (_("Unsupported large constant"));
6572 ++imm_expr
.X_add_number
;
6576 if (mask
== M_BGEUL_I
)
6578 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6580 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6581 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6582 &offset_expr
, sreg
, ZERO
);
6587 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6588 &offset_expr
, AT
, ZERO
);
6596 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6598 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6602 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6603 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6604 &offset_expr
, AT
, ZERO
);
6612 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6613 &offset_expr
, sreg
, ZERO
);
6619 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6620 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6621 &offset_expr
, AT
, ZERO
);
6629 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6631 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6635 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6636 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6637 &offset_expr
, AT
, ZERO
);
6644 maxnum
= 0x7fffffff;
6645 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6652 if (imm_expr
.X_op
== O_constant
6653 && imm_expr
.X_add_number
>= maxnum
6654 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6656 if (imm_expr
.X_op
!= O_constant
)
6657 as_bad (_("Unsupported large constant"));
6658 ++imm_expr
.X_add_number
;
6662 if (mask
== M_BLTL_I
)
6664 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6665 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6666 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6667 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6672 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6673 &offset_expr
, AT
, ZERO
);
6681 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6682 &offset_expr
, sreg
, ZERO
);
6688 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6689 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6690 &offset_expr
, AT
, ZERO
);
6699 && imm_expr
.X_op
== O_constant
6700 && imm_expr
.X_add_number
== -1))
6702 if (imm_expr
.X_op
!= O_constant
)
6703 as_bad (_("Unsupported large constant"));
6704 ++imm_expr
.X_add_number
;
6708 if (mask
== M_BLTUL_I
)
6710 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6712 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6713 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6714 &offset_expr
, sreg
, ZERO
);
6719 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6720 &offset_expr
, AT
, ZERO
);
6728 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6730 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6734 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6735 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6736 &offset_expr
, AT
, ZERO
);
6746 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6747 &offset_expr
, ZERO
, treg
);
6751 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6752 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6753 &offset_expr
, AT
, ZERO
);
6759 /* Use unsigned arithmetic. */
6763 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6765 as_bad (_("Unsupported large constant"));
6770 pos
= imm_expr
.X_add_number
;
6771 size
= imm2_expr
.X_add_number
;
6776 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6779 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6781 as_bad (_("Improper extract size (%lu, position %lu)"),
6782 (unsigned long) size
, (unsigned long) pos
);
6786 if (size
<= 32 && pos
< 32)
6791 else if (size
<= 32)
6801 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6808 /* Use unsigned arithmetic. */
6812 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6814 as_bad (_("Unsupported large constant"));
6819 pos
= imm_expr
.X_add_number
;
6820 size
= imm2_expr
.X_add_number
;
6825 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6828 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6830 as_bad (_("Improper insert size (%lu, position %lu)"),
6831 (unsigned long) size
, (unsigned long) pos
);
6835 if (pos
< 32 && (pos
+ size
- 1) < 32)
6850 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6851 (int) (pos
+ size
- 1));
6867 as_warn (_("Divide by zero."));
6869 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
6871 macro_build (NULL
, "break", BRK_FMT
, 7);
6878 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
6879 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6883 if (mips_opts
.micromips
)
6884 micromips_label_expr (&label_expr
);
6886 label_expr
.X_add_number
= 8;
6887 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
6888 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6889 macro_build (NULL
, "break", BRK_FMT
, 7);
6890 if (mips_opts
.micromips
)
6891 micromips_add_label ();
6893 expr1
.X_add_number
= -1;
6895 load_register (AT
, &expr1
, dbl
);
6896 if (mips_opts
.micromips
)
6897 micromips_label_expr (&label_expr
);
6899 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
6900 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
6903 expr1
.X_add_number
= 1;
6904 load_register (AT
, &expr1
, dbl
);
6905 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
6909 expr1
.X_add_number
= 0x80000000;
6910 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
6914 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
6915 /* We want to close the noreorder block as soon as possible, so
6916 that later insns are available for delay slot filling. */
6921 if (mips_opts
.micromips
)
6922 micromips_label_expr (&label_expr
);
6924 label_expr
.X_add_number
= 8;
6925 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
6926 macro_build (NULL
, "nop", "");
6928 /* We want to close the noreorder block as soon as possible, so
6929 that later insns are available for delay slot filling. */
6932 macro_build (NULL
, "break", BRK_FMT
, 6);
6934 if (mips_opts
.micromips
)
6935 micromips_add_label ();
6936 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
6975 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6977 as_warn (_("Divide by zero."));
6979 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
6981 macro_build (NULL
, "break", BRK_FMT
, 7);
6984 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6986 if (strcmp (s2
, "mflo") == 0)
6987 move_register (dreg
, sreg
);
6989 move_register (dreg
, ZERO
);
6992 if (imm_expr
.X_op
== O_constant
6993 && imm_expr
.X_add_number
== -1
6994 && s
[strlen (s
) - 1] != 'u')
6996 if (strcmp (s2
, "mflo") == 0)
6998 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7001 move_register (dreg
, ZERO
);
7006 load_register (AT
, &imm_expr
, dbl
);
7007 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7008 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7030 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7031 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7032 /* We want to close the noreorder block as soon as possible, so
7033 that later insns are available for delay slot filling. */
7038 if (mips_opts
.micromips
)
7039 micromips_label_expr (&label_expr
);
7041 label_expr
.X_add_number
= 8;
7042 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7043 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7045 /* We want to close the noreorder block as soon as possible, so
7046 that later insns are available for delay slot filling. */
7048 macro_build (NULL
, "break", BRK_FMT
, 7);
7049 if (mips_opts
.micromips
)
7050 micromips_add_label ();
7052 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7064 /* Load the address of a symbol into a register. If breg is not
7065 zero, we then add a base register to it. */
7067 if (dbl
&& HAVE_32BIT_GPRS
)
7068 as_warn (_("dla used to load 32-bit register"));
7070 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7071 as_warn (_("la used to load 64-bit address"));
7073 if (offset_expr
.X_op
== O_constant
7074 && offset_expr
.X_add_number
>= -0x8000
7075 && offset_expr
.X_add_number
< 0x8000)
7077 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7078 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7082 if (mips_opts
.at
&& (treg
== breg
))
7092 if (offset_expr
.X_op
!= O_symbol
7093 && offset_expr
.X_op
!= O_constant
)
7095 as_bad (_("Expression too complex"));
7096 offset_expr
.X_op
= O_constant
;
7099 if (offset_expr
.X_op
== O_constant
)
7100 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7101 else if (mips_pic
== NO_PIC
)
7103 /* If this is a reference to a GP relative symbol, we want
7104 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7106 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7107 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7108 If we have a constant, we need two instructions anyhow,
7109 so we may as well always use the latter form.
7111 With 64bit address space and a usable $at we want
7112 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7113 lui $at,<sym> (BFD_RELOC_HI16_S)
7114 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7115 daddiu $at,<sym> (BFD_RELOC_LO16)
7117 daddu $tempreg,$tempreg,$at
7119 If $at is already in use, we use a path which is suboptimal
7120 on superscalar processors.
7121 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7122 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7124 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7126 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7128 For GP relative symbols in 64bit address space we can use
7129 the same sequence as in 32bit address space. */
7130 if (HAVE_64BIT_SYMBOLS
)
7132 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7133 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7135 relax_start (offset_expr
.X_add_symbol
);
7136 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7137 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7141 if (used_at
== 0 && mips_opts
.at
)
7143 macro_build (&offset_expr
, "lui", LUI_FMT
,
7144 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7145 macro_build (&offset_expr
, "lui", LUI_FMT
,
7146 AT
, BFD_RELOC_HI16_S
);
7147 macro_build (&offset_expr
, "daddiu", "t,r,j",
7148 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7149 macro_build (&offset_expr
, "daddiu", "t,r,j",
7150 AT
, AT
, BFD_RELOC_LO16
);
7151 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7152 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7157 macro_build (&offset_expr
, "lui", LUI_FMT
,
7158 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7159 macro_build (&offset_expr
, "daddiu", "t,r,j",
7160 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7161 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7162 macro_build (&offset_expr
, "daddiu", "t,r,j",
7163 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7164 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7165 macro_build (&offset_expr
, "daddiu", "t,r,j",
7166 tempreg
, tempreg
, BFD_RELOC_LO16
);
7169 if (mips_relax
.sequence
)
7174 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7175 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7177 relax_start (offset_expr
.X_add_symbol
);
7178 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7179 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7182 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7183 as_bad (_("Offset too large"));
7184 macro_build_lui (&offset_expr
, tempreg
);
7185 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7186 tempreg
, tempreg
, BFD_RELOC_LO16
);
7187 if (mips_relax
.sequence
)
7191 else if (!mips_big_got
&& !HAVE_NEWABI
)
7193 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7195 /* If this is a reference to an external symbol, and there
7196 is no constant, we want
7197 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7198 or for lca or if tempreg is PIC_CALL_REG
7199 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7200 For a local symbol, we want
7201 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7203 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7205 If we have a small constant, and this is a reference to
7206 an external symbol, we want
7207 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7209 addiu $tempreg,$tempreg,<constant>
7210 For a local symbol, we want the same instruction
7211 sequence, but we output a BFD_RELOC_LO16 reloc on the
7214 If we have a large constant, and this is a reference to
7215 an external symbol, we want
7216 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7217 lui $at,<hiconstant>
7218 addiu $at,$at,<loconstant>
7219 addu $tempreg,$tempreg,$at
7220 For a local symbol, we want the same instruction
7221 sequence, but we output a BFD_RELOC_LO16 reloc on the
7225 if (offset_expr
.X_add_number
== 0)
7227 if (mips_pic
== SVR4_PIC
7229 && (call
|| tempreg
== PIC_CALL_REG
))
7230 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7232 relax_start (offset_expr
.X_add_symbol
);
7233 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7234 lw_reloc_type
, mips_gp_register
);
7237 /* We're going to put in an addu instruction using
7238 tempreg, so we may as well insert the nop right
7243 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7244 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7246 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7247 tempreg
, tempreg
, BFD_RELOC_LO16
);
7249 /* FIXME: If breg == 0, and the next instruction uses
7250 $tempreg, then if this variant case is used an extra
7251 nop will be generated. */
7253 else if (offset_expr
.X_add_number
>= -0x8000
7254 && offset_expr
.X_add_number
< 0x8000)
7256 load_got_offset (tempreg
, &offset_expr
);
7258 add_got_offset (tempreg
, &offset_expr
);
7262 expr1
.X_add_number
= offset_expr
.X_add_number
;
7263 offset_expr
.X_add_number
=
7264 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
7265 load_got_offset (tempreg
, &offset_expr
);
7266 offset_expr
.X_add_number
= expr1
.X_add_number
;
7267 /* If we are going to add in a base register, and the
7268 target register and the base register are the same,
7269 then we are using AT as a temporary register. Since
7270 we want to load the constant into AT, we add our
7271 current AT (from the global offset table) and the
7272 register into the register now, and pretend we were
7273 not using a base register. */
7277 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7282 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7286 else if (!mips_big_got
&& HAVE_NEWABI
)
7288 int add_breg_early
= 0;
7290 /* If this is a reference to an external, and there is no
7291 constant, or local symbol (*), with or without a
7293 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7294 or for lca or if tempreg is PIC_CALL_REG
7295 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7297 If we have a small constant, and this is a reference to
7298 an external symbol, we want
7299 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7300 addiu $tempreg,$tempreg,<constant>
7302 If we have a large constant, and this is a reference to
7303 an external symbol, we want
7304 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7305 lui $at,<hiconstant>
7306 addiu $at,$at,<loconstant>
7307 addu $tempreg,$tempreg,$at
7309 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7310 local symbols, even though it introduces an additional
7313 if (offset_expr
.X_add_number
)
7315 expr1
.X_add_number
= offset_expr
.X_add_number
;
7316 offset_expr
.X_add_number
= 0;
7318 relax_start (offset_expr
.X_add_symbol
);
7319 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7320 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7322 if (expr1
.X_add_number
>= -0x8000
7323 && expr1
.X_add_number
< 0x8000)
7325 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7326 tempreg
, tempreg
, BFD_RELOC_LO16
);
7328 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7330 /* If we are going to add in a base register, and the
7331 target register and the base register are the same,
7332 then we are using AT as a temporary register. Since
7333 we want to load the constant into AT, we add our
7334 current AT (from the global offset table) and the
7335 register into the register now, and pretend we were
7336 not using a base register. */
7341 gas_assert (tempreg
== AT
);
7342 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7348 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7349 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7355 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7358 offset_expr
.X_add_number
= expr1
.X_add_number
;
7360 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7361 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7364 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7365 treg
, tempreg
, breg
);
7371 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7373 relax_start (offset_expr
.X_add_symbol
);
7374 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7375 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7377 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7378 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7383 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7384 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7387 else if (mips_big_got
&& !HAVE_NEWABI
)
7390 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7391 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7392 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7394 /* This is the large GOT case. If this is a reference to an
7395 external symbol, and there is no constant, we want
7396 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7397 addu $tempreg,$tempreg,$gp
7398 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7399 or for lca or if tempreg is PIC_CALL_REG
7400 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7401 addu $tempreg,$tempreg,$gp
7402 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7403 For a local symbol, we want
7404 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7406 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7408 If we have a small constant, and this is a reference to
7409 an external symbol, we want
7410 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7411 addu $tempreg,$tempreg,$gp
7412 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7414 addiu $tempreg,$tempreg,<constant>
7415 For a local symbol, we want
7416 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7418 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7420 If we have a large constant, and this is a reference to
7421 an external symbol, we want
7422 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7423 addu $tempreg,$tempreg,$gp
7424 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7425 lui $at,<hiconstant>
7426 addiu $at,$at,<loconstant>
7427 addu $tempreg,$tempreg,$at
7428 For a local symbol, we want
7429 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7430 lui $at,<hiconstant>
7431 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7432 addu $tempreg,$tempreg,$at
7435 expr1
.X_add_number
= offset_expr
.X_add_number
;
7436 offset_expr
.X_add_number
= 0;
7437 relax_start (offset_expr
.X_add_symbol
);
7438 gpdelay
= reg_needs_delay (mips_gp_register
);
7439 if (expr1
.X_add_number
== 0 && breg
== 0
7440 && (call
|| tempreg
== PIC_CALL_REG
))
7442 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7443 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7445 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7446 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7447 tempreg
, tempreg
, mips_gp_register
);
7448 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7449 tempreg
, lw_reloc_type
, tempreg
);
7450 if (expr1
.X_add_number
== 0)
7454 /* We're going to put in an addu instruction using
7455 tempreg, so we may as well insert the nop right
7460 else if (expr1
.X_add_number
>= -0x8000
7461 && expr1
.X_add_number
< 0x8000)
7464 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7465 tempreg
, tempreg
, BFD_RELOC_LO16
);
7469 /* If we are going to add in a base register, and the
7470 target register and the base register are the same,
7471 then we are using AT as a temporary register. Since
7472 we want to load the constant into AT, we add our
7473 current AT (from the global offset table) and the
7474 register into the register now, and pretend we were
7475 not using a base register. */
7480 gas_assert (tempreg
== AT
);
7482 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7487 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7488 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7492 offset_expr
.X_add_number
=
7493 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
7498 /* This is needed because this instruction uses $gp, but
7499 the first instruction on the main stream does not. */
7500 macro_build (NULL
, "nop", "");
7503 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7504 local_reloc_type
, mips_gp_register
);
7505 if (expr1
.X_add_number
>= -0x8000
7506 && expr1
.X_add_number
< 0x8000)
7509 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7510 tempreg
, tempreg
, BFD_RELOC_LO16
);
7511 /* FIXME: If add_number is 0, and there was no base
7512 register, the external symbol case ended with a load,
7513 so if the symbol turns out to not be external, and
7514 the next instruction uses tempreg, an unnecessary nop
7515 will be inserted. */
7521 /* We must add in the base register now, as in the
7522 external symbol case. */
7523 gas_assert (tempreg
== AT
);
7525 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7528 /* We set breg to 0 because we have arranged to add
7529 it in in both cases. */
7533 macro_build_lui (&expr1
, AT
);
7534 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7535 AT
, AT
, BFD_RELOC_LO16
);
7536 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7537 tempreg
, tempreg
, AT
);
7542 else if (mips_big_got
&& HAVE_NEWABI
)
7544 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7545 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7546 int add_breg_early
= 0;
7548 /* This is the large GOT case. If this is a reference to an
7549 external symbol, and there is no constant, we want
7550 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7551 add $tempreg,$tempreg,$gp
7552 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7553 or for lca or if tempreg is PIC_CALL_REG
7554 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7555 add $tempreg,$tempreg,$gp
7556 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7558 If we have a small constant, and this is a reference to
7559 an external symbol, we want
7560 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7561 add $tempreg,$tempreg,$gp
7562 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7563 addi $tempreg,$tempreg,<constant>
7565 If we have a large constant, and this is a reference to
7566 an external symbol, we want
7567 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7568 addu $tempreg,$tempreg,$gp
7569 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7570 lui $at,<hiconstant>
7571 addi $at,$at,<loconstant>
7572 add $tempreg,$tempreg,$at
7574 If we have NewABI, and we know it's a local symbol, we want
7575 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7576 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7577 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7579 relax_start (offset_expr
.X_add_symbol
);
7581 expr1
.X_add_number
= offset_expr
.X_add_number
;
7582 offset_expr
.X_add_number
= 0;
7584 if (expr1
.X_add_number
== 0 && breg
== 0
7585 && (call
|| tempreg
== PIC_CALL_REG
))
7587 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7588 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7590 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7591 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7592 tempreg
, tempreg
, mips_gp_register
);
7593 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7594 tempreg
, lw_reloc_type
, tempreg
);
7596 if (expr1
.X_add_number
== 0)
7598 else if (expr1
.X_add_number
>= -0x8000
7599 && expr1
.X_add_number
< 0x8000)
7601 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7602 tempreg
, tempreg
, BFD_RELOC_LO16
);
7604 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7606 /* If we are going to add in a base register, and the
7607 target register and the base register are the same,
7608 then we are using AT as a temporary register. Since
7609 we want to load the constant into AT, we add our
7610 current AT (from the global offset table) and the
7611 register into the register now, and pretend we were
7612 not using a base register. */
7617 gas_assert (tempreg
== AT
);
7618 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7624 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7625 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7630 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7633 offset_expr
.X_add_number
= expr1
.X_add_number
;
7634 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7635 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7636 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7637 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7640 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7641 treg
, tempreg
, breg
);
7651 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7655 gas_assert (!mips_opts
.micromips
);
7657 unsigned long temp
= (treg
<< 16) | (0x01);
7658 macro_build (NULL
, "c2", "C", temp
);
7663 gas_assert (!mips_opts
.micromips
);
7665 unsigned long temp
= (0x02);
7666 macro_build (NULL
, "c2", "C", temp
);
7671 gas_assert (!mips_opts
.micromips
);
7673 unsigned long temp
= (treg
<< 16) | (0x02);
7674 macro_build (NULL
, "c2", "C", temp
);
7679 gas_assert (!mips_opts
.micromips
);
7680 macro_build (NULL
, "c2", "C", 3);
7684 gas_assert (!mips_opts
.micromips
);
7686 unsigned long temp
= (treg
<< 16) | 0x03;
7687 macro_build (NULL
, "c2", "C", temp
);
7692 /* The j instruction may not be used in PIC code, since it
7693 requires an absolute address. We convert it to a b
7695 if (mips_pic
== NO_PIC
)
7696 macro_build (&offset_expr
, "j", "a");
7698 macro_build (&offset_expr
, "b", "p");
7701 /* The jal instructions must be handled as macros because when
7702 generating PIC code they expand to multi-instruction
7703 sequences. Normally they are simple instructions. */
7708 gas_assert (mips_opts
.micromips
);
7716 if (mips_pic
== NO_PIC
)
7718 s
= jals
? "jalrs" : "jalr";
7719 if (mips_opts
.micromips
&& dreg
== RA
)
7720 macro_build (NULL
, s
, "mj", sreg
);
7722 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7726 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7727 && mips_cprestore_offset
>= 0);
7729 if (sreg
!= PIC_CALL_REG
)
7730 as_warn (_("MIPS PIC call to register other than $25"));
7732 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7733 ? "jalrs" : "jalr");
7734 if (mips_opts
.micromips
&& dreg
== RA
)
7735 macro_build (NULL
, s
, "mj", sreg
);
7737 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7738 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7740 if (mips_cprestore_offset
< 0)
7741 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7744 if (!mips_frame_reg_valid
)
7746 as_warn (_("No .frame pseudo-op used in PIC code"));
7747 /* Quiet this warning. */
7748 mips_frame_reg_valid
= 1;
7750 if (!mips_cprestore_valid
)
7752 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7753 /* Quiet this warning. */
7754 mips_cprestore_valid
= 1;
7756 if (mips_opts
.noreorder
)
7757 macro_build (NULL
, "nop", "");
7758 expr1
.X_add_number
= mips_cprestore_offset
;
7759 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7762 HAVE_64BIT_ADDRESSES
);
7770 gas_assert (mips_opts
.micromips
);
7774 if (mips_pic
== NO_PIC
)
7775 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7776 else if (mips_pic
== SVR4_PIC
)
7778 /* If this is a reference to an external symbol, and we are
7779 using a small GOT, we want
7780 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7784 lw $gp,cprestore($sp)
7785 The cprestore value is set using the .cprestore
7786 pseudo-op. If we are using a big GOT, we want
7787 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7789 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7793 lw $gp,cprestore($sp)
7794 If the symbol is not external, we want
7795 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7797 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7800 lw $gp,cprestore($sp)
7802 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7803 sequences above, minus nops, unless the symbol is local,
7804 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7810 relax_start (offset_expr
.X_add_symbol
);
7811 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7812 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7815 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7816 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
7822 relax_start (offset_expr
.X_add_symbol
);
7823 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7824 BFD_RELOC_MIPS_CALL_HI16
);
7825 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7826 PIC_CALL_REG
, mips_gp_register
);
7827 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7828 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7831 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7832 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
7834 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7835 PIC_CALL_REG
, PIC_CALL_REG
,
7836 BFD_RELOC_MIPS_GOT_OFST
);
7840 macro_build_jalr (&offset_expr
, 0);
7844 relax_start (offset_expr
.X_add_symbol
);
7847 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7848 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7857 gpdelay
= reg_needs_delay (mips_gp_register
);
7858 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7859 BFD_RELOC_MIPS_CALL_HI16
);
7860 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7861 PIC_CALL_REG
, mips_gp_register
);
7862 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7863 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7868 macro_build (NULL
, "nop", "");
7870 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7871 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
7874 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7875 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
7877 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
7879 if (mips_cprestore_offset
< 0)
7880 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7883 if (!mips_frame_reg_valid
)
7885 as_warn (_("No .frame pseudo-op used in PIC code"));
7886 /* Quiet this warning. */
7887 mips_frame_reg_valid
= 1;
7889 if (!mips_cprestore_valid
)
7891 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7892 /* Quiet this warning. */
7893 mips_cprestore_valid
= 1;
7895 if (mips_opts
.noreorder
)
7896 macro_build (NULL
, "nop", "");
7897 expr1
.X_add_number
= mips_cprestore_offset
;
7898 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7901 HAVE_64BIT_ADDRESSES
);
7905 else if (mips_pic
== VXWORKS_PIC
)
7906 as_bad (_("Non-PIC jump used in PIC library"));
7916 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
7924 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
7955 gas_assert (!mips_opts
.micromips
);
7958 /* Itbl support may require additional care here. */
7965 /* Itbl support may require additional care here. */
7973 off12
= mips_opts
.micromips
;
7974 /* Itbl support may require additional care here. */
7979 gas_assert (!mips_opts
.micromips
);
7982 /* Itbl support may require additional care here. */
7990 off12
= mips_opts
.micromips
;
7997 off12
= mips_opts
.micromips
;
8003 /* Itbl support may require additional care here. */
8011 off12
= mips_opts
.micromips
;
8012 /* Itbl support may require additional care here. */
8019 /* Itbl support may require additional care here. */
8027 off12
= mips_opts
.micromips
;
8034 off12
= mips_opts
.micromips
;
8041 off12
= mips_opts
.micromips
;
8048 off12
= mips_opts
.micromips
;
8055 off12
= mips_opts
.micromips
;
8060 gas_assert (mips_opts
.micromips
);
8069 gas_assert (mips_opts
.micromips
);
8078 gas_assert (mips_opts
.micromips
);
8086 gas_assert (mips_opts
.micromips
);
8093 if (breg
== treg
+ lp
)
8096 tempreg
= treg
+ lp
;
8116 gas_assert (!mips_opts
.micromips
);
8119 /* Itbl support may require additional care here. */
8126 /* Itbl support may require additional care here. */
8134 off12
= mips_opts
.micromips
;
8135 /* Itbl support may require additional care here. */
8140 gas_assert (!mips_opts
.micromips
);
8143 /* Itbl support may require additional care here. */
8151 off12
= mips_opts
.micromips
;
8158 off12
= mips_opts
.micromips
;
8165 off12
= mips_opts
.micromips
;
8172 off12
= mips_opts
.micromips
;
8178 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8179 off12
= mips_opts
.micromips
;
8185 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8186 off12
= mips_opts
.micromips
;
8193 /* Itbl support may require additional care here. */
8200 off12
= mips_opts
.micromips
;
8201 /* Itbl support may require additional care here. */
8206 gas_assert (!mips_opts
.micromips
);
8209 /* Itbl support may require additional care here. */
8217 off12
= mips_opts
.micromips
;
8224 off12
= mips_opts
.micromips
;
8229 gas_assert (mips_opts
.micromips
);
8237 gas_assert (mips_opts
.micromips
);
8245 gas_assert (mips_opts
.micromips
);
8253 gas_assert (mips_opts
.micromips
);
8263 && NO_ISA_COP (mips_opts
.arch
)
8264 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
8266 as_bad (_("Opcode not supported on this processor: %s"),
8267 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
8271 if (offset_expr
.X_op
!= O_constant
8272 && offset_expr
.X_op
!= O_symbol
)
8274 as_bad (_("Expression too complex"));
8275 offset_expr
.X_op
= O_constant
;
8278 if (HAVE_32BIT_ADDRESSES
8279 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8283 sprintf_vma (value
, offset_expr
.X_add_number
);
8284 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8287 /* A constant expression in PIC code can be handled just as it
8288 is in non PIC code. */
8289 if (offset_expr
.X_op
== O_constant
)
8293 expr1
.X_add_number
= offset_expr
.X_add_number
;
8294 normalize_address_expr (&expr1
);
8295 if (!off12
&& !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8297 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8298 & ~(bfd_vma
) 0xffff);
8301 else if (off12
&& !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8303 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8304 & ~(bfd_vma
) 0xfff);
8309 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8311 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8312 tempreg
, tempreg
, breg
);
8317 if (offset_expr
.X_add_number
== 0)
8320 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8321 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8322 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8325 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8327 macro_build (NULL
, s
, fmt
,
8328 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8330 else if (off12
|| off0
)
8332 /* A 12-bit or 0-bit offset field is too narrow to be used
8333 for a low-part relocation, so load the whole address into
8334 the auxillary register. In the case of "A(b)" addresses,
8335 we first load absolute address "A" into the register and
8336 then add base register "b". In the case of "o(b)" addresses,
8337 we simply need to add 16-bit offset "o" to base register "b", and
8338 offset_reloc already contains the relocations associated
8342 load_address (tempreg
, &offset_expr
, &used_at
);
8344 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8345 tempreg
, tempreg
, breg
);
8348 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8350 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8351 expr1
.X_add_number
= 0;
8353 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8355 macro_build (NULL
, s
, fmt
,
8356 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8358 else if (mips_pic
== NO_PIC
)
8360 /* If this is a reference to a GP relative symbol, and there
8361 is no base register, we want
8362 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8363 Otherwise, if there is no base register, we want
8364 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8365 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8366 If we have a constant, we need two instructions anyhow,
8367 so we always use the latter form.
8369 If we have a base register, and this is a reference to a
8370 GP relative symbol, we want
8371 addu $tempreg,$breg,$gp
8372 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8374 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8375 addu $tempreg,$tempreg,$breg
8376 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8377 With a constant we always use the latter case.
8379 With 64bit address space and no base register and $at usable,
8381 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8382 lui $at,<sym> (BFD_RELOC_HI16_S)
8383 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8386 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8387 If we have a base register, we want
8388 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8389 lui $at,<sym> (BFD_RELOC_HI16_S)
8390 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8394 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8396 Without $at we can't generate the optimal path for superscalar
8397 processors here since this would require two temporary registers.
8398 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8399 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8401 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8403 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8404 If we have a base register, we want
8405 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8406 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8408 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8410 daddu $tempreg,$tempreg,$breg
8411 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8413 For GP relative symbols in 64bit address space we can use
8414 the same sequence as in 32bit address space. */
8415 if (HAVE_64BIT_SYMBOLS
)
8417 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8418 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8420 relax_start (offset_expr
.X_add_symbol
);
8423 macro_build (&offset_expr
, s
, fmt
, treg
,
8424 BFD_RELOC_GPREL16
, mips_gp_register
);
8428 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8429 tempreg
, breg
, mips_gp_register
);
8430 macro_build (&offset_expr
, s
, fmt
, treg
,
8431 BFD_RELOC_GPREL16
, tempreg
);
8436 if (used_at
== 0 && mips_opts
.at
)
8438 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8439 BFD_RELOC_MIPS_HIGHEST
);
8440 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8442 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8443 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8445 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8446 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8447 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8448 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8454 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8455 BFD_RELOC_MIPS_HIGHEST
);
8456 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8457 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8458 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8459 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8460 tempreg
, BFD_RELOC_HI16_S
);
8461 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8463 macro_build (NULL
, "daddu", "d,v,t",
8464 tempreg
, tempreg
, breg
);
8465 macro_build (&offset_expr
, s
, fmt
, treg
,
8466 BFD_RELOC_LO16
, tempreg
);
8469 if (mips_relax
.sequence
)
8476 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8477 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8479 relax_start (offset_expr
.X_add_symbol
);
8480 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8484 macro_build_lui (&offset_expr
, tempreg
);
8485 macro_build (&offset_expr
, s
, fmt
, treg
,
8486 BFD_RELOC_LO16
, tempreg
);
8487 if (mips_relax
.sequence
)
8492 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8493 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8495 relax_start (offset_expr
.X_add_symbol
);
8496 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8497 tempreg
, breg
, mips_gp_register
);
8498 macro_build (&offset_expr
, s
, fmt
, treg
,
8499 BFD_RELOC_GPREL16
, tempreg
);
8502 macro_build_lui (&offset_expr
, tempreg
);
8503 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8504 tempreg
, tempreg
, breg
);
8505 macro_build (&offset_expr
, s
, fmt
, treg
,
8506 BFD_RELOC_LO16
, tempreg
);
8507 if (mips_relax
.sequence
)
8511 else if (!mips_big_got
)
8513 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8515 /* If this is a reference to an external symbol, we want
8516 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8518 <op> $treg,0($tempreg)
8520 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8522 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8523 <op> $treg,0($tempreg)
8526 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8527 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8529 If there is a base register, we add it to $tempreg before
8530 the <op>. If there is a constant, we stick it in the
8531 <op> instruction. We don't handle constants larger than
8532 16 bits, because we have no way to load the upper 16 bits
8533 (actually, we could handle them for the subset of cases
8534 in which we are not using $at). */
8535 gas_assert (offset_expr
.X_op
== O_symbol
);
8538 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8539 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8541 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8542 tempreg
, tempreg
, breg
);
8543 macro_build (&offset_expr
, s
, fmt
, treg
,
8544 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8547 expr1
.X_add_number
= offset_expr
.X_add_number
;
8548 offset_expr
.X_add_number
= 0;
8549 if (expr1
.X_add_number
< -0x8000
8550 || expr1
.X_add_number
>= 0x8000)
8551 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8552 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8553 lw_reloc_type
, mips_gp_register
);
8555 relax_start (offset_expr
.X_add_symbol
);
8557 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8558 tempreg
, BFD_RELOC_LO16
);
8561 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8562 tempreg
, tempreg
, breg
);
8563 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8565 else if (mips_big_got
&& !HAVE_NEWABI
)
8569 /* If this is a reference to an external symbol, we want
8570 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8571 addu $tempreg,$tempreg,$gp
8572 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8573 <op> $treg,0($tempreg)
8575 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8577 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8578 <op> $treg,0($tempreg)
8579 If there is a base register, we add it to $tempreg before
8580 the <op>. If there is a constant, we stick it in the
8581 <op> instruction. We don't handle constants larger than
8582 16 bits, because we have no way to load the upper 16 bits
8583 (actually, we could handle them for the subset of cases
8584 in which we are not using $at). */
8585 gas_assert (offset_expr
.X_op
== O_symbol
);
8586 expr1
.X_add_number
= offset_expr
.X_add_number
;
8587 offset_expr
.X_add_number
= 0;
8588 if (expr1
.X_add_number
< -0x8000
8589 || expr1
.X_add_number
>= 0x8000)
8590 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8591 gpdelay
= reg_needs_delay (mips_gp_register
);
8592 relax_start (offset_expr
.X_add_symbol
);
8593 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8594 BFD_RELOC_MIPS_GOT_HI16
);
8595 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8597 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8598 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8601 macro_build (NULL
, "nop", "");
8602 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8603 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8605 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8606 tempreg
, BFD_RELOC_LO16
);
8610 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8611 tempreg
, tempreg
, breg
);
8612 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8614 else if (mips_big_got
&& HAVE_NEWABI
)
8616 /* If this is a reference to an external symbol, we want
8617 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8618 add $tempreg,$tempreg,$gp
8619 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8620 <op> $treg,<ofst>($tempreg)
8621 Otherwise, for local symbols, we want:
8622 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8623 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8624 gas_assert (offset_expr
.X_op
== O_symbol
);
8625 expr1
.X_add_number
= offset_expr
.X_add_number
;
8626 offset_expr
.X_add_number
= 0;
8627 if (expr1
.X_add_number
< -0x8000
8628 || expr1
.X_add_number
>= 0x8000)
8629 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8630 relax_start (offset_expr
.X_add_symbol
);
8631 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8632 BFD_RELOC_MIPS_GOT_HI16
);
8633 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8635 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8636 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8638 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8639 tempreg
, tempreg
, breg
);
8640 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8643 offset_expr
.X_add_number
= expr1
.X_add_number
;
8644 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8645 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8647 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8648 tempreg
, tempreg
, breg
);
8649 macro_build (&offset_expr
, s
, fmt
, treg
,
8650 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8660 load_register (treg
, &imm_expr
, 0);
8664 load_register (treg
, &imm_expr
, 1);
8668 if (imm_expr
.X_op
== O_constant
)
8671 load_register (AT
, &imm_expr
, 0);
8672 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8677 gas_assert (offset_expr
.X_op
== O_symbol
8678 && strcmp (segment_name (S_GET_SEGMENT
8679 (offset_expr
.X_add_symbol
)),
8681 && offset_expr
.X_add_number
== 0);
8682 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
8683 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8688 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8689 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8690 order 32 bits of the value and the low order 32 bits are either
8691 zero or in OFFSET_EXPR. */
8692 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8694 if (HAVE_64BIT_GPRS
)
8695 load_register (treg
, &imm_expr
, 1);
8700 if (target_big_endian
)
8712 load_register (hreg
, &imm_expr
, 0);
8715 if (offset_expr
.X_op
== O_absent
)
8716 move_register (lreg
, 0);
8719 gas_assert (offset_expr
.X_op
== O_constant
);
8720 load_register (lreg
, &offset_expr
, 0);
8727 /* We know that sym is in the .rdata section. First we get the
8728 upper 16 bits of the address. */
8729 if (mips_pic
== NO_PIC
)
8731 macro_build_lui (&offset_expr
, AT
);
8736 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8737 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8741 /* Now we load the register(s). */
8742 if (HAVE_64BIT_GPRS
)
8745 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8750 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8753 /* FIXME: How in the world do we deal with the possible
8755 offset_expr
.X_add_number
+= 4;
8756 macro_build (&offset_expr
, "lw", "t,o(b)",
8757 treg
+ 1, BFD_RELOC_LO16
, AT
);
8763 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8764 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8765 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8766 the value and the low order 32 bits are either zero or in
8768 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8771 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
8772 if (HAVE_64BIT_FPRS
)
8774 gas_assert (HAVE_64BIT_GPRS
);
8775 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
8779 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
8780 if (offset_expr
.X_op
== O_absent
)
8781 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
8784 gas_assert (offset_expr
.X_op
== O_constant
);
8785 load_register (AT
, &offset_expr
, 0);
8786 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8792 gas_assert (offset_expr
.X_op
== O_symbol
8793 && offset_expr
.X_add_number
== 0);
8794 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
8795 if (strcmp (s
, ".lit8") == 0)
8797 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8799 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
8800 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8803 breg
= mips_gp_register
;
8804 r
= BFD_RELOC_MIPS_LITERAL
;
8809 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
8811 if (mips_pic
!= NO_PIC
)
8812 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8813 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8816 /* FIXME: This won't work for a 64 bit address. */
8817 macro_build_lui (&offset_expr
, AT
);
8820 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8822 macro_build (&offset_expr
, "ldc1", "T,o(b)",
8823 treg
, BFD_RELOC_LO16
, AT
);
8832 /* Even on a big endian machine $fn comes before $fn+1. We have
8833 to adjust when loading from memory. */
8836 gas_assert (!mips_opts
.micromips
);
8837 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8838 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8839 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
8840 /* FIXME: A possible overflow which I don't know how to deal
8842 offset_expr
.X_add_number
+= 4;
8843 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8844 target_big_endian
? treg
: treg
+ 1, r
, breg
);
8848 gas_assert (!mips_opts
.micromips
);
8849 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8850 /* Even on a big endian machine $fn comes before $fn+1. We have
8851 to adjust when storing to memory. */
8852 macro_build (&offset_expr
, "swc1", "T,o(b)",
8853 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
8854 offset_expr
.X_add_number
+= 4;
8855 macro_build (&offset_expr
, "swc1", "T,o(b)",
8856 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
8860 gas_assert (!mips_opts
.micromips
);
8862 * The MIPS assembler seems to check for X_add_number not
8863 * being double aligned and generating:
8866 * addiu at,at,%lo(foo+1)
8869 * But, the resulting address is the same after relocation so why
8870 * generate the extra instruction?
8872 /* Itbl support may require additional care here. */
8875 if (mips_opts
.isa
!= ISA_MIPS1
)
8884 gas_assert (!mips_opts
.micromips
);
8885 /* Itbl support may require additional care here. */
8888 if (mips_opts
.isa
!= ISA_MIPS1
)
8898 if (HAVE_64BIT_GPRS
)
8908 if (HAVE_64BIT_GPRS
)
8916 if (offset_expr
.X_op
!= O_symbol
8917 && offset_expr
.X_op
!= O_constant
)
8919 as_bad (_("Expression too complex"));
8920 offset_expr
.X_op
= O_constant
;
8923 if (HAVE_32BIT_ADDRESSES
8924 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8928 sprintf_vma (value
, offset_expr
.X_add_number
);
8929 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8932 /* Even on a big endian machine $fn comes before $fn+1. We have
8933 to adjust when loading from memory. We set coproc if we must
8934 load $fn+1 first. */
8935 /* Itbl support may require additional care here. */
8936 if (!target_big_endian
)
8939 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
8941 /* If this is a reference to a GP relative symbol, we want
8942 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8943 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8944 If we have a base register, we use this
8946 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8947 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8948 If this is not a GP relative symbol, we want
8949 lui $at,<sym> (BFD_RELOC_HI16_S)
8950 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8951 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8952 If there is a base register, we add it to $at after the
8953 lui instruction. If there is a constant, we always use
8955 if (offset_expr
.X_op
== O_symbol
8956 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8957 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8959 relax_start (offset_expr
.X_add_symbol
);
8962 tempreg
= mips_gp_register
;
8966 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8967 AT
, breg
, mips_gp_register
);
8972 /* Itbl support may require additional care here. */
8973 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
8974 BFD_RELOC_GPREL16
, tempreg
);
8975 offset_expr
.X_add_number
+= 4;
8977 /* Set mips_optimize to 2 to avoid inserting an
8979 hold_mips_optimize
= mips_optimize
;
8981 /* Itbl support may require additional care here. */
8982 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
8983 BFD_RELOC_GPREL16
, tempreg
);
8984 mips_optimize
= hold_mips_optimize
;
8988 offset_expr
.X_add_number
-= 4;
8991 macro_build_lui (&offset_expr
, AT
);
8993 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
8994 /* Itbl support may require additional care here. */
8995 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
8996 BFD_RELOC_LO16
, AT
);
8997 /* FIXME: How do we handle overflow here? */
8998 offset_expr
.X_add_number
+= 4;
8999 /* Itbl support may require additional care here. */
9000 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9001 BFD_RELOC_LO16
, AT
);
9002 if (mips_relax
.sequence
)
9005 else if (!mips_big_got
)
9007 /* If this is a reference to an external symbol, we want
9008 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9013 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9015 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9016 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9017 If there is a base register we add it to $at before the
9018 lwc1 instructions. If there is a constant we include it
9019 in the lwc1 instructions. */
9021 expr1
.X_add_number
= offset_expr
.X_add_number
;
9022 if (expr1
.X_add_number
< -0x8000
9023 || expr1
.X_add_number
>= 0x8000 - 4)
9024 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9025 load_got_offset (AT
, &offset_expr
);
9028 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9030 /* Set mips_optimize to 2 to avoid inserting an undesired
9032 hold_mips_optimize
= mips_optimize
;
9035 /* Itbl support may require additional care here. */
9036 relax_start (offset_expr
.X_add_symbol
);
9037 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9038 BFD_RELOC_LO16
, AT
);
9039 expr1
.X_add_number
+= 4;
9040 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9041 BFD_RELOC_LO16
, AT
);
9043 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9044 BFD_RELOC_LO16
, AT
);
9045 offset_expr
.X_add_number
+= 4;
9046 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9047 BFD_RELOC_LO16
, AT
);
9050 mips_optimize
= hold_mips_optimize
;
9052 else if (mips_big_got
)
9056 /* If this is a reference to an external symbol, we want
9057 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9059 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9064 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9066 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9067 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9068 If there is a base register we add it to $at before the
9069 lwc1 instructions. If there is a constant we include it
9070 in the lwc1 instructions. */
9072 expr1
.X_add_number
= offset_expr
.X_add_number
;
9073 offset_expr
.X_add_number
= 0;
9074 if (expr1
.X_add_number
< -0x8000
9075 || expr1
.X_add_number
>= 0x8000 - 4)
9076 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9077 gpdelay
= reg_needs_delay (mips_gp_register
);
9078 relax_start (offset_expr
.X_add_symbol
);
9079 macro_build (&offset_expr
, "lui", LUI_FMT
,
9080 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9081 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9082 AT
, AT
, mips_gp_register
);
9083 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9084 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9087 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9088 /* Itbl support may require additional care here. */
9089 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9090 BFD_RELOC_LO16
, AT
);
9091 expr1
.X_add_number
+= 4;
9093 /* Set mips_optimize to 2 to avoid inserting an undesired
9095 hold_mips_optimize
= mips_optimize
;
9097 /* Itbl support may require additional care here. */
9098 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9099 BFD_RELOC_LO16
, AT
);
9100 mips_optimize
= hold_mips_optimize
;
9101 expr1
.X_add_number
-= 4;
9104 offset_expr
.X_add_number
= expr1
.X_add_number
;
9106 macro_build (NULL
, "nop", "");
9107 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9108 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9111 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9112 /* Itbl support may require additional care here. */
9113 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9114 BFD_RELOC_LO16
, AT
);
9115 offset_expr
.X_add_number
+= 4;
9117 /* Set mips_optimize to 2 to avoid inserting an undesired
9119 hold_mips_optimize
= mips_optimize
;
9121 /* Itbl support may require additional care here. */
9122 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9123 BFD_RELOC_LO16
, AT
);
9124 mips_optimize
= hold_mips_optimize
;
9133 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9136 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9138 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9139 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9141 if (!HAVE_64BIT_GPRS
)
9143 offset_expr
.X_add_number
+= 4;
9144 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9145 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9166 /* New code added to support COPZ instructions.
9167 This code builds table entries out of the macros in mip_opcodes.
9168 R4000 uses interlocks to handle coproc delays.
9169 Other chips (like the R3000) require nops to be inserted for delays.
9171 FIXME: Currently, we require that the user handle delays.
9172 In order to fill delay slots for non-interlocked chips,
9173 we must have a way to specify delays based on the coprocessor.
9174 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9175 What are the side-effects of the cop instruction?
9176 What cache support might we have and what are its effects?
9177 Both coprocessor & memory require delays. how long???
9178 What registers are read/set/modified?
9180 If an itbl is provided to interpret cop instructions,
9181 this knowledge can be encoded in the itbl spec. */
9195 gas_assert (!mips_opts
.micromips
);
9196 if (NO_ISA_COP (mips_opts
.arch
)
9197 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
9199 as_bad (_("Opcode not supported on this processor: %s"),
9200 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
9204 /* For now we just do C (same as Cz). The parameter will be
9205 stored in insn_opcode by mips_ip. */
9206 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9210 move_register (dreg
, sreg
);
9216 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9217 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9223 /* The MIPS assembler some times generates shifts and adds. I'm
9224 not trying to be that fancy. GCC should do this for us
9227 load_register (AT
, &imm_expr
, dbl
);
9228 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9229 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9245 load_register (AT
, &imm_expr
, dbl
);
9246 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9247 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9248 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9249 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9251 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9254 if (mips_opts
.micromips
)
9255 micromips_label_expr (&label_expr
);
9257 label_expr
.X_add_number
= 8;
9258 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9259 macro_build (NULL
, "nop", "");
9260 macro_build (NULL
, "break", BRK_FMT
, 6);
9261 if (mips_opts
.micromips
)
9262 micromips_add_label ();
9265 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9281 load_register (AT
, &imm_expr
, dbl
);
9282 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9283 sreg
, imm
? AT
: treg
);
9284 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9285 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9287 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9290 if (mips_opts
.micromips
)
9291 micromips_label_expr (&label_expr
);
9293 label_expr
.X_add_number
= 8;
9294 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9295 macro_build (NULL
, "nop", "");
9296 macro_build (NULL
, "break", BRK_FMT
, 6);
9297 if (mips_opts
.micromips
)
9298 micromips_add_label ();
9304 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9315 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9316 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9320 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9321 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9322 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9323 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9327 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9338 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9339 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9343 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9344 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9345 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9346 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9355 if (imm_expr
.X_op
!= O_constant
)
9356 as_bad (_("Improper rotate count"));
9357 rot
= imm_expr
.X_add_number
& 0x3f;
9358 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9360 rot
= (64 - rot
) & 0x3f;
9362 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9364 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9369 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9372 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9373 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9376 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9377 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9378 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9386 if (imm_expr
.X_op
!= O_constant
)
9387 as_bad (_("Improper rotate count"));
9388 rot
= imm_expr
.X_add_number
& 0x1f;
9389 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9391 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9396 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9400 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9401 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9402 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9407 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9409 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9413 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9414 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9415 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9416 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9420 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9422 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9426 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9427 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9428 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9429 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9438 if (imm_expr
.X_op
!= O_constant
)
9439 as_bad (_("Improper rotate count"));
9440 rot
= imm_expr
.X_add_number
& 0x3f;
9441 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9444 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9446 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9451 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9454 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9455 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9458 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9459 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9460 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9468 if (imm_expr
.X_op
!= O_constant
)
9469 as_bad (_("Improper rotate count"));
9470 rot
= imm_expr
.X_add_number
& 0x1f;
9471 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9473 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9478 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9482 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9483 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9484 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9490 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9492 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9495 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9496 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9501 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9503 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9508 as_warn (_("Instruction %s: result is always false"),
9510 move_register (dreg
, 0);
9513 if (CPU_HAS_SEQ (mips_opts
.arch
)
9514 && -512 <= imm_expr
.X_add_number
9515 && imm_expr
.X_add_number
< 512)
9517 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9518 (int) imm_expr
.X_add_number
);
9521 if (imm_expr
.X_op
== O_constant
9522 && imm_expr
.X_add_number
>= 0
9523 && imm_expr
.X_add_number
< 0x10000)
9525 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9527 else if (imm_expr
.X_op
== O_constant
9528 && imm_expr
.X_add_number
> -0x8000
9529 && imm_expr
.X_add_number
< 0)
9531 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9532 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9533 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9535 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9538 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9539 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9544 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9545 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9548 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9551 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9557 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9558 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9561 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9563 if (imm_expr
.X_op
== O_constant
9564 && imm_expr
.X_add_number
>= -0x8000
9565 && imm_expr
.X_add_number
< 0x8000)
9567 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9568 dreg
, sreg
, BFD_RELOC_LO16
);
9572 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9573 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9577 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9580 case M_SGT
: /* sreg > treg <==> treg < sreg */
9586 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9589 case M_SGT_I
: /* sreg > I <==> I < sreg */
9596 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9597 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9600 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9606 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9607 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9610 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9617 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9618 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9619 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9623 if (imm_expr
.X_op
== O_constant
9624 && imm_expr
.X_add_number
>= -0x8000
9625 && imm_expr
.X_add_number
< 0x8000)
9627 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9631 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9632 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9636 if (imm_expr
.X_op
== O_constant
9637 && imm_expr
.X_add_number
>= -0x8000
9638 && imm_expr
.X_add_number
< 0x8000)
9640 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9645 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9646 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9651 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9653 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9656 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9657 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9662 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9664 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9669 as_warn (_("Instruction %s: result is always true"),
9671 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
9672 dreg
, 0, BFD_RELOC_LO16
);
9675 if (CPU_HAS_SEQ (mips_opts
.arch
)
9676 && -512 <= imm_expr
.X_add_number
9677 && imm_expr
.X_add_number
< 512)
9679 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
9680 (int) imm_expr
.X_add_number
);
9683 if (imm_expr
.X_op
== O_constant
9684 && imm_expr
.X_add_number
>= 0
9685 && imm_expr
.X_add_number
< 0x10000)
9687 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9689 else if (imm_expr
.X_op
== O_constant
9690 && imm_expr
.X_add_number
> -0x8000
9691 && imm_expr
.X_add_number
< 0)
9693 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9694 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9695 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9697 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9700 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9701 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
9706 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9707 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9710 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9725 if (!mips_opts
.micromips
)
9727 if (imm_expr
.X_op
== O_constant
9728 && imm_expr
.X_add_number
> -0x200
9729 && imm_expr
.X_add_number
<= 0x200)
9731 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
9740 if (imm_expr
.X_op
== O_constant
9741 && imm_expr
.X_add_number
> -0x8000
9742 && imm_expr
.X_add_number
<= 0x8000)
9744 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9745 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9750 load_register (AT
, &imm_expr
, dbl
);
9751 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
9773 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9774 macro_build (NULL
, s
, "s,t", sreg
, AT
);
9779 gas_assert (!mips_opts
.micromips
);
9780 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
9782 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
9783 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
9786 * Is the double cfc1 instruction a bug in the mips assembler;
9787 * or is there a reason for it?
9790 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9791 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9792 macro_build (NULL
, "nop", "");
9793 expr1
.X_add_number
= 3;
9794 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
9795 expr1
.X_add_number
= 2;
9796 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
9797 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
9798 macro_build (NULL
, "nop", "");
9799 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
9801 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
9802 macro_build (NULL
, "nop", "");
9825 off12
= mips_opts
.micromips
;
9833 off12
= mips_opts
.micromips
;
9849 off12
= mips_opts
.micromips
;
9858 off12
= mips_opts
.micromips
;
9863 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
9864 as_bad (_("Operand overflow"));
9867 expr1
.X_add_number
= 0;
9872 load_address (tempreg
, ep
, &used_at
);
9874 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9875 tempreg
, tempreg
, breg
);
9881 && (offset_expr
.X_op
!= O_constant
9882 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
9883 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
9887 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
9888 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9893 else if (!ust
&& treg
== breg
)
9904 if (!target_big_endian
)
9905 ep
->X_add_number
+= off
;
9907 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9909 macro_build (NULL
, s
, "t,~(b)",
9910 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9912 if (!target_big_endian
)
9913 ep
->X_add_number
-= off
;
9915 ep
->X_add_number
+= off
;
9917 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9919 macro_build (NULL
, s2
, "t,~(b)",
9920 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9922 /* If necessary, move the result in tempreg to the final destination. */
9923 if (!ust
&& treg
!= tempreg
)
9925 /* Protect second load's delay slot. */
9927 move_register (treg
, tempreg
);
9933 if (target_big_endian
== ust
)
9934 ep
->X_add_number
+= off
;
9935 tempreg
= ust
|| ab
? treg
: AT
;
9936 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9938 /* For halfword transfers we need a temporary register to shuffle
9939 bytes. Unfortunately for M_USH_A we have none available before
9940 the next store as AT holds the base address. We deal with this
9941 case by clobbering TREG and then restoring it as with ULH. */
9942 tempreg
= ust
== ab
? treg
: AT
;
9944 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
9946 if (target_big_endian
== ust
)
9947 ep
->X_add_number
-= off
;
9949 ep
->X_add_number
+= off
;
9950 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9952 /* For M_USH_A re-retrieve the LSB. */
9955 if (target_big_endian
)
9956 ep
->X_add_number
+= off
;
9958 ep
->X_add_number
-= off
;
9959 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
9961 /* For ULH and M_USH_A OR the LSB in. */
9964 tempreg
= !ab
? AT
: treg
;
9965 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
9966 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
9971 /* FIXME: Check if this is one of the itbl macros, since they
9972 are added dynamically. */
9973 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
9976 if (!mips_opts
.at
&& used_at
)
9977 as_bad (_("Macro used $at after \".set noat\""));
9980 /* Implement macros in mips16 mode. */
9983 mips16_macro (struct mips_cl_insn
*ip
)
9986 int xreg
, yreg
, zreg
, tmp
;
9989 const char *s
, *s2
, *s3
;
9991 mask
= ip
->insn_mo
->mask
;
9993 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
9994 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
9995 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
9997 expr1
.X_op
= O_constant
;
9998 expr1
.X_op_symbol
= NULL
;
9999 expr1
.X_add_symbol
= NULL
;
10000 expr1
.X_add_number
= 1;
10019 start_noreorder ();
10020 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10021 expr1
.X_add_number
= 2;
10022 macro_build (&expr1
, "bnez", "x,p", yreg
);
10023 macro_build (NULL
, "break", "6", 7);
10025 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10026 since that causes an overflow. We should do that as well,
10027 but I don't see how to do the comparisons without a temporary
10030 macro_build (NULL
, s
, "x", zreg
);
10049 start_noreorder ();
10050 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10051 expr1
.X_add_number
= 2;
10052 macro_build (&expr1
, "bnez", "x,p", yreg
);
10053 macro_build (NULL
, "break", "6", 7);
10055 macro_build (NULL
, s2
, "x", zreg
);
10061 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10062 macro_build (NULL
, "mflo", "x", zreg
);
10070 if (imm_expr
.X_op
!= O_constant
)
10071 as_bad (_("Unsupported large constant"));
10072 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10073 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10077 if (imm_expr
.X_op
!= O_constant
)
10078 as_bad (_("Unsupported large constant"));
10079 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10080 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10084 if (imm_expr
.X_op
!= O_constant
)
10085 as_bad (_("Unsupported large constant"));
10086 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10087 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10109 goto do_reverse_branch
;
10113 goto do_reverse_branch
;
10125 goto do_reverse_branch
;
10136 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10137 macro_build (&offset_expr
, s2
, "p");
10164 goto do_addone_branch_i
;
10169 goto do_addone_branch_i
;
10184 goto do_addone_branch_i
;
10190 do_addone_branch_i
:
10191 if (imm_expr
.X_op
!= O_constant
)
10192 as_bad (_("Unsupported large constant"));
10193 ++imm_expr
.X_add_number
;
10196 macro_build (&imm_expr
, s
, s3
, xreg
);
10197 macro_build (&offset_expr
, s2
, "p");
10201 expr1
.X_add_number
= 0;
10202 macro_build (&expr1
, "slti", "x,8", yreg
);
10204 move_register (xreg
, yreg
);
10205 expr1
.X_add_number
= 2;
10206 macro_build (&expr1
, "bteqz", "p");
10207 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10211 /* For consistency checking, verify that all bits are specified either
10212 by the match/mask part of the instruction definition, or by the
10215 validate_mips_insn (const struct mips_opcode
*opc
)
10217 const char *p
= opc
->args
;
10219 unsigned long used_bits
= opc
->mask
;
10221 if ((used_bits
& opc
->match
) != opc
->match
)
10223 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10224 opc
->name
, opc
->args
);
10227 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10237 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10238 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10239 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10240 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10241 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10242 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10243 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10244 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10245 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10246 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10247 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10248 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10249 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10251 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10252 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10253 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10254 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10255 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10256 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10257 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10258 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10259 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10260 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10261 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10262 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10263 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10264 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10265 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10268 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10269 c
, opc
->name
, opc
->args
);
10273 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10274 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10276 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10277 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10278 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10279 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10281 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10282 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10284 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10285 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10287 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10288 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10289 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10290 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10291 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10292 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10293 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10294 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10295 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10296 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10297 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10298 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10299 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10300 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10301 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10302 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10303 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10305 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10306 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10307 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10308 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10310 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10311 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10312 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10313 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10314 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10315 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10316 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10317 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10318 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10321 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10322 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10323 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10324 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10325 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10328 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10329 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10330 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10331 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10332 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10333 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10334 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10335 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10336 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10337 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10338 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10339 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10340 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10341 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10342 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10343 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10344 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10345 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10346 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10347 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10349 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10350 c
, opc
->name
, opc
->args
);
10354 if (used_bits
!= 0xffffffff)
10356 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10357 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10363 /* For consistency checking, verify that the length implied matches the
10364 major opcode and that all bits are specified either by the match/mask
10365 part of the instruction definition, or by the operand list. */
10368 validate_micromips_insn (const struct mips_opcode
*opc
)
10370 unsigned long match
= opc
->match
;
10371 unsigned long mask
= opc
->mask
;
10372 const char *p
= opc
->args
;
10373 unsigned long insn_bits
;
10374 unsigned long used_bits
;
10375 unsigned long major
;
10376 unsigned int length
;
10380 if ((mask
& match
) != match
)
10382 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10383 opc
->name
, opc
->args
);
10386 length
= micromips_insn_length (opc
);
10387 if (length
!= 2 && length
!= 4)
10389 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10390 "%s %s"), length
, opc
->name
, opc
->args
);
10393 major
= match
>> (10 + 8 * (length
- 2));
10394 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10395 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10397 as_bad (_("Internal error: bad microMIPS opcode "
10398 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10402 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10403 insn_bits
= 1 << 4 * length
;
10404 insn_bits
<<= 4 * length
;
10407 #define USE_BITS(field) \
10408 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10419 case 'A': USE_BITS (EXTLSB
); break;
10420 case 'B': USE_BITS (INSMSB
); break;
10421 case 'C': USE_BITS (EXTMSBD
); break;
10422 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10423 case 'E': USE_BITS (EXTLSB
); break;
10424 case 'F': USE_BITS (INSMSB
); break;
10425 case 'G': USE_BITS (EXTMSBD
); break;
10426 case 'H': USE_BITS (EXTMSBD
); break;
10428 as_bad (_("Internal error: bad mips opcode "
10429 "(unknown extension operand type `%c%c'): %s %s"),
10430 e
, c
, opc
->name
, opc
->args
);
10438 case 'A': USE_BITS (IMMA
); break;
10439 case 'B': USE_BITS (IMMB
); break;
10440 case 'C': USE_BITS (IMMC
); break;
10441 case 'D': USE_BITS (IMMD
); break;
10442 case 'E': USE_BITS (IMME
); break;
10443 case 'F': USE_BITS (IMMF
); break;
10444 case 'G': USE_BITS (IMMG
); break;
10445 case 'H': USE_BITS (IMMH
); break;
10446 case 'I': USE_BITS (IMMI
); break;
10447 case 'J': USE_BITS (IMMJ
); break;
10448 case 'L': USE_BITS (IMML
); break;
10449 case 'M': USE_BITS (IMMM
); break;
10450 case 'N': USE_BITS (IMMN
); break;
10451 case 'O': USE_BITS (IMMO
); break;
10452 case 'P': USE_BITS (IMMP
); break;
10453 case 'Q': USE_BITS (IMMQ
); break;
10454 case 'U': USE_BITS (IMMU
); break;
10455 case 'W': USE_BITS (IMMW
); break;
10456 case 'X': USE_BITS (IMMX
); break;
10457 case 'Y': USE_BITS (IMMY
); break;
10460 case 'b': USE_BITS (MB
); break;
10461 case 'c': USE_BITS (MC
); break;
10462 case 'd': USE_BITS (MD
); break;
10463 case 'e': USE_BITS (ME
); break;
10464 case 'f': USE_BITS (MF
); break;
10465 case 'g': USE_BITS (MG
); break;
10466 case 'h': USE_BITS (MH
); break;
10467 case 'i': USE_BITS (MI
); break;
10468 case 'j': USE_BITS (MJ
); break;
10469 case 'l': USE_BITS (ML
); break;
10470 case 'm': USE_BITS (MM
); break;
10471 case 'n': USE_BITS (MN
); break;
10472 case 'p': USE_BITS (MP
); break;
10473 case 'q': USE_BITS (MQ
); break;
10481 as_bad (_("Internal error: bad mips opcode "
10482 "(unknown extension operand type `%c%c'): %s %s"),
10483 e
, c
, opc
->name
, opc
->args
);
10487 case '.': USE_BITS (OFFSET10
); break;
10488 case '1': USE_BITS (STYPE
); break;
10489 case '<': USE_BITS (SHAMT
); break;
10490 case '>': USE_BITS (SHAMT
); break;
10491 case 'B': USE_BITS (CODE10
); break;
10492 case 'C': USE_BITS (COPZ
); break;
10493 case 'D': USE_BITS (FD
); break;
10494 case 'E': USE_BITS (RT
); break;
10495 case 'G': USE_BITS (RS
); break;
10496 case 'H': USE_BITS (SEL
); break;
10497 case 'K': USE_BITS (RS
); break;
10498 case 'M': USE_BITS (CCC
); break;
10499 case 'N': USE_BITS (BCC
); break;
10500 case 'R': USE_BITS (FR
); break;
10501 case 'S': USE_BITS (FS
); break;
10502 case 'T': USE_BITS (FT
); break;
10503 case 'V': USE_BITS (FS
); break;
10504 case '\\': USE_BITS (3BITPOS
); break;
10505 case 'a': USE_BITS (TARGET
); break;
10506 case 'b': USE_BITS (RS
); break;
10507 case 'c': USE_BITS (CODE
); break;
10508 case 'd': USE_BITS (RD
); break;
10509 case 'h': USE_BITS (PREFX
); break;
10510 case 'i': USE_BITS (IMMEDIATE
); break;
10511 case 'j': USE_BITS (DELTA
); break;
10512 case 'k': USE_BITS (CACHE
); break;
10513 case 'n': USE_BITS (RT
); break;
10514 case 'o': USE_BITS (DELTA
); break;
10515 case 'p': USE_BITS (DELTA
); break;
10516 case 'q': USE_BITS (CODE2
); break;
10517 case 'r': USE_BITS (RS
); break;
10518 case 's': USE_BITS (RS
); break;
10519 case 't': USE_BITS (RT
); break;
10520 case 'u': USE_BITS (IMMEDIATE
); break;
10521 case 'v': USE_BITS (RS
); break;
10522 case 'w': USE_BITS (RT
); break;
10523 case 'y': USE_BITS (RS3
); break;
10525 case '|': USE_BITS (TRAP
); break;
10526 case '~': USE_BITS (OFFSET12
); break;
10528 as_bad (_("Internal error: bad microMIPS opcode "
10529 "(unknown operand type `%c'): %s %s"),
10530 c
, opc
->name
, opc
->args
);
10534 if (used_bits
!= insn_bits
)
10536 if (~used_bits
& insn_bits
)
10537 as_bad (_("Internal error: bad microMIPS opcode "
10538 "(bits 0x%lx undefined): %s %s"),
10539 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10540 if (used_bits
& ~insn_bits
)
10541 as_bad (_("Internal error: bad microMIPS opcode "
10542 "(bits 0x%lx defined): %s %s"),
10543 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10549 /* UDI immediates. */
10550 struct mips_immed
{
10552 unsigned int shift
;
10553 unsigned long mask
;
10557 static const struct mips_immed mips_immed
[] = {
10558 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10559 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10560 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10561 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10565 /* Check whether an odd floating-point register is allowed. */
10567 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10569 const char *s
= insn
->name
;
10571 if (insn
->pinfo
== INSN_MACRO
)
10572 /* Let a macro pass, we'll catch it later when it is expanded. */
10575 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
10577 /* Allow odd registers for single-precision ops. */
10578 switch (insn
->pinfo
& (FP_S
| FP_D
))
10582 return 1; /* both single precision - ok */
10584 return 0; /* both double precision - fail */
10589 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10590 s
= strchr (insn
->name
, '.');
10592 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10593 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10596 /* Single-precision coprocessor loads and moves are OK too. */
10597 if ((insn
->pinfo
& FP_S
)
10598 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10599 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10605 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10606 taking bits from BIT up. */
10608 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10610 return (ep
->X_op
== O_constant
10611 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10612 && ep
->X_add_number
>= min
<< bit
10613 && ep
->X_add_number
< max
<< bit
);
10616 /* This routine assembles an instruction into its binary format. As a
10617 side effect, it sets one of the global variables imm_reloc or
10618 offset_reloc to the type of relocation to do if one of the operands
10619 is an address expression. */
10622 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10624 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10625 bfd_boolean need_delay_slot_ok
= TRUE
;
10626 struct mips_opcode
*firstinsn
= NULL
;
10627 const struct mips_opcode
*past
;
10628 struct hash_control
*hash
;
10632 struct mips_opcode
*insn
;
10634 unsigned int regno
;
10635 unsigned int lastregno
;
10636 unsigned int destregno
= 0;
10637 unsigned int lastpos
= 0;
10638 unsigned int limlo
, limhi
;
10640 offsetT min_range
, max_range
;
10644 unsigned int rtype
;
10650 if (mips_opts
.micromips
)
10652 hash
= micromips_op_hash
;
10653 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10658 past
= &mips_opcodes
[NUMOPCODES
];
10660 forced_insn_length
= 0;
10663 /* We first try to match an instruction up to a space or to the end. */
10664 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10667 /* Make a copy of the instruction so that we can fiddle with it. */
10668 name
= alloca (end
+ 1);
10669 memcpy (name
, str
, end
);
10674 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10676 if (insn
!= NULL
|| !mips_opts
.micromips
)
10678 if (forced_insn_length
)
10681 /* See if there's an instruction size override suffix,
10682 either `16' or `32', at the end of the mnemonic proper,
10683 that defines the operation, i.e. before the first `.'
10684 character if any. Strip it and retry. */
10685 dot
= strchr (name
, '.');
10686 opend
= dot
!= NULL
? dot
- name
: end
;
10689 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10690 forced_insn_length
= 2;
10691 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
10692 forced_insn_length
= 4;
10695 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
10699 insn_error
= _("Unrecognized opcode");
10703 /* For microMIPS instructions placed in a fixed-length branch delay slot
10704 we make up to two passes over the relevant fragment of the opcode
10705 table. First we try instructions that meet the delay slot's length
10706 requirement. If none matched, then we retry with the remaining ones
10707 and if one matches, then we use it and then issue an appropriate
10708 warning later on. */
10709 argsStart
= s
= str
+ end
;
10712 bfd_boolean delay_slot_ok
;
10713 bfd_boolean size_ok
;
10716 gas_assert (strcmp (insn
->name
, name
) == 0);
10718 ok
= is_opcode_valid (insn
);
10719 size_ok
= is_size_valid (insn
);
10720 delay_slot_ok
= is_delay_slot_valid (insn
);
10721 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
10724 wrong_delay_slot_insns
= TRUE
;
10726 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
10728 static char buf
[256];
10730 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
10735 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
10737 gas_assert (firstinsn
);
10738 need_delay_slot_ok
= FALSE
;
10748 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
10749 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10750 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10752 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
10753 8 * forced_insn_length
);
10759 create_insn (ip
, insn
);
10762 lastregno
= 0xffffffff;
10763 for (args
= insn
->args
;; ++args
)
10767 s
+= strspn (s
, " \t");
10771 case '\0': /* end of args */
10776 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
10777 gas_assert (!mips_opts
.micromips
);
10778 my_getExpression (&imm_expr
, s
);
10779 check_absolute_expr (ip
, &imm_expr
);
10780 if ((unsigned long) imm_expr
.X_add_number
!= 1
10781 && (unsigned long) imm_expr
.X_add_number
!= 3)
10783 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10784 (unsigned long) imm_expr
.X_add_number
);
10786 INSERT_OPERAND (0, BP
, *ip
, imm_expr
.X_add_number
);
10787 imm_expr
.X_op
= O_absent
;
10791 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
10792 gas_assert (!mips_opts
.micromips
);
10793 my_getExpression (&imm_expr
, s
);
10794 check_absolute_expr (ip
, &imm_expr
);
10795 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
10797 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10798 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
10800 INSERT_OPERAND (0, SA3
, *ip
, imm_expr
.X_add_number
);
10801 imm_expr
.X_op
= O_absent
;
10805 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
10806 gas_assert (!mips_opts
.micromips
);
10807 my_getExpression (&imm_expr
, s
);
10808 check_absolute_expr (ip
, &imm_expr
);
10809 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
10811 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10812 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
10814 INSERT_OPERAND (0, SA4
, *ip
, imm_expr
.X_add_number
);
10815 imm_expr
.X_op
= O_absent
;
10819 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
10820 gas_assert (!mips_opts
.micromips
);
10821 my_getExpression (&imm_expr
, s
);
10822 check_absolute_expr (ip
, &imm_expr
);
10823 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
10825 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10826 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
10828 INSERT_OPERAND (0, IMM8
, *ip
, imm_expr
.X_add_number
);
10829 imm_expr
.X_op
= O_absent
;
10833 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
10834 gas_assert (!mips_opts
.micromips
);
10835 my_getExpression (&imm_expr
, s
);
10836 check_absolute_expr (ip
, &imm_expr
);
10837 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
10839 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10840 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
10842 INSERT_OPERAND (0, RS
, *ip
, imm_expr
.X_add_number
);
10843 imm_expr
.X_op
= O_absent
;
10847 case '7': /* Four DSP accumulators in bits 11,12. */
10848 gas_assert (!mips_opts
.micromips
);
10849 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
10850 s
[3] >= '0' && s
[3] <= '3')
10852 regno
= s
[3] - '0';
10854 INSERT_OPERAND (0, DSPACC
, *ip
, regno
);
10858 as_bad (_("Invalid dsp acc register"));
10861 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
10862 gas_assert (!mips_opts
.micromips
);
10863 my_getExpression (&imm_expr
, s
);
10864 check_absolute_expr (ip
, &imm_expr
);
10865 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
10867 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10869 (unsigned long) imm_expr
.X_add_number
);
10871 INSERT_OPERAND (0, WRDSP
, *ip
, imm_expr
.X_add_number
);
10872 imm_expr
.X_op
= O_absent
;
10876 case '9': /* Four DSP accumulators in bits 21,22. */
10877 gas_assert (!mips_opts
.micromips
);
10878 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
10879 s
[3] >= '0' && s
[3] <= '3')
10881 regno
= s
[3] - '0';
10883 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
10887 as_bad (_("Invalid dsp acc register"));
10890 case '0': /* DSP 6-bit signed immediate in bit 20. */
10891 gas_assert (!mips_opts
.micromips
);
10892 my_getExpression (&imm_expr
, s
);
10893 check_absolute_expr (ip
, &imm_expr
);
10894 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
10895 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
10896 if (imm_expr
.X_add_number
< min_range
||
10897 imm_expr
.X_add_number
> max_range
)
10899 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10900 (long) min_range
, (long) max_range
,
10901 (long) imm_expr
.X_add_number
);
10903 INSERT_OPERAND (0, DSPSFT
, *ip
, imm_expr
.X_add_number
);
10904 imm_expr
.X_op
= O_absent
;
10908 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10909 gas_assert (!mips_opts
.micromips
);
10910 my_getExpression (&imm_expr
, s
);
10911 check_absolute_expr (ip
, &imm_expr
);
10912 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
10914 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10916 (unsigned long) imm_expr
.X_add_number
);
10918 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
10919 imm_expr
.X_op
= O_absent
;
10923 case ':': /* DSP 7-bit signed immediate in bit 19. */
10924 gas_assert (!mips_opts
.micromips
);
10925 my_getExpression (&imm_expr
, s
);
10926 check_absolute_expr (ip
, &imm_expr
);
10927 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
10928 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
10929 if (imm_expr
.X_add_number
< min_range
||
10930 imm_expr
.X_add_number
> max_range
)
10932 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10933 (long) min_range
, (long) max_range
,
10934 (long) imm_expr
.X_add_number
);
10936 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
10937 imm_expr
.X_op
= O_absent
;
10941 case '@': /* DSP 10-bit signed immediate in bit 16. */
10942 gas_assert (!mips_opts
.micromips
);
10943 my_getExpression (&imm_expr
, s
);
10944 check_absolute_expr (ip
, &imm_expr
);
10945 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
10946 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
10947 if (imm_expr
.X_add_number
< min_range
||
10948 imm_expr
.X_add_number
> max_range
)
10950 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10951 (long) min_range
, (long) max_range
,
10952 (long) imm_expr
.X_add_number
);
10954 INSERT_OPERAND (0, IMM10
, *ip
, imm_expr
.X_add_number
);
10955 imm_expr
.X_op
= O_absent
;
10959 case '!': /* MT usermode flag bit. */
10960 gas_assert (!mips_opts
.micromips
);
10961 my_getExpression (&imm_expr
, s
);
10962 check_absolute_expr (ip
, &imm_expr
);
10963 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
10964 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
10965 (unsigned long) imm_expr
.X_add_number
);
10966 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
10967 imm_expr
.X_op
= O_absent
;
10971 case '$': /* MT load high flag bit. */
10972 gas_assert (!mips_opts
.micromips
);
10973 my_getExpression (&imm_expr
, s
);
10974 check_absolute_expr (ip
, &imm_expr
);
10975 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
10976 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
10977 (unsigned long) imm_expr
.X_add_number
);
10978 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
10979 imm_expr
.X_op
= O_absent
;
10983 case '*': /* Four DSP accumulators in bits 18,19. */
10984 gas_assert (!mips_opts
.micromips
);
10985 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
10986 s
[3] >= '0' && s
[3] <= '3')
10988 regno
= s
[3] - '0';
10990 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
10994 as_bad (_("Invalid dsp/smartmips acc register"));
10997 case '&': /* Four DSP accumulators in bits 13,14. */
10998 gas_assert (!mips_opts
.micromips
);
10999 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11000 s
[3] >= '0' && s
[3] <= '3')
11002 regno
= s
[3] - '0';
11004 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11008 as_bad (_("Invalid dsp/smartmips acc register"));
11011 case '\\': /* 3-bit bit position. */
11013 unsigned long mask
= (mips_opts
.micromips
11014 ? MICROMIPSOP_MASK_3BITPOS
11015 : OP_MASK_3BITPOS
);
11017 my_getExpression (&imm_expr
, s
);
11018 check_absolute_expr (ip
, &imm_expr
);
11019 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11020 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11022 mask
, (unsigned long) imm_expr
.X_add_number
);
11023 INSERT_OPERAND (mips_opts
.micromips
,
11024 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11025 imm_expr
.X_op
= O_absent
;
11039 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11043 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11047 gas_assert (!mips_opts
.micromips
);
11048 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11052 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11058 /* Handle optional base register.
11059 Either the base register is omitted or
11060 we must have a left paren. */
11061 /* This is dependent on the next operand specifier
11062 is a base register specification. */
11063 gas_assert (args
[1] == 'b'
11064 || (mips_opts
.micromips
11066 && (args
[2] == 'l' || args
[2] == 'n'
11067 || args
[2] == 's' || args
[2] == 'a')));
11068 if (*s
== '\0' && args
[1] == 'b')
11070 /* Fall through. */
11072 case ')': /* These must match exactly. */
11077 case '[': /* These must match exactly. */
11079 gas_assert (!mips_opts
.micromips
);
11084 case '+': /* Opcode extension character. */
11087 case '1': /* UDI immediates. */
11091 gas_assert (!mips_opts
.micromips
);
11093 const struct mips_immed
*imm
= mips_immed
;
11095 while (imm
->type
&& imm
->type
!= *args
)
11099 my_getExpression (&imm_expr
, s
);
11100 check_absolute_expr (ip
, &imm_expr
);
11101 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11103 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11104 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11105 (unsigned long) imm_expr
.X_add_number
,
11106 (unsigned long) imm_expr
.X_add_number
);
11107 imm_expr
.X_add_number
&= imm
->mask
;
11109 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11111 imm_expr
.X_op
= O_absent
;
11116 case 'A': /* ins/ext position, becomes LSB. */
11125 my_getExpression (&imm_expr
, s
);
11126 check_absolute_expr (ip
, &imm_expr
);
11127 if ((unsigned long) imm_expr
.X_add_number
< limlo
11128 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11130 as_bad (_("Improper position (%lu)"),
11131 (unsigned long) imm_expr
.X_add_number
);
11132 imm_expr
.X_add_number
= limlo
;
11134 lastpos
= imm_expr
.X_add_number
;
11135 INSERT_OPERAND (mips_opts
.micromips
,
11136 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11137 imm_expr
.X_op
= O_absent
;
11141 case 'B': /* ins size, becomes MSB. */
11150 my_getExpression (&imm_expr
, s
);
11151 check_absolute_expr (ip
, &imm_expr
);
11152 /* Check for negative input so that small negative numbers
11153 will not succeed incorrectly. The checks against
11154 (pos+size) transitively check "size" itself,
11155 assuming that "pos" is reasonable. */
11156 if ((long) imm_expr
.X_add_number
< 0
11157 || ((unsigned long) imm_expr
.X_add_number
11159 || ((unsigned long) imm_expr
.X_add_number
11160 + lastpos
) > limhi
)
11162 as_bad (_("Improper insert size (%lu, position %lu)"),
11163 (unsigned long) imm_expr
.X_add_number
,
11164 (unsigned long) lastpos
);
11165 imm_expr
.X_add_number
= limlo
- lastpos
;
11167 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11168 lastpos
+ imm_expr
.X_add_number
- 1);
11169 imm_expr
.X_op
= O_absent
;
11173 case 'C': /* ext size, becomes MSBD. */
11186 my_getExpression (&imm_expr
, s
);
11187 check_absolute_expr (ip
, &imm_expr
);
11188 /* Check for negative input so that small negative numbers
11189 will not succeed incorrectly. The checks against
11190 (pos+size) transitively check "size" itself,
11191 assuming that "pos" is reasonable. */
11192 if ((long) imm_expr
.X_add_number
< 0
11193 || ((unsigned long) imm_expr
.X_add_number
11195 || ((unsigned long) imm_expr
.X_add_number
11196 + lastpos
) > limhi
)
11198 as_bad (_("Improper extract size (%lu, position %lu)"),
11199 (unsigned long) imm_expr
.X_add_number
,
11200 (unsigned long) lastpos
);
11201 imm_expr
.X_add_number
= limlo
- lastpos
;
11203 INSERT_OPERAND (mips_opts
.micromips
,
11204 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11205 imm_expr
.X_op
= O_absent
;
11210 /* +D is for disassembly only; never match. */
11214 /* "+I" is like "I", except that imm2_expr is used. */
11215 my_getExpression (&imm2_expr
, s
);
11216 if (imm2_expr
.X_op
!= O_big
11217 && imm2_expr
.X_op
!= O_constant
)
11218 insn_error
= _("absolute expression required");
11219 if (HAVE_32BIT_GPRS
)
11220 normalize_constant_expr (&imm2_expr
);
11224 case 'T': /* Coprocessor register. */
11225 gas_assert (!mips_opts
.micromips
);
11226 /* +T is for disassembly only; never match. */
11229 case 't': /* Coprocessor register number. */
11230 gas_assert (!mips_opts
.micromips
);
11231 if (s
[0] == '$' && ISDIGIT (s
[1]))
11241 while (ISDIGIT (*s
));
11243 as_bad (_("Invalid register number (%d)"), regno
);
11246 INSERT_OPERAND (0, RT
, *ip
, regno
);
11251 as_bad (_("Invalid coprocessor 0 register number"));
11255 /* bbit[01] and bbit[01]32 bit index. Give error if index
11256 is not in the valid range. */
11257 gas_assert (!mips_opts
.micromips
);
11258 my_getExpression (&imm_expr
, s
);
11259 check_absolute_expr (ip
, &imm_expr
);
11260 if ((unsigned) imm_expr
.X_add_number
> 31)
11262 as_bad (_("Improper bit index (%lu)"),
11263 (unsigned long) imm_expr
.X_add_number
);
11264 imm_expr
.X_add_number
= 0;
11266 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11267 imm_expr
.X_op
= O_absent
;
11272 /* bbit[01] bit index when bbit is used but we generate
11273 bbit[01]32 because the index is over 32. Move to the
11274 next candidate if index is not in the valid range. */
11275 gas_assert (!mips_opts
.micromips
);
11276 my_getExpression (&imm_expr
, s
);
11277 check_absolute_expr (ip
, &imm_expr
);
11278 if ((unsigned) imm_expr
.X_add_number
< 32
11279 || (unsigned) imm_expr
.X_add_number
> 63)
11281 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11282 imm_expr
.X_op
= O_absent
;
11287 /* cins, cins32, exts and exts32 position field. Give error
11288 if it's not in the valid range. */
11289 gas_assert (!mips_opts
.micromips
);
11290 my_getExpression (&imm_expr
, s
);
11291 check_absolute_expr (ip
, &imm_expr
);
11292 if ((unsigned) imm_expr
.X_add_number
> 31)
11294 as_bad (_("Improper position (%lu)"),
11295 (unsigned long) imm_expr
.X_add_number
);
11296 imm_expr
.X_add_number
= 0;
11298 /* Make the pos explicit to simplify +S. */
11299 lastpos
= imm_expr
.X_add_number
+ 32;
11300 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11301 imm_expr
.X_op
= O_absent
;
11306 /* cins, cins32, exts and exts32 position field. Move to
11307 the next candidate if it's not in the valid range. */
11308 gas_assert (!mips_opts
.micromips
);
11309 my_getExpression (&imm_expr
, s
);
11310 check_absolute_expr (ip
, &imm_expr
);
11311 if ((unsigned) imm_expr
.X_add_number
< 32
11312 || (unsigned) imm_expr
.X_add_number
> 63)
11314 lastpos
= imm_expr
.X_add_number
;
11315 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11316 imm_expr
.X_op
= O_absent
;
11321 /* cins and exts length-minus-one field. */
11322 gas_assert (!mips_opts
.micromips
);
11323 my_getExpression (&imm_expr
, s
);
11324 check_absolute_expr (ip
, &imm_expr
);
11325 if ((unsigned long) imm_expr
.X_add_number
> 31)
11327 as_bad (_("Improper size (%lu)"),
11328 (unsigned long) imm_expr
.X_add_number
);
11329 imm_expr
.X_add_number
= 0;
11331 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11332 imm_expr
.X_op
= O_absent
;
11337 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11338 length-minus-one field. */
11339 gas_assert (!mips_opts
.micromips
);
11340 my_getExpression (&imm_expr
, s
);
11341 check_absolute_expr (ip
, &imm_expr
);
11342 if ((long) imm_expr
.X_add_number
< 0
11343 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11345 as_bad (_("Improper size (%lu)"),
11346 (unsigned long) imm_expr
.X_add_number
);
11347 imm_expr
.X_add_number
= 0;
11349 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11350 imm_expr
.X_op
= O_absent
;
11355 /* seqi/snei immediate field. */
11356 gas_assert (!mips_opts
.micromips
);
11357 my_getExpression (&imm_expr
, s
);
11358 check_absolute_expr (ip
, &imm_expr
);
11359 if ((long) imm_expr
.X_add_number
< -512
11360 || (long) imm_expr
.X_add_number
>= 512)
11362 as_bad (_("Improper immediate (%ld)"),
11363 (long) imm_expr
.X_add_number
);
11364 imm_expr
.X_add_number
= 0;
11366 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11367 imm_expr
.X_op
= O_absent
;
11371 case 'a': /* 8-bit signed offset in bit 6 */
11372 gas_assert (!mips_opts
.micromips
);
11373 my_getExpression (&imm_expr
, s
);
11374 check_absolute_expr (ip
, &imm_expr
);
11375 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11376 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11377 if (imm_expr
.X_add_number
< min_range
11378 || imm_expr
.X_add_number
> max_range
)
11380 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11381 (long) min_range
, (long) max_range
,
11382 (long) imm_expr
.X_add_number
);
11384 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11385 imm_expr
.X_op
= O_absent
;
11389 case 'b': /* 8-bit signed offset in bit 3 */
11390 gas_assert (!mips_opts
.micromips
);
11391 my_getExpression (&imm_expr
, s
);
11392 check_absolute_expr (ip
, &imm_expr
);
11393 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11394 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11395 if (imm_expr
.X_add_number
< min_range
11396 || imm_expr
.X_add_number
> max_range
)
11398 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11399 (long) min_range
, (long) max_range
,
11400 (long) imm_expr
.X_add_number
);
11402 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11403 imm_expr
.X_op
= O_absent
;
11407 case 'c': /* 9-bit signed offset in bit 6 */
11408 gas_assert (!mips_opts
.micromips
);
11409 my_getExpression (&imm_expr
, s
);
11410 check_absolute_expr (ip
, &imm_expr
);
11411 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11412 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11413 /* We check the offset range before adjusted. */
11416 if (imm_expr
.X_add_number
< min_range
11417 || imm_expr
.X_add_number
> max_range
)
11419 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11420 (long) min_range
, (long) max_range
,
11421 (long) imm_expr
.X_add_number
);
11423 if (imm_expr
.X_add_number
& 0xf)
11425 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11426 (long) imm_expr
.X_add_number
);
11428 /* Right shift 4 bits to adjust the offset operand. */
11429 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11430 imm_expr
.X_add_number
>> 4);
11431 imm_expr
.X_op
= O_absent
;
11436 gas_assert (!mips_opts
.micromips
);
11437 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11439 if (regno
== AT
&& mips_opts
.at
)
11441 if (mips_opts
.at
== ATREG
)
11442 as_warn (_("used $at without \".set noat\""));
11444 as_warn (_("used $%u with \".set at=$%u\""),
11445 regno
, mips_opts
.at
);
11447 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11451 gas_assert (!mips_opts
.micromips
);
11452 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11454 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11458 as_bad (_("Internal error: bad %s opcode "
11459 "(unknown extension operand type `+%c'): %s %s"),
11460 mips_opts
.micromips
? "microMIPS" : "MIPS",
11461 *args
, insn
->name
, insn
->args
);
11462 /* Further processing is fruitless. */
11467 case '.': /* 10-bit offset. */
11468 gas_assert (mips_opts
.micromips
);
11469 case '~': /* 12-bit offset. */
11471 int shift
= *args
== '.' ? 9 : 11;
11474 /* Check whether there is only a single bracketed expression
11475 left. If so, it must be the base register and the
11476 constant must be zero. */
11477 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11480 /* If this value won't fit into the offset, then go find
11481 a macro that will generate a 16- or 32-bit offset code
11483 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11484 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11485 || imm_expr
.X_add_number
>= 1 << shift
11486 || imm_expr
.X_add_number
< -1 << shift
))
11489 imm_expr
.X_op
= O_absent
;
11493 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11495 INSERT_OPERAND (mips_opts
.micromips
,
11496 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11497 imm_expr
.X_op
= O_absent
;
11502 case '<': /* must be at least one digit */
11504 * According to the manual, if the shift amount is greater
11505 * than 31 or less than 0, then the shift amount should be
11506 * mod 32. In reality the mips assembler issues an error.
11507 * We issue a warning and mask out all but the low 5 bits.
11509 my_getExpression (&imm_expr
, s
);
11510 check_absolute_expr (ip
, &imm_expr
);
11511 if ((unsigned long) imm_expr
.X_add_number
> 31)
11512 as_warn (_("Improper shift amount (%lu)"),
11513 (unsigned long) imm_expr
.X_add_number
);
11514 INSERT_OPERAND (mips_opts
.micromips
,
11515 SHAMT
, *ip
, imm_expr
.X_add_number
);
11516 imm_expr
.X_op
= O_absent
;
11520 case '>': /* shift amount minus 32 */
11521 my_getExpression (&imm_expr
, s
);
11522 check_absolute_expr (ip
, &imm_expr
);
11523 if ((unsigned long) imm_expr
.X_add_number
< 32
11524 || (unsigned long) imm_expr
.X_add_number
> 63)
11526 INSERT_OPERAND (mips_opts
.micromips
,
11527 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11528 imm_expr
.X_op
= O_absent
;
11532 case 'k': /* CACHE code. */
11533 case 'h': /* PREFX code. */
11534 case '1': /* SYNC type. */
11535 my_getExpression (&imm_expr
, s
);
11536 check_absolute_expr (ip
, &imm_expr
);
11537 if ((unsigned long) imm_expr
.X_add_number
> 31)
11538 as_warn (_("Invalid value for `%s' (%lu)"),
11540 (unsigned long) imm_expr
.X_add_number
);
11544 if (mips_fix_cn63xxp1
11545 && !mips_opts
.micromips
11546 && strcmp ("pref", insn
->name
) == 0)
11547 switch (imm_expr
.X_add_number
)
11556 case 31: /* These are ok. */
11559 default: /* The rest must be changed to 28. */
11560 imm_expr
.X_add_number
= 28;
11563 INSERT_OPERAND (mips_opts
.micromips
,
11564 CACHE
, *ip
, imm_expr
.X_add_number
);
11567 INSERT_OPERAND (mips_opts
.micromips
,
11568 PREFX
, *ip
, imm_expr
.X_add_number
);
11571 INSERT_OPERAND (mips_opts
.micromips
,
11572 STYPE
, *ip
, imm_expr
.X_add_number
);
11575 imm_expr
.X_op
= O_absent
;
11579 case 'c': /* BREAK code. */
11581 unsigned long mask
= (mips_opts
.micromips
11582 ? MICROMIPSOP_MASK_CODE
11585 my_getExpression (&imm_expr
, s
);
11586 check_absolute_expr (ip
, &imm_expr
);
11587 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11588 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11590 mask
, (unsigned long) imm_expr
.X_add_number
);
11591 INSERT_OPERAND (mips_opts
.micromips
,
11592 CODE
, *ip
, imm_expr
.X_add_number
);
11593 imm_expr
.X_op
= O_absent
;
11598 case 'q': /* Lower BREAK code. */
11600 unsigned long mask
= (mips_opts
.micromips
11601 ? MICROMIPSOP_MASK_CODE2
11604 my_getExpression (&imm_expr
, s
);
11605 check_absolute_expr (ip
, &imm_expr
);
11606 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11607 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11609 mask
, (unsigned long) imm_expr
.X_add_number
);
11610 INSERT_OPERAND (mips_opts
.micromips
,
11611 CODE2
, *ip
, imm_expr
.X_add_number
);
11612 imm_expr
.X_op
= O_absent
;
11617 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11619 unsigned long mask
= (mips_opts
.micromips
11620 ? MICROMIPSOP_MASK_CODE10
11623 my_getExpression (&imm_expr
, s
);
11624 check_absolute_expr (ip
, &imm_expr
);
11625 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11626 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11628 mask
, (unsigned long) imm_expr
.X_add_number
);
11629 if (mips_opts
.micromips
)
11630 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
11632 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
11633 imm_expr
.X_op
= O_absent
;
11638 case 'C': /* 25- or 23-bit coprocessor code. */
11640 unsigned long mask
= (mips_opts
.micromips
11641 ? MICROMIPSOP_MASK_COPZ
11644 my_getExpression (&imm_expr
, s
);
11645 check_absolute_expr (ip
, &imm_expr
);
11646 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11647 as_warn (_("Coproccesor code > %u bits (%lu)"),
11648 mips_opts
.micromips
? 23U : 25U,
11649 (unsigned long) imm_expr
.X_add_number
);
11650 INSERT_OPERAND (mips_opts
.micromips
,
11651 COPZ
, *ip
, imm_expr
.X_add_number
);
11652 imm_expr
.X_op
= O_absent
;
11657 case 'J': /* 19-bit WAIT code. */
11658 gas_assert (!mips_opts
.micromips
);
11659 my_getExpression (&imm_expr
, s
);
11660 check_absolute_expr (ip
, &imm_expr
);
11661 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
11663 as_warn (_("Illegal 19-bit code (%lu)"),
11664 (unsigned long) imm_expr
.X_add_number
);
11665 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
11667 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
11668 imm_expr
.X_op
= O_absent
;
11672 case 'P': /* Performance register. */
11673 gas_assert (!mips_opts
.micromips
);
11674 my_getExpression (&imm_expr
, s
);
11675 check_absolute_expr (ip
, &imm_expr
);
11676 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
11677 as_warn (_("Invalid performance register (%lu)"),
11678 (unsigned long) imm_expr
.X_add_number
);
11679 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
11680 imm_expr
.X_op
= O_absent
;
11684 case 'G': /* Coprocessor destination register. */
11686 unsigned long opcode
= ip
->insn_opcode
;
11687 unsigned long mask
;
11688 unsigned int types
;
11691 if (mips_opts
.micromips
)
11693 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
11694 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
11695 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
11699 case 0x000000fc: /* mfc0 */
11700 case 0x000002fc: /* mtc0 */
11701 case 0x580000fc: /* dmfc0 */
11702 case 0x580002fc: /* dmtc0 */
11712 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
11713 cop0
= opcode
== OP_OP_COP0
;
11715 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
11716 ok
= reg_lookup (&s
, types
, ®no
);
11717 if (mips_opts
.micromips
)
11718 INSERT_OPERAND (1, RS
, *ip
, regno
);
11720 INSERT_OPERAND (0, RD
, *ip
, regno
);
11729 case 'y': /* ALNV.PS source register. */
11730 gas_assert (mips_opts
.micromips
);
11732 case 'x': /* Ignore register name. */
11733 case 'U': /* Destination register (CLO/CLZ). */
11734 case 'g': /* Coprocessor destination register. */
11735 gas_assert (!mips_opts
.micromips
);
11736 case 'b': /* Base register. */
11737 case 'd': /* Destination register. */
11738 case 's': /* Source register. */
11739 case 't': /* Target register. */
11740 case 'r': /* Both target and source. */
11741 case 'v': /* Both dest and source. */
11742 case 'w': /* Both dest and target. */
11743 case 'E': /* Coprocessor target register. */
11744 case 'K': /* RDHWR destination register. */
11745 case 'z': /* Must be zero register. */
11748 if (*args
== 'E' || *args
== 'K')
11749 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
11752 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
11753 if (regno
== AT
&& mips_opts
.at
)
11755 if (mips_opts
.at
== ATREG
)
11756 as_warn (_("Used $at without \".set noat\""));
11758 as_warn (_("Used $%u with \".set at=$%u\""),
11759 regno
, mips_opts
.at
);
11769 if (c
== 'r' || c
== 'v' || c
== 'w')
11776 /* 'z' only matches $0. */
11777 if (c
== 'z' && regno
!= 0)
11780 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
11782 if (regno
== lastregno
)
11785 = _("Source and destination must be different");
11788 if (regno
== 31 && lastregno
== 0xffffffff)
11791 = _("A destination register must be supplied");
11795 /* Now that we have assembled one operand, we use the args
11796 string to figure out where it goes in the instruction. */
11803 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
11807 if (mips_opts
.micromips
)
11808 INSERT_OPERAND (1, RS
, *ip
, regno
);
11810 INSERT_OPERAND (0, RD
, *ip
, regno
);
11815 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
11819 gas_assert (!mips_opts
.micromips
);
11820 INSERT_OPERAND (0, RD
, *ip
, regno
);
11821 INSERT_OPERAND (0, RT
, *ip
, regno
);
11827 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
11831 gas_assert (mips_opts
.micromips
);
11832 INSERT_OPERAND (1, RS3
, *ip
, regno
);
11836 /* This case exists because on the r3000 trunc
11837 expands into a macro which requires a gp
11838 register. On the r6000 or r4000 it is
11839 assembled into a single instruction which
11840 ignores the register. Thus the insn version
11841 is MIPS_ISA2 and uses 'x', and the macro
11842 version is MIPS_ISA1 and uses 't'. */
11846 /* This case is for the div instruction, which
11847 acts differently if the destination argument
11848 is $0. This only matches $0, and is checked
11849 outside the switch. */
11859 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11863 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11868 case 'O': /* MDMX alignment immediate constant. */
11869 gas_assert (!mips_opts
.micromips
);
11870 my_getExpression (&imm_expr
, s
);
11871 check_absolute_expr (ip
, &imm_expr
);
11872 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
11873 as_warn (_("Improper align amount (%ld), using low bits"),
11874 (long) imm_expr
.X_add_number
);
11875 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
11876 imm_expr
.X_op
= O_absent
;
11880 case 'Q': /* MDMX vector, element sel, or const. */
11883 /* MDMX Immediate. */
11884 gas_assert (!mips_opts
.micromips
);
11885 my_getExpression (&imm_expr
, s
);
11886 check_absolute_expr (ip
, &imm_expr
);
11887 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
11888 as_warn (_("Invalid MDMX Immediate (%ld)"),
11889 (long) imm_expr
.X_add_number
);
11890 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
11891 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
11892 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
11894 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
11895 imm_expr
.X_op
= O_absent
;
11899 /* Not MDMX Immediate. Fall through. */
11900 case 'X': /* MDMX destination register. */
11901 case 'Y': /* MDMX source register. */
11902 case 'Z': /* MDMX target register. */
11905 gas_assert (!mips_opts
.micromips
);
11906 case 'D': /* Floating point destination register. */
11907 case 'S': /* Floating point source register. */
11908 case 'T': /* Floating point target register. */
11909 case 'R': /* Floating point source register. */
11913 || (mips_opts
.ase_mdmx
11914 && (ip
->insn_mo
->pinfo
& FP_D
)
11915 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
11916 | INSN_COPROC_MEMORY_DELAY
11917 | INSN_LOAD_COPROC_DELAY
11918 | INSN_LOAD_MEMORY_DELAY
11919 | INSN_STORE_MEMORY
))))
11920 rtype
|= RTYPE_VEC
;
11922 if (reg_lookup (&s
, rtype
, ®no
))
11924 if ((regno
& 1) != 0
11926 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
11927 as_warn (_("Float register should be even, was %d"),
11935 if (c
== 'V' || c
== 'W')
11946 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
11952 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
11956 /* This is like 'Z', but also needs to fix the MDMX
11957 vector/scalar select bits. Note that the
11958 scalar immediate case is handled above. */
11961 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
11962 int max_el
= (is_qh
? 3 : 7);
11964 my_getExpression(&imm_expr
, s
);
11965 check_absolute_expr (ip
, &imm_expr
);
11967 if (imm_expr
.X_add_number
> max_el
)
11968 as_bad (_("Bad element selector %ld"),
11969 (long) imm_expr
.X_add_number
);
11970 imm_expr
.X_add_number
&= max_el
;
11971 ip
->insn_opcode
|= (imm_expr
.X_add_number
11974 imm_expr
.X_op
= O_absent
;
11976 as_warn (_("Expecting ']' found '%s'"), s
);
11982 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
11983 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
11986 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
11989 /* Fall through. */
11993 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
11997 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12007 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12011 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12017 my_getExpression (&imm_expr
, s
);
12018 if (imm_expr
.X_op
!= O_big
12019 && imm_expr
.X_op
!= O_constant
)
12020 insn_error
= _("absolute expression required");
12021 if (HAVE_32BIT_GPRS
)
12022 normalize_constant_expr (&imm_expr
);
12027 my_getExpression (&offset_expr
, s
);
12028 normalize_address_expr (&offset_expr
);
12029 *imm_reloc
= BFD_RELOC_32
;
12042 unsigned char temp
[8];
12044 unsigned int length
;
12049 /* These only appear as the last operand in an
12050 instruction, and every instruction that accepts
12051 them in any variant accepts them in all variants.
12052 This means we don't have to worry about backing out
12053 any changes if the instruction does not match.
12055 The difference between them is the size of the
12056 floating point constant and where it goes. For 'F'
12057 and 'L' the constant is 64 bits; for 'f' and 'l' it
12058 is 32 bits. Where the constant is placed is based
12059 on how the MIPS assembler does things:
12062 f -- immediate value
12065 The .lit4 and .lit8 sections are only used if
12066 permitted by the -G argument.
12068 The code below needs to know whether the target register
12069 is 32 or 64 bits wide. It relies on the fact 'f' and
12070 'F' are used with GPR-based instructions and 'l' and
12071 'L' are used with FPR-based instructions. */
12073 f64
= *args
== 'F' || *args
== 'L';
12074 using_gprs
= *args
== 'F' || *args
== 'f';
12076 save_in
= input_line_pointer
;
12077 input_line_pointer
= s
;
12078 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12080 s
= input_line_pointer
;
12081 input_line_pointer
= save_in
;
12082 if (err
!= NULL
&& *err
!= '\0')
12084 as_bad (_("Bad floating point constant: %s"), err
);
12085 memset (temp
, '\0', sizeof temp
);
12086 length
= f64
? 8 : 4;
12089 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12093 && (g_switch_value
< 4
12094 || (temp
[0] == 0 && temp
[1] == 0)
12095 || (temp
[2] == 0 && temp
[3] == 0))))
12097 imm_expr
.X_op
= O_constant
;
12098 if (!target_big_endian
)
12099 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12101 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12103 else if (length
> 4
12104 && !mips_disable_float_construction
12105 /* Constants can only be constructed in GPRs and
12106 copied to FPRs if the GPRs are at least as wide
12107 as the FPRs. Force the constant into memory if
12108 we are using 64-bit FPRs but the GPRs are only
12111 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12112 && ((temp
[0] == 0 && temp
[1] == 0)
12113 || (temp
[2] == 0 && temp
[3] == 0))
12114 && ((temp
[4] == 0 && temp
[5] == 0)
12115 || (temp
[6] == 0 && temp
[7] == 0)))
12117 /* The value is simple enough to load with a couple of
12118 instructions. If using 32-bit registers, set
12119 imm_expr to the high order 32 bits and offset_expr to
12120 the low order 32 bits. Otherwise, set imm_expr to
12121 the entire 64 bit constant. */
12122 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12124 imm_expr
.X_op
= O_constant
;
12125 offset_expr
.X_op
= O_constant
;
12126 if (!target_big_endian
)
12128 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12129 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12133 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12134 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12136 if (offset_expr
.X_add_number
== 0)
12137 offset_expr
.X_op
= O_absent
;
12139 else if (sizeof (imm_expr
.X_add_number
) > 4)
12141 imm_expr
.X_op
= O_constant
;
12142 if (!target_big_endian
)
12143 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12145 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12149 imm_expr
.X_op
= O_big
;
12150 imm_expr
.X_add_number
= 4;
12151 if (!target_big_endian
)
12153 generic_bignum
[0] = bfd_getl16 (temp
);
12154 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12155 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12156 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12160 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12161 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12162 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12163 generic_bignum
[3] = bfd_getb16 (temp
);
12169 const char *newname
;
12172 /* Switch to the right section. */
12174 subseg
= now_subseg
;
12177 default: /* unused default case avoids warnings. */
12179 newname
= RDATA_SECTION_NAME
;
12180 if (g_switch_value
>= 8)
12184 newname
= RDATA_SECTION_NAME
;
12187 gas_assert (g_switch_value
>= 4);
12191 new_seg
= subseg_new (newname
, (subsegT
) 0);
12193 bfd_set_section_flags (stdoutput
, new_seg
,
12198 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12199 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12200 record_alignment (new_seg
, 4);
12202 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12203 if (seg
== now_seg
)
12204 as_bad (_("Can't use floating point insn in this section"));
12206 /* Set the argument to the current address in the
12208 offset_expr
.X_op
= O_symbol
;
12209 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12210 offset_expr
.X_add_number
= 0;
12212 /* Put the floating point number into the section. */
12213 p
= frag_more ((int) length
);
12214 memcpy (p
, temp
, length
);
12216 /* Switch back to the original section. */
12217 subseg_set (seg
, subseg
);
12222 case 'i': /* 16-bit unsigned immediate. */
12223 case 'j': /* 16-bit signed immediate. */
12224 *imm_reloc
= BFD_RELOC_LO16
;
12225 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12228 offsetT minval
, maxval
;
12230 more
= (insn
+ 1 < past
12231 && strcmp (insn
->name
, insn
[1].name
) == 0);
12233 /* If the expression was written as an unsigned number,
12234 only treat it as signed if there are no more
12238 && sizeof (imm_expr
.X_add_number
) <= 4
12239 && imm_expr
.X_op
== O_constant
12240 && imm_expr
.X_add_number
< 0
12241 && imm_expr
.X_unsigned
12242 && HAVE_64BIT_GPRS
)
12245 /* For compatibility with older assemblers, we accept
12246 0x8000-0xffff as signed 16-bit numbers when only
12247 signed numbers are allowed. */
12249 minval
= 0, maxval
= 0xffff;
12251 minval
= -0x8000, maxval
= 0x7fff;
12253 minval
= -0x8000, maxval
= 0xffff;
12255 if (imm_expr
.X_op
!= O_constant
12256 || imm_expr
.X_add_number
< minval
12257 || imm_expr
.X_add_number
> maxval
)
12261 if (imm_expr
.X_op
== O_constant
12262 || imm_expr
.X_op
== O_big
)
12263 as_bad (_("Expression out of range"));
12269 case 'o': /* 16-bit offset. */
12270 offset_reloc
[0] = BFD_RELOC_LO16
;
12271 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12272 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12274 /* Check whether there is only a single bracketed expression
12275 left. If so, it must be the base register and the
12276 constant must be zero. */
12277 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12279 offset_expr
.X_op
= O_constant
;
12280 offset_expr
.X_add_number
= 0;
12284 /* If this value won't fit into a 16 bit offset, then go
12285 find a macro that will generate the 32 bit offset
12287 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12288 && (offset_expr
.X_op
!= O_constant
12289 || offset_expr
.X_add_number
>= 0x8000
12290 || offset_expr
.X_add_number
< -0x8000))
12296 case 'p': /* PC-relative offset. */
12297 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12298 my_getExpression (&offset_expr
, s
);
12302 case 'u': /* Upper 16 bits. */
12303 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12304 && imm_expr
.X_op
== O_constant
12305 && (imm_expr
.X_add_number
< 0
12306 || imm_expr
.X_add_number
>= 0x10000))
12307 as_bad (_("lui expression (%lu) not in range 0..65535"),
12308 (unsigned long) imm_expr
.X_add_number
);
12312 case 'a': /* 26-bit address. */
12313 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12314 my_getExpression (&offset_expr
, s
);
12318 case 'N': /* 3-bit branch condition code. */
12319 case 'M': /* 3-bit compare condition code. */
12321 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12322 rtype
|= RTYPE_FCC
;
12323 if (!reg_lookup (&s
, rtype
, ®no
))
12325 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12326 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12327 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12328 && (regno
& 1) != 0)
12329 as_warn (_("Condition code register should be even for %s, "
12332 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12333 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12334 && (regno
& 3) != 0)
12335 as_warn (_("Condition code register should be 0 or 4 for %s, "
12339 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12341 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12345 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12356 while (ISDIGIT (*s
));
12359 c
= 8; /* Invalid sel value. */
12362 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12363 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12367 gas_assert (!mips_opts
.micromips
);
12368 /* Must be at least one digit. */
12369 my_getExpression (&imm_expr
, s
);
12370 check_absolute_expr (ip
, &imm_expr
);
12372 if ((unsigned long) imm_expr
.X_add_number
12373 > (unsigned long) OP_MASK_VECBYTE
)
12375 as_bad (_("bad byte vector index (%ld)"),
12376 (long) imm_expr
.X_add_number
);
12377 imm_expr
.X_add_number
= 0;
12380 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12381 imm_expr
.X_op
= O_absent
;
12386 gas_assert (!mips_opts
.micromips
);
12387 my_getExpression (&imm_expr
, s
);
12388 check_absolute_expr (ip
, &imm_expr
);
12390 if ((unsigned long) imm_expr
.X_add_number
12391 > (unsigned long) OP_MASK_VECALIGN
)
12393 as_bad (_("bad byte vector index (%ld)"),
12394 (long) imm_expr
.X_add_number
);
12395 imm_expr
.X_add_number
= 0;
12398 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12399 imm_expr
.X_op
= O_absent
;
12403 case 'm': /* Opcode extension character. */
12404 gas_assert (mips_opts
.micromips
);
12409 if (strncmp (s
, "$pc", 3) == 0)
12437 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12438 if (regno
== AT
&& mips_opts
.at
)
12440 if (mips_opts
.at
== ATREG
)
12441 as_warn (_("Used $at without \".set noat\""));
12443 as_warn (_("Used $%u with \".set at=$%u\""),
12444 regno
, mips_opts
.at
);
12450 gas_assert (args
[1] == ',');
12456 gas_assert (args
[1] == ',');
12458 continue; /* Nothing to do. */
12464 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12466 if (regno
== lastregno
)
12469 = _("Source and destination must be different");
12472 if (regno
== 31 && lastregno
== 0xffffffff)
12475 = _("A destination register must be supplied");
12486 gas_assert (args
[1] == ',');
12493 gas_assert (args
[1] == ',');
12496 continue; /* Nothing to do. */
12500 /* Make sure regno is the same as lastregno. */
12501 if (c
== 't' && regno
!= lastregno
)
12504 /* Make sure regno is the same as destregno. */
12505 if (c
== 'x' && regno
!= destregno
)
12508 /* We need to save regno, before regno maps to the
12509 microMIPS register encoding. */
12519 regno
= ILLEGAL_REG
;
12523 regno
= mips32_to_micromips_reg_b_map
[regno
];
12527 regno
= mips32_to_micromips_reg_c_map
[regno
];
12531 regno
= mips32_to_micromips_reg_d_map
[regno
];
12535 regno
= mips32_to_micromips_reg_e_map
[regno
];
12539 regno
= mips32_to_micromips_reg_f_map
[regno
];
12543 regno
= mips32_to_micromips_reg_g_map
[regno
];
12547 regno
= mips32_to_micromips_reg_h_map
[regno
];
12551 switch (EXTRACT_OPERAND (1, MI
, *ip
))
12556 else if (regno
== 22)
12558 else if (regno
== 5)
12560 else if (regno
== 6)
12562 else if (regno
== 7)
12565 regno
= ILLEGAL_REG
;
12571 else if (regno
== 7)
12574 regno
= ILLEGAL_REG
;
12581 regno
= ILLEGAL_REG
;
12585 regno
= ILLEGAL_REG
;
12591 regno
= mips32_to_micromips_reg_l_map
[regno
];
12595 regno
= mips32_to_micromips_reg_m_map
[regno
];
12599 regno
= mips32_to_micromips_reg_n_map
[regno
];
12603 regno
= mips32_to_micromips_reg_q_map
[regno
];
12608 regno
= ILLEGAL_REG
;
12613 regno
= ILLEGAL_REG
;
12618 regno
= ILLEGAL_REG
;
12621 case 'j': /* Do nothing. */
12631 if (regno
== ILLEGAL_REG
)
12637 INSERT_OPERAND (1, MB
, *ip
, regno
);
12641 INSERT_OPERAND (1, MC
, *ip
, regno
);
12645 INSERT_OPERAND (1, MD
, *ip
, regno
);
12649 INSERT_OPERAND (1, ME
, *ip
, regno
);
12653 INSERT_OPERAND (1, MF
, *ip
, regno
);
12657 INSERT_OPERAND (1, MG
, *ip
, regno
);
12661 INSERT_OPERAND (1, MH
, *ip
, regno
);
12665 INSERT_OPERAND (1, MI
, *ip
, regno
);
12669 INSERT_OPERAND (1, MJ
, *ip
, regno
);
12673 INSERT_OPERAND (1, ML
, *ip
, regno
);
12677 INSERT_OPERAND (1, MM
, *ip
, regno
);
12681 INSERT_OPERAND (1, MN
, *ip
, regno
);
12685 INSERT_OPERAND (1, MP
, *ip
, regno
);
12689 INSERT_OPERAND (1, MQ
, *ip
, regno
);
12692 case 'a': /* Do nothing. */
12693 case 's': /* Do nothing. */
12694 case 't': /* Do nothing. */
12695 case 'x': /* Do nothing. */
12696 case 'y': /* Do nothing. */
12697 case 'z': /* Do nothing. */
12707 bfd_reloc_code_real_type r
[3];
12711 /* Check whether there is only a single bracketed
12712 expression left. If so, it must be the base register
12713 and the constant must be zero. */
12714 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12716 INSERT_OPERAND (1, IMMA
, *ip
, 0);
12720 if (my_getSmallExpression (&ep
, r
, s
) > 0
12721 || !expr_const_in_range (&ep
, -64, 64, 2))
12724 imm
= ep
.X_add_number
>> 2;
12725 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
12732 bfd_reloc_code_real_type r
[3];
12736 if (my_getSmallExpression (&ep
, r
, s
) > 0
12737 || ep
.X_op
!= O_constant
)
12740 for (imm
= 0; imm
< 8; imm
++)
12741 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
12746 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
12753 bfd_reloc_code_real_type r
[3];
12757 if (my_getSmallExpression (&ep
, r
, s
) > 0
12758 || ep
.X_op
!= O_constant
)
12761 for (imm
= 0; imm
< 16; imm
++)
12762 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
12767 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
12772 case 'D': /* pc relative offset */
12773 case 'E': /* pc relative offset */
12774 my_getExpression (&offset_expr
, s
);
12775 if (offset_expr
.X_op
== O_register
)
12778 if (!forced_insn_length
)
12779 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12781 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12783 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12789 bfd_reloc_code_real_type r
[3];
12793 if (my_getSmallExpression (&ep
, r
, s
) > 0
12794 || !expr_const_in_range (&ep
, 0, 16, 0))
12797 imm
= ep
.X_add_number
;
12798 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
12805 bfd_reloc_code_real_type r
[3];
12809 /* Check whether there is only a single bracketed
12810 expression left. If so, it must be the base register
12811 and the constant must be zero. */
12812 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12814 INSERT_OPERAND (1, IMMG
, *ip
, 0);
12818 if (my_getSmallExpression (&ep
, r
, s
) > 0
12819 || !expr_const_in_range (&ep
, -1, 15, 0))
12822 imm
= ep
.X_add_number
& 15;
12823 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
12830 bfd_reloc_code_real_type r
[3];
12834 /* Check whether there is only a single bracketed
12835 expression left. If so, it must be the base register
12836 and the constant must be zero. */
12837 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12839 INSERT_OPERAND (1, IMMH
, *ip
, 0);
12843 if (my_getSmallExpression (&ep
, r
, s
) > 0
12844 || !expr_const_in_range (&ep
, 0, 16, 1))
12847 imm
= ep
.X_add_number
>> 1;
12848 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
12855 bfd_reloc_code_real_type r
[3];
12859 if (my_getSmallExpression (&ep
, r
, s
) > 0
12860 || !expr_const_in_range (&ep
, -1, 127, 0))
12863 imm
= ep
.X_add_number
& 127;
12864 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
12871 bfd_reloc_code_real_type r
[3];
12875 /* Check whether there is only a single bracketed
12876 expression left. If so, it must be the base register
12877 and the constant must be zero. */
12878 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12880 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
12884 if (my_getSmallExpression (&ep
, r
, s
) > 0
12885 || !expr_const_in_range (&ep
, 0, 16, 2))
12888 imm
= ep
.X_add_number
>> 2;
12889 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
12896 bfd_reloc_code_real_type r
[3];
12900 /* Check whether there is only a single bracketed
12901 expression left. If so, it must be the base register
12902 and the constant must be zero. */
12903 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12905 INSERT_OPERAND (1, IMML
, *ip
, 0);
12909 if (my_getSmallExpression (&ep
, r
, s
) > 0
12910 || !expr_const_in_range (&ep
, 0, 16, 0))
12913 imm
= ep
.X_add_number
;
12914 INSERT_OPERAND (1, IMML
, *ip
, imm
);
12921 bfd_reloc_code_real_type r
[3];
12925 if (my_getSmallExpression (&ep
, r
, s
) > 0
12926 || !expr_const_in_range (&ep
, 1, 9, 0))
12929 imm
= ep
.X_add_number
& 7;
12930 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
12935 case 'N': /* Register list for lwm and swm. */
12937 /* A comma-separated list of registers and/or
12938 dash-separated contiguous ranges including
12939 both ra and a set of one or more registers
12940 starting at s0 up to s3 which have to be
12947 and any permutations of these. */
12948 unsigned int reglist
;
12951 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
12954 if ((reglist
& 0xfff1ffff) != 0x80010000)
12957 reglist
= (reglist
>> 17) & 7;
12959 if ((reglist
& -reglist
) != reglist
)
12962 imm
= ffs (reglist
) - 1;
12963 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
12967 case 'O': /* sdbbp 4-bit code. */
12969 bfd_reloc_code_real_type r
[3];
12973 if (my_getSmallExpression (&ep
, r
, s
) > 0
12974 || !expr_const_in_range (&ep
, 0, 16, 0))
12977 imm
= ep
.X_add_number
;
12978 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
12985 bfd_reloc_code_real_type r
[3];
12989 if (my_getSmallExpression (&ep
, r
, s
) > 0
12990 || !expr_const_in_range (&ep
, 0, 32, 2))
12993 imm
= ep
.X_add_number
>> 2;
12994 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13001 bfd_reloc_code_real_type r
[3];
13005 if (my_getSmallExpression (&ep
, r
, s
) > 0
13006 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13009 imm
= ep
.X_add_number
>> 2;
13010 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13017 bfd_reloc_code_real_type r
[3];
13021 /* Check whether there is only a single bracketed
13022 expression left. If so, it must be the base register
13023 and the constant must be zero. */
13024 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13026 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13030 if (my_getSmallExpression (&ep
, r
, s
) > 0
13031 || !expr_const_in_range (&ep
, 0, 32, 2))
13034 imm
= ep
.X_add_number
>> 2;
13035 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13042 bfd_reloc_code_real_type r
[3];
13046 if (my_getSmallExpression (&ep
, r
, s
) > 0
13047 || !expr_const_in_range (&ep
, 0, 64, 2))
13050 imm
= ep
.X_add_number
>> 2;
13051 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13058 bfd_reloc_code_real_type r
[3];
13062 if (my_getSmallExpression (&ep
, r
, s
) > 0
13063 || !expr_const_in_range (&ep
, -8, 8, 0))
13066 imm
= ep
.X_add_number
;
13067 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13074 bfd_reloc_code_real_type r
[3];
13078 if (my_getSmallExpression (&ep
, r
, s
) > 0
13079 || expr_const_in_range (&ep
, -2, 2, 2)
13080 || !expr_const_in_range (&ep
, -258, 258, 2))
13083 imm
= ep
.X_add_number
>> 2;
13084 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13085 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13092 bfd_reloc_code_real_type r
[3];
13095 if (my_getSmallExpression (&ep
, r
, s
) > 0
13096 || !expr_const_in_range (&ep
, 0, 1, 0))
13103 as_bad (_("Internal error: bad microMIPS opcode "
13104 "(unknown extension operand type `m%c'): %s %s"),
13105 *args
, insn
->name
, insn
->args
);
13106 /* Further processing is fruitless. */
13111 case 'n': /* Register list for 32-bit lwm and swm. */
13112 gas_assert (mips_opts
.micromips
);
13114 /* A comma-separated list of registers and/or
13115 dash-separated contiguous ranges including
13116 at least one of ra and a set of one or more
13117 registers starting at s0 up to s7 and then
13118 s8 which have to be consecutive, e.g.:
13126 and any permutations of these. */
13127 unsigned int reglist
;
13131 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13134 if ((reglist
& 0x3f00ffff) != 0)
13137 ra
= (reglist
>> 27) & 0x10;
13138 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13140 if ((reglist
& -reglist
) != reglist
)
13143 imm
= (ffs (reglist
) - 1) | ra
;
13144 INSERT_OPERAND (1, RT
, *ip
, imm
);
13145 imm_expr
.X_op
= O_absent
;
13149 case '|': /* 4-bit trap code. */
13150 gas_assert (mips_opts
.micromips
);
13151 my_getExpression (&imm_expr
, s
);
13152 check_absolute_expr (ip
, &imm_expr
);
13153 if ((unsigned long) imm_expr
.X_add_number
13154 > MICROMIPSOP_MASK_TRAP
)
13155 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13156 (unsigned long) imm_expr
.X_add_number
,
13157 ip
->insn_mo
->name
);
13158 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13159 imm_expr
.X_op
= O_absent
;
13164 as_bad (_("Bad char = '%c'\n"), *args
);
13169 /* Args don't match. */
13171 insn_error
= _("Illegal operands");
13172 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13177 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13179 gas_assert (firstinsn
);
13180 need_delay_slot_ok
= FALSE
;
13189 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13191 /* This routine assembles an instruction into its binary format when
13192 assembling for the mips16. As a side effect, it sets one of the
13193 global variables imm_reloc or offset_reloc to the type of relocation
13194 to do if one of the operands is an address expression. It also sets
13195 forced_insn_length to the resulting instruction size in bytes if the
13196 user explicitly requested a small or extended instruction. */
13199 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13203 struct mips_opcode
*insn
;
13205 unsigned int regno
;
13206 unsigned int lastregno
= 0;
13212 forced_insn_length
= 0;
13214 for (s
= str
; ISLOWER (*s
); ++s
)
13226 if (s
[1] == 't' && s
[2] == ' ')
13229 forced_insn_length
= 2;
13233 else if (s
[1] == 'e' && s
[2] == ' ')
13236 forced_insn_length
= 4;
13240 /* Fall through. */
13242 insn_error
= _("unknown opcode");
13246 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13247 forced_insn_length
= 2;
13249 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13251 insn_error
= _("unrecognized opcode");
13260 gas_assert (strcmp (insn
->name
, str
) == 0);
13262 ok
= is_opcode_valid_16 (insn
);
13265 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13266 && strcmp (insn
->name
, insn
[1].name
) == 0)
13275 static char buf
[100];
13277 _("Opcode not supported on this processor: %s (%s)"),
13278 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13279 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13286 create_insn (ip
, insn
);
13287 imm_expr
.X_op
= O_absent
;
13288 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13289 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13290 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13291 imm2_expr
.X_op
= O_absent
;
13292 offset_expr
.X_op
= O_absent
;
13293 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13294 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13295 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13296 for (args
= insn
->args
; 1; ++args
)
13303 /* In this switch statement we call break if we did not find
13304 a match, continue if we did find a match, or return if we
13313 /* Stuff the immediate value in now, if we can. */
13314 if (imm_expr
.X_op
== O_constant
13315 && *imm_reloc
> BFD_RELOC_UNUSED
13316 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
13317 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
13318 && insn
->pinfo
!= INSN_MACRO
)
13322 switch (*offset_reloc
)
13324 case BFD_RELOC_MIPS16_HI16_S
:
13325 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
13328 case BFD_RELOC_MIPS16_HI16
:
13329 tmp
= imm_expr
.X_add_number
>> 16;
13332 case BFD_RELOC_MIPS16_LO16
:
13333 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
13337 case BFD_RELOC_UNUSED
:
13338 tmp
= imm_expr
.X_add_number
;
13344 *offset_reloc
= BFD_RELOC_UNUSED
;
13346 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13347 tmp
, TRUE
, forced_insn_length
== 2,
13348 forced_insn_length
== 4, &ip
->insn_opcode
,
13349 &ip
->use_extend
, &ip
->extend
);
13350 imm_expr
.X_op
= O_absent
;
13351 *imm_reloc
= BFD_RELOC_UNUSED
;
13365 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13368 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13384 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13386 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13390 /* Fall through. */
13401 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13403 if (c
== 'v' || c
== 'w')
13406 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13408 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13419 if (c
== 'v' || c
== 'w')
13421 regno
= mips16_to_32_reg_map
[lastregno
];
13435 regno
= mips32_to_16_reg_map
[regno
];
13440 regno
= ILLEGAL_REG
;
13445 regno
= ILLEGAL_REG
;
13450 regno
= ILLEGAL_REG
;
13455 if (regno
== AT
&& mips_opts
.at
)
13457 if (mips_opts
.at
== ATREG
)
13458 as_warn (_("used $at without \".set noat\""));
13460 as_warn (_("used $%u with \".set at=$%u\""),
13461 regno
, mips_opts
.at
);
13469 if (regno
== ILLEGAL_REG
)
13476 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13480 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13483 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13486 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13492 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13495 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13496 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13506 if (strncmp (s
, "$pc", 3) == 0)
13523 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13526 if (imm_expr
.X_op
!= O_constant
)
13528 forced_insn_length
= 4;
13529 ip
->use_extend
= TRUE
;
13534 /* We need to relax this instruction. */
13535 *offset_reloc
= *imm_reloc
;
13536 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13541 *imm_reloc
= BFD_RELOC_UNUSED
;
13542 /* Fall through. */
13549 my_getExpression (&imm_expr
, s
);
13550 if (imm_expr
.X_op
== O_register
)
13552 /* What we thought was an expression turned out to
13555 if (s
[0] == '(' && args
[1] == '(')
13557 /* It looks like the expression was omitted
13558 before a register indirection, which means
13559 that the expression is implicitly zero. We
13560 still set up imm_expr, so that we handle
13561 explicit extensions correctly. */
13562 imm_expr
.X_op
= O_constant
;
13563 imm_expr
.X_add_number
= 0;
13564 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13571 /* We need to relax this instruction. */
13572 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13581 /* We use offset_reloc rather than imm_reloc for the PC
13582 relative operands. This lets macros with both
13583 immediate and address operands work correctly. */
13584 my_getExpression (&offset_expr
, s
);
13586 if (offset_expr
.X_op
== O_register
)
13589 /* We need to relax this instruction. */
13590 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13594 case '6': /* break code */
13595 my_getExpression (&imm_expr
, s
);
13596 check_absolute_expr (ip
, &imm_expr
);
13597 if ((unsigned long) imm_expr
.X_add_number
> 63)
13598 as_warn (_("Invalid value for `%s' (%lu)"),
13600 (unsigned long) imm_expr
.X_add_number
);
13601 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13602 imm_expr
.X_op
= O_absent
;
13606 case 'a': /* 26 bit address */
13607 my_getExpression (&offset_expr
, s
);
13609 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13610 ip
->insn_opcode
<<= 16;
13613 case 'l': /* register list for entry macro */
13614 case 'L': /* register list for exit macro */
13624 unsigned int freg
, reg1
, reg2
;
13626 while (*s
== ' ' || *s
== ',')
13628 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13630 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13634 as_bad (_("can't parse register list"));
13644 if (!reg_lookup (&s
, freg
? RTYPE_FPU
13645 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
13647 as_bad (_("invalid register list"));
13651 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
13653 mask
&= ~ (7 << 3);
13656 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
13658 mask
&= ~ (7 << 3);
13661 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
13662 mask
|= (reg2
- 3) << 3;
13663 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
13664 mask
|= (reg2
- 15) << 1;
13665 else if (reg1
== RA
&& reg2
== RA
)
13669 as_bad (_("invalid register list"));
13673 /* The mask is filled in in the opcode table for the
13674 benefit of the disassembler. We remove it before
13675 applying the actual mask. */
13676 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
13677 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
13681 case 'm': /* Register list for save insn. */
13682 case 'M': /* Register list for restore insn. */
13685 int framesz
= 0, seen_framesz
= 0;
13686 int nargs
= 0, statics
= 0, sregs
= 0;
13690 unsigned int reg1
, reg2
;
13692 SKIP_SPACE_TABS (s
);
13695 SKIP_SPACE_TABS (s
);
13697 my_getExpression (&imm_expr
, s
);
13698 if (imm_expr
.X_op
== O_constant
)
13700 /* Handle the frame size. */
13703 as_bad (_("more than one frame size in list"));
13707 framesz
= imm_expr
.X_add_number
;
13708 imm_expr
.X_op
= O_absent
;
13713 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13715 as_bad (_("can't parse register list"));
13727 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
13730 as_bad (_("can't parse register list"));
13735 while (reg1
<= reg2
)
13737 if (reg1
>= 4 && reg1
<= 7)
13741 nargs
|= 1 << (reg1
- 4);
13743 /* statics $a0-$a3 */
13744 statics
|= 1 << (reg1
- 4);
13746 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
13749 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
13751 else if (reg1
== 31)
13753 /* Add $ra to insn. */
13758 as_bad (_("unexpected register in list"));
13766 /* Encode args/statics combination. */
13767 if (nargs
& statics
)
13768 as_bad (_("arg/static registers overlap"));
13769 else if (nargs
== 0xf)
13770 /* All $a0-$a3 are args. */
13771 opcode
|= MIPS16_ALL_ARGS
<< 16;
13772 else if (statics
== 0xf)
13773 /* All $a0-$a3 are statics. */
13774 opcode
|= MIPS16_ALL_STATICS
<< 16;
13777 int narg
= 0, nstat
= 0;
13779 /* Count arg registers. */
13780 while (nargs
& 0x1)
13786 as_bad (_("invalid arg register list"));
13788 /* Count static registers. */
13789 while (statics
& 0x8)
13791 statics
= (statics
<< 1) & 0xf;
13795 as_bad (_("invalid static register list"));
13797 /* Encode args/statics. */
13798 opcode
|= ((narg
<< 2) | nstat
) << 16;
13801 /* Encode $s0/$s1. */
13802 if (sregs
& (1 << 0)) /* $s0 */
13804 if (sregs
& (1 << 1)) /* $s1 */
13810 /* Count regs $s2-$s8. */
13818 as_bad (_("invalid static register list"));
13819 /* Encode $s2-$s8. */
13820 opcode
|= nsreg
<< 24;
13823 /* Encode frame size. */
13825 as_bad (_("missing frame size"));
13826 else if ((framesz
& 7) != 0 || framesz
< 0
13827 || framesz
> 0xff * 8)
13828 as_bad (_("invalid frame size"));
13829 else if (framesz
!= 128 || (opcode
>> 16) != 0)
13832 opcode
|= (((framesz
& 0xf0) << 16)
13833 | (framesz
& 0x0f));
13836 /* Finally build the instruction. */
13837 if ((opcode
>> 16) != 0 || framesz
== 0)
13839 ip
->use_extend
= TRUE
;
13840 ip
->extend
= opcode
>> 16;
13842 ip
->insn_opcode
|= opcode
& 0x7f;
13846 case 'e': /* extend code */
13847 my_getExpression (&imm_expr
, s
);
13848 check_absolute_expr (ip
, &imm_expr
);
13849 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
13851 as_warn (_("Invalid value for `%s' (%lu)"),
13853 (unsigned long) imm_expr
.X_add_number
);
13854 imm_expr
.X_add_number
&= 0x7ff;
13856 ip
->insn_opcode
|= imm_expr
.X_add_number
;
13857 imm_expr
.X_op
= O_absent
;
13867 /* Args don't match. */
13868 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
13869 strcmp (insn
->name
, insn
[1].name
) == 0)
13876 insn_error
= _("illegal operands");
13882 /* This structure holds information we know about a mips16 immediate
13885 struct mips16_immed_operand
13887 /* The type code used in the argument string in the opcode table. */
13889 /* The number of bits in the short form of the opcode. */
13891 /* The number of bits in the extended form of the opcode. */
13893 /* The amount by which the short form is shifted when it is used;
13894 for example, the sw instruction has a shift count of 2. */
13896 /* The amount by which the short form is shifted when it is stored
13897 into the instruction code. */
13899 /* Non-zero if the short form is unsigned. */
13901 /* Non-zero if the extended form is unsigned. */
13903 /* Non-zero if the value is PC relative. */
13907 /* The mips16 immediate operand types. */
13909 static const struct mips16_immed_operand mips16_immed_operands
[] =
13911 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13912 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13913 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13914 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13915 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
13916 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13917 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13918 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13919 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13920 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
13921 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13922 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13923 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13924 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
13925 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13926 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13927 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13928 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13929 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
13930 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
13931 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
13934 #define MIPS16_NUM_IMMED \
13935 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13937 /* Handle a mips16 instruction with an immediate value. This or's the
13938 small immediate value into *INSN. It sets *USE_EXTEND to indicate
13939 whether an extended value is needed; if one is needed, it sets
13940 *EXTEND to the value. The argument type is TYPE. The value is VAL.
13941 If SMALL is true, an unextended opcode was explicitly requested.
13942 If EXT is true, an extended opcode was explicitly requested. If
13943 WARN is true, warn if EXT does not match reality. */
13946 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
13947 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
13948 unsigned long *insn
, bfd_boolean
*use_extend
,
13949 unsigned short *extend
)
13951 const struct mips16_immed_operand
*op
;
13952 int mintiny
, maxtiny
;
13953 bfd_boolean needext
;
13955 op
= mips16_immed_operands
;
13956 while (op
->type
!= type
)
13959 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13964 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13967 maxtiny
= 1 << op
->nbits
;
13972 maxtiny
= (1 << op
->nbits
) - 1;
13977 mintiny
= - (1 << (op
->nbits
- 1));
13978 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13981 /* Branch offsets have an implicit 0 in the lowest bit. */
13982 if (type
== 'p' || type
== 'q')
13985 if ((val
& ((1 << op
->shift
) - 1)) != 0
13986 || val
< (mintiny
<< op
->shift
)
13987 || val
> (maxtiny
<< op
->shift
))
13992 if (warn
&& ext
&& ! needext
)
13993 as_warn_where (file
, line
,
13994 _("extended operand requested but not required"));
13995 if (small
&& needext
)
13996 as_bad_where (file
, line
, _("invalid unextended operand value"));
13998 if (small
|| (! ext
&& ! needext
))
14002 *use_extend
= FALSE
;
14003 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14004 insnval
<<= op
->op_shift
;
14009 long minext
, maxext
;
14015 maxext
= (1 << op
->extbits
) - 1;
14019 minext
= - (1 << (op
->extbits
- 1));
14020 maxext
= (1 << (op
->extbits
- 1)) - 1;
14022 if (val
< minext
|| val
> maxext
)
14023 as_bad_where (file
, line
,
14024 _("operand value out of range for instruction"));
14026 *use_extend
= TRUE
;
14027 if (op
->extbits
== 16)
14029 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14032 else if (op
->extbits
== 15)
14034 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14039 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14043 *extend
= (unsigned short) extval
;
14048 struct percent_op_match
14051 bfd_reloc_code_real_type reloc
;
14054 static const struct percent_op_match mips_percent_op
[] =
14056 {"%lo", BFD_RELOC_LO16
},
14058 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14059 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14060 {"%call16", BFD_RELOC_MIPS_CALL16
},
14061 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14062 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14063 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14064 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14065 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14066 {"%got", BFD_RELOC_MIPS_GOT16
},
14067 {"%gp_rel", BFD_RELOC_GPREL16
},
14068 {"%half", BFD_RELOC_16
},
14069 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14070 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14071 {"%neg", BFD_RELOC_MIPS_SUB
},
14072 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14073 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14074 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14075 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14076 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14077 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14078 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14080 {"%hi", BFD_RELOC_HI16_S
}
14083 static const struct percent_op_match mips16_percent_op
[] =
14085 {"%lo", BFD_RELOC_MIPS16_LO16
},
14086 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14087 {"%got", BFD_RELOC_MIPS16_GOT16
},
14088 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14089 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14090 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14091 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14092 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14093 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14094 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14095 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14096 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14100 /* Return true if *STR points to a relocation operator. When returning true,
14101 move *STR over the operator and store its relocation code in *RELOC.
14102 Leave both *STR and *RELOC alone when returning false. */
14105 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14107 const struct percent_op_match
*percent_op
;
14110 if (mips_opts
.mips16
)
14112 percent_op
= mips16_percent_op
;
14113 limit
= ARRAY_SIZE (mips16_percent_op
);
14117 percent_op
= mips_percent_op
;
14118 limit
= ARRAY_SIZE (mips_percent_op
);
14121 for (i
= 0; i
< limit
; i
++)
14122 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14124 int len
= strlen (percent_op
[i
].str
);
14126 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14129 *str
+= strlen (percent_op
[i
].str
);
14130 *reloc
= percent_op
[i
].reloc
;
14132 /* Check whether the output BFD supports this relocation.
14133 If not, issue an error and fall back on something safe. */
14134 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14136 as_bad (_("relocation %s isn't supported by the current ABI"),
14137 percent_op
[i
].str
);
14138 *reloc
= BFD_RELOC_UNUSED
;
14146 /* Parse string STR as a 16-bit relocatable operand. Store the
14147 expression in *EP and the relocations in the array starting
14148 at RELOC. Return the number of relocation operators used.
14150 On exit, EXPR_END points to the first character after the expression. */
14153 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14156 bfd_reloc_code_real_type reversed_reloc
[3];
14157 size_t reloc_index
, i
;
14158 int crux_depth
, str_depth
;
14161 /* Search for the start of the main expression, recoding relocations
14162 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14163 of the main expression and with CRUX_DEPTH containing the number
14164 of open brackets at that point. */
14171 crux_depth
= str_depth
;
14173 /* Skip over whitespace and brackets, keeping count of the number
14175 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14180 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14181 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14183 my_getExpression (ep
, crux
);
14186 /* Match every open bracket. */
14187 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14191 if (crux_depth
> 0)
14192 as_bad (_("unclosed '('"));
14196 if (reloc_index
!= 0)
14198 prev_reloc_op_frag
= frag_now
;
14199 for (i
= 0; i
< reloc_index
; i
++)
14200 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14203 return reloc_index
;
14207 my_getExpression (expressionS
*ep
, char *str
)
14211 save_in
= input_line_pointer
;
14212 input_line_pointer
= str
;
14214 expr_end
= input_line_pointer
;
14215 input_line_pointer
= save_in
;
14219 md_atof (int type
, char *litP
, int *sizeP
)
14221 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14225 md_number_to_chars (char *buf
, valueT val
, int n
)
14227 if (target_big_endian
)
14228 number_to_chars_bigendian (buf
, val
, n
);
14230 number_to_chars_littleendian (buf
, val
, n
);
14234 static int support_64bit_objects(void)
14236 const char **list
, **l
;
14239 list
= bfd_target_list ();
14240 for (l
= list
; *l
!= NULL
; l
++)
14241 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14242 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14244 yes
= (*l
!= NULL
);
14248 #endif /* OBJ_ELF */
14250 const char *md_shortopts
= "O::g::G:";
14254 OPTION_MARCH
= OPTION_MD_BASE
,
14276 OPTION_NO_SMARTMIPS
,
14280 OPTION_NO_MICROMIPS
,
14283 OPTION_COMPAT_ARCH_BASE
,
14292 OPTION_M7000_HILO_FIX
,
14293 OPTION_MNO_7000_HILO_FIX
,
14296 OPTION_FIX_LOONGSON2F_JUMP
,
14297 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14298 OPTION_FIX_LOONGSON2F_NOP
,
14299 OPTION_NO_FIX_LOONGSON2F_NOP
,
14301 OPTION_NO_FIX_VR4120
,
14303 OPTION_NO_FIX_VR4130
,
14304 OPTION_FIX_CN63XXP1
,
14305 OPTION_NO_FIX_CN63XXP1
,
14312 OPTION_CONSTRUCT_FLOATS
,
14313 OPTION_NO_CONSTRUCT_FLOATS
,
14316 OPTION_RELAX_BRANCH
,
14317 OPTION_NO_RELAX_BRANCH
,
14324 OPTION_SINGLE_FLOAT
,
14325 OPTION_DOUBLE_FLOAT
,
14328 OPTION_CALL_SHARED
,
14329 OPTION_CALL_NONPIC
,
14339 OPTION_MVXWORKS_PIC
,
14340 #endif /* OBJ_ELF */
14344 struct option md_longopts
[] =
14346 /* Options which specify architecture. */
14347 {"march", required_argument
, NULL
, OPTION_MARCH
},
14348 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14349 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14350 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14351 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14352 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14353 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14354 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14355 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14356 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14357 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14358 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14360 /* Options which specify Application Specific Extensions (ASEs). */
14361 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14362 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14363 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14364 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14365 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14366 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14367 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14368 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14369 {"mmt", no_argument
, NULL
, OPTION_MT
},
14370 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14371 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14372 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14373 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14374 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14375 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14376 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14377 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
14378 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
14380 /* Old-style architecture options. Don't add more of these. */
14381 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14382 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14383 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14384 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14385 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14386 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14387 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14388 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14390 /* Options which enable bug fixes. */
14391 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14392 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14393 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14394 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14395 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14396 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14397 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14398 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14399 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14400 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14401 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14402 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14403 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14404 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14405 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14407 /* Miscellaneous options. */
14408 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14409 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14410 {"break", no_argument
, NULL
, OPTION_BREAK
},
14411 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14412 {"EB", no_argument
, NULL
, OPTION_EB
},
14413 {"EL", no_argument
, NULL
, OPTION_EL
},
14414 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14415 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14416 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14417 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14418 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14419 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14420 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14421 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14422 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14423 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14424 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14425 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14426 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14427 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14428 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14429 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14431 /* Strictly speaking this next option is ELF specific,
14432 but we allow it for other ports as well in order to
14433 make testing easier. */
14434 {"32", no_argument
, NULL
, OPTION_32
},
14436 /* ELF-specific options. */
14438 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14439 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14440 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14441 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14442 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14443 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14444 {"n32", no_argument
, NULL
, OPTION_N32
},
14445 {"64", no_argument
, NULL
, OPTION_64
},
14446 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14447 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14448 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14449 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14450 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14451 #endif /* OBJ_ELF */
14453 {NULL
, no_argument
, NULL
, 0}
14455 size_t md_longopts_size
= sizeof (md_longopts
);
14457 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14458 NEW_VALUE. Warn if another value was already specified. Note:
14459 we have to defer parsing the -march and -mtune arguments in order
14460 to handle 'from-abi' correctly, since the ABI might be specified
14461 in a later argument. */
14464 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14466 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14467 as_warn (_("A different %s was already specified, is now %s"),
14468 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14471 *string_ptr
= new_value
;
14475 md_parse_option (int c
, char *arg
)
14479 case OPTION_CONSTRUCT_FLOATS
:
14480 mips_disable_float_construction
= 0;
14483 case OPTION_NO_CONSTRUCT_FLOATS
:
14484 mips_disable_float_construction
= 1;
14496 target_big_endian
= 1;
14500 target_big_endian
= 0;
14506 else if (arg
[0] == '0')
14508 else if (arg
[0] == '1')
14518 mips_debug
= atoi (arg
);
14522 file_mips_isa
= ISA_MIPS1
;
14526 file_mips_isa
= ISA_MIPS2
;
14530 file_mips_isa
= ISA_MIPS3
;
14534 file_mips_isa
= ISA_MIPS4
;
14538 file_mips_isa
= ISA_MIPS5
;
14541 case OPTION_MIPS32
:
14542 file_mips_isa
= ISA_MIPS32
;
14545 case OPTION_MIPS32R2
:
14546 file_mips_isa
= ISA_MIPS32R2
;
14549 case OPTION_MIPS64R2
:
14550 file_mips_isa
= ISA_MIPS64R2
;
14553 case OPTION_MIPS64
:
14554 file_mips_isa
= ISA_MIPS64
;
14558 mips_set_option_string (&mips_tune_string
, arg
);
14562 mips_set_option_string (&mips_arch_string
, arg
);
14566 mips_set_option_string (&mips_arch_string
, "4650");
14567 mips_set_option_string (&mips_tune_string
, "4650");
14570 case OPTION_NO_M4650
:
14574 mips_set_option_string (&mips_arch_string
, "4010");
14575 mips_set_option_string (&mips_tune_string
, "4010");
14578 case OPTION_NO_M4010
:
14582 mips_set_option_string (&mips_arch_string
, "4100");
14583 mips_set_option_string (&mips_tune_string
, "4100");
14586 case OPTION_NO_M4100
:
14590 mips_set_option_string (&mips_arch_string
, "3900");
14591 mips_set_option_string (&mips_tune_string
, "3900");
14594 case OPTION_NO_M3900
:
14598 mips_opts
.ase_mdmx
= 1;
14601 case OPTION_NO_MDMX
:
14602 mips_opts
.ase_mdmx
= 0;
14606 mips_opts
.ase_dsp
= 1;
14607 mips_opts
.ase_dspr2
= 0;
14610 case OPTION_NO_DSP
:
14611 mips_opts
.ase_dsp
= 0;
14612 mips_opts
.ase_dspr2
= 0;
14616 mips_opts
.ase_dspr2
= 1;
14617 mips_opts
.ase_dsp
= 1;
14620 case OPTION_NO_DSPR2
:
14621 mips_opts
.ase_dspr2
= 0;
14622 mips_opts
.ase_dsp
= 0;
14626 mips_opts
.ase_mt
= 1;
14630 mips_opts
.ase_mt
= 0;
14634 mips_opts
.ase_mcu
= 1;
14637 case OPTION_NO_MCU
:
14638 mips_opts
.ase_mcu
= 0;
14641 case OPTION_MICROMIPS
:
14642 if (mips_opts
.mips16
== 1)
14644 as_bad (_("-mmicromips cannot be used with -mips16"));
14647 mips_opts
.micromips
= 1;
14648 mips_no_prev_insn ();
14651 case OPTION_NO_MICROMIPS
:
14652 mips_opts
.micromips
= 0;
14653 mips_no_prev_insn ();
14656 case OPTION_MIPS16
:
14657 if (mips_opts
.micromips
== 1)
14659 as_bad (_("-mips16 cannot be used with -micromips"));
14662 mips_opts
.mips16
= 1;
14663 mips_no_prev_insn ();
14666 case OPTION_NO_MIPS16
:
14667 mips_opts
.mips16
= 0;
14668 mips_no_prev_insn ();
14671 case OPTION_MIPS3D
:
14672 mips_opts
.ase_mips3d
= 1;
14675 case OPTION_NO_MIPS3D
:
14676 mips_opts
.ase_mips3d
= 0;
14679 case OPTION_SMARTMIPS
:
14680 mips_opts
.ase_smartmips
= 1;
14683 case OPTION_NO_SMARTMIPS
:
14684 mips_opts
.ase_smartmips
= 0;
14687 case OPTION_FIX_24K
:
14691 case OPTION_NO_FIX_24K
:
14695 case OPTION_FIX_LOONGSON2F_JUMP
:
14696 mips_fix_loongson2f_jump
= TRUE
;
14699 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14700 mips_fix_loongson2f_jump
= FALSE
;
14703 case OPTION_FIX_LOONGSON2F_NOP
:
14704 mips_fix_loongson2f_nop
= TRUE
;
14707 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14708 mips_fix_loongson2f_nop
= FALSE
;
14711 case OPTION_FIX_VR4120
:
14712 mips_fix_vr4120
= 1;
14715 case OPTION_NO_FIX_VR4120
:
14716 mips_fix_vr4120
= 0;
14719 case OPTION_FIX_VR4130
:
14720 mips_fix_vr4130
= 1;
14723 case OPTION_NO_FIX_VR4130
:
14724 mips_fix_vr4130
= 0;
14727 case OPTION_FIX_CN63XXP1
:
14728 mips_fix_cn63xxp1
= TRUE
;
14731 case OPTION_NO_FIX_CN63XXP1
:
14732 mips_fix_cn63xxp1
= FALSE
;
14735 case OPTION_RELAX_BRANCH
:
14736 mips_relax_branch
= 1;
14739 case OPTION_NO_RELAX_BRANCH
:
14740 mips_relax_branch
= 0;
14743 case OPTION_MSHARED
:
14744 mips_in_shared
= TRUE
;
14747 case OPTION_MNO_SHARED
:
14748 mips_in_shared
= FALSE
;
14751 case OPTION_MSYM32
:
14752 mips_opts
.sym32
= TRUE
;
14755 case OPTION_MNO_SYM32
:
14756 mips_opts
.sym32
= FALSE
;
14760 /* When generating ELF code, we permit -KPIC and -call_shared to
14761 select SVR4_PIC, and -non_shared to select no PIC. This is
14762 intended to be compatible with Irix 5. */
14763 case OPTION_CALL_SHARED
:
14766 as_bad (_("-call_shared is supported only for ELF format"));
14769 mips_pic
= SVR4_PIC
;
14770 mips_abicalls
= TRUE
;
14773 case OPTION_CALL_NONPIC
:
14776 as_bad (_("-call_nonpic is supported only for ELF format"));
14780 mips_abicalls
= TRUE
;
14783 case OPTION_NON_SHARED
:
14786 as_bad (_("-non_shared is supported only for ELF format"));
14790 mips_abicalls
= FALSE
;
14793 /* The -xgot option tells the assembler to use 32 bit offsets
14794 when accessing the got in SVR4_PIC mode. It is for Irix
14799 #endif /* OBJ_ELF */
14802 g_switch_value
= atoi (arg
);
14806 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14810 mips_abi
= O32_ABI
;
14811 /* We silently ignore -32 for non-ELF targets. This greatly
14812 simplifies the construction of the MIPS GAS test cases. */
14819 as_bad (_("-n32 is supported for ELF format only"));
14822 mips_abi
= N32_ABI
;
14828 as_bad (_("-64 is supported for ELF format only"));
14831 mips_abi
= N64_ABI
;
14832 if (!support_64bit_objects())
14833 as_fatal (_("No compiled in support for 64 bit object file format"));
14835 #endif /* OBJ_ELF */
14838 file_mips_gp32
= 1;
14842 file_mips_gp32
= 0;
14846 file_mips_fp32
= 1;
14850 file_mips_fp32
= 0;
14853 case OPTION_SINGLE_FLOAT
:
14854 file_mips_single_float
= 1;
14857 case OPTION_DOUBLE_FLOAT
:
14858 file_mips_single_float
= 0;
14861 case OPTION_SOFT_FLOAT
:
14862 file_mips_soft_float
= 1;
14865 case OPTION_HARD_FLOAT
:
14866 file_mips_soft_float
= 0;
14873 as_bad (_("-mabi is supported for ELF format only"));
14876 if (strcmp (arg
, "32") == 0)
14877 mips_abi
= O32_ABI
;
14878 else if (strcmp (arg
, "o64") == 0)
14879 mips_abi
= O64_ABI
;
14880 else if (strcmp (arg
, "n32") == 0)
14881 mips_abi
= N32_ABI
;
14882 else if (strcmp (arg
, "64") == 0)
14884 mips_abi
= N64_ABI
;
14885 if (! support_64bit_objects())
14886 as_fatal (_("No compiled in support for 64 bit object file "
14889 else if (strcmp (arg
, "eabi") == 0)
14890 mips_abi
= EABI_ABI
;
14893 as_fatal (_("invalid abi -mabi=%s"), arg
);
14897 #endif /* OBJ_ELF */
14899 case OPTION_M7000_HILO_FIX
:
14900 mips_7000_hilo_fix
= TRUE
;
14903 case OPTION_MNO_7000_HILO_FIX
:
14904 mips_7000_hilo_fix
= FALSE
;
14908 case OPTION_MDEBUG
:
14909 mips_flag_mdebug
= TRUE
;
14912 case OPTION_NO_MDEBUG
:
14913 mips_flag_mdebug
= FALSE
;
14917 mips_flag_pdr
= TRUE
;
14920 case OPTION_NO_PDR
:
14921 mips_flag_pdr
= FALSE
;
14924 case OPTION_MVXWORKS_PIC
:
14925 mips_pic
= VXWORKS_PIC
;
14927 #endif /* OBJ_ELF */
14933 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14938 /* Set up globals to generate code for the ISA or processor
14939 described by INFO. */
14942 mips_set_architecture (const struct mips_cpu_info
*info
)
14946 file_mips_arch
= info
->cpu
;
14947 mips_opts
.arch
= info
->cpu
;
14948 mips_opts
.isa
= info
->isa
;
14953 /* Likewise for tuning. */
14956 mips_set_tune (const struct mips_cpu_info
*info
)
14959 mips_tune
= info
->cpu
;
14964 mips_after_parse_args (void)
14966 const struct mips_cpu_info
*arch_info
= 0;
14967 const struct mips_cpu_info
*tune_info
= 0;
14969 /* GP relative stuff not working for PE */
14970 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14972 if (g_switch_seen
&& g_switch_value
!= 0)
14973 as_bad (_("-G not supported in this configuration."));
14974 g_switch_value
= 0;
14977 if (mips_abi
== NO_ABI
)
14978 mips_abi
= MIPS_DEFAULT_ABI
;
14980 /* The following code determines the architecture and register size.
14981 Similar code was added to GCC 3.3 (see override_options() in
14982 config/mips/mips.c). The GAS and GCC code should be kept in sync
14983 as much as possible. */
14985 if (mips_arch_string
!= 0)
14986 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14988 if (file_mips_isa
!= ISA_UNKNOWN
)
14990 /* Handle -mipsN. At this point, file_mips_isa contains the
14991 ISA level specified by -mipsN, while arch_info->isa contains
14992 the -march selection (if any). */
14993 if (arch_info
!= 0)
14995 /* -march takes precedence over -mipsN, since it is more descriptive.
14996 There's no harm in specifying both as long as the ISA levels
14998 if (file_mips_isa
!= arch_info
->isa
)
14999 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15000 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15001 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15004 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15007 if (arch_info
== 0)
15008 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15010 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15011 as_bad (_("-march=%s is not compatible with the selected ABI"),
15014 mips_set_architecture (arch_info
);
15016 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15017 if (mips_tune_string
!= 0)
15018 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15020 if (tune_info
== 0)
15021 mips_set_tune (arch_info
);
15023 mips_set_tune (tune_info
);
15025 if (file_mips_gp32
>= 0)
15027 /* The user specified the size of the integer registers. Make sure
15028 it agrees with the ABI and ISA. */
15029 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15030 as_bad (_("-mgp64 used with a 32-bit processor"));
15031 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15032 as_bad (_("-mgp32 used with a 64-bit ABI"));
15033 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15034 as_bad (_("-mgp64 used with a 32-bit ABI"));
15038 /* Infer the integer register size from the ABI and processor.
15039 Restrict ourselves to 32-bit registers if that's all the
15040 processor has, or if the ABI cannot handle 64-bit registers. */
15041 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15042 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15045 switch (file_mips_fp32
)
15049 /* No user specified float register size.
15050 ??? GAS treats single-float processors as though they had 64-bit
15051 float registers (although it complains when double-precision
15052 instructions are used). As things stand, saying they have 32-bit
15053 registers would lead to spurious "register must be even" messages.
15054 So here we assume float registers are never smaller than the
15056 if (file_mips_gp32
== 0)
15057 /* 64-bit integer registers implies 64-bit float registers. */
15058 file_mips_fp32
= 0;
15059 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
15060 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15061 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15062 file_mips_fp32
= 0;
15064 /* 32-bit float registers. */
15065 file_mips_fp32
= 1;
15068 /* The user specified the size of the float registers. Check if it
15069 agrees with the ABI and ISA. */
15071 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15072 as_bad (_("-mfp64 used with a 32-bit fpu"));
15073 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15074 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15075 as_warn (_("-mfp64 used with a 32-bit ABI"));
15078 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15079 as_warn (_("-mfp32 used with a 64-bit ABI"));
15083 /* End of GCC-shared inference code. */
15085 /* This flag is set when we have a 64-bit capable CPU but use only
15086 32-bit wide registers. Note that EABI does not use it. */
15087 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15088 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15089 || mips_abi
== O32_ABI
))
15090 mips_32bitmode
= 1;
15092 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15093 as_bad (_("trap exception not supported at ISA 1"));
15095 /* If the selected architecture includes support for ASEs, enable
15096 generation of code for them. */
15097 if (mips_opts
.mips16
== -1)
15098 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15099 if (mips_opts
.micromips
== -1)
15100 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15101 if (mips_opts
.ase_mips3d
== -1)
15102 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
15103 && file_mips_fp32
== 0) ? 1 : 0;
15104 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
15105 as_bad (_("-mfp32 used with -mips3d"));
15107 if (mips_opts
.ase_mdmx
== -1)
15108 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
15109 && file_mips_fp32
== 0) ? 1 : 0;
15110 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
15111 as_bad (_("-mfp32 used with -mdmx"));
15113 if (mips_opts
.ase_smartmips
== -1)
15114 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15115 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15116 as_warn (_("%s ISA does not support SmartMIPS"),
15117 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15119 if (mips_opts
.ase_dsp
== -1)
15120 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15121 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15122 as_warn (_("%s ISA does not support DSP ASE"),
15123 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15125 if (mips_opts
.ase_dspr2
== -1)
15127 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15128 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15130 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15131 as_warn (_("%s ISA does not support DSP R2 ASE"),
15132 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15134 if (mips_opts
.ase_mt
== -1)
15135 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15136 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15137 as_warn (_("%s ISA does not support MT ASE"),
15138 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15140 if (mips_opts
.ase_mcu
== -1)
15141 mips_opts
.ase_mcu
= (arch_info
->flags
& MIPS_CPU_ASE_MCU
) ? 1 : 0;
15142 if (mips_opts
.ase_mcu
&& !ISA_SUPPORTS_MCU_ASE
)
15143 as_warn (_("%s ISA does not support MCU ASE"),
15144 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15146 file_mips_isa
= mips_opts
.isa
;
15147 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15148 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15149 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15150 file_ase_dsp
= mips_opts
.ase_dsp
;
15151 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15152 file_ase_mt
= mips_opts
.ase_mt
;
15153 mips_opts
.gp32
= file_mips_gp32
;
15154 mips_opts
.fp32
= file_mips_fp32
;
15155 mips_opts
.soft_float
= file_mips_soft_float
;
15156 mips_opts
.single_float
= file_mips_single_float
;
15158 if (mips_flag_mdebug
< 0)
15160 #ifdef OBJ_MAYBE_ECOFF
15161 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15162 mips_flag_mdebug
= 1;
15164 #endif /* OBJ_MAYBE_ECOFF */
15165 mips_flag_mdebug
= 0;
15170 mips_init_after_args (void)
15172 /* initialize opcodes */
15173 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15174 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15178 md_pcrel_from (fixS
*fixP
)
15180 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15181 switch (fixP
->fx_r_type
)
15183 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15184 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15185 /* Return the address of the delay slot. */
15188 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15189 case BFD_RELOC_MICROMIPS_JMP
:
15190 case BFD_RELOC_16_PCREL_S2
:
15191 case BFD_RELOC_MIPS_JMP
:
15192 /* Return the address of the delay slot. */
15196 /* We have no relocation type for PC relative MIPS16 instructions. */
15197 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15199 _("PC relative MIPS16 instruction references a different section"));
15204 /* This is called before the symbol table is processed. In order to
15205 work with gcc when using mips-tfile, we must keep all local labels.
15206 However, in other cases, we want to discard them. If we were
15207 called with -g, but we didn't see any debugging information, it may
15208 mean that gcc is smuggling debugging information through to
15209 mips-tfile, in which case we must generate all local labels. */
15212 mips_frob_file_before_adjust (void)
15214 #ifndef NO_ECOFF_DEBUGGING
15215 if (ECOFF_DEBUGGING
15217 && ! ecoff_debugging_seen
)
15218 flag_keep_locals
= 1;
15222 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15223 the corresponding LO16 reloc. This is called before md_apply_fix and
15224 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15225 relocation operators.
15227 For our purposes, a %lo() expression matches a %got() or %hi()
15230 (a) it refers to the same symbol; and
15231 (b) the offset applied in the %lo() expression is no lower than
15232 the offset applied in the %got() or %hi().
15234 (b) allows us to cope with code like:
15237 lh $4,%lo(foo+2)($4)
15239 ...which is legal on RELA targets, and has a well-defined behaviour
15240 if the user knows that adding 2 to "foo" will not induce a carry to
15243 When several %lo()s match a particular %got() or %hi(), we use the
15244 following rules to distinguish them:
15246 (1) %lo()s with smaller offsets are a better match than %lo()s with
15249 (2) %lo()s with no matching %got() or %hi() are better than those
15250 that already have a matching %got() or %hi().
15252 (3) later %lo()s are better than earlier %lo()s.
15254 These rules are applied in order.
15256 (1) means, among other things, that %lo()s with identical offsets are
15257 chosen if they exist.
15259 (2) means that we won't associate several high-part relocations with
15260 the same low-part relocation unless there's no alternative. Having
15261 several high parts for the same low part is a GNU extension; this rule
15262 allows careful users to avoid it.
15264 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15265 with the last high-part relocation being at the front of the list.
15266 It therefore makes sense to choose the last matching low-part
15267 relocation, all other things being equal. It's also easier
15268 to code that way. */
15271 mips_frob_file (void)
15273 struct mips_hi_fixup
*l
;
15274 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15276 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15278 segment_info_type
*seginfo
;
15279 bfd_boolean matched_lo_p
;
15280 fixS
**hi_pos
, **lo_pos
, **pos
;
15282 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15284 /* If a GOT16 relocation turns out to be against a global symbol,
15285 there isn't supposed to be a matching LO. */
15286 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15287 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
15290 /* Check quickly whether the next fixup happens to be a matching %lo. */
15291 if (fixup_has_matching_lo_p (l
->fixp
))
15294 seginfo
= seg_info (l
->seg
);
15296 /* Set HI_POS to the position of this relocation in the chain.
15297 Set LO_POS to the position of the chosen low-part relocation.
15298 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15299 relocation that matches an immediately-preceding high-part
15303 matched_lo_p
= FALSE
;
15304 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15306 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15308 if (*pos
== l
->fixp
)
15311 if ((*pos
)->fx_r_type
== looking_for_rtype
15312 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15313 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15315 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15317 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15320 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15321 && fixup_has_matching_lo_p (*pos
));
15324 /* If we found a match, remove the high-part relocation from its
15325 current position and insert it before the low-part relocation.
15326 Make the offsets match so that fixup_has_matching_lo_p()
15329 We don't warn about unmatched high-part relocations since some
15330 versions of gcc have been known to emit dead "lui ...%hi(...)"
15332 if (lo_pos
!= NULL
)
15334 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15335 if (l
->fixp
->fx_next
!= *lo_pos
)
15337 *hi_pos
= l
->fixp
->fx_next
;
15338 l
->fixp
->fx_next
= *lo_pos
;
15345 /* We may have combined relocations without symbols in the N32/N64 ABI.
15346 We have to prevent gas from dropping them. */
15349 mips_force_relocation (fixS
*fixp
)
15351 if (generic_force_reloc (fixp
))
15354 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15355 so that the linker relaxation can update targets. */
15356 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15357 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15358 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15362 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
15363 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
15364 || hi16_reloc_p (fixp
->fx_r_type
)
15365 || lo16_reloc_p (fixp
->fx_r_type
)))
15371 /* Apply a fixup to the object file. */
15374 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15378 reloc_howto_type
*howto
;
15380 /* We ignore generic BFD relocations we don't know about. */
15381 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15385 gas_assert (fixP
->fx_size
== 2
15386 || fixP
->fx_size
== 4
15387 || fixP
->fx_r_type
== BFD_RELOC_16
15388 || fixP
->fx_r_type
== BFD_RELOC_64
15389 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15390 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15391 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15392 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15393 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15394 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15396 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
15398 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15399 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15400 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15401 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
15403 /* Don't treat parts of a composite relocation as done. There are two
15406 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15407 should nevertheless be emitted if the first part is.
15409 (2) In normal usage, composite relocations are never assembly-time
15410 constants. The easiest way of dealing with the pathological
15411 exceptions is to generate a relocation against STN_UNDEF and
15412 leave everything up to the linker. */
15413 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15416 switch (fixP
->fx_r_type
)
15418 case BFD_RELOC_MIPS_TLS_GD
:
15419 case BFD_RELOC_MIPS_TLS_LDM
:
15420 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15421 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15422 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15423 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15424 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15425 case BFD_RELOC_MIPS_TLS_TPREL32
:
15426 case BFD_RELOC_MIPS_TLS_TPREL64
:
15427 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15428 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15429 case BFD_RELOC_MICROMIPS_TLS_GD
:
15430 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15431 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15432 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15433 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15434 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15435 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15436 case BFD_RELOC_MIPS16_TLS_GD
:
15437 case BFD_RELOC_MIPS16_TLS_LDM
:
15438 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15439 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15440 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15441 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15442 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15443 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15446 case BFD_RELOC_MIPS_JMP
:
15447 case BFD_RELOC_MIPS_SHIFT5
:
15448 case BFD_RELOC_MIPS_SHIFT6
:
15449 case BFD_RELOC_MIPS_GOT_DISP
:
15450 case BFD_RELOC_MIPS_GOT_PAGE
:
15451 case BFD_RELOC_MIPS_GOT_OFST
:
15452 case BFD_RELOC_MIPS_SUB
:
15453 case BFD_RELOC_MIPS_INSERT_A
:
15454 case BFD_RELOC_MIPS_INSERT_B
:
15455 case BFD_RELOC_MIPS_DELETE
:
15456 case BFD_RELOC_MIPS_HIGHEST
:
15457 case BFD_RELOC_MIPS_HIGHER
:
15458 case BFD_RELOC_MIPS_SCN_DISP
:
15459 case BFD_RELOC_MIPS_REL16
:
15460 case BFD_RELOC_MIPS_RELGOT
:
15461 case BFD_RELOC_MIPS_JALR
:
15462 case BFD_RELOC_HI16
:
15463 case BFD_RELOC_HI16_S
:
15464 case BFD_RELOC_GPREL16
:
15465 case BFD_RELOC_MIPS_LITERAL
:
15466 case BFD_RELOC_MIPS_CALL16
:
15467 case BFD_RELOC_MIPS_GOT16
:
15468 case BFD_RELOC_GPREL32
:
15469 case BFD_RELOC_MIPS_GOT_HI16
:
15470 case BFD_RELOC_MIPS_GOT_LO16
:
15471 case BFD_RELOC_MIPS_CALL_HI16
:
15472 case BFD_RELOC_MIPS_CALL_LO16
:
15473 case BFD_RELOC_MIPS16_GPREL
:
15474 case BFD_RELOC_MIPS16_GOT16
:
15475 case BFD_RELOC_MIPS16_CALL16
:
15476 case BFD_RELOC_MIPS16_HI16
:
15477 case BFD_RELOC_MIPS16_HI16_S
:
15478 case BFD_RELOC_MIPS16_JMP
:
15479 case BFD_RELOC_MICROMIPS_JMP
:
15480 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15481 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15482 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15483 case BFD_RELOC_MICROMIPS_SUB
:
15484 case BFD_RELOC_MICROMIPS_HIGHEST
:
15485 case BFD_RELOC_MICROMIPS_HIGHER
:
15486 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15487 case BFD_RELOC_MICROMIPS_JALR
:
15488 case BFD_RELOC_MICROMIPS_HI16
:
15489 case BFD_RELOC_MICROMIPS_HI16_S
:
15490 case BFD_RELOC_MICROMIPS_GPREL16
:
15491 case BFD_RELOC_MICROMIPS_LITERAL
:
15492 case BFD_RELOC_MICROMIPS_CALL16
:
15493 case BFD_RELOC_MICROMIPS_GOT16
:
15494 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15495 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15496 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15497 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15498 /* Nothing needed to do. The value comes from the reloc entry. */
15502 /* This is handled like BFD_RELOC_32, but we output a sign
15503 extended value if we are only 32 bits. */
15506 if (8 <= sizeof (valueT
))
15507 md_number_to_chars ((char *) buf
, *valP
, 8);
15512 if ((*valP
& 0x80000000) != 0)
15516 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
15518 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
15524 case BFD_RELOC_RVA
:
15527 /* If we are deleting this reloc entry, we must fill in the
15528 value now. This can happen if we have a .word which is not
15529 resolved when it appears but is later defined. */
15531 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
15534 case BFD_RELOC_LO16
:
15535 case BFD_RELOC_MIPS16_LO16
:
15536 case BFD_RELOC_MICROMIPS_LO16
:
15537 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15538 may be safe to remove, but if so it's not obvious. */
15539 /* When handling an embedded PIC switch statement, we can wind
15540 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15543 if (*valP
+ 0x8000 > 0xffff)
15544 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15545 _("relocation overflow"));
15546 /* 32-bit microMIPS instructions are divided into two halfwords.
15547 Relocations always refer to the second halfword, regardless
15549 if (target_big_endian
|| fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_LO16
)
15551 md_number_to_chars ((char *) buf
, *valP
, 2);
15555 case BFD_RELOC_16_PCREL_S2
:
15556 if ((*valP
& 0x3) != 0)
15557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15558 _("Branch to misaligned address (%lx)"), (long) *valP
);
15560 /* We need to save the bits in the instruction since fixup_segment()
15561 might be deleting the relocation entry (i.e., a branch within
15562 the current segment). */
15563 if (! fixP
->fx_done
)
15566 /* Update old instruction data. */
15567 if (target_big_endian
)
15568 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
15570 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
15572 if (*valP
+ 0x20000 <= 0x3ffff)
15574 insn
|= (*valP
>> 2) & 0xffff;
15575 md_number_to_chars ((char *) buf
, insn
, 4);
15577 else if (mips_pic
== NO_PIC
15579 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15580 && (fixP
->fx_frag
->fr_address
15581 < text_section
->vma
+ bfd_get_section_size (text_section
))
15582 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15583 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15584 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15586 /* The branch offset is too large. If this is an
15587 unconditional branch, and we are not generating PIC code,
15588 we can convert it to an absolute jump instruction. */
15589 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15590 insn
= 0x0c000000; /* jal */
15592 insn
= 0x08000000; /* j */
15593 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15595 fixP
->fx_addsy
= section_symbol (text_section
);
15596 *valP
+= md_pcrel_from (fixP
);
15597 md_number_to_chars ((char *) buf
, insn
, 4);
15601 /* If we got here, we have branch-relaxation disabled,
15602 and there's nothing we can do to fix this instruction
15603 without turning it into a longer sequence. */
15604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15605 _("Branch out of range"));
15609 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15610 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15611 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15612 /* We adjust the offset back to even. */
15613 if ((*valP
& 0x1) != 0)
15616 if (! fixP
->fx_done
)
15619 /* Should never visit here, because we keep the relocation. */
15623 case BFD_RELOC_VTABLE_INHERIT
:
15626 && !S_IS_DEFINED (fixP
->fx_addsy
)
15627 && !S_IS_WEAK (fixP
->fx_addsy
))
15628 S_SET_WEAK (fixP
->fx_addsy
);
15631 case BFD_RELOC_VTABLE_ENTRY
:
15639 /* Remember value for tc_gen_reloc. */
15640 fixP
->fx_addnumber
= *valP
;
15650 name
= input_line_pointer
;
15651 c
= get_symbol_end ();
15652 p
= (symbolS
*) symbol_find_or_make (name
);
15653 *input_line_pointer
= c
;
15657 /* Align the current frag to a given power of two. If a particular
15658 fill byte should be used, FILL points to an integer that contains
15659 that byte, otherwise FILL is null.
15661 This function used to have the comment:
15663 The MIPS assembler also automatically adjusts any preceding label.
15665 The implementation therefore applied the adjustment to a maximum of
15666 one label. However, other label adjustments are applied to batches
15667 of labels, and adjusting just one caused problems when new labels
15668 were added for the sake of debugging or unwind information.
15669 We therefore adjust all preceding labels (given as LABELS) instead. */
15672 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15674 mips_emit_delays ();
15675 mips_record_compressed_mode ();
15676 if (fill
== NULL
&& subseg_text_p (now_seg
))
15677 frag_align_code (to
, 0);
15679 frag_align (to
, fill
? *fill
: 0, 0);
15680 record_alignment (now_seg
, to
);
15681 mips_move_labels (labels
, FALSE
);
15684 /* Align to a given power of two. .align 0 turns off the automatic
15685 alignment used by the data creating pseudo-ops. */
15688 s_align (int x ATTRIBUTE_UNUSED
)
15690 int temp
, fill_value
, *fill_ptr
;
15691 long max_alignment
= 28;
15693 /* o Note that the assembler pulls down any immediately preceding label
15694 to the aligned address.
15695 o It's not documented but auto alignment is reinstated by
15696 a .align pseudo instruction.
15697 o Note also that after auto alignment is turned off the mips assembler
15698 issues an error on attempt to assemble an improperly aligned data item.
15701 temp
= get_absolute_expression ();
15702 if (temp
> max_alignment
)
15703 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
15706 as_warn (_("Alignment negative: 0 assumed."));
15709 if (*input_line_pointer
== ',')
15711 ++input_line_pointer
;
15712 fill_value
= get_absolute_expression ();
15713 fill_ptr
= &fill_value
;
15719 segment_info_type
*si
= seg_info (now_seg
);
15720 struct insn_label_list
*l
= si
->label_list
;
15721 /* Auto alignment should be switched on by next section change. */
15723 mips_align (temp
, fill_ptr
, l
);
15730 demand_empty_rest_of_line ();
15734 s_change_sec (int sec
)
15739 /* The ELF backend needs to know that we are changing sections, so
15740 that .previous works correctly. We could do something like check
15741 for an obj_section_change_hook macro, but that might be confusing
15742 as it would not be appropriate to use it in the section changing
15743 functions in read.c, since obj-elf.c intercepts those. FIXME:
15744 This should be cleaner, somehow. */
15746 obj_elf_section_change_hook ();
15749 mips_emit_delays ();
15760 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15761 demand_empty_rest_of_line ();
15765 seg
= subseg_new (RDATA_SECTION_NAME
,
15766 (subsegT
) get_absolute_expression ());
15769 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15770 | SEC_READONLY
| SEC_RELOC
15772 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15773 record_alignment (seg
, 4);
15775 demand_empty_rest_of_line ();
15779 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15782 bfd_set_section_flags (stdoutput
, seg
,
15783 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15784 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15785 record_alignment (seg
, 4);
15787 demand_empty_rest_of_line ();
15791 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15794 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15795 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15796 record_alignment (seg
, 4);
15798 demand_empty_rest_of_line ();
15806 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15809 char *section_name
;
15814 int section_entry_size
;
15815 int section_alignment
;
15820 section_name
= input_line_pointer
;
15821 c
= get_symbol_end ();
15823 next_c
= *(input_line_pointer
+ 1);
15825 /* Do we have .section Name<,"flags">? */
15826 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15828 /* just after name is now '\0'. */
15829 *input_line_pointer
= c
;
15830 input_line_pointer
= section_name
;
15831 obj_elf_section (ignore
);
15834 input_line_pointer
++;
15836 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15838 section_type
= get_absolute_expression ();
15841 if (*input_line_pointer
++ == ',')
15842 section_flag
= get_absolute_expression ();
15845 if (*input_line_pointer
++ == ',')
15846 section_entry_size
= get_absolute_expression ();
15848 section_entry_size
= 0;
15849 if (*input_line_pointer
++ == ',')
15850 section_alignment
= get_absolute_expression ();
15852 section_alignment
= 0;
15853 /* FIXME: really ignore? */
15854 (void) section_alignment
;
15856 section_name
= xstrdup (section_name
);
15858 /* When using the generic form of .section (as implemented by obj-elf.c),
15859 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15860 traditionally had to fall back on the more common @progbits instead.
15862 There's nothing really harmful in this, since bfd will correct
15863 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15864 means that, for backwards compatibility, the special_section entries
15865 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15867 Even so, we shouldn't force users of the MIPS .section syntax to
15868 incorrectly label the sections as SHT_PROGBITS. The best compromise
15869 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15870 generic type-checking code. */
15871 if (section_type
== SHT_MIPS_DWARF
)
15872 section_type
= SHT_PROGBITS
;
15874 obj_elf_change_section (section_name
, section_type
, section_flag
,
15875 section_entry_size
, 0, 0, 0);
15877 if (now_seg
->name
!= section_name
)
15878 free (section_name
);
15879 #endif /* OBJ_ELF */
15883 mips_enable_auto_align (void)
15889 s_cons (int log_size
)
15891 segment_info_type
*si
= seg_info (now_seg
);
15892 struct insn_label_list
*l
= si
->label_list
;
15894 mips_emit_delays ();
15895 if (log_size
> 0 && auto_align
)
15896 mips_align (log_size
, 0, l
);
15897 cons (1 << log_size
);
15898 mips_clear_insn_labels ();
15902 s_float_cons (int type
)
15904 segment_info_type
*si
= seg_info (now_seg
);
15905 struct insn_label_list
*l
= si
->label_list
;
15907 mips_emit_delays ();
15912 mips_align (3, 0, l
);
15914 mips_align (2, 0, l
);
15918 mips_clear_insn_labels ();
15921 /* Handle .globl. We need to override it because on Irix 5 you are
15924 where foo is an undefined symbol, to mean that foo should be
15925 considered to be the address of a function. */
15928 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15937 name
= input_line_pointer
;
15938 c
= get_symbol_end ();
15939 symbolP
= symbol_find_or_make (name
);
15940 S_SET_EXTERNAL (symbolP
);
15942 *input_line_pointer
= c
;
15943 SKIP_WHITESPACE ();
15945 /* On Irix 5, every global symbol that is not explicitly labelled as
15946 being a function is apparently labelled as being an object. */
15949 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15950 && (*input_line_pointer
!= ','))
15955 secname
= input_line_pointer
;
15956 c
= get_symbol_end ();
15957 sec
= bfd_get_section_by_name (stdoutput
, secname
);
15959 as_bad (_("%s: no such section"), secname
);
15960 *input_line_pointer
= c
;
15962 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
15963 flag
= BSF_FUNCTION
;
15966 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
15968 c
= *input_line_pointer
;
15971 input_line_pointer
++;
15972 SKIP_WHITESPACE ();
15973 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
15979 demand_empty_rest_of_line ();
15983 s_option (int x ATTRIBUTE_UNUSED
)
15988 opt
= input_line_pointer
;
15989 c
= get_symbol_end ();
15993 /* FIXME: What does this mean? */
15995 else if (strncmp (opt
, "pic", 3) == 0)
15999 i
= atoi (opt
+ 3);
16004 mips_pic
= SVR4_PIC
;
16005 mips_abicalls
= TRUE
;
16008 as_bad (_(".option pic%d not supported"), i
);
16010 if (mips_pic
== SVR4_PIC
)
16012 if (g_switch_seen
&& g_switch_value
!= 0)
16013 as_warn (_("-G may not be used with SVR4 PIC code"));
16014 g_switch_value
= 0;
16015 bfd_set_gp_size (stdoutput
, 0);
16019 as_warn (_("Unrecognized option \"%s\""), opt
);
16021 *input_line_pointer
= c
;
16022 demand_empty_rest_of_line ();
16025 /* This structure is used to hold a stack of .set values. */
16027 struct mips_option_stack
16029 struct mips_option_stack
*next
;
16030 struct mips_set_options options
;
16033 static struct mips_option_stack
*mips_opts_stack
;
16035 /* Handle the .set pseudo-op. */
16038 s_mipsset (int x ATTRIBUTE_UNUSED
)
16040 char *name
= input_line_pointer
, ch
;
16042 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16043 ++input_line_pointer
;
16044 ch
= *input_line_pointer
;
16045 *input_line_pointer
= '\0';
16047 if (strcmp (name
, "reorder") == 0)
16049 if (mips_opts
.noreorder
)
16052 else if (strcmp (name
, "noreorder") == 0)
16054 if (!mips_opts
.noreorder
)
16055 start_noreorder ();
16057 else if (strncmp (name
, "at=", 3) == 0)
16059 char *s
= name
+ 3;
16061 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16062 as_bad (_("Unrecognized register name `%s'"), s
);
16064 else if (strcmp (name
, "at") == 0)
16066 mips_opts
.at
= ATREG
;
16068 else if (strcmp (name
, "noat") == 0)
16070 mips_opts
.at
= ZERO
;
16072 else if (strcmp (name
, "macro") == 0)
16074 mips_opts
.warn_about_macros
= 0;
16076 else if (strcmp (name
, "nomacro") == 0)
16078 if (mips_opts
.noreorder
== 0)
16079 as_bad (_("`noreorder' must be set before `nomacro'"));
16080 mips_opts
.warn_about_macros
= 1;
16082 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16084 mips_opts
.nomove
= 0;
16086 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16088 mips_opts
.nomove
= 1;
16090 else if (strcmp (name
, "bopt") == 0)
16092 mips_opts
.nobopt
= 0;
16094 else if (strcmp (name
, "nobopt") == 0)
16096 mips_opts
.nobopt
= 1;
16098 else if (strcmp (name
, "gp=default") == 0)
16099 mips_opts
.gp32
= file_mips_gp32
;
16100 else if (strcmp (name
, "gp=32") == 0)
16101 mips_opts
.gp32
= 1;
16102 else if (strcmp (name
, "gp=64") == 0)
16104 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16105 as_warn (_("%s isa does not support 64-bit registers"),
16106 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16107 mips_opts
.gp32
= 0;
16109 else if (strcmp (name
, "fp=default") == 0)
16110 mips_opts
.fp32
= file_mips_fp32
;
16111 else if (strcmp (name
, "fp=32") == 0)
16112 mips_opts
.fp32
= 1;
16113 else if (strcmp (name
, "fp=64") == 0)
16115 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16116 as_warn (_("%s isa does not support 64-bit floating point registers"),
16117 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16118 mips_opts
.fp32
= 0;
16120 else if (strcmp (name
, "softfloat") == 0)
16121 mips_opts
.soft_float
= 1;
16122 else if (strcmp (name
, "hardfloat") == 0)
16123 mips_opts
.soft_float
= 0;
16124 else if (strcmp (name
, "singlefloat") == 0)
16125 mips_opts
.single_float
= 1;
16126 else if (strcmp (name
, "doublefloat") == 0)
16127 mips_opts
.single_float
= 0;
16128 else if (strcmp (name
, "mips16") == 0
16129 || strcmp (name
, "MIPS-16") == 0)
16131 if (mips_opts
.micromips
== 1)
16132 as_fatal (_("`mips16' cannot be used with `micromips'"));
16133 mips_opts
.mips16
= 1;
16135 else if (strcmp (name
, "nomips16") == 0
16136 || strcmp (name
, "noMIPS-16") == 0)
16137 mips_opts
.mips16
= 0;
16138 else if (strcmp (name
, "micromips") == 0)
16140 if (mips_opts
.mips16
== 1)
16141 as_fatal (_("`micromips' cannot be used with `mips16'"));
16142 mips_opts
.micromips
= 1;
16144 else if (strcmp (name
, "nomicromips") == 0)
16145 mips_opts
.micromips
= 0;
16146 else if (strcmp (name
, "smartmips") == 0)
16148 if (!ISA_SUPPORTS_SMARTMIPS
)
16149 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16150 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16151 mips_opts
.ase_smartmips
= 1;
16153 else if (strcmp (name
, "nosmartmips") == 0)
16154 mips_opts
.ase_smartmips
= 0;
16155 else if (strcmp (name
, "mips3d") == 0)
16156 mips_opts
.ase_mips3d
= 1;
16157 else if (strcmp (name
, "nomips3d") == 0)
16158 mips_opts
.ase_mips3d
= 0;
16159 else if (strcmp (name
, "mdmx") == 0)
16160 mips_opts
.ase_mdmx
= 1;
16161 else if (strcmp (name
, "nomdmx") == 0)
16162 mips_opts
.ase_mdmx
= 0;
16163 else if (strcmp (name
, "dsp") == 0)
16165 if (!ISA_SUPPORTS_DSP_ASE
)
16166 as_warn (_("%s ISA does not support DSP ASE"),
16167 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16168 mips_opts
.ase_dsp
= 1;
16169 mips_opts
.ase_dspr2
= 0;
16171 else if (strcmp (name
, "nodsp") == 0)
16173 mips_opts
.ase_dsp
= 0;
16174 mips_opts
.ase_dspr2
= 0;
16176 else if (strcmp (name
, "dspr2") == 0)
16178 if (!ISA_SUPPORTS_DSPR2_ASE
)
16179 as_warn (_("%s ISA does not support DSP R2 ASE"),
16180 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16181 mips_opts
.ase_dspr2
= 1;
16182 mips_opts
.ase_dsp
= 1;
16184 else if (strcmp (name
, "nodspr2") == 0)
16186 mips_opts
.ase_dspr2
= 0;
16187 mips_opts
.ase_dsp
= 0;
16189 else if (strcmp (name
, "mt") == 0)
16191 if (!ISA_SUPPORTS_MT_ASE
)
16192 as_warn (_("%s ISA does not support MT ASE"),
16193 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16194 mips_opts
.ase_mt
= 1;
16196 else if (strcmp (name
, "nomt") == 0)
16197 mips_opts
.ase_mt
= 0;
16198 else if (strcmp (name
, "mcu") == 0)
16199 mips_opts
.ase_mcu
= 1;
16200 else if (strcmp (name
, "nomcu") == 0)
16201 mips_opts
.ase_mcu
= 0;
16202 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16206 /* Permit the user to change the ISA and architecture on the fly.
16207 Needless to say, misuse can cause serious problems. */
16208 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16211 mips_opts
.isa
= file_mips_isa
;
16212 mips_opts
.arch
= file_mips_arch
;
16214 else if (strncmp (name
, "arch=", 5) == 0)
16216 const struct mips_cpu_info
*p
;
16218 p
= mips_parse_cpu("internal use", name
+ 5);
16220 as_bad (_("unknown architecture %s"), name
+ 5);
16223 mips_opts
.arch
= p
->cpu
;
16224 mips_opts
.isa
= p
->isa
;
16227 else if (strncmp (name
, "mips", 4) == 0)
16229 const struct mips_cpu_info
*p
;
16231 p
= mips_parse_cpu("internal use", name
);
16233 as_bad (_("unknown ISA level %s"), name
+ 4);
16236 mips_opts
.arch
= p
->cpu
;
16237 mips_opts
.isa
= p
->isa
;
16241 as_bad (_("unknown ISA or architecture %s"), name
);
16243 switch (mips_opts
.isa
)
16251 mips_opts
.gp32
= 1;
16252 mips_opts
.fp32
= 1;
16259 mips_opts
.gp32
= 0;
16260 mips_opts
.fp32
= 0;
16263 as_bad (_("unknown ISA level %s"), name
+ 4);
16268 mips_opts
.gp32
= file_mips_gp32
;
16269 mips_opts
.fp32
= file_mips_fp32
;
16272 else if (strcmp (name
, "autoextend") == 0)
16273 mips_opts
.noautoextend
= 0;
16274 else if (strcmp (name
, "noautoextend") == 0)
16275 mips_opts
.noautoextend
= 1;
16276 else if (strcmp (name
, "push") == 0)
16278 struct mips_option_stack
*s
;
16280 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16281 s
->next
= mips_opts_stack
;
16282 s
->options
= mips_opts
;
16283 mips_opts_stack
= s
;
16285 else if (strcmp (name
, "pop") == 0)
16287 struct mips_option_stack
*s
;
16289 s
= mips_opts_stack
;
16291 as_bad (_(".set pop with no .set push"));
16294 /* If we're changing the reorder mode we need to handle
16295 delay slots correctly. */
16296 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16297 start_noreorder ();
16298 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16301 mips_opts
= s
->options
;
16302 mips_opts_stack
= s
->next
;
16306 else if (strcmp (name
, "sym32") == 0)
16307 mips_opts
.sym32
= TRUE
;
16308 else if (strcmp (name
, "nosym32") == 0)
16309 mips_opts
.sym32
= FALSE
;
16310 else if (strchr (name
, ','))
16312 /* Generic ".set" directive; use the generic handler. */
16313 *input_line_pointer
= ch
;
16314 input_line_pointer
= name
;
16320 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16322 *input_line_pointer
= ch
;
16323 demand_empty_rest_of_line ();
16326 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16327 .option pic2. It means to generate SVR4 PIC calls. */
16330 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16332 mips_pic
= SVR4_PIC
;
16333 mips_abicalls
= TRUE
;
16335 if (g_switch_seen
&& g_switch_value
!= 0)
16336 as_warn (_("-G may not be used with SVR4 PIC code"));
16337 g_switch_value
= 0;
16339 bfd_set_gp_size (stdoutput
, 0);
16340 demand_empty_rest_of_line ();
16343 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16344 PIC code. It sets the $gp register for the function based on the
16345 function address, which is in the register named in the argument.
16346 This uses a relocation against _gp_disp, which is handled specially
16347 by the linker. The result is:
16348 lui $gp,%hi(_gp_disp)
16349 addiu $gp,$gp,%lo(_gp_disp)
16350 addu $gp,$gp,.cpload argument
16351 The .cpload argument is normally $25 == $t9.
16353 The -mno-shared option changes this to:
16354 lui $gp,%hi(__gnu_local_gp)
16355 addiu $gp,$gp,%lo(__gnu_local_gp)
16356 and the argument is ignored. This saves an instruction, but the
16357 resulting code is not position independent; it uses an absolute
16358 address for __gnu_local_gp. Thus code assembled with -mno-shared
16359 can go into an ordinary executable, but not into a shared library. */
16362 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16368 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16369 .cpload is ignored. */
16370 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16376 /* .cpload should be in a .set noreorder section. */
16377 if (mips_opts
.noreorder
== 0)
16378 as_warn (_(".cpload not in noreorder section"));
16380 reg
= tc_get_register (0);
16382 /* If we need to produce a 64-bit address, we are better off using
16383 the default instruction sequence. */
16384 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16386 ex
.X_op
= O_symbol
;
16387 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16389 ex
.X_op_symbol
= NULL
;
16390 ex
.X_add_number
= 0;
16392 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16393 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16396 macro_build_lui (&ex
, mips_gp_register
);
16397 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16398 mips_gp_register
, BFD_RELOC_LO16
);
16400 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16401 mips_gp_register
, reg
);
16404 demand_empty_rest_of_line ();
16407 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16408 .cpsetup $reg1, offset|$reg2, label
16410 If offset is given, this results in:
16411 sd $gp, offset($sp)
16412 lui $gp, %hi(%neg(%gp_rel(label)))
16413 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16414 daddu $gp, $gp, $reg1
16416 If $reg2 is given, this results in:
16417 daddu $reg2, $gp, $0
16418 lui $gp, %hi(%neg(%gp_rel(label)))
16419 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16420 daddu $gp, $gp, $reg1
16421 $reg1 is normally $25 == $t9.
16423 The -mno-shared option replaces the last three instructions with
16425 addiu $gp,$gp,%lo(_gp) */
16428 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16430 expressionS ex_off
;
16431 expressionS ex_sym
;
16434 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16435 We also need NewABI support. */
16436 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16442 reg1
= tc_get_register (0);
16443 SKIP_WHITESPACE ();
16444 if (*input_line_pointer
!= ',')
16446 as_bad (_("missing argument separator ',' for .cpsetup"));
16450 ++input_line_pointer
;
16451 SKIP_WHITESPACE ();
16452 if (*input_line_pointer
== '$')
16454 mips_cpreturn_register
= tc_get_register (0);
16455 mips_cpreturn_offset
= -1;
16459 mips_cpreturn_offset
= get_absolute_expression ();
16460 mips_cpreturn_register
= -1;
16462 SKIP_WHITESPACE ();
16463 if (*input_line_pointer
!= ',')
16465 as_bad (_("missing argument separator ',' for .cpsetup"));
16469 ++input_line_pointer
;
16470 SKIP_WHITESPACE ();
16471 expression (&ex_sym
);
16474 if (mips_cpreturn_register
== -1)
16476 ex_off
.X_op
= O_constant
;
16477 ex_off
.X_add_symbol
= NULL
;
16478 ex_off
.X_op_symbol
= NULL
;
16479 ex_off
.X_add_number
= mips_cpreturn_offset
;
16481 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16482 BFD_RELOC_LO16
, SP
);
16485 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16486 mips_gp_register
, 0);
16488 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16490 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16491 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16494 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16495 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16496 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16498 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16499 mips_gp_register
, reg1
);
16505 ex
.X_op
= O_symbol
;
16506 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16507 ex
.X_op_symbol
= NULL
;
16508 ex
.X_add_number
= 0;
16510 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16511 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16513 macro_build_lui (&ex
, mips_gp_register
);
16514 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16515 mips_gp_register
, BFD_RELOC_LO16
);
16520 demand_empty_rest_of_line ();
16524 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16526 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16527 .cplocal is ignored. */
16528 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16534 mips_gp_register
= tc_get_register (0);
16535 demand_empty_rest_of_line ();
16538 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16539 offset from $sp. The offset is remembered, and after making a PIC
16540 call $gp is restored from that location. */
16543 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16547 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16548 .cprestore is ignored. */
16549 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16555 mips_cprestore_offset
= get_absolute_expression ();
16556 mips_cprestore_valid
= 1;
16558 ex
.X_op
= O_constant
;
16559 ex
.X_add_symbol
= NULL
;
16560 ex
.X_op_symbol
= NULL
;
16561 ex
.X_add_number
= mips_cprestore_offset
;
16564 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16565 SP
, HAVE_64BIT_ADDRESSES
);
16568 demand_empty_rest_of_line ();
16571 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16572 was given in the preceding .cpsetup, it results in:
16573 ld $gp, offset($sp)
16575 If a register $reg2 was given there, it results in:
16576 daddu $gp, $reg2, $0 */
16579 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16583 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16584 We also need NewABI support. */
16585 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16592 if (mips_cpreturn_register
== -1)
16594 ex
.X_op
= O_constant
;
16595 ex
.X_add_symbol
= NULL
;
16596 ex
.X_op_symbol
= NULL
;
16597 ex
.X_add_number
= mips_cpreturn_offset
;
16599 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16602 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16603 mips_cpreturn_register
, 0);
16606 demand_empty_rest_of_line ();
16609 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16610 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16611 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16612 debug information or MIPS16 TLS. */
16615 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16616 bfd_reloc_code_real_type rtype
)
16623 if (ex
.X_op
!= O_symbol
)
16625 as_bad (_("Unsupported use of %s"), dirstr
);
16626 ignore_rest_of_line ();
16629 p
= frag_more (bytes
);
16630 md_number_to_chars (p
, 0, bytes
);
16631 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16632 demand_empty_rest_of_line ();
16635 /* Handle .dtprelword. */
16638 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16640 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16643 /* Handle .dtpreldword. */
16646 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16648 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16651 /* Handle .tprelword. */
16654 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16656 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16659 /* Handle .tpreldword. */
16662 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16664 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16667 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16668 code. It sets the offset to use in gp_rel relocations. */
16671 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16673 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16674 We also need NewABI support. */
16675 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16681 mips_gprel_offset
= get_absolute_expression ();
16683 demand_empty_rest_of_line ();
16686 /* Handle the .gpword pseudo-op. This is used when generating PIC
16687 code. It generates a 32 bit GP relative reloc. */
16690 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16692 segment_info_type
*si
;
16693 struct insn_label_list
*l
;
16697 /* When not generating PIC code, this is treated as .word. */
16698 if (mips_pic
!= SVR4_PIC
)
16704 si
= seg_info (now_seg
);
16705 l
= si
->label_list
;
16706 mips_emit_delays ();
16708 mips_align (2, 0, l
);
16711 mips_clear_insn_labels ();
16713 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16715 as_bad (_("Unsupported use of .gpword"));
16716 ignore_rest_of_line ();
16720 md_number_to_chars (p
, 0, 4);
16721 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16722 BFD_RELOC_GPREL32
);
16724 demand_empty_rest_of_line ();
16728 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16730 segment_info_type
*si
;
16731 struct insn_label_list
*l
;
16735 /* When not generating PIC code, this is treated as .dword. */
16736 if (mips_pic
!= SVR4_PIC
)
16742 si
= seg_info (now_seg
);
16743 l
= si
->label_list
;
16744 mips_emit_delays ();
16746 mips_align (3, 0, l
);
16749 mips_clear_insn_labels ();
16751 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16753 as_bad (_("Unsupported use of .gpdword"));
16754 ignore_rest_of_line ();
16758 md_number_to_chars (p
, 0, 8);
16759 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16760 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16762 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16763 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16764 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16766 demand_empty_rest_of_line ();
16769 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16770 tables in SVR4 PIC code. */
16773 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16777 /* This is ignored when not generating SVR4 PIC code. */
16778 if (mips_pic
!= SVR4_PIC
)
16784 /* Add $gp to the register named as an argument. */
16786 reg
= tc_get_register (0);
16787 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16790 demand_empty_rest_of_line ();
16793 /* Handle the .insn pseudo-op. This marks instruction labels in
16794 mips16/micromips mode. This permits the linker to handle them specially,
16795 such as generating jalx instructions when needed. We also make
16796 them odd for the duration of the assembly, in order to generate the
16797 right sort of code. We will make them even in the adjust_symtab
16798 routine, while leaving them marked. This is convenient for the
16799 debugger and the disassembler. The linker knows to make them odd
16803 s_insn (int ignore ATTRIBUTE_UNUSED
)
16805 mips_mark_labels ();
16807 demand_empty_rest_of_line ();
16810 /* Handle a .stabn directive. We need these in order to mark a label
16811 as being a mips16 text label correctly. Sometimes the compiler
16812 will emit a label, followed by a .stabn, and then switch sections.
16813 If the label and .stabn are in mips16 mode, then the label is
16814 really a mips16 text label. */
16817 s_mips_stab (int type
)
16820 mips_mark_labels ();
16825 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16828 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16835 name
= input_line_pointer
;
16836 c
= get_symbol_end ();
16837 symbolP
= symbol_find_or_make (name
);
16838 S_SET_WEAK (symbolP
);
16839 *input_line_pointer
= c
;
16841 SKIP_WHITESPACE ();
16843 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16845 if (S_IS_DEFINED (symbolP
))
16847 as_bad (_("ignoring attempt to redefine symbol %s"),
16848 S_GET_NAME (symbolP
));
16849 ignore_rest_of_line ();
16853 if (*input_line_pointer
== ',')
16855 ++input_line_pointer
;
16856 SKIP_WHITESPACE ();
16860 if (exp
.X_op
!= O_symbol
)
16862 as_bad (_("bad .weakext directive"));
16863 ignore_rest_of_line ();
16866 symbol_set_value_expression (symbolP
, &exp
);
16869 demand_empty_rest_of_line ();
16872 /* Parse a register string into a number. Called from the ECOFF code
16873 to parse .frame. The argument is non-zero if this is the frame
16874 register, so that we can record it in mips_frame_reg. */
16877 tc_get_register (int frame
)
16881 SKIP_WHITESPACE ();
16882 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
16886 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
16887 mips_frame_reg_valid
= 1;
16888 mips_cprestore_valid
= 0;
16894 md_section_align (asection
*seg
, valueT addr
)
16896 int align
= bfd_get_section_alignment (stdoutput
, seg
);
16900 /* We don't need to align ELF sections to the full alignment.
16901 However, Irix 5 may prefer that we align them at least to a 16
16902 byte boundary. We don't bother to align the sections if we
16903 are targeted for an embedded system. */
16904 if (strncmp (TARGET_OS
, "elf", 3) == 0)
16910 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
16913 /* Utility routine, called from above as well. If called while the
16914 input file is still being read, it's only an approximation. (For
16915 example, a symbol may later become defined which appeared to be
16916 undefined earlier.) */
16919 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
16924 if (g_switch_value
> 0)
16926 const char *symname
;
16929 /* Find out whether this symbol can be referenced off the $gp
16930 register. It can be if it is smaller than the -G size or if
16931 it is in the .sdata or .sbss section. Certain symbols can
16932 not be referenced off the $gp, although it appears as though
16934 symname
= S_GET_NAME (sym
);
16935 if (symname
!= (const char *) NULL
16936 && (strcmp (symname
, "eprol") == 0
16937 || strcmp (symname
, "etext") == 0
16938 || strcmp (symname
, "_gp") == 0
16939 || strcmp (symname
, "edata") == 0
16940 || strcmp (symname
, "_fbss") == 0
16941 || strcmp (symname
, "_fdata") == 0
16942 || strcmp (symname
, "_ftext") == 0
16943 || strcmp (symname
, "end") == 0
16944 || strcmp (symname
, "_gp_disp") == 0))
16946 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
16948 #ifndef NO_ECOFF_DEBUGGING
16949 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
16950 && (symbol_get_obj (sym
)->ecoff_extern_size
16951 <= g_switch_value
))
16953 /* We must defer this decision until after the whole
16954 file has been read, since there might be a .extern
16955 after the first use of this symbol. */
16956 || (before_relaxing
16957 #ifndef NO_ECOFF_DEBUGGING
16958 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
16960 && S_GET_VALUE (sym
) == 0)
16961 || (S_GET_VALUE (sym
) != 0
16962 && S_GET_VALUE (sym
) <= g_switch_value
)))
16966 const char *segname
;
16968 segname
= segment_name (S_GET_SEGMENT (sym
));
16969 gas_assert (strcmp (segname
, ".lit8") != 0
16970 && strcmp (segname
, ".lit4") != 0);
16971 change
= (strcmp (segname
, ".sdata") != 0
16972 && strcmp (segname
, ".sbss") != 0
16973 && strncmp (segname
, ".sdata.", 7) != 0
16974 && strncmp (segname
, ".sbss.", 6) != 0
16975 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
16976 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
16981 /* We are not optimizing for the $gp register. */
16986 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16989 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16993 /* Handle the case of a symbol equated to another symbol. */
16994 while (symbol_equated_reloc_p (sym
))
16998 /* It's possible to get a loop here in a badly written program. */
16999 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17005 if (symbol_section_p (sym
))
17008 symsec
= S_GET_SEGMENT (sym
);
17010 /* This must duplicate the test in adjust_reloc_syms. */
17011 return (symsec
!= &bfd_und_section
17012 && symsec
!= &bfd_abs_section
17013 && !bfd_is_com_section (symsec
)
17014 && !s_is_linkonce (sym
, segtype
)
17016 /* A global or weak symbol is treated as external. */
17017 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17023 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17024 extended opcode. SEC is the section the frag is in. */
17027 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17030 const struct mips16_immed_operand
*op
;
17032 int mintiny
, maxtiny
;
17036 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17038 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17041 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17042 op
= mips16_immed_operands
;
17043 while (op
->type
!= type
)
17046 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17051 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17054 maxtiny
= 1 << op
->nbits
;
17059 maxtiny
= (1 << op
->nbits
) - 1;
17064 mintiny
= - (1 << (op
->nbits
- 1));
17065 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17068 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17069 val
= S_GET_VALUE (fragp
->fr_symbol
);
17070 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17076 /* We won't have the section when we are called from
17077 mips_relax_frag. However, we will always have been called
17078 from md_estimate_size_before_relax first. If this is a
17079 branch to a different section, we mark it as such. If SEC is
17080 NULL, and the frag is not marked, then it must be a branch to
17081 the same section. */
17084 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17089 /* Must have been called from md_estimate_size_before_relax. */
17092 fragp
->fr_subtype
=
17093 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17095 /* FIXME: We should support this, and let the linker
17096 catch branches and loads that are out of range. */
17097 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17098 _("unsupported PC relative reference to different section"));
17102 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17103 /* Assume non-extended on the first relaxation pass.
17104 The address we have calculated will be bogus if this is
17105 a forward branch to another frag, as the forward frag
17106 will have fr_address == 0. */
17110 /* In this case, we know for sure that the symbol fragment is in
17111 the same section. If the relax_marker of the symbol fragment
17112 differs from the relax_marker of this fragment, we have not
17113 yet adjusted the symbol fragment fr_address. We want to add
17114 in STRETCH in order to get a better estimate of the address.
17115 This particularly matters because of the shift bits. */
17117 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17121 /* Adjust stretch for any alignment frag. Note that if have
17122 been expanding the earlier code, the symbol may be
17123 defined in what appears to be an earlier frag. FIXME:
17124 This doesn't handle the fr_subtype field, which specifies
17125 a maximum number of bytes to skip when doing an
17127 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17129 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17132 stretch
= - ((- stretch
)
17133 & ~ ((1 << (int) f
->fr_offset
) - 1));
17135 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17144 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17146 /* The base address rules are complicated. The base address of
17147 a branch is the following instruction. The base address of a
17148 PC relative load or add is the instruction itself, but if it
17149 is in a delay slot (in which case it can not be extended) use
17150 the address of the instruction whose delay slot it is in. */
17151 if (type
== 'p' || type
== 'q')
17155 /* If we are currently assuming that this frag should be
17156 extended, then, the current address is two bytes
17158 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17161 /* Ignore the low bit in the target, since it will be set
17162 for a text label. */
17163 if ((val
& 1) != 0)
17166 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17168 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17171 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17173 /* Branch offsets have an implicit 0 in the lowest bit. */
17174 if (type
== 'p' || type
== 'q')
17177 /* If any of the shifted bits are set, we must use an extended
17178 opcode. If the address depends on the size of this
17179 instruction, this can lead to a loop, so we arrange to always
17180 use an extended opcode. We only check this when we are in
17181 the main relaxation loop, when SEC is NULL. */
17182 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17184 fragp
->fr_subtype
=
17185 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17189 /* If we are about to mark a frag as extended because the value
17190 is precisely maxtiny + 1, then there is a chance of an
17191 infinite loop as in the following code:
17196 In this case when the la is extended, foo is 0x3fc bytes
17197 away, so the la can be shrunk, but then foo is 0x400 away, so
17198 the la must be extended. To avoid this loop, we mark the
17199 frag as extended if it was small, and is about to become
17200 extended with a value of maxtiny + 1. */
17201 if (val
== ((maxtiny
+ 1) << op
->shift
)
17202 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17205 fragp
->fr_subtype
=
17206 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17210 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17211 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17213 if ((val
& ((1 << op
->shift
) - 1)) != 0
17214 || val
< (mintiny
<< op
->shift
)
17215 || val
> (maxtiny
<< op
->shift
))
17221 /* Compute the length of a branch sequence, and adjust the
17222 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17223 worst-case length is computed, with UPDATE being used to indicate
17224 whether an unconditional (-1), branch-likely (+1) or regular (0)
17225 branch is to be computed. */
17227 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17229 bfd_boolean toofar
;
17233 && S_IS_DEFINED (fragp
->fr_symbol
)
17234 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17239 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17241 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17245 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17248 /* If the symbol is not defined or it's in a different segment,
17249 assume the user knows what's going on and emit a short
17255 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17257 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17258 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17259 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17260 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17266 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17269 if (mips_pic
!= NO_PIC
)
17271 /* Additional space for PIC loading of target address. */
17273 if (mips_opts
.isa
== ISA_MIPS1
)
17274 /* Additional space for $at-stabilizing nop. */
17278 /* If branch is conditional. */
17279 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17286 /* Compute the length of a branch sequence, and adjust the
17287 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17288 worst-case length is computed, with UPDATE being used to indicate
17289 whether an unconditional (-1), or regular (0) branch is to be
17293 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17295 bfd_boolean toofar
;
17299 && S_IS_DEFINED (fragp
->fr_symbol
)
17300 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17305 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17306 /* Ignore the low bit in the target, since it will be set
17307 for a text label. */
17308 if ((val
& 1) != 0)
17311 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17315 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17318 /* If the symbol is not defined or it's in a different segment,
17319 assume the user knows what's going on and emit a short
17325 if (fragp
&& update
17326 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17327 fragp
->fr_subtype
= (toofar
17328 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17329 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17334 bfd_boolean compact_known
= fragp
!= NULL
;
17335 bfd_boolean compact
= FALSE
;
17336 bfd_boolean uncond
;
17339 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17341 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17343 uncond
= update
< 0;
17345 /* If label is out of range, we turn branch <br>:
17347 <br> label # 4 bytes
17353 nop # 2 bytes if compact && !PIC
17356 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17359 /* If assembling PIC code, we further turn:
17365 lw/ld at, %got(label)(gp) # 4 bytes
17366 d/addiu at, %lo(label) # 4 bytes
17369 if (mips_pic
!= NO_PIC
)
17372 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17374 <brneg> 0f # 4 bytes
17375 nop # 2 bytes if !compact
17378 length
+= (compact_known
&& compact
) ? 4 : 6;
17384 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17385 bit accordingly. */
17388 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17390 bfd_boolean toofar
;
17393 && S_IS_DEFINED (fragp
->fr_symbol
)
17394 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17400 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17401 /* Ignore the low bit in the target, since it will be set
17402 for a text label. */
17403 if ((val
& 1) != 0)
17406 /* Assume this is a 2-byte branch. */
17407 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17409 /* We try to avoid the infinite loop by not adding 2 more bytes for
17414 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17416 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17417 else if (type
== 'E')
17418 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17423 /* If the symbol is not defined or it's in a different segment,
17424 we emit a normal 32-bit branch. */
17427 if (fragp
&& update
17428 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17430 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17431 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17439 /* Estimate the size of a frag before relaxing. Unless this is the
17440 mips16, we are not really relaxing here, and the final size is
17441 encoded in the subtype information. For the mips16, we have to
17442 decide whether we are using an extended opcode or not. */
17445 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17449 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17452 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17454 return fragp
->fr_var
;
17457 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17458 /* We don't want to modify the EXTENDED bit here; it might get us
17459 into infinite loops. We change it only in mips_relax_frag(). */
17460 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17462 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17466 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17467 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17468 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17469 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17470 fragp
->fr_var
= length
;
17475 if (mips_pic
== NO_PIC
)
17476 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17477 else if (mips_pic
== SVR4_PIC
)
17478 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17479 else if (mips_pic
== VXWORKS_PIC
)
17480 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17487 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17488 return -RELAX_FIRST (fragp
->fr_subtype
);
17491 return -RELAX_SECOND (fragp
->fr_subtype
);
17494 /* This is called to see whether a reloc against a defined symbol
17495 should be converted into a reloc against a section. */
17498 mips_fix_adjustable (fixS
*fixp
)
17500 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17501 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17504 if (fixp
->fx_addsy
== NULL
)
17507 /* If symbol SYM is in a mergeable section, relocations of the form
17508 SYM + 0 can usually be made section-relative. The mergeable data
17509 is then identified by the section offset rather than by the symbol.
17511 However, if we're generating REL LO16 relocations, the offset is split
17512 between the LO16 and parterning high part relocation. The linker will
17513 need to recalculate the complete offset in order to correctly identify
17516 The linker has traditionally not looked for the parterning high part
17517 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17518 placed anywhere. Rather than break backwards compatibility by changing
17519 this, it seems better not to force the issue, and instead keep the
17520 original symbol. This will work with either linker behavior. */
17521 if ((lo16_reloc_p (fixp
->fx_r_type
)
17522 || reloc_needs_lo_p (fixp
->fx_r_type
))
17523 && HAVE_IN_PLACE_ADDENDS
17524 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17527 /* There is no place to store an in-place offset for JALR relocations.
17528 Likewise an in-range offset of PC-relative relocations may overflow
17529 the in-place relocatable field if recalculated against the start
17530 address of the symbol's containing section. */
17531 if (HAVE_IN_PLACE_ADDENDS
17532 && (fixp
->fx_pcrel
|| jalr_reloc_p (fixp
->fx_r_type
)))
17536 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17537 to a floating-point stub. The same is true for non-R_MIPS16_26
17538 relocations against MIPS16 functions; in this case, the stub becomes
17539 the function's canonical address.
17541 Floating-point stubs are stored in unique .mips16.call.* or
17542 .mips16.fn.* sections. If a stub T for function F is in section S,
17543 the first relocation in section S must be against F; this is how the
17544 linker determines the target function. All relocations that might
17545 resolve to T must also be against F. We therefore have the following
17546 restrictions, which are given in an intentionally-redundant way:
17548 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17551 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17552 if that stub might be used.
17554 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17557 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17558 that stub might be used.
17560 There is a further restriction:
17562 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17563 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17564 targets with in-place addends; the relocation field cannot
17565 encode the low bit.
17567 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17568 against a MIPS16 symbol. We deal with (5) by by not reducing any
17569 such relocations on REL targets.
17571 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17572 relocation against some symbol R, no relocation against R may be
17573 reduced. (Note that this deals with (2) as well as (1) because
17574 relocations against global symbols will never be reduced on ELF
17575 targets.) This approach is a little simpler than trying to detect
17576 stub sections, and gives the "all or nothing" per-symbol consistency
17577 that we have for MIPS16 symbols. */
17579 && fixp
->fx_subsy
== NULL
17580 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17581 || *symbol_get_tc (fixp
->fx_addsy
)
17582 || (HAVE_IN_PLACE_ADDENDS
17583 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17584 && jmp_reloc_p (fixp
->fx_r_type
))))
17591 /* Translate internal representation of relocation info to BFD target
17595 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17597 static arelent
*retval
[4];
17599 bfd_reloc_code_real_type code
;
17601 memset (retval
, 0, sizeof(retval
));
17602 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17603 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17604 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17605 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17607 if (fixp
->fx_pcrel
)
17609 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17610 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17611 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17612 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17614 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17615 Relocations want only the symbol offset. */
17616 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17619 /* A gruesome hack which is a result of the gruesome gas
17620 reloc handling. What's worse, for COFF (as opposed to
17621 ECOFF), we might need yet another copy of reloc->address.
17622 See bfd_install_relocation. */
17623 reloc
->addend
+= reloc
->address
;
17627 reloc
->addend
= fixp
->fx_addnumber
;
17629 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17630 entry to be used in the relocation's section offset. */
17631 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17633 reloc
->address
= reloc
->addend
;
17637 code
= fixp
->fx_r_type
;
17639 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17640 if (reloc
->howto
== NULL
)
17642 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17643 _("Can not represent %s relocation in this object file format"),
17644 bfd_get_reloc_code_name (code
));
17651 /* Relax a machine dependent frag. This returns the amount by which
17652 the current size of the frag should change. */
17655 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17657 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17659 offsetT old_var
= fragp
->fr_var
;
17661 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17663 return fragp
->fr_var
- old_var
;
17666 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17668 offsetT old_var
= fragp
->fr_var
;
17669 offsetT new_var
= 4;
17671 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17672 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17673 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17674 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17675 fragp
->fr_var
= new_var
;
17677 return new_var
- old_var
;
17680 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17683 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17685 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17687 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17692 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17694 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17701 /* Convert a machine dependent frag. */
17704 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17706 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17709 unsigned long insn
;
17713 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
17715 if (target_big_endian
)
17716 insn
= bfd_getb32 (buf
);
17718 insn
= bfd_getl32 (buf
);
17720 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17722 /* We generate a fixup instead of applying it right now
17723 because, if there are linker relaxations, we're going to
17724 need the relocations. */
17725 exp
.X_op
= O_symbol
;
17726 exp
.X_add_symbol
= fragp
->fr_symbol
;
17727 exp
.X_add_number
= fragp
->fr_offset
;
17729 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17730 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
17731 fixp
->fx_file
= fragp
->fr_file
;
17732 fixp
->fx_line
= fragp
->fr_line
;
17734 md_number_to_chars ((char *) buf
, insn
, 4);
17741 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17742 _("Relaxed out-of-range branch into a jump"));
17744 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17747 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17749 /* Reverse the branch. */
17750 switch ((insn
>> 28) & 0xf)
17753 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17754 have the condition reversed by tweaking a single
17755 bit, and their opcodes all have 0x4???????. */
17756 gas_assert ((insn
& 0xf1000000) == 0x41000000);
17757 insn
^= 0x00010000;
17761 /* bltz 0x04000000 bgez 0x04010000
17762 bltzal 0x04100000 bgezal 0x04110000 */
17763 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17764 insn
^= 0x00010000;
17768 /* beq 0x10000000 bne 0x14000000
17769 blez 0x18000000 bgtz 0x1c000000 */
17770 insn
^= 0x04000000;
17778 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17780 /* Clear the and-link bit. */
17781 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17783 /* bltzal 0x04100000 bgezal 0x04110000
17784 bltzall 0x04120000 bgezall 0x04130000 */
17785 insn
&= ~0x00100000;
17788 /* Branch over the branch (if the branch was likely) or the
17789 full jump (not likely case). Compute the offset from the
17790 current instruction to branch to. */
17791 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17795 /* How many bytes in instructions we've already emitted? */
17796 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
17797 /* How many bytes in instructions from here to the end? */
17798 i
= fragp
->fr_var
- i
;
17800 /* Convert to instruction count. */
17802 /* Branch counts from the next instruction. */
17805 /* Branch over the jump. */
17806 md_number_to_chars ((char *) buf
, insn
, 4);
17810 md_number_to_chars ((char *) buf
, 0, 4);
17813 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17815 /* beql $0, $0, 2f */
17817 /* Compute the PC offset from the current instruction to
17818 the end of the variable frag. */
17819 /* How many bytes in instructions we've already emitted? */
17820 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
17821 /* How many bytes in instructions from here to the end? */
17822 i
= fragp
->fr_var
- i
;
17823 /* Convert to instruction count. */
17825 /* Don't decrement i, because we want to branch over the
17829 md_number_to_chars ((char *) buf
, insn
, 4);
17832 md_number_to_chars ((char *) buf
, 0, 4);
17837 if (mips_pic
== NO_PIC
)
17840 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17841 ? 0x0c000000 : 0x08000000);
17842 exp
.X_op
= O_symbol
;
17843 exp
.X_add_symbol
= fragp
->fr_symbol
;
17844 exp
.X_add_number
= fragp
->fr_offset
;
17846 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17847 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
17848 fixp
->fx_file
= fragp
->fr_file
;
17849 fixp
->fx_line
= fragp
->fr_line
;
17851 md_number_to_chars ((char *) buf
, insn
, 4);
17856 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17858 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17859 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17860 insn
|= at
<< OP_SH_RT
;
17861 exp
.X_op
= O_symbol
;
17862 exp
.X_add_symbol
= fragp
->fr_symbol
;
17863 exp
.X_add_number
= fragp
->fr_offset
;
17865 if (fragp
->fr_offset
)
17867 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17868 exp
.X_add_number
= 0;
17871 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17872 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
17873 fixp
->fx_file
= fragp
->fr_file
;
17874 fixp
->fx_line
= fragp
->fr_line
;
17876 md_number_to_chars ((char *) buf
, insn
, 4);
17879 if (mips_opts
.isa
== ISA_MIPS1
)
17882 md_number_to_chars ((char *) buf
, 0, 4);
17886 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17887 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
17888 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
17890 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17891 4, &exp
, FALSE
, BFD_RELOC_LO16
);
17892 fixp
->fx_file
= fragp
->fr_file
;
17893 fixp
->fx_line
= fragp
->fr_line
;
17895 md_number_to_chars ((char *) buf
, insn
, 4);
17899 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17903 insn
|= at
<< OP_SH_RS
;
17905 md_number_to_chars ((char *) buf
, insn
, 4);
17910 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
17911 + fragp
->fr_fix
+ fragp
->fr_var
);
17913 fragp
->fr_fix
+= fragp
->fr_var
;
17918 /* Relax microMIPS branches. */
17919 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17921 bfd_byte
*buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
17922 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17923 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17924 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17925 bfd_boolean short_ds
;
17926 unsigned long insn
;
17930 exp
.X_op
= O_symbol
;
17931 exp
.X_add_symbol
= fragp
->fr_symbol
;
17932 exp
.X_add_number
= fragp
->fr_offset
;
17934 fragp
->fr_fix
+= fragp
->fr_var
;
17936 /* Handle 16-bit branches that fit or are forced to fit. */
17937 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17939 /* We generate a fixup instead of applying it right now,
17940 because if there is linker relaxation, we're going to
17941 need the relocations. */
17943 fixp
= fix_new_exp (fragp
,
17944 buf
- (bfd_byte
*) fragp
->fr_literal
,
17946 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
17947 else if (type
== 'E')
17948 fixp
= fix_new_exp (fragp
,
17949 buf
- (bfd_byte
*) fragp
->fr_literal
,
17951 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
17955 fixp
->fx_file
= fragp
->fr_file
;
17956 fixp
->fx_line
= fragp
->fr_line
;
17958 /* These relocations can have an addend that won't fit in
17960 fixp
->fx_no_overflow
= 1;
17965 /* Handle 32-bit branches that fit or are forced to fit. */
17966 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17967 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17969 /* We generate a fixup instead of applying it right now,
17970 because if there is linker relaxation, we're going to
17971 need the relocations. */
17972 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
17973 4, &exp
, TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17974 fixp
->fx_file
= fragp
->fr_file
;
17975 fixp
->fx_line
= fragp
->fr_line
;
17981 /* Relax 16-bit branches to 32-bit branches. */
17984 if (target_big_endian
)
17985 insn
= bfd_getb16 (buf
);
17987 insn
= bfd_getl16 (buf
);
17989 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
17990 insn
= 0x94000000; /* beq */
17991 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17993 unsigned long regno
;
17995 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
17996 regno
= micromips_to_32_reg_d_map
[regno
];
17997 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
17998 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18003 /* Nothing else to do, just write it out. */
18004 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18005 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18007 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18009 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18012 gas_assert (buf
== ((bfd_byte
*) fragp
->fr_literal
18019 unsigned long next
;
18021 if (target_big_endian
)
18023 insn
= bfd_getb16 (buf
);
18024 next
= bfd_getb16 (buf
+ 2);
18028 insn
= bfd_getl16 (buf
);
18029 next
= bfd_getl16 (buf
+ 2);
18031 insn
= (insn
<< 16) | next
;
18034 /* Relax 32-bit branches to a sequence of instructions. */
18035 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18036 _("Relaxed out-of-range branch into a jump"));
18038 /* Set the short-delay-slot bit. */
18039 short_ds
= al
&& (insn
& 0x02000000) != 0;
18041 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18045 /* Reverse the branch. */
18046 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18047 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18048 insn
^= 0x20000000;
18049 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18050 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18051 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18052 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18053 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18054 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18055 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18056 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18057 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18058 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18059 insn
^= 0x00400000;
18060 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18061 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18062 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18063 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18064 insn
^= 0x00200000;
18070 /* Clear the and-link and short-delay-slot bits. */
18071 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18073 /* bltzal 0x40200000 bgezal 0x40600000 */
18074 /* bltzals 0x42200000 bgezals 0x42600000 */
18075 insn
&= ~0x02200000;
18078 /* Make a label at the end for use with the branch. */
18079 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18080 micromips_label_inc ();
18081 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18083 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18087 fixp
= fix_new (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18088 4, l
, 0, TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18089 fixp
->fx_file
= fragp
->fr_file
;
18090 fixp
->fx_line
= fragp
->fr_line
;
18092 /* Branch over the jump. */
18093 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18095 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18102 md_number_to_chars ((char *) buf
, insn
, 2);
18107 if (mips_pic
== NO_PIC
)
18109 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18111 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18112 insn
= al
? jal
: 0xd4000000;
18114 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18115 4, &exp
, FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18116 fixp
->fx_file
= fragp
->fr_file
;
18117 fixp
->fx_line
= fragp
->fr_line
;
18119 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18121 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18128 md_number_to_chars ((char *) buf
, insn
, 2);
18134 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18135 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18136 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18138 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18139 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18140 insn
|= at
<< MICROMIPSOP_SH_RT
;
18142 if (exp
.X_add_number
)
18144 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18145 exp
.X_add_number
= 0;
18148 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18149 4, &exp
, FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18150 fixp
->fx_file
= fragp
->fr_file
;
18151 fixp
->fx_line
= fragp
->fr_line
;
18153 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18155 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18158 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18159 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18160 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18162 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18163 4, &exp
, FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18164 fixp
->fx_file
= fragp
->fr_file
;
18165 fixp
->fx_line
= fragp
->fr_line
;
18167 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18169 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18172 /* jr/jrc/jalr/jalrs $at */
18173 insn
= al
? jalr
: jr
;
18174 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18176 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18180 gas_assert (buf
== (bfd_byte
*) fragp
->fr_literal
+ fragp
->fr_fix
);
18184 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18187 const struct mips16_immed_operand
*op
;
18188 bfd_boolean small
, ext
;
18191 unsigned long insn
;
18192 bfd_boolean use_extend
;
18193 unsigned short extend
;
18195 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18196 op
= mips16_immed_operands
;
18197 while (op
->type
!= type
)
18200 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18211 val
= resolve_symbol_value (fragp
->fr_symbol
);
18216 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18218 /* The rules for the base address of a PC relative reloc are
18219 complicated; see mips16_extended_frag. */
18220 if (type
== 'p' || type
== 'q')
18225 /* Ignore the low bit in the target, since it will be
18226 set for a text label. */
18227 if ((val
& 1) != 0)
18230 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18232 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18235 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18238 /* Make sure the section winds up with the alignment we have
18241 record_alignment (asec
, op
->shift
);
18245 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18246 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18247 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18248 _("extended instruction in delay slot"));
18250 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
18252 if (target_big_endian
)
18253 insn
= bfd_getb16 (buf
);
18255 insn
= bfd_getl16 (buf
);
18257 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
18258 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
18259 small
, ext
, &insn
, &use_extend
, &extend
);
18263 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
18264 fragp
->fr_fix
+= 2;
18268 md_number_to_chars ((char *) buf
, insn
, 2);
18269 fragp
->fr_fix
+= 2;
18274 relax_substateT subtype
= fragp
->fr_subtype
;
18275 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18276 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18280 first
= RELAX_FIRST (subtype
);
18281 second
= RELAX_SECOND (subtype
);
18282 fixp
= (fixS
*) fragp
->fr_opcode
;
18284 /* If the delay slot chosen does not match the size of the instruction,
18285 then emit a warning. */
18286 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18287 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18292 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18293 | RELAX_DELAY_SLOT_SIZE_FIRST
18294 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18295 msg
= macro_warning (s
);
18297 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18301 /* Possibly emit a warning if we've chosen the longer option. */
18302 if (use_second
== second_longer
)
18308 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18309 msg
= macro_warning (s
);
18311 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18315 /* Go through all the fixups for the first sequence. Disable them
18316 (by marking them as done) if we're going to use the second
18317 sequence instead. */
18319 && fixp
->fx_frag
== fragp
18320 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18322 if (subtype
& RELAX_USE_SECOND
)
18324 fixp
= fixp
->fx_next
;
18327 /* Go through the fixups for the second sequence. Disable them if
18328 we're going to use the first sequence, otherwise adjust their
18329 addresses to account for the relaxation. */
18330 while (fixp
&& fixp
->fx_frag
== fragp
)
18332 if (subtype
& RELAX_USE_SECOND
)
18333 fixp
->fx_where
-= first
;
18336 fixp
= fixp
->fx_next
;
18339 /* Now modify the frag contents. */
18340 if (subtype
& RELAX_USE_SECOND
)
18344 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18345 memmove (start
, start
+ first
, second
);
18346 fragp
->fr_fix
-= first
;
18349 fragp
->fr_fix
-= second
;
18355 /* This function is called after the relocs have been generated.
18356 We've been storing mips16 text labels as odd. Here we convert them
18357 back to even for the convenience of the debugger. */
18360 mips_frob_file_after_relocs (void)
18363 unsigned int count
, i
;
18368 syms
= bfd_get_outsymbols (stdoutput
);
18369 count
= bfd_get_symcount (stdoutput
);
18370 for (i
= 0; i
< count
; i
++, syms
++)
18371 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18372 && ((*syms
)->value
& 1) != 0)
18374 (*syms
)->value
&= ~1;
18375 /* If the symbol has an odd size, it was probably computed
18376 incorrectly, so adjust that as well. */
18377 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18378 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18384 /* This function is called whenever a label is defined, including fake
18385 labels instantiated off the dot special symbol. It is used when
18386 handling branch delays; if a branch has a label, we assume we cannot
18387 move it. This also bumps the value of the symbol by 1 in compressed
18391 mips_record_label (symbolS
*sym
)
18393 segment_info_type
*si
= seg_info (now_seg
);
18394 struct insn_label_list
*l
;
18396 if (free_insn_labels
== NULL
)
18397 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18400 l
= free_insn_labels
;
18401 free_insn_labels
= l
->next
;
18405 l
->next
= si
->label_list
;
18406 si
->label_list
= l
;
18409 /* This function is called as tc_frob_label() whenever a label is defined
18410 and adds a DWARF-2 record we only want for true labels. */
18413 mips_define_label (symbolS
*sym
)
18415 mips_record_label (sym
);
18417 dwarf2_emit_label (sym
);
18421 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18423 /* Some special processing for a MIPS ELF file. */
18426 mips_elf_final_processing (void)
18428 /* Write out the register information. */
18429 if (mips_abi
!= N64_ABI
)
18433 s
.ri_gprmask
= mips_gprmask
;
18434 s
.ri_cprmask
[0] = mips_cprmask
[0];
18435 s
.ri_cprmask
[1] = mips_cprmask
[1];
18436 s
.ri_cprmask
[2] = mips_cprmask
[2];
18437 s
.ri_cprmask
[3] = mips_cprmask
[3];
18438 /* The gp_value field is set by the MIPS ELF backend. */
18440 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18441 ((Elf32_External_RegInfo
*)
18442 mips_regmask_frag
));
18446 Elf64_Internal_RegInfo s
;
18448 s
.ri_gprmask
= mips_gprmask
;
18450 s
.ri_cprmask
[0] = mips_cprmask
[0];
18451 s
.ri_cprmask
[1] = mips_cprmask
[1];
18452 s
.ri_cprmask
[2] = mips_cprmask
[2];
18453 s
.ri_cprmask
[3] = mips_cprmask
[3];
18454 /* The gp_value field is set by the MIPS ELF backend. */
18456 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18457 ((Elf64_External_RegInfo
*)
18458 mips_regmask_frag
));
18461 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18462 sort of BFD interface for this. */
18463 if (mips_any_noreorder
)
18464 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18465 if (mips_pic
!= NO_PIC
)
18467 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18468 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18471 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18473 /* Set MIPS ELF flags for ASEs. */
18474 /* We may need to define a new flag for DSP ASE, and set this flag when
18475 file_ase_dsp is true. */
18476 /* Same for DSP R2. */
18477 /* We may need to define a new flag for MT ASE, and set this flag when
18478 file_ase_mt is true. */
18479 if (file_ase_mips16
)
18480 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18481 if (file_ase_micromips
)
18482 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18483 #if 0 /* XXX FIXME */
18484 if (file_ase_mips3d
)
18485 elf_elfheader (stdoutput
)->e_flags
|= ???;
18488 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18490 /* Set the MIPS ELF ABI flags. */
18491 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18492 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18493 else if (mips_abi
== O64_ABI
)
18494 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18495 else if (mips_abi
== EABI_ABI
)
18497 if (!file_mips_gp32
)
18498 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18500 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18502 else if (mips_abi
== N32_ABI
)
18503 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18505 /* Nothing to do for N64_ABI. */
18507 if (mips_32bitmode
)
18508 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18510 #if 0 /* XXX FIXME */
18511 /* 32 bit code with 64 bit FP registers. */
18512 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18513 elf_elfheader (stdoutput
)->e_flags
|= ???;
18517 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18519 typedef struct proc
{
18521 symbolS
*func_end_sym
;
18522 unsigned long reg_mask
;
18523 unsigned long reg_offset
;
18524 unsigned long fpreg_mask
;
18525 unsigned long fpreg_offset
;
18526 unsigned long frame_offset
;
18527 unsigned long frame_reg
;
18528 unsigned long pc_reg
;
18531 static procS cur_proc
;
18532 static procS
*cur_proc_ptr
;
18533 static int numprocs
;
18535 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18536 as "2", and a normal nop as "0". */
18538 #define NOP_OPCODE_MIPS 0
18539 #define NOP_OPCODE_MIPS16 1
18540 #define NOP_OPCODE_MICROMIPS 2
18543 mips_nop_opcode (void)
18545 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18546 return NOP_OPCODE_MICROMIPS
;
18547 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18548 return NOP_OPCODE_MIPS16
;
18550 return NOP_OPCODE_MIPS
;
18553 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18554 32-bit microMIPS NOPs here (if applicable). */
18557 mips_handle_align (fragS
*fragp
)
18561 int bytes
, size
, excess
;
18564 if (fragp
->fr_type
!= rs_align_code
)
18567 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18569 switch (nop_opcode
)
18571 case NOP_OPCODE_MICROMIPS
:
18572 opcode
= micromips_nop32_insn
.insn_opcode
;
18575 case NOP_OPCODE_MIPS16
:
18576 opcode
= mips16_nop_insn
.insn_opcode
;
18579 case NOP_OPCODE_MIPS
:
18581 opcode
= nop_insn
.insn_opcode
;
18586 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18587 excess
= bytes
% size
;
18589 /* Handle the leading part if we're not inserting a whole number of
18590 instructions, and make it the end of the fixed part of the frag.
18591 Try to fit in a short microMIPS NOP if applicable and possible,
18592 and use zeroes otherwise. */
18593 gas_assert (excess
< 4);
18594 fragp
->fr_fix
+= excess
;
18599 /* Fall through. */
18601 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
18603 md_number_to_chars (p
, micromips_nop16_insn
.insn_opcode
, 2);
18608 /* Fall through. */
18611 /* Fall through. */
18616 md_number_to_chars (p
, opcode
, size
);
18617 fragp
->fr_var
= size
;
18621 md_obj_begin (void)
18628 /* Check for premature end, nesting errors, etc. */
18630 as_warn (_("missing .end at end of assembly"));
18639 if (*input_line_pointer
== '-')
18641 ++input_line_pointer
;
18644 if (!ISDIGIT (*input_line_pointer
))
18645 as_bad (_("expected simple number"));
18646 if (input_line_pointer
[0] == '0')
18648 if (input_line_pointer
[1] == 'x')
18650 input_line_pointer
+= 2;
18651 while (ISXDIGIT (*input_line_pointer
))
18654 val
|= hex_value (*input_line_pointer
++);
18656 return negative
? -val
: val
;
18660 ++input_line_pointer
;
18661 while (ISDIGIT (*input_line_pointer
))
18664 val
|= *input_line_pointer
++ - '0';
18666 return negative
? -val
: val
;
18669 if (!ISDIGIT (*input_line_pointer
))
18671 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18672 *input_line_pointer
, *input_line_pointer
);
18673 as_warn (_("invalid number"));
18676 while (ISDIGIT (*input_line_pointer
))
18679 val
+= *input_line_pointer
++ - '0';
18681 return negative
? -val
: val
;
18684 /* The .file directive; just like the usual .file directive, but there
18685 is an initial number which is the ECOFF file index. In the non-ECOFF
18686 case .file implies DWARF-2. */
18689 s_mips_file (int x ATTRIBUTE_UNUSED
)
18691 static int first_file_directive
= 0;
18693 if (ECOFF_DEBUGGING
)
18702 filename
= dwarf2_directive_file (0);
18704 /* Versions of GCC up to 3.1 start files with a ".file"
18705 directive even for stabs output. Make sure that this
18706 ".file" is handled. Note that you need a version of GCC
18707 after 3.1 in order to support DWARF-2 on MIPS. */
18708 if (filename
!= NULL
&& ! first_file_directive
)
18710 (void) new_logical_line (filename
, -1);
18711 s_app_file_string (filename
, 0);
18713 first_file_directive
= 1;
18717 /* The .loc directive, implying DWARF-2. */
18720 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18722 if (!ECOFF_DEBUGGING
)
18723 dwarf2_directive_loc (0);
18726 /* The .end directive. */
18729 s_mips_end (int x ATTRIBUTE_UNUSED
)
18733 /* Following functions need their own .frame and .cprestore directives. */
18734 mips_frame_reg_valid
= 0;
18735 mips_cprestore_valid
= 0;
18737 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18740 demand_empty_rest_of_line ();
18745 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18746 as_warn (_(".end not in text section"));
18750 as_warn (_(".end directive without a preceding .ent directive."));
18751 demand_empty_rest_of_line ();
18757 gas_assert (S_GET_NAME (p
));
18758 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18759 as_warn (_(".end symbol does not match .ent symbol."));
18761 if (debug_type
== DEBUG_STABS
)
18762 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18766 as_warn (_(".end directive missing or unknown symbol"));
18769 /* Create an expression to calculate the size of the function. */
18770 if (p
&& cur_proc_ptr
)
18772 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18773 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18776 exp
->X_op
= O_subtract
;
18777 exp
->X_add_symbol
= symbol_temp_new_now ();
18778 exp
->X_op_symbol
= p
;
18779 exp
->X_add_number
= 0;
18781 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18784 /* Generate a .pdr section. */
18785 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
18787 segT saved_seg
= now_seg
;
18788 subsegT saved_subseg
= now_subseg
;
18792 #ifdef md_flush_pending_output
18793 md_flush_pending_output ();
18796 gas_assert (pdr_seg
);
18797 subseg_set (pdr_seg
, 0);
18799 /* Write the symbol. */
18800 exp
.X_op
= O_symbol
;
18801 exp
.X_add_symbol
= p
;
18802 exp
.X_add_number
= 0;
18803 emit_expr (&exp
, 4);
18805 fragp
= frag_more (7 * 4);
18807 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18808 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18809 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18810 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18811 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18812 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18813 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18815 subseg_set (saved_seg
, saved_subseg
);
18817 #endif /* OBJ_ELF */
18819 cur_proc_ptr
= NULL
;
18822 /* The .aent and .ent directives. */
18825 s_mips_ent (int aent
)
18829 symbolP
= get_symbol ();
18830 if (*input_line_pointer
== ',')
18831 ++input_line_pointer
;
18832 SKIP_WHITESPACE ();
18833 if (ISDIGIT (*input_line_pointer
)
18834 || *input_line_pointer
== '-')
18837 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18838 as_warn (_(".ent or .aent not in text section."));
18840 if (!aent
&& cur_proc_ptr
)
18841 as_warn (_("missing .end"));
18845 /* This function needs its own .frame and .cprestore directives. */
18846 mips_frame_reg_valid
= 0;
18847 mips_cprestore_valid
= 0;
18849 cur_proc_ptr
= &cur_proc
;
18850 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18852 cur_proc_ptr
->func_sym
= symbolP
;
18856 if (debug_type
== DEBUG_STABS
)
18857 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18858 S_GET_NAME (symbolP
));
18861 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18863 demand_empty_rest_of_line ();
18866 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18867 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18868 s_mips_frame is used so that we can set the PDR information correctly.
18869 We can't use the ecoff routines because they make reference to the ecoff
18870 symbol table (in the mdebug section). */
18873 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18876 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18880 if (cur_proc_ptr
== (procS
*) NULL
)
18882 as_warn (_(".frame outside of .ent"));
18883 demand_empty_rest_of_line ();
18887 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18889 SKIP_WHITESPACE ();
18890 if (*input_line_pointer
++ != ','
18891 || get_absolute_expression_and_terminator (&val
) != ',')
18893 as_warn (_("Bad .frame directive"));
18894 --input_line_pointer
;
18895 demand_empty_rest_of_line ();
18899 cur_proc_ptr
->frame_offset
= val
;
18900 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18902 demand_empty_rest_of_line ();
18905 #endif /* OBJ_ELF */
18909 /* The .fmask and .mask directives. If the mdebug section is present
18910 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18911 embedded targets, s_mips_mask is used so that we can set the PDR
18912 information correctly. We can't use the ecoff routines because they
18913 make reference to the ecoff symbol table (in the mdebug section). */
18916 s_mips_mask (int reg_type
)
18919 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18923 if (cur_proc_ptr
== (procS
*) NULL
)
18925 as_warn (_(".mask/.fmask outside of .ent"));
18926 demand_empty_rest_of_line ();
18930 if (get_absolute_expression_and_terminator (&mask
) != ',')
18932 as_warn (_("Bad .mask/.fmask directive"));
18933 --input_line_pointer
;
18934 demand_empty_rest_of_line ();
18938 off
= get_absolute_expression ();
18940 if (reg_type
== 'F')
18942 cur_proc_ptr
->fpreg_mask
= mask
;
18943 cur_proc_ptr
->fpreg_offset
= off
;
18947 cur_proc_ptr
->reg_mask
= mask
;
18948 cur_proc_ptr
->reg_offset
= off
;
18951 demand_empty_rest_of_line ();
18954 #endif /* OBJ_ELF */
18955 s_ignore (reg_type
);
18958 /* A table describing all the processors gas knows about. Names are
18959 matched in the order listed.
18961 To ease comparison, please keep this table in the same order as
18962 gcc's mips_cpu_info_table[]. */
18963 static const struct mips_cpu_info mips_cpu_info_table
[] =
18965 /* Entries for generic ISAs */
18966 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
18967 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
18968 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
18969 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
18970 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
18971 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
18972 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18973 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
18974 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
18977 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
18978 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
18979 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
18982 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
18985 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
18986 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
18987 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
18988 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
18989 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
18990 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
18991 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
18992 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
18993 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
18994 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
18995 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
18996 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
18997 /* ST Microelectronics Loongson 2E and 2F cores */
18998 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
18999 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19002 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
19003 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
19004 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
19005 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
19006 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
19007 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
19008 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
19009 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
19010 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
19011 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
19012 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
19013 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
19014 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
19015 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
19016 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
19019 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
19020 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
19021 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
19022 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19024 /* MIPS 32 Release 2 */
19025 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19026 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19027 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19028 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19029 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19030 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19031 { "m14k", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19032 { "m14kc", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19033 { "m14ke", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19034 ISA_MIPS32R2
, CPU_MIPS32R2
},
19035 { "m14kec", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19036 ISA_MIPS32R2
, CPU_MIPS32R2
},
19037 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19038 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19039 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19040 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19041 /* Deprecated forms of the above. */
19042 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19043 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19044 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19045 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19046 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19047 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19048 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19049 /* Deprecated forms of the above. */
19050 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19051 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19052 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19053 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19054 ISA_MIPS32R2
, CPU_MIPS32R2
},
19055 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19056 ISA_MIPS32R2
, CPU_MIPS32R2
},
19057 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19058 ISA_MIPS32R2
, CPU_MIPS32R2
},
19059 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19060 ISA_MIPS32R2
, CPU_MIPS32R2
},
19061 /* Deprecated forms of the above. */
19062 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19063 ISA_MIPS32R2
, CPU_MIPS32R2
},
19064 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19065 ISA_MIPS32R2
, CPU_MIPS32R2
},
19066 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19067 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19068 ISA_MIPS32R2
, CPU_MIPS32R2
},
19069 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19070 ISA_MIPS32R2
, CPU_MIPS32R2
},
19071 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19072 ISA_MIPS32R2
, CPU_MIPS32R2
},
19073 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19074 ISA_MIPS32R2
, CPU_MIPS32R2
},
19075 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19076 ISA_MIPS32R2
, CPU_MIPS32R2
},
19077 /* Deprecated forms of the above. */
19078 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19079 ISA_MIPS32R2
, CPU_MIPS32R2
},
19080 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19081 ISA_MIPS32R2
, CPU_MIPS32R2
},
19082 /* 1004K cores are multiprocessor versions of the 34K. */
19083 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19084 ISA_MIPS32R2
, CPU_MIPS32R2
},
19085 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19086 ISA_MIPS32R2
, CPU_MIPS32R2
},
19087 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19088 ISA_MIPS32R2
, CPU_MIPS32R2
},
19089 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19090 ISA_MIPS32R2
, CPU_MIPS32R2
},
19093 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
19094 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
19095 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19096 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19098 /* Broadcom SB-1 CPU core */
19099 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19100 ISA_MIPS64
, CPU_SB1
},
19101 /* Broadcom SB-1A CPU core */
19102 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19103 ISA_MIPS64
, CPU_SB1
},
19105 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19107 /* MIPS 64 Release 2 */
19109 /* Cavium Networks Octeon CPU core */
19110 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
19111 { "octeon+", 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19112 { "octeon2", 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19115 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
19122 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19123 with a final "000" replaced by "k". Ignore case.
19125 Note: this function is shared between GCC and GAS. */
19128 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19130 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19131 given
++, canonical
++;
19133 return ((*given
== 0 && *canonical
== 0)
19134 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19138 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19139 CPU name. We've traditionally allowed a lot of variation here.
19141 Note: this function is shared between GCC and GAS. */
19144 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19146 /* First see if the name matches exactly, or with a final "000"
19147 turned into "k". */
19148 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19151 /* If not, try comparing based on numerical designation alone.
19152 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19153 if (TOLOWER (*given
) == 'r')
19155 if (!ISDIGIT (*given
))
19158 /* Skip over some well-known prefixes in the canonical name,
19159 hoping to find a number there too. */
19160 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19162 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19164 else if (TOLOWER (canonical
[0]) == 'r')
19167 return mips_strict_matching_cpu_name_p (canonical
, given
);
19171 /* Parse an option that takes the name of a processor as its argument.
19172 OPTION is the name of the option and CPU_STRING is the argument.
19173 Return the corresponding processor enumeration if the CPU_STRING is
19174 recognized, otherwise report an error and return null.
19176 A similar function exists in GCC. */
19178 static const struct mips_cpu_info
*
19179 mips_parse_cpu (const char *option
, const char *cpu_string
)
19181 const struct mips_cpu_info
*p
;
19183 /* 'from-abi' selects the most compatible architecture for the given
19184 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19185 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19186 version. Look first at the -mgp options, if given, otherwise base
19187 the choice on MIPS_DEFAULT_64BIT.
19189 Treat NO_ABI like the EABIs. One reason to do this is that the
19190 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19191 architecture. This code picks MIPS I for 'mips' and MIPS III for
19192 'mips64', just as we did in the days before 'from-abi'. */
19193 if (strcasecmp (cpu_string
, "from-abi") == 0)
19195 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19196 return mips_cpu_info_from_isa (ISA_MIPS1
);
19198 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19199 return mips_cpu_info_from_isa (ISA_MIPS3
);
19201 if (file_mips_gp32
>= 0)
19202 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19204 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19209 /* 'default' has traditionally been a no-op. Probably not very useful. */
19210 if (strcasecmp (cpu_string
, "default") == 0)
19213 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19214 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19217 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19221 /* Return the canonical processor information for ISA (a member of the
19222 ISA_MIPS* enumeration). */
19224 static const struct mips_cpu_info
*
19225 mips_cpu_info_from_isa (int isa
)
19229 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19230 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19231 && isa
== mips_cpu_info_table
[i
].isa
)
19232 return (&mips_cpu_info_table
[i
]);
19237 static const struct mips_cpu_info
*
19238 mips_cpu_info_from_arch (int arch
)
19242 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19243 if (arch
== mips_cpu_info_table
[i
].cpu
)
19244 return (&mips_cpu_info_table
[i
]);
19250 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19254 fprintf (stream
, "%24s", "");
19259 fprintf (stream
, ", ");
19263 if (*col_p
+ strlen (string
) > 72)
19265 fprintf (stream
, "\n%24s", "");
19269 fprintf (stream
, "%s", string
);
19270 *col_p
+= strlen (string
);
19276 md_show_usage (FILE *stream
)
19281 fprintf (stream
, _("\
19283 -EB generate big endian output\n\
19284 -EL generate little endian output\n\
19285 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19286 -G NUM allow referencing objects up to NUM bytes\n\
19287 implicitly with the gp register [default 8]\n"));
19288 fprintf (stream
, _("\
19289 -mips1 generate MIPS ISA I instructions\n\
19290 -mips2 generate MIPS ISA II instructions\n\
19291 -mips3 generate MIPS ISA III instructions\n\
19292 -mips4 generate MIPS ISA IV instructions\n\
19293 -mips5 generate MIPS ISA V instructions\n\
19294 -mips32 generate MIPS32 ISA instructions\n\
19295 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19296 -mips64 generate MIPS64 ISA instructions\n\
19297 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19298 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19302 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19303 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19304 show (stream
, "from-abi", &column
, &first
);
19305 fputc ('\n', stream
);
19307 fprintf (stream
, _("\
19308 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19309 -no-mCPU don't generate code specific to CPU.\n\
19310 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19314 show (stream
, "3900", &column
, &first
);
19315 show (stream
, "4010", &column
, &first
);
19316 show (stream
, "4100", &column
, &first
);
19317 show (stream
, "4650", &column
, &first
);
19318 fputc ('\n', stream
);
19320 fprintf (stream
, _("\
19321 -mips16 generate mips16 instructions\n\
19322 -no-mips16 do not generate mips16 instructions\n"));
19323 fprintf (stream
, _("\
19324 -mmicromips generate microMIPS instructions\n\
19325 -mno-micromips do not generate microMIPS instructions\n"));
19326 fprintf (stream
, _("\
19327 -msmartmips generate smartmips instructions\n\
19328 -mno-smartmips do not generate smartmips instructions\n"));
19329 fprintf (stream
, _("\
19330 -mdsp generate DSP instructions\n\
19331 -mno-dsp do not generate DSP instructions\n"));
19332 fprintf (stream
, _("\
19333 -mdspr2 generate DSP R2 instructions\n\
19334 -mno-dspr2 do not generate DSP R2 instructions\n"));
19335 fprintf (stream
, _("\
19336 -mmt generate MT instructions\n\
19337 -mno-mt do not generate MT instructions\n"));
19338 fprintf (stream
, _("\
19339 -mmcu generate MCU instructions\n\
19340 -mno-mcu do not generate MCU instructions\n"));
19341 fprintf (stream
, _("\
19342 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19343 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19344 -mfix-vr4120 work around certain VR4120 errata\n\
19345 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19346 -mfix-24k insert a nop after ERET and DERET instructions\n\
19347 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19348 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19349 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19350 -msym32 assume all symbols have 32-bit values\n\
19351 -O0 remove unneeded NOPs, do not swap branches\n\
19352 -O remove unneeded NOPs and swap branches\n\
19353 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19354 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19355 fprintf (stream
, _("\
19356 -mhard-float allow floating-point instructions\n\
19357 -msoft-float do not allow floating-point instructions\n\
19358 -msingle-float only allow 32-bit floating-point operations\n\
19359 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19360 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19363 fprintf (stream
, _("\
19364 -KPIC, -call_shared generate SVR4 position independent code\n\
19365 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19366 -mvxworks-pic generate VxWorks position independent code\n\
19367 -non_shared do not generate code that can operate with DSOs\n\
19368 -xgot assume a 32 bit GOT\n\
19369 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19370 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19371 position dependent (non shared) code\n\
19372 -mabi=ABI create ABI conformant object file for:\n"));
19376 show (stream
, "32", &column
, &first
);
19377 show (stream
, "o64", &column
, &first
);
19378 show (stream
, "n32", &column
, &first
);
19379 show (stream
, "64", &column
, &first
);
19380 show (stream
, "eabi", &column
, &first
);
19382 fputc ('\n', stream
);
19384 fprintf (stream
, _("\
19385 -32 create o32 ABI object file (default)\n\
19386 -n32 create n32 ABI object file\n\
19387 -64 create 64 ABI object file\n"));
19393 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19395 if (HAVE_64BIT_SYMBOLS
)
19396 return dwarf2_format_64bit_irix
;
19398 return dwarf2_format_32bit
;
19403 mips_dwarf2_addr_size (void)
19405 if (HAVE_64BIT_OBJECTS
)
19411 /* Standard calling conventions leave the CFA at SP on entry. */
19413 mips_cfi_frame_initial_instructions (void)
19415 cfi_add_CFA_def_cfa_register (SP
);
19419 tc_mips_regname_to_dw2regnum (char *regname
)
19421 unsigned int regnum
= -1;
19424 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))