1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* start-sanitize-r5900 */
152 /* Whether Toshiba r5900 instructions are permitted. */
153 static int mips_5900
= -1;
154 /* end-sanitize-r5900 */
156 /* Whether the processor uses hardware interlocks, and thus does not
157 require nops to be inserted. */
158 static int interlocks
= -1;
160 /* As with "interlocks" this is used by hardware that has FP
161 (co-processor) interlocks. */
162 static int cop_interlocks
= -1;
164 /* MIPS PIC level. */
168 /* Do not generate PIC code. */
171 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
172 not sure what it is supposed to do. */
175 /* Generate PIC code as in the SVR4 MIPS ABI. */
178 /* Generate PIC code without using a global offset table: the data
179 segment has a maximum size of 64K, all data references are off
180 the $gp register, and all text references are PC relative. This
181 is used on some embedded systems. */
185 static enum mips_pic_level mips_pic
;
187 /* 1 if we should generate 32 bit offsets from the GP register in
188 SVR4_PIC mode. Currently has no meaning in other modes. */
189 static int mips_big_got
;
191 /* 1 if trap instructions should used for overflow rather than break
193 static int mips_trap
;
195 /* 1 if we should autoextend mips16 instructions. */
196 static int mips16_autoextend
= 1;
198 static int mips_warn_about_macros
;
199 static int mips_noreorder
;
200 static int mips_any_noreorder
;
201 static int mips_nomove
;
202 static int mips_noat
;
203 static int mips_nobopt
;
205 /* The size of the small data section. */
206 static int g_switch_value
= 8;
207 /* Whether the -G option was used. */
208 static int g_switch_seen
= 0;
213 /* If we can determine in advance that GP optimization won't be
214 possible, we can skip the relaxation stuff that tries to produce
215 GP-relative references. This makes delay slot optimization work
218 This function can only provide a guess, but it seems to work for
219 gcc output. If it guesses wrong, the only loss should be in
220 efficiency; it shouldn't introduce any bugs.
222 I don't know if a fix is needed for the SVR4_PIC mode. I've only
223 fixed it for the non-PIC mode. KR 95/04/07 */
224 static int nopic_need_relax
PARAMS ((symbolS
*));
226 /* handle of the OPCODE hash table */
227 static struct hash_control
*op_hash
= NULL
;
229 /* The opcode hash table we use for the mips16. */
230 static struct hash_control
*mips16_op_hash
= NULL
;
232 /* This array holds the chars that always start a comment. If the
233 pre-processor is disabled, these aren't very useful */
234 const char comment_chars
[] = "#";
236 /* This array holds the chars that only start a comment at the beginning of
237 a line. If the line seems to have the form '# 123 filename'
238 .line and .file directives will appear in the pre-processed output */
239 /* Note that input_file.c hand checks for '#' at the beginning of the
240 first line of the input file. This is because the compiler outputs
241 #NO_APP at the beginning of its output. */
242 /* Also note that C style comments are always supported. */
243 const char line_comment_chars
[] = "#";
245 /* This array holds machine specific line separator characters. */
246 const char line_separator_chars
[] = "";
248 /* Chars that can be used to separate mant from exp in floating point nums */
249 const char EXP_CHARS
[] = "eE";
251 /* Chars that mean this number is a floating point constant */
254 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
256 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
257 changed in read.c . Ideally it shouldn't have to know about it at all,
258 but nothing is ideal around here.
261 static char *insn_error
;
263 static int auto_align
= 1;
265 /* When outputting SVR4 PIC code, the assembler needs to know the
266 offset in the stack frame from which to restore the $gp register.
267 This is set by the .cprestore pseudo-op, and saved in this
269 static offsetT mips_cprestore_offset
= -1;
271 /* This is the register which holds the stack frame, as set by the
272 .frame pseudo-op. This is needed to implement .cprestore. */
273 static int mips_frame_reg
= SP
;
275 /* To output NOP instructions correctly, we need to keep information
276 about the previous two instructions. */
278 /* Whether we are optimizing. The default value of 2 means to remove
279 unneeded NOPs and swap branch instructions when possible. A value
280 of 1 means to not swap branches. A value of 0 means to always
282 static int mips_optimize
= 2;
284 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
285 equivalent to seeing no -g option at all. */
286 static int mips_debug
= 0;
288 /* The previous instruction. */
289 static struct mips_cl_insn prev_insn
;
291 /* The instruction before prev_insn. */
292 static struct mips_cl_insn prev_prev_insn
;
294 /* If we don't want information for prev_insn or prev_prev_insn, we
295 point the insn_mo field at this dummy integer. */
296 static const struct mips_opcode dummy_opcode
= { 0 };
298 /* Non-zero if prev_insn is valid. */
299 static int prev_insn_valid
;
301 /* The frag for the previous instruction. */
302 static struct frag
*prev_insn_frag
;
304 /* The offset into prev_insn_frag for the previous instruction. */
305 static long prev_insn_where
;
307 /* The reloc type for the previous instruction, if any. */
308 static bfd_reloc_code_real_type prev_insn_reloc_type
;
310 /* The reloc for the previous instruction, if any. */
311 static fixS
*prev_insn_fixp
;
313 /* Non-zero if the previous instruction was in a delay slot. */
314 static int prev_insn_is_delay_slot
;
316 /* Non-zero if the previous instruction was in a .set noreorder. */
317 static int prev_insn_unreordered
;
319 /* Non-zero if the previous instruction uses an extend opcode (if
321 static int prev_insn_extended
;
323 /* Non-zero if the previous previous instruction was in a .set
325 static int prev_prev_insn_unreordered
;
327 /* For ECOFF and ELF, relocations against symbols are done in two
328 parts, with a HI relocation and a LO relocation. Each relocation
329 has only 16 bits of space to store an addend. This means that in
330 order for the linker to handle carries correctly, it must be able
331 to locate both the HI and the LO relocation. This means that the
332 relocations must appear in order in the relocation table.
334 In order to implement this, we keep track of each unmatched HI
335 relocation. We then sort them so that they immediately precede the
336 corresponding LO relocation. */
341 struct mips_hi_fixup
*next
;
344 /* The section this fixup is in. */
348 /* The list of unmatched HI relocs. */
350 static struct mips_hi_fixup
*mips_hi_fixup_list
;
352 /* Map normal MIPS register numbers to mips16 register numbers. */
354 #define X ILLEGAL_REG
355 static const int mips32_to_16_reg_map
[] =
357 X
, X
, 2, 3, 4, 5, 6, 7,
358 X
, X
, X
, X
, X
, X
, X
, X
,
359 0, 1, X
, X
, X
, X
, X
, X
,
360 X
, X
, X
, X
, X
, X
, X
, X
364 /* Map mips16 register numbers to normal MIPS register numbers. */
366 static const int mips16_to_32_reg_map
[] =
368 16, 17, 2, 3, 4, 5, 6, 7
371 /* Since the MIPS does not have multiple forms of PC relative
372 instructions, we do not have to do relaxing as is done on other
373 platforms. However, we do have to handle GP relative addressing
374 correctly, which turns out to be a similar problem.
376 Every macro that refers to a symbol can occur in (at least) two
377 forms, one with GP relative addressing and one without. For
378 example, loading a global variable into a register generally uses
379 a macro instruction like this:
381 If i can be addressed off the GP register (this is true if it is in
382 the .sbss or .sdata section, or if it is known to be smaller than
383 the -G argument) this will generate the following instruction:
385 This instruction will use a GPREL reloc. If i can not be addressed
386 off the GP register, the following instruction sequence will be used:
389 In this case the first instruction will have a HI16 reloc, and the
390 second reloc will have a LO16 reloc. Both relocs will be against
393 The issue here is that we may not know whether i is GP addressable
394 until after we see the instruction that uses it. Therefore, we
395 want to be able to choose the final instruction sequence only at
396 the end of the assembly. This is similar to the way other
397 platforms choose the size of a PC relative instruction only at the
400 When generating position independent code we do not use GP
401 addressing in quite the same way, but the issue still arises as
402 external symbols and local symbols must be handled differently.
404 We handle these issues by actually generating both possible
405 instruction sequences. The longer one is put in a frag_var with
406 type rs_machine_dependent. We encode what to do with the frag in
407 the subtype field. We encode (1) the number of existing bytes to
408 replace, (2) the number of new bytes to use, (3) the offset from
409 the start of the existing bytes to the first reloc we must generate
410 (that is, the offset is applied from the start of the existing
411 bytes after they are replaced by the new bytes, if any), (4) the
412 offset from the start of the existing bytes to the second reloc,
413 (5) whether a third reloc is needed (the third reloc is always four
414 bytes after the second reloc), and (6) whether to warn if this
415 variant is used (this is sometimes needed if .set nomacro or .set
416 noat is in effect). All these numbers are reasonably small.
418 Generating two instruction sequences must be handled carefully to
419 ensure that delay slots are handled correctly. Fortunately, there
420 are a limited number of cases. When the second instruction
421 sequence is generated, append_insn is directed to maintain the
422 existing delay slot information, so it continues to apply to any
423 code after the second instruction sequence. This means that the
424 second instruction sequence must not impose any requirements not
425 required by the first instruction sequence.
427 These variant frags are then handled in functions called by the
428 machine independent code. md_estimate_size_before_relax returns
429 the final size of the frag. md_convert_frag sets up the final form
430 of the frag. tc_gen_reloc adjust the first reloc and adds a second
432 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
436 | (((reloc1) + 64) << 9) \
437 | (((reloc2) + 64) << 2) \
438 | ((reloc3) ? (1 << 1) : 0) \
440 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
441 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
442 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
443 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
444 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
445 #define RELAX_WARN(i) ((i) & 1)
447 /* For mips16 code, we use an entirely different form of relaxation.
448 mips16 supports two versions of most instructions which take
449 immediate values: a small one which takes some small value, and a
450 larger one which takes a 16 bit value. Since branches also follow
451 this pattern, relaxing these values is required.
453 We can assemble both mips16 and normal MIPS code in a single
454 object. Therefore, we need to support this type of relaxation at
455 the same time that we support the relaxation described above. We
456 use the high bit of the subtype field to distinguish these cases.
458 The information we store for this type of relaxation is the
459 argument code found in the opcode file for this relocation, whether
460 the user explicitly requested a small or extended form, and whether
461 the relocation is in a jump or jal delay slot. That tells us the
462 size of the value, and how it should be stored. We also store
463 whether the fragment is considered to be extended or not. We also
464 store whether this is known to be a branch to a different section,
465 whether we have tried to relax this frag yet, and whether we have
466 ever extended a PC relative fragment because of a shift count. */
467 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
470 | ((small) ? 0x100 : 0) \
471 | ((ext) ? 0x200 : 0) \
472 | ((dslot) ? 0x400 : 0) \
473 | ((jal_dslot) ? 0x800 : 0))
474 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
475 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
476 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
477 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
478 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
479 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
480 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
481 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
482 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
483 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
484 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
485 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
487 /* Prototypes for static functions. */
490 #define internalError() \
491 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
493 #define internalError() as_fatal ("MIPS internal Error");
496 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
498 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
499 unsigned int reg
, enum mips_regclass
class));
500 static int reg_needs_delay
PARAMS ((int));
501 static void append_insn
PARAMS ((char *place
,
502 struct mips_cl_insn
* ip
,
504 bfd_reloc_code_real_type r
,
506 static void mips_no_prev_insn
PARAMS ((void));
507 static void mips_emit_delays
PARAMS ((boolean
));
509 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
510 const char *name
, const char *fmt
,
513 static void macro_build ();
515 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
516 const char *, const char *,
518 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
519 expressionS
* ep
, int regnum
));
520 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
521 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
523 static void load_register
PARAMS ((int *, int, expressionS
*, int));
524 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
525 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
526 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
527 #ifdef LOSING_COMPILER
528 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
530 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
531 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
532 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
533 boolean
, boolean
, unsigned long *,
534 boolean
*, unsigned short *));
535 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
536 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
537 static symbolS
*get_symbol
PARAMS ((void));
538 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
539 static void s_align
PARAMS ((int));
540 static void s_change_sec
PARAMS ((int));
541 static void s_cons
PARAMS ((int));
542 static void s_float_cons
PARAMS ((int));
543 static void s_mips_globl
PARAMS ((int));
544 static void s_option
PARAMS ((int));
545 static void s_mipsset
PARAMS ((int));
546 static void s_abicalls
PARAMS ((int));
547 static void s_cpload
PARAMS ((int));
548 static void s_cprestore
PARAMS ((int));
549 static void s_gpword
PARAMS ((int));
550 static void s_cpadd
PARAMS ((int));
551 static void md_obj_begin
PARAMS ((void));
552 static void md_obj_end
PARAMS ((void));
553 static long get_number
PARAMS ((void));
554 static void s_ent
PARAMS ((int));
555 static void s_mipsend
PARAMS ((int));
556 static void s_file
PARAMS ((int));
557 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
561 The following pseudo-ops from the Kane and Heinrich MIPS book
562 should be defined here, but are currently unsupported: .alias,
563 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
565 The following pseudo-ops from the Kane and Heinrich MIPS book are
566 specific to the type of debugging information being generated, and
567 should be defined by the object format: .aent, .begin, .bend,
568 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
571 The following pseudo-ops from the Kane and Heinrich MIPS book are
572 not MIPS CPU specific, but are also not specific to the object file
573 format. This file is probably the best place to define them, but
574 they are not currently supported: .asm0, .endr, .lab, .repeat,
575 .struct, .weakext. */
577 static const pseudo_typeS mips_pseudo_table
[] =
579 /* MIPS specific pseudo-ops. */
580 {"option", s_option
, 0},
581 {"set", s_mipsset
, 0},
582 {"rdata", s_change_sec
, 'r'},
583 {"sdata", s_change_sec
, 's'},
584 {"livereg", s_ignore
, 0},
585 {"abicalls", s_abicalls
, 0},
586 {"cpload", s_cpload
, 0},
587 {"cprestore", s_cprestore
, 0},
588 {"gpword", s_gpword
, 0},
589 {"cpadd", s_cpadd
, 0},
591 /* Relatively generic pseudo-ops that happen to be used on MIPS
593 {"asciiz", stringer
, 1},
594 {"bss", s_change_sec
, 'b'},
597 {"dword", s_cons
, 3},
599 /* These pseudo-ops are defined in read.c, but must be overridden
600 here for one reason or another. */
601 {"align", s_align
, 0},
603 {"data", s_change_sec
, 'd'},
604 {"double", s_float_cons
, 'd'},
605 {"float", s_float_cons
, 'f'},
606 {"globl", s_mips_globl
, 0},
607 {"global", s_mips_globl
, 0},
608 {"hword", s_cons
, 1},
613 {"short", s_cons
, 1},
614 {"single", s_float_cons
, 'f'},
615 {"text", s_change_sec
, 't'},
620 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
621 /* These pseudo-ops should be defined by the object file format.
622 However, a.out doesn't support them, so we have versions here. */
624 {"bgnb", s_ignore
, 0},
625 {"end", s_mipsend
, 0},
626 {"endb", s_ignore
, 0},
629 {"fmask", s_ignore
, 'F'},
630 {"frame", s_ignore
, 0},
631 {"loc", s_ignore
, 0},
632 {"mask", s_ignore
, 'R'},
633 {"verstamp", s_ignore
, 0},
637 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
642 pop_insert (mips_pseudo_table
);
643 if (! ECOFF_DEBUGGING
)
644 pop_insert (mips_nonecoff_pseudo_table
);
647 /* Symbols labelling the current insn. */
649 struct insn_label_list
651 struct insn_label_list
*next
;
655 static struct insn_label_list
*insn_labels
;
656 static struct insn_label_list
*free_insn_labels
;
658 static void mips_clear_insn_labels
PARAMS ((void));
661 mips_clear_insn_labels ()
663 register struct insn_label_list
**pl
;
665 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
671 static char *expr_end
;
673 /* Expressions which appear in instructions. These are set by
676 static expressionS imm_expr
;
677 static expressionS offset_expr
;
679 /* Relocs associated with imm_expr and offset_expr. */
681 static bfd_reloc_code_real_type imm_reloc
;
682 static bfd_reloc_code_real_type offset_reloc
;
684 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
686 static boolean imm_unmatched_hi
;
688 /* These are set by mips16_ip if an explicit extension is used. */
690 static boolean mips16_small
, mips16_ext
;
693 * This function is called once, at assembler startup time. It should
694 * set up all the tables, etc. that the MD part of the assembler will need.
700 register const char *retval
= NULL
;
701 register unsigned int i
= 0;
709 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
711 a
= xmalloc (sizeof TARGET_CPU
);
712 strcpy (a
, TARGET_CPU
);
713 a
[(sizeof TARGET_CPU
) - 3] = '\0';
717 if (strcmp (cpu
, "mips") == 0)
723 else if (strcmp (cpu
, "r6000") == 0
724 || strcmp (cpu
, "mips2") == 0)
730 else if (strcmp (cpu
, "mips64") == 0
731 || strcmp (cpu
, "r4000") == 0
732 || strcmp (cpu
, "mips3") == 0)
738 else if (strcmp (cpu
, "r4400") == 0)
744 else if (strcmp (cpu
, "mips64orion") == 0
745 || strcmp (cpu
, "r4600") == 0)
751 else if (strcmp (cpu
, "r4650") == 0)
759 else if (strcmp (cpu
, "mips64vr4300") == 0)
765 else if (strcmp (cpu
, "mips64vr4100") == 0)
773 else if (strcmp (cpu
, "r4010") == 0)
781 else if (strcmp (cpu
, "r5000") == 0
782 || strcmp (cpu
, "mips64vr5000") == 0)
788 /* start-sanitize-r5900 */
789 else if (strcmp (cpu
, "r5900") == 0
790 || strcmp (cpu
, "mips64vr5900") == 0
791 || strcmp (cpu
, "mips64vr5900el") == 0)
799 /* end-sanitize-r5900 */
800 else if (strcmp (cpu
, "r8000") == 0
801 || strcmp (cpu
, "mips4") == 0)
807 else if (strcmp (cpu
, "r10000") == 0)
813 else if (strcmp (cpu
, "mips16") == 0)
817 mips_cpu
= 0; /* FIXME */
832 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
847 /* start-sanitize-r5900 */
850 /* end-sanitize-r5900 */
852 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
857 if (mips_cpu
== 4300)
862 if (mips_isa
< 2 && mips_trap
)
863 as_bad ("trap exception not supported at ISA 1");
868 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
871 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
874 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
877 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
881 as_warn ("Could not set architecture and machine");
883 file_mips_isa
= mips_isa
;
885 op_hash
= hash_new ();
887 for (i
= 0; i
< NUMOPCODES
;)
889 const char *name
= mips_opcodes
[i
].name
;
891 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
894 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
895 mips_opcodes
[i
].name
, retval
);
896 as_fatal ("Broken assembler. No assembly attempted.");
900 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
901 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
902 != mips_opcodes
[i
].match
))
904 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
905 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
906 as_fatal ("Broken assembler. No assembly attempted.");
910 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
913 mips16_op_hash
= hash_new ();
916 while (i
< bfd_mips16_num_opcodes
)
918 const char *name
= mips16_opcodes
[i
].name
;
920 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
922 as_fatal ("internal error: can't hash `%s': %s\n",
923 mips16_opcodes
[i
].name
, retval
);
926 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
927 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
928 != mips16_opcodes
[i
].match
))
929 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
930 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
933 while (i
< bfd_mips16_num_opcodes
934 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
937 mips_no_prev_insn ();
945 /* set the default alignment for the text section (2**2) */
946 record_alignment (text_section
, 2);
948 if (USE_GLOBAL_POINTER_OPT
)
949 bfd_set_gp_size (stdoutput
, g_switch_value
);
951 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
953 /* On a native system, sections must be aligned to 16 byte
954 boundaries. When configured for an embedded ELF target, we
956 if (strcmp (TARGET_OS
, "elf") != 0)
958 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
959 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
960 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
963 /* Create a .reginfo section for register masks and a .mdebug
964 section for debugging information. */
974 /* The ABI says this section should be loaded so that the
975 running program can access it. However, we don't load it
976 if we are configured for an embedded target */
977 flags
= SEC_READONLY
| SEC_DATA
;
978 if (strcmp (TARGET_OS
, "elf") != 0)
979 flags
|= SEC_ALLOC
| SEC_LOAD
;
983 sec
= subseg_new (".reginfo", (subsegT
) 0);
986 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
987 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
990 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
995 /* The 64-bit ABI uses a .MIPS.options section rather than
997 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
998 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
999 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1002 /* Set up the option header. */
1004 Elf_Internal_Options opthdr
;
1007 opthdr
.kind
= ODK_REGINFO
;
1008 opthdr
.size
= (sizeof (Elf_External_Options
)
1009 + sizeof (Elf64_External_RegInfo
));
1012 f
= frag_more (sizeof (Elf_External_Options
));
1013 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1014 (Elf_External_Options
*) f
);
1016 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1021 if (ECOFF_DEBUGGING
)
1023 sec
= subseg_new (".mdebug", (subsegT
) 0);
1024 (void) bfd_set_section_flags (stdoutput
, sec
,
1025 SEC_HAS_CONTENTS
| SEC_READONLY
);
1026 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1029 subseg_set (seg
, subseg
);
1033 if (! ECOFF_DEBUGGING
)
1040 if (! ECOFF_DEBUGGING
)
1048 struct mips_cl_insn insn
;
1050 imm_expr
.X_op
= O_absent
;
1051 imm_reloc
= BFD_RELOC_UNUSED
;
1052 imm_unmatched_hi
= false;
1053 offset_expr
.X_op
= O_absent
;
1054 offset_reloc
= BFD_RELOC_UNUSED
;
1057 mips16_ip (str
, &insn
);
1059 mips_ip (str
, &insn
);
1063 as_bad ("%s `%s'", insn_error
, str
);
1067 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1070 mips16_macro (&insn
);
1076 if (imm_expr
.X_op
!= O_absent
)
1077 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1079 else if (offset_expr
.X_op
!= O_absent
)
1080 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1082 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1086 /* See whether instruction IP reads register REG. CLASS is the type
1090 insn_uses_reg (ip
, reg
, class)
1091 struct mips_cl_insn
*ip
;
1093 enum mips_regclass
class;
1095 if (class == MIPS16_REG
)
1098 reg
= mips16_to_32_reg_map
[reg
];
1099 class = MIPS_GR_REG
;
1102 /* Don't report on general register 0, since it never changes. */
1103 if (class == MIPS_GR_REG
&& reg
== 0)
1106 if (class == MIPS_FP_REG
)
1109 /* If we are called with either $f0 or $f1, we must check $f0.
1110 This is not optimal, because it will introduce an unnecessary
1111 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1112 need to distinguish reading both $f0 and $f1 or just one of
1113 them. Note that we don't have to check the other way,
1114 because there is no instruction that sets both $f0 and $f1
1115 and requires a delay. */
1116 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1117 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1118 == (reg
&~ (unsigned) 1)))
1120 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1121 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1122 == (reg
&~ (unsigned) 1)))
1127 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1128 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1130 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1131 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1136 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1137 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1139 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1140 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1142 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1143 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1144 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1146 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1148 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1150 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1152 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1153 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1154 & MIPS16OP_MASK_REGR32
) == reg
)
1161 /* This function returns true if modifying a register requires a
1165 reg_needs_delay (reg
)
1168 unsigned long prev_pinfo
;
1170 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1171 if (! mips_noreorder
1173 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1175 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1177 /* A load from a coprocessor or from memory. All load
1178 delays delay the use of general register rt for one
1179 instruction on the r3000. The r6000 and r4000 use
1181 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1182 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1189 /* Output an instruction. PLACE is where to put the instruction; if
1190 it is NULL, this uses frag_more to get room. IP is the instruction
1191 information. ADDRESS_EXPR is an operand of the instruction to be
1192 used with RELOC_TYPE. */
1195 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1197 struct mips_cl_insn
*ip
;
1198 expressionS
*address_expr
;
1199 bfd_reloc_code_real_type reloc_type
;
1200 boolean unmatched_hi
;
1202 register unsigned long prev_pinfo
, pinfo
;
1207 /* Mark instruction labels in mips16 mode. This permits the linker
1208 to handle them specially, such as generating jalx instructions
1209 when needed. We also make them odd for the duration of the
1210 assembly, in order to generate the right sort of code. We will
1211 make them even in the adjust_symtab routine, while leaving them
1212 marked. This is convenient for the debugger and the
1213 disassembler. The linker knows to make them odd again. */
1216 struct insn_label_list
*l
;
1218 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1221 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1222 S_SET_OTHER (l
->label
, STO_MIPS16
);
1224 ++l
->label
->sy_value
.X_add_number
;
1228 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1229 pinfo
= ip
->insn_mo
->pinfo
;
1231 if (place
== NULL
&& ! mips_noreorder
)
1233 /* If the previous insn required any delay slots, see if we need
1234 to insert a NOP or two. There are eight kinds of possible
1235 hazards, of which an instruction can have at most one type.
1236 (1) a load from memory delay
1237 (2) a load from a coprocessor delay
1238 (3) an unconditional branch delay
1239 (4) a conditional branch delay
1240 (5) a move to coprocessor register delay
1241 (6) a load coprocessor register from memory delay
1242 (7) a coprocessor condition code delay
1243 (8) a HI/LO special register delay
1245 There are a lot of optimizations we could do that we don't.
1246 In particular, we do not, in general, reorder instructions.
1247 If you use gcc with optimization, it will reorder
1248 instructions and generally do much more optimization then we
1249 do here; repeating all that work in the assembler would only
1250 benefit hand written assembly code, and does not seem worth
1253 /* This is how a NOP is emitted. */
1254 #define emit_nop() \
1256 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1257 : md_number_to_chars (frag_more (4), 0, 4))
1259 /* The previous insn might require a delay slot, depending upon
1260 the contents of the current insn. */
1263 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1264 && ! cop_interlocks
)
1266 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1268 /* A load from a coprocessor or from memory. All load
1269 delays delay the use of general register rt for one
1270 instruction on the r3000. The r6000 and r4000 use
1272 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1273 if (mips_optimize
== 0
1274 || insn_uses_reg (ip
,
1275 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1282 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1283 && ! cop_interlocks
)
1285 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1287 /* A generic coprocessor delay. The previous instruction
1288 modified a coprocessor general or control register. If
1289 it modified a control register, we need to avoid any
1290 coprocessor instruction (this is probably not always
1291 required, but it sometimes is). If it modified a general
1292 register, we avoid using that register.
1294 On the r6000 and r4000 loading a coprocessor register
1295 from memory is interlocked, and does not require a delay.
1297 This case is not handled very well. There is no special
1298 knowledge of CP0 handling, and the coprocessors other
1299 than the floating point unit are not distinguished at
1301 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1303 if (mips_optimize
== 0
1304 || insn_uses_reg (ip
,
1305 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1310 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1312 if (mips_optimize
== 0
1313 || insn_uses_reg (ip
,
1314 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1321 /* We don't know exactly what the previous instruction
1322 does. If the current instruction uses a coprocessor
1323 register, we must insert a NOP. If previous
1324 instruction may set the condition codes, and the
1325 current instruction uses them, we must insert two
1327 if (mips_optimize
== 0
1328 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1329 && (pinfo
& INSN_READ_COND_CODE
)))
1331 else if (pinfo
& INSN_COP
)
1337 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1338 && ! cop_interlocks
)
1340 /* The previous instruction sets the coprocessor condition
1341 codes, but does not require a general coprocessor delay
1342 (this means it is a floating point comparison
1343 instruction). If this instruction uses the condition
1344 codes, we need to insert a single NOP. */
1345 if (mips_optimize
== 0
1346 || (pinfo
& INSN_READ_COND_CODE
))
1349 else if (prev_pinfo
& INSN_READ_LO
)
1351 /* The previous instruction reads the LO register; if the
1352 current instruction writes to the LO register, we must
1353 insert two NOPS. Some newer processors have interlocks. */
1355 && (mips_optimize
== 0
1356 || (pinfo
& INSN_WRITE_LO
)))
1359 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1361 /* The previous instruction reads the HI register; if the
1362 current instruction writes to the HI register, we must
1363 insert a NOP. Some newer processors have interlocks. */
1365 && (mips_optimize
== 0
1366 || (pinfo
& INSN_WRITE_HI
)))
1370 /* There are two cases which require two intervening
1371 instructions: 1) setting the condition codes using a move to
1372 coprocessor instruction which requires a general coprocessor
1373 delay and then reading the condition codes 2) reading the HI
1374 or LO register and then writing to it (except on processors
1375 which have interlocks). If we are not already emitting a NOP
1376 instruction, we must check for these cases compared to the
1377 instruction previous to the previous instruction. */
1381 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1382 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1383 && (pinfo
& INSN_READ_COND_CODE
)
1384 && ! cop_interlocks
)
1385 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1386 && (pinfo
& INSN_WRITE_LO
)
1388 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1389 && (pinfo
& INSN_WRITE_HI
)
1393 /* If we are being given a nop instruction, don't bother with
1394 one of the nops we would otherwise output. This will only
1395 happen when a nop instruction is used with mips_optimize set
1397 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1400 /* Now emit the right number of NOP instructions. */
1404 unsigned long old_frag_offset
;
1406 struct insn_label_list
*l
;
1408 old_frag
= frag_now
;
1409 old_frag_offset
= frag_now_fix ();
1411 for (i
= 0; i
< nops
; i
++)
1416 listing_prev_line ();
1417 /* We may be at the start of a variant frag. In case we
1418 are, make sure there is enough space for the frag
1419 after the frags created by listing_prev_line. The
1420 argument to frag_grow here must be at least as large
1421 as the argument to all other calls to frag_grow in
1422 this file. We don't have to worry about being in the
1423 middle of a variant frag, because the variants insert
1424 all needed nop instructions themselves. */
1428 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1430 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1431 l
->label
->sy_frag
= frag_now
;
1432 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1433 /* mips16 text labels are stored as odd. */
1435 ++l
->label
->sy_value
.X_add_number
;
1438 #ifndef NO_ECOFF_DEBUGGING
1439 if (ECOFF_DEBUGGING
)
1440 ecoff_fix_loc (old_frag
, old_frag_offset
);
1445 if (reloc_type
> BFD_RELOC_UNUSED
)
1447 /* We need to set up a variant frag. */
1448 assert (mips16
&& address_expr
!= NULL
);
1449 f
= frag_var (rs_machine_dependent
, 4, 0,
1450 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1451 mips16_small
, mips16_ext
,
1453 & INSN_UNCOND_BRANCH_DELAY
),
1454 (prev_insn_reloc_type
1455 == BFD_RELOC_MIPS16_JMP
)),
1456 make_expr_symbol (address_expr
), (long) 0,
1459 else if (place
!= NULL
)
1461 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1463 /* Make sure there is enough room to swap this instruction with
1464 a following jump instruction. */
1471 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1473 if (address_expr
->X_op
== O_constant
)
1478 ip
->insn_opcode
|= address_expr
->X_add_number
;
1481 case BFD_RELOC_LO16
:
1482 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1485 case BFD_RELOC_MIPS_JMP
:
1486 if ((address_expr
->X_add_number
& 3) != 0)
1487 as_bad ("jump to misaligned address (0x%lx)",
1488 (unsigned long) address_expr
->X_add_number
);
1489 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1492 case BFD_RELOC_MIPS16_JMP
:
1493 if ((address_expr
->X_add_number
& 3) != 0)
1494 as_bad ("jump to misaligned address (0x%lx)",
1495 (unsigned long) address_expr
->X_add_number
);
1497 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1498 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1499 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1502 case BFD_RELOC_16_PCREL_S2
:
1512 /* Don't generate a reloc if we are writing into a variant
1516 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1518 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1522 struct mips_hi_fixup
*hi_fixup
;
1524 assert (reloc_type
== BFD_RELOC_HI16_S
);
1525 hi_fixup
= ((struct mips_hi_fixup
*)
1526 xmalloc (sizeof (struct mips_hi_fixup
)));
1527 hi_fixup
->fixp
= fixp
;
1528 hi_fixup
->seg
= now_seg
;
1529 hi_fixup
->next
= mips_hi_fixup_list
;
1530 mips_hi_fixup_list
= hi_fixup
;
1537 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1538 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1540 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1541 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1547 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1550 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1553 /* Update the register mask information. */
1556 if (pinfo
& INSN_WRITE_GPR_D
)
1557 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1558 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1559 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1560 if (pinfo
& INSN_READ_GPR_S
)
1561 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1562 if (pinfo
& INSN_WRITE_GPR_31
)
1563 mips_gprmask
|= 1 << 31;
1564 if (pinfo
& INSN_WRITE_FPR_D
)
1565 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1566 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1567 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1568 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1569 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1570 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1571 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1572 if (pinfo
& INSN_COP
)
1574 /* We don't keep enough information to sort these cases out. */
1576 /* Never set the bit for $0, which is always zero. */
1577 mips_gprmask
&=~ 1 << 0;
1581 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1582 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1583 & MIPS16OP_MASK_RX
);
1584 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1585 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1586 & MIPS16OP_MASK_RY
);
1587 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1588 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1589 & MIPS16OP_MASK_RZ
);
1590 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1591 mips_gprmask
|= 1 << TREG
;
1592 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1593 mips_gprmask
|= 1 << SP
;
1594 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1595 mips_gprmask
|= 1 << RA
;
1596 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1597 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1598 if (pinfo
& MIPS16_INSN_READ_Z
)
1599 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1600 & MIPS16OP_MASK_MOVE32Z
);
1601 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1602 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1603 & MIPS16OP_MASK_REGR32
);
1606 if (place
== NULL
&& ! mips_noreorder
)
1608 /* Filling the branch delay slot is more complex. We try to
1609 switch the branch with the previous instruction, which we can
1610 do if the previous instruction does not set up a condition
1611 that the branch tests and if the branch is not itself the
1612 target of any branch. */
1613 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1614 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1616 if (mips_optimize
< 2
1617 /* If we have seen .set volatile or .set nomove, don't
1620 /* If we had to emit any NOP instructions, then we
1621 already know we can not swap. */
1623 /* If we don't even know the previous insn, we can not
1625 || ! prev_insn_valid
1626 /* If the previous insn is already in a branch delay
1627 slot, then we can not swap. */
1628 || prev_insn_is_delay_slot
1629 /* If the previous previous insn was in a .set
1630 noreorder, we can't swap. Actually, the MIPS
1631 assembler will swap in this situation. However, gcc
1632 configured -with-gnu-as will generate code like
1638 in which we can not swap the bne and INSN. If gcc is
1639 not configured -with-gnu-as, it does not output the
1640 .set pseudo-ops. We don't have to check
1641 prev_insn_unreordered, because prev_insn_valid will
1642 be 0 in that case. We don't want to use
1643 prev_prev_insn_valid, because we do want to be able
1644 to swap at the start of a function. */
1645 || prev_prev_insn_unreordered
1646 /* If the branch is itself the target of a branch, we
1647 can not swap. We cheat on this; all we check for is
1648 whether there is a label on this instruction. If
1649 there are any branches to anything other than a
1650 label, users must use .set noreorder. */
1651 || insn_labels
!= NULL
1652 /* If the previous instruction is in a variant frag, we
1653 can not do the swap. This does not apply to the
1654 mips16, which uses variant frags for different
1657 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1658 /* If the branch reads the condition codes, we don't
1659 even try to swap, because in the sequence
1664 we can not swap, and I don't feel like handling that
1668 && (pinfo
& INSN_READ_COND_CODE
))
1669 /* We can not swap with an instruction that requires a
1670 delay slot, becase the target of the branch might
1671 interfere with that instruction. */
1675 & (INSN_LOAD_COPROC_DELAY
1676 | INSN_COPROC_MOVE_DELAY
1677 | INSN_WRITE_COND_CODE
)))
1685 & (INSN_LOAD_MEMORY_DELAY
1686 | INSN_COPROC_MEMORY_DELAY
)))
1687 /* We can not swap with a branch instruction. */
1689 & (INSN_UNCOND_BRANCH_DELAY
1690 | INSN_COND_BRANCH_DELAY
1691 | INSN_COND_BRANCH_LIKELY
))
1692 /* We do not swap with a trap instruction, since it
1693 complicates trap handlers to have the trap
1694 instruction be in a delay slot. */
1695 || (prev_pinfo
& INSN_TRAP
)
1696 /* If the branch reads a register that the previous
1697 instruction sets, we can not swap. */
1699 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1700 && insn_uses_reg (ip
,
1701 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1705 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1706 && insn_uses_reg (ip
,
1707 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1711 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1712 && insn_uses_reg (ip
,
1713 ((prev_insn
.insn_opcode
1715 & MIPS16OP_MASK_RX
),
1717 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1718 && insn_uses_reg (ip
,
1719 ((prev_insn
.insn_opcode
1721 & MIPS16OP_MASK_RY
),
1723 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1724 && insn_uses_reg (ip
,
1725 ((prev_insn
.insn_opcode
1727 & MIPS16OP_MASK_RZ
),
1729 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1730 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1731 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1732 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1733 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1734 && insn_uses_reg (ip
,
1735 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1738 /* If the branch writes a register that the previous
1739 instruction sets, we can not swap (we know that
1740 branches write only to RD or to $31). */
1742 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1743 && (((pinfo
& INSN_WRITE_GPR_D
)
1744 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1745 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1746 || ((pinfo
& INSN_WRITE_GPR_31
)
1747 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1751 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1752 && (((pinfo
& INSN_WRITE_GPR_D
)
1753 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1754 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1755 || ((pinfo
& INSN_WRITE_GPR_31
)
1756 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1760 && (pinfo
& MIPS16_INSN_WRITE_31
)
1761 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1762 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1763 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1765 /* If the branch writes a register that the previous
1766 instruction reads, we can not swap (we know that
1767 branches only write to RD or to $31). */
1769 && (pinfo
& INSN_WRITE_GPR_D
)
1770 && insn_uses_reg (&prev_insn
,
1771 ((ip
->insn_opcode
>> OP_SH_RD
)
1775 && (pinfo
& INSN_WRITE_GPR_31
)
1776 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1778 && (pinfo
& MIPS16_INSN_WRITE_31
)
1779 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1780 /* If we are generating embedded PIC code, the branch
1781 might be expanded into a sequence which uses $at, so
1782 we can't swap with an instruction which reads it. */
1783 || (mips_pic
== EMBEDDED_PIC
1784 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1785 /* If the previous previous instruction has a load
1786 delay, and sets a register that the branch reads, we
1790 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1792 && (prev_prev_insn
.insn_mo
->pinfo
1793 & INSN_LOAD_MEMORY_DELAY
)))
1794 && insn_uses_reg (ip
,
1795 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1798 /* If one instruction sets a condition code and the
1799 other one uses a condition code, we can not swap. */
1800 || ((pinfo
& INSN_READ_COND_CODE
)
1801 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1802 || ((pinfo
& INSN_WRITE_COND_CODE
)
1803 && (prev_pinfo
& INSN_READ_COND_CODE
))
1804 /* If the previous instruction uses the PC, we can not
1807 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1808 /* If the previous instruction was extended, we can not
1810 || (mips16
&& prev_insn_extended
)
1811 /* If the previous instruction had a fixup in mips16
1812 mode, we can not swap. This normally means that the
1813 previous instruction was a 4 byte branch anyhow. */
1814 || (mips16
&& prev_insn_fixp
))
1816 /* We could do even better for unconditional branches to
1817 portions of this object file; we could pick up the
1818 instruction at the destination, put it in the delay
1819 slot, and bump the destination address. */
1821 /* Update the previous insn information. */
1822 prev_prev_insn
= *ip
;
1823 prev_insn
.insn_mo
= &dummy_opcode
;
1827 /* It looks like we can actually do the swap. */
1833 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1834 memcpy (temp
, prev_f
, 4);
1835 memcpy (prev_f
, f
, 4);
1836 memcpy (f
, temp
, 4);
1839 prev_insn_fixp
->fx_frag
= frag_now
;
1840 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1844 fixp
->fx_frag
= prev_insn_frag
;
1845 fixp
->fx_where
= prev_insn_where
;
1848 else if (reloc_type
> BFD_RELOC_UNUSED
)
1853 /* We are in mips16 mode, and we have just created a
1854 variant frag. We need to extract the old
1855 instruction from the end of the previous frag,
1856 and add it to a new frag. */
1857 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1858 memcpy (temp
, prev_f
, 2);
1859 prev_insn_frag
->fr_fix
-= 2;
1860 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1862 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1863 memcpy (prev_f
, prev_f
+ 2, 2);
1865 memcpy (frag_more (2), temp
, 2);
1872 assert (prev_insn_fixp
== NULL
);
1873 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1874 memcpy (temp
, prev_f
, 2);
1875 memcpy (prev_f
, f
, 2);
1876 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1877 memcpy (f
, temp
, 2);
1880 memcpy (f
, f
+ 2, 2);
1881 memcpy (f
+ 2, temp
, 2);
1885 fixp
->fx_frag
= prev_insn_frag
;
1886 fixp
->fx_where
= prev_insn_where
;
1890 /* Update the previous insn information; leave prev_insn
1892 prev_prev_insn
= *ip
;
1894 prev_insn_is_delay_slot
= 1;
1896 /* If that was an unconditional branch, forget the previous
1897 insn information. */
1898 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1900 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1901 prev_insn
.insn_mo
= &dummy_opcode
;
1904 prev_insn_fixp
= NULL
;
1905 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1906 prev_insn_extended
= 0;
1908 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1910 /* We don't yet optimize a branch likely. What we should do
1911 is look at the target, copy the instruction found there
1912 into the delay slot, and increment the branch to jump to
1913 the next instruction. */
1915 /* Update the previous insn information. */
1916 prev_prev_insn
= *ip
;
1917 prev_insn
.insn_mo
= &dummy_opcode
;
1918 prev_insn_fixp
= NULL
;
1919 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1920 prev_insn_extended
= 0;
1924 /* Update the previous insn information. */
1926 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1928 prev_prev_insn
= prev_insn
;
1931 /* Any time we see a branch, we always fill the delay slot
1932 immediately; since this insn is not a branch, we know it
1933 is not in a delay slot. */
1934 prev_insn_is_delay_slot
= 0;
1936 prev_insn_fixp
= fixp
;
1937 prev_insn_reloc_type
= reloc_type
;
1939 prev_insn_extended
= (ip
->use_extend
1940 || reloc_type
> BFD_RELOC_UNUSED
);
1943 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1944 prev_insn_unreordered
= 0;
1945 prev_insn_frag
= frag_now
;
1946 prev_insn_where
= f
- frag_now
->fr_literal
;
1947 prev_insn_valid
= 1;
1949 else if (place
== NULL
)
1951 /* We need to record a bit of information even when we are not
1952 reordering, in order to determine the base address for mips16
1953 PC relative relocs. */
1955 prev_insn_reloc_type
= reloc_type
;
1958 /* We just output an insn, so the next one doesn't have a label. */
1959 mips_clear_insn_labels ();
1962 /* This function forgets that there was any previous instruction or
1966 mips_no_prev_insn ()
1968 prev_insn
.insn_mo
= &dummy_opcode
;
1969 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1970 prev_insn_valid
= 0;
1971 prev_insn_is_delay_slot
= 0;
1972 prev_insn_unreordered
= 0;
1973 prev_insn_extended
= 0;
1974 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1975 prev_prev_insn_unreordered
= 0;
1976 mips_clear_insn_labels ();
1979 /* This function must be called whenever we turn on noreorder or emit
1980 something other than instructions. It inserts any NOPS which might
1981 be needed by the previous instruction, and clears the information
1982 kept for the previous instructions. The INSNS parameter is true if
1983 instructions are to follow. */
1986 mips_emit_delays (insns
)
1989 if (! mips_noreorder
)
1996 && (! cop_interlocks
1997 && (prev_insn
.insn_mo
->pinfo
1998 & (INSN_LOAD_COPROC_DELAY
1999 | INSN_COPROC_MOVE_DELAY
2000 | INSN_WRITE_COND_CODE
))))
2002 && (prev_insn
.insn_mo
->pinfo
2007 && (prev_insn
.insn_mo
->pinfo
2008 & (INSN_LOAD_MEMORY_DELAY
2009 | INSN_COPROC_MEMORY_DELAY
))))
2014 && (! cop_interlocks
2015 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2017 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2018 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2023 && (! cop_interlocks
2024 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2026 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2027 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2031 struct insn_label_list
*l
;
2034 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2036 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2037 l
->label
->sy_frag
= frag_now
;
2038 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2039 /* mips16 text labels are stored as odd. */
2041 ++l
->label
->sy_value
.X_add_number
;
2046 /* Mark instruction labels in mips16 mode. This permits the linker
2047 to handle them specially, such as generating jalx instructions
2048 when needed. We also make them odd for the duration of the
2049 assembly, in order to generate the right sort of code. We will
2050 make them even in the adjust_symtab routine, while leaving them
2051 marked. This is convenient for the debugger and the
2052 disassembler. The linker knows to make them odd again. */
2053 if (mips16
&& insns
)
2055 struct insn_label_list
*l
;
2057 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2060 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2061 S_SET_OTHER (l
->label
, STO_MIPS16
);
2063 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2064 ++l
->label
->sy_value
.X_add_number
;
2068 mips_no_prev_insn ();
2071 /* Build an instruction created by a macro expansion. This is passed
2072 a pointer to the count of instructions created so far, an
2073 expression, the name of the instruction to build, an operand format
2074 string, and corresponding arguments. */
2078 macro_build (char *place
,
2086 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2095 struct mips_cl_insn insn
;
2096 bfd_reloc_code_real_type r
;
2100 va_start (args
, fmt
);
2106 * If the macro is about to expand into a second instruction,
2107 * print a warning if needed. We need to pass ip as a parameter
2108 * to generate a better warning message here...
2110 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2111 as_warn ("Macro instruction expanded into multiple instructions");
2114 *counter
+= 1; /* bump instruction counter */
2118 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2123 r
= BFD_RELOC_UNUSED
;
2124 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2125 assert (insn
.insn_mo
);
2126 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2128 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2129 || insn
.insn_mo
->pinfo
== INSN_MACRO
2130 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2132 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2134 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2136 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2138 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2140 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2142 /* start-sanitize-r5900 */
2143 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_5900
2145 /* end-sanitize-r5900 */
2149 assert (insn
.insn_mo
->name
);
2150 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2152 insn
.insn_opcode
= insn
.insn_mo
->match
;
2168 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2174 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2179 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2184 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2191 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2195 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2199 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2206 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2212 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2213 assert (r
== BFD_RELOC_MIPS_GPREL
2214 || r
== BFD_RELOC_MIPS_LITERAL
2215 || r
== BFD_RELOC_LO16
2216 || r
== BFD_RELOC_MIPS_GOT16
2217 || r
== BFD_RELOC_MIPS_CALL16
2218 || r
== BFD_RELOC_MIPS_GOT_LO16
2219 || r
== BFD_RELOC_MIPS_CALL_LO16
2220 || (ep
->X_op
== O_subtract
2221 && now_seg
== text_section
2222 && r
== BFD_RELOC_PCREL_LO16
));
2226 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2228 && (ep
->X_op
== O_constant
2229 || (ep
->X_op
== O_symbol
2230 && (r
== BFD_RELOC_HI16_S
2231 || r
== BFD_RELOC_HI16
2232 || r
== BFD_RELOC_MIPS_GOT_HI16
2233 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2234 || (ep
->X_op
== O_subtract
2235 && now_seg
== text_section
2236 && r
== BFD_RELOC_PCREL_HI16_S
)));
2237 if (ep
->X_op
== O_constant
)
2239 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2241 r
= BFD_RELOC_UNUSED
;
2246 assert (ep
!= NULL
);
2248 * This allows macro() to pass an immediate expression for
2249 * creating short branches without creating a symbol.
2250 * Note that the expression still might come from the assembly
2251 * input, in which case the value is not checked for range nor
2252 * is a relocation entry generated (yuck).
2254 if (ep
->X_op
== O_constant
)
2256 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2260 r
= BFD_RELOC_16_PCREL_S2
;
2264 assert (ep
!= NULL
);
2265 r
= BFD_RELOC_MIPS_JMP
;
2274 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2276 append_insn (place
, &insn
, ep
, r
, false);
2280 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2288 struct mips_cl_insn insn
;
2289 bfd_reloc_code_real_type r
;
2291 r
= BFD_RELOC_UNUSED
;
2292 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2293 assert (insn
.insn_mo
);
2294 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2296 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2297 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2300 assert (insn
.insn_mo
->name
);
2301 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2304 insn
.insn_opcode
= insn
.insn_mo
->match
;
2305 insn
.use_extend
= false;
2324 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2329 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2333 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2337 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2347 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2354 regno
= va_arg (args
, int);
2355 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2356 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2377 assert (ep
!= NULL
);
2379 if (ep
->X_op
!= O_constant
)
2380 r
= BFD_RELOC_UNUSED
+ c
;
2383 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2384 false, false, &insn
.insn_opcode
,
2385 &insn
.use_extend
, &insn
.extend
);
2387 r
= BFD_RELOC_UNUSED
;
2393 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2400 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2402 append_insn (place
, &insn
, ep
, r
, false);
2406 * Generate a "lui" instruction.
2409 macro_build_lui (place
, counter
, ep
, regnum
)
2415 expressionS high_expr
;
2416 struct mips_cl_insn insn
;
2417 bfd_reloc_code_real_type r
;
2418 CONST
char *name
= "lui";
2419 CONST
char *fmt
= "t,u";
2427 high_expr
.X_op
= O_constant
;
2428 high_expr
.X_add_number
= ep
->X_add_number
;
2431 if (high_expr
.X_op
== O_constant
)
2433 /* we can compute the instruction now without a relocation entry */
2434 if (high_expr
.X_add_number
& 0x8000)
2435 high_expr
.X_add_number
+= 0x10000;
2436 high_expr
.X_add_number
=
2437 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2438 r
= BFD_RELOC_UNUSED
;
2442 assert (ep
->X_op
== O_symbol
);
2443 /* _gp_disp is a special case, used from s_cpload. */
2444 assert (mips_pic
== NO_PIC
2445 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2446 r
= BFD_RELOC_HI16_S
;
2450 * If the macro is about to expand into a second instruction,
2451 * print a warning if needed. We need to pass ip as a parameter
2452 * to generate a better warning message here...
2454 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2455 as_warn ("Macro instruction expanded into multiple instructions");
2458 *counter
+= 1; /* bump instruction counter */
2460 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2461 assert (insn
.insn_mo
);
2462 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2463 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2465 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2466 if (r
== BFD_RELOC_UNUSED
)
2468 insn
.insn_opcode
|= high_expr
.X_add_number
;
2469 append_insn (place
, &insn
, NULL
, r
, false);
2472 append_insn (place
, &insn
, &high_expr
, r
, false);
2476 * Generates code to set the $at register to true (one)
2477 * if reg is less than the immediate expression.
2480 set_at (counter
, reg
, unsignedp
)
2485 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2486 macro_build ((char *) NULL
, counter
, &imm_expr
,
2487 unsignedp
? "sltiu" : "slti",
2488 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2491 load_register (counter
, AT
, &imm_expr
, 0);
2492 macro_build ((char *) NULL
, counter
, NULL
,
2493 unsignedp
? "sltu" : "slt",
2494 "d,v,t", AT
, reg
, AT
);
2498 /* Warn if an expression is not a constant. */
2501 check_absolute_expr (ip
, ex
)
2502 struct mips_cl_insn
*ip
;
2505 if (ex
->X_op
!= O_constant
)
2506 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2509 /* Count the leading zeroes by performing a binary chop. This is a
2510 bulky bit of source, but performance is a LOT better for the
2511 majority of values than a simple loop to count the bits:
2512 for (lcnt = 0; (lcnt < 32); lcnt++)
2513 if ((v) & (1 << (31 - lcnt)))
2515 However it is not code size friendly, and the gain will drop a bit
2516 on certain cached systems.
2518 #define COUNT_TOP_ZEROES(v) \
2519 (((v) & ~0xffff) == 0 \
2520 ? ((v) & ~0xff) == 0 \
2521 ? ((v) & ~0xf) == 0 \
2522 ? ((v) & ~0x3) == 0 \
2523 ? ((v) & ~0x1) == 0 \
2528 : ((v) & ~0x7) == 0 \
2531 : ((v) & ~0x3f) == 0 \
2532 ? ((v) & ~0x1f) == 0 \
2535 : ((v) & ~0x7f) == 0 \
2538 : ((v) & ~0xfff) == 0 \
2539 ? ((v) & ~0x3ff) == 0 \
2540 ? ((v) & ~0x1ff) == 0 \
2543 : ((v) & ~0x7ff) == 0 \
2546 : ((v) & ~0x3fff) == 0 \
2547 ? ((v) & ~0x1fff) == 0 \
2550 : ((v) & ~0x7fff) == 0 \
2553 : ((v) & ~0xffffff) == 0 \
2554 ? ((v) & ~0xfffff) == 0 \
2555 ? ((v) & ~0x3ffff) == 0 \
2556 ? ((v) & ~0x1ffff) == 0 \
2559 : ((v) & ~0x7ffff) == 0 \
2562 : ((v) & ~0x3fffff) == 0 \
2563 ? ((v) & ~0x1fffff) == 0 \
2566 : ((v) & ~0x7fffff) == 0 \
2569 : ((v) & ~0xfffffff) == 0 \
2570 ? ((v) & ~0x3ffffff) == 0 \
2571 ? ((v) & ~0x1ffffff) == 0 \
2574 : ((v) & ~0x7ffffff) == 0 \
2577 : ((v) & ~0x3fffffff) == 0 \
2578 ? ((v) & ~0x1fffffff) == 0 \
2581 : ((v) & ~0x7fffffff) == 0 \
2586 * This routine generates the least number of instructions neccessary to load
2587 * an absolute expression value into a register.
2590 load_register (counter
, reg
, ep
, dbl
)
2597 expressionS hi32
, lo32
;
2599 if (ep
->X_op
!= O_big
)
2601 assert (ep
->X_op
== O_constant
);
2602 if (ep
->X_add_number
< 0x8000
2603 && (ep
->X_add_number
>= 0
2604 || (ep
->X_add_number
>= -0x8000
2607 || sizeof (ep
->X_add_number
) > 4))))
2609 /* We can handle 16 bit signed values with an addiu to
2610 $zero. No need to ever use daddiu here, since $zero and
2611 the result are always correct in 32 bit mode. */
2612 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2613 (int) BFD_RELOC_LO16
);
2616 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2618 /* We can handle 16 bit unsigned values with an ori to
2620 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2621 (int) BFD_RELOC_LO16
);
2624 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2625 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2626 == ~ (offsetT
) 0x7fffffff))
2629 || sizeof (ep
->X_add_number
) > 4
2630 || (ep
->X_add_number
& 0x80000000) == 0))
2631 || ((mips_isa
< 3 || !dbl
)
2632 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2634 /* 32 bit values require an lui. */
2635 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2636 (int) BFD_RELOC_HI16
);
2637 if ((ep
->X_add_number
& 0xffff) != 0)
2638 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2639 (int) BFD_RELOC_LO16
);
2644 /* The value is larger than 32 bits. */
2648 as_bad ("Number larger than 32 bits");
2649 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2650 (int) BFD_RELOC_LO16
);
2654 if (ep
->X_op
!= O_big
)
2657 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2658 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2659 hi32
.X_add_number
&= 0xffffffff;
2661 lo32
.X_add_number
&= 0xffffffff;
2665 assert (ep
->X_add_number
> 2);
2666 if (ep
->X_add_number
== 3)
2667 generic_bignum
[3] = 0;
2668 else if (ep
->X_add_number
> 4)
2669 as_bad ("Number larger than 64 bits");
2670 lo32
.X_op
= O_constant
;
2671 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2672 hi32
.X_op
= O_constant
;
2673 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2676 if (hi32
.X_add_number
== 0)
2681 unsigned long hi
, lo
;
2683 if (hi32
.X_add_number
== 0xffffffff)
2685 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2687 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2688 reg
, 0, (int) BFD_RELOC_LO16
);
2691 if (lo32
.X_add_number
& 0x80000000)
2693 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2694 (int) BFD_RELOC_HI16
);
2695 if (lo32
.X_add_number
& 0xffff)
2696 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2697 reg
, reg
, (int) BFD_RELOC_LO16
);
2702 /* Check for 16bit shifted constant. We know that hi32 is
2703 non-zero, so start the mask on the first bit of the hi32
2708 unsigned long himask
, lomask
;
2712 himask
= 0xffff >> (32 - shift
);
2713 lomask
= (0xffff << shift
) & 0xffffffff;
2717 himask
= 0xffff << (shift
- 32);
2720 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2721 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2725 tmp
.X_op
= O_constant
;
2727 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2728 | (lo32
.X_add_number
>> shift
));
2730 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2731 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2732 (int) BFD_RELOC_LO16
);
2733 macro_build ((char *) NULL
, counter
, NULL
,
2734 (shift
>= 32) ? "dsll32" : "dsll",
2736 (shift
>= 32) ? shift
- 32 : shift
);
2740 } while (shift
<= (64 - 16));
2742 /* Find the bit number of the lowest one bit, and store the
2743 shifted value in hi/lo. */
2744 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2745 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2749 while ((lo
& 1) == 0)
2754 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2760 while ((hi
& 1) == 0)
2769 /* Optimize if the shifted value is a (power of 2) - 1. */
2770 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2771 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2773 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2778 /* This instruction will set the register to be all
2780 tmp
.X_op
= O_constant
;
2781 tmp
.X_add_number
= (offsetT
) -1;
2782 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2783 reg
, 0, (int) BFD_RELOC_LO16
);
2787 macro_build ((char *) NULL
, counter
, NULL
,
2788 (bit
>= 32) ? "dsll32" : "dsll",
2790 (bit
>= 32) ? bit
- 32 : bit
);
2792 macro_build ((char *) NULL
, counter
, NULL
,
2793 (shift
>= 32) ? "dsrl32" : "dsrl",
2795 (shift
>= 32) ? shift
- 32 : shift
);
2800 /* Sign extend hi32 before calling load_register, because we can
2801 generally get better code when we load a sign extended value. */
2802 if ((hi32
.X_add_number
& 0x80000000) != 0)
2803 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2804 load_register (counter
, reg
, &hi32
, 0);
2807 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2811 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2820 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2822 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2823 (int) BFD_RELOC_HI16
);
2824 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2831 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2836 mid16
.X_add_number
>>= 16;
2837 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2838 freg
, (int) BFD_RELOC_LO16
);
2839 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2843 if ((lo32
.X_add_number
& 0xffff) != 0)
2844 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2845 (int) BFD_RELOC_LO16
);
2848 /* Load an address into a register. */
2851 load_address (counter
, reg
, ep
)
2858 if (ep
->X_op
!= O_constant
2859 && ep
->X_op
!= O_symbol
)
2861 as_bad ("expression too complex");
2862 ep
->X_op
= O_constant
;
2865 if (ep
->X_op
== O_constant
)
2867 load_register (counter
, reg
, ep
, 0);
2871 if (mips_pic
== NO_PIC
)
2873 /* If this is a reference to a GP relative symbol, we want
2874 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2876 lui $reg,<sym> (BFD_RELOC_HI16_S)
2877 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2878 If we have an addend, we always use the latter form. */
2879 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2880 || nopic_need_relax (ep
->X_add_symbol
))
2885 macro_build ((char *) NULL
, counter
, ep
,
2886 mips_isa
< 3 ? "addiu" : "daddiu",
2887 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2888 p
= frag_var (rs_machine_dependent
, 8, 0,
2889 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2890 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2892 macro_build_lui (p
, counter
, ep
, reg
);
2895 macro_build (p
, counter
, ep
,
2896 mips_isa
< 3 ? "addiu" : "daddiu",
2897 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2899 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2903 /* If this is a reference to an external symbol, we want
2904 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2906 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2908 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2909 If there is a constant, it must be added in after. */
2910 ex
.X_add_number
= ep
->X_add_number
;
2911 ep
->X_add_number
= 0;
2913 macro_build ((char *) NULL
, counter
, ep
,
2914 mips_isa
< 3 ? "lw" : "ld",
2915 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2916 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2917 p
= frag_var (rs_machine_dependent
, 4, 0,
2918 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2919 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2920 macro_build (p
, counter
, ep
,
2921 mips_isa
< 3 ? "addiu" : "daddiu",
2922 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2923 if (ex
.X_add_number
!= 0)
2925 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2926 as_bad ("PIC code offset overflow (max 16 signed bits)");
2927 ex
.X_op
= O_constant
;
2928 macro_build ((char *) NULL
, counter
, &ex
,
2929 mips_isa
< 3 ? "addiu" : "daddiu",
2930 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2933 else if (mips_pic
== SVR4_PIC
)
2938 /* This is the large GOT case. If this is a reference to an
2939 external symbol, we want
2940 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2942 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2943 Otherwise, for a reference to a local symbol, we want
2944 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2946 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2947 If there is a constant, it must be added in after. */
2948 ex
.X_add_number
= ep
->X_add_number
;
2949 ep
->X_add_number
= 0;
2950 if (reg_needs_delay (GP
))
2955 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2956 (int) BFD_RELOC_MIPS_GOT_HI16
);
2957 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2958 mips_isa
< 3 ? "addu" : "daddu",
2959 "d,v,t", reg
, reg
, GP
);
2960 macro_build ((char *) NULL
, counter
, ep
,
2961 mips_isa
< 3 ? "lw" : "ld",
2962 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2963 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2964 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2965 mips_warn_about_macros
),
2966 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2969 /* We need a nop before loading from $gp. This special
2970 check is required because the lui which starts the main
2971 instruction stream does not refer to $gp, and so will not
2972 insert the nop which may be required. */
2973 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2976 macro_build (p
, counter
, ep
,
2977 mips_isa
< 3 ? "lw" : "ld",
2978 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2980 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2982 macro_build (p
, counter
, ep
,
2983 mips_isa
< 3 ? "addiu" : "daddiu",
2984 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2985 if (ex
.X_add_number
!= 0)
2987 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2988 as_bad ("PIC code offset overflow (max 16 signed bits)");
2989 ex
.X_op
= O_constant
;
2990 macro_build ((char *) NULL
, counter
, &ex
,
2991 mips_isa
< 3 ? "addiu" : "daddiu",
2992 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2995 else if (mips_pic
== EMBEDDED_PIC
)
2998 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3000 macro_build ((char *) NULL
, counter
, ep
,
3001 mips_isa
< 3 ? "addiu" : "daddiu",
3002 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3010 * This routine implements the seemingly endless macro or synthesized
3011 * instructions and addressing modes in the mips assembly language. Many
3012 * of these macros are simple and are similar to each other. These could
3013 * probably be handled by some kind of table or grammer aproach instead of
3014 * this verbose method. Others are not simple macros but are more like
3015 * optimizing code generation.
3016 * One interesting optimization is when several store macros appear
3017 * consecutivly that would load AT with the upper half of the same address.
3018 * The ensuing load upper instructions are ommited. This implies some kind
3019 * of global optimization. We currently only optimize within a single macro.
3020 * For many of the load and store macros if the address is specified as a
3021 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3022 * first load register 'at' with zero and use it as the base register. The
3023 * mips assembler simply uses register $zero. Just one tiny optimization
3028 struct mips_cl_insn
*ip
;
3030 register int treg
, sreg
, dreg
, breg
;
3045 bfd_reloc_code_real_type r
;
3047 int hold_mips_optimize
;
3051 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3052 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3053 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3054 mask
= ip
->insn_mo
->mask
;
3056 expr1
.X_op
= O_constant
;
3057 expr1
.X_op_symbol
= NULL
;
3058 expr1
.X_add_symbol
= NULL
;
3059 expr1
.X_add_number
= 1;
3071 mips_emit_delays (true);
3073 mips_any_noreorder
= 1;
3075 expr1
.X_add_number
= 8;
3076 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3078 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3080 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3081 macro_build ((char *) NULL
, &icnt
, NULL
,
3082 dbl
? "dsub" : "sub",
3083 "d,v,t", dreg
, 0, sreg
);
3106 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3108 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3109 (int) BFD_RELOC_LO16
);
3112 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3113 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3132 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3134 if (mask
!= M_NOR_I
)
3135 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3136 sreg
, (int) BFD_RELOC_LO16
);
3139 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3140 treg
, sreg
, (int) BFD_RELOC_LO16
);
3141 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3147 load_register (&icnt
, AT
, &imm_expr
, 0);
3148 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3165 if (imm_expr
.X_add_number
== 0)
3167 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3171 load_register (&icnt
, AT
, &imm_expr
, 0);
3172 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3180 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3181 likely
? "bgezl" : "bgez",
3187 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3188 likely
? "blezl" : "blez",
3192 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3193 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3194 likely
? "beql" : "beq",
3201 /* check for > max integer */
3202 maxnum
= 0x7fffffff;
3210 if (imm_expr
.X_add_number
>= maxnum
3211 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3214 /* result is always false */
3217 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3218 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3222 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3223 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3228 imm_expr
.X_add_number
++;
3232 if (mask
== M_BGEL_I
)
3234 if (imm_expr
.X_add_number
== 0)
3236 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3237 likely
? "bgezl" : "bgez",
3241 if (imm_expr
.X_add_number
== 1)
3243 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3244 likely
? "bgtzl" : "bgtz",
3248 maxnum
= 0x7fffffff;
3256 maxnum
= - maxnum
- 1;
3257 if (imm_expr
.X_add_number
<= maxnum
3258 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3261 /* result is always true */
3262 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3263 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3266 set_at (&icnt
, sreg
, 0);
3267 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3268 likely
? "beql" : "beq",
3279 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3280 likely
? "beql" : "beq",
3284 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3286 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3287 likely
? "beql" : "beq",
3294 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3296 imm_expr
.X_add_number
++;
3300 if (mask
== M_BGEUL_I
)
3302 if (imm_expr
.X_add_number
== 0)
3304 if (imm_expr
.X_add_number
== 1)
3306 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3307 likely
? "bnel" : "bne",
3311 set_at (&icnt
, sreg
, 1);
3312 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3313 likely
? "beql" : "beq",
3322 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3323 likely
? "bgtzl" : "bgtz",
3329 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3330 likely
? "bltzl" : "bltz",
3334 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3335 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3336 likely
? "bnel" : "bne",
3345 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3346 likely
? "bnel" : "bne",
3352 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3354 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3355 likely
? "bnel" : "bne",
3364 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3365 likely
? "blezl" : "blez",
3371 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3372 likely
? "bgezl" : "bgez",
3376 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3377 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3378 likely
? "beql" : "beq",
3385 maxnum
= 0x7fffffff;
3393 if (imm_expr
.X_add_number
>= maxnum
3394 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3396 imm_expr
.X_add_number
++;
3400 if (mask
== M_BLTL_I
)
3402 if (imm_expr
.X_add_number
== 0)
3404 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3405 likely
? "bltzl" : "bltz",
3409 if (imm_expr
.X_add_number
== 1)
3411 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3412 likely
? "blezl" : "blez",
3416 set_at (&icnt
, sreg
, 0);
3417 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3418 likely
? "bnel" : "bne",
3427 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3428 likely
? "beql" : "beq",
3434 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3436 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3437 likely
? "beql" : "beq",
3444 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3446 imm_expr
.X_add_number
++;
3450 if (mask
== M_BLTUL_I
)
3452 if (imm_expr
.X_add_number
== 0)
3454 if (imm_expr
.X_add_number
== 1)
3456 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3457 likely
? "beql" : "beq",
3461 set_at (&icnt
, sreg
, 1);
3462 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3463 likely
? "bnel" : "bne",
3472 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3473 likely
? "bltzl" : "bltz",
3479 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3480 likely
? "bgtzl" : "bgtz",
3484 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3485 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3486 likely
? "bnel" : "bne",
3497 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3498 likely
? "bnel" : "bne",
3502 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3504 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3505 likely
? "bnel" : "bne",
3521 as_warn ("Divide by zero.");
3523 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3525 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3529 mips_emit_delays (true);
3531 mips_any_noreorder
= 1;
3532 macro_build ((char *) NULL
, &icnt
, NULL
,
3533 dbl
? "ddiv" : "div",
3534 "z,s,t", sreg
, treg
);
3536 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3539 expr1
.X_add_number
= 8;
3540 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3541 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3542 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3544 expr1
.X_add_number
= -1;
3545 macro_build ((char *) NULL
, &icnt
, &expr1
,
3546 dbl
? "daddiu" : "addiu",
3547 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3548 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3549 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3552 expr1
.X_add_number
= 1;
3553 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3554 (int) BFD_RELOC_LO16
);
3555 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3560 expr1
.X_add_number
= 0x80000000;
3561 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3562 (int) BFD_RELOC_HI16
);
3565 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3568 expr1
.X_add_number
= 8;
3569 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3570 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3571 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3574 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3613 if (imm_expr
.X_add_number
== 0)
3615 as_warn ("Divide by zero.");
3617 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3619 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3622 if (imm_expr
.X_add_number
== 1)
3624 if (strcmp (s2
, "mflo") == 0)
3625 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3628 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3631 if (imm_expr
.X_add_number
== -1
3632 && s
[strlen (s
) - 1] != 'u')
3634 if (strcmp (s2
, "mflo") == 0)
3637 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3640 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3644 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3648 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3649 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3650 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3669 mips_emit_delays (true);
3671 mips_any_noreorder
= 1;
3672 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3674 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3677 expr1
.X_add_number
= 8;
3678 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3679 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3680 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3683 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3689 /* Load the address of a symbol into a register. If breg is not
3690 zero, we then add a base register to it. */
3692 /* When generating embedded PIC code, we permit expressions of
3695 where bar is an address in the .text section. These are used
3696 when getting the addresses of functions. We don't permit
3697 X_add_number to be non-zero, because if the symbol is
3698 external the relaxing code needs to know that any addend is
3699 purely the offset to X_op_symbol. */
3700 if (mips_pic
== EMBEDDED_PIC
3701 && offset_expr
.X_op
== O_subtract
3702 && now_seg
== text_section
3703 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3704 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3705 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3706 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3707 ->sy_value
.X_add_symbol
)
3710 && offset_expr
.X_add_number
== 0)
3712 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3713 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3714 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3715 mips_isa
< 3 ? "addiu" : "daddiu",
3716 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3720 if (offset_expr
.X_op
!= O_symbol
3721 && offset_expr
.X_op
!= O_constant
)
3723 as_bad ("expression too complex");
3724 offset_expr
.X_op
= O_constant
;
3738 if (offset_expr
.X_op
== O_constant
)
3739 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3740 else if (mips_pic
== NO_PIC
)
3742 /* If this is a reference to an GP relative symbol, we want
3743 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3745 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3746 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3747 If we have a constant, we need two instructions anyhow,
3748 so we may as well always use the latter form. */
3749 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3750 || nopic_need_relax (offset_expr
.X_add_symbol
))
3755 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3756 mips_isa
< 3 ? "addiu" : "daddiu",
3757 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3758 p
= frag_var (rs_machine_dependent
, 8, 0,
3759 RELAX_ENCODE (4, 8, 0, 4, 0,
3760 mips_warn_about_macros
),
3761 offset_expr
.X_add_symbol
, (long) 0,
3764 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3767 macro_build (p
, &icnt
, &offset_expr
,
3768 mips_isa
< 3 ? "addiu" : "daddiu",
3769 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3771 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3773 /* If this is a reference to an external symbol, and there
3774 is no constant, we want
3775 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3776 For a local symbol, we want
3777 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3779 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3781 If we have a small constant, and this is a reference to
3782 an external symbol, we want
3783 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3785 addiu $tempreg,$tempreg,<constant>
3786 For a local symbol, we want the same instruction
3787 sequence, but we output a BFD_RELOC_LO16 reloc on the
3790 If we have a large constant, and this is a reference to
3791 an external symbol, we want
3792 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3793 lui $at,<hiconstant>
3794 addiu $at,$at,<loconstant>
3795 addu $tempreg,$tempreg,$at
3796 For a local symbol, we want the same instruction
3797 sequence, but we output a BFD_RELOC_LO16 reloc on the
3798 addiu instruction. */
3799 expr1
.X_add_number
= offset_expr
.X_add_number
;
3800 offset_expr
.X_add_number
= 0;
3802 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3804 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3805 if (expr1
.X_add_number
== 0)
3813 /* We're going to put in an addu instruction using
3814 tempreg, so we may as well insert the nop right
3816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3820 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3821 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3823 ? mips_warn_about_macros
3825 offset_expr
.X_add_symbol
, (long) 0,
3829 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3832 macro_build (p
, &icnt
, &expr1
,
3833 mips_isa
< 3 ? "addiu" : "daddiu",
3834 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3835 /* FIXME: If breg == 0, and the next instruction uses
3836 $tempreg, then if this variant case is used an extra
3837 nop will be generated. */
3839 else if (expr1
.X_add_number
>= -0x8000
3840 && expr1
.X_add_number
< 0x8000)
3842 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3844 macro_build ((char *) NULL
, &icnt
, &expr1
,
3845 mips_isa
< 3 ? "addiu" : "daddiu",
3846 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3847 (void) frag_var (rs_machine_dependent
, 0, 0,
3848 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3849 offset_expr
.X_add_symbol
, (long) 0,
3856 /* If we are going to add in a base register, and the
3857 target register and the base register are the same,
3858 then we are using AT as a temporary register. Since
3859 we want to load the constant into AT, we add our
3860 current AT (from the global offset table) and the
3861 register into the register now, and pretend we were
3862 not using a base register. */
3867 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3869 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3870 mips_isa
< 3 ? "addu" : "daddu",
3871 "d,v,t", treg
, AT
, breg
);
3877 /* Set mips_optimize around the lui instruction to avoid
3878 inserting an unnecessary nop after the lw. */
3879 hold_mips_optimize
= mips_optimize
;
3881 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3882 mips_optimize
= hold_mips_optimize
;
3884 macro_build ((char *) NULL
, &icnt
, &expr1
,
3885 mips_isa
< 3 ? "addiu" : "daddiu",
3886 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3887 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3888 mips_isa
< 3 ? "addu" : "daddu",
3889 "d,v,t", tempreg
, tempreg
, AT
);
3890 (void) frag_var (rs_machine_dependent
, 0, 0,
3891 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3892 offset_expr
.X_add_symbol
, (long) 0,
3897 else if (mips_pic
== SVR4_PIC
)
3901 /* This is the large GOT case. If this is a reference to an
3902 external symbol, and there is no constant, we want
3903 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3904 addu $tempreg,$tempreg,$gp
3905 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3906 For a local symbol, we want
3907 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3909 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3911 If we have a small constant, and this is a reference to
3912 an external symbol, we want
3913 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3914 addu $tempreg,$tempreg,$gp
3915 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3917 addiu $tempreg,$tempreg,<constant>
3918 For a local symbol, we want
3919 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3921 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3923 If we have a large constant, and this is a reference to
3924 an external symbol, we want
3925 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3926 addu $tempreg,$tempreg,$gp
3927 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3928 lui $at,<hiconstant>
3929 addiu $at,$at,<loconstant>
3930 addu $tempreg,$tempreg,$at
3931 For a local symbol, we want
3932 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3933 lui $at,<hiconstant>
3934 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3935 addu $tempreg,$tempreg,$at
3937 expr1
.X_add_number
= offset_expr
.X_add_number
;
3938 offset_expr
.X_add_number
= 0;
3940 if (reg_needs_delay (GP
))
3944 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3945 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3946 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3947 mips_isa
< 3 ? "addu" : "daddu",
3948 "d,v,t", tempreg
, tempreg
, GP
);
3949 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3951 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3953 if (expr1
.X_add_number
== 0)
3961 /* We're going to put in an addu instruction using
3962 tempreg, so we may as well insert the nop right
3964 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3969 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3970 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3973 ? mips_warn_about_macros
3975 offset_expr
.X_add_symbol
, (long) 0,
3978 else if (expr1
.X_add_number
>= -0x8000
3979 && expr1
.X_add_number
< 0x8000)
3981 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3983 macro_build ((char *) NULL
, &icnt
, &expr1
,
3984 mips_isa
< 3 ? "addiu" : "daddiu",
3985 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3987 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3988 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3990 ? mips_warn_about_macros
3992 offset_expr
.X_add_symbol
, (long) 0,
3999 /* If we are going to add in a base register, and the
4000 target register and the base register are the same,
4001 then we are using AT as a temporary register. Since
4002 we want to load the constant into AT, we add our
4003 current AT (from the global offset table) and the
4004 register into the register now, and pretend we were
4005 not using a base register. */
4013 assert (tempreg
== AT
);
4014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4016 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4017 mips_isa
< 3 ? "addu" : "daddu",
4018 "d,v,t", treg
, AT
, breg
);
4023 /* Set mips_optimize around the lui instruction to avoid
4024 inserting an unnecessary nop after the lw. */
4025 hold_mips_optimize
= mips_optimize
;
4027 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4028 mips_optimize
= hold_mips_optimize
;
4030 macro_build ((char *) NULL
, &icnt
, &expr1
,
4031 mips_isa
< 3 ? "addiu" : "daddiu",
4032 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4034 mips_isa
< 3 ? "addu" : "daddu",
4035 "d,v,t", dreg
, dreg
, AT
);
4037 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4038 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4041 ? mips_warn_about_macros
4043 offset_expr
.X_add_symbol
, (long) 0,
4051 /* This is needed because this instruction uses $gp, but
4052 the first instruction on the main stream does not. */
4053 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4056 macro_build (p
, &icnt
, &offset_expr
,
4058 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4060 if (expr1
.X_add_number
>= -0x8000
4061 && expr1
.X_add_number
< 0x8000)
4063 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4065 macro_build (p
, &icnt
, &expr1
,
4066 mips_isa
< 3 ? "addiu" : "daddiu",
4067 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4068 /* FIXME: If add_number is 0, and there was no base
4069 register, the external symbol case ended with a load,
4070 so if the symbol turns out to not be external, and
4071 the next instruction uses tempreg, an unnecessary nop
4072 will be inserted. */
4078 /* We must add in the base register now, as in the
4079 external symbol case. */
4080 assert (tempreg
== AT
);
4081 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4083 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4084 mips_isa
< 3 ? "addu" : "daddu",
4085 "d,v,t", treg
, AT
, breg
);
4088 /* We set breg to 0 because we have arranged to add
4089 it in in both cases. */
4093 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4095 macro_build (p
, &icnt
, &expr1
,
4096 mips_isa
< 3 ? "addiu" : "daddiu",
4097 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4099 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4100 mips_isa
< 3 ? "addu" : "daddu",
4101 "d,v,t", tempreg
, tempreg
, AT
);
4105 else if (mips_pic
== EMBEDDED_PIC
)
4108 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4110 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4111 mips_isa
< 3 ? "addiu" : "daddiu",
4112 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4119 mips_isa
< 3 ? "addu" : "daddu",
4120 "d,v,t", treg
, tempreg
, breg
);
4128 /* The j instruction may not be used in PIC code, since it
4129 requires an absolute address. We convert it to a b
4131 if (mips_pic
== NO_PIC
)
4132 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4137 /* The jal instructions must be handled as macros because when
4138 generating PIC code they expand to multi-instruction
4139 sequences. Normally they are simple instructions. */
4144 if (mips_pic
== NO_PIC
4145 || mips_pic
== EMBEDDED_PIC
)
4146 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4148 else if (mips_pic
== SVR4_PIC
)
4150 if (sreg
!= PIC_CALL_REG
)
4151 as_warn ("MIPS PIC call to register other than $25");
4153 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4155 if (mips_cprestore_offset
< 0)
4156 as_warn ("No .cprestore pseudo-op used in PIC code");
4159 expr1
.X_add_number
= mips_cprestore_offset
;
4160 macro_build ((char *) NULL
, &icnt
, &expr1
,
4161 mips_isa
< 3 ? "lw" : "ld",
4162 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4171 if (mips_pic
== NO_PIC
)
4172 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4173 else if (mips_pic
== SVR4_PIC
)
4175 /* If this is a reference to an external symbol, and we are
4176 using a small GOT, we want
4177 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4181 lw $gp,cprestore($sp)
4182 The cprestore value is set using the .cprestore
4183 pseudo-op. If we are using a big GOT, we want
4184 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4186 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4190 lw $gp,cprestore($sp)
4191 If the symbol is not external, we want
4192 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4194 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4197 lw $gp,cprestore($sp) */
4201 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4202 mips_isa
< 3 ? "lw" : "ld",
4203 "t,o(b)", PIC_CALL_REG
,
4204 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4205 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4207 p
= frag_var (rs_machine_dependent
, 4, 0,
4208 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4209 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4215 if (reg_needs_delay (GP
))
4219 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4220 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4221 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4222 mips_isa
< 3 ? "addu" : "daddu",
4223 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4224 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4225 mips_isa
< 3 ? "lw" : "ld",
4226 "t,o(b)", PIC_CALL_REG
,
4227 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4228 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4230 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4231 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4233 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4236 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4239 macro_build (p
, &icnt
, &offset_expr
,
4240 mips_isa
< 3 ? "lw" : "ld",
4241 "t,o(b)", PIC_CALL_REG
,
4242 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4244 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4247 macro_build (p
, &icnt
, &offset_expr
,
4248 mips_isa
< 3 ? "addiu" : "daddiu",
4249 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4250 (int) BFD_RELOC_LO16
);
4251 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4252 "jalr", "s", PIC_CALL_REG
);
4253 if (mips_cprestore_offset
< 0)
4254 as_warn ("No .cprestore pseudo-op used in PIC code");
4258 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4260 expr1
.X_add_number
= mips_cprestore_offset
;
4261 macro_build ((char *) NULL
, &icnt
, &expr1
,
4262 mips_isa
< 3 ? "lw" : "ld",
4263 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4267 else if (mips_pic
== EMBEDDED_PIC
)
4269 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4270 /* The linker may expand the call to a longer sequence which
4271 uses $at, so we must break rather than return. */
4347 if (breg
== treg
|| coproc
|| lr
)
4416 if (mask
== M_LWC1_AB
4417 || mask
== M_SWC1_AB
4418 || mask
== M_LDC1_AB
4419 || mask
== M_SDC1_AB
4428 if (offset_expr
.X_op
!= O_constant
4429 && offset_expr
.X_op
!= O_symbol
)
4431 as_bad ("expression too complex");
4432 offset_expr
.X_op
= O_constant
;
4435 /* A constant expression in PIC code can be handled just as it
4436 is in non PIC code. */
4437 if (mips_pic
== NO_PIC
4438 || offset_expr
.X_op
== O_constant
)
4440 /* If this is a reference to a GP relative symbol, and there
4441 is no base register, we want
4442 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4443 Otherwise, if there is no base register, we want
4444 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4445 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4446 If we have a constant, we need two instructions anyhow,
4447 so we always use the latter form.
4449 If we have a base register, and this is a reference to a
4450 GP relative symbol, we want
4451 addu $tempreg,$breg,$gp
4452 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4454 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4455 addu $tempreg,$tempreg,$breg
4456 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4457 With a constant we always use the latter case. */
4460 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4461 || nopic_need_relax (offset_expr
.X_add_symbol
))
4466 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4467 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4468 p
= frag_var (rs_machine_dependent
, 8, 0,
4469 RELAX_ENCODE (4, 8, 0, 4, 0,
4470 (mips_warn_about_macros
4471 || (used_at
&& mips_noat
))),
4472 offset_expr
.X_add_symbol
, (long) 0,
4476 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4479 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4480 (int) BFD_RELOC_LO16
, tempreg
);
4484 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4485 || nopic_need_relax (offset_expr
.X_add_symbol
))
4490 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4491 mips_isa
< 3 ? "addu" : "daddu",
4492 "d,v,t", tempreg
, breg
, GP
);
4493 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4494 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4495 p
= frag_var (rs_machine_dependent
, 12, 0,
4496 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4497 offset_expr
.X_add_symbol
, (long) 0,
4500 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4503 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4504 mips_isa
< 3 ? "addu" : "daddu",
4505 "d,v,t", tempreg
, tempreg
, breg
);
4508 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4509 (int) BFD_RELOC_LO16
, tempreg
);
4512 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4514 /* If this is a reference to an external symbol, we want
4515 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4517 <op> $treg,0($tempreg)
4519 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4521 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4522 <op> $treg,0($tempreg)
4523 If there is a base register, we add it to $tempreg before
4524 the <op>. If there is a constant, we stick it in the
4525 <op> instruction. We don't handle constants larger than
4526 16 bits, because we have no way to load the upper 16 bits
4527 (actually, we could handle them for the subset of cases
4528 in which we are not using $at). */
4529 assert (offset_expr
.X_op
== O_symbol
);
4530 expr1
.X_add_number
= offset_expr
.X_add_number
;
4531 offset_expr
.X_add_number
= 0;
4532 if (expr1
.X_add_number
< -0x8000
4533 || expr1
.X_add_number
>= 0x8000)
4534 as_bad ("PIC code offset overflow (max 16 signed bits)");
4536 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4537 mips_isa
< 3 ? "lw" : "ld",
4538 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4539 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4540 p
= frag_var (rs_machine_dependent
, 4, 0,
4541 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4542 offset_expr
.X_add_symbol
, (long) 0,
4544 macro_build (p
, &icnt
, &offset_expr
,
4545 mips_isa
< 3 ? "addiu" : "daddiu",
4546 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4548 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4549 mips_isa
< 3 ? "addu" : "daddu",
4550 "d,v,t", tempreg
, tempreg
, breg
);
4551 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4552 (int) BFD_RELOC_LO16
, tempreg
);
4554 else if (mips_pic
== SVR4_PIC
)
4558 /* If this is a reference to an external symbol, we want
4559 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4560 addu $tempreg,$tempreg,$gp
4561 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4562 <op> $treg,0($tempreg)
4564 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4566 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4567 <op> $treg,0($tempreg)
4568 If there is a base register, we add it to $tempreg before
4569 the <op>. If there is a constant, we stick it in the
4570 <op> instruction. We don't handle constants larger than
4571 16 bits, because we have no way to load the upper 16 bits
4572 (actually, we could handle them for the subset of cases
4573 in which we are not using $at). */
4574 assert (offset_expr
.X_op
== O_symbol
);
4575 expr1
.X_add_number
= offset_expr
.X_add_number
;
4576 offset_expr
.X_add_number
= 0;
4577 if (expr1
.X_add_number
< -0x8000
4578 || expr1
.X_add_number
>= 0x8000)
4579 as_bad ("PIC code offset overflow (max 16 signed bits)");
4580 if (reg_needs_delay (GP
))
4585 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4586 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4587 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4588 mips_isa
< 3 ? "addu" : "daddu",
4589 "d,v,t", tempreg
, tempreg
, GP
);
4590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4591 mips_isa
< 3 ? "lw" : "ld",
4592 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4594 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4595 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4596 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4599 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4602 macro_build (p
, &icnt
, &offset_expr
,
4603 mips_isa
< 3 ? "lw" : "ld",
4604 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4606 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4608 macro_build (p
, &icnt
, &offset_expr
,
4609 mips_isa
< 3 ? "addiu" : "daddiu",
4610 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4612 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4613 mips_isa
< 3 ? "addu" : "daddu",
4614 "d,v,t", tempreg
, tempreg
, breg
);
4615 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4616 (int) BFD_RELOC_LO16
, tempreg
);
4618 else if (mips_pic
== EMBEDDED_PIC
)
4620 /* If there is no base register, we want
4621 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4622 If there is a base register, we want
4623 addu $tempreg,$breg,$gp
4624 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4626 assert (offset_expr
.X_op
== O_symbol
);
4629 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4630 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4635 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4636 mips_isa
< 3 ? "addu" : "daddu",
4637 "d,v,t", tempreg
, breg
, GP
);
4638 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4639 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4652 load_register (&icnt
, treg
, &imm_expr
, 0);
4656 load_register (&icnt
, treg
, &imm_expr
, 1);
4660 if (imm_expr
.X_op
== O_constant
)
4662 load_register (&icnt
, AT
, &imm_expr
, 0);
4663 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4664 "mtc1", "t,G", AT
, treg
);
4669 assert (offset_expr
.X_op
== O_symbol
4670 && strcmp (segment_name (S_GET_SEGMENT
4671 (offset_expr
.X_add_symbol
)),
4673 && offset_expr
.X_add_number
== 0);
4674 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4675 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4680 /* We know that sym is in the .rdata section. First we get the
4681 upper 16 bits of the address. */
4682 if (mips_pic
== NO_PIC
)
4684 /* FIXME: This won't work for a 64 bit address. */
4685 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4687 else if (mips_pic
== SVR4_PIC
)
4689 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4690 mips_isa
< 3 ? "lw" : "ld",
4691 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4693 else if (mips_pic
== EMBEDDED_PIC
)
4695 /* For embedded PIC we pick up the entire address off $gp in
4696 a single instruction. */
4697 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4698 mips_isa
< 3 ? "addiu" : "daddiu",
4699 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4700 offset_expr
.X_op
= O_constant
;
4701 offset_expr
.X_add_number
= 0;
4706 /* Now we load the register(s). */
4708 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4709 treg
, (int) BFD_RELOC_LO16
, AT
);
4712 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4713 treg
, (int) BFD_RELOC_LO16
, AT
);
4716 /* FIXME: How in the world do we deal with the possible
4718 offset_expr
.X_add_number
+= 4;
4719 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4720 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4724 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4725 does not become a variant frag. */
4726 frag_wane (frag_now
);
4732 assert (offset_expr
.X_op
== O_symbol
4733 && offset_expr
.X_add_number
== 0);
4734 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4735 if (strcmp (s
, ".lit8") == 0)
4739 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4740 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4744 r
= BFD_RELOC_MIPS_LITERAL
;
4749 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4750 if (mips_pic
== SVR4_PIC
)
4751 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4752 mips_isa
< 3 ? "lw" : "ld",
4753 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4756 /* FIXME: This won't work for a 64 bit address. */
4757 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4762 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4763 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4765 /* To avoid confusion in tc_gen_reloc, we must ensure
4766 that this does not become a variant frag. */
4767 frag_wane (frag_now
);
4778 /* Even on a big endian machine $fn comes before $fn+1. We have
4779 to adjust when loading from memory. */
4782 assert (mips_isa
< 2);
4783 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4784 target_big_endian
? treg
+ 1 : treg
,
4786 /* FIXME: A possible overflow which I don't know how to deal
4788 offset_expr
.X_add_number
+= 4;
4789 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4790 target_big_endian
? treg
: treg
+ 1,
4793 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4794 does not become a variant frag. */
4795 frag_wane (frag_now
);
4804 * The MIPS assembler seems to check for X_add_number not
4805 * being double aligned and generating:
4808 * addiu at,at,%lo(foo+1)
4811 * But, the resulting address is the same after relocation so why
4812 * generate the extra instruction?
4859 if (offset_expr
.X_op
!= O_symbol
4860 && offset_expr
.X_op
!= O_constant
)
4862 as_bad ("expression too complex");
4863 offset_expr
.X_op
= O_constant
;
4866 /* Even on a big endian machine $fn comes before $fn+1. We have
4867 to adjust when loading from memory. We set coproc if we must
4868 load $fn+1 first. */
4869 if (! target_big_endian
)
4872 if (mips_pic
== NO_PIC
4873 || offset_expr
.X_op
== O_constant
)
4875 /* If this is a reference to a GP relative symbol, we want
4876 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4877 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4878 If we have a base register, we use this
4880 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4881 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4882 If this is not a GP relative symbol, we want
4883 lui $at,<sym> (BFD_RELOC_HI16_S)
4884 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4885 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4886 If there is a base register, we add it to $at after the
4887 lui instruction. If there is a constant, we always use
4889 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4890 || nopic_need_relax (offset_expr
.X_add_symbol
))
4909 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4910 mips_isa
< 3 ? "addu" : "daddu",
4911 "d,v,t", AT
, breg
, GP
);
4917 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4918 coproc
? treg
+ 1 : treg
,
4919 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4920 offset_expr
.X_add_number
+= 4;
4922 /* Set mips_optimize to 2 to avoid inserting an
4924 hold_mips_optimize
= mips_optimize
;
4926 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4927 coproc
? treg
: treg
+ 1,
4928 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4929 mips_optimize
= hold_mips_optimize
;
4931 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4932 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4933 used_at
&& mips_noat
),
4934 offset_expr
.X_add_symbol
, (long) 0,
4937 /* We just generated two relocs. When tc_gen_reloc
4938 handles this case, it will skip the first reloc and
4939 handle the second. The second reloc already has an
4940 extra addend of 4, which we added above. We must
4941 subtract it out, and then subtract another 4 to make
4942 the first reloc come out right. The second reloc
4943 will come out right because we are going to add 4 to
4944 offset_expr when we build its instruction below. */
4945 offset_expr
.X_add_number
-= 8;
4946 offset_expr
.X_op
= O_constant
;
4948 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4953 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4954 mips_isa
< 3 ? "addu" : "daddu",
4955 "d,v,t", AT
, breg
, AT
);
4959 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4960 coproc
? treg
+ 1 : treg
,
4961 (int) BFD_RELOC_LO16
, AT
);
4964 /* FIXME: How do we handle overflow here? */
4965 offset_expr
.X_add_number
+= 4;
4966 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4967 coproc
? treg
: treg
+ 1,
4968 (int) BFD_RELOC_LO16
, AT
);
4970 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4974 /* If this is a reference to an external symbol, we want
4975 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4980 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4982 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4983 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4984 If there is a base register we add it to $at before the
4985 lwc1 instructions. If there is a constant we include it
4986 in the lwc1 instructions. */
4988 expr1
.X_add_number
= offset_expr
.X_add_number
;
4989 offset_expr
.X_add_number
= 0;
4990 if (expr1
.X_add_number
< -0x8000
4991 || expr1
.X_add_number
>= 0x8000 - 4)
4992 as_bad ("PIC code offset overflow (max 16 signed bits)");
4997 frag_grow (24 + off
);
4998 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4999 mips_isa
< 3 ? "lw" : "ld",
5000 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5003 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5004 mips_isa
< 3 ? "addu" : "daddu",
5005 "d,v,t", AT
, breg
, AT
);
5006 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5007 coproc
? treg
+ 1 : treg
,
5008 (int) BFD_RELOC_LO16
, AT
);
5009 expr1
.X_add_number
+= 4;
5011 /* Set mips_optimize to 2 to avoid inserting an undesired
5013 hold_mips_optimize
= mips_optimize
;
5015 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5016 coproc
? treg
: treg
+ 1,
5017 (int) BFD_RELOC_LO16
, AT
);
5018 mips_optimize
= hold_mips_optimize
;
5020 (void) frag_var (rs_machine_dependent
, 0, 0,
5021 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5022 offset_expr
.X_add_symbol
, (long) 0,
5025 else if (mips_pic
== SVR4_PIC
)
5029 /* If this is a reference to an external symbol, we want
5030 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5032 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5037 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5039 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5040 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5041 If there is a base register we add it to $at before the
5042 lwc1 instructions. If there is a constant we include it
5043 in the lwc1 instructions. */
5045 expr1
.X_add_number
= offset_expr
.X_add_number
;
5046 offset_expr
.X_add_number
= 0;
5047 if (expr1
.X_add_number
< -0x8000
5048 || expr1
.X_add_number
>= 0x8000 - 4)
5049 as_bad ("PIC code offset overflow (max 16 signed bits)");
5050 if (reg_needs_delay (GP
))
5059 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5060 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5061 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5062 mips_isa
< 3 ? "addu" : "daddu",
5063 "d,v,t", AT
, AT
, GP
);
5064 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5065 mips_isa
< 3 ? "lw" : "ld",
5066 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5069 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5070 mips_isa
< 3 ? "addu" : "daddu",
5071 "d,v,t", AT
, breg
, AT
);
5072 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5073 coproc
? treg
+ 1 : treg
,
5074 (int) BFD_RELOC_LO16
, AT
);
5075 expr1
.X_add_number
+= 4;
5077 /* Set mips_optimize to 2 to avoid inserting an undesired
5079 hold_mips_optimize
= mips_optimize
;
5081 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5082 coproc
? treg
: treg
+ 1,
5083 (int) BFD_RELOC_LO16
, AT
);
5084 mips_optimize
= hold_mips_optimize
;
5085 expr1
.X_add_number
-= 4;
5087 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5088 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5089 8 + gpdel
+ off
, 1, 0),
5090 offset_expr
.X_add_symbol
, (long) 0,
5094 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5097 macro_build (p
, &icnt
, &offset_expr
,
5098 mips_isa
< 3 ? "lw" : "ld",
5099 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5101 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5105 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5106 mips_isa
< 3 ? "addu" : "daddu",
5107 "d,v,t", AT
, breg
, AT
);
5110 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5111 coproc
? treg
+ 1 : treg
,
5112 (int) BFD_RELOC_LO16
, AT
);
5114 expr1
.X_add_number
+= 4;
5116 /* Set mips_optimize to 2 to avoid inserting an undesired
5118 hold_mips_optimize
= mips_optimize
;
5120 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5121 coproc
? treg
: treg
+ 1,
5122 (int) BFD_RELOC_LO16
, AT
);
5123 mips_optimize
= hold_mips_optimize
;
5125 else if (mips_pic
== EMBEDDED_PIC
)
5127 /* If there is no base register, we use
5128 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5129 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5130 If we have a base register, we use
5132 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5133 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5142 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5143 mips_isa
< 3 ? "addu" : "daddu",
5144 "d,v,t", AT
, breg
, GP
);
5149 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5150 coproc
? treg
+ 1 : treg
,
5151 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5152 offset_expr
.X_add_number
+= 4;
5153 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5154 coproc
? treg
: treg
+ 1,
5155 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5171 assert (mips_isa
< 3);
5172 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5173 (int) BFD_RELOC_LO16
, breg
);
5174 offset_expr
.X_add_number
+= 4;
5175 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5176 (int) BFD_RELOC_LO16
, breg
);
5178 #ifdef LOSING_COMPILER
5184 as_warn ("Macro used $at after \".set noat\"");
5189 struct mips_cl_insn
*ip
;
5191 register int treg
, sreg
, dreg
, breg
;
5206 bfd_reloc_code_real_type r
;
5209 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5210 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5211 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5212 mask
= ip
->insn_mo
->mask
;
5214 expr1
.X_op
= O_constant
;
5215 expr1
.X_op_symbol
= NULL
;
5216 expr1
.X_add_symbol
= NULL
;
5217 expr1
.X_add_number
= 1;
5221 #endif /* LOSING_COMPILER */
5226 macro_build ((char *) NULL
, &icnt
, NULL
,
5227 dbl
? "dmultu" : "multu",
5229 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5235 /* The MIPS assembler some times generates shifts and adds. I'm
5236 not trying to be that fancy. GCC should do this for us
5238 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5239 macro_build ((char *) NULL
, &icnt
, NULL
,
5240 dbl
? "dmult" : "mult",
5242 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5248 mips_emit_delays (true);
5250 mips_any_noreorder
= 1;
5251 macro_build ((char *) NULL
, &icnt
, NULL
,
5252 dbl
? "dmult" : "mult",
5254 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5255 macro_build ((char *) NULL
, &icnt
, NULL
,
5256 dbl
? "dsra32" : "sra",
5257 "d,w,<", dreg
, dreg
, 31);
5258 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5260 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5263 expr1
.X_add_number
= 8;
5264 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5265 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5266 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5269 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5275 mips_emit_delays (true);
5277 mips_any_noreorder
= 1;
5278 macro_build ((char *) NULL
, &icnt
, NULL
,
5279 dbl
? "dmultu" : "multu",
5281 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5282 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5284 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5287 expr1
.X_add_number
= 8;
5288 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5289 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5290 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5296 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5297 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5298 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5300 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5304 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5305 (int) (imm_expr
.X_add_number
& 0x1f));
5306 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5307 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5308 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5312 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5313 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5314 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5316 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5320 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5321 (int) (imm_expr
.X_add_number
& 0x1f));
5322 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5323 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5324 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5328 assert (mips_isa
< 2);
5329 /* Even on a big endian machine $fn comes before $fn+1. We have
5330 to adjust when storing to memory. */
5331 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5332 target_big_endian
? treg
+ 1 : treg
,
5333 (int) BFD_RELOC_LO16
, breg
);
5334 offset_expr
.X_add_number
+= 4;
5335 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5336 target_big_endian
? treg
: treg
+ 1,
5337 (int) BFD_RELOC_LO16
, breg
);
5342 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5343 treg
, (int) BFD_RELOC_LO16
);
5345 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5346 sreg
, (int) BFD_RELOC_LO16
);
5349 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5351 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5352 dreg
, (int) BFD_RELOC_LO16
);
5357 if (imm_expr
.X_add_number
== 0)
5359 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5360 sreg
, (int) BFD_RELOC_LO16
);
5365 as_warn ("Instruction %s: result is always false",
5367 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5370 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5372 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5373 sreg
, (int) BFD_RELOC_LO16
);
5376 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5378 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5379 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5380 mips_isa
< 3 ? "addiu" : "daddiu",
5381 "t,r,j", dreg
, sreg
,
5382 (int) BFD_RELOC_LO16
);
5387 load_register (&icnt
, AT
, &imm_expr
, 0);
5388 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5392 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5393 (int) BFD_RELOC_LO16
);
5398 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5404 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5405 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5406 (int) BFD_RELOC_LO16
);
5409 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5411 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5413 macro_build ((char *) NULL
, &icnt
, &expr1
,
5414 mask
== M_SGE_I
? "slti" : "sltiu",
5415 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5420 load_register (&icnt
, AT
, &imm_expr
, 0);
5421 macro_build ((char *) NULL
, &icnt
, NULL
,
5422 mask
== M_SGE_I
? "slt" : "sltu",
5423 "d,v,t", dreg
, sreg
, AT
);
5426 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5427 (int) BFD_RELOC_LO16
);
5432 case M_SGT
: /* sreg > treg <==> treg < sreg */
5438 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5441 case M_SGT_I
: /* sreg > I <==> I < sreg */
5447 load_register (&icnt
, AT
, &imm_expr
, 0);
5448 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5451 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5457 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5458 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5459 (int) BFD_RELOC_LO16
);
5462 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5468 load_register (&icnt
, AT
, &imm_expr
, 0);
5469 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5470 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5471 (int) BFD_RELOC_LO16
);
5475 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5477 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5478 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5481 load_register (&icnt
, AT
, &imm_expr
, 0);
5482 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5486 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5488 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5489 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5492 load_register (&icnt
, AT
, &imm_expr
, 0);
5493 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5499 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5502 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5506 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5508 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5514 if (imm_expr
.X_add_number
== 0)
5516 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5522 as_warn ("Instruction %s: result is always true",
5524 macro_build ((char *) NULL
, &icnt
, &expr1
,
5525 mips_isa
< 3 ? "addiu" : "daddiu",
5526 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5529 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5531 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5532 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5535 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5537 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5538 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5539 mips_isa
< 3 ? "addiu" : "daddiu",
5540 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5545 load_register (&icnt
, AT
, &imm_expr
, 0);
5546 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5550 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5558 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5560 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5561 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5562 dbl
? "daddi" : "addi",
5563 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5566 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5567 macro_build ((char *) NULL
, &icnt
, NULL
,
5568 dbl
? "dsub" : "sub",
5569 "d,v,t", dreg
, sreg
, AT
);
5575 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5577 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5578 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5579 dbl
? "daddiu" : "addiu",
5580 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5583 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5584 macro_build ((char *) NULL
, &icnt
, NULL
,
5585 dbl
? "dsubu" : "subu",
5586 "d,v,t", dreg
, sreg
, AT
);
5607 load_register (&icnt
, AT
, &imm_expr
, 0);
5608 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5613 assert (mips_isa
< 2);
5614 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5615 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5618 * Is the double cfc1 instruction a bug in the mips assembler;
5619 * or is there a reason for it?
5621 mips_emit_delays (true);
5623 mips_any_noreorder
= 1;
5624 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5625 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5626 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5627 expr1
.X_add_number
= 3;
5628 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5629 (int) BFD_RELOC_LO16
);
5630 expr1
.X_add_number
= 2;
5631 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5632 (int) BFD_RELOC_LO16
);
5633 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5634 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5635 macro_build ((char *) NULL
, &icnt
, NULL
,
5636 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5637 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5638 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5648 if (offset_expr
.X_add_number
>= 0x7fff)
5649 as_bad ("operand overflow");
5650 /* avoid load delay */
5651 if (! target_big_endian
)
5652 offset_expr
.X_add_number
+= 1;
5653 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5654 (int) BFD_RELOC_LO16
, breg
);
5655 if (! target_big_endian
)
5656 offset_expr
.X_add_number
-= 1;
5658 offset_expr
.X_add_number
+= 1;
5659 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5660 (int) BFD_RELOC_LO16
, breg
);
5661 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5662 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5675 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5676 as_bad ("operand overflow");
5677 if (! target_big_endian
)
5678 offset_expr
.X_add_number
+= off
;
5679 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5680 (int) BFD_RELOC_LO16
, breg
);
5681 if (! target_big_endian
)
5682 offset_expr
.X_add_number
-= off
;
5684 offset_expr
.X_add_number
+= off
;
5685 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5686 (int) BFD_RELOC_LO16
, breg
);
5699 load_address (&icnt
, AT
, &offset_expr
);
5701 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5702 mips_isa
< 3 ? "addu" : "daddu",
5703 "d,v,t", AT
, AT
, breg
);
5704 if (! target_big_endian
)
5705 expr1
.X_add_number
= off
;
5707 expr1
.X_add_number
= 0;
5708 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5709 (int) BFD_RELOC_LO16
, AT
);
5710 if (! target_big_endian
)
5711 expr1
.X_add_number
= 0;
5713 expr1
.X_add_number
= off
;
5714 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5715 (int) BFD_RELOC_LO16
, AT
);
5720 load_address (&icnt
, AT
, &offset_expr
);
5722 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5723 mips_isa
< 3 ? "addu" : "daddu",
5724 "d,v,t", AT
, AT
, breg
);
5725 if (target_big_endian
)
5726 expr1
.X_add_number
= 0;
5727 macro_build ((char *) NULL
, &icnt
, &expr1
,
5728 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5729 (int) BFD_RELOC_LO16
, AT
);
5730 if (target_big_endian
)
5731 expr1
.X_add_number
= 1;
5733 expr1
.X_add_number
= 0;
5734 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5735 (int) BFD_RELOC_LO16
, AT
);
5736 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5738 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5743 if (offset_expr
.X_add_number
>= 0x7fff)
5744 as_bad ("operand overflow");
5745 if (target_big_endian
)
5746 offset_expr
.X_add_number
+= 1;
5747 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5748 (int) BFD_RELOC_LO16
, breg
);
5749 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5750 if (target_big_endian
)
5751 offset_expr
.X_add_number
-= 1;
5753 offset_expr
.X_add_number
+= 1;
5754 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5755 (int) BFD_RELOC_LO16
, breg
);
5768 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5769 as_bad ("operand overflow");
5770 if (! target_big_endian
)
5771 offset_expr
.X_add_number
+= off
;
5772 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5773 (int) BFD_RELOC_LO16
, breg
);
5774 if (! target_big_endian
)
5775 offset_expr
.X_add_number
-= off
;
5777 offset_expr
.X_add_number
+= off
;
5778 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5779 (int) BFD_RELOC_LO16
, breg
);
5792 load_address (&icnt
, AT
, &offset_expr
);
5794 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5795 mips_isa
< 3 ? "addu" : "daddu",
5796 "d,v,t", AT
, AT
, breg
);
5797 if (! target_big_endian
)
5798 expr1
.X_add_number
= off
;
5800 expr1
.X_add_number
= 0;
5801 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5802 (int) BFD_RELOC_LO16
, AT
);
5803 if (! target_big_endian
)
5804 expr1
.X_add_number
= 0;
5806 expr1
.X_add_number
= off
;
5807 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5808 (int) BFD_RELOC_LO16
, AT
);
5812 load_address (&icnt
, AT
, &offset_expr
);
5814 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5815 mips_isa
< 3 ? "addu" : "daddu",
5816 "d,v,t", AT
, AT
, breg
);
5817 if (! target_big_endian
)
5818 expr1
.X_add_number
= 0;
5819 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5820 (int) BFD_RELOC_LO16
, AT
);
5821 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5823 if (! target_big_endian
)
5824 expr1
.X_add_number
= 1;
5826 expr1
.X_add_number
= 0;
5827 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5828 (int) BFD_RELOC_LO16
, AT
);
5829 if (! target_big_endian
)
5830 expr1
.X_add_number
= 0;
5832 expr1
.X_add_number
= 1;
5833 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5834 (int) BFD_RELOC_LO16
, AT
);
5835 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5837 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5842 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5846 as_warn ("Macro used $at after \".set noat\"");
5849 /* Implement macros in mips16 mode. */
5853 struct mips_cl_insn
*ip
;
5856 int xreg
, yreg
, zreg
, tmp
;
5860 const char *s
, *s2
, *s3
;
5862 mask
= ip
->insn_mo
->mask
;
5864 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5865 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5866 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5870 expr1
.X_op
= O_constant
;
5871 expr1
.X_op_symbol
= NULL
;
5872 expr1
.X_add_symbol
= NULL
;
5873 expr1
.X_add_number
= 1;
5892 mips_emit_delays (true);
5894 mips_any_noreorder
= 1;
5895 macro_build ((char *) NULL
, &icnt
, NULL
,
5896 dbl
? "ddiv" : "div",
5897 "0,x,y", xreg
, yreg
);
5898 expr1
.X_add_number
= 2;
5899 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5900 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5901 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5902 since that causes an overflow. We should do that as well,
5903 but I don't see how to do the comparisons without a temporary
5906 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5925 mips_emit_delays (true);
5927 mips_any_noreorder
= 1;
5928 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5929 expr1
.X_add_number
= 2;
5930 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5931 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5933 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5941 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5942 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5943 dbl
? "daddiu" : "addiu",
5944 "y,x,4", yreg
, xreg
);
5948 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5949 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5954 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5955 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
5978 goto do_reverse_branch
;
5982 goto do_reverse_branch
;
5994 goto do_reverse_branch
;
6005 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6007 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6034 goto do_addone_branch_i
;
6039 goto do_addone_branch_i
;
6054 goto do_addone_branch_i
;
6061 ++imm_expr
.X_add_number
;
6064 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6065 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6069 expr1
.X_add_number
= 0;
6070 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6072 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6073 "move", "y,X", xreg
, yreg
);
6074 expr1
.X_add_number
= 2;
6075 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6076 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6077 "neg", "x,w", xreg
, xreg
);
6081 /* This routine assembles an instruction into its binary format. As a
6082 side effect, it sets one of the global variables imm_reloc or
6083 offset_reloc to the type of relocation to do if one of the operands
6084 is an address expression. */
6089 struct mips_cl_insn
*ip
;
6094 struct mips_opcode
*insn
;
6097 unsigned int lastregno
= 0;
6102 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
6114 as_fatal ("Unknown opcode: `%s'", str
);
6116 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6118 insn_error
= "unrecognized opcode";
6126 assert (strcmp (insn
->name
, str
) == 0);
6128 if (insn
->pinfo
== INSN_MACRO
)
6129 insn_isa
= insn
->match
;
6130 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6132 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6134 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6139 if (insn_isa
> mips_isa
6140 || (insn
->pinfo
!= INSN_MACRO
6141 && (((insn
->pinfo
& INSN_ISA
) == INSN_4650
6143 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6145 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6147 /* start-sanitize-r5900 */
6148 || ((insn
->pinfo
& INSN_ISA
) == INSN_5900
6150 /* end-sanitize-r5900 */
6153 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6154 && strcmp (insn
->name
, insn
[1].name
) == 0)
6159 if (insn_isa
<= mips_isa
)
6160 insn_error
= "opcode not supported on this processor";
6163 static char buf
[100];
6165 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6172 ip
->insn_opcode
= insn
->match
;
6173 for (args
= insn
->args
;; ++args
)
6179 case '\0': /* end of args */
6192 ip
->insn_opcode
|= lastregno
<< 21;
6197 ip
->insn_opcode
|= lastregno
<< 16;
6201 ip
->insn_opcode
|= lastregno
<< 11;
6207 /* handle optional base register.
6208 Either the base register is omitted or
6209 we must have a left paren. */
6210 /* this is dependent on the next operand specifier
6211 is a 'b' for base register */
6212 assert (args
[1] == 'b');
6216 case ')': /* these must match exactly */
6221 case '<': /* must be at least one digit */
6223 * According to the manual, if the shift amount is greater
6224 * than 31 or less than 0 the the shift amount should be
6225 * mod 32. In reality the mips assembler issues an error.
6226 * We issue a warning and mask out all but the low 5 bits.
6228 my_getExpression (&imm_expr
, s
);
6229 check_absolute_expr (ip
, &imm_expr
);
6230 if ((unsigned long) imm_expr
.X_add_number
> 31)
6232 as_warn ("Improper shift amount (%ld)",
6233 (long) imm_expr
.X_add_number
);
6234 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6236 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6237 imm_expr
.X_op
= O_absent
;
6241 case '>': /* shift amount minus 32 */
6242 my_getExpression (&imm_expr
, s
);
6243 check_absolute_expr (ip
, &imm_expr
);
6244 if ((unsigned long) imm_expr
.X_add_number
< 32
6245 || (unsigned long) imm_expr
.X_add_number
> 63)
6247 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6248 imm_expr
.X_op
= O_absent
;
6252 case 'k': /* cache code */
6253 case 'h': /* prefx code */
6254 my_getExpression (&imm_expr
, s
);
6255 check_absolute_expr (ip
, &imm_expr
);
6256 if ((unsigned long) imm_expr
.X_add_number
> 31)
6258 as_warn ("Invalid value for `%s' (%lu)",
6260 (unsigned long) imm_expr
.X_add_number
);
6261 imm_expr
.X_add_number
&= 0x1f;
6264 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6266 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6267 imm_expr
.X_op
= O_absent
;
6271 case 'c': /* break code */
6272 my_getExpression (&imm_expr
, s
);
6273 check_absolute_expr (ip
, &imm_expr
);
6274 if ((unsigned) imm_expr
.X_add_number
> 1023)
6275 as_warn ("Illegal break code (%ld)",
6276 (long) imm_expr
.X_add_number
);
6277 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6278 imm_expr
.X_op
= O_absent
;
6282 case 'B': /* syscall code */
6283 my_getExpression (&imm_expr
, s
);
6284 check_absolute_expr (ip
, &imm_expr
);
6285 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6286 as_warn ("Illegal syscall code (%ld)",
6287 (long) imm_expr
.X_add_number
);
6288 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6289 imm_expr
.X_op
= O_absent
;
6293 case 'C': /* Coprocessor code */
6294 my_getExpression (&imm_expr
, s
);
6295 check_absolute_expr (ip
, &imm_expr
);
6296 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6298 as_warn ("Coproccesor code > 25 bits (%ld)",
6299 (long) imm_expr
.X_add_number
);
6300 imm_expr
.X_add_number
&= ((1<<25) - 1);
6302 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6303 imm_expr
.X_op
= O_absent
;
6307 case 'b': /* base register */
6308 case 'd': /* destination register */
6309 case 's': /* source register */
6310 case 't': /* target register */
6311 case 'r': /* both target and source */
6312 case 'v': /* both dest and source */
6313 case 'w': /* both dest and target */
6314 case 'E': /* coprocessor target register */
6315 case 'G': /* coprocessor destination register */
6316 case 'x': /* ignore register name */
6317 case 'z': /* must be zero register */
6331 while (isdigit (*s
));
6333 as_bad ("Invalid register number (%d)", regno
);
6335 else if (*args
== 'E' || *args
== 'G')
6339 if (s
[1] == 'f' && s
[2] == 'p')
6344 else if (s
[1] == 's' && s
[2] == 'p')
6349 else if (s
[1] == 'g' && s
[2] == 'p')
6354 else if (s
[1] == 'a' && s
[2] == 't')
6359 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6364 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6376 as_warn ("Used $at without \".set noat\"");
6382 if (c
== 'r' || c
== 'v' || c
== 'w')
6389 /* 'z' only matches $0. */
6390 if (c
== 'z' && regno
!= 0)
6398 ip
->insn_opcode
|= regno
<< 21;
6402 ip
->insn_opcode
|= regno
<< 11;
6407 ip
->insn_opcode
|= regno
<< 16;
6410 /* This case exists because on the r3000 trunc
6411 expands into a macro which requires a gp
6412 register. On the r6000 or r4000 it is
6413 assembled into a single instruction which
6414 ignores the register. Thus the insn version
6415 is MIPS_ISA2 and uses 'x', and the macro
6416 version is MIPS_ISA1 and uses 't'. */
6419 /* This case is for the div instruction, which
6420 acts differently if the destination argument
6421 is $0. This only matches $0, and is checked
6422 outside the switch. */
6433 ip
->insn_opcode
|= lastregno
<< 21;
6436 ip
->insn_opcode
|= lastregno
<< 16;
6441 case 'D': /* floating point destination register */
6442 case 'S': /* floating point source register */
6443 case 'T': /* floating point target register */
6444 case 'R': /* floating point source register */
6448 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6458 while (isdigit (*s
));
6461 as_bad ("Invalid float register number (%d)", regno
);
6463 if ((regno
& 1) != 0
6465 && ! (strcmp (str
, "mtc1") == 0
6466 || strcmp (str
, "mfc1") == 0
6467 || strcmp (str
, "lwc1") == 0
6468 || strcmp (str
, "swc1") == 0
6469 || strcmp (str
, "l.s") == 0
6470 || strcmp (str
, "s.s") == 0))
6471 as_warn ("Float register should be even, was %d",
6479 if (c
== 'V' || c
== 'W')
6489 ip
->insn_opcode
|= regno
<< 6;
6493 ip
->insn_opcode
|= regno
<< 11;
6497 ip
->insn_opcode
|= regno
<< 16;
6500 ip
->insn_opcode
|= regno
<< 21;
6509 ip
->insn_opcode
|= lastregno
<< 11;
6512 ip
->insn_opcode
|= lastregno
<< 16;
6518 my_getExpression (&imm_expr
, s
);
6519 if (imm_expr
.X_op
!= O_big
6520 && imm_expr
.X_op
!= O_constant
)
6521 insn_error
= "absolute expression required";
6526 my_getExpression (&offset_expr
, s
);
6527 imm_reloc
= BFD_RELOC_32
;
6539 unsigned char temp
[8];
6541 unsigned int length
;
6546 /* These only appear as the last operand in an
6547 instruction, and every instruction that accepts
6548 them in any variant accepts them in all variants.
6549 This means we don't have to worry about backing out
6550 any changes if the instruction does not match.
6552 The difference between them is the size of the
6553 floating point constant and where it goes. For 'F'
6554 and 'L' the constant is 64 bits; for 'f' and 'l' it
6555 is 32 bits. Where the constant is placed is based
6556 on how the MIPS assembler does things:
6559 f -- immediate value
6562 The .lit4 and .lit8 sections are only used if
6563 permitted by the -G argument.
6565 When generating embedded PIC code, we use the
6566 .lit8 section but not the .lit4 section (we can do
6567 .lit4 inline easily; we need to put .lit8
6568 somewhere in the data segment, and using .lit8
6569 permits the linker to eventually combine identical
6572 f64
= *args
== 'F' || *args
== 'L';
6574 save_in
= input_line_pointer
;
6575 input_line_pointer
= s
;
6576 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6578 s
= input_line_pointer
;
6579 input_line_pointer
= save_in
;
6580 if (err
!= NULL
&& *err
!= '\0')
6582 as_bad ("Bad floating point constant: %s", err
);
6583 memset (temp
, '\0', sizeof temp
);
6584 length
= f64
? 8 : 4;
6587 assert (length
== (f64
? 8 : 4));
6591 && (! USE_GLOBAL_POINTER_OPT
6592 || mips_pic
== EMBEDDED_PIC
6593 || g_switch_value
< 4)
6596 imm_expr
.X_op
= O_constant
;
6597 if (! target_big_endian
)
6598 imm_expr
.X_add_number
=
6599 (((((((int) temp
[3] << 8)
6604 imm_expr
.X_add_number
=
6605 (((((((int) temp
[0] << 8)
6612 const char *newname
;
6615 /* Switch to the right section. */
6617 subseg
= now_subseg
;
6620 default: /* unused default case avoids warnings. */
6622 newname
= RDATA_SECTION_NAME
;
6623 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6627 newname
= RDATA_SECTION_NAME
;
6630 assert (!USE_GLOBAL_POINTER_OPT
6631 || g_switch_value
>= 4);
6635 new_seg
= subseg_new (newname
, (subsegT
) 0);
6636 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6637 bfd_set_section_flags (stdoutput
, new_seg
,
6642 frag_align (*args
== 'l' ? 2 : 3, 0);
6643 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6644 record_alignment (new_seg
, 4);
6646 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6648 as_bad ("Can't use floating point insn in this section");
6650 /* Set the argument to the current address in the
6652 offset_expr
.X_op
= O_symbol
;
6653 offset_expr
.X_add_symbol
=
6654 symbol_new ("L0\001", now_seg
,
6655 (valueT
) frag_now_fix (), frag_now
);
6656 offset_expr
.X_add_number
= 0;
6658 /* Put the floating point number into the section. */
6659 p
= frag_more ((int) length
);
6660 memcpy (p
, temp
, length
);
6662 /* Switch back to the original section. */
6663 subseg_set (seg
, subseg
);
6668 case 'i': /* 16 bit unsigned immediate */
6669 case 'j': /* 16 bit signed immediate */
6670 imm_reloc
= BFD_RELOC_LO16
;
6671 c
= my_getSmallExpression (&imm_expr
, s
);
6676 if (imm_expr
.X_op
== O_constant
)
6677 imm_expr
.X_add_number
=
6678 (imm_expr
.X_add_number
>> 16) & 0xffff;
6681 imm_reloc
= BFD_RELOC_HI16_S
;
6682 imm_unmatched_hi
= true;
6685 imm_reloc
= BFD_RELOC_HI16
;
6690 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6691 || ((imm_expr
.X_add_number
< 0
6692 || imm_expr
.X_add_number
>= 0x10000)
6693 && imm_expr
.X_op
== O_constant
))
6695 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6696 !strcmp (insn
->name
, insn
[1].name
))
6698 if (imm_expr
.X_op
!= O_constant
6699 && imm_expr
.X_op
!= O_big
)
6700 insn_error
= "absolute expression required";
6702 as_bad ("16 bit expression not in range 0..65535");
6710 /* The upper bound should be 0x8000, but
6711 unfortunately the MIPS assembler accepts numbers
6712 from 0x8000 to 0xffff and sign extends them, and
6713 we want to be compatible. We only permit this
6714 extended range for an instruction which does not
6715 provide any further alternates, since those
6716 alternates may handle other cases. People should
6717 use the numbers they mean, rather than relying on
6718 a mysterious sign extension. */
6719 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6720 strcmp (insn
->name
, insn
[1].name
) == 0);
6725 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6726 || ((imm_expr
.X_add_number
< -0x8000
6727 || imm_expr
.X_add_number
>= max
)
6728 && imm_expr
.X_op
== O_constant
)
6730 && imm_expr
.X_add_number
< 0
6732 && imm_expr
.X_unsigned
6733 && sizeof (imm_expr
.X_add_number
) <= 4))
6737 if (imm_expr
.X_op
!= O_constant
6738 && imm_expr
.X_op
!= O_big
)
6739 insn_error
= "absolute expression required";
6741 as_bad ("16 bit expression not in range -32768..32767");
6747 case 'o': /* 16 bit offset */
6748 c
= my_getSmallExpression (&offset_expr
, s
);
6750 /* If this value won't fit into a 16 bit offset, then go
6751 find a macro that will generate the 32 bit offset
6752 code pattern. As a special hack, we accept the
6753 difference of two local symbols as a constant. This
6754 is required to suppose embedded PIC switches, which
6755 use an instruction which looks like
6756 lw $4,$L12-$LS12($4)
6757 The problem with handling this in a more general
6758 fashion is that the macro function doesn't expect to
6759 see anything which can be handled in a single
6760 constant instruction. */
6762 && (offset_expr
.X_op
!= O_constant
6763 || offset_expr
.X_add_number
>= 0x8000
6764 || offset_expr
.X_add_number
< -0x8000)
6765 && (mips_pic
!= EMBEDDED_PIC
6766 || offset_expr
.X_op
!= O_subtract
6767 || now_seg
!= text_section
6768 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6772 offset_reloc
= BFD_RELOC_LO16
;
6773 if (c
== 'h' || c
== 'H')
6775 assert (offset_expr
.X_op
== O_constant
);
6776 offset_expr
.X_add_number
=
6777 (offset_expr
.X_add_number
>> 16) & 0xffff;
6782 case 'p': /* pc relative offset */
6783 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6784 my_getExpression (&offset_expr
, s
);
6788 case 'u': /* upper 16 bits */
6789 c
= my_getSmallExpression (&imm_expr
, s
);
6790 if (imm_expr
.X_op
== O_constant
6791 && (imm_expr
.X_add_number
< 0
6792 || imm_expr
.X_add_number
>= 0x10000))
6793 as_bad ("lui expression not in range 0..65535");
6794 imm_reloc
= BFD_RELOC_LO16
;
6799 if (imm_expr
.X_op
== O_constant
)
6800 imm_expr
.X_add_number
=
6801 (imm_expr
.X_add_number
>> 16) & 0xffff;
6804 imm_reloc
= BFD_RELOC_HI16_S
;
6805 imm_unmatched_hi
= true;
6808 imm_reloc
= BFD_RELOC_HI16
;
6814 case 'a': /* 26 bit address */
6815 my_getExpression (&offset_expr
, s
);
6817 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6820 case 'N': /* 3 bit branch condition code */
6821 case 'M': /* 3 bit compare condition code */
6822 if (strncmp (s
, "$fcc", 4) != 0)
6832 while (isdigit (*s
));
6834 as_bad ("invalid condition code register $fcc%d", regno
);
6836 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6838 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6842 fprintf (stderr
, "bad char = '%c'\n", *args
);
6847 /* Args don't match. */
6848 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6849 !strcmp (insn
->name
, insn
[1].name
))
6855 insn_error
= "illegal operands";
6860 /* This routine assembles an instruction into its binary format when
6861 assembling for the mips16. As a side effect, it sets one of the
6862 global variables imm_reloc or offset_reloc to the type of
6863 relocation to do if one of the operands is an address expression.
6864 It also sets mips16_small and mips16_ext if the user explicitly
6865 requested a small or extended instruction. */
6870 struct mips_cl_insn
*ip
;
6874 struct mips_opcode
*insn
;
6877 unsigned int lastregno
= 0;
6882 mips16_small
= false;
6885 for (s
= str
; islower (*s
); ++s
)
6897 if (s
[1] == 't' && s
[2] == ' ')
6900 mips16_small
= true;
6904 else if (s
[1] == 'e' && s
[2] == ' ')
6913 insn_error
= "unknown opcode";
6917 if (! mips16_autoextend
&& ! mips16_ext
)
6918 mips16_small
= true;
6920 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6922 insn_error
= "unrecognized opcode";
6929 assert (strcmp (insn
->name
, str
) == 0);
6932 ip
->insn_opcode
= insn
->match
;
6933 ip
->use_extend
= false;
6934 imm_expr
.X_op
= O_absent
;
6935 imm_reloc
= BFD_RELOC_UNUSED
;
6936 offset_expr
.X_op
= O_absent
;
6937 offset_reloc
= BFD_RELOC_UNUSED
;
6938 for (args
= insn
->args
; 1; ++args
)
6945 /* In this switch statement we call break if we did not find
6946 a match, continue if we did find a match, or return if we
6955 /* Stuff the immediate value in now, if we can. */
6956 if (imm_expr
.X_op
== O_constant
6957 && imm_reloc
> BFD_RELOC_UNUSED
6958 && insn
->pinfo
!= INSN_MACRO
)
6960 mips16_immed ((char *) NULL
, 0,
6961 imm_reloc
- BFD_RELOC_UNUSED
,
6962 imm_expr
.X_add_number
, true, mips16_small
,
6963 mips16_ext
, &ip
->insn_opcode
,
6964 &ip
->use_extend
, &ip
->extend
);
6965 imm_expr
.X_op
= O_absent
;
6966 imm_reloc
= BFD_RELOC_UNUSED
;
6980 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6983 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6999 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7001 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7028 while (isdigit (*s
));
7031 as_bad ("invalid register number (%d)", regno
);
7037 if (s
[1] == 'f' && s
[2] == 'p')
7042 else if (s
[1] == 's' && s
[2] == 'p')
7047 else if (s
[1] == 'g' && s
[2] == 'p')
7052 else if (s
[1] == 'a' && s
[2] == 't')
7057 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7062 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7075 if (c
== 'v' || c
== 'w')
7077 regno
= mips16_to_32_reg_map
[lastregno
];
7091 regno
= mips32_to_16_reg_map
[regno
];
7096 regno
= ILLEGAL_REG
;
7101 regno
= ILLEGAL_REG
;
7106 regno
= ILLEGAL_REG
;
7111 if (regno
== AT
&& ! mips_noat
)
7112 as_warn ("used $at without \".set noat\"");
7119 if (regno
== ILLEGAL_REG
)
7126 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7130 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7133 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7136 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7142 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7145 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7146 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7156 if (strncmp (s
, "$pc", 3) == 0)
7179 if (s
[0] == '$' && isdigit (s
[1]))
7181 /* Looks like a register name. */
7189 /* It looks like the expression was omitted before a
7190 register indirection, which means that the
7191 expression is implicitly zero. We still set up
7192 imm_expr, so that we handle explicit extensions
7194 imm_expr
.X_op
= O_constant
;
7195 imm_expr
.X_add_number
= 0;
7196 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7201 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7203 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7204 and generate the appropriate reloc. If the text
7205 inside %gprel is not a symbol name with an
7206 optional offset, then we generate a normal reloc
7207 and will probably fail later. */
7208 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7209 if (imm_expr
.X_op
== O_symbol
)
7212 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7214 ip
->use_extend
= true;
7221 /* Just pick up a normal expression. */
7222 my_getExpression (&imm_expr
, s
);
7225 /* We need to relax this instruction. */
7226 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7235 /* We use offset_reloc rather than imm_reloc for the PC
7236 relative operands. This lets macros with both
7237 immediate and address operands work correctly. */
7238 if (s
[0] == '$' && isdigit (s
[1]))
7240 /* Looks like a register name. */
7243 my_getExpression (&offset_expr
, s
);
7244 /* We need to relax this instruction. */
7245 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7249 case '6': /* break code */
7250 my_getExpression (&imm_expr
, s
);
7251 check_absolute_expr (ip
, &imm_expr
);
7252 if ((unsigned long) imm_expr
.X_add_number
> 63)
7254 as_warn ("Invalid value for `%s' (%lu)",
7256 (unsigned long) imm_expr
.X_add_number
);
7257 imm_expr
.X_add_number
&= 0x3f;
7259 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7260 imm_expr
.X_op
= O_absent
;
7264 case 'a': /* 26 bit address */
7265 my_getExpression (&offset_expr
, s
);
7267 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7268 ip
->insn_opcode
<<= 16;
7271 case 'l': /* register list for entry macro */
7272 case 'L': /* register list for exit macro */
7282 int freg
, reg1
, reg2
;
7284 while (*s
== ' ' || *s
== ',')
7288 as_bad ("can't parse register list");
7300 while (isdigit (*s
))
7322 as_bad ("invalid register list");
7327 while (isdigit (*s
))
7334 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7339 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7344 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7345 mask
|= (reg2
- 3) << 3;
7346 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7347 mask
|= (reg2
- 15) << 1;
7348 else if (reg1
== 31 && reg2
== 31)
7352 as_bad ("invalid register list");
7356 /* The mask is filled in in the opcode table for the
7357 benefit of the disassembler. We remove it before
7358 applying the actual mask. */
7359 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7360 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7370 /* Args don't match. */
7371 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7372 strcmp (insn
->name
, insn
[1].name
) == 0)
7379 insn_error
= "illegal operands";
7385 /* This structure holds information we know about a mips16 immediate
7388 struct mips16_immed_operand
7390 /* The type code used in the argument string in the opcode table. */
7392 /* The number of bits in the short form of the opcode. */
7394 /* The number of bits in the extended form of the opcode. */
7396 /* The amount by which the short form is shifted when it is used;
7397 for example, the sw instruction has a shift count of 2. */
7399 /* The amount by which the short form is shifted when it is stored
7400 into the instruction code. */
7402 /* Non-zero if the short form is unsigned. */
7404 /* Non-zero if the extended form is unsigned. */
7406 /* Non-zero if the value is PC relative. */
7410 /* The mips16 immediate operand types. */
7412 static const struct mips16_immed_operand mips16_immed_operands
[] =
7414 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7415 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7416 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7417 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7418 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7419 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7420 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7421 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7422 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7423 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7424 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7425 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7426 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7427 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7428 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7429 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7430 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7431 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7432 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7433 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7434 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7437 #define MIPS16_NUM_IMMED \
7438 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7440 /* Handle a mips16 instruction with an immediate value. This or's the
7441 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7442 whether an extended value is needed; if one is needed, it sets
7443 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7444 If SMALL is true, an unextended opcode was explicitly requested.
7445 If EXT is true, an extended opcode was explicitly requested. If
7446 WARN is true, warn if EXT does not match reality. */
7449 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7458 unsigned long *insn
;
7459 boolean
*use_extend
;
7460 unsigned short *extend
;
7462 register const struct mips16_immed_operand
*op
;
7463 int mintiny
, maxtiny
;
7466 op
= mips16_immed_operands
;
7467 while (op
->type
!= type
)
7470 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7475 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7478 maxtiny
= 1 << op
->nbits
;
7483 maxtiny
= (1 << op
->nbits
) - 1;
7488 mintiny
= - (1 << (op
->nbits
- 1));
7489 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7492 /* Branch offsets have an implicit 0 in the lowest bit. */
7493 if (type
== 'p' || type
== 'q')
7496 if ((val
& ((1 << op
->shift
) - 1)) != 0
7497 || val
< (mintiny
<< op
->shift
)
7498 || val
> (maxtiny
<< op
->shift
))
7503 if (warn
&& ext
&& ! needext
)
7504 as_warn_where (file
, line
, "extended operand requested but not required");
7505 if (small
&& needext
)
7506 as_bad_where (file
, line
, "invalid unextended operand value");
7508 if (small
|| (! ext
&& ! needext
))
7512 *use_extend
= false;
7513 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7514 insnval
<<= op
->op_shift
;
7519 long minext
, maxext
;
7525 maxext
= (1 << op
->extbits
) - 1;
7529 minext
= - (1 << (op
->extbits
- 1));
7530 maxext
= (1 << (op
->extbits
- 1)) - 1;
7532 if (val
< minext
|| val
> maxext
)
7533 as_bad_where (file
, line
,
7534 "operand value out of range for instruction");
7537 if (op
->extbits
== 16)
7539 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7542 else if (op
->extbits
== 15)
7544 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7549 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7553 *extend
= (unsigned short) extval
;
7562 my_getSmallExpression (ep
, str
)
7573 ((str
[1] == 'h' && str
[2] == 'i')
7574 || (str
[1] == 'H' && str
[2] == 'I')
7575 || (str
[1] == 'l' && str
[2] == 'o'))
7587 * A small expression may be followed by a base register.
7588 * Scan to the end of this operand, and then back over a possible
7589 * base register. Then scan the small expression up to that
7590 * point. (Based on code in sparc.c...)
7592 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7594 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7596 if (isdigit (sp
[-2]))
7598 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7600 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7606 else if (sp
- 5 >= str
7609 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7610 || (sp
[-3] == 's' && sp
[-2] == 'p')
7611 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7612 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7618 /* no expression means zero offset */
7621 /* %xx(reg) is an error */
7622 ep
->X_op
= O_absent
;
7627 ep
->X_op
= O_constant
;
7630 ep
->X_add_symbol
= NULL
;
7631 ep
->X_op_symbol
= NULL
;
7632 ep
->X_add_number
= 0;
7637 my_getExpression (ep
, str
);
7644 my_getExpression (ep
, str
);
7645 return c
; /* => %hi or %lo encountered */
7649 my_getExpression (ep
, str
)
7655 save_in
= input_line_pointer
;
7656 input_line_pointer
= str
;
7658 expr_end
= input_line_pointer
;
7659 input_line_pointer
= save_in
;
7662 /* Turn a string in input_line_pointer into a floating point constant
7663 of type type, and store the appropriate bytes in *litP. The number
7664 of LITTLENUMS emitted is stored in *sizeP . An error message is
7665 returned, or NULL on OK. */
7668 md_atof (type
, litP
, sizeP
)
7674 LITTLENUM_TYPE words
[4];
7690 return "bad call to md_atof";
7693 t
= atof_ieee (input_line_pointer
, type
, words
);
7695 input_line_pointer
= t
;
7699 if (! target_big_endian
)
7701 for (i
= prec
- 1; i
>= 0; i
--)
7703 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7709 for (i
= 0; i
< prec
; i
++)
7711 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7720 md_number_to_chars (buf
, val
, n
)
7725 if (target_big_endian
)
7726 number_to_chars_bigendian (buf
, val
, n
);
7728 number_to_chars_littleendian (buf
, val
, n
);
7731 CONST
char *md_shortopts
= "O::g::G:";
7733 struct option md_longopts
[] = {
7734 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7735 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7736 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7737 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7738 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7739 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7740 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7741 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7742 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7743 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7744 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7745 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7746 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7747 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7748 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7749 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7750 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7751 {"break", no_argument
, NULL
, OPTION_BREAK
},
7752 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7753 #define OPTION_EB (OPTION_MD_BASE + 11)
7754 {"EB", no_argument
, NULL
, OPTION_EB
},
7755 #define OPTION_EL (OPTION_MD_BASE + 12)
7756 {"EL", no_argument
, NULL
, OPTION_EL
},
7757 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7758 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7759 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7760 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7761 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7762 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7763 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7764 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7765 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7766 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7767 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7768 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7769 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7770 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7771 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7772 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7773 /* start-sanitize-5900 */
7774 #define OPTION_M5900 (OPTION_MD_BASE + 24)
7775 {"m5900", no_argument
, NULL
, OPTION_M5900
},
7776 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
7777 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
7778 /* end-sanitize-5900 */
7780 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7781 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7782 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7783 #define OPTION_32 (OPTION_MD_BASE + 20)
7784 #define OPTION_64 (OPTION_MD_BASE + 21)
7786 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7787 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7788 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7789 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7790 {"32", no_argument
, NULL
, OPTION_32
},
7791 {"64", no_argument
, NULL
, OPTION_64
},
7794 {NULL
, no_argument
, NULL
, 0}
7796 size_t md_longopts_size
= sizeof(md_longopts
);
7799 md_parse_option (c
, arg
)
7814 target_big_endian
= 1;
7818 target_big_endian
= 0;
7822 if (arg
&& arg
[1] == '0')
7832 mips_debug
= atoi (arg
);
7833 /* When the MIPS assembler sees -g or -g2, it does not do
7834 optimizations which limit full symbolic debugging. We take
7835 that to be equivalent to -O0. */
7836 if (mips_debug
== 2)
7868 /* Identify the processor type */
7870 if (strcmp (p
, "default") == 0
7871 || strcmp (p
, "DEFAULT") == 0)
7877 /* We need to cope with the various "vr" prefixes for the 4300
7879 if (*p
== 'v' || *p
== 'V')
7885 if (*p
== 'r' || *p
== 'R')
7892 if (strcmp (p
, "10000") == 0
7893 || strcmp (p
, "10k") == 0
7894 || strcmp (p
, "10K") == 0)
7899 if (strcmp (p
, "2000") == 0
7900 || strcmp (p
, "2k") == 0
7901 || strcmp (p
, "2K") == 0)
7906 if (strcmp (p
, "3000") == 0
7907 || strcmp (p
, "3k") == 0
7908 || strcmp (p
, "3K") == 0)
7913 if (strcmp (p
, "4000") == 0
7914 || strcmp (p
, "4k") == 0
7915 || strcmp (p
, "4K") == 0)
7917 else if (strcmp (p
, "4100") == 0)
7923 else if (strcmp (p
, "4300") == 0)
7925 else if (strcmp (p
, "4400") == 0)
7927 else if (strcmp (p
, "4600") == 0)
7929 else if (strcmp (p
, "4650") == 0)
7935 else if (strcmp (p
, "4010") == 0)
7944 if (strcmp (p
, "5000") == 0
7945 || strcmp (p
, "5k") == 0
7946 || strcmp (p
, "5K") == 0)
7948 /* start-sanitize-r5900 */
7949 else if (strcmp (p
, "5900") == 0)
7951 /* end-sanitize-r5900 */
7955 if (strcmp (p
, "6000") == 0
7956 || strcmp (p
, "6k") == 0
7957 || strcmp (p
, "6K") == 0)
7962 if (strcmp (p
, "8000") == 0
7963 || strcmp (p
, "8k") == 0
7964 || strcmp (p
, "8K") == 0)
7969 if (strcmp (p
, "orion") == 0)
7974 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
7976 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
7982 as_bad ("invalid architecture -mcpu=%s", arg
);
7993 case OPTION_NO_M4650
:
8001 case OPTION_NO_M4010
:
8009 case OPTION_NO_M4100
:
8013 /* start-sanitize-r5900 */
8018 case OPTION_NO_M5900
:
8021 /* end-sanitize-r5900 */
8025 mips_no_prev_insn ();
8028 case OPTION_NO_MIPS16
:
8030 mips_no_prev_insn ();
8033 case OPTION_MEMBEDDED_PIC
:
8034 mips_pic
= EMBEDDED_PIC
;
8035 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8037 as_bad ("-G may not be used with embedded PIC code");
8040 g_switch_value
= 0x7fffffff;
8043 /* When generating ELF code, we permit -KPIC and -call_shared to
8044 select SVR4_PIC, and -non_shared to select no PIC. This is
8045 intended to be compatible with Irix 5. */
8046 case OPTION_CALL_SHARED
:
8047 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8049 as_bad ("-call_shared is supported only for ELF format");
8052 mips_pic
= SVR4_PIC
;
8053 if (g_switch_seen
&& g_switch_value
!= 0)
8055 as_bad ("-G may not be used with SVR4 PIC code");
8061 case OPTION_NON_SHARED
:
8062 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8064 as_bad ("-non_shared is supported only for ELF format");
8070 /* The -xgot option tells the assembler to use 32 offsets when
8071 accessing the got in SVR4_PIC mode. It is for Irix
8078 if (! USE_GLOBAL_POINTER_OPT
)
8080 as_bad ("-G is not supported for this configuration");
8083 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8085 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8089 g_switch_value
= atoi (arg
);
8093 /* The -32 and -64 options tell the assembler to output the 32
8094 bit or the 64 bit MIPS ELF format. */
8101 const char **list
, **l
;
8103 list
= bfd_target_list ();
8104 for (l
= list
; *l
!= NULL
; l
++)
8105 if (strcmp (*l
, "elf64-bigmips") == 0
8106 || strcmp (*l
, "elf64-littlemips") == 0)
8109 as_fatal ("No compiled in support for 64 bit object file format");
8123 md_show_usage (stream
)
8128 -membedded-pic generate embedded position independent code\n\
8129 -EB generate big endian output\n\
8130 -EL generate little endian output\n\
8131 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8132 -G NUM allow referencing objects up to NUM bytes\n\
8133 implicitly with the gp register [default 8]\n");
8135 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8136 -mips2, -mcpu=r6000 generate code for r6000\n\
8137 -mips3, -mcpu=r4000 generate code for r4000\n\
8138 -mips4, -mcpu=r8000 generate code for r8000\n\
8139 -mcpu=vr4300 generate code for vr4300\n\
8140 -mcpu=vr4100 generate code for vr4100\n\
8141 -m4650 permit R4650 instructions\n\
8142 -no-m4650 do not permit R4650 instructions\n\
8143 -m4010 permit R4010 instructions\n\
8144 -no-m4010 do not permit R4010 instructions\n\
8145 -m4100 permit VR4100 instructions\n\
8146 -no-m4100 do not permit VR4100 instructions\n");
8148 -mips16 generate mips16 instructions\n\
8149 -no-mips16 do not generate mips16 instructions\n");
8151 -O0 remove unneeded NOPs, do not swap branches\n\
8152 -O remove unneeded NOPs and swap branches\n\
8153 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8154 --break, --no-trap break exception on div by 0 and mult overflow\n");
8157 -KPIC, -call_shared generate SVR4 position independent code\n\
8158 -non_shared do not generate position independent code\n\
8159 -xgot assume a 32 bit GOT\n\
8160 -32 create 32 bit object file (default)\n\
8161 -64 create 64 bit object file\n");
8166 md_pcrel_from (fixP
)
8169 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8170 && fixP
->fx_addsy
!= (symbolS
*) NULL
8171 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8173 /* This makes a branch to an undefined symbol be a branch to the
8174 current location. */
8178 /* return the address of the delay slot */
8179 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8182 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8183 reloc for a cons. We could use the definition there, except that
8184 we want to handle 64 bit relocs specially. */
8187 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8190 unsigned int nbytes
;
8194 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8196 if (nbytes
== 8 && ! mips_64
)
8198 if (target_big_endian
)
8204 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8205 as_bad ("Unsupported reloc size %d", nbytes
);
8207 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8210 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8213 /* Sort any unmatched HI16_S relocs so that they immediately precede
8214 the corresponding LO reloc. This is called before md_apply_fix and
8215 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8216 explicit use of the %hi modifier. */
8221 struct mips_hi_fixup
*l
;
8223 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8225 segment_info_type
*seginfo
;
8228 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8230 /* Check quickly whether the next fixup happens to be a matching
8232 if (l
->fixp
->fx_next
!= NULL
8233 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8234 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8235 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8238 /* Look through the fixups for this segment for a matching %lo.
8239 When we find one, move the %hi just in front of it. We do
8240 this in two passes. In the first pass, we try to find a
8241 unique %lo. In the second pass, we permit multiple %hi
8242 relocs for a single %lo (this is a GNU extension). */
8243 seginfo
= seg_info (l
->seg
);
8244 for (pass
= 0; pass
< 2; pass
++)
8249 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8251 /* Check whether this is a %lo fixup which matches l->fixp. */
8252 if (f
->fx_r_type
== BFD_RELOC_LO16
8253 && f
->fx_addsy
== l
->fixp
->fx_addsy
8254 && f
->fx_offset
== l
->fixp
->fx_offset
8257 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8258 || prev
->fx_addsy
!= f
->fx_addsy
8259 || prev
->fx_offset
!= f
->fx_offset
))
8263 /* Move l->fixp before f. */
8264 for (pf
= &seginfo
->fix_root
;
8266 pf
= &(*pf
)->fx_next
)
8267 assert (*pf
!= NULL
);
8269 *pf
= l
->fixp
->fx_next
;
8271 l
->fixp
->fx_next
= f
;
8273 seginfo
->fix_root
= l
->fixp
;
8275 prev
->fx_next
= l
->fixp
;
8287 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8288 "Unmatched %%hi reloc");
8293 /* When generating embedded PIC code we need to use a special
8294 relocation to represent the difference of two symbols in the .text
8295 section (switch tables use a difference of this sort). See
8296 include/coff/mips.h for details. This macro checks whether this
8297 fixup requires the special reloc. */
8298 #define SWITCH_TABLE(fixp) \
8299 ((fixp)->fx_r_type == BFD_RELOC_32 \
8300 && (fixp)->fx_addsy != NULL \
8301 && (fixp)->fx_subsy != NULL \
8302 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8303 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8305 /* When generating embedded PIC code we must keep all PC relative
8306 relocations, in case the linker has to relax a call. We also need
8307 to keep relocations for switch table entries. */
8311 mips_force_relocation (fixp
)
8314 return (mips_pic
== EMBEDDED_PIC
8316 || SWITCH_TABLE (fixp
)
8317 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8318 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8321 /* Apply a fixup to the object file. */
8324 md_apply_fix (fixP
, valueP
)
8331 assert (fixP
->fx_size
== 4
8332 || fixP
->fx_r_type
== BFD_RELOC_16
8333 || fixP
->fx_r_type
== BFD_RELOC_64
);
8337 /* If we aren't adjusting this fixup to be against the section
8338 symbol, we need to adjust the value. */
8340 if (fixP
->fx_addsy
!= NULL
8341 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8342 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8344 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8345 if (value
!= 0 && ! fixP
->fx_pcrel
)
8347 /* In this case, the bfd_install_relocation routine will
8348 incorrectly add the symbol value back in. We just want
8349 the addend to appear in the object file. */
8350 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8355 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8357 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8360 switch (fixP
->fx_r_type
)
8362 case BFD_RELOC_MIPS_JMP
:
8363 case BFD_RELOC_HI16
:
8364 case BFD_RELOC_HI16_S
:
8365 case BFD_RELOC_MIPS_GPREL
:
8366 case BFD_RELOC_MIPS_LITERAL
:
8367 case BFD_RELOC_MIPS_CALL16
:
8368 case BFD_RELOC_MIPS_GOT16
:
8369 case BFD_RELOC_MIPS_GPREL32
:
8370 case BFD_RELOC_MIPS_GOT_HI16
:
8371 case BFD_RELOC_MIPS_GOT_LO16
:
8372 case BFD_RELOC_MIPS_CALL_HI16
:
8373 case BFD_RELOC_MIPS_CALL_LO16
:
8374 case BFD_RELOC_MIPS16_GPREL
:
8376 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8377 "Invalid PC relative reloc");
8378 /* Nothing needed to do. The value comes from the reloc entry */
8381 case BFD_RELOC_MIPS16_JMP
:
8382 /* We currently always generate a reloc against a symbol, which
8383 means that we don't want an addend even if the symbol is
8385 fixP
->fx_addnumber
= 0;
8388 case BFD_RELOC_PCREL_HI16_S
:
8389 /* The addend for this is tricky if it is internal, so we just
8390 do everything here rather than in bfd_perform_relocation. */
8391 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8393 /* For an external symbol adjust by the address to make it
8394 pcrel_offset. We use the address of the RELLO reloc
8395 which follows this one. */
8396 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8397 + fixP
->fx_next
->fx_where
);
8402 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8403 if (target_big_endian
)
8405 md_number_to_chars (buf
, value
, 2);
8408 case BFD_RELOC_PCREL_LO16
:
8409 /* The addend for this is tricky if it is internal, so we just
8410 do everything here rather than in bfd_perform_relocation. */
8411 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8412 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8413 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8414 if (target_big_endian
)
8416 md_number_to_chars (buf
, value
, 2);
8420 /* This is handled like BFD_RELOC_32, but we output a sign
8421 extended value if we are only 32 bits. */
8423 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8425 if (8 <= sizeof (valueT
))
8426 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8433 w1
= w2
= fixP
->fx_where
;
8434 if (target_big_endian
)
8438 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8439 if ((value
& 0x80000000) != 0)
8443 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8449 /* If we are deleting this reloc entry, we must fill in the
8450 value now. This can happen if we have a .word which is not
8451 resolved when it appears but is later defined. We also need
8452 to fill in the value if this is an embedded PIC switch table
8455 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8456 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8461 /* If we are deleting this reloc entry, we must fill in the
8463 assert (fixP
->fx_size
== 2);
8465 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8469 case BFD_RELOC_LO16
:
8470 /* When handling an embedded PIC switch statement, we can wind
8471 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8474 if (value
< -0x8000 || value
> 0x7fff)
8475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8476 "relocation overflow");
8477 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8478 if (target_big_endian
)
8480 md_number_to_chars (buf
, value
, 2);
8484 case BFD_RELOC_16_PCREL_S2
:
8486 * We need to save the bits in the instruction since fixup_segment()
8487 * might be deleting the relocation entry (i.e., a branch within
8488 * the current segment).
8490 if ((value
& 0x3) != 0)
8491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8492 "Branch to odd address (%lx)", value
);
8495 /* update old instruction data */
8496 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8497 if (target_big_endian
)
8498 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8500 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8502 if (value
>= -0x8000 && value
< 0x8000)
8503 insn
|= value
& 0xffff;
8506 /* The branch offset is too large. If this is an
8507 unconditional branch, and we are not generating PIC code,
8508 we can convert it to an absolute jump instruction. */
8509 if (mips_pic
== NO_PIC
8511 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8512 && (fixP
->fx_frag
->fr_address
8513 < text_section
->vma
+ text_section
->_raw_size
)
8514 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8515 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8516 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8518 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8519 insn
= 0x0c000000; /* jal */
8521 insn
= 0x08000000; /* j */
8522 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8524 fixP
->fx_addsy
= section_symbol (text_section
);
8525 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8529 /* FIXME. It would be possible in principle to handle
8530 conditional branches which overflow. They could be
8531 transformed into a branch around a jump. This would
8532 require setting up variant frags for each different
8533 branch type. The native MIPS assembler attempts to
8534 handle these cases, but it appears to do it
8536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8537 "Relocation overflow");
8541 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8556 const struct mips_opcode
*p
;
8557 int treg
, sreg
, dreg
, shamt
;
8562 for (i
= 0; i
< NUMOPCODES
; ++i
)
8564 p
= &mips_opcodes
[i
];
8565 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8567 printf ("%08lx %s\t", oc
, p
->name
);
8568 treg
= (oc
>> 16) & 0x1f;
8569 sreg
= (oc
>> 21) & 0x1f;
8570 dreg
= (oc
>> 11) & 0x1f;
8571 shamt
= (oc
>> 6) & 0x1f;
8573 for (args
= p
->args
;; ++args
)
8584 printf ("%c", *args
);
8588 assert (treg
== sreg
);
8589 printf ("$%d,$%d", treg
, sreg
);
8594 printf ("$%d", dreg
);
8599 printf ("$%d", treg
);
8603 printf ("0x%x", treg
);
8608 printf ("$%d", sreg
);
8612 printf ("0x%08lx", oc
& 0x1ffffff);
8624 printf ("$%d", shamt
);
8635 printf ("%08lx UNDEFINED\n", oc
);
8646 name
= input_line_pointer
;
8647 c
= get_symbol_end ();
8648 p
= (symbolS
*) symbol_find_or_make (name
);
8649 *input_line_pointer
= c
;
8653 /* Align the current frag to a given power of two. The MIPS assembler
8654 also automatically adjusts any preceding label. */
8657 mips_align (to
, fill
, label
)
8662 mips_emit_delays (false);
8663 frag_align (to
, fill
);
8664 record_alignment (now_seg
, to
);
8667 assert (S_GET_SEGMENT (label
) == now_seg
);
8668 label
->sy_frag
= frag_now
;
8669 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8673 /* Align to a given power of two. .align 0 turns off the automatic
8674 alignment used by the data creating pseudo-ops. */
8681 register long temp_fill
;
8682 long max_alignment
= 15;
8686 o Note that the assembler pulls down any immediately preceeding label
8687 to the aligned address.
8688 o It's not documented but auto alignment is reinstated by
8689 a .align pseudo instruction.
8690 o Note also that after auto alignment is turned off the mips assembler
8691 issues an error on attempt to assemble an improperly aligned data item.
8696 temp
= get_absolute_expression ();
8697 if (temp
> max_alignment
)
8698 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8701 as_warn ("Alignment negative: 0 assumed.");
8704 if (*input_line_pointer
== ',')
8706 input_line_pointer
++;
8707 temp_fill
= get_absolute_expression ();
8714 mips_align (temp
, (int) temp_fill
,
8715 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
8722 demand_empty_rest_of_line ();
8726 mips_flush_pending_output ()
8728 mips_emit_delays (false);
8729 mips_clear_insn_labels ();
8738 /* When generating embedded PIC code, we only use the .text, .lit8,
8739 .sdata and .sbss sections. We change the .data and .rdata
8740 pseudo-ops to use .sdata. */
8741 if (mips_pic
== EMBEDDED_PIC
8742 && (sec
== 'd' || sec
== 'r'))
8745 mips_emit_delays (false);
8755 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8756 demand_empty_rest_of_line ();
8760 if (USE_GLOBAL_POINTER_OPT
)
8762 seg
= subseg_new (RDATA_SECTION_NAME
,
8763 (subsegT
) get_absolute_expression ());
8764 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8766 bfd_set_section_flags (stdoutput
, seg
,
8772 if (strcmp (TARGET_OS
, "elf") != 0)
8773 bfd_set_section_alignment (stdoutput
, seg
, 4);
8775 demand_empty_rest_of_line ();
8779 as_bad ("No read only data section in this object file format");
8780 demand_empty_rest_of_line ();
8786 if (USE_GLOBAL_POINTER_OPT
)
8788 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8789 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8791 bfd_set_section_flags (stdoutput
, seg
,
8792 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8794 if (strcmp (TARGET_OS
, "elf") != 0)
8795 bfd_set_section_alignment (stdoutput
, seg
, 4);
8797 demand_empty_rest_of_line ();
8802 as_bad ("Global pointers not supported; recompile -G 0");
8803 demand_empty_rest_of_line ();
8812 mips_enable_auto_align ()
8823 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8824 mips_emit_delays (false);
8825 if (log_size
> 0 && auto_align
)
8826 mips_align (log_size
, 0, label
);
8827 mips_clear_insn_labels ();
8828 cons (1 << log_size
);
8837 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8839 mips_emit_delays (false);
8843 mips_align (3, 0, label
);
8845 mips_align (2, 0, label
);
8847 mips_clear_insn_labels ();
8852 /* Handle .globl. We need to override it because on Irix 5 you are
8855 where foo is an undefined symbol, to mean that foo should be
8856 considered to be the address of a function. */
8867 name
= input_line_pointer
;
8868 c
= get_symbol_end ();
8869 symbolP
= symbol_find_or_make (name
);
8870 *input_line_pointer
= c
;
8873 /* On Irix 5, every global symbol that is not explicitly labelled as
8874 being a function is apparently labelled as being an object. */
8877 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8882 secname
= input_line_pointer
;
8883 c
= get_symbol_end ();
8884 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8886 as_bad ("%s: no such section", secname
);
8887 *input_line_pointer
= c
;
8889 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8890 flag
= BSF_FUNCTION
;
8893 symbolP
->bsym
->flags
|= flag
;
8895 S_SET_EXTERNAL (symbolP
);
8896 demand_empty_rest_of_line ();
8906 opt
= input_line_pointer
;
8907 c
= get_symbol_end ();
8911 /* FIXME: What does this mean? */
8913 else if (strncmp (opt
, "pic", 3) == 0)
8921 mips_pic
= SVR4_PIC
;
8923 as_bad (".option pic%d not supported", i
);
8925 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8927 if (g_switch_seen
&& g_switch_value
!= 0)
8928 as_warn ("-G may not be used with SVR4 PIC code");
8930 bfd_set_gp_size (stdoutput
, 0);
8934 as_warn ("Unrecognized option \"%s\"", opt
);
8936 *input_line_pointer
= c
;
8937 demand_empty_rest_of_line ();
8944 char *name
= input_line_pointer
, ch
;
8946 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8947 input_line_pointer
++;
8948 ch
= *input_line_pointer
;
8949 *input_line_pointer
= '\0';
8951 if (strcmp (name
, "reorder") == 0)
8955 prev_insn_unreordered
= 1;
8956 prev_prev_insn_unreordered
= 1;
8960 else if (strcmp (name
, "noreorder") == 0)
8962 mips_emit_delays (true);
8964 mips_any_noreorder
= 1;
8966 else if (strcmp (name
, "at") == 0)
8970 else if (strcmp (name
, "noat") == 0)
8974 else if (strcmp (name
, "macro") == 0)
8976 mips_warn_about_macros
= 0;
8978 else if (strcmp (name
, "nomacro") == 0)
8980 if (mips_noreorder
== 0)
8981 as_bad ("`noreorder' must be set before `nomacro'");
8982 mips_warn_about_macros
= 1;
8984 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
8988 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
8992 else if (strcmp (name
, "bopt") == 0)
8996 else if (strcmp (name
, "nobopt") == 0)
9000 else if (strcmp (name
, "mips16") == 0
9001 || strcmp (name
, "MIPS-16") == 0)
9003 else if (strcmp (name
, "nomips16") == 0
9004 || strcmp (name
, "noMIPS-16") == 0)
9006 else if (strncmp (name
, "mips", 4) == 0)
9010 /* Permit the user to change the ISA on the fly. Needless to
9011 say, misuse can cause serious problems. */
9012 isa
= atoi (name
+ 4);
9014 mips_isa
= file_mips_isa
;
9015 else if (isa
< 1 || isa
> 4)
9016 as_bad ("unknown ISA level");
9020 else if (strcmp (name
, "autoextend") == 0)
9021 mips16_autoextend
= 1;
9022 else if (strcmp (name
, "noautoextend") == 0)
9023 mips16_autoextend
= 0;
9026 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9028 *input_line_pointer
= ch
;
9029 demand_empty_rest_of_line ();
9032 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9033 .option pic2. It means to generate SVR4 PIC calls. */
9039 mips_pic
= SVR4_PIC
;
9040 if (USE_GLOBAL_POINTER_OPT
)
9042 if (g_switch_seen
&& g_switch_value
!= 0)
9043 as_warn ("-G may not be used with SVR4 PIC code");
9046 bfd_set_gp_size (stdoutput
, 0);
9047 demand_empty_rest_of_line ();
9050 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9051 PIC code. It sets the $gp register for the function based on the
9052 function address, which is in the register named in the argument.
9053 This uses a relocation against _gp_disp, which is handled specially
9054 by the linker. The result is:
9055 lui $gp,%hi(_gp_disp)
9056 addiu $gp,$gp,%lo(_gp_disp)
9057 addu $gp,$gp,.cpload argument
9058 The .cpload argument is normally $25 == $t9. */
9067 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9068 if (mips_pic
!= SVR4_PIC
)
9074 /* .cpload should be a in .set noreorder section. */
9075 if (mips_noreorder
== 0)
9076 as_warn (".cpload not in noreorder section");
9079 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9080 ex
.X_op_symbol
= NULL
;
9081 ex
.X_add_number
= 0;
9083 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9084 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9086 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9087 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9088 (int) BFD_RELOC_LO16
);
9090 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9091 GP
, GP
, tc_get_register (0));
9093 demand_empty_rest_of_line ();
9096 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9097 offset from $sp. The offset is remembered, and after making a PIC
9098 call $gp is restored from that location. */
9101 s_cprestore (ignore
)
9107 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9108 if (mips_pic
!= SVR4_PIC
)
9114 mips_cprestore_offset
= get_absolute_expression ();
9116 ex
.X_op
= O_constant
;
9117 ex
.X_add_symbol
= NULL
;
9118 ex
.X_op_symbol
= NULL
;
9119 ex
.X_add_number
= mips_cprestore_offset
;
9121 macro_build ((char *) NULL
, &icnt
, &ex
,
9122 mips_isa
< 3 ? "sw" : "sd",
9123 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9125 demand_empty_rest_of_line ();
9128 /* Handle the .gpword pseudo-op. This is used when generating PIC
9129 code. It generates a 32 bit GP relative reloc. */
9139 /* When not generating PIC code, this is treated as .word. */
9140 if (mips_pic
!= SVR4_PIC
)
9146 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9147 mips_emit_delays (true);
9149 mips_align (2, 0, label
);
9150 mips_clear_insn_labels ();
9154 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9156 as_bad ("Unsupported use of .gpword");
9157 ignore_rest_of_line ();
9161 md_number_to_chars (p
, (valueT
) 0, 4);
9162 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9163 BFD_RELOC_MIPS_GPREL32
);
9165 demand_empty_rest_of_line ();
9168 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9169 tables in SVR4 PIC code. */
9178 /* This is ignored when not generating SVR4 PIC code. */
9179 if (mips_pic
!= SVR4_PIC
)
9185 /* Add $gp to the register named as an argument. */
9186 reg
= tc_get_register (0);
9187 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9188 mips_isa
< 3 ? "addu" : "daddu",
9189 "d,v,t", reg
, reg
, GP
);
9191 demand_empty_rest_of_line ();
9194 /* Parse a register string into a number. Called from the ECOFF code
9195 to parse .frame. The argument is non-zero if this is the frame
9196 register, so that we can record it in mips_frame_reg. */
9199 tc_get_register (frame
)
9205 if (*input_line_pointer
++ != '$')
9207 as_warn ("expected `$'");
9210 else if (isdigit ((unsigned char) *input_line_pointer
))
9212 reg
= get_absolute_expression ();
9213 if (reg
< 0 || reg
>= 32)
9215 as_warn ("Bad register number");
9221 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9223 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9225 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9227 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9231 as_warn ("Unrecognized register name");
9234 input_line_pointer
+= 2;
9237 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9242 md_section_align (seg
, addr
)
9246 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9249 /* We don't need to align ELF sections to the full alignment.
9250 However, Irix 5 may prefer that we align them at least to a 16
9251 byte boundary. We don't bother to align the sections if we are
9252 targeted for an embedded system. */
9253 if (strcmp (TARGET_OS
, "elf") == 0)
9259 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9262 /* Utility routine, called from above as well. If called while the
9263 input file is still being read, it's only an approximation. (For
9264 example, a symbol may later become defined which appeared to be
9265 undefined earlier.) */
9268 nopic_need_relax (sym
)
9274 if (USE_GLOBAL_POINTER_OPT
)
9276 const char *symname
;
9279 /* Find out whether this symbol can be referenced off the GP
9280 register. It can be if it is smaller than the -G size or if
9281 it is in the .sdata or .sbss section. Certain symbols can
9282 not be referenced off the GP, although it appears as though
9284 symname
= S_GET_NAME (sym
);
9285 if (symname
!= (const char *) NULL
9286 && (strcmp (symname
, "eprol") == 0
9287 || strcmp (symname
, "etext") == 0
9288 || strcmp (symname
, "_gp") == 0
9289 || strcmp (symname
, "edata") == 0
9290 || strcmp (symname
, "_fbss") == 0
9291 || strcmp (symname
, "_fdata") == 0
9292 || strcmp (symname
, "_ftext") == 0
9293 || strcmp (symname
, "end") == 0
9294 || strcmp (symname
, "_gp_disp") == 0))
9296 else if (! S_IS_DEFINED (sym
)
9298 #ifndef NO_ECOFF_DEBUGGING
9299 || (sym
->ecoff_extern_size
!= 0
9300 && sym
->ecoff_extern_size
<= g_switch_value
)
9302 || (S_GET_VALUE (sym
) != 0
9303 && S_GET_VALUE (sym
) <= g_switch_value
)))
9307 const char *segname
;
9309 segname
= segment_name (S_GET_SEGMENT (sym
));
9310 assert (strcmp (segname
, ".lit8") != 0
9311 && strcmp (segname
, ".lit4") != 0);
9312 change
= (strcmp (segname
, ".sdata") != 0
9313 && strcmp (segname
, ".sbss") != 0);
9318 /* We are not optimizing for the GP register. */
9322 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9323 extended opcode. SEC is the section the frag is in. */
9326 mips16_extended_frag (fragp
, sec
, stretch
)
9332 register const struct mips16_immed_operand
*op
;
9334 int mintiny
, maxtiny
;
9337 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9339 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9342 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9343 op
= mips16_immed_operands
;
9344 while (op
->type
!= type
)
9347 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9352 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9355 maxtiny
= 1 << op
->nbits
;
9360 maxtiny
= (1 << op
->nbits
) - 1;
9365 mintiny
= - (1 << (op
->nbits
- 1));
9366 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9369 /* We can't call S_GET_VALUE here, because we don't want to lock in
9370 a particular frag address. */
9371 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9373 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9374 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9375 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9377 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9378 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9381 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9382 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9383 + fragp
->fr_symbol
->sy_value
.X_add_number
9384 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9385 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9394 /* We won't have the section when we are called from
9395 mips_relax_frag. However, we will always have been called
9396 from md_estimate_size_before_relax first. If this is a
9397 branch to a different section, we mark it as such. If SEC is
9398 NULL, and the frag is not marked, then it must be a branch to
9399 the same section. */
9402 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9410 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9412 /* FIXME: We should support this, and let the linker
9413 catch branches and loads that are out of range. */
9414 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9415 "unsupported PC relative reference to different section");
9421 /* In this case, we know for sure that the symbol fragment is in
9422 the same section. If the fr_address of the symbol fragment
9423 is greater then the address of this fragment we want to add
9424 in STRETCH in order to get a better estimate of the address.
9425 This particularly matters because of the shift bits. */
9427 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9431 /* Adjust stretch for any alignment frag. */
9432 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9435 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9438 stretch
= - ((- stretch
)
9439 & ~ ((1 << (int) f
->fr_offset
) - 1));
9441 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9449 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9451 /* The base address rules are complicated. The base address of
9452 a branch is the following instruction. The base address of a
9453 PC relative load or add is the instruction itself, but if it
9454 is extended add 2, and if it is in a delay slot (in which
9455 case it can not be extended) use the address of the
9456 instruction whose delay slot it is in. */
9457 if (type
== 'p' || type
== 'q')
9460 /* Ignore the low bit in the target, since it will be set
9461 for a text label. */
9465 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9467 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9470 /* If we are currently assuming that this frag should be
9471 extended, then the current address is two bytes higher. */
9472 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9475 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9477 /* Branch offsets have an implicit 0 in the lowest bit. */
9478 if (type
== 'p' || type
== 'q')
9481 /* If any of the shifted bits are set, we must use an extended
9482 opcode. If the address depends on the size of this
9483 instruction, this can lead to a loop, so we arrange to always
9484 use an extended opcode. We only check this when we are in
9485 the main relaxation loop, when SEC is NULL. */
9486 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9489 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9493 /* If we are about to mark a frag as extended because the value
9494 is precisely maxtiny + 1, then there is a chance of an
9495 infinite loop as in the following code:
9500 In this case when the la is extended, foo is 0x3fc bytes
9501 away, so the la can be shrunk, but then foo is 0x400 away, so
9502 the la must be extended. To avoid this loop, we mark the
9503 frag as extended if it was small, and is about to become
9504 extended with a value of maxtiny + 1. */
9505 if (val
== ((maxtiny
+ 1) << op
->shift
)
9506 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9510 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9514 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9515 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9517 if ((val
& ((1 << op
->shift
) - 1)) != 0
9518 || val
< (mintiny
<< op
->shift
)
9519 || val
> (maxtiny
<< op
->shift
))
9525 /* Estimate the size of a frag before relaxing. Unless this is the
9526 mips16, we are not really relaxing here, and the final size is
9527 encoded in the subtype information. For the mips16, we have to
9528 decide whether we are using an extended opcode or not. */
9532 md_estimate_size_before_relax (fragp
, segtype
)
9538 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9540 if (mips16_extended_frag (fragp
, segtype
, 0))
9542 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9547 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9552 if (mips_pic
== NO_PIC
)
9554 change
= nopic_need_relax (fragp
->fr_symbol
);
9556 else if (mips_pic
== SVR4_PIC
)
9558 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9560 /* This must duplicate the test in adjust_reloc_syms. */
9561 change
= (symsec
!= &bfd_und_section
9562 && symsec
!= &bfd_abs_section
9563 && ! bfd_is_com_section (symsec
));
9570 /* Record the offset to the first reloc in the fr_opcode field.
9571 This lets md_convert_frag and tc_gen_reloc know that the code
9572 must be expanded. */
9573 fragp
->fr_opcode
= (fragp
->fr_literal
9575 - RELAX_OLD (fragp
->fr_subtype
)
9576 + RELAX_RELOC1 (fragp
->fr_subtype
));
9577 /* FIXME: This really needs as_warn_where. */
9578 if (RELAX_WARN (fragp
->fr_subtype
))
9579 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9585 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9588 /* This is called to see whether a reloc against a defined symbol
9589 should be converted into a reloc against a section. Don't adjust
9590 MIPS16 jump relocations, so we don't have to worry about the format
9591 of the offset in the .o file. Don't adjust relocations against
9592 mips16 symbols, so that the linker can find them if it needs to set
9596 mips_fix_adjustable (fixp
)
9599 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
9601 if (fixp
->fx_addsy
== NULL
)
9604 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9605 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
)
9611 /* Translate internal representation of relocation info to BFD target
9615 tc_gen_reloc (section
, fixp
)
9619 static arelent
*retval
[4];
9621 bfd_reloc_code_real_type code
;
9623 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9626 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9627 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9629 if (mips_pic
== EMBEDDED_PIC
9630 && SWITCH_TABLE (fixp
))
9632 /* For a switch table entry we use a special reloc. The addend
9633 is actually the difference between the reloc address and the
9635 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9636 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9637 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9638 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9640 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9642 /* We use a special addend for an internal RELLO reloc. */
9643 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9644 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9646 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9648 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9650 assert (fixp
->fx_next
!= NULL
9651 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9652 /* We use a special addend for an internal RELHI reloc. The
9653 reloc is relative to the RELLO; adjust the addend
9655 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9656 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9657 + fixp
->fx_next
->fx_where
9658 - S_GET_VALUE (fixp
->fx_subsy
));
9660 reloc
->addend
= (fixp
->fx_addnumber
9661 + fixp
->fx_next
->fx_frag
->fr_address
9662 + fixp
->fx_next
->fx_where
);
9664 else if (fixp
->fx_pcrel
== 0)
9665 reloc
->addend
= fixp
->fx_addnumber
;
9668 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9669 /* A gruesome hack which is a result of the gruesome gas reloc
9671 reloc
->addend
= reloc
->address
;
9673 reloc
->addend
= -reloc
->address
;
9676 /* If this is a variant frag, we may need to adjust the existing
9677 reloc and generate a new one. */
9678 if (fixp
->fx_frag
->fr_opcode
!= NULL
9679 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9680 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9681 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9682 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9683 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9684 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9685 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9689 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9691 /* If this is not the last reloc in this frag, then we have two
9692 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9693 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9694 the second one handle all of them. */
9695 if (fixp
->fx_next
!= NULL
9696 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9698 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9699 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9700 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9701 && (fixp
->fx_next
->fx_r_type
9702 == BFD_RELOC_MIPS_GOT_LO16
))
9703 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9704 && (fixp
->fx_next
->fx_r_type
9705 == BFD_RELOC_MIPS_CALL_LO16
)));
9710 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9711 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9712 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9714 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9715 reloc2
->address
= (reloc
->address
9716 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9717 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9718 reloc2
->addend
= fixp
->fx_addnumber
;
9719 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9720 assert (reloc2
->howto
!= NULL
);
9722 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9726 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9729 reloc3
->address
+= 4;
9732 if (mips_pic
== NO_PIC
)
9734 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9735 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9737 else if (mips_pic
== SVR4_PIC
)
9739 switch (fixp
->fx_r_type
)
9743 case BFD_RELOC_MIPS_GOT16
:
9745 case BFD_RELOC_MIPS_CALL16
:
9746 case BFD_RELOC_MIPS_GOT_LO16
:
9747 case BFD_RELOC_MIPS_CALL_LO16
:
9748 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9756 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9757 fixup_segment converted a non-PC relative reloc into a PC
9758 relative reloc. In such a case, we need to convert the reloc
9760 code
= fixp
->fx_r_type
;
9766 code
= BFD_RELOC_8_PCREL
;
9769 code
= BFD_RELOC_16_PCREL
;
9772 code
= BFD_RELOC_32_PCREL
;
9775 code
= BFD_RELOC_64_PCREL
;
9777 case BFD_RELOC_8_PCREL
:
9778 case BFD_RELOC_16_PCREL
:
9779 case BFD_RELOC_32_PCREL
:
9780 case BFD_RELOC_64_PCREL
:
9781 case BFD_RELOC_16_PCREL_S2
:
9782 case BFD_RELOC_PCREL_HI16_S
:
9783 case BFD_RELOC_PCREL_LO16
:
9786 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9787 "Cannot make %s relocation PC relative",
9788 bfd_get_reloc_code_name (code
));
9792 /* To support a PC relative reloc when generating embedded PIC code
9793 for ECOFF, we use a Cygnus extension. We check for that here to
9794 make sure that we don't let such a reloc escape normally. */
9795 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9796 && code
== BFD_RELOC_16_PCREL_S2
9797 && mips_pic
!= EMBEDDED_PIC
)
9798 reloc
->howto
= NULL
;
9800 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9802 if (reloc
->howto
== NULL
)
9804 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9805 "Can not represent %s relocation in this object file format",
9806 bfd_get_reloc_code_name (code
));
9813 /* Relax a machine dependent frag. This returns the amount by which
9814 the current size of the frag should change. */
9817 mips_relax_frag (fragp
, stretch
)
9821 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9824 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9826 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9828 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9833 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9835 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9842 /* Convert a machine dependent frag. */
9845 md_convert_frag (abfd
, asec
, fragp
)
9853 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9856 register const struct mips16_immed_operand
*op
;
9862 unsigned short extend
;
9864 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9865 op
= mips16_immed_operands
;
9866 while (op
->type
!= type
)
9869 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9880 resolve_symbol_value (fragp
->fr_symbol
);
9881 val
= S_GET_VALUE (fragp
->fr_symbol
);
9886 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9888 /* The rules for the base address of a PC relative reloc are
9889 complicated; see mips16_extended_frag. */
9890 if (type
== 'p' || type
== 'q')
9893 /* Ignore the low bit in the target, since it will be
9894 set for a text label. */
9898 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9900 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9905 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9908 /* Make sure the section winds up with the alignment we have
9911 record_alignment (asec
, op
->shift
);
9914 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9916 if (target_big_endian
)
9917 insn
= bfd_getb16 (buf
);
9919 insn
= bfd_getl16 (buf
);
9921 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
9922 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
9923 small
, ext
, &insn
, &use_extend
, &extend
);
9927 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9932 md_number_to_chars (buf
, insn
, 2);
9938 if (fragp
->fr_opcode
== NULL
)
9941 old
= RELAX_OLD (fragp
->fr_subtype
);
9942 new = RELAX_NEW (fragp
->fr_subtype
);
9943 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9946 memcpy (fixptr
- old
, fixptr
, new);
9948 fragp
->fr_fix
+= new - old
;
9954 /* This function is called after the relocs have been generated.
9955 We've been storing mips16 text labels as odd. Here we convert them
9956 back to even for the convenience of the debugger. */
9959 mips_frob_file_after_relocs ()
9962 unsigned int count
, i
;
9964 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9967 syms
= bfd_get_outsymbols (stdoutput
);
9968 count
= bfd_get_symcount (stdoutput
);
9969 for (i
= 0; i
< count
; i
++, syms
++)
9971 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
9972 && ((*syms
)->value
& 1) != 0)
9974 (*syms
)->value
&= ~1;
9975 /* If the symbol has an odd size, it was probably computed
9976 incorrectly, so adjust that as well. */
9977 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
9978 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
9985 /* This function is called whenever a label is defined. It is used
9986 when handling branch delays; if a branch has a label, we assume we
9990 mips_define_label (sym
)
9993 struct insn_label_list
*l
;
9995 if (free_insn_labels
== NULL
)
9996 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
9999 l
= free_insn_labels
;
10000 free_insn_labels
= l
->next
;
10004 l
->next
= insn_labels
;
10008 /* Decide whether a label is local. This is called by LOCAL_LABEL.
10009 In order to work with gcc when using mips-tfile, we must keep all
10010 local labels. However, in other cases, we want to discard them,
10011 since they are useless. */
10014 mips_local_label (name
)
10017 #ifndef NO_ECOFF_DEBUGGING
10018 if (ECOFF_DEBUGGING
10020 && ! ecoff_debugging_seen
)
10022 /* We were called with -g, but we didn't see any debugging
10023 information. That may mean that gcc is smuggling debugging
10024 information through to mips-tfile, in which case we must
10025 generate all local labels. */
10030 /* Here it's OK to discard local labels. */
10032 return name
[0] == '$';
10035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10037 /* Some special processing for a MIPS ELF file. */
10040 mips_elf_final_processing ()
10042 /* Write out the register information. */
10047 s
.ri_gprmask
= mips_gprmask
;
10048 s
.ri_cprmask
[0] = mips_cprmask
[0];
10049 s
.ri_cprmask
[1] = mips_cprmask
[1];
10050 s
.ri_cprmask
[2] = mips_cprmask
[2];
10051 s
.ri_cprmask
[3] = mips_cprmask
[3];
10052 /* The gp_value field is set by the MIPS ELF backend. */
10054 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10055 ((Elf32_External_RegInfo
*)
10056 mips_regmask_frag
));
10060 Elf64_Internal_RegInfo s
;
10062 s
.ri_gprmask
= mips_gprmask
;
10064 s
.ri_cprmask
[0] = mips_cprmask
[0];
10065 s
.ri_cprmask
[1] = mips_cprmask
[1];
10066 s
.ri_cprmask
[2] = mips_cprmask
[2];
10067 s
.ri_cprmask
[3] = mips_cprmask
[3];
10068 /* The gp_value field is set by the MIPS ELF backend. */
10070 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10071 ((Elf64_External_RegInfo
*)
10072 mips_regmask_frag
));
10075 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10076 sort of BFD interface for this. */
10077 if (mips_any_noreorder
)
10078 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10079 if (mips_pic
!= NO_PIC
)
10080 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10083 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10085 /* These functions should really be defined by the object file format,
10086 since they are related to debugging information. However, this
10087 code has to work for the a.out format, which does not define them,
10088 so we provide simple versions here. These don't actually generate
10089 any debugging information, but they do simple checking and someday
10090 somebody may make them useful. */
10094 struct loc
*loc_next
;
10095 unsigned long loc_fileno
;
10096 unsigned long loc_lineno
;
10097 unsigned long loc_offset
;
10098 unsigned short loc_delta
;
10099 unsigned short loc_count
;
10106 typedef struct proc
10108 struct proc
*proc_next
;
10109 struct symbol
*proc_isym
;
10110 struct symbol
*proc_end
;
10111 unsigned long proc_reg_mask
;
10112 unsigned long proc_reg_offset
;
10113 unsigned long proc_fpreg_mask
;
10114 unsigned long proc_fpreg_offset
;
10115 unsigned long proc_frameoffset
;
10116 unsigned long proc_framereg
;
10117 unsigned long proc_pcreg
;
10119 struct file
*proc_file
;
10124 typedef struct file
10126 struct file
*file_next
;
10127 unsigned long file_fileno
;
10128 struct symbol
*file_symbol
;
10129 struct symbol
*file_end
;
10130 struct proc
*file_proc
;
10135 static struct obstack proc_frags
;
10136 static procS
*proc_lastP
;
10137 static procS
*proc_rootP
;
10138 static int numprocs
;
10143 obstack_begin (&proc_frags
, 0x2000);
10149 /* check for premature end, nesting errors, etc */
10150 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10151 as_warn ("missing `.end' at end of assembly");
10160 if (*input_line_pointer
== '-')
10162 ++input_line_pointer
;
10165 if (!isdigit (*input_line_pointer
))
10166 as_bad ("Expected simple number.");
10167 if (input_line_pointer
[0] == '0')
10169 if (input_line_pointer
[1] == 'x')
10171 input_line_pointer
+= 2;
10172 while (isxdigit (*input_line_pointer
))
10175 val
|= hex_value (*input_line_pointer
++);
10177 return negative
? -val
: val
;
10181 ++input_line_pointer
;
10182 while (isdigit (*input_line_pointer
))
10185 val
|= *input_line_pointer
++ - '0';
10187 return negative
? -val
: val
;
10190 if (!isdigit (*input_line_pointer
))
10192 printf (" *input_line_pointer == '%c' 0x%02x\n",
10193 *input_line_pointer
, *input_line_pointer
);
10194 as_warn ("Invalid number");
10197 while (isdigit (*input_line_pointer
))
10200 val
+= *input_line_pointer
++ - '0';
10202 return negative
? -val
: val
;
10205 /* The .file directive; just like the usual .file directive, but there
10206 is an initial number which is the ECOFF file index. */
10214 line
= get_number ();
10219 /* The .end directive. */
10227 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10230 demand_empty_rest_of_line ();
10234 if (now_seg
!= text_section
)
10235 as_warn (".end not in text section");
10238 as_warn (".end and no .ent seen yet.");
10244 assert (S_GET_NAME (p
));
10245 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10246 as_warn (".end symbol does not match .ent symbol.");
10249 proc_lastP
->proc_end
= (symbolS
*) 1;
10252 /* The .aent and .ent directives. */
10262 symbolP
= get_symbol ();
10263 if (*input_line_pointer
== ',')
10264 input_line_pointer
++;
10265 SKIP_WHITESPACE ();
10266 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10267 number
= get_number ();
10268 if (now_seg
!= text_section
)
10269 as_warn (".ent or .aent not in text section.");
10271 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10272 as_warn ("missing `.end'");
10276 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10277 procP
->proc_isym
= symbolP
;
10278 procP
->proc_reg_mask
= 0;
10279 procP
->proc_reg_offset
= 0;
10280 procP
->proc_fpreg_mask
= 0;
10281 procP
->proc_fpreg_offset
= 0;
10282 procP
->proc_frameoffset
= 0;
10283 procP
->proc_framereg
= 0;
10284 procP
->proc_pcreg
= 0;
10285 procP
->proc_end
= NULL
;
10286 procP
->proc_next
= NULL
;
10288 proc_lastP
->proc_next
= procP
;
10290 proc_rootP
= procP
;
10291 proc_lastP
= procP
;
10294 demand_empty_rest_of_line ();
10297 /* The .frame directive. */
10310 frame_reg
= tc_get_register (1);
10311 if (*input_line_pointer
== ',')
10312 input_line_pointer
++;
10313 frame_off
= get_absolute_expression ();
10314 if (*input_line_pointer
== ',')
10315 input_line_pointer
++;
10316 pcreg
= tc_get_register (0);
10318 /* bob third eye */
10319 assert (proc_rootP
);
10320 proc_rootP
->proc_framereg
= frame_reg
;
10321 proc_rootP
->proc_frameoffset
= frame_off
;
10322 proc_rootP
->proc_pcreg
= pcreg
;
10323 /* bob macho .frame */
10325 /* We don't have to write out a frame stab for unoptimized code. */
10326 if (!(frame_reg
== FP
&& frame_off
== 0))
10329 as_warn ("No .ent for .frame to use.");
10330 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10331 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10332 S_SET_TYPE (symP
, N_RMASK
);
10333 S_SET_OTHER (symP
, 0);
10334 S_SET_DESC (symP
, 0);
10335 symP
->sy_forward
= proc_lastP
->proc_isym
;
10336 /* bob perhaps I should have used pseudo set */
10338 demand_empty_rest_of_line ();
10342 /* The .fmask and .mask directives. */
10349 char str
[100], *strP
;
10355 mask
= get_number ();
10356 if (*input_line_pointer
== ',')
10357 input_line_pointer
++;
10358 off
= get_absolute_expression ();
10360 /* bob only for coff */
10361 assert (proc_rootP
);
10362 if (reg_type
== 'F')
10364 proc_rootP
->proc_fpreg_mask
= mask
;
10365 proc_rootP
->proc_fpreg_offset
= off
;
10369 proc_rootP
->proc_reg_mask
= mask
;
10370 proc_rootP
->proc_reg_offset
= off
;
10373 /* bob macho .mask + .fmask */
10375 /* We don't have to write out a mask stab if no saved regs. */
10379 as_warn ("No .ent for .mask to use.");
10381 for (i
= 0; i
< 32; i
++)
10385 sprintf (strP
, "%c%d,", reg_type
, i
);
10386 strP
+= strlen (strP
);
10390 sprintf (strP
, ";%d,", off
);
10391 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10392 S_SET_TYPE (symP
, N_RMASK
);
10393 S_SET_OTHER (symP
, 0);
10394 S_SET_DESC (symP
, 0);
10395 symP
->sy_forward
= proc_lastP
->proc_isym
;
10396 /* bob perhaps I should have used pseudo set */
10401 /* The .loc directive. */
10412 assert (now_seg
== text_section
);
10414 lineno
= get_number ();
10415 addroff
= frag_now_fix ();
10417 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10418 S_SET_TYPE (symbolP
, N_SLINE
);
10419 S_SET_OTHER (symbolP
, 0);
10420 S_SET_DESC (symbolP
, lineno
);
10421 symbolP
->sy_segment
= now_seg
;