1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2015 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether the branch is
1155 unconditional, whether it is compact, whether it stores the link
1156 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1157 branches to a sequence of instructions is enabled, and whether the
1158 displacement of a branch is too large to fit as an immediate argument
1159 of a 16-bit and a 32-bit branch, respectively. */
1160 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1161 relax32, toofar16, toofar32) \
1164 | (((at) & 0x1f) << 8) \
1165 | ((uncond) ? 0x2000 : 0) \
1166 | ((compact) ? 0x4000 : 0) \
1167 | ((link) ? 0x8000 : 0) \
1168 | ((relax32) ? 0x10000 : 0) \
1169 | ((toofar16) ? 0x20000 : 0) \
1170 | ((toofar32) ? 0x40000 : 0))
1171 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1172 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1173 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1174 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1175 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1176 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1177 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1179 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1180 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1181 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1182 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1186 /* Sign-extend 16-bit value X. */
1187 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1189 /* Is the given value a sign-extended 32-bit value? */
1190 #define IS_SEXT_32BIT_NUM(x) \
1191 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1192 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1194 /* Is the given value a sign-extended 16-bit value? */
1195 #define IS_SEXT_16BIT_NUM(x) \
1196 (((x) &~ (offsetT) 0x7fff) == 0 \
1197 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1199 /* Is the given value a sign-extended 12-bit value? */
1200 #define IS_SEXT_12BIT_NUM(x) \
1201 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1203 /* Is the given value a sign-extended 9-bit value? */
1204 #define IS_SEXT_9BIT_NUM(x) \
1205 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1207 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1208 #define IS_ZEXT_32BIT_NUM(x) \
1209 (((x) &~ (offsetT) 0xffffffff) == 0 \
1210 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1212 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1214 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1215 (((STRUCT) >> (SHIFT)) & (MASK))
1217 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1218 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1220 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1221 : EXTRACT_BITS ((INSN).insn_opcode, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1223 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1224 EXTRACT_BITS ((INSN).insn_opcode, \
1225 MIPS16OP_MASK_##FIELD, \
1226 MIPS16OP_SH_##FIELD)
1228 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1229 #define MIPS16_EXTEND (0xf000U << 16)
1231 /* Whether or not we are emitting a branch-likely macro. */
1232 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1234 /* Global variables used when generating relaxable macros. See the
1235 comment above RELAX_ENCODE for more details about how relaxation
1238 /* 0 if we're not emitting a relaxable macro.
1239 1 if we're emitting the first of the two relaxation alternatives.
1240 2 if we're emitting the second alternative. */
1243 /* The first relaxable fixup in the current frag. (In other words,
1244 the first fixup that refers to relaxable code.) */
1247 /* sizes[0] says how many bytes of the first alternative are stored in
1248 the current frag. Likewise sizes[1] for the second alternative. */
1249 unsigned int sizes
[2];
1251 /* The symbol on which the choice of sequence depends. */
1255 /* Global variables used to decide whether a macro needs a warning. */
1257 /* True if the macro is in a branch delay slot. */
1258 bfd_boolean delay_slot_p
;
1260 /* Set to the length in bytes required if the macro is in a delay slot
1261 that requires a specific length of instruction, otherwise zero. */
1262 unsigned int delay_slot_length
;
1264 /* For relaxable macros, sizes[0] is the length of the first alternative
1265 in bytes and sizes[1] is the length of the second alternative.
1266 For non-relaxable macros, both elements give the length of the
1268 unsigned int sizes
[2];
1270 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1271 instruction of the first alternative in bytes and first_insn_sizes[1]
1272 is the length of the first instruction of the second alternative.
1273 For non-relaxable macros, both elements give the length of the first
1274 instruction in bytes.
1276 Set to zero if we haven't yet seen the first instruction. */
1277 unsigned int first_insn_sizes
[2];
1279 /* For relaxable macros, insns[0] is the number of instructions for the
1280 first alternative and insns[1] is the number of instructions for the
1283 For non-relaxable macros, both elements give the number of
1284 instructions for the macro. */
1285 unsigned int insns
[2];
1287 /* The first variant frag for this macro. */
1289 } mips_macro_warning
;
1291 /* Prototypes for static functions. */
1293 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1295 static void append_insn
1296 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1297 bfd_boolean expansionp
);
1298 static void mips_no_prev_insn (void);
1299 static void macro_build (expressionS
*, const char *, const char *, ...);
1300 static void mips16_macro_build
1301 (expressionS
*, const char *, const char *, va_list *);
1302 static void load_register (int, expressionS
*, int);
1303 static void macro_start (void);
1304 static void macro_end (void);
1305 static void macro (struct mips_cl_insn
*ip
, char *str
);
1306 static void mips16_macro (struct mips_cl_insn
* ip
);
1307 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1308 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1309 static void mips16_immed
1310 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1311 unsigned int, unsigned long *);
1312 static size_t my_getSmallExpression
1313 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1314 static void my_getExpression (expressionS
*, char *);
1315 static void s_align (int);
1316 static void s_change_sec (int);
1317 static void s_change_section (int);
1318 static void s_cons (int);
1319 static void s_float_cons (int);
1320 static void s_mips_globl (int);
1321 static void s_option (int);
1322 static void s_mipsset (int);
1323 static void s_abicalls (int);
1324 static void s_cpload (int);
1325 static void s_cpsetup (int);
1326 static void s_cplocal (int);
1327 static void s_cprestore (int);
1328 static void s_cpreturn (int);
1329 static void s_dtprelword (int);
1330 static void s_dtpreldword (int);
1331 static void s_tprelword (int);
1332 static void s_tpreldword (int);
1333 static void s_gpvalue (int);
1334 static void s_gpword (int);
1335 static void s_gpdword (int);
1336 static void s_ehword (int);
1337 static void s_cpadd (int);
1338 static void s_insn (int);
1339 static void s_nan (int);
1340 static void s_module (int);
1341 static void s_mips_ent (int);
1342 static void s_mips_end (int);
1343 static void s_mips_frame (int);
1344 static void s_mips_mask (int reg_type
);
1345 static void s_mips_stab (int);
1346 static void s_mips_weakext (int);
1347 static void s_mips_file (int);
1348 static void s_mips_loc (int);
1349 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1350 static int relaxed_branch_length (fragS
*, asection
*, int);
1351 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1352 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1353 static void file_mips_check_options (void);
1355 /* Table and functions used to map between CPU/ISA names, and
1356 ISA levels, and CPU numbers. */
1358 struct mips_cpu_info
1360 const char *name
; /* CPU or ISA name. */
1361 int flags
; /* MIPS_CPU_* flags. */
1362 int ase
; /* Set of ASEs implemented by the CPU. */
1363 int isa
; /* ISA level. */
1364 int cpu
; /* CPU number (default CPU if ISA). */
1367 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1369 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1370 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1371 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1373 /* Command-line options. */
1374 const char *md_shortopts
= "O::g::G:";
1378 OPTION_MARCH
= OPTION_MD_BASE
,
1410 OPTION_NO_SMARTMIPS
,
1418 OPTION_NO_MICROMIPS
,
1421 OPTION_COMPAT_ARCH_BASE
,
1430 OPTION_M7000_HILO_FIX
,
1431 OPTION_MNO_7000_HILO_FIX
,
1435 OPTION_NO_FIX_RM7000
,
1436 OPTION_FIX_LOONGSON2F_JUMP
,
1437 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1438 OPTION_FIX_LOONGSON2F_NOP
,
1439 OPTION_NO_FIX_LOONGSON2F_NOP
,
1441 OPTION_NO_FIX_VR4120
,
1443 OPTION_NO_FIX_VR4130
,
1444 OPTION_FIX_CN63XXP1
,
1445 OPTION_NO_FIX_CN63XXP1
,
1452 OPTION_CONSTRUCT_FLOATS
,
1453 OPTION_NO_CONSTRUCT_FLOATS
,
1457 OPTION_RELAX_BRANCH
,
1458 OPTION_NO_RELAX_BRANCH
,
1467 OPTION_SINGLE_FLOAT
,
1468 OPTION_DOUBLE_FLOAT
,
1481 OPTION_MVXWORKS_PIC
,
1484 OPTION_NO_ODD_SPREG
,
1488 struct option md_longopts
[] =
1490 /* Options which specify architecture. */
1491 {"march", required_argument
, NULL
, OPTION_MARCH
},
1492 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1493 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1494 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1495 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1496 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1497 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1498 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1499 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1500 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1501 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1502 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1503 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1504 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1505 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1506 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1507 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1508 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1510 /* Options which specify Application Specific Extensions (ASEs). */
1511 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1512 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1513 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1514 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1515 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1516 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1517 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1518 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1519 {"mmt", no_argument
, NULL
, OPTION_MT
},
1520 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1521 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1522 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1523 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1524 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1525 {"meva", no_argument
, NULL
, OPTION_EVA
},
1526 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1527 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1528 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1529 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1530 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1531 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1532 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1533 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1534 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1535 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1536 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1538 /* Old-style architecture options. Don't add more of these. */
1539 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1540 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1541 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1542 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1543 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1544 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1545 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1546 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1548 /* Options which enable bug fixes. */
1549 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1550 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1551 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1552 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1553 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1554 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1555 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1556 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1557 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1558 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1559 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1560 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1561 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1562 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1563 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1564 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1565 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1567 /* Miscellaneous options. */
1568 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1569 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1570 {"break", no_argument
, NULL
, OPTION_BREAK
},
1571 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1572 {"EB", no_argument
, NULL
, OPTION_EB
},
1573 {"EL", no_argument
, NULL
, OPTION_EL
},
1574 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1575 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1576 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1577 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1578 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1579 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1580 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1581 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1582 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1583 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1584 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1585 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1586 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1587 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1588 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1589 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1590 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1591 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1592 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1593 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1594 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1596 /* Strictly speaking this next option is ELF specific,
1597 but we allow it for other ports as well in order to
1598 make testing easier. */
1599 {"32", no_argument
, NULL
, OPTION_32
},
1601 /* ELF-specific options. */
1602 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1603 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1604 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1605 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1606 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1607 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1608 {"n32", no_argument
, NULL
, OPTION_N32
},
1609 {"64", no_argument
, NULL
, OPTION_64
},
1610 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1611 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1612 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1613 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1614 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1615 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1617 {NULL
, no_argument
, NULL
, 0}
1619 size_t md_longopts_size
= sizeof (md_longopts
);
1621 /* Information about either an Application Specific Extension or an
1622 optional architecture feature that, for simplicity, we treat in the
1623 same way as an ASE. */
1626 /* The name of the ASE, used in both the command-line and .set options. */
1629 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1630 and 64-bit architectures, the flags here refer to the subset that
1631 is available on both. */
1634 /* The ASE_* flag used for instructions that are available on 64-bit
1635 architectures but that are not included in FLAGS. */
1636 unsigned int flags64
;
1638 /* The command-line options that turn the ASE on and off. */
1642 /* The minimum required architecture revisions for MIPS32, MIPS64,
1643 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1646 int micromips32_rev
;
1647 int micromips64_rev
;
1649 /* The architecture where the ASE was removed or -1 if the extension has not
1654 /* A table of all supported ASEs. */
1655 static const struct mips_ase mips_ases
[] = {
1656 { "dsp", ASE_DSP
, ASE_DSP64
,
1657 OPTION_DSP
, OPTION_NO_DSP
,
1661 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1662 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1666 { "eva", ASE_EVA
, 0,
1667 OPTION_EVA
, OPTION_NO_EVA
,
1671 { "mcu", ASE_MCU
, 0,
1672 OPTION_MCU
, OPTION_NO_MCU
,
1676 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1677 { "mdmx", ASE_MDMX
, 0,
1678 OPTION_MDMX
, OPTION_NO_MDMX
,
1682 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1683 { "mips3d", ASE_MIPS3D
, 0,
1684 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1689 OPTION_MT
, OPTION_NO_MT
,
1693 { "smartmips", ASE_SMARTMIPS
, 0,
1694 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1698 { "virt", ASE_VIRT
, ASE_VIRT64
,
1699 OPTION_VIRT
, OPTION_NO_VIRT
,
1703 { "msa", ASE_MSA
, ASE_MSA64
,
1704 OPTION_MSA
, OPTION_NO_MSA
,
1708 { "xpa", ASE_XPA
, 0,
1709 OPTION_XPA
, OPTION_NO_XPA
,
1714 /* The set of ASEs that require -mfp64. */
1715 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1717 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1718 static const unsigned int mips_ase_groups
[] = {
1724 The following pseudo-ops from the Kane and Heinrich MIPS book
1725 should be defined here, but are currently unsupported: .alias,
1726 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1728 The following pseudo-ops from the Kane and Heinrich MIPS book are
1729 specific to the type of debugging information being generated, and
1730 should be defined by the object format: .aent, .begin, .bend,
1731 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1734 The following pseudo-ops from the Kane and Heinrich MIPS book are
1735 not MIPS CPU specific, but are also not specific to the object file
1736 format. This file is probably the best place to define them, but
1737 they are not currently supported: .asm0, .endr, .lab, .struct. */
1739 static const pseudo_typeS mips_pseudo_table
[] =
1741 /* MIPS specific pseudo-ops. */
1742 {"option", s_option
, 0},
1743 {"set", s_mipsset
, 0},
1744 {"rdata", s_change_sec
, 'r'},
1745 {"sdata", s_change_sec
, 's'},
1746 {"livereg", s_ignore
, 0},
1747 {"abicalls", s_abicalls
, 0},
1748 {"cpload", s_cpload
, 0},
1749 {"cpsetup", s_cpsetup
, 0},
1750 {"cplocal", s_cplocal
, 0},
1751 {"cprestore", s_cprestore
, 0},
1752 {"cpreturn", s_cpreturn
, 0},
1753 {"dtprelword", s_dtprelword
, 0},
1754 {"dtpreldword", s_dtpreldword
, 0},
1755 {"tprelword", s_tprelword
, 0},
1756 {"tpreldword", s_tpreldword
, 0},
1757 {"gpvalue", s_gpvalue
, 0},
1758 {"gpword", s_gpword
, 0},
1759 {"gpdword", s_gpdword
, 0},
1760 {"ehword", s_ehword
, 0},
1761 {"cpadd", s_cpadd
, 0},
1762 {"insn", s_insn
, 0},
1764 {"module", s_module
, 0},
1766 /* Relatively generic pseudo-ops that happen to be used on MIPS
1768 {"asciiz", stringer
, 8 + 1},
1769 {"bss", s_change_sec
, 'b'},
1771 {"half", s_cons
, 1},
1772 {"dword", s_cons
, 3},
1773 {"weakext", s_mips_weakext
, 0},
1774 {"origin", s_org
, 0},
1775 {"repeat", s_rept
, 0},
1777 /* For MIPS this is non-standard, but we define it for consistency. */
1778 {"sbss", s_change_sec
, 'B'},
1780 /* These pseudo-ops are defined in read.c, but must be overridden
1781 here for one reason or another. */
1782 {"align", s_align
, 0},
1783 {"byte", s_cons
, 0},
1784 {"data", s_change_sec
, 'd'},
1785 {"double", s_float_cons
, 'd'},
1786 {"float", s_float_cons
, 'f'},
1787 {"globl", s_mips_globl
, 0},
1788 {"global", s_mips_globl
, 0},
1789 {"hword", s_cons
, 1},
1791 {"long", s_cons
, 2},
1792 {"octa", s_cons
, 4},
1793 {"quad", s_cons
, 3},
1794 {"section", s_change_section
, 0},
1795 {"short", s_cons
, 1},
1796 {"single", s_float_cons
, 'f'},
1797 {"stabd", s_mips_stab
, 'd'},
1798 {"stabn", s_mips_stab
, 'n'},
1799 {"stabs", s_mips_stab
, 's'},
1800 {"text", s_change_sec
, 't'},
1801 {"word", s_cons
, 2},
1803 { "extern", ecoff_directive_extern
, 0},
1808 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1810 /* These pseudo-ops should be defined by the object file format.
1811 However, a.out doesn't support them, so we have versions here. */
1812 {"aent", s_mips_ent
, 1},
1813 {"bgnb", s_ignore
, 0},
1814 {"end", s_mips_end
, 0},
1815 {"endb", s_ignore
, 0},
1816 {"ent", s_mips_ent
, 0},
1817 {"file", s_mips_file
, 0},
1818 {"fmask", s_mips_mask
, 'F'},
1819 {"frame", s_mips_frame
, 0},
1820 {"loc", s_mips_loc
, 0},
1821 {"mask", s_mips_mask
, 'R'},
1822 {"verstamp", s_ignore
, 0},
1826 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1827 purpose of the `.dc.a' internal pseudo-op. */
1830 mips_address_bytes (void)
1832 file_mips_check_options ();
1833 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1836 extern void pop_insert (const pseudo_typeS
*);
1839 mips_pop_insert (void)
1841 pop_insert (mips_pseudo_table
);
1842 if (! ECOFF_DEBUGGING
)
1843 pop_insert (mips_nonecoff_pseudo_table
);
1846 /* Symbols labelling the current insn. */
1848 struct insn_label_list
1850 struct insn_label_list
*next
;
1854 static struct insn_label_list
*free_insn_labels
;
1855 #define label_list tc_segment_info_data.labels
1857 static void mips_clear_insn_labels (void);
1858 static void mips_mark_labels (void);
1859 static void mips_compressed_mark_labels (void);
1862 mips_clear_insn_labels (void)
1864 struct insn_label_list
**pl
;
1865 segment_info_type
*si
;
1869 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1872 si
= seg_info (now_seg
);
1873 *pl
= si
->label_list
;
1874 si
->label_list
= NULL
;
1878 /* Mark instruction labels in MIPS16/microMIPS mode. */
1881 mips_mark_labels (void)
1883 if (HAVE_CODE_COMPRESSION
)
1884 mips_compressed_mark_labels ();
1887 static char *expr_end
;
1889 /* An expression in a macro instruction. This is set by mips_ip and
1890 mips16_ip and when populated is always an O_constant. */
1892 static expressionS imm_expr
;
1894 /* The relocatable field in an instruction and the relocs associated
1895 with it. These variables are used for instructions like LUI and
1896 JAL as well as true offsets. They are also used for address
1897 operands in macros. */
1899 static expressionS offset_expr
;
1900 static bfd_reloc_code_real_type offset_reloc
[3]
1901 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1903 /* This is set to the resulting size of the instruction to be produced
1904 by mips16_ip if an explicit extension is used or by mips_ip if an
1905 explicit size is supplied. */
1907 static unsigned int forced_insn_length
;
1909 /* True if we are assembling an instruction. All dot symbols defined during
1910 this time should be treated as code labels. */
1912 static bfd_boolean mips_assembling_insn
;
1914 /* The pdr segment for per procedure frame/regmask info. Not used for
1917 static segT pdr_seg
;
1919 /* The default target format to use. */
1921 #if defined (TE_FreeBSD)
1922 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1923 #elif defined (TE_TMIPS)
1924 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1926 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1930 mips_target_format (void)
1932 switch (OUTPUT_FLAVOR
)
1934 case bfd_target_elf_flavour
:
1936 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1937 return (target_big_endian
1938 ? "elf32-bigmips-vxworks"
1939 : "elf32-littlemips-vxworks");
1941 return (target_big_endian
1942 ? (HAVE_64BIT_OBJECTS
1943 ? ELF_TARGET ("elf64-", "big")
1945 ? ELF_TARGET ("elf32-n", "big")
1946 : ELF_TARGET ("elf32-", "big")))
1947 : (HAVE_64BIT_OBJECTS
1948 ? ELF_TARGET ("elf64-", "little")
1950 ? ELF_TARGET ("elf32-n", "little")
1951 : ELF_TARGET ("elf32-", "little"))));
1958 /* Return the ISA revision that is currently in use, or 0 if we are
1959 generating code for MIPS V or below. */
1964 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1967 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
1970 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
1973 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
1976 /* microMIPS implies revision 2 or above. */
1977 if (mips_opts
.micromips
)
1980 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1986 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1989 mips_ase_mask (unsigned int flags
)
1993 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1994 if (flags
& mips_ase_groups
[i
])
1995 flags
|= mips_ase_groups
[i
];
1999 /* Check whether the current ISA supports ASE. Issue a warning if
2003 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2007 static unsigned int warned_isa
;
2008 static unsigned int warned_fp32
;
2010 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2011 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2013 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2014 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2015 && (warned_isa
& ase
->flags
) != ase
->flags
)
2017 warned_isa
|= ase
->flags
;
2018 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2019 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2021 as_warn (_("the %d-bit %s architecture does not support the"
2022 " `%s' extension"), size
, base
, ase
->name
);
2024 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2025 ase
->name
, base
, size
, min_rev
);
2027 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2028 && (warned_isa
& ase
->flags
) != ase
->flags
)
2030 warned_isa
|= ase
->flags
;
2031 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2032 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2033 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2034 ase
->name
, base
, size
, ase
->rem_rev
);
2037 if ((ase
->flags
& FP64_ASES
)
2038 && mips_opts
.fp
!= 64
2039 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2041 warned_fp32
|= ase
->flags
;
2042 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2046 /* Check all enabled ASEs to see whether they are supported by the
2047 chosen architecture. */
2050 mips_check_isa_supports_ases (void)
2052 unsigned int i
, mask
;
2054 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2056 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2057 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2058 mips_check_isa_supports_ase (&mips_ases
[i
]);
2062 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2063 that were affected. */
2066 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2067 bfd_boolean enabled_p
)
2071 mask
= mips_ase_mask (ase
->flags
);
2074 opts
->ase
|= ase
->flags
;
2078 /* Return the ASE called NAME, or null if none. */
2080 static const struct mips_ase
*
2081 mips_lookup_ase (const char *name
)
2085 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2086 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2087 return &mips_ases
[i
];
2091 /* Return the length of a microMIPS instruction in bytes. If bits of
2092 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
2093 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
2094 major opcode) will require further modifications to the opcode
2097 static inline unsigned int
2098 micromips_insn_length (const struct mips_opcode
*mo
)
2100 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2103 /* Return the length of MIPS16 instruction OPCODE. */
2105 static inline unsigned int
2106 mips16_opcode_length (unsigned long opcode
)
2108 return (opcode
>> 16) == 0 ? 2 : 4;
2111 /* Return the length of instruction INSN. */
2113 static inline unsigned int
2114 insn_length (const struct mips_cl_insn
*insn
)
2116 if (mips_opts
.micromips
)
2117 return micromips_insn_length (insn
->insn_mo
);
2118 else if (mips_opts
.mips16
)
2119 return mips16_opcode_length (insn
->insn_opcode
);
2124 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2127 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2132 insn
->insn_opcode
= mo
->match
;
2135 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2136 insn
->fixp
[i
] = NULL
;
2137 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2138 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2139 insn
->mips16_absolute_jump_p
= 0;
2140 insn
->complete_p
= 0;
2141 insn
->cleared_p
= 0;
2144 /* Get a list of all the operands in INSN. */
2146 static const struct mips_operand_array
*
2147 insn_operands (const struct mips_cl_insn
*insn
)
2149 if (insn
->insn_mo
>= &mips_opcodes
[0]
2150 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2151 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2153 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2154 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2155 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2157 if (insn
->insn_mo
>= µmips_opcodes
[0]
2158 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2159 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2164 /* Get a description of operand OPNO of INSN. */
2166 static const struct mips_operand
*
2167 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2169 const struct mips_operand_array
*operands
;
2171 operands
= insn_operands (insn
);
2172 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2174 return operands
->operand
[opno
];
2177 /* Install UVAL as the value of OPERAND in INSN. */
2180 insn_insert_operand (struct mips_cl_insn
*insn
,
2181 const struct mips_operand
*operand
, unsigned int uval
)
2183 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2186 /* Extract the value of OPERAND from INSN. */
2188 static inline unsigned
2189 insn_extract_operand (const struct mips_cl_insn
*insn
,
2190 const struct mips_operand
*operand
)
2192 return mips_extract_operand (operand
, insn
->insn_opcode
);
2195 /* Record the current MIPS16/microMIPS mode in now_seg. */
2198 mips_record_compressed_mode (void)
2200 segment_info_type
*si
;
2202 si
= seg_info (now_seg
);
2203 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2204 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2205 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2206 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2209 /* Read a standard MIPS instruction from BUF. */
2211 static unsigned long
2212 read_insn (char *buf
)
2214 if (target_big_endian
)
2215 return bfd_getb32 ((bfd_byte
*) buf
);
2217 return bfd_getl32 ((bfd_byte
*) buf
);
2220 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2224 write_insn (char *buf
, unsigned int insn
)
2226 md_number_to_chars (buf
, insn
, 4);
2230 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2231 has length LENGTH. */
2233 static unsigned long
2234 read_compressed_insn (char *buf
, unsigned int length
)
2240 for (i
= 0; i
< length
; i
+= 2)
2243 if (target_big_endian
)
2244 insn
|= bfd_getb16 ((char *) buf
);
2246 insn
|= bfd_getl16 ((char *) buf
);
2252 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2253 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2256 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2260 for (i
= 0; i
< length
; i
+= 2)
2261 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2262 return buf
+ length
;
2265 /* Install INSN at the location specified by its "frag" and "where" fields. */
2268 install_insn (const struct mips_cl_insn
*insn
)
2270 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2271 if (HAVE_CODE_COMPRESSION
)
2272 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2274 write_insn (f
, insn
->insn_opcode
);
2275 mips_record_compressed_mode ();
2278 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2279 and install the opcode in the new location. */
2282 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2287 insn
->where
= where
;
2288 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2289 if (insn
->fixp
[i
] != NULL
)
2291 insn
->fixp
[i
]->fx_frag
= frag
;
2292 insn
->fixp
[i
]->fx_where
= where
;
2294 install_insn (insn
);
2297 /* Add INSN to the end of the output. */
2300 add_fixed_insn (struct mips_cl_insn
*insn
)
2302 char *f
= frag_more (insn_length (insn
));
2303 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2306 /* Start a variant frag and move INSN to the start of the variant part,
2307 marking it as fixed. The other arguments are as for frag_var. */
2310 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2311 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2313 frag_grow (max_chars
);
2314 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2316 frag_var (rs_machine_dependent
, max_chars
, var
,
2317 subtype
, symbol
, offset
, NULL
);
2320 /* Insert N copies of INSN into the history buffer, starting at
2321 position FIRST. Neither FIRST nor N need to be clipped. */
2324 insert_into_history (unsigned int first
, unsigned int n
,
2325 const struct mips_cl_insn
*insn
)
2327 if (mips_relax
.sequence
!= 2)
2331 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2333 history
[i
] = history
[i
- n
];
2339 /* Clear the error in insn_error. */
2342 clear_insn_error (void)
2344 memset (&insn_error
, 0, sizeof (insn_error
));
2347 /* Possibly record error message MSG for the current instruction.
2348 If the error is about a particular argument, ARGNUM is the 1-based
2349 number of that argument, otherwise it is 0. FORMAT is the format
2350 of MSG. Return true if MSG was used, false if the current message
2354 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2359 /* Give priority to errors against specific arguments, and to
2360 the first whole-instruction message. */
2366 /* Keep insn_error if it is against a later argument. */
2367 if (argnum
< insn_error
.min_argnum
)
2370 /* If both errors are against the same argument but are different,
2371 give up on reporting a specific error for this argument.
2372 See the comment about mips_insn_error for details. */
2373 if (argnum
== insn_error
.min_argnum
2375 && strcmp (insn_error
.msg
, msg
) != 0)
2378 insn_error
.min_argnum
+= 1;
2382 insn_error
.min_argnum
= argnum
;
2383 insn_error
.format
= format
;
2384 insn_error
.msg
= msg
;
2388 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2389 as for set_insn_error_format. */
2392 set_insn_error (int argnum
, const char *msg
)
2394 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2397 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2398 as for set_insn_error_format. */
2401 set_insn_error_i (int argnum
, const char *msg
, int i
)
2403 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2407 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2408 are as for set_insn_error_format. */
2411 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2413 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2415 insn_error
.u
.ss
[0] = s1
;
2416 insn_error
.u
.ss
[1] = s2
;
2420 /* Report the error in insn_error, which is against assembly code STR. */
2423 report_insn_error (const char *str
)
2427 msg
= ACONCAT ((insn_error
.msg
, " `%s'", NULL
));
2428 switch (insn_error
.format
)
2435 as_bad (msg
, insn_error
.u
.i
, str
);
2439 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2444 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2445 the idea is to make it obvious at a glance that each errata is
2449 init_vr4120_conflicts (void)
2451 #define CONFLICT(FIRST, SECOND) \
2452 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2454 /* Errata 21 - [D]DIV[U] after [D]MACC */
2455 CONFLICT (MACC
, DIV
);
2456 CONFLICT (DMACC
, DIV
);
2458 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2459 CONFLICT (DMULT
, DMULT
);
2460 CONFLICT (DMULT
, DMACC
);
2461 CONFLICT (DMACC
, DMULT
);
2462 CONFLICT (DMACC
, DMACC
);
2464 /* Errata 24 - MT{LO,HI} after [D]MACC */
2465 CONFLICT (MACC
, MTHILO
);
2466 CONFLICT (DMACC
, MTHILO
);
2468 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2469 instruction is executed immediately after a MACC or DMACC
2470 instruction, the result of [either instruction] is incorrect." */
2471 CONFLICT (MACC
, MULT
);
2472 CONFLICT (MACC
, DMULT
);
2473 CONFLICT (DMACC
, MULT
);
2474 CONFLICT (DMACC
, DMULT
);
2476 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2477 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2478 DDIV or DDIVU instruction, the result of the MACC or
2479 DMACC instruction is incorrect.". */
2480 CONFLICT (DMULT
, MACC
);
2481 CONFLICT (DMULT
, DMACC
);
2482 CONFLICT (DIV
, MACC
);
2483 CONFLICT (DIV
, DMACC
);
2493 #define RNUM_MASK 0x00000ff
2494 #define RTYPE_MASK 0x0ffff00
2495 #define RTYPE_NUM 0x0000100
2496 #define RTYPE_FPU 0x0000200
2497 #define RTYPE_FCC 0x0000400
2498 #define RTYPE_VEC 0x0000800
2499 #define RTYPE_GP 0x0001000
2500 #define RTYPE_CP0 0x0002000
2501 #define RTYPE_PC 0x0004000
2502 #define RTYPE_ACC 0x0008000
2503 #define RTYPE_CCC 0x0010000
2504 #define RTYPE_VI 0x0020000
2505 #define RTYPE_VF 0x0040000
2506 #define RTYPE_R5900_I 0x0080000
2507 #define RTYPE_R5900_Q 0x0100000
2508 #define RTYPE_R5900_R 0x0200000
2509 #define RTYPE_R5900_ACC 0x0400000
2510 #define RTYPE_MSA 0x0800000
2511 #define RWARN 0x8000000
2513 #define GENERIC_REGISTER_NUMBERS \
2514 {"$0", RTYPE_NUM | 0}, \
2515 {"$1", RTYPE_NUM | 1}, \
2516 {"$2", RTYPE_NUM | 2}, \
2517 {"$3", RTYPE_NUM | 3}, \
2518 {"$4", RTYPE_NUM | 4}, \
2519 {"$5", RTYPE_NUM | 5}, \
2520 {"$6", RTYPE_NUM | 6}, \
2521 {"$7", RTYPE_NUM | 7}, \
2522 {"$8", RTYPE_NUM | 8}, \
2523 {"$9", RTYPE_NUM | 9}, \
2524 {"$10", RTYPE_NUM | 10}, \
2525 {"$11", RTYPE_NUM | 11}, \
2526 {"$12", RTYPE_NUM | 12}, \
2527 {"$13", RTYPE_NUM | 13}, \
2528 {"$14", RTYPE_NUM | 14}, \
2529 {"$15", RTYPE_NUM | 15}, \
2530 {"$16", RTYPE_NUM | 16}, \
2531 {"$17", RTYPE_NUM | 17}, \
2532 {"$18", RTYPE_NUM | 18}, \
2533 {"$19", RTYPE_NUM | 19}, \
2534 {"$20", RTYPE_NUM | 20}, \
2535 {"$21", RTYPE_NUM | 21}, \
2536 {"$22", RTYPE_NUM | 22}, \
2537 {"$23", RTYPE_NUM | 23}, \
2538 {"$24", RTYPE_NUM | 24}, \
2539 {"$25", RTYPE_NUM | 25}, \
2540 {"$26", RTYPE_NUM | 26}, \
2541 {"$27", RTYPE_NUM | 27}, \
2542 {"$28", RTYPE_NUM | 28}, \
2543 {"$29", RTYPE_NUM | 29}, \
2544 {"$30", RTYPE_NUM | 30}, \
2545 {"$31", RTYPE_NUM | 31}
2547 #define FPU_REGISTER_NAMES \
2548 {"$f0", RTYPE_FPU | 0}, \
2549 {"$f1", RTYPE_FPU | 1}, \
2550 {"$f2", RTYPE_FPU | 2}, \
2551 {"$f3", RTYPE_FPU | 3}, \
2552 {"$f4", RTYPE_FPU | 4}, \
2553 {"$f5", RTYPE_FPU | 5}, \
2554 {"$f6", RTYPE_FPU | 6}, \
2555 {"$f7", RTYPE_FPU | 7}, \
2556 {"$f8", RTYPE_FPU | 8}, \
2557 {"$f9", RTYPE_FPU | 9}, \
2558 {"$f10", RTYPE_FPU | 10}, \
2559 {"$f11", RTYPE_FPU | 11}, \
2560 {"$f12", RTYPE_FPU | 12}, \
2561 {"$f13", RTYPE_FPU | 13}, \
2562 {"$f14", RTYPE_FPU | 14}, \
2563 {"$f15", RTYPE_FPU | 15}, \
2564 {"$f16", RTYPE_FPU | 16}, \
2565 {"$f17", RTYPE_FPU | 17}, \
2566 {"$f18", RTYPE_FPU | 18}, \
2567 {"$f19", RTYPE_FPU | 19}, \
2568 {"$f20", RTYPE_FPU | 20}, \
2569 {"$f21", RTYPE_FPU | 21}, \
2570 {"$f22", RTYPE_FPU | 22}, \
2571 {"$f23", RTYPE_FPU | 23}, \
2572 {"$f24", RTYPE_FPU | 24}, \
2573 {"$f25", RTYPE_FPU | 25}, \
2574 {"$f26", RTYPE_FPU | 26}, \
2575 {"$f27", RTYPE_FPU | 27}, \
2576 {"$f28", RTYPE_FPU | 28}, \
2577 {"$f29", RTYPE_FPU | 29}, \
2578 {"$f30", RTYPE_FPU | 30}, \
2579 {"$f31", RTYPE_FPU | 31}
2581 #define FPU_CONDITION_CODE_NAMES \
2582 {"$fcc0", RTYPE_FCC | 0}, \
2583 {"$fcc1", RTYPE_FCC | 1}, \
2584 {"$fcc2", RTYPE_FCC | 2}, \
2585 {"$fcc3", RTYPE_FCC | 3}, \
2586 {"$fcc4", RTYPE_FCC | 4}, \
2587 {"$fcc5", RTYPE_FCC | 5}, \
2588 {"$fcc6", RTYPE_FCC | 6}, \
2589 {"$fcc7", RTYPE_FCC | 7}
2591 #define COPROC_CONDITION_CODE_NAMES \
2592 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2593 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2594 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2595 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2596 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2597 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2598 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2599 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2601 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2602 {"$a4", RTYPE_GP | 8}, \
2603 {"$a5", RTYPE_GP | 9}, \
2604 {"$a6", RTYPE_GP | 10}, \
2605 {"$a7", RTYPE_GP | 11}, \
2606 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2607 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2608 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2609 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2610 {"$t0", RTYPE_GP | 12}, \
2611 {"$t1", RTYPE_GP | 13}, \
2612 {"$t2", RTYPE_GP | 14}, \
2613 {"$t3", RTYPE_GP | 15}
2615 #define O32_SYMBOLIC_REGISTER_NAMES \
2616 {"$t0", RTYPE_GP | 8}, \
2617 {"$t1", RTYPE_GP | 9}, \
2618 {"$t2", RTYPE_GP | 10}, \
2619 {"$t3", RTYPE_GP | 11}, \
2620 {"$t4", RTYPE_GP | 12}, \
2621 {"$t5", RTYPE_GP | 13}, \
2622 {"$t6", RTYPE_GP | 14}, \
2623 {"$t7", RTYPE_GP | 15}, \
2624 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2625 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2626 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2627 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2629 /* Remaining symbolic register names */
2630 #define SYMBOLIC_REGISTER_NAMES \
2631 {"$zero", RTYPE_GP | 0}, \
2632 {"$at", RTYPE_GP | 1}, \
2633 {"$AT", RTYPE_GP | 1}, \
2634 {"$v0", RTYPE_GP | 2}, \
2635 {"$v1", RTYPE_GP | 3}, \
2636 {"$a0", RTYPE_GP | 4}, \
2637 {"$a1", RTYPE_GP | 5}, \
2638 {"$a2", RTYPE_GP | 6}, \
2639 {"$a3", RTYPE_GP | 7}, \
2640 {"$s0", RTYPE_GP | 16}, \
2641 {"$s1", RTYPE_GP | 17}, \
2642 {"$s2", RTYPE_GP | 18}, \
2643 {"$s3", RTYPE_GP | 19}, \
2644 {"$s4", RTYPE_GP | 20}, \
2645 {"$s5", RTYPE_GP | 21}, \
2646 {"$s6", RTYPE_GP | 22}, \
2647 {"$s7", RTYPE_GP | 23}, \
2648 {"$t8", RTYPE_GP | 24}, \
2649 {"$t9", RTYPE_GP | 25}, \
2650 {"$k0", RTYPE_GP | 26}, \
2651 {"$kt0", RTYPE_GP | 26}, \
2652 {"$k1", RTYPE_GP | 27}, \
2653 {"$kt1", RTYPE_GP | 27}, \
2654 {"$gp", RTYPE_GP | 28}, \
2655 {"$sp", RTYPE_GP | 29}, \
2656 {"$s8", RTYPE_GP | 30}, \
2657 {"$fp", RTYPE_GP | 30}, \
2658 {"$ra", RTYPE_GP | 31}
2660 #define MIPS16_SPECIAL_REGISTER_NAMES \
2661 {"$pc", RTYPE_PC | 0}
2663 #define MDMX_VECTOR_REGISTER_NAMES \
2664 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2665 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2666 {"$v2", RTYPE_VEC | 2}, \
2667 {"$v3", RTYPE_VEC | 3}, \
2668 {"$v4", RTYPE_VEC | 4}, \
2669 {"$v5", RTYPE_VEC | 5}, \
2670 {"$v6", RTYPE_VEC | 6}, \
2671 {"$v7", RTYPE_VEC | 7}, \
2672 {"$v8", RTYPE_VEC | 8}, \
2673 {"$v9", RTYPE_VEC | 9}, \
2674 {"$v10", RTYPE_VEC | 10}, \
2675 {"$v11", RTYPE_VEC | 11}, \
2676 {"$v12", RTYPE_VEC | 12}, \
2677 {"$v13", RTYPE_VEC | 13}, \
2678 {"$v14", RTYPE_VEC | 14}, \
2679 {"$v15", RTYPE_VEC | 15}, \
2680 {"$v16", RTYPE_VEC | 16}, \
2681 {"$v17", RTYPE_VEC | 17}, \
2682 {"$v18", RTYPE_VEC | 18}, \
2683 {"$v19", RTYPE_VEC | 19}, \
2684 {"$v20", RTYPE_VEC | 20}, \
2685 {"$v21", RTYPE_VEC | 21}, \
2686 {"$v22", RTYPE_VEC | 22}, \
2687 {"$v23", RTYPE_VEC | 23}, \
2688 {"$v24", RTYPE_VEC | 24}, \
2689 {"$v25", RTYPE_VEC | 25}, \
2690 {"$v26", RTYPE_VEC | 26}, \
2691 {"$v27", RTYPE_VEC | 27}, \
2692 {"$v28", RTYPE_VEC | 28}, \
2693 {"$v29", RTYPE_VEC | 29}, \
2694 {"$v30", RTYPE_VEC | 30}, \
2695 {"$v31", RTYPE_VEC | 31}
2697 #define R5900_I_NAMES \
2698 {"$I", RTYPE_R5900_I | 0}
2700 #define R5900_Q_NAMES \
2701 {"$Q", RTYPE_R5900_Q | 0}
2703 #define R5900_R_NAMES \
2704 {"$R", RTYPE_R5900_R | 0}
2706 #define R5900_ACC_NAMES \
2707 {"$ACC", RTYPE_R5900_ACC | 0 }
2709 #define MIPS_DSP_ACCUMULATOR_NAMES \
2710 {"$ac0", RTYPE_ACC | 0}, \
2711 {"$ac1", RTYPE_ACC | 1}, \
2712 {"$ac2", RTYPE_ACC | 2}, \
2713 {"$ac3", RTYPE_ACC | 3}
2715 static const struct regname reg_names
[] = {
2716 GENERIC_REGISTER_NUMBERS
,
2718 FPU_CONDITION_CODE_NAMES
,
2719 COPROC_CONDITION_CODE_NAMES
,
2721 /* The $txx registers depends on the abi,
2722 these will be added later into the symbol table from
2723 one of the tables below once mips_abi is set after
2724 parsing of arguments from the command line. */
2725 SYMBOLIC_REGISTER_NAMES
,
2727 MIPS16_SPECIAL_REGISTER_NAMES
,
2728 MDMX_VECTOR_REGISTER_NAMES
,
2733 MIPS_DSP_ACCUMULATOR_NAMES
,
2737 static const struct regname reg_names_o32
[] = {
2738 O32_SYMBOLIC_REGISTER_NAMES
,
2742 static const struct regname reg_names_n32n64
[] = {
2743 N32N64_SYMBOLIC_REGISTER_NAMES
,
2747 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2748 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2749 of these register symbols, return the associated vector register,
2750 otherwise return SYMVAL itself. */
2753 mips_prefer_vec_regno (unsigned int symval
)
2755 if ((symval
& -2) == (RTYPE_GP
| 2))
2756 return RTYPE_VEC
| (symval
& 1);
2760 /* Return true if string [S, E) is a valid register name, storing its
2761 symbol value in *SYMVAL_PTR if so. */
2764 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2769 /* Terminate name. */
2773 /* Look up the name. */
2774 symbol
= symbol_find (s
);
2777 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2780 *symval_ptr
= S_GET_VALUE (symbol
);
2784 /* Return true if the string at *SPTR is a valid register name. Allow it
2785 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2788 When returning true, move *SPTR past the register, store the
2789 register's symbol value in *SYMVAL_PTR and the channel mask in
2790 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2791 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2792 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2795 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2796 unsigned int *channels_ptr
)
2800 unsigned int channels
, symval
, bit
;
2802 /* Find end of name. */
2804 if (is_name_beginner (*e
))
2806 while (is_part_of_name (*e
))
2810 if (!mips_parse_register_1 (s
, e
, &symval
))
2815 /* Eat characters from the end of the string that are valid
2816 channel suffixes. The preceding register must be $ACC or
2817 end with a digit, so there is no ambiguity. */
2820 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2821 if (m
> s
&& m
[-1] == *q
)
2828 || !mips_parse_register_1 (s
, m
, &symval
)
2829 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2834 *symval_ptr
= symval
;
2836 *channels_ptr
= channels
;
2840 /* Check if SPTR points at a valid register specifier according to TYPES.
2841 If so, then return 1, advance S to consume the specifier and store
2842 the register's number in REGNOP, otherwise return 0. */
2845 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2849 if (mips_parse_register (s
, ®no
, NULL
))
2851 if (types
& RTYPE_VEC
)
2852 regno
= mips_prefer_vec_regno (regno
);
2861 as_warn (_("unrecognized register name `%s'"), *s
);
2866 return regno
<= RNUM_MASK
;
2869 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2870 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2873 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2878 for (i
= 0; i
< 4; i
++)
2879 if (*s
== "xyzw"[i
])
2881 *channels
|= 1 << (3 - i
);
2887 /* Token types for parsed operand lists. */
2888 enum mips_operand_token_type
{
2889 /* A plain register, e.g. $f2. */
2892 /* A 4-bit XYZW channel mask. */
2895 /* A constant vector index, e.g. [1]. */
2898 /* A register vector index, e.g. [$2]. */
2901 /* A continuous range of registers, e.g. $s0-$s4. */
2904 /* A (possibly relocated) expression. */
2907 /* A floating-point value. */
2910 /* A single character. This can be '(', ')' or ',', but '(' only appears
2914 /* A doubled character, either "--" or "++". */
2917 /* The end of the operand list. */
2921 /* A parsed operand token. */
2922 struct mips_operand_token
2924 /* The type of token. */
2925 enum mips_operand_token_type type
;
2928 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2931 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2932 unsigned int channels
;
2934 /* The integer value of an OT_INTEGER_INDEX. */
2937 /* The two register symbol values involved in an OT_REG_RANGE. */
2939 unsigned int regno1
;
2940 unsigned int regno2
;
2943 /* The value of an OT_INTEGER. The value is represented as an
2944 expression and the relocation operators that were applied to
2945 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2946 relocation operators were used. */
2949 bfd_reloc_code_real_type relocs
[3];
2952 /* The binary data for an OT_FLOAT constant, and the number of bytes
2955 unsigned char data
[8];
2959 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2964 /* An obstack used to construct lists of mips_operand_tokens. */
2965 static struct obstack mips_operand_tokens
;
2967 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2970 mips_add_token (struct mips_operand_token
*token
,
2971 enum mips_operand_token_type type
)
2974 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2977 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2978 and OT_REG tokens for them if so, and return a pointer to the first
2979 unconsumed character. Return null otherwise. */
2982 mips_parse_base_start (char *s
)
2984 struct mips_operand_token token
;
2985 unsigned int regno
, channels
;
2986 bfd_boolean decrement_p
;
2992 SKIP_SPACE_TABS (s
);
2994 /* Only match "--" as part of a base expression. In other contexts "--X"
2995 is a double negative. */
2996 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3000 SKIP_SPACE_TABS (s
);
3003 /* Allow a channel specifier because that leads to better error messages
3004 than treating something like "$vf0x++" as an expression. */
3005 if (!mips_parse_register (&s
, ®no
, &channels
))
3009 mips_add_token (&token
, OT_CHAR
);
3014 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3017 token
.u
.regno
= regno
;
3018 mips_add_token (&token
, OT_REG
);
3022 token
.u
.channels
= channels
;
3023 mips_add_token (&token
, OT_CHANNELS
);
3026 /* For consistency, only match "++" as part of base expressions too. */
3027 SKIP_SPACE_TABS (s
);
3028 if (s
[0] == '+' && s
[1] == '+')
3032 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3038 /* Parse one or more tokens from S. Return a pointer to the first
3039 unconsumed character on success. Return null if an error was found
3040 and store the error text in insn_error. FLOAT_FORMAT is as for
3041 mips_parse_arguments. */
3044 mips_parse_argument_token (char *s
, char float_format
)
3046 char *end
, *save_in
, *err
;
3047 unsigned int regno1
, regno2
, channels
;
3048 struct mips_operand_token token
;
3050 /* First look for "($reg", since we want to treat that as an
3051 OT_CHAR and OT_REG rather than an expression. */
3052 end
= mips_parse_base_start (s
);
3056 /* Handle other characters that end up as OT_CHARs. */
3057 if (*s
== ')' || *s
== ',')
3060 mips_add_token (&token
, OT_CHAR
);
3065 /* Handle tokens that start with a register. */
3066 if (mips_parse_register (&s
, ®no1
, &channels
))
3070 /* A register and a VU0 channel suffix. */
3071 token
.u
.regno
= regno1
;
3072 mips_add_token (&token
, OT_REG
);
3074 token
.u
.channels
= channels
;
3075 mips_add_token (&token
, OT_CHANNELS
);
3079 SKIP_SPACE_TABS (s
);
3082 /* A register range. */
3084 SKIP_SPACE_TABS (s
);
3085 if (!mips_parse_register (&s
, ®no2
, NULL
))
3087 set_insn_error (0, _("invalid register range"));
3091 token
.u
.reg_range
.regno1
= regno1
;
3092 token
.u
.reg_range
.regno2
= regno2
;
3093 mips_add_token (&token
, OT_REG_RANGE
);
3097 /* Add the register itself. */
3098 token
.u
.regno
= regno1
;
3099 mips_add_token (&token
, OT_REG
);
3101 /* Check for a vector index. */
3105 SKIP_SPACE_TABS (s
);
3106 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3107 mips_add_token (&token
, OT_REG_INDEX
);
3110 expressionS element
;
3112 my_getExpression (&element
, s
);
3113 if (element
.X_op
!= O_constant
)
3115 set_insn_error (0, _("vector element must be constant"));
3119 token
.u
.index
= element
.X_add_number
;
3120 mips_add_token (&token
, OT_INTEGER_INDEX
);
3122 SKIP_SPACE_TABS (s
);
3125 set_insn_error (0, _("missing `]'"));
3135 /* First try to treat expressions as floats. */
3136 save_in
= input_line_pointer
;
3137 input_line_pointer
= s
;
3138 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3139 &token
.u
.flt
.length
);
3140 end
= input_line_pointer
;
3141 input_line_pointer
= save_in
;
3144 set_insn_error (0, err
);
3149 mips_add_token (&token
, OT_FLOAT
);
3154 /* Treat everything else as an integer expression. */
3155 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3156 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3157 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3158 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3160 mips_add_token (&token
, OT_INTEGER
);
3164 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3165 if expressions should be treated as 32-bit floating-point constants,
3166 'd' if they should be treated as 64-bit floating-point constants,
3167 or 0 if they should be treated as integer expressions (the usual case).
3169 Return a list of tokens on success, otherwise return 0. The caller
3170 must obstack_free the list after use. */
3172 static struct mips_operand_token
*
3173 mips_parse_arguments (char *s
, char float_format
)
3175 struct mips_operand_token token
;
3177 SKIP_SPACE_TABS (s
);
3180 s
= mips_parse_argument_token (s
, float_format
);
3183 obstack_free (&mips_operand_tokens
,
3184 obstack_finish (&mips_operand_tokens
));
3187 SKIP_SPACE_TABS (s
);
3189 mips_add_token (&token
, OT_END
);
3190 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3193 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3194 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3197 is_opcode_valid (const struct mips_opcode
*mo
)
3199 int isa
= mips_opts
.isa
;
3200 int ase
= mips_opts
.ase
;
3204 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3205 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3206 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3207 ase
|= mips_ases
[i
].flags64
;
3209 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3212 /* Check whether the instruction or macro requires single-precision or
3213 double-precision floating-point support. Note that this information is
3214 stored differently in the opcode table for insns and macros. */
3215 if (mo
->pinfo
== INSN_MACRO
)
3217 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3218 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3222 fp_s
= mo
->pinfo
& FP_S
;
3223 fp_d
= mo
->pinfo
& FP_D
;
3226 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3229 if (fp_s
&& mips_opts
.soft_float
)
3235 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3236 selected ISA and architecture. */
3239 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3241 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3244 /* Return TRUE if the size of the microMIPS opcode MO matches one
3245 explicitly requested. Always TRUE in the standard MIPS mode. */
3248 is_size_valid (const struct mips_opcode
*mo
)
3250 if (!mips_opts
.micromips
)
3253 if (mips_opts
.insn32
)
3255 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3257 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3260 if (!forced_insn_length
)
3262 if (mo
->pinfo
== INSN_MACRO
)
3264 return forced_insn_length
== micromips_insn_length (mo
);
3267 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3268 of the preceding instruction. Always TRUE in the standard MIPS mode.
3270 We don't accept macros in 16-bit delay slots to avoid a case where
3271 a macro expansion fails because it relies on a preceding 32-bit real
3272 instruction to have matched and does not handle the operands correctly.
3273 The only macros that may expand to 16-bit instructions are JAL that
3274 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3275 and BGT (that likewise cannot be placed in a delay slot) that decay to
3276 a NOP. In all these cases the macros precede any corresponding real
3277 instruction definitions in the opcode table, so they will match in the
3278 second pass where the size of the delay slot is ignored and therefore
3279 produce correct code. */
3282 is_delay_slot_valid (const struct mips_opcode
*mo
)
3284 if (!mips_opts
.micromips
)
3287 if (mo
->pinfo
== INSN_MACRO
)
3288 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3289 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3290 && micromips_insn_length (mo
) != 4)
3292 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3293 && micromips_insn_length (mo
) != 2)
3299 /* For consistency checking, verify that all bits of OPCODE are specified
3300 either by the match/mask part of the instruction definition, or by the
3301 operand list. Also build up a list of operands in OPERANDS.
3303 INSN_BITS says which bits of the instruction are significant.
3304 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3305 provides the mips_operand description of each operand. DECODE_OPERAND
3306 is null for MIPS16 instructions. */
3309 validate_mips_insn (const struct mips_opcode
*opcode
,
3310 unsigned long insn_bits
,
3311 const struct mips_operand
*(*decode_operand
) (const char *),
3312 struct mips_operand_array
*operands
)
3315 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3316 const struct mips_operand
*operand
;
3318 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3319 if ((mask
& opcode
->match
) != opcode
->match
)
3321 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3322 opcode
->name
, opcode
->args
);
3327 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3328 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3329 for (s
= opcode
->args
; *s
; ++s
)
3342 if (!decode_operand
)
3343 operand
= decode_mips16_operand (*s
, FALSE
);
3345 operand
= decode_operand (s
);
3346 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3348 as_bad (_("internal: unknown operand type: %s %s"),
3349 opcode
->name
, opcode
->args
);
3352 gas_assert (opno
< MAX_OPERANDS
);
3353 operands
->operand
[opno
] = operand
;
3354 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3356 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3357 if (operand
->type
== OP_MDMX_IMM_REG
)
3358 /* Bit 5 is the format selector (OB vs QH). The opcode table
3359 has separate entries for each format. */
3360 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3361 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3362 used_bits
&= ~(mask
& 0x700);
3364 /* Skip prefix characters. */
3365 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3370 doubled
= used_bits
& mask
& insn_bits
;
3373 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3374 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3378 undefined
= ~used_bits
& insn_bits
;
3379 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3381 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3382 undefined
, opcode
->name
, opcode
->args
);
3385 used_bits
&= ~insn_bits
;
3388 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3389 used_bits
, opcode
->name
, opcode
->args
);
3395 /* The MIPS16 version of validate_mips_insn. */
3398 validate_mips16_insn (const struct mips_opcode
*opcode
,
3399 struct mips_operand_array
*operands
)
3401 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3403 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3404 instruction. Use TMP to describe the full instruction. */
3405 struct mips_opcode tmp
;
3410 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3412 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3415 /* The microMIPS version of validate_mips_insn. */
3418 validate_micromips_insn (const struct mips_opcode
*opc
,
3419 struct mips_operand_array
*operands
)
3421 unsigned long insn_bits
;
3422 unsigned long major
;
3423 unsigned int length
;
3425 if (opc
->pinfo
== INSN_MACRO
)
3426 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3429 length
= micromips_insn_length (opc
);
3430 if (length
!= 2 && length
!= 4)
3432 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3433 "%s %s"), length
, opc
->name
, opc
->args
);
3436 major
= opc
->match
>> (10 + 8 * (length
- 2));
3437 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3438 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3440 as_bad (_("internal error: bad microMIPS opcode "
3441 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3445 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3446 insn_bits
= 1 << 4 * length
;
3447 insn_bits
<<= 4 * length
;
3449 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3453 /* This function is called once, at assembler startup time. It should set up
3454 all the tables, etc. that the MD part of the assembler will need. */
3459 const char *retval
= NULL
;
3463 if (mips_pic
!= NO_PIC
)
3465 if (g_switch_seen
&& g_switch_value
!= 0)
3466 as_bad (_("-G may not be used in position-independent code"));
3470 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3471 as_warn (_("could not set architecture and machine"));
3473 op_hash
= hash_new ();
3475 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3476 for (i
= 0; i
< NUMOPCODES
;)
3478 const char *name
= mips_opcodes
[i
].name
;
3480 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3483 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3484 mips_opcodes
[i
].name
, retval
);
3485 /* Probably a memory allocation problem? Give up now. */
3486 as_fatal (_("broken assembler, no assembly attempted"));
3490 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3491 decode_mips_operand
, &mips_operands
[i
]))
3493 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3495 create_insn (&nop_insn
, mips_opcodes
+ i
);
3496 if (mips_fix_loongson2f_nop
)
3497 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3498 nop_insn
.fixed_p
= 1;
3502 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3505 mips16_op_hash
= hash_new ();
3506 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3507 bfd_mips16_num_opcodes
);
3510 while (i
< bfd_mips16_num_opcodes
)
3512 const char *name
= mips16_opcodes
[i
].name
;
3514 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3516 as_fatal (_("internal: can't hash `%s': %s"),
3517 mips16_opcodes
[i
].name
, retval
);
3520 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3522 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3524 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3525 mips16_nop_insn
.fixed_p
= 1;
3529 while (i
< bfd_mips16_num_opcodes
3530 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3533 micromips_op_hash
= hash_new ();
3534 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3535 bfd_micromips_num_opcodes
);
3538 while (i
< bfd_micromips_num_opcodes
)
3540 const char *name
= micromips_opcodes
[i
].name
;
3542 retval
= hash_insert (micromips_op_hash
, name
,
3543 (void *) µmips_opcodes
[i
]);
3545 as_fatal (_("internal: can't hash `%s': %s"),
3546 micromips_opcodes
[i
].name
, retval
);
3549 struct mips_cl_insn
*micromips_nop_insn
;
3551 if (!validate_micromips_insn (µmips_opcodes
[i
],
3552 µmips_operands
[i
]))
3555 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3557 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3558 micromips_nop_insn
= µmips_nop16_insn
;
3559 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3560 micromips_nop_insn
= µmips_nop32_insn
;
3564 if (micromips_nop_insn
->insn_mo
== NULL
3565 && strcmp (name
, "nop") == 0)
3567 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3568 micromips_nop_insn
->fixed_p
= 1;
3572 while (++i
< bfd_micromips_num_opcodes
3573 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3577 as_fatal (_("broken assembler, no assembly attempted"));
3579 /* We add all the general register names to the symbol table. This
3580 helps us detect invalid uses of them. */
3581 for (i
= 0; reg_names
[i
].name
; i
++)
3582 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3583 reg_names
[i
].num
, /* & RNUM_MASK, */
3584 &zero_address_frag
));
3586 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3587 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3588 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3589 &zero_address_frag
));
3591 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3592 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3593 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3594 &zero_address_frag
));
3596 for (i
= 0; i
< 32; i
++)
3600 /* R5900 VU0 floating-point register. */
3601 regname
[sizeof (rename
) - 1] = 0;
3602 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3603 symbol_table_insert (symbol_new (regname
, reg_section
,
3604 RTYPE_VF
| i
, &zero_address_frag
));
3606 /* R5900 VU0 integer register. */
3607 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3608 symbol_table_insert (symbol_new (regname
, reg_section
,
3609 RTYPE_VI
| i
, &zero_address_frag
));
3612 snprintf (regname
, sizeof (regname
) - 1, "$w%d", i
);
3613 symbol_table_insert (symbol_new (regname
, reg_section
,
3614 RTYPE_MSA
| i
, &zero_address_frag
));
3617 obstack_init (&mips_operand_tokens
);
3619 mips_no_prev_insn ();
3622 mips_cprmask
[0] = 0;
3623 mips_cprmask
[1] = 0;
3624 mips_cprmask
[2] = 0;
3625 mips_cprmask
[3] = 0;
3627 /* set the default alignment for the text section (2**2) */
3628 record_alignment (text_section
, 2);
3630 bfd_set_gp_size (stdoutput
, g_switch_value
);
3632 /* On a native system other than VxWorks, sections must be aligned
3633 to 16 byte boundaries. When configured for an embedded ELF
3634 target, we don't bother. */
3635 if (strncmp (TARGET_OS
, "elf", 3) != 0
3636 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3638 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3639 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3640 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3643 /* Create a .reginfo section for register masks and a .mdebug
3644 section for debugging information. */
3652 subseg
= now_subseg
;
3654 /* The ABI says this section should be loaded so that the
3655 running program can access it. However, we don't load it
3656 if we are configured for an embedded target */
3657 flags
= SEC_READONLY
| SEC_DATA
;
3658 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3659 flags
|= SEC_ALLOC
| SEC_LOAD
;
3661 if (mips_abi
!= N64_ABI
)
3663 sec
= subseg_new (".reginfo", (subsegT
) 0);
3665 bfd_set_section_flags (stdoutput
, sec
, flags
);
3666 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3668 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3672 /* The 64-bit ABI uses a .MIPS.options section rather than
3673 .reginfo section. */
3674 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3675 bfd_set_section_flags (stdoutput
, sec
, flags
);
3676 bfd_set_section_alignment (stdoutput
, sec
, 3);
3678 /* Set up the option header. */
3680 Elf_Internal_Options opthdr
;
3683 opthdr
.kind
= ODK_REGINFO
;
3684 opthdr
.size
= (sizeof (Elf_External_Options
)
3685 + sizeof (Elf64_External_RegInfo
));
3688 f
= frag_more (sizeof (Elf_External_Options
));
3689 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3690 (Elf_External_Options
*) f
);
3692 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3696 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3697 bfd_set_section_flags (stdoutput
, sec
,
3698 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3699 bfd_set_section_alignment (stdoutput
, sec
, 3);
3700 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3702 if (ECOFF_DEBUGGING
)
3704 sec
= subseg_new (".mdebug", (subsegT
) 0);
3705 (void) bfd_set_section_flags (stdoutput
, sec
,
3706 SEC_HAS_CONTENTS
| SEC_READONLY
);
3707 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3709 else if (mips_flag_pdr
)
3711 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3712 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3713 SEC_READONLY
| SEC_RELOC
3715 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3718 subseg_set (seg
, subseg
);
3721 if (mips_fix_vr4120
)
3722 init_vr4120_conflicts ();
3726 fpabi_incompatible_with (int fpabi
, const char *what
)
3728 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3729 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3733 fpabi_requires (int fpabi
, const char *what
)
3735 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3736 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3739 /* Check -mabi and register sizes against the specified FP ABI. */
3741 check_fpabi (int fpabi
)
3745 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3746 if (file_mips_opts
.soft_float
)
3747 fpabi_incompatible_with (fpabi
, "softfloat");
3748 else if (file_mips_opts
.single_float
)
3749 fpabi_incompatible_with (fpabi
, "singlefloat");
3750 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3751 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3752 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3753 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3756 case Val_GNU_MIPS_ABI_FP_XX
:
3757 if (mips_abi
!= O32_ABI
)
3758 fpabi_requires (fpabi
, "-mabi=32");
3759 else if (file_mips_opts
.soft_float
)
3760 fpabi_incompatible_with (fpabi
, "softfloat");
3761 else if (file_mips_opts
.single_float
)
3762 fpabi_incompatible_with (fpabi
, "singlefloat");
3763 else if (file_mips_opts
.fp
!= 0)
3764 fpabi_requires (fpabi
, "fp=xx");
3767 case Val_GNU_MIPS_ABI_FP_64A
:
3768 case Val_GNU_MIPS_ABI_FP_64
:
3769 if (mips_abi
!= O32_ABI
)
3770 fpabi_requires (fpabi
, "-mabi=32");
3771 else if (file_mips_opts
.soft_float
)
3772 fpabi_incompatible_with (fpabi
, "softfloat");
3773 else if (file_mips_opts
.single_float
)
3774 fpabi_incompatible_with (fpabi
, "singlefloat");
3775 else if (file_mips_opts
.fp
!= 64)
3776 fpabi_requires (fpabi
, "fp=64");
3777 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3778 fpabi_incompatible_with (fpabi
, "nooddspreg");
3779 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3780 fpabi_requires (fpabi
, "nooddspreg");
3783 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3784 if (file_mips_opts
.soft_float
)
3785 fpabi_incompatible_with (fpabi
, "softfloat");
3786 else if (!file_mips_opts
.single_float
)
3787 fpabi_requires (fpabi
, "singlefloat");
3790 case Val_GNU_MIPS_ABI_FP_SOFT
:
3791 if (!file_mips_opts
.soft_float
)
3792 fpabi_requires (fpabi
, "softfloat");
3795 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3796 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3797 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3801 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3802 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3807 /* Perform consistency checks on the current options. */
3810 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3812 /* Check the size of integer registers agrees with the ABI and ISA. */
3813 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3814 as_bad (_("`gp=64' used with a 32-bit processor"));
3816 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3817 as_bad (_("`gp=32' used with a 64-bit ABI"));
3819 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3820 as_bad (_("`gp=64' used with a 32-bit ABI"));
3822 /* Check the size of the float registers agrees with the ABI and ISA. */
3826 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3827 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3828 else if (opts
->single_float
== 1)
3829 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3832 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3833 as_bad (_("`fp=64' used with a 32-bit fpu"));
3835 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3836 && !ISA_HAS_MXHC1 (opts
->isa
))
3837 as_warn (_("`fp=64' used with a 32-bit ABI"));
3841 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3842 as_warn (_("`fp=32' used with a 64-bit ABI"));
3843 if (ISA_IS_R6 (mips_opts
.isa
) && opts
->single_float
== 0)
3844 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3847 as_bad (_("Unknown size of floating point registers"));
3851 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3852 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3854 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3855 as_bad (_("`mips16' cannot be used with `micromips'"));
3856 else if (ISA_IS_R6 (mips_opts
.isa
)
3857 && (opts
->micromips
== 1
3858 || opts
->mips16
== 1))
3859 as_fatal (_("`%s' can not be used with `%s'"),
3860 opts
->micromips
? "micromips" : "mips16",
3861 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
3863 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3864 as_fatal (_("branch relaxation is not supported in `%s'"),
3865 mips_cpu_info_from_isa (opts
->isa
)->name
);
3868 /* Perform consistency checks on the module level options exactly once.
3869 This is a deferred check that happens:
3870 at the first .set directive
3871 or, at the first pseudo op that generates code (inc .dc.a)
3872 or, at the first instruction
3876 file_mips_check_options (void)
3878 const struct mips_cpu_info
*arch_info
= 0;
3880 if (file_mips_opts_checked
)
3883 /* The following code determines the register size.
3884 Similar code was added to GCC 3.3 (see override_options() in
3885 config/mips/mips.c). The GAS and GCC code should be kept in sync
3886 as much as possible. */
3888 if (file_mips_opts
.gp
< 0)
3890 /* Infer the integer register size from the ABI and processor.
3891 Restrict ourselves to 32-bit registers if that's all the
3892 processor has, or if the ABI cannot handle 64-bit registers. */
3893 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
3894 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
3898 if (file_mips_opts
.fp
< 0)
3900 /* No user specified float register size.
3901 ??? GAS treats single-float processors as though they had 64-bit
3902 float registers (although it complains when double-precision
3903 instructions are used). As things stand, saying they have 32-bit
3904 registers would lead to spurious "register must be even" messages.
3905 So here we assume float registers are never smaller than the
3907 if (file_mips_opts
.gp
== 64)
3908 /* 64-bit integer registers implies 64-bit float registers. */
3909 file_mips_opts
.fp
= 64;
3910 else if ((file_mips_opts
.ase
& FP64_ASES
)
3911 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
3912 /* Handle ASEs that require 64-bit float registers, if possible. */
3913 file_mips_opts
.fp
= 64;
3914 else if (ISA_IS_R6 (mips_opts
.isa
))
3915 /* R6 implies 64-bit float registers. */
3916 file_mips_opts
.fp
= 64;
3918 /* 32-bit float registers. */
3919 file_mips_opts
.fp
= 32;
3922 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
3924 /* Disable operations on odd-numbered floating-point registers by default
3925 when using the FPXX ABI. */
3926 if (file_mips_opts
.oddspreg
< 0)
3928 if (file_mips_opts
.fp
== 0)
3929 file_mips_opts
.oddspreg
= 0;
3931 file_mips_opts
.oddspreg
= 1;
3934 /* End of GCC-shared inference code. */
3936 /* This flag is set when we have a 64-bit capable CPU but use only
3937 32-bit wide registers. Note that EABI does not use it. */
3938 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
3939 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
3940 || mips_abi
== O32_ABI
))
3943 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
3944 as_bad (_("trap exception not supported at ISA 1"));
3946 /* If the selected architecture includes support for ASEs, enable
3947 generation of code for them. */
3948 if (file_mips_opts
.mips16
== -1)
3949 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
3950 if (file_mips_opts
.micromips
== -1)
3951 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
3954 if (mips_nan2008
== -1)
3955 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
3956 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
3957 as_fatal (_("`%s' does not support legacy NaN"),
3958 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
3960 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3961 being selected implicitly. */
3962 if (file_mips_opts
.fp
!= 64)
3963 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
3965 /* If the user didn't explicitly select or deselect a particular ASE,
3966 use the default setting for the CPU. */
3967 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
3969 /* Set up the current options. These may change throughout assembly. */
3970 mips_opts
= file_mips_opts
;
3972 mips_check_isa_supports_ases ();
3973 mips_check_options (&file_mips_opts
, TRUE
);
3974 file_mips_opts_checked
= TRUE
;
3976 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3977 as_warn (_("could not set architecture and machine"));
3981 md_assemble (char *str
)
3983 struct mips_cl_insn insn
;
3984 bfd_reloc_code_real_type unused_reloc
[3]
3985 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3987 file_mips_check_options ();
3989 imm_expr
.X_op
= O_absent
;
3990 offset_expr
.X_op
= O_absent
;
3991 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3992 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3993 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3995 mips_mark_labels ();
3996 mips_assembling_insn
= TRUE
;
3997 clear_insn_error ();
3999 if (mips_opts
.mips16
)
4000 mips16_ip (str
, &insn
);
4003 mips_ip (str
, &insn
);
4004 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4005 str
, insn
.insn_opcode
));
4009 report_insn_error (str
);
4010 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4013 if (mips_opts
.mips16
)
4014 mips16_macro (&insn
);
4021 if (offset_expr
.X_op
!= O_absent
)
4022 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4024 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4027 mips_assembling_insn
= FALSE
;
4030 /* Convenience functions for abstracting away the differences between
4031 MIPS16 and non-MIPS16 relocations. */
4033 static inline bfd_boolean
4034 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4038 case BFD_RELOC_MIPS16_JMP
:
4039 case BFD_RELOC_MIPS16_GPREL
:
4040 case BFD_RELOC_MIPS16_GOT16
:
4041 case BFD_RELOC_MIPS16_CALL16
:
4042 case BFD_RELOC_MIPS16_HI16_S
:
4043 case BFD_RELOC_MIPS16_HI16
:
4044 case BFD_RELOC_MIPS16_LO16
:
4052 static inline bfd_boolean
4053 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4057 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4058 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4059 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4060 case BFD_RELOC_MICROMIPS_GPREL16
:
4061 case BFD_RELOC_MICROMIPS_JMP
:
4062 case BFD_RELOC_MICROMIPS_HI16
:
4063 case BFD_RELOC_MICROMIPS_HI16_S
:
4064 case BFD_RELOC_MICROMIPS_LO16
:
4065 case BFD_RELOC_MICROMIPS_LITERAL
:
4066 case BFD_RELOC_MICROMIPS_GOT16
:
4067 case BFD_RELOC_MICROMIPS_CALL16
:
4068 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4069 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4070 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4071 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4072 case BFD_RELOC_MICROMIPS_SUB
:
4073 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4074 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4075 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4076 case BFD_RELOC_MICROMIPS_HIGHEST
:
4077 case BFD_RELOC_MICROMIPS_HIGHER
:
4078 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4079 case BFD_RELOC_MICROMIPS_JALR
:
4087 static inline bfd_boolean
4088 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4090 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4093 static inline bfd_boolean
4094 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4096 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4097 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4100 static inline bfd_boolean
4101 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4103 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4104 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4107 static inline bfd_boolean
4108 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4110 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4111 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4114 static inline bfd_boolean
4115 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4117 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4120 static inline bfd_boolean
4121 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4123 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4124 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4127 /* Return true if RELOC is a PC-relative relocation that does not have
4128 full address range. */
4130 static inline bfd_boolean
4131 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4135 case BFD_RELOC_16_PCREL_S2
:
4136 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4137 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4138 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4139 case BFD_RELOC_MIPS_21_PCREL_S2
:
4140 case BFD_RELOC_MIPS_26_PCREL_S2
:
4141 case BFD_RELOC_MIPS_18_PCREL_S3
:
4142 case BFD_RELOC_MIPS_19_PCREL_S2
:
4145 case BFD_RELOC_32_PCREL
:
4146 case BFD_RELOC_HI16_S_PCREL
:
4147 case BFD_RELOC_LO16_PCREL
:
4148 return HAVE_64BIT_ADDRESSES
;
4155 /* Return true if the given relocation might need a matching %lo().
4156 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4157 need a matching %lo() when applied to local symbols. */
4159 static inline bfd_boolean
4160 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4162 return (HAVE_IN_PLACE_ADDENDS
4163 && (hi16_reloc_p (reloc
)
4164 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4165 all GOT16 relocations evaluate to "G". */
4166 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4169 /* Return the type of %lo() reloc needed by RELOC, given that
4170 reloc_needs_lo_p. */
4172 static inline bfd_reloc_code_real_type
4173 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4175 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4176 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4180 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4183 static inline bfd_boolean
4184 fixup_has_matching_lo_p (fixS
*fixp
)
4186 return (fixp
->fx_next
!= NULL
4187 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4188 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4189 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4192 /* Move all labels in LABELS to the current insertion point. TEXT_P
4193 says whether the labels refer to text or data. */
4196 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4198 struct insn_label_list
*l
;
4201 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4203 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4204 symbol_set_frag (l
->label
, frag_now
);
4205 val
= (valueT
) frag_now_fix ();
4206 /* MIPS16/microMIPS text labels are stored as odd. */
4207 if (text_p
&& HAVE_CODE_COMPRESSION
)
4209 S_SET_VALUE (l
->label
, val
);
4213 /* Move all labels in insn_labels to the current insertion point
4214 and treat them as text labels. */
4217 mips_move_text_labels (void)
4219 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4223 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4225 bfd_boolean linkonce
= FALSE
;
4226 segT symseg
= S_GET_SEGMENT (sym
);
4228 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4230 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4232 /* The GNU toolchain uses an extension for ELF: a section
4233 beginning with the magic string .gnu.linkonce is a
4234 linkonce section. */
4235 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4236 sizeof ".gnu.linkonce" - 1) == 0)
4242 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4243 linker to handle them specially, such as generating jalx instructions
4244 when needed. We also make them odd for the duration of the assembly,
4245 in order to generate the right sort of code. We will make them even
4246 in the adjust_symtab routine, while leaving them marked. This is
4247 convenient for the debugger and the disassembler. The linker knows
4248 to make them odd again. */
4251 mips_compressed_mark_label (symbolS
*label
)
4253 gas_assert (HAVE_CODE_COMPRESSION
);
4255 if (mips_opts
.mips16
)
4256 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4258 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4259 if ((S_GET_VALUE (label
) & 1) == 0
4260 /* Don't adjust the address if the label is global or weak, or
4261 in a link-once section, since we'll be emitting symbol reloc
4262 references to it which will be patched up by the linker, and
4263 the final value of the symbol may or may not be MIPS16/microMIPS. */
4264 && !S_IS_WEAK (label
)
4265 && !S_IS_EXTERNAL (label
)
4266 && !s_is_linkonce (label
, now_seg
))
4267 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4270 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4273 mips_compressed_mark_labels (void)
4275 struct insn_label_list
*l
;
4277 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4278 mips_compressed_mark_label (l
->label
);
4281 /* End the current frag. Make it a variant frag and record the
4285 relax_close_frag (void)
4287 mips_macro_warning
.first_frag
= frag_now
;
4288 frag_var (rs_machine_dependent
, 0, 0,
4289 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
4290 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4292 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4293 mips_relax
.first_fixup
= 0;
4296 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4297 See the comment above RELAX_ENCODE for more details. */
4300 relax_start (symbolS
*symbol
)
4302 gas_assert (mips_relax
.sequence
== 0);
4303 mips_relax
.sequence
= 1;
4304 mips_relax
.symbol
= symbol
;
4307 /* Start generating the second version of a relaxable sequence.
4308 See the comment above RELAX_ENCODE for more details. */
4313 gas_assert (mips_relax
.sequence
== 1);
4314 mips_relax
.sequence
= 2;
4317 /* End the current relaxable sequence. */
4322 gas_assert (mips_relax
.sequence
== 2);
4323 relax_close_frag ();
4324 mips_relax
.sequence
= 0;
4327 /* Return true if IP is a delayed branch or jump. */
4329 static inline bfd_boolean
4330 delayed_branch_p (const struct mips_cl_insn
*ip
)
4332 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4333 | INSN_COND_BRANCH_DELAY
4334 | INSN_COND_BRANCH_LIKELY
)) != 0;
4337 /* Return true if IP is a compact branch or jump. */
4339 static inline bfd_boolean
4340 compact_branch_p (const struct mips_cl_insn
*ip
)
4342 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4343 | INSN2_COND_BRANCH
)) != 0;
4346 /* Return true if IP is an unconditional branch or jump. */
4348 static inline bfd_boolean
4349 uncond_branch_p (const struct mips_cl_insn
*ip
)
4351 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4352 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4355 /* Return true if IP is a branch-likely instruction. */
4357 static inline bfd_boolean
4358 branch_likely_p (const struct mips_cl_insn
*ip
)
4360 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4363 /* Return the type of nop that should be used to fill the delay slot
4364 of delayed branch IP. */
4366 static struct mips_cl_insn
*
4367 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4369 if (mips_opts
.micromips
4370 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4371 return µmips_nop32_insn
;
4375 /* Return a mask that has bit N set if OPCODE reads the register(s)
4379 insn_read_mask (const struct mips_opcode
*opcode
)
4381 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4384 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4388 insn_write_mask (const struct mips_opcode
*opcode
)
4390 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4393 /* Return a mask of the registers specified by operand OPERAND of INSN.
4394 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4398 operand_reg_mask (const struct mips_cl_insn
*insn
,
4399 const struct mips_operand
*operand
,
4400 unsigned int type_mask
)
4402 unsigned int uval
, vsel
;
4404 switch (operand
->type
)
4411 case OP_ADDIUSP_INT
:
4412 case OP_ENTRY_EXIT_LIST
:
4413 case OP_REPEAT_DEST_REG
:
4414 case OP_REPEAT_PREV_REG
:
4417 case OP_VU0_MATCH_SUFFIX
:
4422 case OP_OPTIONAL_REG
:
4424 const struct mips_reg_operand
*reg_op
;
4426 reg_op
= (const struct mips_reg_operand
*) operand
;
4427 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4429 uval
= insn_extract_operand (insn
, operand
);
4430 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4435 const struct mips_reg_pair_operand
*pair_op
;
4437 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4438 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4440 uval
= insn_extract_operand (insn
, operand
);
4441 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4444 case OP_CLO_CLZ_DEST
:
4445 if (!(type_mask
& (1 << OP_REG_GP
)))
4447 uval
= insn_extract_operand (insn
, operand
);
4448 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4451 if (!(type_mask
& (1 << OP_REG_GP
)))
4453 uval
= insn_extract_operand (insn
, operand
);
4454 gas_assert ((uval
& 31) == (uval
>> 5));
4455 return 1 << (uval
& 31);
4458 case OP_NON_ZERO_REG
:
4459 if (!(type_mask
& (1 << OP_REG_GP
)))
4461 uval
= insn_extract_operand (insn
, operand
);
4462 return 1 << (uval
& 31);
4464 case OP_LWM_SWM_LIST
:
4467 case OP_SAVE_RESTORE_LIST
:
4470 case OP_MDMX_IMM_REG
:
4471 if (!(type_mask
& (1 << OP_REG_VEC
)))
4473 uval
= insn_extract_operand (insn
, operand
);
4475 if ((vsel
& 0x18) == 0x18)
4477 return 1 << (uval
& 31);
4480 if (!(type_mask
& (1 << OP_REG_GP
)))
4482 return 1 << insn_extract_operand (insn
, operand
);
4487 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4488 where bit N of OPNO_MASK is set if operand N should be included.
4489 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4493 insn_reg_mask (const struct mips_cl_insn
*insn
,
4494 unsigned int type_mask
, unsigned int opno_mask
)
4496 unsigned int opno
, reg_mask
;
4500 while (opno_mask
!= 0)
4503 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4510 /* Return the mask of core registers that IP reads. */
4513 gpr_read_mask (const struct mips_cl_insn
*ip
)
4515 unsigned long pinfo
, pinfo2
;
4518 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4519 pinfo
= ip
->insn_mo
->pinfo
;
4520 pinfo2
= ip
->insn_mo
->pinfo2
;
4521 if (pinfo
& INSN_UDI
)
4523 /* UDI instructions have traditionally been assumed to read RS
4525 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4526 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4528 if (pinfo
& INSN_READ_GPR_24
)
4530 if (pinfo2
& INSN2_READ_GPR_16
)
4532 if (pinfo2
& INSN2_READ_SP
)
4534 if (pinfo2
& INSN2_READ_GPR_31
)
4536 /* Don't include register 0. */
4540 /* Return the mask of core registers that IP writes. */
4543 gpr_write_mask (const struct mips_cl_insn
*ip
)
4545 unsigned long pinfo
, pinfo2
;
4548 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4549 pinfo
= ip
->insn_mo
->pinfo
;
4550 pinfo2
= ip
->insn_mo
->pinfo2
;
4551 if (pinfo
& INSN_WRITE_GPR_24
)
4553 if (pinfo
& INSN_WRITE_GPR_31
)
4555 if (pinfo
& INSN_UDI
)
4556 /* UDI instructions have traditionally been assumed to write to RD. */
4557 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4558 if (pinfo2
& INSN2_WRITE_SP
)
4560 /* Don't include register 0. */
4564 /* Return the mask of floating-point registers that IP reads. */
4567 fpr_read_mask (const struct mips_cl_insn
*ip
)
4569 unsigned long pinfo
;
4572 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4573 | (1 << OP_REG_MSA
)),
4574 insn_read_mask (ip
->insn_mo
));
4575 pinfo
= ip
->insn_mo
->pinfo
;
4576 /* Conservatively treat all operands to an FP_D instruction are doubles.
4577 (This is overly pessimistic for things like cvt.d.s.) */
4578 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4583 /* Return the mask of floating-point registers that IP writes. */
4586 fpr_write_mask (const struct mips_cl_insn
*ip
)
4588 unsigned long pinfo
;
4591 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4592 | (1 << OP_REG_MSA
)),
4593 insn_write_mask (ip
->insn_mo
));
4594 pinfo
= ip
->insn_mo
->pinfo
;
4595 /* Conservatively treat all operands to an FP_D instruction are doubles.
4596 (This is overly pessimistic for things like cvt.s.d.) */
4597 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4602 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4603 Check whether that is allowed. */
4606 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4608 const char *s
= insn
->name
;
4609 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4611 && mips_opts
.oddspreg
;
4613 if (insn
->pinfo
== INSN_MACRO
)
4614 /* Let a macro pass, we'll catch it later when it is expanded. */
4617 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4618 otherwise it depends on oddspreg. */
4619 if ((insn
->pinfo
& FP_S
)
4620 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4621 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4622 return FPR_SIZE
== 32 || oddspreg
;
4624 /* Allow odd registers for single-precision ops and double-precision if the
4625 floating-point registers are 64-bit wide. */
4626 switch (insn
->pinfo
& (FP_S
| FP_D
))
4632 return FPR_SIZE
== 64;
4637 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4638 s
= strchr (insn
->name
, '.');
4639 if (s
!= NULL
&& opnum
== 2)
4640 s
= strchr (s
+ 1, '.');
4641 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4644 return FPR_SIZE
== 64;
4647 /* Information about an instruction argument that we're trying to match. */
4648 struct mips_arg_info
4650 /* The instruction so far. */
4651 struct mips_cl_insn
*insn
;
4653 /* The first unconsumed operand token. */
4654 struct mips_operand_token
*token
;
4656 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4659 /* The 1-based argument number, for error reporting. This does not
4660 count elided optional registers, etc.. */
4663 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4664 unsigned int last_regno
;
4666 /* If the first operand was an OP_REG, this is the register that it
4667 specified, otherwise it is ILLEGAL_REG. */
4668 unsigned int dest_regno
;
4670 /* The value of the last OP_INT operand. Only used for OP_MSB,
4671 where it gives the lsb position. */
4672 unsigned int last_op_int
;
4674 /* If true, match routines should assume that no later instruction
4675 alternative matches and should therefore be as accomodating as
4676 possible. Match routines should not report errors if something
4677 is only invalid for !LAX_MATCH. */
4678 bfd_boolean lax_match
;
4680 /* True if a reference to the current AT register was seen. */
4681 bfd_boolean seen_at
;
4684 /* Record that the argument is out of range. */
4687 match_out_of_range (struct mips_arg_info
*arg
)
4689 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4692 /* Record that the argument isn't constant but needs to be. */
4695 match_not_constant (struct mips_arg_info
*arg
)
4697 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4701 /* Try to match an OT_CHAR token for character CH. Consume the token
4702 and return true on success, otherwise return false. */
4705 match_char (struct mips_arg_info
*arg
, char ch
)
4707 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4717 /* Try to get an expression from the next tokens in ARG. Consume the
4718 tokens and return true on success, storing the expression value in
4719 VALUE and relocation types in R. */
4722 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4723 bfd_reloc_code_real_type
*r
)
4725 /* If the next token is a '(' that was parsed as being part of a base
4726 expression, assume we have an elided offset. The later match will fail
4727 if this turns out to be wrong. */
4728 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4730 value
->X_op
= O_constant
;
4731 value
->X_add_number
= 0;
4732 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4736 /* Reject register-based expressions such as "0+$2" and "(($2))".
4737 For plain registers the default error seems more appropriate. */
4738 if (arg
->token
->type
== OT_INTEGER
4739 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4741 set_insn_error (arg
->argnum
, _("register value used as expression"));
4745 if (arg
->token
->type
== OT_INTEGER
)
4747 *value
= arg
->token
->u
.integer
.value
;
4748 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4754 (arg
->argnum
, _("operand %d must be an immediate expression"),
4759 /* Try to get a constant expression from the next tokens in ARG. Consume
4760 the tokens and return return true on success, storing the constant value
4761 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4765 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4768 bfd_reloc_code_real_type r
[3];
4770 if (!match_expression (arg
, &ex
, r
))
4773 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4774 *value
= ex
.X_add_number
;
4777 match_not_constant (arg
);
4783 /* Return the RTYPE_* flags for a register operand of type TYPE that
4784 appears in instruction OPCODE. */
4787 convert_reg_type (const struct mips_opcode
*opcode
,
4788 enum mips_reg_operand_type type
)
4793 return RTYPE_NUM
| RTYPE_GP
;
4796 /* Allow vector register names for MDMX if the instruction is a 64-bit
4797 FPR load, store or move (including moves to and from GPRs). */
4798 if ((mips_opts
.ase
& ASE_MDMX
)
4799 && (opcode
->pinfo
& FP_D
)
4800 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4801 | INSN_COPROC_MEMORY_DELAY
4804 | INSN_STORE_MEMORY
)))
4805 return RTYPE_FPU
| RTYPE_VEC
;
4809 if (opcode
->pinfo
& (FP_D
| FP_S
))
4810 return RTYPE_CCC
| RTYPE_FCC
;
4814 if (opcode
->membership
& INSN_5400
)
4816 return RTYPE_FPU
| RTYPE_VEC
;
4822 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4823 return RTYPE_NUM
| RTYPE_CP0
;
4830 return RTYPE_NUM
| RTYPE_VI
;
4833 return RTYPE_NUM
| RTYPE_VF
;
4835 case OP_REG_R5900_I
:
4836 return RTYPE_R5900_I
;
4838 case OP_REG_R5900_Q
:
4839 return RTYPE_R5900_Q
;
4841 case OP_REG_R5900_R
:
4842 return RTYPE_R5900_R
;
4844 case OP_REG_R5900_ACC
:
4845 return RTYPE_R5900_ACC
;
4850 case OP_REG_MSA_CTRL
:
4856 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4859 check_regno (struct mips_arg_info
*arg
,
4860 enum mips_reg_operand_type type
, unsigned int regno
)
4862 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4863 arg
->seen_at
= TRUE
;
4865 if (type
== OP_REG_FP
4867 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4869 /* This was a warning prior to introducing O32 FPXX and FP64 support
4870 so maintain a warning for FP32 but raise an error for the new
4873 as_warn (_("float register should be even, was %d"), regno
);
4875 as_bad (_("float register should be even, was %d"), regno
);
4878 if (type
== OP_REG_CCC
)
4883 name
= arg
->insn
->insn_mo
->name
;
4884 length
= strlen (name
);
4885 if ((regno
& 1) != 0
4886 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4887 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4888 as_warn (_("condition code register should be even for %s, was %d"),
4891 if ((regno
& 3) != 0
4892 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4893 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4898 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4899 a register of type TYPE. Return true on success, storing the register
4900 number in *REGNO and warning about any dubious uses. */
4903 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4904 unsigned int symval
, unsigned int *regno
)
4906 if (type
== OP_REG_VEC
)
4907 symval
= mips_prefer_vec_regno (symval
);
4908 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4911 *regno
= symval
& RNUM_MASK
;
4912 check_regno (arg
, type
, *regno
);
4916 /* Try to interpret the next token in ARG as a register of type TYPE.
4917 Consume the token and return true on success, storing the register
4918 number in *REGNO. Return false on failure. */
4921 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4922 unsigned int *regno
)
4924 if (arg
->token
->type
== OT_REG
4925 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4933 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4934 Consume the token and return true on success, storing the register numbers
4935 in *REGNO1 and *REGNO2. Return false on failure. */
4938 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4939 unsigned int *regno1
, unsigned int *regno2
)
4941 if (match_reg (arg
, type
, regno1
))
4946 if (arg
->token
->type
== OT_REG_RANGE
4947 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4948 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4949 && *regno1
<= *regno2
)
4957 /* OP_INT matcher. */
4960 match_int_operand (struct mips_arg_info
*arg
,
4961 const struct mips_operand
*operand_base
)
4963 const struct mips_int_operand
*operand
;
4965 int min_val
, max_val
, factor
;
4968 operand
= (const struct mips_int_operand
*) operand_base
;
4969 factor
= 1 << operand
->shift
;
4970 min_val
= mips_int_operand_min (operand
);
4971 max_val
= mips_int_operand_max (operand
);
4973 if (operand_base
->lsb
== 0
4974 && operand_base
->size
== 16
4975 && operand
->shift
== 0
4976 && operand
->bias
== 0
4977 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4979 /* The operand can be relocated. */
4980 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4983 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4984 /* Relocation operators were used. Accept the arguent and
4985 leave the relocation value in offset_expr and offset_relocs
4986 for the caller to process. */
4989 if (offset_expr
.X_op
!= O_constant
)
4991 /* Accept non-constant operands if no later alternative matches,
4992 leaving it for the caller to process. */
4993 if (!arg
->lax_match
)
4995 offset_reloc
[0] = BFD_RELOC_LO16
;
4999 /* Clear the global state; we're going to install the operand
5001 sval
= offset_expr
.X_add_number
;
5002 offset_expr
.X_op
= O_absent
;
5004 /* For compatibility with older assemblers, we accept
5005 0x8000-0xffff as signed 16-bit numbers when only
5006 signed numbers are allowed. */
5009 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5010 if (!arg
->lax_match
&& sval
<= max_val
)
5016 if (!match_const_int (arg
, &sval
))
5020 arg
->last_op_int
= sval
;
5022 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5024 match_out_of_range (arg
);
5028 uval
= (unsigned int) sval
>> operand
->shift
;
5029 uval
-= operand
->bias
;
5031 /* Handle -mfix-cn63xxp1. */
5033 && mips_fix_cn63xxp1
5034 && !mips_opts
.micromips
5035 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5050 /* The rest must be changed to 28. */
5055 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5059 /* OP_MAPPED_INT matcher. */
5062 match_mapped_int_operand (struct mips_arg_info
*arg
,
5063 const struct mips_operand
*operand_base
)
5065 const struct mips_mapped_int_operand
*operand
;
5066 unsigned int uval
, num_vals
;
5069 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5070 if (!match_const_int (arg
, &sval
))
5073 num_vals
= 1 << operand_base
->size
;
5074 for (uval
= 0; uval
< num_vals
; uval
++)
5075 if (operand
->int_map
[uval
] == sval
)
5077 if (uval
== num_vals
)
5079 match_out_of_range (arg
);
5083 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5087 /* OP_MSB matcher. */
5090 match_msb_operand (struct mips_arg_info
*arg
,
5091 const struct mips_operand
*operand_base
)
5093 const struct mips_msb_operand
*operand
;
5094 int min_val
, max_val
, max_high
;
5095 offsetT size
, sval
, high
;
5097 operand
= (const struct mips_msb_operand
*) operand_base
;
5098 min_val
= operand
->bias
;
5099 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5100 max_high
= operand
->opsize
;
5102 if (!match_const_int (arg
, &size
))
5105 high
= size
+ arg
->last_op_int
;
5106 sval
= operand
->add_lsb
? high
: size
;
5108 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5110 match_out_of_range (arg
);
5113 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5117 /* OP_REG matcher. */
5120 match_reg_operand (struct mips_arg_info
*arg
,
5121 const struct mips_operand
*operand_base
)
5123 const struct mips_reg_operand
*operand
;
5124 unsigned int regno
, uval
, num_vals
;
5126 operand
= (const struct mips_reg_operand
*) operand_base
;
5127 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5130 if (operand
->reg_map
)
5132 num_vals
= 1 << operand
->root
.size
;
5133 for (uval
= 0; uval
< num_vals
; uval
++)
5134 if (operand
->reg_map
[uval
] == regno
)
5136 if (num_vals
== uval
)
5142 arg
->last_regno
= regno
;
5143 if (arg
->opnum
== 1)
5144 arg
->dest_regno
= regno
;
5145 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5149 /* OP_REG_PAIR matcher. */
5152 match_reg_pair_operand (struct mips_arg_info
*arg
,
5153 const struct mips_operand
*operand_base
)
5155 const struct mips_reg_pair_operand
*operand
;
5156 unsigned int regno1
, regno2
, uval
, num_vals
;
5158 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5159 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5160 || !match_char (arg
, ',')
5161 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5164 num_vals
= 1 << operand_base
->size
;
5165 for (uval
= 0; uval
< num_vals
; uval
++)
5166 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5168 if (uval
== num_vals
)
5171 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5175 /* OP_PCREL matcher. The caller chooses the relocation type. */
5178 match_pcrel_operand (struct mips_arg_info
*arg
)
5180 bfd_reloc_code_real_type r
[3];
5182 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5185 /* OP_PERF_REG matcher. */
5188 match_perf_reg_operand (struct mips_arg_info
*arg
,
5189 const struct mips_operand
*operand
)
5193 if (!match_const_int (arg
, &sval
))
5198 || (mips_opts
.arch
== CPU_R5900
5199 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5200 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5202 set_insn_error (arg
->argnum
, _("invalid performance register"));
5206 insn_insert_operand (arg
->insn
, operand
, sval
);
5210 /* OP_ADDIUSP matcher. */
5213 match_addiusp_operand (struct mips_arg_info
*arg
,
5214 const struct mips_operand
*operand
)
5219 if (!match_const_int (arg
, &sval
))
5224 match_out_of_range (arg
);
5229 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5231 match_out_of_range (arg
);
5235 uval
= (unsigned int) sval
;
5236 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5237 insn_insert_operand (arg
->insn
, operand
, uval
);
5241 /* OP_CLO_CLZ_DEST matcher. */
5244 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5245 const struct mips_operand
*operand
)
5249 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5252 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5256 /* OP_CHECK_PREV matcher. */
5259 match_check_prev_operand (struct mips_arg_info
*arg
,
5260 const struct mips_operand
*operand_base
)
5262 const struct mips_check_prev_operand
*operand
;
5265 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5267 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5270 if (!operand
->zero_ok
&& regno
== 0)
5273 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5274 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5275 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5277 arg
->last_regno
= regno
;
5278 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5285 /* OP_SAME_RS_RT matcher. */
5288 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5289 const struct mips_operand
*operand
)
5293 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5298 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5302 arg
->last_regno
= regno
;
5304 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5308 /* OP_LWM_SWM_LIST matcher. */
5311 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5312 const struct mips_operand
*operand
)
5314 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5315 struct mips_arg_info reset
;
5318 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5322 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5327 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5330 while (match_char (arg
, ',')
5331 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5334 if (operand
->size
== 2)
5336 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5342 and any permutations of these. */
5343 if ((reglist
& 0xfff1ffff) != 0x80010000)
5346 sregs
= (reglist
>> 17) & 7;
5351 /* The list must include at least one of ra and s0-sN,
5352 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5353 which are $23 and $30 respectively.) E.g.:
5361 and any permutations of these. */
5362 if ((reglist
& 0x3f00ffff) != 0)
5365 ra
= (reglist
>> 27) & 0x10;
5366 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5369 if ((sregs
& -sregs
) != sregs
)
5372 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5376 /* OP_ENTRY_EXIT_LIST matcher. */
5379 match_entry_exit_operand (struct mips_arg_info
*arg
,
5380 const struct mips_operand
*operand
)
5383 bfd_boolean is_exit
;
5385 /* The format is the same for both ENTRY and EXIT, but the constraints
5387 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5388 mask
= (is_exit
? 7 << 3 : 0);
5391 unsigned int regno1
, regno2
;
5392 bfd_boolean is_freg
;
5394 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5396 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5401 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5404 mask
|= (5 + regno2
) << 3;
5406 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5407 mask
|= (regno2
- 3) << 3;
5408 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5409 mask
|= (regno2
- 15) << 1;
5410 else if (regno1
== RA
&& regno2
== RA
)
5415 while (match_char (arg
, ','));
5417 insn_insert_operand (arg
->insn
, operand
, mask
);
5421 /* OP_SAVE_RESTORE_LIST matcher. */
5424 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5426 unsigned int opcode
, args
, statics
, sregs
;
5427 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5430 opcode
= arg
->insn
->insn_opcode
;
5432 num_frame_sizes
= 0;
5438 unsigned int regno1
, regno2
;
5440 if (arg
->token
->type
== OT_INTEGER
)
5442 /* Handle the frame size. */
5443 if (!match_const_int (arg
, &frame_size
))
5445 num_frame_sizes
+= 1;
5449 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5452 while (regno1
<= regno2
)
5454 if (regno1
>= 4 && regno1
<= 7)
5456 if (num_frame_sizes
== 0)
5458 args
|= 1 << (regno1
- 4);
5460 /* statics $a0-$a3 */
5461 statics
|= 1 << (regno1
- 4);
5463 else if (regno1
>= 16 && regno1
<= 23)
5465 sregs
|= 1 << (regno1
- 16);
5466 else if (regno1
== 30)
5469 else if (regno1
== 31)
5470 /* Add $ra to insn. */
5480 while (match_char (arg
, ','));
5482 /* Encode args/statics combination. */
5485 else if (args
== 0xf)
5486 /* All $a0-$a3 are args. */
5487 opcode
|= MIPS16_ALL_ARGS
<< 16;
5488 else if (statics
== 0xf)
5489 /* All $a0-$a3 are statics. */
5490 opcode
|= MIPS16_ALL_STATICS
<< 16;
5493 /* Count arg registers. */
5503 /* Count static registers. */
5505 while (statics
& 0x8)
5507 statics
= (statics
<< 1) & 0xf;
5513 /* Encode args/statics. */
5514 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5517 /* Encode $s0/$s1. */
5518 if (sregs
& (1 << 0)) /* $s0 */
5520 if (sregs
& (1 << 1)) /* $s1 */
5524 /* Encode $s2-$s8. */
5533 opcode
|= num_sregs
<< 24;
5535 /* Encode frame size. */
5536 if (num_frame_sizes
== 0)
5538 set_insn_error (arg
->argnum
, _("missing frame size"));
5541 if (num_frame_sizes
> 1)
5543 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5546 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5548 set_insn_error (arg
->argnum
, _("invalid frame size"));
5551 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5554 opcode
|= (((frame_size
& 0xf0) << 16)
5555 | (frame_size
& 0x0f));
5558 /* Finally build the instruction. */
5559 if ((opcode
>> 16) != 0 || frame_size
== 0)
5560 opcode
|= MIPS16_EXTEND
;
5561 arg
->insn
->insn_opcode
= opcode
;
5565 /* OP_MDMX_IMM_REG matcher. */
5568 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5569 const struct mips_operand
*operand
)
5571 unsigned int regno
, uval
;
5573 const struct mips_opcode
*opcode
;
5575 /* The mips_opcode records whether this is an octobyte or quadhalf
5576 instruction. Start out with that bit in place. */
5577 opcode
= arg
->insn
->insn_mo
;
5578 uval
= mips_extract_operand (operand
, opcode
->match
);
5579 is_qh
= (uval
!= 0);
5581 if (arg
->token
->type
== OT_REG
)
5583 if ((opcode
->membership
& INSN_5400
)
5584 && strcmp (opcode
->name
, "rzu.ob") == 0)
5586 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5591 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5595 /* Check whether this is a vector register or a broadcast of
5596 a single element. */
5597 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5599 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5601 set_insn_error (arg
->argnum
, _("invalid element selector"));
5604 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5609 /* A full vector. */
5610 if ((opcode
->membership
& INSN_5400
)
5611 && (strcmp (opcode
->name
, "sll.ob") == 0
5612 || strcmp (opcode
->name
, "srl.ob") == 0))
5614 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5620 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5622 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5630 if (!match_const_int (arg
, &sval
))
5632 if (sval
< 0 || sval
> 31)
5634 match_out_of_range (arg
);
5637 uval
|= (sval
& 31);
5639 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5641 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5643 insn_insert_operand (arg
->insn
, operand
, uval
);
5647 /* OP_IMM_INDEX matcher. */
5650 match_imm_index_operand (struct mips_arg_info
*arg
,
5651 const struct mips_operand
*operand
)
5653 unsigned int max_val
;
5655 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5658 max_val
= (1 << operand
->size
) - 1;
5659 if (arg
->token
->u
.index
> max_val
)
5661 match_out_of_range (arg
);
5664 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5669 /* OP_REG_INDEX matcher. */
5672 match_reg_index_operand (struct mips_arg_info
*arg
,
5673 const struct mips_operand
*operand
)
5677 if (arg
->token
->type
!= OT_REG_INDEX
)
5680 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5683 insn_insert_operand (arg
->insn
, operand
, regno
);
5688 /* OP_PC matcher. */
5691 match_pc_operand (struct mips_arg_info
*arg
)
5693 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5701 /* OP_NON_ZERO_REG matcher. */
5704 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5705 const struct mips_operand
*operand
)
5709 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5715 arg
->last_regno
= regno
;
5716 insn_insert_operand (arg
->insn
, operand
, regno
);
5720 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5721 register that we need to match. */
5724 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5728 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5731 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5732 the length of the value in bytes (4 for float, 8 for double) and
5733 USING_GPRS says whether the destination is a GPR rather than an FPR.
5735 Return the constant in IMM and OFFSET as follows:
5737 - If the constant should be loaded via memory, set IMM to O_absent and
5738 OFFSET to the memory address.
5740 - Otherwise, if the constant should be loaded into two 32-bit registers,
5741 set IMM to the O_constant to load into the high register and OFFSET
5742 to the corresponding value for the low register.
5744 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5746 These constants only appear as the last operand in an instruction,
5747 and every instruction that accepts them in any variant accepts them
5748 in all variants. This means we don't have to worry about backing out
5749 any changes if the instruction does not match. We just match
5750 unconditionally and report an error if the constant is invalid. */
5753 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5754 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5759 const char *newname
;
5760 unsigned char *data
;
5762 /* Where the constant is placed is based on how the MIPS assembler
5765 length == 4 && using_gprs -- immediate value only
5766 length == 8 && using_gprs -- .rdata or immediate value
5767 length == 4 && !using_gprs -- .lit4 or immediate value
5768 length == 8 && !using_gprs -- .lit8 or immediate value
5770 The .lit4 and .lit8 sections are only used if permitted by the
5772 if (arg
->token
->type
!= OT_FLOAT
)
5774 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5778 gas_assert (arg
->token
->u
.flt
.length
== length
);
5779 data
= arg
->token
->u
.flt
.data
;
5782 /* Handle 32-bit constants for which an immediate value is best. */
5785 || g_switch_value
< 4
5786 || (data
[0] == 0 && data
[1] == 0)
5787 || (data
[2] == 0 && data
[3] == 0)))
5789 imm
->X_op
= O_constant
;
5790 if (!target_big_endian
)
5791 imm
->X_add_number
= bfd_getl32 (data
);
5793 imm
->X_add_number
= bfd_getb32 (data
);
5794 offset
->X_op
= O_absent
;
5798 /* Handle 64-bit constants for which an immediate value is best. */
5800 && !mips_disable_float_construction
5801 /* Constants can only be constructed in GPRs and copied to FPRs if the
5802 GPRs are at least as wide as the FPRs or MTHC1 is available.
5803 Unlike most tests for 32-bit floating-point registers this check
5804 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5805 permit 64-bit moves without MXHC1.
5806 Force the constant into memory otherwise. */
5809 || ISA_HAS_MXHC1 (mips_opts
.isa
)
5811 && ((data
[0] == 0 && data
[1] == 0)
5812 || (data
[2] == 0 && data
[3] == 0))
5813 && ((data
[4] == 0 && data
[5] == 0)
5814 || (data
[6] == 0 && data
[7] == 0)))
5816 /* The value is simple enough to load with a couple of instructions.
5817 If using 32-bit registers, set IMM to the high order 32 bits and
5818 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5820 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
5822 imm
->X_op
= O_constant
;
5823 offset
->X_op
= O_constant
;
5824 if (!target_big_endian
)
5826 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5827 offset
->X_add_number
= bfd_getl32 (data
);
5831 imm
->X_add_number
= bfd_getb32 (data
);
5832 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5834 if (offset
->X_add_number
== 0)
5835 offset
->X_op
= O_absent
;
5839 imm
->X_op
= O_constant
;
5840 if (!target_big_endian
)
5841 imm
->X_add_number
= bfd_getl64 (data
);
5843 imm
->X_add_number
= bfd_getb64 (data
);
5844 offset
->X_op
= O_absent
;
5849 /* Switch to the right section. */
5851 subseg
= now_subseg
;
5854 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5859 if (using_gprs
|| g_switch_value
< 8)
5860 newname
= RDATA_SECTION_NAME
;
5865 new_seg
= subseg_new (newname
, (subsegT
) 0);
5866 bfd_set_section_flags (stdoutput
, new_seg
,
5867 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5868 frag_align (length
== 4 ? 2 : 3, 0, 0);
5869 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5870 record_alignment (new_seg
, 4);
5872 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5874 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5876 /* Set the argument to the current address in the section. */
5877 imm
->X_op
= O_absent
;
5878 offset
->X_op
= O_symbol
;
5879 offset
->X_add_symbol
= symbol_temp_new_now ();
5880 offset
->X_add_number
= 0;
5882 /* Put the floating point number into the section. */
5883 p
= frag_more (length
);
5884 memcpy (p
, data
, length
);
5886 /* Switch back to the original section. */
5887 subseg_set (seg
, subseg
);
5891 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5895 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5896 const struct mips_operand
*operand
,
5897 bfd_boolean match_p
)
5901 /* The operand can be an XYZW mask or a single 2-bit channel index
5902 (with X being 0). */
5903 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5905 /* The suffix can be omitted when it is already part of the opcode. */
5906 if (arg
->token
->type
!= OT_CHANNELS
)
5909 uval
= arg
->token
->u
.channels
;
5910 if (operand
->size
== 2)
5912 /* Check that a single bit is set and convert it into a 2-bit index. */
5913 if ((uval
& -uval
) != uval
)
5915 uval
= 4 - ffs (uval
);
5918 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5923 insn_insert_operand (arg
->insn
, operand
, uval
);
5927 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5928 of the argument text if the match is successful, otherwise return null. */
5931 match_operand (struct mips_arg_info
*arg
,
5932 const struct mips_operand
*operand
)
5934 switch (operand
->type
)
5937 return match_int_operand (arg
, operand
);
5940 return match_mapped_int_operand (arg
, operand
);
5943 return match_msb_operand (arg
, operand
);
5946 case OP_OPTIONAL_REG
:
5947 return match_reg_operand (arg
, operand
);
5950 return match_reg_pair_operand (arg
, operand
);
5953 return match_pcrel_operand (arg
);
5956 return match_perf_reg_operand (arg
, operand
);
5958 case OP_ADDIUSP_INT
:
5959 return match_addiusp_operand (arg
, operand
);
5961 case OP_CLO_CLZ_DEST
:
5962 return match_clo_clz_dest_operand (arg
, operand
);
5964 case OP_LWM_SWM_LIST
:
5965 return match_lwm_swm_list_operand (arg
, operand
);
5967 case OP_ENTRY_EXIT_LIST
:
5968 return match_entry_exit_operand (arg
, operand
);
5970 case OP_SAVE_RESTORE_LIST
:
5971 return match_save_restore_list_operand (arg
);
5973 case OP_MDMX_IMM_REG
:
5974 return match_mdmx_imm_reg_operand (arg
, operand
);
5976 case OP_REPEAT_DEST_REG
:
5977 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5979 case OP_REPEAT_PREV_REG
:
5980 return match_tied_reg_operand (arg
, arg
->last_regno
);
5983 return match_pc_operand (arg
);
5986 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5988 case OP_VU0_MATCH_SUFFIX
:
5989 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5992 return match_imm_index_operand (arg
, operand
);
5995 return match_reg_index_operand (arg
, operand
);
5998 return match_same_rs_rt_operand (arg
, operand
);
6001 return match_check_prev_operand (arg
, operand
);
6003 case OP_NON_ZERO_REG
:
6004 return match_non_zero_reg_operand (arg
, operand
);
6009 /* ARG is the state after successfully matching an instruction.
6010 Issue any queued-up warnings. */
6013 check_completed_insn (struct mips_arg_info
*arg
)
6018 as_warn (_("used $at without \".set noat\""));
6020 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6024 /* Return true if modifying general-purpose register REG needs a delay. */
6027 reg_needs_delay (unsigned int reg
)
6029 unsigned long prev_pinfo
;
6031 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6032 if (!mips_opts
.noreorder
6033 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6034 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6035 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6041 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6042 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6043 by VR4120 errata. */
6046 classify_vr4120_insn (const char *name
)
6048 if (strncmp (name
, "macc", 4) == 0)
6049 return FIX_VR4120_MACC
;
6050 if (strncmp (name
, "dmacc", 5) == 0)
6051 return FIX_VR4120_DMACC
;
6052 if (strncmp (name
, "mult", 4) == 0)
6053 return FIX_VR4120_MULT
;
6054 if (strncmp (name
, "dmult", 5) == 0)
6055 return FIX_VR4120_DMULT
;
6056 if (strstr (name
, "div"))
6057 return FIX_VR4120_DIV
;
6058 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6059 return FIX_VR4120_MTHILO
;
6060 return NUM_FIX_VR4120_CLASSES
;
6063 #define INSN_ERET 0x42000018
6064 #define INSN_DERET 0x4200001f
6065 #define INSN_DMULT 0x1c
6066 #define INSN_DMULTU 0x1d
6068 /* Return the number of instructions that must separate INSN1 and INSN2,
6069 where INSN1 is the earlier instruction. Return the worst-case value
6070 for any INSN2 if INSN2 is null. */
6073 insns_between (const struct mips_cl_insn
*insn1
,
6074 const struct mips_cl_insn
*insn2
)
6076 unsigned long pinfo1
, pinfo2
;
6079 /* If INFO2 is null, pessimistically assume that all flags are set for
6080 the second instruction. */
6081 pinfo1
= insn1
->insn_mo
->pinfo
;
6082 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6084 /* For most targets, write-after-read dependencies on the HI and LO
6085 registers must be separated by at least two instructions. */
6086 if (!hilo_interlocks
)
6088 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6090 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6094 /* If we're working around r7000 errata, there must be two instructions
6095 between an mfhi or mflo and any instruction that uses the result. */
6096 if (mips_7000_hilo_fix
6097 && !mips_opts
.micromips
6098 && MF_HILO_INSN (pinfo1
)
6099 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6102 /* If we're working around 24K errata, one instruction is required
6103 if an ERET or DERET is followed by a branch instruction. */
6104 if (mips_fix_24k
&& !mips_opts
.micromips
)
6106 if (insn1
->insn_opcode
== INSN_ERET
6107 || insn1
->insn_opcode
== INSN_DERET
)
6110 || insn2
->insn_opcode
== INSN_ERET
6111 || insn2
->insn_opcode
== INSN_DERET
6112 || delayed_branch_p (insn2
))
6117 /* If we're working around PMC RM7000 errata, there must be three
6118 nops between a dmult and a load instruction. */
6119 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6121 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6122 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6124 if (pinfo2
& INSN_LOAD_MEMORY
)
6129 /* If working around VR4120 errata, check for combinations that need
6130 a single intervening instruction. */
6131 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6133 unsigned int class1
, class2
;
6135 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6136 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6140 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6141 if (vr4120_conflicts
[class1
] & (1 << class2
))
6146 if (!HAVE_CODE_COMPRESSION
)
6148 /* Check for GPR or coprocessor load delays. All such delays
6149 are on the RT register. */
6150 /* Itbl support may require additional care here. */
6151 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6152 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6154 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6158 /* Check for generic coprocessor hazards.
6160 This case is not handled very well. There is no special
6161 knowledge of CP0 handling, and the coprocessors other than
6162 the floating point unit are not distinguished at all. */
6163 /* Itbl support may require additional care here. FIXME!
6164 Need to modify this to include knowledge about
6165 user specified delays! */
6166 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6167 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6169 /* Handle cases where INSN1 writes to a known general coprocessor
6170 register. There must be a one instruction delay before INSN2
6171 if INSN2 reads that register, otherwise no delay is needed. */
6172 mask
= fpr_write_mask (insn1
);
6175 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6180 /* Read-after-write dependencies on the control registers
6181 require a two-instruction gap. */
6182 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6183 && (pinfo2
& INSN_READ_COND_CODE
))
6186 /* We don't know exactly what INSN1 does. If INSN2 is
6187 also a coprocessor instruction, assume there must be
6188 a one instruction gap. */
6189 if (pinfo2
& INSN_COP
)
6194 /* Check for read-after-write dependencies on the coprocessor
6195 control registers in cases where INSN1 does not need a general
6196 coprocessor delay. This means that INSN1 is a floating point
6197 comparison instruction. */
6198 /* Itbl support may require additional care here. */
6199 else if (!cop_interlocks
6200 && (pinfo1
& INSN_WRITE_COND_CODE
)
6201 && (pinfo2
& INSN_READ_COND_CODE
))
6205 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6206 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6208 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6209 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6210 || (insn2
&& delayed_branch_p (insn2
))))
6216 /* Return the number of nops that would be needed to work around the
6217 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6218 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6219 that are contained within the first IGNORE instructions of HIST. */
6222 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6223 const struct mips_cl_insn
*insn
)
6228 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6229 are not affected by the errata. */
6231 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6232 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6233 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6236 /* Search for the first MFLO or MFHI. */
6237 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6238 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6240 /* Extract the destination register. */
6241 mask
= gpr_write_mask (&hist
[i
]);
6243 /* No nops are needed if INSN reads that register. */
6244 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6247 /* ...or if any of the intervening instructions do. */
6248 for (j
= 0; j
< i
; j
++)
6249 if (gpr_read_mask (&hist
[j
]) & mask
)
6253 return MAX_VR4130_NOPS
- i
;
6258 #define BASE_REG_EQ(INSN1, INSN2) \
6259 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6260 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6262 /* Return the minimum alignment for this store instruction. */
6265 fix_24k_align_to (const struct mips_opcode
*mo
)
6267 if (strcmp (mo
->name
, "sh") == 0)
6270 if (strcmp (mo
->name
, "swc1") == 0
6271 || strcmp (mo
->name
, "swc2") == 0
6272 || strcmp (mo
->name
, "sw") == 0
6273 || strcmp (mo
->name
, "sc") == 0
6274 || strcmp (mo
->name
, "s.s") == 0)
6277 if (strcmp (mo
->name
, "sdc1") == 0
6278 || strcmp (mo
->name
, "sdc2") == 0
6279 || strcmp (mo
->name
, "s.d") == 0)
6286 struct fix_24k_store_info
6288 /* Immediate offset, if any, for this store instruction. */
6290 /* Alignment required by this store instruction. */
6292 /* True for register offsets. */
6293 int register_offset
;
6296 /* Comparison function used by qsort. */
6299 fix_24k_sort (const void *a
, const void *b
)
6301 const struct fix_24k_store_info
*pos1
= a
;
6302 const struct fix_24k_store_info
*pos2
= b
;
6304 return (pos1
->off
- pos2
->off
);
6307 /* INSN is a store instruction. Try to record the store information
6308 in STINFO. Return false if the information isn't known. */
6311 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6312 const struct mips_cl_insn
*insn
)
6314 /* The instruction must have a known offset. */
6315 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6318 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6319 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6323 /* Return the number of nops that would be needed to work around the 24k
6324 "lost data on stores during refill" errata if instruction INSN
6325 immediately followed the 2 instructions described by HIST.
6326 Ignore hazards that are contained within the first IGNORE
6327 instructions of HIST.
6329 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6330 for the data cache refills and store data. The following describes
6331 the scenario where the store data could be lost.
6333 * A data cache miss, due to either a load or a store, causing fill
6334 data to be supplied by the memory subsystem
6335 * The first three doublewords of fill data are returned and written
6337 * A sequence of four stores occurs in consecutive cycles around the
6338 final doubleword of the fill:
6342 * Zero, One or more instructions
6345 The four stores A-D must be to different doublewords of the line that
6346 is being filled. The fourth instruction in the sequence above permits
6347 the fill of the final doubleword to be transferred from the FSB into
6348 the cache. In the sequence above, the stores may be either integer
6349 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6350 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6351 different doublewords on the line. If the floating point unit is
6352 running in 1:2 mode, it is not possible to create the sequence above
6353 using only floating point store instructions.
6355 In this case, the cache line being filled is incorrectly marked
6356 invalid, thereby losing the data from any store to the line that
6357 occurs between the original miss and the completion of the five
6358 cycle sequence shown above.
6360 The workarounds are:
6362 * Run the data cache in write-through mode.
6363 * Insert a non-store instruction between
6364 Store A and Store B or Store B and Store C. */
6367 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6368 const struct mips_cl_insn
*insn
)
6370 struct fix_24k_store_info pos
[3];
6371 int align
, i
, base_offset
;
6376 /* If the previous instruction wasn't a store, there's nothing to
6378 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6381 /* If the instructions after the previous one are unknown, we have
6382 to assume the worst. */
6386 /* Check whether we are dealing with three consecutive stores. */
6387 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6388 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6391 /* If we don't know the relationship between the store addresses,
6392 assume the worst. */
6393 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6394 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6397 if (!fix_24k_record_store_info (&pos
[0], insn
)
6398 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6399 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6402 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6404 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6405 X bytes and such that the base register + X is known to be aligned
6408 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6412 align
= pos
[0].align_to
;
6413 base_offset
= pos
[0].off
;
6414 for (i
= 1; i
< 3; i
++)
6415 if (align
< pos
[i
].align_to
)
6417 align
= pos
[i
].align_to
;
6418 base_offset
= pos
[i
].off
;
6420 for (i
= 0; i
< 3; i
++)
6421 pos
[i
].off
-= base_offset
;
6424 pos
[0].off
&= ~align
+ 1;
6425 pos
[1].off
&= ~align
+ 1;
6426 pos
[2].off
&= ~align
+ 1;
6428 /* If any two stores write to the same chunk, they also write to the
6429 same doubleword. The offsets are still sorted at this point. */
6430 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6433 /* A range of at least 9 bytes is needed for the stores to be in
6434 non-overlapping doublewords. */
6435 if (pos
[2].off
- pos
[0].off
<= 8)
6438 if (pos
[2].off
- pos
[1].off
>= 24
6439 || pos
[1].off
- pos
[0].off
>= 24
6440 || pos
[2].off
- pos
[0].off
>= 32)
6446 /* Return the number of nops that would be needed if instruction INSN
6447 immediately followed the MAX_NOPS instructions given by HIST,
6448 where HIST[0] is the most recent instruction. Ignore hazards
6449 between INSN and the first IGNORE instructions in HIST.
6451 If INSN is null, return the worse-case number of nops for any
6455 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6456 const struct mips_cl_insn
*insn
)
6458 int i
, nops
, tmp_nops
;
6461 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6463 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6464 if (tmp_nops
> nops
)
6468 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6470 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6471 if (tmp_nops
> nops
)
6475 if (mips_fix_24k
&& !mips_opts
.micromips
)
6477 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6478 if (tmp_nops
> nops
)
6485 /* The variable arguments provide NUM_INSNS extra instructions that
6486 might be added to HIST. Return the largest number of nops that
6487 would be needed after the extended sequence, ignoring hazards
6488 in the first IGNORE instructions. */
6491 nops_for_sequence (int num_insns
, int ignore
,
6492 const struct mips_cl_insn
*hist
, ...)
6495 struct mips_cl_insn buffer
[MAX_NOPS
];
6496 struct mips_cl_insn
*cursor
;
6499 va_start (args
, hist
);
6500 cursor
= buffer
+ num_insns
;
6501 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6502 while (cursor
> buffer
)
6503 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6505 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6510 /* Like nops_for_insn, but if INSN is a branch, take into account the
6511 worst-case delay for the branch target. */
6514 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6515 const struct mips_cl_insn
*insn
)
6519 nops
= nops_for_insn (ignore
, hist
, insn
);
6520 if (delayed_branch_p (insn
))
6522 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6523 hist
, insn
, get_delay_slot_nop (insn
));
6524 if (tmp_nops
> nops
)
6527 else if (compact_branch_p (insn
))
6529 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6530 if (tmp_nops
> nops
)
6536 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6539 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6541 gas_assert (!HAVE_CODE_COMPRESSION
);
6542 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6543 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6546 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6547 jr target pc &= 'hffff_ffff_cfff_ffff. */
6550 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6552 gas_assert (!HAVE_CODE_COMPRESSION
);
6553 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6554 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6555 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6563 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6564 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6567 ep
.X_op
= O_constant
;
6568 ep
.X_add_number
= 0xcfff0000;
6569 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6570 ep
.X_add_number
= 0xffff;
6571 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6572 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6577 fix_loongson2f (struct mips_cl_insn
* ip
)
6579 if (mips_fix_loongson2f_nop
)
6580 fix_loongson2f_nop (ip
);
6582 if (mips_fix_loongson2f_jump
)
6583 fix_loongson2f_jump (ip
);
6586 /* IP is a branch that has a delay slot, and we need to fill it
6587 automatically. Return true if we can do that by swapping IP
6588 with the previous instruction.
6589 ADDRESS_EXPR is an operand of the instruction to be used with
6593 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6594 bfd_reloc_code_real_type
*reloc_type
)
6596 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6597 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6598 unsigned int fpr_read
, prev_fpr_write
;
6600 /* -O2 and above is required for this optimization. */
6601 if (mips_optimize
< 2)
6604 /* If we have seen .set volatile or .set nomove, don't optimize. */
6605 if (mips_opts
.nomove
)
6608 /* We can't swap if the previous instruction's position is fixed. */
6609 if (history
[0].fixed_p
)
6612 /* If the previous previous insn was in a .set noreorder, we can't
6613 swap. Actually, the MIPS assembler will swap in this situation.
6614 However, gcc configured -with-gnu-as will generate code like
6622 in which we can not swap the bne and INSN. If gcc is not configured
6623 -with-gnu-as, it does not output the .set pseudo-ops. */
6624 if (history
[1].noreorder_p
)
6627 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6628 This means that the previous instruction was a 4-byte one anyhow. */
6629 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6632 /* If the branch is itself the target of a branch, we can not swap.
6633 We cheat on this; all we check for is whether there is a label on
6634 this instruction. If there are any branches to anything other than
6635 a label, users must use .set noreorder. */
6636 if (seg_info (now_seg
)->label_list
)
6639 /* If the previous instruction is in a variant frag other than this
6640 branch's one, we cannot do the swap. This does not apply to
6641 MIPS16 code, which uses variant frags for different purposes. */
6642 if (!mips_opts
.mips16
6644 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6647 /* We do not swap with instructions that cannot architecturally
6648 be placed in a branch delay slot, such as SYNC or ERET. We
6649 also refrain from swapping with a trap instruction, since it
6650 complicates trap handlers to have the trap instruction be in
6652 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6653 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6656 /* Check for conflicts between the branch and the instructions
6657 before the candidate delay slot. */
6658 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6661 /* Check for conflicts between the swapped sequence and the
6662 target of the branch. */
6663 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6666 /* If the branch reads a register that the previous
6667 instruction sets, we can not swap. */
6668 gpr_read
= gpr_read_mask (ip
);
6669 prev_gpr_write
= gpr_write_mask (&history
[0]);
6670 if (gpr_read
& prev_gpr_write
)
6673 fpr_read
= fpr_read_mask (ip
);
6674 prev_fpr_write
= fpr_write_mask (&history
[0]);
6675 if (fpr_read
& prev_fpr_write
)
6678 /* If the branch writes a register that the previous
6679 instruction sets, we can not swap. */
6680 gpr_write
= gpr_write_mask (ip
);
6681 if (gpr_write
& prev_gpr_write
)
6684 /* If the branch writes a register that the previous
6685 instruction reads, we can not swap. */
6686 prev_gpr_read
= gpr_read_mask (&history
[0]);
6687 if (gpr_write
& prev_gpr_read
)
6690 /* If one instruction sets a condition code and the
6691 other one uses a condition code, we can not swap. */
6692 pinfo
= ip
->insn_mo
->pinfo
;
6693 if ((pinfo
& INSN_READ_COND_CODE
)
6694 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6696 if ((pinfo
& INSN_WRITE_COND_CODE
)
6697 && (prev_pinfo
& INSN_READ_COND_CODE
))
6700 /* If the previous instruction uses the PC, we can not swap. */
6701 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6702 if (prev_pinfo2
& INSN2_READ_PC
)
6705 /* If the previous instruction has an incorrect size for a fixed
6706 branch delay slot in microMIPS mode, we cannot swap. */
6707 pinfo2
= ip
->insn_mo
->pinfo2
;
6708 if (mips_opts
.micromips
6709 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6710 && insn_length (history
) != 2)
6712 if (mips_opts
.micromips
6713 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6714 && insn_length (history
) != 4)
6717 /* On R5900 short loops need to be fixed by inserting a nop in
6718 the branch delay slots.
6719 A short loop can be terminated too early. */
6720 if (mips_opts
.arch
== CPU_R5900
6721 /* Check if instruction has a parameter, ignore "j $31". */
6722 && (address_expr
!= NULL
)
6723 /* Parameter must be 16 bit. */
6724 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6725 /* Branch to same segment. */
6726 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6727 /* Branch to same code fragment. */
6728 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6729 /* Can only calculate branch offset if value is known. */
6730 && symbol_constant_p(address_expr
->X_add_symbol
)
6731 /* Check if branch is really conditional. */
6732 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6733 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6734 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6737 /* Check if loop is shorter than 6 instructions including
6738 branch and delay slot. */
6739 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6746 /* When the loop includes branches or jumps,
6747 it is not a short loop. */
6748 for (i
= 0; i
< (distance
/ 4); i
++)
6750 if ((history
[i
].cleared_p
)
6751 || delayed_branch_p(&history
[i
]))
6759 /* Insert nop after branch to fix short loop. */
6768 /* Decide how we should add IP to the instruction stream.
6769 ADDRESS_EXPR is an operand of the instruction to be used with
6772 static enum append_method
6773 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6774 bfd_reloc_code_real_type
*reloc_type
)
6776 /* The relaxed version of a macro sequence must be inherently
6778 if (mips_relax
.sequence
== 2)
6781 /* We must not dabble with instructions in a ".set norerorder" block. */
6782 if (mips_opts
.noreorder
)
6785 /* Otherwise, it's our responsibility to fill branch delay slots. */
6786 if (delayed_branch_p (ip
))
6788 if (!branch_likely_p (ip
)
6789 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6792 if (mips_opts
.mips16
6793 && ISA_SUPPORTS_MIPS16E
6794 && gpr_read_mask (ip
) != 0)
6795 return APPEND_ADD_COMPACT
;
6797 return APPEND_ADD_WITH_NOP
;
6803 /* IP is a MIPS16 instruction whose opcode we have just changed.
6804 Point IP->insn_mo to the new opcode's definition. */
6807 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6809 const struct mips_opcode
*mo
, *end
;
6811 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6812 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6813 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6821 /* For microMIPS macros, we need to generate a local number label
6822 as the target of branches. */
6823 #define MICROMIPS_LABEL_CHAR '\037'
6824 static unsigned long micromips_target_label
;
6825 static char micromips_target_name
[32];
6828 micromips_label_name (void)
6830 char *p
= micromips_target_name
;
6831 char symbol_name_temporary
[24];
6839 l
= micromips_target_label
;
6840 #ifdef LOCAL_LABEL_PREFIX
6841 *p
++ = LOCAL_LABEL_PREFIX
;
6844 *p
++ = MICROMIPS_LABEL_CHAR
;
6847 symbol_name_temporary
[i
++] = l
% 10 + '0';
6852 *p
++ = symbol_name_temporary
[--i
];
6855 return micromips_target_name
;
6859 micromips_label_expr (expressionS
*label_expr
)
6861 label_expr
->X_op
= O_symbol
;
6862 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6863 label_expr
->X_add_number
= 0;
6867 micromips_label_inc (void)
6869 micromips_target_label
++;
6870 *micromips_target_name
= '\0';
6874 micromips_add_label (void)
6878 s
= colon (micromips_label_name ());
6879 micromips_label_inc ();
6880 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6883 /* If assembling microMIPS code, then return the microMIPS reloc
6884 corresponding to the requested one if any. Otherwise return
6885 the reloc unchanged. */
6887 static bfd_reloc_code_real_type
6888 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6890 static const bfd_reloc_code_real_type relocs
[][2] =
6892 /* Keep sorted incrementally by the left-hand key. */
6893 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6894 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6895 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6896 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6897 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6898 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6899 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6900 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6901 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6902 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6903 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6904 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6905 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6906 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6907 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6908 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6909 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6910 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6911 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6912 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6913 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6914 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6915 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6916 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6917 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6918 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6919 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6921 bfd_reloc_code_real_type r
;
6924 if (!mips_opts
.micromips
)
6926 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6932 return relocs
[i
][1];
6937 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6938 Return true on success, storing the resolved value in RESULT. */
6941 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6946 case BFD_RELOC_MIPS_HIGHEST
:
6947 case BFD_RELOC_MICROMIPS_HIGHEST
:
6948 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6951 case BFD_RELOC_MIPS_HIGHER
:
6952 case BFD_RELOC_MICROMIPS_HIGHER
:
6953 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6956 case BFD_RELOC_HI16_S
:
6957 case BFD_RELOC_MICROMIPS_HI16_S
:
6958 case BFD_RELOC_MIPS16_HI16_S
:
6959 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6962 case BFD_RELOC_HI16
:
6963 case BFD_RELOC_MICROMIPS_HI16
:
6964 case BFD_RELOC_MIPS16_HI16
:
6965 *result
= (operand
>> 16) & 0xffff;
6968 case BFD_RELOC_LO16
:
6969 case BFD_RELOC_MICROMIPS_LO16
:
6970 case BFD_RELOC_MIPS16_LO16
:
6971 *result
= operand
& 0xffff;
6974 case BFD_RELOC_UNUSED
:
6983 /* Output an instruction. IP is the instruction information.
6984 ADDRESS_EXPR is an operand of the instruction to be used with
6985 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6986 a macro expansion. */
6989 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6990 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6992 unsigned long prev_pinfo2
, pinfo
;
6993 bfd_boolean relaxed_branch
= FALSE
;
6994 enum append_method method
;
6995 bfd_boolean relax32
;
6998 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6999 fix_loongson2f (ip
);
7001 file_ase_mips16
|= mips_opts
.mips16
;
7002 file_ase_micromips
|= mips_opts
.micromips
;
7004 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7005 pinfo
= ip
->insn_mo
->pinfo
;
7007 if (mips_opts
.micromips
7009 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7010 && micromips_insn_length (ip
->insn_mo
) != 2)
7011 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7012 && micromips_insn_length (ip
->insn_mo
) != 4)))
7013 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7014 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7016 if (address_expr
== NULL
)
7018 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7019 && reloc_type
[1] == BFD_RELOC_UNUSED
7020 && reloc_type
[2] == BFD_RELOC_UNUSED
7021 && address_expr
->X_op
== O_constant
)
7023 switch (*reloc_type
)
7025 case BFD_RELOC_MIPS_JMP
:
7029 shift
= mips_opts
.micromips
? 1 : 2;
7030 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7031 as_bad (_("jump to misaligned address (0x%lx)"),
7032 (unsigned long) address_expr
->X_add_number
);
7033 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7039 case BFD_RELOC_MIPS16_JMP
:
7040 if ((address_expr
->X_add_number
& 3) != 0)
7041 as_bad (_("jump to misaligned address (0x%lx)"),
7042 (unsigned long) address_expr
->X_add_number
);
7044 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7045 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7046 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7050 case BFD_RELOC_16_PCREL_S2
:
7054 shift
= mips_opts
.micromips
? 1 : 2;
7055 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7056 as_bad (_("branch to misaligned address (0x%lx)"),
7057 (unsigned long) address_expr
->X_add_number
);
7058 if (!mips_relax_branch
)
7060 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7061 & ~((1 << (shift
+ 16)) - 1))
7062 as_bad (_("branch address range overflow (0x%lx)"),
7063 (unsigned long) address_expr
->X_add_number
);
7064 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7070 case BFD_RELOC_MIPS_21_PCREL_S2
:
7075 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7076 as_bad (_("branch to misaligned address (0x%lx)"),
7077 (unsigned long) address_expr
->X_add_number
);
7078 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7079 & ~((1 << (shift
+ 21)) - 1))
7080 as_bad (_("branch address range overflow (0x%lx)"),
7081 (unsigned long) address_expr
->X_add_number
);
7082 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7087 case BFD_RELOC_MIPS_26_PCREL_S2
:
7092 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7093 as_bad (_("branch to misaligned address (0x%lx)"),
7094 (unsigned long) address_expr
->X_add_number
);
7095 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7096 & ~((1 << (shift
+ 26)) - 1))
7097 as_bad (_("branch address range overflow (0x%lx)"),
7098 (unsigned long) address_expr
->X_add_number
);
7099 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7108 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7111 ip
->insn_opcode
|= value
& 0xffff;
7119 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7121 /* There are a lot of optimizations we could do that we don't.
7122 In particular, we do not, in general, reorder instructions.
7123 If you use gcc with optimization, it will reorder
7124 instructions and generally do much more optimization then we
7125 do here; repeating all that work in the assembler would only
7126 benefit hand written assembly code, and does not seem worth
7128 int nops
= (mips_optimize
== 0
7129 ? nops_for_insn (0, history
, NULL
)
7130 : nops_for_insn_or_target (0, history
, ip
));
7134 unsigned long old_frag_offset
;
7137 old_frag
= frag_now
;
7138 old_frag_offset
= frag_now_fix ();
7140 for (i
= 0; i
< nops
; i
++)
7141 add_fixed_insn (NOP_INSN
);
7142 insert_into_history (0, nops
, NOP_INSN
);
7146 listing_prev_line ();
7147 /* We may be at the start of a variant frag. In case we
7148 are, make sure there is enough space for the frag
7149 after the frags created by listing_prev_line. The
7150 argument to frag_grow here must be at least as large
7151 as the argument to all other calls to frag_grow in
7152 this file. We don't have to worry about being in the
7153 middle of a variant frag, because the variants insert
7154 all needed nop instructions themselves. */
7158 mips_move_text_labels ();
7160 #ifndef NO_ECOFF_DEBUGGING
7161 if (ECOFF_DEBUGGING
)
7162 ecoff_fix_loc (old_frag
, old_frag_offset
);
7166 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7170 /* Work out how many nops in prev_nop_frag are needed by IP,
7171 ignoring hazards generated by the first prev_nop_frag_since
7173 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7174 gas_assert (nops
<= prev_nop_frag_holds
);
7176 /* Enforce NOPS as a minimum. */
7177 if (nops
> prev_nop_frag_required
)
7178 prev_nop_frag_required
= nops
;
7180 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7182 /* Settle for the current number of nops. Update the history
7183 accordingly (for the benefit of any future .set reorder code). */
7184 prev_nop_frag
= NULL
;
7185 insert_into_history (prev_nop_frag_since
,
7186 prev_nop_frag_holds
, NOP_INSN
);
7190 /* Allow this instruction to replace one of the nops that was
7191 tentatively added to prev_nop_frag. */
7192 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7193 prev_nop_frag_holds
--;
7194 prev_nop_frag_since
++;
7198 method
= get_append_method (ip
, address_expr
, reloc_type
);
7199 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7201 dwarf2_emit_insn (0);
7202 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7203 so "move" the instruction address accordingly.
7205 Also, it doesn't seem appropriate for the assembler to reorder .loc
7206 entries. If this instruction is a branch that we are going to swap
7207 with the previous instruction, the two instructions should be
7208 treated as a unit, and the debug information for both instructions
7209 should refer to the start of the branch sequence. Using the
7210 current position is certainly wrong when swapping a 32-bit branch
7211 and a 16-bit delay slot, since the current position would then be
7212 in the middle of a branch. */
7213 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7215 relax32
= (mips_relax_branch
7216 /* Don't try branch relaxation within .set nomacro, or within
7217 .set noat if we use $at for PIC computations. If it turns
7218 out that the branch was out-of-range, we'll get an error. */
7219 && !mips_opts
.warn_about_macros
7220 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7221 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7222 as they have no complementing branches. */
7223 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7225 if (!HAVE_CODE_COMPRESSION
7228 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7229 && delayed_branch_p (ip
))
7231 relaxed_branch
= TRUE
;
7232 add_relaxed_insn (ip
, (relaxed_branch_length
7234 uncond_branch_p (ip
) ? -1
7235 : branch_likely_p (ip
) ? 1
7239 uncond_branch_p (ip
),
7240 branch_likely_p (ip
),
7241 pinfo
& INSN_WRITE_GPR_31
,
7243 address_expr
->X_add_symbol
,
7244 address_expr
->X_add_number
);
7245 *reloc_type
= BFD_RELOC_UNUSED
;
7247 else if (mips_opts
.micromips
7249 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7250 || *reloc_type
> BFD_RELOC_UNUSED
)
7251 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7252 /* Don't try branch relaxation when users specify
7253 16-bit/32-bit instructions. */
7254 && !forced_insn_length
)
7256 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
7257 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7258 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7259 int compact
= compact_branch_p (ip
);
7260 int al
= pinfo
& INSN_WRITE_GPR_31
;
7263 gas_assert (address_expr
!= NULL
);
7264 gas_assert (!mips_relax
.sequence
);
7266 relaxed_branch
= TRUE
;
7267 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7268 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
7269 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
7271 address_expr
->X_add_symbol
,
7272 address_expr
->X_add_number
);
7273 *reloc_type
= BFD_RELOC_UNUSED
;
7275 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7277 /* We need to set up a variant frag. */
7278 gas_assert (address_expr
!= NULL
);
7279 add_relaxed_insn (ip
, 4, 0,
7281 (*reloc_type
- BFD_RELOC_UNUSED
,
7282 forced_insn_length
== 2, forced_insn_length
== 4,
7283 delayed_branch_p (&history
[0]),
7284 history
[0].mips16_absolute_jump_p
),
7285 make_expr_symbol (address_expr
), 0);
7287 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7289 if (!delayed_branch_p (ip
))
7290 /* Make sure there is enough room to swap this instruction with
7291 a following jump instruction. */
7293 add_fixed_insn (ip
);
7297 if (mips_opts
.mips16
7298 && mips_opts
.noreorder
7299 && delayed_branch_p (&history
[0]))
7300 as_warn (_("extended instruction in delay slot"));
7302 if (mips_relax
.sequence
)
7304 /* If we've reached the end of this frag, turn it into a variant
7305 frag and record the information for the instructions we've
7307 if (frag_room () < 4)
7308 relax_close_frag ();
7309 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7312 if (mips_relax
.sequence
!= 2)
7314 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7315 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7316 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7317 mips_macro_warning
.insns
[0]++;
7319 if (mips_relax
.sequence
!= 1)
7321 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7322 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7323 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7324 mips_macro_warning
.insns
[1]++;
7327 if (mips_opts
.mips16
)
7330 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7332 add_fixed_insn (ip
);
7335 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7337 bfd_reloc_code_real_type final_type
[3];
7338 reloc_howto_type
*howto0
;
7339 reloc_howto_type
*howto
;
7342 /* Perform any necessary conversion to microMIPS relocations
7343 and find out how many relocations there actually are. */
7344 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7345 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7347 /* In a compound relocation, it is the final (outermost)
7348 operator that determines the relocated field. */
7349 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7354 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7355 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7356 bfd_get_reloc_size (howto
),
7358 howto0
&& howto0
->pc_relative
,
7361 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7362 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7363 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7365 /* These relocations can have an addend that won't fit in
7366 4 octets for 64bit assembly. */
7368 && ! howto
->partial_inplace
7369 && (reloc_type
[0] == BFD_RELOC_16
7370 || reloc_type
[0] == BFD_RELOC_32
7371 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7372 || reloc_type
[0] == BFD_RELOC_GPREL16
7373 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7374 || reloc_type
[0] == BFD_RELOC_GPREL32
7375 || reloc_type
[0] == BFD_RELOC_64
7376 || reloc_type
[0] == BFD_RELOC_CTOR
7377 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7378 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7379 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7380 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7381 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7382 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7383 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7384 || hi16_reloc_p (reloc_type
[0])
7385 || lo16_reloc_p (reloc_type
[0])))
7386 ip
->fixp
[0]->fx_no_overflow
= 1;
7388 /* These relocations can have an addend that won't fit in 2 octets. */
7389 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7390 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7391 ip
->fixp
[0]->fx_no_overflow
= 1;
7393 if (mips_relax
.sequence
)
7395 if (mips_relax
.first_fixup
== 0)
7396 mips_relax
.first_fixup
= ip
->fixp
[0];
7398 else if (reloc_needs_lo_p (*reloc_type
))
7400 struct mips_hi_fixup
*hi_fixup
;
7402 /* Reuse the last entry if it already has a matching %lo. */
7403 hi_fixup
= mips_hi_fixup_list
;
7405 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7407 hi_fixup
= ((struct mips_hi_fixup
*)
7408 xmalloc (sizeof (struct mips_hi_fixup
)));
7409 hi_fixup
->next
= mips_hi_fixup_list
;
7410 mips_hi_fixup_list
= hi_fixup
;
7412 hi_fixup
->fixp
= ip
->fixp
[0];
7413 hi_fixup
->seg
= now_seg
;
7416 /* Add fixups for the second and third relocations, if given.
7417 Note that the ABI allows the second relocation to be
7418 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7419 moment we only use RSS_UNDEF, but we could add support
7420 for the others if it ever becomes necessary. */
7421 for (i
= 1; i
< 3; i
++)
7422 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7424 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7425 ip
->fixp
[0]->fx_size
, NULL
, 0,
7426 FALSE
, final_type
[i
]);
7428 /* Use fx_tcbit to mark compound relocs. */
7429 ip
->fixp
[0]->fx_tcbit
= 1;
7430 ip
->fixp
[i
]->fx_tcbit
= 1;
7435 /* Update the register mask information. */
7436 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7437 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7442 insert_into_history (0, 1, ip
);
7445 case APPEND_ADD_WITH_NOP
:
7447 struct mips_cl_insn
*nop
;
7449 insert_into_history (0, 1, ip
);
7450 nop
= get_delay_slot_nop (ip
);
7451 add_fixed_insn (nop
);
7452 insert_into_history (0, 1, nop
);
7453 if (mips_relax
.sequence
)
7454 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7458 case APPEND_ADD_COMPACT
:
7459 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7460 gas_assert (mips_opts
.mips16
);
7461 ip
->insn_opcode
|= 0x0080;
7462 find_altered_mips16_opcode (ip
);
7464 insert_into_history (0, 1, ip
);
7469 struct mips_cl_insn delay
= history
[0];
7470 if (mips_opts
.mips16
)
7472 know (delay
.frag
== ip
->frag
);
7473 move_insn (ip
, delay
.frag
, delay
.where
);
7474 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7476 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7478 /* Add the delay slot instruction to the end of the
7479 current frag and shrink the fixed part of the
7480 original frag. If the branch occupies the tail of
7481 the latter, move it backwards to cover the gap. */
7482 delay
.frag
->fr_fix
-= branch_disp
;
7483 if (delay
.frag
== ip
->frag
)
7484 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7485 add_fixed_insn (&delay
);
7489 move_insn (&delay
, ip
->frag
,
7490 ip
->where
- branch_disp
+ insn_length (ip
));
7491 move_insn (ip
, history
[0].frag
, history
[0].where
);
7495 insert_into_history (0, 1, &delay
);
7500 /* If we have just completed an unconditional branch, clear the history. */
7501 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7502 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7506 mips_no_prev_insn ();
7508 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7509 history
[i
].cleared_p
= 1;
7512 /* We need to emit a label at the end of branch-likely macros. */
7513 if (emit_branch_likely_macro
)
7515 emit_branch_likely_macro
= FALSE
;
7516 micromips_add_label ();
7519 /* We just output an insn, so the next one doesn't have a label. */
7520 mips_clear_insn_labels ();
7523 /* Forget that there was any previous instruction or label.
7524 When BRANCH is true, the branch history is also flushed. */
7527 mips_no_prev_insn (void)
7529 prev_nop_frag
= NULL
;
7530 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7531 mips_clear_insn_labels ();
7534 /* This function must be called before we emit something other than
7535 instructions. It is like mips_no_prev_insn except that it inserts
7536 any NOPS that might be needed by previous instructions. */
7539 mips_emit_delays (void)
7541 if (! mips_opts
.noreorder
)
7543 int nops
= nops_for_insn (0, history
, NULL
);
7547 add_fixed_insn (NOP_INSN
);
7548 mips_move_text_labels ();
7551 mips_no_prev_insn ();
7554 /* Start a (possibly nested) noreorder block. */
7557 start_noreorder (void)
7559 if (mips_opts
.noreorder
== 0)
7564 /* None of the instructions before the .set noreorder can be moved. */
7565 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7566 history
[i
].fixed_p
= 1;
7568 /* Insert any nops that might be needed between the .set noreorder
7569 block and the previous instructions. We will later remove any
7570 nops that turn out not to be needed. */
7571 nops
= nops_for_insn (0, history
, NULL
);
7574 if (mips_optimize
!= 0)
7576 /* Record the frag which holds the nop instructions, so
7577 that we can remove them if we don't need them. */
7578 frag_grow (nops
* NOP_INSN_SIZE
);
7579 prev_nop_frag
= frag_now
;
7580 prev_nop_frag_holds
= nops
;
7581 prev_nop_frag_required
= 0;
7582 prev_nop_frag_since
= 0;
7585 for (; nops
> 0; --nops
)
7586 add_fixed_insn (NOP_INSN
);
7588 /* Move on to a new frag, so that it is safe to simply
7589 decrease the size of prev_nop_frag. */
7590 frag_wane (frag_now
);
7592 mips_move_text_labels ();
7594 mips_mark_labels ();
7595 mips_clear_insn_labels ();
7597 mips_opts
.noreorder
++;
7598 mips_any_noreorder
= 1;
7601 /* End a nested noreorder block. */
7604 end_noreorder (void)
7606 mips_opts
.noreorder
--;
7607 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7609 /* Commit to inserting prev_nop_frag_required nops and go back to
7610 handling nop insertion the .set reorder way. */
7611 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7613 insert_into_history (prev_nop_frag_since
,
7614 prev_nop_frag_required
, NOP_INSN
);
7615 prev_nop_frag
= NULL
;
7619 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7620 higher bits unset. */
7623 normalize_constant_expr (expressionS
*ex
)
7625 if (ex
->X_op
== O_constant
7626 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7627 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7631 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7632 all higher bits unset. */
7635 normalize_address_expr (expressionS
*ex
)
7637 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7638 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7639 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7640 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7644 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7645 Return true if the match was successful.
7647 OPCODE_EXTRA is a value that should be ORed into the opcode
7648 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7649 there are more alternatives after OPCODE and SOFT_MATCH is
7650 as for mips_arg_info. */
7653 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7654 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7655 bfd_boolean lax_match
, bfd_boolean complete_p
)
7658 struct mips_arg_info arg
;
7659 const struct mips_operand
*operand
;
7662 imm_expr
.X_op
= O_absent
;
7663 offset_expr
.X_op
= O_absent
;
7664 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7665 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7666 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7668 create_insn (insn
, opcode
);
7669 /* When no opcode suffix is specified, assume ".xyzw". */
7670 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7671 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7673 insn
->insn_opcode
|= opcode_extra
;
7674 memset (&arg
, 0, sizeof (arg
));
7678 arg
.last_regno
= ILLEGAL_REG
;
7679 arg
.dest_regno
= ILLEGAL_REG
;
7680 arg
.lax_match
= lax_match
;
7681 for (args
= opcode
->args
;; ++args
)
7683 if (arg
.token
->type
== OT_END
)
7685 /* Handle unary instructions in which only one operand is given.
7686 The source is then the same as the destination. */
7687 if (arg
.opnum
== 1 && *args
== ',')
7689 operand
= (mips_opts
.micromips
7690 ? decode_micromips_operand (args
+ 1)
7691 : decode_mips_operand (args
+ 1));
7692 if (operand
&& mips_optional_operand_p (operand
))
7700 /* Treat elided base registers as $0. */
7701 if (strcmp (args
, "(b)") == 0)
7709 /* The register suffix is optional. */
7714 /* Fail the match if there were too few operands. */
7718 /* Successful match. */
7721 clear_insn_error ();
7722 if (arg
.dest_regno
== arg
.last_regno
7723 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7727 (0, _("source and destination must be different"));
7728 else if (arg
.last_regno
== 31)
7730 (0, _("a destination register must be supplied"));
7732 else if (arg
.last_regno
== 31
7733 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7734 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7735 set_insn_error (0, _("the source register must not be $31"));
7736 check_completed_insn (&arg
);
7740 /* Fail the match if the line has too many operands. */
7744 /* Handle characters that need to match exactly. */
7745 if (*args
== '(' || *args
== ')' || *args
== ',')
7747 if (match_char (&arg
, *args
))
7754 if (arg
.token
->type
== OT_DOUBLE_CHAR
7755 && arg
.token
->u
.ch
== *args
)
7763 /* Handle special macro operands. Work out the properties of
7772 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
7776 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
7785 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7789 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
7793 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
7799 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7801 imm_expr
.X_op
= O_constant
;
7803 normalize_constant_expr (&imm_expr
);
7807 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7809 /* Assume that the offset has been elided and that what
7810 we saw was a base register. The match will fail later
7811 if that assumption turns out to be wrong. */
7812 offset_expr
.X_op
= O_constant
;
7813 offset_expr
.X_add_number
= 0;
7817 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7819 normalize_address_expr (&offset_expr
);
7824 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7830 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7836 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7842 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7848 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7852 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7856 gas_assert (mips_opts
.micromips
);
7862 if (!forced_insn_length
)
7863 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7865 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7867 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7873 operand
= (mips_opts
.micromips
7874 ? decode_micromips_operand (args
)
7875 : decode_mips_operand (args
));
7879 /* Skip prefixes. */
7880 if (*args
== '+' || *args
== 'm' || *args
== '-')
7883 if (mips_optional_operand_p (operand
)
7885 && (arg
.token
[0].type
!= OT_REG
7886 || arg
.token
[1].type
== OT_END
))
7888 /* Assume that the register has been elided and is the
7889 same as the first operand. */
7894 if (!match_operand (&arg
, operand
))
7899 /* Like match_insn, but for MIPS16. */
7902 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7903 struct mips_operand_token
*tokens
)
7906 const struct mips_operand
*operand
;
7907 const struct mips_operand
*ext_operand
;
7908 struct mips_arg_info arg
;
7911 create_insn (insn
, opcode
);
7912 imm_expr
.X_op
= O_absent
;
7913 offset_expr
.X_op
= O_absent
;
7914 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7915 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7916 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7919 memset (&arg
, 0, sizeof (arg
));
7923 arg
.last_regno
= ILLEGAL_REG
;
7924 arg
.dest_regno
= ILLEGAL_REG
;
7926 for (args
= opcode
->args
;; ++args
)
7930 if (arg
.token
->type
== OT_END
)
7934 /* Handle unary instructions in which only one operand is given.
7935 The source is then the same as the destination. */
7936 if (arg
.opnum
== 1 && *args
== ',')
7938 operand
= decode_mips16_operand (args
[1], FALSE
);
7939 if (operand
&& mips_optional_operand_p (operand
))
7947 /* Fail the match if there were too few operands. */
7951 /* Successful match. Stuff the immediate value in now, if
7953 clear_insn_error ();
7954 if (opcode
->pinfo
== INSN_MACRO
)
7956 gas_assert (relax_char
== 0 || relax_char
== 'p');
7957 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7960 && offset_expr
.X_op
== O_constant
7961 && calculate_reloc (*offset_reloc
,
7962 offset_expr
.X_add_number
,
7965 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7966 forced_insn_length
, &insn
->insn_opcode
);
7967 offset_expr
.X_op
= O_absent
;
7968 *offset_reloc
= BFD_RELOC_UNUSED
;
7970 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7972 if (forced_insn_length
== 2)
7973 set_insn_error (0, _("invalid unextended operand value"));
7974 forced_insn_length
= 4;
7975 insn
->insn_opcode
|= MIPS16_EXTEND
;
7977 else if (relax_char
)
7978 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7980 check_completed_insn (&arg
);
7984 /* Fail the match if the line has too many operands. */
7988 /* Handle characters that need to match exactly. */
7989 if (*args
== '(' || *args
== ')' || *args
== ',')
7991 if (match_char (&arg
, *args
))
8009 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8011 imm_expr
.X_op
= O_constant
;
8013 normalize_constant_expr (&imm_expr
);
8018 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8019 insn
->insn_opcode
<<= 16;
8023 operand
= decode_mips16_operand (c
, FALSE
);
8027 /* '6' is a special case. It is used for BREAK and SDBBP,
8028 whose operands are only meaningful to the software that decodes
8029 them. This means that there is no architectural reason why
8030 they cannot be prefixed by EXTEND, but in practice,
8031 exception handlers will only look at the instruction
8032 itself. We therefore allow '6' to be extended when
8033 disassembling but not when assembling. */
8034 if (operand
->type
!= OP_PCREL
&& c
!= '6')
8036 ext_operand
= decode_mips16_operand (c
, TRUE
);
8037 if (operand
!= ext_operand
)
8039 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8041 offset_expr
.X_op
= O_constant
;
8042 offset_expr
.X_add_number
= 0;
8047 /* We need the OT_INTEGER check because some MIPS16
8048 immediate variants are listed before the register ones. */
8049 if (arg
.token
->type
!= OT_INTEGER
8050 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
8053 /* '8' is used for SLTI(U) and has traditionally not
8054 been allowed to take relocation operators. */
8055 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8056 && (ext_operand
->size
!= 16 || c
== '8'))
8064 if (mips_optional_operand_p (operand
)
8066 && (arg
.token
[0].type
!= OT_REG
8067 || arg
.token
[1].type
== OT_END
))
8069 /* Assume that the register has been elided and is the
8070 same as the first operand. */
8075 if (!match_operand (&arg
, operand
))
8080 /* Record that the current instruction is invalid for the current ISA. */
8083 match_invalid_for_isa (void)
8086 (0, _("opcode not supported on this processor: %s (%s)"),
8087 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8088 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8091 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8092 Return true if a definite match or failure was found, storing any match
8093 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8094 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8095 tried and failed to match under normal conditions and now want to try a
8096 more relaxed match. */
8099 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8100 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8101 int opcode_extra
, bfd_boolean lax_match
)
8103 const struct mips_opcode
*opcode
;
8104 const struct mips_opcode
*invalid_delay_slot
;
8105 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8107 /* Search for a match, ignoring alternatives that don't satisfy the
8108 current ISA or forced_length. */
8109 invalid_delay_slot
= 0;
8110 seen_valid_for_isa
= FALSE
;
8111 seen_valid_for_size
= FALSE
;
8115 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8116 if (is_opcode_valid (opcode
))
8118 seen_valid_for_isa
= TRUE
;
8119 if (is_size_valid (opcode
))
8121 bfd_boolean delay_slot_ok
;
8123 seen_valid_for_size
= TRUE
;
8124 delay_slot_ok
= is_delay_slot_valid (opcode
);
8125 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8126 lax_match
, delay_slot_ok
))
8130 if (!invalid_delay_slot
)
8131 invalid_delay_slot
= opcode
;
8140 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8142 /* If the only matches we found had the wrong length for the delay slot,
8143 pick the first such match. We'll issue an appropriate warning later. */
8144 if (invalid_delay_slot
)
8146 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8152 /* Handle the case where we didn't try to match an instruction because
8153 all the alternatives were incompatible with the current ISA. */
8154 if (!seen_valid_for_isa
)
8156 match_invalid_for_isa ();
8160 /* Handle the case where we didn't try to match an instruction because
8161 all the alternatives were of the wrong size. */
8162 if (!seen_valid_for_size
)
8164 if (mips_opts
.insn32
)
8165 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8168 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8169 8 * forced_insn_length
);
8176 /* Like match_insns, but for MIPS16. */
8179 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8180 struct mips_operand_token
*tokens
)
8182 const struct mips_opcode
*opcode
;
8183 bfd_boolean seen_valid_for_isa
;
8185 /* Search for a match, ignoring alternatives that don't satisfy the
8186 current ISA. There are no separate entries for extended forms so
8187 we deal with forced_length later. */
8188 seen_valid_for_isa
= FALSE
;
8192 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8193 if (is_opcode_valid_16 (opcode
))
8195 seen_valid_for_isa
= TRUE
;
8196 if (match_mips16_insn (insn
, opcode
, tokens
))
8201 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8202 && strcmp (opcode
->name
, first
->name
) == 0);
8204 /* Handle the case where we didn't try to match an instruction because
8205 all the alternatives were incompatible with the current ISA. */
8206 if (!seen_valid_for_isa
)
8208 match_invalid_for_isa ();
8215 /* Set up global variables for the start of a new macro. */
8220 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8221 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8222 sizeof (mips_macro_warning
.first_insn_sizes
));
8223 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8224 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8225 && delayed_branch_p (&history
[0]));
8226 switch (history
[0].insn_mo
->pinfo2
8227 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8229 case INSN2_BRANCH_DELAY_32BIT
:
8230 mips_macro_warning
.delay_slot_length
= 4;
8232 case INSN2_BRANCH_DELAY_16BIT
:
8233 mips_macro_warning
.delay_slot_length
= 2;
8236 mips_macro_warning
.delay_slot_length
= 0;
8239 mips_macro_warning
.first_frag
= NULL
;
8242 /* Given that a macro is longer than one instruction or of the wrong size,
8243 return the appropriate warning for it. Return null if no warning is
8244 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8245 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8246 and RELAX_NOMACRO. */
8249 macro_warning (relax_substateT subtype
)
8251 if (subtype
& RELAX_DELAY_SLOT
)
8252 return _("macro instruction expanded into multiple instructions"
8253 " in a branch delay slot");
8254 else if (subtype
& RELAX_NOMACRO
)
8255 return _("macro instruction expanded into multiple instructions");
8256 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8257 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8258 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8259 ? _("macro instruction expanded into a wrong size instruction"
8260 " in a 16-bit branch delay slot")
8261 : _("macro instruction expanded into a wrong size instruction"
8262 " in a 32-bit branch delay slot"));
8267 /* Finish up a macro. Emit warnings as appropriate. */
8272 /* Relaxation warning flags. */
8273 relax_substateT subtype
= 0;
8275 /* Check delay slot size requirements. */
8276 if (mips_macro_warning
.delay_slot_length
== 2)
8277 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8278 if (mips_macro_warning
.delay_slot_length
!= 0)
8280 if (mips_macro_warning
.delay_slot_length
8281 != mips_macro_warning
.first_insn_sizes
[0])
8282 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8283 if (mips_macro_warning
.delay_slot_length
8284 != mips_macro_warning
.first_insn_sizes
[1])
8285 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8288 /* Check instruction count requirements. */
8289 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8291 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8292 subtype
|= RELAX_SECOND_LONGER
;
8293 if (mips_opts
.warn_about_macros
)
8294 subtype
|= RELAX_NOMACRO
;
8295 if (mips_macro_warning
.delay_slot_p
)
8296 subtype
|= RELAX_DELAY_SLOT
;
8299 /* If both alternatives fail to fill a delay slot correctly,
8300 emit the warning now. */
8301 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8302 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8307 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8308 | RELAX_DELAY_SLOT_SIZE_FIRST
8309 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8310 msg
= macro_warning (s
);
8312 as_warn ("%s", msg
);
8316 /* If both implementations are longer than 1 instruction, then emit the
8318 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8323 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8324 msg
= macro_warning (s
);
8326 as_warn ("%s", msg
);
8330 /* If any flags still set, then one implementation might need a warning
8331 and the other either will need one of a different kind or none at all.
8332 Pass any remaining flags over to relaxation. */
8333 if (mips_macro_warning
.first_frag
!= NULL
)
8334 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8337 /* Instruction operand formats used in macros that vary between
8338 standard MIPS and microMIPS code. */
8340 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8341 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8342 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8343 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8344 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8345 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8346 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8347 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8349 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8350 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8351 : cop12_fmt[mips_opts.micromips])
8352 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8353 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8354 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8355 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8356 : mem12_fmt[mips_opts.micromips])
8357 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8358 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8359 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8361 /* Read a macro's relocation codes from *ARGS and store them in *R.
8362 The first argument in *ARGS will be either the code for a single
8363 relocation or -1 followed by the three codes that make up a
8364 composite relocation. */
8367 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8371 next
= va_arg (*args
, int);
8373 r
[0] = (bfd_reloc_code_real_type
) next
;
8376 for (i
= 0; i
< 3; i
++)
8377 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8378 /* This function is only used for 16-bit relocation fields.
8379 To make the macro code simpler, treat an unrelocated value
8380 in the same way as BFD_RELOC_LO16. */
8381 if (r
[0] == BFD_RELOC_UNUSED
)
8382 r
[0] = BFD_RELOC_LO16
;
8386 /* Build an instruction created by a macro expansion. This is passed
8387 a pointer to the count of instructions created so far, an
8388 expression, the name of the instruction to build, an operand format
8389 string, and corresponding arguments. */
8392 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8394 const struct mips_opcode
*mo
= NULL
;
8395 bfd_reloc_code_real_type r
[3];
8396 const struct mips_opcode
*amo
;
8397 const struct mips_operand
*operand
;
8398 struct hash_control
*hash
;
8399 struct mips_cl_insn insn
;
8403 va_start (args
, fmt
);
8405 if (mips_opts
.mips16
)
8407 mips16_macro_build (ep
, name
, fmt
, &args
);
8412 r
[0] = BFD_RELOC_UNUSED
;
8413 r
[1] = BFD_RELOC_UNUSED
;
8414 r
[2] = BFD_RELOC_UNUSED
;
8415 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8416 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8418 gas_assert (strcmp (name
, amo
->name
) == 0);
8422 /* Search until we get a match for NAME. It is assumed here that
8423 macros will never generate MDMX, MIPS-3D, or MT instructions.
8424 We try to match an instruction that fulfils the branch delay
8425 slot instruction length requirement (if any) of the previous
8426 instruction. While doing this we record the first instruction
8427 seen that matches all the other conditions and use it anyway
8428 if the requirement cannot be met; we will issue an appropriate
8429 warning later on. */
8430 if (strcmp (fmt
, amo
->args
) == 0
8431 && amo
->pinfo
!= INSN_MACRO
8432 && is_opcode_valid (amo
)
8433 && is_size_valid (amo
))
8435 if (is_delay_slot_valid (amo
))
8445 gas_assert (amo
->name
);
8447 while (strcmp (name
, amo
->name
) == 0);
8450 create_insn (&insn
, mo
);
8463 macro_read_relocs (&args
, r
);
8464 gas_assert (*r
== BFD_RELOC_GPREL16
8465 || *r
== BFD_RELOC_MIPS_HIGHER
8466 || *r
== BFD_RELOC_HI16_S
8467 || *r
== BFD_RELOC_LO16
8468 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8472 macro_read_relocs (&args
, r
);
8476 macro_read_relocs (&args
, r
);
8477 gas_assert (ep
!= NULL
8478 && (ep
->X_op
== O_constant
8479 || (ep
->X_op
== O_symbol
8480 && (*r
== BFD_RELOC_MIPS_HIGHEST
8481 || *r
== BFD_RELOC_HI16_S
8482 || *r
== BFD_RELOC_HI16
8483 || *r
== BFD_RELOC_GPREL16
8484 || *r
== BFD_RELOC_MIPS_GOT_HI16
8485 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8489 gas_assert (ep
!= NULL
);
8492 * This allows macro() to pass an immediate expression for
8493 * creating short branches without creating a symbol.
8495 * We don't allow branch relaxation for these branches, as
8496 * they should only appear in ".set nomacro" anyway.
8498 if (ep
->X_op
== O_constant
)
8500 /* For microMIPS we always use relocations for branches.
8501 So we should not resolve immediate values. */
8502 gas_assert (!mips_opts
.micromips
);
8504 if ((ep
->X_add_number
& 3) != 0)
8505 as_bad (_("branch to misaligned address (0x%lx)"),
8506 (unsigned long) ep
->X_add_number
);
8507 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8508 as_bad (_("branch address range overflow (0x%lx)"),
8509 (unsigned long) ep
->X_add_number
);
8510 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8514 *r
= BFD_RELOC_16_PCREL_S2
;
8518 gas_assert (ep
!= NULL
);
8519 *r
= BFD_RELOC_MIPS_JMP
;
8523 operand
= (mips_opts
.micromips
8524 ? decode_micromips_operand (fmt
)
8525 : decode_mips_operand (fmt
));
8529 uval
= va_arg (args
, int);
8530 if (operand
->type
== OP_CLO_CLZ_DEST
)
8531 uval
|= (uval
<< 5);
8532 insn_insert_operand (&insn
, operand
, uval
);
8534 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8540 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8542 append_insn (&insn
, ep
, r
, TRUE
);
8546 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8549 struct mips_opcode
*mo
;
8550 struct mips_cl_insn insn
;
8551 const struct mips_operand
*operand
;
8552 bfd_reloc_code_real_type r
[3]
8553 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8555 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8557 gas_assert (strcmp (name
, mo
->name
) == 0);
8559 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8562 gas_assert (mo
->name
);
8563 gas_assert (strcmp (name
, mo
->name
) == 0);
8566 create_insn (&insn
, mo
);
8604 gas_assert (ep
!= NULL
);
8606 if (ep
->X_op
!= O_constant
)
8607 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8608 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8610 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8612 *r
= BFD_RELOC_UNUSED
;
8618 operand
= decode_mips16_operand (c
, FALSE
);
8622 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8627 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8629 append_insn (&insn
, ep
, r
, TRUE
);
8633 * Generate a "jalr" instruction with a relocation hint to the called
8634 * function. This occurs in NewABI PIC code.
8637 macro_build_jalr (expressionS
*ep
, int cprestore
)
8639 static const bfd_reloc_code_real_type jalr_relocs
[2]
8640 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8641 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8645 if (MIPS_JALR_HINT_P (ep
))
8650 if (mips_opts
.micromips
)
8652 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8653 ? "jalr" : "jalrs");
8654 if (MIPS_JALR_HINT_P (ep
)
8656 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8657 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8659 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8662 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8663 if (MIPS_JALR_HINT_P (ep
))
8664 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8668 * Generate a "lui" instruction.
8671 macro_build_lui (expressionS
*ep
, int regnum
)
8673 gas_assert (! mips_opts
.mips16
);
8675 if (ep
->X_op
!= O_constant
)
8677 gas_assert (ep
->X_op
== O_symbol
);
8678 /* _gp_disp is a special case, used from s_cpload.
8679 __gnu_local_gp is used if mips_no_shared. */
8680 gas_assert (mips_pic
== NO_PIC
8682 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8683 || (! mips_in_shared
8684 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8685 "__gnu_local_gp") == 0));
8688 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8691 /* Generate a sequence of instructions to do a load or store from a constant
8692 offset off of a base register (breg) into/from a target register (treg),
8693 using AT if necessary. */
8695 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8696 int treg
, int breg
, int dbl
)
8698 gas_assert (ep
->X_op
== O_constant
);
8700 /* Sign-extending 32-bit constants makes their handling easier. */
8702 normalize_constant_expr (ep
);
8704 /* Right now, this routine can only handle signed 32-bit constants. */
8705 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8706 as_warn (_("operand overflow"));
8708 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8710 /* Signed 16-bit offset will fit in the op. Easy! */
8711 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8715 /* 32-bit offset, need multiple instructions and AT, like:
8716 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8717 addu $tempreg,$tempreg,$breg
8718 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8719 to handle the complete offset. */
8720 macro_build_lui (ep
, AT
);
8721 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8722 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8725 as_bad (_("macro used $at after \".set noat\""));
8730 * Generates code to set the $at register to true (one)
8731 * if reg is less than the immediate expression.
8734 set_at (int reg
, int unsignedp
)
8736 if (imm_expr
.X_add_number
>= -0x8000
8737 && imm_expr
.X_add_number
< 0x8000)
8738 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8739 AT
, reg
, BFD_RELOC_LO16
);
8742 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
8743 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8747 /* Count the leading zeroes by performing a binary chop. This is a
8748 bulky bit of source, but performance is a LOT better for the
8749 majority of values than a simple loop to count the bits:
8750 for (lcnt = 0; (lcnt < 32); lcnt++)
8751 if ((v) & (1 << (31 - lcnt)))
8753 However it is not code size friendly, and the gain will drop a bit
8754 on certain cached systems.
8756 #define COUNT_TOP_ZEROES(v) \
8757 (((v) & ~0xffff) == 0 \
8758 ? ((v) & ~0xff) == 0 \
8759 ? ((v) & ~0xf) == 0 \
8760 ? ((v) & ~0x3) == 0 \
8761 ? ((v) & ~0x1) == 0 \
8766 : ((v) & ~0x7) == 0 \
8769 : ((v) & ~0x3f) == 0 \
8770 ? ((v) & ~0x1f) == 0 \
8773 : ((v) & ~0x7f) == 0 \
8776 : ((v) & ~0xfff) == 0 \
8777 ? ((v) & ~0x3ff) == 0 \
8778 ? ((v) & ~0x1ff) == 0 \
8781 : ((v) & ~0x7ff) == 0 \
8784 : ((v) & ~0x3fff) == 0 \
8785 ? ((v) & ~0x1fff) == 0 \
8788 : ((v) & ~0x7fff) == 0 \
8791 : ((v) & ~0xffffff) == 0 \
8792 ? ((v) & ~0xfffff) == 0 \
8793 ? ((v) & ~0x3ffff) == 0 \
8794 ? ((v) & ~0x1ffff) == 0 \
8797 : ((v) & ~0x7ffff) == 0 \
8800 : ((v) & ~0x3fffff) == 0 \
8801 ? ((v) & ~0x1fffff) == 0 \
8804 : ((v) & ~0x7fffff) == 0 \
8807 : ((v) & ~0xfffffff) == 0 \
8808 ? ((v) & ~0x3ffffff) == 0 \
8809 ? ((v) & ~0x1ffffff) == 0 \
8812 : ((v) & ~0x7ffffff) == 0 \
8815 : ((v) & ~0x3fffffff) == 0 \
8816 ? ((v) & ~0x1fffffff) == 0 \
8819 : ((v) & ~0x7fffffff) == 0 \
8824 * This routine generates the least number of instructions necessary to load
8825 * an absolute expression value into a register.
8828 load_register (int reg
, expressionS
*ep
, int dbl
)
8831 expressionS hi32
, lo32
;
8833 if (ep
->X_op
!= O_big
)
8835 gas_assert (ep
->X_op
== O_constant
);
8837 /* Sign-extending 32-bit constants makes their handling easier. */
8839 normalize_constant_expr (ep
);
8841 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8843 /* We can handle 16 bit signed values with an addiu to
8844 $zero. No need to ever use daddiu here, since $zero and
8845 the result are always correct in 32 bit mode. */
8846 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8849 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8851 /* We can handle 16 bit unsigned values with an ori to
8853 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8856 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8858 /* 32 bit values require an lui. */
8859 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8860 if ((ep
->X_add_number
& 0xffff) != 0)
8861 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8866 /* The value is larger than 32 bits. */
8868 if (!dbl
|| GPR_SIZE
== 32)
8872 sprintf_vma (value
, ep
->X_add_number
);
8873 as_bad (_("number (0x%s) larger than 32 bits"), value
);
8874 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8878 if (ep
->X_op
!= O_big
)
8881 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8882 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8883 hi32
.X_add_number
&= 0xffffffff;
8885 lo32
.X_add_number
&= 0xffffffff;
8889 gas_assert (ep
->X_add_number
> 2);
8890 if (ep
->X_add_number
== 3)
8891 generic_bignum
[3] = 0;
8892 else if (ep
->X_add_number
> 4)
8893 as_bad (_("number larger than 64 bits"));
8894 lo32
.X_op
= O_constant
;
8895 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8896 hi32
.X_op
= O_constant
;
8897 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8900 if (hi32
.X_add_number
== 0)
8905 unsigned long hi
, lo
;
8907 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8909 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8911 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8914 if (lo32
.X_add_number
& 0x80000000)
8916 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8917 if (lo32
.X_add_number
& 0xffff)
8918 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8923 /* Check for 16bit shifted constant. We know that hi32 is
8924 non-zero, so start the mask on the first bit of the hi32
8929 unsigned long himask
, lomask
;
8933 himask
= 0xffff >> (32 - shift
);
8934 lomask
= (0xffff << shift
) & 0xffffffff;
8938 himask
= 0xffff << (shift
- 32);
8941 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8942 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8946 tmp
.X_op
= O_constant
;
8948 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8949 | (lo32
.X_add_number
>> shift
));
8951 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8952 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8953 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8954 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8959 while (shift
<= (64 - 16));
8961 /* Find the bit number of the lowest one bit, and store the
8962 shifted value in hi/lo. */
8963 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8964 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8968 while ((lo
& 1) == 0)
8973 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8979 while ((hi
& 1) == 0)
8988 /* Optimize if the shifted value is a (power of 2) - 1. */
8989 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
8990 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
8992 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
8997 /* This instruction will set the register to be all
8999 tmp
.X_op
= O_constant
;
9000 tmp
.X_add_number
= (offsetT
) -1;
9001 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9005 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9006 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9008 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9009 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9014 /* Sign extend hi32 before calling load_register, because we can
9015 generally get better code when we load a sign extended value. */
9016 if ((hi32
.X_add_number
& 0x80000000) != 0)
9017 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9018 load_register (reg
, &hi32
, 0);
9021 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9025 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9033 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9035 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9036 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9042 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9046 mid16
.X_add_number
>>= 16;
9047 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9048 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9051 if ((lo32
.X_add_number
& 0xffff) != 0)
9052 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9056 load_delay_nop (void)
9058 if (!gpr_interlocks
)
9059 macro_build (NULL
, "nop", "");
9062 /* Load an address into a register. */
9065 load_address (int reg
, expressionS
*ep
, int *used_at
)
9067 if (ep
->X_op
!= O_constant
9068 && ep
->X_op
!= O_symbol
)
9070 as_bad (_("expression too complex"));
9071 ep
->X_op
= O_constant
;
9074 if (ep
->X_op
== O_constant
)
9076 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9080 if (mips_pic
== NO_PIC
)
9082 /* If this is a reference to a GP relative symbol, we want
9083 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9085 lui $reg,<sym> (BFD_RELOC_HI16_S)
9086 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9087 If we have an addend, we always use the latter form.
9089 With 64bit address space and a usable $at we want
9090 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9091 lui $at,<sym> (BFD_RELOC_HI16_S)
9092 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9093 daddiu $at,<sym> (BFD_RELOC_LO16)
9097 If $at is already in use, we use a path which is suboptimal
9098 on superscalar processors.
9099 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9100 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9102 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9104 daddiu $reg,<sym> (BFD_RELOC_LO16)
9106 For GP relative symbols in 64bit address space we can use
9107 the same sequence as in 32bit address space. */
9108 if (HAVE_64BIT_SYMBOLS
)
9110 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9111 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9113 relax_start (ep
->X_add_symbol
);
9114 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9115 mips_gp_register
, BFD_RELOC_GPREL16
);
9119 if (*used_at
== 0 && mips_opts
.at
)
9121 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9122 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9123 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9124 BFD_RELOC_MIPS_HIGHER
);
9125 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9126 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9127 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9132 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9133 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9134 BFD_RELOC_MIPS_HIGHER
);
9135 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9136 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9137 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9138 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9141 if (mips_relax
.sequence
)
9146 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9147 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9149 relax_start (ep
->X_add_symbol
);
9150 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9151 mips_gp_register
, BFD_RELOC_GPREL16
);
9154 macro_build_lui (ep
, reg
);
9155 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9156 reg
, reg
, BFD_RELOC_LO16
);
9157 if (mips_relax
.sequence
)
9161 else if (!mips_big_got
)
9165 /* If this is a reference to an external symbol, we want
9166 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9168 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9170 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9171 If there is a constant, it must be added in after.
9173 If we have NewABI, we want
9174 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9175 unless we're referencing a global symbol with a non-zero
9176 offset, in which case cst must be added separately. */
9179 if (ep
->X_add_number
)
9181 ex
.X_add_number
= ep
->X_add_number
;
9182 ep
->X_add_number
= 0;
9183 relax_start (ep
->X_add_symbol
);
9184 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9185 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9186 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9187 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9188 ex
.X_op
= O_constant
;
9189 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9190 reg
, reg
, BFD_RELOC_LO16
);
9191 ep
->X_add_number
= ex
.X_add_number
;
9194 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9195 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9196 if (mips_relax
.sequence
)
9201 ex
.X_add_number
= ep
->X_add_number
;
9202 ep
->X_add_number
= 0;
9203 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9204 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9206 relax_start (ep
->X_add_symbol
);
9208 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9212 if (ex
.X_add_number
!= 0)
9214 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9215 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9216 ex
.X_op
= O_constant
;
9217 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9218 reg
, reg
, BFD_RELOC_LO16
);
9222 else if (mips_big_got
)
9226 /* This is the large GOT case. If this is a reference to an
9227 external symbol, we want
9228 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9230 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9232 Otherwise, for a reference to a local symbol in old ABI, we want
9233 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9235 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9236 If there is a constant, it must be added in after.
9238 In the NewABI, for local symbols, with or without offsets, we want:
9239 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9240 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9244 ex
.X_add_number
= ep
->X_add_number
;
9245 ep
->X_add_number
= 0;
9246 relax_start (ep
->X_add_symbol
);
9247 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9248 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9249 reg
, reg
, mips_gp_register
);
9250 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9251 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9252 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9253 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9254 else if (ex
.X_add_number
)
9256 ex
.X_op
= O_constant
;
9257 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9261 ep
->X_add_number
= ex
.X_add_number
;
9263 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9264 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9265 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9266 BFD_RELOC_MIPS_GOT_OFST
);
9271 ex
.X_add_number
= ep
->X_add_number
;
9272 ep
->X_add_number
= 0;
9273 relax_start (ep
->X_add_symbol
);
9274 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9275 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9276 reg
, reg
, mips_gp_register
);
9277 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9278 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9280 if (reg_needs_delay (mips_gp_register
))
9282 /* We need a nop before loading from $gp. This special
9283 check is required because the lui which starts the main
9284 instruction stream does not refer to $gp, and so will not
9285 insert the nop which may be required. */
9286 macro_build (NULL
, "nop", "");
9288 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9289 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9291 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9295 if (ex
.X_add_number
!= 0)
9297 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9298 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9299 ex
.X_op
= O_constant
;
9300 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9308 if (!mips_opts
.at
&& *used_at
== 1)
9309 as_bad (_("macro used $at after \".set noat\""));
9312 /* Move the contents of register SOURCE into register DEST. */
9315 move_register (int dest
, int source
)
9317 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9318 instruction specifically requires a 32-bit one. */
9319 if (mips_opts
.micromips
9320 && !mips_opts
.insn32
9321 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9322 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9324 macro_build (NULL
, GPR_SIZE
== 32 ? "addu" : "daddu", "d,v,t",
9328 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9329 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9330 The two alternatives are:
9332 Global symbol Local sybmol
9333 ------------- ------------
9334 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9336 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9338 load_got_offset emits the first instruction and add_got_offset
9339 emits the second for a 16-bit offset or add_got_offset_hilo emits
9340 a sequence to add a 32-bit offset using a scratch register. */
9343 load_got_offset (int dest
, expressionS
*local
)
9348 global
.X_add_number
= 0;
9350 relax_start (local
->X_add_symbol
);
9351 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9352 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9354 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9355 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9360 add_got_offset (int dest
, expressionS
*local
)
9364 global
.X_op
= O_constant
;
9365 global
.X_op_symbol
= NULL
;
9366 global
.X_add_symbol
= NULL
;
9367 global
.X_add_number
= local
->X_add_number
;
9369 relax_start (local
->X_add_symbol
);
9370 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9371 dest
, dest
, BFD_RELOC_LO16
);
9373 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9378 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9381 int hold_mips_optimize
;
9383 global
.X_op
= O_constant
;
9384 global
.X_op_symbol
= NULL
;
9385 global
.X_add_symbol
= NULL
;
9386 global
.X_add_number
= local
->X_add_number
;
9388 relax_start (local
->X_add_symbol
);
9389 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9391 /* Set mips_optimize around the lui instruction to avoid
9392 inserting an unnecessary nop after the lw. */
9393 hold_mips_optimize
= mips_optimize
;
9395 macro_build_lui (&global
, tmp
);
9396 mips_optimize
= hold_mips_optimize
;
9397 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9400 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9403 /* Emit a sequence of instructions to emulate a branch likely operation.
9404 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9405 is its complementing branch with the original condition negated.
9406 CALL is set if the original branch specified the link operation.
9407 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9409 Code like this is produced in the noreorder mode:
9414 delay slot (executed only if branch taken)
9422 delay slot (executed only if branch taken)
9425 In the reorder mode the delay slot would be filled with a nop anyway,
9426 so code produced is simply:
9431 This function is used when producing code for the microMIPS ASE that
9432 does not implement branch likely instructions in hardware. */
9435 macro_build_branch_likely (const char *br
, const char *brneg
,
9436 int call
, expressionS
*ep
, const char *fmt
,
9437 unsigned int sreg
, unsigned int treg
)
9439 int noreorder
= mips_opts
.noreorder
;
9442 gas_assert (mips_opts
.micromips
);
9446 micromips_label_expr (&expr1
);
9447 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9448 macro_build (NULL
, "nop", "");
9449 macro_build (ep
, call
? "bal" : "b", "p");
9451 /* Set to true so that append_insn adds a label. */
9452 emit_branch_likely_macro
= TRUE
;
9456 macro_build (ep
, br
, fmt
, sreg
, treg
);
9457 macro_build (NULL
, "nop", "");
9462 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9463 the condition code tested. EP specifies the branch target. */
9466 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9493 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9496 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9497 the register tested. EP specifies the branch target. */
9500 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9502 const char *brneg
= NULL
;
9512 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9516 gas_assert (mips_opts
.micromips
);
9517 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9525 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9532 br
= mips_opts
.micromips
? "blez" : "blezl";
9539 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9543 gas_assert (mips_opts
.micromips
);
9544 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9551 if (mips_opts
.micromips
&& brneg
)
9552 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9554 macro_build (ep
, br
, "s,p", sreg
);
9557 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9558 TREG as the registers tested. EP specifies the branch target. */
9561 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9562 unsigned int sreg
, unsigned int treg
)
9564 const char *brneg
= NULL
;
9576 br
= mips_opts
.micromips
? "beq" : "beql";
9585 br
= mips_opts
.micromips
? "bne" : "bnel";
9591 if (mips_opts
.micromips
&& brneg
)
9592 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9594 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9597 /* Return the high part that should be loaded in order to make the low
9598 part of VALUE accessible using an offset of OFFBITS bits. */
9601 offset_high_part (offsetT value
, unsigned int offbits
)
9608 bias
= 1 << (offbits
- 1);
9609 low_mask
= bias
* 2 - 1;
9610 return (value
+ bias
) & ~low_mask
;
9613 /* Return true if the value stored in offset_expr and offset_reloc
9614 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9615 amount that the caller wants to add without inducing overflow
9616 and ALIGN is the known alignment of the value in bytes. */
9619 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9623 /* Accept any relocation operator if overflow isn't a concern. */
9624 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9627 /* These relocations are guaranteed not to overflow in correct links. */
9628 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9629 || gprel16_reloc_p (*offset_reloc
))
9632 if (offset_expr
.X_op
== O_constant
9633 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9634 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9641 * This routine implements the seemingly endless macro or synthesized
9642 * instructions and addressing modes in the mips assembly language. Many
9643 * of these macros are simple and are similar to each other. These could
9644 * probably be handled by some kind of table or grammar approach instead of
9645 * this verbose method. Others are not simple macros but are more like
9646 * optimizing code generation.
9647 * One interesting optimization is when several store macros appear
9648 * consecutively that would load AT with the upper half of the same address.
9649 * The ensuing load upper instructions are ommited. This implies some kind
9650 * of global optimization. We currently only optimize within a single macro.
9651 * For many of the load and store macros if the address is specified as a
9652 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9653 * first load register 'at' with zero and use it as the base register. The
9654 * mips assembler simply uses register $zero. Just one tiny optimization
9658 macro (struct mips_cl_insn
*ip
, char *str
)
9660 const struct mips_operand_array
*operands
;
9661 unsigned int breg
, i
;
9662 unsigned int tempreg
;
9665 expressionS label_expr
;
9680 bfd_boolean large_offset
;
9682 int hold_mips_optimize
;
9684 unsigned int op
[MAX_OPERANDS
];
9686 gas_assert (! mips_opts
.mips16
);
9688 operands
= insn_operands (ip
);
9689 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9690 if (operands
->operand
[i
])
9691 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9695 mask
= ip
->insn_mo
->mask
;
9697 label_expr
.X_op
= O_constant
;
9698 label_expr
.X_op_symbol
= NULL
;
9699 label_expr
.X_add_symbol
= NULL
;
9700 label_expr
.X_add_number
= 0;
9702 expr1
.X_op
= O_constant
;
9703 expr1
.X_op_symbol
= NULL
;
9704 expr1
.X_add_symbol
= NULL
;
9705 expr1
.X_add_number
= 1;
9721 if (mips_opts
.micromips
)
9722 micromips_label_expr (&label_expr
);
9724 label_expr
.X_add_number
= 8;
9725 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9727 macro_build (NULL
, "nop", "");
9729 move_register (op
[0], op
[1]);
9730 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9731 if (mips_opts
.micromips
)
9732 micromips_add_label ();
9749 if (!mips_opts
.micromips
)
9751 if (imm_expr
.X_add_number
>= -0x200
9752 && imm_expr
.X_add_number
< 0x200)
9754 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9755 (int) imm_expr
.X_add_number
);
9764 if (imm_expr
.X_add_number
>= -0x8000
9765 && imm_expr
.X_add_number
< 0x8000)
9767 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9772 load_register (AT
, &imm_expr
, dbl
);
9773 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9792 if (imm_expr
.X_add_number
>= 0
9793 && imm_expr
.X_add_number
< 0x10000)
9795 if (mask
!= M_NOR_I
)
9796 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9799 macro_build (&imm_expr
, "ori", "t,r,i",
9800 op
[0], op
[1], BFD_RELOC_LO16
);
9801 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9807 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9808 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9812 switch (imm_expr
.X_add_number
)
9815 macro_build (NULL
, "nop", "");
9818 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9822 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9823 (int) imm_expr
.X_add_number
);
9826 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9827 (unsigned long) imm_expr
.X_add_number
);
9836 gas_assert (mips_opts
.micromips
);
9837 macro_build_branch_ccl (mask
, &offset_expr
,
9838 EXTRACT_OPERAND (1, BCC
, *ip
));
9845 if (imm_expr
.X_add_number
== 0)
9851 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
9856 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9863 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9864 else if (op
[0] == 0)
9865 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9869 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9870 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9871 &offset_expr
, AT
, ZERO
);
9881 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9887 /* Check for > max integer. */
9888 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9891 /* Result is always false. */
9893 macro_build (NULL
, "nop", "");
9895 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9898 ++imm_expr
.X_add_number
;
9902 if (mask
== M_BGEL_I
)
9904 if (imm_expr
.X_add_number
== 0)
9906 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9907 &offset_expr
, op
[0]);
9910 if (imm_expr
.X_add_number
== 1)
9912 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9913 &offset_expr
, op
[0]);
9916 if (imm_expr
.X_add_number
<= GPR_SMIN
)
9919 /* result is always true */
9920 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
9921 macro_build (&offset_expr
, "b", "p");
9926 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9927 &offset_expr
, AT
, ZERO
);
9935 else if (op
[0] == 0)
9936 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9937 &offset_expr
, ZERO
, op
[1]);
9941 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9942 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9943 &offset_expr
, AT
, ZERO
);
9952 && imm_expr
.X_add_number
== -1))
9954 ++imm_expr
.X_add_number
;
9958 if (mask
== M_BGEUL_I
)
9960 if (imm_expr
.X_add_number
== 0)
9962 else if (imm_expr
.X_add_number
== 1)
9963 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9964 &offset_expr
, op
[0], ZERO
);
9969 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9970 &offset_expr
, AT
, ZERO
);
9978 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9979 else if (op
[0] == 0)
9980 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9984 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9985 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9986 &offset_expr
, AT
, ZERO
);
9994 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9995 &offset_expr
, op
[0], ZERO
);
9996 else if (op
[0] == 0)
10001 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10002 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10003 &offset_expr
, AT
, ZERO
);
10011 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10012 else if (op
[0] == 0)
10013 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10017 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10018 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10019 &offset_expr
, AT
, ZERO
);
10026 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10028 ++imm_expr
.X_add_number
;
10032 if (mask
== M_BLTL_I
)
10034 if (imm_expr
.X_add_number
== 0)
10035 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10036 else if (imm_expr
.X_add_number
== 1)
10037 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10042 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10043 &offset_expr
, AT
, ZERO
);
10051 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10052 &offset_expr
, op
[0], ZERO
);
10053 else if (op
[0] == 0)
10058 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10059 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10060 &offset_expr
, AT
, ZERO
);
10069 && imm_expr
.X_add_number
== -1))
10071 ++imm_expr
.X_add_number
;
10075 if (mask
== M_BLTUL_I
)
10077 if (imm_expr
.X_add_number
== 0)
10079 else if (imm_expr
.X_add_number
== 1)
10080 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10081 &offset_expr
, op
[0], ZERO
);
10086 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10087 &offset_expr
, AT
, ZERO
);
10095 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10096 else if (op
[0] == 0)
10097 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10101 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10102 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10103 &offset_expr
, AT
, ZERO
);
10112 else if (op
[0] == 0)
10113 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10114 &offset_expr
, ZERO
, op
[1]);
10118 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10119 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10120 &offset_expr
, AT
, ZERO
);
10136 as_warn (_("divide by zero"));
10138 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10140 macro_build (NULL
, "break", BRK_FMT
, 7);
10144 start_noreorder ();
10147 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10148 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10152 if (mips_opts
.micromips
)
10153 micromips_label_expr (&label_expr
);
10155 label_expr
.X_add_number
= 8;
10156 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10157 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10158 macro_build (NULL
, "break", BRK_FMT
, 7);
10159 if (mips_opts
.micromips
)
10160 micromips_add_label ();
10162 expr1
.X_add_number
= -1;
10164 load_register (AT
, &expr1
, dbl
);
10165 if (mips_opts
.micromips
)
10166 micromips_label_expr (&label_expr
);
10168 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10169 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10172 expr1
.X_add_number
= 1;
10173 load_register (AT
, &expr1
, dbl
);
10174 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10178 expr1
.X_add_number
= 0x80000000;
10179 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10183 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10184 /* We want to close the noreorder block as soon as possible, so
10185 that later insns are available for delay slot filling. */
10190 if (mips_opts
.micromips
)
10191 micromips_label_expr (&label_expr
);
10193 label_expr
.X_add_number
= 8;
10194 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10195 macro_build (NULL
, "nop", "");
10197 /* We want to close the noreorder block as soon as possible, so
10198 that later insns are available for delay slot filling. */
10201 macro_build (NULL
, "break", BRK_FMT
, 6);
10203 if (mips_opts
.micromips
)
10204 micromips_add_label ();
10205 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10244 if (imm_expr
.X_add_number
== 0)
10246 as_warn (_("divide by zero"));
10248 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10250 macro_build (NULL
, "break", BRK_FMT
, 7);
10253 if (imm_expr
.X_add_number
== 1)
10255 if (strcmp (s2
, "mflo") == 0)
10256 move_register (op
[0], op
[1]);
10258 move_register (op
[0], ZERO
);
10261 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10263 if (strcmp (s2
, "mflo") == 0)
10264 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10266 move_register (op
[0], ZERO
);
10271 load_register (AT
, &imm_expr
, dbl
);
10272 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10273 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10292 start_noreorder ();
10295 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10296 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10297 /* We want to close the noreorder block as soon as possible, so
10298 that later insns are available for delay slot filling. */
10303 if (mips_opts
.micromips
)
10304 micromips_label_expr (&label_expr
);
10306 label_expr
.X_add_number
= 8;
10307 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10308 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10310 /* We want to close the noreorder block as soon as possible, so
10311 that later insns are available for delay slot filling. */
10313 macro_build (NULL
, "break", BRK_FMT
, 7);
10314 if (mips_opts
.micromips
)
10315 micromips_add_label ();
10317 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10329 /* Load the address of a symbol into a register. If breg is not
10330 zero, we then add a base register to it. */
10333 if (dbl
&& GPR_SIZE
== 32)
10334 as_warn (_("dla used to load 32-bit register; recommend using la "
10337 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10338 as_warn (_("la used to load 64-bit address; recommend using dla "
10341 if (small_offset_p (0, align
, 16))
10343 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10344 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10348 if (mips_opts
.at
&& (op
[0] == breg
))
10356 if (offset_expr
.X_op
!= O_symbol
10357 && offset_expr
.X_op
!= O_constant
)
10359 as_bad (_("expression too complex"));
10360 offset_expr
.X_op
= O_constant
;
10363 if (offset_expr
.X_op
== O_constant
)
10364 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10365 else if (mips_pic
== NO_PIC
)
10367 /* If this is a reference to a GP relative symbol, we want
10368 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10370 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10371 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10372 If we have a constant, we need two instructions anyhow,
10373 so we may as well always use the latter form.
10375 With 64bit address space and a usable $at we want
10376 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10377 lui $at,<sym> (BFD_RELOC_HI16_S)
10378 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10379 daddiu $at,<sym> (BFD_RELOC_LO16)
10381 daddu $tempreg,$tempreg,$at
10383 If $at is already in use, we use a path which is suboptimal
10384 on superscalar processors.
10385 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10386 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10388 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10390 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10392 For GP relative symbols in 64bit address space we can use
10393 the same sequence as in 32bit address space. */
10394 if (HAVE_64BIT_SYMBOLS
)
10396 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10397 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10399 relax_start (offset_expr
.X_add_symbol
);
10400 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10401 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10405 if (used_at
== 0 && mips_opts
.at
)
10407 macro_build (&offset_expr
, "lui", LUI_FMT
,
10408 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10409 macro_build (&offset_expr
, "lui", LUI_FMT
,
10410 AT
, BFD_RELOC_HI16_S
);
10411 macro_build (&offset_expr
, "daddiu", "t,r,j",
10412 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10413 macro_build (&offset_expr
, "daddiu", "t,r,j",
10414 AT
, AT
, BFD_RELOC_LO16
);
10415 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10416 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10421 macro_build (&offset_expr
, "lui", LUI_FMT
,
10422 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10423 macro_build (&offset_expr
, "daddiu", "t,r,j",
10424 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10425 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10426 macro_build (&offset_expr
, "daddiu", "t,r,j",
10427 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10428 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10429 macro_build (&offset_expr
, "daddiu", "t,r,j",
10430 tempreg
, tempreg
, BFD_RELOC_LO16
);
10433 if (mips_relax
.sequence
)
10438 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10439 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10441 relax_start (offset_expr
.X_add_symbol
);
10442 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10443 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10446 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10447 as_bad (_("offset too large"));
10448 macro_build_lui (&offset_expr
, tempreg
);
10449 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10450 tempreg
, tempreg
, BFD_RELOC_LO16
);
10451 if (mips_relax
.sequence
)
10455 else if (!mips_big_got
&& !HAVE_NEWABI
)
10457 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10459 /* If this is a reference to an external symbol, and there
10460 is no constant, we want
10461 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10462 or for lca or if tempreg is PIC_CALL_REG
10463 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10464 For a local symbol, we want
10465 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10467 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10469 If we have a small constant, and this is a reference to
10470 an external symbol, we want
10471 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10473 addiu $tempreg,$tempreg,<constant>
10474 For a local symbol, we want the same instruction
10475 sequence, but we output a BFD_RELOC_LO16 reloc on the
10478 If we have a large constant, and this is a reference to
10479 an external symbol, we want
10480 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10481 lui $at,<hiconstant>
10482 addiu $at,$at,<loconstant>
10483 addu $tempreg,$tempreg,$at
10484 For a local symbol, we want the same instruction
10485 sequence, but we output a BFD_RELOC_LO16 reloc on the
10489 if (offset_expr
.X_add_number
== 0)
10491 if (mips_pic
== SVR4_PIC
10493 && (call
|| tempreg
== PIC_CALL_REG
))
10494 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10496 relax_start (offset_expr
.X_add_symbol
);
10497 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10498 lw_reloc_type
, mips_gp_register
);
10501 /* We're going to put in an addu instruction using
10502 tempreg, so we may as well insert the nop right
10507 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10508 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10510 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10511 tempreg
, tempreg
, BFD_RELOC_LO16
);
10513 /* FIXME: If breg == 0, and the next instruction uses
10514 $tempreg, then if this variant case is used an extra
10515 nop will be generated. */
10517 else if (offset_expr
.X_add_number
>= -0x8000
10518 && offset_expr
.X_add_number
< 0x8000)
10520 load_got_offset (tempreg
, &offset_expr
);
10522 add_got_offset (tempreg
, &offset_expr
);
10526 expr1
.X_add_number
= offset_expr
.X_add_number
;
10527 offset_expr
.X_add_number
=
10528 SEXT_16BIT (offset_expr
.X_add_number
);
10529 load_got_offset (tempreg
, &offset_expr
);
10530 offset_expr
.X_add_number
= expr1
.X_add_number
;
10531 /* If we are going to add in a base register, and the
10532 target register and the base register are the same,
10533 then we are using AT as a temporary register. Since
10534 we want to load the constant into AT, we add our
10535 current AT (from the global offset table) and the
10536 register into the register now, and pretend we were
10537 not using a base register. */
10541 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10546 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10550 else if (!mips_big_got
&& HAVE_NEWABI
)
10552 int add_breg_early
= 0;
10554 /* If this is a reference to an external, and there is no
10555 constant, or local symbol (*), with or without a
10557 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10558 or for lca or if tempreg is PIC_CALL_REG
10559 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10561 If we have a small constant, and this is a reference to
10562 an external symbol, we want
10563 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10564 addiu $tempreg,$tempreg,<constant>
10566 If we have a large constant, and this is a reference to
10567 an external symbol, we want
10568 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10569 lui $at,<hiconstant>
10570 addiu $at,$at,<loconstant>
10571 addu $tempreg,$tempreg,$at
10573 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10574 local symbols, even though it introduces an additional
10577 if (offset_expr
.X_add_number
)
10579 expr1
.X_add_number
= offset_expr
.X_add_number
;
10580 offset_expr
.X_add_number
= 0;
10582 relax_start (offset_expr
.X_add_symbol
);
10583 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10584 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10586 if (expr1
.X_add_number
>= -0x8000
10587 && expr1
.X_add_number
< 0x8000)
10589 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10590 tempreg
, tempreg
, BFD_RELOC_LO16
);
10592 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10596 /* If we are going to add in a base register, and the
10597 target register and the base register are the same,
10598 then we are using AT as a temporary register. Since
10599 we want to load the constant into AT, we add our
10600 current AT (from the global offset table) and the
10601 register into the register now, and pretend we were
10602 not using a base register. */
10607 gas_assert (tempreg
== AT
);
10608 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10611 add_breg_early
= 1;
10614 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10615 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10621 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10624 offset_expr
.X_add_number
= expr1
.X_add_number
;
10626 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10627 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10628 if (add_breg_early
)
10630 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10631 op
[0], tempreg
, breg
);
10637 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10639 relax_start (offset_expr
.X_add_symbol
);
10640 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10641 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10643 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10644 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10649 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10650 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10653 else if (mips_big_got
&& !HAVE_NEWABI
)
10656 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10657 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10658 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10660 /* This is the large GOT case. If this is a reference to an
10661 external symbol, and there is no constant, we want
10662 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10663 addu $tempreg,$tempreg,$gp
10664 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10665 or for lca or if tempreg is PIC_CALL_REG
10666 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10667 addu $tempreg,$tempreg,$gp
10668 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10669 For a local symbol, we want
10670 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10672 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10674 If we have a small constant, and this is a reference to
10675 an external symbol, we want
10676 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10677 addu $tempreg,$tempreg,$gp
10678 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10680 addiu $tempreg,$tempreg,<constant>
10681 For a local symbol, we want
10682 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10684 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10686 If we have a large constant, and this is a reference to
10687 an external symbol, we want
10688 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10689 addu $tempreg,$tempreg,$gp
10690 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10691 lui $at,<hiconstant>
10692 addiu $at,$at,<loconstant>
10693 addu $tempreg,$tempreg,$at
10694 For a local symbol, we want
10695 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10696 lui $at,<hiconstant>
10697 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10698 addu $tempreg,$tempreg,$at
10701 expr1
.X_add_number
= offset_expr
.X_add_number
;
10702 offset_expr
.X_add_number
= 0;
10703 relax_start (offset_expr
.X_add_symbol
);
10704 gpdelay
= reg_needs_delay (mips_gp_register
);
10705 if (expr1
.X_add_number
== 0 && breg
== 0
10706 && (call
|| tempreg
== PIC_CALL_REG
))
10708 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10709 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10711 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10712 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10713 tempreg
, tempreg
, mips_gp_register
);
10714 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10715 tempreg
, lw_reloc_type
, tempreg
);
10716 if (expr1
.X_add_number
== 0)
10720 /* We're going to put in an addu instruction using
10721 tempreg, so we may as well insert the nop right
10726 else if (expr1
.X_add_number
>= -0x8000
10727 && expr1
.X_add_number
< 0x8000)
10730 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10731 tempreg
, tempreg
, BFD_RELOC_LO16
);
10737 /* If we are going to add in a base register, and the
10738 target register and the base register are the same,
10739 then we are using AT as a temporary register. Since
10740 we want to load the constant into AT, we add our
10741 current AT (from the global offset table) and the
10742 register into the register now, and pretend we were
10743 not using a base register. */
10748 gas_assert (tempreg
== AT
);
10750 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10755 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10756 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10760 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10765 /* This is needed because this instruction uses $gp, but
10766 the first instruction on the main stream does not. */
10767 macro_build (NULL
, "nop", "");
10770 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10771 local_reloc_type
, mips_gp_register
);
10772 if (expr1
.X_add_number
>= -0x8000
10773 && expr1
.X_add_number
< 0x8000)
10776 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10777 tempreg
, tempreg
, BFD_RELOC_LO16
);
10778 /* FIXME: If add_number is 0, and there was no base
10779 register, the external symbol case ended with a load,
10780 so if the symbol turns out to not be external, and
10781 the next instruction uses tempreg, an unnecessary nop
10782 will be inserted. */
10788 /* We must add in the base register now, as in the
10789 external symbol case. */
10790 gas_assert (tempreg
== AT
);
10792 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10795 /* We set breg to 0 because we have arranged to add
10796 it in in both cases. */
10800 macro_build_lui (&expr1
, AT
);
10801 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10802 AT
, AT
, BFD_RELOC_LO16
);
10803 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10804 tempreg
, tempreg
, AT
);
10809 else if (mips_big_got
&& HAVE_NEWABI
)
10811 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10812 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10813 int add_breg_early
= 0;
10815 /* This is the large GOT case. If this is a reference to an
10816 external symbol, and there is no constant, we want
10817 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10818 add $tempreg,$tempreg,$gp
10819 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10820 or for lca or if tempreg is PIC_CALL_REG
10821 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10822 add $tempreg,$tempreg,$gp
10823 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10825 If we have a small constant, and this is a reference to
10826 an external symbol, we want
10827 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10828 add $tempreg,$tempreg,$gp
10829 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10830 addi $tempreg,$tempreg,<constant>
10832 If we have a large constant, and this is a reference to
10833 an external symbol, we want
10834 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10835 addu $tempreg,$tempreg,$gp
10836 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10837 lui $at,<hiconstant>
10838 addi $at,$at,<loconstant>
10839 add $tempreg,$tempreg,$at
10841 If we have NewABI, and we know it's a local symbol, we want
10842 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10843 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10844 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10846 relax_start (offset_expr
.X_add_symbol
);
10848 expr1
.X_add_number
= offset_expr
.X_add_number
;
10849 offset_expr
.X_add_number
= 0;
10851 if (expr1
.X_add_number
== 0 && breg
== 0
10852 && (call
|| tempreg
== PIC_CALL_REG
))
10854 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10855 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10857 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10858 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10859 tempreg
, tempreg
, mips_gp_register
);
10860 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10861 tempreg
, lw_reloc_type
, tempreg
);
10863 if (expr1
.X_add_number
== 0)
10865 else if (expr1
.X_add_number
>= -0x8000
10866 && expr1
.X_add_number
< 0x8000)
10868 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10869 tempreg
, tempreg
, BFD_RELOC_LO16
);
10871 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10875 /* If we are going to add in a base register, and the
10876 target register and the base register are the same,
10877 then we are using AT as a temporary register. Since
10878 we want to load the constant into AT, we add our
10879 current AT (from the global offset table) and the
10880 register into the register now, and pretend we were
10881 not using a base register. */
10886 gas_assert (tempreg
== AT
);
10887 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10890 add_breg_early
= 1;
10893 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10894 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10899 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10902 offset_expr
.X_add_number
= expr1
.X_add_number
;
10903 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10904 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10905 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10906 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10907 if (add_breg_early
)
10909 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10910 op
[0], tempreg
, breg
);
10920 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10924 gas_assert (!mips_opts
.micromips
);
10925 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10929 gas_assert (!mips_opts
.micromips
);
10930 macro_build (NULL
, "c2", "C", 0x02);
10934 gas_assert (!mips_opts
.micromips
);
10935 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10939 gas_assert (!mips_opts
.micromips
);
10940 macro_build (NULL
, "c2", "C", 3);
10944 gas_assert (!mips_opts
.micromips
);
10945 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10949 /* The j instruction may not be used in PIC code, since it
10950 requires an absolute address. We convert it to a b
10952 if (mips_pic
== NO_PIC
)
10953 macro_build (&offset_expr
, "j", "a");
10955 macro_build (&offset_expr
, "b", "p");
10958 /* The jal instructions must be handled as macros because when
10959 generating PIC code they expand to multi-instruction
10960 sequences. Normally they are simple instructions. */
10964 /* Fall through. */
10966 gas_assert (mips_opts
.micromips
);
10967 if (mips_opts
.insn32
)
10969 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10977 /* Fall through. */
10980 if (mips_pic
== NO_PIC
)
10982 s
= jals
? "jalrs" : "jalr";
10983 if (mips_opts
.micromips
10984 && !mips_opts
.insn32
10986 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10987 macro_build (NULL
, s
, "mj", op
[1]);
10989 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10993 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
10994 && mips_cprestore_offset
>= 0);
10996 if (op
[1] != PIC_CALL_REG
)
10997 as_warn (_("MIPS PIC call to register other than $25"));
10999 s
= ((mips_opts
.micromips
11000 && !mips_opts
.insn32
11001 && (!mips_opts
.noreorder
|| cprestore
))
11002 ? "jalrs" : "jalr");
11003 if (mips_opts
.micromips
11004 && !mips_opts
.insn32
11006 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11007 macro_build (NULL
, s
, "mj", op
[1]);
11009 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11010 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11012 if (mips_cprestore_offset
< 0)
11013 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11016 if (!mips_frame_reg_valid
)
11018 as_warn (_("no .frame pseudo-op used in PIC code"));
11019 /* Quiet this warning. */
11020 mips_frame_reg_valid
= 1;
11022 if (!mips_cprestore_valid
)
11024 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11025 /* Quiet this warning. */
11026 mips_cprestore_valid
= 1;
11028 if (mips_opts
.noreorder
)
11029 macro_build (NULL
, "nop", "");
11030 expr1
.X_add_number
= mips_cprestore_offset
;
11031 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11034 HAVE_64BIT_ADDRESSES
);
11042 gas_assert (mips_opts
.micromips
);
11043 if (mips_opts
.insn32
)
11045 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11049 /* Fall through. */
11051 if (mips_pic
== NO_PIC
)
11052 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11053 else if (mips_pic
== SVR4_PIC
)
11055 /* If this is a reference to an external symbol, and we are
11056 using a small GOT, we want
11057 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11061 lw $gp,cprestore($sp)
11062 The cprestore value is set using the .cprestore
11063 pseudo-op. If we are using a big GOT, we want
11064 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11066 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11070 lw $gp,cprestore($sp)
11071 If the symbol is not external, we want
11072 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11074 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11077 lw $gp,cprestore($sp)
11079 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11080 sequences above, minus nops, unless the symbol is local,
11081 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11087 relax_start (offset_expr
.X_add_symbol
);
11088 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11089 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11092 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11093 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11099 relax_start (offset_expr
.X_add_symbol
);
11100 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11101 BFD_RELOC_MIPS_CALL_HI16
);
11102 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11103 PIC_CALL_REG
, mips_gp_register
);
11104 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11105 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11108 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11109 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11111 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11112 PIC_CALL_REG
, PIC_CALL_REG
,
11113 BFD_RELOC_MIPS_GOT_OFST
);
11117 macro_build_jalr (&offset_expr
, 0);
11121 relax_start (offset_expr
.X_add_symbol
);
11124 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11125 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11134 gpdelay
= reg_needs_delay (mips_gp_register
);
11135 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11136 BFD_RELOC_MIPS_CALL_HI16
);
11137 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11138 PIC_CALL_REG
, mips_gp_register
);
11139 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11140 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11145 macro_build (NULL
, "nop", "");
11147 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11148 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11151 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11152 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11154 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11156 if (mips_cprestore_offset
< 0)
11157 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11160 if (!mips_frame_reg_valid
)
11162 as_warn (_("no .frame pseudo-op used in PIC code"));
11163 /* Quiet this warning. */
11164 mips_frame_reg_valid
= 1;
11166 if (!mips_cprestore_valid
)
11168 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11169 /* Quiet this warning. */
11170 mips_cprestore_valid
= 1;
11172 if (mips_opts
.noreorder
)
11173 macro_build (NULL
, "nop", "");
11174 expr1
.X_add_number
= mips_cprestore_offset
;
11175 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11178 HAVE_64BIT_ADDRESSES
);
11182 else if (mips_pic
== VXWORKS_PIC
)
11183 as_bad (_("non-PIC jump used in PIC library"));
11290 gas_assert (!mips_opts
.micromips
);
11293 /* Itbl support may require additional care here. */
11299 /* Itbl support may require additional care here. */
11305 offbits
= (mips_opts
.micromips
? 12
11306 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11308 /* Itbl support may require additional care here. */
11312 gas_assert (!mips_opts
.micromips
);
11315 /* Itbl support may require additional care here. */
11321 offbits
= (mips_opts
.micromips
? 12 : 16);
11326 offbits
= (mips_opts
.micromips
? 12 : 16);
11331 /* Itbl support may require additional care here. */
11337 offbits
= (mips_opts
.micromips
? 12
11338 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11340 /* Itbl support may require additional care here. */
11346 /* Itbl support may require additional care here. */
11352 /* Itbl support may require additional care here. */
11358 offbits
= (mips_opts
.micromips
? 12 : 16);
11363 offbits
= (mips_opts
.micromips
? 12 : 16);
11368 offbits
= (mips_opts
.micromips
? 12
11369 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11375 offbits
= (mips_opts
.micromips
? 12
11376 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11382 offbits
= (mips_opts
.micromips
? 12 : 16);
11385 gas_assert (mips_opts
.micromips
);
11392 gas_assert (mips_opts
.micromips
);
11399 gas_assert (mips_opts
.micromips
);
11405 gas_assert (mips_opts
.micromips
);
11412 /* We don't want to use $0 as tempreg. */
11413 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11416 tempreg
= op
[0] + lp
;
11432 gas_assert (!mips_opts
.micromips
);
11435 /* Itbl support may require additional care here. */
11441 /* Itbl support may require additional care here. */
11447 offbits
= (mips_opts
.micromips
? 12
11448 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11450 /* Itbl support may require additional care here. */
11454 gas_assert (!mips_opts
.micromips
);
11457 /* Itbl support may require additional care here. */
11463 offbits
= (mips_opts
.micromips
? 12 : 16);
11468 offbits
= (mips_opts
.micromips
? 12 : 16);
11473 offbits
= (mips_opts
.micromips
? 12
11474 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11480 offbits
= (mips_opts
.micromips
? 12
11481 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11486 fmt
= (mips_opts
.micromips
? "k,~(b)"
11487 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11489 offbits
= (mips_opts
.micromips
? 12
11490 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11500 fmt
= (mips_opts
.micromips
? "k,~(b)"
11501 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11503 offbits
= (mips_opts
.micromips
? 12
11504 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11516 /* Itbl support may require additional care here. */
11521 offbits
= (mips_opts
.micromips
? 12
11522 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11524 /* Itbl support may require additional care here. */
11530 /* Itbl support may require additional care here. */
11534 gas_assert (!mips_opts
.micromips
);
11537 /* Itbl support may require additional care here. */
11543 offbits
= (mips_opts
.micromips
? 12 : 16);
11548 offbits
= (mips_opts
.micromips
? 12 : 16);
11551 gas_assert (mips_opts
.micromips
);
11557 gas_assert (mips_opts
.micromips
);
11563 gas_assert (mips_opts
.micromips
);
11569 gas_assert (mips_opts
.micromips
);
11578 if (small_offset_p (0, align
, 16))
11580 /* The first case exists for M_LD_AB and M_SD_AB, which are
11581 macros for o32 but which should act like normal instructions
11584 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11585 offset_reloc
[1], offset_reloc
[2], breg
);
11586 else if (small_offset_p (0, align
, offbits
))
11589 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11591 macro_build (NULL
, s
, fmt
, op
[0],
11592 (int) offset_expr
.X_add_number
, breg
);
11598 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11599 tempreg
, breg
, -1, offset_reloc
[0],
11600 offset_reloc
[1], offset_reloc
[2]);
11602 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11604 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11612 if (offset_expr
.X_op
!= O_constant
11613 && offset_expr
.X_op
!= O_symbol
)
11615 as_bad (_("expression too complex"));
11616 offset_expr
.X_op
= O_constant
;
11619 if (HAVE_32BIT_ADDRESSES
11620 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11624 sprintf_vma (value
, offset_expr
.X_add_number
);
11625 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11628 /* A constant expression in PIC code can be handled just as it
11629 is in non PIC code. */
11630 if (offset_expr
.X_op
== O_constant
)
11632 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11633 offbits
== 0 ? 16 : offbits
);
11634 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11636 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11638 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11639 tempreg
, tempreg
, breg
);
11642 if (offset_expr
.X_add_number
!= 0)
11643 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11644 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11645 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11647 else if (offbits
== 16)
11648 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11650 macro_build (NULL
, s
, fmt
, op
[0],
11651 (int) offset_expr
.X_add_number
, tempreg
);
11653 else if (offbits
!= 16)
11655 /* The offset field is too narrow to be used for a low-part
11656 relocation, so load the whole address into the auxillary
11658 load_address (tempreg
, &offset_expr
, &used_at
);
11660 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11661 tempreg
, tempreg
, breg
);
11663 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11665 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11667 else if (mips_pic
== NO_PIC
)
11669 /* If this is a reference to a GP relative symbol, and there
11670 is no base register, we want
11671 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11672 Otherwise, if there is no base register, we want
11673 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11674 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11675 If we have a constant, we need two instructions anyhow,
11676 so we always use the latter form.
11678 If we have a base register, and this is a reference to a
11679 GP relative symbol, we want
11680 addu $tempreg,$breg,$gp
11681 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11683 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11684 addu $tempreg,$tempreg,$breg
11685 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11686 With a constant we always use the latter case.
11688 With 64bit address space and no base register and $at usable,
11690 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11691 lui $at,<sym> (BFD_RELOC_HI16_S)
11692 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11695 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11696 If we have a base register, we want
11697 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11698 lui $at,<sym> (BFD_RELOC_HI16_S)
11699 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11703 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11705 Without $at we can't generate the optimal path for superscalar
11706 processors here since this would require two temporary registers.
11707 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11708 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11710 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11712 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11713 If we have a base register, we want
11714 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11715 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11717 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11719 daddu $tempreg,$tempreg,$breg
11720 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11722 For GP relative symbols in 64bit address space we can use
11723 the same sequence as in 32bit address space. */
11724 if (HAVE_64BIT_SYMBOLS
)
11726 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11727 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11729 relax_start (offset_expr
.X_add_symbol
);
11732 macro_build (&offset_expr
, s
, fmt
, op
[0],
11733 BFD_RELOC_GPREL16
, mips_gp_register
);
11737 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11738 tempreg
, breg
, mips_gp_register
);
11739 macro_build (&offset_expr
, s
, fmt
, op
[0],
11740 BFD_RELOC_GPREL16
, tempreg
);
11745 if (used_at
== 0 && mips_opts
.at
)
11747 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11748 BFD_RELOC_MIPS_HIGHEST
);
11749 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11751 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11752 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11754 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11755 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11756 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11757 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11763 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11764 BFD_RELOC_MIPS_HIGHEST
);
11765 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11766 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11767 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11768 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11769 tempreg
, BFD_RELOC_HI16_S
);
11770 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11772 macro_build (NULL
, "daddu", "d,v,t",
11773 tempreg
, tempreg
, breg
);
11774 macro_build (&offset_expr
, s
, fmt
, op
[0],
11775 BFD_RELOC_LO16
, tempreg
);
11778 if (mips_relax
.sequence
)
11785 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11786 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11788 relax_start (offset_expr
.X_add_symbol
);
11789 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11793 macro_build_lui (&offset_expr
, tempreg
);
11794 macro_build (&offset_expr
, s
, fmt
, op
[0],
11795 BFD_RELOC_LO16
, tempreg
);
11796 if (mips_relax
.sequence
)
11801 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11802 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11804 relax_start (offset_expr
.X_add_symbol
);
11805 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11806 tempreg
, breg
, mips_gp_register
);
11807 macro_build (&offset_expr
, s
, fmt
, op
[0],
11808 BFD_RELOC_GPREL16
, tempreg
);
11811 macro_build_lui (&offset_expr
, tempreg
);
11812 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11813 tempreg
, tempreg
, breg
);
11814 macro_build (&offset_expr
, s
, fmt
, op
[0],
11815 BFD_RELOC_LO16
, tempreg
);
11816 if (mips_relax
.sequence
)
11820 else if (!mips_big_got
)
11822 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11824 /* If this is a reference to an external symbol, we want
11825 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11827 <op> op[0],0($tempreg)
11829 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11831 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11832 <op> op[0],0($tempreg)
11834 For NewABI, we want
11835 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11836 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11838 If there is a base register, we add it to $tempreg before
11839 the <op>. If there is a constant, we stick it in the
11840 <op> instruction. We don't handle constants larger than
11841 16 bits, because we have no way to load the upper 16 bits
11842 (actually, we could handle them for the subset of cases
11843 in which we are not using $at). */
11844 gas_assert (offset_expr
.X_op
== O_symbol
);
11847 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11848 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11850 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11851 tempreg
, tempreg
, breg
);
11852 macro_build (&offset_expr
, s
, fmt
, op
[0],
11853 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11856 expr1
.X_add_number
= offset_expr
.X_add_number
;
11857 offset_expr
.X_add_number
= 0;
11858 if (expr1
.X_add_number
< -0x8000
11859 || expr1
.X_add_number
>= 0x8000)
11860 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11861 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11862 lw_reloc_type
, mips_gp_register
);
11864 relax_start (offset_expr
.X_add_symbol
);
11866 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11867 tempreg
, BFD_RELOC_LO16
);
11870 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11871 tempreg
, tempreg
, breg
);
11872 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11874 else if (mips_big_got
&& !HAVE_NEWABI
)
11878 /* If this is a reference to an external symbol, we want
11879 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11880 addu $tempreg,$tempreg,$gp
11881 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11882 <op> op[0],0($tempreg)
11884 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11886 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11887 <op> op[0],0($tempreg)
11888 If there is a base register, we add it to $tempreg before
11889 the <op>. If there is a constant, we stick it in the
11890 <op> instruction. We don't handle constants larger than
11891 16 bits, because we have no way to load the upper 16 bits
11892 (actually, we could handle them for the subset of cases
11893 in which we are not using $at). */
11894 gas_assert (offset_expr
.X_op
== O_symbol
);
11895 expr1
.X_add_number
= offset_expr
.X_add_number
;
11896 offset_expr
.X_add_number
= 0;
11897 if (expr1
.X_add_number
< -0x8000
11898 || expr1
.X_add_number
>= 0x8000)
11899 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11900 gpdelay
= reg_needs_delay (mips_gp_register
);
11901 relax_start (offset_expr
.X_add_symbol
);
11902 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11903 BFD_RELOC_MIPS_GOT_HI16
);
11904 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11906 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11907 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11910 macro_build (NULL
, "nop", "");
11911 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11912 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11914 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11915 tempreg
, BFD_RELOC_LO16
);
11919 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11920 tempreg
, tempreg
, breg
);
11921 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11923 else if (mips_big_got
&& HAVE_NEWABI
)
11925 /* If this is a reference to an external symbol, we want
11926 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11927 add $tempreg,$tempreg,$gp
11928 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11929 <op> op[0],<ofst>($tempreg)
11930 Otherwise, for local symbols, we want:
11931 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11932 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11933 gas_assert (offset_expr
.X_op
== O_symbol
);
11934 expr1
.X_add_number
= offset_expr
.X_add_number
;
11935 offset_expr
.X_add_number
= 0;
11936 if (expr1
.X_add_number
< -0x8000
11937 || expr1
.X_add_number
>= 0x8000)
11938 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11939 relax_start (offset_expr
.X_add_symbol
);
11940 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11941 BFD_RELOC_MIPS_GOT_HI16
);
11942 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11944 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11945 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11947 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11948 tempreg
, tempreg
, breg
);
11949 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11952 offset_expr
.X_add_number
= expr1
.X_add_number
;
11953 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11954 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11956 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11957 tempreg
, tempreg
, breg
);
11958 macro_build (&offset_expr
, s
, fmt
, op
[0],
11959 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11968 gas_assert (mips_opts
.micromips
);
11969 gas_assert (mips_opts
.insn32
);
11970 start_noreorder ();
11971 macro_build (NULL
, "jr", "s", RA
);
11972 expr1
.X_add_number
= op
[0] << 2;
11973 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11978 gas_assert (mips_opts
.micromips
);
11979 gas_assert (mips_opts
.insn32
);
11980 macro_build (NULL
, "jr", "s", op
[0]);
11981 if (mips_opts
.noreorder
)
11982 macro_build (NULL
, "nop", "");
11987 load_register (op
[0], &imm_expr
, 0);
11991 load_register (op
[0], &imm_expr
, 1);
11995 if (imm_expr
.X_op
== O_constant
)
11998 load_register (AT
, &imm_expr
, 0);
11999 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12004 gas_assert (imm_expr
.X_op
== O_absent
12005 && offset_expr
.X_op
== O_symbol
12006 && strcmp (segment_name (S_GET_SEGMENT
12007 (offset_expr
.X_add_symbol
)),
12009 && offset_expr
.X_add_number
== 0);
12010 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12011 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12016 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12017 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12018 order 32 bits of the value and the low order 32 bits are either
12019 zero or in OFFSET_EXPR. */
12020 if (imm_expr
.X_op
== O_constant
)
12022 if (GPR_SIZE
== 64)
12023 load_register (op
[0], &imm_expr
, 1);
12028 if (target_big_endian
)
12040 load_register (hreg
, &imm_expr
, 0);
12043 if (offset_expr
.X_op
== O_absent
)
12044 move_register (lreg
, 0);
12047 gas_assert (offset_expr
.X_op
== O_constant
);
12048 load_register (lreg
, &offset_expr
, 0);
12054 gas_assert (imm_expr
.X_op
== O_absent
);
12056 /* We know that sym is in the .rdata section. First we get the
12057 upper 16 bits of the address. */
12058 if (mips_pic
== NO_PIC
)
12060 macro_build_lui (&offset_expr
, AT
);
12065 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12066 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12070 /* Now we load the register(s). */
12071 if (GPR_SIZE
== 64)
12074 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12075 BFD_RELOC_LO16
, AT
);
12080 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12081 BFD_RELOC_LO16
, AT
);
12084 /* FIXME: How in the world do we deal with the possible
12086 offset_expr
.X_add_number
+= 4;
12087 macro_build (&offset_expr
, "lw", "t,o(b)",
12088 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12094 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12095 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12096 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12097 the value and the low order 32 bits are either zero or in
12099 if (imm_expr
.X_op
== O_constant
)
12102 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12103 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12104 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12107 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12108 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12109 else if (FPR_SIZE
!= 32)
12110 as_bad (_("Unable to generate `%s' compliant code "
12112 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12114 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12115 if (offset_expr
.X_op
== O_absent
)
12116 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12119 gas_assert (offset_expr
.X_op
== O_constant
);
12120 load_register (AT
, &offset_expr
, 0);
12121 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12127 gas_assert (imm_expr
.X_op
== O_absent
12128 && offset_expr
.X_op
== O_symbol
12129 && offset_expr
.X_add_number
== 0);
12130 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12131 if (strcmp (s
, ".lit8") == 0)
12133 op
[2] = mips_gp_register
;
12134 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12135 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12136 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12140 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12142 if (mips_pic
!= NO_PIC
)
12143 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12144 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12147 /* FIXME: This won't work for a 64 bit address. */
12148 macro_build_lui (&offset_expr
, AT
);
12152 offset_reloc
[0] = BFD_RELOC_LO16
;
12153 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12154 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12161 * The MIPS assembler seems to check for X_add_number not
12162 * being double aligned and generating:
12163 * lui at,%hi(foo+1)
12165 * addiu at,at,%lo(foo+1)
12168 * But, the resulting address is the same after relocation so why
12169 * generate the extra instruction?
12171 /* Itbl support may require additional care here. */
12174 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12183 gas_assert (!mips_opts
.micromips
);
12184 /* Itbl support may require additional care here. */
12187 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12207 if (GPR_SIZE
== 64)
12217 if (GPR_SIZE
== 64)
12225 /* Even on a big endian machine $fn comes before $fn+1. We have
12226 to adjust when loading from memory. We set coproc if we must
12227 load $fn+1 first. */
12228 /* Itbl support may require additional care here. */
12229 if (!target_big_endian
)
12233 if (small_offset_p (0, align
, 16))
12236 if (!small_offset_p (4, align
, 16))
12238 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12239 -1, offset_reloc
[0], offset_reloc
[1],
12241 expr1
.X_add_number
= 0;
12245 offset_reloc
[0] = BFD_RELOC_LO16
;
12246 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12247 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12249 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12251 ep
->X_add_number
+= 4;
12252 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12253 offset_reloc
[1], offset_reloc
[2], breg
);
12254 ep
->X_add_number
-= 4;
12255 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12256 offset_reloc
[1], offset_reloc
[2], breg
);
12260 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12261 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12263 ep
->X_add_number
+= 4;
12264 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12265 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12271 if (offset_expr
.X_op
!= O_symbol
12272 && offset_expr
.X_op
!= O_constant
)
12274 as_bad (_("expression too complex"));
12275 offset_expr
.X_op
= O_constant
;
12278 if (HAVE_32BIT_ADDRESSES
12279 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12283 sprintf_vma (value
, offset_expr
.X_add_number
);
12284 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12287 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12289 /* If this is a reference to a GP relative symbol, we want
12290 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12291 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12292 If we have a base register, we use this
12294 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12295 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12296 If this is not a GP relative symbol, we want
12297 lui $at,<sym> (BFD_RELOC_HI16_S)
12298 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12299 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12300 If there is a base register, we add it to $at after the
12301 lui instruction. If there is a constant, we always use
12303 if (offset_expr
.X_op
== O_symbol
12304 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12305 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12307 relax_start (offset_expr
.X_add_symbol
);
12310 tempreg
= mips_gp_register
;
12314 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12315 AT
, breg
, mips_gp_register
);
12320 /* Itbl support may require additional care here. */
12321 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12322 BFD_RELOC_GPREL16
, tempreg
);
12323 offset_expr
.X_add_number
+= 4;
12325 /* Set mips_optimize to 2 to avoid inserting an
12327 hold_mips_optimize
= mips_optimize
;
12329 /* Itbl support may require additional care here. */
12330 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12331 BFD_RELOC_GPREL16
, tempreg
);
12332 mips_optimize
= hold_mips_optimize
;
12336 offset_expr
.X_add_number
-= 4;
12339 if (offset_high_part (offset_expr
.X_add_number
, 16)
12340 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12342 load_address (AT
, &offset_expr
, &used_at
);
12343 offset_expr
.X_op
= O_constant
;
12344 offset_expr
.X_add_number
= 0;
12347 macro_build_lui (&offset_expr
, AT
);
12349 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12350 /* Itbl support may require additional care here. */
12351 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12352 BFD_RELOC_LO16
, AT
);
12353 /* FIXME: How do we handle overflow here? */
12354 offset_expr
.X_add_number
+= 4;
12355 /* Itbl support may require additional care here. */
12356 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12357 BFD_RELOC_LO16
, AT
);
12358 if (mips_relax
.sequence
)
12361 else if (!mips_big_got
)
12363 /* If this is a reference to an external symbol, we want
12364 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12367 <op> op[0]+1,4($at)
12369 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12371 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12372 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12373 If there is a base register we add it to $at before the
12374 lwc1 instructions. If there is a constant we include it
12375 in the lwc1 instructions. */
12377 expr1
.X_add_number
= offset_expr
.X_add_number
;
12378 if (expr1
.X_add_number
< -0x8000
12379 || expr1
.X_add_number
>= 0x8000 - 4)
12380 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12381 load_got_offset (AT
, &offset_expr
);
12384 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12386 /* Set mips_optimize to 2 to avoid inserting an undesired
12388 hold_mips_optimize
= mips_optimize
;
12391 /* Itbl support may require additional care here. */
12392 relax_start (offset_expr
.X_add_symbol
);
12393 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12394 BFD_RELOC_LO16
, AT
);
12395 expr1
.X_add_number
+= 4;
12396 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12397 BFD_RELOC_LO16
, AT
);
12399 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12400 BFD_RELOC_LO16
, AT
);
12401 offset_expr
.X_add_number
+= 4;
12402 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12403 BFD_RELOC_LO16
, AT
);
12406 mips_optimize
= hold_mips_optimize
;
12408 else if (mips_big_got
)
12412 /* If this is a reference to an external symbol, we want
12413 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12415 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12418 <op> op[0]+1,4($at)
12420 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12422 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12423 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12424 If there is a base register we add it to $at before the
12425 lwc1 instructions. If there is a constant we include it
12426 in the lwc1 instructions. */
12428 expr1
.X_add_number
= offset_expr
.X_add_number
;
12429 offset_expr
.X_add_number
= 0;
12430 if (expr1
.X_add_number
< -0x8000
12431 || expr1
.X_add_number
>= 0x8000 - 4)
12432 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12433 gpdelay
= reg_needs_delay (mips_gp_register
);
12434 relax_start (offset_expr
.X_add_symbol
);
12435 macro_build (&offset_expr
, "lui", LUI_FMT
,
12436 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12437 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12438 AT
, AT
, mips_gp_register
);
12439 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12440 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12443 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12444 /* Itbl support may require additional care here. */
12445 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12446 BFD_RELOC_LO16
, AT
);
12447 expr1
.X_add_number
+= 4;
12449 /* Set mips_optimize to 2 to avoid inserting an undesired
12451 hold_mips_optimize
= mips_optimize
;
12453 /* Itbl support may require additional care here. */
12454 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12455 BFD_RELOC_LO16
, AT
);
12456 mips_optimize
= hold_mips_optimize
;
12457 expr1
.X_add_number
-= 4;
12460 offset_expr
.X_add_number
= expr1
.X_add_number
;
12462 macro_build (NULL
, "nop", "");
12463 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12464 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12467 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12468 /* Itbl support may require additional care here. */
12469 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12470 BFD_RELOC_LO16
, AT
);
12471 offset_expr
.X_add_number
+= 4;
12473 /* Set mips_optimize to 2 to avoid inserting an undesired
12475 hold_mips_optimize
= mips_optimize
;
12477 /* Itbl support may require additional care here. */
12478 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12479 BFD_RELOC_LO16
, AT
);
12480 mips_optimize
= hold_mips_optimize
;
12494 gas_assert (!mips_opts
.micromips
);
12499 /* New code added to support COPZ instructions.
12500 This code builds table entries out of the macros in mip_opcodes.
12501 R4000 uses interlocks to handle coproc delays.
12502 Other chips (like the R3000) require nops to be inserted for delays.
12504 FIXME: Currently, we require that the user handle delays.
12505 In order to fill delay slots for non-interlocked chips,
12506 we must have a way to specify delays based on the coprocessor.
12507 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12508 What are the side-effects of the cop instruction?
12509 What cache support might we have and what are its effects?
12510 Both coprocessor & memory require delays. how long???
12511 What registers are read/set/modified?
12513 If an itbl is provided to interpret cop instructions,
12514 this knowledge can be encoded in the itbl spec. */
12528 gas_assert (!mips_opts
.micromips
);
12529 /* For now we just do C (same as Cz). The parameter will be
12530 stored in insn_opcode by mips_ip. */
12531 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12535 move_register (op
[0], op
[1]);
12539 gas_assert (mips_opts
.micromips
);
12540 gas_assert (mips_opts
.insn32
);
12541 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12542 micromips_to_32_reg_m_map
[op
[1]]);
12543 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12544 micromips_to_32_reg_n_map
[op
[2]]);
12550 if (mips_opts
.arch
== CPU_R5900
)
12551 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12555 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12556 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12563 /* The MIPS assembler some times generates shifts and adds. I'm
12564 not trying to be that fancy. GCC should do this for us
12567 load_register (AT
, &imm_expr
, dbl
);
12568 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12569 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12582 start_noreorder ();
12585 load_register (AT
, &imm_expr
, dbl
);
12586 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12587 op
[1], imm
? AT
: op
[2]);
12588 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12589 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12590 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12592 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12595 if (mips_opts
.micromips
)
12596 micromips_label_expr (&label_expr
);
12598 label_expr
.X_add_number
= 8;
12599 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12600 macro_build (NULL
, "nop", "");
12601 macro_build (NULL
, "break", BRK_FMT
, 6);
12602 if (mips_opts
.micromips
)
12603 micromips_add_label ();
12606 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12619 start_noreorder ();
12622 load_register (AT
, &imm_expr
, dbl
);
12623 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12624 op
[1], imm
? AT
: op
[2]);
12625 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12626 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12628 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12631 if (mips_opts
.micromips
)
12632 micromips_label_expr (&label_expr
);
12634 label_expr
.X_add_number
= 8;
12635 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12636 macro_build (NULL
, "nop", "");
12637 macro_build (NULL
, "break", BRK_FMT
, 6);
12638 if (mips_opts
.micromips
)
12639 micromips_add_label ();
12645 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12647 if (op
[0] == op
[1])
12654 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12655 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12659 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12660 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12661 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12662 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12666 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12668 if (op
[0] == op
[1])
12675 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12676 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12680 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12681 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12682 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12683 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12692 rot
= imm_expr
.X_add_number
& 0x3f;
12693 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12695 rot
= (64 - rot
) & 0x3f;
12697 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12699 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12704 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12707 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12708 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12711 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12712 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12713 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12721 rot
= imm_expr
.X_add_number
& 0x1f;
12722 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12724 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12725 (32 - rot
) & 0x1f);
12730 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12734 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12735 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12736 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12741 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12743 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12747 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12748 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12749 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12750 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12754 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12756 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12760 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12761 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12762 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12763 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12772 rot
= imm_expr
.X_add_number
& 0x3f;
12773 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12776 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12778 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12783 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12786 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12787 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12790 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12791 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12792 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12800 rot
= imm_expr
.X_add_number
& 0x1f;
12801 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12803 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12808 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12812 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12813 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12814 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12820 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12821 else if (op
[2] == 0)
12822 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12825 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12826 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12831 if (imm_expr
.X_add_number
== 0)
12833 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12838 as_warn (_("instruction %s: result is always false"),
12839 ip
->insn_mo
->name
);
12840 move_register (op
[0], 0);
12843 if (CPU_HAS_SEQ (mips_opts
.arch
)
12844 && -512 <= imm_expr
.X_add_number
12845 && imm_expr
.X_add_number
< 512)
12847 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12848 (int) imm_expr
.X_add_number
);
12851 if (imm_expr
.X_add_number
>= 0
12852 && imm_expr
.X_add_number
< 0x10000)
12853 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12854 else if (imm_expr
.X_add_number
> -0x8000
12855 && imm_expr
.X_add_number
< 0)
12857 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12858 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
12859 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12861 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12864 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12865 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12870 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12871 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12874 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12877 case M_SGE
: /* X >= Y <==> not (X < Y) */
12883 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12884 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12887 case M_SGE_I
: /* X >= I <==> not (X < I) */
12889 if (imm_expr
.X_add_number
>= -0x8000
12890 && imm_expr
.X_add_number
< 0x8000)
12891 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12892 op
[0], op
[1], BFD_RELOC_LO16
);
12895 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12896 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12900 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12903 case M_SGT
: /* X > Y <==> Y < X */
12909 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12912 case M_SGT_I
: /* X > I <==> I < X */
12919 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12920 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12923 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12929 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12930 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12933 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12940 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12941 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12942 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12946 if (imm_expr
.X_add_number
>= -0x8000
12947 && imm_expr
.X_add_number
< 0x8000)
12949 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12954 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12955 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12959 if (imm_expr
.X_add_number
>= -0x8000
12960 && imm_expr
.X_add_number
< 0x8000)
12962 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12967 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12968 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12973 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12974 else if (op
[2] == 0)
12975 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12978 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12979 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12984 if (imm_expr
.X_add_number
== 0)
12986 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12991 as_warn (_("instruction %s: result is always true"),
12992 ip
->insn_mo
->name
);
12993 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
12994 op
[0], 0, BFD_RELOC_LO16
);
12997 if (CPU_HAS_SEQ (mips_opts
.arch
)
12998 && -512 <= imm_expr
.X_add_number
12999 && imm_expr
.X_add_number
< 512)
13001 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13002 (int) imm_expr
.X_add_number
);
13005 if (imm_expr
.X_add_number
>= 0
13006 && imm_expr
.X_add_number
< 0x10000)
13008 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13011 else if (imm_expr
.X_add_number
> -0x8000
13012 && imm_expr
.X_add_number
< 0)
13014 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13015 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13016 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13018 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13021 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13022 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13027 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13028 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13031 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13046 if (!mips_opts
.micromips
)
13048 if (imm_expr
.X_add_number
> -0x200
13049 && imm_expr
.X_add_number
<= 0x200)
13051 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13052 (int) -imm_expr
.X_add_number
);
13061 if (imm_expr
.X_add_number
> -0x8000
13062 && imm_expr
.X_add_number
<= 0x8000)
13064 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13065 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13070 load_register (AT
, &imm_expr
, dbl
);
13071 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13093 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13094 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13099 gas_assert (!mips_opts
.micromips
);
13100 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13104 * Is the double cfc1 instruction a bug in the mips assembler;
13105 * or is there a reason for it?
13107 start_noreorder ();
13108 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13109 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13110 macro_build (NULL
, "nop", "");
13111 expr1
.X_add_number
= 3;
13112 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13113 expr1
.X_add_number
= 2;
13114 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13115 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13116 macro_build (NULL
, "nop", "");
13117 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13119 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13120 macro_build (NULL
, "nop", "");
13137 offbits
= (mips_opts
.micromips
? 12 : 16);
13143 offbits
= (mips_opts
.micromips
? 12 : 16);
13155 offbits
= (mips_opts
.micromips
? 12 : 16);
13162 offbits
= (mips_opts
.micromips
? 12 : 16);
13168 large_offset
= !small_offset_p (off
, align
, offbits
);
13170 expr1
.X_add_number
= 0;
13175 if (small_offset_p (0, align
, 16))
13176 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13177 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13180 load_address (tempreg
, ep
, &used_at
);
13182 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13183 tempreg
, tempreg
, breg
);
13185 offset_reloc
[0] = BFD_RELOC_LO16
;
13186 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13187 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13192 else if (!ust
&& op
[0] == breg
)
13203 if (!target_big_endian
)
13204 ep
->X_add_number
+= off
;
13206 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13208 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13209 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13211 if (!target_big_endian
)
13212 ep
->X_add_number
-= off
;
13214 ep
->X_add_number
+= off
;
13216 macro_build (NULL
, s2
, "t,~(b)",
13217 tempreg
, (int) ep
->X_add_number
, breg
);
13219 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13220 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13222 /* If necessary, move the result in tempreg to the final destination. */
13223 if (!ust
&& op
[0] != tempreg
)
13225 /* Protect second load's delay slot. */
13227 move_register (op
[0], tempreg
);
13233 if (target_big_endian
== ust
)
13234 ep
->X_add_number
+= off
;
13235 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13236 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13237 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13239 /* For halfword transfers we need a temporary register to shuffle
13240 bytes. Unfortunately for M_USH_A we have none available before
13241 the next store as AT holds the base address. We deal with this
13242 case by clobbering TREG and then restoring it as with ULH. */
13243 tempreg
= ust
== large_offset
? op
[0] : AT
;
13245 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13247 if (target_big_endian
== ust
)
13248 ep
->X_add_number
-= off
;
13250 ep
->X_add_number
+= off
;
13251 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13252 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13254 /* For M_USH_A re-retrieve the LSB. */
13255 if (ust
&& large_offset
)
13257 if (target_big_endian
)
13258 ep
->X_add_number
+= off
;
13260 ep
->X_add_number
-= off
;
13261 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13262 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13264 /* For ULH and M_USH_A OR the LSB in. */
13265 if (!ust
|| large_offset
)
13267 tempreg
= !large_offset
? AT
: op
[0];
13268 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13269 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13274 /* FIXME: Check if this is one of the itbl macros, since they
13275 are added dynamically. */
13276 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13279 if (!mips_opts
.at
&& used_at
)
13280 as_bad (_("macro used $at after \".set noat\""));
13283 /* Implement macros in mips16 mode. */
13286 mips16_macro (struct mips_cl_insn
*ip
)
13288 const struct mips_operand_array
*operands
;
13293 const char *s
, *s2
, *s3
;
13294 unsigned int op
[MAX_OPERANDS
];
13297 mask
= ip
->insn_mo
->mask
;
13299 operands
= insn_operands (ip
);
13300 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13301 if (operands
->operand
[i
])
13302 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13306 expr1
.X_op
= O_constant
;
13307 expr1
.X_op_symbol
= NULL
;
13308 expr1
.X_add_symbol
= NULL
;
13309 expr1
.X_add_number
= 1;
13328 start_noreorder ();
13329 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
13330 expr1
.X_add_number
= 2;
13331 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13332 macro_build (NULL
, "break", "6", 7);
13334 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13335 since that causes an overflow. We should do that as well,
13336 but I don't see how to do the comparisons without a temporary
13339 macro_build (NULL
, s
, "x", op
[0]);
13358 start_noreorder ();
13359 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
13360 expr1
.X_add_number
= 2;
13361 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13362 macro_build (NULL
, "break", "6", 7);
13364 macro_build (NULL
, s2
, "x", op
[0]);
13370 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13371 macro_build (NULL
, "mflo", "x", op
[0]);
13379 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13380 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
13384 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13385 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13389 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13390 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13412 goto do_reverse_branch
;
13416 goto do_reverse_branch
;
13428 goto do_reverse_branch
;
13439 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13440 macro_build (&offset_expr
, s2
, "p");
13467 goto do_addone_branch_i
;
13472 goto do_addone_branch_i
;
13487 goto do_addone_branch_i
;
13493 do_addone_branch_i
:
13494 ++imm_expr
.X_add_number
;
13497 macro_build (&imm_expr
, s
, s3
, op
[0]);
13498 macro_build (&offset_expr
, s2
, "p");
13502 expr1
.X_add_number
= 0;
13503 macro_build (&expr1
, "slti", "x,8", op
[1]);
13504 if (op
[0] != op
[1])
13505 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13506 expr1
.X_add_number
= 2;
13507 macro_build (&expr1
, "bteqz", "p");
13508 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13513 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13514 opcode bits in *OPCODE_EXTRA. */
13516 static struct mips_opcode
*
13517 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13518 ssize_t length
, unsigned int *opcode_extra
)
13520 char *name
, *dot
, *p
;
13521 unsigned int mask
, suffix
;
13523 struct mips_opcode
*insn
;
13525 /* Make a copy of the instruction so that we can fiddle with it. */
13526 name
= alloca (length
+ 1);
13527 memcpy (name
, start
, length
);
13528 name
[length
] = '\0';
13530 /* Look up the instruction as-is. */
13531 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13535 dot
= strchr (name
, '.');
13538 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13539 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13540 if (*p
== 0 && mask
!= 0)
13543 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13545 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13547 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13553 if (mips_opts
.micromips
)
13555 /* See if there's an instruction size override suffix,
13556 either `16' or `32', at the end of the mnemonic proper,
13557 that defines the operation, i.e. before the first `.'
13558 character if any. Strip it and retry. */
13559 opend
= dot
!= NULL
? dot
- name
: length
;
13560 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13562 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13568 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13569 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13572 forced_insn_length
= suffix
;
13581 /* Assemble an instruction into its binary format. If the instruction
13582 is a macro, set imm_expr and offset_expr to the values associated
13583 with "I" and "A" operands respectively. Otherwise store the value
13584 of the relocatable field (if any) in offset_expr. In both cases
13585 set offset_reloc to the relocation operators applied to offset_expr. */
13588 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13590 const struct mips_opcode
*first
, *past
;
13591 struct hash_control
*hash
;
13594 struct mips_operand_token
*tokens
;
13595 unsigned int opcode_extra
;
13597 if (mips_opts
.micromips
)
13599 hash
= micromips_op_hash
;
13600 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13605 past
= &mips_opcodes
[NUMOPCODES
];
13607 forced_insn_length
= 0;
13610 /* We first try to match an instruction up to a space or to the end. */
13611 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13614 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13617 set_insn_error (0, _("unrecognized opcode"));
13621 if (strcmp (first
->name
, "li.s") == 0)
13623 else if (strcmp (first
->name
, "li.d") == 0)
13627 tokens
= mips_parse_arguments (str
+ end
, format
);
13631 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13632 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13633 set_insn_error (0, _("invalid operands"));
13635 obstack_free (&mips_operand_tokens
, tokens
);
13638 /* As for mips_ip, but used when assembling MIPS16 code.
13639 Also set forced_insn_length to the resulting instruction size in
13640 bytes if the user explicitly requested a small or extended instruction. */
13643 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13646 struct mips_opcode
*first
;
13647 struct mips_operand_token
*tokens
;
13649 forced_insn_length
= 0;
13651 for (s
= str
; ISLOWER (*s
); ++s
)
13665 if (s
[1] == 't' && s
[2] == ' ')
13667 forced_insn_length
= 2;
13671 else if (s
[1] == 'e' && s
[2] == ' ')
13673 forced_insn_length
= 4;
13677 /* Fall through. */
13679 set_insn_error (0, _("unrecognized opcode"));
13683 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13684 forced_insn_length
= 2;
13687 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13692 set_insn_error (0, _("unrecognized opcode"));
13696 tokens
= mips_parse_arguments (s
, 0);
13700 if (!match_mips16_insns (insn
, first
, tokens
))
13701 set_insn_error (0, _("invalid operands"));
13703 obstack_free (&mips_operand_tokens
, tokens
);
13706 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13707 NBITS is the number of significant bits in VAL. */
13709 static unsigned long
13710 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13715 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13718 else if (nbits
== 15)
13720 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13725 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13728 return (extval
<< 16) | val
;
13731 /* Like decode_mips16_operand, but require the operand to be defined and
13732 require it to be an integer. */
13734 static const struct mips_int_operand
*
13735 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13737 const struct mips_operand
*operand
;
13739 operand
= decode_mips16_operand (type
, extended_p
);
13740 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13742 return (const struct mips_int_operand
*) operand
;
13745 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13748 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13749 bfd_reloc_code_real_type reloc
, offsetT sval
)
13751 int min_val
, max_val
;
13753 min_val
= mips_int_operand_min (operand
);
13754 max_val
= mips_int_operand_max (operand
);
13755 if (reloc
!= BFD_RELOC_UNUSED
)
13758 sval
= SEXT_16BIT (sval
);
13763 return (sval
>= min_val
13765 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13768 /* Install immediate value VAL into MIPS16 instruction *INSN,
13769 extending it if necessary. The instruction in *INSN may
13770 already be extended.
13772 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13773 if none. In the former case, VAL is a 16-bit number with no
13774 defined signedness.
13776 TYPE is the type of the immediate field. USER_INSN_LENGTH
13777 is the length that the user requested, or 0 if none. */
13780 mips16_immed (char *file
, unsigned int line
, int type
,
13781 bfd_reloc_code_real_type reloc
, offsetT val
,
13782 unsigned int user_insn_length
, unsigned long *insn
)
13784 const struct mips_int_operand
*operand
;
13785 unsigned int uval
, length
;
13787 operand
= mips16_immed_operand (type
, FALSE
);
13788 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13790 /* We need an extended instruction. */
13791 if (user_insn_length
== 2)
13792 as_bad_where (file
, line
, _("invalid unextended operand value"));
13794 *insn
|= MIPS16_EXTEND
;
13796 else if (user_insn_length
== 4)
13798 /* The operand doesn't force an unextended instruction to be extended.
13799 Warn if the user wanted an extended instruction anyway. */
13800 *insn
|= MIPS16_EXTEND
;
13801 as_warn_where (file
, line
,
13802 _("extended operand requested but not required"));
13805 length
= mips16_opcode_length (*insn
);
13808 operand
= mips16_immed_operand (type
, TRUE
);
13809 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13810 as_bad_where (file
, line
,
13811 _("operand value out of range for instruction"));
13813 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13815 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13817 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13820 struct percent_op_match
13823 bfd_reloc_code_real_type reloc
;
13826 static const struct percent_op_match mips_percent_op
[] =
13828 {"%lo", BFD_RELOC_LO16
},
13829 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13830 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13831 {"%call16", BFD_RELOC_MIPS_CALL16
},
13832 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13833 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13834 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13835 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13836 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13837 {"%got", BFD_RELOC_MIPS_GOT16
},
13838 {"%gp_rel", BFD_RELOC_GPREL16
},
13839 {"%half", BFD_RELOC_16
},
13840 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13841 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13842 {"%neg", BFD_RELOC_MIPS_SUB
},
13843 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13844 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13845 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13846 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13847 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13848 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13849 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13850 {"%hi", BFD_RELOC_HI16_S
},
13851 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
13852 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
13855 static const struct percent_op_match mips16_percent_op
[] =
13857 {"%lo", BFD_RELOC_MIPS16_LO16
},
13858 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13859 {"%got", BFD_RELOC_MIPS16_GOT16
},
13860 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13861 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13862 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13863 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13864 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13865 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13866 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13867 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13868 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13872 /* Return true if *STR points to a relocation operator. When returning true,
13873 move *STR over the operator and store its relocation code in *RELOC.
13874 Leave both *STR and *RELOC alone when returning false. */
13877 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13879 const struct percent_op_match
*percent_op
;
13882 if (mips_opts
.mips16
)
13884 percent_op
= mips16_percent_op
;
13885 limit
= ARRAY_SIZE (mips16_percent_op
);
13889 percent_op
= mips_percent_op
;
13890 limit
= ARRAY_SIZE (mips_percent_op
);
13893 for (i
= 0; i
< limit
; i
++)
13894 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13896 int len
= strlen (percent_op
[i
].str
);
13898 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13901 *str
+= strlen (percent_op
[i
].str
);
13902 *reloc
= percent_op
[i
].reloc
;
13904 /* Check whether the output BFD supports this relocation.
13905 If not, issue an error and fall back on something safe. */
13906 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13908 as_bad (_("relocation %s isn't supported by the current ABI"),
13909 percent_op
[i
].str
);
13910 *reloc
= BFD_RELOC_UNUSED
;
13918 /* Parse string STR as a 16-bit relocatable operand. Store the
13919 expression in *EP and the relocations in the array starting
13920 at RELOC. Return the number of relocation operators used.
13922 On exit, EXPR_END points to the first character after the expression. */
13925 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13928 bfd_reloc_code_real_type reversed_reloc
[3];
13929 size_t reloc_index
, i
;
13930 int crux_depth
, str_depth
;
13933 /* Search for the start of the main expression, recoding relocations
13934 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13935 of the main expression and with CRUX_DEPTH containing the number
13936 of open brackets at that point. */
13943 crux_depth
= str_depth
;
13945 /* Skip over whitespace and brackets, keeping count of the number
13947 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13952 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13953 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13955 my_getExpression (ep
, crux
);
13958 /* Match every open bracket. */
13959 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13963 if (crux_depth
> 0)
13964 as_bad (_("unclosed '('"));
13968 if (reloc_index
!= 0)
13970 prev_reloc_op_frag
= frag_now
;
13971 for (i
= 0; i
< reloc_index
; i
++)
13972 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13975 return reloc_index
;
13979 my_getExpression (expressionS
*ep
, char *str
)
13983 save_in
= input_line_pointer
;
13984 input_line_pointer
= str
;
13986 expr_end
= input_line_pointer
;
13987 input_line_pointer
= save_in
;
13991 md_atof (int type
, char *litP
, int *sizeP
)
13993 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13997 md_number_to_chars (char *buf
, valueT val
, int n
)
13999 if (target_big_endian
)
14000 number_to_chars_bigendian (buf
, val
, n
);
14002 number_to_chars_littleendian (buf
, val
, n
);
14005 static int support_64bit_objects(void)
14007 const char **list
, **l
;
14010 list
= bfd_target_list ();
14011 for (l
= list
; *l
!= NULL
; l
++)
14012 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14013 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14015 yes
= (*l
!= NULL
);
14020 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14021 NEW_VALUE. Warn if another value was already specified. Note:
14022 we have to defer parsing the -march and -mtune arguments in order
14023 to handle 'from-abi' correctly, since the ABI might be specified
14024 in a later argument. */
14027 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14029 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14030 as_warn (_("a different %s was already specified, is now %s"),
14031 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14034 *string_ptr
= new_value
;
14038 md_parse_option (int c
, char *arg
)
14042 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14043 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14045 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14046 c
== mips_ases
[i
].option_on
);
14052 case OPTION_CONSTRUCT_FLOATS
:
14053 mips_disable_float_construction
= 0;
14056 case OPTION_NO_CONSTRUCT_FLOATS
:
14057 mips_disable_float_construction
= 1;
14069 target_big_endian
= 1;
14073 target_big_endian
= 0;
14079 else if (arg
[0] == '0')
14081 else if (arg
[0] == '1')
14091 mips_debug
= atoi (arg
);
14095 file_mips_opts
.isa
= ISA_MIPS1
;
14099 file_mips_opts
.isa
= ISA_MIPS2
;
14103 file_mips_opts
.isa
= ISA_MIPS3
;
14107 file_mips_opts
.isa
= ISA_MIPS4
;
14111 file_mips_opts
.isa
= ISA_MIPS5
;
14114 case OPTION_MIPS32
:
14115 file_mips_opts
.isa
= ISA_MIPS32
;
14118 case OPTION_MIPS32R2
:
14119 file_mips_opts
.isa
= ISA_MIPS32R2
;
14122 case OPTION_MIPS32R3
:
14123 file_mips_opts
.isa
= ISA_MIPS32R3
;
14126 case OPTION_MIPS32R5
:
14127 file_mips_opts
.isa
= ISA_MIPS32R5
;
14130 case OPTION_MIPS32R6
:
14131 file_mips_opts
.isa
= ISA_MIPS32R6
;
14134 case OPTION_MIPS64R2
:
14135 file_mips_opts
.isa
= ISA_MIPS64R2
;
14138 case OPTION_MIPS64R3
:
14139 file_mips_opts
.isa
= ISA_MIPS64R3
;
14142 case OPTION_MIPS64R5
:
14143 file_mips_opts
.isa
= ISA_MIPS64R5
;
14146 case OPTION_MIPS64R6
:
14147 file_mips_opts
.isa
= ISA_MIPS64R6
;
14150 case OPTION_MIPS64
:
14151 file_mips_opts
.isa
= ISA_MIPS64
;
14155 mips_set_option_string (&mips_tune_string
, arg
);
14159 mips_set_option_string (&mips_arch_string
, arg
);
14163 mips_set_option_string (&mips_arch_string
, "4650");
14164 mips_set_option_string (&mips_tune_string
, "4650");
14167 case OPTION_NO_M4650
:
14171 mips_set_option_string (&mips_arch_string
, "4010");
14172 mips_set_option_string (&mips_tune_string
, "4010");
14175 case OPTION_NO_M4010
:
14179 mips_set_option_string (&mips_arch_string
, "4100");
14180 mips_set_option_string (&mips_tune_string
, "4100");
14183 case OPTION_NO_M4100
:
14187 mips_set_option_string (&mips_arch_string
, "3900");
14188 mips_set_option_string (&mips_tune_string
, "3900");
14191 case OPTION_NO_M3900
:
14194 case OPTION_MICROMIPS
:
14195 if (file_mips_opts
.mips16
== 1)
14197 as_bad (_("-mmicromips cannot be used with -mips16"));
14200 file_mips_opts
.micromips
= 1;
14201 mips_no_prev_insn ();
14204 case OPTION_NO_MICROMIPS
:
14205 file_mips_opts
.micromips
= 0;
14206 mips_no_prev_insn ();
14209 case OPTION_MIPS16
:
14210 if (file_mips_opts
.micromips
== 1)
14212 as_bad (_("-mips16 cannot be used with -micromips"));
14215 file_mips_opts
.mips16
= 1;
14216 mips_no_prev_insn ();
14219 case OPTION_NO_MIPS16
:
14220 file_mips_opts
.mips16
= 0;
14221 mips_no_prev_insn ();
14224 case OPTION_FIX_24K
:
14228 case OPTION_NO_FIX_24K
:
14232 case OPTION_FIX_RM7000
:
14233 mips_fix_rm7000
= 1;
14236 case OPTION_NO_FIX_RM7000
:
14237 mips_fix_rm7000
= 0;
14240 case OPTION_FIX_LOONGSON2F_JUMP
:
14241 mips_fix_loongson2f_jump
= TRUE
;
14244 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14245 mips_fix_loongson2f_jump
= FALSE
;
14248 case OPTION_FIX_LOONGSON2F_NOP
:
14249 mips_fix_loongson2f_nop
= TRUE
;
14252 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14253 mips_fix_loongson2f_nop
= FALSE
;
14256 case OPTION_FIX_VR4120
:
14257 mips_fix_vr4120
= 1;
14260 case OPTION_NO_FIX_VR4120
:
14261 mips_fix_vr4120
= 0;
14264 case OPTION_FIX_VR4130
:
14265 mips_fix_vr4130
= 1;
14268 case OPTION_NO_FIX_VR4130
:
14269 mips_fix_vr4130
= 0;
14272 case OPTION_FIX_CN63XXP1
:
14273 mips_fix_cn63xxp1
= TRUE
;
14276 case OPTION_NO_FIX_CN63XXP1
:
14277 mips_fix_cn63xxp1
= FALSE
;
14280 case OPTION_RELAX_BRANCH
:
14281 mips_relax_branch
= 1;
14284 case OPTION_NO_RELAX_BRANCH
:
14285 mips_relax_branch
= 0;
14288 case OPTION_INSN32
:
14289 file_mips_opts
.insn32
= TRUE
;
14292 case OPTION_NO_INSN32
:
14293 file_mips_opts
.insn32
= FALSE
;
14296 case OPTION_MSHARED
:
14297 mips_in_shared
= TRUE
;
14300 case OPTION_MNO_SHARED
:
14301 mips_in_shared
= FALSE
;
14304 case OPTION_MSYM32
:
14305 file_mips_opts
.sym32
= TRUE
;
14308 case OPTION_MNO_SYM32
:
14309 file_mips_opts
.sym32
= FALSE
;
14312 /* When generating ELF code, we permit -KPIC and -call_shared to
14313 select SVR4_PIC, and -non_shared to select no PIC. This is
14314 intended to be compatible with Irix 5. */
14315 case OPTION_CALL_SHARED
:
14316 mips_pic
= SVR4_PIC
;
14317 mips_abicalls
= TRUE
;
14320 case OPTION_CALL_NONPIC
:
14322 mips_abicalls
= TRUE
;
14325 case OPTION_NON_SHARED
:
14327 mips_abicalls
= FALSE
;
14330 /* The -xgot option tells the assembler to use 32 bit offsets
14331 when accessing the got in SVR4_PIC mode. It is for Irix
14338 g_switch_value
= atoi (arg
);
14342 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14345 mips_abi
= O32_ABI
;
14349 mips_abi
= N32_ABI
;
14353 mips_abi
= N64_ABI
;
14354 if (!support_64bit_objects())
14355 as_fatal (_("no compiled in support for 64 bit object file format"));
14359 file_mips_opts
.gp
= 32;
14363 file_mips_opts
.gp
= 64;
14367 file_mips_opts
.fp
= 32;
14371 file_mips_opts
.fp
= 0;
14375 file_mips_opts
.fp
= 64;
14378 case OPTION_ODD_SPREG
:
14379 file_mips_opts
.oddspreg
= 1;
14382 case OPTION_NO_ODD_SPREG
:
14383 file_mips_opts
.oddspreg
= 0;
14386 case OPTION_SINGLE_FLOAT
:
14387 file_mips_opts
.single_float
= 1;
14390 case OPTION_DOUBLE_FLOAT
:
14391 file_mips_opts
.single_float
= 0;
14394 case OPTION_SOFT_FLOAT
:
14395 file_mips_opts
.soft_float
= 1;
14398 case OPTION_HARD_FLOAT
:
14399 file_mips_opts
.soft_float
= 0;
14403 if (strcmp (arg
, "32") == 0)
14404 mips_abi
= O32_ABI
;
14405 else if (strcmp (arg
, "o64") == 0)
14406 mips_abi
= O64_ABI
;
14407 else if (strcmp (arg
, "n32") == 0)
14408 mips_abi
= N32_ABI
;
14409 else if (strcmp (arg
, "64") == 0)
14411 mips_abi
= N64_ABI
;
14412 if (! support_64bit_objects())
14413 as_fatal (_("no compiled in support for 64 bit object file "
14416 else if (strcmp (arg
, "eabi") == 0)
14417 mips_abi
= EABI_ABI
;
14420 as_fatal (_("invalid abi -mabi=%s"), arg
);
14425 case OPTION_M7000_HILO_FIX
:
14426 mips_7000_hilo_fix
= TRUE
;
14429 case OPTION_MNO_7000_HILO_FIX
:
14430 mips_7000_hilo_fix
= FALSE
;
14433 case OPTION_MDEBUG
:
14434 mips_flag_mdebug
= TRUE
;
14437 case OPTION_NO_MDEBUG
:
14438 mips_flag_mdebug
= FALSE
;
14442 mips_flag_pdr
= TRUE
;
14445 case OPTION_NO_PDR
:
14446 mips_flag_pdr
= FALSE
;
14449 case OPTION_MVXWORKS_PIC
:
14450 mips_pic
= VXWORKS_PIC
;
14454 if (strcmp (arg
, "2008") == 0)
14456 else if (strcmp (arg
, "legacy") == 0)
14460 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14469 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14474 /* Set up globals to tune for the ISA or processor described by INFO. */
14477 mips_set_tune (const struct mips_cpu_info
*info
)
14480 mips_tune
= info
->cpu
;
14485 mips_after_parse_args (void)
14487 const struct mips_cpu_info
*arch_info
= 0;
14488 const struct mips_cpu_info
*tune_info
= 0;
14490 /* GP relative stuff not working for PE */
14491 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14493 if (g_switch_seen
&& g_switch_value
!= 0)
14494 as_bad (_("-G not supported in this configuration"));
14495 g_switch_value
= 0;
14498 if (mips_abi
== NO_ABI
)
14499 mips_abi
= MIPS_DEFAULT_ABI
;
14501 /* The following code determines the architecture.
14502 Similar code was added to GCC 3.3 (see override_options() in
14503 config/mips/mips.c). The GAS and GCC code should be kept in sync
14504 as much as possible. */
14506 if (mips_arch_string
!= 0)
14507 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14509 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14511 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14512 ISA level specified by -mipsN, while arch_info->isa contains
14513 the -march selection (if any). */
14514 if (arch_info
!= 0)
14516 /* -march takes precedence over -mipsN, since it is more descriptive.
14517 There's no harm in specifying both as long as the ISA levels
14519 if (file_mips_opts
.isa
!= arch_info
->isa
)
14520 as_bad (_("-%s conflicts with the other architecture options,"
14521 " which imply -%s"),
14522 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14523 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14526 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14529 if (arch_info
== 0)
14531 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14532 gas_assert (arch_info
);
14535 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14536 as_bad (_("-march=%s is not compatible with the selected ABI"),
14539 file_mips_opts
.arch
= arch_info
->cpu
;
14540 file_mips_opts
.isa
= arch_info
->isa
;
14542 /* Set up initial mips_opts state. */
14543 mips_opts
= file_mips_opts
;
14545 /* The register size inference code is now placed in
14546 file_mips_check_options. */
14548 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14550 if (mips_tune_string
!= 0)
14551 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14553 if (tune_info
== 0)
14554 mips_set_tune (arch_info
);
14556 mips_set_tune (tune_info
);
14558 if (mips_flag_mdebug
< 0)
14559 mips_flag_mdebug
= 0;
14563 mips_init_after_args (void)
14565 /* initialize opcodes */
14566 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14567 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14571 md_pcrel_from (fixS
*fixP
)
14573 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14574 switch (fixP
->fx_r_type
)
14576 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14577 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14578 /* Return the address of the delay slot. */
14581 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14582 case BFD_RELOC_MICROMIPS_JMP
:
14583 case BFD_RELOC_16_PCREL_S2
:
14584 case BFD_RELOC_MIPS_21_PCREL_S2
:
14585 case BFD_RELOC_MIPS_26_PCREL_S2
:
14586 case BFD_RELOC_MIPS_JMP
:
14587 /* Return the address of the delay slot. */
14595 /* This is called before the symbol table is processed. In order to
14596 work with gcc when using mips-tfile, we must keep all local labels.
14597 However, in other cases, we want to discard them. If we were
14598 called with -g, but we didn't see any debugging information, it may
14599 mean that gcc is smuggling debugging information through to
14600 mips-tfile, in which case we must generate all local labels. */
14603 mips_frob_file_before_adjust (void)
14605 #ifndef NO_ECOFF_DEBUGGING
14606 if (ECOFF_DEBUGGING
14608 && ! ecoff_debugging_seen
)
14609 flag_keep_locals
= 1;
14613 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14614 the corresponding LO16 reloc. This is called before md_apply_fix and
14615 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14616 relocation operators.
14618 For our purposes, a %lo() expression matches a %got() or %hi()
14621 (a) it refers to the same symbol; and
14622 (b) the offset applied in the %lo() expression is no lower than
14623 the offset applied in the %got() or %hi().
14625 (b) allows us to cope with code like:
14628 lh $4,%lo(foo+2)($4)
14630 ...which is legal on RELA targets, and has a well-defined behaviour
14631 if the user knows that adding 2 to "foo" will not induce a carry to
14634 When several %lo()s match a particular %got() or %hi(), we use the
14635 following rules to distinguish them:
14637 (1) %lo()s with smaller offsets are a better match than %lo()s with
14640 (2) %lo()s with no matching %got() or %hi() are better than those
14641 that already have a matching %got() or %hi().
14643 (3) later %lo()s are better than earlier %lo()s.
14645 These rules are applied in order.
14647 (1) means, among other things, that %lo()s with identical offsets are
14648 chosen if they exist.
14650 (2) means that we won't associate several high-part relocations with
14651 the same low-part relocation unless there's no alternative. Having
14652 several high parts for the same low part is a GNU extension; this rule
14653 allows careful users to avoid it.
14655 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14656 with the last high-part relocation being at the front of the list.
14657 It therefore makes sense to choose the last matching low-part
14658 relocation, all other things being equal. It's also easier
14659 to code that way. */
14662 mips_frob_file (void)
14664 struct mips_hi_fixup
*l
;
14665 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14667 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14669 segment_info_type
*seginfo
;
14670 bfd_boolean matched_lo_p
;
14671 fixS
**hi_pos
, **lo_pos
, **pos
;
14673 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14675 /* If a GOT16 relocation turns out to be against a global symbol,
14676 there isn't supposed to be a matching LO. Ignore %gots against
14677 constants; we'll report an error for those later. */
14678 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14679 && !(l
->fixp
->fx_addsy
14680 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14683 /* Check quickly whether the next fixup happens to be a matching %lo. */
14684 if (fixup_has_matching_lo_p (l
->fixp
))
14687 seginfo
= seg_info (l
->seg
);
14689 /* Set HI_POS to the position of this relocation in the chain.
14690 Set LO_POS to the position of the chosen low-part relocation.
14691 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14692 relocation that matches an immediately-preceding high-part
14696 matched_lo_p
= FALSE
;
14697 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14699 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14701 if (*pos
== l
->fixp
)
14704 if ((*pos
)->fx_r_type
== looking_for_rtype
14705 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14706 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14708 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14710 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14713 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14714 && fixup_has_matching_lo_p (*pos
));
14717 /* If we found a match, remove the high-part relocation from its
14718 current position and insert it before the low-part relocation.
14719 Make the offsets match so that fixup_has_matching_lo_p()
14722 We don't warn about unmatched high-part relocations since some
14723 versions of gcc have been known to emit dead "lui ...%hi(...)"
14725 if (lo_pos
!= NULL
)
14727 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14728 if (l
->fixp
->fx_next
!= *lo_pos
)
14730 *hi_pos
= l
->fixp
->fx_next
;
14731 l
->fixp
->fx_next
= *lo_pos
;
14739 mips_force_relocation (fixS
*fixp
)
14741 if (generic_force_reloc (fixp
))
14744 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14745 so that the linker relaxation can update targets. */
14746 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14747 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14748 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14751 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14752 if (ISA_IS_R6 (mips_opts
.isa
)
14753 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14754 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
14755 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
14756 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
14757 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
14758 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
14759 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
14765 /* Read the instruction associated with RELOC from BUF. */
14767 static unsigned int
14768 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14770 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14771 return read_compressed_insn (buf
, 4);
14773 return read_insn (buf
);
14776 /* Write instruction INSN to BUF, given that it has been relocated
14780 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14781 unsigned long insn
)
14783 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14784 write_compressed_insn (buf
, insn
, 4);
14786 write_insn (buf
, insn
);
14789 /* Apply a fixup to the object file. */
14792 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14795 unsigned long insn
;
14796 reloc_howto_type
*howto
;
14798 if (fixP
->fx_pcrel
)
14799 switch (fixP
->fx_r_type
)
14801 case BFD_RELOC_16_PCREL_S2
:
14802 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14803 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14804 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14805 case BFD_RELOC_32_PCREL
:
14806 case BFD_RELOC_MIPS_21_PCREL_S2
:
14807 case BFD_RELOC_MIPS_26_PCREL_S2
:
14808 case BFD_RELOC_MIPS_18_PCREL_S3
:
14809 case BFD_RELOC_MIPS_19_PCREL_S2
:
14810 case BFD_RELOC_HI16_S_PCREL
:
14811 case BFD_RELOC_LO16_PCREL
:
14815 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
14819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14820 _("PC-relative reference to a different section"));
14824 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14825 that have no MIPS ELF equivalent. */
14826 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
14828 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14833 gas_assert (fixP
->fx_size
== 2
14834 || fixP
->fx_size
== 4
14835 || fixP
->fx_r_type
== BFD_RELOC_8
14836 || fixP
->fx_r_type
== BFD_RELOC_16
14837 || fixP
->fx_r_type
== BFD_RELOC_64
14838 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14839 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14840 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14841 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14842 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14843 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
14844 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
14846 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14848 /* Don't treat parts of a composite relocation as done. There are two
14851 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14852 should nevertheless be emitted if the first part is.
14854 (2) In normal usage, composite relocations are never assembly-time
14855 constants. The easiest way of dealing with the pathological
14856 exceptions is to generate a relocation against STN_UNDEF and
14857 leave everything up to the linker. */
14858 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14861 switch (fixP
->fx_r_type
)
14863 case BFD_RELOC_MIPS_TLS_GD
:
14864 case BFD_RELOC_MIPS_TLS_LDM
:
14865 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14866 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14867 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14868 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14869 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14870 case BFD_RELOC_MIPS_TLS_TPREL32
:
14871 case BFD_RELOC_MIPS_TLS_TPREL64
:
14872 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14873 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14874 case BFD_RELOC_MICROMIPS_TLS_GD
:
14875 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14876 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14877 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14878 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14879 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14880 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14881 case BFD_RELOC_MIPS16_TLS_GD
:
14882 case BFD_RELOC_MIPS16_TLS_LDM
:
14883 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14884 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14885 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14886 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14887 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14888 if (!fixP
->fx_addsy
)
14890 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14891 _("TLS relocation against a constant"));
14894 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14897 case BFD_RELOC_MIPS_JMP
:
14898 case BFD_RELOC_MIPS_SHIFT5
:
14899 case BFD_RELOC_MIPS_SHIFT6
:
14900 case BFD_RELOC_MIPS_GOT_DISP
:
14901 case BFD_RELOC_MIPS_GOT_PAGE
:
14902 case BFD_RELOC_MIPS_GOT_OFST
:
14903 case BFD_RELOC_MIPS_SUB
:
14904 case BFD_RELOC_MIPS_INSERT_A
:
14905 case BFD_RELOC_MIPS_INSERT_B
:
14906 case BFD_RELOC_MIPS_DELETE
:
14907 case BFD_RELOC_MIPS_HIGHEST
:
14908 case BFD_RELOC_MIPS_HIGHER
:
14909 case BFD_RELOC_MIPS_SCN_DISP
:
14910 case BFD_RELOC_MIPS_REL16
:
14911 case BFD_RELOC_MIPS_RELGOT
:
14912 case BFD_RELOC_MIPS_JALR
:
14913 case BFD_RELOC_HI16
:
14914 case BFD_RELOC_HI16_S
:
14915 case BFD_RELOC_LO16
:
14916 case BFD_RELOC_GPREL16
:
14917 case BFD_RELOC_MIPS_LITERAL
:
14918 case BFD_RELOC_MIPS_CALL16
:
14919 case BFD_RELOC_MIPS_GOT16
:
14920 case BFD_RELOC_GPREL32
:
14921 case BFD_RELOC_MIPS_GOT_HI16
:
14922 case BFD_RELOC_MIPS_GOT_LO16
:
14923 case BFD_RELOC_MIPS_CALL_HI16
:
14924 case BFD_RELOC_MIPS_CALL_LO16
:
14925 case BFD_RELOC_MIPS16_GPREL
:
14926 case BFD_RELOC_MIPS16_GOT16
:
14927 case BFD_RELOC_MIPS16_CALL16
:
14928 case BFD_RELOC_MIPS16_HI16
:
14929 case BFD_RELOC_MIPS16_HI16_S
:
14930 case BFD_RELOC_MIPS16_LO16
:
14931 case BFD_RELOC_MIPS16_JMP
:
14932 case BFD_RELOC_MICROMIPS_JMP
:
14933 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14934 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14935 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14936 case BFD_RELOC_MICROMIPS_SUB
:
14937 case BFD_RELOC_MICROMIPS_HIGHEST
:
14938 case BFD_RELOC_MICROMIPS_HIGHER
:
14939 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14940 case BFD_RELOC_MICROMIPS_JALR
:
14941 case BFD_RELOC_MICROMIPS_HI16
:
14942 case BFD_RELOC_MICROMIPS_HI16_S
:
14943 case BFD_RELOC_MICROMIPS_LO16
:
14944 case BFD_RELOC_MICROMIPS_GPREL16
:
14945 case BFD_RELOC_MICROMIPS_LITERAL
:
14946 case BFD_RELOC_MICROMIPS_CALL16
:
14947 case BFD_RELOC_MICROMIPS_GOT16
:
14948 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14949 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14950 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14951 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14952 case BFD_RELOC_MIPS_EH
:
14957 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14959 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14960 if (mips16_reloc_p (fixP
->fx_r_type
))
14961 insn
|= mips16_immed_extend (value
, 16);
14963 insn
|= (value
& 0xffff);
14964 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14968 _("unsupported constant in relocation"));
14973 /* This is handled like BFD_RELOC_32, but we output a sign
14974 extended value if we are only 32 bits. */
14977 if (8 <= sizeof (valueT
))
14978 md_number_to_chars (buf
, *valP
, 8);
14983 if ((*valP
& 0x80000000) != 0)
14987 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14988 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14993 case BFD_RELOC_RVA
:
14995 case BFD_RELOC_32_PCREL
:
14998 /* If we are deleting this reloc entry, we must fill in the
14999 value now. This can happen if we have a .word which is not
15000 resolved when it appears but is later defined. */
15002 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15005 case BFD_RELOC_MIPS_21_PCREL_S2
:
15006 case BFD_RELOC_MIPS_26_PCREL_S2
:
15007 if ((*valP
& 0x3) != 0)
15008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15009 _("branch to misaligned address (%lx)"), (long) *valP
);
15011 gas_assert (!fixP
->fx_done
);
15014 case BFD_RELOC_MIPS_18_PCREL_S3
:
15015 if ((S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15017 _("PC-relative access using misaligned symbol (%lx)"),
15018 (long) S_GET_VALUE (fixP
->fx_addsy
));
15019 if ((fixP
->fx_offset
& 0x7) != 0)
15020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15021 _("PC-relative access using misaligned offset (%lx)"),
15022 (long) fixP
->fx_offset
);
15024 gas_assert (!fixP
->fx_done
);
15027 case BFD_RELOC_MIPS_19_PCREL_S2
:
15028 if ((*valP
& 0x3) != 0)
15029 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15030 _("PC-relative access to misaligned address (%lx)"),
15031 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15033 gas_assert (!fixP
->fx_done
);
15036 case BFD_RELOC_HI16_S_PCREL
:
15037 case BFD_RELOC_LO16_PCREL
:
15038 gas_assert (!fixP
->fx_done
);
15041 case BFD_RELOC_16_PCREL_S2
:
15042 if ((*valP
& 0x3) != 0)
15043 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15044 _("branch to misaligned address (%lx)"), (long) *valP
);
15046 /* We need to save the bits in the instruction since fixup_segment()
15047 might be deleting the relocation entry (i.e., a branch within
15048 the current segment). */
15049 if (! fixP
->fx_done
)
15052 /* Update old instruction data. */
15053 insn
= read_insn (buf
);
15055 if (*valP
+ 0x20000 <= 0x3ffff)
15057 insn
|= (*valP
>> 2) & 0xffff;
15058 write_insn (buf
, insn
);
15060 else if (mips_pic
== NO_PIC
15062 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15063 && (fixP
->fx_frag
->fr_address
15064 < text_section
->vma
+ bfd_get_section_size (text_section
))
15065 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15066 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15067 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15069 /* The branch offset is too large. If this is an
15070 unconditional branch, and we are not generating PIC code,
15071 we can convert it to an absolute jump instruction. */
15072 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15073 insn
= 0x0c000000; /* jal */
15075 insn
= 0x08000000; /* j */
15076 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15078 fixP
->fx_addsy
= section_symbol (text_section
);
15079 *valP
+= md_pcrel_from (fixP
);
15080 write_insn (buf
, insn
);
15084 /* If we got here, we have branch-relaxation disabled,
15085 and there's nothing we can do to fix this instruction
15086 without turning it into a longer sequence. */
15087 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15088 _("branch out of range"));
15092 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15093 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15094 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15095 /* We adjust the offset back to even. */
15096 if ((*valP
& 0x1) != 0)
15099 if (! fixP
->fx_done
)
15102 /* Should never visit here, because we keep the relocation. */
15106 case BFD_RELOC_VTABLE_INHERIT
:
15109 && !S_IS_DEFINED (fixP
->fx_addsy
)
15110 && !S_IS_WEAK (fixP
->fx_addsy
))
15111 S_SET_WEAK (fixP
->fx_addsy
);
15114 case BFD_RELOC_NONE
:
15115 case BFD_RELOC_VTABLE_ENTRY
:
15123 /* Remember value for tc_gen_reloc. */
15124 fixP
->fx_addnumber
= *valP
;
15134 name
= input_line_pointer
;
15135 c
= get_symbol_end ();
15136 p
= (symbolS
*) symbol_find_or_make (name
);
15137 *input_line_pointer
= c
;
15141 /* Align the current frag to a given power of two. If a particular
15142 fill byte should be used, FILL points to an integer that contains
15143 that byte, otherwise FILL is null.
15145 This function used to have the comment:
15147 The MIPS assembler also automatically adjusts any preceding label.
15149 The implementation therefore applied the adjustment to a maximum of
15150 one label. However, other label adjustments are applied to batches
15151 of labels, and adjusting just one caused problems when new labels
15152 were added for the sake of debugging or unwind information.
15153 We therefore adjust all preceding labels (given as LABELS) instead. */
15156 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15158 mips_emit_delays ();
15159 mips_record_compressed_mode ();
15160 if (fill
== NULL
&& subseg_text_p (now_seg
))
15161 frag_align_code (to
, 0);
15163 frag_align (to
, fill
? *fill
: 0, 0);
15164 record_alignment (now_seg
, to
);
15165 mips_move_labels (labels
, FALSE
);
15168 /* Align to a given power of two. .align 0 turns off the automatic
15169 alignment used by the data creating pseudo-ops. */
15172 s_align (int x ATTRIBUTE_UNUSED
)
15174 int temp
, fill_value
, *fill_ptr
;
15175 long max_alignment
= 28;
15177 /* o Note that the assembler pulls down any immediately preceding label
15178 to the aligned address.
15179 o It's not documented but auto alignment is reinstated by
15180 a .align pseudo instruction.
15181 o Note also that after auto alignment is turned off the mips assembler
15182 issues an error on attempt to assemble an improperly aligned data item.
15185 temp
= get_absolute_expression ();
15186 if (temp
> max_alignment
)
15187 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15190 as_warn (_("alignment negative, 0 assumed"));
15193 if (*input_line_pointer
== ',')
15195 ++input_line_pointer
;
15196 fill_value
= get_absolute_expression ();
15197 fill_ptr
= &fill_value
;
15203 segment_info_type
*si
= seg_info (now_seg
);
15204 struct insn_label_list
*l
= si
->label_list
;
15205 /* Auto alignment should be switched on by next section change. */
15207 mips_align (temp
, fill_ptr
, l
);
15214 demand_empty_rest_of_line ();
15218 s_change_sec (int sec
)
15222 /* The ELF backend needs to know that we are changing sections, so
15223 that .previous works correctly. We could do something like check
15224 for an obj_section_change_hook macro, but that might be confusing
15225 as it would not be appropriate to use it in the section changing
15226 functions in read.c, since obj-elf.c intercepts those. FIXME:
15227 This should be cleaner, somehow. */
15228 obj_elf_section_change_hook ();
15230 mips_emit_delays ();
15241 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15242 demand_empty_rest_of_line ();
15246 seg
= subseg_new (RDATA_SECTION_NAME
,
15247 (subsegT
) get_absolute_expression ());
15248 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15249 | SEC_READONLY
| SEC_RELOC
15251 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15252 record_alignment (seg
, 4);
15253 demand_empty_rest_of_line ();
15257 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15258 bfd_set_section_flags (stdoutput
, seg
,
15259 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15260 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15261 record_alignment (seg
, 4);
15262 demand_empty_rest_of_line ();
15266 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15267 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15268 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15269 record_alignment (seg
, 4);
15270 demand_empty_rest_of_line ();
15278 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15280 char *section_name
;
15285 int section_entry_size
;
15286 int section_alignment
;
15288 section_name
= input_line_pointer
;
15289 c
= get_symbol_end ();
15291 next_c
= *(input_line_pointer
+ 1);
15293 /* Do we have .section Name<,"flags">? */
15294 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15296 /* just after name is now '\0'. */
15297 *input_line_pointer
= c
;
15298 input_line_pointer
= section_name
;
15299 obj_elf_section (ignore
);
15302 input_line_pointer
++;
15304 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15306 section_type
= get_absolute_expression ();
15309 if (*input_line_pointer
++ == ',')
15310 section_flag
= get_absolute_expression ();
15313 if (*input_line_pointer
++ == ',')
15314 section_entry_size
= get_absolute_expression ();
15316 section_entry_size
= 0;
15317 if (*input_line_pointer
++ == ',')
15318 section_alignment
= get_absolute_expression ();
15320 section_alignment
= 0;
15321 /* FIXME: really ignore? */
15322 (void) section_alignment
;
15324 section_name
= xstrdup (section_name
);
15326 /* When using the generic form of .section (as implemented by obj-elf.c),
15327 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15328 traditionally had to fall back on the more common @progbits instead.
15330 There's nothing really harmful in this, since bfd will correct
15331 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15332 means that, for backwards compatibility, the special_section entries
15333 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15335 Even so, we shouldn't force users of the MIPS .section syntax to
15336 incorrectly label the sections as SHT_PROGBITS. The best compromise
15337 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15338 generic type-checking code. */
15339 if (section_type
== SHT_MIPS_DWARF
)
15340 section_type
= SHT_PROGBITS
;
15342 obj_elf_change_section (section_name
, section_type
, section_flag
,
15343 section_entry_size
, 0, 0, 0);
15345 if (now_seg
->name
!= section_name
)
15346 free (section_name
);
15350 mips_enable_auto_align (void)
15356 s_cons (int log_size
)
15358 segment_info_type
*si
= seg_info (now_seg
);
15359 struct insn_label_list
*l
= si
->label_list
;
15361 mips_emit_delays ();
15362 if (log_size
> 0 && auto_align
)
15363 mips_align (log_size
, 0, l
);
15364 cons (1 << log_size
);
15365 mips_clear_insn_labels ();
15369 s_float_cons (int type
)
15371 segment_info_type
*si
= seg_info (now_seg
);
15372 struct insn_label_list
*l
= si
->label_list
;
15374 mips_emit_delays ();
15379 mips_align (3, 0, l
);
15381 mips_align (2, 0, l
);
15385 mips_clear_insn_labels ();
15388 /* Handle .globl. We need to override it because on Irix 5 you are
15391 where foo is an undefined symbol, to mean that foo should be
15392 considered to be the address of a function. */
15395 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15404 name
= input_line_pointer
;
15405 c
= get_symbol_end ();
15406 symbolP
= symbol_find_or_make (name
);
15407 S_SET_EXTERNAL (symbolP
);
15409 *input_line_pointer
= c
;
15410 SKIP_WHITESPACE ();
15412 /* On Irix 5, every global symbol that is not explicitly labelled as
15413 being a function is apparently labelled as being an object. */
15416 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15417 && (*input_line_pointer
!= ','))
15422 secname
= input_line_pointer
;
15423 c
= get_symbol_end ();
15424 sec
= bfd_get_section_by_name (stdoutput
, secname
);
15426 as_bad (_("%s: no such section"), secname
);
15427 *input_line_pointer
= c
;
15429 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
15430 flag
= BSF_FUNCTION
;
15433 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
15435 c
= *input_line_pointer
;
15438 input_line_pointer
++;
15439 SKIP_WHITESPACE ();
15440 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
15446 demand_empty_rest_of_line ();
15450 s_option (int x ATTRIBUTE_UNUSED
)
15455 opt
= input_line_pointer
;
15456 c
= get_symbol_end ();
15460 /* FIXME: What does this mean? */
15462 else if (strncmp (opt
, "pic", 3) == 0)
15466 i
= atoi (opt
+ 3);
15471 mips_pic
= SVR4_PIC
;
15472 mips_abicalls
= TRUE
;
15475 as_bad (_(".option pic%d not supported"), i
);
15477 if (mips_pic
== SVR4_PIC
)
15479 if (g_switch_seen
&& g_switch_value
!= 0)
15480 as_warn (_("-G may not be used with SVR4 PIC code"));
15481 g_switch_value
= 0;
15482 bfd_set_gp_size (stdoutput
, 0);
15486 as_warn (_("unrecognized option \"%s\""), opt
);
15488 *input_line_pointer
= c
;
15489 demand_empty_rest_of_line ();
15492 /* This structure is used to hold a stack of .set values. */
15494 struct mips_option_stack
15496 struct mips_option_stack
*next
;
15497 struct mips_set_options options
;
15500 static struct mips_option_stack
*mips_opts_stack
;
15503 parse_code_option (char * name
)
15505 const struct mips_ase
*ase
;
15506 if (strncmp (name
, "at=", 3) == 0)
15508 char *s
= name
+ 3;
15510 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
15511 as_bad (_("unrecognized register name `%s'"), s
);
15513 else if (strcmp (name
, "at") == 0)
15514 mips_opts
.at
= ATREG
;
15515 else if (strcmp (name
, "noat") == 0)
15516 mips_opts
.at
= ZERO
;
15517 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
15518 mips_opts
.nomove
= 0;
15519 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
15520 mips_opts
.nomove
= 1;
15521 else if (strcmp (name
, "bopt") == 0)
15522 mips_opts
.nobopt
= 0;
15523 else if (strcmp (name
, "nobopt") == 0)
15524 mips_opts
.nobopt
= 1;
15525 else if (strcmp (name
, "gp=32") == 0)
15527 else if (strcmp (name
, "gp=64") == 0)
15529 else if (strcmp (name
, "fp=32") == 0)
15531 else if (strcmp (name
, "fp=xx") == 0)
15533 else if (strcmp (name
, "fp=64") == 0)
15535 else if (strcmp (name
, "softfloat") == 0)
15536 mips_opts
.soft_float
= 1;
15537 else if (strcmp (name
, "hardfloat") == 0)
15538 mips_opts
.soft_float
= 0;
15539 else if (strcmp (name
, "singlefloat") == 0)
15540 mips_opts
.single_float
= 1;
15541 else if (strcmp (name
, "doublefloat") == 0)
15542 mips_opts
.single_float
= 0;
15543 else if (strcmp (name
, "nooddspreg") == 0)
15544 mips_opts
.oddspreg
= 0;
15545 else if (strcmp (name
, "oddspreg") == 0)
15546 mips_opts
.oddspreg
= 1;
15547 else if (strcmp (name
, "mips16") == 0
15548 || strcmp (name
, "MIPS-16") == 0)
15549 mips_opts
.mips16
= 1;
15550 else if (strcmp (name
, "nomips16") == 0
15551 || strcmp (name
, "noMIPS-16") == 0)
15552 mips_opts
.mips16
= 0;
15553 else if (strcmp (name
, "micromips") == 0)
15554 mips_opts
.micromips
= 1;
15555 else if (strcmp (name
, "nomicromips") == 0)
15556 mips_opts
.micromips
= 0;
15557 else if (name
[0] == 'n'
15559 && (ase
= mips_lookup_ase (name
+ 2)))
15560 mips_set_ase (ase
, &mips_opts
, FALSE
);
15561 else if ((ase
= mips_lookup_ase (name
)))
15562 mips_set_ase (ase
, &mips_opts
, TRUE
);
15563 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15565 /* Permit the user to change the ISA and architecture on the fly.
15566 Needless to say, misuse can cause serious problems. */
15567 if (strncmp (name
, "arch=", 5) == 0)
15569 const struct mips_cpu_info
*p
;
15571 p
= mips_parse_cpu ("internal use", name
+ 5);
15573 as_bad (_("unknown architecture %s"), name
+ 5);
15576 mips_opts
.arch
= p
->cpu
;
15577 mips_opts
.isa
= p
->isa
;
15580 else if (strncmp (name
, "mips", 4) == 0)
15582 const struct mips_cpu_info
*p
;
15584 p
= mips_parse_cpu ("internal use", name
);
15586 as_bad (_("unknown ISA level %s"), name
+ 4);
15589 mips_opts
.arch
= p
->cpu
;
15590 mips_opts
.isa
= p
->isa
;
15594 as_bad (_("unknown ISA or architecture %s"), name
);
15596 else if (strcmp (name
, "autoextend") == 0)
15597 mips_opts
.noautoextend
= 0;
15598 else if (strcmp (name
, "noautoextend") == 0)
15599 mips_opts
.noautoextend
= 1;
15600 else if (strcmp (name
, "insn32") == 0)
15601 mips_opts
.insn32
= TRUE
;
15602 else if (strcmp (name
, "noinsn32") == 0)
15603 mips_opts
.insn32
= FALSE
;
15604 else if (strcmp (name
, "sym32") == 0)
15605 mips_opts
.sym32
= TRUE
;
15606 else if (strcmp (name
, "nosym32") == 0)
15607 mips_opts
.sym32
= FALSE
;
15613 /* Handle the .set pseudo-op. */
15616 s_mipsset (int x ATTRIBUTE_UNUSED
)
15618 char *name
= input_line_pointer
, ch
;
15619 int prev_isa
= mips_opts
.isa
;
15621 file_mips_check_options ();
15623 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15624 ++input_line_pointer
;
15625 ch
= *input_line_pointer
;
15626 *input_line_pointer
= '\0';
15628 if (strchr (name
, ','))
15630 /* Generic ".set" directive; use the generic handler. */
15631 *input_line_pointer
= ch
;
15632 input_line_pointer
= name
;
15637 if (strcmp (name
, "reorder") == 0)
15639 if (mips_opts
.noreorder
)
15642 else if (strcmp (name
, "noreorder") == 0)
15644 if (!mips_opts
.noreorder
)
15645 start_noreorder ();
15647 else if (strcmp (name
, "macro") == 0)
15648 mips_opts
.warn_about_macros
= 0;
15649 else if (strcmp (name
, "nomacro") == 0)
15651 if (mips_opts
.noreorder
== 0)
15652 as_bad (_("`noreorder' must be set before `nomacro'"));
15653 mips_opts
.warn_about_macros
= 1;
15655 else if (strcmp (name
, "gp=default") == 0)
15656 mips_opts
.gp
= file_mips_opts
.gp
;
15657 else if (strcmp (name
, "fp=default") == 0)
15658 mips_opts
.fp
= file_mips_opts
.fp
;
15659 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15661 mips_opts
.isa
= file_mips_opts
.isa
;
15662 mips_opts
.arch
= file_mips_opts
.arch
;
15663 mips_opts
.gp
= file_mips_opts
.gp
;
15664 mips_opts
.fp
= file_mips_opts
.fp
;
15666 else if (strcmp (name
, "push") == 0)
15668 struct mips_option_stack
*s
;
15670 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15671 s
->next
= mips_opts_stack
;
15672 s
->options
= mips_opts
;
15673 mips_opts_stack
= s
;
15675 else if (strcmp (name
, "pop") == 0)
15677 struct mips_option_stack
*s
;
15679 s
= mips_opts_stack
;
15681 as_bad (_(".set pop with no .set push"));
15684 /* If we're changing the reorder mode we need to handle
15685 delay slots correctly. */
15686 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15687 start_noreorder ();
15688 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15691 mips_opts
= s
->options
;
15692 mips_opts_stack
= s
->next
;
15696 else if (!parse_code_option (name
))
15697 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
15699 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
15700 registers based on what is supported by the arch/cpu. */
15701 if (mips_opts
.isa
!= prev_isa
)
15703 switch (mips_opts
.isa
)
15708 /* MIPS I cannot support FPXX. */
15710 /* fall-through. */
15717 if (mips_opts
.fp
!= 0)
15733 if (mips_opts
.fp
!= 0)
15735 if (mips_opts
.arch
== CPU_R5900
)
15742 as_bad (_("unknown ISA level %s"), name
+ 4);
15747 mips_check_options (&mips_opts
, FALSE
);
15749 mips_check_isa_supports_ases ();
15750 *input_line_pointer
= ch
;
15751 demand_empty_rest_of_line ();
15754 /* Handle the .module pseudo-op. */
15757 s_module (int ignore ATTRIBUTE_UNUSED
)
15759 char *name
= input_line_pointer
, ch
;
15761 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15762 ++input_line_pointer
;
15763 ch
= *input_line_pointer
;
15764 *input_line_pointer
= '\0';
15766 if (!file_mips_opts_checked
)
15768 if (!parse_code_option (name
))
15769 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
15771 /* Update module level settings from mips_opts. */
15772 file_mips_opts
= mips_opts
;
15775 as_bad (_(".module is not permitted after generating code"));
15777 *input_line_pointer
= ch
;
15778 demand_empty_rest_of_line ();
15781 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15782 .option pic2. It means to generate SVR4 PIC calls. */
15785 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15787 mips_pic
= SVR4_PIC
;
15788 mips_abicalls
= TRUE
;
15790 if (g_switch_seen
&& g_switch_value
!= 0)
15791 as_warn (_("-G may not be used with SVR4 PIC code"));
15792 g_switch_value
= 0;
15794 bfd_set_gp_size (stdoutput
, 0);
15795 demand_empty_rest_of_line ();
15798 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15799 PIC code. It sets the $gp register for the function based on the
15800 function address, which is in the register named in the argument.
15801 This uses a relocation against _gp_disp, which is handled specially
15802 by the linker. The result is:
15803 lui $gp,%hi(_gp_disp)
15804 addiu $gp,$gp,%lo(_gp_disp)
15805 addu $gp,$gp,.cpload argument
15806 The .cpload argument is normally $25 == $t9.
15808 The -mno-shared option changes this to:
15809 lui $gp,%hi(__gnu_local_gp)
15810 addiu $gp,$gp,%lo(__gnu_local_gp)
15811 and the argument is ignored. This saves an instruction, but the
15812 resulting code is not position independent; it uses an absolute
15813 address for __gnu_local_gp. Thus code assembled with -mno-shared
15814 can go into an ordinary executable, but not into a shared library. */
15817 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15823 file_mips_check_options ();
15825 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15826 .cpload is ignored. */
15827 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15833 if (mips_opts
.mips16
)
15835 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15836 ignore_rest_of_line ();
15840 /* .cpload should be in a .set noreorder section. */
15841 if (mips_opts
.noreorder
== 0)
15842 as_warn (_(".cpload not in noreorder section"));
15844 reg
= tc_get_register (0);
15846 /* If we need to produce a 64-bit address, we are better off using
15847 the default instruction sequence. */
15848 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15850 ex
.X_op
= O_symbol
;
15851 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15853 ex
.X_op_symbol
= NULL
;
15854 ex
.X_add_number
= 0;
15856 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15857 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15859 mips_mark_labels ();
15860 mips_assembling_insn
= TRUE
;
15863 macro_build_lui (&ex
, mips_gp_register
);
15864 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15865 mips_gp_register
, BFD_RELOC_LO16
);
15867 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15868 mips_gp_register
, reg
);
15871 mips_assembling_insn
= FALSE
;
15872 demand_empty_rest_of_line ();
15875 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15876 .cpsetup $reg1, offset|$reg2, label
15878 If offset is given, this results in:
15879 sd $gp, offset($sp)
15880 lui $gp, %hi(%neg(%gp_rel(label)))
15881 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15882 daddu $gp, $gp, $reg1
15884 If $reg2 is given, this results in:
15885 daddu $reg2, $gp, $0
15886 lui $gp, %hi(%neg(%gp_rel(label)))
15887 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15888 daddu $gp, $gp, $reg1
15889 $reg1 is normally $25 == $t9.
15891 The -mno-shared option replaces the last three instructions with
15893 addiu $gp,$gp,%lo(_gp) */
15896 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15898 expressionS ex_off
;
15899 expressionS ex_sym
;
15902 file_mips_check_options ();
15904 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15905 We also need NewABI support. */
15906 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15912 if (mips_opts
.mips16
)
15914 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15915 ignore_rest_of_line ();
15919 reg1
= tc_get_register (0);
15920 SKIP_WHITESPACE ();
15921 if (*input_line_pointer
!= ',')
15923 as_bad (_("missing argument separator ',' for .cpsetup"));
15927 ++input_line_pointer
;
15928 SKIP_WHITESPACE ();
15929 if (*input_line_pointer
== '$')
15931 mips_cpreturn_register
= tc_get_register (0);
15932 mips_cpreturn_offset
= -1;
15936 mips_cpreturn_offset
= get_absolute_expression ();
15937 mips_cpreturn_register
= -1;
15939 SKIP_WHITESPACE ();
15940 if (*input_line_pointer
!= ',')
15942 as_bad (_("missing argument separator ',' for .cpsetup"));
15946 ++input_line_pointer
;
15947 SKIP_WHITESPACE ();
15948 expression (&ex_sym
);
15950 mips_mark_labels ();
15951 mips_assembling_insn
= TRUE
;
15954 if (mips_cpreturn_register
== -1)
15956 ex_off
.X_op
= O_constant
;
15957 ex_off
.X_add_symbol
= NULL
;
15958 ex_off
.X_op_symbol
= NULL
;
15959 ex_off
.X_add_number
= mips_cpreturn_offset
;
15961 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15962 BFD_RELOC_LO16
, SP
);
15965 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15966 mips_gp_register
, 0);
15968 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15970 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15971 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15974 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15975 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15976 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15978 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15979 mips_gp_register
, reg1
);
15985 ex
.X_op
= O_symbol
;
15986 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15987 ex
.X_op_symbol
= NULL
;
15988 ex
.X_add_number
= 0;
15990 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15991 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15993 macro_build_lui (&ex
, mips_gp_register
);
15994 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15995 mips_gp_register
, BFD_RELOC_LO16
);
16000 mips_assembling_insn
= FALSE
;
16001 demand_empty_rest_of_line ();
16005 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16007 file_mips_check_options ();
16009 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16010 .cplocal is ignored. */
16011 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16017 if (mips_opts
.mips16
)
16019 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16020 ignore_rest_of_line ();
16024 mips_gp_register
= tc_get_register (0);
16025 demand_empty_rest_of_line ();
16028 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16029 offset from $sp. The offset is remembered, and after making a PIC
16030 call $gp is restored from that location. */
16033 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16037 file_mips_check_options ();
16039 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16040 .cprestore is ignored. */
16041 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16047 if (mips_opts
.mips16
)
16049 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16050 ignore_rest_of_line ();
16054 mips_cprestore_offset
= get_absolute_expression ();
16055 mips_cprestore_valid
= 1;
16057 ex
.X_op
= O_constant
;
16058 ex
.X_add_symbol
= NULL
;
16059 ex
.X_op_symbol
= NULL
;
16060 ex
.X_add_number
= mips_cprestore_offset
;
16062 mips_mark_labels ();
16063 mips_assembling_insn
= TRUE
;
16066 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16067 SP
, HAVE_64BIT_ADDRESSES
);
16070 mips_assembling_insn
= FALSE
;
16071 demand_empty_rest_of_line ();
16074 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16075 was given in the preceding .cpsetup, it results in:
16076 ld $gp, offset($sp)
16078 If a register $reg2 was given there, it results in:
16079 daddu $gp, $reg2, $0 */
16082 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16086 file_mips_check_options ();
16088 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16089 We also need NewABI support. */
16090 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16096 if (mips_opts
.mips16
)
16098 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16099 ignore_rest_of_line ();
16103 mips_mark_labels ();
16104 mips_assembling_insn
= TRUE
;
16107 if (mips_cpreturn_register
== -1)
16109 ex
.X_op
= O_constant
;
16110 ex
.X_add_symbol
= NULL
;
16111 ex
.X_op_symbol
= NULL
;
16112 ex
.X_add_number
= mips_cpreturn_offset
;
16114 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16117 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16118 mips_cpreturn_register
, 0);
16121 mips_assembling_insn
= FALSE
;
16122 demand_empty_rest_of_line ();
16125 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16126 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16127 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16128 debug information or MIPS16 TLS. */
16131 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16132 bfd_reloc_code_real_type rtype
)
16139 if (ex
.X_op
!= O_symbol
)
16141 as_bad (_("unsupported use of %s"), dirstr
);
16142 ignore_rest_of_line ();
16145 p
= frag_more (bytes
);
16146 md_number_to_chars (p
, 0, bytes
);
16147 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16148 demand_empty_rest_of_line ();
16149 mips_clear_insn_labels ();
16152 /* Handle .dtprelword. */
16155 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16157 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16160 /* Handle .dtpreldword. */
16163 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16165 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16168 /* Handle .tprelword. */
16171 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16173 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16176 /* Handle .tpreldword. */
16179 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16181 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16184 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16185 code. It sets the offset to use in gp_rel relocations. */
16188 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16190 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16191 We also need NewABI support. */
16192 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16198 mips_gprel_offset
= get_absolute_expression ();
16200 demand_empty_rest_of_line ();
16203 /* Handle the .gpword pseudo-op. This is used when generating PIC
16204 code. It generates a 32 bit GP relative reloc. */
16207 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16209 segment_info_type
*si
;
16210 struct insn_label_list
*l
;
16214 /* When not generating PIC code, this is treated as .word. */
16215 if (mips_pic
!= SVR4_PIC
)
16221 si
= seg_info (now_seg
);
16222 l
= si
->label_list
;
16223 mips_emit_delays ();
16225 mips_align (2, 0, l
);
16228 mips_clear_insn_labels ();
16230 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16232 as_bad (_("unsupported use of .gpword"));
16233 ignore_rest_of_line ();
16237 md_number_to_chars (p
, 0, 4);
16238 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16239 BFD_RELOC_GPREL32
);
16241 demand_empty_rest_of_line ();
16245 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16247 segment_info_type
*si
;
16248 struct insn_label_list
*l
;
16252 /* When not generating PIC code, this is treated as .dword. */
16253 if (mips_pic
!= SVR4_PIC
)
16259 si
= seg_info (now_seg
);
16260 l
= si
->label_list
;
16261 mips_emit_delays ();
16263 mips_align (3, 0, l
);
16266 mips_clear_insn_labels ();
16268 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16270 as_bad (_("unsupported use of .gpdword"));
16271 ignore_rest_of_line ();
16275 md_number_to_chars (p
, 0, 8);
16276 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16277 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16279 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16280 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16281 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16283 demand_empty_rest_of_line ();
16286 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16287 tables. It generates a R_MIPS_EH reloc. */
16290 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16295 mips_emit_delays ();
16298 mips_clear_insn_labels ();
16300 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16302 as_bad (_("unsupported use of .ehword"));
16303 ignore_rest_of_line ();
16307 md_number_to_chars (p
, 0, 4);
16308 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16309 BFD_RELOC_32_PCREL
);
16311 demand_empty_rest_of_line ();
16314 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16315 tables in SVR4 PIC code. */
16318 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16322 file_mips_check_options ();
16324 /* This is ignored when not generating SVR4 PIC code. */
16325 if (mips_pic
!= SVR4_PIC
)
16331 mips_mark_labels ();
16332 mips_assembling_insn
= TRUE
;
16334 /* Add $gp to the register named as an argument. */
16336 reg
= tc_get_register (0);
16337 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16340 mips_assembling_insn
= FALSE
;
16341 demand_empty_rest_of_line ();
16344 /* Handle the .insn pseudo-op. This marks instruction labels in
16345 mips16/micromips mode. This permits the linker to handle them specially,
16346 such as generating jalx instructions when needed. We also make
16347 them odd for the duration of the assembly, in order to generate the
16348 right sort of code. We will make them even in the adjust_symtab
16349 routine, while leaving them marked. This is convenient for the
16350 debugger and the disassembler. The linker knows to make them odd
16354 s_insn (int ignore ATTRIBUTE_UNUSED
)
16356 file_mips_check_options ();
16357 file_ase_mips16
|= mips_opts
.mips16
;
16358 file_ase_micromips
|= mips_opts
.micromips
;
16360 mips_mark_labels ();
16362 demand_empty_rest_of_line ();
16365 /* Handle the .nan pseudo-op. */
16368 s_nan (int ignore ATTRIBUTE_UNUSED
)
16370 static const char str_legacy
[] = "legacy";
16371 static const char str_2008
[] = "2008";
16374 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16376 if (i
== sizeof (str_2008
) - 1
16377 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
16379 else if (i
== sizeof (str_legacy
) - 1
16380 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
16382 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
16385 as_bad (_("`%s' does not support legacy NaN"),
16386 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
16389 as_bad (_("bad .nan directive"));
16391 input_line_pointer
+= i
;
16392 demand_empty_rest_of_line ();
16395 /* Handle a .stab[snd] directive. Ideally these directives would be
16396 implemented in a transparent way, so that removing them would not
16397 have any effect on the generated instructions. However, s_stab
16398 internally changes the section, so in practice we need to decide
16399 now whether the preceding label marks compressed code. We do not
16400 support changing the compression mode of a label after a .stab*
16401 directive, such as in:
16407 so the current mode wins. */
16410 s_mips_stab (int type
)
16412 mips_mark_labels ();
16416 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16419 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16426 name
= input_line_pointer
;
16427 c
= get_symbol_end ();
16428 symbolP
= symbol_find_or_make (name
);
16429 S_SET_WEAK (symbolP
);
16430 *input_line_pointer
= c
;
16432 SKIP_WHITESPACE ();
16434 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16436 if (S_IS_DEFINED (symbolP
))
16438 as_bad (_("ignoring attempt to redefine symbol %s"),
16439 S_GET_NAME (symbolP
));
16440 ignore_rest_of_line ();
16444 if (*input_line_pointer
== ',')
16446 ++input_line_pointer
;
16447 SKIP_WHITESPACE ();
16451 if (exp
.X_op
!= O_symbol
)
16453 as_bad (_("bad .weakext directive"));
16454 ignore_rest_of_line ();
16457 symbol_set_value_expression (symbolP
, &exp
);
16460 demand_empty_rest_of_line ();
16463 /* Parse a register string into a number. Called from the ECOFF code
16464 to parse .frame. The argument is non-zero if this is the frame
16465 register, so that we can record it in mips_frame_reg. */
16468 tc_get_register (int frame
)
16472 SKIP_WHITESPACE ();
16473 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
16477 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
16478 mips_frame_reg_valid
= 1;
16479 mips_cprestore_valid
= 0;
16485 md_section_align (asection
*seg
, valueT addr
)
16487 int align
= bfd_get_section_alignment (stdoutput
, seg
);
16489 /* We don't need to align ELF sections to the full alignment.
16490 However, Irix 5 may prefer that we align them at least to a 16
16491 byte boundary. We don't bother to align the sections if we
16492 are targeted for an embedded system. */
16493 if (strncmp (TARGET_OS
, "elf", 3) == 0)
16498 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
16501 /* Utility routine, called from above as well. If called while the
16502 input file is still being read, it's only an approximation. (For
16503 example, a symbol may later become defined which appeared to be
16504 undefined earlier.) */
16507 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
16512 if (g_switch_value
> 0)
16514 const char *symname
;
16517 /* Find out whether this symbol can be referenced off the $gp
16518 register. It can be if it is smaller than the -G size or if
16519 it is in the .sdata or .sbss section. Certain symbols can
16520 not be referenced off the $gp, although it appears as though
16522 symname
= S_GET_NAME (sym
);
16523 if (symname
!= (const char *) NULL
16524 && (strcmp (symname
, "eprol") == 0
16525 || strcmp (symname
, "etext") == 0
16526 || strcmp (symname
, "_gp") == 0
16527 || strcmp (symname
, "edata") == 0
16528 || strcmp (symname
, "_fbss") == 0
16529 || strcmp (symname
, "_fdata") == 0
16530 || strcmp (symname
, "_ftext") == 0
16531 || strcmp (symname
, "end") == 0
16532 || strcmp (symname
, "_gp_disp") == 0))
16534 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
16536 #ifndef NO_ECOFF_DEBUGGING
16537 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
16538 && (symbol_get_obj (sym
)->ecoff_extern_size
16539 <= g_switch_value
))
16541 /* We must defer this decision until after the whole
16542 file has been read, since there might be a .extern
16543 after the first use of this symbol. */
16544 || (before_relaxing
16545 #ifndef NO_ECOFF_DEBUGGING
16546 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
16548 && S_GET_VALUE (sym
) == 0)
16549 || (S_GET_VALUE (sym
) != 0
16550 && S_GET_VALUE (sym
) <= g_switch_value
)))
16554 const char *segname
;
16556 segname
= segment_name (S_GET_SEGMENT (sym
));
16557 gas_assert (strcmp (segname
, ".lit8") != 0
16558 && strcmp (segname
, ".lit4") != 0);
16559 change
= (strcmp (segname
, ".sdata") != 0
16560 && strcmp (segname
, ".sbss") != 0
16561 && strncmp (segname
, ".sdata.", 7) != 0
16562 && strncmp (segname
, ".sbss.", 6) != 0
16563 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
16564 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
16569 /* We are not optimizing for the $gp register. */
16574 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16577 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16581 /* Handle the case of a symbol equated to another symbol. */
16582 while (symbol_equated_reloc_p (sym
))
16586 /* It's possible to get a loop here in a badly written program. */
16587 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
16593 if (symbol_section_p (sym
))
16596 symsec
= S_GET_SEGMENT (sym
);
16598 /* This must duplicate the test in adjust_reloc_syms. */
16599 return (!bfd_is_und_section (symsec
)
16600 && !bfd_is_abs_section (symsec
)
16601 && !bfd_is_com_section (symsec
)
16602 && !s_is_linkonce (sym
, segtype
)
16603 /* A global or weak symbol is treated as external. */
16604 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
16608 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16609 extended opcode. SEC is the section the frag is in. */
16612 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
16615 const struct mips_int_operand
*operand
;
16620 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16622 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16625 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16626 operand
= mips16_immed_operand (type
, FALSE
);
16628 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
16629 val
= S_GET_VALUE (fragp
->fr_symbol
);
16630 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
16632 if (operand
->root
.type
== OP_PCREL
)
16634 const struct mips_pcrel_operand
*pcrel_op
;
16638 /* We won't have the section when we are called from
16639 mips_relax_frag. However, we will always have been called
16640 from md_estimate_size_before_relax first. If this is a
16641 branch to a different section, we mark it as such. If SEC is
16642 NULL, and the frag is not marked, then it must be a branch to
16643 the same section. */
16644 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16647 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16652 /* Must have been called from md_estimate_size_before_relax. */
16655 fragp
->fr_subtype
=
16656 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16658 /* FIXME: We should support this, and let the linker
16659 catch branches and loads that are out of range. */
16660 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16661 _("unsupported PC relative reference to different section"));
16665 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16666 /* Assume non-extended on the first relaxation pass.
16667 The address we have calculated will be bogus if this is
16668 a forward branch to another frag, as the forward frag
16669 will have fr_address == 0. */
16673 /* In this case, we know for sure that the symbol fragment is in
16674 the same section. If the relax_marker of the symbol fragment
16675 differs from the relax_marker of this fragment, we have not
16676 yet adjusted the symbol fragment fr_address. We want to add
16677 in STRETCH in order to get a better estimate of the address.
16678 This particularly matters because of the shift bits. */
16680 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16684 /* Adjust stretch for any alignment frag. Note that if have
16685 been expanding the earlier code, the symbol may be
16686 defined in what appears to be an earlier frag. FIXME:
16687 This doesn't handle the fr_subtype field, which specifies
16688 a maximum number of bytes to skip when doing an
16690 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16692 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16695 stretch
= - ((- stretch
)
16696 & ~ ((1 << (int) f
->fr_offset
) - 1));
16698 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16707 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16709 /* The base address rules are complicated. The base address of
16710 a branch is the following instruction. The base address of a
16711 PC relative load or add is the instruction itself, but if it
16712 is in a delay slot (in which case it can not be extended) use
16713 the address of the instruction whose delay slot it is in. */
16714 if (pcrel_op
->include_isa_bit
)
16718 /* If we are currently assuming that this frag should be
16719 extended, then, the current address is two bytes
16721 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16724 /* Ignore the low bit in the target, since it will be set
16725 for a text label. */
16728 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16730 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16733 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16735 /* If any of the shifted bits are set, we must use an extended
16736 opcode. If the address depends on the size of this
16737 instruction, this can lead to a loop, so we arrange to always
16738 use an extended opcode. We only check this when we are in
16739 the main relaxation loop, when SEC is NULL. */
16740 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16742 fragp
->fr_subtype
=
16743 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16747 /* If we are about to mark a frag as extended because the value
16748 is precisely the next value above maxtiny, then there is a
16749 chance of an infinite loop as in the following code:
16754 In this case when the la is extended, foo is 0x3fc bytes
16755 away, so the la can be shrunk, but then foo is 0x400 away, so
16756 the la must be extended. To avoid this loop, we mark the
16757 frag as extended if it was small, and is about to become
16758 extended with the next value above maxtiny. */
16759 maxtiny
= mips_int_operand_max (operand
);
16760 if (val
== maxtiny
+ (1 << operand
->shift
)
16761 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16764 fragp
->fr_subtype
=
16765 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16769 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16770 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16772 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16775 /* Compute the length of a branch sequence, and adjust the
16776 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16777 worst-case length is computed, with UPDATE being used to indicate
16778 whether an unconditional (-1), branch-likely (+1) or regular (0)
16779 branch is to be computed. */
16781 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16783 bfd_boolean toofar
;
16787 && S_IS_DEFINED (fragp
->fr_symbol
)
16788 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16793 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16795 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16799 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16802 /* If the symbol is not defined or it's in a different segment,
16803 assume the user knows what's going on and emit a short
16809 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16811 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16812 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16813 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16814 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16820 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16823 if (mips_pic
!= NO_PIC
)
16825 /* Additional space for PIC loading of target address. */
16827 if (mips_opts
.isa
== ISA_MIPS1
)
16828 /* Additional space for $at-stabilizing nop. */
16832 /* If branch is conditional. */
16833 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16840 /* Compute the length of a branch sequence, and adjust the
16841 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16842 worst-case length is computed, with UPDATE being used to indicate
16843 whether an unconditional (-1), or regular (0) branch is to be
16847 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16849 bfd_boolean toofar
;
16853 && S_IS_DEFINED (fragp
->fr_symbol
)
16854 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16859 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16860 /* Ignore the low bit in the target, since it will be set
16861 for a text label. */
16862 if ((val
& 1) != 0)
16865 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16869 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16872 /* If the symbol is not defined or it's in a different segment,
16873 assume the user knows what's going on and emit a short
16879 if (fragp
&& update
16880 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16881 fragp
->fr_subtype
= (toofar
16882 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16883 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16888 bfd_boolean compact_known
= fragp
!= NULL
;
16889 bfd_boolean compact
= FALSE
;
16890 bfd_boolean uncond
;
16893 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16895 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16897 uncond
= update
< 0;
16899 /* If label is out of range, we turn branch <br>:
16901 <br> label # 4 bytes
16907 nop # 2 bytes if compact && !PIC
16910 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16913 /* If assembling PIC code, we further turn:
16919 lw/ld at, %got(label)(gp) # 4 bytes
16920 d/addiu at, %lo(label) # 4 bytes
16923 if (mips_pic
!= NO_PIC
)
16926 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16928 <brneg> 0f # 4 bytes
16929 nop # 2 bytes if !compact
16932 length
+= (compact_known
&& compact
) ? 4 : 6;
16938 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16939 bit accordingly. */
16942 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16944 bfd_boolean toofar
;
16947 && S_IS_DEFINED (fragp
->fr_symbol
)
16948 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16954 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16955 /* Ignore the low bit in the target, since it will be set
16956 for a text label. */
16957 if ((val
& 1) != 0)
16960 /* Assume this is a 2-byte branch. */
16961 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16963 /* We try to avoid the infinite loop by not adding 2 more bytes for
16968 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16970 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16971 else if (type
== 'E')
16972 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16977 /* If the symbol is not defined or it's in a different segment,
16978 we emit a normal 32-bit branch. */
16981 if (fragp
&& update
16982 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16984 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16985 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16993 /* Estimate the size of a frag before relaxing. Unless this is the
16994 mips16, we are not really relaxing here, and the final size is
16995 encoded in the subtype information. For the mips16, we have to
16996 decide whether we are using an extended opcode or not. */
16999 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17003 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17006 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17008 return fragp
->fr_var
;
17011 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17012 /* We don't want to modify the EXTENDED bit here; it might get us
17013 into infinite loops. We change it only in mips_relax_frag(). */
17014 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17016 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17020 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17021 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17022 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17023 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17024 fragp
->fr_var
= length
;
17029 if (mips_pic
== NO_PIC
)
17030 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17031 else if (mips_pic
== SVR4_PIC
)
17032 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17033 else if (mips_pic
== VXWORKS_PIC
)
17034 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17041 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17042 return -RELAX_FIRST (fragp
->fr_subtype
);
17045 return -RELAX_SECOND (fragp
->fr_subtype
);
17048 /* This is called to see whether a reloc against a defined symbol
17049 should be converted into a reloc against a section. */
17052 mips_fix_adjustable (fixS
*fixp
)
17054 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17055 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17058 if (fixp
->fx_addsy
== NULL
)
17061 /* Allow relocs used for EH tables. */
17062 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17065 /* If symbol SYM is in a mergeable section, relocations of the form
17066 SYM + 0 can usually be made section-relative. The mergeable data
17067 is then identified by the section offset rather than by the symbol.
17069 However, if we're generating REL LO16 relocations, the offset is split
17070 between the LO16 and parterning high part relocation. The linker will
17071 need to recalculate the complete offset in order to correctly identify
17074 The linker has traditionally not looked for the parterning high part
17075 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17076 placed anywhere. Rather than break backwards compatibility by changing
17077 this, it seems better not to force the issue, and instead keep the
17078 original symbol. This will work with either linker behavior. */
17079 if ((lo16_reloc_p (fixp
->fx_r_type
)
17080 || reloc_needs_lo_p (fixp
->fx_r_type
))
17081 && HAVE_IN_PLACE_ADDENDS
17082 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17085 /* There is no place to store an in-place offset for JALR relocations.
17086 Likewise an in-range offset of limited PC-relative relocations may
17087 overflow the in-place relocatable field if recalculated against the
17088 start address of the symbol's containing section.
17090 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17091 section relative to allow linker relaxations to be performed later on. */
17092 if ((HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (mips_opts
.isa
))
17093 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17094 || jalr_reloc_p (fixp
->fx_r_type
)))
17097 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17098 to a floating-point stub. The same is true for non-R_MIPS16_26
17099 relocations against MIPS16 functions; in this case, the stub becomes
17100 the function's canonical address.
17102 Floating-point stubs are stored in unique .mips16.call.* or
17103 .mips16.fn.* sections. If a stub T for function F is in section S,
17104 the first relocation in section S must be against F; this is how the
17105 linker determines the target function. All relocations that might
17106 resolve to T must also be against F. We therefore have the following
17107 restrictions, which are given in an intentionally-redundant way:
17109 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17112 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17113 if that stub might be used.
17115 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17118 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17119 that stub might be used.
17121 There is a further restriction:
17123 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17124 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17125 targets with in-place addends; the relocation field cannot
17126 encode the low bit.
17128 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17129 against a MIPS16 symbol. We deal with (5) by by not reducing any
17130 such relocations on REL targets.
17132 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17133 relocation against some symbol R, no relocation against R may be
17134 reduced. (Note that this deals with (2) as well as (1) because
17135 relocations against global symbols will never be reduced on ELF
17136 targets.) This approach is a little simpler than trying to detect
17137 stub sections, and gives the "all or nothing" per-symbol consistency
17138 that we have for MIPS16 symbols. */
17139 if (fixp
->fx_subsy
== NULL
17140 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17141 || *symbol_get_tc (fixp
->fx_addsy
)
17142 || (HAVE_IN_PLACE_ADDENDS
17143 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17144 && jmp_reloc_p (fixp
->fx_r_type
))))
17150 /* Translate internal representation of relocation info to BFD target
17154 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17156 static arelent
*retval
[4];
17158 bfd_reloc_code_real_type code
;
17160 memset (retval
, 0, sizeof(retval
));
17161 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17162 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17163 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17164 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17166 if (fixp
->fx_pcrel
)
17168 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17169 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17170 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17171 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17172 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17173 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17174 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17175 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17176 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17177 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17178 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17180 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17181 Relocations want only the symbol offset. */
17182 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17185 reloc
->addend
= fixp
->fx_addnumber
;
17187 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17188 entry to be used in the relocation's section offset. */
17189 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17191 reloc
->address
= reloc
->addend
;
17195 code
= fixp
->fx_r_type
;
17197 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17198 if (reloc
->howto
== NULL
)
17200 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17201 _("cannot represent %s relocation in this object file"
17203 bfd_get_reloc_code_name (code
));
17210 /* Relax a machine dependent frag. This returns the amount by which
17211 the current size of the frag should change. */
17214 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17216 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17218 offsetT old_var
= fragp
->fr_var
;
17220 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17222 return fragp
->fr_var
- old_var
;
17225 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17227 offsetT old_var
= fragp
->fr_var
;
17228 offsetT new_var
= 4;
17230 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17231 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17232 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17233 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17234 fragp
->fr_var
= new_var
;
17236 return new_var
- old_var
;
17239 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17242 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17244 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17246 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17251 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17253 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17260 /* Convert a machine dependent frag. */
17263 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17265 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17268 unsigned long insn
;
17272 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17273 insn
= read_insn (buf
);
17275 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17277 /* We generate a fixup instead of applying it right now
17278 because, if there are linker relaxations, we're going to
17279 need the relocations. */
17280 exp
.X_op
= O_symbol
;
17281 exp
.X_add_symbol
= fragp
->fr_symbol
;
17282 exp
.X_add_number
= fragp
->fr_offset
;
17284 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17285 BFD_RELOC_16_PCREL_S2
);
17286 fixp
->fx_file
= fragp
->fr_file
;
17287 fixp
->fx_line
= fragp
->fr_line
;
17289 buf
= write_insn (buf
, insn
);
17295 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17296 _("relaxed out-of-range branch into a jump"));
17298 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17301 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17303 /* Reverse the branch. */
17304 switch ((insn
>> 28) & 0xf)
17307 if ((insn
& 0xff000000) == 0x47000000
17308 || (insn
& 0xff600000) == 0x45600000)
17310 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17311 reversed by tweaking bit 23. */
17312 insn
^= 0x00800000;
17316 /* bc[0-3][tf]l? instructions can have the condition
17317 reversed by tweaking a single TF bit, and their
17318 opcodes all have 0x4???????. */
17319 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
17320 insn
^= 0x00010000;
17325 /* bltz 0x04000000 bgez 0x04010000
17326 bltzal 0x04100000 bgezal 0x04110000 */
17327 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17328 insn
^= 0x00010000;
17332 /* beq 0x10000000 bne 0x14000000
17333 blez 0x18000000 bgtz 0x1c000000 */
17334 insn
^= 0x04000000;
17342 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17344 /* Clear the and-link bit. */
17345 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17347 /* bltzal 0x04100000 bgezal 0x04110000
17348 bltzall 0x04120000 bgezall 0x04130000 */
17349 insn
&= ~0x00100000;
17352 /* Branch over the branch (if the branch was likely) or the
17353 full jump (not likely case). Compute the offset from the
17354 current instruction to branch to. */
17355 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17359 /* How many bytes in instructions we've already emitted? */
17360 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17361 /* How many bytes in instructions from here to the end? */
17362 i
= fragp
->fr_var
- i
;
17364 /* Convert to instruction count. */
17366 /* Branch counts from the next instruction. */
17369 /* Branch over the jump. */
17370 buf
= write_insn (buf
, insn
);
17373 buf
= write_insn (buf
, 0);
17375 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17377 /* beql $0, $0, 2f */
17379 /* Compute the PC offset from the current instruction to
17380 the end of the variable frag. */
17381 /* How many bytes in instructions we've already emitted? */
17382 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17383 /* How many bytes in instructions from here to the end? */
17384 i
= fragp
->fr_var
- i
;
17385 /* Convert to instruction count. */
17387 /* Don't decrement i, because we want to branch over the
17391 buf
= write_insn (buf
, insn
);
17392 buf
= write_insn (buf
, 0);
17396 if (mips_pic
== NO_PIC
)
17399 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17400 ? 0x0c000000 : 0x08000000);
17401 exp
.X_op
= O_symbol
;
17402 exp
.X_add_symbol
= fragp
->fr_symbol
;
17403 exp
.X_add_number
= fragp
->fr_offset
;
17405 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17406 FALSE
, BFD_RELOC_MIPS_JMP
);
17407 fixp
->fx_file
= fragp
->fr_file
;
17408 fixp
->fx_line
= fragp
->fr_line
;
17410 buf
= write_insn (buf
, insn
);
17414 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17416 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17417 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17418 insn
|= at
<< OP_SH_RT
;
17419 exp
.X_op
= O_symbol
;
17420 exp
.X_add_symbol
= fragp
->fr_symbol
;
17421 exp
.X_add_number
= fragp
->fr_offset
;
17423 if (fragp
->fr_offset
)
17425 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17426 exp
.X_add_number
= 0;
17429 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17430 FALSE
, BFD_RELOC_MIPS_GOT16
);
17431 fixp
->fx_file
= fragp
->fr_file
;
17432 fixp
->fx_line
= fragp
->fr_line
;
17434 buf
= write_insn (buf
, insn
);
17436 if (mips_opts
.isa
== ISA_MIPS1
)
17438 buf
= write_insn (buf
, 0);
17440 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17441 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
17442 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
17444 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17445 FALSE
, BFD_RELOC_LO16
);
17446 fixp
->fx_file
= fragp
->fr_file
;
17447 fixp
->fx_line
= fragp
->fr_line
;
17449 buf
= write_insn (buf
, insn
);
17452 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17456 insn
|= at
<< OP_SH_RS
;
17458 buf
= write_insn (buf
, insn
);
17462 fragp
->fr_fix
+= fragp
->fr_var
;
17463 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17467 /* Relax microMIPS branches. */
17468 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17470 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17471 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17472 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17473 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17474 bfd_boolean short_ds
;
17475 unsigned long insn
;
17479 exp
.X_op
= O_symbol
;
17480 exp
.X_add_symbol
= fragp
->fr_symbol
;
17481 exp
.X_add_number
= fragp
->fr_offset
;
17483 fragp
->fr_fix
+= fragp
->fr_var
;
17485 /* Handle 16-bit branches that fit or are forced to fit. */
17486 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17488 /* We generate a fixup instead of applying it right now,
17489 because if there is linker relaxation, we're going to
17490 need the relocations. */
17492 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
17493 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
17494 else if (type
== 'E')
17495 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
17496 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
17500 fixp
->fx_file
= fragp
->fr_file
;
17501 fixp
->fx_line
= fragp
->fr_line
;
17503 /* These relocations can have an addend that won't fit in
17505 fixp
->fx_no_overflow
= 1;
17510 /* Handle 32-bit branches that fit or are forced to fit. */
17511 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17512 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17514 /* We generate a fixup instead of applying it right now,
17515 because if there is linker relaxation, we're going to
17516 need the relocations. */
17517 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17518 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17519 fixp
->fx_file
= fragp
->fr_file
;
17520 fixp
->fx_line
= fragp
->fr_line
;
17526 /* Relax 16-bit branches to 32-bit branches. */
17529 insn
= read_compressed_insn (buf
, 2);
17531 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
17532 insn
= 0x94000000; /* beq */
17533 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17535 unsigned long regno
;
17537 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
17538 regno
= micromips_to_32_reg_d_map
[regno
];
17539 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
17540 insn
|= regno
<< MICROMIPSOP_SH_RS
;
17545 /* Nothing else to do, just write it out. */
17546 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17547 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17549 buf
= write_compressed_insn (buf
, insn
, 4);
17550 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17555 insn
= read_compressed_insn (buf
, 4);
17557 /* Relax 32-bit branches to a sequence of instructions. */
17558 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17559 _("relaxed out-of-range branch into a jump"));
17561 /* Set the short-delay-slot bit. */
17562 short_ds
= al
&& (insn
& 0x02000000) != 0;
17564 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
17568 /* Reverse the branch. */
17569 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
17570 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
17571 insn
^= 0x20000000;
17572 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
17573 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
17574 || (insn
& 0xffe00000) == 0x40800000 /* blez */
17575 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
17576 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
17577 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
17578 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
17579 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
17580 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
17581 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
17582 insn
^= 0x00400000;
17583 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
17584 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
17585 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
17586 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
17587 insn
^= 0x00200000;
17588 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
17590 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
17592 insn
^= 0x00800000;
17598 /* Clear the and-link and short-delay-slot bits. */
17599 gas_assert ((insn
& 0xfda00000) == 0x40200000);
17601 /* bltzal 0x40200000 bgezal 0x40600000 */
17602 /* bltzals 0x42200000 bgezals 0x42600000 */
17603 insn
&= ~0x02200000;
17606 /* Make a label at the end for use with the branch. */
17607 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
17608 micromips_label_inc ();
17609 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
17612 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
17613 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17614 fixp
->fx_file
= fragp
->fr_file
;
17615 fixp
->fx_line
= fragp
->fr_line
;
17617 /* Branch over the jump. */
17618 buf
= write_compressed_insn (buf
, insn
, 4);
17621 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17624 if (mips_pic
== NO_PIC
)
17626 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
17628 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17629 insn
= al
? jal
: 0xd4000000;
17631 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17632 BFD_RELOC_MICROMIPS_JMP
);
17633 fixp
->fx_file
= fragp
->fr_file
;
17634 fixp
->fx_line
= fragp
->fr_line
;
17636 buf
= write_compressed_insn (buf
, insn
, 4);
17639 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17643 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
17644 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
17645 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
17647 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17648 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
17649 insn
|= at
<< MICROMIPSOP_SH_RT
;
17651 if (exp
.X_add_number
)
17653 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17654 exp
.X_add_number
= 0;
17657 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17658 BFD_RELOC_MICROMIPS_GOT16
);
17659 fixp
->fx_file
= fragp
->fr_file
;
17660 fixp
->fx_line
= fragp
->fr_line
;
17662 buf
= write_compressed_insn (buf
, insn
, 4);
17664 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17665 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
17666 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
17668 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17669 BFD_RELOC_MICROMIPS_LO16
);
17670 fixp
->fx_file
= fragp
->fr_file
;
17671 fixp
->fx_line
= fragp
->fr_line
;
17673 buf
= write_compressed_insn (buf
, insn
, 4);
17675 /* jr/jrc/jalr/jalrs $at */
17676 insn
= al
? jalr
: jr
;
17677 insn
|= at
<< MICROMIPSOP_SH_MJ
;
17679 buf
= write_compressed_insn (buf
, insn
, 2);
17682 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17686 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17689 const struct mips_int_operand
*operand
;
17692 unsigned int user_length
, length
;
17693 unsigned long insn
;
17696 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17697 operand
= mips16_immed_operand (type
, FALSE
);
17699 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17700 val
= resolve_symbol_value (fragp
->fr_symbol
);
17701 if (operand
->root
.type
== OP_PCREL
)
17703 const struct mips_pcrel_operand
*pcrel_op
;
17706 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17707 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17709 /* The rules for the base address of a PC relative reloc are
17710 complicated; see mips16_extended_frag. */
17711 if (pcrel_op
->include_isa_bit
)
17716 /* Ignore the low bit in the target, since it will be
17717 set for a text label. */
17720 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17722 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17725 addr
&= -(1 << pcrel_op
->align_log2
);
17728 /* Make sure the section winds up with the alignment we have
17730 if (operand
->shift
> 0)
17731 record_alignment (asec
, operand
->shift
);
17735 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17736 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17737 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17738 _("extended instruction in delay slot"));
17740 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17742 insn
= read_compressed_insn (buf
, 2);
17744 insn
|= MIPS16_EXTEND
;
17746 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17748 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17753 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17754 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17756 length
= (ext
? 4 : 2);
17757 gas_assert (mips16_opcode_length (insn
) == length
);
17758 write_compressed_insn (buf
, insn
, length
);
17759 fragp
->fr_fix
+= length
;
17763 relax_substateT subtype
= fragp
->fr_subtype
;
17764 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17765 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17769 first
= RELAX_FIRST (subtype
);
17770 second
= RELAX_SECOND (subtype
);
17771 fixp
= (fixS
*) fragp
->fr_opcode
;
17773 /* If the delay slot chosen does not match the size of the instruction,
17774 then emit a warning. */
17775 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17776 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17781 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17782 | RELAX_DELAY_SLOT_SIZE_FIRST
17783 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17784 msg
= macro_warning (s
);
17786 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17790 /* Possibly emit a warning if we've chosen the longer option. */
17791 if (use_second
== second_longer
)
17797 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17798 msg
= macro_warning (s
);
17800 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17804 /* Go through all the fixups for the first sequence. Disable them
17805 (by marking them as done) if we're going to use the second
17806 sequence instead. */
17808 && fixp
->fx_frag
== fragp
17809 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17811 if (subtype
& RELAX_USE_SECOND
)
17813 fixp
= fixp
->fx_next
;
17816 /* Go through the fixups for the second sequence. Disable them if
17817 we're going to use the first sequence, otherwise adjust their
17818 addresses to account for the relaxation. */
17819 while (fixp
&& fixp
->fx_frag
== fragp
)
17821 if (subtype
& RELAX_USE_SECOND
)
17822 fixp
->fx_where
-= first
;
17825 fixp
= fixp
->fx_next
;
17828 /* Now modify the frag contents. */
17829 if (subtype
& RELAX_USE_SECOND
)
17833 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17834 memmove (start
, start
+ first
, second
);
17835 fragp
->fr_fix
-= first
;
17838 fragp
->fr_fix
-= second
;
17842 /* This function is called after the relocs have been generated.
17843 We've been storing mips16 text labels as odd. Here we convert them
17844 back to even for the convenience of the debugger. */
17847 mips_frob_file_after_relocs (void)
17850 unsigned int count
, i
;
17852 syms
= bfd_get_outsymbols (stdoutput
);
17853 count
= bfd_get_symcount (stdoutput
);
17854 for (i
= 0; i
< count
; i
++, syms
++)
17855 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17856 && ((*syms
)->value
& 1) != 0)
17858 (*syms
)->value
&= ~1;
17859 /* If the symbol has an odd size, it was probably computed
17860 incorrectly, so adjust that as well. */
17861 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17862 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17866 /* This function is called whenever a label is defined, including fake
17867 labels instantiated off the dot special symbol. It is used when
17868 handling branch delays; if a branch has a label, we assume we cannot
17869 move it. This also bumps the value of the symbol by 1 in compressed
17873 mips_record_label (symbolS
*sym
)
17875 segment_info_type
*si
= seg_info (now_seg
);
17876 struct insn_label_list
*l
;
17878 if (free_insn_labels
== NULL
)
17879 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17882 l
= free_insn_labels
;
17883 free_insn_labels
= l
->next
;
17887 l
->next
= si
->label_list
;
17888 si
->label_list
= l
;
17891 /* This function is called as tc_frob_label() whenever a label is defined
17892 and adds a DWARF-2 record we only want for true labels. */
17895 mips_define_label (symbolS
*sym
)
17897 mips_record_label (sym
);
17898 dwarf2_emit_label (sym
);
17901 /* This function is called by tc_new_dot_label whenever a new dot symbol
17905 mips_add_dot_label (symbolS
*sym
)
17907 mips_record_label (sym
);
17908 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17909 mips_compressed_mark_label (sym
);
17912 /* Converting ASE flags from internal to .MIPS.abiflags values. */
17913 static unsigned int
17914 mips_convert_ase_flags (int ase
)
17916 unsigned int ext_ases
= 0;
17919 ext_ases
|= AFL_ASE_DSP
;
17920 if (ase
& ASE_DSPR2
)
17921 ext_ases
|= AFL_ASE_DSPR2
;
17923 ext_ases
|= AFL_ASE_EVA
;
17925 ext_ases
|= AFL_ASE_MCU
;
17926 if (ase
& ASE_MDMX
)
17927 ext_ases
|= AFL_ASE_MDMX
;
17928 if (ase
& ASE_MIPS3D
)
17929 ext_ases
|= AFL_ASE_MIPS3D
;
17931 ext_ases
|= AFL_ASE_MT
;
17932 if (ase
& ASE_SMARTMIPS
)
17933 ext_ases
|= AFL_ASE_SMARTMIPS
;
17934 if (ase
& ASE_VIRT
)
17935 ext_ases
|= AFL_ASE_VIRT
;
17937 ext_ases
|= AFL_ASE_MSA
;
17939 ext_ases
|= AFL_ASE_XPA
;
17943 /* Some special processing for a MIPS ELF file. */
17946 mips_elf_final_processing (void)
17949 Elf_Internal_ABIFlags_v0 flags
;
17953 switch (file_mips_opts
.isa
)
17956 flags
.isa_level
= 1;
17959 flags
.isa_level
= 2;
17962 flags
.isa_level
= 3;
17965 flags
.isa_level
= 4;
17968 flags
.isa_level
= 5;
17971 flags
.isa_level
= 32;
17975 flags
.isa_level
= 32;
17979 flags
.isa_level
= 32;
17983 flags
.isa_level
= 32;
17987 flags
.isa_level
= 32;
17991 flags
.isa_level
= 64;
17995 flags
.isa_level
= 64;
17999 flags
.isa_level
= 64;
18003 flags
.isa_level
= 64;
18007 flags
.isa_level
= 64;
18012 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
18013 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
18014 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
18015 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
18017 flags
.cpr2_size
= AFL_REG_NONE
;
18018 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18019 Tag_GNU_MIPS_ABI_FP
);
18020 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
18021 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
18022 if (file_ase_mips16
)
18023 flags
.ases
|= AFL_ASE_MIPS16
;
18024 if (file_ase_micromips
)
18025 flags
.ases
|= AFL_ASE_MICROMIPS
;
18027 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
18028 || file_mips_opts
.fp
== 64)
18029 && file_mips_opts
.oddspreg
)
18030 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
18033 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
18034 ((Elf_External_ABIFlags_v0
*)
18037 /* Write out the register information. */
18038 if (mips_abi
!= N64_ABI
)
18042 s
.ri_gprmask
= mips_gprmask
;
18043 s
.ri_cprmask
[0] = mips_cprmask
[0];
18044 s
.ri_cprmask
[1] = mips_cprmask
[1];
18045 s
.ri_cprmask
[2] = mips_cprmask
[2];
18046 s
.ri_cprmask
[3] = mips_cprmask
[3];
18047 /* The gp_value field is set by the MIPS ELF backend. */
18049 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18050 ((Elf32_External_RegInfo
*)
18051 mips_regmask_frag
));
18055 Elf64_Internal_RegInfo s
;
18057 s
.ri_gprmask
= mips_gprmask
;
18059 s
.ri_cprmask
[0] = mips_cprmask
[0];
18060 s
.ri_cprmask
[1] = mips_cprmask
[1];
18061 s
.ri_cprmask
[2] = mips_cprmask
[2];
18062 s
.ri_cprmask
[3] = mips_cprmask
[3];
18063 /* The gp_value field is set by the MIPS ELF backend. */
18065 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18066 ((Elf64_External_RegInfo
*)
18067 mips_regmask_frag
));
18070 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18071 sort of BFD interface for this. */
18072 if (mips_any_noreorder
)
18073 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18074 if (mips_pic
!= NO_PIC
)
18076 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18077 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18080 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18082 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18083 defined at present; this might need to change in future. */
18084 if (file_ase_mips16
)
18085 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18086 if (file_ase_micromips
)
18087 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18088 if (file_mips_opts
.ase
& ASE_MDMX
)
18089 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18091 /* Set the MIPS ELF ABI flags. */
18092 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18093 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18094 else if (mips_abi
== O64_ABI
)
18095 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18096 else if (mips_abi
== EABI_ABI
)
18098 if (file_mips_opts
.gp
== 64)
18099 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18101 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18103 else if (mips_abi
== N32_ABI
)
18104 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18106 /* Nothing to do for N64_ABI. */
18108 if (mips_32bitmode
)
18109 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18111 if (mips_nan2008
== 1)
18112 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
18114 /* 32 bit code with 64 bit FP registers. */
18115 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18116 Tag_GNU_MIPS_ABI_FP
);
18117 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
18118 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
18121 typedef struct proc
{
18123 symbolS
*func_end_sym
;
18124 unsigned long reg_mask
;
18125 unsigned long reg_offset
;
18126 unsigned long fpreg_mask
;
18127 unsigned long fpreg_offset
;
18128 unsigned long frame_offset
;
18129 unsigned long frame_reg
;
18130 unsigned long pc_reg
;
18133 static procS cur_proc
;
18134 static procS
*cur_proc_ptr
;
18135 static int numprocs
;
18137 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18138 as "2", and a normal nop as "0". */
18140 #define NOP_OPCODE_MIPS 0
18141 #define NOP_OPCODE_MIPS16 1
18142 #define NOP_OPCODE_MICROMIPS 2
18145 mips_nop_opcode (void)
18147 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18148 return NOP_OPCODE_MICROMIPS
;
18149 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18150 return NOP_OPCODE_MIPS16
;
18152 return NOP_OPCODE_MIPS
;
18155 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18156 32-bit microMIPS NOPs here (if applicable). */
18159 mips_handle_align (fragS
*fragp
)
18163 int bytes
, size
, excess
;
18166 if (fragp
->fr_type
!= rs_align_code
)
18169 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18171 switch (nop_opcode
)
18173 case NOP_OPCODE_MICROMIPS
:
18174 opcode
= micromips_nop32_insn
.insn_opcode
;
18177 case NOP_OPCODE_MIPS16
:
18178 opcode
= mips16_nop_insn
.insn_opcode
;
18181 case NOP_OPCODE_MIPS
:
18183 opcode
= nop_insn
.insn_opcode
;
18188 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18189 excess
= bytes
% size
;
18191 /* Handle the leading part if we're not inserting a whole number of
18192 instructions, and make it the end of the fixed part of the frag.
18193 Try to fit in a short microMIPS NOP if applicable and possible,
18194 and use zeroes otherwise. */
18195 gas_assert (excess
< 4);
18196 fragp
->fr_fix
+= excess
;
18201 /* Fall through. */
18203 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
18205 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18209 /* Fall through. */
18212 /* Fall through. */
18217 md_number_to_chars (p
, opcode
, size
);
18218 fragp
->fr_var
= size
;
18227 if (*input_line_pointer
== '-')
18229 ++input_line_pointer
;
18232 if (!ISDIGIT (*input_line_pointer
))
18233 as_bad (_("expected simple number"));
18234 if (input_line_pointer
[0] == '0')
18236 if (input_line_pointer
[1] == 'x')
18238 input_line_pointer
+= 2;
18239 while (ISXDIGIT (*input_line_pointer
))
18242 val
|= hex_value (*input_line_pointer
++);
18244 return negative
? -val
: val
;
18248 ++input_line_pointer
;
18249 while (ISDIGIT (*input_line_pointer
))
18252 val
|= *input_line_pointer
++ - '0';
18254 return negative
? -val
: val
;
18257 if (!ISDIGIT (*input_line_pointer
))
18259 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18260 *input_line_pointer
, *input_line_pointer
);
18261 as_warn (_("invalid number"));
18264 while (ISDIGIT (*input_line_pointer
))
18267 val
+= *input_line_pointer
++ - '0';
18269 return negative
? -val
: val
;
18272 /* The .file directive; just like the usual .file directive, but there
18273 is an initial number which is the ECOFF file index. In the non-ECOFF
18274 case .file implies DWARF-2. */
18277 s_mips_file (int x ATTRIBUTE_UNUSED
)
18279 static int first_file_directive
= 0;
18281 if (ECOFF_DEBUGGING
)
18290 filename
= dwarf2_directive_file (0);
18292 /* Versions of GCC up to 3.1 start files with a ".file"
18293 directive even for stabs output. Make sure that this
18294 ".file" is handled. Note that you need a version of GCC
18295 after 3.1 in order to support DWARF-2 on MIPS. */
18296 if (filename
!= NULL
&& ! first_file_directive
)
18298 (void) new_logical_line (filename
, -1);
18299 s_app_file_string (filename
, 0);
18301 first_file_directive
= 1;
18305 /* The .loc directive, implying DWARF-2. */
18308 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18310 if (!ECOFF_DEBUGGING
)
18311 dwarf2_directive_loc (0);
18314 /* The .end directive. */
18317 s_mips_end (int x ATTRIBUTE_UNUSED
)
18321 /* Following functions need their own .frame and .cprestore directives. */
18322 mips_frame_reg_valid
= 0;
18323 mips_cprestore_valid
= 0;
18325 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18328 demand_empty_rest_of_line ();
18333 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18334 as_warn (_(".end not in text section"));
18338 as_warn (_(".end directive without a preceding .ent directive"));
18339 demand_empty_rest_of_line ();
18345 gas_assert (S_GET_NAME (p
));
18346 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18347 as_warn (_(".end symbol does not match .ent symbol"));
18349 if (debug_type
== DEBUG_STABS
)
18350 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18354 as_warn (_(".end directive missing or unknown symbol"));
18356 /* Create an expression to calculate the size of the function. */
18357 if (p
&& cur_proc_ptr
)
18359 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18360 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18363 exp
->X_op
= O_subtract
;
18364 exp
->X_add_symbol
= symbol_temp_new_now ();
18365 exp
->X_op_symbol
= p
;
18366 exp
->X_add_number
= 0;
18368 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18371 /* Generate a .pdr section. */
18372 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
18374 segT saved_seg
= now_seg
;
18375 subsegT saved_subseg
= now_subseg
;
18379 #ifdef md_flush_pending_output
18380 md_flush_pending_output ();
18383 gas_assert (pdr_seg
);
18384 subseg_set (pdr_seg
, 0);
18386 /* Write the symbol. */
18387 exp
.X_op
= O_symbol
;
18388 exp
.X_add_symbol
= p
;
18389 exp
.X_add_number
= 0;
18390 emit_expr (&exp
, 4);
18392 fragp
= frag_more (7 * 4);
18394 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18395 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18396 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18397 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18398 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18399 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18400 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18402 subseg_set (saved_seg
, saved_subseg
);
18405 cur_proc_ptr
= NULL
;
18408 /* The .aent and .ent directives. */
18411 s_mips_ent (int aent
)
18415 symbolP
= get_symbol ();
18416 if (*input_line_pointer
== ',')
18417 ++input_line_pointer
;
18418 SKIP_WHITESPACE ();
18419 if (ISDIGIT (*input_line_pointer
)
18420 || *input_line_pointer
== '-')
18423 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18424 as_warn (_(".ent or .aent not in text section"));
18426 if (!aent
&& cur_proc_ptr
)
18427 as_warn (_("missing .end"));
18431 /* This function needs its own .frame and .cprestore directives. */
18432 mips_frame_reg_valid
= 0;
18433 mips_cprestore_valid
= 0;
18435 cur_proc_ptr
= &cur_proc
;
18436 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18438 cur_proc_ptr
->func_sym
= symbolP
;
18442 if (debug_type
== DEBUG_STABS
)
18443 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18444 S_GET_NAME (symbolP
));
18447 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18449 demand_empty_rest_of_line ();
18452 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18453 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18454 s_mips_frame is used so that we can set the PDR information correctly.
18455 We can't use the ecoff routines because they make reference to the ecoff
18456 symbol table (in the mdebug section). */
18459 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18461 if (ECOFF_DEBUGGING
)
18467 if (cur_proc_ptr
== (procS
*) NULL
)
18469 as_warn (_(".frame outside of .ent"));
18470 demand_empty_rest_of_line ();
18474 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18476 SKIP_WHITESPACE ();
18477 if (*input_line_pointer
++ != ','
18478 || get_absolute_expression_and_terminator (&val
) != ',')
18480 as_warn (_("bad .frame directive"));
18481 --input_line_pointer
;
18482 demand_empty_rest_of_line ();
18486 cur_proc_ptr
->frame_offset
= val
;
18487 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18489 demand_empty_rest_of_line ();
18493 /* The .fmask and .mask directives. If the mdebug section is present
18494 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18495 embedded targets, s_mips_mask is used so that we can set the PDR
18496 information correctly. We can't use the ecoff routines because they
18497 make reference to the ecoff symbol table (in the mdebug section). */
18500 s_mips_mask (int reg_type
)
18502 if (ECOFF_DEBUGGING
)
18503 s_ignore (reg_type
);
18508 if (cur_proc_ptr
== (procS
*) NULL
)
18510 as_warn (_(".mask/.fmask outside of .ent"));
18511 demand_empty_rest_of_line ();
18515 if (get_absolute_expression_and_terminator (&mask
) != ',')
18517 as_warn (_("bad .mask/.fmask directive"));
18518 --input_line_pointer
;
18519 demand_empty_rest_of_line ();
18523 off
= get_absolute_expression ();
18525 if (reg_type
== 'F')
18527 cur_proc_ptr
->fpreg_mask
= mask
;
18528 cur_proc_ptr
->fpreg_offset
= off
;
18532 cur_proc_ptr
->reg_mask
= mask
;
18533 cur_proc_ptr
->reg_offset
= off
;
18536 demand_empty_rest_of_line ();
18540 /* A table describing all the processors gas knows about. Names are
18541 matched in the order listed.
18543 To ease comparison, please keep this table in the same order as
18544 gcc's mips_cpu_info_table[]. */
18545 static const struct mips_cpu_info mips_cpu_info_table
[] =
18547 /* Entries for generic ISAs */
18548 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
18549 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
18550 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
18551 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
18552 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
18553 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
18554 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18555 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
18556 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
18557 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
18558 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
18559 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
18560 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
18561 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
18562 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
18565 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
18566 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
18567 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
18570 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
18573 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
18574 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
18575 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
18576 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
18577 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
18578 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
18579 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
18580 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
18581 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
18582 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
18583 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
18584 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
18585 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
18586 /* ST Microelectronics Loongson 2E and 2F cores */
18587 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
18588 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
18591 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
18592 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
18593 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
18594 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
18595 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
18596 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
18597 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
18598 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
18599 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
18600 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
18601 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
18602 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
18603 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
18604 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
18605 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
18608 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18609 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18610 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18611 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
18613 /* MIPS 32 Release 2 */
18614 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18615 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18616 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18617 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18618 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18619 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18620 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18621 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18622 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
18623 ISA_MIPS32R2
, CPU_MIPS32R2
},
18624 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
18625 ISA_MIPS32R2
, CPU_MIPS32R2
},
18626 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18627 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18628 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18629 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18630 /* Deprecated forms of the above. */
18631 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18632 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18633 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18634 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18635 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18636 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18637 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18638 /* Deprecated forms of the above. */
18639 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18640 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18641 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18642 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18643 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18644 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18645 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18646 /* Deprecated forms of the above. */
18647 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18648 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18649 /* 34Kn is a 34kc without DSP. */
18650 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18651 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18652 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18653 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18654 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18655 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18656 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18657 /* Deprecated forms of the above. */
18658 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18659 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18660 /* 1004K cores are multiprocessor versions of the 34K. */
18661 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18662 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18663 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18664 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18665 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
18666 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
18669 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
18670 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
18671 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18672 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18674 /* Broadcom SB-1 CPU core */
18675 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
18676 /* Broadcom SB-1A CPU core */
18677 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
18679 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
18681 /* MIPS 64 Release 2 */
18683 /* Cavium Networks Octeon CPU core */
18684 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
18685 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
18686 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
18687 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
18690 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
18693 XLP is mostly like XLR, with the prominent exception that it is
18694 MIPS64R2 rather than MIPS64. */
18695 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
18698 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
18701 { NULL
, 0, 0, 0, 0 }
18705 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18706 with a final "000" replaced by "k". Ignore case.
18708 Note: this function is shared between GCC and GAS. */
18711 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
18713 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
18714 given
++, canonical
++;
18716 return ((*given
== 0 && *canonical
== 0)
18717 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
18721 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18722 CPU name. We've traditionally allowed a lot of variation here.
18724 Note: this function is shared between GCC and GAS. */
18727 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
18729 /* First see if the name matches exactly, or with a final "000"
18730 turned into "k". */
18731 if (mips_strict_matching_cpu_name_p (canonical
, given
))
18734 /* If not, try comparing based on numerical designation alone.
18735 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18736 if (TOLOWER (*given
) == 'r')
18738 if (!ISDIGIT (*given
))
18741 /* Skip over some well-known prefixes in the canonical name,
18742 hoping to find a number there too. */
18743 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
18745 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
18747 else if (TOLOWER (canonical
[0]) == 'r')
18750 return mips_strict_matching_cpu_name_p (canonical
, given
);
18754 /* Parse an option that takes the name of a processor as its argument.
18755 OPTION is the name of the option and CPU_STRING is the argument.
18756 Return the corresponding processor enumeration if the CPU_STRING is
18757 recognized, otherwise report an error and return null.
18759 A similar function exists in GCC. */
18761 static const struct mips_cpu_info
*
18762 mips_parse_cpu (const char *option
, const char *cpu_string
)
18764 const struct mips_cpu_info
*p
;
18766 /* 'from-abi' selects the most compatible architecture for the given
18767 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18768 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18769 version. Look first at the -mgp options, if given, otherwise base
18770 the choice on MIPS_DEFAULT_64BIT.
18772 Treat NO_ABI like the EABIs. One reason to do this is that the
18773 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18774 architecture. This code picks MIPS I for 'mips' and MIPS III for
18775 'mips64', just as we did in the days before 'from-abi'. */
18776 if (strcasecmp (cpu_string
, "from-abi") == 0)
18778 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
18779 return mips_cpu_info_from_isa (ISA_MIPS1
);
18781 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
18782 return mips_cpu_info_from_isa (ISA_MIPS3
);
18784 if (file_mips_opts
.gp
>= 0)
18785 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
18786 ? ISA_MIPS1
: ISA_MIPS3
);
18788 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18793 /* 'default' has traditionally been a no-op. Probably not very useful. */
18794 if (strcasecmp (cpu_string
, "default") == 0)
18797 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
18798 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
18801 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
18805 /* Return the canonical processor information for ISA (a member of the
18806 ISA_MIPS* enumeration). */
18808 static const struct mips_cpu_info
*
18809 mips_cpu_info_from_isa (int isa
)
18813 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18814 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18815 && isa
== mips_cpu_info_table
[i
].isa
)
18816 return (&mips_cpu_info_table
[i
]);
18821 static const struct mips_cpu_info
*
18822 mips_cpu_info_from_arch (int arch
)
18826 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18827 if (arch
== mips_cpu_info_table
[i
].cpu
)
18828 return (&mips_cpu_info_table
[i
]);
18834 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18838 fprintf (stream
, "%24s", "");
18843 fprintf (stream
, ", ");
18847 if (*col_p
+ strlen (string
) > 72)
18849 fprintf (stream
, "\n%24s", "");
18853 fprintf (stream
, "%s", string
);
18854 *col_p
+= strlen (string
);
18860 md_show_usage (FILE *stream
)
18865 fprintf (stream
, _("\
18867 -EB generate big endian output\n\
18868 -EL generate little endian output\n\
18869 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18870 -G NUM allow referencing objects up to NUM bytes\n\
18871 implicitly with the gp register [default 8]\n"));
18872 fprintf (stream
, _("\
18873 -mips1 generate MIPS ISA I instructions\n\
18874 -mips2 generate MIPS ISA II instructions\n\
18875 -mips3 generate MIPS ISA III instructions\n\
18876 -mips4 generate MIPS ISA IV instructions\n\
18877 -mips5 generate MIPS ISA V instructions\n\
18878 -mips32 generate MIPS32 ISA instructions\n\
18879 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18880 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
18881 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
18882 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
18883 -mips64 generate MIPS64 ISA instructions\n\
18884 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18885 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
18886 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
18887 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
18888 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18892 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18893 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18894 show (stream
, "from-abi", &column
, &first
);
18895 fputc ('\n', stream
);
18897 fprintf (stream
, _("\
18898 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18899 -no-mCPU don't generate code specific to CPU.\n\
18900 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18904 show (stream
, "3900", &column
, &first
);
18905 show (stream
, "4010", &column
, &first
);
18906 show (stream
, "4100", &column
, &first
);
18907 show (stream
, "4650", &column
, &first
);
18908 fputc ('\n', stream
);
18910 fprintf (stream
, _("\
18911 -mips16 generate mips16 instructions\n\
18912 -no-mips16 do not generate mips16 instructions\n"));
18913 fprintf (stream
, _("\
18914 -mmicromips generate microMIPS instructions\n\
18915 -mno-micromips do not generate microMIPS instructions\n"));
18916 fprintf (stream
, _("\
18917 -msmartmips generate smartmips instructions\n\
18918 -mno-smartmips do not generate smartmips instructions\n"));
18919 fprintf (stream
, _("\
18920 -mdsp generate DSP instructions\n\
18921 -mno-dsp do not generate DSP instructions\n"));
18922 fprintf (stream
, _("\
18923 -mdspr2 generate DSP R2 instructions\n\
18924 -mno-dspr2 do not generate DSP R2 instructions\n"));
18925 fprintf (stream
, _("\
18926 -mmt generate MT instructions\n\
18927 -mno-mt do not generate MT instructions\n"));
18928 fprintf (stream
, _("\
18929 -mmcu generate MCU instructions\n\
18930 -mno-mcu do not generate MCU instructions\n"));
18931 fprintf (stream
, _("\
18932 -mmsa generate MSA instructions\n\
18933 -mno-msa do not generate MSA instructions\n"));
18934 fprintf (stream
, _("\
18935 -mxpa generate eXtended Physical Address (XPA) instructions\n\
18936 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
18937 fprintf (stream
, _("\
18938 -mvirt generate Virtualization instructions\n\
18939 -mno-virt do not generate Virtualization instructions\n"));
18940 fprintf (stream
, _("\
18941 -minsn32 only generate 32-bit microMIPS instructions\n\
18942 -mno-insn32 generate all microMIPS instructions\n"));
18943 fprintf (stream
, _("\
18944 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18945 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18946 -mfix-vr4120 work around certain VR4120 errata\n\
18947 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18948 -mfix-24k insert a nop after ERET and DERET instructions\n\
18949 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18950 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18951 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18952 -msym32 assume all symbols have 32-bit values\n\
18953 -O0 remove unneeded NOPs, do not swap branches\n\
18954 -O remove unneeded NOPs and swap branches\n\
18955 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18956 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18957 fprintf (stream
, _("\
18958 -mhard-float allow floating-point instructions\n\
18959 -msoft-float do not allow floating-point instructions\n\
18960 -msingle-float only allow 32-bit floating-point operations\n\
18961 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18962 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18963 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18964 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18968 show (stream
, "legacy", &column
, &first
);
18969 show (stream
, "2008", &column
, &first
);
18971 fputc ('\n', stream
);
18973 fprintf (stream
, _("\
18974 -KPIC, -call_shared generate SVR4 position independent code\n\
18975 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18976 -mvxworks-pic generate VxWorks position independent code\n\
18977 -non_shared do not generate code that can operate with DSOs\n\
18978 -xgot assume a 32 bit GOT\n\
18979 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18980 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18981 position dependent (non shared) code\n\
18982 -mabi=ABI create ABI conformant object file for:\n"));
18986 show (stream
, "32", &column
, &first
);
18987 show (stream
, "o64", &column
, &first
);
18988 show (stream
, "n32", &column
, &first
);
18989 show (stream
, "64", &column
, &first
);
18990 show (stream
, "eabi", &column
, &first
);
18992 fputc ('\n', stream
);
18994 fprintf (stream
, _("\
18995 -32 create o32 ABI object file (default)\n\
18996 -n32 create n32 ABI object file\n\
18997 -64 create 64 ABI object file\n"));
19002 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19004 if (HAVE_64BIT_SYMBOLS
)
19005 return dwarf2_format_64bit_irix
;
19007 return dwarf2_format_32bit
;
19012 mips_dwarf2_addr_size (void)
19014 if (HAVE_64BIT_OBJECTS
)
19020 /* Standard calling conventions leave the CFA at SP on entry. */
19022 mips_cfi_frame_initial_instructions (void)
19024 cfi_add_CFA_def_cfa_register (SP
);
19028 tc_mips_regname_to_dw2regnum (char *regname
)
19030 unsigned int regnum
= -1;
19033 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
19039 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19040 Given a symbolic attribute NAME, return the proper integer value.
19041 Returns -1 if the attribute is not known. */
19044 mips_convert_symbolic_attribute (const char *name
)
19046 static const struct
19051 attribute_table
[] =
19053 #define T(tag) {#tag, tag}
19054 T (Tag_GNU_MIPS_ABI_FP
),
19055 T (Tag_GNU_MIPS_ABI_MSA
),
19063 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
19064 if (streq (name
, attribute_table
[i
].name
))
19065 return attribute_table
[i
].tag
;
19073 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
19075 mips_emit_delays ();
19077 as_warn (_("missing .end at end of assembly"));
19079 /* Just in case no code was emitted, do the consistency check. */
19080 file_mips_check_options ();
19082 /* Set a floating-point ABI if the user did not. */
19083 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
19085 /* Perform consistency checks on the floating-point ABI. */
19086 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19087 Tag_GNU_MIPS_ABI_FP
);
19088 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
19089 check_fpabi (fpabi
);
19093 /* Soft-float gets precedence over single-float, the two options should
19094 not be used together so this should not matter. */
19095 if (file_mips_opts
.soft_float
== 1)
19096 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
19097 /* Single-float gets precedence over all double_float cases. */
19098 else if (file_mips_opts
.single_float
== 1)
19099 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
19102 switch (file_mips_opts
.fp
)
19105 if (file_mips_opts
.gp
== 32)
19106 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19109 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
19112 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
19113 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
19114 else if (file_mips_opts
.gp
== 32)
19115 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
19117 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19122 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19123 Tag_GNU_MIPS_ABI_FP
, fpabi
);
19127 /* Returns the relocation type required for a particular CFI encoding. */
19129 bfd_reloc_code_real_type
19130 mips_cfi_reloc_for_encoding (int encoding
)
19132 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
19133 return BFD_RELOC_32_PCREL
;
19134 else return BFD_RELOC_NONE
;