1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 #include "opcode/mips.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
115 mips_target_format ()
117 switch (OUTPUT_FLAVOR
)
119 case bfd_target_aout_flavour
:
120 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
121 case bfd_target_ecoff_flavour
:
122 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
123 case bfd_target_coff_flavour
:
125 case bfd_target_elf_flavour
:
127 /* This is traditional mips */
128 return (target_big_endian
129 ? (mips_64
? "elf64-tradbigmips" : "elf32-tradbigmips")
130 : (mips_64
? "elf64-tradlittlemips" : "elf32-tradlittlemips"));
132 return (target_big_endian
133 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
134 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
142 /* The name of the readonly data section. */
143 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
145 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
147 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
149 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
153 /* This is the set of options which may be modified by the .set
154 pseudo-op. We use a struct so that .set push and .set pop are more
157 struct mips_set_options
159 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
160 if it has not been initialized. Changed by `.set mipsN', and the
161 -mipsN command line option, and the default CPU. */
163 /* Whether we are assembling for the mips16 processor. 0 if we are
164 not, 1 if we are, and -1 if the value has not been initialized.
165 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
166 -nomips16 command line options, and the default CPU. */
168 /* Non-zero if we should not reorder instructions. Changed by `.set
169 reorder' and `.set noreorder'. */
171 /* Non-zero if we should not permit the $at ($1) register to be used
172 in instructions. Changed by `.set at' and `.set noat'. */
174 /* Non-zero if we should warn when a macro instruction expands into
175 more than one machine instruction. Changed by `.set nomacro' and
177 int warn_about_macros
;
178 /* Non-zero if we should not move instructions. Changed by `.set
179 move', `.set volatile', `.set nomove', and `.set novolatile'. */
181 /* Non-zero if we should not optimize branches by moving the target
182 of the branch into the delay slot. Actually, we don't perform
183 this optimization anyhow. Changed by `.set bopt' and `.set
186 /* Non-zero if we should not autoextend mips16 instructions.
187 Changed by `.set autoextend' and `.set noautoextend'. */
191 /* This is the struct we use to hold the current set of options. Note
192 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
193 -1 to indicate that they have not been initialized. */
195 static struct mips_set_options mips_opts
=
197 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0
200 /* These variables are filled in with the masks of registers used.
201 The object format code reads them and puts them in the appropriate
203 unsigned long mips_gprmask
;
204 unsigned long mips_cprmask
[4];
206 /* MIPS ISA we are using for this output file. */
207 static int file_mips_isa
= ISA_UNKNOWN
;
209 /* The CPU type we are using for this output file. */
210 static int mips_cpu
= CPU_UNKNOWN
;
212 /* The argument of the -mabi= flag. */
213 static char * mips_abi_string
= 0;
215 /* Wether we should mark the file EABI64 or EABI32. */
216 static int mips_eabi64
= 0;
218 /* If they asked for mips1 or mips2 and a cpu that is
219 mips3 or greater, then mark the object file 32BITMODE. */
220 static int mips_32bitmode
= 0;
222 /* True if -mgp32 was passed. */
223 static int mips_gp32
= 0;
225 /* Some ISA's have delay slots for instructions which read or write
226 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
227 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
228 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
229 delay slot in this ISA. The uses of this macro assume that any
230 ISA that has delay slots for one of these, has them for all. They
231 also assume that ISAs which don't have delays for these insns, don't
232 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
233 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
235 || (ISA) == ISA_MIPS2 \
236 || (ISA) == ISA_MIPS3 \
239 /* Return true if ISA supports 64 bit gp register instructions. */
240 #define ISA_HAS_64BIT_REGS(ISA) ( \
242 || (ISA) == ISA_MIPS4 \
243 || (ISA) == ISA_MIPS5 \
244 || (ISA) == ISA_MIPS32 \
247 /* Whether the processor uses hardware interlocks to protect
248 reads from the HI and LO registers, and thus does not
249 require nops to be inserted.
251 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
252 -mcpu=FOO schedules for FOO, but still produces code that meets the
253 requirements of MIPS ISA I. For example, it won't generate any
254 FOO-specific instructions, and it will still assume that any
255 scheduling hazards described in MIPS ISA I are there, even if FOO
256 has interlocks. -mFOO gives GCC permission to generate code that
257 will only run on a FOO; it will generate FOO-specific instructions,
258 and assume interlocks provided by a FOO.
260 However, GAS currently doesn't make this distinction; before Jan 28
261 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
262 assumptions. The GCC driver passes these flags through to GAS, so
263 if GAS actually does anything that doesn't meet MIPS ISA I with
264 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
266 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
267 which seems senseless --- why generate code which will only run on
268 a FOO, but schedule for something else?
270 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
272 -- Jim Blandy <jimb@cygnus.com> */
274 #define hilo_interlocks (mips_cpu == CPU_R4010 \
277 /* Whether the processor uses hardware interlocks to protect reads
278 from the GPRs, and thus does not require nops to be inserted. */
279 #define gpr_interlocks \
280 (mips_opts.isa != ISA_MIPS1 \
281 || mips_cpu == CPU_R3900)
283 /* As with other "interlocks" this is used by hardware that has FP
284 (co-processor) interlocks. */
285 /* Itbl support may require additional care here. */
286 #define cop_interlocks (mips_cpu == CPU_R4300 \
289 /* Is this a mfhi or mflo instruction? */
290 #define MF_HILO_INSN(PINFO) \
291 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
293 /* MIPS PIC level. */
297 /* Do not generate PIC code. */
300 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
301 not sure what it is supposed to do. */
304 /* Generate PIC code as in the SVR4 MIPS ABI. */
307 /* Generate PIC code without using a global offset table: the data
308 segment has a maximum size of 64K, all data references are off
309 the $gp register, and all text references are PC relative. This
310 is used on some embedded systems. */
314 static enum mips_pic_level mips_pic
;
316 /* 1 if we should generate 32 bit offsets from the GP register in
317 SVR4_PIC mode. Currently has no meaning in other modes. */
318 static int mips_big_got
;
320 /* 1 if trap instructions should used for overflow rather than break
322 static int mips_trap
;
324 /* 1 if double width floating point constants should not be constructed
325 by a assembling two single width halves into two single width floating
326 point registers which just happen to alias the double width destination
327 register. On some architectures this aliasing can be disabled by a bit
328 in the status register, and the setting of this bit cannot be determined
329 automatically at assemble time. */
330 static int mips_disable_float_construction
;
332 /* Non-zero if any .set noreorder directives were used. */
334 static int mips_any_noreorder
;
336 /* Non-zero if nops should be inserted when the register referenced in
337 an mfhi/mflo instruction is read in the next two instructions. */
338 static int mips_7000_hilo_fix
;
340 /* The size of the small data section. */
341 static unsigned int g_switch_value
= 8;
342 /* Whether the -G option was used. */
343 static int g_switch_seen
= 0;
348 /* If we can determine in advance that GP optimization won't be
349 possible, we can skip the relaxation stuff that tries to produce
350 GP-relative references. This makes delay slot optimization work
353 This function can only provide a guess, but it seems to work for
354 gcc output. It needs to guess right for gcc, otherwise gcc
355 will put what it thinks is a GP-relative instruction in a branch
358 I don't know if a fix is needed for the SVR4_PIC mode. I've only
359 fixed it for the non-PIC mode. KR 95/04/07 */
360 static int nopic_need_relax
PARAMS ((symbolS
*, int));
362 /* handle of the OPCODE hash table */
363 static struct hash_control
*op_hash
= NULL
;
365 /* The opcode hash table we use for the mips16. */
366 static struct hash_control
*mips16_op_hash
= NULL
;
368 /* This array holds the chars that always start a comment. If the
369 pre-processor is disabled, these aren't very useful */
370 const char comment_chars
[] = "#";
372 /* This array holds the chars that only start a comment at the beginning of
373 a line. If the line seems to have the form '# 123 filename'
374 .line and .file directives will appear in the pre-processed output */
375 /* Note that input_file.c hand checks for '#' at the beginning of the
376 first line of the input file. This is because the compiler outputs
377 #NO_APP at the beginning of its output. */
378 /* Also note that C style comments are always supported. */
379 const char line_comment_chars
[] = "#";
381 /* This array holds machine specific line separator characters. */
382 const char line_separator_chars
[] = ";";
384 /* Chars that can be used to separate mant from exp in floating point nums */
385 const char EXP_CHARS
[] = "eE";
387 /* Chars that mean this number is a floating point constant */
390 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
392 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
393 changed in read.c . Ideally it shouldn't have to know about it at all,
394 but nothing is ideal around here.
397 static char *insn_error
;
399 static int auto_align
= 1;
401 /* When outputting SVR4 PIC code, the assembler needs to know the
402 offset in the stack frame from which to restore the $gp register.
403 This is set by the .cprestore pseudo-op, and saved in this
405 static offsetT mips_cprestore_offset
= -1;
407 /* This is the register which holds the stack frame, as set by the
408 .frame pseudo-op. This is needed to implement .cprestore. */
409 static int mips_frame_reg
= SP
;
411 /* To output NOP instructions correctly, we need to keep information
412 about the previous two instructions. */
414 /* Whether we are optimizing. The default value of 2 means to remove
415 unneeded NOPs and swap branch instructions when possible. A value
416 of 1 means to not swap branches. A value of 0 means to always
418 static int mips_optimize
= 2;
420 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
421 equivalent to seeing no -g option at all. */
422 static int mips_debug
= 0;
424 /* The previous instruction. */
425 static struct mips_cl_insn prev_insn
;
427 /* The instruction before prev_insn. */
428 static struct mips_cl_insn prev_prev_insn
;
430 /* If we don't want information for prev_insn or prev_prev_insn, we
431 point the insn_mo field at this dummy integer. */
432 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
434 /* Non-zero if prev_insn is valid. */
435 static int prev_insn_valid
;
437 /* The frag for the previous instruction. */
438 static struct frag
*prev_insn_frag
;
440 /* The offset into prev_insn_frag for the previous instruction. */
441 static long prev_insn_where
;
443 /* The reloc type for the previous instruction, if any. */
444 static bfd_reloc_code_real_type prev_insn_reloc_type
;
446 /* The reloc for the previous instruction, if any. */
447 static fixS
*prev_insn_fixp
;
449 /* Non-zero if the previous instruction was in a delay slot. */
450 static int prev_insn_is_delay_slot
;
452 /* Non-zero if the previous instruction was in a .set noreorder. */
453 static int prev_insn_unreordered
;
455 /* Non-zero if the previous instruction uses an extend opcode (if
457 static int prev_insn_extended
;
459 /* Non-zero if the previous previous instruction was in a .set
461 static int prev_prev_insn_unreordered
;
463 /* If this is set, it points to a frag holding nop instructions which
464 were inserted before the start of a noreorder section. If those
465 nops turn out to be unnecessary, the size of the frag can be
467 static fragS
*prev_nop_frag
;
469 /* The number of nop instructions we created in prev_nop_frag. */
470 static int prev_nop_frag_holds
;
472 /* The number of nop instructions that we know we need in
474 static int prev_nop_frag_required
;
476 /* The number of instructions we've seen since prev_nop_frag. */
477 static int prev_nop_frag_since
;
479 /* For ECOFF and ELF, relocations against symbols are done in two
480 parts, with a HI relocation and a LO relocation. Each relocation
481 has only 16 bits of space to store an addend. This means that in
482 order for the linker to handle carries correctly, it must be able
483 to locate both the HI and the LO relocation. This means that the
484 relocations must appear in order in the relocation table.
486 In order to implement this, we keep track of each unmatched HI
487 relocation. We then sort them so that they immediately precede the
488 corresponding LO relocation. */
493 struct mips_hi_fixup
*next
;
496 /* The section this fixup is in. */
500 /* The list of unmatched HI relocs. */
502 static struct mips_hi_fixup
*mips_hi_fixup_list
;
504 /* Map normal MIPS register numbers to mips16 register numbers. */
506 #define X ILLEGAL_REG
507 static const int mips32_to_16_reg_map
[] =
509 X
, X
, 2, 3, 4, 5, 6, 7,
510 X
, X
, X
, X
, X
, X
, X
, X
,
511 0, 1, X
, X
, X
, X
, X
, X
,
512 X
, X
, X
, X
, X
, X
, X
, X
516 /* Map mips16 register numbers to normal MIPS register numbers. */
518 static const unsigned int mips16_to_32_reg_map
[] =
520 16, 17, 2, 3, 4, 5, 6, 7
523 /* Since the MIPS does not have multiple forms of PC relative
524 instructions, we do not have to do relaxing as is done on other
525 platforms. However, we do have to handle GP relative addressing
526 correctly, which turns out to be a similar problem.
528 Every macro that refers to a symbol can occur in (at least) two
529 forms, one with GP relative addressing and one without. For
530 example, loading a global variable into a register generally uses
531 a macro instruction like this:
533 If i can be addressed off the GP register (this is true if it is in
534 the .sbss or .sdata section, or if it is known to be smaller than
535 the -G argument) this will generate the following instruction:
537 This instruction will use a GPREL reloc. If i can not be addressed
538 off the GP register, the following instruction sequence will be used:
541 In this case the first instruction will have a HI16 reloc, and the
542 second reloc will have a LO16 reloc. Both relocs will be against
545 The issue here is that we may not know whether i is GP addressable
546 until after we see the instruction that uses it. Therefore, we
547 want to be able to choose the final instruction sequence only at
548 the end of the assembly. This is similar to the way other
549 platforms choose the size of a PC relative instruction only at the
552 When generating position independent code we do not use GP
553 addressing in quite the same way, but the issue still arises as
554 external symbols and local symbols must be handled differently.
556 We handle these issues by actually generating both possible
557 instruction sequences. The longer one is put in a frag_var with
558 type rs_machine_dependent. We encode what to do with the frag in
559 the subtype field. We encode (1) the number of existing bytes to
560 replace, (2) the number of new bytes to use, (3) the offset from
561 the start of the existing bytes to the first reloc we must generate
562 (that is, the offset is applied from the start of the existing
563 bytes after they are replaced by the new bytes, if any), (4) the
564 offset from the start of the existing bytes to the second reloc,
565 (5) whether a third reloc is needed (the third reloc is always four
566 bytes after the second reloc), and (6) whether to warn if this
567 variant is used (this is sometimes needed if .set nomacro or .set
568 noat is in effect). All these numbers are reasonably small.
570 Generating two instruction sequences must be handled carefully to
571 ensure that delay slots are handled correctly. Fortunately, there
572 are a limited number of cases. When the second instruction
573 sequence is generated, append_insn is directed to maintain the
574 existing delay slot information, so it continues to apply to any
575 code after the second instruction sequence. This means that the
576 second instruction sequence must not impose any requirements not
577 required by the first instruction sequence.
579 These variant frags are then handled in functions called by the
580 machine independent code. md_estimate_size_before_relax returns
581 the final size of the frag. md_convert_frag sets up the final form
582 of the frag. tc_gen_reloc adjust the first reloc and adds a second
584 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
588 | (((reloc1) + 64) << 9) \
589 | (((reloc2) + 64) << 2) \
590 | ((reloc3) ? (1 << 1) : 0) \
592 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
593 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
594 #define RELAX_RELOC1(i) ((bfd_vma) (((i) >> 9) & 0x7f) - 64)
595 #define RELAX_RELOC2(i) ((bfd_vma) (((i) >> 2) & 0x7f) - 64)
596 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
597 #define RELAX_WARN(i) ((i) & 1)
599 /* For mips16 code, we use an entirely different form of relaxation.
600 mips16 supports two versions of most instructions which take
601 immediate values: a small one which takes some small value, and a
602 larger one which takes a 16 bit value. Since branches also follow
603 this pattern, relaxing these values is required.
605 We can assemble both mips16 and normal MIPS code in a single
606 object. Therefore, we need to support this type of relaxation at
607 the same time that we support the relaxation described above. We
608 use the high bit of the subtype field to distinguish these cases.
610 The information we store for this type of relaxation is the
611 argument code found in the opcode file for this relocation, whether
612 the user explicitly requested a small or extended form, and whether
613 the relocation is in a jump or jal delay slot. That tells us the
614 size of the value, and how it should be stored. We also store
615 whether the fragment is considered to be extended or not. We also
616 store whether this is known to be a branch to a different section,
617 whether we have tried to relax this frag yet, and whether we have
618 ever extended a PC relative fragment because of a shift count. */
619 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
622 | ((small) ? 0x100 : 0) \
623 | ((ext) ? 0x200 : 0) \
624 | ((dslot) ? 0x400 : 0) \
625 | ((jal_dslot) ? 0x800 : 0))
626 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
627 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
628 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
629 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
630 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
631 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
632 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
633 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
634 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
635 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
636 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
637 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
639 /* Prototypes for static functions. */
642 #define internalError() \
643 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
645 #define internalError() as_fatal (_("MIPS internal Error"));
648 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
650 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
651 unsigned int reg
, enum mips_regclass
class));
652 static int reg_needs_delay
PARAMS ((unsigned int));
653 static void mips16_mark_labels
PARAMS ((void));
654 static void append_insn
PARAMS ((char *place
,
655 struct mips_cl_insn
* ip
,
657 bfd_reloc_code_real_type r
,
659 static void mips_no_prev_insn
PARAMS ((int));
660 static void mips_emit_delays
PARAMS ((boolean
));
662 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
663 const char *name
, const char *fmt
,
666 static void macro_build ();
668 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
669 const char *, const char *,
671 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
672 expressionS
* ep
, int regnum
));
673 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
674 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
676 static void load_register
PARAMS ((int *, int, expressionS
*, int));
677 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
678 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
679 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
680 #ifdef LOSING_COMPILER
681 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
683 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
684 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
685 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
686 boolean
, boolean
, unsigned long *,
687 boolean
*, unsigned short *));
688 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
689 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
690 static symbolS
*get_symbol
PARAMS ((void));
691 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
692 static void s_align
PARAMS ((int));
693 static void s_change_sec
PARAMS ((int));
694 static void s_cons
PARAMS ((int));
695 static void s_float_cons
PARAMS ((int));
696 static void s_mips_globl
PARAMS ((int));
697 static void s_option
PARAMS ((int));
698 static void s_mipsset
PARAMS ((int));
699 static void s_abicalls
PARAMS ((int));
700 static void s_cpload
PARAMS ((int));
701 static void s_cprestore
PARAMS ((int));
702 static void s_gpword
PARAMS ((int));
703 static void s_cpadd
PARAMS ((int));
704 static void s_insn
PARAMS ((int));
705 static void md_obj_begin
PARAMS ((void));
706 static void md_obj_end
PARAMS ((void));
707 static long get_number
PARAMS ((void));
708 static void s_mips_ent
PARAMS ((int));
709 static void s_mips_end
PARAMS ((int));
710 static void s_mips_frame
PARAMS ((int));
711 static void s_mips_mask
PARAMS ((int));
712 static void s_mips_stab
PARAMS ((int));
713 static void s_mips_weakext
PARAMS ((int));
714 static void s_file
PARAMS ((int));
715 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
716 static const char *mips_isa_to_str
PARAMS ((int));
717 static const char *mips_cpu_to_str
PARAMS ((int));
718 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
720 /* Table and functions used to map between CPU/ISA names, and
721 ISA levels, and CPU numbers. */
725 const char *name
; /* CPU or ISA name. */
726 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
727 int isa
; /* ISA level. */
728 int cpu
; /* CPU number (default CPU if ISA). */
731 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
732 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
733 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
737 The following pseudo-ops from the Kane and Heinrich MIPS book
738 should be defined here, but are currently unsupported: .alias,
739 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
741 The following pseudo-ops from the Kane and Heinrich MIPS book are
742 specific to the type of debugging information being generated, and
743 should be defined by the object format: .aent, .begin, .bend,
744 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
747 The following pseudo-ops from the Kane and Heinrich MIPS book are
748 not MIPS CPU specific, but are also not specific to the object file
749 format. This file is probably the best place to define them, but
750 they are not currently supported: .asm0, .endr, .lab, .repeat,
753 static const pseudo_typeS mips_pseudo_table
[] =
755 /* MIPS specific pseudo-ops. */
756 {"option", s_option
, 0},
757 {"set", s_mipsset
, 0},
758 {"rdata", s_change_sec
, 'r'},
759 {"sdata", s_change_sec
, 's'},
760 {"livereg", s_ignore
, 0},
761 {"abicalls", s_abicalls
, 0},
762 {"cpload", s_cpload
, 0},
763 {"cprestore", s_cprestore
, 0},
764 {"gpword", s_gpword
, 0},
765 {"cpadd", s_cpadd
, 0},
768 /* Relatively generic pseudo-ops that happen to be used on MIPS
770 {"asciiz", stringer
, 1},
771 {"bss", s_change_sec
, 'b'},
774 {"dword", s_cons
, 3},
775 {"weakext", s_mips_weakext
, 0},
777 /* These pseudo-ops are defined in read.c, but must be overridden
778 here for one reason or another. */
779 {"align", s_align
, 0},
781 {"data", s_change_sec
, 'd'},
782 {"double", s_float_cons
, 'd'},
783 {"float", s_float_cons
, 'f'},
784 {"globl", s_mips_globl
, 0},
785 {"global", s_mips_globl
, 0},
786 {"hword", s_cons
, 1},
791 {"short", s_cons
, 1},
792 {"single", s_float_cons
, 'f'},
793 {"stabn", s_mips_stab
, 'n'},
794 {"text", s_change_sec
, 't'},
799 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
801 /* These pseudo-ops should be defined by the object file format.
802 However, a.out doesn't support them, so we have versions here. */
803 {"aent", s_mips_ent
, 1},
804 {"bgnb", s_ignore
, 0},
805 {"end", s_mips_end
, 0},
806 {"endb", s_ignore
, 0},
807 {"ent", s_mips_ent
, 0},
809 {"fmask", s_mips_mask
, 'F'},
810 {"frame", s_mips_frame
, 0},
811 {"loc", s_ignore
, 0},
812 {"mask", s_mips_mask
, 'R'},
813 {"verstamp", s_ignore
, 0},
817 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
822 pop_insert (mips_pseudo_table
);
823 if (! ECOFF_DEBUGGING
)
824 pop_insert (mips_nonecoff_pseudo_table
);
827 /* Symbols labelling the current insn. */
829 struct insn_label_list
831 struct insn_label_list
*next
;
835 static struct insn_label_list
*insn_labels
;
836 static struct insn_label_list
*free_insn_labels
;
838 static void mips_clear_insn_labels
PARAMS ((void));
841 mips_clear_insn_labels ()
843 register struct insn_label_list
**pl
;
845 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
851 static char *expr_end
;
853 /* Expressions which appear in instructions. These are set by
856 static expressionS imm_expr
;
857 static expressionS offset_expr
;
859 /* Relocs associated with imm_expr and offset_expr. */
861 static bfd_reloc_code_real_type imm_reloc
;
862 static bfd_reloc_code_real_type offset_reloc
;
864 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
866 static boolean imm_unmatched_hi
;
868 /* These are set by mips16_ip if an explicit extension is used. */
870 static boolean mips16_small
, mips16_ext
;
872 #ifdef MIPS_STABS_ELF
873 /* The pdr segment for per procedure frame/regmask info */
879 mips_isa_to_str (isa
)
882 const struct mips_cpu_info
*ci
;
885 ci
= mips_cpu_info_from_isa (isa
);
889 sprintf (s
, "ISA#%d", isa
);
894 mips_cpu_to_str (cpu
)
897 const struct mips_cpu_info
*ci
;
900 ci
= mips_cpu_info_from_cpu (cpu
);
904 sprintf (s
, "CPU#%d", cpu
);
908 /* This function is called once, at assembler startup time. It should
909 set up all the tables, etc. that the MD part of the assembler will need. */
914 register const char *retval
= NULL
;
919 int mips_isa_from_cpu
;
920 int target_cpu_had_mips16
= 0;
921 const struct mips_cpu_info
*ci
;
923 /* GP relative stuff not working for PE */
924 if (strncmp (TARGET_OS
, "pe", 2) == 0
925 && g_switch_value
!= 0)
928 as_bad (_("-G not supported in this configuration."));
933 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
935 a
= xmalloc (sizeof TARGET_CPU
);
936 strcpy (a
, TARGET_CPU
);
937 a
[(sizeof TARGET_CPU
) - 3] = '\0';
941 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
943 target_cpu_had_mips16
= 1;
944 cpu
+= sizeof "mips16" - 1;
947 if (mips_opts
.mips16
< 0)
948 mips_opts
.mips16
= target_cpu_had_mips16
;
950 /* At this point, mips_cpu will either be CPU_UNKNOWN if no CPU was
951 specified on the command line, or some other value if one was.
952 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
953 the command line, or will be set otherwise if one was. */
954 if (mips_cpu
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
956 /* We have it all. There's nothing to do. */
958 else if (mips_cpu
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
960 /* We have CPU, we need ISA. */
961 ci
= mips_cpu_info_from_cpu (mips_cpu
);
963 mips_opts
.isa
= ci
->isa
;
965 else if (mips_cpu
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
967 /* We have ISA, we need default CPU. */
968 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
974 /* We need to set both ISA and CPU from target cpu. */
975 ci
= mips_cpu_info_from_name (cpu
);
977 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
979 mips_opts
.isa
= ci
->isa
;
983 ci
= mips_cpu_info_from_cpu (mips_cpu
);
985 mips_isa_from_cpu
= ci
->isa
;
987 /* End of TARGET_CPU processing, get rid of malloced memory
996 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
997 as_bad (_("trap exception not supported at ISA 1"));
999 /* Set the EABI kind based on the ISA before the user gets
1000 to change the ISA with directives. This isn't really
1001 the best, but then neither is basing the abi on the isa. */
1002 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1004 && 0 == strcmp (mips_abi_string
, "eabi"))
1007 /* If they asked for mips1 or mips2 and a cpu that is
1008 mips3 or greater, then mark the object file 32BITMODE. */
1009 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1010 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1011 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1014 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
))
1015 as_warn (_("Could not set architecture and machine"));
1017 file_mips_isa
= mips_opts
.isa
;
1019 op_hash
= hash_new ();
1021 for (i
= 0; i
< NUMOPCODES
;)
1023 const char *name
= mips_opcodes
[i
].name
;
1025 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1028 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1029 mips_opcodes
[i
].name
, retval
);
1030 /* Probably a memory allocation problem? Give up now. */
1031 as_fatal (_("Broken assembler. No assembly attempted."));
1035 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1037 if (!validate_mips_insn (&mips_opcodes
[i
]))
1042 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1045 mips16_op_hash
= hash_new ();
1048 while (i
< bfd_mips16_num_opcodes
)
1050 const char *name
= mips16_opcodes
[i
].name
;
1052 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1054 as_fatal (_("internal: can't hash `%s': %s"),
1055 mips16_opcodes
[i
].name
, retval
);
1058 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1059 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1060 != mips16_opcodes
[i
].match
))
1062 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1063 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1068 while (i
< bfd_mips16_num_opcodes
1069 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1073 as_fatal (_("Broken assembler. No assembly attempted."));
1075 /* We add all the general register names to the symbol table. This
1076 helps us detect invalid uses of them. */
1077 for (i
= 0; i
< 32; i
++)
1081 sprintf (buf
, "$%d", i
);
1082 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1083 &zero_address_frag
));
1085 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1086 &zero_address_frag
));
1087 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1088 &zero_address_frag
));
1089 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1090 &zero_address_frag
));
1091 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1092 &zero_address_frag
));
1093 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1094 &zero_address_frag
));
1095 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1096 &zero_address_frag
));
1097 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1098 &zero_address_frag
));
1100 mips_no_prev_insn (false);
1103 mips_cprmask
[0] = 0;
1104 mips_cprmask
[1] = 0;
1105 mips_cprmask
[2] = 0;
1106 mips_cprmask
[3] = 0;
1108 /* set the default alignment for the text section (2**2) */
1109 record_alignment (text_section
, 2);
1111 if (USE_GLOBAL_POINTER_OPT
)
1112 bfd_set_gp_size (stdoutput
, g_switch_value
);
1114 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1116 /* On a native system, sections must be aligned to 16 byte
1117 boundaries. When configured for an embedded ELF target, we
1119 if (strcmp (TARGET_OS
, "elf") != 0)
1121 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1122 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1123 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1126 /* Create a .reginfo section for register masks and a .mdebug
1127 section for debugging information. */
1135 subseg
= now_subseg
;
1137 /* The ABI says this section should be loaded so that the
1138 running program can access it. However, we don't load it
1139 if we are configured for an embedded target */
1140 flags
= SEC_READONLY
| SEC_DATA
;
1141 if (strcmp (TARGET_OS
, "elf") != 0)
1142 flags
|= SEC_ALLOC
| SEC_LOAD
;
1146 sec
= subseg_new (".reginfo", (subsegT
) 0);
1148 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1149 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1152 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1157 /* The 64-bit ABI uses a .MIPS.options section rather than
1158 .reginfo section. */
1159 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1160 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1161 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1164 /* Set up the option header. */
1166 Elf_Internal_Options opthdr
;
1169 opthdr
.kind
= ODK_REGINFO
;
1170 opthdr
.size
= (sizeof (Elf_External_Options
)
1171 + sizeof (Elf64_External_RegInfo
));
1174 f
= frag_more (sizeof (Elf_External_Options
));
1175 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1176 (Elf_External_Options
*) f
);
1178 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1183 if (ECOFF_DEBUGGING
)
1185 sec
= subseg_new (".mdebug", (subsegT
) 0);
1186 (void) bfd_set_section_flags (stdoutput
, sec
,
1187 SEC_HAS_CONTENTS
| SEC_READONLY
);
1188 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1191 #ifdef MIPS_STABS_ELF
1192 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1193 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1194 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1195 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1198 subseg_set (seg
, subseg
);
1202 if (! ECOFF_DEBUGGING
)
1209 if (! ECOFF_DEBUGGING
)
1217 struct mips_cl_insn insn
;
1219 imm_expr
.X_op
= O_absent
;
1220 imm_reloc
= BFD_RELOC_UNUSED
;
1221 imm_unmatched_hi
= false;
1222 offset_expr
.X_op
= O_absent
;
1223 offset_reloc
= BFD_RELOC_UNUSED
;
1225 if (mips_opts
.mips16
)
1226 mips16_ip (str
, &insn
);
1229 mips_ip (str
, &insn
);
1230 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1231 str
, insn
.insn_opcode
));
1236 as_bad ("%s `%s'", insn_error
, str
);
1240 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1242 if (mips_opts
.mips16
)
1243 mips16_macro (&insn
);
1249 if (imm_expr
.X_op
!= O_absent
)
1250 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1252 else if (offset_expr
.X_op
!= O_absent
)
1253 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1255 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1259 /* See whether instruction IP reads register REG. CLASS is the type
1263 insn_uses_reg (ip
, reg
, class)
1264 struct mips_cl_insn
*ip
;
1266 enum mips_regclass
class;
1268 if (class == MIPS16_REG
)
1270 assert (mips_opts
.mips16
);
1271 reg
= mips16_to_32_reg_map
[reg
];
1272 class = MIPS_GR_REG
;
1275 /* Don't report on general register 0, since it never changes. */
1276 if (class == MIPS_GR_REG
&& reg
== 0)
1279 if (class == MIPS_FP_REG
)
1281 assert (! mips_opts
.mips16
);
1282 /* If we are called with either $f0 or $f1, we must check $f0.
1283 This is not optimal, because it will introduce an unnecessary
1284 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1285 need to distinguish reading both $f0 and $f1 or just one of
1286 them. Note that we don't have to check the other way,
1287 because there is no instruction that sets both $f0 and $f1
1288 and requires a delay. */
1289 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1290 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1291 == (reg
&~ (unsigned) 1)))
1293 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1294 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1295 == (reg
&~ (unsigned) 1)))
1298 else if (! mips_opts
.mips16
)
1300 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1301 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1303 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1304 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1309 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1310 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1311 & MIPS16OP_MASK_RX
)]
1314 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1315 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1316 & MIPS16OP_MASK_RY
)]
1319 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1320 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1321 & MIPS16OP_MASK_MOVE32Z
)]
1324 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1326 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1328 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1330 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1331 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1332 & MIPS16OP_MASK_REGR32
) == reg
)
1339 /* This function returns true if modifying a register requires a
1343 reg_needs_delay (reg
)
1346 unsigned long prev_pinfo
;
1348 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1349 if (! mips_opts
.noreorder
1350 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1351 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1352 || (! gpr_interlocks
1353 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1355 /* A load from a coprocessor or from memory. All load
1356 delays delay the use of general register rt for one
1357 instruction on the r3000. The r6000 and r4000 use
1359 /* Itbl support may require additional care here. */
1360 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1361 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1368 /* Mark instruction labels in mips16 mode. This permits the linker to
1369 handle them specially, such as generating jalx instructions when
1370 needed. We also make them odd for the duration of the assembly, in
1371 order to generate the right sort of code. We will make them even
1372 in the adjust_symtab routine, while leaving them marked. This is
1373 convenient for the debugger and the disassembler. The linker knows
1374 to make them odd again. */
1377 mips16_mark_labels ()
1379 if (mips_opts
.mips16
)
1381 struct insn_label_list
*l
;
1383 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1386 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1387 S_SET_OTHER (l
->label
, STO_MIPS16
);
1389 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1390 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1395 /* Output an instruction. PLACE is where to put the instruction; if
1396 it is NULL, this uses frag_more to get room. IP is the instruction
1397 information. ADDRESS_EXPR is an operand of the instruction to be
1398 used with RELOC_TYPE. */
1401 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1403 struct mips_cl_insn
*ip
;
1404 expressionS
*address_expr
;
1405 bfd_reloc_code_real_type reloc_type
;
1406 boolean unmatched_hi
;
1408 register unsigned long prev_pinfo
, pinfo
;
1413 /* Mark instruction labels in mips16 mode. */
1414 if (mips_opts
.mips16
)
1415 mips16_mark_labels ();
1417 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1418 pinfo
= ip
->insn_mo
->pinfo
;
1420 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1424 /* If the previous insn required any delay slots, see if we need
1425 to insert a NOP or two. There are eight kinds of possible
1426 hazards, of which an instruction can have at most one type.
1427 (1) a load from memory delay
1428 (2) a load from a coprocessor delay
1429 (3) an unconditional branch delay
1430 (4) a conditional branch delay
1431 (5) a move to coprocessor register delay
1432 (6) a load coprocessor register from memory delay
1433 (7) a coprocessor condition code delay
1434 (8) a HI/LO special register delay
1436 There are a lot of optimizations we could do that we don't.
1437 In particular, we do not, in general, reorder instructions.
1438 If you use gcc with optimization, it will reorder
1439 instructions and generally do much more optimization then we
1440 do here; repeating all that work in the assembler would only
1441 benefit hand written assembly code, and does not seem worth
1444 /* This is how a NOP is emitted. */
1445 #define emit_nop() \
1447 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1448 : md_number_to_chars (frag_more (4), 0, 4))
1450 /* The previous insn might require a delay slot, depending upon
1451 the contents of the current insn. */
1452 if (! mips_opts
.mips16
1453 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1454 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1455 && ! cop_interlocks
)
1456 || (! gpr_interlocks
1457 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1459 /* A load from a coprocessor or from memory. All load
1460 delays delay the use of general register rt for one
1461 instruction on the r3000. The r6000 and r4000 use
1463 /* Itbl support may require additional care here. */
1464 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1465 if (mips_optimize
== 0
1466 || insn_uses_reg (ip
,
1467 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1472 else if (! mips_opts
.mips16
1473 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1474 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1475 && ! cop_interlocks
)
1476 || (mips_opts
.isa
== ISA_MIPS1
1477 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1479 /* A generic coprocessor delay. The previous instruction
1480 modified a coprocessor general or control register. If
1481 it modified a control register, we need to avoid any
1482 coprocessor instruction (this is probably not always
1483 required, but it sometimes is). If it modified a general
1484 register, we avoid using that register.
1486 On the r6000 and r4000 loading a coprocessor register
1487 from memory is interlocked, and does not require a delay.
1489 This case is not handled very well. There is no special
1490 knowledge of CP0 handling, and the coprocessors other
1491 than the floating point unit are not distinguished at
1493 /* Itbl support may require additional care here. FIXME!
1494 Need to modify this to include knowledge about
1495 user specified delays! */
1496 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1498 if (mips_optimize
== 0
1499 || insn_uses_reg (ip
,
1500 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1505 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1507 if (mips_optimize
== 0
1508 || insn_uses_reg (ip
,
1509 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1516 /* We don't know exactly what the previous instruction
1517 does. If the current instruction uses a coprocessor
1518 register, we must insert a NOP. If previous
1519 instruction may set the condition codes, and the
1520 current instruction uses them, we must insert two
1522 /* Itbl support may require additional care here. */
1523 if (mips_optimize
== 0
1524 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1525 && (pinfo
& INSN_READ_COND_CODE
)))
1527 else if (pinfo
& INSN_COP
)
1531 else if (! mips_opts
.mips16
1532 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1533 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1534 && ! cop_interlocks
)
1536 /* The previous instruction sets the coprocessor condition
1537 codes, but does not require a general coprocessor delay
1538 (this means it is a floating point comparison
1539 instruction). If this instruction uses the condition
1540 codes, we need to insert a single NOP. */
1541 /* Itbl support may require additional care here. */
1542 if (mips_optimize
== 0
1543 || (pinfo
& INSN_READ_COND_CODE
))
1547 /* If we're fixing up mfhi/mflo for the r7000 and the
1548 previous insn was an mfhi/mflo and the current insn
1549 reads the register that the mfhi/mflo wrote to, then
1552 else if (mips_7000_hilo_fix
1553 && MF_HILO_INSN (prev_pinfo
)
1554 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1561 /* If we're fixing up mfhi/mflo for the r7000 and the
1562 2nd previous insn was an mfhi/mflo and the current insn
1563 reads the register that the mfhi/mflo wrote to, then
1566 else if (mips_7000_hilo_fix
1567 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1568 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1576 else if (prev_pinfo
& INSN_READ_LO
)
1578 /* The previous instruction reads the LO register; if the
1579 current instruction writes to the LO register, we must
1580 insert two NOPS. Some newer processors have interlocks.
1581 Also the tx39's multiply instructions can be exectuted
1582 immediatly after a read from HI/LO (without the delay),
1583 though the tx39's divide insns still do require the
1585 if (! (hilo_interlocks
1586 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1587 && (mips_optimize
== 0
1588 || (pinfo
& INSN_WRITE_LO
)))
1590 /* Most mips16 branch insns don't have a delay slot.
1591 If a read from LO is immediately followed by a branch
1592 to a write to LO we have a read followed by a write
1593 less than 2 insns away. We assume the target of
1594 a branch might be a write to LO, and insert a nop
1595 between a read and an immediately following branch. */
1596 else if (mips_opts
.mips16
1597 && (mips_optimize
== 0
1598 || (pinfo
& MIPS16_INSN_BRANCH
)))
1601 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1603 /* The previous instruction reads the HI register; if the
1604 current instruction writes to the HI register, we must
1605 insert a NOP. Some newer processors have interlocks.
1606 Also the note tx39's multiply above. */
1607 if (! (hilo_interlocks
1608 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1609 && (mips_optimize
== 0
1610 || (pinfo
& INSN_WRITE_HI
)))
1612 /* Most mips16 branch insns don't have a delay slot.
1613 If a read from HI is immediately followed by a branch
1614 to a write to HI we have a read followed by a write
1615 less than 2 insns away. We assume the target of
1616 a branch might be a write to HI, and insert a nop
1617 between a read and an immediately following branch. */
1618 else if (mips_opts
.mips16
1619 && (mips_optimize
== 0
1620 || (pinfo
& MIPS16_INSN_BRANCH
)))
1624 /* If the previous instruction was in a noreorder section, then
1625 we don't want to insert the nop after all. */
1626 /* Itbl support may require additional care here. */
1627 if (prev_insn_unreordered
)
1630 /* There are two cases which require two intervening
1631 instructions: 1) setting the condition codes using a move to
1632 coprocessor instruction which requires a general coprocessor
1633 delay and then reading the condition codes 2) reading the HI
1634 or LO register and then writing to it (except on processors
1635 which have interlocks). If we are not already emitting a NOP
1636 instruction, we must check for these cases compared to the
1637 instruction previous to the previous instruction. */
1638 if ((! mips_opts
.mips16
1639 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1640 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1641 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1642 && (pinfo
& INSN_READ_COND_CODE
)
1643 && ! cop_interlocks
)
1644 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1645 && (pinfo
& INSN_WRITE_LO
)
1646 && ! (hilo_interlocks
1647 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1648 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1649 && (pinfo
& INSN_WRITE_HI
)
1650 && ! (hilo_interlocks
1651 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1656 if (prev_prev_insn_unreordered
)
1659 if (prev_prev_nop
&& nops
== 0)
1662 /* If we are being given a nop instruction, don't bother with
1663 one of the nops we would otherwise output. This will only
1664 happen when a nop instruction is used with mips_optimize set
1667 && ! mips_opts
.noreorder
1668 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1671 /* Now emit the right number of NOP instructions. */
1672 if (nops
> 0 && ! mips_opts
.noreorder
)
1675 unsigned long old_frag_offset
;
1677 struct insn_label_list
*l
;
1679 old_frag
= frag_now
;
1680 old_frag_offset
= frag_now_fix ();
1682 for (i
= 0; i
< nops
; i
++)
1687 listing_prev_line ();
1688 /* We may be at the start of a variant frag. In case we
1689 are, make sure there is enough space for the frag
1690 after the frags created by listing_prev_line. The
1691 argument to frag_grow here must be at least as large
1692 as the argument to all other calls to frag_grow in
1693 this file. We don't have to worry about being in the
1694 middle of a variant frag, because the variants insert
1695 all needed nop instructions themselves. */
1699 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1701 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1702 symbol_set_frag (l
->label
, frag_now
);
1703 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1704 /* mips16 text labels are stored as odd. */
1705 if (mips_opts
.mips16
)
1706 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1709 #ifndef NO_ECOFF_DEBUGGING
1710 if (ECOFF_DEBUGGING
)
1711 ecoff_fix_loc (old_frag
, old_frag_offset
);
1714 else if (prev_nop_frag
!= NULL
)
1716 /* We have a frag holding nops we may be able to remove. If
1717 we don't need any nops, we can decrease the size of
1718 prev_nop_frag by the size of one instruction. If we do
1719 need some nops, we count them in prev_nops_required. */
1720 if (prev_nop_frag_since
== 0)
1724 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1725 --prev_nop_frag_holds
;
1728 prev_nop_frag_required
+= nops
;
1732 if (prev_prev_nop
== 0)
1734 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1735 --prev_nop_frag_holds
;
1738 ++prev_nop_frag_required
;
1741 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1742 prev_nop_frag
= NULL
;
1744 ++prev_nop_frag_since
;
1746 /* Sanity check: by the time we reach the second instruction
1747 after prev_nop_frag, we should have used up all the nops
1748 one way or another. */
1749 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1753 if (reloc_type
> BFD_RELOC_UNUSED
)
1755 /* We need to set up a variant frag. */
1756 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1757 f
= frag_var (rs_machine_dependent
, 4, 0,
1758 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1759 mips16_small
, mips16_ext
,
1761 & INSN_UNCOND_BRANCH_DELAY
),
1762 (prev_insn_reloc_type
1763 == BFD_RELOC_MIPS16_JMP
)),
1764 make_expr_symbol (address_expr
), (offsetT
) 0,
1767 else if (place
!= NULL
)
1769 else if (mips_opts
.mips16
1771 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1773 /* Make sure there is enough room to swap this instruction with
1774 a following jump instruction. */
1780 if (mips_opts
.mips16
1781 && mips_opts
.noreorder
1782 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1783 as_warn (_("extended instruction in delay slot"));
1789 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1791 if (address_expr
->X_op
== O_constant
)
1796 ip
->insn_opcode
|= address_expr
->X_add_number
;
1799 case BFD_RELOC_LO16
:
1800 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1803 case BFD_RELOC_MIPS_JMP
:
1804 if ((address_expr
->X_add_number
& 3) != 0)
1805 as_bad (_("jump to misaligned address (0x%lx)"),
1806 (unsigned long) address_expr
->X_add_number
);
1807 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1810 case BFD_RELOC_MIPS16_JMP
:
1811 if ((address_expr
->X_add_number
& 3) != 0)
1812 as_bad (_("jump to misaligned address (0x%lx)"),
1813 (unsigned long) address_expr
->X_add_number
);
1815 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1816 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1817 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1820 case BFD_RELOC_16_PCREL_S2
:
1830 /* Don't generate a reloc if we are writing into a variant
1834 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1836 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1840 struct mips_hi_fixup
*hi_fixup
;
1842 assert (reloc_type
== BFD_RELOC_HI16_S
);
1843 hi_fixup
= ((struct mips_hi_fixup
*)
1844 xmalloc (sizeof (struct mips_hi_fixup
)));
1845 hi_fixup
->fixp
= fixp
;
1846 hi_fixup
->seg
= now_seg
;
1847 hi_fixup
->next
= mips_hi_fixup_list
;
1848 mips_hi_fixup_list
= hi_fixup
;
1854 if (! mips_opts
.mips16
)
1855 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1856 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1858 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1859 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1865 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1868 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1871 /* Update the register mask information. */
1872 if (! mips_opts
.mips16
)
1874 if (pinfo
& INSN_WRITE_GPR_D
)
1875 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1876 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1877 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1878 if (pinfo
& INSN_READ_GPR_S
)
1879 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1880 if (pinfo
& INSN_WRITE_GPR_31
)
1881 mips_gprmask
|= 1 << 31;
1882 if (pinfo
& INSN_WRITE_FPR_D
)
1883 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1884 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1885 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1886 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1887 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1888 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1889 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1890 if (pinfo
& INSN_COP
)
1892 /* We don't keep enough information to sort these cases out.
1893 The itbl support does keep this information however, although
1894 we currently don't support itbl fprmats as part of the cop
1895 instruction. May want to add this support in the future. */
1897 /* Never set the bit for $0, which is always zero. */
1898 mips_gprmask
&= ~1 << 0;
1902 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1903 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1904 & MIPS16OP_MASK_RX
);
1905 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1906 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1907 & MIPS16OP_MASK_RY
);
1908 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1909 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1910 & MIPS16OP_MASK_RZ
);
1911 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1912 mips_gprmask
|= 1 << TREG
;
1913 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1914 mips_gprmask
|= 1 << SP
;
1915 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1916 mips_gprmask
|= 1 << RA
;
1917 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1918 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1919 if (pinfo
& MIPS16_INSN_READ_Z
)
1920 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1921 & MIPS16OP_MASK_MOVE32Z
);
1922 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1923 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1924 & MIPS16OP_MASK_REGR32
);
1927 if (place
== NULL
&& ! mips_opts
.noreorder
)
1929 /* Filling the branch delay slot is more complex. We try to
1930 switch the branch with the previous instruction, which we can
1931 do if the previous instruction does not set up a condition
1932 that the branch tests and if the branch is not itself the
1933 target of any branch. */
1934 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1935 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1937 if (mips_optimize
< 2
1938 /* If we have seen .set volatile or .set nomove, don't
1940 || mips_opts
.nomove
!= 0
1941 /* If we had to emit any NOP instructions, then we
1942 already know we can not swap. */
1944 /* If we don't even know the previous insn, we can not
1946 || ! prev_insn_valid
1947 /* If the previous insn is already in a branch delay
1948 slot, then we can not swap. */
1949 || prev_insn_is_delay_slot
1950 /* If the previous previous insn was in a .set
1951 noreorder, we can't swap. Actually, the MIPS
1952 assembler will swap in this situation. However, gcc
1953 configured -with-gnu-as will generate code like
1959 in which we can not swap the bne and INSN. If gcc is
1960 not configured -with-gnu-as, it does not output the
1961 .set pseudo-ops. We don't have to check
1962 prev_insn_unreordered, because prev_insn_valid will
1963 be 0 in that case. We don't want to use
1964 prev_prev_insn_valid, because we do want to be able
1965 to swap at the start of a function. */
1966 || prev_prev_insn_unreordered
1967 /* If the branch is itself the target of a branch, we
1968 can not swap. We cheat on this; all we check for is
1969 whether there is a label on this instruction. If
1970 there are any branches to anything other than a
1971 label, users must use .set noreorder. */
1972 || insn_labels
!= NULL
1973 /* If the previous instruction is in a variant frag, we
1974 can not do the swap. This does not apply to the
1975 mips16, which uses variant frags for different
1977 || (! mips_opts
.mips16
1978 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1979 /* If the branch reads the condition codes, we don't
1980 even try to swap, because in the sequence
1985 we can not swap, and I don't feel like handling that
1987 || (! mips_opts
.mips16
1988 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1989 && (pinfo
& INSN_READ_COND_CODE
))
1990 /* We can not swap with an instruction that requires a
1991 delay slot, becase the target of the branch might
1992 interfere with that instruction. */
1993 || (! mips_opts
.mips16
1994 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1996 /* Itbl support may require additional care here. */
1997 & (INSN_LOAD_COPROC_DELAY
1998 | INSN_COPROC_MOVE_DELAY
1999 | INSN_WRITE_COND_CODE
)))
2000 || (! (hilo_interlocks
2001 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2005 || (! mips_opts
.mips16
2007 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2008 || (! mips_opts
.mips16
2009 && mips_opts
.isa
== ISA_MIPS1
2010 /* Itbl support may require additional care here. */
2011 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2012 /* We can not swap with a branch instruction. */
2014 & (INSN_UNCOND_BRANCH_DELAY
2015 | INSN_COND_BRANCH_DELAY
2016 | INSN_COND_BRANCH_LIKELY
))
2017 /* We do not swap with a trap instruction, since it
2018 complicates trap handlers to have the trap
2019 instruction be in a delay slot. */
2020 || (prev_pinfo
& INSN_TRAP
)
2021 /* If the branch reads a register that the previous
2022 instruction sets, we can not swap. */
2023 || (! mips_opts
.mips16
2024 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2025 && insn_uses_reg (ip
,
2026 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2029 || (! mips_opts
.mips16
2030 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2031 && insn_uses_reg (ip
,
2032 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2035 || (mips_opts
.mips16
2036 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2037 && insn_uses_reg (ip
,
2038 ((prev_insn
.insn_opcode
2040 & MIPS16OP_MASK_RX
),
2042 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2043 && insn_uses_reg (ip
,
2044 ((prev_insn
.insn_opcode
2046 & MIPS16OP_MASK_RY
),
2048 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2049 && insn_uses_reg (ip
,
2050 ((prev_insn
.insn_opcode
2052 & MIPS16OP_MASK_RZ
),
2054 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2055 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2056 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2057 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2058 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2059 && insn_uses_reg (ip
,
2060 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2063 /* If the branch writes a register that the previous
2064 instruction sets, we can not swap (we know that
2065 branches write only to RD or to $31). */
2066 || (! mips_opts
.mips16
2067 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2068 && (((pinfo
& INSN_WRITE_GPR_D
)
2069 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2070 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2071 || ((pinfo
& INSN_WRITE_GPR_31
)
2072 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2075 || (! mips_opts
.mips16
2076 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2077 && (((pinfo
& INSN_WRITE_GPR_D
)
2078 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2079 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2080 || ((pinfo
& INSN_WRITE_GPR_31
)
2081 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2084 || (mips_opts
.mips16
2085 && (pinfo
& MIPS16_INSN_WRITE_31
)
2086 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2087 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2088 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2090 /* If the branch writes a register that the previous
2091 instruction reads, we can not swap (we know that
2092 branches only write to RD or to $31). */
2093 || (! mips_opts
.mips16
2094 && (pinfo
& INSN_WRITE_GPR_D
)
2095 && insn_uses_reg (&prev_insn
,
2096 ((ip
->insn_opcode
>> OP_SH_RD
)
2099 || (! mips_opts
.mips16
2100 && (pinfo
& INSN_WRITE_GPR_31
)
2101 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2102 || (mips_opts
.mips16
2103 && (pinfo
& MIPS16_INSN_WRITE_31
)
2104 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2105 /* If we are generating embedded PIC code, the branch
2106 might be expanded into a sequence which uses $at, so
2107 we can't swap with an instruction which reads it. */
2108 || (mips_pic
== EMBEDDED_PIC
2109 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2110 /* If the previous previous instruction has a load
2111 delay, and sets a register that the branch reads, we
2113 || (! mips_opts
.mips16
2114 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2115 /* Itbl support may require additional care here. */
2116 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2117 || (! gpr_interlocks
2118 && (prev_prev_insn
.insn_mo
->pinfo
2119 & INSN_LOAD_MEMORY_DELAY
)))
2120 && insn_uses_reg (ip
,
2121 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2124 /* If one instruction sets a condition code and the
2125 other one uses a condition code, we can not swap. */
2126 || ((pinfo
& INSN_READ_COND_CODE
)
2127 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2128 || ((pinfo
& INSN_WRITE_COND_CODE
)
2129 && (prev_pinfo
& INSN_READ_COND_CODE
))
2130 /* If the previous instruction uses the PC, we can not
2132 || (mips_opts
.mips16
2133 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2134 /* If the previous instruction was extended, we can not
2136 || (mips_opts
.mips16
&& prev_insn_extended
)
2137 /* If the previous instruction had a fixup in mips16
2138 mode, we can not swap. This normally means that the
2139 previous instruction was a 4 byte branch anyhow. */
2140 || (mips_opts
.mips16
&& prev_insn_fixp
)
2141 /* If the previous instruction is a sync, sync.l, or
2142 sync.p, we can not swap. */
2143 || (prev_pinfo
& INSN_SYNC
))
2145 /* We could do even better for unconditional branches to
2146 portions of this object file; we could pick up the
2147 instruction at the destination, put it in the delay
2148 slot, and bump the destination address. */
2150 /* Update the previous insn information. */
2151 prev_prev_insn
= *ip
;
2152 prev_insn
.insn_mo
= &dummy_opcode
;
2156 /* It looks like we can actually do the swap. */
2157 if (! mips_opts
.mips16
)
2162 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2163 memcpy (temp
, prev_f
, 4);
2164 memcpy (prev_f
, f
, 4);
2165 memcpy (f
, temp
, 4);
2168 prev_insn_fixp
->fx_frag
= frag_now
;
2169 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2173 fixp
->fx_frag
= prev_insn_frag
;
2174 fixp
->fx_where
= prev_insn_where
;
2182 assert (prev_insn_fixp
== NULL
);
2183 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2184 memcpy (temp
, prev_f
, 2);
2185 memcpy (prev_f
, f
, 2);
2186 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2188 assert (reloc_type
== BFD_RELOC_UNUSED
);
2189 memcpy (f
, temp
, 2);
2193 memcpy (f
, f
+ 2, 2);
2194 memcpy (f
+ 2, temp
, 2);
2198 fixp
->fx_frag
= prev_insn_frag
;
2199 fixp
->fx_where
= prev_insn_where
;
2203 /* Update the previous insn information; leave prev_insn
2205 prev_prev_insn
= *ip
;
2207 prev_insn_is_delay_slot
= 1;
2209 /* If that was an unconditional branch, forget the previous
2210 insn information. */
2211 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2213 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2214 prev_insn
.insn_mo
= &dummy_opcode
;
2217 prev_insn_fixp
= NULL
;
2218 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2219 prev_insn_extended
= 0;
2221 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2223 /* We don't yet optimize a branch likely. What we should do
2224 is look at the target, copy the instruction found there
2225 into the delay slot, and increment the branch to jump to
2226 the next instruction. */
2228 /* Update the previous insn information. */
2229 prev_prev_insn
= *ip
;
2230 prev_insn
.insn_mo
= &dummy_opcode
;
2231 prev_insn_fixp
= NULL
;
2232 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2233 prev_insn_extended
= 0;
2237 /* Update the previous insn information. */
2239 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2241 prev_prev_insn
= prev_insn
;
2244 /* Any time we see a branch, we always fill the delay slot
2245 immediately; since this insn is not a branch, we know it
2246 is not in a delay slot. */
2247 prev_insn_is_delay_slot
= 0;
2249 prev_insn_fixp
= fixp
;
2250 prev_insn_reloc_type
= reloc_type
;
2251 if (mips_opts
.mips16
)
2252 prev_insn_extended
= (ip
->use_extend
2253 || reloc_type
> BFD_RELOC_UNUSED
);
2256 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2257 prev_insn_unreordered
= 0;
2258 prev_insn_frag
= frag_now
;
2259 prev_insn_where
= f
- frag_now
->fr_literal
;
2260 prev_insn_valid
= 1;
2262 else if (place
== NULL
)
2264 /* We need to record a bit of information even when we are not
2265 reordering, in order to determine the base address for mips16
2266 PC relative relocs. */
2267 prev_prev_insn
= prev_insn
;
2269 prev_insn_reloc_type
= reloc_type
;
2270 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2271 prev_insn_unreordered
= 1;
2274 /* We just output an insn, so the next one doesn't have a label. */
2275 mips_clear_insn_labels ();
2277 /* We must ensure that a fixup associated with an unmatched %hi
2278 reloc does not become a variant frag. Otherwise, the
2279 rearrangement of %hi relocs in frob_file may confuse
2283 frag_wane (frag_now
);
2288 /* This function forgets that there was any previous instruction or
2289 label. If PRESERVE is non-zero, it remembers enough information to
2290 know whether nops are needed before a noreorder section. */
2293 mips_no_prev_insn (preserve
)
2298 prev_insn
.insn_mo
= &dummy_opcode
;
2299 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2300 prev_nop_frag
= NULL
;
2301 prev_nop_frag_holds
= 0;
2302 prev_nop_frag_required
= 0;
2303 prev_nop_frag_since
= 0;
2305 prev_insn_valid
= 0;
2306 prev_insn_is_delay_slot
= 0;
2307 prev_insn_unreordered
= 0;
2308 prev_insn_extended
= 0;
2309 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2310 prev_prev_insn_unreordered
= 0;
2311 mips_clear_insn_labels ();
2314 /* This function must be called whenever we turn on noreorder or emit
2315 something other than instructions. It inserts any NOPS which might
2316 be needed by the previous instruction, and clears the information
2317 kept for the previous instructions. The INSNS parameter is true if
2318 instructions are to follow. */
2321 mips_emit_delays (insns
)
2324 if (! mips_opts
.noreorder
)
2329 if ((! mips_opts
.mips16
2330 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2331 && (! cop_interlocks
2332 && (prev_insn
.insn_mo
->pinfo
2333 & (INSN_LOAD_COPROC_DELAY
2334 | INSN_COPROC_MOVE_DELAY
2335 | INSN_WRITE_COND_CODE
))))
2336 || (! hilo_interlocks
2337 && (prev_insn
.insn_mo
->pinfo
2340 || (! mips_opts
.mips16
2342 && (prev_insn
.insn_mo
->pinfo
2343 & INSN_LOAD_MEMORY_DELAY
))
2344 || (! mips_opts
.mips16
2345 && mips_opts
.isa
== ISA_MIPS1
2346 && (prev_insn
.insn_mo
->pinfo
2347 & INSN_COPROC_MEMORY_DELAY
)))
2349 /* Itbl support may require additional care here. */
2351 if ((! mips_opts
.mips16
2352 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2353 && (! cop_interlocks
2354 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2355 || (! hilo_interlocks
2356 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2357 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2360 if (prev_insn_unreordered
)
2363 else if ((! mips_opts
.mips16
2364 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2365 && (! cop_interlocks
2366 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2367 || (! hilo_interlocks
2368 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2369 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2371 /* Itbl support may require additional care here. */
2372 if (! prev_prev_insn_unreordered
)
2378 struct insn_label_list
*l
;
2382 /* Record the frag which holds the nop instructions, so
2383 that we can remove them if we don't need them. */
2384 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2385 prev_nop_frag
= frag_now
;
2386 prev_nop_frag_holds
= nops
;
2387 prev_nop_frag_required
= 0;
2388 prev_nop_frag_since
= 0;
2391 for (; nops
> 0; --nops
)
2396 /* Move on to a new frag, so that it is safe to simply
2397 decrease the size of prev_nop_frag. */
2398 frag_wane (frag_now
);
2402 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2404 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2405 symbol_set_frag (l
->label
, frag_now
);
2406 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2407 /* mips16 text labels are stored as odd. */
2408 if (mips_opts
.mips16
)
2409 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2414 /* Mark instruction labels in mips16 mode. */
2415 if (mips_opts
.mips16
&& insns
)
2416 mips16_mark_labels ();
2418 mips_no_prev_insn (insns
);
2421 /* Build an instruction created by a macro expansion. This is passed
2422 a pointer to the count of instructions created so far, an
2423 expression, the name of the instruction to build, an operand format
2424 string, and corresponding arguments. */
2428 macro_build (char *place
,
2436 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2445 struct mips_cl_insn insn
;
2446 bfd_reloc_code_real_type r
;
2450 va_start (args
, fmt
);
2456 * If the macro is about to expand into a second instruction,
2457 * print a warning if needed. We need to pass ip as a parameter
2458 * to generate a better warning message here...
2460 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2461 as_warn (_("Macro instruction expanded into multiple instructions"));
2464 *counter
+= 1; /* bump instruction counter */
2466 if (mips_opts
.mips16
)
2468 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2473 r
= BFD_RELOC_UNUSED
;
2474 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2475 assert (insn
.insn_mo
);
2476 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2478 /* Search until we get a match for NAME. */
2481 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2482 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2483 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2485 && (mips_cpu
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2489 assert (insn
.insn_mo
->name
);
2490 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2493 insn
.insn_opcode
= insn
.insn_mo
->match
;
2509 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2515 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2520 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2525 int tmp
= va_arg (args
, int);
2527 insn
.insn_opcode
|= tmp
<< 16;
2528 insn
.insn_opcode
|= tmp
<< 11;
2534 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2541 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2545 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2549 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2553 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2557 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2564 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2570 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2571 assert (r
== BFD_RELOC_MIPS_GPREL
2572 || r
== BFD_RELOC_MIPS_LITERAL
2573 || r
== BFD_RELOC_LO16
2574 || r
== BFD_RELOC_MIPS_GOT16
2575 || r
== BFD_RELOC_MIPS_CALL16
2576 || r
== BFD_RELOC_MIPS_GOT_LO16
2577 || r
== BFD_RELOC_MIPS_CALL_LO16
2578 || (ep
->X_op
== O_subtract
2579 && r
== BFD_RELOC_PCREL_LO16
));
2583 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2585 && (ep
->X_op
== O_constant
2586 || (ep
->X_op
== O_symbol
2587 && (r
== BFD_RELOC_HI16_S
2588 || r
== BFD_RELOC_HI16
2589 || r
== BFD_RELOC_MIPS_GOT_HI16
2590 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2591 || (ep
->X_op
== O_subtract
2592 && r
== BFD_RELOC_PCREL_HI16_S
)));
2593 if (ep
->X_op
== O_constant
)
2595 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2597 r
= BFD_RELOC_UNUSED
;
2602 assert (ep
!= NULL
);
2604 * This allows macro() to pass an immediate expression for
2605 * creating short branches without creating a symbol.
2606 * Note that the expression still might come from the assembly
2607 * input, in which case the value is not checked for range nor
2608 * is a relocation entry generated (yuck).
2610 if (ep
->X_op
== O_constant
)
2612 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2616 r
= BFD_RELOC_16_PCREL_S2
;
2620 assert (ep
!= NULL
);
2621 r
= BFD_RELOC_MIPS_JMP
;
2625 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2634 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2636 append_insn (place
, &insn
, ep
, r
, false);
2640 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2642 int *counter ATTRIBUTE_UNUSED
;
2648 struct mips_cl_insn insn
;
2649 bfd_reloc_code_real_type r
;
2651 r
= BFD_RELOC_UNUSED
;
2652 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2653 assert (insn
.insn_mo
);
2654 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2656 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2657 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2660 assert (insn
.insn_mo
->name
);
2661 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2664 insn
.insn_opcode
= insn
.insn_mo
->match
;
2665 insn
.use_extend
= false;
2684 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2689 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2693 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2697 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2707 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2714 regno
= va_arg (args
, int);
2715 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2716 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2737 assert (ep
!= NULL
);
2739 if (ep
->X_op
!= O_constant
)
2740 r
= BFD_RELOC_UNUSED
+ c
;
2743 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2744 false, false, &insn
.insn_opcode
,
2745 &insn
.use_extend
, &insn
.extend
);
2747 r
= BFD_RELOC_UNUSED
;
2753 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2760 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2762 append_insn (place
, &insn
, ep
, r
, false);
2766 * Generate a "lui" instruction.
2769 macro_build_lui (place
, counter
, ep
, regnum
)
2775 expressionS high_expr
;
2776 struct mips_cl_insn insn
;
2777 bfd_reloc_code_real_type r
;
2778 CONST
char *name
= "lui";
2779 CONST
char *fmt
= "t,u";
2781 assert (! mips_opts
.mips16
);
2787 high_expr
.X_op
= O_constant
;
2788 high_expr
.X_add_number
= ep
->X_add_number
;
2791 if (high_expr
.X_op
== O_constant
)
2793 /* we can compute the instruction now without a relocation entry */
2794 if (high_expr
.X_add_number
& 0x8000)
2795 high_expr
.X_add_number
+= 0x10000;
2796 high_expr
.X_add_number
=
2797 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2798 r
= BFD_RELOC_UNUSED
;
2802 assert (ep
->X_op
== O_symbol
);
2803 /* _gp_disp is a special case, used from s_cpload. */
2804 assert (mips_pic
== NO_PIC
2805 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2806 r
= BFD_RELOC_HI16_S
;
2810 * If the macro is about to expand into a second instruction,
2811 * print a warning if needed. We need to pass ip as a parameter
2812 * to generate a better warning message here...
2814 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2815 as_warn (_("Macro instruction expanded into multiple instructions"));
2818 *counter
+= 1; /* bump instruction counter */
2820 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2821 assert (insn
.insn_mo
);
2822 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2823 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2825 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2826 if (r
== BFD_RELOC_UNUSED
)
2828 insn
.insn_opcode
|= high_expr
.X_add_number
;
2829 append_insn (place
, &insn
, NULL
, r
, false);
2832 append_insn (place
, &insn
, &high_expr
, r
, false);
2836 * Generates code to set the $at register to true (one)
2837 * if reg is less than the immediate expression.
2840 set_at (counter
, reg
, unsignedp
)
2845 if (imm_expr
.X_op
== O_constant
2846 && imm_expr
.X_add_number
>= -0x8000
2847 && imm_expr
.X_add_number
< 0x8000)
2848 macro_build ((char *) NULL
, counter
, &imm_expr
,
2849 unsignedp
? "sltiu" : "slti",
2850 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2853 load_register (counter
, AT
, &imm_expr
, 0);
2854 macro_build ((char *) NULL
, counter
, NULL
,
2855 unsignedp
? "sltu" : "slt",
2856 "d,v,t", AT
, reg
, AT
);
2860 /* Warn if an expression is not a constant. */
2863 check_absolute_expr (ip
, ex
)
2864 struct mips_cl_insn
*ip
;
2867 if (ex
->X_op
== O_big
)
2868 as_bad (_("unsupported large constant"));
2869 else if (ex
->X_op
!= O_constant
)
2870 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2873 /* Count the leading zeroes by performing a binary chop. This is a
2874 bulky bit of source, but performance is a LOT better for the
2875 majority of values than a simple loop to count the bits:
2876 for (lcnt = 0; (lcnt < 32); lcnt++)
2877 if ((v) & (1 << (31 - lcnt)))
2879 However it is not code size friendly, and the gain will drop a bit
2880 on certain cached systems.
2882 #define COUNT_TOP_ZEROES(v) \
2883 (((v) & ~0xffff) == 0 \
2884 ? ((v) & ~0xff) == 0 \
2885 ? ((v) & ~0xf) == 0 \
2886 ? ((v) & ~0x3) == 0 \
2887 ? ((v) & ~0x1) == 0 \
2892 : ((v) & ~0x7) == 0 \
2895 : ((v) & ~0x3f) == 0 \
2896 ? ((v) & ~0x1f) == 0 \
2899 : ((v) & ~0x7f) == 0 \
2902 : ((v) & ~0xfff) == 0 \
2903 ? ((v) & ~0x3ff) == 0 \
2904 ? ((v) & ~0x1ff) == 0 \
2907 : ((v) & ~0x7ff) == 0 \
2910 : ((v) & ~0x3fff) == 0 \
2911 ? ((v) & ~0x1fff) == 0 \
2914 : ((v) & ~0x7fff) == 0 \
2917 : ((v) & ~0xffffff) == 0 \
2918 ? ((v) & ~0xfffff) == 0 \
2919 ? ((v) & ~0x3ffff) == 0 \
2920 ? ((v) & ~0x1ffff) == 0 \
2923 : ((v) & ~0x7ffff) == 0 \
2926 : ((v) & ~0x3fffff) == 0 \
2927 ? ((v) & ~0x1fffff) == 0 \
2930 : ((v) & ~0x7fffff) == 0 \
2933 : ((v) & ~0xfffffff) == 0 \
2934 ? ((v) & ~0x3ffffff) == 0 \
2935 ? ((v) & ~0x1ffffff) == 0 \
2938 : ((v) & ~0x7ffffff) == 0 \
2941 : ((v) & ~0x3fffffff) == 0 \
2942 ? ((v) & ~0x1fffffff) == 0 \
2945 : ((v) & ~0x7fffffff) == 0 \
2950 * This routine generates the least number of instructions neccessary to load
2951 * an absolute expression value into a register.
2954 load_register (counter
, reg
, ep
, dbl
)
2961 expressionS hi32
, lo32
;
2963 if (ep
->X_op
!= O_big
)
2965 assert (ep
->X_op
== O_constant
);
2966 if (ep
->X_add_number
< 0x8000
2967 && (ep
->X_add_number
>= 0
2968 || (ep
->X_add_number
>= -0x8000
2971 || sizeof (ep
->X_add_number
) > 4))))
2973 /* We can handle 16 bit signed values with an addiu to
2974 $zero. No need to ever use daddiu here, since $zero and
2975 the result are always correct in 32 bit mode. */
2976 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2977 (int) BFD_RELOC_LO16
);
2980 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2982 /* We can handle 16 bit unsigned values with an ori to
2984 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2985 (int) BFD_RELOC_LO16
);
2988 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2989 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2990 == ~ (offsetT
) 0x7fffffff))
2993 || sizeof (ep
->X_add_number
) > 4
2994 || (ep
->X_add_number
& 0x80000000) == 0))
2995 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
2996 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2997 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
2999 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3000 == ~ (offsetT
) 0xffffffff)))
3002 /* 32 bit values require an lui. */
3003 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3004 (int) BFD_RELOC_HI16
);
3005 if ((ep
->X_add_number
& 0xffff) != 0)
3006 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3007 (int) BFD_RELOC_LO16
);
3012 /* The value is larger than 32 bits. */
3014 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3016 as_bad (_("Number larger than 32 bits"));
3017 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3018 (int) BFD_RELOC_LO16
);
3022 if (ep
->X_op
!= O_big
)
3025 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3026 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3027 hi32
.X_add_number
&= 0xffffffff;
3029 lo32
.X_add_number
&= 0xffffffff;
3033 assert (ep
->X_add_number
> 2);
3034 if (ep
->X_add_number
== 3)
3035 generic_bignum
[3] = 0;
3036 else if (ep
->X_add_number
> 4)
3037 as_bad (_("Number larger than 64 bits"));
3038 lo32
.X_op
= O_constant
;
3039 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3040 hi32
.X_op
= O_constant
;
3041 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3044 if (hi32
.X_add_number
== 0)
3049 unsigned long hi
, lo
;
3051 if (hi32
.X_add_number
== 0xffffffff)
3053 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3055 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3056 reg
, 0, (int) BFD_RELOC_LO16
);
3059 if (lo32
.X_add_number
& 0x80000000)
3061 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3062 (int) BFD_RELOC_HI16
);
3063 if (lo32
.X_add_number
& 0xffff)
3064 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3065 reg
, reg
, (int) BFD_RELOC_LO16
);
3070 /* Check for 16bit shifted constant. We know that hi32 is
3071 non-zero, so start the mask on the first bit of the hi32
3076 unsigned long himask
, lomask
;
3080 himask
= 0xffff >> (32 - shift
);
3081 lomask
= (0xffff << shift
) & 0xffffffff;
3085 himask
= 0xffff << (shift
- 32);
3088 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3089 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3093 tmp
.X_op
= O_constant
;
3095 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3096 | (lo32
.X_add_number
>> shift
));
3098 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3099 macro_build ((char *) NULL
, counter
, &tmp
,
3100 "ori", "t,r,i", reg
, 0,
3101 (int) BFD_RELOC_LO16
);
3102 macro_build ((char *) NULL
, counter
, NULL
,
3103 (shift
>= 32) ? "dsll32" : "dsll",
3105 (shift
>= 32) ? shift
- 32 : shift
);
3110 while (shift
<= (64 - 16));
3112 /* Find the bit number of the lowest one bit, and store the
3113 shifted value in hi/lo. */
3114 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3115 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3119 while ((lo
& 1) == 0)
3124 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3130 while ((hi
& 1) == 0)
3139 /* Optimize if the shifted value is a (power of 2) - 1. */
3140 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3141 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3143 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3148 /* This instruction will set the register to be all
3150 tmp
.X_op
= O_constant
;
3151 tmp
.X_add_number
= (offsetT
) -1;
3152 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3153 reg
, 0, (int) BFD_RELOC_LO16
);
3157 macro_build ((char *) NULL
, counter
, NULL
,
3158 (bit
>= 32) ? "dsll32" : "dsll",
3160 (bit
>= 32) ? bit
- 32 : bit
);
3162 macro_build ((char *) NULL
, counter
, NULL
,
3163 (shift
>= 32) ? "dsrl32" : "dsrl",
3165 (shift
>= 32) ? shift
- 32 : shift
);
3170 /* Sign extend hi32 before calling load_register, because we can
3171 generally get better code when we load a sign extended value. */
3172 if ((hi32
.X_add_number
& 0x80000000) != 0)
3173 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3174 load_register (counter
, reg
, &hi32
, 0);
3177 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3181 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3190 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3192 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3193 (int) BFD_RELOC_HI16
);
3194 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3201 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3206 mid16
.X_add_number
>>= 16;
3207 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3208 freg
, (int) BFD_RELOC_LO16
);
3209 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3213 if ((lo32
.X_add_number
& 0xffff) != 0)
3214 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3215 (int) BFD_RELOC_LO16
);
3218 /* Load an address into a register. */
3221 load_address (counter
, reg
, ep
)
3228 if (ep
->X_op
!= O_constant
3229 && ep
->X_op
!= O_symbol
)
3231 as_bad (_("expression too complex"));
3232 ep
->X_op
= O_constant
;
3235 if (ep
->X_op
== O_constant
)
3237 load_register (counter
, reg
, ep
, 0);
3241 if (mips_pic
== NO_PIC
)
3243 /* If this is a reference to a GP relative symbol, we want
3244 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3246 lui $reg,<sym> (BFD_RELOC_HI16_S)
3247 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3248 If we have an addend, we always use the latter form. */
3249 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3250 || nopic_need_relax (ep
->X_add_symbol
, 1))
3255 macro_build ((char *) NULL
, counter
, ep
,
3256 ((bfd_arch_bits_per_address (stdoutput
) == 32
3257 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3258 ? "addiu" : "daddiu"),
3259 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3260 p
= frag_var (rs_machine_dependent
, 8, 0,
3261 RELAX_ENCODE (4, 8, 0, 4, 0,
3262 mips_opts
.warn_about_macros
),
3263 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3265 macro_build_lui (p
, counter
, ep
, reg
);
3268 macro_build (p
, counter
, ep
,
3269 ((bfd_arch_bits_per_address (stdoutput
) == 32
3270 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3271 ? "addiu" : "daddiu"),
3272 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3274 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3278 /* If this is a reference to an external symbol, we want
3279 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3281 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3283 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3284 If there is a constant, it must be added in after. */
3285 ex
.X_add_number
= ep
->X_add_number
;
3286 ep
->X_add_number
= 0;
3288 macro_build ((char *) NULL
, counter
, ep
,
3289 ((bfd_arch_bits_per_address (stdoutput
) == 32
3290 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3292 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3293 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3294 p
= frag_var (rs_machine_dependent
, 4, 0,
3295 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3296 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3297 macro_build (p
, counter
, ep
,
3298 ((bfd_arch_bits_per_address (stdoutput
) == 32
3299 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3300 ? "addiu" : "daddiu"),
3301 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3302 if (ex
.X_add_number
!= 0)
3304 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3305 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3306 ex
.X_op
= O_constant
;
3307 macro_build ((char *) NULL
, counter
, &ex
,
3308 ((bfd_arch_bits_per_address (stdoutput
) == 32
3309 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3310 ? "addiu" : "daddiu"),
3311 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3314 else if (mips_pic
== SVR4_PIC
)
3319 /* This is the large GOT case. If this is a reference to an
3320 external symbol, we want
3321 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3323 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3324 Otherwise, for a reference to a local symbol, we want
3325 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3327 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3328 If there is a constant, it must be added in after. */
3329 ex
.X_add_number
= ep
->X_add_number
;
3330 ep
->X_add_number
= 0;
3331 if (reg_needs_delay (GP
))
3336 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3337 (int) BFD_RELOC_MIPS_GOT_HI16
);
3338 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3339 ((bfd_arch_bits_per_address (stdoutput
) == 32
3340 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3341 ? "addu" : "daddu"),
3342 "d,v,t", reg
, reg
, GP
);
3343 macro_build ((char *) NULL
, counter
, ep
,
3344 ((bfd_arch_bits_per_address (stdoutput
) == 32
3345 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3347 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3348 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3349 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3350 mips_opts
.warn_about_macros
),
3351 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3354 /* We need a nop before loading from $gp. This special
3355 check is required because the lui which starts the main
3356 instruction stream does not refer to $gp, and so will not
3357 insert the nop which may be required. */
3358 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3361 macro_build (p
, counter
, ep
,
3362 ((bfd_arch_bits_per_address (stdoutput
) == 32
3363 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3365 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3367 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3369 macro_build (p
, counter
, ep
,
3370 ((bfd_arch_bits_per_address (stdoutput
) == 32
3371 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3372 ? "addiu" : "daddiu"),
3373 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3374 if (ex
.X_add_number
!= 0)
3376 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3377 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3378 ex
.X_op
= O_constant
;
3379 macro_build ((char *) NULL
, counter
, &ex
,
3380 ((bfd_arch_bits_per_address (stdoutput
) == 32
3381 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3382 ? "addiu" : "daddiu"),
3383 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3386 else if (mips_pic
== EMBEDDED_PIC
)
3389 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3391 macro_build ((char *) NULL
, counter
, ep
,
3392 ((bfd_arch_bits_per_address (stdoutput
) == 32
3393 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3394 ? "addiu" : "daddiu"),
3395 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3403 * This routine implements the seemingly endless macro or synthesized
3404 * instructions and addressing modes in the mips assembly language. Many
3405 * of these macros are simple and are similar to each other. These could
3406 * probably be handled by some kind of table or grammer aproach instead of
3407 * this verbose method. Others are not simple macros but are more like
3408 * optimizing code generation.
3409 * One interesting optimization is when several store macros appear
3410 * consecutivly that would load AT with the upper half of the same address.
3411 * The ensuing load upper instructions are ommited. This implies some kind
3412 * of global optimization. We currently only optimize within a single macro.
3413 * For many of the load and store macros if the address is specified as a
3414 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3415 * first load register 'at' with zero and use it as the base register. The
3416 * mips assembler simply uses register $zero. Just one tiny optimization
3421 struct mips_cl_insn
*ip
;
3423 register int treg
, sreg
, dreg
, breg
;
3439 bfd_reloc_code_real_type r
;
3441 int hold_mips_optimize
;
3443 assert (! mips_opts
.mips16
);
3445 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3446 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3447 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3448 mask
= ip
->insn_mo
->mask
;
3450 expr1
.X_op
= O_constant
;
3451 expr1
.X_op_symbol
= NULL
;
3452 expr1
.X_add_symbol
= NULL
;
3453 expr1
.X_add_number
= 1;
3465 mips_emit_delays (true);
3466 ++mips_opts
.noreorder
;
3467 mips_any_noreorder
= 1;
3469 expr1
.X_add_number
= 8;
3470 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3472 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3474 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3475 macro_build ((char *) NULL
, &icnt
, NULL
,
3476 dbl
? "dsub" : "sub",
3477 "d,v,t", dreg
, 0, sreg
);
3479 --mips_opts
.noreorder
;
3500 if (imm_expr
.X_op
== O_constant
3501 && imm_expr
.X_add_number
>= -0x8000
3502 && imm_expr
.X_add_number
< 0x8000)
3504 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3505 (int) BFD_RELOC_LO16
);
3508 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3509 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3528 if (imm_expr
.X_op
== O_constant
3529 && imm_expr
.X_add_number
>= 0
3530 && imm_expr
.X_add_number
< 0x10000)
3532 if (mask
!= M_NOR_I
)
3533 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3534 sreg
, (int) BFD_RELOC_LO16
);
3537 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3538 treg
, sreg
, (int) BFD_RELOC_LO16
);
3539 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3545 load_register (&icnt
, AT
, &imm_expr
, 0);
3546 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3563 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3565 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3569 load_register (&icnt
, AT
, &imm_expr
, 0);
3570 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3578 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3579 likely
? "bgezl" : "bgez",
3585 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3586 likely
? "blezl" : "blez",
3590 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3591 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3592 likely
? "beql" : "beq",
3599 /* check for > max integer */
3600 maxnum
= 0x7fffffff;
3601 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3608 if (imm_expr
.X_op
== O_constant
3609 && imm_expr
.X_add_number
>= maxnum
3610 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3613 /* result is always false */
3616 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3617 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3621 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3622 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3627 if (imm_expr
.X_op
!= O_constant
)
3628 as_bad (_("Unsupported large constant"));
3629 imm_expr
.X_add_number
++;
3633 if (mask
== M_BGEL_I
)
3635 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3637 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3638 likely
? "bgezl" : "bgez",
3642 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3644 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3645 likely
? "bgtzl" : "bgtz",
3649 maxnum
= 0x7fffffff;
3650 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3657 maxnum
= - maxnum
- 1;
3658 if (imm_expr
.X_op
== O_constant
3659 && imm_expr
.X_add_number
<= maxnum
3660 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3663 /* result is always true */
3664 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3668 set_at (&icnt
, sreg
, 0);
3669 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3670 likely
? "beql" : "beq",
3681 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3682 likely
? "beql" : "beq",
3686 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3688 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3689 likely
? "beql" : "beq",
3697 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3698 && imm_expr
.X_op
== O_constant
3699 && imm_expr
.X_add_number
== 0xffffffff))
3701 if (imm_expr
.X_op
!= O_constant
)
3702 as_bad (_("Unsupported large constant"));
3703 imm_expr
.X_add_number
++;
3707 if (mask
== M_BGEUL_I
)
3709 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3711 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3713 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3714 likely
? "bnel" : "bne",
3718 set_at (&icnt
, sreg
, 1);
3719 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3720 likely
? "beql" : "beq",
3729 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3730 likely
? "bgtzl" : "bgtz",
3736 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3737 likely
? "bltzl" : "bltz",
3741 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3742 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3743 likely
? "bnel" : "bne",
3752 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3753 likely
? "bnel" : "bne",
3759 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3761 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3762 likely
? "bnel" : "bne",
3771 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3772 likely
? "blezl" : "blez",
3778 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3779 likely
? "bgezl" : "bgez",
3783 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3784 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3785 likely
? "beql" : "beq",
3792 maxnum
= 0x7fffffff;
3793 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3800 if (imm_expr
.X_op
== O_constant
3801 && imm_expr
.X_add_number
>= maxnum
3802 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3804 if (imm_expr
.X_op
!= O_constant
)
3805 as_bad (_("Unsupported large constant"));
3806 imm_expr
.X_add_number
++;
3810 if (mask
== M_BLTL_I
)
3812 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3814 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3815 likely
? "bltzl" : "bltz",
3819 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3821 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3822 likely
? "blezl" : "blez",
3826 set_at (&icnt
, sreg
, 0);
3827 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3828 likely
? "bnel" : "bne",
3837 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3838 likely
? "beql" : "beq",
3844 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3846 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3847 likely
? "beql" : "beq",
3855 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3856 && imm_expr
.X_op
== O_constant
3857 && imm_expr
.X_add_number
== 0xffffffff))
3859 if (imm_expr
.X_op
!= O_constant
)
3860 as_bad (_("Unsupported large constant"));
3861 imm_expr
.X_add_number
++;
3865 if (mask
== M_BLTUL_I
)
3867 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3869 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3871 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3872 likely
? "beql" : "beq",
3876 set_at (&icnt
, sreg
, 1);
3877 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3878 likely
? "bnel" : "bne",
3887 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3888 likely
? "bltzl" : "bltz",
3894 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3895 likely
? "bgtzl" : "bgtz",
3899 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3900 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3901 likely
? "bnel" : "bne",
3912 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3913 likely
? "bnel" : "bne",
3917 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3919 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3920 likely
? "bnel" : "bne",
3936 as_warn (_("Divide by zero."));
3938 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3940 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3944 mips_emit_delays (true);
3945 ++mips_opts
.noreorder
;
3946 mips_any_noreorder
= 1;
3949 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3950 macro_build ((char *) NULL
, &icnt
, NULL
,
3951 dbl
? "ddiv" : "div",
3952 "z,s,t", sreg
, treg
);
3956 expr1
.X_add_number
= 8;
3957 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3958 macro_build ((char *) NULL
, &icnt
, NULL
,
3959 dbl
? "ddiv" : "div",
3960 "z,s,t", sreg
, treg
);
3961 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3963 expr1
.X_add_number
= -1;
3964 macro_build ((char *) NULL
, &icnt
, &expr1
,
3965 dbl
? "daddiu" : "addiu",
3966 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3967 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3968 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3971 expr1
.X_add_number
= 1;
3972 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3973 (int) BFD_RELOC_LO16
);
3974 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3979 expr1
.X_add_number
= 0x80000000;
3980 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3981 (int) BFD_RELOC_HI16
);
3985 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3986 /* We want to close the noreorder block as soon as possible, so
3987 that later insns are available for delay slot filling. */
3988 --mips_opts
.noreorder
;
3992 expr1
.X_add_number
= 8;
3993 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3994 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3996 /* We want to close the noreorder block as soon as possible, so
3997 that later insns are available for delay slot filling. */
3998 --mips_opts
.noreorder
;
4000 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4002 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4041 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4043 as_warn (_("Divide by zero."));
4045 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4047 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4050 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4052 if (strcmp (s2
, "mflo") == 0)
4053 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4056 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4059 if (imm_expr
.X_op
== O_constant
4060 && imm_expr
.X_add_number
== -1
4061 && s
[strlen (s
) - 1] != 'u')
4063 if (strcmp (s2
, "mflo") == 0)
4066 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4069 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4073 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4077 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4078 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4079 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4098 mips_emit_delays (true);
4099 ++mips_opts
.noreorder
;
4100 mips_any_noreorder
= 1;
4103 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4104 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4105 /* We want to close the noreorder block as soon as possible, so
4106 that later insns are available for delay slot filling. */
4107 --mips_opts
.noreorder
;
4111 expr1
.X_add_number
= 8;
4112 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4113 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4115 /* We want to close the noreorder block as soon as possible, so
4116 that later insns are available for delay slot filling. */
4117 --mips_opts
.noreorder
;
4118 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4120 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4126 /* Load the address of a symbol into a register. If breg is not
4127 zero, we then add a base register to it. */
4129 /* When generating embedded PIC code, we permit expressions of
4132 where bar is an address in the current section. These are used
4133 when getting the addresses of functions. We don't permit
4134 X_add_number to be non-zero, because if the symbol is
4135 external the relaxing code needs to know that any addend is
4136 purely the offset to X_op_symbol. */
4137 if (mips_pic
== EMBEDDED_PIC
4138 && offset_expr
.X_op
== O_subtract
4139 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4140 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4141 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4143 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4147 && (offset_expr
.X_add_number
== 0
4148 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4150 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4151 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4152 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4153 ((bfd_arch_bits_per_address (stdoutput
) == 32
4154 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4155 ? "addiu" : "daddiu"),
4156 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4160 if (offset_expr
.X_op
!= O_symbol
4161 && offset_expr
.X_op
!= O_constant
)
4163 as_bad (_("expression too complex"));
4164 offset_expr
.X_op
= O_constant
;
4178 if (offset_expr
.X_op
== O_constant
)
4179 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4180 else if (mips_pic
== NO_PIC
)
4182 /* If this is a reference to an GP relative symbol, we want
4183 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4185 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4186 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4187 If we have a constant, we need two instructions anyhow,
4188 so we may as well always use the latter form. */
4189 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4190 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4195 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4196 ((bfd_arch_bits_per_address (stdoutput
) == 32
4197 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4198 ? "addiu" : "daddiu"),
4199 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4200 p
= frag_var (rs_machine_dependent
, 8, 0,
4201 RELAX_ENCODE (4, 8, 0, 4, 0,
4202 mips_opts
.warn_about_macros
),
4203 offset_expr
.X_add_symbol
, (offsetT
) 0,
4206 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4209 macro_build (p
, &icnt
, &offset_expr
,
4210 ((bfd_arch_bits_per_address (stdoutput
) == 32
4211 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4212 ? "addiu" : "daddiu"),
4213 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4215 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4217 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4219 /* If this is a reference to an external symbol, and there
4220 is no constant, we want
4221 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4222 or if tempreg is PIC_CALL_REG
4223 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4224 For a local symbol, we want
4225 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4227 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4229 If we have a small constant, and this is a reference to
4230 an external symbol, we want
4231 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4233 addiu $tempreg,$tempreg,<constant>
4234 For a local symbol, we want the same instruction
4235 sequence, but we output a BFD_RELOC_LO16 reloc on the
4238 If we have a large constant, and this is a reference to
4239 an external symbol, we want
4240 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4241 lui $at,<hiconstant>
4242 addiu $at,$at,<loconstant>
4243 addu $tempreg,$tempreg,$at
4244 For a local symbol, we want the same instruction
4245 sequence, but we output a BFD_RELOC_LO16 reloc on the
4246 addiu instruction. */
4247 expr1
.X_add_number
= offset_expr
.X_add_number
;
4248 offset_expr
.X_add_number
= 0;
4250 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4251 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4252 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4254 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4255 if (expr1
.X_add_number
== 0)
4263 /* We're going to put in an addu instruction using
4264 tempreg, so we may as well insert the nop right
4266 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4270 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4271 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4273 ? mips_opts
.warn_about_macros
4275 offset_expr
.X_add_symbol
, (offsetT
) 0,
4279 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4282 macro_build (p
, &icnt
, &expr1
,
4283 ((bfd_arch_bits_per_address (stdoutput
) == 32
4284 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4285 ? "addiu" : "daddiu"),
4286 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4287 /* FIXME: If breg == 0, and the next instruction uses
4288 $tempreg, then if this variant case is used an extra
4289 nop will be generated. */
4291 else if (expr1
.X_add_number
>= -0x8000
4292 && expr1
.X_add_number
< 0x8000)
4294 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4296 macro_build ((char *) NULL
, &icnt
, &expr1
,
4297 ((bfd_arch_bits_per_address (stdoutput
) == 32
4298 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4299 ? "addiu" : "daddiu"),
4300 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4301 (void) frag_var (rs_machine_dependent
, 0, 0,
4302 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4303 offset_expr
.X_add_symbol
, (offsetT
) 0,
4310 /* If we are going to add in a base register, and the
4311 target register and the base register are the same,
4312 then we are using AT as a temporary register. Since
4313 we want to load the constant into AT, we add our
4314 current AT (from the global offset table) and the
4315 register into the register now, and pretend we were
4316 not using a base register. */
4321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4323 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4324 ((bfd_arch_bits_per_address (stdoutput
) == 32
4325 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4326 ? "addu" : "daddu"),
4327 "d,v,t", treg
, AT
, breg
);
4333 /* Set mips_optimize around the lui instruction to avoid
4334 inserting an unnecessary nop after the lw. */
4335 hold_mips_optimize
= mips_optimize
;
4337 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4338 mips_optimize
= hold_mips_optimize
;
4340 macro_build ((char *) NULL
, &icnt
, &expr1
,
4341 ((bfd_arch_bits_per_address (stdoutput
) == 32
4342 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4343 ? "addiu" : "daddiu"),
4344 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4346 ((bfd_arch_bits_per_address (stdoutput
) == 32
4347 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4348 ? "addu" : "daddu"),
4349 "d,v,t", tempreg
, tempreg
, AT
);
4350 (void) frag_var (rs_machine_dependent
, 0, 0,
4351 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4352 offset_expr
.X_add_symbol
, (offsetT
) 0,
4357 else if (mips_pic
== SVR4_PIC
)
4360 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4361 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4363 /* This is the large GOT case. If this is a reference to an
4364 external symbol, and there is no constant, we want
4365 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4366 addu $tempreg,$tempreg,$gp
4367 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4368 or if tempreg is PIC_CALL_REG
4369 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4370 addu $tempreg,$tempreg,$gp
4371 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4372 For a local symbol, we want
4373 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4375 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4377 If we have a small constant, and this is a reference to
4378 an external symbol, we want
4379 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4380 addu $tempreg,$tempreg,$gp
4381 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4383 addiu $tempreg,$tempreg,<constant>
4384 For a local symbol, we want
4385 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4387 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4389 If we have a large constant, and this is a reference to
4390 an external symbol, we want
4391 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4392 addu $tempreg,$tempreg,$gp
4393 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4394 lui $at,<hiconstant>
4395 addiu $at,$at,<loconstant>
4396 addu $tempreg,$tempreg,$at
4397 For a local symbol, we want
4398 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4399 lui $at,<hiconstant>
4400 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4401 addu $tempreg,$tempreg,$at
4403 expr1
.X_add_number
= offset_expr
.X_add_number
;
4404 offset_expr
.X_add_number
= 0;
4406 if (reg_needs_delay (GP
))
4410 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4412 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4413 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4415 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4416 tempreg
, lui_reloc_type
);
4417 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4418 ((bfd_arch_bits_per_address (stdoutput
) == 32
4419 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4420 ? "addu" : "daddu"),
4421 "d,v,t", tempreg
, tempreg
, GP
);
4422 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4424 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4425 if (expr1
.X_add_number
== 0)
4433 /* We're going to put in an addu instruction using
4434 tempreg, so we may as well insert the nop right
4436 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4441 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4442 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4445 ? mips_opts
.warn_about_macros
4447 offset_expr
.X_add_symbol
, (offsetT
) 0,
4450 else if (expr1
.X_add_number
>= -0x8000
4451 && expr1
.X_add_number
< 0x8000)
4453 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4455 macro_build ((char *) NULL
, &icnt
, &expr1
,
4456 ((bfd_arch_bits_per_address (stdoutput
) == 32
4457 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4458 ? "addiu" : "daddiu"),
4459 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4461 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4462 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4464 ? mips_opts
.warn_about_macros
4466 offset_expr
.X_add_symbol
, (offsetT
) 0,
4473 /* If we are going to add in a base register, and the
4474 target register and the base register are the same,
4475 then we are using AT as a temporary register. Since
4476 we want to load the constant into AT, we add our
4477 current AT (from the global offset table) and the
4478 register into the register now, and pretend we were
4479 not using a base register. */
4487 assert (tempreg
== AT
);
4488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4490 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4491 ((bfd_arch_bits_per_address (stdoutput
) == 32
4492 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4493 ? "addu" : "daddu"),
4494 "d,v,t", treg
, AT
, breg
);
4499 /* Set mips_optimize around the lui instruction to avoid
4500 inserting an unnecessary nop after the lw. */
4501 hold_mips_optimize
= mips_optimize
;
4503 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4504 mips_optimize
= hold_mips_optimize
;
4506 macro_build ((char *) NULL
, &icnt
, &expr1
,
4507 ((bfd_arch_bits_per_address (stdoutput
) == 32
4508 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4509 ? "addiu" : "daddiu"),
4510 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4511 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4512 ((bfd_arch_bits_per_address (stdoutput
) == 32
4513 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4514 ? "addu" : "daddu"),
4515 "d,v,t", dreg
, dreg
, AT
);
4517 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4518 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4521 ? mips_opts
.warn_about_macros
4523 offset_expr
.X_add_symbol
, (offsetT
) 0,
4531 /* This is needed because this instruction uses $gp, but
4532 the first instruction on the main stream does not. */
4533 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4536 macro_build (p
, &icnt
, &offset_expr
,
4538 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4540 if (expr1
.X_add_number
>= -0x8000
4541 && expr1
.X_add_number
< 0x8000)
4543 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4545 macro_build (p
, &icnt
, &expr1
,
4546 ((bfd_arch_bits_per_address (stdoutput
) == 32
4547 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4548 ? "addiu" : "daddiu"),
4549 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4550 /* FIXME: If add_number is 0, and there was no base
4551 register, the external symbol case ended with a load,
4552 so if the symbol turns out to not be external, and
4553 the next instruction uses tempreg, an unnecessary nop
4554 will be inserted. */
4560 /* We must add in the base register now, as in the
4561 external symbol case. */
4562 assert (tempreg
== AT
);
4563 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4565 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4566 ((bfd_arch_bits_per_address (stdoutput
) == 32
4567 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4568 ? "addu" : "daddu"),
4569 "d,v,t", treg
, AT
, breg
);
4572 /* We set breg to 0 because we have arranged to add
4573 it in in both cases. */
4577 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4579 macro_build (p
, &icnt
, &expr1
,
4580 ((bfd_arch_bits_per_address (stdoutput
) == 32
4581 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4582 ? "addiu" : "daddiu"),
4583 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4585 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4586 ((bfd_arch_bits_per_address (stdoutput
) == 32
4587 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4588 ? "addu" : "daddu"),
4589 "d,v,t", tempreg
, tempreg
, AT
);
4593 else if (mips_pic
== EMBEDDED_PIC
)
4596 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4598 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4599 ((bfd_arch_bits_per_address (stdoutput
) == 32
4600 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4601 ? "addiu" : "daddiu"),
4602 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4608 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4609 ((bfd_arch_bits_per_address (stdoutput
) == 32
4610 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4611 ? "addu" : "daddu"),
4612 "d,v,t", treg
, tempreg
, breg
);
4620 /* The j instruction may not be used in PIC code, since it
4621 requires an absolute address. We convert it to a b
4623 if (mips_pic
== NO_PIC
)
4624 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4626 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4629 /* The jal instructions must be handled as macros because when
4630 generating PIC code they expand to multi-instruction
4631 sequences. Normally they are simple instructions. */
4636 if (mips_pic
== NO_PIC
4637 || mips_pic
== EMBEDDED_PIC
)
4638 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4640 else if (mips_pic
== SVR4_PIC
)
4642 if (sreg
!= PIC_CALL_REG
)
4643 as_warn (_("MIPS PIC call to register other than $25"));
4645 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4647 if (mips_cprestore_offset
< 0)
4648 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4651 expr1
.X_add_number
= mips_cprestore_offset
;
4652 macro_build ((char *) NULL
, &icnt
, &expr1
,
4653 ((bfd_arch_bits_per_address (stdoutput
) == 32
4654 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4656 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4665 if (mips_pic
== NO_PIC
)
4666 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4667 else if (mips_pic
== SVR4_PIC
)
4669 /* If this is a reference to an external symbol, and we are
4670 using a small GOT, we want
4671 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4675 lw $gp,cprestore($sp)
4676 The cprestore value is set using the .cprestore
4677 pseudo-op. If we are using a big GOT, we want
4678 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4680 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4684 lw $gp,cprestore($sp)
4685 If the symbol is not external, we want
4686 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4688 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4691 lw $gp,cprestore($sp) */
4695 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4696 ((bfd_arch_bits_per_address (stdoutput
) == 32
4697 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4699 "t,o(b)", PIC_CALL_REG
,
4700 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4701 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4703 p
= frag_var (rs_machine_dependent
, 4, 0,
4704 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4705 offset_expr
.X_add_symbol
, (offsetT
) 0,
4712 if (reg_needs_delay (GP
))
4716 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4717 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4718 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4719 ((bfd_arch_bits_per_address (stdoutput
) == 32
4720 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4721 ? "addu" : "daddu"),
4722 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4723 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4724 ((bfd_arch_bits_per_address (stdoutput
) == 32
4725 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4727 "t,o(b)", PIC_CALL_REG
,
4728 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4729 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4731 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4732 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4734 offset_expr
.X_add_symbol
, (offsetT
) 0,
4738 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4741 macro_build (p
, &icnt
, &offset_expr
,
4742 ((bfd_arch_bits_per_address (stdoutput
) == 32
4743 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4745 "t,o(b)", PIC_CALL_REG
,
4746 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4748 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4751 macro_build (p
, &icnt
, &offset_expr
,
4752 ((bfd_arch_bits_per_address (stdoutput
) == 32
4753 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4754 ? "addiu" : "daddiu"),
4755 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4756 (int) BFD_RELOC_LO16
);
4757 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4758 "jalr", "s", PIC_CALL_REG
);
4759 if (mips_cprestore_offset
< 0)
4760 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4763 if (mips_opts
.noreorder
)
4764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4766 expr1
.X_add_number
= mips_cprestore_offset
;
4767 macro_build ((char *) NULL
, &icnt
, &expr1
,
4768 ((bfd_arch_bits_per_address (stdoutput
) == 32
4769 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4771 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4775 else if (mips_pic
== EMBEDDED_PIC
)
4777 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4778 /* The linker may expand the call to a longer sequence which
4779 uses $at, so we must break rather than return. */
4804 /* Itbl support may require additional care here. */
4809 /* Itbl support may require additional care here. */
4814 /* Itbl support may require additional care here. */
4819 /* Itbl support may require additional care here. */
4831 if (mips_cpu
== CPU_R4650
)
4833 as_bad (_("opcode not supported on this processor"));
4837 /* Itbl support may require additional care here. */
4842 /* Itbl support may require additional care here. */
4847 /* Itbl support may require additional care here. */
4867 if (breg
== treg
|| coproc
|| lr
)
4889 /* Itbl support may require additional care here. */
4894 /* Itbl support may require additional care here. */
4899 /* Itbl support may require additional care here. */
4904 /* Itbl support may require additional care here. */
4920 if (mips_cpu
== CPU_R4650
)
4922 as_bad (_("opcode not supported on this processor"));
4927 /* Itbl support may require additional care here. */
4931 /* Itbl support may require additional care here. */
4936 /* Itbl support may require additional care here. */
4948 /* Itbl support may require additional care here. */
4949 if (mask
== M_LWC1_AB
4950 || mask
== M_SWC1_AB
4951 || mask
== M_LDC1_AB
4952 || mask
== M_SDC1_AB
4961 if (offset_expr
.X_op
!= O_constant
4962 && offset_expr
.X_op
!= O_symbol
)
4964 as_bad (_("expression too complex"));
4965 offset_expr
.X_op
= O_constant
;
4968 /* A constant expression in PIC code can be handled just as it
4969 is in non PIC code. */
4970 if (mips_pic
== NO_PIC
4971 || offset_expr
.X_op
== O_constant
)
4973 /* If this is a reference to a GP relative symbol, and there
4974 is no base register, we want
4975 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4976 Otherwise, if there is no base register, we want
4977 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4978 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4979 If we have a constant, we need two instructions anyhow,
4980 so we always use the latter form.
4982 If we have a base register, and this is a reference to a
4983 GP relative symbol, we want
4984 addu $tempreg,$breg,$gp
4985 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4987 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4988 addu $tempreg,$tempreg,$breg
4989 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4990 With a constant we always use the latter case. */
4993 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4994 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4999 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5000 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5001 p
= frag_var (rs_machine_dependent
, 8, 0,
5002 RELAX_ENCODE (4, 8, 0, 4, 0,
5003 (mips_opts
.warn_about_macros
5005 && mips_opts
.noat
))),
5006 offset_expr
.X_add_symbol
, (offsetT
) 0,
5010 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5013 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5014 (int) BFD_RELOC_LO16
, tempreg
);
5018 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5019 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5024 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5025 ((bfd_arch_bits_per_address (stdoutput
) == 32
5026 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5027 ? "addu" : "daddu"),
5028 "d,v,t", tempreg
, breg
, GP
);
5029 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5030 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5031 p
= frag_var (rs_machine_dependent
, 12, 0,
5032 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5033 offset_expr
.X_add_symbol
, (offsetT
) 0,
5036 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5039 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5040 ((bfd_arch_bits_per_address (stdoutput
) == 32
5041 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5042 ? "addu" : "daddu"),
5043 "d,v,t", tempreg
, tempreg
, breg
);
5046 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5047 (int) BFD_RELOC_LO16
, tempreg
);
5050 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5052 /* If this is a reference to an external symbol, we want
5053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5055 <op> $treg,0($tempreg)
5057 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5059 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5060 <op> $treg,0($tempreg)
5061 If there is a base register, we add it to $tempreg before
5062 the <op>. If there is a constant, we stick it in the
5063 <op> instruction. We don't handle constants larger than
5064 16 bits, because we have no way to load the upper 16 bits
5065 (actually, we could handle them for the subset of cases
5066 in which we are not using $at). */
5067 assert (offset_expr
.X_op
== O_symbol
);
5068 expr1
.X_add_number
= offset_expr
.X_add_number
;
5069 offset_expr
.X_add_number
= 0;
5070 if (expr1
.X_add_number
< -0x8000
5071 || expr1
.X_add_number
>= 0x8000)
5072 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5074 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5075 ((bfd_arch_bits_per_address (stdoutput
) == 32
5076 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5078 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5079 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5080 p
= frag_var (rs_machine_dependent
, 4, 0,
5081 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5082 offset_expr
.X_add_symbol
, (offsetT
) 0,
5084 macro_build (p
, &icnt
, &offset_expr
,
5085 ((bfd_arch_bits_per_address (stdoutput
) == 32
5086 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5087 ? "addiu" : "daddiu"),
5088 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5090 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5091 ((bfd_arch_bits_per_address (stdoutput
) == 32
5092 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5093 ? "addu" : "daddu"),
5094 "d,v,t", tempreg
, tempreg
, breg
);
5095 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5096 (int) BFD_RELOC_LO16
, tempreg
);
5098 else if (mips_pic
== SVR4_PIC
)
5102 /* If this is a reference to an external symbol, we want
5103 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5104 addu $tempreg,$tempreg,$gp
5105 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5106 <op> $treg,0($tempreg)
5108 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5110 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5111 <op> $treg,0($tempreg)
5112 If there is a base register, we add it to $tempreg before
5113 the <op>. If there is a constant, we stick it in the
5114 <op> instruction. We don't handle constants larger than
5115 16 bits, because we have no way to load the upper 16 bits
5116 (actually, we could handle them for the subset of cases
5117 in which we are not using $at). */
5118 assert (offset_expr
.X_op
== O_symbol
);
5119 expr1
.X_add_number
= offset_expr
.X_add_number
;
5120 offset_expr
.X_add_number
= 0;
5121 if (expr1
.X_add_number
< -0x8000
5122 || expr1
.X_add_number
>= 0x8000)
5123 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5124 if (reg_needs_delay (GP
))
5129 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5130 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5132 ((bfd_arch_bits_per_address (stdoutput
) == 32
5133 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5134 ? "addu" : "daddu"),
5135 "d,v,t", tempreg
, tempreg
, GP
);
5136 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5137 ((bfd_arch_bits_per_address (stdoutput
) == 32
5138 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5140 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5142 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5143 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5144 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5147 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5150 macro_build (p
, &icnt
, &offset_expr
,
5151 ((bfd_arch_bits_per_address (stdoutput
) == 32
5152 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5154 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5156 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5158 macro_build (p
, &icnt
, &offset_expr
,
5159 ((bfd_arch_bits_per_address (stdoutput
) == 32
5160 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5161 ? "addiu" : "daddiu"),
5162 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5164 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5165 ((bfd_arch_bits_per_address (stdoutput
) == 32
5166 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5167 ? "addu" : "daddu"),
5168 "d,v,t", tempreg
, tempreg
, breg
);
5169 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5170 (int) BFD_RELOC_LO16
, tempreg
);
5172 else if (mips_pic
== EMBEDDED_PIC
)
5174 /* If there is no base register, we want
5175 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5176 If there is a base register, we want
5177 addu $tempreg,$breg,$gp
5178 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5180 assert (offset_expr
.X_op
== O_symbol
);
5183 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5184 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5190 ((bfd_arch_bits_per_address (stdoutput
) == 32
5191 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5192 ? "addu" : "daddu"),
5193 "d,v,t", tempreg
, breg
, GP
);
5194 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5195 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5208 load_register (&icnt
, treg
, &imm_expr
, 0);
5212 load_register (&icnt
, treg
, &imm_expr
, 1);
5216 if (imm_expr
.X_op
== O_constant
)
5218 load_register (&icnt
, AT
, &imm_expr
, 0);
5219 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5220 "mtc1", "t,G", AT
, treg
);
5225 assert (offset_expr
.X_op
== O_symbol
5226 && strcmp (segment_name (S_GET_SEGMENT
5227 (offset_expr
.X_add_symbol
)),
5229 && offset_expr
.X_add_number
== 0);
5230 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5231 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5236 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5237 the entire value, and in mips1 mode it is the high order 32
5238 bits of the value and the low order 32 bits are either zero
5239 or in offset_expr. */
5240 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5242 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5243 load_register (&icnt
, treg
, &imm_expr
, 1);
5248 if (target_big_endian
)
5260 load_register (&icnt
, hreg
, &imm_expr
, 0);
5263 if (offset_expr
.X_op
== O_absent
)
5264 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5268 assert (offset_expr
.X_op
== O_constant
);
5269 load_register (&icnt
, lreg
, &offset_expr
, 0);
5276 /* We know that sym is in the .rdata section. First we get the
5277 upper 16 bits of the address. */
5278 if (mips_pic
== NO_PIC
)
5280 /* FIXME: This won't work for a 64 bit address. */
5281 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5283 else if (mips_pic
== SVR4_PIC
)
5285 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5286 ((bfd_arch_bits_per_address (stdoutput
) == 32
5287 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5289 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5291 else if (mips_pic
== EMBEDDED_PIC
)
5293 /* For embedded PIC we pick up the entire address off $gp in
5294 a single instruction. */
5295 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5296 ((bfd_arch_bits_per_address (stdoutput
) == 32
5297 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5298 ? "addiu" : "daddiu"),
5299 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5300 offset_expr
.X_op
= O_constant
;
5301 offset_expr
.X_add_number
= 0;
5306 /* Now we load the register(s). */
5307 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5308 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5309 treg
, (int) BFD_RELOC_LO16
, AT
);
5312 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5313 treg
, (int) BFD_RELOC_LO16
, AT
);
5316 /* FIXME: How in the world do we deal with the possible
5318 offset_expr
.X_add_number
+= 4;
5319 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5320 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5324 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5325 does not become a variant frag. */
5326 frag_wane (frag_now
);
5332 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5333 the entire value, and in mips1 mode it is the high order 32
5334 bits of the value and the low order 32 bits are either zero
5335 or in offset_expr. */
5336 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5338 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5339 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5340 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5341 "dmtc1", "t,S", AT
, treg
);
5344 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5345 "mtc1", "t,G", AT
, treg
+ 1);
5346 if (offset_expr
.X_op
== O_absent
)
5347 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5348 "mtc1", "t,G", 0, treg
);
5351 assert (offset_expr
.X_op
== O_constant
);
5352 load_register (&icnt
, AT
, &offset_expr
, 0);
5353 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5354 "mtc1", "t,G", AT
, treg
);
5360 assert (offset_expr
.X_op
== O_symbol
5361 && offset_expr
.X_add_number
== 0);
5362 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5363 if (strcmp (s
, ".lit8") == 0)
5365 if (mips_opts
.isa
!= ISA_MIPS1
)
5367 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5368 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5372 r
= BFD_RELOC_MIPS_LITERAL
;
5377 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5378 if (mips_pic
== SVR4_PIC
)
5379 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5380 ((bfd_arch_bits_per_address (stdoutput
) == 32
5381 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5383 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5386 /* FIXME: This won't work for a 64 bit address. */
5387 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5390 if (mips_opts
.isa
!= ISA_MIPS1
)
5392 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5393 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5395 /* To avoid confusion in tc_gen_reloc, we must ensure
5396 that this does not become a variant frag. */
5397 frag_wane (frag_now
);
5408 if (mips_cpu
== CPU_R4650
)
5410 as_bad (_("opcode not supported on this processor"));
5413 /* Even on a big endian machine $fn comes before $fn+1. We have
5414 to adjust when loading from memory. */
5417 assert (mips_opts
.isa
== ISA_MIPS1
);
5418 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5419 target_big_endian
? treg
+ 1 : treg
,
5421 /* FIXME: A possible overflow which I don't know how to deal
5423 offset_expr
.X_add_number
+= 4;
5424 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5425 target_big_endian
? treg
: treg
+ 1,
5428 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5429 does not become a variant frag. */
5430 frag_wane (frag_now
);
5439 * The MIPS assembler seems to check for X_add_number not
5440 * being double aligned and generating:
5443 * addiu at,at,%lo(foo+1)
5446 * But, the resulting address is the same after relocation so why
5447 * generate the extra instruction?
5449 if (mips_cpu
== CPU_R4650
)
5451 as_bad (_("opcode not supported on this processor"));
5454 /* Itbl support may require additional care here. */
5456 if (mips_opts
.isa
!= ISA_MIPS1
)
5467 if (mips_cpu
== CPU_R4650
)
5469 as_bad (_("opcode not supported on this processor"));
5473 if (mips_opts
.isa
!= ISA_MIPS1
)
5481 /* Itbl support may require additional care here. */
5486 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5497 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5507 if (offset_expr
.X_op
!= O_symbol
5508 && offset_expr
.X_op
!= O_constant
)
5510 as_bad (_("expression too complex"));
5511 offset_expr
.X_op
= O_constant
;
5514 /* Even on a big endian machine $fn comes before $fn+1. We have
5515 to adjust when loading from memory. We set coproc if we must
5516 load $fn+1 first. */
5517 /* Itbl support may require additional care here. */
5518 if (! target_big_endian
)
5521 if (mips_pic
== NO_PIC
5522 || offset_expr
.X_op
== O_constant
)
5524 /* If this is a reference to a GP relative symbol, we want
5525 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5526 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5527 If we have a base register, we use this
5529 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5530 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5531 If this is not a GP relative symbol, we want
5532 lui $at,<sym> (BFD_RELOC_HI16_S)
5533 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5534 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5535 If there is a base register, we add it to $at after the
5536 lui instruction. If there is a constant, we always use
5538 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5539 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5558 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5559 ((bfd_arch_bits_per_address (stdoutput
) == 32
5560 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5561 ? "addu" : "daddu"),
5562 "d,v,t", AT
, breg
, GP
);
5568 /* Itbl support may require additional care here. */
5569 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5570 coproc
? treg
+ 1 : treg
,
5571 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5572 offset_expr
.X_add_number
+= 4;
5574 /* Set mips_optimize to 2 to avoid inserting an
5576 hold_mips_optimize
= mips_optimize
;
5578 /* Itbl support may require additional care here. */
5579 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5580 coproc
? treg
: treg
+ 1,
5581 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5582 mips_optimize
= hold_mips_optimize
;
5584 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5585 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5586 used_at
&& mips_opts
.noat
),
5587 offset_expr
.X_add_symbol
, (offsetT
) 0,
5590 /* We just generated two relocs. When tc_gen_reloc
5591 handles this case, it will skip the first reloc and
5592 handle the second. The second reloc already has an
5593 extra addend of 4, which we added above. We must
5594 subtract it out, and then subtract another 4 to make
5595 the first reloc come out right. The second reloc
5596 will come out right because we are going to add 4 to
5597 offset_expr when we build its instruction below.
5599 If we have a symbol, then we don't want to include
5600 the offset, because it will wind up being included
5601 when we generate the reloc. */
5603 if (offset_expr
.X_op
== O_constant
)
5604 offset_expr
.X_add_number
-= 8;
5607 offset_expr
.X_add_number
= -4;
5608 offset_expr
.X_op
= O_constant
;
5611 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5616 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5617 ((bfd_arch_bits_per_address (stdoutput
) == 32
5618 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5619 ? "addu" : "daddu"),
5620 "d,v,t", AT
, breg
, AT
);
5624 /* Itbl support may require additional care here. */
5625 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5626 coproc
? treg
+ 1 : treg
,
5627 (int) BFD_RELOC_LO16
, AT
);
5630 /* FIXME: How do we handle overflow here? */
5631 offset_expr
.X_add_number
+= 4;
5632 /* Itbl support may require additional care here. */
5633 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5634 coproc
? treg
: treg
+ 1,
5635 (int) BFD_RELOC_LO16
, AT
);
5637 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5641 /* If this is a reference to an external symbol, we want
5642 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5647 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5649 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5650 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5651 If there is a base register we add it to $at before the
5652 lwc1 instructions. If there is a constant we include it
5653 in the lwc1 instructions. */
5655 expr1
.X_add_number
= offset_expr
.X_add_number
;
5656 offset_expr
.X_add_number
= 0;
5657 if (expr1
.X_add_number
< -0x8000
5658 || expr1
.X_add_number
>= 0x8000 - 4)
5659 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5664 frag_grow (24 + off
);
5665 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5666 ((bfd_arch_bits_per_address (stdoutput
) == 32
5667 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5669 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5670 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5672 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5673 ((bfd_arch_bits_per_address (stdoutput
) == 32
5674 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5675 ? "addu" : "daddu"),
5676 "d,v,t", AT
, breg
, AT
);
5677 /* Itbl support may require additional care here. */
5678 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5679 coproc
? treg
+ 1 : treg
,
5680 (int) BFD_RELOC_LO16
, AT
);
5681 expr1
.X_add_number
+= 4;
5683 /* Set mips_optimize to 2 to avoid inserting an undesired
5685 hold_mips_optimize
= mips_optimize
;
5687 /* Itbl support may require additional care here. */
5688 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5689 coproc
? treg
: treg
+ 1,
5690 (int) BFD_RELOC_LO16
, AT
);
5691 mips_optimize
= hold_mips_optimize
;
5693 (void) frag_var (rs_machine_dependent
, 0, 0,
5694 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5695 offset_expr
.X_add_symbol
, (offsetT
) 0,
5698 else if (mips_pic
== SVR4_PIC
)
5702 /* If this is a reference to an external symbol, we want
5703 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5705 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5710 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5712 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5713 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5714 If there is a base register we add it to $at before the
5715 lwc1 instructions. If there is a constant we include it
5716 in the lwc1 instructions. */
5718 expr1
.X_add_number
= offset_expr
.X_add_number
;
5719 offset_expr
.X_add_number
= 0;
5720 if (expr1
.X_add_number
< -0x8000
5721 || expr1
.X_add_number
>= 0x8000 - 4)
5722 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5723 if (reg_needs_delay (GP
))
5732 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5733 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5734 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5735 ((bfd_arch_bits_per_address (stdoutput
) == 32
5736 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5737 ? "addu" : "daddu"),
5738 "d,v,t", AT
, AT
, GP
);
5739 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5740 ((bfd_arch_bits_per_address (stdoutput
) == 32
5741 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5743 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5744 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5746 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5747 ((bfd_arch_bits_per_address (stdoutput
) == 32
5748 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5749 ? "addu" : "daddu"),
5750 "d,v,t", AT
, breg
, AT
);
5751 /* Itbl support may require additional care here. */
5752 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5753 coproc
? treg
+ 1 : treg
,
5754 (int) BFD_RELOC_LO16
, AT
);
5755 expr1
.X_add_number
+= 4;
5757 /* Set mips_optimize to 2 to avoid inserting an undesired
5759 hold_mips_optimize
= mips_optimize
;
5761 /* Itbl support may require additional care here. */
5762 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5763 coproc
? treg
: treg
+ 1,
5764 (int) BFD_RELOC_LO16
, AT
);
5765 mips_optimize
= hold_mips_optimize
;
5766 expr1
.X_add_number
-= 4;
5768 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5769 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5770 8 + gpdel
+ off
, 1, 0),
5771 offset_expr
.X_add_symbol
, (offsetT
) 0,
5775 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5778 macro_build (p
, &icnt
, &offset_expr
,
5779 ((bfd_arch_bits_per_address (stdoutput
) == 32
5780 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5782 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5784 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5788 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5789 ((bfd_arch_bits_per_address (stdoutput
) == 32
5790 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5791 ? "addu" : "daddu"),
5792 "d,v,t", AT
, breg
, AT
);
5795 /* Itbl support may require additional care here. */
5796 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5797 coproc
? treg
+ 1 : treg
,
5798 (int) BFD_RELOC_LO16
, AT
);
5800 expr1
.X_add_number
+= 4;
5802 /* Set mips_optimize to 2 to avoid inserting an undesired
5804 hold_mips_optimize
= mips_optimize
;
5806 /* Itbl support may require additional care here. */
5807 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5808 coproc
? treg
: treg
+ 1,
5809 (int) BFD_RELOC_LO16
, AT
);
5810 mips_optimize
= hold_mips_optimize
;
5812 else if (mips_pic
== EMBEDDED_PIC
)
5814 /* If there is no base register, we use
5815 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5816 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5817 If we have a base register, we use
5819 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5820 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5829 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5830 ((bfd_arch_bits_per_address (stdoutput
) == 32
5831 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5832 ? "addu" : "daddu"),
5833 "d,v,t", AT
, breg
, GP
);
5838 /* Itbl support may require additional care here. */
5839 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5840 coproc
? treg
+ 1 : treg
,
5841 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5842 offset_expr
.X_add_number
+= 4;
5843 /* Itbl support may require additional care here. */
5844 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5845 coproc
? treg
: treg
+ 1,
5846 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5862 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5863 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5864 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5865 (int) BFD_RELOC_LO16
, breg
);
5866 offset_expr
.X_add_number
+= 4;
5867 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5868 (int) BFD_RELOC_LO16
, breg
);
5871 /* New code added to support COPZ instructions.
5872 This code builds table entries out of the macros in mip_opcodes.
5873 R4000 uses interlocks to handle coproc delays.
5874 Other chips (like the R3000) require nops to be inserted for delays.
5876 FIXME: Currently, we require that the user handle delays.
5877 In order to fill delay slots for non-interlocked chips,
5878 we must have a way to specify delays based on the coprocessor.
5879 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5880 What are the side-effects of the cop instruction?
5881 What cache support might we have and what are its effects?
5882 Both coprocessor & memory require delays. how long???
5883 What registers are read/set/modified?
5885 If an itbl is provided to interpret cop instructions,
5886 this knowledge can be encoded in the itbl spec. */
5900 /* For now we just do C (same as Cz). The parameter will be
5901 stored in insn_opcode by mips_ip. */
5902 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5906 #ifdef LOSING_COMPILER
5908 /* Try and see if this is a new itbl instruction.
5909 This code builds table entries out of the macros in mip_opcodes.
5910 FIXME: For now we just assemble the expression and pass it's
5911 value along as a 32-bit immediate.
5912 We may want to have the assembler assemble this value,
5913 so that we gain the assembler's knowledge of delay slots,
5915 Would it be more efficient to use mask (id) here? */
5916 if (itbl_have_entries
5917 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5919 s
= ip
->insn_mo
->name
;
5921 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5922 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5929 as_warn (_("Macro used $at after \".set noat\""));
5934 struct mips_cl_insn
*ip
;
5936 register int treg
, sreg
, dreg
, breg
;
5952 bfd_reloc_code_real_type r
;
5955 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5956 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5957 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5958 mask
= ip
->insn_mo
->mask
;
5960 expr1
.X_op
= O_constant
;
5961 expr1
.X_op_symbol
= NULL
;
5962 expr1
.X_add_symbol
= NULL
;
5963 expr1
.X_add_number
= 1;
5967 #endif /* LOSING_COMPILER */
5972 macro_build ((char *) NULL
, &icnt
, NULL
,
5973 dbl
? "dmultu" : "multu",
5975 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5981 /* The MIPS assembler some times generates shifts and adds. I'm
5982 not trying to be that fancy. GCC should do this for us
5984 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5985 macro_build ((char *) NULL
, &icnt
, NULL
,
5986 dbl
? "dmult" : "mult",
5988 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6001 mips_emit_delays (true);
6002 ++mips_opts
.noreorder
;
6003 mips_any_noreorder
= 1;
6005 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6006 macro_build ((char *) NULL
, &icnt
, NULL
,
6007 dbl
? "dmult" : "mult",
6008 "s,t", sreg
, imm
? AT
: treg
);
6009 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6010 macro_build ((char *) NULL
, &icnt
, NULL
,
6011 dbl
? "dsra32" : "sra",
6012 "d,w,<", dreg
, dreg
, 31);
6013 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6015 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6018 expr1
.X_add_number
= 8;
6019 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6020 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6021 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6023 --mips_opts
.noreorder
;
6024 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6037 mips_emit_delays (true);
6038 ++mips_opts
.noreorder
;
6039 mips_any_noreorder
= 1;
6041 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6042 macro_build ((char *) NULL
, &icnt
, NULL
,
6043 dbl
? "dmultu" : "multu",
6044 "s,t", sreg
, imm
? AT
: treg
);
6045 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6046 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6048 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6051 expr1
.X_add_number
= 8;
6052 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6053 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6054 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6056 --mips_opts
.noreorder
;
6060 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6061 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6062 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6064 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6068 if (imm_expr
.X_op
!= O_constant
)
6069 as_bad (_("rotate count too large"));
6070 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6071 (int) (imm_expr
.X_add_number
& 0x1f));
6072 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6073 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6074 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6078 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6079 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6080 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6082 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6086 if (imm_expr
.X_op
!= O_constant
)
6087 as_bad (_("rotate count too large"));
6088 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6089 (int) (imm_expr
.X_add_number
& 0x1f));
6090 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6091 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6092 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6096 if (mips_cpu
== CPU_R4650
)
6098 as_bad (_("opcode not supported on this processor"));
6101 assert (mips_opts
.isa
== ISA_MIPS1
);
6102 /* Even on a big endian machine $fn comes before $fn+1. We have
6103 to adjust when storing to memory. */
6104 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6105 target_big_endian
? treg
+ 1 : treg
,
6106 (int) BFD_RELOC_LO16
, breg
);
6107 offset_expr
.X_add_number
+= 4;
6108 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6109 target_big_endian
? treg
: treg
+ 1,
6110 (int) BFD_RELOC_LO16
, breg
);
6115 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6116 treg
, (int) BFD_RELOC_LO16
);
6118 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6119 sreg
, (int) BFD_RELOC_LO16
);
6122 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6124 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6125 dreg
, (int) BFD_RELOC_LO16
);
6130 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6132 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6133 sreg
, (int) BFD_RELOC_LO16
);
6138 as_warn (_("Instruction %s: result is always false"),
6140 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6143 if (imm_expr
.X_op
== O_constant
6144 && imm_expr
.X_add_number
>= 0
6145 && imm_expr
.X_add_number
< 0x10000)
6147 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6148 sreg
, (int) BFD_RELOC_LO16
);
6151 else if (imm_expr
.X_op
== O_constant
6152 && imm_expr
.X_add_number
> -0x8000
6153 && imm_expr
.X_add_number
< 0)
6155 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6156 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6157 ((bfd_arch_bits_per_address (stdoutput
) == 32
6158 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6159 ? "addiu" : "daddiu"),
6160 "t,r,j", dreg
, sreg
,
6161 (int) BFD_RELOC_LO16
);
6166 load_register (&icnt
, AT
, &imm_expr
, 0);
6167 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6171 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6172 (int) BFD_RELOC_LO16
);
6177 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6183 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6184 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6185 (int) BFD_RELOC_LO16
);
6188 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6190 if (imm_expr
.X_op
== O_constant
6191 && imm_expr
.X_add_number
>= -0x8000
6192 && imm_expr
.X_add_number
< 0x8000)
6194 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6195 mask
== M_SGE_I
? "slti" : "sltiu",
6196 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6201 load_register (&icnt
, AT
, &imm_expr
, 0);
6202 macro_build ((char *) NULL
, &icnt
, NULL
,
6203 mask
== M_SGE_I
? "slt" : "sltu",
6204 "d,v,t", dreg
, sreg
, AT
);
6207 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6208 (int) BFD_RELOC_LO16
);
6213 case M_SGT
: /* sreg > treg <==> treg < sreg */
6219 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6222 case M_SGT_I
: /* sreg > I <==> I < sreg */
6228 load_register (&icnt
, AT
, &imm_expr
, 0);
6229 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6232 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6238 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6239 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6240 (int) BFD_RELOC_LO16
);
6243 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6249 load_register (&icnt
, AT
, &imm_expr
, 0);
6250 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6251 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6252 (int) BFD_RELOC_LO16
);
6256 if (imm_expr
.X_op
== O_constant
6257 && imm_expr
.X_add_number
>= -0x8000
6258 && imm_expr
.X_add_number
< 0x8000)
6260 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6261 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6264 load_register (&icnt
, AT
, &imm_expr
, 0);
6265 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6269 if (imm_expr
.X_op
== O_constant
6270 && imm_expr
.X_add_number
>= -0x8000
6271 && imm_expr
.X_add_number
< 0x8000)
6273 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6274 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6277 load_register (&icnt
, AT
, &imm_expr
, 0);
6278 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6284 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6287 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6291 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6293 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6299 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6301 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6307 as_warn (_("Instruction %s: result is always true"),
6309 macro_build ((char *) NULL
, &icnt
, &expr1
,
6310 ((bfd_arch_bits_per_address (stdoutput
) == 32
6311 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6312 ? "addiu" : "daddiu"),
6313 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6316 if (imm_expr
.X_op
== O_constant
6317 && imm_expr
.X_add_number
>= 0
6318 && imm_expr
.X_add_number
< 0x10000)
6320 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6321 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6324 else if (imm_expr
.X_op
== O_constant
6325 && imm_expr
.X_add_number
> -0x8000
6326 && imm_expr
.X_add_number
< 0)
6328 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6329 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6330 ((bfd_arch_bits_per_address (stdoutput
) == 32
6331 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6332 ? "addiu" : "daddiu"),
6333 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6338 load_register (&icnt
, AT
, &imm_expr
, 0);
6339 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6343 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6351 if (imm_expr
.X_op
== O_constant
6352 && imm_expr
.X_add_number
> -0x8000
6353 && imm_expr
.X_add_number
<= 0x8000)
6355 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6356 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6357 dbl
? "daddi" : "addi",
6358 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6361 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6362 macro_build ((char *) NULL
, &icnt
, NULL
,
6363 dbl
? "dsub" : "sub",
6364 "d,v,t", dreg
, sreg
, AT
);
6370 if (imm_expr
.X_op
== O_constant
6371 && imm_expr
.X_add_number
> -0x8000
6372 && imm_expr
.X_add_number
<= 0x8000)
6374 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6375 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6376 dbl
? "daddiu" : "addiu",
6377 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6380 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6381 macro_build ((char *) NULL
, &icnt
, NULL
,
6382 dbl
? "dsubu" : "subu",
6383 "d,v,t", dreg
, sreg
, AT
);
6404 load_register (&icnt
, AT
, &imm_expr
, 0);
6405 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6410 assert (mips_opts
.isa
== ISA_MIPS1
);
6411 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6412 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6415 * Is the double cfc1 instruction a bug in the mips assembler;
6416 * or is there a reason for it?
6418 mips_emit_delays (true);
6419 ++mips_opts
.noreorder
;
6420 mips_any_noreorder
= 1;
6421 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6422 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6423 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6424 expr1
.X_add_number
= 3;
6425 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6426 (int) BFD_RELOC_LO16
);
6427 expr1
.X_add_number
= 2;
6428 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6429 (int) BFD_RELOC_LO16
);
6430 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6431 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6432 macro_build ((char *) NULL
, &icnt
, NULL
,
6433 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6434 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6435 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6436 --mips_opts
.noreorder
;
6445 if (offset_expr
.X_add_number
>= 0x7fff)
6446 as_bad (_("operand overflow"));
6447 /* avoid load delay */
6448 if (! target_big_endian
)
6449 offset_expr
.X_add_number
+= 1;
6450 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6451 (int) BFD_RELOC_LO16
, breg
);
6452 if (! target_big_endian
)
6453 offset_expr
.X_add_number
-= 1;
6455 offset_expr
.X_add_number
+= 1;
6456 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6457 (int) BFD_RELOC_LO16
, breg
);
6458 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6459 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6472 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6473 as_bad (_("operand overflow"));
6474 if (! target_big_endian
)
6475 offset_expr
.X_add_number
+= off
;
6476 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6477 (int) BFD_RELOC_LO16
, breg
);
6478 if (! target_big_endian
)
6479 offset_expr
.X_add_number
-= off
;
6481 offset_expr
.X_add_number
+= off
;
6482 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6483 (int) BFD_RELOC_LO16
, breg
);
6496 load_address (&icnt
, AT
, &offset_expr
);
6498 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6499 ((bfd_arch_bits_per_address (stdoutput
) == 32
6500 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6501 ? "addu" : "daddu"),
6502 "d,v,t", AT
, AT
, breg
);
6503 if (! target_big_endian
)
6504 expr1
.X_add_number
= off
;
6506 expr1
.X_add_number
= 0;
6507 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6508 (int) BFD_RELOC_LO16
, AT
);
6509 if (! target_big_endian
)
6510 expr1
.X_add_number
= 0;
6512 expr1
.X_add_number
= off
;
6513 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6514 (int) BFD_RELOC_LO16
, AT
);
6519 load_address (&icnt
, AT
, &offset_expr
);
6521 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6522 ((bfd_arch_bits_per_address (stdoutput
) == 32
6523 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6524 ? "addu" : "daddu"),
6525 "d,v,t", AT
, AT
, breg
);
6526 if (target_big_endian
)
6527 expr1
.X_add_number
= 0;
6528 macro_build ((char *) NULL
, &icnt
, &expr1
,
6529 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6530 (int) BFD_RELOC_LO16
, AT
);
6531 if (target_big_endian
)
6532 expr1
.X_add_number
= 1;
6534 expr1
.X_add_number
= 0;
6535 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6536 (int) BFD_RELOC_LO16
, AT
);
6537 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6539 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6544 if (offset_expr
.X_add_number
>= 0x7fff)
6545 as_bad (_("operand overflow"));
6546 if (target_big_endian
)
6547 offset_expr
.X_add_number
+= 1;
6548 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6549 (int) BFD_RELOC_LO16
, breg
);
6550 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6551 if (target_big_endian
)
6552 offset_expr
.X_add_number
-= 1;
6554 offset_expr
.X_add_number
+= 1;
6555 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6556 (int) BFD_RELOC_LO16
, breg
);
6569 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6570 as_bad (_("operand overflow"));
6571 if (! target_big_endian
)
6572 offset_expr
.X_add_number
+= off
;
6573 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6574 (int) BFD_RELOC_LO16
, breg
);
6575 if (! target_big_endian
)
6576 offset_expr
.X_add_number
-= off
;
6578 offset_expr
.X_add_number
+= off
;
6579 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6580 (int) BFD_RELOC_LO16
, breg
);
6593 load_address (&icnt
, AT
, &offset_expr
);
6595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6596 ((bfd_arch_bits_per_address (stdoutput
) == 32
6597 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6598 ? "addu" : "daddu"),
6599 "d,v,t", AT
, AT
, breg
);
6600 if (! target_big_endian
)
6601 expr1
.X_add_number
= off
;
6603 expr1
.X_add_number
= 0;
6604 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6605 (int) BFD_RELOC_LO16
, AT
);
6606 if (! target_big_endian
)
6607 expr1
.X_add_number
= 0;
6609 expr1
.X_add_number
= off
;
6610 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6611 (int) BFD_RELOC_LO16
, AT
);
6615 load_address (&icnt
, AT
, &offset_expr
);
6617 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6618 ((bfd_arch_bits_per_address (stdoutput
) == 32
6619 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6620 ? "addu" : "daddu"),
6621 "d,v,t", AT
, AT
, breg
);
6622 if (! target_big_endian
)
6623 expr1
.X_add_number
= 0;
6624 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6625 (int) BFD_RELOC_LO16
, AT
);
6626 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6628 if (! target_big_endian
)
6629 expr1
.X_add_number
= 1;
6631 expr1
.X_add_number
= 0;
6632 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6633 (int) BFD_RELOC_LO16
, AT
);
6634 if (! target_big_endian
)
6635 expr1
.X_add_number
= 0;
6637 expr1
.X_add_number
= 1;
6638 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6639 (int) BFD_RELOC_LO16
, AT
);
6640 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6642 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6647 /* FIXME: Check if this is one of the itbl macros, since they
6648 are added dynamically. */
6649 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6653 as_warn (_("Macro used $at after \".set noat\""));
6656 /* Implement macros in mips16 mode. */
6660 struct mips_cl_insn
*ip
;
6663 int xreg
, yreg
, zreg
, tmp
;
6667 const char *s
, *s2
, *s3
;
6669 mask
= ip
->insn_mo
->mask
;
6671 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6672 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6673 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6677 expr1
.X_op
= O_constant
;
6678 expr1
.X_op_symbol
= NULL
;
6679 expr1
.X_add_symbol
= NULL
;
6680 expr1
.X_add_number
= 1;
6699 mips_emit_delays (true);
6700 ++mips_opts
.noreorder
;
6701 mips_any_noreorder
= 1;
6702 macro_build ((char *) NULL
, &icnt
, NULL
,
6703 dbl
? "ddiv" : "div",
6704 "0,x,y", xreg
, yreg
);
6705 expr1
.X_add_number
= 2;
6706 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6707 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6709 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6710 since that causes an overflow. We should do that as well,
6711 but I don't see how to do the comparisons without a temporary
6713 --mips_opts
.noreorder
;
6714 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6733 mips_emit_delays (true);
6734 ++mips_opts
.noreorder
;
6735 mips_any_noreorder
= 1;
6736 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6737 expr1
.X_add_number
= 2;
6738 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6739 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6740 --mips_opts
.noreorder
;
6741 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6747 macro_build ((char *) NULL
, &icnt
, NULL
,
6748 dbl
? "dmultu" : "multu",
6750 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6758 if (imm_expr
.X_op
!= O_constant
)
6759 as_bad (_("Unsupported large constant"));
6760 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6761 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6762 dbl
? "daddiu" : "addiu",
6763 "y,x,4", yreg
, xreg
);
6767 if (imm_expr
.X_op
!= O_constant
)
6768 as_bad (_("Unsupported large constant"));
6769 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6770 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6775 if (imm_expr
.X_op
!= O_constant
)
6776 as_bad (_("Unsupported large constant"));
6777 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6778 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6801 goto do_reverse_branch
;
6805 goto do_reverse_branch
;
6817 goto do_reverse_branch
;
6828 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6830 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6857 goto do_addone_branch_i
;
6862 goto do_addone_branch_i
;
6877 goto do_addone_branch_i
;
6884 if (imm_expr
.X_op
!= O_constant
)
6885 as_bad (_("Unsupported large constant"));
6886 ++imm_expr
.X_add_number
;
6889 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6890 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6894 expr1
.X_add_number
= 0;
6895 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6897 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6898 "move", "y,X", xreg
, yreg
);
6899 expr1
.X_add_number
= 2;
6900 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6901 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6902 "neg", "x,w", xreg
, xreg
);
6906 /* For consistency checking, verify that all bits are specified either
6907 by the match/mask part of the instruction definition, or by the
6910 validate_mips_insn (opc
)
6911 const struct mips_opcode
*opc
;
6913 const char *p
= opc
->args
;
6915 unsigned long used_bits
= opc
->mask
;
6917 if ((used_bits
& opc
->match
) != opc
->match
)
6919 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6920 opc
->name
, opc
->args
);
6923 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6930 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6931 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6933 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
6934 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6935 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6936 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6938 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6939 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
6941 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
6943 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6944 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6945 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6946 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6947 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6948 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6949 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6950 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6951 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6952 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6953 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6955 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6956 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6957 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6958 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6960 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6961 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6962 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6963 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6964 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6965 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6966 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6967 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6968 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6971 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6972 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
6973 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6975 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6976 c
, opc
->name
, opc
->args
);
6980 if (used_bits
!= 0xffffffff)
6982 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6983 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6989 /* This routine assembles an instruction into its binary format. As a
6990 side effect, it sets one of the global variables imm_reloc or
6991 offset_reloc to the type of relocation to do if one of the operands
6992 is an address expression. */
6997 struct mips_cl_insn
*ip
;
7002 struct mips_opcode
*insn
;
7005 unsigned int lastregno
= 0;
7008 int full_opcode_match
= 1;
7012 /* If the instruction contains a '.', we first try to match an instruction
7013 including the '.'. Then we try again without the '.'. */
7015 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
7018 /* If we stopped on whitespace, then replace the whitespace with null for
7019 the call to hash_find. Save the character we replaced just in case we
7020 have to re-parse the instruction. */
7021 if (isspace ((unsigned char) *s
))
7027 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7029 /* If we didn't find the instruction in the opcode table, try again, but
7030 this time with just the instruction up to, but not including the
7034 /* Restore the character we overwrite above (if any). */
7038 /* Scan up to the first '.' or whitespace. */
7039 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7042 /* If we did not find a '.', then we can quit now. */
7045 insn_error
= "unrecognized opcode";
7049 /* Lookup the instruction in the hash table. */
7051 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7053 insn_error
= "unrecognized opcode";
7057 full_opcode_match
= 0;
7065 assert (strcmp (insn
->name
, str
) == 0);
7067 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7072 if (insn
->pinfo
!= INSN_MACRO
)
7074 if (mips_cpu
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7080 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7081 && strcmp (insn
->name
, insn
[1].name
) == 0)
7088 static char buf
[100];
7090 _("opcode not supported on this processor: %s (%s)"),
7091 mips_cpu_to_str (mips_cpu
),
7092 mips_isa_to_str (mips_opts
.isa
));
7100 ip
->insn_opcode
= insn
->match
;
7101 for (args
= insn
->args
;; ++args
)
7107 case '\0': /* end of args */
7120 ip
->insn_opcode
|= lastregno
<< 21;
7125 ip
->insn_opcode
|= lastregno
<< 16;
7129 ip
->insn_opcode
|= lastregno
<< 11;
7135 /* Handle optional base register.
7136 Either the base register is omitted or
7137 we must have a left paren. */
7138 /* This is dependent on the next operand specifier
7139 is a base register specification. */
7140 assert (args
[1] == 'b' || args
[1] == '5'
7141 || args
[1] == '-' || args
[1] == '4');
7145 case ')': /* these must match exactly */
7150 case '<': /* must be at least one digit */
7152 * According to the manual, if the shift amount is greater
7153 * than 31 or less than 0 the the shift amount should be
7154 * mod 32. In reality the mips assembler issues an error.
7155 * We issue a warning and mask out all but the low 5 bits.
7157 my_getExpression (&imm_expr
, s
);
7158 check_absolute_expr (ip
, &imm_expr
);
7159 if ((unsigned long) imm_expr
.X_add_number
> 31)
7161 as_warn (_("Improper shift amount (%ld)"),
7162 (long) imm_expr
.X_add_number
);
7163 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7165 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7166 imm_expr
.X_op
= O_absent
;
7170 case '>': /* shift amount minus 32 */
7171 my_getExpression (&imm_expr
, s
);
7172 check_absolute_expr (ip
, &imm_expr
);
7173 if ((unsigned long) imm_expr
.X_add_number
< 32
7174 || (unsigned long) imm_expr
.X_add_number
> 63)
7176 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7177 imm_expr
.X_op
= O_absent
;
7181 case 'k': /* cache code */
7182 case 'h': /* prefx code */
7183 my_getExpression (&imm_expr
, s
);
7184 check_absolute_expr (ip
, &imm_expr
);
7185 if ((unsigned long) imm_expr
.X_add_number
> 31)
7187 as_warn (_("Invalid value for `%s' (%lu)"),
7189 (unsigned long) imm_expr
.X_add_number
);
7190 imm_expr
.X_add_number
&= 0x1f;
7193 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7195 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7196 imm_expr
.X_op
= O_absent
;
7200 case 'c': /* break code */
7201 my_getExpression (&imm_expr
, s
);
7202 check_absolute_expr (ip
, &imm_expr
);
7203 if ((unsigned) imm_expr
.X_add_number
> 1023)
7205 as_warn (_("Illegal break code (%ld)"),
7206 (long) imm_expr
.X_add_number
);
7207 imm_expr
.X_add_number
&= 0x3ff;
7209 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7210 imm_expr
.X_op
= O_absent
;
7214 case 'q': /* lower break code */
7215 my_getExpression (&imm_expr
, s
);
7216 check_absolute_expr (ip
, &imm_expr
);
7217 if ((unsigned) imm_expr
.X_add_number
> 1023)
7219 as_warn (_("Illegal lower break code (%ld)"),
7220 (long) imm_expr
.X_add_number
);
7221 imm_expr
.X_add_number
&= 0x3ff;
7223 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7224 imm_expr
.X_op
= O_absent
;
7228 case 'B': /* 20-bit syscall/break code. */
7229 my_getExpression (&imm_expr
, s
);
7230 check_absolute_expr (ip
, &imm_expr
);
7231 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7232 as_warn (_("Illegal 20-bit code (%ld)"),
7233 (long) imm_expr
.X_add_number
);
7234 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7235 imm_expr
.X_op
= O_absent
;
7239 case 'C': /* Coprocessor code */
7240 my_getExpression (&imm_expr
, s
);
7241 check_absolute_expr (ip
, &imm_expr
);
7242 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7244 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7245 (long) imm_expr
.X_add_number
);
7246 imm_expr
.X_add_number
&= ((1<<25) - 1);
7248 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7249 imm_expr
.X_op
= O_absent
;
7253 case 'J': /* 19-bit wait code. */
7254 my_getExpression (&imm_expr
, s
);
7255 check_absolute_expr (ip
, &imm_expr
);
7256 if ((unsigned) imm_expr
.X_add_number
> 0x7ffff)
7257 as_warn (_("Illegal 19-bit code (%ld)"),
7258 (long) imm_expr
.X_add_number
);
7259 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7260 imm_expr
.X_op
= O_absent
;
7264 case 'P': /* Performance register */
7265 my_getExpression (&imm_expr
, s
);
7266 check_absolute_expr (ip
, &imm_expr
);
7267 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7269 as_warn (_("Invalidate performance regster (%ld)"),
7270 (long) imm_expr
.X_add_number
);
7271 imm_expr
.X_add_number
&= 1;
7273 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7274 imm_expr
.X_op
= O_absent
;
7278 case 'b': /* base register */
7279 case 'd': /* destination register */
7280 case 's': /* source register */
7281 case 't': /* target register */
7282 case 'r': /* both target and source */
7283 case 'v': /* both dest and source */
7284 case 'w': /* both dest and target */
7285 case 'E': /* coprocessor target register */
7286 case 'G': /* coprocessor destination register */
7287 case 'x': /* ignore register name */
7288 case 'z': /* must be zero register */
7289 case 'U': /* destination register (clo/clz). */
7294 if (isdigit ((unsigned char) s
[1]))
7304 while (isdigit ((unsigned char) *s
));
7306 as_bad (_("Invalid register number (%d)"), regno
);
7308 else if (*args
== 'E' || *args
== 'G')
7312 if (s
[1] == 'f' && s
[2] == 'p')
7317 else if (s
[1] == 's' && s
[2] == 'p')
7322 else if (s
[1] == 'g' && s
[2] == 'p')
7327 else if (s
[1] == 'a' && s
[2] == 't')
7332 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7337 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7342 else if (itbl_have_entries
)
7347 p
= s
+ 1; /* advance past '$' */
7348 n
= itbl_get_field (&p
); /* n is name */
7350 /* See if this is a register defined in an
7352 if (itbl_get_reg_val (n
, &r
))
7354 /* Get_field advances to the start of
7355 the next field, so we need to back
7356 rack to the end of the last field. */
7360 s
= strchr (s
, '\0');
7373 as_warn (_("Used $at without \".set noat\""));
7379 if (c
== 'r' || c
== 'v' || c
== 'w')
7386 /* 'z' only matches $0. */
7387 if (c
== 'z' && regno
!= 0)
7390 /* Now that we have assembled one operand, we use the args string
7391 * to figure out where it goes in the instruction. */
7398 ip
->insn_opcode
|= regno
<< 21;
7402 ip
->insn_opcode
|= regno
<< 11;
7405 ip
->insn_opcode
|= regno
<< 11;
7406 ip
->insn_opcode
|= regno
<< 16;
7411 ip
->insn_opcode
|= regno
<< 16;
7414 /* This case exists because on the r3000 trunc
7415 expands into a macro which requires a gp
7416 register. On the r6000 or r4000 it is
7417 assembled into a single instruction which
7418 ignores the register. Thus the insn version
7419 is MIPS_ISA2 and uses 'x', and the macro
7420 version is MIPS_ISA1 and uses 't'. */
7423 /* This case is for the div instruction, which
7424 acts differently if the destination argument
7425 is $0. This only matches $0, and is checked
7426 outside the switch. */
7429 /* Itbl operand; not yet implemented. FIXME ?? */
7431 /* What about all other operands like 'i', which
7432 can be specified in the opcode table? */
7442 ip
->insn_opcode
|= lastregno
<< 21;
7445 ip
->insn_opcode
|= lastregno
<< 16;
7450 case 'D': /* floating point destination register */
7451 case 'S': /* floating point source register */
7452 case 'T': /* floating point target register */
7453 case 'R': /* floating point source register */
7457 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7467 while (isdigit ((unsigned char) *s
));
7470 as_bad (_("Invalid float register number (%d)"), regno
);
7472 if ((regno
& 1) != 0
7473 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7474 && ! (strcmp (str
, "mtc1") == 0
7475 || strcmp (str
, "mfc1") == 0
7476 || strcmp (str
, "lwc1") == 0
7477 || strcmp (str
, "swc1") == 0
7478 || strcmp (str
, "l.s") == 0
7479 || strcmp (str
, "s.s") == 0))
7480 as_warn (_("Float register should be even, was %d"),
7488 if (c
== 'V' || c
== 'W')
7498 ip
->insn_opcode
|= regno
<< 6;
7502 ip
->insn_opcode
|= regno
<< 11;
7506 ip
->insn_opcode
|= regno
<< 16;
7509 ip
->insn_opcode
|= regno
<< 21;
7519 ip
->insn_opcode
|= lastregno
<< 11;
7522 ip
->insn_opcode
|= lastregno
<< 16;
7528 my_getExpression (&imm_expr
, s
);
7529 if (imm_expr
.X_op
!= O_big
7530 && imm_expr
.X_op
!= O_constant
)
7531 insn_error
= _("absolute expression required");
7536 my_getExpression (&offset_expr
, s
);
7537 imm_reloc
= BFD_RELOC_32
;
7549 unsigned char temp
[8];
7551 unsigned int length
;
7556 /* These only appear as the last operand in an
7557 instruction, and every instruction that accepts
7558 them in any variant accepts them in all variants.
7559 This means we don't have to worry about backing out
7560 any changes if the instruction does not match.
7562 The difference between them is the size of the
7563 floating point constant and where it goes. For 'F'
7564 and 'L' the constant is 64 bits; for 'f' and 'l' it
7565 is 32 bits. Where the constant is placed is based
7566 on how the MIPS assembler does things:
7569 f -- immediate value
7572 The .lit4 and .lit8 sections are only used if
7573 permitted by the -G argument.
7575 When generating embedded PIC code, we use the
7576 .lit8 section but not the .lit4 section (we can do
7577 .lit4 inline easily; we need to put .lit8
7578 somewhere in the data segment, and using .lit8
7579 permits the linker to eventually combine identical
7582 f64
= *args
== 'F' || *args
== 'L';
7584 save_in
= input_line_pointer
;
7585 input_line_pointer
= s
;
7586 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7588 s
= input_line_pointer
;
7589 input_line_pointer
= save_in
;
7590 if (err
!= NULL
&& *err
!= '\0')
7592 as_bad (_("Bad floating point constant: %s"), err
);
7593 memset (temp
, '\0', sizeof temp
);
7594 length
= f64
? 8 : 4;
7597 assert (length
== (unsigned) (f64
? 8 : 4));
7601 && (! USE_GLOBAL_POINTER_OPT
7602 || mips_pic
== EMBEDDED_PIC
7603 || g_switch_value
< 4
7604 || (temp
[0] == 0 && temp
[1] == 0)
7605 || (temp
[2] == 0 && temp
[3] == 0))))
7607 imm_expr
.X_op
= O_constant
;
7608 if (! target_big_endian
)
7609 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7611 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7614 && ! mips_disable_float_construction
7615 && ((temp
[0] == 0 && temp
[1] == 0)
7616 || (temp
[2] == 0 && temp
[3] == 0))
7617 && ((temp
[4] == 0 && temp
[5] == 0)
7618 || (temp
[6] == 0 && temp
[7] == 0)))
7620 /* The value is simple enough to load with a
7621 couple of instructions. In mips1 mode, set
7622 imm_expr to the high order 32 bits and
7623 offset_expr to the low order 32 bits.
7624 Otherwise, set imm_expr to the entire 64 bit
7626 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7628 imm_expr
.X_op
= O_constant
;
7629 offset_expr
.X_op
= O_constant
;
7630 if (! target_big_endian
)
7632 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7633 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7637 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7638 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7640 if (offset_expr
.X_add_number
== 0)
7641 offset_expr
.X_op
= O_absent
;
7643 else if (sizeof (imm_expr
.X_add_number
) > 4)
7645 imm_expr
.X_op
= O_constant
;
7646 if (! target_big_endian
)
7647 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7649 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7653 imm_expr
.X_op
= O_big
;
7654 imm_expr
.X_add_number
= 4;
7655 if (! target_big_endian
)
7657 generic_bignum
[0] = bfd_getl16 (temp
);
7658 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7659 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7660 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7664 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7665 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7666 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7667 generic_bignum
[3] = bfd_getb16 (temp
);
7673 const char *newname
;
7676 /* Switch to the right section. */
7678 subseg
= now_subseg
;
7681 default: /* unused default case avoids warnings. */
7683 newname
= RDATA_SECTION_NAME
;
7684 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7685 || mips_pic
== EMBEDDED_PIC
)
7689 if (mips_pic
== EMBEDDED_PIC
)
7692 newname
= RDATA_SECTION_NAME
;
7695 assert (!USE_GLOBAL_POINTER_OPT
7696 || g_switch_value
>= 4);
7700 new_seg
= subseg_new (newname
, (subsegT
) 0);
7701 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7702 bfd_set_section_flags (stdoutput
, new_seg
,
7707 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7708 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7709 && strcmp (TARGET_OS
, "elf") != 0)
7710 record_alignment (new_seg
, 4);
7712 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7714 as_bad (_("Can't use floating point insn in this section"));
7716 /* Set the argument to the current address in the
7718 offset_expr
.X_op
= O_symbol
;
7719 offset_expr
.X_add_symbol
=
7720 symbol_new ("L0\001", now_seg
,
7721 (valueT
) frag_now_fix (), frag_now
);
7722 offset_expr
.X_add_number
= 0;
7724 /* Put the floating point number into the section. */
7725 p
= frag_more ((int) length
);
7726 memcpy (p
, temp
, length
);
7728 /* Switch back to the original section. */
7729 subseg_set (seg
, subseg
);
7734 case 'i': /* 16 bit unsigned immediate */
7735 case 'j': /* 16 bit signed immediate */
7736 imm_reloc
= BFD_RELOC_LO16
;
7737 c
= my_getSmallExpression (&imm_expr
, s
);
7742 if (imm_expr
.X_op
== O_constant
)
7743 imm_expr
.X_add_number
=
7744 (imm_expr
.X_add_number
>> 16) & 0xffff;
7747 imm_reloc
= BFD_RELOC_HI16_S
;
7748 imm_unmatched_hi
= true;
7751 imm_reloc
= BFD_RELOC_HI16
;
7753 else if (imm_expr
.X_op
== O_constant
)
7754 imm_expr
.X_add_number
&= 0xffff;
7758 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7759 || ((imm_expr
.X_add_number
< 0
7760 || imm_expr
.X_add_number
>= 0x10000)
7761 && imm_expr
.X_op
== O_constant
))
7763 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7764 !strcmp (insn
->name
, insn
[1].name
))
7766 if (imm_expr
.X_op
== O_constant
7767 || imm_expr
.X_op
== O_big
)
7768 as_bad (_("16 bit expression not in range 0..65535"));
7776 /* The upper bound should be 0x8000, but
7777 unfortunately the MIPS assembler accepts numbers
7778 from 0x8000 to 0xffff and sign extends them, and
7779 we want to be compatible. We only permit this
7780 extended range for an instruction which does not
7781 provide any further alternates, since those
7782 alternates may handle other cases. People should
7783 use the numbers they mean, rather than relying on
7784 a mysterious sign extension. */
7785 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7786 strcmp (insn
->name
, insn
[1].name
) == 0);
7791 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7792 || ((imm_expr
.X_add_number
< -0x8000
7793 || imm_expr
.X_add_number
>= max
)
7794 && imm_expr
.X_op
== O_constant
)
7796 && imm_expr
.X_add_number
< 0
7797 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7798 && imm_expr
.X_unsigned
7799 && sizeof (imm_expr
.X_add_number
) <= 4))
7803 if (imm_expr
.X_op
== O_constant
7804 || imm_expr
.X_op
== O_big
)
7805 as_bad (_("16 bit expression not in range -32768..32767"));
7811 case 'o': /* 16 bit offset */
7812 c
= my_getSmallExpression (&offset_expr
, s
);
7814 /* If this value won't fit into a 16 bit offset, then go
7815 find a macro that will generate the 32 bit offset
7816 code pattern. As a special hack, we accept the
7817 difference of two local symbols as a constant. This
7818 is required to suppose embedded PIC switches, which
7819 use an instruction which looks like
7820 lw $4,$L12-$LS12($4)
7821 The problem with handling this in a more general
7822 fashion is that the macro function doesn't expect to
7823 see anything which can be handled in a single
7824 constant instruction. */
7826 && (offset_expr
.X_op
!= O_constant
7827 || offset_expr
.X_add_number
>= 0x8000
7828 || offset_expr
.X_add_number
< -0x8000)
7829 && (mips_pic
!= EMBEDDED_PIC
7830 || offset_expr
.X_op
!= O_subtract
7831 || (S_GET_SEGMENT (offset_expr
.X_add_symbol
)
7832 != S_GET_SEGMENT (offset_expr
.X_op_symbol
))))
7835 if (c
== 'h' || c
== 'H')
7837 if (offset_expr
.X_op
!= O_constant
)
7839 offset_expr
.X_add_number
=
7840 (offset_expr
.X_add_number
>> 16) & 0xffff;
7842 offset_reloc
= BFD_RELOC_LO16
;
7846 case 'p': /* pc relative offset */
7847 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7848 my_getExpression (&offset_expr
, s
);
7852 case 'u': /* upper 16 bits */
7853 c
= my_getSmallExpression (&imm_expr
, s
);
7854 imm_reloc
= BFD_RELOC_LO16
;
7859 if (imm_expr
.X_op
== O_constant
)
7860 imm_expr
.X_add_number
=
7861 (imm_expr
.X_add_number
>> 16) & 0xffff;
7864 imm_reloc
= BFD_RELOC_HI16_S
;
7865 imm_unmatched_hi
= true;
7868 imm_reloc
= BFD_RELOC_HI16
;
7870 else if (imm_expr
.X_op
== O_constant
)
7871 imm_expr
.X_add_number
&= 0xffff;
7873 if (imm_expr
.X_op
== O_constant
7874 && (imm_expr
.X_add_number
< 0
7875 || imm_expr
.X_add_number
>= 0x10000))
7876 as_bad (_("lui expression not in range 0..65535"));
7880 case 'a': /* 26 bit address */
7881 my_getExpression (&offset_expr
, s
);
7883 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7886 case 'N': /* 3 bit branch condition code */
7887 case 'M': /* 3 bit compare condition code */
7888 if (strncmp (s
, "$fcc", 4) != 0)
7898 while (isdigit ((unsigned char) *s
));
7900 as_bad (_("invalid condition code register $fcc%d"), regno
);
7902 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7904 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7908 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
7910 if (isdigit ((unsigned char) *s
))
7919 while (isdigit ((unsigned char) *s
));
7922 c
= 8; /* Invalid sel value. */
7925 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
7926 ip
->insn_opcode
|= c
;
7930 as_bad (_("bad char = '%c'\n"), *args
);
7935 /* Args don't match. */
7936 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7937 !strcmp (insn
->name
, insn
[1].name
))
7943 insn_error
= _("illegal operands");
7948 /* This routine assembles an instruction into its binary format when
7949 assembling for the mips16. As a side effect, it sets one of the
7950 global variables imm_reloc or offset_reloc to the type of
7951 relocation to do if one of the operands is an address expression.
7952 It also sets mips16_small and mips16_ext if the user explicitly
7953 requested a small or extended instruction. */
7958 struct mips_cl_insn
*ip
;
7962 struct mips_opcode
*insn
;
7965 unsigned int lastregno
= 0;
7970 mips16_small
= false;
7973 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7985 if (s
[1] == 't' && s
[2] == ' ')
7988 mips16_small
= true;
7992 else if (s
[1] == 'e' && s
[2] == ' ')
8001 insn_error
= _("unknown opcode");
8005 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8006 mips16_small
= true;
8008 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8010 insn_error
= _("unrecognized opcode");
8017 assert (strcmp (insn
->name
, str
) == 0);
8020 ip
->insn_opcode
= insn
->match
;
8021 ip
->use_extend
= false;
8022 imm_expr
.X_op
= O_absent
;
8023 imm_reloc
= BFD_RELOC_UNUSED
;
8024 offset_expr
.X_op
= O_absent
;
8025 offset_reloc
= BFD_RELOC_UNUSED
;
8026 for (args
= insn
->args
; 1; ++args
)
8033 /* In this switch statement we call break if we did not find
8034 a match, continue if we did find a match, or return if we
8043 /* Stuff the immediate value in now, if we can. */
8044 if (imm_expr
.X_op
== O_constant
8045 && imm_reloc
> BFD_RELOC_UNUSED
8046 && insn
->pinfo
!= INSN_MACRO
)
8048 mips16_immed ((char *) NULL
, 0,
8049 imm_reloc
- BFD_RELOC_UNUSED
,
8050 imm_expr
.X_add_number
, true, mips16_small
,
8051 mips16_ext
, &ip
->insn_opcode
,
8052 &ip
->use_extend
, &ip
->extend
);
8053 imm_expr
.X_op
= O_absent
;
8054 imm_reloc
= BFD_RELOC_UNUSED
;
8068 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8071 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8087 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8089 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8106 if (isdigit ((unsigned char) s
[1]))
8116 while (isdigit ((unsigned char) *s
));
8119 as_bad (_("invalid register number (%d)"), regno
);
8125 if (s
[1] == 'f' && s
[2] == 'p')
8130 else if (s
[1] == 's' && s
[2] == 'p')
8135 else if (s
[1] == 'g' && s
[2] == 'p')
8140 else if (s
[1] == 'a' && s
[2] == 't')
8145 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8150 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8163 if (c
== 'v' || c
== 'w')
8165 regno
= mips16_to_32_reg_map
[lastregno
];
8179 regno
= mips32_to_16_reg_map
[regno
];
8184 regno
= ILLEGAL_REG
;
8189 regno
= ILLEGAL_REG
;
8194 regno
= ILLEGAL_REG
;
8199 if (regno
== AT
&& ! mips_opts
.noat
)
8200 as_warn (_("used $at without \".set noat\""));
8207 if (regno
== ILLEGAL_REG
)
8214 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8218 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8221 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8224 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8230 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8233 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8234 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8244 if (strncmp (s
, "$pc", 3) == 0)
8268 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8270 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8271 and generate the appropriate reloc. If the text
8272 inside %gprel is not a symbol name with an
8273 optional offset, then we generate a normal reloc
8274 and will probably fail later. */
8275 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8276 if (imm_expr
.X_op
== O_symbol
)
8279 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8281 ip
->use_extend
= true;
8288 /* Just pick up a normal expression. */
8289 my_getExpression (&imm_expr
, s
);
8292 if (imm_expr
.X_op
== O_register
)
8294 /* What we thought was an expression turned out to
8297 if (s
[0] == '(' && args
[1] == '(')
8299 /* It looks like the expression was omitted
8300 before a register indirection, which means
8301 that the expression is implicitly zero. We
8302 still set up imm_expr, so that we handle
8303 explicit extensions correctly. */
8304 imm_expr
.X_op
= O_constant
;
8305 imm_expr
.X_add_number
= 0;
8306 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8313 /* We need to relax this instruction. */
8314 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8323 /* We use offset_reloc rather than imm_reloc for the PC
8324 relative operands. This lets macros with both
8325 immediate and address operands work correctly. */
8326 my_getExpression (&offset_expr
, s
);
8328 if (offset_expr
.X_op
== O_register
)
8331 /* We need to relax this instruction. */
8332 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8336 case '6': /* break code */
8337 my_getExpression (&imm_expr
, s
);
8338 check_absolute_expr (ip
, &imm_expr
);
8339 if ((unsigned long) imm_expr
.X_add_number
> 63)
8341 as_warn (_("Invalid value for `%s' (%lu)"),
8343 (unsigned long) imm_expr
.X_add_number
);
8344 imm_expr
.X_add_number
&= 0x3f;
8346 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8347 imm_expr
.X_op
= O_absent
;
8351 case 'a': /* 26 bit address */
8352 my_getExpression (&offset_expr
, s
);
8354 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8355 ip
->insn_opcode
<<= 16;
8358 case 'l': /* register list for entry macro */
8359 case 'L': /* register list for exit macro */
8369 int freg
, reg1
, reg2
;
8371 while (*s
== ' ' || *s
== ',')
8375 as_bad (_("can't parse register list"));
8387 while (isdigit ((unsigned char) *s
))
8409 as_bad (_("invalid register list"));
8414 while (isdigit ((unsigned char) *s
))
8421 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8426 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8431 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8432 mask
|= (reg2
- 3) << 3;
8433 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8434 mask
|= (reg2
- 15) << 1;
8435 else if (reg1
== 31 && reg2
== 31)
8439 as_bad (_("invalid register list"));
8443 /* The mask is filled in in the opcode table for the
8444 benefit of the disassembler. We remove it before
8445 applying the actual mask. */
8446 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8447 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8451 case 'e': /* extend code */
8452 my_getExpression (&imm_expr
, s
);
8453 check_absolute_expr (ip
, &imm_expr
);
8454 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8456 as_warn (_("Invalid value for `%s' (%lu)"),
8458 (unsigned long) imm_expr
.X_add_number
);
8459 imm_expr
.X_add_number
&= 0x7ff;
8461 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8462 imm_expr
.X_op
= O_absent
;
8472 /* Args don't match. */
8473 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8474 strcmp (insn
->name
, insn
[1].name
) == 0)
8481 insn_error
= _("illegal operands");
8487 /* This structure holds information we know about a mips16 immediate
8490 struct mips16_immed_operand
8492 /* The type code used in the argument string in the opcode table. */
8494 /* The number of bits in the short form of the opcode. */
8496 /* The number of bits in the extended form of the opcode. */
8498 /* The amount by which the short form is shifted when it is used;
8499 for example, the sw instruction has a shift count of 2. */
8501 /* The amount by which the short form is shifted when it is stored
8502 into the instruction code. */
8504 /* Non-zero if the short form is unsigned. */
8506 /* Non-zero if the extended form is unsigned. */
8508 /* Non-zero if the value is PC relative. */
8512 /* The mips16 immediate operand types. */
8514 static const struct mips16_immed_operand mips16_immed_operands
[] =
8516 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8517 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8518 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8519 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8520 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8521 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8522 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8523 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8524 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8525 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8526 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8527 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8528 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8529 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8530 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8531 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8532 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8533 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8534 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8535 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8536 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8539 #define MIPS16_NUM_IMMED \
8540 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8542 /* Handle a mips16 instruction with an immediate value. This or's the
8543 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8544 whether an extended value is needed; if one is needed, it sets
8545 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8546 If SMALL is true, an unextended opcode was explicitly requested.
8547 If EXT is true, an extended opcode was explicitly requested. If
8548 WARN is true, warn if EXT does not match reality. */
8551 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8560 unsigned long *insn
;
8561 boolean
*use_extend
;
8562 unsigned short *extend
;
8564 register const struct mips16_immed_operand
*op
;
8565 int mintiny
, maxtiny
;
8568 op
= mips16_immed_operands
;
8569 while (op
->type
!= type
)
8572 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8577 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8580 maxtiny
= 1 << op
->nbits
;
8585 maxtiny
= (1 << op
->nbits
) - 1;
8590 mintiny
= - (1 << (op
->nbits
- 1));
8591 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8594 /* Branch offsets have an implicit 0 in the lowest bit. */
8595 if (type
== 'p' || type
== 'q')
8598 if ((val
& ((1 << op
->shift
) - 1)) != 0
8599 || val
< (mintiny
<< op
->shift
)
8600 || val
> (maxtiny
<< op
->shift
))
8605 if (warn
&& ext
&& ! needext
)
8606 as_warn_where (file
, line
,
8607 _("extended operand requested but not required"));
8608 if (small
&& needext
)
8609 as_bad_where (file
, line
, _("invalid unextended operand value"));
8611 if (small
|| (! ext
&& ! needext
))
8615 *use_extend
= false;
8616 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8617 insnval
<<= op
->op_shift
;
8622 long minext
, maxext
;
8628 maxext
= (1 << op
->extbits
) - 1;
8632 minext
= - (1 << (op
->extbits
- 1));
8633 maxext
= (1 << (op
->extbits
- 1)) - 1;
8635 if (val
< minext
|| val
> maxext
)
8636 as_bad_where (file
, line
,
8637 _("operand value out of range for instruction"));
8640 if (op
->extbits
== 16)
8642 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8645 else if (op
->extbits
== 15)
8647 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8652 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8656 *extend
= (unsigned short) extval
;
8665 my_getSmallExpression (ep
, str
)
8676 ((str
[1] == 'h' && str
[2] == 'i')
8677 || (str
[1] == 'H' && str
[2] == 'I')
8678 || (str
[1] == 'l' && str
[2] == 'o'))
8690 * A small expression may be followed by a base register.
8691 * Scan to the end of this operand, and then back over a possible
8692 * base register. Then scan the small expression up to that
8693 * point. (Based on code in sparc.c...)
8695 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8697 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8699 if (isdigit ((unsigned char) sp
[-2]))
8701 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8703 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8709 else if (sp
- 5 >= str
8712 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8713 || (sp
[-3] == 's' && sp
[-2] == 'p')
8714 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8715 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8721 /* no expression means zero offset */
8724 /* %xx(reg) is an error */
8725 ep
->X_op
= O_absent
;
8730 ep
->X_op
= O_constant
;
8733 ep
->X_add_symbol
= NULL
;
8734 ep
->X_op_symbol
= NULL
;
8735 ep
->X_add_number
= 0;
8740 my_getExpression (ep
, str
);
8747 my_getExpression (ep
, str
);
8748 return c
; /* => %hi or %lo encountered */
8752 my_getExpression (ep
, str
)
8758 save_in
= input_line_pointer
;
8759 input_line_pointer
= str
;
8761 expr_end
= input_line_pointer
;
8762 input_line_pointer
= save_in
;
8764 /* If we are in mips16 mode, and this is an expression based on `.',
8765 then we bump the value of the symbol by 1 since that is how other
8766 text symbols are handled. We don't bother to handle complex
8767 expressions, just `.' plus or minus a constant. */
8768 if (mips_opts
.mips16
8769 && ep
->X_op
== O_symbol
8770 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8771 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8772 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8773 && symbol_constant_p (ep
->X_add_symbol
)
8774 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8775 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8778 /* Turn a string in input_line_pointer into a floating point constant
8779 of type TYPE, and store the appropriate bytes in *LITP. The number
8780 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8781 returned, or NULL on OK. */
8784 md_atof (type
, litP
, sizeP
)
8790 LITTLENUM_TYPE words
[4];
8806 return _("bad call to md_atof");
8809 t
= atof_ieee (input_line_pointer
, type
, words
);
8811 input_line_pointer
= t
;
8815 if (! target_big_endian
)
8817 for (i
= prec
- 1; i
>= 0; i
--)
8819 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8825 for (i
= 0; i
< prec
; i
++)
8827 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8836 md_number_to_chars (buf
, val
, n
)
8841 if (target_big_endian
)
8842 number_to_chars_bigendian (buf
, val
, n
);
8844 number_to_chars_littleendian (buf
, val
, n
);
8847 CONST
char *md_shortopts
= "O::g::G:";
8849 struct option md_longopts
[] =
8851 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8852 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8853 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8854 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8855 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8856 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8857 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8858 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8859 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8860 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8861 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8862 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8863 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8864 #define OPTION_TRAP (OPTION_MD_BASE + 7)
8865 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8866 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8867 #define OPTION_BREAK (OPTION_MD_BASE + 8)
8868 {"break", no_argument
, NULL
, OPTION_BREAK
},
8869 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8870 #define OPTION_EB (OPTION_MD_BASE + 9)
8871 {"EB", no_argument
, NULL
, OPTION_EB
},
8872 #define OPTION_EL (OPTION_MD_BASE + 10)
8873 {"EL", no_argument
, NULL
, OPTION_EL
},
8874 #define OPTION_M4650 (OPTION_MD_BASE + 11)
8875 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8876 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
8877 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8878 #define OPTION_M4010 (OPTION_MD_BASE + 13)
8879 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8880 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
8881 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8882 #define OPTION_M4100 (OPTION_MD_BASE + 15)
8883 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8884 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
8885 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8886 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
8887 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8888 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
8889 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8890 #define OPTION_M3900 (OPTION_MD_BASE + 19)
8891 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8892 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
8893 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8894 #define OPTION_MABI (OPTION_MD_BASE + 21)
8895 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8896 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
8897 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8898 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
8899 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8900 #define OPTION_GP32 (OPTION_MD_BASE + 24)
8901 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8902 #define OPTION_GP64 (OPTION_MD_BASE + 25)
8903 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8904 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
8905 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
8906 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
8907 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
8908 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
8909 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
8910 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
8911 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
8912 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
8913 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
8915 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
8916 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
8917 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
8918 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
8919 #define OPTION_32 (OPTION_ELF_BASE + 3)
8920 #define OPTION_64 (OPTION_ELF_BASE + 4)
8921 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8922 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8923 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8924 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8925 {"32", no_argument
, NULL
, OPTION_32
},
8926 {"64", no_argument
, NULL
, OPTION_64
},
8929 {NULL
, no_argument
, NULL
, 0}
8931 size_t md_longopts_size
= sizeof (md_longopts
);
8934 md_parse_option (c
, arg
)
8940 case OPTION_CONSTRUCT_FLOATS
:
8941 mips_disable_float_construction
= 0;
8944 case OPTION_NO_CONSTRUCT_FLOATS
:
8945 mips_disable_float_construction
= 1;
8957 target_big_endian
= 1;
8961 target_big_endian
= 0;
8965 if (arg
&& arg
[1] == '0')
8975 mips_debug
= atoi (arg
);
8976 /* When the MIPS assembler sees -g or -g2, it does not do
8977 optimizations which limit full symbolic debugging. We take
8978 that to be equivalent to -O0. */
8979 if (mips_debug
== 2)
8984 mips_opts
.isa
= ISA_MIPS1
;
8988 mips_opts
.isa
= ISA_MIPS2
;
8992 mips_opts
.isa
= ISA_MIPS3
;
8996 mips_opts
.isa
= ISA_MIPS4
;
9000 mips_opts
.isa
= ISA_MIPS5
;
9004 mips_opts
.isa
= ISA_MIPS32
;
9008 mips_opts
.isa
= ISA_MIPS64
;
9013 /* Identify the processor type. */
9014 if (strcasecmp (arg
, "default") == 0)
9015 mips_cpu
= CPU_UNKNOWN
;
9018 const struct mips_cpu_info
*ci
;
9020 ci
= mips_cpu_info_from_name (arg
);
9021 if (ci
== NULL
|| ci
->is_isa
)
9022 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9030 mips_cpu
= CPU_R4650
;
9033 case OPTION_NO_M4650
:
9037 mips_cpu
= CPU_R4010
;
9040 case OPTION_NO_M4010
:
9044 mips_cpu
= CPU_VR4100
;
9047 case OPTION_NO_M4100
:
9051 mips_cpu
= CPU_R3900
;
9054 case OPTION_NO_M3900
:
9058 mips_opts
.mips16
= 1;
9059 mips_no_prev_insn (false);
9062 case OPTION_NO_MIPS16
:
9063 mips_opts
.mips16
= 0;
9064 mips_no_prev_insn (false);
9067 case OPTION_MEMBEDDED_PIC
:
9068 mips_pic
= EMBEDDED_PIC
;
9069 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9071 as_bad (_("-G may not be used with embedded PIC code"));
9074 g_switch_value
= 0x7fffffff;
9078 /* When generating ELF code, we permit -KPIC and -call_shared to
9079 select SVR4_PIC, and -non_shared to select no PIC. This is
9080 intended to be compatible with Irix 5. */
9081 case OPTION_CALL_SHARED
:
9082 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9084 as_bad (_("-call_shared is supported only for ELF format"));
9087 mips_pic
= SVR4_PIC
;
9088 if (g_switch_seen
&& g_switch_value
!= 0)
9090 as_bad (_("-G may not be used with SVR4 PIC code"));
9096 case OPTION_NON_SHARED
:
9097 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9099 as_bad (_("-non_shared is supported only for ELF format"));
9105 /* The -xgot option tells the assembler to use 32 offsets when
9106 accessing the got in SVR4_PIC mode. It is for Irix
9111 #endif /* OBJ_ELF */
9114 if (! USE_GLOBAL_POINTER_OPT
)
9116 as_bad (_("-G is not supported for this configuration"));
9119 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9121 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9125 g_switch_value
= atoi (arg
);
9130 /* The -32 and -64 options tell the assembler to output the 32
9131 bit or the 64 bit MIPS ELF format. */
9138 const char **list
, **l
;
9140 list
= bfd_target_list ();
9141 for (l
= list
; *l
!= NULL
; l
++)
9142 if (strcmp (*l
, "elf64-bigmips") == 0
9143 || strcmp (*l
, "elf64-littlemips") == 0
9144 || strcmp (*l
, "elf64-tradbigmips") == 0
9145 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9148 as_fatal (_("No compiled in support for 64 bit object file format"));
9153 #endif /* OBJ_ELF */
9159 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9160 flag in object files because to do so would make it
9161 impossible to link with libraries compiled without "-gp32".
9162 This is unnecessarily restrictive.
9164 We could solve this problem by adding "-gp32" multilibs to
9165 gcc, but to set this flag before gcc is built with such
9166 multilibs will break too many systems. */
9182 if (strcmp (arg
, "32") == 0
9183 || strcmp (arg
, "n32") == 0
9184 || strcmp (arg
, "64") == 0
9185 || strcmp (arg
, "o64") == 0
9186 || strcmp (arg
, "eabi") == 0)
9187 mips_abi_string
= arg
;
9190 case OPTION_M7000_HILO_FIX
:
9191 mips_7000_hilo_fix
= true;
9194 case OPTION_NO_M7000_HILO_FIX
:
9195 mips_7000_hilo_fix
= false;
9206 show (stream
, string
, col_p
, first_p
)
9214 fprintf (stream
, "%24s", "");
9219 fprintf (stream
, ", ");
9223 if (*col_p
+ strlen (string
) > 72)
9225 fprintf (stream
, "\n%24s", "");
9229 fprintf (stream
, "%s", string
);
9230 *col_p
+= strlen (string
);
9236 md_show_usage (stream
)
9241 fprintf (stream
, _("\
9243 -membedded-pic generate embedded position independent code\n\
9244 -EB generate big endian output\n\
9245 -EL generate little endian output\n\
9246 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9247 -G NUM allow referencing objects up to NUM bytes\n\
9248 implicitly with the gp register [default 8]\n"));
9249 fprintf (stream
, _("\
9250 -mips1 generate MIPS ISA I instructions\n\
9251 -mips2 generate MIPS ISA II instructions\n\
9252 -mips3 generate MIPS ISA III instructions\n\
9253 -mips4 generate MIPS ISA IV instructions\n\
9254 -mips5 generate MIPS ISA V instructions\n\
9255 -mips32 generate MIPS32 ISA instructions\n\
9256 -mips64 generate MIPS64 ISA instructions\n\
9257 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9261 show (stream
, "2000", &column
, &first
);
9262 show (stream
, "3000", &column
, &first
);
9263 show (stream
, "3900", &column
, &first
);
9264 show (stream
, "4000", &column
, &first
);
9265 show (stream
, "4010", &column
, &first
);
9266 show (stream
, "4100", &column
, &first
);
9267 show (stream
, "4111", &column
, &first
);
9268 show (stream
, "4300", &column
, &first
);
9269 show (stream
, "4400", &column
, &first
);
9270 show (stream
, "4600", &column
, &first
);
9271 show (stream
, "4650", &column
, &first
);
9272 show (stream
, "5000", &column
, &first
);
9273 show (stream
, "6000", &column
, &first
);
9274 show (stream
, "8000", &column
, &first
);
9275 show (stream
, "10000", &column
, &first
);
9276 show (stream
, "mips32-4k", &column
, &first
);
9277 show (stream
, "sb-1", &column
, &first
);
9278 fputc ('\n', stream
);
9280 fprintf (stream
, _("\
9281 -mCPU equivalent to -mcpu=CPU.\n\
9282 -no-mCPU don't generate code specific to CPU.\n\
9283 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9287 show (stream
, "3900", &column
, &first
);
9288 show (stream
, "4010", &column
, &first
);
9289 show (stream
, "4100", &column
, &first
);
9290 show (stream
, "4650", &column
, &first
);
9291 fputc ('\n', stream
);
9293 fprintf (stream
, _("\
9294 -mips16 generate mips16 instructions\n\
9295 -no-mips16 do not generate mips16 instructions\n"));
9296 fprintf (stream
, _("\
9297 -O0 remove unneeded NOPs, do not swap branches\n\
9298 -O remove unneeded NOPs and swap branches\n\
9299 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9300 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9301 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9303 fprintf (stream
, _("\
9304 -KPIC, -call_shared generate SVR4 position independent code\n\
9305 -non_shared do not generate position independent code\n\
9306 -xgot assume a 32 bit GOT\n\
9307 -32 create 32 bit object file (default)\n\
9308 -64 create 64 bit object file\n"));
9313 mips_init_after_args ()
9315 /* initialize opcodes */
9316 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9317 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9321 md_pcrel_from (fixP
)
9324 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9325 && fixP
->fx_addsy
!= (symbolS
*) NULL
9326 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9328 /* This makes a branch to an undefined symbol be a branch to the
9329 current location. */
9333 /* return the address of the delay slot */
9334 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9337 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9338 reloc for a cons. We could use the definition there, except that
9339 we want to handle 64 bit relocs specially. */
9342 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9343 fragS
*frag ATTRIBUTE_UNUSED
;
9345 unsigned int nbytes
;
9349 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9351 if (nbytes
== 8 && ! mips_64
)
9353 if (target_big_endian
)
9359 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9360 as_bad (_("Unsupported reloc size %d"), nbytes
);
9362 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9365 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9368 /* This is called before the symbol table is processed. In order to
9369 work with gcc when using mips-tfile, we must keep all local labels.
9370 However, in other cases, we want to discard them. If we were
9371 called with -g, but we didn't see any debugging information, it may
9372 mean that gcc is smuggling debugging information through to
9373 mips-tfile, in which case we must generate all local labels. */
9376 mips_frob_file_before_adjust ()
9378 #ifndef NO_ECOFF_DEBUGGING
9381 && ! ecoff_debugging_seen
)
9382 flag_keep_locals
= 1;
9386 /* Sort any unmatched HI16_S relocs so that they immediately precede
9387 the corresponding LO reloc. This is called before md_apply_fix and
9388 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9389 explicit use of the %hi modifier. */
9394 struct mips_hi_fixup
*l
;
9396 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9398 segment_info_type
*seginfo
;
9401 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9403 /* Check quickly whether the next fixup happens to be a matching
9405 if (l
->fixp
->fx_next
!= NULL
9406 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9407 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9408 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9411 /* Look through the fixups for this segment for a matching %lo.
9412 When we find one, move the %hi just in front of it. We do
9413 this in two passes. In the first pass, we try to find a
9414 unique %lo. In the second pass, we permit multiple %hi
9415 relocs for a single %lo (this is a GNU extension). */
9416 seginfo
= seg_info (l
->seg
);
9417 for (pass
= 0; pass
< 2; pass
++)
9422 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9424 /* Check whether this is a %lo fixup which matches l->fixp. */
9425 if (f
->fx_r_type
== BFD_RELOC_LO16
9426 && f
->fx_addsy
== l
->fixp
->fx_addsy
9427 && f
->fx_offset
== l
->fixp
->fx_offset
9430 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9431 || prev
->fx_addsy
!= f
->fx_addsy
9432 || prev
->fx_offset
!= f
->fx_offset
))
9436 /* Move l->fixp before f. */
9437 for (pf
= &seginfo
->fix_root
;
9439 pf
= &(*pf
)->fx_next
)
9440 assert (*pf
!= NULL
);
9442 *pf
= l
->fixp
->fx_next
;
9444 l
->fixp
->fx_next
= f
;
9446 seginfo
->fix_root
= l
->fixp
;
9448 prev
->fx_next
= l
->fixp
;
9459 #if 0 /* GCC code motion plus incomplete dead code elimination
9460 can leave a %hi without a %lo. */
9462 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9463 _("Unmatched %%hi reloc"));
9469 /* When generating embedded PIC code we need to use a special
9470 relocation to represent the difference of two symbols in the .text
9471 section (switch tables use a difference of this sort). See
9472 include/coff/mips.h for details. This macro checks whether this
9473 fixup requires the special reloc. */
9474 #define SWITCH_TABLE(fixp) \
9475 ((fixp)->fx_r_type == BFD_RELOC_32 \
9476 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9477 && (fixp)->fx_addsy != NULL \
9478 && (fixp)->fx_subsy != NULL \
9479 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9480 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9482 /* When generating embedded PIC code we must keep all PC relative
9483 relocations, in case the linker has to relax a call. We also need
9484 to keep relocations for switch table entries. */
9487 mips_force_relocation (fixp
)
9490 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9491 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9494 return (mips_pic
== EMBEDDED_PIC
9496 || SWITCH_TABLE (fixp
)
9497 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9498 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9501 /* Apply a fixup to the object file. */
9504 md_apply_fix (fixP
, valueP
)
9511 assert (fixP
->fx_size
== 4
9512 || fixP
->fx_r_type
== BFD_RELOC_16
9513 || fixP
->fx_r_type
== BFD_RELOC_64
9514 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9515 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9519 /* If we aren't adjusting this fixup to be against the section
9520 symbol, we need to adjust the value. */
9522 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9524 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9525 || S_IS_WEAK (fixP
->fx_addsy
)
9526 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9527 && (((bfd_get_section_flags (stdoutput
,
9528 S_GET_SEGMENT (fixP
->fx_addsy
))
9529 & SEC_LINK_ONCE
) != 0)
9530 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9532 sizeof (".gnu.linkonce") - 1))))
9535 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9536 if (value
!= 0 && ! fixP
->fx_pcrel
)
9538 /* In this case, the bfd_install_relocation routine will
9539 incorrectly add the symbol value back in. We just want
9540 the addend to appear in the object file.
9541 FIXME: If this makes VALUE zero, we're toast. */
9542 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9546 /* This code was generated using trial and error and so is
9547 fragile and not trustworthy. If you change it, you should
9548 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9550 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9552 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9554 /* BFD's REL handling, for MIPS, is _very_ weird.
9555 This gives the right results, but it can't possibly
9556 be the way things are supposed to work. */
9557 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9558 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9559 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9564 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9566 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9569 switch (fixP
->fx_r_type
)
9571 case BFD_RELOC_MIPS_JMP
:
9572 case BFD_RELOC_HI16
:
9573 case BFD_RELOC_HI16_S
:
9574 case BFD_RELOC_MIPS_GPREL
:
9575 case BFD_RELOC_MIPS_LITERAL
:
9576 case BFD_RELOC_MIPS_CALL16
:
9577 case BFD_RELOC_MIPS_GOT16
:
9578 case BFD_RELOC_MIPS_GPREL32
:
9579 case BFD_RELOC_MIPS_GOT_HI16
:
9580 case BFD_RELOC_MIPS_GOT_LO16
:
9581 case BFD_RELOC_MIPS_CALL_HI16
:
9582 case BFD_RELOC_MIPS_CALL_LO16
:
9583 case BFD_RELOC_MIPS16_GPREL
:
9585 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9586 _("Invalid PC relative reloc"));
9587 /* Nothing needed to do. The value comes from the reloc entry */
9590 case BFD_RELOC_MIPS16_JMP
:
9591 /* We currently always generate a reloc against a symbol, which
9592 means that we don't want an addend even if the symbol is
9594 fixP
->fx_addnumber
= 0;
9597 case BFD_RELOC_PCREL_HI16_S
:
9598 /* The addend for this is tricky if it is internal, so we just
9599 do everything here rather than in bfd_install_relocation. */
9600 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9605 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9607 /* For an external symbol adjust by the address to make it
9608 pcrel_offset. We use the address of the RELLO reloc
9609 which follows this one. */
9610 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9611 + fixP
->fx_next
->fx_where
);
9616 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9617 if (target_big_endian
)
9619 md_number_to_chars (buf
, value
, 2);
9622 case BFD_RELOC_PCREL_LO16
:
9623 /* The addend for this is tricky if it is internal, so we just
9624 do everything here rather than in bfd_install_relocation. */
9625 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9630 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9631 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9632 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9633 if (target_big_endian
)
9635 md_number_to_chars (buf
, value
, 2);
9639 /* This is handled like BFD_RELOC_32, but we output a sign
9640 extended value if we are only 32 bits. */
9642 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9644 if (8 <= sizeof (valueT
))
9645 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9652 w1
= w2
= fixP
->fx_where
;
9653 if (target_big_endian
)
9657 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9658 if ((value
& 0x80000000) != 0)
9662 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9669 /* If we are deleting this reloc entry, we must fill in the
9670 value now. This can happen if we have a .word which is not
9671 resolved when it appears but is later defined. We also need
9672 to fill in the value if this is an embedded PIC switch table
9675 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9676 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9681 /* If we are deleting this reloc entry, we must fill in the
9683 assert (fixP
->fx_size
== 2);
9685 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9689 case BFD_RELOC_LO16
:
9690 /* When handling an embedded PIC switch statement, we can wind
9691 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9694 if (value
< -0x8000 || value
> 0x7fff)
9695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9696 _("relocation overflow"));
9697 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9698 if (target_big_endian
)
9700 md_number_to_chars (buf
, value
, 2);
9704 case BFD_RELOC_16_PCREL_S2
:
9706 * We need to save the bits in the instruction since fixup_segment()
9707 * might be deleting the relocation entry (i.e., a branch within
9708 * the current segment).
9710 if ((value
& 0x3) != 0)
9711 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9712 _("Branch to odd address (%lx)"), value
);
9714 if (!fixP
->fx_done
&& value
!= 0)
9716 /* If 'value' is zero, the remaining reloc code won't actually
9717 do the store, so it must be done here. This is probably
9720 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9724 /* update old instruction data */
9725 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9726 if (target_big_endian
)
9727 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9729 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9731 if (value
>= -0x8000 && value
< 0x8000)
9732 insn
|= value
& 0xffff;
9735 /* The branch offset is too large. If this is an
9736 unconditional branch, and we are not generating PIC code,
9737 we can convert it to an absolute jump instruction. */
9738 if (mips_pic
== NO_PIC
9740 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9741 && (fixP
->fx_frag
->fr_address
9742 < text_section
->vma
+ text_section
->_raw_size
)
9743 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9744 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9745 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9747 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9748 insn
= 0x0c000000; /* jal */
9750 insn
= 0x08000000; /* j */
9751 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9753 fixP
->fx_addsy
= section_symbol (text_section
);
9754 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9758 /* FIXME. It would be possible in principle to handle
9759 conditional branches which overflow. They could be
9760 transformed into a branch around a jump. This would
9761 require setting up variant frags for each different
9762 branch type. The native MIPS assembler attempts to
9763 handle these cases, but it appears to do it
9765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9766 _("Branch out of range"));
9770 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9773 case BFD_RELOC_VTABLE_INHERIT
:
9776 && !S_IS_DEFINED (fixP
->fx_addsy
)
9777 && !S_IS_WEAK (fixP
->fx_addsy
))
9778 S_SET_WEAK (fixP
->fx_addsy
);
9781 case BFD_RELOC_VTABLE_ENTRY
:
9797 const struct mips_opcode
*p
;
9798 int treg
, sreg
, dreg
, shamt
;
9803 for (i
= 0; i
< NUMOPCODES
; ++i
)
9805 p
= &mips_opcodes
[i
];
9806 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9808 printf ("%08lx %s\t", oc
, p
->name
);
9809 treg
= (oc
>> 16) & 0x1f;
9810 sreg
= (oc
>> 21) & 0x1f;
9811 dreg
= (oc
>> 11) & 0x1f;
9812 shamt
= (oc
>> 6) & 0x1f;
9814 for (args
= p
->args
;; ++args
)
9825 printf ("%c", *args
);
9829 assert (treg
== sreg
);
9830 printf ("$%d,$%d", treg
, sreg
);
9835 printf ("$%d", dreg
);
9840 printf ("$%d", treg
);
9844 printf ("0x%x", treg
);
9849 printf ("$%d", sreg
);
9853 printf ("0x%08lx", oc
& 0x1ffffff);
9865 printf ("$%d", shamt
);
9876 printf (_("%08lx UNDEFINED\n"), oc
);
9887 name
= input_line_pointer
;
9888 c
= get_symbol_end ();
9889 p
= (symbolS
*) symbol_find_or_make (name
);
9890 *input_line_pointer
= c
;
9894 /* Align the current frag to a given power of two. The MIPS assembler
9895 also automatically adjusts any preceding label. */
9898 mips_align (to
, fill
, label
)
9903 mips_emit_delays (false);
9904 frag_align (to
, fill
, 0);
9905 record_alignment (now_seg
, to
);
9908 assert (S_GET_SEGMENT (label
) == now_seg
);
9909 symbol_set_frag (label
, frag_now
);
9910 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9914 /* Align to a given power of two. .align 0 turns off the automatic
9915 alignment used by the data creating pseudo-ops. */
9919 int x ATTRIBUTE_UNUSED
;
9922 register long temp_fill
;
9923 long max_alignment
= 15;
9927 o Note that the assembler pulls down any immediately preceeding label
9928 to the aligned address.
9929 o It's not documented but auto alignment is reinstated by
9930 a .align pseudo instruction.
9931 o Note also that after auto alignment is turned off the mips assembler
9932 issues an error on attempt to assemble an improperly aligned data item.
9937 temp
= get_absolute_expression ();
9938 if (temp
> max_alignment
)
9939 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9942 as_warn (_("Alignment negative: 0 assumed."));
9945 if (*input_line_pointer
== ',')
9947 input_line_pointer
++;
9948 temp_fill
= get_absolute_expression ();
9955 mips_align (temp
, (int) temp_fill
,
9956 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9963 demand_empty_rest_of_line ();
9967 mips_flush_pending_output ()
9969 mips_emit_delays (false);
9970 mips_clear_insn_labels ();
9979 /* When generating embedded PIC code, we only use the .text, .lit8,
9980 .sdata and .sbss sections. We change the .data and .rdata
9981 pseudo-ops to use .sdata. */
9982 if (mips_pic
== EMBEDDED_PIC
9983 && (sec
== 'd' || sec
== 'r'))
9987 /* The ELF backend needs to know that we are changing sections, so
9988 that .previous works correctly. We could do something like check
9989 for a obj_section_change_hook macro, but that might be confusing
9990 as it would not be appropriate to use it in the section changing
9991 functions in read.c, since obj-elf.c intercepts those. FIXME:
9992 This should be cleaner, somehow. */
9993 obj_elf_section_change_hook ();
9996 mips_emit_delays (false);
10006 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10007 demand_empty_rest_of_line ();
10011 if (USE_GLOBAL_POINTER_OPT
)
10013 seg
= subseg_new (RDATA_SECTION_NAME
,
10014 (subsegT
) get_absolute_expression ());
10015 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10017 bfd_set_section_flags (stdoutput
, seg
,
10023 if (strcmp (TARGET_OS
, "elf") != 0)
10024 record_alignment (seg
, 4);
10026 demand_empty_rest_of_line ();
10030 as_bad (_("No read only data section in this object file format"));
10031 demand_empty_rest_of_line ();
10037 if (USE_GLOBAL_POINTER_OPT
)
10039 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10040 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10042 bfd_set_section_flags (stdoutput
, seg
,
10043 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10045 if (strcmp (TARGET_OS
, "elf") != 0)
10046 record_alignment (seg
, 4);
10048 demand_empty_rest_of_line ();
10053 as_bad (_("Global pointers not supported; recompile -G 0"));
10054 demand_empty_rest_of_line ();
10063 mips_enable_auto_align ()
10074 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10075 mips_emit_delays (false);
10076 if (log_size
> 0 && auto_align
)
10077 mips_align (log_size
, 0, label
);
10078 mips_clear_insn_labels ();
10079 cons (1 << log_size
);
10083 s_float_cons (type
)
10088 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10090 mips_emit_delays (false);
10095 mips_align (3, 0, label
);
10097 mips_align (2, 0, label
);
10100 mips_clear_insn_labels ();
10105 /* Handle .globl. We need to override it because on Irix 5 you are
10108 where foo is an undefined symbol, to mean that foo should be
10109 considered to be the address of a function. */
10113 int x ATTRIBUTE_UNUSED
;
10120 name
= input_line_pointer
;
10121 c
= get_symbol_end ();
10122 symbolP
= symbol_find_or_make (name
);
10123 *input_line_pointer
= c
;
10124 SKIP_WHITESPACE ();
10126 /* On Irix 5, every global symbol that is not explicitly labelled as
10127 being a function is apparently labelled as being an object. */
10130 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10135 secname
= input_line_pointer
;
10136 c
= get_symbol_end ();
10137 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10139 as_bad (_("%s: no such section"), secname
);
10140 *input_line_pointer
= c
;
10142 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10143 flag
= BSF_FUNCTION
;
10146 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10148 S_SET_EXTERNAL (symbolP
);
10149 demand_empty_rest_of_line ();
10154 int x ATTRIBUTE_UNUSED
;
10159 opt
= input_line_pointer
;
10160 c
= get_symbol_end ();
10164 /* FIXME: What does this mean? */
10166 else if (strncmp (opt
, "pic", 3) == 0)
10170 i
= atoi (opt
+ 3);
10174 mips_pic
= SVR4_PIC
;
10176 as_bad (_(".option pic%d not supported"), i
);
10178 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10180 if (g_switch_seen
&& g_switch_value
!= 0)
10181 as_warn (_("-G may not be used with SVR4 PIC code"));
10182 g_switch_value
= 0;
10183 bfd_set_gp_size (stdoutput
, 0);
10187 as_warn (_("Unrecognized option \"%s\""), opt
);
10189 *input_line_pointer
= c
;
10190 demand_empty_rest_of_line ();
10193 /* This structure is used to hold a stack of .set values. */
10195 struct mips_option_stack
10197 struct mips_option_stack
*next
;
10198 struct mips_set_options options
;
10201 static struct mips_option_stack
*mips_opts_stack
;
10203 /* Handle the .set pseudo-op. */
10207 int x ATTRIBUTE_UNUSED
;
10209 char *name
= input_line_pointer
, ch
;
10211 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10212 input_line_pointer
++;
10213 ch
= *input_line_pointer
;
10214 *input_line_pointer
= '\0';
10216 if (strcmp (name
, "reorder") == 0)
10218 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10220 /* If we still have pending nops, we can discard them. The
10221 usual nop handling will insert any that are still
10223 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10224 * (mips_opts
.mips16
? 2 : 4));
10225 prev_nop_frag
= NULL
;
10227 mips_opts
.noreorder
= 0;
10229 else if (strcmp (name
, "noreorder") == 0)
10231 mips_emit_delays (true);
10232 mips_opts
.noreorder
= 1;
10233 mips_any_noreorder
= 1;
10235 else if (strcmp (name
, "at") == 0)
10237 mips_opts
.noat
= 0;
10239 else if (strcmp (name
, "noat") == 0)
10241 mips_opts
.noat
= 1;
10243 else if (strcmp (name
, "macro") == 0)
10245 mips_opts
.warn_about_macros
= 0;
10247 else if (strcmp (name
, "nomacro") == 0)
10249 if (mips_opts
.noreorder
== 0)
10250 as_bad (_("`noreorder' must be set before `nomacro'"));
10251 mips_opts
.warn_about_macros
= 1;
10253 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10255 mips_opts
.nomove
= 0;
10257 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10259 mips_opts
.nomove
= 1;
10261 else if (strcmp (name
, "bopt") == 0)
10263 mips_opts
.nobopt
= 0;
10265 else if (strcmp (name
, "nobopt") == 0)
10267 mips_opts
.nobopt
= 1;
10269 else if (strcmp (name
, "mips16") == 0
10270 || strcmp (name
, "MIPS-16") == 0)
10271 mips_opts
.mips16
= 1;
10272 else if (strcmp (name
, "nomips16") == 0
10273 || strcmp (name
, "noMIPS-16") == 0)
10274 mips_opts
.mips16
= 0;
10275 else if (strncmp (name
, "mips", 4) == 0)
10279 /* Permit the user to change the ISA on the fly. Needless to
10280 say, misuse can cause serious problems. */
10281 isa
= atoi (name
+ 4);
10284 case 0: mips_opts
.isa
= file_mips_isa
; break;
10285 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
10286 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
10287 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
10288 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
10289 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
10290 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
10291 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
10292 default: as_bad (_("unknown ISA level")); break;
10295 else if (strcmp (name
, "autoextend") == 0)
10296 mips_opts
.noautoextend
= 0;
10297 else if (strcmp (name
, "noautoextend") == 0)
10298 mips_opts
.noautoextend
= 1;
10299 else if (strcmp (name
, "push") == 0)
10301 struct mips_option_stack
*s
;
10303 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10304 s
->next
= mips_opts_stack
;
10305 s
->options
= mips_opts
;
10306 mips_opts_stack
= s
;
10308 else if (strcmp (name
, "pop") == 0)
10310 struct mips_option_stack
*s
;
10312 s
= mips_opts_stack
;
10314 as_bad (_(".set pop with no .set push"));
10317 /* If we're changing the reorder mode we need to handle
10318 delay slots correctly. */
10319 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10320 mips_emit_delays (true);
10321 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10323 if (prev_nop_frag
!= NULL
)
10325 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10326 * (mips_opts
.mips16
? 2 : 4));
10327 prev_nop_frag
= NULL
;
10331 mips_opts
= s
->options
;
10332 mips_opts_stack
= s
->next
;
10338 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10340 *input_line_pointer
= ch
;
10341 demand_empty_rest_of_line ();
10344 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10345 .option pic2. It means to generate SVR4 PIC calls. */
10348 s_abicalls (ignore
)
10349 int ignore ATTRIBUTE_UNUSED
;
10351 mips_pic
= SVR4_PIC
;
10352 if (USE_GLOBAL_POINTER_OPT
)
10354 if (g_switch_seen
&& g_switch_value
!= 0)
10355 as_warn (_("-G may not be used with SVR4 PIC code"));
10356 g_switch_value
= 0;
10358 bfd_set_gp_size (stdoutput
, 0);
10359 demand_empty_rest_of_line ();
10362 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10363 PIC code. It sets the $gp register for the function based on the
10364 function address, which is in the register named in the argument.
10365 This uses a relocation against _gp_disp, which is handled specially
10366 by the linker. The result is:
10367 lui $gp,%hi(_gp_disp)
10368 addiu $gp,$gp,%lo(_gp_disp)
10369 addu $gp,$gp,.cpload argument
10370 The .cpload argument is normally $25 == $t9. */
10374 int ignore ATTRIBUTE_UNUSED
;
10379 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10380 if (mips_pic
!= SVR4_PIC
)
10386 /* .cpload should be a in .set noreorder section. */
10387 if (mips_opts
.noreorder
== 0)
10388 as_warn (_(".cpload not in noreorder section"));
10390 ex
.X_op
= O_symbol
;
10391 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10392 ex
.X_op_symbol
= NULL
;
10393 ex
.X_add_number
= 0;
10395 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10396 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10398 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10399 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10400 (int) BFD_RELOC_LO16
);
10402 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10403 GP
, GP
, tc_get_register (0));
10405 demand_empty_rest_of_line ();
10408 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10409 offset from $sp. The offset is remembered, and after making a PIC
10410 call $gp is restored from that location. */
10413 s_cprestore (ignore
)
10414 int ignore ATTRIBUTE_UNUSED
;
10419 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10420 if (mips_pic
!= SVR4_PIC
)
10426 mips_cprestore_offset
= get_absolute_expression ();
10428 ex
.X_op
= O_constant
;
10429 ex
.X_add_symbol
= NULL
;
10430 ex
.X_op_symbol
= NULL
;
10431 ex
.X_add_number
= mips_cprestore_offset
;
10433 macro_build ((char *) NULL
, &icnt
, &ex
,
10434 ((bfd_arch_bits_per_address (stdoutput
) == 32
10435 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10437 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10439 demand_empty_rest_of_line ();
10442 /* Handle the .gpword pseudo-op. This is used when generating PIC
10443 code. It generates a 32 bit GP relative reloc. */
10447 int ignore ATTRIBUTE_UNUSED
;
10453 /* When not generating PIC code, this is treated as .word. */
10454 if (mips_pic
!= SVR4_PIC
)
10460 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10461 mips_emit_delays (true);
10463 mips_align (2, 0, label
);
10464 mips_clear_insn_labels ();
10468 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10470 as_bad (_("Unsupported use of .gpword"));
10471 ignore_rest_of_line ();
10475 md_number_to_chars (p
, (valueT
) 0, 4);
10476 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10477 BFD_RELOC_MIPS_GPREL32
);
10479 demand_empty_rest_of_line ();
10482 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10483 tables in SVR4 PIC code. */
10487 int ignore ATTRIBUTE_UNUSED
;
10492 /* This is ignored when not generating SVR4 PIC code. */
10493 if (mips_pic
!= SVR4_PIC
)
10499 /* Add $gp to the register named as an argument. */
10500 reg
= tc_get_register (0);
10501 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10502 ((bfd_arch_bits_per_address (stdoutput
) == 32
10503 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10504 ? "addu" : "daddu"),
10505 "d,v,t", reg
, reg
, GP
);
10507 demand_empty_rest_of_line ();
10510 /* Handle the .insn pseudo-op. This marks instruction labels in
10511 mips16 mode. This permits the linker to handle them specially,
10512 such as generating jalx instructions when needed. We also make
10513 them odd for the duration of the assembly, in order to generate the
10514 right sort of code. We will make them even in the adjust_symtab
10515 routine, while leaving them marked. This is convenient for the
10516 debugger and the disassembler. The linker knows to make them odd
10521 int ignore ATTRIBUTE_UNUSED
;
10523 if (mips_opts
.mips16
)
10524 mips16_mark_labels ();
10526 demand_empty_rest_of_line ();
10529 /* Handle a .stabn directive. We need these in order to mark a label
10530 as being a mips16 text label correctly. Sometimes the compiler
10531 will emit a label, followed by a .stabn, and then switch sections.
10532 If the label and .stabn are in mips16 mode, then the label is
10533 really a mips16 text label. */
10539 if (type
== 'n' && mips_opts
.mips16
)
10540 mips16_mark_labels ();
10545 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10549 s_mips_weakext (ignore
)
10550 int ignore ATTRIBUTE_UNUSED
;
10557 name
= input_line_pointer
;
10558 c
= get_symbol_end ();
10559 symbolP
= symbol_find_or_make (name
);
10560 S_SET_WEAK (symbolP
);
10561 *input_line_pointer
= c
;
10563 SKIP_WHITESPACE ();
10565 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10567 if (S_IS_DEFINED (symbolP
))
10569 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10570 S_GET_NAME (symbolP
));
10571 ignore_rest_of_line ();
10575 if (*input_line_pointer
== ',')
10577 ++input_line_pointer
;
10578 SKIP_WHITESPACE ();
10582 if (exp
.X_op
!= O_symbol
)
10584 as_bad ("bad .weakext directive");
10585 ignore_rest_of_line();
10588 symbol_set_value_expression (symbolP
, &exp
);
10591 demand_empty_rest_of_line ();
10594 /* Parse a register string into a number. Called from the ECOFF code
10595 to parse .frame. The argument is non-zero if this is the frame
10596 register, so that we can record it in mips_frame_reg. */
10599 tc_get_register (frame
)
10604 SKIP_WHITESPACE ();
10605 if (*input_line_pointer
++ != '$')
10607 as_warn (_("expected `$'"));
10610 else if (isdigit ((unsigned char) *input_line_pointer
))
10612 reg
= get_absolute_expression ();
10613 if (reg
< 0 || reg
>= 32)
10615 as_warn (_("Bad register number"));
10621 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10623 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10625 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10627 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10631 as_warn (_("Unrecognized register name"));
10634 input_line_pointer
+= 2;
10637 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10642 md_section_align (seg
, addr
)
10646 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10649 /* We don't need to align ELF sections to the full alignment.
10650 However, Irix 5 may prefer that we align them at least to a 16
10651 byte boundary. We don't bother to align the sections if we are
10652 targeted for an embedded system. */
10653 if (strcmp (TARGET_OS
, "elf") == 0)
10659 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10662 /* Utility routine, called from above as well. If called while the
10663 input file is still being read, it's only an approximation. (For
10664 example, a symbol may later become defined which appeared to be
10665 undefined earlier.) */
10668 nopic_need_relax (sym
, before_relaxing
)
10670 int before_relaxing
;
10675 if (USE_GLOBAL_POINTER_OPT
)
10677 const char *symname
;
10680 /* Find out whether this symbol can be referenced off the GP
10681 register. It can be if it is smaller than the -G size or if
10682 it is in the .sdata or .sbss section. Certain symbols can
10683 not be referenced off the GP, although it appears as though
10685 symname
= S_GET_NAME (sym
);
10686 if (symname
!= (const char *) NULL
10687 && (strcmp (symname
, "eprol") == 0
10688 || strcmp (symname
, "etext") == 0
10689 || strcmp (symname
, "_gp") == 0
10690 || strcmp (symname
, "edata") == 0
10691 || strcmp (symname
, "_fbss") == 0
10692 || strcmp (symname
, "_fdata") == 0
10693 || strcmp (symname
, "_ftext") == 0
10694 || strcmp (symname
, "end") == 0
10695 || strcmp (symname
, "_gp_disp") == 0))
10697 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10699 #ifndef NO_ECOFF_DEBUGGING
10700 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10701 && (symbol_get_obj (sym
)->ecoff_extern_size
10702 <= g_switch_value
))
10704 /* We must defer this decision until after the whole
10705 file has been read, since there might be a .extern
10706 after the first use of this symbol. */
10707 || (before_relaxing
10708 #ifndef NO_ECOFF_DEBUGGING
10709 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10711 && S_GET_VALUE (sym
) == 0)
10712 || (S_GET_VALUE (sym
) != 0
10713 && S_GET_VALUE (sym
) <= g_switch_value
)))
10717 const char *segname
;
10719 segname
= segment_name (S_GET_SEGMENT (sym
));
10720 assert (strcmp (segname
, ".lit8") != 0
10721 && strcmp (segname
, ".lit4") != 0);
10722 change
= (strcmp (segname
, ".sdata") != 0
10723 && strcmp (segname
, ".sbss") != 0
10724 && strncmp (segname
, ".sdata.", 7) != 0
10725 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10730 /* We are not optimizing for the GP register. */
10734 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10735 extended opcode. SEC is the section the frag is in. */
10738 mips16_extended_frag (fragp
, sec
, stretch
)
10744 register const struct mips16_immed_operand
*op
;
10746 int mintiny
, maxtiny
;
10749 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10751 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10754 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10755 op
= mips16_immed_operands
;
10756 while (op
->type
!= type
)
10759 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10764 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10767 maxtiny
= 1 << op
->nbits
;
10772 maxtiny
= (1 << op
->nbits
) - 1;
10777 mintiny
= - (1 << (op
->nbits
- 1));
10778 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10781 /* We can't always call S_GET_VALUE here, because we don't want to
10782 lock in a particular frag address. */
10783 if (symbol_constant_p (fragp
->fr_symbol
))
10785 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10786 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10787 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10789 else if (symbol_equated_p (fragp
->fr_symbol
)
10790 && (symbol_constant_p
10791 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10795 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10796 val
= (S_GET_VALUE (eqsym
)
10797 + symbol_get_frag (eqsym
)->fr_address
10798 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10799 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10800 symsec
= S_GET_SEGMENT (eqsym
);
10809 /* We won't have the section when we are called from
10810 mips_relax_frag. However, we will always have been called
10811 from md_estimate_size_before_relax first. If this is a
10812 branch to a different section, we mark it as such. If SEC is
10813 NULL, and the frag is not marked, then it must be a branch to
10814 the same section. */
10817 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10824 fragp
->fr_subtype
=
10825 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10827 /* FIXME: We should support this, and let the linker
10828 catch branches and loads that are out of range. */
10829 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10830 _("unsupported PC relative reference to different section"));
10836 /* In this case, we know for sure that the symbol fragment is in
10837 the same section. If the fr_address of the symbol fragment
10838 is greater then the address of this fragment we want to add
10839 in STRETCH in order to get a better estimate of the address.
10840 This particularly matters because of the shift bits. */
10842 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10843 >= fragp
->fr_address
))
10847 /* Adjust stretch for any alignment frag. Note that if have
10848 been expanding the earlier code, the symbol may be
10849 defined in what appears to be an earlier frag. FIXME:
10850 This doesn't handle the fr_subtype field, which specifies
10851 a maximum number of bytes to skip when doing an
10854 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10857 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10860 stretch
= - ((- stretch
)
10861 & ~ ((1 << (int) f
->fr_offset
) - 1));
10863 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10872 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10874 /* The base address rules are complicated. The base address of
10875 a branch is the following instruction. The base address of a
10876 PC relative load or add is the instruction itself, but if it
10877 is in a delay slot (in which case it can not be extended) use
10878 the address of the instruction whose delay slot it is in. */
10879 if (type
== 'p' || type
== 'q')
10883 /* If we are currently assuming that this frag should be
10884 extended, then, the current address is two bytes
10886 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10889 /* Ignore the low bit in the target, since it will be set
10890 for a text label. */
10891 if ((val
& 1) != 0)
10894 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10896 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10899 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10901 /* Branch offsets have an implicit 0 in the lowest bit. */
10902 if (type
== 'p' || type
== 'q')
10905 /* If any of the shifted bits are set, we must use an extended
10906 opcode. If the address depends on the size of this
10907 instruction, this can lead to a loop, so we arrange to always
10908 use an extended opcode. We only check this when we are in
10909 the main relaxation loop, when SEC is NULL. */
10910 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10912 fragp
->fr_subtype
=
10913 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10917 /* If we are about to mark a frag as extended because the value
10918 is precisely maxtiny + 1, then there is a chance of an
10919 infinite loop as in the following code:
10924 In this case when the la is extended, foo is 0x3fc bytes
10925 away, so the la can be shrunk, but then foo is 0x400 away, so
10926 the la must be extended. To avoid this loop, we mark the
10927 frag as extended if it was small, and is about to become
10928 extended with a value of maxtiny + 1. */
10929 if (val
== ((maxtiny
+ 1) << op
->shift
)
10930 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10933 fragp
->fr_subtype
=
10934 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10938 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10939 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10941 if ((val
& ((1 << op
->shift
) - 1)) != 0
10942 || val
< (mintiny
<< op
->shift
)
10943 || val
> (maxtiny
<< op
->shift
))
10949 /* Estimate the size of a frag before relaxing. Unless this is the
10950 mips16, we are not really relaxing here, and the final size is
10951 encoded in the subtype information. For the mips16, we have to
10952 decide whether we are using an extended opcode or not. */
10955 md_estimate_size_before_relax (fragp
, segtype
)
10960 boolean linkonce
= false;
10962 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10964 if (mips16_extended_frag (fragp
, segtype
, 0))
10966 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10971 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10976 if (mips_pic
== NO_PIC
)
10978 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10980 else if (mips_pic
== SVR4_PIC
)
10985 sym
= fragp
->fr_symbol
;
10987 /* Handle the case of a symbol equated to another symbol. */
10988 while (symbol_equated_p (sym
)
10989 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10993 /* It's possible to get a loop here in a badly written
10995 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11001 symsec
= S_GET_SEGMENT (sym
);
11003 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11004 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11006 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11010 /* The GNU toolchain uses an extension for ELF: a section
11011 beginning with the magic string .gnu.linkonce is a linkonce
11013 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11014 sizeof ".gnu.linkonce" - 1) == 0)
11018 /* This must duplicate the test in adjust_reloc_syms. */
11019 change
= (symsec
!= &bfd_und_section
11020 && symsec
!= &bfd_abs_section
11021 && ! bfd_is_com_section (symsec
)
11024 /* A weak symbol is treated as external. */
11025 && ! S_IS_WEAK (sym
)
11034 /* Record the offset to the first reloc in the fr_opcode field.
11035 This lets md_convert_frag and tc_gen_reloc know that the code
11036 must be expanded. */
11037 fragp
->fr_opcode
= (fragp
->fr_literal
11039 - RELAX_OLD (fragp
->fr_subtype
)
11040 + RELAX_RELOC1 (fragp
->fr_subtype
));
11041 /* FIXME: This really needs as_warn_where. */
11042 if (RELAX_WARN (fragp
->fr_subtype
))
11043 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11049 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11052 /* This is called to see whether a reloc against a defined symbol
11053 should be converted into a reloc against a section. Don't adjust
11054 MIPS16 jump relocations, so we don't have to worry about the format
11055 of the offset in the .o file. Don't adjust relocations against
11056 mips16 symbols, so that the linker can find them if it needs to set
11060 mips_fix_adjustable (fixp
)
11063 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11065 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11066 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11068 if (fixp
->fx_addsy
== NULL
)
11071 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11072 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11073 && fixp
->fx_subsy
== NULL
)
11079 /* Translate internal representation of relocation info to BFD target
11083 tc_gen_reloc (section
, fixp
)
11084 asection
*section ATTRIBUTE_UNUSED
;
11087 static arelent
*retval
[4];
11089 bfd_reloc_code_real_type code
;
11091 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11094 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11095 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11096 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11098 if (mips_pic
== EMBEDDED_PIC
11099 && SWITCH_TABLE (fixp
))
11101 /* For a switch table entry we use a special reloc. The addend
11102 is actually the difference between the reloc address and the
11104 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11105 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11106 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11107 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11109 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11110 reloc
->addend
= fixp
->fx_addnumber
;
11111 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11113 /* We use a special addend for an internal RELLO reloc. */
11114 if (symbol_section_p (fixp
->fx_addsy
))
11115 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11117 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11119 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11121 assert (fixp
->fx_next
!= NULL
11122 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11123 /* We use a special addend for an internal RELHI reloc. The
11124 reloc is relative to the RELLO; adjust the addend
11126 if (symbol_section_p (fixp
->fx_addsy
))
11127 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11128 + fixp
->fx_next
->fx_where
11129 - S_GET_VALUE (fixp
->fx_subsy
));
11131 reloc
->addend
= (fixp
->fx_addnumber
11132 + fixp
->fx_next
->fx_frag
->fr_address
11133 + fixp
->fx_next
->fx_where
);
11137 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11138 /* A gruesome hack which is a result of the gruesome gas reloc
11140 reloc
->addend
= reloc
->address
;
11142 reloc
->addend
= -reloc
->address
;
11145 /* If this is a variant frag, we may need to adjust the existing
11146 reloc and generate a new one. */
11147 if (fixp
->fx_frag
->fr_opcode
!= NULL
11148 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11149 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11150 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11151 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11152 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11153 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11154 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11158 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11160 /* If this is not the last reloc in this frag, then we have two
11161 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11162 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11163 the second one handle all of them. */
11164 if (fixp
->fx_next
!= NULL
11165 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11167 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11168 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11169 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11170 && (fixp
->fx_next
->fx_r_type
11171 == BFD_RELOC_MIPS_GOT_LO16
))
11172 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11173 && (fixp
->fx_next
->fx_r_type
11174 == BFD_RELOC_MIPS_CALL_LO16
)));
11179 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11180 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11181 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11183 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11184 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11185 reloc2
->address
= (reloc
->address
11186 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11187 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11188 reloc2
->addend
= fixp
->fx_addnumber
;
11189 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11190 assert (reloc2
->howto
!= NULL
);
11192 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11196 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11199 reloc3
->address
+= 4;
11202 if (mips_pic
== NO_PIC
)
11204 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11205 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11207 else if (mips_pic
== SVR4_PIC
)
11209 switch (fixp
->fx_r_type
)
11213 case BFD_RELOC_MIPS_GOT16
:
11215 case BFD_RELOC_MIPS_CALL16
:
11216 case BFD_RELOC_MIPS_GOT_LO16
:
11217 case BFD_RELOC_MIPS_CALL_LO16
:
11218 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11226 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11227 to be used in the relocation's section offset. */
11228 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11230 reloc
->address
= reloc
->addend
;
11234 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11235 fixup_segment converted a non-PC relative reloc into a PC
11236 relative reloc. In such a case, we need to convert the reloc
11238 code
= fixp
->fx_r_type
;
11239 if (fixp
->fx_pcrel
)
11244 code
= BFD_RELOC_8_PCREL
;
11247 code
= BFD_RELOC_16_PCREL
;
11250 code
= BFD_RELOC_32_PCREL
;
11253 code
= BFD_RELOC_64_PCREL
;
11255 case BFD_RELOC_8_PCREL
:
11256 case BFD_RELOC_16_PCREL
:
11257 case BFD_RELOC_32_PCREL
:
11258 case BFD_RELOC_64_PCREL
:
11259 case BFD_RELOC_16_PCREL_S2
:
11260 case BFD_RELOC_PCREL_HI16_S
:
11261 case BFD_RELOC_PCREL_LO16
:
11264 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11265 _("Cannot make %s relocation PC relative"),
11266 bfd_get_reloc_code_name (code
));
11270 /* To support a PC relative reloc when generating embedded PIC code
11271 for ECOFF, we use a Cygnus extension. We check for that here to
11272 make sure that we don't let such a reloc escape normally. */
11273 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11274 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11275 && code
== BFD_RELOC_16_PCREL_S2
11276 && mips_pic
!= EMBEDDED_PIC
)
11277 reloc
->howto
= NULL
;
11279 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11281 if (reloc
->howto
== NULL
)
11283 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11284 _("Can not represent %s relocation in this object file format"),
11285 bfd_get_reloc_code_name (code
));
11292 /* Relax a machine dependent frag. This returns the amount by which
11293 the current size of the frag should change. */
11296 mips_relax_frag (fragp
, stretch
)
11300 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11303 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11305 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11307 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11312 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11314 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11321 /* Convert a machine dependent frag. */
11324 md_convert_frag (abfd
, asec
, fragp
)
11325 bfd
*abfd ATTRIBUTE_UNUSED
;
11332 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11335 register const struct mips16_immed_operand
*op
;
11336 boolean small
, ext
;
11339 unsigned long insn
;
11340 boolean use_extend
;
11341 unsigned short extend
;
11343 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11344 op
= mips16_immed_operands
;
11345 while (op
->type
!= type
)
11348 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11359 resolve_symbol_value (fragp
->fr_symbol
, finalize_syms
);
11360 val
= S_GET_VALUE (fragp
->fr_symbol
);
11365 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11367 /* The rules for the base address of a PC relative reloc are
11368 complicated; see mips16_extended_frag. */
11369 if (type
== 'p' || type
== 'q')
11374 /* Ignore the low bit in the target, since it will be
11375 set for a text label. */
11376 if ((val
& 1) != 0)
11379 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11381 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11384 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11387 /* Make sure the section winds up with the alignment we have
11390 record_alignment (asec
, op
->shift
);
11394 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11395 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11396 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11397 _("extended instruction in delay slot"));
11399 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11401 if (target_big_endian
)
11402 insn
= bfd_getb16 (buf
);
11404 insn
= bfd_getl16 (buf
);
11406 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11407 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11408 small
, ext
, &insn
, &use_extend
, &extend
);
11412 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11413 fragp
->fr_fix
+= 2;
11417 md_number_to_chars (buf
, insn
, 2);
11418 fragp
->fr_fix
+= 2;
11423 if (fragp
->fr_opcode
== NULL
)
11426 old
= RELAX_OLD (fragp
->fr_subtype
);
11427 new = RELAX_NEW (fragp
->fr_subtype
);
11428 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11431 memcpy (fixptr
- old
, fixptr
, new);
11433 fragp
->fr_fix
+= new - old
;
11439 /* This function is called after the relocs have been generated.
11440 We've been storing mips16 text labels as odd. Here we convert them
11441 back to even for the convenience of the debugger. */
11444 mips_frob_file_after_relocs ()
11447 unsigned int count
, i
;
11449 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11452 syms
= bfd_get_outsymbols (stdoutput
);
11453 count
= bfd_get_symcount (stdoutput
);
11454 for (i
= 0; i
< count
; i
++, syms
++)
11456 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11457 && ((*syms
)->value
& 1) != 0)
11459 (*syms
)->value
&= ~1;
11460 /* If the symbol has an odd size, it was probably computed
11461 incorrectly, so adjust that as well. */
11462 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11463 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11470 /* This function is called whenever a label is defined. It is used
11471 when handling branch delays; if a branch has a label, we assume we
11472 can not move it. */
11475 mips_define_label (sym
)
11478 struct insn_label_list
*l
;
11480 if (free_insn_labels
== NULL
)
11481 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11484 l
= free_insn_labels
;
11485 free_insn_labels
= l
->next
;
11489 l
->next
= insn_labels
;
11493 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11495 /* Some special processing for a MIPS ELF file. */
11498 mips_elf_final_processing ()
11500 /* Write out the register information. */
11505 s
.ri_gprmask
= mips_gprmask
;
11506 s
.ri_cprmask
[0] = mips_cprmask
[0];
11507 s
.ri_cprmask
[1] = mips_cprmask
[1];
11508 s
.ri_cprmask
[2] = mips_cprmask
[2];
11509 s
.ri_cprmask
[3] = mips_cprmask
[3];
11510 /* The gp_value field is set by the MIPS ELF backend. */
11512 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11513 ((Elf32_External_RegInfo
*)
11514 mips_regmask_frag
));
11518 Elf64_Internal_RegInfo s
;
11520 s
.ri_gprmask
= mips_gprmask
;
11522 s
.ri_cprmask
[0] = mips_cprmask
[0];
11523 s
.ri_cprmask
[1] = mips_cprmask
[1];
11524 s
.ri_cprmask
[2] = mips_cprmask
[2];
11525 s
.ri_cprmask
[3] = mips_cprmask
[3];
11526 /* The gp_value field is set by the MIPS ELF backend. */
11528 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11529 ((Elf64_External_RegInfo
*)
11530 mips_regmask_frag
));
11533 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11534 sort of BFD interface for this. */
11535 if (mips_any_noreorder
)
11536 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11537 if (mips_pic
!= NO_PIC
)
11538 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11540 /* Set the MIPS ELF ABI flags. */
11541 if (mips_abi_string
== 0)
11543 else if (strcmp (mips_abi_string
, "32") == 0)
11544 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11545 else if (strcmp (mips_abi_string
, "o64") == 0)
11546 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11547 else if (strcmp (mips_abi_string
, "eabi") == 0)
11550 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11552 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11555 if (mips_32bitmode
)
11556 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11559 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11561 typedef struct proc
{
11563 unsigned long reg_mask
;
11564 unsigned long reg_offset
;
11565 unsigned long fpreg_mask
;
11566 unsigned long fpreg_offset
;
11567 unsigned long frame_offset
;
11568 unsigned long frame_reg
;
11569 unsigned long pc_reg
;
11572 static procS cur_proc
;
11573 static procS
*cur_proc_ptr
;
11574 static int numprocs
;
11576 /* Fill in an rs_align_code fragment. */
11579 mips_handle_align (fragp
)
11582 if (fragp
->fr_type
!= rs_align_code
)
11585 if (mips_opts
.mips16
)
11587 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11588 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11593 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
11594 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
11599 fragp
->fr_fix
+= 1;
11602 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
11606 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
11617 /* check for premature end, nesting errors, etc */
11619 as_warn (_("missing `.end' at end of assembly"));
11628 if (*input_line_pointer
== '-')
11630 ++input_line_pointer
;
11633 if (!isdigit ((unsigned char) *input_line_pointer
))
11634 as_bad (_("Expected simple number."));
11635 if (input_line_pointer
[0] == '0')
11637 if (input_line_pointer
[1] == 'x')
11639 input_line_pointer
+= 2;
11640 while (isxdigit ((unsigned char) *input_line_pointer
))
11643 val
|= hex_value (*input_line_pointer
++);
11645 return negative
? -val
: val
;
11649 ++input_line_pointer
;
11650 while (isdigit ((unsigned char) *input_line_pointer
))
11653 val
|= *input_line_pointer
++ - '0';
11655 return negative
? -val
: val
;
11658 if (!isdigit ((unsigned char) *input_line_pointer
))
11660 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11661 *input_line_pointer
, *input_line_pointer
);
11662 as_warn (_("Invalid number"));
11665 while (isdigit ((unsigned char) *input_line_pointer
))
11668 val
+= *input_line_pointer
++ - '0';
11670 return negative
? -val
: val
;
11673 /* The .file directive; just like the usual .file directive, but there
11674 is an initial number which is the ECOFF file index. */
11678 int x ATTRIBUTE_UNUSED
;
11682 line
= get_number ();
11686 /* The .end directive. */
11690 int x ATTRIBUTE_UNUSED
;
11695 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11698 demand_empty_rest_of_line ();
11703 #ifdef BFD_ASSEMBLER
11704 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11709 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11716 as_warn (_(".end not in text section"));
11720 as_warn (_(".end directive without a preceding .ent directive."));
11721 demand_empty_rest_of_line ();
11727 assert (S_GET_NAME (p
));
11728 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11729 as_warn (_(".end symbol does not match .ent symbol."));
11732 as_warn (_(".end directive missing or unknown symbol"));
11734 #ifdef MIPS_STABS_ELF
11736 segT saved_seg
= now_seg
;
11737 subsegT saved_subseg
= now_subseg
;
11738 fragS
*saved_frag
= frag_now
;
11744 dot
= frag_now_fix ();
11746 #ifdef md_flush_pending_output
11747 md_flush_pending_output ();
11751 subseg_set (pdr_seg
, 0);
11753 /* Write the symbol. */
11754 exp
.X_op
= O_symbol
;
11755 exp
.X_add_symbol
= p
;
11756 exp
.X_add_number
= 0;
11757 emit_expr (&exp
, 4);
11759 fragp
= frag_more (7 * 4);
11761 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11762 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11763 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11764 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11765 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11766 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11767 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11769 subseg_set (saved_seg
, saved_subseg
);
11773 cur_proc_ptr
= NULL
;
11776 /* The .aent and .ent directives. */
11786 symbolP
= get_symbol ();
11787 if (*input_line_pointer
== ',')
11788 input_line_pointer
++;
11789 SKIP_WHITESPACE ();
11790 if (isdigit ((unsigned char) *input_line_pointer
)
11791 || *input_line_pointer
== '-')
11792 number
= get_number ();
11794 #ifdef BFD_ASSEMBLER
11795 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11800 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11807 as_warn (_(".ent or .aent not in text section."));
11809 if (!aent
&& cur_proc_ptr
)
11810 as_warn (_("missing `.end'"));
11814 cur_proc_ptr
= &cur_proc
;
11815 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11817 cur_proc_ptr
->isym
= symbolP
;
11819 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11824 demand_empty_rest_of_line ();
11827 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11828 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11829 s_mips_frame is used so that we can set the PDR information correctly.
11830 We can't use the ecoff routines because they make reference to the ecoff
11831 symbol table (in the mdebug section). */
11834 s_mips_frame (ignore
)
11837 #ifdef MIPS_STABS_ELF
11841 if (cur_proc_ptr
== (procS
*) NULL
)
11843 as_warn (_(".frame outside of .ent"));
11844 demand_empty_rest_of_line ();
11848 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11850 SKIP_WHITESPACE ();
11851 if (*input_line_pointer
++ != ','
11852 || get_absolute_expression_and_terminator (&val
) != ',')
11854 as_warn (_("Bad .frame directive"));
11855 --input_line_pointer
;
11856 demand_empty_rest_of_line ();
11860 cur_proc_ptr
->frame_offset
= val
;
11861 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11863 demand_empty_rest_of_line ();
11866 #endif /* MIPS_STABS_ELF */
11869 /* The .fmask and .mask directives. If the mdebug section is present
11870 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11871 embedded targets, s_mips_mask is used so that we can set the PDR
11872 information correctly. We can't use the ecoff routines because they
11873 make reference to the ecoff symbol table (in the mdebug section). */
11876 s_mips_mask (reg_type
)
11879 #ifdef MIPS_STABS_ELF
11882 if (cur_proc_ptr
== (procS
*) NULL
)
11884 as_warn (_(".mask/.fmask outside of .ent"));
11885 demand_empty_rest_of_line ();
11889 if (get_absolute_expression_and_terminator (&mask
) != ',')
11891 as_warn (_("Bad .mask/.fmask directive"));
11892 --input_line_pointer
;
11893 demand_empty_rest_of_line ();
11897 off
= get_absolute_expression ();
11899 if (reg_type
== 'F')
11901 cur_proc_ptr
->fpreg_mask
= mask
;
11902 cur_proc_ptr
->fpreg_offset
= off
;
11906 cur_proc_ptr
->reg_mask
= mask
;
11907 cur_proc_ptr
->reg_offset
= off
;
11910 demand_empty_rest_of_line ();
11912 s_ignore (reg_type
);
11913 #endif /* MIPS_STABS_ELF */
11916 /* The .loc directive. */
11927 assert (now_seg
== text_section
);
11929 lineno
= get_number ();
11930 addroff
= frag_now_fix ();
11932 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11933 S_SET_TYPE (symbolP
, N_SLINE
);
11934 S_SET_OTHER (symbolP
, 0);
11935 S_SET_DESC (symbolP
, lineno
);
11936 symbolP
->sy_segment
= now_seg
;
11940 /* CPU name/ISA/number mapping table.
11942 Entries are grouped by type. The first matching CPU or ISA entry
11943 gets chosen by CPU or ISA, so it should be the 'canonical' name
11944 for that type. Entries after that within the type are sorted
11947 Case is ignored in comparison, so put the canonical entry in the
11948 appropriate case but everything else in lower case to ease eye pain. */
11949 static const struct mips_cpu_info mips_cpu_info_table
[] =
11952 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
11953 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
11956 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
11959 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
11962 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
11965 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
11966 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
11969 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
11970 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
11973 /* XXX for now, MIPS64 -> MIPS3 because of history */
11974 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
}, /* XXX! */
11977 { "MIPS64", 1, ISA_MIPS64
, CPU_MIPS64
},
11979 { "mips64isa", 1, ISA_MIPS64
, CPU_MIPS64
},
11980 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
11983 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
11984 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
11985 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
11986 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
11989 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
11990 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
11991 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
11992 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
11995 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
11996 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
11997 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
12000 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
12001 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
12002 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
12003 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
12006 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
12007 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
12010 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
12011 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
12014 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
12015 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
12016 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
12017 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
12020 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
12021 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
12024 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
12025 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
12026 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
12027 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
12030 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
12031 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
12032 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
12033 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
12036 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
12037 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
12038 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
12039 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
12042 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12043 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12044 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12045 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12048 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
12049 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
12050 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
12051 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
12054 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
12055 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
12056 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
12057 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
12060 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
12061 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
12062 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
12063 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
12064 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
12065 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
12066 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
12067 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
12068 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
12069 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
12070 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
12071 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
12073 /* MIPS32 4K CPU */
12074 { "MIPS32-4K", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12075 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12076 { "4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12077 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12078 { "mips32-4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12079 { "mips32-4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12080 { "mips32-4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12082 /* SiByte SB-1 CPU */
12083 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
12084 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
12085 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
12086 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
12089 { NULL
, 0, 0, 0, },
12092 static const struct mips_cpu_info
*
12093 mips_cpu_info_from_name (name
)
12098 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12099 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
12100 return (&mips_cpu_info_table
[i
]);
12105 static const struct mips_cpu_info
*
12106 mips_cpu_info_from_isa (isa
)
12111 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12112 if (mips_cpu_info_table
[i
].is_isa
12113 && isa
== mips_cpu_info_table
[i
].isa
)
12114 return (&mips_cpu_info_table
[i
]);
12119 static const struct mips_cpu_info
*
12120 mips_cpu_info_from_cpu (cpu
)
12125 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12126 if (!mips_cpu_info_table
[i
].is_isa
12127 && cpu
== mips_cpu_info_table
[i
].cpu
)
12128 return (&mips_cpu_info_table
[i
]);