1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && ((CPU) != CPU_GS464 \
426 || (CPU) != CPU_GS464E \
427 || (CPU) != CPU_GS264E))
429 /* Return true if ISA supports move to/from high part of a 64-bit
430 floating-point register. */
431 #define ISA_HAS_MXHC1(ISA) \
432 ((ISA) == ISA_MIPS32R2 \
433 || (ISA) == ISA_MIPS32R3 \
434 || (ISA) == ISA_MIPS32R5 \
435 || (ISA) == ISA_MIPS32R6 \
436 || (ISA) == ISA_MIPS64R2 \
437 || (ISA) == ISA_MIPS64R3 \
438 || (ISA) == ISA_MIPS64R5 \
439 || (ISA) == ISA_MIPS64R6)
441 /* Return true if ISA supports legacy NAN. */
442 #define ISA_HAS_LEGACY_NAN(ISA) \
443 ((ISA) == ISA_MIPS1 \
444 || (ISA) == ISA_MIPS2 \
445 || (ISA) == ISA_MIPS3 \
446 || (ISA) == ISA_MIPS4 \
447 || (ISA) == ISA_MIPS5 \
448 || (ISA) == ISA_MIPS32 \
449 || (ISA) == ISA_MIPS32R2 \
450 || (ISA) == ISA_MIPS32R3 \
451 || (ISA) == ISA_MIPS32R5 \
452 || (ISA) == ISA_MIPS64 \
453 || (ISA) == ISA_MIPS64R2 \
454 || (ISA) == ISA_MIPS64R3 \
455 || (ISA) == ISA_MIPS64R5)
458 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
463 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
467 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
469 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
471 /* True if relocations are stored in-place. */
472 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
474 /* The ABI-derived address size. */
475 #define HAVE_64BIT_ADDRESSES \
476 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
477 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
479 /* The size of symbolic constants (i.e., expressions of the form
480 "SYMBOL" or "SYMBOL + OFFSET"). */
481 #define HAVE_32BIT_SYMBOLS \
482 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
483 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
485 /* Addresses are loaded in different ways, depending on the address size
486 in use. The n32 ABI Documentation also mandates the use of additions
487 with overflow checking, but existing implementations don't follow it. */
488 #define ADDRESS_ADD_INSN \
489 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
491 #define ADDRESS_ADDI_INSN \
492 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
494 #define ADDRESS_LOAD_INSN \
495 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
497 #define ADDRESS_STORE_INSN \
498 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
500 /* Return true if the given CPU supports the MIPS16 ASE. */
501 #define CPU_HAS_MIPS16(cpu) \
502 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
503 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
505 /* Return true if the given CPU supports the microMIPS ASE. */
506 #define CPU_HAS_MICROMIPS(cpu) 0
508 /* True if CPU has a dror instruction. */
509 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
511 /* True if CPU has a ror instruction. */
512 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
514 /* True if CPU is in the Octeon family */
515 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
516 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
518 /* True if CPU has seq/sne and seqi/snei instructions. */
519 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
521 /* True, if CPU has support for ldc1 and sdc1. */
522 #define CPU_HAS_LDC1_SDC1(CPU) \
523 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
525 /* True if mflo and mfhi can be immediately followed by instructions
526 which write to the HI and LO registers.
528 According to MIPS specifications, MIPS ISAs I, II, and III need
529 (at least) two instructions between the reads of HI/LO and
530 instructions which write them, and later ISAs do not. Contradicting
531 the MIPS specifications, some MIPS IV processor user manuals (e.g.
532 the UM for the NEC Vr5000) document needing the instructions between
533 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
534 MIPS64 and later ISAs to have the interlocks, plus any specific
535 earlier-ISA CPUs for which CPU documentation declares that the
536 instructions are really interlocked. */
537 #define hilo_interlocks \
538 (mips_opts.isa == ISA_MIPS32 \
539 || mips_opts.isa == ISA_MIPS32R2 \
540 || mips_opts.isa == ISA_MIPS32R3 \
541 || mips_opts.isa == ISA_MIPS32R5 \
542 || mips_opts.isa == ISA_MIPS32R6 \
543 || mips_opts.isa == ISA_MIPS64 \
544 || mips_opts.isa == ISA_MIPS64R2 \
545 || mips_opts.isa == ISA_MIPS64R3 \
546 || mips_opts.isa == ISA_MIPS64R5 \
547 || mips_opts.isa == ISA_MIPS64R6 \
548 || mips_opts.arch == CPU_R4010 \
549 || mips_opts.arch == CPU_R5900 \
550 || mips_opts.arch == CPU_R10000 \
551 || mips_opts.arch == CPU_R12000 \
552 || mips_opts.arch == CPU_R14000 \
553 || mips_opts.arch == CPU_R16000 \
554 || mips_opts.arch == CPU_RM7000 \
555 || mips_opts.arch == CPU_VR5500 \
556 || mips_opts.micromips \
559 /* Whether the processor uses hardware interlocks to protect reads
560 from the GPRs after they are loaded from memory, and thus does not
561 require nops to be inserted. This applies to instructions marked
562 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
563 level I and microMIPS mode instructions are always interlocked. */
564 #define gpr_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.arch == CPU_R3900 \
567 || mips_opts.arch == CPU_R5900 \
568 || mips_opts.micromips \
571 /* Whether the processor uses hardware interlocks to avoid delays
572 required by coprocessor instructions, and thus does not require
573 nops to be inserted. This applies to instructions marked
574 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
575 instructions marked INSN_WRITE_COND_CODE and ones marked
576 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
577 levels I, II, and III and microMIPS mode instructions are always
579 /* Itbl support may require additional care here. */
580 #define cop_interlocks \
581 ((mips_opts.isa != ISA_MIPS1 \
582 && mips_opts.isa != ISA_MIPS2 \
583 && mips_opts.isa != ISA_MIPS3) \
584 || mips_opts.arch == CPU_R4300 \
585 || mips_opts.micromips \
588 /* Whether the processor uses hardware interlocks to protect reads
589 from coprocessor registers after they are loaded from memory, and
590 thus does not require nops to be inserted. This applies to
591 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
592 requires at MIPS ISA level I and microMIPS mode instructions are
593 always interlocked. */
594 #define cop_mem_interlocks \
595 (mips_opts.isa != ISA_MIPS1 \
596 || mips_opts.micromips \
599 /* Is this a mfhi or mflo instruction? */
600 #define MF_HILO_INSN(PINFO) \
601 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
603 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
604 has been selected. This implies, in particular, that addresses of text
605 labels have their LSB set. */
606 #define HAVE_CODE_COMPRESSION \
607 ((mips_opts.mips16 | mips_opts.micromips) != 0)
609 /* The minimum and maximum signed values that can be stored in a GPR. */
610 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
611 #define GPR_SMIN (-GPR_SMAX - 1)
613 /* MIPS PIC level. */
615 enum mips_pic_level mips_pic
;
617 /* 1 if we should generate 32 bit offsets from the $gp register in
618 SVR4_PIC mode. Currently has no meaning in other modes. */
619 static int mips_big_got
= 0;
621 /* 1 if trap instructions should used for overflow rather than break
623 static int mips_trap
= 0;
625 /* 1 if double width floating point constants should not be constructed
626 by assembling two single width halves into two single width floating
627 point registers which just happen to alias the double width destination
628 register. On some architectures this aliasing can be disabled by a bit
629 in the status register, and the setting of this bit cannot be determined
630 automatically at assemble time. */
631 static int mips_disable_float_construction
;
633 /* Non-zero if any .set noreorder directives were used. */
635 static int mips_any_noreorder
;
637 /* Non-zero if nops should be inserted when the register referenced in
638 an mfhi/mflo instruction is read in the next two instructions. */
639 static int mips_7000_hilo_fix
;
641 /* The size of objects in the small data section. */
642 static unsigned int g_switch_value
= 8;
643 /* Whether the -G option was used. */
644 static int g_switch_seen
= 0;
649 /* If we can determine in advance that GP optimization won't be
650 possible, we can skip the relaxation stuff that tries to produce
651 GP-relative references. This makes delay slot optimization work
654 This function can only provide a guess, but it seems to work for
655 gcc output. It needs to guess right for gcc, otherwise gcc
656 will put what it thinks is a GP-relative instruction in a branch
659 I don't know if a fix is needed for the SVR4_PIC mode. I've only
660 fixed it for the non-PIC mode. KR 95/04/07 */
661 static int nopic_need_relax (symbolS
*, int);
663 /* handle of the OPCODE hash table */
664 static struct hash_control
*op_hash
= NULL
;
666 /* The opcode hash table we use for the mips16. */
667 static struct hash_control
*mips16_op_hash
= NULL
;
669 /* The opcode hash table we use for the microMIPS ASE. */
670 static struct hash_control
*micromips_op_hash
= NULL
;
672 /* This array holds the chars that always start a comment. If the
673 pre-processor is disabled, these aren't very useful */
674 const char comment_chars
[] = "#";
676 /* This array holds the chars that only start a comment at the beginning of
677 a line. If the line seems to have the form '# 123 filename'
678 .line and .file directives will appear in the pre-processed output */
679 /* Note that input_file.c hand checks for '#' at the beginning of the
680 first line of the input file. This is because the compiler outputs
681 #NO_APP at the beginning of its output. */
682 /* Also note that C style comments are always supported. */
683 const char line_comment_chars
[] = "#";
685 /* This array holds machine specific line separator characters. */
686 const char line_separator_chars
[] = ";";
688 /* Chars that can be used to separate mant from exp in floating point nums */
689 const char EXP_CHARS
[] = "eE";
691 /* Chars that mean this number is a floating point constant */
694 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
696 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
697 changed in read.c . Ideally it shouldn't have to know about it at all,
698 but nothing is ideal around here.
701 /* Types of printf format used for instruction-related error messages.
702 "I" means int ("%d") and "S" means string ("%s"). */
703 enum mips_insn_error_format
{
709 /* Information about an error that was found while assembling the current
711 struct mips_insn_error
{
712 /* We sometimes need to match an instruction against more than one
713 opcode table entry. Errors found during this matching are reported
714 against a particular syntactic argument rather than against the
715 instruction as a whole. We grade these messages so that errors
716 against argument N have a greater priority than an error against
717 any argument < N, since the former implies that arguments up to N
718 were acceptable and that the opcode entry was therefore a closer match.
719 If several matches report an error against the same argument,
720 we only use that error if it is the same in all cases.
722 min_argnum is the minimum argument number for which an error message
723 should be accepted. It is 0 if MSG is against the instruction as
727 /* The printf()-style message, including its format and arguments. */
728 enum mips_insn_error_format format
;
736 /* The error that should be reported for the current instruction. */
737 static struct mips_insn_error insn_error
;
739 static int auto_align
= 1;
741 /* When outputting SVR4 PIC code, the assembler needs to know the
742 offset in the stack frame from which to restore the $gp register.
743 This is set by the .cprestore pseudo-op, and saved in this
745 static offsetT mips_cprestore_offset
= -1;
747 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
748 more optimizations, it can use a register value instead of a memory-saved
749 offset and even an other register than $gp as global pointer. */
750 static offsetT mips_cpreturn_offset
= -1;
751 static int mips_cpreturn_register
= -1;
752 static int mips_gp_register
= GP
;
753 static int mips_gprel_offset
= 0;
755 /* Whether mips_cprestore_offset has been set in the current function
756 (or whether it has already been warned about, if not). */
757 static int mips_cprestore_valid
= 0;
759 /* This is the register which holds the stack frame, as set by the
760 .frame pseudo-op. This is needed to implement .cprestore. */
761 static int mips_frame_reg
= SP
;
763 /* Whether mips_frame_reg has been set in the current function
764 (or whether it has already been warned about, if not). */
765 static int mips_frame_reg_valid
= 0;
767 /* To output NOP instructions correctly, we need to keep information
768 about the previous two instructions. */
770 /* Whether we are optimizing. The default value of 2 means to remove
771 unneeded NOPs and swap branch instructions when possible. A value
772 of 1 means to not swap branches. A value of 0 means to always
774 static int mips_optimize
= 2;
776 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
777 equivalent to seeing no -g option at all. */
778 static int mips_debug
= 0;
780 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
781 #define MAX_VR4130_NOPS 4
783 /* The maximum number of NOPs needed to fill delay slots. */
784 #define MAX_DELAY_NOPS 2
786 /* The maximum number of NOPs needed for any purpose. */
789 /* A list of previous instructions, with index 0 being the most recent.
790 We need to look back MAX_NOPS instructions when filling delay slots
791 or working around processor errata. We need to look back one
792 instruction further if we're thinking about using history[0] to
793 fill a branch delay slot. */
794 static struct mips_cl_insn history
[1 + MAX_NOPS
];
796 /* Arrays of operands for each instruction. */
797 #define MAX_OPERANDS 6
798 struct mips_operand_array
{
799 const struct mips_operand
*operand
[MAX_OPERANDS
];
801 static struct mips_operand_array
*mips_operands
;
802 static struct mips_operand_array
*mips16_operands
;
803 static struct mips_operand_array
*micromips_operands
;
805 /* Nop instructions used by emit_nop. */
806 static struct mips_cl_insn nop_insn
;
807 static struct mips_cl_insn mips16_nop_insn
;
808 static struct mips_cl_insn micromips_nop16_insn
;
809 static struct mips_cl_insn micromips_nop32_insn
;
811 /* The appropriate nop for the current mode. */
812 #define NOP_INSN (mips_opts.mips16 \
814 : (mips_opts.micromips \
815 ? (mips_opts.insn32 \
816 ? µmips_nop32_insn \
817 : µmips_nop16_insn) \
820 /* The size of NOP_INSN in bytes. */
821 #define NOP_INSN_SIZE ((mips_opts.mips16 \
822 || (mips_opts.micromips && !mips_opts.insn32)) \
825 /* If this is set, it points to a frag holding nop instructions which
826 were inserted before the start of a noreorder section. If those
827 nops turn out to be unnecessary, the size of the frag can be
829 static fragS
*prev_nop_frag
;
831 /* The number of nop instructions we created in prev_nop_frag. */
832 static int prev_nop_frag_holds
;
834 /* The number of nop instructions that we know we need in
836 static int prev_nop_frag_required
;
838 /* The number of instructions we've seen since prev_nop_frag. */
839 static int prev_nop_frag_since
;
841 /* Relocations against symbols are sometimes done in two parts, with a HI
842 relocation and a LO relocation. Each relocation has only 16 bits of
843 space to store an addend. This means that in order for the linker to
844 handle carries correctly, it must be able to locate both the HI and
845 the LO relocation. This means that the relocations must appear in
846 order in the relocation table.
848 In order to implement this, we keep track of each unmatched HI
849 relocation. We then sort them so that they immediately precede the
850 corresponding LO relocation. */
855 struct mips_hi_fixup
*next
;
858 /* The section this fixup is in. */
862 /* The list of unmatched HI relocs. */
864 static struct mips_hi_fixup
*mips_hi_fixup_list
;
866 /* The frag containing the last explicit relocation operator.
867 Null if explicit relocations have not been used. */
869 static fragS
*prev_reloc_op_frag
;
871 /* Map mips16 register numbers to normal MIPS register numbers. */
873 static const unsigned int mips16_to_32_reg_map
[] =
875 16, 17, 2, 3, 4, 5, 6, 7
878 /* Map microMIPS register numbers to normal MIPS register numbers. */
880 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
882 /* The microMIPS registers with type h. */
883 static const unsigned int micromips_to_32_reg_h_map1
[] =
885 5, 5, 6, 4, 4, 4, 4, 4
887 static const unsigned int micromips_to_32_reg_h_map2
[] =
889 6, 7, 7, 21, 22, 5, 6, 7
892 /* The microMIPS registers with type m. */
893 static const unsigned int micromips_to_32_reg_m_map
[] =
895 0, 17, 2, 3, 16, 18, 19, 20
898 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
900 /* Classifies the kind of instructions we're interested in when
901 implementing -mfix-vr4120. */
902 enum fix_vr4120_class
910 NUM_FIX_VR4120_CLASSES
913 /* ...likewise -mfix-loongson2f-jump. */
914 static bfd_boolean mips_fix_loongson2f_jump
;
916 /* ...likewise -mfix-loongson2f-nop. */
917 static bfd_boolean mips_fix_loongson2f_nop
;
919 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
920 static bfd_boolean mips_fix_loongson2f
;
922 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
923 there must be at least one other instruction between an instruction
924 of type X and an instruction of type Y. */
925 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
927 /* True if -mfix-vr4120 is in force. */
928 static int mips_fix_vr4120
;
930 /* ...likewise -mfix-vr4130. */
931 static int mips_fix_vr4130
;
933 /* ...likewise -mfix-24k. */
934 static int mips_fix_24k
;
936 /* ...likewise -mfix-rm7000 */
937 static int mips_fix_rm7000
;
939 /* ...likewise -mfix-cn63xxp1 */
940 static bfd_boolean mips_fix_cn63xxp1
;
942 /* We don't relax branches by default, since this causes us to expand
943 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
944 fail to compute the offset before expanding the macro to the most
945 efficient expansion. */
947 static int mips_relax_branch
;
949 /* TRUE if checks are suppressed for invalid branches between ISA modes.
950 Needed for broken assembly produced by some GCC versions and some
951 sloppy code out there, where branches to data labels are present. */
952 static bfd_boolean mips_ignore_branch_isa
;
954 /* The expansion of many macros depends on the type of symbol that
955 they refer to. For example, when generating position-dependent code,
956 a macro that refers to a symbol may have two different expansions,
957 one which uses GP-relative addresses and one which uses absolute
958 addresses. When generating SVR4-style PIC, a macro may have
959 different expansions for local and global symbols.
961 We handle these situations by generating both sequences and putting
962 them in variant frags. In position-dependent code, the first sequence
963 will be the GP-relative one and the second sequence will be the
964 absolute one. In SVR4 PIC, the first sequence will be for global
965 symbols and the second will be for local symbols.
967 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
968 SECOND are the lengths of the two sequences in bytes. These fields
969 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
970 the subtype has the following flags:
973 Set if generating PIC code.
976 Set if it has been decided that we should use the second
977 sequence instead of the first.
980 Set in the first variant frag if the macro's second implementation
981 is longer than its first. This refers to the macro as a whole,
982 not an individual relaxation.
985 Set in the first variant frag if the macro appeared in a .set nomacro
986 block and if one alternative requires a warning but the other does not.
989 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
992 RELAX_DELAY_SLOT_16BIT
993 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
996 RELAX_DELAY_SLOT_SIZE_FIRST
997 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
998 the macro is of the wrong size for the branch delay slot.
1000 RELAX_DELAY_SLOT_SIZE_SECOND
1001 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1002 the macro is of the wrong size for the branch delay slot.
1004 The frag's "opcode" points to the first fixup for relaxable code.
1006 Relaxable macros are generated using a sequence such as:
1008 relax_start (SYMBOL);
1009 ... generate first expansion ...
1011 ... generate second expansion ...
1014 The code and fixups for the unwanted alternative are discarded
1015 by md_convert_frag. */
1016 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1017 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1019 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1020 #define RELAX_SECOND(X) ((X) & 0xff)
1021 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1022 #define RELAX_USE_SECOND 0x20000
1023 #define RELAX_SECOND_LONGER 0x40000
1024 #define RELAX_NOMACRO 0x80000
1025 #define RELAX_DELAY_SLOT 0x100000
1026 #define RELAX_DELAY_SLOT_16BIT 0x200000
1027 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1028 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1030 /* Branch without likely bit. If label is out of range, we turn:
1032 beq reg1, reg2, label
1042 with the following opcode replacements:
1049 bltzal <-> bgezal (with jal label instead of j label)
1051 Even though keeping the delay slot instruction in the delay slot of
1052 the branch would be more efficient, it would be very tricky to do
1053 correctly, because we'd have to introduce a variable frag *after*
1054 the delay slot instruction, and expand that instead. Let's do it
1055 the easy way for now, even if the branch-not-taken case now costs
1056 one additional instruction. Out-of-range branches are not supposed
1057 to be common, anyway.
1059 Branch likely. If label is out of range, we turn:
1061 beql reg1, reg2, label
1062 delay slot (annulled if branch not taken)
1071 delay slot (executed only if branch taken)
1074 It would be possible to generate a shorter sequence by losing the
1075 likely bit, generating something like:
1080 delay slot (executed only if branch taken)
1092 bltzall -> bgezal (with jal label instead of j label)
1093 bgezall -> bltzal (ditto)
1096 but it's not clear that it would actually improve performance. */
1097 #define RELAX_BRANCH_ENCODE(at, pic, \
1098 uncond, likely, link, toofar) \
1099 ((relax_substateT) \
1102 | ((pic) ? 0x20 : 0) \
1103 | ((toofar) ? 0x40 : 0) \
1104 | ((link) ? 0x80 : 0) \
1105 | ((likely) ? 0x100 : 0) \
1106 | ((uncond) ? 0x200 : 0)))
1107 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1108 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1109 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1110 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1111 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1112 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1113 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1115 /* For mips16 code, we use an entirely different form of relaxation.
1116 mips16 supports two versions of most instructions which take
1117 immediate values: a small one which takes some small value, and a
1118 larger one which takes a 16 bit value. Since branches also follow
1119 this pattern, relaxing these values is required.
1121 We can assemble both mips16 and normal MIPS code in a single
1122 object. Therefore, we need to support this type of relaxation at
1123 the same time that we support the relaxation described above. We
1124 use the high bit of the subtype field to distinguish these cases.
1126 The information we store for this type of relaxation is the
1127 argument code found in the opcode file for this relocation, whether
1128 the user explicitly requested a small or extended form, and whether
1129 the relocation is in a jump or jal delay slot. That tells us the
1130 size of the value, and how it should be stored. We also store
1131 whether the fragment is considered to be extended or not. We also
1132 store whether this is known to be a branch to a different section,
1133 whether we have tried to relax this frag yet, and whether we have
1134 ever extended a PC relative fragment because of a shift count. */
1135 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1140 | ((e2) ? 0x100 : 0) \
1141 | ((pic) ? 0x200 : 0) \
1142 | ((sym32) ? 0x400 : 0) \
1143 | ((nomacro) ? 0x800 : 0) \
1144 | ((small) ? 0x1000 : 0) \
1145 | ((ext) ? 0x2000 : 0) \
1146 | ((dslot) ? 0x4000 : 0) \
1147 | ((jal_dslot) ? 0x8000 : 0))
1149 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1150 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1151 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1152 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1153 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1154 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1155 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1156 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1157 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1158 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1160 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1161 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1162 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1163 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1164 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1165 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1166 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1167 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1168 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1170 /* For microMIPS code, we use relaxation similar to one we use for
1171 MIPS16 code. Some instructions that take immediate values support
1172 two encodings: a small one which takes some small value, and a
1173 larger one which takes a 16 bit value. As some branches also follow
1174 this pattern, relaxing these values is required.
1176 We can assemble both microMIPS and normal MIPS code in a single
1177 object. Therefore, we need to support this type of relaxation at
1178 the same time that we support the relaxation described above. We
1179 use one of the high bits of the subtype field to distinguish these
1182 The information we store for this type of relaxation is the argument
1183 code found in the opcode file for this relocation, the register
1184 selected as the assembler temporary, whether in the 32-bit
1185 instruction mode, whether the branch is unconditional, whether it is
1186 compact, whether there is no delay-slot instruction available to fill
1187 in, whether it stores the link address implicitly in $ra, whether
1188 relaxation of out-of-range 32-bit branches to a sequence of
1189 instructions is enabled, and whether the displacement of a branch is
1190 too large to fit as an immediate argument of a 16-bit and a 32-bit
1191 branch, respectively. */
1192 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1193 uncond, compact, link, nods, \
1194 relax32, toofar16, toofar32) \
1197 | (((at) & 0x1f) << 8) \
1198 | ((insn32) ? 0x2000 : 0) \
1199 | ((pic) ? 0x4000 : 0) \
1200 | ((uncond) ? 0x8000 : 0) \
1201 | ((compact) ? 0x10000 : 0) \
1202 | ((link) ? 0x20000 : 0) \
1203 | ((nods) ? 0x40000 : 0) \
1204 | ((relax32) ? 0x80000 : 0) \
1205 | ((toofar16) ? 0x100000 : 0) \
1206 | ((toofar32) ? 0x200000 : 0))
1207 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1208 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1209 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1210 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1211 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1212 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1213 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1214 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1215 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1216 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1218 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1219 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1220 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1221 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1222 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1223 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1225 /* Sign-extend 16-bit value X. */
1226 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1228 /* Is the given value a sign-extended 32-bit value? */
1229 #define IS_SEXT_32BIT_NUM(x) \
1230 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1231 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1233 /* Is the given value a sign-extended 16-bit value? */
1234 #define IS_SEXT_16BIT_NUM(x) \
1235 (((x) &~ (offsetT) 0x7fff) == 0 \
1236 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1238 /* Is the given value a sign-extended 12-bit value? */
1239 #define IS_SEXT_12BIT_NUM(x) \
1240 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1242 /* Is the given value a sign-extended 9-bit value? */
1243 #define IS_SEXT_9BIT_NUM(x) \
1244 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1246 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1247 #define IS_ZEXT_32BIT_NUM(x) \
1248 (((x) &~ (offsetT) 0xffffffff) == 0 \
1249 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1251 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1253 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1254 (((STRUCT) >> (SHIFT)) & (MASK))
1256 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1257 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1259 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1260 : EXTRACT_BITS ((INSN).insn_opcode, \
1261 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1262 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1263 EXTRACT_BITS ((INSN).insn_opcode, \
1264 MIPS16OP_MASK_##FIELD, \
1265 MIPS16OP_SH_##FIELD)
1267 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1268 #define MIPS16_EXTEND (0xf000U << 16)
1270 /* Whether or not we are emitting a branch-likely macro. */
1271 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1273 /* Global variables used when generating relaxable macros. See the
1274 comment above RELAX_ENCODE for more details about how relaxation
1277 /* 0 if we're not emitting a relaxable macro.
1278 1 if we're emitting the first of the two relaxation alternatives.
1279 2 if we're emitting the second alternative. */
1282 /* The first relaxable fixup in the current frag. (In other words,
1283 the first fixup that refers to relaxable code.) */
1286 /* sizes[0] says how many bytes of the first alternative are stored in
1287 the current frag. Likewise sizes[1] for the second alternative. */
1288 unsigned int sizes
[2];
1290 /* The symbol on which the choice of sequence depends. */
1294 /* Global variables used to decide whether a macro needs a warning. */
1296 /* True if the macro is in a branch delay slot. */
1297 bfd_boolean delay_slot_p
;
1299 /* Set to the length in bytes required if the macro is in a delay slot
1300 that requires a specific length of instruction, otherwise zero. */
1301 unsigned int delay_slot_length
;
1303 /* For relaxable macros, sizes[0] is the length of the first alternative
1304 in bytes and sizes[1] is the length of the second alternative.
1305 For non-relaxable macros, both elements give the length of the
1307 unsigned int sizes
[2];
1309 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1310 instruction of the first alternative in bytes and first_insn_sizes[1]
1311 is the length of the first instruction of the second alternative.
1312 For non-relaxable macros, both elements give the length of the first
1313 instruction in bytes.
1315 Set to zero if we haven't yet seen the first instruction. */
1316 unsigned int first_insn_sizes
[2];
1318 /* For relaxable macros, insns[0] is the number of instructions for the
1319 first alternative and insns[1] is the number of instructions for the
1322 For non-relaxable macros, both elements give the number of
1323 instructions for the macro. */
1324 unsigned int insns
[2];
1326 /* The first variant frag for this macro. */
1328 } mips_macro_warning
;
1330 /* Prototypes for static functions. */
1332 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1334 static void append_insn
1335 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1336 bfd_boolean expansionp
);
1337 static void mips_no_prev_insn (void);
1338 static void macro_build (expressionS
*, const char *, const char *, ...);
1339 static void mips16_macro_build
1340 (expressionS
*, const char *, const char *, va_list *);
1341 static void load_register (int, expressionS
*, int);
1342 static void macro_start (void);
1343 static void macro_end (void);
1344 static void macro (struct mips_cl_insn
*ip
, char *str
);
1345 static void mips16_macro (struct mips_cl_insn
* ip
);
1346 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1347 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1348 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1349 static void mips16_immed
1350 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1351 unsigned int, unsigned long *);
1352 static size_t my_getSmallExpression
1353 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1354 static void my_getExpression (expressionS
*, char *);
1355 static void s_align (int);
1356 static void s_change_sec (int);
1357 static void s_change_section (int);
1358 static void s_cons (int);
1359 static void s_float_cons (int);
1360 static void s_mips_globl (int);
1361 static void s_option (int);
1362 static void s_mipsset (int);
1363 static void s_abicalls (int);
1364 static void s_cpload (int);
1365 static void s_cpsetup (int);
1366 static void s_cplocal (int);
1367 static void s_cprestore (int);
1368 static void s_cpreturn (int);
1369 static void s_dtprelword (int);
1370 static void s_dtpreldword (int);
1371 static void s_tprelword (int);
1372 static void s_tpreldword (int);
1373 static void s_gpvalue (int);
1374 static void s_gpword (int);
1375 static void s_gpdword (int);
1376 static void s_ehword (int);
1377 static void s_cpadd (int);
1378 static void s_insn (int);
1379 static void s_nan (int);
1380 static void s_module (int);
1381 static void s_mips_ent (int);
1382 static void s_mips_end (int);
1383 static void s_mips_frame (int);
1384 static void s_mips_mask (int reg_type
);
1385 static void s_mips_stab (int);
1386 static void s_mips_weakext (int);
1387 static void s_mips_file (int);
1388 static void s_mips_loc (int);
1389 static bfd_boolean
pic_need_relax (symbolS
*);
1390 static int relaxed_branch_length (fragS
*, asection
*, int);
1391 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1392 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1393 static void file_mips_check_options (void);
1395 /* Table and functions used to map between CPU/ISA names, and
1396 ISA levels, and CPU numbers. */
1398 struct mips_cpu_info
1400 const char *name
; /* CPU or ISA name. */
1401 int flags
; /* MIPS_CPU_* flags. */
1402 int ase
; /* Set of ASEs implemented by the CPU. */
1403 int isa
; /* ISA level. */
1404 int cpu
; /* CPU number (default CPU if ISA). */
1407 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1409 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1410 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1411 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1413 /* Command-line options. */
1414 const char *md_shortopts
= "O::g::G:";
1418 OPTION_MARCH
= OPTION_MD_BASE
,
1450 OPTION_NO_SMARTMIPS
,
1460 OPTION_NO_MICROMIPS
,
1475 OPTION_M7000_HILO_FIX
,
1476 OPTION_MNO_7000_HILO_FIX
,
1480 OPTION_NO_FIX_RM7000
,
1481 OPTION_FIX_LOONGSON2F_JUMP
,
1482 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1483 OPTION_FIX_LOONGSON2F_NOP
,
1484 OPTION_NO_FIX_LOONGSON2F_NOP
,
1486 OPTION_NO_FIX_VR4120
,
1488 OPTION_NO_FIX_VR4130
,
1489 OPTION_FIX_CN63XXP1
,
1490 OPTION_NO_FIX_CN63XXP1
,
1497 OPTION_CONSTRUCT_FLOATS
,
1498 OPTION_NO_CONSTRUCT_FLOATS
,
1502 OPTION_RELAX_BRANCH
,
1503 OPTION_NO_RELAX_BRANCH
,
1504 OPTION_IGNORE_BRANCH_ISA
,
1505 OPTION_NO_IGNORE_BRANCH_ISA
,
1514 OPTION_SINGLE_FLOAT
,
1515 OPTION_DOUBLE_FLOAT
,
1528 OPTION_MVXWORKS_PIC
,
1531 OPTION_NO_ODD_SPREG
,
1534 OPTION_LOONGSON_MMI
,
1535 OPTION_NO_LOONGSON_MMI
,
1536 OPTION_LOONGSON_CAM
,
1537 OPTION_NO_LOONGSON_CAM
,
1538 OPTION_LOONGSON_EXT
,
1539 OPTION_NO_LOONGSON_EXT
,
1540 OPTION_LOONGSON_EXT2
,
1541 OPTION_NO_LOONGSON_EXT2
,
1545 struct option md_longopts
[] =
1547 /* Options which specify architecture. */
1548 {"march", required_argument
, NULL
, OPTION_MARCH
},
1549 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1550 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1551 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1552 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1553 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1554 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1555 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1556 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1557 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1558 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1559 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1560 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1561 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1562 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1563 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1564 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1565 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1567 /* Options which specify Application Specific Extensions (ASEs). */
1568 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1569 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1570 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1571 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1572 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1573 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1574 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1575 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1576 {"mmt", no_argument
, NULL
, OPTION_MT
},
1577 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1578 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1579 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1580 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1581 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1582 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1583 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1584 {"meva", no_argument
, NULL
, OPTION_EVA
},
1585 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1586 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1587 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1588 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1589 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1590 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1591 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1592 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1593 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1594 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1595 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1596 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1597 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1598 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1599 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1600 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1601 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1602 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1603 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1604 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1605 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1606 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1607 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1608 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1609 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1611 /* Old-style architecture options. Don't add more of these. */
1612 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1613 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1614 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1615 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1616 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1617 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1618 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1619 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1621 /* Options which enable bug fixes. */
1622 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1623 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1624 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1625 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1626 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1627 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1628 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1629 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1630 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1631 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1632 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1633 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1634 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1635 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1636 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1637 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1638 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1640 /* Miscellaneous options. */
1641 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1642 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1643 {"break", no_argument
, NULL
, OPTION_BREAK
},
1644 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1645 {"EB", no_argument
, NULL
, OPTION_EB
},
1646 {"EL", no_argument
, NULL
, OPTION_EL
},
1647 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1648 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1649 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1650 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1651 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1652 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1653 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1654 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1655 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1656 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1657 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1658 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1659 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1660 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1661 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1662 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1663 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1664 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1665 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1666 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1667 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1668 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1669 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1671 /* Strictly speaking this next option is ELF specific,
1672 but we allow it for other ports as well in order to
1673 make testing easier. */
1674 {"32", no_argument
, NULL
, OPTION_32
},
1676 /* ELF-specific options. */
1677 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1678 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1679 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1680 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1681 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1682 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1683 {"n32", no_argument
, NULL
, OPTION_N32
},
1684 {"64", no_argument
, NULL
, OPTION_64
},
1685 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1686 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1687 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1688 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1689 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1690 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1692 {NULL
, no_argument
, NULL
, 0}
1694 size_t md_longopts_size
= sizeof (md_longopts
);
1696 /* Information about either an Application Specific Extension or an
1697 optional architecture feature that, for simplicity, we treat in the
1698 same way as an ASE. */
1701 /* The name of the ASE, used in both the command-line and .set options. */
1704 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1705 and 64-bit architectures, the flags here refer to the subset that
1706 is available on both. */
1709 /* The ASE_* flag used for instructions that are available on 64-bit
1710 architectures but that are not included in FLAGS. */
1711 unsigned int flags64
;
1713 /* The command-line options that turn the ASE on and off. */
1717 /* The minimum required architecture revisions for MIPS32, MIPS64,
1718 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1721 int micromips32_rev
;
1722 int micromips64_rev
;
1724 /* The architecture where the ASE was removed or -1 if the extension has not
1729 /* A table of all supported ASEs. */
1730 static const struct mips_ase mips_ases
[] = {
1731 { "dsp", ASE_DSP
, ASE_DSP64
,
1732 OPTION_DSP
, OPTION_NO_DSP
,
1736 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1737 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1741 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1742 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1746 { "eva", ASE_EVA
, 0,
1747 OPTION_EVA
, OPTION_NO_EVA
,
1751 { "mcu", ASE_MCU
, 0,
1752 OPTION_MCU
, OPTION_NO_MCU
,
1756 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1757 { "mdmx", ASE_MDMX
, 0,
1758 OPTION_MDMX
, OPTION_NO_MDMX
,
1762 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1763 { "mips3d", ASE_MIPS3D
, 0,
1764 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1769 OPTION_MT
, OPTION_NO_MT
,
1773 { "smartmips", ASE_SMARTMIPS
, 0,
1774 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1778 { "virt", ASE_VIRT
, ASE_VIRT64
,
1779 OPTION_VIRT
, OPTION_NO_VIRT
,
1783 { "msa", ASE_MSA
, ASE_MSA64
,
1784 OPTION_MSA
, OPTION_NO_MSA
,
1788 { "xpa", ASE_XPA
, 0,
1789 OPTION_XPA
, OPTION_NO_XPA
,
1793 { "mips16e2", ASE_MIPS16E2
, 0,
1794 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1798 { "crc", ASE_CRC
, ASE_CRC64
,
1799 OPTION_CRC
, OPTION_NO_CRC
,
1803 { "ginv", ASE_GINV
, 0,
1804 OPTION_GINV
, OPTION_NO_GINV
,
1808 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1809 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1813 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1814 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1818 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1819 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1823 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1824 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1829 /* The set of ASEs that require -mfp64. */
1830 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1832 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1833 static const unsigned int mips_ase_groups
[] = {
1834 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1835 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1840 The following pseudo-ops from the Kane and Heinrich MIPS book
1841 should be defined here, but are currently unsupported: .alias,
1842 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1844 The following pseudo-ops from the Kane and Heinrich MIPS book are
1845 specific to the type of debugging information being generated, and
1846 should be defined by the object format: .aent, .begin, .bend,
1847 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1850 The following pseudo-ops from the Kane and Heinrich MIPS book are
1851 not MIPS CPU specific, but are also not specific to the object file
1852 format. This file is probably the best place to define them, but
1853 they are not currently supported: .asm0, .endr, .lab, .struct. */
1855 static const pseudo_typeS mips_pseudo_table
[] =
1857 /* MIPS specific pseudo-ops. */
1858 {"option", s_option
, 0},
1859 {"set", s_mipsset
, 0},
1860 {"rdata", s_change_sec
, 'r'},
1861 {"sdata", s_change_sec
, 's'},
1862 {"livereg", s_ignore
, 0},
1863 {"abicalls", s_abicalls
, 0},
1864 {"cpload", s_cpload
, 0},
1865 {"cpsetup", s_cpsetup
, 0},
1866 {"cplocal", s_cplocal
, 0},
1867 {"cprestore", s_cprestore
, 0},
1868 {"cpreturn", s_cpreturn
, 0},
1869 {"dtprelword", s_dtprelword
, 0},
1870 {"dtpreldword", s_dtpreldword
, 0},
1871 {"tprelword", s_tprelword
, 0},
1872 {"tpreldword", s_tpreldword
, 0},
1873 {"gpvalue", s_gpvalue
, 0},
1874 {"gpword", s_gpword
, 0},
1875 {"gpdword", s_gpdword
, 0},
1876 {"ehword", s_ehword
, 0},
1877 {"cpadd", s_cpadd
, 0},
1878 {"insn", s_insn
, 0},
1880 {"module", s_module
, 0},
1882 /* Relatively generic pseudo-ops that happen to be used on MIPS
1884 {"asciiz", stringer
, 8 + 1},
1885 {"bss", s_change_sec
, 'b'},
1887 {"half", s_cons
, 1},
1888 {"dword", s_cons
, 3},
1889 {"weakext", s_mips_weakext
, 0},
1890 {"origin", s_org
, 0},
1891 {"repeat", s_rept
, 0},
1893 /* For MIPS this is non-standard, but we define it for consistency. */
1894 {"sbss", s_change_sec
, 'B'},
1896 /* These pseudo-ops are defined in read.c, but must be overridden
1897 here for one reason or another. */
1898 {"align", s_align
, 0},
1899 {"byte", s_cons
, 0},
1900 {"data", s_change_sec
, 'd'},
1901 {"double", s_float_cons
, 'd'},
1902 {"float", s_float_cons
, 'f'},
1903 {"globl", s_mips_globl
, 0},
1904 {"global", s_mips_globl
, 0},
1905 {"hword", s_cons
, 1},
1907 {"long", s_cons
, 2},
1908 {"octa", s_cons
, 4},
1909 {"quad", s_cons
, 3},
1910 {"section", s_change_section
, 0},
1911 {"short", s_cons
, 1},
1912 {"single", s_float_cons
, 'f'},
1913 {"stabd", s_mips_stab
, 'd'},
1914 {"stabn", s_mips_stab
, 'n'},
1915 {"stabs", s_mips_stab
, 's'},
1916 {"text", s_change_sec
, 't'},
1917 {"word", s_cons
, 2},
1919 { "extern", ecoff_directive_extern
, 0},
1924 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1926 /* These pseudo-ops should be defined by the object file format.
1927 However, a.out doesn't support them, so we have versions here. */
1928 {"aent", s_mips_ent
, 1},
1929 {"bgnb", s_ignore
, 0},
1930 {"end", s_mips_end
, 0},
1931 {"endb", s_ignore
, 0},
1932 {"ent", s_mips_ent
, 0},
1933 {"file", s_mips_file
, 0},
1934 {"fmask", s_mips_mask
, 'F'},
1935 {"frame", s_mips_frame
, 0},
1936 {"loc", s_mips_loc
, 0},
1937 {"mask", s_mips_mask
, 'R'},
1938 {"verstamp", s_ignore
, 0},
1942 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1943 purpose of the `.dc.a' internal pseudo-op. */
1946 mips_address_bytes (void)
1948 file_mips_check_options ();
1949 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1952 extern void pop_insert (const pseudo_typeS
*);
1955 mips_pop_insert (void)
1957 pop_insert (mips_pseudo_table
);
1958 if (! ECOFF_DEBUGGING
)
1959 pop_insert (mips_nonecoff_pseudo_table
);
1962 /* Symbols labelling the current insn. */
1964 struct insn_label_list
1966 struct insn_label_list
*next
;
1970 static struct insn_label_list
*free_insn_labels
;
1971 #define label_list tc_segment_info_data.labels
1973 static void mips_clear_insn_labels (void);
1974 static void mips_mark_labels (void);
1975 static void mips_compressed_mark_labels (void);
1978 mips_clear_insn_labels (void)
1980 struct insn_label_list
**pl
;
1981 segment_info_type
*si
;
1985 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1988 si
= seg_info (now_seg
);
1989 *pl
= si
->label_list
;
1990 si
->label_list
= NULL
;
1994 /* Mark instruction labels in MIPS16/microMIPS mode. */
1997 mips_mark_labels (void)
1999 if (HAVE_CODE_COMPRESSION
)
2000 mips_compressed_mark_labels ();
2003 static char *expr_end
;
2005 /* An expression in a macro instruction. This is set by mips_ip and
2006 mips16_ip and when populated is always an O_constant. */
2008 static expressionS imm_expr
;
2010 /* The relocatable field in an instruction and the relocs associated
2011 with it. These variables are used for instructions like LUI and
2012 JAL as well as true offsets. They are also used for address
2013 operands in macros. */
2015 static expressionS offset_expr
;
2016 static bfd_reloc_code_real_type offset_reloc
[3]
2017 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2019 /* This is set to the resulting size of the instruction to be produced
2020 by mips16_ip if an explicit extension is used or by mips_ip if an
2021 explicit size is supplied. */
2023 static unsigned int forced_insn_length
;
2025 /* True if we are assembling an instruction. All dot symbols defined during
2026 this time should be treated as code labels. */
2028 static bfd_boolean mips_assembling_insn
;
2030 /* The pdr segment for per procedure frame/regmask info. Not used for
2033 static segT pdr_seg
;
2035 /* The default target format to use. */
2037 #if defined (TE_FreeBSD)
2038 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2039 #elif defined (TE_TMIPS)
2040 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2042 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2046 mips_target_format (void)
2048 switch (OUTPUT_FLAVOR
)
2050 case bfd_target_elf_flavour
:
2052 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2053 return (target_big_endian
2054 ? "elf32-bigmips-vxworks"
2055 : "elf32-littlemips-vxworks");
2057 return (target_big_endian
2058 ? (HAVE_64BIT_OBJECTS
2059 ? ELF_TARGET ("elf64-", "big")
2061 ? ELF_TARGET ("elf32-n", "big")
2062 : ELF_TARGET ("elf32-", "big")))
2063 : (HAVE_64BIT_OBJECTS
2064 ? ELF_TARGET ("elf64-", "little")
2066 ? ELF_TARGET ("elf32-n", "little")
2067 : ELF_TARGET ("elf32-", "little"))));
2074 /* Return the ISA revision that is currently in use, or 0 if we are
2075 generating code for MIPS V or below. */
2080 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2083 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2086 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2089 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2092 /* microMIPS implies revision 2 or above. */
2093 if (mips_opts
.micromips
)
2096 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2102 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2105 mips_ase_mask (unsigned int flags
)
2109 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2110 if (flags
& mips_ase_groups
[i
])
2111 flags
|= mips_ase_groups
[i
];
2115 /* Check whether the current ISA supports ASE. Issue a warning if
2119 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2123 static unsigned int warned_isa
;
2124 static unsigned int warned_fp32
;
2126 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2127 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2129 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2130 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2131 && (warned_isa
& ase
->flags
) != ase
->flags
)
2133 warned_isa
|= ase
->flags
;
2134 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2135 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2137 as_warn (_("the %d-bit %s architecture does not support the"
2138 " `%s' extension"), size
, base
, ase
->name
);
2140 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2141 ase
->name
, base
, size
, min_rev
);
2143 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2144 && (warned_isa
& ase
->flags
) != ase
->flags
)
2146 warned_isa
|= ase
->flags
;
2147 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2148 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2149 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2150 ase
->name
, base
, size
, ase
->rem_rev
);
2153 if ((ase
->flags
& FP64_ASES
)
2154 && mips_opts
.fp
!= 64
2155 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2157 warned_fp32
|= ase
->flags
;
2158 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2162 /* Check all enabled ASEs to see whether they are supported by the
2163 chosen architecture. */
2166 mips_check_isa_supports_ases (void)
2168 unsigned int i
, mask
;
2170 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2172 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2173 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2174 mips_check_isa_supports_ase (&mips_ases
[i
]);
2178 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2179 that were affected. */
2182 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2183 bfd_boolean enabled_p
)
2187 mask
= mips_ase_mask (ase
->flags
);
2190 /* Clear combination ASE flags, which need to be recalculated based on
2191 updated regular ASE settings. */
2192 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
);
2195 opts
->ase
|= ase
->flags
;
2197 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2198 instructions which are only valid when both ASEs are enabled.
2199 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2200 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2202 opts
->ase
|= ASE_XPA_VIRT
;
2203 mask
|= ASE_XPA_VIRT
;
2205 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2207 opts
->ase
|= ASE_MIPS16E2_MT
;
2208 mask
|= ASE_MIPS16E2_MT
;
2214 /* Return the ASE called NAME, or null if none. */
2216 static const struct mips_ase
*
2217 mips_lookup_ase (const char *name
)
2221 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2222 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2223 return &mips_ases
[i
];
2227 /* Return the length of a microMIPS instruction in bytes. If bits of
2228 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2229 otherwise it is a 32-bit instruction. */
2231 static inline unsigned int
2232 micromips_insn_length (const struct mips_opcode
*mo
)
2234 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2237 /* Return the length of MIPS16 instruction OPCODE. */
2239 static inline unsigned int
2240 mips16_opcode_length (unsigned long opcode
)
2242 return (opcode
>> 16) == 0 ? 2 : 4;
2245 /* Return the length of instruction INSN. */
2247 static inline unsigned int
2248 insn_length (const struct mips_cl_insn
*insn
)
2250 if (mips_opts
.micromips
)
2251 return micromips_insn_length (insn
->insn_mo
);
2252 else if (mips_opts
.mips16
)
2253 return mips16_opcode_length (insn
->insn_opcode
);
2258 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2261 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2266 insn
->insn_opcode
= mo
->match
;
2269 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2270 insn
->fixp
[i
] = NULL
;
2271 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2272 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2273 insn
->mips16_absolute_jump_p
= 0;
2274 insn
->complete_p
= 0;
2275 insn
->cleared_p
= 0;
2278 /* Get a list of all the operands in INSN. */
2280 static const struct mips_operand_array
*
2281 insn_operands (const struct mips_cl_insn
*insn
)
2283 if (insn
->insn_mo
>= &mips_opcodes
[0]
2284 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2285 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2287 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2288 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2289 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2291 if (insn
->insn_mo
>= µmips_opcodes
[0]
2292 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2293 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2298 /* Get a description of operand OPNO of INSN. */
2300 static const struct mips_operand
*
2301 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2303 const struct mips_operand_array
*operands
;
2305 operands
= insn_operands (insn
);
2306 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2308 return operands
->operand
[opno
];
2311 /* Install UVAL as the value of OPERAND in INSN. */
2314 insn_insert_operand (struct mips_cl_insn
*insn
,
2315 const struct mips_operand
*operand
, unsigned int uval
)
2317 if (mips_opts
.mips16
2318 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2319 && mips_opcode_32bit_p (insn
->insn_mo
))
2320 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2322 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2325 /* Extract the value of OPERAND from INSN. */
2327 static inline unsigned
2328 insn_extract_operand (const struct mips_cl_insn
*insn
,
2329 const struct mips_operand
*operand
)
2331 return mips_extract_operand (operand
, insn
->insn_opcode
);
2334 /* Record the current MIPS16/microMIPS mode in now_seg. */
2337 mips_record_compressed_mode (void)
2339 segment_info_type
*si
;
2341 si
= seg_info (now_seg
);
2342 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2343 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2344 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2345 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2348 /* Read a standard MIPS instruction from BUF. */
2350 static unsigned long
2351 read_insn (char *buf
)
2353 if (target_big_endian
)
2354 return bfd_getb32 ((bfd_byte
*) buf
);
2356 return bfd_getl32 ((bfd_byte
*) buf
);
2359 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2363 write_insn (char *buf
, unsigned int insn
)
2365 md_number_to_chars (buf
, insn
, 4);
2369 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2370 has length LENGTH. */
2372 static unsigned long
2373 read_compressed_insn (char *buf
, unsigned int length
)
2379 for (i
= 0; i
< length
; i
+= 2)
2382 if (target_big_endian
)
2383 insn
|= bfd_getb16 ((char *) buf
);
2385 insn
|= bfd_getl16 ((char *) buf
);
2391 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2392 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2395 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2399 for (i
= 0; i
< length
; i
+= 2)
2400 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2401 return buf
+ length
;
2404 /* Install INSN at the location specified by its "frag" and "where" fields. */
2407 install_insn (const struct mips_cl_insn
*insn
)
2409 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2410 if (HAVE_CODE_COMPRESSION
)
2411 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2413 write_insn (f
, insn
->insn_opcode
);
2414 mips_record_compressed_mode ();
2417 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2418 and install the opcode in the new location. */
2421 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2426 insn
->where
= where
;
2427 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2428 if (insn
->fixp
[i
] != NULL
)
2430 insn
->fixp
[i
]->fx_frag
= frag
;
2431 insn
->fixp
[i
]->fx_where
= where
;
2433 install_insn (insn
);
2436 /* Add INSN to the end of the output. */
2439 add_fixed_insn (struct mips_cl_insn
*insn
)
2441 char *f
= frag_more (insn_length (insn
));
2442 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2445 /* Start a variant frag and move INSN to the start of the variant part,
2446 marking it as fixed. The other arguments are as for frag_var. */
2449 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2450 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2452 frag_grow (max_chars
);
2453 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2455 frag_var (rs_machine_dependent
, max_chars
, var
,
2456 subtype
, symbol
, offset
, NULL
);
2459 /* Insert N copies of INSN into the history buffer, starting at
2460 position FIRST. Neither FIRST nor N need to be clipped. */
2463 insert_into_history (unsigned int first
, unsigned int n
,
2464 const struct mips_cl_insn
*insn
)
2466 if (mips_relax
.sequence
!= 2)
2470 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2472 history
[i
] = history
[i
- n
];
2478 /* Clear the error in insn_error. */
2481 clear_insn_error (void)
2483 memset (&insn_error
, 0, sizeof (insn_error
));
2486 /* Possibly record error message MSG for the current instruction.
2487 If the error is about a particular argument, ARGNUM is the 1-based
2488 number of that argument, otherwise it is 0. FORMAT is the format
2489 of MSG. Return true if MSG was used, false if the current message
2493 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2498 /* Give priority to errors against specific arguments, and to
2499 the first whole-instruction message. */
2505 /* Keep insn_error if it is against a later argument. */
2506 if (argnum
< insn_error
.min_argnum
)
2509 /* If both errors are against the same argument but are different,
2510 give up on reporting a specific error for this argument.
2511 See the comment about mips_insn_error for details. */
2512 if (argnum
== insn_error
.min_argnum
2514 && strcmp (insn_error
.msg
, msg
) != 0)
2517 insn_error
.min_argnum
+= 1;
2521 insn_error
.min_argnum
= argnum
;
2522 insn_error
.format
= format
;
2523 insn_error
.msg
= msg
;
2527 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2528 as for set_insn_error_format. */
2531 set_insn_error (int argnum
, const char *msg
)
2533 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2536 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2537 as for set_insn_error_format. */
2540 set_insn_error_i (int argnum
, const char *msg
, int i
)
2542 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2546 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2547 are as for set_insn_error_format. */
2550 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2552 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2554 insn_error
.u
.ss
[0] = s1
;
2555 insn_error
.u
.ss
[1] = s2
;
2559 /* Report the error in insn_error, which is against assembly code STR. */
2562 report_insn_error (const char *str
)
2564 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2566 switch (insn_error
.format
)
2573 as_bad (msg
, insn_error
.u
.i
, str
);
2577 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2581 free ((char *) msg
);
2584 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2585 the idea is to make it obvious at a glance that each errata is
2589 init_vr4120_conflicts (void)
2591 #define CONFLICT(FIRST, SECOND) \
2592 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2594 /* Errata 21 - [D]DIV[U] after [D]MACC */
2595 CONFLICT (MACC
, DIV
);
2596 CONFLICT (DMACC
, DIV
);
2598 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2599 CONFLICT (DMULT
, DMULT
);
2600 CONFLICT (DMULT
, DMACC
);
2601 CONFLICT (DMACC
, DMULT
);
2602 CONFLICT (DMACC
, DMACC
);
2604 /* Errata 24 - MT{LO,HI} after [D]MACC */
2605 CONFLICT (MACC
, MTHILO
);
2606 CONFLICT (DMACC
, MTHILO
);
2608 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2609 instruction is executed immediately after a MACC or DMACC
2610 instruction, the result of [either instruction] is incorrect." */
2611 CONFLICT (MACC
, MULT
);
2612 CONFLICT (MACC
, DMULT
);
2613 CONFLICT (DMACC
, MULT
);
2614 CONFLICT (DMACC
, DMULT
);
2616 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2617 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2618 DDIV or DDIVU instruction, the result of the MACC or
2619 DMACC instruction is incorrect.". */
2620 CONFLICT (DMULT
, MACC
);
2621 CONFLICT (DMULT
, DMACC
);
2622 CONFLICT (DIV
, MACC
);
2623 CONFLICT (DIV
, DMACC
);
2633 #define RNUM_MASK 0x00000ff
2634 #define RTYPE_MASK 0x0ffff00
2635 #define RTYPE_NUM 0x0000100
2636 #define RTYPE_FPU 0x0000200
2637 #define RTYPE_FCC 0x0000400
2638 #define RTYPE_VEC 0x0000800
2639 #define RTYPE_GP 0x0001000
2640 #define RTYPE_CP0 0x0002000
2641 #define RTYPE_PC 0x0004000
2642 #define RTYPE_ACC 0x0008000
2643 #define RTYPE_CCC 0x0010000
2644 #define RTYPE_VI 0x0020000
2645 #define RTYPE_VF 0x0040000
2646 #define RTYPE_R5900_I 0x0080000
2647 #define RTYPE_R5900_Q 0x0100000
2648 #define RTYPE_R5900_R 0x0200000
2649 #define RTYPE_R5900_ACC 0x0400000
2650 #define RTYPE_MSA 0x0800000
2651 #define RWARN 0x8000000
2653 #define GENERIC_REGISTER_NUMBERS \
2654 {"$0", RTYPE_NUM | 0}, \
2655 {"$1", RTYPE_NUM | 1}, \
2656 {"$2", RTYPE_NUM | 2}, \
2657 {"$3", RTYPE_NUM | 3}, \
2658 {"$4", RTYPE_NUM | 4}, \
2659 {"$5", RTYPE_NUM | 5}, \
2660 {"$6", RTYPE_NUM | 6}, \
2661 {"$7", RTYPE_NUM | 7}, \
2662 {"$8", RTYPE_NUM | 8}, \
2663 {"$9", RTYPE_NUM | 9}, \
2664 {"$10", RTYPE_NUM | 10}, \
2665 {"$11", RTYPE_NUM | 11}, \
2666 {"$12", RTYPE_NUM | 12}, \
2667 {"$13", RTYPE_NUM | 13}, \
2668 {"$14", RTYPE_NUM | 14}, \
2669 {"$15", RTYPE_NUM | 15}, \
2670 {"$16", RTYPE_NUM | 16}, \
2671 {"$17", RTYPE_NUM | 17}, \
2672 {"$18", RTYPE_NUM | 18}, \
2673 {"$19", RTYPE_NUM | 19}, \
2674 {"$20", RTYPE_NUM | 20}, \
2675 {"$21", RTYPE_NUM | 21}, \
2676 {"$22", RTYPE_NUM | 22}, \
2677 {"$23", RTYPE_NUM | 23}, \
2678 {"$24", RTYPE_NUM | 24}, \
2679 {"$25", RTYPE_NUM | 25}, \
2680 {"$26", RTYPE_NUM | 26}, \
2681 {"$27", RTYPE_NUM | 27}, \
2682 {"$28", RTYPE_NUM | 28}, \
2683 {"$29", RTYPE_NUM | 29}, \
2684 {"$30", RTYPE_NUM | 30}, \
2685 {"$31", RTYPE_NUM | 31}
2687 #define FPU_REGISTER_NAMES \
2688 {"$f0", RTYPE_FPU | 0}, \
2689 {"$f1", RTYPE_FPU | 1}, \
2690 {"$f2", RTYPE_FPU | 2}, \
2691 {"$f3", RTYPE_FPU | 3}, \
2692 {"$f4", RTYPE_FPU | 4}, \
2693 {"$f5", RTYPE_FPU | 5}, \
2694 {"$f6", RTYPE_FPU | 6}, \
2695 {"$f7", RTYPE_FPU | 7}, \
2696 {"$f8", RTYPE_FPU | 8}, \
2697 {"$f9", RTYPE_FPU | 9}, \
2698 {"$f10", RTYPE_FPU | 10}, \
2699 {"$f11", RTYPE_FPU | 11}, \
2700 {"$f12", RTYPE_FPU | 12}, \
2701 {"$f13", RTYPE_FPU | 13}, \
2702 {"$f14", RTYPE_FPU | 14}, \
2703 {"$f15", RTYPE_FPU | 15}, \
2704 {"$f16", RTYPE_FPU | 16}, \
2705 {"$f17", RTYPE_FPU | 17}, \
2706 {"$f18", RTYPE_FPU | 18}, \
2707 {"$f19", RTYPE_FPU | 19}, \
2708 {"$f20", RTYPE_FPU | 20}, \
2709 {"$f21", RTYPE_FPU | 21}, \
2710 {"$f22", RTYPE_FPU | 22}, \
2711 {"$f23", RTYPE_FPU | 23}, \
2712 {"$f24", RTYPE_FPU | 24}, \
2713 {"$f25", RTYPE_FPU | 25}, \
2714 {"$f26", RTYPE_FPU | 26}, \
2715 {"$f27", RTYPE_FPU | 27}, \
2716 {"$f28", RTYPE_FPU | 28}, \
2717 {"$f29", RTYPE_FPU | 29}, \
2718 {"$f30", RTYPE_FPU | 30}, \
2719 {"$f31", RTYPE_FPU | 31}
2721 #define FPU_CONDITION_CODE_NAMES \
2722 {"$fcc0", RTYPE_FCC | 0}, \
2723 {"$fcc1", RTYPE_FCC | 1}, \
2724 {"$fcc2", RTYPE_FCC | 2}, \
2725 {"$fcc3", RTYPE_FCC | 3}, \
2726 {"$fcc4", RTYPE_FCC | 4}, \
2727 {"$fcc5", RTYPE_FCC | 5}, \
2728 {"$fcc6", RTYPE_FCC | 6}, \
2729 {"$fcc7", RTYPE_FCC | 7}
2731 #define COPROC_CONDITION_CODE_NAMES \
2732 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2733 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2734 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2735 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2736 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2737 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2738 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2739 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2741 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2742 {"$a4", RTYPE_GP | 8}, \
2743 {"$a5", RTYPE_GP | 9}, \
2744 {"$a6", RTYPE_GP | 10}, \
2745 {"$a7", RTYPE_GP | 11}, \
2746 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2747 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2748 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2749 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2750 {"$t0", RTYPE_GP | 12}, \
2751 {"$t1", RTYPE_GP | 13}, \
2752 {"$t2", RTYPE_GP | 14}, \
2753 {"$t3", RTYPE_GP | 15}
2755 #define O32_SYMBOLIC_REGISTER_NAMES \
2756 {"$t0", RTYPE_GP | 8}, \
2757 {"$t1", RTYPE_GP | 9}, \
2758 {"$t2", RTYPE_GP | 10}, \
2759 {"$t3", RTYPE_GP | 11}, \
2760 {"$t4", RTYPE_GP | 12}, \
2761 {"$t5", RTYPE_GP | 13}, \
2762 {"$t6", RTYPE_GP | 14}, \
2763 {"$t7", RTYPE_GP | 15}, \
2764 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2765 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2766 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2767 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2769 /* Remaining symbolic register names */
2770 #define SYMBOLIC_REGISTER_NAMES \
2771 {"$zero", RTYPE_GP | 0}, \
2772 {"$at", RTYPE_GP | 1}, \
2773 {"$AT", RTYPE_GP | 1}, \
2774 {"$v0", RTYPE_GP | 2}, \
2775 {"$v1", RTYPE_GP | 3}, \
2776 {"$a0", RTYPE_GP | 4}, \
2777 {"$a1", RTYPE_GP | 5}, \
2778 {"$a2", RTYPE_GP | 6}, \
2779 {"$a3", RTYPE_GP | 7}, \
2780 {"$s0", RTYPE_GP | 16}, \
2781 {"$s1", RTYPE_GP | 17}, \
2782 {"$s2", RTYPE_GP | 18}, \
2783 {"$s3", RTYPE_GP | 19}, \
2784 {"$s4", RTYPE_GP | 20}, \
2785 {"$s5", RTYPE_GP | 21}, \
2786 {"$s6", RTYPE_GP | 22}, \
2787 {"$s7", RTYPE_GP | 23}, \
2788 {"$t8", RTYPE_GP | 24}, \
2789 {"$t9", RTYPE_GP | 25}, \
2790 {"$k0", RTYPE_GP | 26}, \
2791 {"$kt0", RTYPE_GP | 26}, \
2792 {"$k1", RTYPE_GP | 27}, \
2793 {"$kt1", RTYPE_GP | 27}, \
2794 {"$gp", RTYPE_GP | 28}, \
2795 {"$sp", RTYPE_GP | 29}, \
2796 {"$s8", RTYPE_GP | 30}, \
2797 {"$fp", RTYPE_GP | 30}, \
2798 {"$ra", RTYPE_GP | 31}
2800 #define MIPS16_SPECIAL_REGISTER_NAMES \
2801 {"$pc", RTYPE_PC | 0}
2803 #define MDMX_VECTOR_REGISTER_NAMES \
2804 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2805 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2806 {"$v2", RTYPE_VEC | 2}, \
2807 {"$v3", RTYPE_VEC | 3}, \
2808 {"$v4", RTYPE_VEC | 4}, \
2809 {"$v5", RTYPE_VEC | 5}, \
2810 {"$v6", RTYPE_VEC | 6}, \
2811 {"$v7", RTYPE_VEC | 7}, \
2812 {"$v8", RTYPE_VEC | 8}, \
2813 {"$v9", RTYPE_VEC | 9}, \
2814 {"$v10", RTYPE_VEC | 10}, \
2815 {"$v11", RTYPE_VEC | 11}, \
2816 {"$v12", RTYPE_VEC | 12}, \
2817 {"$v13", RTYPE_VEC | 13}, \
2818 {"$v14", RTYPE_VEC | 14}, \
2819 {"$v15", RTYPE_VEC | 15}, \
2820 {"$v16", RTYPE_VEC | 16}, \
2821 {"$v17", RTYPE_VEC | 17}, \
2822 {"$v18", RTYPE_VEC | 18}, \
2823 {"$v19", RTYPE_VEC | 19}, \
2824 {"$v20", RTYPE_VEC | 20}, \
2825 {"$v21", RTYPE_VEC | 21}, \
2826 {"$v22", RTYPE_VEC | 22}, \
2827 {"$v23", RTYPE_VEC | 23}, \
2828 {"$v24", RTYPE_VEC | 24}, \
2829 {"$v25", RTYPE_VEC | 25}, \
2830 {"$v26", RTYPE_VEC | 26}, \
2831 {"$v27", RTYPE_VEC | 27}, \
2832 {"$v28", RTYPE_VEC | 28}, \
2833 {"$v29", RTYPE_VEC | 29}, \
2834 {"$v30", RTYPE_VEC | 30}, \
2835 {"$v31", RTYPE_VEC | 31}
2837 #define R5900_I_NAMES \
2838 {"$I", RTYPE_R5900_I | 0}
2840 #define R5900_Q_NAMES \
2841 {"$Q", RTYPE_R5900_Q | 0}
2843 #define R5900_R_NAMES \
2844 {"$R", RTYPE_R5900_R | 0}
2846 #define R5900_ACC_NAMES \
2847 {"$ACC", RTYPE_R5900_ACC | 0 }
2849 #define MIPS_DSP_ACCUMULATOR_NAMES \
2850 {"$ac0", RTYPE_ACC | 0}, \
2851 {"$ac1", RTYPE_ACC | 1}, \
2852 {"$ac2", RTYPE_ACC | 2}, \
2853 {"$ac3", RTYPE_ACC | 3}
2855 static const struct regname reg_names
[] = {
2856 GENERIC_REGISTER_NUMBERS
,
2858 FPU_CONDITION_CODE_NAMES
,
2859 COPROC_CONDITION_CODE_NAMES
,
2861 /* The $txx registers depends on the abi,
2862 these will be added later into the symbol table from
2863 one of the tables below once mips_abi is set after
2864 parsing of arguments from the command line. */
2865 SYMBOLIC_REGISTER_NAMES
,
2867 MIPS16_SPECIAL_REGISTER_NAMES
,
2868 MDMX_VECTOR_REGISTER_NAMES
,
2873 MIPS_DSP_ACCUMULATOR_NAMES
,
2877 static const struct regname reg_names_o32
[] = {
2878 O32_SYMBOLIC_REGISTER_NAMES
,
2882 static const struct regname reg_names_n32n64
[] = {
2883 N32N64_SYMBOLIC_REGISTER_NAMES
,
2887 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2888 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2889 of these register symbols, return the associated vector register,
2890 otherwise return SYMVAL itself. */
2893 mips_prefer_vec_regno (unsigned int symval
)
2895 if ((symval
& -2) == (RTYPE_GP
| 2))
2896 return RTYPE_VEC
| (symval
& 1);
2900 /* Return true if string [S, E) is a valid register name, storing its
2901 symbol value in *SYMVAL_PTR if so. */
2904 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2909 /* Terminate name. */
2913 /* Look up the name. */
2914 symbol
= symbol_find (s
);
2917 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2920 *symval_ptr
= S_GET_VALUE (symbol
);
2924 /* Return true if the string at *SPTR is a valid register name. Allow it
2925 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2928 When returning true, move *SPTR past the register, store the
2929 register's symbol value in *SYMVAL_PTR and the channel mask in
2930 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2931 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2932 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2935 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2936 unsigned int *channels_ptr
)
2940 unsigned int channels
, symval
, bit
;
2942 /* Find end of name. */
2944 if (is_name_beginner (*e
))
2946 while (is_part_of_name (*e
))
2950 if (!mips_parse_register_1 (s
, e
, &symval
))
2955 /* Eat characters from the end of the string that are valid
2956 channel suffixes. The preceding register must be $ACC or
2957 end with a digit, so there is no ambiguity. */
2960 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2961 if (m
> s
&& m
[-1] == *q
)
2968 || !mips_parse_register_1 (s
, m
, &symval
)
2969 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2974 *symval_ptr
= symval
;
2976 *channels_ptr
= channels
;
2980 /* Check if SPTR points at a valid register specifier according to TYPES.
2981 If so, then return 1, advance S to consume the specifier and store
2982 the register's number in REGNOP, otherwise return 0. */
2985 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2989 if (mips_parse_register (s
, ®no
, NULL
))
2991 if (types
& RTYPE_VEC
)
2992 regno
= mips_prefer_vec_regno (regno
);
3001 as_warn (_("unrecognized register name `%s'"), *s
);
3006 return regno
<= RNUM_MASK
;
3009 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3010 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3013 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3018 for (i
= 0; i
< 4; i
++)
3019 if (*s
== "xyzw"[i
])
3021 *channels
|= 1 << (3 - i
);
3027 /* Token types for parsed operand lists. */
3028 enum mips_operand_token_type
{
3029 /* A plain register, e.g. $f2. */
3032 /* A 4-bit XYZW channel mask. */
3035 /* A constant vector index, e.g. [1]. */
3038 /* A register vector index, e.g. [$2]. */
3041 /* A continuous range of registers, e.g. $s0-$s4. */
3044 /* A (possibly relocated) expression. */
3047 /* A floating-point value. */
3050 /* A single character. This can be '(', ')' or ',', but '(' only appears
3054 /* A doubled character, either "--" or "++". */
3057 /* The end of the operand list. */
3061 /* A parsed operand token. */
3062 struct mips_operand_token
3064 /* The type of token. */
3065 enum mips_operand_token_type type
;
3068 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3071 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3072 unsigned int channels
;
3074 /* The integer value of an OT_INTEGER_INDEX. */
3077 /* The two register symbol values involved in an OT_REG_RANGE. */
3079 unsigned int regno1
;
3080 unsigned int regno2
;
3083 /* The value of an OT_INTEGER. The value is represented as an
3084 expression and the relocation operators that were applied to
3085 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3086 relocation operators were used. */
3089 bfd_reloc_code_real_type relocs
[3];
3092 /* The binary data for an OT_FLOAT constant, and the number of bytes
3095 unsigned char data
[8];
3099 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3104 /* An obstack used to construct lists of mips_operand_tokens. */
3105 static struct obstack mips_operand_tokens
;
3107 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3110 mips_add_token (struct mips_operand_token
*token
,
3111 enum mips_operand_token_type type
)
3114 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3117 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3118 and OT_REG tokens for them if so, and return a pointer to the first
3119 unconsumed character. Return null otherwise. */
3122 mips_parse_base_start (char *s
)
3124 struct mips_operand_token token
;
3125 unsigned int regno
, channels
;
3126 bfd_boolean decrement_p
;
3132 SKIP_SPACE_TABS (s
);
3134 /* Only match "--" as part of a base expression. In other contexts "--X"
3135 is a double negative. */
3136 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3140 SKIP_SPACE_TABS (s
);
3143 /* Allow a channel specifier because that leads to better error messages
3144 than treating something like "$vf0x++" as an expression. */
3145 if (!mips_parse_register (&s
, ®no
, &channels
))
3149 mips_add_token (&token
, OT_CHAR
);
3154 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3157 token
.u
.regno
= regno
;
3158 mips_add_token (&token
, OT_REG
);
3162 token
.u
.channels
= channels
;
3163 mips_add_token (&token
, OT_CHANNELS
);
3166 /* For consistency, only match "++" as part of base expressions too. */
3167 SKIP_SPACE_TABS (s
);
3168 if (s
[0] == '+' && s
[1] == '+')
3172 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3178 /* Parse one or more tokens from S. Return a pointer to the first
3179 unconsumed character on success. Return null if an error was found
3180 and store the error text in insn_error. FLOAT_FORMAT is as for
3181 mips_parse_arguments. */
3184 mips_parse_argument_token (char *s
, char float_format
)
3186 char *end
, *save_in
;
3188 unsigned int regno1
, regno2
, channels
;
3189 struct mips_operand_token token
;
3191 /* First look for "($reg", since we want to treat that as an
3192 OT_CHAR and OT_REG rather than an expression. */
3193 end
= mips_parse_base_start (s
);
3197 /* Handle other characters that end up as OT_CHARs. */
3198 if (*s
== ')' || *s
== ',')
3201 mips_add_token (&token
, OT_CHAR
);
3206 /* Handle tokens that start with a register. */
3207 if (mips_parse_register (&s
, ®no1
, &channels
))
3211 /* A register and a VU0 channel suffix. */
3212 token
.u
.regno
= regno1
;
3213 mips_add_token (&token
, OT_REG
);
3215 token
.u
.channels
= channels
;
3216 mips_add_token (&token
, OT_CHANNELS
);
3220 SKIP_SPACE_TABS (s
);
3223 /* A register range. */
3225 SKIP_SPACE_TABS (s
);
3226 if (!mips_parse_register (&s
, ®no2
, NULL
))
3228 set_insn_error (0, _("invalid register range"));
3232 token
.u
.reg_range
.regno1
= regno1
;
3233 token
.u
.reg_range
.regno2
= regno2
;
3234 mips_add_token (&token
, OT_REG_RANGE
);
3238 /* Add the register itself. */
3239 token
.u
.regno
= regno1
;
3240 mips_add_token (&token
, OT_REG
);
3242 /* Check for a vector index. */
3246 SKIP_SPACE_TABS (s
);
3247 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3248 mips_add_token (&token
, OT_REG_INDEX
);
3251 expressionS element
;
3253 my_getExpression (&element
, s
);
3254 if (element
.X_op
!= O_constant
)
3256 set_insn_error (0, _("vector element must be constant"));
3260 token
.u
.index
= element
.X_add_number
;
3261 mips_add_token (&token
, OT_INTEGER_INDEX
);
3263 SKIP_SPACE_TABS (s
);
3266 set_insn_error (0, _("missing `]'"));
3276 /* First try to treat expressions as floats. */
3277 save_in
= input_line_pointer
;
3278 input_line_pointer
= s
;
3279 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3280 &token
.u
.flt
.length
);
3281 end
= input_line_pointer
;
3282 input_line_pointer
= save_in
;
3285 set_insn_error (0, err
);
3290 mips_add_token (&token
, OT_FLOAT
);
3295 /* Treat everything else as an integer expression. */
3296 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3297 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3298 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3299 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3301 mips_add_token (&token
, OT_INTEGER
);
3305 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3306 if expressions should be treated as 32-bit floating-point constants,
3307 'd' if they should be treated as 64-bit floating-point constants,
3308 or 0 if they should be treated as integer expressions (the usual case).
3310 Return a list of tokens on success, otherwise return 0. The caller
3311 must obstack_free the list after use. */
3313 static struct mips_operand_token
*
3314 mips_parse_arguments (char *s
, char float_format
)
3316 struct mips_operand_token token
;
3318 SKIP_SPACE_TABS (s
);
3321 s
= mips_parse_argument_token (s
, float_format
);
3324 obstack_free (&mips_operand_tokens
,
3325 obstack_finish (&mips_operand_tokens
));
3328 SKIP_SPACE_TABS (s
);
3330 mips_add_token (&token
, OT_END
);
3331 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3334 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3335 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3338 is_opcode_valid (const struct mips_opcode
*mo
)
3340 int isa
= mips_opts
.isa
;
3341 int ase
= mips_opts
.ase
;
3345 if (ISA_HAS_64BIT_REGS (isa
))
3346 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3347 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3348 ase
|= mips_ases
[i
].flags64
;
3350 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3353 /* Check whether the instruction or macro requires single-precision or
3354 double-precision floating-point support. Note that this information is
3355 stored differently in the opcode table for insns and macros. */
3356 if (mo
->pinfo
== INSN_MACRO
)
3358 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3359 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3363 fp_s
= mo
->pinfo
& FP_S
;
3364 fp_d
= mo
->pinfo
& FP_D
;
3367 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3370 if (fp_s
&& mips_opts
.soft_float
)
3376 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3377 selected ISA and architecture. */
3380 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3382 int isa
= mips_opts
.isa
;
3383 int ase
= mips_opts
.ase
;
3386 if (ISA_HAS_64BIT_REGS (isa
))
3387 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3388 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3389 ase
|= mips_ases
[i
].flags64
;
3391 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3394 /* Return TRUE if the size of the microMIPS opcode MO matches one
3395 explicitly requested. Always TRUE in the standard MIPS mode.
3396 Use is_size_valid_16 for MIPS16 opcodes. */
3399 is_size_valid (const struct mips_opcode
*mo
)
3401 if (!mips_opts
.micromips
)
3404 if (mips_opts
.insn32
)
3406 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3408 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3411 if (!forced_insn_length
)
3413 if (mo
->pinfo
== INSN_MACRO
)
3415 return forced_insn_length
== micromips_insn_length (mo
);
3418 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3419 explicitly requested. */
3422 is_size_valid_16 (const struct mips_opcode
*mo
)
3424 if (!forced_insn_length
)
3426 if (mo
->pinfo
== INSN_MACRO
)
3428 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3430 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3435 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3436 of the preceding instruction. Always TRUE in the standard MIPS mode.
3438 We don't accept macros in 16-bit delay slots to avoid a case where
3439 a macro expansion fails because it relies on a preceding 32-bit real
3440 instruction to have matched and does not handle the operands correctly.
3441 The only macros that may expand to 16-bit instructions are JAL that
3442 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3443 and BGT (that likewise cannot be placed in a delay slot) that decay to
3444 a NOP. In all these cases the macros precede any corresponding real
3445 instruction definitions in the opcode table, so they will match in the
3446 second pass where the size of the delay slot is ignored and therefore
3447 produce correct code. */
3450 is_delay_slot_valid (const struct mips_opcode
*mo
)
3452 if (!mips_opts
.micromips
)
3455 if (mo
->pinfo
== INSN_MACRO
)
3456 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3457 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3458 && micromips_insn_length (mo
) != 4)
3460 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3461 && micromips_insn_length (mo
) != 2)
3467 /* For consistency checking, verify that all bits of OPCODE are specified
3468 either by the match/mask part of the instruction definition, or by the
3469 operand list. Also build up a list of operands in OPERANDS.
3471 INSN_BITS says which bits of the instruction are significant.
3472 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3473 provides the mips_operand description of each operand. DECODE_OPERAND
3474 is null for MIPS16 instructions. */
3477 validate_mips_insn (const struct mips_opcode
*opcode
,
3478 unsigned long insn_bits
,
3479 const struct mips_operand
*(*decode_operand
) (const char *),
3480 struct mips_operand_array
*operands
)
3483 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3484 const struct mips_operand
*operand
;
3486 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3487 if ((mask
& opcode
->match
) != opcode
->match
)
3489 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3490 opcode
->name
, opcode
->args
);
3495 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3496 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3497 for (s
= opcode
->args
; *s
; ++s
)
3510 if (!decode_operand
)
3511 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3513 operand
= decode_operand (s
);
3514 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3516 as_bad (_("internal: unknown operand type: %s %s"),
3517 opcode
->name
, opcode
->args
);
3520 gas_assert (opno
< MAX_OPERANDS
);
3521 operands
->operand
[opno
] = operand
;
3522 if (!decode_operand
&& operand
3523 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3524 && mips_opcode_32bit_p (opcode
))
3525 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3526 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3528 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3529 if (operand
->type
== OP_MDMX_IMM_REG
)
3530 /* Bit 5 is the format selector (OB vs QH). The opcode table
3531 has separate entries for each format. */
3532 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3533 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3534 used_bits
&= ~(mask
& 0x700);
3535 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3536 operand field that cannot be fully described with LSB/SIZE. */
3537 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3538 used_bits
&= ~0x6000;
3540 /* Skip prefix characters. */
3541 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3546 doubled
= used_bits
& mask
& insn_bits
;
3549 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3550 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3554 undefined
= ~used_bits
& insn_bits
;
3555 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3557 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3558 undefined
, opcode
->name
, opcode
->args
);
3561 used_bits
&= ~insn_bits
;
3564 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3565 used_bits
, opcode
->name
, opcode
->args
);
3571 /* The MIPS16 version of validate_mips_insn. */
3574 validate_mips16_insn (const struct mips_opcode
*opcode
,
3575 struct mips_operand_array
*operands
)
3577 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3579 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3582 /* The microMIPS version of validate_mips_insn. */
3585 validate_micromips_insn (const struct mips_opcode
*opc
,
3586 struct mips_operand_array
*operands
)
3588 unsigned long insn_bits
;
3589 unsigned long major
;
3590 unsigned int length
;
3592 if (opc
->pinfo
== INSN_MACRO
)
3593 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3596 length
= micromips_insn_length (opc
);
3597 if (length
!= 2 && length
!= 4)
3599 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3600 "%s %s"), length
, opc
->name
, opc
->args
);
3603 major
= opc
->match
>> (10 + 8 * (length
- 2));
3604 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3605 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3607 as_bad (_("internal error: bad microMIPS opcode "
3608 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3612 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3613 insn_bits
= 1 << 4 * length
;
3614 insn_bits
<<= 4 * length
;
3616 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3620 /* This function is called once, at assembler startup time. It should set up
3621 all the tables, etc. that the MD part of the assembler will need. */
3626 const char *retval
= NULL
;
3630 if (mips_pic
!= NO_PIC
)
3632 if (g_switch_seen
&& g_switch_value
!= 0)
3633 as_bad (_("-G may not be used in position-independent code"));
3636 else if (mips_abicalls
)
3638 if (g_switch_seen
&& g_switch_value
!= 0)
3639 as_bad (_("-G may not be used with abicalls"));
3643 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3644 as_warn (_("could not set architecture and machine"));
3646 op_hash
= hash_new ();
3648 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3649 for (i
= 0; i
< NUMOPCODES
;)
3651 const char *name
= mips_opcodes
[i
].name
;
3653 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3656 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3657 mips_opcodes
[i
].name
, retval
);
3658 /* Probably a memory allocation problem? Give up now. */
3659 as_fatal (_("broken assembler, no assembly attempted"));
3663 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3664 decode_mips_operand
, &mips_operands
[i
]))
3666 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3668 create_insn (&nop_insn
, mips_opcodes
+ i
);
3669 if (mips_fix_loongson2f_nop
)
3670 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3671 nop_insn
.fixed_p
= 1;
3675 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3678 mips16_op_hash
= hash_new ();
3679 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3680 bfd_mips16_num_opcodes
);
3683 while (i
< bfd_mips16_num_opcodes
)
3685 const char *name
= mips16_opcodes
[i
].name
;
3687 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3689 as_fatal (_("internal: can't hash `%s': %s"),
3690 mips16_opcodes
[i
].name
, retval
);
3693 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3695 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3697 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3698 mips16_nop_insn
.fixed_p
= 1;
3702 while (i
< bfd_mips16_num_opcodes
3703 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3706 micromips_op_hash
= hash_new ();
3707 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3708 bfd_micromips_num_opcodes
);
3711 while (i
< bfd_micromips_num_opcodes
)
3713 const char *name
= micromips_opcodes
[i
].name
;
3715 retval
= hash_insert (micromips_op_hash
, name
,
3716 (void *) µmips_opcodes
[i
]);
3718 as_fatal (_("internal: can't hash `%s': %s"),
3719 micromips_opcodes
[i
].name
, retval
);
3722 struct mips_cl_insn
*micromips_nop_insn
;
3724 if (!validate_micromips_insn (µmips_opcodes
[i
],
3725 µmips_operands
[i
]))
3728 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3730 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3731 micromips_nop_insn
= µmips_nop16_insn
;
3732 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3733 micromips_nop_insn
= µmips_nop32_insn
;
3737 if (micromips_nop_insn
->insn_mo
== NULL
3738 && strcmp (name
, "nop") == 0)
3740 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3741 micromips_nop_insn
->fixed_p
= 1;
3745 while (++i
< bfd_micromips_num_opcodes
3746 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3750 as_fatal (_("broken assembler, no assembly attempted"));
3752 /* We add all the general register names to the symbol table. This
3753 helps us detect invalid uses of them. */
3754 for (i
= 0; reg_names
[i
].name
; i
++)
3755 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3756 reg_names
[i
].num
, /* & RNUM_MASK, */
3757 &zero_address_frag
));
3759 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3760 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3761 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3762 &zero_address_frag
));
3764 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3765 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3766 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3767 &zero_address_frag
));
3769 for (i
= 0; i
< 32; i
++)
3773 /* R5900 VU0 floating-point register. */
3774 sprintf (regname
, "$vf%d", i
);
3775 symbol_table_insert (symbol_new (regname
, reg_section
,
3776 RTYPE_VF
| i
, &zero_address_frag
));
3778 /* R5900 VU0 integer register. */
3779 sprintf (regname
, "$vi%d", i
);
3780 symbol_table_insert (symbol_new (regname
, reg_section
,
3781 RTYPE_VI
| i
, &zero_address_frag
));
3784 sprintf (regname
, "$w%d", i
);
3785 symbol_table_insert (symbol_new (regname
, reg_section
,
3786 RTYPE_MSA
| i
, &zero_address_frag
));
3789 obstack_init (&mips_operand_tokens
);
3791 mips_no_prev_insn ();
3794 mips_cprmask
[0] = 0;
3795 mips_cprmask
[1] = 0;
3796 mips_cprmask
[2] = 0;
3797 mips_cprmask
[3] = 0;
3799 /* set the default alignment for the text section (2**2) */
3800 record_alignment (text_section
, 2);
3802 bfd_set_gp_size (stdoutput
, g_switch_value
);
3804 /* On a native system other than VxWorks, sections must be aligned
3805 to 16 byte boundaries. When configured for an embedded ELF
3806 target, we don't bother. */
3807 if (strncmp (TARGET_OS
, "elf", 3) != 0
3808 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3810 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3811 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3812 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3815 /* Create a .reginfo section for register masks and a .mdebug
3816 section for debugging information. */
3824 subseg
= now_subseg
;
3826 /* The ABI says this section should be loaded so that the
3827 running program can access it. However, we don't load it
3828 if we are configured for an embedded target */
3829 flags
= SEC_READONLY
| SEC_DATA
;
3830 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3831 flags
|= SEC_ALLOC
| SEC_LOAD
;
3833 if (mips_abi
!= N64_ABI
)
3835 sec
= subseg_new (".reginfo", (subsegT
) 0);
3837 bfd_set_section_flags (stdoutput
, sec
, flags
);
3838 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3840 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3844 /* The 64-bit ABI uses a .MIPS.options section rather than
3845 .reginfo section. */
3846 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3847 bfd_set_section_flags (stdoutput
, sec
, flags
);
3848 bfd_set_section_alignment (stdoutput
, sec
, 3);
3850 /* Set up the option header. */
3852 Elf_Internal_Options opthdr
;
3855 opthdr
.kind
= ODK_REGINFO
;
3856 opthdr
.size
= (sizeof (Elf_External_Options
)
3857 + sizeof (Elf64_External_RegInfo
));
3860 f
= frag_more (sizeof (Elf_External_Options
));
3861 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3862 (Elf_External_Options
*) f
);
3864 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3868 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3869 bfd_set_section_flags (stdoutput
, sec
,
3870 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3871 bfd_set_section_alignment (stdoutput
, sec
, 3);
3872 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3874 if (ECOFF_DEBUGGING
)
3876 sec
= subseg_new (".mdebug", (subsegT
) 0);
3877 (void) bfd_set_section_flags (stdoutput
, sec
,
3878 SEC_HAS_CONTENTS
| SEC_READONLY
);
3879 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3881 else if (mips_flag_pdr
)
3883 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3884 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3885 SEC_READONLY
| SEC_RELOC
3887 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3890 subseg_set (seg
, subseg
);
3893 if (mips_fix_vr4120
)
3894 init_vr4120_conflicts ();
3898 fpabi_incompatible_with (int fpabi
, const char *what
)
3900 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3901 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3905 fpabi_requires (int fpabi
, const char *what
)
3907 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3908 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3911 /* Check -mabi and register sizes against the specified FP ABI. */
3913 check_fpabi (int fpabi
)
3917 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3918 if (file_mips_opts
.soft_float
)
3919 fpabi_incompatible_with (fpabi
, "softfloat");
3920 else if (file_mips_opts
.single_float
)
3921 fpabi_incompatible_with (fpabi
, "singlefloat");
3922 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3923 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3924 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3925 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3928 case Val_GNU_MIPS_ABI_FP_XX
:
3929 if (mips_abi
!= O32_ABI
)
3930 fpabi_requires (fpabi
, "-mabi=32");
3931 else if (file_mips_opts
.soft_float
)
3932 fpabi_incompatible_with (fpabi
, "softfloat");
3933 else if (file_mips_opts
.single_float
)
3934 fpabi_incompatible_with (fpabi
, "singlefloat");
3935 else if (file_mips_opts
.fp
!= 0)
3936 fpabi_requires (fpabi
, "fp=xx");
3939 case Val_GNU_MIPS_ABI_FP_64A
:
3940 case Val_GNU_MIPS_ABI_FP_64
:
3941 if (mips_abi
!= O32_ABI
)
3942 fpabi_requires (fpabi
, "-mabi=32");
3943 else if (file_mips_opts
.soft_float
)
3944 fpabi_incompatible_with (fpabi
, "softfloat");
3945 else if (file_mips_opts
.single_float
)
3946 fpabi_incompatible_with (fpabi
, "singlefloat");
3947 else if (file_mips_opts
.fp
!= 64)
3948 fpabi_requires (fpabi
, "fp=64");
3949 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3950 fpabi_incompatible_with (fpabi
, "nooddspreg");
3951 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3952 fpabi_requires (fpabi
, "nooddspreg");
3955 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3956 if (file_mips_opts
.soft_float
)
3957 fpabi_incompatible_with (fpabi
, "softfloat");
3958 else if (!file_mips_opts
.single_float
)
3959 fpabi_requires (fpabi
, "singlefloat");
3962 case Val_GNU_MIPS_ABI_FP_SOFT
:
3963 if (!file_mips_opts
.soft_float
)
3964 fpabi_requires (fpabi
, "softfloat");
3967 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3968 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3969 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3972 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3973 /* Silently ignore compatibility value. */
3977 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3978 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3983 /* Perform consistency checks on the current options. */
3986 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3988 /* Check the size of integer registers agrees with the ABI and ISA. */
3989 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3990 as_bad (_("`gp=64' used with a 32-bit processor"));
3992 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3993 as_bad (_("`gp=32' used with a 64-bit ABI"));
3995 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3996 as_bad (_("`gp=64' used with a 32-bit ABI"));
3998 /* Check the size of the float registers agrees with the ABI and ISA. */
4002 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4003 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4004 else if (opts
->single_float
== 1)
4005 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4008 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4009 as_bad (_("`fp=64' used with a 32-bit fpu"));
4011 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4012 && !ISA_HAS_MXHC1 (opts
->isa
))
4013 as_warn (_("`fp=64' used with a 32-bit ABI"));
4017 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4018 as_warn (_("`fp=32' used with a 64-bit ABI"));
4019 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4020 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4023 as_bad (_("Unknown size of floating point registers"));
4027 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4028 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4030 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4031 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4032 else if (ISA_IS_R6 (opts
->isa
)
4033 && (opts
->micromips
== 1
4034 || opts
->mips16
== 1))
4035 as_fatal (_("`%s' cannot be used with `%s'"),
4036 opts
->micromips
? "micromips" : "mips16",
4037 mips_cpu_info_from_isa (opts
->isa
)->name
);
4039 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4040 as_fatal (_("branch relaxation is not supported in `%s'"),
4041 mips_cpu_info_from_isa (opts
->isa
)->name
);
4044 /* Perform consistency checks on the module level options exactly once.
4045 This is a deferred check that happens:
4046 at the first .set directive
4047 or, at the first pseudo op that generates code (inc .dc.a)
4048 or, at the first instruction
4052 file_mips_check_options (void)
4054 const struct mips_cpu_info
*arch_info
= 0;
4056 if (file_mips_opts_checked
)
4059 /* The following code determines the register size.
4060 Similar code was added to GCC 3.3 (see override_options() in
4061 config/mips/mips.c). The GAS and GCC code should be kept in sync
4062 as much as possible. */
4064 if (file_mips_opts
.gp
< 0)
4066 /* Infer the integer register size from the ABI and processor.
4067 Restrict ourselves to 32-bit registers if that's all the
4068 processor has, or if the ABI cannot handle 64-bit registers. */
4069 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4070 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4074 if (file_mips_opts
.fp
< 0)
4076 /* No user specified float register size.
4077 ??? GAS treats single-float processors as though they had 64-bit
4078 float registers (although it complains when double-precision
4079 instructions are used). As things stand, saying they have 32-bit
4080 registers would lead to spurious "register must be even" messages.
4081 So here we assume float registers are never smaller than the
4083 if (file_mips_opts
.gp
== 64)
4084 /* 64-bit integer registers implies 64-bit float registers. */
4085 file_mips_opts
.fp
= 64;
4086 else if ((file_mips_opts
.ase
& FP64_ASES
)
4087 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4088 /* Handle ASEs that require 64-bit float registers, if possible. */
4089 file_mips_opts
.fp
= 64;
4090 else if (ISA_IS_R6 (mips_opts
.isa
))
4091 /* R6 implies 64-bit float registers. */
4092 file_mips_opts
.fp
= 64;
4094 /* 32-bit float registers. */
4095 file_mips_opts
.fp
= 32;
4098 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
4100 /* Disable operations on odd-numbered floating-point registers by default
4101 when using the FPXX ABI. */
4102 if (file_mips_opts
.oddspreg
< 0)
4104 if (file_mips_opts
.fp
== 0)
4105 file_mips_opts
.oddspreg
= 0;
4107 file_mips_opts
.oddspreg
= 1;
4110 /* End of GCC-shared inference code. */
4112 /* This flag is set when we have a 64-bit capable CPU but use only
4113 32-bit wide registers. Note that EABI does not use it. */
4114 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4115 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4116 || mips_abi
== O32_ABI
))
4119 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4120 as_bad (_("trap exception not supported at ISA 1"));
4122 /* If the selected architecture includes support for ASEs, enable
4123 generation of code for them. */
4124 if (file_mips_opts
.mips16
== -1)
4125 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4126 if (file_mips_opts
.micromips
== -1)
4127 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4130 if (mips_nan2008
== -1)
4131 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4132 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4133 as_fatal (_("`%s' does not support legacy NaN"),
4134 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4136 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4137 being selected implicitly. */
4138 if (file_mips_opts
.fp
!= 64)
4139 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4141 /* If the user didn't explicitly select or deselect a particular ASE,
4142 use the default setting for the CPU. */
4143 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4145 /* Set up the current options. These may change throughout assembly. */
4146 mips_opts
= file_mips_opts
;
4148 mips_check_isa_supports_ases ();
4149 mips_check_options (&file_mips_opts
, TRUE
);
4150 file_mips_opts_checked
= TRUE
;
4152 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4153 as_warn (_("could not set architecture and machine"));
4157 md_assemble (char *str
)
4159 struct mips_cl_insn insn
;
4160 bfd_reloc_code_real_type unused_reloc
[3]
4161 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4163 file_mips_check_options ();
4165 imm_expr
.X_op
= O_absent
;
4166 offset_expr
.X_op
= O_absent
;
4167 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4168 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4169 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4171 mips_mark_labels ();
4172 mips_assembling_insn
= TRUE
;
4173 clear_insn_error ();
4175 if (mips_opts
.mips16
)
4176 mips16_ip (str
, &insn
);
4179 mips_ip (str
, &insn
);
4180 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4181 str
, insn
.insn_opcode
));
4185 report_insn_error (str
);
4186 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4189 if (mips_opts
.mips16
)
4190 mips16_macro (&insn
);
4197 if (offset_expr
.X_op
!= O_absent
)
4198 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4200 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4203 mips_assembling_insn
= FALSE
;
4206 /* Convenience functions for abstracting away the differences between
4207 MIPS16 and non-MIPS16 relocations. */
4209 static inline bfd_boolean
4210 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4214 case BFD_RELOC_MIPS16_JMP
:
4215 case BFD_RELOC_MIPS16_GPREL
:
4216 case BFD_RELOC_MIPS16_GOT16
:
4217 case BFD_RELOC_MIPS16_CALL16
:
4218 case BFD_RELOC_MIPS16_HI16_S
:
4219 case BFD_RELOC_MIPS16_HI16
:
4220 case BFD_RELOC_MIPS16_LO16
:
4221 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4229 static inline bfd_boolean
4230 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4234 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4235 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4236 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4237 case BFD_RELOC_MICROMIPS_GPREL16
:
4238 case BFD_RELOC_MICROMIPS_JMP
:
4239 case BFD_RELOC_MICROMIPS_HI16
:
4240 case BFD_RELOC_MICROMIPS_HI16_S
:
4241 case BFD_RELOC_MICROMIPS_LO16
:
4242 case BFD_RELOC_MICROMIPS_LITERAL
:
4243 case BFD_RELOC_MICROMIPS_GOT16
:
4244 case BFD_RELOC_MICROMIPS_CALL16
:
4245 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4246 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4247 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4248 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4249 case BFD_RELOC_MICROMIPS_SUB
:
4250 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4251 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4252 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4253 case BFD_RELOC_MICROMIPS_HIGHEST
:
4254 case BFD_RELOC_MICROMIPS_HIGHER
:
4255 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4256 case BFD_RELOC_MICROMIPS_JALR
:
4264 static inline bfd_boolean
4265 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4267 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4270 static inline bfd_boolean
4271 b_reloc_p (bfd_reloc_code_real_type reloc
)
4273 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4274 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4275 || reloc
== BFD_RELOC_16_PCREL_S2
4276 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4277 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4278 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4279 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4282 static inline bfd_boolean
4283 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4285 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4286 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4289 static inline bfd_boolean
4290 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4292 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4293 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4296 static inline bfd_boolean
4297 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4299 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4300 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4303 static inline bfd_boolean
4304 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4306 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4309 static inline bfd_boolean
4310 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4312 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4313 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4316 /* Return true if RELOC is a PC-relative relocation that does not have
4317 full address range. */
4319 static inline bfd_boolean
4320 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4324 case BFD_RELOC_16_PCREL_S2
:
4325 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4326 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4327 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4328 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4329 case BFD_RELOC_MIPS_21_PCREL_S2
:
4330 case BFD_RELOC_MIPS_26_PCREL_S2
:
4331 case BFD_RELOC_MIPS_18_PCREL_S3
:
4332 case BFD_RELOC_MIPS_19_PCREL_S2
:
4335 case BFD_RELOC_32_PCREL
:
4336 case BFD_RELOC_HI16_S_PCREL
:
4337 case BFD_RELOC_LO16_PCREL
:
4338 return HAVE_64BIT_ADDRESSES
;
4345 /* Return true if the given relocation might need a matching %lo().
4346 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4347 need a matching %lo() when applied to local symbols. */
4349 static inline bfd_boolean
4350 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4352 return (HAVE_IN_PLACE_ADDENDS
4353 && (hi16_reloc_p (reloc
)
4354 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4355 all GOT16 relocations evaluate to "G". */
4356 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4359 /* Return the type of %lo() reloc needed by RELOC, given that
4360 reloc_needs_lo_p. */
4362 static inline bfd_reloc_code_real_type
4363 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4365 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4366 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4370 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4373 static inline bfd_boolean
4374 fixup_has_matching_lo_p (fixS
*fixp
)
4376 return (fixp
->fx_next
!= NULL
4377 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4378 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4379 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4382 /* Move all labels in LABELS to the current insertion point. TEXT_P
4383 says whether the labels refer to text or data. */
4386 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4388 struct insn_label_list
*l
;
4391 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4393 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4394 symbol_set_frag (l
->label
, frag_now
);
4395 val
= (valueT
) frag_now_fix ();
4396 /* MIPS16/microMIPS text labels are stored as odd. */
4397 if (text_p
&& HAVE_CODE_COMPRESSION
)
4399 S_SET_VALUE (l
->label
, val
);
4403 /* Move all labels in insn_labels to the current insertion point
4404 and treat them as text labels. */
4407 mips_move_text_labels (void)
4409 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4412 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4415 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4417 bfd_boolean linkonce
= FALSE
;
4418 segT symseg
= S_GET_SEGMENT (sym
);
4420 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4422 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4424 /* The GNU toolchain uses an extension for ELF: a section
4425 beginning with the magic string .gnu.linkonce is a
4426 linkonce section. */
4427 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4428 sizeof ".gnu.linkonce" - 1) == 0)
4434 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4435 linker to handle them specially, such as generating jalx instructions
4436 when needed. We also make them odd for the duration of the assembly,
4437 in order to generate the right sort of code. We will make them even
4438 in the adjust_symtab routine, while leaving them marked. This is
4439 convenient for the debugger and the disassembler. The linker knows
4440 to make them odd again. */
4443 mips_compressed_mark_label (symbolS
*label
)
4445 gas_assert (HAVE_CODE_COMPRESSION
);
4447 if (mips_opts
.mips16
)
4448 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4450 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4451 if ((S_GET_VALUE (label
) & 1) == 0
4452 /* Don't adjust the address if the label is global or weak, or
4453 in a link-once section, since we'll be emitting symbol reloc
4454 references to it which will be patched up by the linker, and
4455 the final value of the symbol may or may not be MIPS16/microMIPS. */
4456 && !S_IS_WEAK (label
)
4457 && !S_IS_EXTERNAL (label
)
4458 && !s_is_linkonce (label
, now_seg
))
4459 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4462 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4465 mips_compressed_mark_labels (void)
4467 struct insn_label_list
*l
;
4469 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4470 mips_compressed_mark_label (l
->label
);
4473 /* End the current frag. Make it a variant frag and record the
4477 relax_close_frag (void)
4479 mips_macro_warning
.first_frag
= frag_now
;
4480 frag_var (rs_machine_dependent
, 0, 0,
4481 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4482 mips_pic
!= NO_PIC
),
4483 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4485 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4486 mips_relax
.first_fixup
= 0;
4489 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4490 See the comment above RELAX_ENCODE for more details. */
4493 relax_start (symbolS
*symbol
)
4495 gas_assert (mips_relax
.sequence
== 0);
4496 mips_relax
.sequence
= 1;
4497 mips_relax
.symbol
= symbol
;
4500 /* Start generating the second version of a relaxable sequence.
4501 See the comment above RELAX_ENCODE for more details. */
4506 gas_assert (mips_relax
.sequence
== 1);
4507 mips_relax
.sequence
= 2;
4510 /* End the current relaxable sequence. */
4515 gas_assert (mips_relax
.sequence
== 2);
4516 relax_close_frag ();
4517 mips_relax
.sequence
= 0;
4520 /* Return true if IP is a delayed branch or jump. */
4522 static inline bfd_boolean
4523 delayed_branch_p (const struct mips_cl_insn
*ip
)
4525 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4526 | INSN_COND_BRANCH_DELAY
4527 | INSN_COND_BRANCH_LIKELY
)) != 0;
4530 /* Return true if IP is a compact branch or jump. */
4532 static inline bfd_boolean
4533 compact_branch_p (const struct mips_cl_insn
*ip
)
4535 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4536 | INSN2_COND_BRANCH
)) != 0;
4539 /* Return true if IP is an unconditional branch or jump. */
4541 static inline bfd_boolean
4542 uncond_branch_p (const struct mips_cl_insn
*ip
)
4544 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4545 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4548 /* Return true if IP is a branch-likely instruction. */
4550 static inline bfd_boolean
4551 branch_likely_p (const struct mips_cl_insn
*ip
)
4553 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4556 /* Return the type of nop that should be used to fill the delay slot
4557 of delayed branch IP. */
4559 static struct mips_cl_insn
*
4560 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4562 if (mips_opts
.micromips
4563 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4564 return µmips_nop32_insn
;
4568 /* Return a mask that has bit N set if OPCODE reads the register(s)
4572 insn_read_mask (const struct mips_opcode
*opcode
)
4574 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4577 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4581 insn_write_mask (const struct mips_opcode
*opcode
)
4583 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4586 /* Return a mask of the registers specified by operand OPERAND of INSN.
4587 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4591 operand_reg_mask (const struct mips_cl_insn
*insn
,
4592 const struct mips_operand
*operand
,
4593 unsigned int type_mask
)
4595 unsigned int uval
, vsel
;
4597 switch (operand
->type
)
4604 case OP_ADDIUSP_INT
:
4605 case OP_ENTRY_EXIT_LIST
:
4606 case OP_REPEAT_DEST_REG
:
4607 case OP_REPEAT_PREV_REG
:
4610 case OP_VU0_MATCH_SUFFIX
:
4618 case OP_OPTIONAL_REG
:
4620 const struct mips_reg_operand
*reg_op
;
4622 reg_op
= (const struct mips_reg_operand
*) operand
;
4623 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4625 uval
= insn_extract_operand (insn
, operand
);
4626 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4631 const struct mips_reg_pair_operand
*pair_op
;
4633 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4634 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4636 uval
= insn_extract_operand (insn
, operand
);
4637 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4640 case OP_CLO_CLZ_DEST
:
4641 if (!(type_mask
& (1 << OP_REG_GP
)))
4643 uval
= insn_extract_operand (insn
, operand
);
4644 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4647 if (!(type_mask
& (1 << OP_REG_GP
)))
4649 uval
= insn_extract_operand (insn
, operand
);
4650 gas_assert ((uval
& 31) == (uval
>> 5));
4651 return 1 << (uval
& 31);
4654 case OP_NON_ZERO_REG
:
4655 if (!(type_mask
& (1 << OP_REG_GP
)))
4657 uval
= insn_extract_operand (insn
, operand
);
4658 return 1 << (uval
& 31);
4660 case OP_LWM_SWM_LIST
:
4663 case OP_SAVE_RESTORE_LIST
:
4666 case OP_MDMX_IMM_REG
:
4667 if (!(type_mask
& (1 << OP_REG_VEC
)))
4669 uval
= insn_extract_operand (insn
, operand
);
4671 if ((vsel
& 0x18) == 0x18)
4673 return 1 << (uval
& 31);
4676 if (!(type_mask
& (1 << OP_REG_GP
)))
4678 return 1 << insn_extract_operand (insn
, operand
);
4683 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4684 where bit N of OPNO_MASK is set if operand N should be included.
4685 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4689 insn_reg_mask (const struct mips_cl_insn
*insn
,
4690 unsigned int type_mask
, unsigned int opno_mask
)
4692 unsigned int opno
, reg_mask
;
4696 while (opno_mask
!= 0)
4699 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4706 /* Return the mask of core registers that IP reads. */
4709 gpr_read_mask (const struct mips_cl_insn
*ip
)
4711 unsigned long pinfo
, pinfo2
;
4714 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4715 pinfo
= ip
->insn_mo
->pinfo
;
4716 pinfo2
= ip
->insn_mo
->pinfo2
;
4717 if (pinfo
& INSN_UDI
)
4719 /* UDI instructions have traditionally been assumed to read RS
4721 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4722 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4724 if (pinfo
& INSN_READ_GPR_24
)
4726 if (pinfo2
& INSN2_READ_GPR_16
)
4728 if (pinfo2
& INSN2_READ_SP
)
4730 if (pinfo2
& INSN2_READ_GPR_31
)
4732 /* Don't include register 0. */
4736 /* Return the mask of core registers that IP writes. */
4739 gpr_write_mask (const struct mips_cl_insn
*ip
)
4741 unsigned long pinfo
, pinfo2
;
4744 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4745 pinfo
= ip
->insn_mo
->pinfo
;
4746 pinfo2
= ip
->insn_mo
->pinfo2
;
4747 if (pinfo
& INSN_WRITE_GPR_24
)
4749 if (pinfo
& INSN_WRITE_GPR_31
)
4751 if (pinfo
& INSN_UDI
)
4752 /* UDI instructions have traditionally been assumed to write to RD. */
4753 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4754 if (pinfo2
& INSN2_WRITE_SP
)
4756 /* Don't include register 0. */
4760 /* Return the mask of floating-point registers that IP reads. */
4763 fpr_read_mask (const struct mips_cl_insn
*ip
)
4765 unsigned long pinfo
;
4768 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4769 | (1 << OP_REG_MSA
)),
4770 insn_read_mask (ip
->insn_mo
));
4771 pinfo
= ip
->insn_mo
->pinfo
;
4772 /* Conservatively treat all operands to an FP_D instruction are doubles.
4773 (This is overly pessimistic for things like cvt.d.s.) */
4774 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4779 /* Return the mask of floating-point registers that IP writes. */
4782 fpr_write_mask (const struct mips_cl_insn
*ip
)
4784 unsigned long pinfo
;
4787 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4788 | (1 << OP_REG_MSA
)),
4789 insn_write_mask (ip
->insn_mo
));
4790 pinfo
= ip
->insn_mo
->pinfo
;
4791 /* Conservatively treat all operands to an FP_D instruction are doubles.
4792 (This is overly pessimistic for things like cvt.s.d.) */
4793 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4798 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4799 Check whether that is allowed. */
4802 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4804 const char *s
= insn
->name
;
4805 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4807 && mips_opts
.oddspreg
;
4809 if (insn
->pinfo
== INSN_MACRO
)
4810 /* Let a macro pass, we'll catch it later when it is expanded. */
4813 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4814 otherwise it depends on oddspreg. */
4815 if ((insn
->pinfo
& FP_S
)
4816 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4817 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4818 return FPR_SIZE
== 32 || oddspreg
;
4820 /* Allow odd registers for single-precision ops and double-precision if the
4821 floating-point registers are 64-bit wide. */
4822 switch (insn
->pinfo
& (FP_S
| FP_D
))
4828 return FPR_SIZE
== 64;
4833 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4834 s
= strchr (insn
->name
, '.');
4835 if (s
!= NULL
&& opnum
== 2)
4836 s
= strchr (s
+ 1, '.');
4837 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4840 return FPR_SIZE
== 64;
4843 /* Information about an instruction argument that we're trying to match. */
4844 struct mips_arg_info
4846 /* The instruction so far. */
4847 struct mips_cl_insn
*insn
;
4849 /* The first unconsumed operand token. */
4850 struct mips_operand_token
*token
;
4852 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4855 /* The 1-based argument number, for error reporting. This does not
4856 count elided optional registers, etc.. */
4859 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4860 unsigned int last_regno
;
4862 /* If the first operand was an OP_REG, this is the register that it
4863 specified, otherwise it is ILLEGAL_REG. */
4864 unsigned int dest_regno
;
4866 /* The value of the last OP_INT operand. Only used for OP_MSB,
4867 where it gives the lsb position. */
4868 unsigned int last_op_int
;
4870 /* If true, match routines should assume that no later instruction
4871 alternative matches and should therefore be as accommodating as
4872 possible. Match routines should not report errors if something
4873 is only invalid for !LAX_MATCH. */
4874 bfd_boolean lax_match
;
4876 /* True if a reference to the current AT register was seen. */
4877 bfd_boolean seen_at
;
4880 /* Record that the argument is out of range. */
4883 match_out_of_range (struct mips_arg_info
*arg
)
4885 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4888 /* Record that the argument isn't constant but needs to be. */
4891 match_not_constant (struct mips_arg_info
*arg
)
4893 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4897 /* Try to match an OT_CHAR token for character CH. Consume the token
4898 and return true on success, otherwise return false. */
4901 match_char (struct mips_arg_info
*arg
, char ch
)
4903 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4913 /* Try to get an expression from the next tokens in ARG. Consume the
4914 tokens and return true on success, storing the expression value in
4915 VALUE and relocation types in R. */
4918 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4919 bfd_reloc_code_real_type
*r
)
4921 /* If the next token is a '(' that was parsed as being part of a base
4922 expression, assume we have an elided offset. The later match will fail
4923 if this turns out to be wrong. */
4924 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4926 value
->X_op
= O_constant
;
4927 value
->X_add_number
= 0;
4928 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4932 /* Reject register-based expressions such as "0+$2" and "(($2))".
4933 For plain registers the default error seems more appropriate. */
4934 if (arg
->token
->type
== OT_INTEGER
4935 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4937 set_insn_error (arg
->argnum
, _("register value used as expression"));
4941 if (arg
->token
->type
== OT_INTEGER
)
4943 *value
= arg
->token
->u
.integer
.value
;
4944 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4950 (arg
->argnum
, _("operand %d must be an immediate expression"),
4955 /* Try to get a constant expression from the next tokens in ARG. Consume
4956 the tokens and return true on success, storing the constant value
4960 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4963 bfd_reloc_code_real_type r
[3];
4965 if (!match_expression (arg
, &ex
, r
))
4968 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4969 *value
= ex
.X_add_number
;
4972 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
4973 match_out_of_range (arg
);
4975 match_not_constant (arg
);
4981 /* Return the RTYPE_* flags for a register operand of type TYPE that
4982 appears in instruction OPCODE. */
4985 convert_reg_type (const struct mips_opcode
*opcode
,
4986 enum mips_reg_operand_type type
)
4991 return RTYPE_NUM
| RTYPE_GP
;
4994 /* Allow vector register names for MDMX if the instruction is a 64-bit
4995 FPR load, store or move (including moves to and from GPRs). */
4996 if ((mips_opts
.ase
& ASE_MDMX
)
4997 && (opcode
->pinfo
& FP_D
)
4998 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4999 | INSN_COPROC_MEMORY_DELAY
5002 | INSN_STORE_MEMORY
)))
5003 return RTYPE_FPU
| RTYPE_VEC
;
5007 if (opcode
->pinfo
& (FP_D
| FP_S
))
5008 return RTYPE_CCC
| RTYPE_FCC
;
5012 if (opcode
->membership
& INSN_5400
)
5014 return RTYPE_FPU
| RTYPE_VEC
;
5020 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5021 return RTYPE_NUM
| RTYPE_CP0
;
5028 return RTYPE_NUM
| RTYPE_VI
;
5031 return RTYPE_NUM
| RTYPE_VF
;
5033 case OP_REG_R5900_I
:
5034 return RTYPE_R5900_I
;
5036 case OP_REG_R5900_Q
:
5037 return RTYPE_R5900_Q
;
5039 case OP_REG_R5900_R
:
5040 return RTYPE_R5900_R
;
5042 case OP_REG_R5900_ACC
:
5043 return RTYPE_R5900_ACC
;
5048 case OP_REG_MSA_CTRL
:
5054 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5057 check_regno (struct mips_arg_info
*arg
,
5058 enum mips_reg_operand_type type
, unsigned int regno
)
5060 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5061 arg
->seen_at
= TRUE
;
5063 if (type
== OP_REG_FP
5065 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5067 /* This was a warning prior to introducing O32 FPXX and FP64 support
5068 so maintain a warning for FP32 but raise an error for the new
5071 as_warn (_("float register should be even, was %d"), regno
);
5073 as_bad (_("float register should be even, was %d"), regno
);
5076 if (type
== OP_REG_CCC
)
5081 name
= arg
->insn
->insn_mo
->name
;
5082 length
= strlen (name
);
5083 if ((regno
& 1) != 0
5084 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5085 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5086 as_warn (_("condition code register should be even for %s, was %d"),
5089 if ((regno
& 3) != 0
5090 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5091 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5096 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5097 a register of type TYPE. Return true on success, storing the register
5098 number in *REGNO and warning about any dubious uses. */
5101 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5102 unsigned int symval
, unsigned int *regno
)
5104 if (type
== OP_REG_VEC
)
5105 symval
= mips_prefer_vec_regno (symval
);
5106 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5109 *regno
= symval
& RNUM_MASK
;
5110 check_regno (arg
, type
, *regno
);
5114 /* Try to interpret the next token in ARG as a register of type TYPE.
5115 Consume the token and return true on success, storing the register
5116 number in *REGNO. Return false on failure. */
5119 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5120 unsigned int *regno
)
5122 if (arg
->token
->type
== OT_REG
5123 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5131 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5132 Consume the token and return true on success, storing the register numbers
5133 in *REGNO1 and *REGNO2. Return false on failure. */
5136 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5137 unsigned int *regno1
, unsigned int *regno2
)
5139 if (match_reg (arg
, type
, regno1
))
5144 if (arg
->token
->type
== OT_REG_RANGE
5145 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5146 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5147 && *regno1
<= *regno2
)
5155 /* OP_INT matcher. */
5158 match_int_operand (struct mips_arg_info
*arg
,
5159 const struct mips_operand
*operand_base
)
5161 const struct mips_int_operand
*operand
;
5163 int min_val
, max_val
, factor
;
5166 operand
= (const struct mips_int_operand
*) operand_base
;
5167 factor
= 1 << operand
->shift
;
5168 min_val
= mips_int_operand_min (operand
);
5169 max_val
= mips_int_operand_max (operand
);
5171 if (operand_base
->lsb
== 0
5172 && operand_base
->size
== 16
5173 && operand
->shift
== 0
5174 && operand
->bias
== 0
5175 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5177 /* The operand can be relocated. */
5178 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5181 if (offset_expr
.X_op
== O_big
)
5183 match_out_of_range (arg
);
5187 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5188 /* Relocation operators were used. Accept the argument and
5189 leave the relocation value in offset_expr and offset_relocs
5190 for the caller to process. */
5193 if (offset_expr
.X_op
!= O_constant
)
5195 /* Accept non-constant operands if no later alternative matches,
5196 leaving it for the caller to process. */
5197 if (!arg
->lax_match
)
5199 match_not_constant (arg
);
5202 offset_reloc
[0] = BFD_RELOC_LO16
;
5206 /* Clear the global state; we're going to install the operand
5208 sval
= offset_expr
.X_add_number
;
5209 offset_expr
.X_op
= O_absent
;
5211 /* For compatibility with older assemblers, we accept
5212 0x8000-0xffff as signed 16-bit numbers when only
5213 signed numbers are allowed. */
5216 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5217 if (!arg
->lax_match
&& sval
<= max_val
)
5219 match_out_of_range (arg
);
5226 if (!match_const_int (arg
, &sval
))
5230 arg
->last_op_int
= sval
;
5232 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5234 match_out_of_range (arg
);
5238 uval
= (unsigned int) sval
>> operand
->shift
;
5239 uval
-= operand
->bias
;
5241 /* Handle -mfix-cn63xxp1. */
5243 && mips_fix_cn63xxp1
5244 && !mips_opts
.micromips
5245 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5260 /* The rest must be changed to 28. */
5265 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5269 /* OP_MAPPED_INT matcher. */
5272 match_mapped_int_operand (struct mips_arg_info
*arg
,
5273 const struct mips_operand
*operand_base
)
5275 const struct mips_mapped_int_operand
*operand
;
5276 unsigned int uval
, num_vals
;
5279 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5280 if (!match_const_int (arg
, &sval
))
5283 num_vals
= 1 << operand_base
->size
;
5284 for (uval
= 0; uval
< num_vals
; uval
++)
5285 if (operand
->int_map
[uval
] == sval
)
5287 if (uval
== num_vals
)
5289 match_out_of_range (arg
);
5293 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5297 /* OP_MSB matcher. */
5300 match_msb_operand (struct mips_arg_info
*arg
,
5301 const struct mips_operand
*operand_base
)
5303 const struct mips_msb_operand
*operand
;
5304 int min_val
, max_val
, max_high
;
5305 offsetT size
, sval
, high
;
5307 operand
= (const struct mips_msb_operand
*) operand_base
;
5308 min_val
= operand
->bias
;
5309 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5310 max_high
= operand
->opsize
;
5312 if (!match_const_int (arg
, &size
))
5315 high
= size
+ arg
->last_op_int
;
5316 sval
= operand
->add_lsb
? high
: size
;
5318 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5320 match_out_of_range (arg
);
5323 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5327 /* OP_REG matcher. */
5330 match_reg_operand (struct mips_arg_info
*arg
,
5331 const struct mips_operand
*operand_base
)
5333 const struct mips_reg_operand
*operand
;
5334 unsigned int regno
, uval
, num_vals
;
5336 operand
= (const struct mips_reg_operand
*) operand_base
;
5337 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5340 if (operand
->reg_map
)
5342 num_vals
= 1 << operand
->root
.size
;
5343 for (uval
= 0; uval
< num_vals
; uval
++)
5344 if (operand
->reg_map
[uval
] == regno
)
5346 if (num_vals
== uval
)
5352 arg
->last_regno
= regno
;
5353 if (arg
->opnum
== 1)
5354 arg
->dest_regno
= regno
;
5355 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5359 /* OP_REG_PAIR matcher. */
5362 match_reg_pair_operand (struct mips_arg_info
*arg
,
5363 const struct mips_operand
*operand_base
)
5365 const struct mips_reg_pair_operand
*operand
;
5366 unsigned int regno1
, regno2
, uval
, num_vals
;
5368 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5369 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5370 || !match_char (arg
, ',')
5371 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5374 num_vals
= 1 << operand_base
->size
;
5375 for (uval
= 0; uval
< num_vals
; uval
++)
5376 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5378 if (uval
== num_vals
)
5381 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5385 /* OP_PCREL matcher. The caller chooses the relocation type. */
5388 match_pcrel_operand (struct mips_arg_info
*arg
)
5390 bfd_reloc_code_real_type r
[3];
5392 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5395 /* OP_PERF_REG matcher. */
5398 match_perf_reg_operand (struct mips_arg_info
*arg
,
5399 const struct mips_operand
*operand
)
5403 if (!match_const_int (arg
, &sval
))
5408 || (mips_opts
.arch
== CPU_R5900
5409 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5410 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5412 set_insn_error (arg
->argnum
, _("invalid performance register"));
5416 insn_insert_operand (arg
->insn
, operand
, sval
);
5420 /* OP_ADDIUSP matcher. */
5423 match_addiusp_operand (struct mips_arg_info
*arg
,
5424 const struct mips_operand
*operand
)
5429 if (!match_const_int (arg
, &sval
))
5434 match_out_of_range (arg
);
5439 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5441 match_out_of_range (arg
);
5445 uval
= (unsigned int) sval
;
5446 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5447 insn_insert_operand (arg
->insn
, operand
, uval
);
5451 /* OP_CLO_CLZ_DEST matcher. */
5454 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5455 const struct mips_operand
*operand
)
5459 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5462 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5466 /* OP_CHECK_PREV matcher. */
5469 match_check_prev_operand (struct mips_arg_info
*arg
,
5470 const struct mips_operand
*operand_base
)
5472 const struct mips_check_prev_operand
*operand
;
5475 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5477 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5480 if (!operand
->zero_ok
&& regno
== 0)
5483 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5484 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5485 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5487 arg
->last_regno
= regno
;
5488 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5495 /* OP_SAME_RS_RT matcher. */
5498 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5499 const struct mips_operand
*operand
)
5503 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5508 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5512 arg
->last_regno
= regno
;
5514 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5518 /* OP_LWM_SWM_LIST matcher. */
5521 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5522 const struct mips_operand
*operand
)
5524 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5525 struct mips_arg_info reset
;
5528 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5532 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5537 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5540 while (match_char (arg
, ',')
5541 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5544 if (operand
->size
== 2)
5546 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5552 and any permutations of these. */
5553 if ((reglist
& 0xfff1ffff) != 0x80010000)
5556 sregs
= (reglist
>> 17) & 7;
5561 /* The list must include at least one of ra and s0-sN,
5562 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5563 which are $23 and $30 respectively.) E.g.:
5571 and any permutations of these. */
5572 if ((reglist
& 0x3f00ffff) != 0)
5575 ra
= (reglist
>> 27) & 0x10;
5576 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5579 if ((sregs
& -sregs
) != sregs
)
5582 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5586 /* OP_ENTRY_EXIT_LIST matcher. */
5589 match_entry_exit_operand (struct mips_arg_info
*arg
,
5590 const struct mips_operand
*operand
)
5593 bfd_boolean is_exit
;
5595 /* The format is the same for both ENTRY and EXIT, but the constraints
5597 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5598 mask
= (is_exit
? 7 << 3 : 0);
5601 unsigned int regno1
, regno2
;
5602 bfd_boolean is_freg
;
5604 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5606 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5611 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5614 mask
|= (5 + regno2
) << 3;
5616 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5617 mask
|= (regno2
- 3) << 3;
5618 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5619 mask
|= (regno2
- 15) << 1;
5620 else if (regno1
== RA
&& regno2
== RA
)
5625 while (match_char (arg
, ','));
5627 insn_insert_operand (arg
->insn
, operand
, mask
);
5631 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5632 the argument register mask AMASK, the number of static registers
5633 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5634 respectively, and the frame size FRAME_SIZE. */
5637 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5638 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5639 unsigned int frame_size
)
5641 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5642 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5645 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5646 argument register mask AMASK, the number of static registers saved
5647 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5648 respectively, and the frame size FRAME_SIZE. */
5651 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5652 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5653 unsigned int frame_size
)
5657 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5658 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5659 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5660 | ((frame_size
& 0xf0) << 16));
5664 /* OP_SAVE_RESTORE_LIST matcher. */
5667 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5669 unsigned int opcode
, args
, statics
, sregs
;
5670 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5671 unsigned int arg_mask
, ra
, s0
, s1
;
5674 opcode
= arg
->insn
->insn_opcode
;
5676 num_frame_sizes
= 0;
5685 unsigned int regno1
, regno2
;
5687 if (arg
->token
->type
== OT_INTEGER
)
5689 /* Handle the frame size. */
5690 if (!match_const_int (arg
, &frame_size
))
5692 num_frame_sizes
+= 1;
5696 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5699 while (regno1
<= regno2
)
5701 if (regno1
>= 4 && regno1
<= 7)
5703 if (num_frame_sizes
== 0)
5705 args
|= 1 << (regno1
- 4);
5707 /* statics $a0-$a3 */
5708 statics
|= 1 << (regno1
- 4);
5710 else if (regno1
>= 16 && regno1
<= 23)
5712 sregs
|= 1 << (regno1
- 16);
5713 else if (regno1
== 30)
5716 else if (regno1
== 31)
5717 /* Add $ra to insn. */
5727 while (match_char (arg
, ','));
5729 /* Encode args/statics combination. */
5732 else if (args
== 0xf)
5733 /* All $a0-$a3 are args. */
5734 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5735 else if (statics
== 0xf)
5736 /* All $a0-$a3 are statics. */
5737 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5740 /* Count arg registers. */
5750 /* Count static registers. */
5752 while (statics
& 0x8)
5754 statics
= (statics
<< 1) & 0xf;
5760 /* Encode args/statics. */
5761 arg_mask
= (num_args
<< 2) | num_statics
;
5764 /* Encode $s0/$s1. */
5765 if (sregs
& (1 << 0)) /* $s0 */
5767 if (sregs
& (1 << 1)) /* $s1 */
5771 /* Encode $s2-$s8. */
5781 /* Encode frame size. */
5782 if (num_frame_sizes
== 0)
5784 set_insn_error (arg
->argnum
, _("missing frame size"));
5787 if (num_frame_sizes
> 1)
5789 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5792 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5794 set_insn_error (arg
->argnum
, _("invalid frame size"));
5799 /* Finally build the instruction. */
5800 if (mips_opts
.mips16
)
5801 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5803 else if (!mips_opts
.micromips
)
5804 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5809 arg
->insn
->insn_opcode
= opcode
;
5813 /* OP_MDMX_IMM_REG matcher. */
5816 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5817 const struct mips_operand
*operand
)
5819 unsigned int regno
, uval
;
5821 const struct mips_opcode
*opcode
;
5823 /* The mips_opcode records whether this is an octobyte or quadhalf
5824 instruction. Start out with that bit in place. */
5825 opcode
= arg
->insn
->insn_mo
;
5826 uval
= mips_extract_operand (operand
, opcode
->match
);
5827 is_qh
= (uval
!= 0);
5829 if (arg
->token
->type
== OT_REG
)
5831 if ((opcode
->membership
& INSN_5400
)
5832 && strcmp (opcode
->name
, "rzu.ob") == 0)
5834 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5839 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5843 /* Check whether this is a vector register or a broadcast of
5844 a single element. */
5845 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5847 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5849 set_insn_error (arg
->argnum
, _("invalid element selector"));
5852 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5857 /* A full vector. */
5858 if ((opcode
->membership
& INSN_5400
)
5859 && (strcmp (opcode
->name
, "sll.ob") == 0
5860 || strcmp (opcode
->name
, "srl.ob") == 0))
5862 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5868 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5870 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5878 if (!match_const_int (arg
, &sval
))
5880 if (sval
< 0 || sval
> 31)
5882 match_out_of_range (arg
);
5885 uval
|= (sval
& 31);
5887 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5889 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5891 insn_insert_operand (arg
->insn
, operand
, uval
);
5895 /* OP_IMM_INDEX matcher. */
5898 match_imm_index_operand (struct mips_arg_info
*arg
,
5899 const struct mips_operand
*operand
)
5901 unsigned int max_val
;
5903 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5906 max_val
= (1 << operand
->size
) - 1;
5907 if (arg
->token
->u
.index
> max_val
)
5909 match_out_of_range (arg
);
5912 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5917 /* OP_REG_INDEX matcher. */
5920 match_reg_index_operand (struct mips_arg_info
*arg
,
5921 const struct mips_operand
*operand
)
5925 if (arg
->token
->type
!= OT_REG_INDEX
)
5928 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5931 insn_insert_operand (arg
->insn
, operand
, regno
);
5936 /* OP_PC matcher. */
5939 match_pc_operand (struct mips_arg_info
*arg
)
5941 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5949 /* OP_REG28 matcher. */
5952 match_reg28_operand (struct mips_arg_info
*arg
)
5956 if (arg
->token
->type
== OT_REG
5957 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
5966 /* OP_NON_ZERO_REG matcher. */
5969 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5970 const struct mips_operand
*operand
)
5974 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5980 arg
->last_regno
= regno
;
5981 insn_insert_operand (arg
->insn
, operand
, regno
);
5985 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5986 register that we need to match. */
5989 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5993 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5996 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
5997 LENGTH is the length of the value in bytes (4 for float, 8 for double)
5998 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6000 Return the constant in IMM and OFFSET as follows:
6002 - If the constant should be loaded via memory, set IMM to O_absent and
6003 OFFSET to the memory address.
6005 - Otherwise, if the constant should be loaded into two 32-bit registers,
6006 set IMM to the O_constant to load into the high register and OFFSET
6007 to the corresponding value for the low register.
6009 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6011 These constants only appear as the last operand in an instruction,
6012 and every instruction that accepts them in any variant accepts them
6013 in all variants. This means we don't have to worry about backing out
6014 any changes if the instruction does not match. We just match
6015 unconditionally and report an error if the constant is invalid. */
6018 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6019 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6024 const char *newname
;
6025 unsigned char *data
;
6027 /* Where the constant is placed is based on how the MIPS assembler
6030 length == 4 && using_gprs -- immediate value only
6031 length == 8 && using_gprs -- .rdata or immediate value
6032 length == 4 && !using_gprs -- .lit4 or immediate value
6033 length == 8 && !using_gprs -- .lit8 or immediate value
6035 The .lit4 and .lit8 sections are only used if permitted by the
6037 if (arg
->token
->type
!= OT_FLOAT
)
6039 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6043 gas_assert (arg
->token
->u
.flt
.length
== length
);
6044 data
= arg
->token
->u
.flt
.data
;
6047 /* Handle 32-bit constants for which an immediate value is best. */
6050 || g_switch_value
< 4
6051 || (data
[0] == 0 && data
[1] == 0)
6052 || (data
[2] == 0 && data
[3] == 0)))
6054 imm
->X_op
= O_constant
;
6055 if (!target_big_endian
)
6056 imm
->X_add_number
= bfd_getl32 (data
);
6058 imm
->X_add_number
= bfd_getb32 (data
);
6059 offset
->X_op
= O_absent
;
6063 /* Handle 64-bit constants for which an immediate value is best. */
6065 && !mips_disable_float_construction
6066 /* Constants can only be constructed in GPRs and copied to FPRs if the
6067 GPRs are at least as wide as the FPRs or MTHC1 is available.
6068 Unlike most tests for 32-bit floating-point registers this check
6069 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6070 permit 64-bit moves without MXHC1.
6071 Force the constant into memory otherwise. */
6074 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6076 && ((data
[0] == 0 && data
[1] == 0)
6077 || (data
[2] == 0 && data
[3] == 0))
6078 && ((data
[4] == 0 && data
[5] == 0)
6079 || (data
[6] == 0 && data
[7] == 0)))
6081 /* The value is simple enough to load with a couple of instructions.
6082 If using 32-bit registers, set IMM to the high order 32 bits and
6083 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6085 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6087 imm
->X_op
= O_constant
;
6088 offset
->X_op
= O_constant
;
6089 if (!target_big_endian
)
6091 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6092 offset
->X_add_number
= bfd_getl32 (data
);
6096 imm
->X_add_number
= bfd_getb32 (data
);
6097 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6099 if (offset
->X_add_number
== 0)
6100 offset
->X_op
= O_absent
;
6104 imm
->X_op
= O_constant
;
6105 if (!target_big_endian
)
6106 imm
->X_add_number
= bfd_getl64 (data
);
6108 imm
->X_add_number
= bfd_getb64 (data
);
6109 offset
->X_op
= O_absent
;
6114 /* Switch to the right section. */
6116 subseg
= now_subseg
;
6119 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6124 if (using_gprs
|| g_switch_value
< 8)
6125 newname
= RDATA_SECTION_NAME
;
6130 new_seg
= subseg_new (newname
, (subsegT
) 0);
6131 bfd_set_section_flags (stdoutput
, new_seg
,
6132 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6133 frag_align (length
== 4 ? 2 : 3, 0, 0);
6134 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6135 record_alignment (new_seg
, 4);
6137 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6139 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6141 /* Set the argument to the current address in the section. */
6142 imm
->X_op
= O_absent
;
6143 offset
->X_op
= O_symbol
;
6144 offset
->X_add_symbol
= symbol_temp_new_now ();
6145 offset
->X_add_number
= 0;
6147 /* Put the floating point number into the section. */
6148 p
= frag_more (length
);
6149 memcpy (p
, data
, length
);
6151 /* Switch back to the original section. */
6152 subseg_set (seg
, subseg
);
6156 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6160 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6161 const struct mips_operand
*operand
,
6162 bfd_boolean match_p
)
6166 /* The operand can be an XYZW mask or a single 2-bit channel index
6167 (with X being 0). */
6168 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6170 /* The suffix can be omitted when it is already part of the opcode. */
6171 if (arg
->token
->type
!= OT_CHANNELS
)
6174 uval
= arg
->token
->u
.channels
;
6175 if (operand
->size
== 2)
6177 /* Check that a single bit is set and convert it into a 2-bit index. */
6178 if ((uval
& -uval
) != uval
)
6180 uval
= 4 - ffs (uval
);
6183 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6188 insn_insert_operand (arg
->insn
, operand
, uval
);
6192 /* Try to match a token from ARG against OPERAND. Consume the token
6193 and return true on success, otherwise return false. */
6196 match_operand (struct mips_arg_info
*arg
,
6197 const struct mips_operand
*operand
)
6199 switch (operand
->type
)
6202 return match_int_operand (arg
, operand
);
6205 return match_mapped_int_operand (arg
, operand
);
6208 return match_msb_operand (arg
, operand
);
6211 case OP_OPTIONAL_REG
:
6212 return match_reg_operand (arg
, operand
);
6215 return match_reg_pair_operand (arg
, operand
);
6218 return match_pcrel_operand (arg
);
6221 return match_perf_reg_operand (arg
, operand
);
6223 case OP_ADDIUSP_INT
:
6224 return match_addiusp_operand (arg
, operand
);
6226 case OP_CLO_CLZ_DEST
:
6227 return match_clo_clz_dest_operand (arg
, operand
);
6229 case OP_LWM_SWM_LIST
:
6230 return match_lwm_swm_list_operand (arg
, operand
);
6232 case OP_ENTRY_EXIT_LIST
:
6233 return match_entry_exit_operand (arg
, operand
);
6235 case OP_SAVE_RESTORE_LIST
:
6236 return match_save_restore_list_operand (arg
);
6238 case OP_MDMX_IMM_REG
:
6239 return match_mdmx_imm_reg_operand (arg
, operand
);
6241 case OP_REPEAT_DEST_REG
:
6242 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6244 case OP_REPEAT_PREV_REG
:
6245 return match_tied_reg_operand (arg
, arg
->last_regno
);
6248 return match_pc_operand (arg
);
6251 return match_reg28_operand (arg
);
6254 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6256 case OP_VU0_MATCH_SUFFIX
:
6257 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6260 return match_imm_index_operand (arg
, operand
);
6263 return match_reg_index_operand (arg
, operand
);
6266 return match_same_rs_rt_operand (arg
, operand
);
6269 return match_check_prev_operand (arg
, operand
);
6271 case OP_NON_ZERO_REG
:
6272 return match_non_zero_reg_operand (arg
, operand
);
6277 /* ARG is the state after successfully matching an instruction.
6278 Issue any queued-up warnings. */
6281 check_completed_insn (struct mips_arg_info
*arg
)
6286 as_warn (_("used $at without \".set noat\""));
6288 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6292 /* Return true if modifying general-purpose register REG needs a delay. */
6295 reg_needs_delay (unsigned int reg
)
6297 unsigned long prev_pinfo
;
6299 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6300 if (!mips_opts
.noreorder
6301 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6302 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6303 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6309 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6310 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6311 by VR4120 errata. */
6314 classify_vr4120_insn (const char *name
)
6316 if (strncmp (name
, "macc", 4) == 0)
6317 return FIX_VR4120_MACC
;
6318 if (strncmp (name
, "dmacc", 5) == 0)
6319 return FIX_VR4120_DMACC
;
6320 if (strncmp (name
, "mult", 4) == 0)
6321 return FIX_VR4120_MULT
;
6322 if (strncmp (name
, "dmult", 5) == 0)
6323 return FIX_VR4120_DMULT
;
6324 if (strstr (name
, "div"))
6325 return FIX_VR4120_DIV
;
6326 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6327 return FIX_VR4120_MTHILO
;
6328 return NUM_FIX_VR4120_CLASSES
;
6331 #define INSN_ERET 0x42000018
6332 #define INSN_DERET 0x4200001f
6333 #define INSN_DMULT 0x1c
6334 #define INSN_DMULTU 0x1d
6336 /* Return the number of instructions that must separate INSN1 and INSN2,
6337 where INSN1 is the earlier instruction. Return the worst-case value
6338 for any INSN2 if INSN2 is null. */
6341 insns_between (const struct mips_cl_insn
*insn1
,
6342 const struct mips_cl_insn
*insn2
)
6344 unsigned long pinfo1
, pinfo2
;
6347 /* If INFO2 is null, pessimistically assume that all flags are set for
6348 the second instruction. */
6349 pinfo1
= insn1
->insn_mo
->pinfo
;
6350 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6352 /* For most targets, write-after-read dependencies on the HI and LO
6353 registers must be separated by at least two instructions. */
6354 if (!hilo_interlocks
)
6356 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6358 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6362 /* If we're working around r7000 errata, there must be two instructions
6363 between an mfhi or mflo and any instruction that uses the result. */
6364 if (mips_7000_hilo_fix
6365 && !mips_opts
.micromips
6366 && MF_HILO_INSN (pinfo1
)
6367 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6370 /* If we're working around 24K errata, one instruction is required
6371 if an ERET or DERET is followed by a branch instruction. */
6372 if (mips_fix_24k
&& !mips_opts
.micromips
)
6374 if (insn1
->insn_opcode
== INSN_ERET
6375 || insn1
->insn_opcode
== INSN_DERET
)
6378 || insn2
->insn_opcode
== INSN_ERET
6379 || insn2
->insn_opcode
== INSN_DERET
6380 || delayed_branch_p (insn2
))
6385 /* If we're working around PMC RM7000 errata, there must be three
6386 nops between a dmult and a load instruction. */
6387 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6389 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6390 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6392 if (pinfo2
& INSN_LOAD_MEMORY
)
6397 /* If working around VR4120 errata, check for combinations that need
6398 a single intervening instruction. */
6399 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6401 unsigned int class1
, class2
;
6403 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6404 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6408 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6409 if (vr4120_conflicts
[class1
] & (1 << class2
))
6414 if (!HAVE_CODE_COMPRESSION
)
6416 /* Check for GPR or coprocessor load delays. All such delays
6417 are on the RT register. */
6418 /* Itbl support may require additional care here. */
6419 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6420 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6422 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6426 /* Check for generic coprocessor hazards.
6428 This case is not handled very well. There is no special
6429 knowledge of CP0 handling, and the coprocessors other than
6430 the floating point unit are not distinguished at all. */
6431 /* Itbl support may require additional care here. FIXME!
6432 Need to modify this to include knowledge about
6433 user specified delays! */
6434 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6435 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6437 /* Handle cases where INSN1 writes to a known general coprocessor
6438 register. There must be a one instruction delay before INSN2
6439 if INSN2 reads that register, otherwise no delay is needed. */
6440 mask
= fpr_write_mask (insn1
);
6443 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6448 /* Read-after-write dependencies on the control registers
6449 require a two-instruction gap. */
6450 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6451 && (pinfo2
& INSN_READ_COND_CODE
))
6454 /* We don't know exactly what INSN1 does. If INSN2 is
6455 also a coprocessor instruction, assume there must be
6456 a one instruction gap. */
6457 if (pinfo2
& INSN_COP
)
6462 /* Check for read-after-write dependencies on the coprocessor
6463 control registers in cases where INSN1 does not need a general
6464 coprocessor delay. This means that INSN1 is a floating point
6465 comparison instruction. */
6466 /* Itbl support may require additional care here. */
6467 else if (!cop_interlocks
6468 && (pinfo1
& INSN_WRITE_COND_CODE
)
6469 && (pinfo2
& INSN_READ_COND_CODE
))
6473 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6474 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6476 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6477 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6478 || (insn2
&& delayed_branch_p (insn2
))))
6484 /* Return the number of nops that would be needed to work around the
6485 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6486 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6487 that are contained within the first IGNORE instructions of HIST. */
6490 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6491 const struct mips_cl_insn
*insn
)
6496 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6497 are not affected by the errata. */
6499 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6500 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6501 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6504 /* Search for the first MFLO or MFHI. */
6505 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6506 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6508 /* Extract the destination register. */
6509 mask
= gpr_write_mask (&hist
[i
]);
6511 /* No nops are needed if INSN reads that register. */
6512 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6515 /* ...or if any of the intervening instructions do. */
6516 for (j
= 0; j
< i
; j
++)
6517 if (gpr_read_mask (&hist
[j
]) & mask
)
6521 return MAX_VR4130_NOPS
- i
;
6526 #define BASE_REG_EQ(INSN1, INSN2) \
6527 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6528 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6530 /* Return the minimum alignment for this store instruction. */
6533 fix_24k_align_to (const struct mips_opcode
*mo
)
6535 if (strcmp (mo
->name
, "sh") == 0)
6538 if (strcmp (mo
->name
, "swc1") == 0
6539 || strcmp (mo
->name
, "swc2") == 0
6540 || strcmp (mo
->name
, "sw") == 0
6541 || strcmp (mo
->name
, "sc") == 0
6542 || strcmp (mo
->name
, "s.s") == 0)
6545 if (strcmp (mo
->name
, "sdc1") == 0
6546 || strcmp (mo
->name
, "sdc2") == 0
6547 || strcmp (mo
->name
, "s.d") == 0)
6554 struct fix_24k_store_info
6556 /* Immediate offset, if any, for this store instruction. */
6558 /* Alignment required by this store instruction. */
6560 /* True for register offsets. */
6561 int register_offset
;
6564 /* Comparison function used by qsort. */
6567 fix_24k_sort (const void *a
, const void *b
)
6569 const struct fix_24k_store_info
*pos1
= a
;
6570 const struct fix_24k_store_info
*pos2
= b
;
6572 return (pos1
->off
- pos2
->off
);
6575 /* INSN is a store instruction. Try to record the store information
6576 in STINFO. Return false if the information isn't known. */
6579 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6580 const struct mips_cl_insn
*insn
)
6582 /* The instruction must have a known offset. */
6583 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6586 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6587 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6591 /* Return the number of nops that would be needed to work around the 24k
6592 "lost data on stores during refill" errata if instruction INSN
6593 immediately followed the 2 instructions described by HIST.
6594 Ignore hazards that are contained within the first IGNORE
6595 instructions of HIST.
6597 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6598 for the data cache refills and store data. The following describes
6599 the scenario where the store data could be lost.
6601 * A data cache miss, due to either a load or a store, causing fill
6602 data to be supplied by the memory subsystem
6603 * The first three doublewords of fill data are returned and written
6605 * A sequence of four stores occurs in consecutive cycles around the
6606 final doubleword of the fill:
6610 * Zero, One or more instructions
6613 The four stores A-D must be to different doublewords of the line that
6614 is being filled. The fourth instruction in the sequence above permits
6615 the fill of the final doubleword to be transferred from the FSB into
6616 the cache. In the sequence above, the stores may be either integer
6617 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6618 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6619 different doublewords on the line. If the floating point unit is
6620 running in 1:2 mode, it is not possible to create the sequence above
6621 using only floating point store instructions.
6623 In this case, the cache line being filled is incorrectly marked
6624 invalid, thereby losing the data from any store to the line that
6625 occurs between the original miss and the completion of the five
6626 cycle sequence shown above.
6628 The workarounds are:
6630 * Run the data cache in write-through mode.
6631 * Insert a non-store instruction between
6632 Store A and Store B or Store B and Store C. */
6635 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6636 const struct mips_cl_insn
*insn
)
6638 struct fix_24k_store_info pos
[3];
6639 int align
, i
, base_offset
;
6644 /* If the previous instruction wasn't a store, there's nothing to
6646 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6649 /* If the instructions after the previous one are unknown, we have
6650 to assume the worst. */
6654 /* Check whether we are dealing with three consecutive stores. */
6655 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6656 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6659 /* If we don't know the relationship between the store addresses,
6660 assume the worst. */
6661 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6662 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6665 if (!fix_24k_record_store_info (&pos
[0], insn
)
6666 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6667 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6670 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6672 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6673 X bytes and such that the base register + X is known to be aligned
6676 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6680 align
= pos
[0].align_to
;
6681 base_offset
= pos
[0].off
;
6682 for (i
= 1; i
< 3; i
++)
6683 if (align
< pos
[i
].align_to
)
6685 align
= pos
[i
].align_to
;
6686 base_offset
= pos
[i
].off
;
6688 for (i
= 0; i
< 3; i
++)
6689 pos
[i
].off
-= base_offset
;
6692 pos
[0].off
&= ~align
+ 1;
6693 pos
[1].off
&= ~align
+ 1;
6694 pos
[2].off
&= ~align
+ 1;
6696 /* If any two stores write to the same chunk, they also write to the
6697 same doubleword. The offsets are still sorted at this point. */
6698 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6701 /* A range of at least 9 bytes is needed for the stores to be in
6702 non-overlapping doublewords. */
6703 if (pos
[2].off
- pos
[0].off
<= 8)
6706 if (pos
[2].off
- pos
[1].off
>= 24
6707 || pos
[1].off
- pos
[0].off
>= 24
6708 || pos
[2].off
- pos
[0].off
>= 32)
6714 /* Return the number of nops that would be needed if instruction INSN
6715 immediately followed the MAX_NOPS instructions given by HIST,
6716 where HIST[0] is the most recent instruction. Ignore hazards
6717 between INSN and the first IGNORE instructions in HIST.
6719 If INSN is null, return the worse-case number of nops for any
6723 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6724 const struct mips_cl_insn
*insn
)
6726 int i
, nops
, tmp_nops
;
6729 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6731 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6732 if (tmp_nops
> nops
)
6736 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6738 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6739 if (tmp_nops
> nops
)
6743 if (mips_fix_24k
&& !mips_opts
.micromips
)
6745 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6746 if (tmp_nops
> nops
)
6753 /* The variable arguments provide NUM_INSNS extra instructions that
6754 might be added to HIST. Return the largest number of nops that
6755 would be needed after the extended sequence, ignoring hazards
6756 in the first IGNORE instructions. */
6759 nops_for_sequence (int num_insns
, int ignore
,
6760 const struct mips_cl_insn
*hist
, ...)
6763 struct mips_cl_insn buffer
[MAX_NOPS
];
6764 struct mips_cl_insn
*cursor
;
6767 va_start (args
, hist
);
6768 cursor
= buffer
+ num_insns
;
6769 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6770 while (cursor
> buffer
)
6771 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6773 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6778 /* Like nops_for_insn, but if INSN is a branch, take into account the
6779 worst-case delay for the branch target. */
6782 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6783 const struct mips_cl_insn
*insn
)
6787 nops
= nops_for_insn (ignore
, hist
, insn
);
6788 if (delayed_branch_p (insn
))
6790 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6791 hist
, insn
, get_delay_slot_nop (insn
));
6792 if (tmp_nops
> nops
)
6795 else if (compact_branch_p (insn
))
6797 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6798 if (tmp_nops
> nops
)
6804 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6807 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6809 gas_assert (!HAVE_CODE_COMPRESSION
);
6810 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6811 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6814 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6815 jr target pc &= 'hffff_ffff_cfff_ffff. */
6818 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6820 gas_assert (!HAVE_CODE_COMPRESSION
);
6821 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6822 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6823 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6831 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6832 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6835 ep
.X_op
= O_constant
;
6836 ep
.X_add_number
= 0xcfff0000;
6837 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6838 ep
.X_add_number
= 0xffff;
6839 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6840 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6845 fix_loongson2f (struct mips_cl_insn
* ip
)
6847 if (mips_fix_loongson2f_nop
)
6848 fix_loongson2f_nop (ip
);
6850 if (mips_fix_loongson2f_jump
)
6851 fix_loongson2f_jump (ip
);
6854 /* IP is a branch that has a delay slot, and we need to fill it
6855 automatically. Return true if we can do that by swapping IP
6856 with the previous instruction.
6857 ADDRESS_EXPR is an operand of the instruction to be used with
6861 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6862 bfd_reloc_code_real_type
*reloc_type
)
6864 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6865 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6866 unsigned int fpr_read
, prev_fpr_write
;
6868 /* -O2 and above is required for this optimization. */
6869 if (mips_optimize
< 2)
6872 /* If we have seen .set volatile or .set nomove, don't optimize. */
6873 if (mips_opts
.nomove
)
6876 /* We can't swap if the previous instruction's position is fixed. */
6877 if (history
[0].fixed_p
)
6880 /* If the previous previous insn was in a .set noreorder, we can't
6881 swap. Actually, the MIPS assembler will swap in this situation.
6882 However, gcc configured -with-gnu-as will generate code like
6890 in which we can not swap the bne and INSN. If gcc is not configured
6891 -with-gnu-as, it does not output the .set pseudo-ops. */
6892 if (history
[1].noreorder_p
)
6895 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6896 This means that the previous instruction was a 4-byte one anyhow. */
6897 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6900 /* If the branch is itself the target of a branch, we can not swap.
6901 We cheat on this; all we check for is whether there is a label on
6902 this instruction. If there are any branches to anything other than
6903 a label, users must use .set noreorder. */
6904 if (seg_info (now_seg
)->label_list
)
6907 /* If the previous instruction is in a variant frag other than this
6908 branch's one, we cannot do the swap. This does not apply to
6909 MIPS16 code, which uses variant frags for different purposes. */
6910 if (!mips_opts
.mips16
6912 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6915 /* We do not swap with instructions that cannot architecturally
6916 be placed in a branch delay slot, such as SYNC or ERET. We
6917 also refrain from swapping with a trap instruction, since it
6918 complicates trap handlers to have the trap instruction be in
6920 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6921 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6924 /* Check for conflicts between the branch and the instructions
6925 before the candidate delay slot. */
6926 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6929 /* Check for conflicts between the swapped sequence and the
6930 target of the branch. */
6931 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6934 /* If the branch reads a register that the previous
6935 instruction sets, we can not swap. */
6936 gpr_read
= gpr_read_mask (ip
);
6937 prev_gpr_write
= gpr_write_mask (&history
[0]);
6938 if (gpr_read
& prev_gpr_write
)
6941 fpr_read
= fpr_read_mask (ip
);
6942 prev_fpr_write
= fpr_write_mask (&history
[0]);
6943 if (fpr_read
& prev_fpr_write
)
6946 /* If the branch writes a register that the previous
6947 instruction sets, we can not swap. */
6948 gpr_write
= gpr_write_mask (ip
);
6949 if (gpr_write
& prev_gpr_write
)
6952 /* If the branch writes a register that the previous
6953 instruction reads, we can not swap. */
6954 prev_gpr_read
= gpr_read_mask (&history
[0]);
6955 if (gpr_write
& prev_gpr_read
)
6958 /* If one instruction sets a condition code and the
6959 other one uses a condition code, we can not swap. */
6960 pinfo
= ip
->insn_mo
->pinfo
;
6961 if ((pinfo
& INSN_READ_COND_CODE
)
6962 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6964 if ((pinfo
& INSN_WRITE_COND_CODE
)
6965 && (prev_pinfo
& INSN_READ_COND_CODE
))
6968 /* If the previous instruction uses the PC, we can not swap. */
6969 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6970 if (prev_pinfo2
& INSN2_READ_PC
)
6973 /* If the previous instruction has an incorrect size for a fixed
6974 branch delay slot in microMIPS mode, we cannot swap. */
6975 pinfo2
= ip
->insn_mo
->pinfo2
;
6976 if (mips_opts
.micromips
6977 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6978 && insn_length (history
) != 2)
6980 if (mips_opts
.micromips
6981 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6982 && insn_length (history
) != 4)
6985 /* On the R5900 short loops need to be fixed by inserting a NOP in the
6988 The short loop bug under certain conditions causes loops to execute
6989 only once or twice. We must ensure that the assembler never
6990 generates loops that satisfy all of the following conditions:
6992 - a loop consists of less than or equal to six instructions
6993 (including the branch delay slot);
6994 - a loop contains only one conditional branch instruction at the end
6996 - a loop does not contain any other branch or jump instructions;
6997 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
6999 We need to do this because of a hardware bug in the R5900 chip. */
7000 if (mips_opts
.arch
== CPU_R5900
7001 /* Check if instruction has a parameter, ignore "j $31". */
7002 && (address_expr
!= NULL
)
7003 /* Parameter must be 16 bit. */
7004 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7005 /* Branch to same segment. */
7006 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7007 /* Branch to same code fragment. */
7008 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7009 /* Can only calculate branch offset if value is known. */
7010 && symbol_constant_p (address_expr
->X_add_symbol
)
7011 /* Check if branch is really conditional. */
7012 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7013 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7014 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7017 /* Check if loop is shorter than or equal to 6 instructions
7018 including branch and delay slot. */
7019 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7026 /* When the loop includes branches or jumps,
7027 it is not a short loop. */
7028 for (i
= 0; i
< (distance
/ 4); i
++)
7030 if ((history
[i
].cleared_p
)
7031 || delayed_branch_p (&history
[i
]))
7039 /* Insert nop after branch to fix short loop. */
7048 /* Decide how we should add IP to the instruction stream.
7049 ADDRESS_EXPR is an operand of the instruction to be used with
7052 static enum append_method
7053 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7054 bfd_reloc_code_real_type
*reloc_type
)
7056 /* The relaxed version of a macro sequence must be inherently
7058 if (mips_relax
.sequence
== 2)
7061 /* We must not dabble with instructions in a ".set noreorder" block. */
7062 if (mips_opts
.noreorder
)
7065 /* Otherwise, it's our responsibility to fill branch delay slots. */
7066 if (delayed_branch_p (ip
))
7068 if (!branch_likely_p (ip
)
7069 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7072 if (mips_opts
.mips16
7073 && ISA_SUPPORTS_MIPS16E
7074 && gpr_read_mask (ip
) != 0)
7075 return APPEND_ADD_COMPACT
;
7077 if (mips_opts
.micromips
7078 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7079 || (!forced_insn_length
7080 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7081 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7082 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7083 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7084 return APPEND_ADD_COMPACT
;
7086 return APPEND_ADD_WITH_NOP
;
7092 /* IP is an instruction whose opcode we have just changed, END points
7093 to the end of the opcode table processed. Point IP->insn_mo to the
7094 new opcode's definition. */
7097 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7099 const struct mips_opcode
*mo
;
7101 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7102 if (mo
->pinfo
!= INSN_MACRO
7103 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7111 /* IP is a MIPS16 instruction whose opcode we have just changed.
7112 Point IP->insn_mo to the new opcode's definition. */
7115 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7117 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7120 /* IP is a microMIPS instruction whose opcode we have just changed.
7121 Point IP->insn_mo to the new opcode's definition. */
7124 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7126 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7129 /* For microMIPS macros, we need to generate a local number label
7130 as the target of branches. */
7131 #define MICROMIPS_LABEL_CHAR '\037'
7132 static unsigned long micromips_target_label
;
7133 static char micromips_target_name
[32];
7136 micromips_label_name (void)
7138 char *p
= micromips_target_name
;
7139 char symbol_name_temporary
[24];
7147 l
= micromips_target_label
;
7148 #ifdef LOCAL_LABEL_PREFIX
7149 *p
++ = LOCAL_LABEL_PREFIX
;
7152 *p
++ = MICROMIPS_LABEL_CHAR
;
7155 symbol_name_temporary
[i
++] = l
% 10 + '0';
7160 *p
++ = symbol_name_temporary
[--i
];
7163 return micromips_target_name
;
7167 micromips_label_expr (expressionS
*label_expr
)
7169 label_expr
->X_op
= O_symbol
;
7170 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7171 label_expr
->X_add_number
= 0;
7175 micromips_label_inc (void)
7177 micromips_target_label
++;
7178 *micromips_target_name
= '\0';
7182 micromips_add_label (void)
7186 s
= colon (micromips_label_name ());
7187 micromips_label_inc ();
7188 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7191 /* If assembling microMIPS code, then return the microMIPS reloc
7192 corresponding to the requested one if any. Otherwise return
7193 the reloc unchanged. */
7195 static bfd_reloc_code_real_type
7196 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7198 static const bfd_reloc_code_real_type relocs
[][2] =
7200 /* Keep sorted incrementally by the left-hand key. */
7201 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7202 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7203 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7204 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7205 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7206 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7207 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7208 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7209 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7210 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7211 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7212 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7213 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7214 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7215 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7216 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7217 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7218 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7219 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7220 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7221 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7222 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7223 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7224 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7225 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7226 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7227 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7229 bfd_reloc_code_real_type r
;
7232 if (!mips_opts
.micromips
)
7234 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7240 return relocs
[i
][1];
7245 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7246 Return true on success, storing the resolved value in RESULT. */
7249 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7254 case BFD_RELOC_MIPS_HIGHEST
:
7255 case BFD_RELOC_MICROMIPS_HIGHEST
:
7256 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7259 case BFD_RELOC_MIPS_HIGHER
:
7260 case BFD_RELOC_MICROMIPS_HIGHER
:
7261 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7264 case BFD_RELOC_HI16_S
:
7265 case BFD_RELOC_HI16_S_PCREL
:
7266 case BFD_RELOC_MICROMIPS_HI16_S
:
7267 case BFD_RELOC_MIPS16_HI16_S
:
7268 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7271 case BFD_RELOC_HI16
:
7272 case BFD_RELOC_MICROMIPS_HI16
:
7273 case BFD_RELOC_MIPS16_HI16
:
7274 *result
= (operand
>> 16) & 0xffff;
7277 case BFD_RELOC_LO16
:
7278 case BFD_RELOC_LO16_PCREL
:
7279 case BFD_RELOC_MICROMIPS_LO16
:
7280 case BFD_RELOC_MIPS16_LO16
:
7281 *result
= operand
& 0xffff;
7284 case BFD_RELOC_UNUSED
:
7293 /* Output an instruction. IP is the instruction information.
7294 ADDRESS_EXPR is an operand of the instruction to be used with
7295 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7296 a macro expansion. */
7299 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7300 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7302 unsigned long prev_pinfo2
, pinfo
;
7303 bfd_boolean relaxed_branch
= FALSE
;
7304 enum append_method method
;
7305 bfd_boolean relax32
;
7308 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7309 fix_loongson2f (ip
);
7311 file_ase_mips16
|= mips_opts
.mips16
;
7312 file_ase_micromips
|= mips_opts
.micromips
;
7314 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7315 pinfo
= ip
->insn_mo
->pinfo
;
7317 /* Don't raise alarm about `nods' frags as they'll fill in the right
7318 kind of nop in relaxation if required. */
7319 if (mips_opts
.micromips
7321 && !(history
[0].frag
7322 && history
[0].frag
->fr_type
== rs_machine_dependent
7323 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7324 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7325 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7326 && micromips_insn_length (ip
->insn_mo
) != 2)
7327 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7328 && micromips_insn_length (ip
->insn_mo
) != 4)))
7329 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7330 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7332 if (address_expr
== NULL
)
7334 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7335 && reloc_type
[1] == BFD_RELOC_UNUSED
7336 && reloc_type
[2] == BFD_RELOC_UNUSED
7337 && address_expr
->X_op
== O_constant
)
7339 switch (*reloc_type
)
7341 case BFD_RELOC_MIPS_JMP
:
7345 /* Shift is 2, unusually, for microMIPS JALX. */
7346 shift
= (mips_opts
.micromips
7347 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7348 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7349 as_bad (_("jump to misaligned address (0x%lx)"),
7350 (unsigned long) address_expr
->X_add_number
);
7351 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7357 case BFD_RELOC_MIPS16_JMP
:
7358 if ((address_expr
->X_add_number
& 3) != 0)
7359 as_bad (_("jump to misaligned address (0x%lx)"),
7360 (unsigned long) address_expr
->X_add_number
);
7362 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7363 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7364 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7368 case BFD_RELOC_16_PCREL_S2
:
7372 shift
= mips_opts
.micromips
? 1 : 2;
7373 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7374 as_bad (_("branch to misaligned address (0x%lx)"),
7375 (unsigned long) address_expr
->X_add_number
);
7376 if (!mips_relax_branch
)
7378 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7379 & ~((1 << (shift
+ 16)) - 1))
7380 as_bad (_("branch address range overflow (0x%lx)"),
7381 (unsigned long) address_expr
->X_add_number
);
7382 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7388 case BFD_RELOC_MIPS_21_PCREL_S2
:
7393 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7394 as_bad (_("branch to misaligned address (0x%lx)"),
7395 (unsigned long) address_expr
->X_add_number
);
7396 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7397 & ~((1 << (shift
+ 21)) - 1))
7398 as_bad (_("branch address range overflow (0x%lx)"),
7399 (unsigned long) address_expr
->X_add_number
);
7400 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7405 case BFD_RELOC_MIPS_26_PCREL_S2
:
7410 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7411 as_bad (_("branch to misaligned address (0x%lx)"),
7412 (unsigned long) address_expr
->X_add_number
);
7413 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7414 & ~((1 << (shift
+ 26)) - 1))
7415 as_bad (_("branch address range overflow (0x%lx)"),
7416 (unsigned long) address_expr
->X_add_number
);
7417 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7426 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7429 ip
->insn_opcode
|= value
& 0xffff;
7437 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7439 /* There are a lot of optimizations we could do that we don't.
7440 In particular, we do not, in general, reorder instructions.
7441 If you use gcc with optimization, it will reorder
7442 instructions and generally do much more optimization then we
7443 do here; repeating all that work in the assembler would only
7444 benefit hand written assembly code, and does not seem worth
7446 int nops
= (mips_optimize
== 0
7447 ? nops_for_insn (0, history
, NULL
)
7448 : nops_for_insn_or_target (0, history
, ip
));
7452 unsigned long old_frag_offset
;
7455 old_frag
= frag_now
;
7456 old_frag_offset
= frag_now_fix ();
7458 for (i
= 0; i
< nops
; i
++)
7459 add_fixed_insn (NOP_INSN
);
7460 insert_into_history (0, nops
, NOP_INSN
);
7464 listing_prev_line ();
7465 /* We may be at the start of a variant frag. In case we
7466 are, make sure there is enough space for the frag
7467 after the frags created by listing_prev_line. The
7468 argument to frag_grow here must be at least as large
7469 as the argument to all other calls to frag_grow in
7470 this file. We don't have to worry about being in the
7471 middle of a variant frag, because the variants insert
7472 all needed nop instructions themselves. */
7476 mips_move_text_labels ();
7478 #ifndef NO_ECOFF_DEBUGGING
7479 if (ECOFF_DEBUGGING
)
7480 ecoff_fix_loc (old_frag
, old_frag_offset
);
7484 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7488 /* Work out how many nops in prev_nop_frag are needed by IP,
7489 ignoring hazards generated by the first prev_nop_frag_since
7491 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7492 gas_assert (nops
<= prev_nop_frag_holds
);
7494 /* Enforce NOPS as a minimum. */
7495 if (nops
> prev_nop_frag_required
)
7496 prev_nop_frag_required
= nops
;
7498 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7500 /* Settle for the current number of nops. Update the history
7501 accordingly (for the benefit of any future .set reorder code). */
7502 prev_nop_frag
= NULL
;
7503 insert_into_history (prev_nop_frag_since
,
7504 prev_nop_frag_holds
, NOP_INSN
);
7508 /* Allow this instruction to replace one of the nops that was
7509 tentatively added to prev_nop_frag. */
7510 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7511 prev_nop_frag_holds
--;
7512 prev_nop_frag_since
++;
7516 method
= get_append_method (ip
, address_expr
, reloc_type
);
7517 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7519 dwarf2_emit_insn (0);
7520 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7521 so "move" the instruction address accordingly.
7523 Also, it doesn't seem appropriate for the assembler to reorder .loc
7524 entries. If this instruction is a branch that we are going to swap
7525 with the previous instruction, the two instructions should be
7526 treated as a unit, and the debug information for both instructions
7527 should refer to the start of the branch sequence. Using the
7528 current position is certainly wrong when swapping a 32-bit branch
7529 and a 16-bit delay slot, since the current position would then be
7530 in the middle of a branch. */
7531 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7533 relax32
= (mips_relax_branch
7534 /* Don't try branch relaxation within .set nomacro, or within
7535 .set noat if we use $at for PIC computations. If it turns
7536 out that the branch was out-of-range, we'll get an error. */
7537 && !mips_opts
.warn_about_macros
7538 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7539 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7540 as they have no complementing branches. */
7541 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7543 if (!HAVE_CODE_COMPRESSION
7546 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7547 && delayed_branch_p (ip
))
7549 relaxed_branch
= TRUE
;
7550 add_relaxed_insn (ip
, (relaxed_branch_length
7552 uncond_branch_p (ip
) ? -1
7553 : branch_likely_p (ip
) ? 1
7556 (AT
, mips_pic
!= NO_PIC
,
7557 uncond_branch_p (ip
),
7558 branch_likely_p (ip
),
7559 pinfo
& INSN_WRITE_GPR_31
,
7561 address_expr
->X_add_symbol
,
7562 address_expr
->X_add_number
);
7563 *reloc_type
= BFD_RELOC_UNUSED
;
7565 else if (mips_opts
.micromips
7567 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7568 || *reloc_type
> BFD_RELOC_UNUSED
)
7569 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7570 /* Don't try branch relaxation when users specify
7571 16-bit/32-bit instructions. */
7572 && !forced_insn_length
)
7574 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7575 && *reloc_type
> BFD_RELOC_UNUSED
);
7576 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7577 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7578 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7579 int nods
= method
== APPEND_ADD_WITH_NOP
;
7580 int al
= pinfo
& INSN_WRITE_GPR_31
;
7581 int length32
= nods
? 8 : 4;
7583 gas_assert (address_expr
!= NULL
);
7584 gas_assert (!mips_relax
.sequence
);
7586 relaxed_branch
= TRUE
;
7588 method
= APPEND_ADD
;
7590 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7591 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7592 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7594 uncond
, compact
, al
, nods
,
7596 address_expr
->X_add_symbol
,
7597 address_expr
->X_add_number
);
7598 *reloc_type
= BFD_RELOC_UNUSED
;
7600 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7602 bfd_boolean require_unextended
;
7603 bfd_boolean require_extended
;
7607 if (forced_insn_length
!= 0)
7609 require_unextended
= forced_insn_length
== 2;
7610 require_extended
= forced_insn_length
== 4;
7614 require_unextended
= (mips_opts
.noautoextend
7615 && !mips_opcode_32bit_p (ip
->insn_mo
));
7616 require_extended
= 0;
7619 /* We need to set up a variant frag. */
7620 gas_assert (address_expr
!= NULL
);
7621 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7622 symbol created by `make_expr_symbol' may not get a necessary
7623 external relocation produced. */
7624 if (address_expr
->X_op
== O_symbol
)
7626 symbol
= address_expr
->X_add_symbol
;
7627 offset
= address_expr
->X_add_number
;
7631 symbol
= make_expr_symbol (address_expr
);
7632 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7635 add_relaxed_insn (ip
, 12, 0,
7637 (*reloc_type
- BFD_RELOC_UNUSED
,
7638 mips_opts
.ase
& ASE_MIPS16E2
,
7641 mips_opts
.warn_about_macros
,
7642 require_unextended
, require_extended
,
7643 delayed_branch_p (&history
[0]),
7644 history
[0].mips16_absolute_jump_p
),
7647 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7649 if (!delayed_branch_p (ip
))
7650 /* Make sure there is enough room to swap this instruction with
7651 a following jump instruction. */
7653 add_fixed_insn (ip
);
7657 if (mips_opts
.mips16
7658 && mips_opts
.noreorder
7659 && delayed_branch_p (&history
[0]))
7660 as_warn (_("extended instruction in delay slot"));
7662 if (mips_relax
.sequence
)
7664 /* If we've reached the end of this frag, turn it into a variant
7665 frag and record the information for the instructions we've
7667 if (frag_room () < 4)
7668 relax_close_frag ();
7669 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7672 if (mips_relax
.sequence
!= 2)
7674 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7675 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7676 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7677 mips_macro_warning
.insns
[0]++;
7679 if (mips_relax
.sequence
!= 1)
7681 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7682 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7683 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7684 mips_macro_warning
.insns
[1]++;
7687 if (mips_opts
.mips16
)
7690 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7692 add_fixed_insn (ip
);
7695 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7697 bfd_reloc_code_real_type final_type
[3];
7698 reloc_howto_type
*howto0
;
7699 reloc_howto_type
*howto
;
7702 /* Perform any necessary conversion to microMIPS relocations
7703 and find out how many relocations there actually are. */
7704 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7705 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7707 /* In a compound relocation, it is the final (outermost)
7708 operator that determines the relocated field. */
7709 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7714 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7715 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7716 bfd_get_reloc_size (howto
),
7718 howto0
&& howto0
->pc_relative
,
7720 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7721 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7723 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7724 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7725 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7727 /* These relocations can have an addend that won't fit in
7728 4 octets for 64bit assembly. */
7730 && ! howto
->partial_inplace
7731 && (reloc_type
[0] == BFD_RELOC_16
7732 || reloc_type
[0] == BFD_RELOC_32
7733 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7734 || reloc_type
[0] == BFD_RELOC_GPREL16
7735 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7736 || reloc_type
[0] == BFD_RELOC_GPREL32
7737 || reloc_type
[0] == BFD_RELOC_64
7738 || reloc_type
[0] == BFD_RELOC_CTOR
7739 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7740 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7741 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7742 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7743 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7744 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7745 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7746 || hi16_reloc_p (reloc_type
[0])
7747 || lo16_reloc_p (reloc_type
[0])))
7748 ip
->fixp
[0]->fx_no_overflow
= 1;
7750 /* These relocations can have an addend that won't fit in 2 octets. */
7751 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7752 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7753 ip
->fixp
[0]->fx_no_overflow
= 1;
7755 if (mips_relax
.sequence
)
7757 if (mips_relax
.first_fixup
== 0)
7758 mips_relax
.first_fixup
= ip
->fixp
[0];
7760 else if (reloc_needs_lo_p (*reloc_type
))
7762 struct mips_hi_fixup
*hi_fixup
;
7764 /* Reuse the last entry if it already has a matching %lo. */
7765 hi_fixup
= mips_hi_fixup_list
;
7767 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7769 hi_fixup
= XNEW (struct mips_hi_fixup
);
7770 hi_fixup
->next
= mips_hi_fixup_list
;
7771 mips_hi_fixup_list
= hi_fixup
;
7773 hi_fixup
->fixp
= ip
->fixp
[0];
7774 hi_fixup
->seg
= now_seg
;
7777 /* Add fixups for the second and third relocations, if given.
7778 Note that the ABI allows the second relocation to be
7779 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7780 moment we only use RSS_UNDEF, but we could add support
7781 for the others if it ever becomes necessary. */
7782 for (i
= 1; i
< 3; i
++)
7783 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7785 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7786 ip
->fixp
[0]->fx_size
, NULL
, 0,
7787 FALSE
, final_type
[i
]);
7789 /* Use fx_tcbit to mark compound relocs. */
7790 ip
->fixp
[0]->fx_tcbit
= 1;
7791 ip
->fixp
[i
]->fx_tcbit
= 1;
7795 /* Update the register mask information. */
7796 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7797 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7802 insert_into_history (0, 1, ip
);
7805 case APPEND_ADD_WITH_NOP
:
7807 struct mips_cl_insn
*nop
;
7809 insert_into_history (0, 1, ip
);
7810 nop
= get_delay_slot_nop (ip
);
7811 add_fixed_insn (nop
);
7812 insert_into_history (0, 1, nop
);
7813 if (mips_relax
.sequence
)
7814 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7818 case APPEND_ADD_COMPACT
:
7819 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7820 if (mips_opts
.mips16
)
7822 ip
->insn_opcode
|= 0x0080;
7823 find_altered_mips16_opcode (ip
);
7825 /* Convert microMIPS instructions. */
7826 else if (mips_opts
.micromips
)
7829 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7830 ip
->insn_opcode
|= 0x0020;
7832 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7833 ip
->insn_opcode
= 0x40e00000;
7834 /* beqz16->beqzc, bnez16->bnezc */
7835 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7837 unsigned long regno
;
7839 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7840 regno
&= MICROMIPSOP_MASK_MD
;
7841 regno
= micromips_to_32_reg_d_map
[regno
];
7842 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7843 | (regno
<< MICROMIPSOP_SH_RS
)
7844 | 0x40a00000) ^ 0x00400000;
7846 /* beqz->beqzc, bnez->bnezc */
7847 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7848 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7849 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7850 | 0x40a00000) ^ 0x00400000;
7851 /* beq $0->beqzc, bne $0->bnezc */
7852 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7853 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7854 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7855 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7856 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7857 | 0x40a00000) ^ 0x00400000;
7860 find_altered_micromips_opcode (ip
);
7865 insert_into_history (0, 1, ip
);
7870 struct mips_cl_insn delay
= history
[0];
7872 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7874 /* Add the delay slot instruction to the end of the
7875 current frag and shrink the fixed part of the
7876 original frag. If the branch occupies the tail of
7877 the latter, move it backwards to cover the gap. */
7878 delay
.frag
->fr_fix
-= branch_disp
;
7879 if (delay
.frag
== ip
->frag
)
7880 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7881 add_fixed_insn (&delay
);
7885 /* If this is not a relaxed branch and we are in the
7886 same frag, then just swap the instructions. */
7887 move_insn (ip
, delay
.frag
, delay
.where
);
7888 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7892 insert_into_history (0, 1, &delay
);
7897 /* If we have just completed an unconditional branch, clear the history. */
7898 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7899 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7903 mips_no_prev_insn ();
7905 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7906 history
[i
].cleared_p
= 1;
7909 /* We need to emit a label at the end of branch-likely macros. */
7910 if (emit_branch_likely_macro
)
7912 emit_branch_likely_macro
= FALSE
;
7913 micromips_add_label ();
7916 /* We just output an insn, so the next one doesn't have a label. */
7917 mips_clear_insn_labels ();
7920 /* Forget that there was any previous instruction or label.
7921 When BRANCH is true, the branch history is also flushed. */
7924 mips_no_prev_insn (void)
7926 prev_nop_frag
= NULL
;
7927 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7928 mips_clear_insn_labels ();
7931 /* This function must be called before we emit something other than
7932 instructions. It is like mips_no_prev_insn except that it inserts
7933 any NOPS that might be needed by previous instructions. */
7936 mips_emit_delays (void)
7938 if (! mips_opts
.noreorder
)
7940 int nops
= nops_for_insn (0, history
, NULL
);
7944 add_fixed_insn (NOP_INSN
);
7945 mips_move_text_labels ();
7948 mips_no_prev_insn ();
7951 /* Start a (possibly nested) noreorder block. */
7954 start_noreorder (void)
7956 if (mips_opts
.noreorder
== 0)
7961 /* None of the instructions before the .set noreorder can be moved. */
7962 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7963 history
[i
].fixed_p
= 1;
7965 /* Insert any nops that might be needed between the .set noreorder
7966 block and the previous instructions. We will later remove any
7967 nops that turn out not to be needed. */
7968 nops
= nops_for_insn (0, history
, NULL
);
7971 if (mips_optimize
!= 0)
7973 /* Record the frag which holds the nop instructions, so
7974 that we can remove them if we don't need them. */
7975 frag_grow (nops
* NOP_INSN_SIZE
);
7976 prev_nop_frag
= frag_now
;
7977 prev_nop_frag_holds
= nops
;
7978 prev_nop_frag_required
= 0;
7979 prev_nop_frag_since
= 0;
7982 for (; nops
> 0; --nops
)
7983 add_fixed_insn (NOP_INSN
);
7985 /* Move on to a new frag, so that it is safe to simply
7986 decrease the size of prev_nop_frag. */
7987 frag_wane (frag_now
);
7989 mips_move_text_labels ();
7991 mips_mark_labels ();
7992 mips_clear_insn_labels ();
7994 mips_opts
.noreorder
++;
7995 mips_any_noreorder
= 1;
7998 /* End a nested noreorder block. */
8001 end_noreorder (void)
8003 mips_opts
.noreorder
--;
8004 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8006 /* Commit to inserting prev_nop_frag_required nops and go back to
8007 handling nop insertion the .set reorder way. */
8008 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8010 insert_into_history (prev_nop_frag_since
,
8011 prev_nop_frag_required
, NOP_INSN
);
8012 prev_nop_frag
= NULL
;
8016 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8017 higher bits unset. */
8020 normalize_constant_expr (expressionS
*ex
)
8022 if (ex
->X_op
== O_constant
8023 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8024 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8028 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8029 all higher bits unset. */
8032 normalize_address_expr (expressionS
*ex
)
8034 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8035 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8036 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8037 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8041 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8042 Return true if the match was successful.
8044 OPCODE_EXTRA is a value that should be ORed into the opcode
8045 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8046 there are more alternatives after OPCODE and SOFT_MATCH is
8047 as for mips_arg_info. */
8050 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8051 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8052 bfd_boolean lax_match
, bfd_boolean complete_p
)
8055 struct mips_arg_info arg
;
8056 const struct mips_operand
*operand
;
8059 imm_expr
.X_op
= O_absent
;
8060 offset_expr
.X_op
= O_absent
;
8061 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8062 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8063 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8065 create_insn (insn
, opcode
);
8066 /* When no opcode suffix is specified, assume ".xyzw". */
8067 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8068 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8070 insn
->insn_opcode
|= opcode_extra
;
8071 memset (&arg
, 0, sizeof (arg
));
8075 arg
.last_regno
= ILLEGAL_REG
;
8076 arg
.dest_regno
= ILLEGAL_REG
;
8077 arg
.lax_match
= lax_match
;
8078 for (args
= opcode
->args
;; ++args
)
8080 if (arg
.token
->type
== OT_END
)
8082 /* Handle unary instructions in which only one operand is given.
8083 The source is then the same as the destination. */
8084 if (arg
.opnum
== 1 && *args
== ',')
8086 operand
= (mips_opts
.micromips
8087 ? decode_micromips_operand (args
+ 1)
8088 : decode_mips_operand (args
+ 1));
8089 if (operand
&& mips_optional_operand_p (operand
))
8097 /* Treat elided base registers as $0. */
8098 if (strcmp (args
, "(b)") == 0)
8106 /* The register suffix is optional. */
8111 /* Fail the match if there were too few operands. */
8115 /* Successful match. */
8118 clear_insn_error ();
8119 if (arg
.dest_regno
== arg
.last_regno
8120 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8124 (0, _("source and destination must be different"));
8125 else if (arg
.last_regno
== 31)
8127 (0, _("a destination register must be supplied"));
8129 else if (arg
.last_regno
== 31
8130 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8131 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8132 set_insn_error (0, _("the source register must not be $31"));
8133 check_completed_insn (&arg
);
8137 /* Fail the match if the line has too many operands. */
8141 /* Handle characters that need to match exactly. */
8142 if (*args
== '(' || *args
== ')' || *args
== ',')
8144 if (match_char (&arg
, *args
))
8151 if (arg
.token
->type
== OT_DOUBLE_CHAR
8152 && arg
.token
->u
.ch
== *args
)
8160 /* Handle special macro operands. Work out the properties of
8169 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8173 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8182 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8186 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8190 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8196 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8198 imm_expr
.X_op
= O_constant
;
8200 normalize_constant_expr (&imm_expr
);
8204 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8206 /* Assume that the offset has been elided and that what
8207 we saw was a base register. The match will fail later
8208 if that assumption turns out to be wrong. */
8209 offset_expr
.X_op
= O_constant
;
8210 offset_expr
.X_add_number
= 0;
8214 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8216 normalize_address_expr (&offset_expr
);
8221 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8227 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8233 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8239 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8245 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8249 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8253 gas_assert (mips_opts
.micromips
);
8259 if (!forced_insn_length
)
8260 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8262 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8264 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8270 operand
= (mips_opts
.micromips
8271 ? decode_micromips_operand (args
)
8272 : decode_mips_operand (args
));
8276 /* Skip prefixes. */
8277 if (*args
== '+' || *args
== 'm' || *args
== '-')
8280 if (mips_optional_operand_p (operand
)
8282 && (arg
.token
[0].type
!= OT_REG
8283 || arg
.token
[1].type
== OT_END
))
8285 /* Assume that the register has been elided and is the
8286 same as the first operand. */
8291 if (!match_operand (&arg
, operand
))
8296 /* Like match_insn, but for MIPS16. */
8299 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8300 struct mips_operand_token
*tokens
)
8303 const struct mips_operand
*operand
;
8304 const struct mips_operand
*ext_operand
;
8305 bfd_boolean pcrel
= FALSE
;
8306 int required_insn_length
;
8307 struct mips_arg_info arg
;
8310 if (forced_insn_length
)
8311 required_insn_length
= forced_insn_length
;
8312 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8313 required_insn_length
= 2;
8315 required_insn_length
= 0;
8317 create_insn (insn
, opcode
);
8318 imm_expr
.X_op
= O_absent
;
8319 offset_expr
.X_op
= O_absent
;
8320 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8321 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8322 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8325 memset (&arg
, 0, sizeof (arg
));
8329 arg
.last_regno
= ILLEGAL_REG
;
8330 arg
.dest_regno
= ILLEGAL_REG
;
8332 for (args
= opcode
->args
;; ++args
)
8336 if (arg
.token
->type
== OT_END
)
8340 /* Handle unary instructions in which only one operand is given.
8341 The source is then the same as the destination. */
8342 if (arg
.opnum
== 1 && *args
== ',')
8344 operand
= decode_mips16_operand (args
[1], FALSE
);
8345 if (operand
&& mips_optional_operand_p (operand
))
8353 /* Fail the match if there were too few operands. */
8357 /* Successful match. Stuff the immediate value in now, if
8359 clear_insn_error ();
8360 if (opcode
->pinfo
== INSN_MACRO
)
8362 gas_assert (relax_char
== 0 || relax_char
== 'p');
8363 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8366 && offset_expr
.X_op
== O_constant
8368 && calculate_reloc (*offset_reloc
,
8369 offset_expr
.X_add_number
,
8372 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8373 required_insn_length
, &insn
->insn_opcode
);
8374 offset_expr
.X_op
= O_absent
;
8375 *offset_reloc
= BFD_RELOC_UNUSED
;
8377 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8379 if (required_insn_length
== 2)
8380 set_insn_error (0, _("invalid unextended operand value"));
8381 else if (!mips_opcode_32bit_p (opcode
))
8383 forced_insn_length
= 4;
8384 insn
->insn_opcode
|= MIPS16_EXTEND
;
8387 else if (relax_char
)
8388 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8390 check_completed_insn (&arg
);
8394 /* Fail the match if the line has too many operands. */
8398 /* Handle characters that need to match exactly. */
8399 if (*args
== '(' || *args
== ')' || *args
== ',')
8401 if (match_char (&arg
, *args
))
8421 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8423 imm_expr
.X_op
= O_constant
;
8425 normalize_constant_expr (&imm_expr
);
8430 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8434 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8438 if (operand
->type
== OP_PCREL
)
8442 ext_operand
= decode_mips16_operand (c
, TRUE
);
8443 if (operand
!= ext_operand
)
8445 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8447 offset_expr
.X_op
= O_constant
;
8448 offset_expr
.X_add_number
= 0;
8453 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8456 /* '8' is used for SLTI(U) and has traditionally not
8457 been allowed to take relocation operators. */
8458 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8459 && (ext_operand
->size
!= 16 || c
== '8'))
8461 match_not_constant (&arg
);
8465 if (offset_expr
.X_op
== O_big
)
8467 match_out_of_range (&arg
);
8476 if (mips_optional_operand_p (operand
)
8478 && (arg
.token
[0].type
!= OT_REG
8479 || arg
.token
[1].type
== OT_END
))
8481 /* Assume that the register has been elided and is the
8482 same as the first operand. */
8487 if (!match_operand (&arg
, operand
))
8492 /* Record that the current instruction is invalid for the current ISA. */
8495 match_invalid_for_isa (void)
8498 (0, _("opcode not supported on this processor: %s (%s)"),
8499 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8500 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8503 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8504 Return true if a definite match or failure was found, storing any match
8505 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8506 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8507 tried and failed to match under normal conditions and now want to try a
8508 more relaxed match. */
8511 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8512 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8513 int opcode_extra
, bfd_boolean lax_match
)
8515 const struct mips_opcode
*opcode
;
8516 const struct mips_opcode
*invalid_delay_slot
;
8517 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8519 /* Search for a match, ignoring alternatives that don't satisfy the
8520 current ISA or forced_length. */
8521 invalid_delay_slot
= 0;
8522 seen_valid_for_isa
= FALSE
;
8523 seen_valid_for_size
= FALSE
;
8527 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8528 if (is_opcode_valid (opcode
))
8530 seen_valid_for_isa
= TRUE
;
8531 if (is_size_valid (opcode
))
8533 bfd_boolean delay_slot_ok
;
8535 seen_valid_for_size
= TRUE
;
8536 delay_slot_ok
= is_delay_slot_valid (opcode
);
8537 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8538 lax_match
, delay_slot_ok
))
8542 if (!invalid_delay_slot
)
8543 invalid_delay_slot
= opcode
;
8552 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8554 /* If the only matches we found had the wrong length for the delay slot,
8555 pick the first such match. We'll issue an appropriate warning later. */
8556 if (invalid_delay_slot
)
8558 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8564 /* Handle the case where we didn't try to match an instruction because
8565 all the alternatives were incompatible with the current ISA. */
8566 if (!seen_valid_for_isa
)
8568 match_invalid_for_isa ();
8572 /* Handle the case where we didn't try to match an instruction because
8573 all the alternatives were of the wrong size. */
8574 if (!seen_valid_for_size
)
8576 if (mips_opts
.insn32
)
8577 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8580 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8581 8 * forced_insn_length
);
8588 /* Like match_insns, but for MIPS16. */
8591 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8592 struct mips_operand_token
*tokens
)
8594 const struct mips_opcode
*opcode
;
8595 bfd_boolean seen_valid_for_isa
;
8596 bfd_boolean seen_valid_for_size
;
8598 /* Search for a match, ignoring alternatives that don't satisfy the
8599 current ISA. There are no separate entries for extended forms so
8600 we deal with forced_length later. */
8601 seen_valid_for_isa
= FALSE
;
8602 seen_valid_for_size
= FALSE
;
8606 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8607 if (is_opcode_valid_16 (opcode
))
8609 seen_valid_for_isa
= TRUE
;
8610 if (is_size_valid_16 (opcode
))
8612 seen_valid_for_size
= TRUE
;
8613 if (match_mips16_insn (insn
, opcode
, tokens
))
8619 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8620 && strcmp (opcode
->name
, first
->name
) == 0);
8622 /* Handle the case where we didn't try to match an instruction because
8623 all the alternatives were incompatible with the current ISA. */
8624 if (!seen_valid_for_isa
)
8626 match_invalid_for_isa ();
8630 /* Handle the case where we didn't try to match an instruction because
8631 all the alternatives were of the wrong size. */
8632 if (!seen_valid_for_size
)
8634 if (forced_insn_length
== 2)
8636 (0, _("unrecognized unextended version of MIPS16 opcode"));
8639 (0, _("unrecognized extended version of MIPS16 opcode"));
8646 /* Set up global variables for the start of a new macro. */
8651 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8652 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8653 sizeof (mips_macro_warning
.first_insn_sizes
));
8654 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8655 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8656 && delayed_branch_p (&history
[0]));
8658 && history
[0].frag
->fr_type
== rs_machine_dependent
8659 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8660 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8661 mips_macro_warning
.delay_slot_length
= 0;
8663 switch (history
[0].insn_mo
->pinfo2
8664 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8666 case INSN2_BRANCH_DELAY_32BIT
:
8667 mips_macro_warning
.delay_slot_length
= 4;
8669 case INSN2_BRANCH_DELAY_16BIT
:
8670 mips_macro_warning
.delay_slot_length
= 2;
8673 mips_macro_warning
.delay_slot_length
= 0;
8676 mips_macro_warning
.first_frag
= NULL
;
8679 /* Given that a macro is longer than one instruction or of the wrong size,
8680 return the appropriate warning for it. Return null if no warning is
8681 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8682 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8683 and RELAX_NOMACRO. */
8686 macro_warning (relax_substateT subtype
)
8688 if (subtype
& RELAX_DELAY_SLOT
)
8689 return _("macro instruction expanded into multiple instructions"
8690 " in a branch delay slot");
8691 else if (subtype
& RELAX_NOMACRO
)
8692 return _("macro instruction expanded into multiple instructions");
8693 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8694 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8695 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8696 ? _("macro instruction expanded into a wrong size instruction"
8697 " in a 16-bit branch delay slot")
8698 : _("macro instruction expanded into a wrong size instruction"
8699 " in a 32-bit branch delay slot"));
8704 /* Finish up a macro. Emit warnings as appropriate. */
8709 /* Relaxation warning flags. */
8710 relax_substateT subtype
= 0;
8712 /* Check delay slot size requirements. */
8713 if (mips_macro_warning
.delay_slot_length
== 2)
8714 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8715 if (mips_macro_warning
.delay_slot_length
!= 0)
8717 if (mips_macro_warning
.delay_slot_length
8718 != mips_macro_warning
.first_insn_sizes
[0])
8719 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8720 if (mips_macro_warning
.delay_slot_length
8721 != mips_macro_warning
.first_insn_sizes
[1])
8722 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8725 /* Check instruction count requirements. */
8726 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8728 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8729 subtype
|= RELAX_SECOND_LONGER
;
8730 if (mips_opts
.warn_about_macros
)
8731 subtype
|= RELAX_NOMACRO
;
8732 if (mips_macro_warning
.delay_slot_p
)
8733 subtype
|= RELAX_DELAY_SLOT
;
8736 /* If both alternatives fail to fill a delay slot correctly,
8737 emit the warning now. */
8738 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8739 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8744 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8745 | RELAX_DELAY_SLOT_SIZE_FIRST
8746 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8747 msg
= macro_warning (s
);
8749 as_warn ("%s", msg
);
8753 /* If both implementations are longer than 1 instruction, then emit the
8755 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8760 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8761 msg
= macro_warning (s
);
8763 as_warn ("%s", msg
);
8767 /* If any flags still set, then one implementation might need a warning
8768 and the other either will need one of a different kind or none at all.
8769 Pass any remaining flags over to relaxation. */
8770 if (mips_macro_warning
.first_frag
!= NULL
)
8771 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8774 /* Instruction operand formats used in macros that vary between
8775 standard MIPS and microMIPS code. */
8777 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8778 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8779 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8780 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8781 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8782 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8783 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8784 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8786 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8787 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8788 : cop12_fmt[mips_opts.micromips])
8789 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8790 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8791 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8792 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8793 : mem12_fmt[mips_opts.micromips])
8794 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8795 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8796 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8798 /* Read a macro's relocation codes from *ARGS and store them in *R.
8799 The first argument in *ARGS will be either the code for a single
8800 relocation or -1 followed by the three codes that make up a
8801 composite relocation. */
8804 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8808 next
= va_arg (*args
, int);
8810 r
[0] = (bfd_reloc_code_real_type
) next
;
8813 for (i
= 0; i
< 3; i
++)
8814 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8815 /* This function is only used for 16-bit relocation fields.
8816 To make the macro code simpler, treat an unrelocated value
8817 in the same way as BFD_RELOC_LO16. */
8818 if (r
[0] == BFD_RELOC_UNUSED
)
8819 r
[0] = BFD_RELOC_LO16
;
8823 /* Build an instruction created by a macro expansion. This is passed
8824 a pointer to the count of instructions created so far, an
8825 expression, the name of the instruction to build, an operand format
8826 string, and corresponding arguments. */
8829 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8831 const struct mips_opcode
*mo
= NULL
;
8832 bfd_reloc_code_real_type r
[3];
8833 const struct mips_opcode
*amo
;
8834 const struct mips_operand
*operand
;
8835 struct hash_control
*hash
;
8836 struct mips_cl_insn insn
;
8840 va_start (args
, fmt
);
8842 if (mips_opts
.mips16
)
8844 mips16_macro_build (ep
, name
, fmt
, &args
);
8849 r
[0] = BFD_RELOC_UNUSED
;
8850 r
[1] = BFD_RELOC_UNUSED
;
8851 r
[2] = BFD_RELOC_UNUSED
;
8852 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8853 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8855 gas_assert (strcmp (name
, amo
->name
) == 0);
8859 /* Search until we get a match for NAME. It is assumed here that
8860 macros will never generate MDMX, MIPS-3D, or MT instructions.
8861 We try to match an instruction that fulfills the branch delay
8862 slot instruction length requirement (if any) of the previous
8863 instruction. While doing this we record the first instruction
8864 seen that matches all the other conditions and use it anyway
8865 if the requirement cannot be met; we will issue an appropriate
8866 warning later on. */
8867 if (strcmp (fmt
, amo
->args
) == 0
8868 && amo
->pinfo
!= INSN_MACRO
8869 && is_opcode_valid (amo
)
8870 && is_size_valid (amo
))
8872 if (is_delay_slot_valid (amo
))
8882 gas_assert (amo
->name
);
8884 while (strcmp (name
, amo
->name
) == 0);
8887 create_insn (&insn
, mo
);
8900 macro_read_relocs (&args
, r
);
8901 gas_assert (*r
== BFD_RELOC_GPREL16
8902 || *r
== BFD_RELOC_MIPS_HIGHER
8903 || *r
== BFD_RELOC_HI16_S
8904 || *r
== BFD_RELOC_LO16
8905 || *r
== BFD_RELOC_MIPS_GOT_OFST
8906 || (mips_opts
.micromips
8907 && (*r
== BFD_RELOC_16
8908 || *r
== BFD_RELOC_MIPS_GOT16
8909 || *r
== BFD_RELOC_MIPS_CALL16
8910 || *r
== BFD_RELOC_MIPS_GOT_HI16
8911 || *r
== BFD_RELOC_MIPS_GOT_LO16
8912 || *r
== BFD_RELOC_MIPS_CALL_HI16
8913 || *r
== BFD_RELOC_MIPS_CALL_LO16
8914 || *r
== BFD_RELOC_MIPS_SUB
8915 || *r
== BFD_RELOC_MIPS_GOT_PAGE
8916 || *r
== BFD_RELOC_MIPS_HIGHEST
8917 || *r
== BFD_RELOC_MIPS_GOT_DISP
8918 || *r
== BFD_RELOC_MIPS_TLS_GD
8919 || *r
== BFD_RELOC_MIPS_TLS_LDM
8920 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
8921 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
8922 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
8923 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
8924 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
8928 macro_read_relocs (&args
, r
);
8932 macro_read_relocs (&args
, r
);
8933 gas_assert (ep
!= NULL
8934 && (ep
->X_op
== O_constant
8935 || (ep
->X_op
== O_symbol
8936 && (*r
== BFD_RELOC_MIPS_HIGHEST
8937 || *r
== BFD_RELOC_HI16_S
8938 || *r
== BFD_RELOC_HI16
8939 || *r
== BFD_RELOC_GPREL16
8940 || *r
== BFD_RELOC_MIPS_GOT_HI16
8941 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8945 gas_assert (ep
!= NULL
);
8948 * This allows macro() to pass an immediate expression for
8949 * creating short branches without creating a symbol.
8951 * We don't allow branch relaxation for these branches, as
8952 * they should only appear in ".set nomacro" anyway.
8954 if (ep
->X_op
== O_constant
)
8956 /* For microMIPS we always use relocations for branches.
8957 So we should not resolve immediate values. */
8958 gas_assert (!mips_opts
.micromips
);
8960 if ((ep
->X_add_number
& 3) != 0)
8961 as_bad (_("branch to misaligned address (0x%lx)"),
8962 (unsigned long) ep
->X_add_number
);
8963 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8964 as_bad (_("branch address range overflow (0x%lx)"),
8965 (unsigned long) ep
->X_add_number
);
8966 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8970 *r
= BFD_RELOC_16_PCREL_S2
;
8974 gas_assert (ep
!= NULL
);
8975 *r
= BFD_RELOC_MIPS_JMP
;
8979 operand
= (mips_opts
.micromips
8980 ? decode_micromips_operand (fmt
)
8981 : decode_mips_operand (fmt
));
8985 uval
= va_arg (args
, int);
8986 if (operand
->type
== OP_CLO_CLZ_DEST
)
8987 uval
|= (uval
<< 5);
8988 insn_insert_operand (&insn
, operand
, uval
);
8990 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8996 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8998 append_insn (&insn
, ep
, r
, TRUE
);
9002 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9005 struct mips_opcode
*mo
;
9006 struct mips_cl_insn insn
;
9007 const struct mips_operand
*operand
;
9008 bfd_reloc_code_real_type r
[3]
9009 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9011 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
9013 gas_assert (strcmp (name
, mo
->name
) == 0);
9015 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9018 gas_assert (mo
->name
);
9019 gas_assert (strcmp (name
, mo
->name
) == 0);
9022 create_insn (&insn
, mo
);
9059 gas_assert (ep
!= NULL
);
9061 if (ep
->X_op
!= O_constant
)
9062 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9063 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9065 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9067 *r
= BFD_RELOC_UNUSED
;
9073 operand
= decode_mips16_operand (c
, FALSE
);
9077 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9082 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9084 append_insn (&insn
, ep
, r
, TRUE
);
9088 * Generate a "jalr" instruction with a relocation hint to the called
9089 * function. This occurs in NewABI PIC code.
9092 macro_build_jalr (expressionS
*ep
, int cprestore
)
9094 static const bfd_reloc_code_real_type jalr_relocs
[2]
9095 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9096 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9100 if (MIPS_JALR_HINT_P (ep
))
9105 if (mips_opts
.micromips
)
9107 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9108 ? "jalr" : "jalrs");
9109 if (MIPS_JALR_HINT_P (ep
)
9111 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9112 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9114 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9117 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9118 if (MIPS_JALR_HINT_P (ep
))
9119 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9123 * Generate a "lui" instruction.
9126 macro_build_lui (expressionS
*ep
, int regnum
)
9128 gas_assert (! mips_opts
.mips16
);
9130 if (ep
->X_op
!= O_constant
)
9132 gas_assert (ep
->X_op
== O_symbol
);
9133 /* _gp_disp is a special case, used from s_cpload.
9134 __gnu_local_gp is used if mips_no_shared. */
9135 gas_assert (mips_pic
== NO_PIC
9137 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9138 || (! mips_in_shared
9139 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9140 "__gnu_local_gp") == 0));
9143 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9146 /* Generate a sequence of instructions to do a load or store from a constant
9147 offset off of a base register (breg) into/from a target register (treg),
9148 using AT if necessary. */
9150 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9151 int treg
, int breg
, int dbl
)
9153 gas_assert (ep
->X_op
== O_constant
);
9155 /* Sign-extending 32-bit constants makes their handling easier. */
9157 normalize_constant_expr (ep
);
9159 /* Right now, this routine can only handle signed 32-bit constants. */
9160 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9161 as_warn (_("operand overflow"));
9163 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9165 /* Signed 16-bit offset will fit in the op. Easy! */
9166 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9170 /* 32-bit offset, need multiple instructions and AT, like:
9171 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9172 addu $tempreg,$tempreg,$breg
9173 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9174 to handle the complete offset. */
9175 macro_build_lui (ep
, AT
);
9176 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9177 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9180 as_bad (_("macro used $at after \".set noat\""));
9185 * Generates code to set the $at register to true (one)
9186 * if reg is less than the immediate expression.
9189 set_at (int reg
, int unsignedp
)
9191 if (imm_expr
.X_add_number
>= -0x8000
9192 && imm_expr
.X_add_number
< 0x8000)
9193 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9194 AT
, reg
, BFD_RELOC_LO16
);
9197 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9198 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9202 /* Count the leading zeroes by performing a binary chop. This is a
9203 bulky bit of source, but performance is a LOT better for the
9204 majority of values than a simple loop to count the bits:
9205 for (lcnt = 0; (lcnt < 32); lcnt++)
9206 if ((v) & (1 << (31 - lcnt)))
9208 However it is not code size friendly, and the gain will drop a bit
9209 on certain cached systems.
9211 #define COUNT_TOP_ZEROES(v) \
9212 (((v) & ~0xffff) == 0 \
9213 ? ((v) & ~0xff) == 0 \
9214 ? ((v) & ~0xf) == 0 \
9215 ? ((v) & ~0x3) == 0 \
9216 ? ((v) & ~0x1) == 0 \
9221 : ((v) & ~0x7) == 0 \
9224 : ((v) & ~0x3f) == 0 \
9225 ? ((v) & ~0x1f) == 0 \
9228 : ((v) & ~0x7f) == 0 \
9231 : ((v) & ~0xfff) == 0 \
9232 ? ((v) & ~0x3ff) == 0 \
9233 ? ((v) & ~0x1ff) == 0 \
9236 : ((v) & ~0x7ff) == 0 \
9239 : ((v) & ~0x3fff) == 0 \
9240 ? ((v) & ~0x1fff) == 0 \
9243 : ((v) & ~0x7fff) == 0 \
9246 : ((v) & ~0xffffff) == 0 \
9247 ? ((v) & ~0xfffff) == 0 \
9248 ? ((v) & ~0x3ffff) == 0 \
9249 ? ((v) & ~0x1ffff) == 0 \
9252 : ((v) & ~0x7ffff) == 0 \
9255 : ((v) & ~0x3fffff) == 0 \
9256 ? ((v) & ~0x1fffff) == 0 \
9259 : ((v) & ~0x7fffff) == 0 \
9262 : ((v) & ~0xfffffff) == 0 \
9263 ? ((v) & ~0x3ffffff) == 0 \
9264 ? ((v) & ~0x1ffffff) == 0 \
9267 : ((v) & ~0x7ffffff) == 0 \
9270 : ((v) & ~0x3fffffff) == 0 \
9271 ? ((v) & ~0x1fffffff) == 0 \
9274 : ((v) & ~0x7fffffff) == 0 \
9279 * This routine generates the least number of instructions necessary to load
9280 * an absolute expression value into a register.
9283 load_register (int reg
, expressionS
*ep
, int dbl
)
9286 expressionS hi32
, lo32
;
9288 if (ep
->X_op
!= O_big
)
9290 gas_assert (ep
->X_op
== O_constant
);
9292 /* Sign-extending 32-bit constants makes their handling easier. */
9294 normalize_constant_expr (ep
);
9296 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9298 /* We can handle 16 bit signed values with an addiu to
9299 $zero. No need to ever use daddiu here, since $zero and
9300 the result are always correct in 32 bit mode. */
9301 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9304 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9306 /* We can handle 16 bit unsigned values with an ori to
9308 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9311 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9313 /* 32 bit values require an lui. */
9314 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9315 if ((ep
->X_add_number
& 0xffff) != 0)
9316 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9321 /* The value is larger than 32 bits. */
9323 if (!dbl
|| GPR_SIZE
== 32)
9327 sprintf_vma (value
, ep
->X_add_number
);
9328 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9329 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9333 if (ep
->X_op
!= O_big
)
9336 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9337 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9338 hi32
.X_add_number
&= 0xffffffff;
9340 lo32
.X_add_number
&= 0xffffffff;
9344 gas_assert (ep
->X_add_number
> 2);
9345 if (ep
->X_add_number
== 3)
9346 generic_bignum
[3] = 0;
9347 else if (ep
->X_add_number
> 4)
9348 as_bad (_("number larger than 64 bits"));
9349 lo32
.X_op
= O_constant
;
9350 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9351 hi32
.X_op
= O_constant
;
9352 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9355 if (hi32
.X_add_number
== 0)
9360 unsigned long hi
, lo
;
9362 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9364 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9366 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9369 if (lo32
.X_add_number
& 0x80000000)
9371 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9372 if (lo32
.X_add_number
& 0xffff)
9373 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9378 /* Check for 16bit shifted constant. We know that hi32 is
9379 non-zero, so start the mask on the first bit of the hi32
9384 unsigned long himask
, lomask
;
9388 himask
= 0xffff >> (32 - shift
);
9389 lomask
= (0xffff << shift
) & 0xffffffff;
9393 himask
= 0xffff << (shift
- 32);
9396 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9397 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9401 tmp
.X_op
= O_constant
;
9403 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9404 | (lo32
.X_add_number
>> shift
));
9406 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9407 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9408 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9409 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9414 while (shift
<= (64 - 16));
9416 /* Find the bit number of the lowest one bit, and store the
9417 shifted value in hi/lo. */
9418 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9419 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9423 while ((lo
& 1) == 0)
9428 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9434 while ((hi
& 1) == 0)
9443 /* Optimize if the shifted value is a (power of 2) - 1. */
9444 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9445 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9447 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9452 /* This instruction will set the register to be all
9454 tmp
.X_op
= O_constant
;
9455 tmp
.X_add_number
= (offsetT
) -1;
9456 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9460 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9461 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9463 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9464 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9469 /* Sign extend hi32 before calling load_register, because we can
9470 generally get better code when we load a sign extended value. */
9471 if ((hi32
.X_add_number
& 0x80000000) != 0)
9472 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9473 load_register (reg
, &hi32
, 0);
9476 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9480 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9488 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9490 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9491 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9497 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9501 mid16
.X_add_number
>>= 16;
9502 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9503 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9506 if ((lo32
.X_add_number
& 0xffff) != 0)
9507 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9511 load_delay_nop (void)
9513 if (!gpr_interlocks
)
9514 macro_build (NULL
, "nop", "");
9517 /* Load an address into a register. */
9520 load_address (int reg
, expressionS
*ep
, int *used_at
)
9522 if (ep
->X_op
!= O_constant
9523 && ep
->X_op
!= O_symbol
)
9525 as_bad (_("expression too complex"));
9526 ep
->X_op
= O_constant
;
9529 if (ep
->X_op
== O_constant
)
9531 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9535 if (mips_pic
== NO_PIC
)
9537 /* If this is a reference to a GP relative symbol, we want
9538 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9540 lui $reg,<sym> (BFD_RELOC_HI16_S)
9541 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9542 If we have an addend, we always use the latter form.
9544 With 64bit address space and a usable $at we want
9545 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9546 lui $at,<sym> (BFD_RELOC_HI16_S)
9547 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9548 daddiu $at,<sym> (BFD_RELOC_LO16)
9552 If $at is already in use, we use a path which is suboptimal
9553 on superscalar processors.
9554 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9555 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9557 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9559 daddiu $reg,<sym> (BFD_RELOC_LO16)
9561 For GP relative symbols in 64bit address space we can use
9562 the same sequence as in 32bit address space. */
9563 if (HAVE_64BIT_SYMBOLS
)
9565 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9566 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9568 relax_start (ep
->X_add_symbol
);
9569 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9570 mips_gp_register
, BFD_RELOC_GPREL16
);
9574 if (*used_at
== 0 && mips_opts
.at
)
9576 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9577 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9578 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9579 BFD_RELOC_MIPS_HIGHER
);
9580 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9581 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9582 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9587 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9588 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9589 BFD_RELOC_MIPS_HIGHER
);
9590 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9591 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9592 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9593 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9596 if (mips_relax
.sequence
)
9601 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9602 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9604 relax_start (ep
->X_add_symbol
);
9605 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9606 mips_gp_register
, BFD_RELOC_GPREL16
);
9609 macro_build_lui (ep
, reg
);
9610 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9611 reg
, reg
, BFD_RELOC_LO16
);
9612 if (mips_relax
.sequence
)
9616 else if (!mips_big_got
)
9620 /* If this is a reference to an external symbol, we want
9621 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9623 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9625 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9626 If there is a constant, it must be added in after.
9628 If we have NewABI, we want
9629 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9630 unless we're referencing a global symbol with a non-zero
9631 offset, in which case cst must be added separately. */
9634 if (ep
->X_add_number
)
9636 ex
.X_add_number
= ep
->X_add_number
;
9637 ep
->X_add_number
= 0;
9638 relax_start (ep
->X_add_symbol
);
9639 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9640 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9641 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9642 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9643 ex
.X_op
= O_constant
;
9644 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9645 reg
, reg
, BFD_RELOC_LO16
);
9646 ep
->X_add_number
= ex
.X_add_number
;
9649 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9650 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9651 if (mips_relax
.sequence
)
9656 ex
.X_add_number
= ep
->X_add_number
;
9657 ep
->X_add_number
= 0;
9658 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9659 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9661 relax_start (ep
->X_add_symbol
);
9663 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9667 if (ex
.X_add_number
!= 0)
9669 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9670 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9671 ex
.X_op
= O_constant
;
9672 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9673 reg
, reg
, BFD_RELOC_LO16
);
9677 else if (mips_big_got
)
9681 /* This is the large GOT case. If this is a reference to an
9682 external symbol, we want
9683 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9685 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9687 Otherwise, for a reference to a local symbol in old ABI, we want
9688 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9690 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9691 If there is a constant, it must be added in after.
9693 In the NewABI, for local symbols, with or without offsets, we want:
9694 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9695 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9699 ex
.X_add_number
= ep
->X_add_number
;
9700 ep
->X_add_number
= 0;
9701 relax_start (ep
->X_add_symbol
);
9702 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9703 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9704 reg
, reg
, mips_gp_register
);
9705 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9706 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9707 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9708 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9709 else if (ex
.X_add_number
)
9711 ex
.X_op
= O_constant
;
9712 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9716 ep
->X_add_number
= ex
.X_add_number
;
9718 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9719 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9720 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9721 BFD_RELOC_MIPS_GOT_OFST
);
9726 ex
.X_add_number
= ep
->X_add_number
;
9727 ep
->X_add_number
= 0;
9728 relax_start (ep
->X_add_symbol
);
9729 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9730 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9731 reg
, reg
, mips_gp_register
);
9732 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9733 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9735 if (reg_needs_delay (mips_gp_register
))
9737 /* We need a nop before loading from $gp. This special
9738 check is required because the lui which starts the main
9739 instruction stream does not refer to $gp, and so will not
9740 insert the nop which may be required. */
9741 macro_build (NULL
, "nop", "");
9743 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9744 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9746 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9750 if (ex
.X_add_number
!= 0)
9752 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9753 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9754 ex
.X_op
= O_constant
;
9755 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9763 if (!mips_opts
.at
&& *used_at
== 1)
9764 as_bad (_("macro used $at after \".set noat\""));
9767 /* Move the contents of register SOURCE into register DEST. */
9770 move_register (int dest
, int source
)
9772 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9773 instruction specifically requires a 32-bit one. */
9774 if (mips_opts
.micromips
9775 && !mips_opts
.insn32
9776 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9777 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9779 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9782 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9783 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9784 The two alternatives are:
9786 Global symbol Local symbol
9787 ------------- ------------
9788 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9790 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9792 load_got_offset emits the first instruction and add_got_offset
9793 emits the second for a 16-bit offset or add_got_offset_hilo emits
9794 a sequence to add a 32-bit offset using a scratch register. */
9797 load_got_offset (int dest
, expressionS
*local
)
9802 global
.X_add_number
= 0;
9804 relax_start (local
->X_add_symbol
);
9805 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9806 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9808 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9809 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9814 add_got_offset (int dest
, expressionS
*local
)
9818 global
.X_op
= O_constant
;
9819 global
.X_op_symbol
= NULL
;
9820 global
.X_add_symbol
= NULL
;
9821 global
.X_add_number
= local
->X_add_number
;
9823 relax_start (local
->X_add_symbol
);
9824 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9825 dest
, dest
, BFD_RELOC_LO16
);
9827 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9832 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9835 int hold_mips_optimize
;
9837 global
.X_op
= O_constant
;
9838 global
.X_op_symbol
= NULL
;
9839 global
.X_add_symbol
= NULL
;
9840 global
.X_add_number
= local
->X_add_number
;
9842 relax_start (local
->X_add_symbol
);
9843 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9845 /* Set mips_optimize around the lui instruction to avoid
9846 inserting an unnecessary nop after the lw. */
9847 hold_mips_optimize
= mips_optimize
;
9849 macro_build_lui (&global
, tmp
);
9850 mips_optimize
= hold_mips_optimize
;
9851 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9854 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9857 /* Emit a sequence of instructions to emulate a branch likely operation.
9858 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9859 is its complementing branch with the original condition negated.
9860 CALL is set if the original branch specified the link operation.
9861 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9863 Code like this is produced in the noreorder mode:
9868 delay slot (executed only if branch taken)
9876 delay slot (executed only if branch taken)
9879 In the reorder mode the delay slot would be filled with a nop anyway,
9880 so code produced is simply:
9885 This function is used when producing code for the microMIPS ASE that
9886 does not implement branch likely instructions in hardware. */
9889 macro_build_branch_likely (const char *br
, const char *brneg
,
9890 int call
, expressionS
*ep
, const char *fmt
,
9891 unsigned int sreg
, unsigned int treg
)
9893 int noreorder
= mips_opts
.noreorder
;
9896 gas_assert (mips_opts
.micromips
);
9900 micromips_label_expr (&expr1
);
9901 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9902 macro_build (NULL
, "nop", "");
9903 macro_build (ep
, call
? "bal" : "b", "p");
9905 /* Set to true so that append_insn adds a label. */
9906 emit_branch_likely_macro
= TRUE
;
9910 macro_build (ep
, br
, fmt
, sreg
, treg
);
9911 macro_build (NULL
, "nop", "");
9916 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9917 the condition code tested. EP specifies the branch target. */
9920 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9947 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9950 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9951 the register tested. EP specifies the branch target. */
9954 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9956 const char *brneg
= NULL
;
9966 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9970 gas_assert (mips_opts
.micromips
);
9971 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9979 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9986 br
= mips_opts
.micromips
? "blez" : "blezl";
9993 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9997 gas_assert (mips_opts
.micromips
);
9998 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10005 if (mips_opts
.micromips
&& brneg
)
10006 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10008 macro_build (ep
, br
, "s,p", sreg
);
10011 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10012 TREG as the registers tested. EP specifies the branch target. */
10015 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10016 unsigned int sreg
, unsigned int treg
)
10018 const char *brneg
= NULL
;
10019 const int call
= 0;
10030 br
= mips_opts
.micromips
? "beq" : "beql";
10039 br
= mips_opts
.micromips
? "bne" : "bnel";
10045 if (mips_opts
.micromips
&& brneg
)
10046 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10048 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10051 /* Return the high part that should be loaded in order to make the low
10052 part of VALUE accessible using an offset of OFFBITS bits. */
10055 offset_high_part (offsetT value
, unsigned int offbits
)
10062 bias
= 1 << (offbits
- 1);
10063 low_mask
= bias
* 2 - 1;
10064 return (value
+ bias
) & ~low_mask
;
10067 /* Return true if the value stored in offset_expr and offset_reloc
10068 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10069 amount that the caller wants to add without inducing overflow
10070 and ALIGN is the known alignment of the value in bytes. */
10073 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10077 /* Accept any relocation operator if overflow isn't a concern. */
10078 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10081 /* These relocations are guaranteed not to overflow in correct links. */
10082 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10083 || gprel16_reloc_p (*offset_reloc
))
10086 if (offset_expr
.X_op
== O_constant
10087 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10088 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10095 * This routine implements the seemingly endless macro or synthesized
10096 * instructions and addressing modes in the mips assembly language. Many
10097 * of these macros are simple and are similar to each other. These could
10098 * probably be handled by some kind of table or grammar approach instead of
10099 * this verbose method. Others are not simple macros but are more like
10100 * optimizing code generation.
10101 * One interesting optimization is when several store macros appear
10102 * consecutively that would load AT with the upper half of the same address.
10103 * The ensuing load upper instructions are omitted. This implies some kind
10104 * of global optimization. We currently only optimize within a single macro.
10105 * For many of the load and store macros if the address is specified as a
10106 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10107 * first load register 'at' with zero and use it as the base register. The
10108 * mips assembler simply uses register $zero. Just one tiny optimization
10112 macro (struct mips_cl_insn
*ip
, char *str
)
10114 const struct mips_operand_array
*operands
;
10115 unsigned int breg
, i
;
10116 unsigned int tempreg
;
10119 expressionS label_expr
;
10134 bfd_boolean large_offset
;
10136 int hold_mips_optimize
;
10137 unsigned int align
;
10138 unsigned int op
[MAX_OPERANDS
];
10140 gas_assert (! mips_opts
.mips16
);
10142 operands
= insn_operands (ip
);
10143 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10144 if (operands
->operand
[i
])
10145 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10149 mask
= ip
->insn_mo
->mask
;
10151 label_expr
.X_op
= O_constant
;
10152 label_expr
.X_op_symbol
= NULL
;
10153 label_expr
.X_add_symbol
= NULL
;
10154 label_expr
.X_add_number
= 0;
10156 expr1
.X_op
= O_constant
;
10157 expr1
.X_op_symbol
= NULL
;
10158 expr1
.X_add_symbol
= NULL
;
10159 expr1
.X_add_number
= 1;
10166 /* Fall through. */
10174 start_noreorder ();
10176 if (mips_opts
.micromips
)
10177 micromips_label_expr (&label_expr
);
10179 label_expr
.X_add_number
= 8;
10180 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10181 if (op
[0] == op
[1])
10182 macro_build (NULL
, "nop", "");
10184 move_register (op
[0], op
[1]);
10185 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10186 if (mips_opts
.micromips
)
10187 micromips_add_label ();
10204 if (!mips_opts
.micromips
)
10206 if (imm_expr
.X_add_number
>= -0x200
10207 && imm_expr
.X_add_number
< 0x200)
10209 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10210 (int) imm_expr
.X_add_number
);
10219 if (imm_expr
.X_add_number
>= -0x8000
10220 && imm_expr
.X_add_number
< 0x8000)
10222 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10227 load_register (AT
, &imm_expr
, dbl
);
10228 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10247 if (imm_expr
.X_add_number
>= 0
10248 && imm_expr
.X_add_number
< 0x10000)
10250 if (mask
!= M_NOR_I
)
10251 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10254 macro_build (&imm_expr
, "ori", "t,r,i",
10255 op
[0], op
[1], BFD_RELOC_LO16
);
10256 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10262 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10263 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10267 switch (imm_expr
.X_add_number
)
10270 macro_build (NULL
, "nop", "");
10273 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10277 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10278 (int) imm_expr
.X_add_number
);
10281 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10282 (unsigned long) imm_expr
.X_add_number
);
10291 gas_assert (mips_opts
.micromips
);
10292 macro_build_branch_ccl (mask
, &offset_expr
,
10293 EXTRACT_OPERAND (1, BCC
, *ip
));
10300 if (imm_expr
.X_add_number
== 0)
10306 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10308 /* Fall through. */
10311 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10316 /* Fall through. */
10319 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10320 else if (op
[0] == 0)
10321 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10325 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10326 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10327 &offset_expr
, AT
, ZERO
);
10337 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10342 /* Fall through. */
10344 /* Check for > max integer. */
10345 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10348 /* Result is always false. */
10350 macro_build (NULL
, "nop", "");
10352 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10355 ++imm_expr
.X_add_number
;
10359 if (mask
== M_BGEL_I
)
10361 if (imm_expr
.X_add_number
== 0)
10363 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10364 &offset_expr
, op
[0]);
10367 if (imm_expr
.X_add_number
== 1)
10369 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10370 &offset_expr
, op
[0]);
10373 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10376 /* result is always true */
10377 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10378 macro_build (&offset_expr
, "b", "p");
10383 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10384 &offset_expr
, AT
, ZERO
);
10389 /* Fall through. */
10393 else if (op
[0] == 0)
10394 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10395 &offset_expr
, ZERO
, op
[1]);
10399 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10400 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10401 &offset_expr
, AT
, ZERO
);
10407 /* Fall through. */
10411 && imm_expr
.X_add_number
== -1))
10413 ++imm_expr
.X_add_number
;
10417 if (mask
== M_BGEUL_I
)
10419 if (imm_expr
.X_add_number
== 0)
10421 else if (imm_expr
.X_add_number
== 1)
10422 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10423 &offset_expr
, op
[0], ZERO
);
10428 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10429 &offset_expr
, AT
, ZERO
);
10435 /* Fall through. */
10438 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10439 else if (op
[0] == 0)
10440 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10444 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10445 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10446 &offset_expr
, AT
, ZERO
);
10452 /* Fall through. */
10455 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10456 &offset_expr
, op
[0], ZERO
);
10457 else if (op
[0] == 0)
10462 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10463 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10464 &offset_expr
, AT
, ZERO
);
10470 /* Fall through. */
10473 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10474 else if (op
[0] == 0)
10475 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10479 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10480 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10481 &offset_expr
, AT
, ZERO
);
10487 /* Fall through. */
10489 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10491 ++imm_expr
.X_add_number
;
10495 if (mask
== M_BLTL_I
)
10497 if (imm_expr
.X_add_number
== 0)
10498 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10499 else if (imm_expr
.X_add_number
== 1)
10500 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10505 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10506 &offset_expr
, AT
, ZERO
);
10512 /* Fall through. */
10515 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10516 &offset_expr
, op
[0], ZERO
);
10517 else if (op
[0] == 0)
10522 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10523 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10524 &offset_expr
, AT
, ZERO
);
10530 /* Fall through. */
10534 && imm_expr
.X_add_number
== -1))
10536 ++imm_expr
.X_add_number
;
10540 if (mask
== M_BLTUL_I
)
10542 if (imm_expr
.X_add_number
== 0)
10544 else if (imm_expr
.X_add_number
== 1)
10545 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10546 &offset_expr
, op
[0], ZERO
);
10551 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10552 &offset_expr
, AT
, ZERO
);
10558 /* Fall through. */
10561 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10562 else if (op
[0] == 0)
10563 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10567 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10568 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10569 &offset_expr
, AT
, ZERO
);
10575 /* Fall through. */
10579 else if (op
[0] == 0)
10580 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10581 &offset_expr
, ZERO
, op
[1]);
10585 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10586 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10587 &offset_expr
, AT
, ZERO
);
10593 /* Fall through. */
10599 /* Fall through. */
10605 as_warn (_("divide by zero"));
10607 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10609 macro_build (NULL
, "break", BRK_FMT
, 7);
10613 start_noreorder ();
10616 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10617 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10621 if (mips_opts
.micromips
)
10622 micromips_label_expr (&label_expr
);
10624 label_expr
.X_add_number
= 8;
10625 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10626 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10627 macro_build (NULL
, "break", BRK_FMT
, 7);
10628 if (mips_opts
.micromips
)
10629 micromips_add_label ();
10631 expr1
.X_add_number
= -1;
10633 load_register (AT
, &expr1
, dbl
);
10634 if (mips_opts
.micromips
)
10635 micromips_label_expr (&label_expr
);
10637 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10638 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10641 expr1
.X_add_number
= 1;
10642 load_register (AT
, &expr1
, dbl
);
10643 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10647 expr1
.X_add_number
= 0x80000000;
10648 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10652 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10653 /* We want to close the noreorder block as soon as possible, so
10654 that later insns are available for delay slot filling. */
10659 if (mips_opts
.micromips
)
10660 micromips_label_expr (&label_expr
);
10662 label_expr
.X_add_number
= 8;
10663 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10664 macro_build (NULL
, "nop", "");
10666 /* We want to close the noreorder block as soon as possible, so
10667 that later insns are available for delay slot filling. */
10670 macro_build (NULL
, "break", BRK_FMT
, 6);
10672 if (mips_opts
.micromips
)
10673 micromips_add_label ();
10674 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10713 if (imm_expr
.X_add_number
== 0)
10715 as_warn (_("divide by zero"));
10717 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10719 macro_build (NULL
, "break", BRK_FMT
, 7);
10722 if (imm_expr
.X_add_number
== 1)
10724 if (strcmp (s2
, "mflo") == 0)
10725 move_register (op
[0], op
[1]);
10727 move_register (op
[0], ZERO
);
10730 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10732 if (strcmp (s2
, "mflo") == 0)
10733 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10735 move_register (op
[0], ZERO
);
10740 load_register (AT
, &imm_expr
, dbl
);
10741 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10742 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10761 start_noreorder ();
10764 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10765 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10766 /* We want to close the noreorder block as soon as possible, so
10767 that later insns are available for delay slot filling. */
10772 if (mips_opts
.micromips
)
10773 micromips_label_expr (&label_expr
);
10775 label_expr
.X_add_number
= 8;
10776 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10777 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10779 /* We want to close the noreorder block as soon as possible, so
10780 that later insns are available for delay slot filling. */
10782 macro_build (NULL
, "break", BRK_FMT
, 7);
10783 if (mips_opts
.micromips
)
10784 micromips_add_label ();
10786 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10791 /* Fall through. */
10797 /* Fall through. */
10800 /* Load the address of a symbol into a register. If breg is not
10801 zero, we then add a base register to it. */
10804 if (dbl
&& GPR_SIZE
== 32)
10805 as_warn (_("dla used to load 32-bit register; recommend using la "
10808 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10809 as_warn (_("la used to load 64-bit address; recommend using dla "
10812 if (small_offset_p (0, align
, 16))
10814 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10815 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10819 if (mips_opts
.at
&& (op
[0] == breg
))
10827 if (offset_expr
.X_op
!= O_symbol
10828 && offset_expr
.X_op
!= O_constant
)
10830 as_bad (_("expression too complex"));
10831 offset_expr
.X_op
= O_constant
;
10834 if (offset_expr
.X_op
== O_constant
)
10835 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10836 else if (mips_pic
== NO_PIC
)
10838 /* If this is a reference to a GP relative symbol, we want
10839 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10841 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10842 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10843 If we have a constant, we need two instructions anyhow,
10844 so we may as well always use the latter form.
10846 With 64bit address space and a usable $at we want
10847 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10848 lui $at,<sym> (BFD_RELOC_HI16_S)
10849 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10850 daddiu $at,<sym> (BFD_RELOC_LO16)
10852 daddu $tempreg,$tempreg,$at
10854 If $at is already in use, we use a path which is suboptimal
10855 on superscalar processors.
10856 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10857 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10859 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10861 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10863 For GP relative symbols in 64bit address space we can use
10864 the same sequence as in 32bit address space. */
10865 if (HAVE_64BIT_SYMBOLS
)
10867 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10868 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10870 relax_start (offset_expr
.X_add_symbol
);
10871 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10872 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10876 if (used_at
== 0 && mips_opts
.at
)
10878 macro_build (&offset_expr
, "lui", LUI_FMT
,
10879 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10880 macro_build (&offset_expr
, "lui", LUI_FMT
,
10881 AT
, BFD_RELOC_HI16_S
);
10882 macro_build (&offset_expr
, "daddiu", "t,r,j",
10883 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10884 macro_build (&offset_expr
, "daddiu", "t,r,j",
10885 AT
, AT
, BFD_RELOC_LO16
);
10886 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10887 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10892 macro_build (&offset_expr
, "lui", LUI_FMT
,
10893 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10894 macro_build (&offset_expr
, "daddiu", "t,r,j",
10895 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10896 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10897 macro_build (&offset_expr
, "daddiu", "t,r,j",
10898 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10899 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10900 macro_build (&offset_expr
, "daddiu", "t,r,j",
10901 tempreg
, tempreg
, BFD_RELOC_LO16
);
10904 if (mips_relax
.sequence
)
10909 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10910 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10912 relax_start (offset_expr
.X_add_symbol
);
10913 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10914 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10917 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10918 as_bad (_("offset too large"));
10919 macro_build_lui (&offset_expr
, tempreg
);
10920 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10921 tempreg
, tempreg
, BFD_RELOC_LO16
);
10922 if (mips_relax
.sequence
)
10926 else if (!mips_big_got
&& !HAVE_NEWABI
)
10928 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10930 /* If this is a reference to an external symbol, and there
10931 is no constant, we want
10932 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10933 or for lca or if tempreg is PIC_CALL_REG
10934 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10935 For a local symbol, we want
10936 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10938 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10940 If we have a small constant, and this is a reference to
10941 an external symbol, we want
10942 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10944 addiu $tempreg,$tempreg,<constant>
10945 For a local symbol, we want the same instruction
10946 sequence, but we output a BFD_RELOC_LO16 reloc on the
10949 If we have a large constant, and this is a reference to
10950 an external symbol, we want
10951 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10952 lui $at,<hiconstant>
10953 addiu $at,$at,<loconstant>
10954 addu $tempreg,$tempreg,$at
10955 For a local symbol, we want the same instruction
10956 sequence, but we output a BFD_RELOC_LO16 reloc on the
10960 if (offset_expr
.X_add_number
== 0)
10962 if (mips_pic
== SVR4_PIC
10964 && (call
|| tempreg
== PIC_CALL_REG
))
10965 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10967 relax_start (offset_expr
.X_add_symbol
);
10968 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10969 lw_reloc_type
, mips_gp_register
);
10972 /* We're going to put in an addu instruction using
10973 tempreg, so we may as well insert the nop right
10978 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10979 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10981 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10982 tempreg
, tempreg
, BFD_RELOC_LO16
);
10984 /* FIXME: If breg == 0, and the next instruction uses
10985 $tempreg, then if this variant case is used an extra
10986 nop will be generated. */
10988 else if (offset_expr
.X_add_number
>= -0x8000
10989 && offset_expr
.X_add_number
< 0x8000)
10991 load_got_offset (tempreg
, &offset_expr
);
10993 add_got_offset (tempreg
, &offset_expr
);
10997 expr1
.X_add_number
= offset_expr
.X_add_number
;
10998 offset_expr
.X_add_number
=
10999 SEXT_16BIT (offset_expr
.X_add_number
);
11000 load_got_offset (tempreg
, &offset_expr
);
11001 offset_expr
.X_add_number
= expr1
.X_add_number
;
11002 /* If we are going to add in a base register, and the
11003 target register and the base register are the same,
11004 then we are using AT as a temporary register. Since
11005 we want to load the constant into AT, we add our
11006 current AT (from the global offset table) and the
11007 register into the register now, and pretend we were
11008 not using a base register. */
11012 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11017 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11021 else if (!mips_big_got
&& HAVE_NEWABI
)
11023 int add_breg_early
= 0;
11025 /* If this is a reference to an external, and there is no
11026 constant, or local symbol (*), with or without a
11028 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11029 or for lca or if tempreg is PIC_CALL_REG
11030 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11032 If we have a small constant, and this is a reference to
11033 an external symbol, we want
11034 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11035 addiu $tempreg,$tempreg,<constant>
11037 If we have a large constant, and this is a reference to
11038 an external symbol, we want
11039 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11040 lui $at,<hiconstant>
11041 addiu $at,$at,<loconstant>
11042 addu $tempreg,$tempreg,$at
11044 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11045 local symbols, even though it introduces an additional
11048 if (offset_expr
.X_add_number
)
11050 expr1
.X_add_number
= offset_expr
.X_add_number
;
11051 offset_expr
.X_add_number
= 0;
11053 relax_start (offset_expr
.X_add_symbol
);
11054 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11055 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11057 if (expr1
.X_add_number
>= -0x8000
11058 && expr1
.X_add_number
< 0x8000)
11060 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11061 tempreg
, tempreg
, BFD_RELOC_LO16
);
11063 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11067 /* If we are going to add in a base register, and the
11068 target register and the base register are the same,
11069 then we are using AT as a temporary register. Since
11070 we want to load the constant into AT, we add our
11071 current AT (from the global offset table) and the
11072 register into the register now, and pretend we were
11073 not using a base register. */
11078 gas_assert (tempreg
== AT
);
11079 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11082 add_breg_early
= 1;
11085 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11086 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11092 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11095 offset_expr
.X_add_number
= expr1
.X_add_number
;
11097 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11098 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11099 if (add_breg_early
)
11101 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11102 op
[0], tempreg
, breg
);
11108 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11110 relax_start (offset_expr
.X_add_symbol
);
11111 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11112 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11114 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11115 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11120 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11121 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11124 else if (mips_big_got
&& !HAVE_NEWABI
)
11127 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11128 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11129 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11131 /* This is the large GOT case. If this is a reference to an
11132 external symbol, and there is no constant, we want
11133 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11134 addu $tempreg,$tempreg,$gp
11135 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11136 or for lca or if tempreg is PIC_CALL_REG
11137 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11138 addu $tempreg,$tempreg,$gp
11139 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11140 For a local symbol, we want
11141 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11143 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11145 If we have a small constant, and this is a reference to
11146 an external symbol, we want
11147 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11148 addu $tempreg,$tempreg,$gp
11149 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11151 addiu $tempreg,$tempreg,<constant>
11152 For a local symbol, we want
11153 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11155 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11157 If we have a large constant, and this is a reference to
11158 an external symbol, we want
11159 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11160 addu $tempreg,$tempreg,$gp
11161 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11162 lui $at,<hiconstant>
11163 addiu $at,$at,<loconstant>
11164 addu $tempreg,$tempreg,$at
11165 For a local symbol, we want
11166 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11167 lui $at,<hiconstant>
11168 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11169 addu $tempreg,$tempreg,$at
11172 expr1
.X_add_number
= offset_expr
.X_add_number
;
11173 offset_expr
.X_add_number
= 0;
11174 relax_start (offset_expr
.X_add_symbol
);
11175 gpdelay
= reg_needs_delay (mips_gp_register
);
11176 if (expr1
.X_add_number
== 0 && breg
== 0
11177 && (call
|| tempreg
== PIC_CALL_REG
))
11179 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11180 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11182 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11183 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11184 tempreg
, tempreg
, mips_gp_register
);
11185 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11186 tempreg
, lw_reloc_type
, tempreg
);
11187 if (expr1
.X_add_number
== 0)
11191 /* We're going to put in an addu instruction using
11192 tempreg, so we may as well insert the nop right
11197 else if (expr1
.X_add_number
>= -0x8000
11198 && expr1
.X_add_number
< 0x8000)
11201 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11202 tempreg
, tempreg
, BFD_RELOC_LO16
);
11208 /* If we are going to add in a base register, and the
11209 target register and the base register are the same,
11210 then we are using AT as a temporary register. Since
11211 we want to load the constant into AT, we add our
11212 current AT (from the global offset table) and the
11213 register into the register now, and pretend we were
11214 not using a base register. */
11219 gas_assert (tempreg
== AT
);
11221 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11226 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11227 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11231 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11236 /* This is needed because this instruction uses $gp, but
11237 the first instruction on the main stream does not. */
11238 macro_build (NULL
, "nop", "");
11241 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11242 local_reloc_type
, mips_gp_register
);
11243 if (expr1
.X_add_number
>= -0x8000
11244 && expr1
.X_add_number
< 0x8000)
11247 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11248 tempreg
, tempreg
, BFD_RELOC_LO16
);
11249 /* FIXME: If add_number is 0, and there was no base
11250 register, the external symbol case ended with a load,
11251 so if the symbol turns out to not be external, and
11252 the next instruction uses tempreg, an unnecessary nop
11253 will be inserted. */
11259 /* We must add in the base register now, as in the
11260 external symbol case. */
11261 gas_assert (tempreg
== AT
);
11263 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11266 /* We set breg to 0 because we have arranged to add
11267 it in in both cases. */
11271 macro_build_lui (&expr1
, AT
);
11272 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11273 AT
, AT
, BFD_RELOC_LO16
);
11274 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11275 tempreg
, tempreg
, AT
);
11280 else if (mips_big_got
&& HAVE_NEWABI
)
11282 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11283 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11284 int add_breg_early
= 0;
11286 /* This is the large GOT case. If this is a reference to an
11287 external symbol, and there is no constant, we want
11288 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11289 add $tempreg,$tempreg,$gp
11290 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11291 or for lca or if tempreg is PIC_CALL_REG
11292 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11293 add $tempreg,$tempreg,$gp
11294 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11296 If we have a small constant, and this is a reference to
11297 an external symbol, we want
11298 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11299 add $tempreg,$tempreg,$gp
11300 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11301 addi $tempreg,$tempreg,<constant>
11303 If we have a large constant, and this is a reference to
11304 an external symbol, we want
11305 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11306 addu $tempreg,$tempreg,$gp
11307 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11308 lui $at,<hiconstant>
11309 addi $at,$at,<loconstant>
11310 add $tempreg,$tempreg,$at
11312 If we have NewABI, and we know it's a local symbol, we want
11313 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11314 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11315 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11317 relax_start (offset_expr
.X_add_symbol
);
11319 expr1
.X_add_number
= offset_expr
.X_add_number
;
11320 offset_expr
.X_add_number
= 0;
11322 if (expr1
.X_add_number
== 0 && breg
== 0
11323 && (call
|| tempreg
== PIC_CALL_REG
))
11325 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11326 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11328 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11329 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11330 tempreg
, tempreg
, mips_gp_register
);
11331 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11332 tempreg
, lw_reloc_type
, tempreg
);
11334 if (expr1
.X_add_number
== 0)
11336 else if (expr1
.X_add_number
>= -0x8000
11337 && expr1
.X_add_number
< 0x8000)
11339 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11340 tempreg
, tempreg
, BFD_RELOC_LO16
);
11342 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11346 /* If we are going to add in a base register, and the
11347 target register and the base register are the same,
11348 then we are using AT as a temporary register. Since
11349 we want to load the constant into AT, we add our
11350 current AT (from the global offset table) and the
11351 register into the register now, and pretend we were
11352 not using a base register. */
11357 gas_assert (tempreg
== AT
);
11358 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11361 add_breg_early
= 1;
11364 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11365 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11370 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11373 offset_expr
.X_add_number
= expr1
.X_add_number
;
11374 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11375 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11376 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11377 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11378 if (add_breg_early
)
11380 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11381 op
[0], tempreg
, breg
);
11391 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11395 gas_assert (!mips_opts
.micromips
);
11396 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11400 gas_assert (!mips_opts
.micromips
);
11401 macro_build (NULL
, "c2", "C", 0x02);
11405 gas_assert (!mips_opts
.micromips
);
11406 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11410 gas_assert (!mips_opts
.micromips
);
11411 macro_build (NULL
, "c2", "C", 3);
11415 gas_assert (!mips_opts
.micromips
);
11416 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11420 /* The j instruction may not be used in PIC code, since it
11421 requires an absolute address. We convert it to a b
11423 if (mips_pic
== NO_PIC
)
11424 macro_build (&offset_expr
, "j", "a");
11426 macro_build (&offset_expr
, "b", "p");
11429 /* The jal instructions must be handled as macros because when
11430 generating PIC code they expand to multi-instruction
11431 sequences. Normally they are simple instructions. */
11435 /* Fall through. */
11437 gas_assert (mips_opts
.micromips
);
11438 if (mips_opts
.insn32
)
11440 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11448 /* Fall through. */
11451 if (mips_pic
== NO_PIC
)
11453 s
= jals
? "jalrs" : "jalr";
11454 if (mips_opts
.micromips
11455 && !mips_opts
.insn32
11457 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11458 macro_build (NULL
, s
, "mj", op
[1]);
11460 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11464 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11465 && mips_cprestore_offset
>= 0);
11467 if (op
[1] != PIC_CALL_REG
)
11468 as_warn (_("MIPS PIC call to register other than $25"));
11470 s
= ((mips_opts
.micromips
11471 && !mips_opts
.insn32
11472 && (!mips_opts
.noreorder
|| cprestore
))
11473 ? "jalrs" : "jalr");
11474 if (mips_opts
.micromips
11475 && !mips_opts
.insn32
11477 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11478 macro_build (NULL
, s
, "mj", op
[1]);
11480 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11481 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11483 if (mips_cprestore_offset
< 0)
11484 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11487 if (!mips_frame_reg_valid
)
11489 as_warn (_("no .frame pseudo-op used in PIC code"));
11490 /* Quiet this warning. */
11491 mips_frame_reg_valid
= 1;
11493 if (!mips_cprestore_valid
)
11495 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11496 /* Quiet this warning. */
11497 mips_cprestore_valid
= 1;
11499 if (mips_opts
.noreorder
)
11500 macro_build (NULL
, "nop", "");
11501 expr1
.X_add_number
= mips_cprestore_offset
;
11502 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11505 HAVE_64BIT_ADDRESSES
);
11513 gas_assert (mips_opts
.micromips
);
11514 if (mips_opts
.insn32
)
11516 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11520 /* Fall through. */
11522 if (mips_pic
== NO_PIC
)
11523 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11524 else if (mips_pic
== SVR4_PIC
)
11526 /* If this is a reference to an external symbol, and we are
11527 using a small GOT, we want
11528 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11532 lw $gp,cprestore($sp)
11533 The cprestore value is set using the .cprestore
11534 pseudo-op. If we are using a big GOT, we want
11535 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11537 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11541 lw $gp,cprestore($sp)
11542 If the symbol is not external, we want
11543 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11545 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11548 lw $gp,cprestore($sp)
11550 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11551 sequences above, minus nops, unless the symbol is local,
11552 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11558 relax_start (offset_expr
.X_add_symbol
);
11559 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11560 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11563 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11564 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11570 relax_start (offset_expr
.X_add_symbol
);
11571 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11572 BFD_RELOC_MIPS_CALL_HI16
);
11573 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11574 PIC_CALL_REG
, mips_gp_register
);
11575 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11576 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11579 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11580 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11582 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11583 PIC_CALL_REG
, PIC_CALL_REG
,
11584 BFD_RELOC_MIPS_GOT_OFST
);
11588 macro_build_jalr (&offset_expr
, 0);
11592 relax_start (offset_expr
.X_add_symbol
);
11595 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11596 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11605 gpdelay
= reg_needs_delay (mips_gp_register
);
11606 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11607 BFD_RELOC_MIPS_CALL_HI16
);
11608 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11609 PIC_CALL_REG
, mips_gp_register
);
11610 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11611 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11616 macro_build (NULL
, "nop", "");
11618 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11619 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11622 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11623 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11625 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11627 if (mips_cprestore_offset
< 0)
11628 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11631 if (!mips_frame_reg_valid
)
11633 as_warn (_("no .frame pseudo-op used in PIC code"));
11634 /* Quiet this warning. */
11635 mips_frame_reg_valid
= 1;
11637 if (!mips_cprestore_valid
)
11639 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11640 /* Quiet this warning. */
11641 mips_cprestore_valid
= 1;
11643 if (mips_opts
.noreorder
)
11644 macro_build (NULL
, "nop", "");
11645 expr1
.X_add_number
= mips_cprestore_offset
;
11646 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11649 HAVE_64BIT_ADDRESSES
);
11653 else if (mips_pic
== VXWORKS_PIC
)
11654 as_bad (_("non-PIC jump used in PIC library"));
11761 gas_assert (!mips_opts
.micromips
);
11764 /* Itbl support may require additional care here. */
11770 /* Itbl support may require additional care here. */
11776 offbits
= (mips_opts
.micromips
? 12
11777 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11779 /* Itbl support may require additional care here. */
11783 gas_assert (!mips_opts
.micromips
);
11786 /* Itbl support may require additional care here. */
11792 offbits
= (mips_opts
.micromips
? 12 : 16);
11797 offbits
= (mips_opts
.micromips
? 12 : 16);
11802 /* Itbl support may require additional care here. */
11808 offbits
= (mips_opts
.micromips
? 12
11809 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11811 /* Itbl support may require additional care here. */
11817 /* Itbl support may require additional care here. */
11823 /* Itbl support may require additional care here. */
11829 offbits
= (mips_opts
.micromips
? 12 : 16);
11834 offbits
= (mips_opts
.micromips
? 12 : 16);
11839 offbits
= (mips_opts
.micromips
? 12
11840 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11846 offbits
= (mips_opts
.micromips
? 12
11847 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11853 offbits
= (mips_opts
.micromips
? 12 : 16);
11856 gas_assert (mips_opts
.micromips
);
11863 gas_assert (mips_opts
.micromips
);
11870 gas_assert (mips_opts
.micromips
);
11876 gas_assert (mips_opts
.micromips
);
11883 /* We don't want to use $0 as tempreg. */
11884 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11887 tempreg
= op
[0] + lp
;
11903 gas_assert (!mips_opts
.micromips
);
11906 /* Itbl support may require additional care here. */
11912 /* Itbl support may require additional care here. */
11918 offbits
= (mips_opts
.micromips
? 12
11919 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11921 /* Itbl support may require additional care here. */
11925 gas_assert (!mips_opts
.micromips
);
11928 /* Itbl support may require additional care here. */
11934 offbits
= (mips_opts
.micromips
? 12 : 16);
11939 offbits
= (mips_opts
.micromips
? 12 : 16);
11944 offbits
= (mips_opts
.micromips
? 12
11945 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11951 offbits
= (mips_opts
.micromips
? 12
11952 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11957 fmt
= (mips_opts
.micromips
? "k,~(b)"
11958 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11960 offbits
= (mips_opts
.micromips
? 12
11961 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11971 fmt
= (mips_opts
.micromips
? "k,~(b)"
11972 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11974 offbits
= (mips_opts
.micromips
? 12
11975 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11987 /* Itbl support may require additional care here. */
11992 offbits
= (mips_opts
.micromips
? 12
11993 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11995 /* Itbl support may require additional care here. */
12001 /* Itbl support may require additional care here. */
12005 gas_assert (!mips_opts
.micromips
);
12008 /* Itbl support may require additional care here. */
12014 offbits
= (mips_opts
.micromips
? 12 : 16);
12019 offbits
= (mips_opts
.micromips
? 12 : 16);
12022 gas_assert (mips_opts
.micromips
);
12028 gas_assert (mips_opts
.micromips
);
12034 gas_assert (mips_opts
.micromips
);
12040 gas_assert (mips_opts
.micromips
);
12049 if (small_offset_p (0, align
, 16))
12051 /* The first case exists for M_LD_AB and M_SD_AB, which are
12052 macros for o32 but which should act like normal instructions
12055 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12056 offset_reloc
[1], offset_reloc
[2], breg
);
12057 else if (small_offset_p (0, align
, offbits
))
12060 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12062 macro_build (NULL
, s
, fmt
, op
[0],
12063 (int) offset_expr
.X_add_number
, breg
);
12069 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12070 tempreg
, breg
, -1, offset_reloc
[0],
12071 offset_reloc
[1], offset_reloc
[2]);
12073 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12075 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12083 if (offset_expr
.X_op
!= O_constant
12084 && offset_expr
.X_op
!= O_symbol
)
12086 as_bad (_("expression too complex"));
12087 offset_expr
.X_op
= O_constant
;
12090 if (HAVE_32BIT_ADDRESSES
12091 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12095 sprintf_vma (value
, offset_expr
.X_add_number
);
12096 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12099 /* A constant expression in PIC code can be handled just as it
12100 is in non PIC code. */
12101 if (offset_expr
.X_op
== O_constant
)
12103 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12104 offbits
== 0 ? 16 : offbits
);
12105 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12107 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12109 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12110 tempreg
, tempreg
, breg
);
12113 if (offset_expr
.X_add_number
!= 0)
12114 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12115 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12116 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12118 else if (offbits
== 16)
12119 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12121 macro_build (NULL
, s
, fmt
, op
[0],
12122 (int) offset_expr
.X_add_number
, tempreg
);
12124 else if (offbits
!= 16)
12126 /* The offset field is too narrow to be used for a low-part
12127 relocation, so load the whole address into the auxiliary
12129 load_address (tempreg
, &offset_expr
, &used_at
);
12131 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12132 tempreg
, tempreg
, breg
);
12134 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12136 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12138 else if (mips_pic
== NO_PIC
)
12140 /* If this is a reference to a GP relative symbol, and there
12141 is no base register, we want
12142 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12143 Otherwise, if there is no base register, we want
12144 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12145 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12146 If we have a constant, we need two instructions anyhow,
12147 so we always use the latter form.
12149 If we have a base register, and this is a reference to a
12150 GP relative symbol, we want
12151 addu $tempreg,$breg,$gp
12152 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12154 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12155 addu $tempreg,$tempreg,$breg
12156 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12157 With a constant we always use the latter case.
12159 With 64bit address space and no base register and $at usable,
12161 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12162 lui $at,<sym> (BFD_RELOC_HI16_S)
12163 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12166 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12167 If we have a base register, we want
12168 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12169 lui $at,<sym> (BFD_RELOC_HI16_S)
12170 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12174 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12176 Without $at we can't generate the optimal path for superscalar
12177 processors here since this would require two temporary registers.
12178 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12179 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12181 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12183 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12184 If we have a base register, we want
12185 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12186 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12188 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12190 daddu $tempreg,$tempreg,$breg
12191 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12193 For GP relative symbols in 64bit address space we can use
12194 the same sequence as in 32bit address space. */
12195 if (HAVE_64BIT_SYMBOLS
)
12197 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12198 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12200 relax_start (offset_expr
.X_add_symbol
);
12203 macro_build (&offset_expr
, s
, fmt
, op
[0],
12204 BFD_RELOC_GPREL16
, mips_gp_register
);
12208 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12209 tempreg
, breg
, mips_gp_register
);
12210 macro_build (&offset_expr
, s
, fmt
, op
[0],
12211 BFD_RELOC_GPREL16
, tempreg
);
12216 if (used_at
== 0 && mips_opts
.at
)
12218 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12219 BFD_RELOC_MIPS_HIGHEST
);
12220 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12222 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12223 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12225 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12226 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12227 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12228 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12234 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12235 BFD_RELOC_MIPS_HIGHEST
);
12236 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12237 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12238 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12239 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12240 tempreg
, BFD_RELOC_HI16_S
);
12241 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12243 macro_build (NULL
, "daddu", "d,v,t",
12244 tempreg
, tempreg
, breg
);
12245 macro_build (&offset_expr
, s
, fmt
, op
[0],
12246 BFD_RELOC_LO16
, tempreg
);
12249 if (mips_relax
.sequence
)
12256 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12257 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12259 relax_start (offset_expr
.X_add_symbol
);
12260 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12264 macro_build_lui (&offset_expr
, tempreg
);
12265 macro_build (&offset_expr
, s
, fmt
, op
[0],
12266 BFD_RELOC_LO16
, tempreg
);
12267 if (mips_relax
.sequence
)
12272 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12273 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12275 relax_start (offset_expr
.X_add_symbol
);
12276 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12277 tempreg
, breg
, mips_gp_register
);
12278 macro_build (&offset_expr
, s
, fmt
, op
[0],
12279 BFD_RELOC_GPREL16
, tempreg
);
12282 macro_build_lui (&offset_expr
, tempreg
);
12283 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12284 tempreg
, tempreg
, breg
);
12285 macro_build (&offset_expr
, s
, fmt
, op
[0],
12286 BFD_RELOC_LO16
, tempreg
);
12287 if (mips_relax
.sequence
)
12291 else if (!mips_big_got
)
12293 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12295 /* If this is a reference to an external symbol, we want
12296 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12298 <op> op[0],0($tempreg)
12300 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12302 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12303 <op> op[0],0($tempreg)
12305 For NewABI, we want
12306 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12307 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12309 If there is a base register, we add it to $tempreg before
12310 the <op>. If there is a constant, we stick it in the
12311 <op> instruction. We don't handle constants larger than
12312 16 bits, because we have no way to load the upper 16 bits
12313 (actually, we could handle them for the subset of cases
12314 in which we are not using $at). */
12315 gas_assert (offset_expr
.X_op
== O_symbol
);
12318 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12319 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12321 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12322 tempreg
, tempreg
, breg
);
12323 macro_build (&offset_expr
, s
, fmt
, op
[0],
12324 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12327 expr1
.X_add_number
= offset_expr
.X_add_number
;
12328 offset_expr
.X_add_number
= 0;
12329 if (expr1
.X_add_number
< -0x8000
12330 || expr1
.X_add_number
>= 0x8000)
12331 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12332 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12333 lw_reloc_type
, mips_gp_register
);
12335 relax_start (offset_expr
.X_add_symbol
);
12337 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12338 tempreg
, BFD_RELOC_LO16
);
12341 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12342 tempreg
, tempreg
, breg
);
12343 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12345 else if (mips_big_got
&& !HAVE_NEWABI
)
12349 /* If this is a reference to an external symbol, we want
12350 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12351 addu $tempreg,$tempreg,$gp
12352 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12353 <op> op[0],0($tempreg)
12355 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12357 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12358 <op> op[0],0($tempreg)
12359 If there is a base register, we add it to $tempreg before
12360 the <op>. If there is a constant, we stick it in the
12361 <op> instruction. We don't handle constants larger than
12362 16 bits, because we have no way to load the upper 16 bits
12363 (actually, we could handle them for the subset of cases
12364 in which we are not using $at). */
12365 gas_assert (offset_expr
.X_op
== O_symbol
);
12366 expr1
.X_add_number
= offset_expr
.X_add_number
;
12367 offset_expr
.X_add_number
= 0;
12368 if (expr1
.X_add_number
< -0x8000
12369 || expr1
.X_add_number
>= 0x8000)
12370 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12371 gpdelay
= reg_needs_delay (mips_gp_register
);
12372 relax_start (offset_expr
.X_add_symbol
);
12373 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12374 BFD_RELOC_MIPS_GOT_HI16
);
12375 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12377 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12378 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12381 macro_build (NULL
, "nop", "");
12382 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12383 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12385 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12386 tempreg
, BFD_RELOC_LO16
);
12390 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12391 tempreg
, tempreg
, breg
);
12392 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12394 else if (mips_big_got
&& HAVE_NEWABI
)
12396 /* If this is a reference to an external symbol, we want
12397 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12398 add $tempreg,$tempreg,$gp
12399 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12400 <op> op[0],<ofst>($tempreg)
12401 Otherwise, for local symbols, we want:
12402 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12403 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12404 gas_assert (offset_expr
.X_op
== O_symbol
);
12405 expr1
.X_add_number
= offset_expr
.X_add_number
;
12406 offset_expr
.X_add_number
= 0;
12407 if (expr1
.X_add_number
< -0x8000
12408 || expr1
.X_add_number
>= 0x8000)
12409 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12410 relax_start (offset_expr
.X_add_symbol
);
12411 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12412 BFD_RELOC_MIPS_GOT_HI16
);
12413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12415 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12416 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12418 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12419 tempreg
, tempreg
, breg
);
12420 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12423 offset_expr
.X_add_number
= expr1
.X_add_number
;
12424 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12425 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12427 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12428 tempreg
, tempreg
, breg
);
12429 macro_build (&offset_expr
, s
, fmt
, op
[0],
12430 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12439 gas_assert (mips_opts
.micromips
);
12440 gas_assert (mips_opts
.insn32
);
12441 start_noreorder ();
12442 macro_build (NULL
, "jr", "s", RA
);
12443 expr1
.X_add_number
= op
[0] << 2;
12444 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12449 gas_assert (mips_opts
.micromips
);
12450 gas_assert (mips_opts
.insn32
);
12451 macro_build (NULL
, "jr", "s", op
[0]);
12452 if (mips_opts
.noreorder
)
12453 macro_build (NULL
, "nop", "");
12458 load_register (op
[0], &imm_expr
, 0);
12462 load_register (op
[0], &imm_expr
, 1);
12466 if (imm_expr
.X_op
== O_constant
)
12469 load_register (AT
, &imm_expr
, 0);
12470 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12475 gas_assert (imm_expr
.X_op
== O_absent
12476 && offset_expr
.X_op
== O_symbol
12477 && strcmp (segment_name (S_GET_SEGMENT
12478 (offset_expr
.X_add_symbol
)),
12480 && offset_expr
.X_add_number
== 0);
12481 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12482 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12487 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12488 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12489 order 32 bits of the value and the low order 32 bits are either
12490 zero or in OFFSET_EXPR. */
12491 if (imm_expr
.X_op
== O_constant
)
12493 if (GPR_SIZE
== 64)
12494 load_register (op
[0], &imm_expr
, 1);
12499 if (target_big_endian
)
12511 load_register (hreg
, &imm_expr
, 0);
12514 if (offset_expr
.X_op
== O_absent
)
12515 move_register (lreg
, 0);
12518 gas_assert (offset_expr
.X_op
== O_constant
);
12519 load_register (lreg
, &offset_expr
, 0);
12525 gas_assert (imm_expr
.X_op
== O_absent
);
12527 /* We know that sym is in the .rdata section. First we get the
12528 upper 16 bits of the address. */
12529 if (mips_pic
== NO_PIC
)
12531 macro_build_lui (&offset_expr
, AT
);
12536 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12537 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12541 /* Now we load the register(s). */
12542 if (GPR_SIZE
== 64)
12545 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12546 BFD_RELOC_LO16
, AT
);
12551 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12552 BFD_RELOC_LO16
, AT
);
12555 /* FIXME: How in the world do we deal with the possible
12557 offset_expr
.X_add_number
+= 4;
12558 macro_build (&offset_expr
, "lw", "t,o(b)",
12559 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12565 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12566 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12567 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12568 the value and the low order 32 bits are either zero or in
12570 if (imm_expr
.X_op
== O_constant
)
12573 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12574 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12575 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12578 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12579 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12580 else if (FPR_SIZE
!= 32)
12581 as_bad (_("Unable to generate `%s' compliant code "
12583 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12585 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12586 if (offset_expr
.X_op
== O_absent
)
12587 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12590 gas_assert (offset_expr
.X_op
== O_constant
);
12591 load_register (AT
, &offset_expr
, 0);
12592 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12598 gas_assert (imm_expr
.X_op
== O_absent
12599 && offset_expr
.X_op
== O_symbol
12600 && offset_expr
.X_add_number
== 0);
12601 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12602 if (strcmp (s
, ".lit8") == 0)
12604 op
[2] = mips_gp_register
;
12605 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12606 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12607 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12611 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12613 if (mips_pic
!= NO_PIC
)
12614 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12615 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12618 /* FIXME: This won't work for a 64 bit address. */
12619 macro_build_lui (&offset_expr
, AT
);
12623 offset_reloc
[0] = BFD_RELOC_LO16
;
12624 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12625 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12632 * The MIPS assembler seems to check for X_add_number not
12633 * being double aligned and generating:
12634 * lui at,%hi(foo+1)
12636 * addiu at,at,%lo(foo+1)
12639 * But, the resulting address is the same after relocation so why
12640 * generate the extra instruction?
12642 /* Itbl support may require additional care here. */
12645 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12654 gas_assert (!mips_opts
.micromips
);
12655 /* Itbl support may require additional care here. */
12658 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12678 if (GPR_SIZE
== 64)
12688 if (GPR_SIZE
== 64)
12696 /* Even on a big endian machine $fn comes before $fn+1. We have
12697 to adjust when loading from memory. We set coproc if we must
12698 load $fn+1 first. */
12699 /* Itbl support may require additional care here. */
12700 if (!target_big_endian
)
12704 if (small_offset_p (0, align
, 16))
12707 if (!small_offset_p (4, align
, 16))
12709 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12710 -1, offset_reloc
[0], offset_reloc
[1],
12712 expr1
.X_add_number
= 0;
12716 offset_reloc
[0] = BFD_RELOC_LO16
;
12717 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12718 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12720 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12722 ep
->X_add_number
+= 4;
12723 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12724 offset_reloc
[1], offset_reloc
[2], breg
);
12725 ep
->X_add_number
-= 4;
12726 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12727 offset_reloc
[1], offset_reloc
[2], breg
);
12731 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12732 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12734 ep
->X_add_number
+= 4;
12735 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12736 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12742 if (offset_expr
.X_op
!= O_symbol
12743 && offset_expr
.X_op
!= O_constant
)
12745 as_bad (_("expression too complex"));
12746 offset_expr
.X_op
= O_constant
;
12749 if (HAVE_32BIT_ADDRESSES
12750 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12754 sprintf_vma (value
, offset_expr
.X_add_number
);
12755 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12758 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12760 /* If this is a reference to a GP relative symbol, we want
12761 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12762 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12763 If we have a base register, we use this
12765 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12766 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12767 If this is not a GP relative symbol, we want
12768 lui $at,<sym> (BFD_RELOC_HI16_S)
12769 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12770 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12771 If there is a base register, we add it to $at after the
12772 lui instruction. If there is a constant, we always use
12774 if (offset_expr
.X_op
== O_symbol
12775 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12776 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12778 relax_start (offset_expr
.X_add_symbol
);
12781 tempreg
= mips_gp_register
;
12785 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12786 AT
, breg
, mips_gp_register
);
12791 /* Itbl support may require additional care here. */
12792 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12793 BFD_RELOC_GPREL16
, tempreg
);
12794 offset_expr
.X_add_number
+= 4;
12796 /* Set mips_optimize to 2 to avoid inserting an
12798 hold_mips_optimize
= mips_optimize
;
12800 /* Itbl support may require additional care here. */
12801 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12802 BFD_RELOC_GPREL16
, tempreg
);
12803 mips_optimize
= hold_mips_optimize
;
12807 offset_expr
.X_add_number
-= 4;
12810 if (offset_high_part (offset_expr
.X_add_number
, 16)
12811 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12813 load_address (AT
, &offset_expr
, &used_at
);
12814 offset_expr
.X_op
= O_constant
;
12815 offset_expr
.X_add_number
= 0;
12818 macro_build_lui (&offset_expr
, AT
);
12820 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12821 /* Itbl support may require additional care here. */
12822 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12823 BFD_RELOC_LO16
, AT
);
12824 /* FIXME: How do we handle overflow here? */
12825 offset_expr
.X_add_number
+= 4;
12826 /* Itbl support may require additional care here. */
12827 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12828 BFD_RELOC_LO16
, AT
);
12829 if (mips_relax
.sequence
)
12832 else if (!mips_big_got
)
12834 /* If this is a reference to an external symbol, we want
12835 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12838 <op> op[0]+1,4($at)
12840 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12842 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12843 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12844 If there is a base register we add it to $at before the
12845 lwc1 instructions. If there is a constant we include it
12846 in the lwc1 instructions. */
12848 expr1
.X_add_number
= offset_expr
.X_add_number
;
12849 if (expr1
.X_add_number
< -0x8000
12850 || expr1
.X_add_number
>= 0x8000 - 4)
12851 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12852 load_got_offset (AT
, &offset_expr
);
12855 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12857 /* Set mips_optimize to 2 to avoid inserting an undesired
12859 hold_mips_optimize
= mips_optimize
;
12862 /* Itbl support may require additional care here. */
12863 relax_start (offset_expr
.X_add_symbol
);
12864 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12865 BFD_RELOC_LO16
, AT
);
12866 expr1
.X_add_number
+= 4;
12867 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12868 BFD_RELOC_LO16
, AT
);
12870 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12871 BFD_RELOC_LO16
, AT
);
12872 offset_expr
.X_add_number
+= 4;
12873 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12874 BFD_RELOC_LO16
, AT
);
12877 mips_optimize
= hold_mips_optimize
;
12879 else if (mips_big_got
)
12883 /* If this is a reference to an external symbol, we want
12884 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12886 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12889 <op> op[0]+1,4($at)
12891 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12893 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12894 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12895 If there is a base register we add it to $at before the
12896 lwc1 instructions. If there is a constant we include it
12897 in the lwc1 instructions. */
12899 expr1
.X_add_number
= offset_expr
.X_add_number
;
12900 offset_expr
.X_add_number
= 0;
12901 if (expr1
.X_add_number
< -0x8000
12902 || expr1
.X_add_number
>= 0x8000 - 4)
12903 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12904 gpdelay
= reg_needs_delay (mips_gp_register
);
12905 relax_start (offset_expr
.X_add_symbol
);
12906 macro_build (&offset_expr
, "lui", LUI_FMT
,
12907 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12908 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12909 AT
, AT
, mips_gp_register
);
12910 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12911 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12914 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12915 /* Itbl support may require additional care here. */
12916 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12917 BFD_RELOC_LO16
, AT
);
12918 expr1
.X_add_number
+= 4;
12920 /* Set mips_optimize to 2 to avoid inserting an undesired
12922 hold_mips_optimize
= mips_optimize
;
12924 /* Itbl support may require additional care here. */
12925 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12926 BFD_RELOC_LO16
, AT
);
12927 mips_optimize
= hold_mips_optimize
;
12928 expr1
.X_add_number
-= 4;
12931 offset_expr
.X_add_number
= expr1
.X_add_number
;
12933 macro_build (NULL
, "nop", "");
12934 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12935 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12938 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12939 /* Itbl support may require additional care here. */
12940 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12941 BFD_RELOC_LO16
, AT
);
12942 offset_expr
.X_add_number
+= 4;
12944 /* Set mips_optimize to 2 to avoid inserting an undesired
12946 hold_mips_optimize
= mips_optimize
;
12948 /* Itbl support may require additional care here. */
12949 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12950 BFD_RELOC_LO16
, AT
);
12951 mips_optimize
= hold_mips_optimize
;
12965 gas_assert (!mips_opts
.micromips
);
12970 /* New code added to support COPZ instructions.
12971 This code builds table entries out of the macros in mip_opcodes.
12972 R4000 uses interlocks to handle coproc delays.
12973 Other chips (like the R3000) require nops to be inserted for delays.
12975 FIXME: Currently, we require that the user handle delays.
12976 In order to fill delay slots for non-interlocked chips,
12977 we must have a way to specify delays based on the coprocessor.
12978 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12979 What are the side-effects of the cop instruction?
12980 What cache support might we have and what are its effects?
12981 Both coprocessor & memory require delays. how long???
12982 What registers are read/set/modified?
12984 If an itbl is provided to interpret cop instructions,
12985 this knowledge can be encoded in the itbl spec. */
12999 gas_assert (!mips_opts
.micromips
);
13000 /* For now we just do C (same as Cz). The parameter will be
13001 stored in insn_opcode by mips_ip. */
13002 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13006 move_register (op
[0], op
[1]);
13010 gas_assert (mips_opts
.micromips
);
13011 gas_assert (mips_opts
.insn32
);
13012 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13013 micromips_to_32_reg_m_map
[op
[1]]);
13014 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13015 micromips_to_32_reg_n_map
[op
[2]]);
13020 /* Fall through. */
13022 if (mips_opts
.arch
== CPU_R5900
)
13023 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13027 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13028 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13034 /* Fall through. */
13036 /* The MIPS assembler some times generates shifts and adds. I'm
13037 not trying to be that fancy. GCC should do this for us
13040 load_register (AT
, &imm_expr
, dbl
);
13041 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13042 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13047 /* Fall through. */
13054 /* Fall through. */
13057 start_noreorder ();
13060 load_register (AT
, &imm_expr
, dbl
);
13061 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13062 op
[1], imm
? AT
: op
[2]);
13063 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13064 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13065 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13067 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13070 if (mips_opts
.micromips
)
13071 micromips_label_expr (&label_expr
);
13073 label_expr
.X_add_number
= 8;
13074 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13075 macro_build (NULL
, "nop", "");
13076 macro_build (NULL
, "break", BRK_FMT
, 6);
13077 if (mips_opts
.micromips
)
13078 micromips_add_label ();
13081 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13086 /* Fall through. */
13093 /* Fall through. */
13096 start_noreorder ();
13099 load_register (AT
, &imm_expr
, dbl
);
13100 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13101 op
[1], imm
? AT
: op
[2]);
13102 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13103 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13105 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13108 if (mips_opts
.micromips
)
13109 micromips_label_expr (&label_expr
);
13111 label_expr
.X_add_number
= 8;
13112 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13113 macro_build (NULL
, "nop", "");
13114 macro_build (NULL
, "break", BRK_FMT
, 6);
13115 if (mips_opts
.micromips
)
13116 micromips_add_label ();
13122 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13124 if (op
[0] == op
[1])
13131 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13132 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13136 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13137 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13138 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13139 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13143 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13145 if (op
[0] == op
[1])
13152 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13153 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13157 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13158 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13159 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13160 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13169 rot
= imm_expr
.X_add_number
& 0x3f;
13170 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13172 rot
= (64 - rot
) & 0x3f;
13174 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13176 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13181 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13184 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13185 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13188 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13189 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13190 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13198 rot
= imm_expr
.X_add_number
& 0x1f;
13199 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13201 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13202 (32 - rot
) & 0x1f);
13207 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13211 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13212 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13213 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13218 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13220 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13224 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13225 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13226 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13227 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13231 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13233 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13237 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13238 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13239 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13240 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13249 rot
= imm_expr
.X_add_number
& 0x3f;
13250 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13253 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13255 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13260 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13263 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13264 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13267 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13268 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13269 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13277 rot
= imm_expr
.X_add_number
& 0x1f;
13278 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13280 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13285 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13289 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13290 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13291 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13297 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13298 else if (op
[2] == 0)
13299 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13302 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13303 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13308 if (imm_expr
.X_add_number
== 0)
13310 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13315 as_warn (_("instruction %s: result is always false"),
13316 ip
->insn_mo
->name
);
13317 move_register (op
[0], 0);
13320 if (CPU_HAS_SEQ (mips_opts
.arch
)
13321 && -512 <= imm_expr
.X_add_number
13322 && imm_expr
.X_add_number
< 512)
13324 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13325 (int) imm_expr
.X_add_number
);
13328 if (imm_expr
.X_add_number
>= 0
13329 && imm_expr
.X_add_number
< 0x10000)
13330 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13331 else if (imm_expr
.X_add_number
> -0x8000
13332 && imm_expr
.X_add_number
< 0)
13334 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13335 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13336 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13338 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13341 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13342 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13347 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13348 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13351 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13354 case M_SGE
: /* X >= Y <==> not (X < Y) */
13360 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13361 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13364 case M_SGE_I
: /* X >= I <==> not (X < I) */
13366 if (imm_expr
.X_add_number
>= -0x8000
13367 && imm_expr
.X_add_number
< 0x8000)
13368 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13369 op
[0], op
[1], BFD_RELOC_LO16
);
13372 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13373 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13377 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13380 case M_SGT
: /* X > Y <==> Y < X */
13386 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13389 case M_SGT_I
: /* X > I <==> I < X */
13396 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13397 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13400 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13406 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13407 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13410 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13417 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13418 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13419 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13423 if (imm_expr
.X_add_number
>= -0x8000
13424 && imm_expr
.X_add_number
< 0x8000)
13426 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13431 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13432 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13436 if (imm_expr
.X_add_number
>= -0x8000
13437 && imm_expr
.X_add_number
< 0x8000)
13439 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13444 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13445 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13450 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13451 else if (op
[2] == 0)
13452 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13455 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13456 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13461 if (imm_expr
.X_add_number
== 0)
13463 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13468 as_warn (_("instruction %s: result is always true"),
13469 ip
->insn_mo
->name
);
13470 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13471 op
[0], 0, BFD_RELOC_LO16
);
13474 if (CPU_HAS_SEQ (mips_opts
.arch
)
13475 && -512 <= imm_expr
.X_add_number
13476 && imm_expr
.X_add_number
< 512)
13478 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13479 (int) imm_expr
.X_add_number
);
13482 if (imm_expr
.X_add_number
>= 0
13483 && imm_expr
.X_add_number
< 0x10000)
13485 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13488 else if (imm_expr
.X_add_number
> -0x8000
13489 && imm_expr
.X_add_number
< 0)
13491 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13492 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13493 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13495 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13498 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13499 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13504 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13505 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13508 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13523 if (!mips_opts
.micromips
)
13525 if (imm_expr
.X_add_number
> -0x200
13526 && imm_expr
.X_add_number
<= 0x200)
13528 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13529 (int) -imm_expr
.X_add_number
);
13538 if (imm_expr
.X_add_number
> -0x8000
13539 && imm_expr
.X_add_number
<= 0x8000)
13541 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13542 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13547 load_register (AT
, &imm_expr
, dbl
);
13548 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13570 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13571 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13576 gas_assert (!mips_opts
.micromips
);
13577 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13581 * Is the double cfc1 instruction a bug in the mips assembler;
13582 * or is there a reason for it?
13584 start_noreorder ();
13585 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13586 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13587 macro_build (NULL
, "nop", "");
13588 expr1
.X_add_number
= 3;
13589 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13590 expr1
.X_add_number
= 2;
13591 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13592 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13593 macro_build (NULL
, "nop", "");
13594 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13596 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13597 macro_build (NULL
, "nop", "");
13614 offbits
= (mips_opts
.micromips
? 12 : 16);
13620 offbits
= (mips_opts
.micromips
? 12 : 16);
13632 offbits
= (mips_opts
.micromips
? 12 : 16);
13639 offbits
= (mips_opts
.micromips
? 12 : 16);
13645 large_offset
= !small_offset_p (off
, align
, offbits
);
13647 expr1
.X_add_number
= 0;
13652 if (small_offset_p (0, align
, 16))
13653 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13654 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13657 load_address (tempreg
, ep
, &used_at
);
13659 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13660 tempreg
, tempreg
, breg
);
13662 offset_reloc
[0] = BFD_RELOC_LO16
;
13663 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13664 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13669 else if (!ust
&& op
[0] == breg
)
13680 if (!target_big_endian
)
13681 ep
->X_add_number
+= off
;
13683 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13685 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13686 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13688 if (!target_big_endian
)
13689 ep
->X_add_number
-= off
;
13691 ep
->X_add_number
+= off
;
13693 macro_build (NULL
, s2
, "t,~(b)",
13694 tempreg
, (int) ep
->X_add_number
, breg
);
13696 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13697 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13699 /* If necessary, move the result in tempreg to the final destination. */
13700 if (!ust
&& op
[0] != tempreg
)
13702 /* Protect second load's delay slot. */
13704 move_register (op
[0], tempreg
);
13710 if (target_big_endian
== ust
)
13711 ep
->X_add_number
+= off
;
13712 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13713 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13714 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13716 /* For halfword transfers we need a temporary register to shuffle
13717 bytes. Unfortunately for M_USH_A we have none available before
13718 the next store as AT holds the base address. We deal with this
13719 case by clobbering TREG and then restoring it as with ULH. */
13720 tempreg
= ust
== large_offset
? op
[0] : AT
;
13722 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13724 if (target_big_endian
== ust
)
13725 ep
->X_add_number
-= off
;
13727 ep
->X_add_number
+= off
;
13728 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13729 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13731 /* For M_USH_A re-retrieve the LSB. */
13732 if (ust
&& large_offset
)
13734 if (target_big_endian
)
13735 ep
->X_add_number
+= off
;
13737 ep
->X_add_number
-= off
;
13738 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13739 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13741 /* For ULH and M_USH_A OR the LSB in. */
13742 if (!ust
|| large_offset
)
13744 tempreg
= !large_offset
? AT
: op
[0];
13745 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13746 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13751 /* FIXME: Check if this is one of the itbl macros, since they
13752 are added dynamically. */
13753 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13756 if (!mips_opts
.at
&& used_at
)
13757 as_bad (_("macro used $at after \".set noat\""));
13760 /* Implement macros in mips16 mode. */
13763 mips16_macro (struct mips_cl_insn
*ip
)
13765 const struct mips_operand_array
*operands
;
13770 const char *s
, *s2
, *s3
;
13771 unsigned int op
[MAX_OPERANDS
];
13774 mask
= ip
->insn_mo
->mask
;
13776 operands
= insn_operands (ip
);
13777 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13778 if (operands
->operand
[i
])
13779 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13783 expr1
.X_op
= O_constant
;
13784 expr1
.X_op_symbol
= NULL
;
13785 expr1
.X_add_symbol
= NULL
;
13786 expr1
.X_add_number
= 1;
13797 /* Fall through. */
13803 /* Fall through. */
13807 start_noreorder ();
13808 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13809 expr1
.X_add_number
= 2;
13810 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13811 macro_build (NULL
, "break", "6", 7);
13813 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13814 since that causes an overflow. We should do that as well,
13815 but I don't see how to do the comparisons without a temporary
13818 macro_build (NULL
, s
, "x", op
[0]);
13837 start_noreorder ();
13838 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13839 expr1
.X_add_number
= 2;
13840 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13841 macro_build (NULL
, "break", "6", 7);
13843 macro_build (NULL
, s2
, "x", op
[0]);
13848 /* Fall through. */
13850 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13851 macro_build (NULL
, "mflo", "x", op
[0]);
13859 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13860 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13864 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13865 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13869 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13870 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13892 goto do_reverse_branch
;
13896 goto do_reverse_branch
;
13908 goto do_reverse_branch
;
13919 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13920 macro_build (&offset_expr
, s2
, "p");
13947 goto do_addone_branch_i
;
13952 goto do_addone_branch_i
;
13967 goto do_addone_branch_i
;
13973 do_addone_branch_i
:
13974 ++imm_expr
.X_add_number
;
13977 macro_build (&imm_expr
, s
, s3
, op
[0]);
13978 macro_build (&offset_expr
, s2
, "p");
13982 expr1
.X_add_number
= 0;
13983 macro_build (&expr1
, "slti", "x,8", op
[1]);
13984 if (op
[0] != op
[1])
13985 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13986 expr1
.X_add_number
= 2;
13987 macro_build (&expr1
, "bteqz", "p");
13988 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13993 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13994 opcode bits in *OPCODE_EXTRA. */
13996 static struct mips_opcode
*
13997 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13998 ssize_t length
, unsigned int *opcode_extra
)
14000 char *name
, *dot
, *p
;
14001 unsigned int mask
, suffix
;
14003 struct mips_opcode
*insn
;
14005 /* Make a copy of the instruction so that we can fiddle with it. */
14006 name
= xstrndup (start
, length
);
14008 /* Look up the instruction as-is. */
14009 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14013 dot
= strchr (name
, '.');
14016 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14017 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14018 if (*p
== 0 && mask
!= 0)
14021 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14023 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14025 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14031 if (mips_opts
.micromips
)
14033 /* See if there's an instruction size override suffix,
14034 either `16' or `32', at the end of the mnemonic proper,
14035 that defines the operation, i.e. before the first `.'
14036 character if any. Strip it and retry. */
14037 opend
= dot
!= NULL
? dot
- name
: length
;
14038 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14040 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14046 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14047 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14050 forced_insn_length
= suffix
;
14062 /* Assemble an instruction into its binary format. If the instruction
14063 is a macro, set imm_expr and offset_expr to the values associated
14064 with "I" and "A" operands respectively. Otherwise store the value
14065 of the relocatable field (if any) in offset_expr. In both cases
14066 set offset_reloc to the relocation operators applied to offset_expr. */
14069 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14071 const struct mips_opcode
*first
, *past
;
14072 struct hash_control
*hash
;
14075 struct mips_operand_token
*tokens
;
14076 unsigned int opcode_extra
;
14078 if (mips_opts
.micromips
)
14080 hash
= micromips_op_hash
;
14081 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14086 past
= &mips_opcodes
[NUMOPCODES
];
14088 forced_insn_length
= 0;
14091 /* We first try to match an instruction up to a space or to the end. */
14092 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14095 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14098 set_insn_error (0, _("unrecognized opcode"));
14102 if (strcmp (first
->name
, "li.s") == 0)
14104 else if (strcmp (first
->name
, "li.d") == 0)
14108 tokens
= mips_parse_arguments (str
+ end
, format
);
14112 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14113 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14114 set_insn_error (0, _("invalid operands"));
14116 obstack_free (&mips_operand_tokens
, tokens
);
14119 /* As for mips_ip, but used when assembling MIPS16 code.
14120 Also set forced_insn_length to the resulting instruction size in
14121 bytes if the user explicitly requested a small or extended instruction. */
14124 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14127 struct mips_opcode
*first
;
14128 struct mips_operand_token
*tokens
;
14131 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14153 else if (*s
== 'e')
14160 else if (*s
++ == ' ')
14162 set_insn_error (0, _("unrecognized opcode"));
14165 forced_insn_length
= l
;
14168 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14173 set_insn_error (0, _("unrecognized opcode"));
14177 tokens
= mips_parse_arguments (s
, 0);
14181 if (!match_mips16_insns (insn
, first
, tokens
))
14182 set_insn_error (0, _("invalid operands"));
14184 obstack_free (&mips_operand_tokens
, tokens
);
14187 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14188 NBITS is the number of significant bits in VAL. */
14190 static unsigned long
14191 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14196 val
&= (1U << nbits
) - 1;
14197 if (nbits
== 16 || nbits
== 9)
14199 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14202 else if (nbits
== 15)
14204 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14207 else if (nbits
== 6)
14209 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14212 return (extval
<< 16) | val
;
14215 /* Like decode_mips16_operand, but require the operand to be defined and
14216 require it to be an integer. */
14218 static const struct mips_int_operand
*
14219 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14221 const struct mips_operand
*operand
;
14223 operand
= decode_mips16_operand (type
, extended_p
);
14224 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14226 return (const struct mips_int_operand
*) operand
;
14229 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14232 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14233 bfd_reloc_code_real_type reloc
, offsetT sval
)
14235 int min_val
, max_val
;
14237 min_val
= mips_int_operand_min (operand
);
14238 max_val
= mips_int_operand_max (operand
);
14239 if (reloc
!= BFD_RELOC_UNUSED
)
14242 sval
= SEXT_16BIT (sval
);
14247 return (sval
>= min_val
14249 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14252 /* Install immediate value VAL into MIPS16 instruction *INSN,
14253 extending it if necessary. The instruction in *INSN may
14254 already be extended.
14256 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14257 if none. In the former case, VAL is a 16-bit number with no
14258 defined signedness.
14260 TYPE is the type of the immediate field. USER_INSN_LENGTH
14261 is the length that the user requested, or 0 if none. */
14264 mips16_immed (const char *file
, unsigned int line
, int type
,
14265 bfd_reloc_code_real_type reloc
, offsetT val
,
14266 unsigned int user_insn_length
, unsigned long *insn
)
14268 const struct mips_int_operand
*operand
;
14269 unsigned int uval
, length
;
14271 operand
= mips16_immed_operand (type
, FALSE
);
14272 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14274 /* We need an extended instruction. */
14275 if (user_insn_length
== 2)
14276 as_bad_where (file
, line
, _("invalid unextended operand value"));
14278 *insn
|= MIPS16_EXTEND
;
14280 else if (user_insn_length
== 4)
14282 /* The operand doesn't force an unextended instruction to be extended.
14283 Warn if the user wanted an extended instruction anyway. */
14284 *insn
|= MIPS16_EXTEND
;
14285 as_warn_where (file
, line
,
14286 _("extended operand requested but not required"));
14289 length
= mips16_opcode_length (*insn
);
14292 operand
= mips16_immed_operand (type
, TRUE
);
14293 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14294 as_bad_where (file
, line
,
14295 _("operand value out of range for instruction"));
14297 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14298 if (length
== 2 || operand
->root
.lsb
!= 0)
14299 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14301 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14304 struct percent_op_match
14307 bfd_reloc_code_real_type reloc
;
14310 static const struct percent_op_match mips_percent_op
[] =
14312 {"%lo", BFD_RELOC_LO16
},
14313 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14314 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14315 {"%call16", BFD_RELOC_MIPS_CALL16
},
14316 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14317 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14318 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14319 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14320 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14321 {"%got", BFD_RELOC_MIPS_GOT16
},
14322 {"%gp_rel", BFD_RELOC_GPREL16
},
14323 {"%gprel", BFD_RELOC_GPREL16
},
14324 {"%half", BFD_RELOC_16
},
14325 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14326 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14327 {"%neg", BFD_RELOC_MIPS_SUB
},
14328 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14329 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14330 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14331 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14332 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14333 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14334 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14335 {"%hi", BFD_RELOC_HI16_S
},
14336 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14337 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14340 static const struct percent_op_match mips16_percent_op
[] =
14342 {"%lo", BFD_RELOC_MIPS16_LO16
},
14343 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14344 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14345 {"%got", BFD_RELOC_MIPS16_GOT16
},
14346 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14347 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14348 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14349 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14350 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14351 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14352 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14353 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14354 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14358 /* Return true if *STR points to a relocation operator. When returning true,
14359 move *STR over the operator and store its relocation code in *RELOC.
14360 Leave both *STR and *RELOC alone when returning false. */
14363 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14365 const struct percent_op_match
*percent_op
;
14368 if (mips_opts
.mips16
)
14370 percent_op
= mips16_percent_op
;
14371 limit
= ARRAY_SIZE (mips16_percent_op
);
14375 percent_op
= mips_percent_op
;
14376 limit
= ARRAY_SIZE (mips_percent_op
);
14379 for (i
= 0; i
< limit
; i
++)
14380 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14382 int len
= strlen (percent_op
[i
].str
);
14384 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14387 *str
+= strlen (percent_op
[i
].str
);
14388 *reloc
= percent_op
[i
].reloc
;
14390 /* Check whether the output BFD supports this relocation.
14391 If not, issue an error and fall back on something safe. */
14392 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14394 as_bad (_("relocation %s isn't supported by the current ABI"),
14395 percent_op
[i
].str
);
14396 *reloc
= BFD_RELOC_UNUSED
;
14404 /* Parse string STR as a 16-bit relocatable operand. Store the
14405 expression in *EP and the relocations in the array starting
14406 at RELOC. Return the number of relocation operators used.
14408 On exit, EXPR_END points to the first character after the expression. */
14411 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14414 bfd_reloc_code_real_type reversed_reloc
[3];
14415 size_t reloc_index
, i
;
14416 int crux_depth
, str_depth
;
14419 /* Search for the start of the main expression, recoding relocations
14420 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14421 of the main expression and with CRUX_DEPTH containing the number
14422 of open brackets at that point. */
14429 crux_depth
= str_depth
;
14431 /* Skip over whitespace and brackets, keeping count of the number
14433 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14438 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14439 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14441 my_getExpression (ep
, crux
);
14444 /* Match every open bracket. */
14445 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14449 if (crux_depth
> 0)
14450 as_bad (_("unclosed '('"));
14454 if (reloc_index
!= 0)
14456 prev_reloc_op_frag
= frag_now
;
14457 for (i
= 0; i
< reloc_index
; i
++)
14458 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14461 return reloc_index
;
14465 my_getExpression (expressionS
*ep
, char *str
)
14469 save_in
= input_line_pointer
;
14470 input_line_pointer
= str
;
14472 expr_end
= input_line_pointer
;
14473 input_line_pointer
= save_in
;
14477 md_atof (int type
, char *litP
, int *sizeP
)
14479 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14483 md_number_to_chars (char *buf
, valueT val
, int n
)
14485 if (target_big_endian
)
14486 number_to_chars_bigendian (buf
, val
, n
);
14488 number_to_chars_littleendian (buf
, val
, n
);
14491 static int support_64bit_objects(void)
14493 const char **list
, **l
;
14496 list
= bfd_target_list ();
14497 for (l
= list
; *l
!= NULL
; l
++)
14498 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14499 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14501 yes
= (*l
!= NULL
);
14506 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14507 NEW_VALUE. Warn if another value was already specified. Note:
14508 we have to defer parsing the -march and -mtune arguments in order
14509 to handle 'from-abi' correctly, since the ABI might be specified
14510 in a later argument. */
14513 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14515 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14516 as_warn (_("a different %s was already specified, is now %s"),
14517 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14520 *string_ptr
= new_value
;
14524 md_parse_option (int c
, const char *arg
)
14528 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14529 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14531 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14532 c
== mips_ases
[i
].option_on
);
14538 case OPTION_CONSTRUCT_FLOATS
:
14539 mips_disable_float_construction
= 0;
14542 case OPTION_NO_CONSTRUCT_FLOATS
:
14543 mips_disable_float_construction
= 1;
14555 target_big_endian
= 1;
14559 target_big_endian
= 0;
14565 else if (arg
[0] == '0')
14567 else if (arg
[0] == '1')
14577 mips_debug
= atoi (arg
);
14581 file_mips_opts
.isa
= ISA_MIPS1
;
14585 file_mips_opts
.isa
= ISA_MIPS2
;
14589 file_mips_opts
.isa
= ISA_MIPS3
;
14593 file_mips_opts
.isa
= ISA_MIPS4
;
14597 file_mips_opts
.isa
= ISA_MIPS5
;
14600 case OPTION_MIPS32
:
14601 file_mips_opts
.isa
= ISA_MIPS32
;
14604 case OPTION_MIPS32R2
:
14605 file_mips_opts
.isa
= ISA_MIPS32R2
;
14608 case OPTION_MIPS32R3
:
14609 file_mips_opts
.isa
= ISA_MIPS32R3
;
14612 case OPTION_MIPS32R5
:
14613 file_mips_opts
.isa
= ISA_MIPS32R5
;
14616 case OPTION_MIPS32R6
:
14617 file_mips_opts
.isa
= ISA_MIPS32R6
;
14620 case OPTION_MIPS64R2
:
14621 file_mips_opts
.isa
= ISA_MIPS64R2
;
14624 case OPTION_MIPS64R3
:
14625 file_mips_opts
.isa
= ISA_MIPS64R3
;
14628 case OPTION_MIPS64R5
:
14629 file_mips_opts
.isa
= ISA_MIPS64R5
;
14632 case OPTION_MIPS64R6
:
14633 file_mips_opts
.isa
= ISA_MIPS64R6
;
14636 case OPTION_MIPS64
:
14637 file_mips_opts
.isa
= ISA_MIPS64
;
14641 mips_set_option_string (&mips_tune_string
, arg
);
14645 mips_set_option_string (&mips_arch_string
, arg
);
14649 mips_set_option_string (&mips_arch_string
, "4650");
14650 mips_set_option_string (&mips_tune_string
, "4650");
14653 case OPTION_NO_M4650
:
14657 mips_set_option_string (&mips_arch_string
, "4010");
14658 mips_set_option_string (&mips_tune_string
, "4010");
14661 case OPTION_NO_M4010
:
14665 mips_set_option_string (&mips_arch_string
, "4100");
14666 mips_set_option_string (&mips_tune_string
, "4100");
14669 case OPTION_NO_M4100
:
14673 mips_set_option_string (&mips_arch_string
, "3900");
14674 mips_set_option_string (&mips_tune_string
, "3900");
14677 case OPTION_NO_M3900
:
14680 case OPTION_MICROMIPS
:
14681 if (file_mips_opts
.mips16
== 1)
14683 as_bad (_("-mmicromips cannot be used with -mips16"));
14686 file_mips_opts
.micromips
= 1;
14687 mips_no_prev_insn ();
14690 case OPTION_NO_MICROMIPS
:
14691 file_mips_opts
.micromips
= 0;
14692 mips_no_prev_insn ();
14695 case OPTION_MIPS16
:
14696 if (file_mips_opts
.micromips
== 1)
14698 as_bad (_("-mips16 cannot be used with -micromips"));
14701 file_mips_opts
.mips16
= 1;
14702 mips_no_prev_insn ();
14705 case OPTION_NO_MIPS16
:
14706 file_mips_opts
.mips16
= 0;
14707 mips_no_prev_insn ();
14710 case OPTION_FIX_24K
:
14714 case OPTION_NO_FIX_24K
:
14718 case OPTION_FIX_RM7000
:
14719 mips_fix_rm7000
= 1;
14722 case OPTION_NO_FIX_RM7000
:
14723 mips_fix_rm7000
= 0;
14726 case OPTION_FIX_LOONGSON2F_JUMP
:
14727 mips_fix_loongson2f_jump
= TRUE
;
14730 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14731 mips_fix_loongson2f_jump
= FALSE
;
14734 case OPTION_FIX_LOONGSON2F_NOP
:
14735 mips_fix_loongson2f_nop
= TRUE
;
14738 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14739 mips_fix_loongson2f_nop
= FALSE
;
14742 case OPTION_FIX_VR4120
:
14743 mips_fix_vr4120
= 1;
14746 case OPTION_NO_FIX_VR4120
:
14747 mips_fix_vr4120
= 0;
14750 case OPTION_FIX_VR4130
:
14751 mips_fix_vr4130
= 1;
14754 case OPTION_NO_FIX_VR4130
:
14755 mips_fix_vr4130
= 0;
14758 case OPTION_FIX_CN63XXP1
:
14759 mips_fix_cn63xxp1
= TRUE
;
14762 case OPTION_NO_FIX_CN63XXP1
:
14763 mips_fix_cn63xxp1
= FALSE
;
14766 case OPTION_RELAX_BRANCH
:
14767 mips_relax_branch
= 1;
14770 case OPTION_NO_RELAX_BRANCH
:
14771 mips_relax_branch
= 0;
14774 case OPTION_IGNORE_BRANCH_ISA
:
14775 mips_ignore_branch_isa
= TRUE
;
14778 case OPTION_NO_IGNORE_BRANCH_ISA
:
14779 mips_ignore_branch_isa
= FALSE
;
14782 case OPTION_INSN32
:
14783 file_mips_opts
.insn32
= TRUE
;
14786 case OPTION_NO_INSN32
:
14787 file_mips_opts
.insn32
= FALSE
;
14790 case OPTION_MSHARED
:
14791 mips_in_shared
= TRUE
;
14794 case OPTION_MNO_SHARED
:
14795 mips_in_shared
= FALSE
;
14798 case OPTION_MSYM32
:
14799 file_mips_opts
.sym32
= TRUE
;
14802 case OPTION_MNO_SYM32
:
14803 file_mips_opts
.sym32
= FALSE
;
14806 /* When generating ELF code, we permit -KPIC and -call_shared to
14807 select SVR4_PIC, and -non_shared to select no PIC. This is
14808 intended to be compatible with Irix 5. */
14809 case OPTION_CALL_SHARED
:
14810 mips_pic
= SVR4_PIC
;
14811 mips_abicalls
= TRUE
;
14814 case OPTION_CALL_NONPIC
:
14816 mips_abicalls
= TRUE
;
14819 case OPTION_NON_SHARED
:
14821 mips_abicalls
= FALSE
;
14824 /* The -xgot option tells the assembler to use 32 bit offsets
14825 when accessing the got in SVR4_PIC mode. It is for Irix
14832 g_switch_value
= atoi (arg
);
14836 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14839 mips_abi
= O32_ABI
;
14843 mips_abi
= N32_ABI
;
14847 mips_abi
= N64_ABI
;
14848 if (!support_64bit_objects())
14849 as_fatal (_("no compiled in support for 64 bit object file format"));
14853 file_mips_opts
.gp
= 32;
14857 file_mips_opts
.gp
= 64;
14861 file_mips_opts
.fp
= 32;
14865 file_mips_opts
.fp
= 0;
14869 file_mips_opts
.fp
= 64;
14872 case OPTION_ODD_SPREG
:
14873 file_mips_opts
.oddspreg
= 1;
14876 case OPTION_NO_ODD_SPREG
:
14877 file_mips_opts
.oddspreg
= 0;
14880 case OPTION_SINGLE_FLOAT
:
14881 file_mips_opts
.single_float
= 1;
14884 case OPTION_DOUBLE_FLOAT
:
14885 file_mips_opts
.single_float
= 0;
14888 case OPTION_SOFT_FLOAT
:
14889 file_mips_opts
.soft_float
= 1;
14892 case OPTION_HARD_FLOAT
:
14893 file_mips_opts
.soft_float
= 0;
14897 if (strcmp (arg
, "32") == 0)
14898 mips_abi
= O32_ABI
;
14899 else if (strcmp (arg
, "o64") == 0)
14900 mips_abi
= O64_ABI
;
14901 else if (strcmp (arg
, "n32") == 0)
14902 mips_abi
= N32_ABI
;
14903 else if (strcmp (arg
, "64") == 0)
14905 mips_abi
= N64_ABI
;
14906 if (! support_64bit_objects())
14907 as_fatal (_("no compiled in support for 64 bit object file "
14910 else if (strcmp (arg
, "eabi") == 0)
14911 mips_abi
= EABI_ABI
;
14914 as_fatal (_("invalid abi -mabi=%s"), arg
);
14919 case OPTION_M7000_HILO_FIX
:
14920 mips_7000_hilo_fix
= TRUE
;
14923 case OPTION_MNO_7000_HILO_FIX
:
14924 mips_7000_hilo_fix
= FALSE
;
14927 case OPTION_MDEBUG
:
14928 mips_flag_mdebug
= TRUE
;
14931 case OPTION_NO_MDEBUG
:
14932 mips_flag_mdebug
= FALSE
;
14936 mips_flag_pdr
= TRUE
;
14939 case OPTION_NO_PDR
:
14940 mips_flag_pdr
= FALSE
;
14943 case OPTION_MVXWORKS_PIC
:
14944 mips_pic
= VXWORKS_PIC
;
14948 if (strcmp (arg
, "2008") == 0)
14950 else if (strcmp (arg
, "legacy") == 0)
14954 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14963 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14968 /* Set up globals to tune for the ISA or processor described by INFO. */
14971 mips_set_tune (const struct mips_cpu_info
*info
)
14974 mips_tune
= info
->cpu
;
14979 mips_after_parse_args (void)
14981 const struct mips_cpu_info
*arch_info
= 0;
14982 const struct mips_cpu_info
*tune_info
= 0;
14984 /* GP relative stuff not working for PE */
14985 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14987 if (g_switch_seen
&& g_switch_value
!= 0)
14988 as_bad (_("-G not supported in this configuration"));
14989 g_switch_value
= 0;
14992 if (mips_abi
== NO_ABI
)
14993 mips_abi
= MIPS_DEFAULT_ABI
;
14995 /* The following code determines the architecture.
14996 Similar code was added to GCC 3.3 (see override_options() in
14997 config/mips/mips.c). The GAS and GCC code should be kept in sync
14998 as much as possible. */
15000 if (mips_arch_string
!= 0)
15001 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15003 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15005 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15006 ISA level specified by -mipsN, while arch_info->isa contains
15007 the -march selection (if any). */
15008 if (arch_info
!= 0)
15010 /* -march takes precedence over -mipsN, since it is more descriptive.
15011 There's no harm in specifying both as long as the ISA levels
15013 if (file_mips_opts
.isa
!= arch_info
->isa
)
15014 as_bad (_("-%s conflicts with the other architecture options,"
15015 " which imply -%s"),
15016 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15017 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15020 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15023 if (arch_info
== 0)
15025 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15026 gas_assert (arch_info
);
15029 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15030 as_bad (_("-march=%s is not compatible with the selected ABI"),
15033 file_mips_opts
.arch
= arch_info
->cpu
;
15034 file_mips_opts
.isa
= arch_info
->isa
;
15036 /* Set up initial mips_opts state. */
15037 mips_opts
= file_mips_opts
;
15039 /* The register size inference code is now placed in
15040 file_mips_check_options. */
15042 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15044 if (mips_tune_string
!= 0)
15045 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15047 if (tune_info
== 0)
15048 mips_set_tune (arch_info
);
15050 mips_set_tune (tune_info
);
15052 if (mips_flag_mdebug
< 0)
15053 mips_flag_mdebug
= 0;
15057 mips_init_after_args (void)
15059 /* initialize opcodes */
15060 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15061 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15065 md_pcrel_from (fixS
*fixP
)
15067 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15068 switch (fixP
->fx_r_type
)
15070 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15071 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15072 /* Return the address of the delay slot. */
15075 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15076 case BFD_RELOC_MICROMIPS_JMP
:
15077 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15078 case BFD_RELOC_16_PCREL_S2
:
15079 case BFD_RELOC_MIPS_21_PCREL_S2
:
15080 case BFD_RELOC_MIPS_26_PCREL_S2
:
15081 case BFD_RELOC_MIPS_JMP
:
15082 /* Return the address of the delay slot. */
15085 case BFD_RELOC_MIPS_18_PCREL_S3
:
15086 /* Return the aligned address of the doubleword containing
15087 the instruction. */
15095 /* This is called before the symbol table is processed. In order to
15096 work with gcc when using mips-tfile, we must keep all local labels.
15097 However, in other cases, we want to discard them. If we were
15098 called with -g, but we didn't see any debugging information, it may
15099 mean that gcc is smuggling debugging information through to
15100 mips-tfile, in which case we must generate all local labels. */
15103 mips_frob_file_before_adjust (void)
15105 #ifndef NO_ECOFF_DEBUGGING
15106 if (ECOFF_DEBUGGING
15108 && ! ecoff_debugging_seen
)
15109 flag_keep_locals
= 1;
15113 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15114 the corresponding LO16 reloc. This is called before md_apply_fix and
15115 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15116 relocation operators.
15118 For our purposes, a %lo() expression matches a %got() or %hi()
15121 (a) it refers to the same symbol; and
15122 (b) the offset applied in the %lo() expression is no lower than
15123 the offset applied in the %got() or %hi().
15125 (b) allows us to cope with code like:
15128 lh $4,%lo(foo+2)($4)
15130 ...which is legal on RELA targets, and has a well-defined behaviour
15131 if the user knows that adding 2 to "foo" will not induce a carry to
15134 When several %lo()s match a particular %got() or %hi(), we use the
15135 following rules to distinguish them:
15137 (1) %lo()s with smaller offsets are a better match than %lo()s with
15140 (2) %lo()s with no matching %got() or %hi() are better than those
15141 that already have a matching %got() or %hi().
15143 (3) later %lo()s are better than earlier %lo()s.
15145 These rules are applied in order.
15147 (1) means, among other things, that %lo()s with identical offsets are
15148 chosen if they exist.
15150 (2) means that we won't associate several high-part relocations with
15151 the same low-part relocation unless there's no alternative. Having
15152 several high parts for the same low part is a GNU extension; this rule
15153 allows careful users to avoid it.
15155 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15156 with the last high-part relocation being at the front of the list.
15157 It therefore makes sense to choose the last matching low-part
15158 relocation, all other things being equal. It's also easier
15159 to code that way. */
15162 mips_frob_file (void)
15164 struct mips_hi_fixup
*l
;
15165 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15167 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15169 segment_info_type
*seginfo
;
15170 bfd_boolean matched_lo_p
;
15171 fixS
**hi_pos
, **lo_pos
, **pos
;
15173 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15175 /* If a GOT16 relocation turns out to be against a global symbol,
15176 there isn't supposed to be a matching LO. Ignore %gots against
15177 constants; we'll report an error for those later. */
15178 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15179 && !(l
->fixp
->fx_addsy
15180 && pic_need_relax (l
->fixp
->fx_addsy
)))
15183 /* Check quickly whether the next fixup happens to be a matching %lo. */
15184 if (fixup_has_matching_lo_p (l
->fixp
))
15187 seginfo
= seg_info (l
->seg
);
15189 /* Set HI_POS to the position of this relocation in the chain.
15190 Set LO_POS to the position of the chosen low-part relocation.
15191 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15192 relocation that matches an immediately-preceding high-part
15196 matched_lo_p
= FALSE
;
15197 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15199 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15201 if (*pos
== l
->fixp
)
15204 if ((*pos
)->fx_r_type
== looking_for_rtype
15205 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15206 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15208 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15210 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15213 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15214 && fixup_has_matching_lo_p (*pos
));
15217 /* If we found a match, remove the high-part relocation from its
15218 current position and insert it before the low-part relocation.
15219 Make the offsets match so that fixup_has_matching_lo_p()
15222 We don't warn about unmatched high-part relocations since some
15223 versions of gcc have been known to emit dead "lui ...%hi(...)"
15225 if (lo_pos
!= NULL
)
15227 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15228 if (l
->fixp
->fx_next
!= *lo_pos
)
15230 *hi_pos
= l
->fixp
->fx_next
;
15231 l
->fixp
->fx_next
= *lo_pos
;
15239 mips_force_relocation (fixS
*fixp
)
15241 if (generic_force_reloc (fixp
))
15244 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15245 so that the linker relaxation can update targets. */
15246 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15247 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15248 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15251 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15252 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15253 microMIPS symbols so that we can do cross-mode branch diagnostics
15254 and BAL to JALX conversion by the linker. */
15255 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15256 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15257 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15259 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15262 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15263 if (ISA_IS_R6 (file_mips_opts
.isa
)
15264 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15265 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15266 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15267 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15268 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15269 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15270 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15276 /* Implement TC_FORCE_RELOCATION_ABS. */
15279 mips_force_relocation_abs (fixS
*fixp
)
15281 if (generic_force_reloc (fixp
))
15284 /* These relocations do not have enough bits in the in-place addend
15285 to hold an arbitrary absolute section's offset. */
15286 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15292 /* Read the instruction associated with RELOC from BUF. */
15294 static unsigned int
15295 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15297 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15298 return read_compressed_insn (buf
, 4);
15300 return read_insn (buf
);
15303 /* Write instruction INSN to BUF, given that it has been relocated
15307 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15308 unsigned long insn
)
15310 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15311 write_compressed_insn (buf
, insn
, 4);
15313 write_insn (buf
, insn
);
15316 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15317 to a symbol in another ISA mode, which cannot be converted to JALX. */
15320 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15322 unsigned long opcode
;
15326 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15329 other
= S_GET_OTHER (fixP
->fx_addsy
);
15330 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15331 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15332 switch (fixP
->fx_r_type
)
15334 case BFD_RELOC_MIPS_JMP
:
15335 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15336 case BFD_RELOC_MICROMIPS_JMP
:
15337 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15343 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15344 jump to a symbol in the same ISA mode. */
15347 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15349 unsigned long opcode
;
15353 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15356 other
= S_GET_OTHER (fixP
->fx_addsy
);
15357 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15358 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15359 switch (fixP
->fx_r_type
)
15361 case BFD_RELOC_MIPS_JMP
:
15362 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15363 case BFD_RELOC_MIPS16_JMP
:
15364 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15365 case BFD_RELOC_MICROMIPS_JMP
:
15366 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15372 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15373 to a symbol whose value plus addend is not aligned according to the
15374 ultimate (after linker relaxation) jump instruction's immediate field
15375 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15376 regular MIPS code, to (1 << 2). */
15379 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15381 bfd_boolean micro_to_mips_p
;
15385 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15388 other
= S_GET_OTHER (fixP
->fx_addsy
);
15389 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15390 val
+= fixP
->fx_offset
;
15391 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15392 && !ELF_ST_IS_MICROMIPS (other
));
15393 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15394 != ELF_ST_IS_COMPRESSED (other
));
15397 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15398 to a symbol whose annotation indicates another ISA mode. For absolute
15399 symbols check the ISA bit instead.
15401 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15402 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15403 MIPS symbols and associated with BAL instructions as these instructions
15404 may be converted to JALX by the linker. */
15407 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15409 bfd_boolean absolute_p
;
15410 unsigned long opcode
;
15416 if (mips_ignore_branch_isa
)
15419 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15422 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15423 absolute_p
= bfd_is_abs_section (symsec
);
15425 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15426 other
= S_GET_OTHER (fixP
->fx_addsy
);
15428 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15429 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15430 switch (fixP
->fx_r_type
)
15432 case BFD_RELOC_16_PCREL_S2
:
15433 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15434 && opcode
!= 0x0411);
15435 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15436 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15437 && opcode
!= 0x4060);
15438 case BFD_RELOC_MIPS_21_PCREL_S2
:
15439 case BFD_RELOC_MIPS_26_PCREL_S2
:
15440 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15441 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15442 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15443 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15444 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15445 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15451 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15452 branch instruction pointed to by FIXP is not aligned according to the
15453 branch instruction's immediate field requirement. We need the addend
15454 to preserve the ISA bit and also the sum must not have bit 2 set. We
15455 must explicitly OR in the ISA bit from symbol annotation as the bit
15456 won't be set in the symbol's value then. */
15459 fix_bad_misaligned_branch_p (fixS
*fixP
)
15461 bfd_boolean absolute_p
;
15468 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15471 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15472 absolute_p
= bfd_is_abs_section (symsec
);
15474 val
= S_GET_VALUE (fixP
->fx_addsy
);
15475 other
= S_GET_OTHER (fixP
->fx_addsy
);
15476 off
= fixP
->fx_offset
;
15478 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15479 val
|= ELF_ST_IS_COMPRESSED (other
);
15481 return (val
& 0x3) != isa_bit
;
15484 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15485 and its calculated value VAL. */
15488 fix_validate_branch (fixS
*fixP
, valueT val
)
15490 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15492 _("branch to misaligned address (0x%lx)"),
15493 (long) (val
+ md_pcrel_from (fixP
)));
15494 else if (fix_bad_cross_mode_branch_p (fixP
))
15495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15496 _("branch to a symbol in another ISA mode"));
15497 else if (fix_bad_misaligned_branch_p (fixP
))
15498 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15499 _("branch to misaligned address (0x%lx)"),
15500 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15501 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15503 _("cannot encode misaligned addend "
15504 "in the relocatable field (0x%lx)"),
15505 (long) fixP
->fx_offset
);
15508 /* Apply a fixup to the object file. */
15511 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15514 unsigned long insn
;
15515 reloc_howto_type
*howto
;
15517 if (fixP
->fx_pcrel
)
15518 switch (fixP
->fx_r_type
)
15520 case BFD_RELOC_16_PCREL_S2
:
15521 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15522 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15523 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15524 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15525 case BFD_RELOC_32_PCREL
:
15526 case BFD_RELOC_MIPS_21_PCREL_S2
:
15527 case BFD_RELOC_MIPS_26_PCREL_S2
:
15528 case BFD_RELOC_MIPS_18_PCREL_S3
:
15529 case BFD_RELOC_MIPS_19_PCREL_S2
:
15530 case BFD_RELOC_HI16_S_PCREL
:
15531 case BFD_RELOC_LO16_PCREL
:
15535 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15540 _("PC-relative reference to a different section"));
15544 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15545 that have no MIPS ELF equivalent. */
15546 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15548 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15553 gas_assert (fixP
->fx_size
== 2
15554 || fixP
->fx_size
== 4
15555 || fixP
->fx_r_type
== BFD_RELOC_8
15556 || fixP
->fx_r_type
== BFD_RELOC_16
15557 || fixP
->fx_r_type
== BFD_RELOC_64
15558 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15559 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15560 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15561 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15562 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15563 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15564 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15566 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15568 /* Don't treat parts of a composite relocation as done. There are two
15571 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15572 should nevertheless be emitted if the first part is.
15574 (2) In normal usage, composite relocations are never assembly-time
15575 constants. The easiest way of dealing with the pathological
15576 exceptions is to generate a relocation against STN_UNDEF and
15577 leave everything up to the linker. */
15578 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15581 switch (fixP
->fx_r_type
)
15583 case BFD_RELOC_MIPS_TLS_GD
:
15584 case BFD_RELOC_MIPS_TLS_LDM
:
15585 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15586 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15587 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15588 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15589 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15590 case BFD_RELOC_MIPS_TLS_TPREL32
:
15591 case BFD_RELOC_MIPS_TLS_TPREL64
:
15592 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15593 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15594 case BFD_RELOC_MICROMIPS_TLS_GD
:
15595 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15596 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15597 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15598 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15599 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15600 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15601 case BFD_RELOC_MIPS16_TLS_GD
:
15602 case BFD_RELOC_MIPS16_TLS_LDM
:
15603 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15604 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15605 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15606 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15607 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15608 if (fixP
->fx_addsy
)
15609 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15612 _("TLS relocation against a constant"));
15615 case BFD_RELOC_MIPS_JMP
:
15616 case BFD_RELOC_MIPS16_JMP
:
15617 case BFD_RELOC_MICROMIPS_JMP
:
15621 gas_assert (!fixP
->fx_done
);
15623 /* Shift is 2, unusually, for microMIPS JALX. */
15624 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15625 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15630 if (fix_bad_cross_mode_jump_p (fixP
))
15631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15632 _("jump to a symbol in another ISA mode"));
15633 else if (fix_bad_same_mode_jalx_p (fixP
))
15634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15635 _("JALX to a symbol in the same ISA mode"));
15636 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15638 _("jump to misaligned address (0x%lx)"),
15639 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15640 + fixP
->fx_offset
));
15641 else if (HAVE_IN_PLACE_ADDENDS
15642 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15644 _("cannot encode misaligned addend "
15645 "in the relocatable field (0x%lx)"),
15646 (long) fixP
->fx_offset
);
15648 /* Fall through. */
15650 case BFD_RELOC_MIPS_SHIFT5
:
15651 case BFD_RELOC_MIPS_SHIFT6
:
15652 case BFD_RELOC_MIPS_GOT_DISP
:
15653 case BFD_RELOC_MIPS_GOT_PAGE
:
15654 case BFD_RELOC_MIPS_GOT_OFST
:
15655 case BFD_RELOC_MIPS_SUB
:
15656 case BFD_RELOC_MIPS_INSERT_A
:
15657 case BFD_RELOC_MIPS_INSERT_B
:
15658 case BFD_RELOC_MIPS_DELETE
:
15659 case BFD_RELOC_MIPS_HIGHEST
:
15660 case BFD_RELOC_MIPS_HIGHER
:
15661 case BFD_RELOC_MIPS_SCN_DISP
:
15662 case BFD_RELOC_MIPS_REL16
:
15663 case BFD_RELOC_MIPS_RELGOT
:
15664 case BFD_RELOC_MIPS_JALR
:
15665 case BFD_RELOC_HI16
:
15666 case BFD_RELOC_HI16_S
:
15667 case BFD_RELOC_LO16
:
15668 case BFD_RELOC_GPREL16
:
15669 case BFD_RELOC_MIPS_LITERAL
:
15670 case BFD_RELOC_MIPS_CALL16
:
15671 case BFD_RELOC_MIPS_GOT16
:
15672 case BFD_RELOC_GPREL32
:
15673 case BFD_RELOC_MIPS_GOT_HI16
:
15674 case BFD_RELOC_MIPS_GOT_LO16
:
15675 case BFD_RELOC_MIPS_CALL_HI16
:
15676 case BFD_RELOC_MIPS_CALL_LO16
:
15677 case BFD_RELOC_HI16_S_PCREL
:
15678 case BFD_RELOC_LO16_PCREL
:
15679 case BFD_RELOC_MIPS16_GPREL
:
15680 case BFD_RELOC_MIPS16_GOT16
:
15681 case BFD_RELOC_MIPS16_CALL16
:
15682 case BFD_RELOC_MIPS16_HI16
:
15683 case BFD_RELOC_MIPS16_HI16_S
:
15684 case BFD_RELOC_MIPS16_LO16
:
15685 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15686 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15687 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15688 case BFD_RELOC_MICROMIPS_SUB
:
15689 case BFD_RELOC_MICROMIPS_HIGHEST
:
15690 case BFD_RELOC_MICROMIPS_HIGHER
:
15691 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15692 case BFD_RELOC_MICROMIPS_JALR
:
15693 case BFD_RELOC_MICROMIPS_HI16
:
15694 case BFD_RELOC_MICROMIPS_HI16_S
:
15695 case BFD_RELOC_MICROMIPS_LO16
:
15696 case BFD_RELOC_MICROMIPS_GPREL16
:
15697 case BFD_RELOC_MICROMIPS_LITERAL
:
15698 case BFD_RELOC_MICROMIPS_CALL16
:
15699 case BFD_RELOC_MICROMIPS_GOT16
:
15700 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15701 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15702 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15703 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15704 case BFD_RELOC_MIPS_EH
:
15709 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15711 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15712 if (mips16_reloc_p (fixP
->fx_r_type
))
15713 insn
|= mips16_immed_extend (value
, 16);
15715 insn
|= (value
& 0xffff);
15716 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15720 _("unsupported constant in relocation"));
15725 /* This is handled like BFD_RELOC_32, but we output a sign
15726 extended value if we are only 32 bits. */
15729 if (8 <= sizeof (valueT
))
15730 md_number_to_chars (buf
, *valP
, 8);
15735 if ((*valP
& 0x80000000) != 0)
15739 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15740 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15745 case BFD_RELOC_RVA
:
15747 case BFD_RELOC_32_PCREL
:
15750 /* If we are deleting this reloc entry, we must fill in the
15751 value now. This can happen if we have a .word which is not
15752 resolved when it appears but is later defined. */
15754 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15757 case BFD_RELOC_MIPS_21_PCREL_S2
:
15758 fix_validate_branch (fixP
, *valP
);
15759 if (!fixP
->fx_done
)
15762 if (*valP
+ 0x400000 <= 0x7fffff)
15764 insn
= read_insn (buf
);
15765 insn
|= (*valP
>> 2) & 0x1fffff;
15766 write_insn (buf
, insn
);
15769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15770 _("branch out of range"));
15773 case BFD_RELOC_MIPS_26_PCREL_S2
:
15774 fix_validate_branch (fixP
, *valP
);
15775 if (!fixP
->fx_done
)
15778 if (*valP
+ 0x8000000 <= 0xfffffff)
15780 insn
= read_insn (buf
);
15781 insn
|= (*valP
>> 2) & 0x3ffffff;
15782 write_insn (buf
, insn
);
15785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15786 _("branch out of range"));
15789 case BFD_RELOC_MIPS_18_PCREL_S3
:
15790 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15792 _("PC-relative access using misaligned symbol (%lx)"),
15793 (long) S_GET_VALUE (fixP
->fx_addsy
));
15794 if ((fixP
->fx_offset
& 0x7) != 0)
15795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15796 _("PC-relative access using misaligned offset (%lx)"),
15797 (long) fixP
->fx_offset
);
15798 if (!fixP
->fx_done
)
15801 if (*valP
+ 0x100000 <= 0x1fffff)
15803 insn
= read_insn (buf
);
15804 insn
|= (*valP
>> 3) & 0x3ffff;
15805 write_insn (buf
, insn
);
15808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15809 _("PC-relative access out of range"));
15812 case BFD_RELOC_MIPS_19_PCREL_S2
:
15813 if ((*valP
& 0x3) != 0)
15814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15815 _("PC-relative access to misaligned address (%lx)"),
15817 if (!fixP
->fx_done
)
15820 if (*valP
+ 0x100000 <= 0x1fffff)
15822 insn
= read_insn (buf
);
15823 insn
|= (*valP
>> 2) & 0x7ffff;
15824 write_insn (buf
, insn
);
15827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15828 _("PC-relative access out of range"));
15831 case BFD_RELOC_16_PCREL_S2
:
15832 fix_validate_branch (fixP
, *valP
);
15834 /* We need to save the bits in the instruction since fixup_segment()
15835 might be deleting the relocation entry (i.e., a branch within
15836 the current segment). */
15837 if (! fixP
->fx_done
)
15840 /* Update old instruction data. */
15841 insn
= read_insn (buf
);
15843 if (*valP
+ 0x20000 <= 0x3ffff)
15845 insn
|= (*valP
>> 2) & 0xffff;
15846 write_insn (buf
, insn
);
15848 else if (fixP
->fx_tcbit2
15850 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15851 && (fixP
->fx_frag
->fr_address
15852 < text_section
->vma
+ bfd_get_section_size (text_section
))
15853 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15854 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15855 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15857 /* The branch offset is too large. If this is an
15858 unconditional branch, and we are not generating PIC code,
15859 we can convert it to an absolute jump instruction. */
15860 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15861 insn
= 0x0c000000; /* jal */
15863 insn
= 0x08000000; /* j */
15864 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15866 fixP
->fx_addsy
= section_symbol (text_section
);
15867 *valP
+= md_pcrel_from (fixP
);
15868 write_insn (buf
, insn
);
15872 /* If we got here, we have branch-relaxation disabled,
15873 and there's nothing we can do to fix this instruction
15874 without turning it into a longer sequence. */
15875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15876 _("branch out of range"));
15880 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15881 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15882 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15883 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15884 gas_assert (!fixP
->fx_done
);
15885 if (fix_bad_cross_mode_branch_p (fixP
))
15886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15887 _("branch to a symbol in another ISA mode"));
15888 else if (fixP
->fx_addsy
15889 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15890 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15891 && (fixP
->fx_offset
& 0x1) != 0)
15892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15893 _("branch to misaligned address (0x%lx)"),
15894 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15895 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15897 _("cannot encode misaligned addend "
15898 "in the relocatable field (0x%lx)"),
15899 (long) fixP
->fx_offset
);
15902 case BFD_RELOC_VTABLE_INHERIT
:
15905 && !S_IS_DEFINED (fixP
->fx_addsy
)
15906 && !S_IS_WEAK (fixP
->fx_addsy
))
15907 S_SET_WEAK (fixP
->fx_addsy
);
15910 case BFD_RELOC_NONE
:
15911 case BFD_RELOC_VTABLE_ENTRY
:
15919 /* Remember value for tc_gen_reloc. */
15920 fixP
->fx_addnumber
= *valP
;
15930 c
= get_symbol_name (&name
);
15931 p
= (symbolS
*) symbol_find_or_make (name
);
15932 (void) restore_line_pointer (c
);
15936 /* Align the current frag to a given power of two. If a particular
15937 fill byte should be used, FILL points to an integer that contains
15938 that byte, otherwise FILL is null.
15940 This function used to have the comment:
15942 The MIPS assembler also automatically adjusts any preceding label.
15944 The implementation therefore applied the adjustment to a maximum of
15945 one label. However, other label adjustments are applied to batches
15946 of labels, and adjusting just one caused problems when new labels
15947 were added for the sake of debugging or unwind information.
15948 We therefore adjust all preceding labels (given as LABELS) instead. */
15951 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15953 mips_emit_delays ();
15954 mips_record_compressed_mode ();
15955 if (fill
== NULL
&& subseg_text_p (now_seg
))
15956 frag_align_code (to
, 0);
15958 frag_align (to
, fill
? *fill
: 0, 0);
15959 record_alignment (now_seg
, to
);
15960 mips_move_labels (labels
, FALSE
);
15963 /* Align to a given power of two. .align 0 turns off the automatic
15964 alignment used by the data creating pseudo-ops. */
15967 s_align (int x ATTRIBUTE_UNUSED
)
15969 int temp
, fill_value
, *fill_ptr
;
15970 long max_alignment
= 28;
15972 /* o Note that the assembler pulls down any immediately preceding label
15973 to the aligned address.
15974 o It's not documented but auto alignment is reinstated by
15975 a .align pseudo instruction.
15976 o Note also that after auto alignment is turned off the mips assembler
15977 issues an error on attempt to assemble an improperly aligned data item.
15980 temp
= get_absolute_expression ();
15981 if (temp
> max_alignment
)
15982 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15985 as_warn (_("alignment negative, 0 assumed"));
15988 if (*input_line_pointer
== ',')
15990 ++input_line_pointer
;
15991 fill_value
= get_absolute_expression ();
15992 fill_ptr
= &fill_value
;
15998 segment_info_type
*si
= seg_info (now_seg
);
15999 struct insn_label_list
*l
= si
->label_list
;
16000 /* Auto alignment should be switched on by next section change. */
16002 mips_align (temp
, fill_ptr
, l
);
16009 demand_empty_rest_of_line ();
16013 s_change_sec (int sec
)
16017 /* The ELF backend needs to know that we are changing sections, so
16018 that .previous works correctly. We could do something like check
16019 for an obj_section_change_hook macro, but that might be confusing
16020 as it would not be appropriate to use it in the section changing
16021 functions in read.c, since obj-elf.c intercepts those. FIXME:
16022 This should be cleaner, somehow. */
16023 obj_elf_section_change_hook ();
16025 mips_emit_delays ();
16036 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16037 demand_empty_rest_of_line ();
16041 seg
= subseg_new (RDATA_SECTION_NAME
,
16042 (subsegT
) get_absolute_expression ());
16043 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16044 | SEC_READONLY
| SEC_RELOC
16046 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16047 record_alignment (seg
, 4);
16048 demand_empty_rest_of_line ();
16052 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16053 bfd_set_section_flags (stdoutput
, seg
,
16054 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16055 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16056 record_alignment (seg
, 4);
16057 demand_empty_rest_of_line ();
16061 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16062 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16063 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16064 record_alignment (seg
, 4);
16065 demand_empty_rest_of_line ();
16073 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16076 char *section_name
;
16081 int section_entry_size
;
16082 int section_alignment
;
16084 saved_ilp
= input_line_pointer
;
16085 endc
= get_symbol_name (§ion_name
);
16086 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16088 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16090 /* Do we have .section Name<,"flags">? */
16091 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16093 /* Just after name is now '\0'. */
16094 (void) restore_line_pointer (endc
);
16095 input_line_pointer
= saved_ilp
;
16096 obj_elf_section (ignore
);
16100 section_name
= xstrdup (section_name
);
16101 c
= restore_line_pointer (endc
);
16103 input_line_pointer
++;
16105 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16107 section_type
= get_absolute_expression ();
16111 if (*input_line_pointer
++ == ',')
16112 section_flag
= get_absolute_expression ();
16116 if (*input_line_pointer
++ == ',')
16117 section_entry_size
= get_absolute_expression ();
16119 section_entry_size
= 0;
16121 if (*input_line_pointer
++ == ',')
16122 section_alignment
= get_absolute_expression ();
16124 section_alignment
= 0;
16126 /* FIXME: really ignore? */
16127 (void) section_alignment
;
16129 /* When using the generic form of .section (as implemented by obj-elf.c),
16130 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16131 traditionally had to fall back on the more common @progbits instead.
16133 There's nothing really harmful in this, since bfd will correct
16134 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16135 means that, for backwards compatibility, the special_section entries
16136 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16138 Even so, we shouldn't force users of the MIPS .section syntax to
16139 incorrectly label the sections as SHT_PROGBITS. The best compromise
16140 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16141 generic type-checking code. */
16142 if (section_type
== SHT_MIPS_DWARF
)
16143 section_type
= SHT_PROGBITS
;
16145 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
16146 section_entry_size
, 0, 0, 0);
16148 if (now_seg
->name
!= section_name
)
16149 free (section_name
);
16153 mips_enable_auto_align (void)
16159 s_cons (int log_size
)
16161 segment_info_type
*si
= seg_info (now_seg
);
16162 struct insn_label_list
*l
= si
->label_list
;
16164 mips_emit_delays ();
16165 if (log_size
> 0 && auto_align
)
16166 mips_align (log_size
, 0, l
);
16167 cons (1 << log_size
);
16168 mips_clear_insn_labels ();
16172 s_float_cons (int type
)
16174 segment_info_type
*si
= seg_info (now_seg
);
16175 struct insn_label_list
*l
= si
->label_list
;
16177 mips_emit_delays ();
16182 mips_align (3, 0, l
);
16184 mips_align (2, 0, l
);
16188 mips_clear_insn_labels ();
16191 /* Handle .globl. We need to override it because on Irix 5 you are
16194 where foo is an undefined symbol, to mean that foo should be
16195 considered to be the address of a function. */
16198 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16207 c
= get_symbol_name (&name
);
16208 symbolP
= symbol_find_or_make (name
);
16209 S_SET_EXTERNAL (symbolP
);
16211 *input_line_pointer
= c
;
16212 SKIP_WHITESPACE_AFTER_NAME ();
16214 /* On Irix 5, every global symbol that is not explicitly labelled as
16215 being a function is apparently labelled as being an object. */
16218 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16219 && (*input_line_pointer
!= ','))
16224 c
= get_symbol_name (&secname
);
16225 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16227 as_bad (_("%s: no such section"), secname
);
16228 (void) restore_line_pointer (c
);
16230 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16231 flag
= BSF_FUNCTION
;
16234 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16236 c
= *input_line_pointer
;
16239 input_line_pointer
++;
16240 SKIP_WHITESPACE ();
16241 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16247 demand_empty_rest_of_line ();
16251 s_option (int x ATTRIBUTE_UNUSED
)
16256 c
= get_symbol_name (&opt
);
16260 /* FIXME: What does this mean? */
16262 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16266 i
= atoi (opt
+ 3);
16267 if (i
!= 0 && i
!= 2)
16268 as_bad (_(".option pic%d not supported"), i
);
16269 else if (mips_pic
== VXWORKS_PIC
)
16270 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16275 mips_pic
= SVR4_PIC
;
16276 mips_abicalls
= TRUE
;
16279 if (mips_pic
== SVR4_PIC
)
16281 if (g_switch_seen
&& g_switch_value
!= 0)
16282 as_warn (_("-G may not be used with SVR4 PIC code"));
16283 g_switch_value
= 0;
16284 bfd_set_gp_size (stdoutput
, 0);
16288 as_warn (_("unrecognized option \"%s\""), opt
);
16290 (void) restore_line_pointer (c
);
16291 demand_empty_rest_of_line ();
16294 /* This structure is used to hold a stack of .set values. */
16296 struct mips_option_stack
16298 struct mips_option_stack
*next
;
16299 struct mips_set_options options
;
16302 static struct mips_option_stack
*mips_opts_stack
;
16304 /* Return status for .set/.module option handling. */
16306 enum code_option_type
16308 /* Unrecognized option. */
16309 OPTION_TYPE_BAD
= -1,
16311 /* Ordinary option. */
16312 OPTION_TYPE_NORMAL
,
16314 /* ISA changing option. */
16318 /* Handle common .set/.module options. Return status indicating option
16321 static enum code_option_type
16322 parse_code_option (char * name
)
16324 bfd_boolean isa_set
= FALSE
;
16325 const struct mips_ase
*ase
;
16327 if (strncmp (name
, "at=", 3) == 0)
16329 char *s
= name
+ 3;
16331 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16332 as_bad (_("unrecognized register name `%s'"), s
);
16334 else if (strcmp (name
, "at") == 0)
16335 mips_opts
.at
= ATREG
;
16336 else if (strcmp (name
, "noat") == 0)
16337 mips_opts
.at
= ZERO
;
16338 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16339 mips_opts
.nomove
= 0;
16340 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16341 mips_opts
.nomove
= 1;
16342 else if (strcmp (name
, "bopt") == 0)
16343 mips_opts
.nobopt
= 0;
16344 else if (strcmp (name
, "nobopt") == 0)
16345 mips_opts
.nobopt
= 1;
16346 else if (strcmp (name
, "gp=32") == 0)
16348 else if (strcmp (name
, "gp=64") == 0)
16350 else if (strcmp (name
, "fp=32") == 0)
16352 else if (strcmp (name
, "fp=xx") == 0)
16354 else if (strcmp (name
, "fp=64") == 0)
16356 else if (strcmp (name
, "softfloat") == 0)
16357 mips_opts
.soft_float
= 1;
16358 else if (strcmp (name
, "hardfloat") == 0)
16359 mips_opts
.soft_float
= 0;
16360 else if (strcmp (name
, "singlefloat") == 0)
16361 mips_opts
.single_float
= 1;
16362 else if (strcmp (name
, "doublefloat") == 0)
16363 mips_opts
.single_float
= 0;
16364 else if (strcmp (name
, "nooddspreg") == 0)
16365 mips_opts
.oddspreg
= 0;
16366 else if (strcmp (name
, "oddspreg") == 0)
16367 mips_opts
.oddspreg
= 1;
16368 else if (strcmp (name
, "mips16") == 0
16369 || strcmp (name
, "MIPS-16") == 0)
16370 mips_opts
.mips16
= 1;
16371 else if (strcmp (name
, "nomips16") == 0
16372 || strcmp (name
, "noMIPS-16") == 0)
16373 mips_opts
.mips16
= 0;
16374 else if (strcmp (name
, "micromips") == 0)
16375 mips_opts
.micromips
= 1;
16376 else if (strcmp (name
, "nomicromips") == 0)
16377 mips_opts
.micromips
= 0;
16378 else if (name
[0] == 'n'
16380 && (ase
= mips_lookup_ase (name
+ 2)))
16381 mips_set_ase (ase
, &mips_opts
, FALSE
);
16382 else if ((ase
= mips_lookup_ase (name
)))
16383 mips_set_ase (ase
, &mips_opts
, TRUE
);
16384 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16386 /* Permit the user to change the ISA and architecture on the fly.
16387 Needless to say, misuse can cause serious problems. */
16388 if (strncmp (name
, "arch=", 5) == 0)
16390 const struct mips_cpu_info
*p
;
16392 p
= mips_parse_cpu ("internal use", name
+ 5);
16394 as_bad (_("unknown architecture %s"), name
+ 5);
16397 mips_opts
.arch
= p
->cpu
;
16398 mips_opts
.isa
= p
->isa
;
16402 else if (strncmp (name
, "mips", 4) == 0)
16404 const struct mips_cpu_info
*p
;
16406 p
= mips_parse_cpu ("internal use", name
);
16408 as_bad (_("unknown ISA level %s"), name
+ 4);
16411 mips_opts
.arch
= p
->cpu
;
16412 mips_opts
.isa
= p
->isa
;
16417 as_bad (_("unknown ISA or architecture %s"), name
);
16419 else if (strcmp (name
, "autoextend") == 0)
16420 mips_opts
.noautoextend
= 0;
16421 else if (strcmp (name
, "noautoextend") == 0)
16422 mips_opts
.noautoextend
= 1;
16423 else if (strcmp (name
, "insn32") == 0)
16424 mips_opts
.insn32
= TRUE
;
16425 else if (strcmp (name
, "noinsn32") == 0)
16426 mips_opts
.insn32
= FALSE
;
16427 else if (strcmp (name
, "sym32") == 0)
16428 mips_opts
.sym32
= TRUE
;
16429 else if (strcmp (name
, "nosym32") == 0)
16430 mips_opts
.sym32
= FALSE
;
16432 return OPTION_TYPE_BAD
;
16434 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16437 /* Handle the .set pseudo-op. */
16440 s_mipsset (int x ATTRIBUTE_UNUSED
)
16442 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16443 char *name
= input_line_pointer
, ch
;
16445 file_mips_check_options ();
16447 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16448 ++input_line_pointer
;
16449 ch
= *input_line_pointer
;
16450 *input_line_pointer
= '\0';
16452 if (strchr (name
, ','))
16454 /* Generic ".set" directive; use the generic handler. */
16455 *input_line_pointer
= ch
;
16456 input_line_pointer
= name
;
16461 if (strcmp (name
, "reorder") == 0)
16463 if (mips_opts
.noreorder
)
16466 else if (strcmp (name
, "noreorder") == 0)
16468 if (!mips_opts
.noreorder
)
16469 start_noreorder ();
16471 else if (strcmp (name
, "macro") == 0)
16472 mips_opts
.warn_about_macros
= 0;
16473 else if (strcmp (name
, "nomacro") == 0)
16475 if (mips_opts
.noreorder
== 0)
16476 as_bad (_("`noreorder' must be set before `nomacro'"));
16477 mips_opts
.warn_about_macros
= 1;
16479 else if (strcmp (name
, "gp=default") == 0)
16480 mips_opts
.gp
= file_mips_opts
.gp
;
16481 else if (strcmp (name
, "fp=default") == 0)
16482 mips_opts
.fp
= file_mips_opts
.fp
;
16483 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16485 mips_opts
.isa
= file_mips_opts
.isa
;
16486 mips_opts
.arch
= file_mips_opts
.arch
;
16487 mips_opts
.gp
= file_mips_opts
.gp
;
16488 mips_opts
.fp
= file_mips_opts
.fp
;
16490 else if (strcmp (name
, "push") == 0)
16492 struct mips_option_stack
*s
;
16494 s
= XNEW (struct mips_option_stack
);
16495 s
->next
= mips_opts_stack
;
16496 s
->options
= mips_opts
;
16497 mips_opts_stack
= s
;
16499 else if (strcmp (name
, "pop") == 0)
16501 struct mips_option_stack
*s
;
16503 s
= mips_opts_stack
;
16505 as_bad (_(".set pop with no .set push"));
16508 /* If we're changing the reorder mode we need to handle
16509 delay slots correctly. */
16510 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16511 start_noreorder ();
16512 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16515 mips_opts
= s
->options
;
16516 mips_opts_stack
= s
->next
;
16522 type
= parse_code_option (name
);
16523 if (type
== OPTION_TYPE_BAD
)
16524 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16527 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16528 registers based on what is supported by the arch/cpu. */
16529 if (type
== OPTION_TYPE_ISA
)
16531 switch (mips_opts
.isa
)
16536 /* MIPS I cannot support FPXX. */
16538 /* fall-through. */
16545 if (mips_opts
.fp
!= 0)
16561 if (mips_opts
.fp
!= 0)
16563 if (mips_opts
.arch
== CPU_R5900
)
16570 as_bad (_("unknown ISA level %s"), name
+ 4);
16575 mips_check_options (&mips_opts
, FALSE
);
16577 mips_check_isa_supports_ases ();
16578 *input_line_pointer
= ch
;
16579 demand_empty_rest_of_line ();
16582 /* Handle the .module pseudo-op. */
16585 s_module (int ignore ATTRIBUTE_UNUSED
)
16587 char *name
= input_line_pointer
, ch
;
16589 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16590 ++input_line_pointer
;
16591 ch
= *input_line_pointer
;
16592 *input_line_pointer
= '\0';
16594 if (!file_mips_opts_checked
)
16596 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16597 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16599 /* Update module level settings from mips_opts. */
16600 file_mips_opts
= mips_opts
;
16603 as_bad (_(".module is not permitted after generating code"));
16605 *input_line_pointer
= ch
;
16606 demand_empty_rest_of_line ();
16609 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16610 .option pic2. It means to generate SVR4 PIC calls. */
16613 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16615 mips_pic
= SVR4_PIC
;
16616 mips_abicalls
= TRUE
;
16618 if (g_switch_seen
&& g_switch_value
!= 0)
16619 as_warn (_("-G may not be used with SVR4 PIC code"));
16620 g_switch_value
= 0;
16622 bfd_set_gp_size (stdoutput
, 0);
16623 demand_empty_rest_of_line ();
16626 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16627 PIC code. It sets the $gp register for the function based on the
16628 function address, which is in the register named in the argument.
16629 This uses a relocation against _gp_disp, which is handled specially
16630 by the linker. The result is:
16631 lui $gp,%hi(_gp_disp)
16632 addiu $gp,$gp,%lo(_gp_disp)
16633 addu $gp,$gp,.cpload argument
16634 The .cpload argument is normally $25 == $t9.
16636 The -mno-shared option changes this to:
16637 lui $gp,%hi(__gnu_local_gp)
16638 addiu $gp,$gp,%lo(__gnu_local_gp)
16639 and the argument is ignored. This saves an instruction, but the
16640 resulting code is not position independent; it uses an absolute
16641 address for __gnu_local_gp. Thus code assembled with -mno-shared
16642 can go into an ordinary executable, but not into a shared library. */
16645 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16651 file_mips_check_options ();
16653 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16654 .cpload is ignored. */
16655 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16661 if (mips_opts
.mips16
)
16663 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16664 ignore_rest_of_line ();
16668 /* .cpload should be in a .set noreorder section. */
16669 if (mips_opts
.noreorder
== 0)
16670 as_warn (_(".cpload not in noreorder section"));
16672 reg
= tc_get_register (0);
16674 /* If we need to produce a 64-bit address, we are better off using
16675 the default instruction sequence. */
16676 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16678 ex
.X_op
= O_symbol
;
16679 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16681 ex
.X_op_symbol
= NULL
;
16682 ex
.X_add_number
= 0;
16684 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16685 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16687 mips_mark_labels ();
16688 mips_assembling_insn
= TRUE
;
16691 macro_build_lui (&ex
, mips_gp_register
);
16692 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16693 mips_gp_register
, BFD_RELOC_LO16
);
16695 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16696 mips_gp_register
, reg
);
16699 mips_assembling_insn
= FALSE
;
16700 demand_empty_rest_of_line ();
16703 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16704 .cpsetup $reg1, offset|$reg2, label
16706 If offset is given, this results in:
16707 sd $gp, offset($sp)
16708 lui $gp, %hi(%neg(%gp_rel(label)))
16709 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16710 daddu $gp, $gp, $reg1
16712 If $reg2 is given, this results in:
16714 lui $gp, %hi(%neg(%gp_rel(label)))
16715 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16716 daddu $gp, $gp, $reg1
16717 $reg1 is normally $25 == $t9.
16719 The -mno-shared option replaces the last three instructions with
16721 addiu $gp,$gp,%lo(_gp) */
16724 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16726 expressionS ex_off
;
16727 expressionS ex_sym
;
16730 file_mips_check_options ();
16732 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16733 We also need NewABI support. */
16734 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16740 if (mips_opts
.mips16
)
16742 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16743 ignore_rest_of_line ();
16747 reg1
= tc_get_register (0);
16748 SKIP_WHITESPACE ();
16749 if (*input_line_pointer
!= ',')
16751 as_bad (_("missing argument separator ',' for .cpsetup"));
16755 ++input_line_pointer
;
16756 SKIP_WHITESPACE ();
16757 if (*input_line_pointer
== '$')
16759 mips_cpreturn_register
= tc_get_register (0);
16760 mips_cpreturn_offset
= -1;
16764 mips_cpreturn_offset
= get_absolute_expression ();
16765 mips_cpreturn_register
= -1;
16767 SKIP_WHITESPACE ();
16768 if (*input_line_pointer
!= ',')
16770 as_bad (_("missing argument separator ',' for .cpsetup"));
16774 ++input_line_pointer
;
16775 SKIP_WHITESPACE ();
16776 expression (&ex_sym
);
16778 mips_mark_labels ();
16779 mips_assembling_insn
= TRUE
;
16782 if (mips_cpreturn_register
== -1)
16784 ex_off
.X_op
= O_constant
;
16785 ex_off
.X_add_symbol
= NULL
;
16786 ex_off
.X_op_symbol
= NULL
;
16787 ex_off
.X_add_number
= mips_cpreturn_offset
;
16789 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16790 BFD_RELOC_LO16
, SP
);
16793 move_register (mips_cpreturn_register
, mips_gp_register
);
16795 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16797 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16798 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16801 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16802 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16803 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16805 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16806 mips_gp_register
, reg1
);
16812 ex
.X_op
= O_symbol
;
16813 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16814 ex
.X_op_symbol
= NULL
;
16815 ex
.X_add_number
= 0;
16817 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16818 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16820 macro_build_lui (&ex
, mips_gp_register
);
16821 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16822 mips_gp_register
, BFD_RELOC_LO16
);
16827 mips_assembling_insn
= FALSE
;
16828 demand_empty_rest_of_line ();
16832 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16834 file_mips_check_options ();
16836 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16837 .cplocal is ignored. */
16838 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16844 if (mips_opts
.mips16
)
16846 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16847 ignore_rest_of_line ();
16851 mips_gp_register
= tc_get_register (0);
16852 demand_empty_rest_of_line ();
16855 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16856 offset from $sp. The offset is remembered, and after making a PIC
16857 call $gp is restored from that location. */
16860 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16864 file_mips_check_options ();
16866 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16867 .cprestore is ignored. */
16868 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16874 if (mips_opts
.mips16
)
16876 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16877 ignore_rest_of_line ();
16881 mips_cprestore_offset
= get_absolute_expression ();
16882 mips_cprestore_valid
= 1;
16884 ex
.X_op
= O_constant
;
16885 ex
.X_add_symbol
= NULL
;
16886 ex
.X_op_symbol
= NULL
;
16887 ex
.X_add_number
= mips_cprestore_offset
;
16889 mips_mark_labels ();
16890 mips_assembling_insn
= TRUE
;
16893 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16894 SP
, HAVE_64BIT_ADDRESSES
);
16897 mips_assembling_insn
= FALSE
;
16898 demand_empty_rest_of_line ();
16901 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16902 was given in the preceding .cpsetup, it results in:
16903 ld $gp, offset($sp)
16905 If a register $reg2 was given there, it results in:
16906 or $gp, $reg2, $0 */
16909 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16913 file_mips_check_options ();
16915 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16916 We also need NewABI support. */
16917 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16923 if (mips_opts
.mips16
)
16925 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16926 ignore_rest_of_line ();
16930 mips_mark_labels ();
16931 mips_assembling_insn
= TRUE
;
16934 if (mips_cpreturn_register
== -1)
16936 ex
.X_op
= O_constant
;
16937 ex
.X_add_symbol
= NULL
;
16938 ex
.X_op_symbol
= NULL
;
16939 ex
.X_add_number
= mips_cpreturn_offset
;
16941 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16944 move_register (mips_gp_register
, mips_cpreturn_register
);
16948 mips_assembling_insn
= FALSE
;
16949 demand_empty_rest_of_line ();
16952 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16953 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16954 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16955 debug information or MIPS16 TLS. */
16958 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16959 bfd_reloc_code_real_type rtype
)
16966 if (ex
.X_op
!= O_symbol
)
16968 as_bad (_("unsupported use of %s"), dirstr
);
16969 ignore_rest_of_line ();
16972 p
= frag_more (bytes
);
16973 md_number_to_chars (p
, 0, bytes
);
16974 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16975 demand_empty_rest_of_line ();
16976 mips_clear_insn_labels ();
16979 /* Handle .dtprelword. */
16982 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16984 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16987 /* Handle .dtpreldword. */
16990 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16992 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16995 /* Handle .tprelword. */
16998 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17000 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17003 /* Handle .tpreldword. */
17006 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17008 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17011 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17012 code. It sets the offset to use in gp_rel relocations. */
17015 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17017 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17018 We also need NewABI support. */
17019 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17025 mips_gprel_offset
= get_absolute_expression ();
17027 demand_empty_rest_of_line ();
17030 /* Handle the .gpword pseudo-op. This is used when generating PIC
17031 code. It generates a 32 bit GP relative reloc. */
17034 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17036 segment_info_type
*si
;
17037 struct insn_label_list
*l
;
17041 /* When not generating PIC code, this is treated as .word. */
17042 if (mips_pic
!= SVR4_PIC
)
17048 si
= seg_info (now_seg
);
17049 l
= si
->label_list
;
17050 mips_emit_delays ();
17052 mips_align (2, 0, l
);
17055 mips_clear_insn_labels ();
17057 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17059 as_bad (_("unsupported use of .gpword"));
17060 ignore_rest_of_line ();
17064 md_number_to_chars (p
, 0, 4);
17065 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17066 BFD_RELOC_GPREL32
);
17068 demand_empty_rest_of_line ();
17072 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17074 segment_info_type
*si
;
17075 struct insn_label_list
*l
;
17079 /* When not generating PIC code, this is treated as .dword. */
17080 if (mips_pic
!= SVR4_PIC
)
17086 si
= seg_info (now_seg
);
17087 l
= si
->label_list
;
17088 mips_emit_delays ();
17090 mips_align (3, 0, l
);
17093 mips_clear_insn_labels ();
17095 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17097 as_bad (_("unsupported use of .gpdword"));
17098 ignore_rest_of_line ();
17102 md_number_to_chars (p
, 0, 8);
17103 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17104 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17106 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17107 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17108 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17110 demand_empty_rest_of_line ();
17113 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17114 tables. It generates a R_MIPS_EH reloc. */
17117 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17122 mips_emit_delays ();
17125 mips_clear_insn_labels ();
17127 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17129 as_bad (_("unsupported use of .ehword"));
17130 ignore_rest_of_line ();
17134 md_number_to_chars (p
, 0, 4);
17135 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17136 BFD_RELOC_32_PCREL
);
17138 demand_empty_rest_of_line ();
17141 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17142 tables in SVR4 PIC code. */
17145 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17149 file_mips_check_options ();
17151 /* This is ignored when not generating SVR4 PIC code. */
17152 if (mips_pic
!= SVR4_PIC
)
17158 mips_mark_labels ();
17159 mips_assembling_insn
= TRUE
;
17161 /* Add $gp to the register named as an argument. */
17163 reg
= tc_get_register (0);
17164 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17167 mips_assembling_insn
= FALSE
;
17168 demand_empty_rest_of_line ();
17171 /* Handle the .insn pseudo-op. This marks instruction labels in
17172 mips16/micromips mode. This permits the linker to handle them specially,
17173 such as generating jalx instructions when needed. We also make
17174 them odd for the duration of the assembly, in order to generate the
17175 right sort of code. We will make them even in the adjust_symtab
17176 routine, while leaving them marked. This is convenient for the
17177 debugger and the disassembler. The linker knows to make them odd
17181 s_insn (int ignore ATTRIBUTE_UNUSED
)
17183 file_mips_check_options ();
17184 file_ase_mips16
|= mips_opts
.mips16
;
17185 file_ase_micromips
|= mips_opts
.micromips
;
17187 mips_mark_labels ();
17189 demand_empty_rest_of_line ();
17192 /* Handle the .nan pseudo-op. */
17195 s_nan (int ignore ATTRIBUTE_UNUSED
)
17197 static const char str_legacy
[] = "legacy";
17198 static const char str_2008
[] = "2008";
17201 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17203 if (i
== sizeof (str_2008
) - 1
17204 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17206 else if (i
== sizeof (str_legacy
) - 1
17207 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17209 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17212 as_bad (_("`%s' does not support legacy NaN"),
17213 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17216 as_bad (_("bad .nan directive"));
17218 input_line_pointer
+= i
;
17219 demand_empty_rest_of_line ();
17222 /* Handle a .stab[snd] directive. Ideally these directives would be
17223 implemented in a transparent way, so that removing them would not
17224 have any effect on the generated instructions. However, s_stab
17225 internally changes the section, so in practice we need to decide
17226 now whether the preceding label marks compressed code. We do not
17227 support changing the compression mode of a label after a .stab*
17228 directive, such as in:
17234 so the current mode wins. */
17237 s_mips_stab (int type
)
17239 file_mips_check_options ();
17240 mips_mark_labels ();
17244 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17247 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17254 c
= get_symbol_name (&name
);
17255 symbolP
= symbol_find_or_make (name
);
17256 S_SET_WEAK (symbolP
);
17257 *input_line_pointer
= c
;
17259 SKIP_WHITESPACE_AFTER_NAME ();
17261 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17263 if (S_IS_DEFINED (symbolP
))
17265 as_bad (_("ignoring attempt to redefine symbol %s"),
17266 S_GET_NAME (symbolP
));
17267 ignore_rest_of_line ();
17271 if (*input_line_pointer
== ',')
17273 ++input_line_pointer
;
17274 SKIP_WHITESPACE ();
17278 if (exp
.X_op
!= O_symbol
)
17280 as_bad (_("bad .weakext directive"));
17281 ignore_rest_of_line ();
17284 symbol_set_value_expression (symbolP
, &exp
);
17287 demand_empty_rest_of_line ();
17290 /* Parse a register string into a number. Called from the ECOFF code
17291 to parse .frame. The argument is non-zero if this is the frame
17292 register, so that we can record it in mips_frame_reg. */
17295 tc_get_register (int frame
)
17299 SKIP_WHITESPACE ();
17300 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17304 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17305 mips_frame_reg_valid
= 1;
17306 mips_cprestore_valid
= 0;
17312 md_section_align (asection
*seg
, valueT addr
)
17314 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17316 /* We don't need to align ELF sections to the full alignment.
17317 However, Irix 5 may prefer that we align them at least to a 16
17318 byte boundary. We don't bother to align the sections if we
17319 are targeted for an embedded system. */
17320 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17325 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17328 /* Utility routine, called from above as well. If called while the
17329 input file is still being read, it's only an approximation. (For
17330 example, a symbol may later become defined which appeared to be
17331 undefined earlier.) */
17334 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17339 if (g_switch_value
> 0)
17341 const char *symname
;
17344 /* Find out whether this symbol can be referenced off the $gp
17345 register. It can be if it is smaller than the -G size or if
17346 it is in the .sdata or .sbss section. Certain symbols can
17347 not be referenced off the $gp, although it appears as though
17349 symname
= S_GET_NAME (sym
);
17350 if (symname
!= (const char *) NULL
17351 && (strcmp (symname
, "eprol") == 0
17352 || strcmp (symname
, "etext") == 0
17353 || strcmp (symname
, "_gp") == 0
17354 || strcmp (symname
, "edata") == 0
17355 || strcmp (symname
, "_fbss") == 0
17356 || strcmp (symname
, "_fdata") == 0
17357 || strcmp (symname
, "_ftext") == 0
17358 || strcmp (symname
, "end") == 0
17359 || strcmp (symname
, "_gp_disp") == 0))
17361 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17363 #ifndef NO_ECOFF_DEBUGGING
17364 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17365 && (symbol_get_obj (sym
)->ecoff_extern_size
17366 <= g_switch_value
))
17368 /* We must defer this decision until after the whole
17369 file has been read, since there might be a .extern
17370 after the first use of this symbol. */
17371 || (before_relaxing
17372 #ifndef NO_ECOFF_DEBUGGING
17373 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17375 && S_GET_VALUE (sym
) == 0)
17376 || (S_GET_VALUE (sym
) != 0
17377 && S_GET_VALUE (sym
) <= g_switch_value
)))
17381 const char *segname
;
17383 segname
= segment_name (S_GET_SEGMENT (sym
));
17384 gas_assert (strcmp (segname
, ".lit8") != 0
17385 && strcmp (segname
, ".lit4") != 0);
17386 change
= (strcmp (segname
, ".sdata") != 0
17387 && strcmp (segname
, ".sbss") != 0
17388 && strncmp (segname
, ".sdata.", 7) != 0
17389 && strncmp (segname
, ".sbss.", 6) != 0
17390 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17391 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17396 /* We are not optimizing for the $gp register. */
17401 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17404 pic_need_relax (symbolS
*sym
)
17408 /* Handle the case of a symbol equated to another symbol. */
17409 while (symbol_equated_reloc_p (sym
))
17413 /* It's possible to get a loop here in a badly written program. */
17414 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17420 if (symbol_section_p (sym
))
17423 symsec
= S_GET_SEGMENT (sym
);
17425 /* This must duplicate the test in adjust_reloc_syms. */
17426 return (!bfd_is_und_section (symsec
)
17427 && !bfd_is_abs_section (symsec
)
17428 && !bfd_is_com_section (symsec
)
17429 /* A global or weak symbol is treated as external. */
17430 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17433 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17434 convert a section-relative value VAL to the equivalent PC-relative
17438 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17439 offsetT val
, long stretch
)
17444 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17446 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17448 /* If the relax_marker of the symbol fragment differs from the
17449 relax_marker of this fragment, we have not yet adjusted the
17450 symbol fragment fr_address. We want to add in STRETCH in
17451 order to get a better estimate of the address. This
17452 particularly matters because of the shift bits. */
17453 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17457 /* Adjust stretch for any alignment frag. Note that if have
17458 been expanding the earlier code, the symbol may be
17459 defined in what appears to be an earlier frag. FIXME:
17460 This doesn't handle the fr_subtype field, which specifies
17461 a maximum number of bytes to skip when doing an
17463 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17465 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17468 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17470 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17479 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17481 /* The base address rules are complicated. The base address of
17482 a branch is the following instruction. The base address of a
17483 PC relative load or add is the instruction itself, but if it
17484 is in a delay slot (in which case it can not be extended) use
17485 the address of the instruction whose delay slot it is in. */
17486 if (pcrel_op
->include_isa_bit
)
17490 /* If we are currently assuming that this frag should be
17491 extended, then the current address is two bytes higher. */
17492 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17495 /* Ignore the low bit in the target, since it will be set
17496 for a text label. */
17499 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17501 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17504 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17509 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17510 extended opcode. SEC is the section the frag is in. */
17513 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17515 const struct mips_int_operand
*operand
;
17520 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17522 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17525 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17526 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17527 operand
= mips16_immed_operand (type
, FALSE
);
17528 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17529 || (operand
->root
.type
== OP_PCREL
17531 : !bfd_is_abs_section (symsec
)))
17534 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17536 if (operand
->root
.type
== OP_PCREL
)
17538 const struct mips_pcrel_operand
*pcrel_op
;
17541 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17544 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17545 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17547 /* If any of the shifted bits are set, we must use an extended
17548 opcode. If the address depends on the size of this
17549 instruction, this can lead to a loop, so we arrange to always
17550 use an extended opcode. */
17551 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17553 fragp
->fr_subtype
=
17554 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17558 /* If we are about to mark a frag as extended because the value
17559 is precisely the next value above maxtiny, then there is a
17560 chance of an infinite loop as in the following code:
17565 In this case when the la is extended, foo is 0x3fc bytes
17566 away, so the la can be shrunk, but then foo is 0x400 away, so
17567 the la must be extended. To avoid this loop, we mark the
17568 frag as extended if it was small, and is about to become
17569 extended with the next value above maxtiny. */
17570 maxtiny
= mips_int_operand_max (operand
);
17571 if (val
== maxtiny
+ (1 << operand
->shift
)
17572 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17574 fragp
->fr_subtype
=
17575 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17580 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17583 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17584 macro expansion. SEC is the section the frag is in. We only
17585 support PC-relative instructions (LA, DLA, LW, LD) here, in
17586 non-PIC code using 32-bit addressing. */
17589 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17591 const struct mips_pcrel_operand
*pcrel_op
;
17592 const struct mips_int_operand
*operand
;
17597 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17599 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17601 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17604 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17610 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17611 if (bfd_is_abs_section (symsec
))
17613 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17615 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17618 operand
= mips16_immed_operand (type
, TRUE
);
17619 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17620 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17621 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17623 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17630 /* Compute the length of a branch sequence, and adjust the
17631 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17632 worst-case length is computed, with UPDATE being used to indicate
17633 whether an unconditional (-1), branch-likely (+1) or regular (0)
17634 branch is to be computed. */
17636 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17638 bfd_boolean toofar
;
17642 && S_IS_DEFINED (fragp
->fr_symbol
)
17643 && !S_IS_WEAK (fragp
->fr_symbol
)
17644 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17649 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17651 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17655 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17658 /* If the symbol is not defined or it's in a different segment,
17659 we emit the long sequence. */
17662 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17664 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17665 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17666 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17667 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17668 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17674 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17677 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17679 /* Additional space for PIC loading of target address. */
17681 if (mips_opts
.isa
== ISA_MIPS1
)
17682 /* Additional space for $at-stabilizing nop. */
17686 /* If branch is conditional. */
17687 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17694 /* Get a FRAG's branch instruction delay slot size, either from the
17695 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17696 or SHORT_INSN_SIZE otherwise. */
17699 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17701 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17704 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17706 return short_insn_size
;
17709 /* Compute the length of a branch sequence, and adjust the
17710 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17711 worst-case length is computed, with UPDATE being used to indicate
17712 whether an unconditional (-1), or regular (0) branch is to be
17716 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17718 bfd_boolean insn32
= TRUE
;
17719 bfd_boolean nods
= TRUE
;
17720 bfd_boolean pic
= TRUE
;
17721 bfd_boolean al
= TRUE
;
17722 int short_insn_size
;
17723 bfd_boolean toofar
;
17728 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17729 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17730 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17731 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17733 short_insn_size
= insn32
? 4 : 2;
17736 && S_IS_DEFINED (fragp
->fr_symbol
)
17737 && !S_IS_WEAK (fragp
->fr_symbol
)
17738 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17743 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17744 /* Ignore the low bit in the target, since it will be set
17745 for a text label. */
17746 if ((val
& 1) != 0)
17749 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17753 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17756 /* If the symbol is not defined or it's in a different segment,
17757 we emit the long sequence. */
17760 if (fragp
&& update
17761 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17762 fragp
->fr_subtype
= (toofar
17763 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17764 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17769 bfd_boolean compact_known
= fragp
!= NULL
;
17770 bfd_boolean compact
= FALSE
;
17771 bfd_boolean uncond
;
17775 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17776 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17779 uncond
= update
< 0;
17781 /* If label is out of range, we turn branch <br>:
17783 <br> label # 4 bytes
17790 # compact && (!PIC || insn32)
17793 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17794 length
+= short_insn_size
;
17796 /* If assembling PIC code, we further turn:
17802 lw/ld at, %got(label)(gp) # 4 bytes
17803 d/addiu at, %lo(label) # 4 bytes
17804 jr/c at # 2/4 bytes
17807 length
+= 4 + short_insn_size
;
17809 /* Add an extra nop if the jump has no compact form and we need
17810 to fill the delay slot. */
17811 if ((!pic
|| al
) && nods
)
17813 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17814 : short_insn_size
);
17816 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17818 <brneg> 0f # 4 bytes
17819 nop # 2/4 bytes if !compact
17822 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17826 /* Add an extra nop to fill the delay slot. */
17827 gas_assert (fragp
);
17828 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17834 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17835 bit accordingly. */
17838 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17840 bfd_boolean toofar
;
17843 && S_IS_DEFINED (fragp
->fr_symbol
)
17844 && !S_IS_WEAK (fragp
->fr_symbol
)
17845 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17851 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17852 /* Ignore the low bit in the target, since it will be set
17853 for a text label. */
17854 if ((val
& 1) != 0)
17857 /* Assume this is a 2-byte branch. */
17858 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17860 /* We try to avoid the infinite loop by not adding 2 more bytes for
17865 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17867 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17868 else if (type
== 'E')
17869 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17874 /* If the symbol is not defined or it's in a different segment,
17875 we emit a normal 32-bit branch. */
17878 if (fragp
&& update
17879 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17881 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17882 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17890 /* Estimate the size of a frag before relaxing. Unless this is the
17891 mips16, we are not really relaxing here, and the final size is
17892 encoded in the subtype information. For the mips16, we have to
17893 decide whether we are using an extended opcode or not. */
17896 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17900 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17903 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17905 return fragp
->fr_var
;
17908 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17910 /* We don't want to modify the EXTENDED bit here; it might get us
17911 into infinite loops. We change it only in mips_relax_frag(). */
17912 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17913 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
17915 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
17918 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17922 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17923 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17924 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17925 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17926 fragp
->fr_var
= length
;
17931 if (mips_pic
== VXWORKS_PIC
)
17932 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17934 else if (RELAX_PIC (fragp
->fr_subtype
))
17935 change
= pic_need_relax (fragp
->fr_symbol
);
17937 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17941 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17942 return -RELAX_FIRST (fragp
->fr_subtype
);
17945 return -RELAX_SECOND (fragp
->fr_subtype
);
17948 /* This is called to see whether a reloc against a defined symbol
17949 should be converted into a reloc against a section. */
17952 mips_fix_adjustable (fixS
*fixp
)
17954 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17955 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17958 if (fixp
->fx_addsy
== NULL
)
17961 /* Allow relocs used for EH tables. */
17962 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17965 /* If symbol SYM is in a mergeable section, relocations of the form
17966 SYM + 0 can usually be made section-relative. The mergeable data
17967 is then identified by the section offset rather than by the symbol.
17969 However, if we're generating REL LO16 relocations, the offset is split
17970 between the LO16 and partnering high part relocation. The linker will
17971 need to recalculate the complete offset in order to correctly identify
17974 The linker has traditionally not looked for the partnering high part
17975 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17976 placed anywhere. Rather than break backwards compatibility by changing
17977 this, it seems better not to force the issue, and instead keep the
17978 original symbol. This will work with either linker behavior. */
17979 if ((lo16_reloc_p (fixp
->fx_r_type
)
17980 || reloc_needs_lo_p (fixp
->fx_r_type
))
17981 && HAVE_IN_PLACE_ADDENDS
17982 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17985 /* There is no place to store an in-place offset for JALR relocations. */
17986 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17989 /* Likewise an in-range offset of limited PC-relative relocations may
17990 overflow the in-place relocatable field if recalculated against the
17991 start address of the symbol's containing section.
17993 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17994 section relative to allow linker relaxations to be performed later on. */
17995 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17996 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17999 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18000 to a floating-point stub. The same is true for non-R_MIPS16_26
18001 relocations against MIPS16 functions; in this case, the stub becomes
18002 the function's canonical address.
18004 Floating-point stubs are stored in unique .mips16.call.* or
18005 .mips16.fn.* sections. If a stub T for function F is in section S,
18006 the first relocation in section S must be against F; this is how the
18007 linker determines the target function. All relocations that might
18008 resolve to T must also be against F. We therefore have the following
18009 restrictions, which are given in an intentionally-redundant way:
18011 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18014 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18015 if that stub might be used.
18017 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18020 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18021 that stub might be used.
18023 There is a further restriction:
18025 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18026 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18027 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18028 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18029 against MIPS16 or microMIPS symbols because we need to keep the
18030 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18031 detection and JAL or BAL to JALX instruction conversion in the
18034 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18035 against a MIPS16 symbol. We deal with (5) by additionally leaving
18036 alone any jump and branch relocations against a microMIPS symbol.
18038 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18039 relocation against some symbol R, no relocation against R may be
18040 reduced. (Note that this deals with (2) as well as (1) because
18041 relocations against global symbols will never be reduced on ELF
18042 targets.) This approach is a little simpler than trying to detect
18043 stub sections, and gives the "all or nothing" per-symbol consistency
18044 that we have for MIPS16 symbols. */
18045 if (fixp
->fx_subsy
== NULL
18046 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18047 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18048 && (jmp_reloc_p (fixp
->fx_r_type
)
18049 || b_reloc_p (fixp
->fx_r_type
)))
18050 || *symbol_get_tc (fixp
->fx_addsy
)))
18056 /* Translate internal representation of relocation info to BFD target
18060 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18062 static arelent
*retval
[4];
18064 bfd_reloc_code_real_type code
;
18066 memset (retval
, 0, sizeof(retval
));
18067 reloc
= retval
[0] = XCNEW (arelent
);
18068 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18069 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18070 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18072 if (fixp
->fx_pcrel
)
18074 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18075 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18076 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18077 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18078 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18079 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18080 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18081 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18082 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18083 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18084 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18085 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18087 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18088 Relocations want only the symbol offset. */
18089 switch (fixp
->fx_r_type
)
18091 case BFD_RELOC_MIPS_18_PCREL_S3
:
18092 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18095 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18099 else if (HAVE_IN_PLACE_ADDENDS
18100 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18101 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18102 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18104 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18105 addend accordingly. */
18106 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18109 reloc
->addend
= fixp
->fx_addnumber
;
18111 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18112 entry to be used in the relocation's section offset. */
18113 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18115 reloc
->address
= reloc
->addend
;
18119 code
= fixp
->fx_r_type
;
18121 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18122 if (reloc
->howto
== NULL
)
18124 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18125 _("cannot represent %s relocation in this object file"
18127 bfd_get_reloc_code_name (code
));
18134 /* Relax a machine dependent frag. This returns the amount by which
18135 the current size of the frag should change. */
18138 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18140 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18142 offsetT old_var
= fragp
->fr_var
;
18144 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18146 return fragp
->fr_var
- old_var
;
18149 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18151 offsetT old_var
= fragp
->fr_var
;
18152 offsetT new_var
= 4;
18154 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18155 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18156 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18157 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18158 fragp
->fr_var
= new_var
;
18160 return new_var
- old_var
;
18163 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18166 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18168 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18170 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18171 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18173 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18175 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18181 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18183 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18185 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18186 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18187 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18189 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18191 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18199 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18201 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18203 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18204 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18205 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18209 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18210 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18217 /* Convert a machine dependent frag. */
18220 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18222 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18225 unsigned long insn
;
18228 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18229 insn
= read_insn (buf
);
18231 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18233 /* We generate a fixup instead of applying it right now
18234 because, if there are linker relaxations, we're going to
18235 need the relocations. */
18236 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18237 fragp
->fr_symbol
, fragp
->fr_offset
,
18238 TRUE
, BFD_RELOC_16_PCREL_S2
);
18239 fixp
->fx_file
= fragp
->fr_file
;
18240 fixp
->fx_line
= fragp
->fr_line
;
18242 buf
= write_insn (buf
, insn
);
18248 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18249 _("relaxed out-of-range branch into a jump"));
18251 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18254 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18256 /* Reverse the branch. */
18257 switch ((insn
>> 28) & 0xf)
18260 if ((insn
& 0xff000000) == 0x47000000
18261 || (insn
& 0xff600000) == 0x45600000)
18263 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18264 reversed by tweaking bit 23. */
18265 insn
^= 0x00800000;
18269 /* bc[0-3][tf]l? instructions can have the condition
18270 reversed by tweaking a single TF bit, and their
18271 opcodes all have 0x4???????. */
18272 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18273 insn
^= 0x00010000;
18278 /* bltz 0x04000000 bgez 0x04010000
18279 bltzal 0x04100000 bgezal 0x04110000 */
18280 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18281 insn
^= 0x00010000;
18285 /* beq 0x10000000 bne 0x14000000
18286 blez 0x18000000 bgtz 0x1c000000 */
18287 insn
^= 0x04000000;
18295 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18297 /* Clear the and-link bit. */
18298 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18300 /* bltzal 0x04100000 bgezal 0x04110000
18301 bltzall 0x04120000 bgezall 0x04130000 */
18302 insn
&= ~0x00100000;
18305 /* Branch over the branch (if the branch was likely) or the
18306 full jump (not likely case). Compute the offset from the
18307 current instruction to branch to. */
18308 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18312 /* How many bytes in instructions we've already emitted? */
18313 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18314 /* How many bytes in instructions from here to the end? */
18315 i
= fragp
->fr_var
- i
;
18317 /* Convert to instruction count. */
18319 /* Branch counts from the next instruction. */
18322 /* Branch over the jump. */
18323 buf
= write_insn (buf
, insn
);
18326 buf
= write_insn (buf
, 0);
18328 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18330 /* beql $0, $0, 2f */
18332 /* Compute the PC offset from the current instruction to
18333 the end of the variable frag. */
18334 /* How many bytes in instructions we've already emitted? */
18335 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18336 /* How many bytes in instructions from here to the end? */
18337 i
= fragp
->fr_var
- i
;
18338 /* Convert to instruction count. */
18340 /* Don't decrement i, because we want to branch over the
18344 buf
= write_insn (buf
, insn
);
18345 buf
= write_insn (buf
, 0);
18349 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18352 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18353 ? 0x0c000000 : 0x08000000);
18355 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18356 fragp
->fr_symbol
, fragp
->fr_offset
,
18357 FALSE
, BFD_RELOC_MIPS_JMP
);
18358 fixp
->fx_file
= fragp
->fr_file
;
18359 fixp
->fx_line
= fragp
->fr_line
;
18361 buf
= write_insn (buf
, insn
);
18365 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18367 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18368 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18369 insn
|= at
<< OP_SH_RT
;
18371 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18372 fragp
->fr_symbol
, fragp
->fr_offset
,
18373 FALSE
, BFD_RELOC_MIPS_GOT16
);
18374 fixp
->fx_file
= fragp
->fr_file
;
18375 fixp
->fx_line
= fragp
->fr_line
;
18377 buf
= write_insn (buf
, insn
);
18379 if (mips_opts
.isa
== ISA_MIPS1
)
18381 buf
= write_insn (buf
, 0);
18383 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18384 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18385 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18387 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18388 fragp
->fr_symbol
, fragp
->fr_offset
,
18389 FALSE
, BFD_RELOC_LO16
);
18390 fixp
->fx_file
= fragp
->fr_file
;
18391 fixp
->fx_line
= fragp
->fr_line
;
18393 buf
= write_insn (buf
, insn
);
18396 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18400 insn
|= at
<< OP_SH_RS
;
18402 buf
= write_insn (buf
, insn
);
18406 fragp
->fr_fix
+= fragp
->fr_var
;
18407 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18411 /* Relax microMIPS branches. */
18412 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18414 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18415 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18416 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18417 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18418 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18419 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18420 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18421 bfd_boolean short_ds
;
18422 unsigned long insn
;
18425 fragp
->fr_fix
+= fragp
->fr_var
;
18427 /* Handle 16-bit branches that fit or are forced to fit. */
18428 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18430 /* We generate a fixup instead of applying it right now,
18431 because if there is linker relaxation, we're going to
18432 need the relocations. */
18436 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18437 fragp
->fr_symbol
, fragp
->fr_offset
,
18438 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18441 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18442 fragp
->fr_symbol
, fragp
->fr_offset
,
18443 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18449 fixp
->fx_file
= fragp
->fr_file
;
18450 fixp
->fx_line
= fragp
->fr_line
;
18452 /* These relocations can have an addend that won't fit in
18454 fixp
->fx_no_overflow
= 1;
18459 /* Handle 32-bit branches that fit or are forced to fit. */
18460 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18461 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18463 /* We generate a fixup instead of applying it right now,
18464 because if there is linker relaxation, we're going to
18465 need the relocations. */
18466 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18467 fragp
->fr_symbol
, fragp
->fr_offset
,
18468 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18469 fixp
->fx_file
= fragp
->fr_file
;
18470 fixp
->fx_line
= fragp
->fr_line
;
18474 insn
= read_compressed_insn (buf
, 4);
18479 /* Check the short-delay-slot bit. */
18480 if (!al
|| (insn
& 0x02000000) != 0)
18481 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18483 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18486 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18491 /* Relax 16-bit branches to 32-bit branches. */
18494 insn
= read_compressed_insn (buf
, 2);
18496 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18497 insn
= 0x94000000; /* beq */
18498 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18500 unsigned long regno
;
18502 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18503 regno
= micromips_to_32_reg_d_map
[regno
];
18504 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18505 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18510 /* Nothing else to do, just write it out. */
18511 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18512 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18514 buf
= write_compressed_insn (buf
, insn
, 4);
18516 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18517 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18522 insn
= read_compressed_insn (buf
, 4);
18524 /* Relax 32-bit branches to a sequence of instructions. */
18525 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18526 _("relaxed out-of-range branch into a jump"));
18528 /* Set the short-delay-slot bit. */
18529 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18531 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18535 /* Reverse the branch. */
18536 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18537 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18538 insn
^= 0x20000000;
18539 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18540 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18541 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18542 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18543 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18544 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18545 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18546 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18547 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18548 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18549 insn
^= 0x00400000;
18550 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18551 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18552 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18553 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18554 insn
^= 0x00200000;
18555 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18557 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18559 insn
^= 0x00800000;
18565 /* Clear the and-link and short-delay-slot bits. */
18566 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18568 /* bltzal 0x40200000 bgezal 0x40600000 */
18569 /* bltzals 0x42200000 bgezals 0x42600000 */
18570 insn
&= ~0x02200000;
18573 /* Make a label at the end for use with the branch. */
18574 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18575 micromips_label_inc ();
18576 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18579 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18580 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18581 fixp
->fx_file
= fragp
->fr_file
;
18582 fixp
->fx_line
= fragp
->fr_line
;
18584 /* Branch over the jump. */
18585 buf
= write_compressed_insn (buf
, insn
, 4);
18591 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18593 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18599 unsigned long jal
= (short_ds
|| nods
18600 ? 0x74000000 : 0xf4000000); /* jal/s */
18602 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18603 insn
= al
? jal
: 0xd4000000;
18605 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18606 fragp
->fr_symbol
, fragp
->fr_offset
,
18607 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18608 fixp
->fx_file
= fragp
->fr_file
;
18609 fixp
->fx_line
= fragp
->fr_line
;
18611 buf
= write_compressed_insn (buf
, insn
, 4);
18613 if (compact
|| nods
)
18617 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18619 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18624 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18626 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18627 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18628 insn
|= at
<< MICROMIPSOP_SH_RT
;
18630 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18631 fragp
->fr_symbol
, fragp
->fr_offset
,
18632 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18633 fixp
->fx_file
= fragp
->fr_file
;
18634 fixp
->fx_line
= fragp
->fr_line
;
18636 buf
= write_compressed_insn (buf
, insn
, 4);
18638 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18639 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18640 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18642 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18643 fragp
->fr_symbol
, fragp
->fr_offset
,
18644 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18645 fixp
->fx_file
= fragp
->fr_file
;
18646 fixp
->fx_line
= fragp
->fr_line
;
18648 buf
= write_compressed_insn (buf
, insn
, 4);
18653 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18654 insn
|= at
<< MICROMIPSOP_SH_RS
;
18656 buf
= write_compressed_insn (buf
, insn
, 4);
18658 if (compact
|| nods
)
18660 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18664 /* jr/jrc/jalr/jalrs $at */
18665 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18666 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18668 insn
= al
? jalr
: jr
;
18669 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18671 buf
= write_compressed_insn (buf
, insn
, 2);
18676 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18678 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18683 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18687 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18690 const struct mips_int_operand
*operand
;
18693 unsigned int user_length
;
18694 bfd_boolean need_reloc
;
18695 unsigned long insn
;
18700 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18701 operand
= mips16_immed_operand (type
, FALSE
);
18703 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18704 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18705 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18707 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18708 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18709 || (operand
->root
.type
== OP_PCREL
&& !mac
18711 : !bfd_is_abs_section (symsec
)));
18713 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18715 const struct mips_pcrel_operand
*pcrel_op
;
18717 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18719 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18721 if (!mips_ignore_branch_isa
18722 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18723 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18724 _("branch to a symbol in another ISA mode"));
18725 else if ((fragp
->fr_offset
& 0x1) != 0)
18726 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18727 _("branch to misaligned address (0x%lx)"),
18731 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18733 /* Make sure the section winds up with the alignment we have
18735 if (operand
->shift
> 0)
18736 record_alignment (asec
, operand
->shift
);
18739 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18740 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18743 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18744 _("macro instruction expanded into multiple "
18745 "instructions in a branch delay slot"));
18747 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18748 _("extended instruction in a branch delay slot"));
18750 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18751 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18752 _("macro instruction expanded into multiple "
18755 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18757 insn
= read_compressed_insn (buf
, 2);
18759 insn
|= MIPS16_EXTEND
;
18761 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18763 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18775 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18776 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18778 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
18784 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18786 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18787 fragp
->fr_symbol
, fragp
->fr_offset
,
18788 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18789 fixp
->fx_file
= fragp
->fr_file
;
18790 fixp
->fx_line
= fragp
->fr_line
;
18792 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
18793 fragp
->fr_symbol
, fragp
->fr_offset
,
18794 FALSE
, BFD_RELOC_MIPS16_LO16
);
18795 fixp
->fx_file
= fragp
->fr_file
;
18796 fixp
->fx_line
= fragp
->fr_line
;
18801 switch (insn
& 0xf800)
18803 case 0x0800: /* ADDIU */
18804 reg
= (insn
>> 8) & 0x7;
18805 op
= 0xf0004800 | (reg
<< 8);
18807 case 0xb000: /* LW */
18808 reg
= (insn
>> 8) & 0x7;
18809 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18811 case 0xf800: /* I64 */
18812 reg
= (insn
>> 5) & 0x7;
18813 switch (insn
& 0x0700)
18815 case 0x0400: /* LD */
18816 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18818 case 0x0600: /* DADDIU */
18819 op
= 0xf000fd00 | (reg
<< 5);
18829 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
18830 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18831 buf
= write_compressed_insn (buf
, new, 4);
18834 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18835 buf
= write_compressed_insn (buf
, new, 4);
18837 op
|= mips16_immed_extend (val
, 16);
18838 buf
= write_compressed_insn (buf
, op
, 4);
18840 fragp
->fr_fix
+= e2
? 8 : 12;
18844 unsigned int length
= ext
? 4 : 2;
18848 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18855 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18860 if (mac
|| reloc
== BFD_RELOC_NONE
)
18861 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18862 _("unsupported relocation"));
18865 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18866 fragp
->fr_symbol
, fragp
->fr_offset
,
18868 fixp
->fx_file
= fragp
->fr_file
;
18869 fixp
->fx_line
= fragp
->fr_line
;
18872 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18873 _("invalid unextended operand value"));
18876 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18877 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18879 gas_assert (mips16_opcode_length (insn
) == length
);
18880 write_compressed_insn (buf
, insn
, length
);
18881 fragp
->fr_fix
+= length
;
18886 relax_substateT subtype
= fragp
->fr_subtype
;
18887 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18888 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18892 first
= RELAX_FIRST (subtype
);
18893 second
= RELAX_SECOND (subtype
);
18894 fixp
= (fixS
*) fragp
->fr_opcode
;
18896 /* If the delay slot chosen does not match the size of the instruction,
18897 then emit a warning. */
18898 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18899 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18904 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18905 | RELAX_DELAY_SLOT_SIZE_FIRST
18906 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18907 msg
= macro_warning (s
);
18909 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18913 /* Possibly emit a warning if we've chosen the longer option. */
18914 if (use_second
== second_longer
)
18920 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18921 msg
= macro_warning (s
);
18923 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18927 /* Go through all the fixups for the first sequence. Disable them
18928 (by marking them as done) if we're going to use the second
18929 sequence instead. */
18931 && fixp
->fx_frag
== fragp
18932 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18934 if (subtype
& RELAX_USE_SECOND
)
18936 fixp
= fixp
->fx_next
;
18939 /* Go through the fixups for the second sequence. Disable them if
18940 we're going to use the first sequence, otherwise adjust their
18941 addresses to account for the relaxation. */
18942 while (fixp
&& fixp
->fx_frag
== fragp
)
18944 if (subtype
& RELAX_USE_SECOND
)
18945 fixp
->fx_where
-= first
;
18948 fixp
= fixp
->fx_next
;
18951 /* Now modify the frag contents. */
18952 if (subtype
& RELAX_USE_SECOND
)
18956 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18957 memmove (start
, start
+ first
, second
);
18958 fragp
->fr_fix
-= first
;
18961 fragp
->fr_fix
-= second
;
18965 /* This function is called after the relocs have been generated.
18966 We've been storing mips16 text labels as odd. Here we convert them
18967 back to even for the convenience of the debugger. */
18970 mips_frob_file_after_relocs (void)
18973 unsigned int count
, i
;
18975 syms
= bfd_get_outsymbols (stdoutput
);
18976 count
= bfd_get_symcount (stdoutput
);
18977 for (i
= 0; i
< count
; i
++, syms
++)
18978 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18979 && ((*syms
)->value
& 1) != 0)
18981 (*syms
)->value
&= ~1;
18982 /* If the symbol has an odd size, it was probably computed
18983 incorrectly, so adjust that as well. */
18984 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18985 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18989 /* This function is called whenever a label is defined, including fake
18990 labels instantiated off the dot special symbol. It is used when
18991 handling branch delays; if a branch has a label, we assume we cannot
18992 move it. This also bumps the value of the symbol by 1 in compressed
18996 mips_record_label (symbolS
*sym
)
18998 segment_info_type
*si
= seg_info (now_seg
);
18999 struct insn_label_list
*l
;
19001 if (free_insn_labels
== NULL
)
19002 l
= XNEW (struct insn_label_list
);
19005 l
= free_insn_labels
;
19006 free_insn_labels
= l
->next
;
19010 l
->next
= si
->label_list
;
19011 si
->label_list
= l
;
19014 /* This function is called as tc_frob_label() whenever a label is defined
19015 and adds a DWARF-2 record we only want for true labels. */
19018 mips_define_label (symbolS
*sym
)
19020 mips_record_label (sym
);
19021 dwarf2_emit_label (sym
);
19024 /* This function is called by tc_new_dot_label whenever a new dot symbol
19028 mips_add_dot_label (symbolS
*sym
)
19030 mips_record_label (sym
);
19031 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19032 mips_compressed_mark_label (sym
);
19035 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19036 static unsigned int
19037 mips_convert_ase_flags (int ase
)
19039 unsigned int ext_ases
= 0;
19042 ext_ases
|= AFL_ASE_DSP
;
19043 if (ase
& ASE_DSPR2
)
19044 ext_ases
|= AFL_ASE_DSPR2
;
19045 if (ase
& ASE_DSPR3
)
19046 ext_ases
|= AFL_ASE_DSPR3
;
19048 ext_ases
|= AFL_ASE_EVA
;
19050 ext_ases
|= AFL_ASE_MCU
;
19051 if (ase
& ASE_MDMX
)
19052 ext_ases
|= AFL_ASE_MDMX
;
19053 if (ase
& ASE_MIPS3D
)
19054 ext_ases
|= AFL_ASE_MIPS3D
;
19056 ext_ases
|= AFL_ASE_MT
;
19057 if (ase
& ASE_SMARTMIPS
)
19058 ext_ases
|= AFL_ASE_SMARTMIPS
;
19059 if (ase
& ASE_VIRT
)
19060 ext_ases
|= AFL_ASE_VIRT
;
19062 ext_ases
|= AFL_ASE_MSA
;
19064 ext_ases
|= AFL_ASE_XPA
;
19065 if (ase
& ASE_MIPS16E2
)
19066 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19068 ext_ases
|= AFL_ASE_CRC
;
19069 if (ase
& ASE_GINV
)
19070 ext_ases
|= AFL_ASE_GINV
;
19071 if (ase
& ASE_LOONGSON_MMI
)
19072 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19073 if (ase
& ASE_LOONGSON_CAM
)
19074 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19075 if (ase
& ASE_LOONGSON_EXT
)
19076 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19077 if (ase
& ASE_LOONGSON_EXT2
)
19078 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19082 /* Some special processing for a MIPS ELF file. */
19085 mips_elf_final_processing (void)
19088 Elf_Internal_ABIFlags_v0 flags
;
19092 switch (file_mips_opts
.isa
)
19095 flags
.isa_level
= 1;
19098 flags
.isa_level
= 2;
19101 flags
.isa_level
= 3;
19104 flags
.isa_level
= 4;
19107 flags
.isa_level
= 5;
19110 flags
.isa_level
= 32;
19114 flags
.isa_level
= 32;
19118 flags
.isa_level
= 32;
19122 flags
.isa_level
= 32;
19126 flags
.isa_level
= 32;
19130 flags
.isa_level
= 64;
19134 flags
.isa_level
= 64;
19138 flags
.isa_level
= 64;
19142 flags
.isa_level
= 64;
19146 flags
.isa_level
= 64;
19151 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19152 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19153 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19154 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19156 flags
.cpr2_size
= AFL_REG_NONE
;
19157 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19158 Tag_GNU_MIPS_ABI_FP
);
19159 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19160 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19161 if (file_ase_mips16
)
19162 flags
.ases
|= AFL_ASE_MIPS16
;
19163 if (file_ase_micromips
)
19164 flags
.ases
|= AFL_ASE_MICROMIPS
;
19166 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19167 || file_mips_opts
.fp
== 64)
19168 && file_mips_opts
.oddspreg
)
19169 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19172 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19173 ((Elf_External_ABIFlags_v0
*)
19176 /* Write out the register information. */
19177 if (mips_abi
!= N64_ABI
)
19181 s
.ri_gprmask
= mips_gprmask
;
19182 s
.ri_cprmask
[0] = mips_cprmask
[0];
19183 s
.ri_cprmask
[1] = mips_cprmask
[1];
19184 s
.ri_cprmask
[2] = mips_cprmask
[2];
19185 s
.ri_cprmask
[3] = mips_cprmask
[3];
19186 /* The gp_value field is set by the MIPS ELF backend. */
19188 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19189 ((Elf32_External_RegInfo
*)
19190 mips_regmask_frag
));
19194 Elf64_Internal_RegInfo s
;
19196 s
.ri_gprmask
= mips_gprmask
;
19198 s
.ri_cprmask
[0] = mips_cprmask
[0];
19199 s
.ri_cprmask
[1] = mips_cprmask
[1];
19200 s
.ri_cprmask
[2] = mips_cprmask
[2];
19201 s
.ri_cprmask
[3] = mips_cprmask
[3];
19202 /* The gp_value field is set by the MIPS ELF backend. */
19204 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19205 ((Elf64_External_RegInfo
*)
19206 mips_regmask_frag
));
19209 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19210 sort of BFD interface for this. */
19211 if (mips_any_noreorder
)
19212 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19213 if (mips_pic
!= NO_PIC
)
19215 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19216 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19219 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19221 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19222 defined at present; this might need to change in future. */
19223 if (file_ase_mips16
)
19224 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19225 if (file_ase_micromips
)
19226 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19227 if (file_mips_opts
.ase
& ASE_MDMX
)
19228 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19230 /* Set the MIPS ELF ABI flags. */
19231 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19232 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19233 else if (mips_abi
== O64_ABI
)
19234 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19235 else if (mips_abi
== EABI_ABI
)
19237 if (file_mips_opts
.gp
== 64)
19238 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19240 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19243 /* Nothing to do for N32_ABI or N64_ABI. */
19245 if (mips_32bitmode
)
19246 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19248 if (mips_nan2008
== 1)
19249 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19251 /* 32 bit code with 64 bit FP registers. */
19252 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19253 Tag_GNU_MIPS_ABI_FP
);
19254 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19255 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19258 typedef struct proc
{
19260 symbolS
*func_end_sym
;
19261 unsigned long reg_mask
;
19262 unsigned long reg_offset
;
19263 unsigned long fpreg_mask
;
19264 unsigned long fpreg_offset
;
19265 unsigned long frame_offset
;
19266 unsigned long frame_reg
;
19267 unsigned long pc_reg
;
19270 static procS cur_proc
;
19271 static procS
*cur_proc_ptr
;
19272 static int numprocs
;
19274 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19275 as "2", and a normal nop as "0". */
19277 #define NOP_OPCODE_MIPS 0
19278 #define NOP_OPCODE_MIPS16 1
19279 #define NOP_OPCODE_MICROMIPS 2
19282 mips_nop_opcode (void)
19284 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19285 return NOP_OPCODE_MICROMIPS
;
19286 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19287 return NOP_OPCODE_MIPS16
;
19289 return NOP_OPCODE_MIPS
;
19292 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19293 32-bit microMIPS NOPs here (if applicable). */
19296 mips_handle_align (fragS
*fragp
)
19300 int bytes
, size
, excess
;
19303 if (fragp
->fr_type
!= rs_align_code
)
19306 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19308 switch (nop_opcode
)
19310 case NOP_OPCODE_MICROMIPS
:
19311 opcode
= micromips_nop32_insn
.insn_opcode
;
19314 case NOP_OPCODE_MIPS16
:
19315 opcode
= mips16_nop_insn
.insn_opcode
;
19318 case NOP_OPCODE_MIPS
:
19320 opcode
= nop_insn
.insn_opcode
;
19325 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19326 excess
= bytes
% size
;
19328 /* Handle the leading part if we're not inserting a whole number of
19329 instructions, and make it the end of the fixed part of the frag.
19330 Try to fit in a short microMIPS NOP if applicable and possible,
19331 and use zeroes otherwise. */
19332 gas_assert (excess
< 4);
19333 fragp
->fr_fix
+= excess
;
19338 /* Fall through. */
19340 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19342 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19346 /* Fall through. */
19349 /* Fall through. */
19354 md_number_to_chars (p
, opcode
, size
);
19355 fragp
->fr_var
= size
;
19364 if (*input_line_pointer
== '-')
19366 ++input_line_pointer
;
19369 if (!ISDIGIT (*input_line_pointer
))
19370 as_bad (_("expected simple number"));
19371 if (input_line_pointer
[0] == '0')
19373 if (input_line_pointer
[1] == 'x')
19375 input_line_pointer
+= 2;
19376 while (ISXDIGIT (*input_line_pointer
))
19379 val
|= hex_value (*input_line_pointer
++);
19381 return negative
? -val
: val
;
19385 ++input_line_pointer
;
19386 while (ISDIGIT (*input_line_pointer
))
19389 val
|= *input_line_pointer
++ - '0';
19391 return negative
? -val
: val
;
19394 if (!ISDIGIT (*input_line_pointer
))
19396 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19397 *input_line_pointer
, *input_line_pointer
);
19398 as_warn (_("invalid number"));
19401 while (ISDIGIT (*input_line_pointer
))
19404 val
+= *input_line_pointer
++ - '0';
19406 return negative
? -val
: val
;
19409 /* The .file directive; just like the usual .file directive, but there
19410 is an initial number which is the ECOFF file index. In the non-ECOFF
19411 case .file implies DWARF-2. */
19414 s_mips_file (int x ATTRIBUTE_UNUSED
)
19416 static int first_file_directive
= 0;
19418 if (ECOFF_DEBUGGING
)
19427 filename
= dwarf2_directive_filename ();
19429 /* Versions of GCC up to 3.1 start files with a ".file"
19430 directive even for stabs output. Make sure that this
19431 ".file" is handled. Note that you need a version of GCC
19432 after 3.1 in order to support DWARF-2 on MIPS. */
19433 if (filename
!= NULL
&& ! first_file_directive
)
19435 (void) new_logical_line (filename
, -1);
19436 s_app_file_string (filename
, 0);
19438 first_file_directive
= 1;
19442 /* The .loc directive, implying DWARF-2. */
19445 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19447 if (!ECOFF_DEBUGGING
)
19448 dwarf2_directive_loc (0);
19451 /* The .end directive. */
19454 s_mips_end (int x ATTRIBUTE_UNUSED
)
19458 /* Following functions need their own .frame and .cprestore directives. */
19459 mips_frame_reg_valid
= 0;
19460 mips_cprestore_valid
= 0;
19462 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19465 demand_empty_rest_of_line ();
19470 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19471 as_warn (_(".end not in text section"));
19475 as_warn (_(".end directive without a preceding .ent directive"));
19476 demand_empty_rest_of_line ();
19482 gas_assert (S_GET_NAME (p
));
19483 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19484 as_warn (_(".end symbol does not match .ent symbol"));
19486 if (debug_type
== DEBUG_STABS
)
19487 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19491 as_warn (_(".end directive missing or unknown symbol"));
19493 /* Create an expression to calculate the size of the function. */
19494 if (p
&& cur_proc_ptr
)
19496 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19497 expressionS
*exp
= XNEW (expressionS
);
19500 exp
->X_op
= O_subtract
;
19501 exp
->X_add_symbol
= symbol_temp_new_now ();
19502 exp
->X_op_symbol
= p
;
19503 exp
->X_add_number
= 0;
19505 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19508 #ifdef md_flush_pending_output
19509 md_flush_pending_output ();
19512 /* Generate a .pdr section. */
19513 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19515 segT saved_seg
= now_seg
;
19516 subsegT saved_subseg
= now_subseg
;
19520 gas_assert (pdr_seg
);
19521 subseg_set (pdr_seg
, 0);
19523 /* Write the symbol. */
19524 exp
.X_op
= O_symbol
;
19525 exp
.X_add_symbol
= p
;
19526 exp
.X_add_number
= 0;
19527 emit_expr (&exp
, 4);
19529 fragp
= frag_more (7 * 4);
19531 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19532 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19533 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19534 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19535 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19536 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19537 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19539 subseg_set (saved_seg
, saved_subseg
);
19542 cur_proc_ptr
= NULL
;
19545 /* The .aent and .ent directives. */
19548 s_mips_ent (int aent
)
19552 symbolP
= get_symbol ();
19553 if (*input_line_pointer
== ',')
19554 ++input_line_pointer
;
19555 SKIP_WHITESPACE ();
19556 if (ISDIGIT (*input_line_pointer
)
19557 || *input_line_pointer
== '-')
19560 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19561 as_warn (_(".ent or .aent not in text section"));
19563 if (!aent
&& cur_proc_ptr
)
19564 as_warn (_("missing .end"));
19568 /* This function needs its own .frame and .cprestore directives. */
19569 mips_frame_reg_valid
= 0;
19570 mips_cprestore_valid
= 0;
19572 cur_proc_ptr
= &cur_proc
;
19573 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19575 cur_proc_ptr
->func_sym
= symbolP
;
19579 if (debug_type
== DEBUG_STABS
)
19580 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19581 S_GET_NAME (symbolP
));
19584 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19586 demand_empty_rest_of_line ();
19589 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19590 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19591 s_mips_frame is used so that we can set the PDR information correctly.
19592 We can't use the ecoff routines because they make reference to the ecoff
19593 symbol table (in the mdebug section). */
19596 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19598 if (ECOFF_DEBUGGING
)
19604 if (cur_proc_ptr
== (procS
*) NULL
)
19606 as_warn (_(".frame outside of .ent"));
19607 demand_empty_rest_of_line ();
19611 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19613 SKIP_WHITESPACE ();
19614 if (*input_line_pointer
++ != ','
19615 || get_absolute_expression_and_terminator (&val
) != ',')
19617 as_warn (_("bad .frame directive"));
19618 --input_line_pointer
;
19619 demand_empty_rest_of_line ();
19623 cur_proc_ptr
->frame_offset
= val
;
19624 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19626 demand_empty_rest_of_line ();
19630 /* The .fmask and .mask directives. If the mdebug section is present
19631 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19632 embedded targets, s_mips_mask is used so that we can set the PDR
19633 information correctly. We can't use the ecoff routines because they
19634 make reference to the ecoff symbol table (in the mdebug section). */
19637 s_mips_mask (int reg_type
)
19639 if (ECOFF_DEBUGGING
)
19640 s_ignore (reg_type
);
19645 if (cur_proc_ptr
== (procS
*) NULL
)
19647 as_warn (_(".mask/.fmask outside of .ent"));
19648 demand_empty_rest_of_line ();
19652 if (get_absolute_expression_and_terminator (&mask
) != ',')
19654 as_warn (_("bad .mask/.fmask directive"));
19655 --input_line_pointer
;
19656 demand_empty_rest_of_line ();
19660 off
= get_absolute_expression ();
19662 if (reg_type
== 'F')
19664 cur_proc_ptr
->fpreg_mask
= mask
;
19665 cur_proc_ptr
->fpreg_offset
= off
;
19669 cur_proc_ptr
->reg_mask
= mask
;
19670 cur_proc_ptr
->reg_offset
= off
;
19673 demand_empty_rest_of_line ();
19677 /* A table describing all the processors gas knows about. Names are
19678 matched in the order listed.
19680 To ease comparison, please keep this table in the same order as
19681 gcc's mips_cpu_info_table[]. */
19682 static const struct mips_cpu_info mips_cpu_info_table
[] =
19684 /* Entries for generic ISAs */
19685 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19686 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19687 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19688 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19689 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19690 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19691 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19692 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19693 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19694 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19695 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19696 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19697 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19698 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19699 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19702 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19703 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19704 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19707 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19710 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19711 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19712 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19713 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19714 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19715 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19716 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19717 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19718 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19719 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19720 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19721 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19722 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19723 /* ST Microelectronics Loongson 2E and 2F cores */
19724 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19725 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
19728 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19729 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19730 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19731 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19732 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19733 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19734 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19735 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19736 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19737 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19738 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19739 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19740 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19741 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19742 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19745 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19746 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19747 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19748 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19750 /* MIPS 32 Release 2 */
19751 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19752 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19753 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19754 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19755 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19756 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19757 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19758 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19759 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19760 ISA_MIPS32R2
, CPU_MIPS32R2
},
19761 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19762 ISA_MIPS32R2
, CPU_MIPS32R2
},
19763 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19764 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19765 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19766 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19767 /* Deprecated forms of the above. */
19768 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19769 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19770 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19771 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19772 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19773 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19774 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19775 /* Deprecated forms of the above. */
19776 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19777 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19778 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19779 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19780 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19781 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19782 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19783 /* Deprecated forms of the above. */
19784 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19785 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19786 /* 34Kn is a 34kc without DSP. */
19787 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19788 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19789 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19790 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19791 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19792 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19793 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19794 /* Deprecated forms of the above. */
19795 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19796 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19797 /* 1004K cores are multiprocessor versions of the 34K. */
19798 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19799 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19800 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19801 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19802 /* interaptiv is the new name for 1004kf */
19803 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19804 { "interaptiv-mr2", 0,
19805 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
19806 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
19808 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19809 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19810 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19811 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19814 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19815 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19816 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19817 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19819 /* Broadcom SB-1 CPU core */
19820 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19821 /* Broadcom SB-1A CPU core */
19822 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19824 /* MIPS 64 Release 2 */
19825 /* Loongson CPU core */
19826 /* -march=loongson3a is an alias of -march=gs464 for compatibility */
19827 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
19828 ISA_MIPS64R2
, CPU_GS464
},
19829 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
19830 ISA_MIPS64R2
, CPU_GS464
},
19831 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
19832 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
19833 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
19834 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
19836 /* Cavium Networks Octeon CPU core */
19837 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19838 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19839 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19840 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19843 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19846 XLP is mostly like XLR, with the prominent exception that it is
19847 MIPS64R2 rather than MIPS64. */
19848 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19850 /* MIPS 64 Release 6 */
19851 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19852 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19855 { NULL
, 0, 0, 0, 0 }
19859 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19860 with a final "000" replaced by "k". Ignore case.
19862 Note: this function is shared between GCC and GAS. */
19865 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19867 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19868 given
++, canonical
++;
19870 return ((*given
== 0 && *canonical
== 0)
19871 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19875 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19876 CPU name. We've traditionally allowed a lot of variation here.
19878 Note: this function is shared between GCC and GAS. */
19881 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19883 /* First see if the name matches exactly, or with a final "000"
19884 turned into "k". */
19885 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19888 /* If not, try comparing based on numerical designation alone.
19889 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19890 if (TOLOWER (*given
) == 'r')
19892 if (!ISDIGIT (*given
))
19895 /* Skip over some well-known prefixes in the canonical name,
19896 hoping to find a number there too. */
19897 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19899 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19901 else if (TOLOWER (canonical
[0]) == 'r')
19904 return mips_strict_matching_cpu_name_p (canonical
, given
);
19908 /* Parse an option that takes the name of a processor as its argument.
19909 OPTION is the name of the option and CPU_STRING is the argument.
19910 Return the corresponding processor enumeration if the CPU_STRING is
19911 recognized, otherwise report an error and return null.
19913 A similar function exists in GCC. */
19915 static const struct mips_cpu_info
*
19916 mips_parse_cpu (const char *option
, const char *cpu_string
)
19918 const struct mips_cpu_info
*p
;
19920 /* 'from-abi' selects the most compatible architecture for the given
19921 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19922 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19923 version. Look first at the -mgp options, if given, otherwise base
19924 the choice on MIPS_DEFAULT_64BIT.
19926 Treat NO_ABI like the EABIs. One reason to do this is that the
19927 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19928 architecture. This code picks MIPS I for 'mips' and MIPS III for
19929 'mips64', just as we did in the days before 'from-abi'. */
19930 if (strcasecmp (cpu_string
, "from-abi") == 0)
19932 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19933 return mips_cpu_info_from_isa (ISA_MIPS1
);
19935 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19936 return mips_cpu_info_from_isa (ISA_MIPS3
);
19938 if (file_mips_opts
.gp
>= 0)
19939 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19940 ? ISA_MIPS1
: ISA_MIPS3
);
19942 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19947 /* 'default' has traditionally been a no-op. Probably not very useful. */
19948 if (strcasecmp (cpu_string
, "default") == 0)
19951 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19952 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19955 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19959 /* Return the canonical processor information for ISA (a member of the
19960 ISA_MIPS* enumeration). */
19962 static const struct mips_cpu_info
*
19963 mips_cpu_info_from_isa (int isa
)
19967 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19968 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19969 && isa
== mips_cpu_info_table
[i
].isa
)
19970 return (&mips_cpu_info_table
[i
]);
19975 static const struct mips_cpu_info
*
19976 mips_cpu_info_from_arch (int arch
)
19980 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19981 if (arch
== mips_cpu_info_table
[i
].cpu
)
19982 return (&mips_cpu_info_table
[i
]);
19988 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19992 fprintf (stream
, "%24s", "");
19997 fprintf (stream
, ", ");
20001 if (*col_p
+ strlen (string
) > 72)
20003 fprintf (stream
, "\n%24s", "");
20007 fprintf (stream
, "%s", string
);
20008 *col_p
+= strlen (string
);
20014 md_show_usage (FILE *stream
)
20019 fprintf (stream
, _("\
20021 -EB generate big endian output\n\
20022 -EL generate little endian output\n\
20023 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20024 -G NUM allow referencing objects up to NUM bytes\n\
20025 implicitly with the gp register [default 8]\n"));
20026 fprintf (stream
, _("\
20027 -mips1 generate MIPS ISA I instructions\n\
20028 -mips2 generate MIPS ISA II instructions\n\
20029 -mips3 generate MIPS ISA III instructions\n\
20030 -mips4 generate MIPS ISA IV instructions\n\
20031 -mips5 generate MIPS ISA V instructions\n\
20032 -mips32 generate MIPS32 ISA instructions\n\
20033 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20034 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20035 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20036 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20037 -mips64 generate MIPS64 ISA instructions\n\
20038 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20039 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20040 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20041 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20042 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20046 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20047 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20048 show (stream
, "from-abi", &column
, &first
);
20049 fputc ('\n', stream
);
20051 fprintf (stream
, _("\
20052 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20053 -no-mCPU don't generate code specific to CPU.\n\
20054 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20058 show (stream
, "3900", &column
, &first
);
20059 show (stream
, "4010", &column
, &first
);
20060 show (stream
, "4100", &column
, &first
);
20061 show (stream
, "4650", &column
, &first
);
20062 fputc ('\n', stream
);
20064 fprintf (stream
, _("\
20065 -mips16 generate mips16 instructions\n\
20066 -no-mips16 do not generate mips16 instructions\n"));
20067 fprintf (stream
, _("\
20068 -mmips16e2 generate MIPS16e2 instructions\n\
20069 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20070 fprintf (stream
, _("\
20071 -mmicromips generate microMIPS instructions\n\
20072 -mno-micromips do not generate microMIPS instructions\n"));
20073 fprintf (stream
, _("\
20074 -msmartmips generate smartmips instructions\n\
20075 -mno-smartmips do not generate smartmips instructions\n"));
20076 fprintf (stream
, _("\
20077 -mdsp generate DSP instructions\n\
20078 -mno-dsp do not generate DSP instructions\n"));
20079 fprintf (stream
, _("\
20080 -mdspr2 generate DSP R2 instructions\n\
20081 -mno-dspr2 do not generate DSP R2 instructions\n"));
20082 fprintf (stream
, _("\
20083 -mdspr3 generate DSP R3 instructions\n\
20084 -mno-dspr3 do not generate DSP R3 instructions\n"));
20085 fprintf (stream
, _("\
20086 -mmt generate MT instructions\n\
20087 -mno-mt do not generate MT instructions\n"));
20088 fprintf (stream
, _("\
20089 -mmcu generate MCU instructions\n\
20090 -mno-mcu do not generate MCU instructions\n"));
20091 fprintf (stream
, _("\
20092 -mmsa generate MSA instructions\n\
20093 -mno-msa do not generate MSA instructions\n"));
20094 fprintf (stream
, _("\
20095 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20096 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20097 fprintf (stream
, _("\
20098 -mvirt generate Virtualization instructions\n\
20099 -mno-virt do not generate Virtualization instructions\n"));
20100 fprintf (stream
, _("\
20101 -mcrc generate CRC instructions\n\
20102 -mno-crc do not generate CRC instructions\n"));
20103 fprintf (stream
, _("\
20104 -mginv generate Global INValidate (GINV) instructions\n\
20105 -mno-ginv do not generate Global INValidate instructions\n"));
20106 fprintf (stream
, _("\
20107 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20108 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20109 fprintf (stream
, _("\
20110 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20111 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20112 fprintf (stream
, _("\
20113 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20114 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20115 fprintf (stream
, _("\
20116 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20117 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20118 fprintf (stream
, _("\
20119 -minsn32 only generate 32-bit microMIPS instructions\n\
20120 -mno-insn32 generate all microMIPS instructions\n"));
20121 fprintf (stream
, _("\
20122 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20123 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20124 -mfix-vr4120 work around certain VR4120 errata\n\
20125 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20126 -mfix-24k insert a nop after ERET and DERET instructions\n\
20127 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20128 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20129 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20130 -msym32 assume all symbols have 32-bit values\n\
20131 -O0 do not remove unneeded NOPs, do not swap branches\n\
20132 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20133 -O2 remove unneeded NOPs and swap branches\n\
20134 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20135 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20136 fprintf (stream
, _("\
20137 -mhard-float allow floating-point instructions\n\
20138 -msoft-float do not allow floating-point instructions\n\
20139 -msingle-float only allow 32-bit floating-point operations\n\
20140 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20141 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20142 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20143 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20144 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20145 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20149 show (stream
, "legacy", &column
, &first
);
20150 show (stream
, "2008", &column
, &first
);
20152 fputc ('\n', stream
);
20154 fprintf (stream
, _("\
20155 -KPIC, -call_shared generate SVR4 position independent code\n\
20156 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20157 -mvxworks-pic generate VxWorks position independent code\n\
20158 -non_shared do not generate code that can operate with DSOs\n\
20159 -xgot assume a 32 bit GOT\n\
20160 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20161 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20162 position dependent (non shared) code\n\
20163 -mabi=ABI create ABI conformant object file for:\n"));
20167 show (stream
, "32", &column
, &first
);
20168 show (stream
, "o64", &column
, &first
);
20169 show (stream
, "n32", &column
, &first
);
20170 show (stream
, "64", &column
, &first
);
20171 show (stream
, "eabi", &column
, &first
);
20173 fputc ('\n', stream
);
20175 fprintf (stream
, _("\
20176 -32 create o32 ABI object file%s\n"),
20177 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20178 fprintf (stream
, _("\
20179 -n32 create n32 ABI object file%s\n"),
20180 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20181 fprintf (stream
, _("\
20182 -64 create 64 ABI object file%s\n"),
20183 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20188 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20190 if (HAVE_64BIT_SYMBOLS
)
20191 return dwarf2_format_64bit_irix
;
20193 return dwarf2_format_32bit
;
20198 mips_dwarf2_addr_size (void)
20200 if (HAVE_64BIT_OBJECTS
)
20206 /* Standard calling conventions leave the CFA at SP on entry. */
20208 mips_cfi_frame_initial_instructions (void)
20210 cfi_add_CFA_def_cfa_register (SP
);
20214 tc_mips_regname_to_dw2regnum (char *regname
)
20216 unsigned int regnum
= -1;
20219 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20225 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20226 Given a symbolic attribute NAME, return the proper integer value.
20227 Returns -1 if the attribute is not known. */
20230 mips_convert_symbolic_attribute (const char *name
)
20232 static const struct
20237 attribute_table
[] =
20239 #define T(tag) {#tag, tag}
20240 T (Tag_GNU_MIPS_ABI_FP
),
20241 T (Tag_GNU_MIPS_ABI_MSA
),
20249 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20250 if (streq (name
, attribute_table
[i
].name
))
20251 return attribute_table
[i
].tag
;
20259 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20261 mips_emit_delays ();
20263 as_warn (_("missing .end at end of assembly"));
20265 /* Just in case no code was emitted, do the consistency check. */
20266 file_mips_check_options ();
20268 /* Set a floating-point ABI if the user did not. */
20269 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20271 /* Perform consistency checks on the floating-point ABI. */
20272 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20273 Tag_GNU_MIPS_ABI_FP
);
20274 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20275 check_fpabi (fpabi
);
20279 /* Soft-float gets precedence over single-float, the two options should
20280 not be used together so this should not matter. */
20281 if (file_mips_opts
.soft_float
== 1)
20282 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20283 /* Single-float gets precedence over all double_float cases. */
20284 else if (file_mips_opts
.single_float
== 1)
20285 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20288 switch (file_mips_opts
.fp
)
20291 if (file_mips_opts
.gp
== 32)
20292 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20295 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20298 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20299 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20300 else if (file_mips_opts
.gp
== 32)
20301 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20303 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20308 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20309 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20313 /* Returns the relocation type required for a particular CFI encoding. */
20315 bfd_reloc_code_real_type
20316 mips_cfi_reloc_for_encoding (int encoding
)
20318 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20319 return BFD_RELOC_32_PCREL
;
20320 else return BFD_RELOC_NONE
;