1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* Whether or not we have code that can call pic code. */
135 int mips_abicalls
= FALSE
;
137 /* This is the set of options which may be modified by the .set
138 pseudo-op. We use a struct so that .set push and .set pop are more
141 struct mips_set_options
143 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
144 if it has not been initialized. Changed by `.set mipsN', and the
145 -mipsN command line option, and the default CPU. */
147 /* Enabled Application Specific Extensions (ASEs). These are set to -1
148 if they have not been initialized. Changed by `.set <asename>', by
149 command line options, and based on the default architecture. */
152 /* Whether we are assembling for the mips16 processor. 0 if we are
153 not, 1 if we are, and -1 if the value has not been initialized.
154 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
155 -nomips16 command line options, and the default CPU. */
157 /* Non-zero if we should not reorder instructions. Changed by `.set
158 reorder' and `.set noreorder'. */
160 /* Non-zero if we should not permit the $at ($1) register to be used
161 in instructions. Changed by `.set at' and `.set noat'. */
163 /* Non-zero if we should warn when a macro instruction expands into
164 more than one machine instruction. Changed by `.set nomacro' and
166 int warn_about_macros
;
167 /* Non-zero if we should not move instructions. Changed by `.set
168 move', `.set volatile', `.set nomove', and `.set novolatile'. */
170 /* Non-zero if we should not optimize branches by moving the target
171 of the branch into the delay slot. Actually, we don't perform
172 this optimization anyhow. Changed by `.set bopt' and `.set
175 /* Non-zero if we should not autoextend mips16 instructions.
176 Changed by `.set autoextend' and `.set noautoextend'. */
178 /* Restrict general purpose registers and floating point registers
179 to 32 bit. This is initially determined when -mgp32 or -mfp32
180 is passed but can changed if the assembler code uses .set mipsN. */
185 /* True if -mgp32 was passed. */
186 static int file_mips_gp32
= -1;
188 /* True if -mfp32 was passed. */
189 static int file_mips_fp32
= -1;
191 /* This is the struct we use to hold the current set of options. Note
192 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
193 -1 to indicate that they have not been initialized. */
195 static struct mips_set_options mips_opts
=
197 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
200 /* These variables are filled in with the masks of registers used.
201 The object format code reads them and puts them in the appropriate
203 unsigned long mips_gprmask
;
204 unsigned long mips_cprmask
[4];
206 /* MIPS ISA we are using for this output file. */
207 static int file_mips_isa
= ISA_UNKNOWN
;
209 /* True if -mips16 was passed or implied by arguments passed on the
210 command line (e.g., by -march). */
211 static int file_ase_mips16
;
213 /* True if -mips3d was passed or implied by arguments passed on the
214 command line (e.g., by -march). */
215 static int file_ase_mips3d
;
217 /* True if -mdmx was passed or implied by arguments passed on the
218 command line (e.g., by -march). */
219 static int file_ase_mdmx
;
221 /* The argument of the -march= flag. The architecture we are assembling. */
222 static int mips_arch
= CPU_UNKNOWN
;
223 static const char *mips_arch_string
;
224 static const struct mips_cpu_info
*mips_arch_info
;
226 /* The argument of the -mtune= flag. The architecture for which we
228 static int mips_tune
= CPU_UNKNOWN
;
229 static const char *mips_tune_string
;
230 static const struct mips_cpu_info
*mips_tune_info
;
232 /* True when generating 32-bit code for a 64-bit processor. */
233 static int mips_32bitmode
= 0;
235 /* Some ISA's have delay slots for instructions which read or write
236 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
237 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
238 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
239 delay slot in this ISA. The uses of this macro assume that any
240 ISA that has delay slots for one of these, has them for all. They
241 also assume that ISAs which don't have delays for these insns, don't
242 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
243 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
245 || (ISA) == ISA_MIPS2 \
246 || (ISA) == ISA_MIPS3 \
249 /* True if the given ABI requires 32-bit registers. */
250 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
252 /* Likewise 64-bit registers. */
253 #define ABI_NEEDS_64BIT_REGS(ABI) \
255 || (ABI) == N64_ABI \
258 /* Return true if ISA supports 64 bit gp register instructions. */
259 #define ISA_HAS_64BIT_REGS(ISA) ( \
261 || (ISA) == ISA_MIPS4 \
262 || (ISA) == ISA_MIPS5 \
263 || (ISA) == ISA_MIPS64 \
266 /* Return true if ISA supports 64-bit right rotate (dror et al.)
268 #define ISA_HAS_DROR(ISA) ( \
272 /* Return true if ISA supports 32-bit right rotate (ror et al.)
274 #define ISA_HAS_ROR(ISA) ( \
275 (ISA) == ISA_MIPS32R2 \
278 #define HAVE_32BIT_GPRS \
279 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
281 #define HAVE_32BIT_FPRS \
282 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
284 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
285 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
287 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
289 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
291 /* We can only have 64bit addresses if the object file format
293 #define HAVE_32BIT_ADDRESSES \
295 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
296 || ! HAVE_64BIT_OBJECTS) \
297 && mips_pic != EMBEDDED_PIC))
299 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
300 #define HAVE_64BIT_ADDRESS_CONSTANTS (HAVE_64BIT_ADDRESSES \
303 /* Return true if the given CPU supports the MIPS16 ASE. */
304 #define CPU_HAS_MIPS16(cpu) \
305 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
306 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
308 /* Return true if the given CPU supports the MIPS3D ASE. */
309 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
312 /* Return true if the given CPU supports the MDMX ASE. */
313 #define CPU_HAS_MDMX(cpu) (FALSE \
316 /* True if CPU has a dror instruction. */
317 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
319 /* True if CPU has a ror instruction. */
320 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
322 /* Whether the processor uses hardware interlocks to protect
323 reads from the HI and LO registers, and thus does not
324 require nops to be inserted. */
326 #define hilo_interlocks (mips_arch == CPU_R4010 \
327 || mips_arch == CPU_VR5500 \
328 || mips_arch == CPU_SB1 \
331 /* Whether the processor uses hardware interlocks to protect reads
332 from the GPRs, and thus does not require nops to be inserted. */
333 #define gpr_interlocks \
334 (mips_opts.isa != ISA_MIPS1 \
335 || mips_arch == CPU_VR5400 \
336 || mips_arch == CPU_VR5500 \
337 || mips_arch == CPU_R3900)
339 /* As with other "interlocks" this is used by hardware that has FP
340 (co-processor) interlocks. */
341 /* Itbl support may require additional care here. */
342 #define cop_interlocks (mips_arch == CPU_R4300 \
343 || mips_arch == CPU_VR5400 \
344 || mips_arch == CPU_VR5500 \
345 || mips_arch == CPU_SB1 \
348 /* Is this a mfhi or mflo instruction? */
349 #define MF_HILO_INSN(PINFO) \
350 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
352 /* MIPS PIC level. */
354 enum mips_pic_level mips_pic
;
356 /* Warn about all NOPS that the assembler generates. */
357 static int warn_nops
= 0;
359 /* 1 if we should generate 32 bit offsets from the $gp register in
360 SVR4_PIC mode. Currently has no meaning in other modes. */
361 static int mips_big_got
= 0;
363 /* 1 if trap instructions should used for overflow rather than break
365 static int mips_trap
= 0;
367 /* 1 if double width floating point constants should not be constructed
368 by assembling two single width halves into two single width floating
369 point registers which just happen to alias the double width destination
370 register. On some architectures this aliasing can be disabled by a bit
371 in the status register, and the setting of this bit cannot be determined
372 automatically at assemble time. */
373 static int mips_disable_float_construction
;
375 /* Non-zero if any .set noreorder directives were used. */
377 static int mips_any_noreorder
;
379 /* Non-zero if nops should be inserted when the register referenced in
380 an mfhi/mflo instruction is read in the next two instructions. */
381 static int mips_7000_hilo_fix
;
383 /* The size of the small data section. */
384 static unsigned int g_switch_value
= 8;
385 /* Whether the -G option was used. */
386 static int g_switch_seen
= 0;
391 /* If we can determine in advance that GP optimization won't be
392 possible, we can skip the relaxation stuff that tries to produce
393 GP-relative references. This makes delay slot optimization work
396 This function can only provide a guess, but it seems to work for
397 gcc output. It needs to guess right for gcc, otherwise gcc
398 will put what it thinks is a GP-relative instruction in a branch
401 I don't know if a fix is needed for the SVR4_PIC mode. I've only
402 fixed it for the non-PIC mode. KR 95/04/07 */
403 static int nopic_need_relax
PARAMS ((symbolS
*, int));
405 /* handle of the OPCODE hash table */
406 static struct hash_control
*op_hash
= NULL
;
408 /* The opcode hash table we use for the mips16. */
409 static struct hash_control
*mips16_op_hash
= NULL
;
411 /* This array holds the chars that always start a comment. If the
412 pre-processor is disabled, these aren't very useful */
413 const char comment_chars
[] = "#";
415 /* This array holds the chars that only start a comment at the beginning of
416 a line. If the line seems to have the form '# 123 filename'
417 .line and .file directives will appear in the pre-processed output */
418 /* Note that input_file.c hand checks for '#' at the beginning of the
419 first line of the input file. This is because the compiler outputs
420 #NO_APP at the beginning of its output. */
421 /* Also note that C style comments are always supported. */
422 const char line_comment_chars
[] = "#";
424 /* This array holds machine specific line separator characters. */
425 const char line_separator_chars
[] = ";";
427 /* Chars that can be used to separate mant from exp in floating point nums */
428 const char EXP_CHARS
[] = "eE";
430 /* Chars that mean this number is a floating point constant */
433 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
435 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
436 changed in read.c . Ideally it shouldn't have to know about it at all,
437 but nothing is ideal around here.
440 static char *insn_error
;
442 static int auto_align
= 1;
444 /* When outputting SVR4 PIC code, the assembler needs to know the
445 offset in the stack frame from which to restore the $gp register.
446 This is set by the .cprestore pseudo-op, and saved in this
448 static offsetT mips_cprestore_offset
= -1;
450 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
451 more optimizations, it can use a register value instead of a memory-saved
452 offset and even an other register than $gp as global pointer. */
453 static offsetT mips_cpreturn_offset
= -1;
454 static int mips_cpreturn_register
= -1;
455 static int mips_gp_register
= GP
;
456 static int mips_gprel_offset
= 0;
458 /* Whether mips_cprestore_offset has been set in the current function
459 (or whether it has already been warned about, if not). */
460 static int mips_cprestore_valid
= 0;
462 /* This is the register which holds the stack frame, as set by the
463 .frame pseudo-op. This is needed to implement .cprestore. */
464 static int mips_frame_reg
= SP
;
466 /* Whether mips_frame_reg has been set in the current function
467 (or whether it has already been warned about, if not). */
468 static int mips_frame_reg_valid
= 0;
470 /* To output NOP instructions correctly, we need to keep information
471 about the previous two instructions. */
473 /* Whether we are optimizing. The default value of 2 means to remove
474 unneeded NOPs and swap branch instructions when possible. A value
475 of 1 means to not swap branches. A value of 0 means to always
477 static int mips_optimize
= 2;
479 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
480 equivalent to seeing no -g option at all. */
481 static int mips_debug
= 0;
483 /* The previous instruction. */
484 static struct mips_cl_insn prev_insn
;
486 /* The instruction before prev_insn. */
487 static struct mips_cl_insn prev_prev_insn
;
489 /* If we don't want information for prev_insn or prev_prev_insn, we
490 point the insn_mo field at this dummy integer. */
491 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
493 /* Non-zero if prev_insn is valid. */
494 static int prev_insn_valid
;
496 /* The frag for the previous instruction. */
497 static struct frag
*prev_insn_frag
;
499 /* The offset into prev_insn_frag for the previous instruction. */
500 static long prev_insn_where
;
502 /* The reloc type for the previous instruction, if any. */
503 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
505 /* The reloc for the previous instruction, if any. */
506 static fixS
*prev_insn_fixp
[3];
508 /* Non-zero if the previous instruction was in a delay slot. */
509 static int prev_insn_is_delay_slot
;
511 /* Non-zero if the previous instruction was in a .set noreorder. */
512 static int prev_insn_unreordered
;
514 /* Non-zero if the previous instruction uses an extend opcode (if
516 static int prev_insn_extended
;
518 /* Non-zero if the previous previous instruction was in a .set
520 static int prev_prev_insn_unreordered
;
522 /* If this is set, it points to a frag holding nop instructions which
523 were inserted before the start of a noreorder section. If those
524 nops turn out to be unnecessary, the size of the frag can be
526 static fragS
*prev_nop_frag
;
528 /* The number of nop instructions we created in prev_nop_frag. */
529 static int prev_nop_frag_holds
;
531 /* The number of nop instructions that we know we need in
533 static int prev_nop_frag_required
;
535 /* The number of instructions we've seen since prev_nop_frag. */
536 static int prev_nop_frag_since
;
538 /* For ECOFF and ELF, relocations against symbols are done in two
539 parts, with a HI relocation and a LO relocation. Each relocation
540 has only 16 bits of space to store an addend. This means that in
541 order for the linker to handle carries correctly, it must be able
542 to locate both the HI and the LO relocation. This means that the
543 relocations must appear in order in the relocation table.
545 In order to implement this, we keep track of each unmatched HI
546 relocation. We then sort them so that they immediately precede the
547 corresponding LO relocation. */
552 struct mips_hi_fixup
*next
;
555 /* The section this fixup is in. */
559 /* The list of unmatched HI relocs. */
561 static struct mips_hi_fixup
*mips_hi_fixup_list
;
563 /* The frag containing the last explicit relocation operator.
564 Null if explicit relocations have not been used. */
566 static fragS
*prev_reloc_op_frag
;
568 /* Map normal MIPS register numbers to mips16 register numbers. */
570 #define X ILLEGAL_REG
571 static const int mips32_to_16_reg_map
[] =
573 X
, X
, 2, 3, 4, 5, 6, 7,
574 X
, X
, X
, X
, X
, X
, X
, X
,
575 0, 1, X
, X
, X
, X
, X
, X
,
576 X
, X
, X
, X
, X
, X
, X
, X
580 /* Map mips16 register numbers to normal MIPS register numbers. */
582 static const unsigned int mips16_to_32_reg_map
[] =
584 16, 17, 2, 3, 4, 5, 6, 7
587 static int mips_fix_4122_bugs
;
589 /* We don't relax branches by default, since this causes us to expand
590 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
591 fail to compute the offset before expanding the macro to the most
592 efficient expansion. */
594 static int mips_relax_branch
;
596 /* Since the MIPS does not have multiple forms of PC relative
597 instructions, we do not have to do relaxing as is done on other
598 platforms. However, we do have to handle GP relative addressing
599 correctly, which turns out to be a similar problem.
601 Every macro that refers to a symbol can occur in (at least) two
602 forms, one with GP relative addressing and one without. For
603 example, loading a global variable into a register generally uses
604 a macro instruction like this:
606 If i can be addressed off the GP register (this is true if it is in
607 the .sbss or .sdata section, or if it is known to be smaller than
608 the -G argument) this will generate the following instruction:
610 This instruction will use a GPREL reloc. If i can not be addressed
611 off the GP register, the following instruction sequence will be used:
614 In this case the first instruction will have a HI16 reloc, and the
615 second reloc will have a LO16 reloc. Both relocs will be against
618 The issue here is that we may not know whether i is GP addressable
619 until after we see the instruction that uses it. Therefore, we
620 want to be able to choose the final instruction sequence only at
621 the end of the assembly. This is similar to the way other
622 platforms choose the size of a PC relative instruction only at the
625 When generating position independent code we do not use GP
626 addressing in quite the same way, but the issue still arises as
627 external symbols and local symbols must be handled differently.
629 We handle these issues by actually generating both possible
630 instruction sequences. The longer one is put in a frag_var with
631 type rs_machine_dependent. We encode what to do with the frag in
632 the subtype field. We encode (1) the number of existing bytes to
633 replace, (2) the number of new bytes to use, (3) the offset from
634 the start of the existing bytes to the first reloc we must generate
635 (that is, the offset is applied from the start of the existing
636 bytes after they are replaced by the new bytes, if any), (4) the
637 offset from the start of the existing bytes to the second reloc,
638 (5) whether a third reloc is needed (the third reloc is always four
639 bytes after the second reloc), and (6) whether to warn if this
640 variant is used (this is sometimes needed if .set nomacro or .set
641 noat is in effect). All these numbers are reasonably small.
643 Generating two instruction sequences must be handled carefully to
644 ensure that delay slots are handled correctly. Fortunately, there
645 are a limited number of cases. When the second instruction
646 sequence is generated, append_insn is directed to maintain the
647 existing delay slot information, so it continues to apply to any
648 code after the second instruction sequence. This means that the
649 second instruction sequence must not impose any requirements not
650 required by the first instruction sequence.
652 These variant frags are then handled in functions called by the
653 machine independent code. md_estimate_size_before_relax returns
654 the final size of the frag. md_convert_frag sets up the final form
655 of the frag. tc_gen_reloc adjust the first reloc and adds a second
657 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
661 | (((reloc1) + 64) << 9) \
662 | (((reloc2) + 64) << 2) \
663 | ((reloc3) ? (1 << 1) : 0) \
665 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
666 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
667 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
668 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
669 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
670 #define RELAX_WARN(i) ((i) & 1)
672 /* Branch without likely bit. If label is out of range, we turn:
674 beq reg1, reg2, label
684 with the following opcode replacements:
691 bltzal <-> bgezal (with jal label instead of j label)
693 Even though keeping the delay slot instruction in the delay slot of
694 the branch would be more efficient, it would be very tricky to do
695 correctly, because we'd have to introduce a variable frag *after*
696 the delay slot instruction, and expand that instead. Let's do it
697 the easy way for now, even if the branch-not-taken case now costs
698 one additional instruction. Out-of-range branches are not supposed
699 to be common, anyway.
701 Branch likely. If label is out of range, we turn:
703 beql reg1, reg2, label
704 delay slot (annulled if branch not taken)
713 delay slot (executed only if branch taken)
716 It would be possible to generate a shorter sequence by losing the
717 likely bit, generating something like:
722 delay slot (executed only if branch taken)
734 bltzall -> bgezal (with jal label instead of j label)
735 bgezall -> bltzal (ditto)
738 but it's not clear that it would actually improve performance. */
739 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
742 | ((toofar) ? 1 : 0) \
744 | ((likely) ? 4 : 0) \
745 | ((uncond) ? 8 : 0)))
746 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
747 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
748 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
749 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
750 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
752 /* For mips16 code, we use an entirely different form of relaxation.
753 mips16 supports two versions of most instructions which take
754 immediate values: a small one which takes some small value, and a
755 larger one which takes a 16 bit value. Since branches also follow
756 this pattern, relaxing these values is required.
758 We can assemble both mips16 and normal MIPS code in a single
759 object. Therefore, we need to support this type of relaxation at
760 the same time that we support the relaxation described above. We
761 use the high bit of the subtype field to distinguish these cases.
763 The information we store for this type of relaxation is the
764 argument code found in the opcode file for this relocation, whether
765 the user explicitly requested a small or extended form, and whether
766 the relocation is in a jump or jal delay slot. That tells us the
767 size of the value, and how it should be stored. We also store
768 whether the fragment is considered to be extended or not. We also
769 store whether this is known to be a branch to a different section,
770 whether we have tried to relax this frag yet, and whether we have
771 ever extended a PC relative fragment because of a shift count. */
772 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
775 | ((small) ? 0x100 : 0) \
776 | ((ext) ? 0x200 : 0) \
777 | ((dslot) ? 0x400 : 0) \
778 | ((jal_dslot) ? 0x800 : 0))
779 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
780 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
781 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
782 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
783 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
784 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
785 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
786 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
787 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
788 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
789 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
790 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
792 /* Is the given value a sign-extended 32-bit value? */
793 #define IS_SEXT_32BIT_NUM(x) \
794 (((x) &~ (offsetT) 0x7fffffff) == 0 \
795 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
797 /* Is the given value a sign-extended 16-bit value? */
798 #define IS_SEXT_16BIT_NUM(x) \
799 (((x) &~ (offsetT) 0x7fff) == 0 \
800 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
803 /* Prototypes for static functions. */
806 #define internalError() \
807 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
809 #define internalError() as_fatal (_("MIPS internal Error"));
812 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
814 static inline bfd_boolean reloc_needs_lo_p
815 PARAMS ((bfd_reloc_code_real_type
));
816 static inline bfd_boolean fixup_has_matching_lo_p
818 static int insn_uses_reg
819 PARAMS ((struct mips_cl_insn
*ip
, unsigned int reg
,
820 enum mips_regclass
class));
821 static int reg_needs_delay
822 PARAMS ((unsigned int));
823 static void mips16_mark_labels
825 static void append_insn
826 PARAMS ((char *place
, struct mips_cl_insn
* ip
, expressionS
* p
,
827 bfd_reloc_code_real_type
*r
));
828 static void mips_no_prev_insn
830 static void mips_emit_delays
831 PARAMS ((bfd_boolean
));
833 static void macro_build
834 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *name
,
835 const char *fmt
, ...));
837 static void macro_build ();
839 static void mips16_macro_build
840 PARAMS ((char *, int *, expressionS
*, const char *, const char *, va_list));
841 static void macro_build_jalr
842 PARAMS ((int, expressionS
*));
843 static void macro_build_lui
844 PARAMS ((char *place
, int *counter
, expressionS
* ep
, int regnum
));
845 static void macro_build_ldst_constoffset
846 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *op
,
847 int valreg
, int breg
));
849 PARAMS ((int *counter
, int reg
, int unsignedp
));
850 static void check_absolute_expr
851 PARAMS ((struct mips_cl_insn
* ip
, expressionS
*));
852 static void load_register
853 PARAMS ((int *, int, expressionS
*, int));
854 static void load_address
855 PARAMS ((int *, int, expressionS
*, int *));
856 static void move_register
857 PARAMS ((int *, int, int));
859 PARAMS ((struct mips_cl_insn
* ip
));
860 static void mips16_macro
861 PARAMS ((struct mips_cl_insn
* ip
));
862 #ifdef LOSING_COMPILER
864 PARAMS ((struct mips_cl_insn
* ip
));
867 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
868 static void mips16_ip
869 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
870 static void mips16_immed
871 PARAMS ((char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
,
872 bfd_boolean
, unsigned long *, bfd_boolean
*, unsigned short *));
873 static bfd_boolean parse_relocation
874 PARAMS ((char **, bfd_reloc_code_real_type
*));
875 static size_t my_getSmallExpression
876 PARAMS ((expressionS
*, bfd_reloc_code_real_type
*, char *));
877 static void my_getExpression
878 PARAMS ((expressionS
*, char *));
880 static int support_64bit_objects
883 static void mips_set_option_string
884 PARAMS ((const char **, const char *));
885 static symbolS
*get_symbol
887 static void mips_align
888 PARAMS ((int to
, int fill
, symbolS
*label
));
891 static void s_change_sec
893 static void s_change_section
897 static void s_float_cons
899 static void s_mips_globl
903 static void s_mipsset
905 static void s_abicalls
909 static void s_cpsetup
911 static void s_cplocal
913 static void s_cprestore
915 static void s_cpreturn
917 static void s_gpvalue
921 static void s_gpdword
927 static void md_obj_begin
929 static void md_obj_end
931 static long get_number
933 static void s_mips_ent
935 static void s_mips_end
937 static void s_mips_frame
939 static void s_mips_mask
941 static void s_mips_stab
943 static void s_mips_weakext
945 static void s_mips_file
947 static void s_mips_loc
949 static bfd_boolean pic_need_relax
950 PARAMS ((symbolS
*, asection
*));
951 static int mips16_extended_frag
952 PARAMS ((fragS
*, asection
*, long));
953 static int relaxed_branch_length (fragS
*, asection
*, int);
954 static int validate_mips_insn
955 PARAMS ((const struct mips_opcode
*));
957 PARAMS ((FILE *, const char *, int *, int *));
959 static int mips_need_elf_addend_fixup
963 /* Table and functions used to map between CPU/ISA names, and
964 ISA levels, and CPU numbers. */
968 const char *name
; /* CPU or ISA name. */
969 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
970 int isa
; /* ISA level. */
971 int cpu
; /* CPU number (default CPU if ISA). */
974 static void mips_set_architecture
975 PARAMS ((const struct mips_cpu_info
*));
976 static void mips_set_tune
977 PARAMS ((const struct mips_cpu_info
*));
978 static bfd_boolean mips_strict_matching_cpu_name_p
979 PARAMS ((const char *, const char *));
980 static bfd_boolean mips_matching_cpu_name_p
981 PARAMS ((const char *, const char *));
982 static const struct mips_cpu_info
*mips_parse_cpu
983 PARAMS ((const char *, const char *));
984 static const struct mips_cpu_info
*mips_cpu_info_from_isa
989 The following pseudo-ops from the Kane and Heinrich MIPS book
990 should be defined here, but are currently unsupported: .alias,
991 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
993 The following pseudo-ops from the Kane and Heinrich MIPS book are
994 specific to the type of debugging information being generated, and
995 should be defined by the object format: .aent, .begin, .bend,
996 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
999 The following pseudo-ops from the Kane and Heinrich MIPS book are
1000 not MIPS CPU specific, but are also not specific to the object file
1001 format. This file is probably the best place to define them, but
1002 they are not currently supported: .asm0, .endr, .lab, .repeat,
1005 static const pseudo_typeS mips_pseudo_table
[] =
1007 /* MIPS specific pseudo-ops. */
1008 {"option", s_option
, 0},
1009 {"set", s_mipsset
, 0},
1010 {"rdata", s_change_sec
, 'r'},
1011 {"sdata", s_change_sec
, 's'},
1012 {"livereg", s_ignore
, 0},
1013 {"abicalls", s_abicalls
, 0},
1014 {"cpload", s_cpload
, 0},
1015 {"cpsetup", s_cpsetup
, 0},
1016 {"cplocal", s_cplocal
, 0},
1017 {"cprestore", s_cprestore
, 0},
1018 {"cpreturn", s_cpreturn
, 0},
1019 {"gpvalue", s_gpvalue
, 0},
1020 {"gpword", s_gpword
, 0},
1021 {"gpdword", s_gpdword
, 0},
1022 {"cpadd", s_cpadd
, 0},
1023 {"insn", s_insn
, 0},
1025 /* Relatively generic pseudo-ops that happen to be used on MIPS
1027 {"asciiz", stringer
, 1},
1028 {"bss", s_change_sec
, 'b'},
1030 {"half", s_cons
, 1},
1031 {"dword", s_cons
, 3},
1032 {"weakext", s_mips_weakext
, 0},
1034 /* These pseudo-ops are defined in read.c, but must be overridden
1035 here for one reason or another. */
1036 {"align", s_align
, 0},
1037 {"byte", s_cons
, 0},
1038 {"data", s_change_sec
, 'd'},
1039 {"double", s_float_cons
, 'd'},
1040 {"float", s_float_cons
, 'f'},
1041 {"globl", s_mips_globl
, 0},
1042 {"global", s_mips_globl
, 0},
1043 {"hword", s_cons
, 1},
1045 {"long", s_cons
, 2},
1046 {"octa", s_cons
, 4},
1047 {"quad", s_cons
, 3},
1048 {"section", s_change_section
, 0},
1049 {"short", s_cons
, 1},
1050 {"single", s_float_cons
, 'f'},
1051 {"stabn", s_mips_stab
, 'n'},
1052 {"text", s_change_sec
, 't'},
1053 {"word", s_cons
, 2},
1055 { "extern", ecoff_directive_extern
, 0},
1060 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1062 /* These pseudo-ops should be defined by the object file format.
1063 However, a.out doesn't support them, so we have versions here. */
1064 {"aent", s_mips_ent
, 1},
1065 {"bgnb", s_ignore
, 0},
1066 {"end", s_mips_end
, 0},
1067 {"endb", s_ignore
, 0},
1068 {"ent", s_mips_ent
, 0},
1069 {"file", s_mips_file
, 0},
1070 {"fmask", s_mips_mask
, 'F'},
1071 {"frame", s_mips_frame
, 0},
1072 {"loc", s_mips_loc
, 0},
1073 {"mask", s_mips_mask
, 'R'},
1074 {"verstamp", s_ignore
, 0},
1078 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
1083 pop_insert (mips_pseudo_table
);
1084 if (! ECOFF_DEBUGGING
)
1085 pop_insert (mips_nonecoff_pseudo_table
);
1088 /* Symbols labelling the current insn. */
1090 struct insn_label_list
1092 struct insn_label_list
*next
;
1096 static struct insn_label_list
*insn_labels
;
1097 static struct insn_label_list
*free_insn_labels
;
1099 static void mips_clear_insn_labels
PARAMS ((void));
1102 mips_clear_insn_labels ()
1104 register struct insn_label_list
**pl
;
1106 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1112 static char *expr_end
;
1114 /* Expressions which appear in instructions. These are set by
1117 static expressionS imm_expr
;
1118 static expressionS offset_expr
;
1120 /* Relocs associated with imm_expr and offset_expr. */
1122 static bfd_reloc_code_real_type imm_reloc
[3]
1123 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1124 static bfd_reloc_code_real_type offset_reloc
[3]
1125 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1127 /* These are set by mips16_ip if an explicit extension is used. */
1129 static bfd_boolean mips16_small
, mips16_ext
;
1132 /* The pdr segment for per procedure frame/regmask info. Not used for
1135 static segT pdr_seg
;
1138 /* The default target format to use. */
1141 mips_target_format ()
1143 switch (OUTPUT_FLAVOR
)
1145 case bfd_target_aout_flavour
:
1146 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1147 case bfd_target_ecoff_flavour
:
1148 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1149 case bfd_target_coff_flavour
:
1151 case bfd_target_elf_flavour
:
1153 /* This is traditional mips. */
1154 return (target_big_endian
1155 ? (HAVE_64BIT_OBJECTS
1156 ? "elf64-tradbigmips"
1158 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1159 : (HAVE_64BIT_OBJECTS
1160 ? "elf64-tradlittlemips"
1162 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1164 return (target_big_endian
1165 ? (HAVE_64BIT_OBJECTS
1168 ? "elf32-nbigmips" : "elf32-bigmips"))
1169 : (HAVE_64BIT_OBJECTS
1170 ? "elf64-littlemips"
1172 ? "elf32-nlittlemips" : "elf32-littlemips")));
1180 /* This function is called once, at assembler startup time. It should
1181 set up all the tables, etc. that the MD part of the assembler will need. */
1186 register const char *retval
= NULL
;
1190 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1191 as_warn (_("Could not set architecture and machine"));
1193 op_hash
= hash_new ();
1195 for (i
= 0; i
< NUMOPCODES
;)
1197 const char *name
= mips_opcodes
[i
].name
;
1199 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1202 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1203 mips_opcodes
[i
].name
, retval
);
1204 /* Probably a memory allocation problem? Give up now. */
1205 as_fatal (_("Broken assembler. No assembly attempted."));
1209 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1211 if (!validate_mips_insn (&mips_opcodes
[i
]))
1216 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1219 mips16_op_hash
= hash_new ();
1222 while (i
< bfd_mips16_num_opcodes
)
1224 const char *name
= mips16_opcodes
[i
].name
;
1226 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1228 as_fatal (_("internal: can't hash `%s': %s"),
1229 mips16_opcodes
[i
].name
, retval
);
1232 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1233 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1234 != mips16_opcodes
[i
].match
))
1236 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1237 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1242 while (i
< bfd_mips16_num_opcodes
1243 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1247 as_fatal (_("Broken assembler. No assembly attempted."));
1249 /* We add all the general register names to the symbol table. This
1250 helps us detect invalid uses of them. */
1251 for (i
= 0; i
< 32; i
++)
1255 sprintf (buf
, "$%d", i
);
1256 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1257 &zero_address_frag
));
1259 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1260 &zero_address_frag
));
1261 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1262 &zero_address_frag
));
1263 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1264 &zero_address_frag
));
1265 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1266 &zero_address_frag
));
1267 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1268 &zero_address_frag
));
1269 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1270 &zero_address_frag
));
1271 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1272 &zero_address_frag
));
1273 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1274 &zero_address_frag
));
1275 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1276 &zero_address_frag
));
1278 /* If we don't add these register names to the symbol table, they
1279 may end up being added as regular symbols by operand(), and then
1280 make it to the object file as undefined in case they're not
1281 regarded as local symbols. They're local in o32, since `$' is a
1282 local symbol prefix, but not in n32 or n64. */
1283 for (i
= 0; i
< 8; i
++)
1287 sprintf (buf
, "$fcc%i", i
);
1288 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1289 &zero_address_frag
));
1292 mips_no_prev_insn (FALSE
);
1295 mips_cprmask
[0] = 0;
1296 mips_cprmask
[1] = 0;
1297 mips_cprmask
[2] = 0;
1298 mips_cprmask
[3] = 0;
1300 /* set the default alignment for the text section (2**2) */
1301 record_alignment (text_section
, 2);
1303 if (USE_GLOBAL_POINTER_OPT
)
1304 bfd_set_gp_size (stdoutput
, g_switch_value
);
1306 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1308 /* On a native system, sections must be aligned to 16 byte
1309 boundaries. When configured for an embedded ELF target, we
1311 if (strcmp (TARGET_OS
, "elf") != 0)
1313 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1314 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1315 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1318 /* Create a .reginfo section for register masks and a .mdebug
1319 section for debugging information. */
1327 subseg
= now_subseg
;
1329 /* The ABI says this section should be loaded so that the
1330 running program can access it. However, we don't load it
1331 if we are configured for an embedded target */
1332 flags
= SEC_READONLY
| SEC_DATA
;
1333 if (strcmp (TARGET_OS
, "elf") != 0)
1334 flags
|= SEC_ALLOC
| SEC_LOAD
;
1336 if (mips_abi
!= N64_ABI
)
1338 sec
= subseg_new (".reginfo", (subsegT
) 0);
1340 bfd_set_section_flags (stdoutput
, sec
, flags
);
1341 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1344 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1349 /* The 64-bit ABI uses a .MIPS.options section rather than
1350 .reginfo section. */
1351 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1352 bfd_set_section_flags (stdoutput
, sec
, flags
);
1353 bfd_set_section_alignment (stdoutput
, sec
, 3);
1356 /* Set up the option header. */
1358 Elf_Internal_Options opthdr
;
1361 opthdr
.kind
= ODK_REGINFO
;
1362 opthdr
.size
= (sizeof (Elf_External_Options
)
1363 + sizeof (Elf64_External_RegInfo
));
1366 f
= frag_more (sizeof (Elf_External_Options
));
1367 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1368 (Elf_External_Options
*) f
);
1370 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1375 if (ECOFF_DEBUGGING
)
1377 sec
= subseg_new (".mdebug", (subsegT
) 0);
1378 (void) bfd_set_section_flags (stdoutput
, sec
,
1379 SEC_HAS_CONTENTS
| SEC_READONLY
);
1380 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1383 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1385 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1386 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1387 SEC_READONLY
| SEC_RELOC
1389 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1393 subseg_set (seg
, subseg
);
1397 if (! ECOFF_DEBUGGING
)
1404 if (! ECOFF_DEBUGGING
)
1412 struct mips_cl_insn insn
;
1413 bfd_reloc_code_real_type unused_reloc
[3]
1414 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1416 imm_expr
.X_op
= O_absent
;
1417 offset_expr
.X_op
= O_absent
;
1418 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1419 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1420 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1421 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1422 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1423 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1425 if (mips_opts
.mips16
)
1426 mips16_ip (str
, &insn
);
1429 mips_ip (str
, &insn
);
1430 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1431 str
, insn
.insn_opcode
));
1436 as_bad ("%s `%s'", insn_error
, str
);
1440 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1442 if (mips_opts
.mips16
)
1443 mips16_macro (&insn
);
1449 if (imm_expr
.X_op
!= O_absent
)
1450 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
);
1451 else if (offset_expr
.X_op
!= O_absent
)
1452 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
);
1454 append_insn (NULL
, &insn
, NULL
, unused_reloc
);
1458 /* Return true if the given relocation might need a matching %lo().
1459 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1460 applied to local symbols. */
1462 static inline bfd_boolean
1463 reloc_needs_lo_p (reloc
)
1464 bfd_reloc_code_real_type reloc
;
1466 return (reloc
== BFD_RELOC_HI16_S
1467 || reloc
== BFD_RELOC_MIPS_GOT16
);
1470 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1473 static inline bfd_boolean
1474 fixup_has_matching_lo_p (fixp
)
1477 return (fixp
->fx_next
!= NULL
1478 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1479 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1480 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1483 /* See whether instruction IP reads register REG. CLASS is the type
1487 insn_uses_reg (ip
, reg
, class)
1488 struct mips_cl_insn
*ip
;
1490 enum mips_regclass
class;
1492 if (class == MIPS16_REG
)
1494 assert (mips_opts
.mips16
);
1495 reg
= mips16_to_32_reg_map
[reg
];
1496 class = MIPS_GR_REG
;
1499 /* Don't report on general register ZERO, since it never changes. */
1500 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1503 if (class == MIPS_FP_REG
)
1505 assert (! mips_opts
.mips16
);
1506 /* If we are called with either $f0 or $f1, we must check $f0.
1507 This is not optimal, because it will introduce an unnecessary
1508 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1509 need to distinguish reading both $f0 and $f1 or just one of
1510 them. Note that we don't have to check the other way,
1511 because there is no instruction that sets both $f0 and $f1
1512 and requires a delay. */
1513 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1514 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1515 == (reg
&~ (unsigned) 1)))
1517 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1518 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1519 == (reg
&~ (unsigned) 1)))
1522 else if (! mips_opts
.mips16
)
1524 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1525 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1527 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1528 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1533 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1534 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1535 & MIPS16OP_MASK_RX
)]
1538 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1539 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1540 & MIPS16OP_MASK_RY
)]
1543 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1544 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1545 & MIPS16OP_MASK_MOVE32Z
)]
1548 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1550 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1552 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1554 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1555 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1556 & MIPS16OP_MASK_REGR32
) == reg
)
1563 /* This function returns true if modifying a register requires a
1567 reg_needs_delay (reg
)
1570 unsigned long prev_pinfo
;
1572 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1573 if (! mips_opts
.noreorder
1574 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1575 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1576 || (! gpr_interlocks
1577 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1579 /* A load from a coprocessor or from memory. All load
1580 delays delay the use of general register rt for one
1581 instruction on the r3000. The r6000 and r4000 use
1583 /* Itbl support may require additional care here. */
1584 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1585 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1592 /* Mark instruction labels in mips16 mode. This permits the linker to
1593 handle them specially, such as generating jalx instructions when
1594 needed. We also make them odd for the duration of the assembly, in
1595 order to generate the right sort of code. We will make them even
1596 in the adjust_symtab routine, while leaving them marked. This is
1597 convenient for the debugger and the disassembler. The linker knows
1598 to make them odd again. */
1601 mips16_mark_labels ()
1603 if (mips_opts
.mips16
)
1605 struct insn_label_list
*l
;
1608 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1611 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1612 S_SET_OTHER (l
->label
, STO_MIPS16
);
1614 val
= S_GET_VALUE (l
->label
);
1616 S_SET_VALUE (l
->label
, val
+ 1);
1621 /* Output an instruction. PLACE is where to put the instruction; if
1622 it is NULL, this uses frag_more to get room. IP is the instruction
1623 information. ADDRESS_EXPR is an operand of the instruction to be
1624 used with RELOC_TYPE. */
1627 append_insn (place
, ip
, address_expr
, reloc_type
)
1629 struct mips_cl_insn
*ip
;
1630 expressionS
*address_expr
;
1631 bfd_reloc_code_real_type
*reloc_type
;
1633 register unsigned long prev_pinfo
, pinfo
;
1637 bfd_boolean force_new_frag
= FALSE
;
1639 /* Mark instruction labels in mips16 mode. */
1640 mips16_mark_labels ();
1642 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1643 pinfo
= ip
->insn_mo
->pinfo
;
1645 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1649 /* If the previous insn required any delay slots, see if we need
1650 to insert a NOP or two. There are eight kinds of possible
1651 hazards, of which an instruction can have at most one type.
1652 (1) a load from memory delay
1653 (2) a load from a coprocessor delay
1654 (3) an unconditional branch delay
1655 (4) a conditional branch delay
1656 (5) a move to coprocessor register delay
1657 (6) a load coprocessor register from memory delay
1658 (7) a coprocessor condition code delay
1659 (8) a HI/LO special register delay
1661 There are a lot of optimizations we could do that we don't.
1662 In particular, we do not, in general, reorder instructions.
1663 If you use gcc with optimization, it will reorder
1664 instructions and generally do much more optimization then we
1665 do here; repeating all that work in the assembler would only
1666 benefit hand written assembly code, and does not seem worth
1669 /* This is how a NOP is emitted. */
1670 #define emit_nop() \
1672 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1673 : md_number_to_chars (frag_more (4), 0, 4))
1675 /* The previous insn might require a delay slot, depending upon
1676 the contents of the current insn. */
1677 if (! mips_opts
.mips16
1678 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1679 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1680 && ! cop_interlocks
)
1681 || (! gpr_interlocks
1682 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1684 /* A load from a coprocessor or from memory. All load
1685 delays delay the use of general register rt for one
1686 instruction on the r3000. The r6000 and r4000 use
1688 /* Itbl support may require additional care here. */
1689 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1690 if (mips_optimize
== 0
1691 || insn_uses_reg (ip
,
1692 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1697 else if (! mips_opts
.mips16
1698 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1699 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1700 && ! cop_interlocks
)
1701 || (mips_opts
.isa
== ISA_MIPS1
1702 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1704 /* A generic coprocessor delay. The previous instruction
1705 modified a coprocessor general or control register. If
1706 it modified a control register, we need to avoid any
1707 coprocessor instruction (this is probably not always
1708 required, but it sometimes is). If it modified a general
1709 register, we avoid using that register.
1711 On the r6000 and r4000 loading a coprocessor register
1712 from memory is interlocked, and does not require a delay.
1714 This case is not handled very well. There is no special
1715 knowledge of CP0 handling, and the coprocessors other
1716 than the floating point unit are not distinguished at
1718 /* Itbl support may require additional care here. FIXME!
1719 Need to modify this to include knowledge about
1720 user specified delays! */
1721 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1723 if (mips_optimize
== 0
1724 || insn_uses_reg (ip
,
1725 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1730 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1732 if (mips_optimize
== 0
1733 || insn_uses_reg (ip
,
1734 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1741 /* We don't know exactly what the previous instruction
1742 does. If the current instruction uses a coprocessor
1743 register, we must insert a NOP. If previous
1744 instruction may set the condition codes, and the
1745 current instruction uses them, we must insert two
1747 /* Itbl support may require additional care here. */
1748 if (mips_optimize
== 0
1749 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1750 && (pinfo
& INSN_READ_COND_CODE
)))
1752 else if (pinfo
& INSN_COP
)
1756 else if (! mips_opts
.mips16
1757 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1758 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1759 && ! cop_interlocks
)
1761 /* The previous instruction sets the coprocessor condition
1762 codes, but does not require a general coprocessor delay
1763 (this means it is a floating point comparison
1764 instruction). If this instruction uses the condition
1765 codes, we need to insert a single NOP. */
1766 /* Itbl support may require additional care here. */
1767 if (mips_optimize
== 0
1768 || (pinfo
& INSN_READ_COND_CODE
))
1772 /* If we're fixing up mfhi/mflo for the r7000 and the
1773 previous insn was an mfhi/mflo and the current insn
1774 reads the register that the mfhi/mflo wrote to, then
1777 else if (mips_7000_hilo_fix
1778 && MF_HILO_INSN (prev_pinfo
)
1779 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1786 /* If we're fixing up mfhi/mflo for the r7000 and the
1787 2nd previous insn was an mfhi/mflo and the current insn
1788 reads the register that the mfhi/mflo wrote to, then
1791 else if (mips_7000_hilo_fix
1792 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1793 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1801 else if (prev_pinfo
& INSN_READ_LO
)
1803 /* The previous instruction reads the LO register; if the
1804 current instruction writes to the LO register, we must
1805 insert two NOPS. Some newer processors have interlocks.
1806 Also the tx39's multiply instructions can be exectuted
1807 immediatly after a read from HI/LO (without the delay),
1808 though the tx39's divide insns still do require the
1810 if (! (hilo_interlocks
1811 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1812 && (mips_optimize
== 0
1813 || (pinfo
& INSN_WRITE_LO
)))
1815 /* Most mips16 branch insns don't have a delay slot.
1816 If a read from LO is immediately followed by a branch
1817 to a write to LO we have a read followed by a write
1818 less than 2 insns away. We assume the target of
1819 a branch might be a write to LO, and insert a nop
1820 between a read and an immediately following branch. */
1821 else if (mips_opts
.mips16
1822 && (mips_optimize
== 0
1823 || (pinfo
& MIPS16_INSN_BRANCH
)))
1826 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1828 /* The previous instruction reads the HI register; if the
1829 current instruction writes to the HI register, we must
1830 insert a NOP. Some newer processors have interlocks.
1831 Also the note tx39's multiply above. */
1832 if (! (hilo_interlocks
1833 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1834 && (mips_optimize
== 0
1835 || (pinfo
& INSN_WRITE_HI
)))
1837 /* Most mips16 branch insns don't have a delay slot.
1838 If a read from HI is immediately followed by a branch
1839 to a write to HI we have a read followed by a write
1840 less than 2 insns away. We assume the target of
1841 a branch might be a write to HI, and insert a nop
1842 between a read and an immediately following branch. */
1843 else if (mips_opts
.mips16
1844 && (mips_optimize
== 0
1845 || (pinfo
& MIPS16_INSN_BRANCH
)))
1849 /* If the previous instruction was in a noreorder section, then
1850 we don't want to insert the nop after all. */
1851 /* Itbl support may require additional care here. */
1852 if (prev_insn_unreordered
)
1855 /* There are two cases which require two intervening
1856 instructions: 1) setting the condition codes using a move to
1857 coprocessor instruction which requires a general coprocessor
1858 delay and then reading the condition codes 2) reading the HI
1859 or LO register and then writing to it (except on processors
1860 which have interlocks). If we are not already emitting a NOP
1861 instruction, we must check for these cases compared to the
1862 instruction previous to the previous instruction. */
1863 if ((! mips_opts
.mips16
1864 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1865 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1866 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1867 && (pinfo
& INSN_READ_COND_CODE
)
1868 && ! cop_interlocks
)
1869 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1870 && (pinfo
& INSN_WRITE_LO
)
1871 && ! (hilo_interlocks
1872 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1873 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1874 && (pinfo
& INSN_WRITE_HI
)
1875 && ! (hilo_interlocks
1876 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1881 if (prev_prev_insn_unreordered
)
1884 if (prev_prev_nop
&& nops
== 0)
1887 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
1889 /* We're out of bits in pinfo, so we must resort to string
1890 ops here. Shortcuts are selected based on opcodes being
1891 limited to the VR4122 instruction set. */
1893 const char *pn
= prev_insn
.insn_mo
->name
;
1894 const char *tn
= ip
->insn_mo
->name
;
1895 if (strncmp(pn
, "macc", 4) == 0
1896 || strncmp(pn
, "dmacc", 5) == 0)
1898 /* Errata 21 - [D]DIV[U] after [D]MACC */
1899 if (strstr (tn
, "div"))
1904 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1905 if (pn
[0] == 'd' /* dmacc */
1906 && (strncmp(tn
, "dmult", 5) == 0
1907 || strncmp(tn
, "dmacc", 5) == 0))
1912 /* Errata 24 - MT{LO,HI} after [D]MACC */
1913 if (strcmp (tn
, "mtlo") == 0
1914 || strcmp (tn
, "mthi") == 0)
1920 else if (strncmp(pn
, "dmult", 5) == 0
1921 && (strncmp(tn
, "dmult", 5) == 0
1922 || strncmp(tn
, "dmacc", 5) == 0))
1924 /* Here is the rest of errata 23. */
1927 if (nops
< min_nops
)
1931 /* If we are being given a nop instruction, don't bother with
1932 one of the nops we would otherwise output. This will only
1933 happen when a nop instruction is used with mips_optimize set
1936 && ! mips_opts
.noreorder
1937 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1940 /* Now emit the right number of NOP instructions. */
1941 if (nops
> 0 && ! mips_opts
.noreorder
)
1944 unsigned long old_frag_offset
;
1946 struct insn_label_list
*l
;
1948 old_frag
= frag_now
;
1949 old_frag_offset
= frag_now_fix ();
1951 for (i
= 0; i
< nops
; i
++)
1956 listing_prev_line ();
1957 /* We may be at the start of a variant frag. In case we
1958 are, make sure there is enough space for the frag
1959 after the frags created by listing_prev_line. The
1960 argument to frag_grow here must be at least as large
1961 as the argument to all other calls to frag_grow in
1962 this file. We don't have to worry about being in the
1963 middle of a variant frag, because the variants insert
1964 all needed nop instructions themselves. */
1968 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1972 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1973 symbol_set_frag (l
->label
, frag_now
);
1974 val
= (valueT
) frag_now_fix ();
1975 /* mips16 text labels are stored as odd. */
1976 if (mips_opts
.mips16
)
1978 S_SET_VALUE (l
->label
, val
);
1981 #ifndef NO_ECOFF_DEBUGGING
1982 if (ECOFF_DEBUGGING
)
1983 ecoff_fix_loc (old_frag
, old_frag_offset
);
1986 else if (prev_nop_frag
!= NULL
)
1988 /* We have a frag holding nops we may be able to remove. If
1989 we don't need any nops, we can decrease the size of
1990 prev_nop_frag by the size of one instruction. If we do
1991 need some nops, we count them in prev_nops_required. */
1992 if (prev_nop_frag_since
== 0)
1996 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1997 --prev_nop_frag_holds
;
2000 prev_nop_frag_required
+= nops
;
2004 if (prev_prev_nop
== 0)
2006 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2007 --prev_nop_frag_holds
;
2010 ++prev_nop_frag_required
;
2013 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2014 prev_nop_frag
= NULL
;
2016 ++prev_nop_frag_since
;
2018 /* Sanity check: by the time we reach the second instruction
2019 after prev_nop_frag, we should have used up all the nops
2020 one way or another. */
2021 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2027 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2028 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2029 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2030 && mips_relax_branch
2031 /* Don't try branch relaxation within .set nomacro, or within
2032 .set noat if we use $at for PIC computations. If it turns
2033 out that the branch was out-of-range, we'll get an error. */
2034 && !mips_opts
.warn_about_macros
2035 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2036 && !mips_opts
.mips16
)
2038 f
= frag_var (rs_machine_dependent
,
2039 relaxed_branch_length
2041 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2042 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2044 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2045 pinfo
& INSN_COND_BRANCH_LIKELY
,
2046 pinfo
& INSN_WRITE_GPR_31
,
2048 address_expr
->X_add_symbol
,
2049 address_expr
->X_add_number
,
2051 *reloc_type
= BFD_RELOC_UNUSED
;
2053 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2055 /* We need to set up a variant frag. */
2056 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2057 f
= frag_var (rs_machine_dependent
, 4, 0,
2058 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2059 mips16_small
, mips16_ext
,
2061 & INSN_UNCOND_BRANCH_DELAY
),
2062 (*prev_insn_reloc_type
2063 == BFD_RELOC_MIPS16_JMP
)),
2064 make_expr_symbol (address_expr
), 0, NULL
);
2066 else if (place
!= NULL
)
2068 else if (mips_opts
.mips16
2070 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2072 /* Make sure there is enough room to swap this instruction with
2073 a following jump instruction. */
2079 if (mips_opts
.mips16
2080 && mips_opts
.noreorder
2081 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2082 as_warn (_("extended instruction in delay slot"));
2087 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2088 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2090 if (address_expr
->X_op
== O_constant
)
2094 switch (*reloc_type
)
2097 ip
->insn_opcode
|= address_expr
->X_add_number
;
2100 case BFD_RELOC_MIPS_HIGHEST
:
2101 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2103 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2106 case BFD_RELOC_MIPS_HIGHER
:
2107 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2108 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2111 case BFD_RELOC_HI16_S
:
2112 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2116 case BFD_RELOC_HI16
:
2117 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2120 case BFD_RELOC_LO16
:
2121 case BFD_RELOC_MIPS_GOT_DISP
:
2122 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2125 case BFD_RELOC_MIPS_JMP
:
2126 if ((address_expr
->X_add_number
& 3) != 0)
2127 as_bad (_("jump to misaligned address (0x%lx)"),
2128 (unsigned long) address_expr
->X_add_number
);
2129 if (address_expr
->X_add_number
& ~0xfffffff)
2130 as_bad (_("jump address range overflow (0x%lx)"),
2131 (unsigned long) address_expr
->X_add_number
);
2132 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2135 case BFD_RELOC_MIPS16_JMP
:
2136 if ((address_expr
->X_add_number
& 3) != 0)
2137 as_bad (_("jump to misaligned address (0x%lx)"),
2138 (unsigned long) address_expr
->X_add_number
);
2139 if (address_expr
->X_add_number
& ~0xfffffff)
2140 as_bad (_("jump address range overflow (0x%lx)"),
2141 (unsigned long) address_expr
->X_add_number
);
2143 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2144 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2145 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2148 case BFD_RELOC_16_PCREL_S2
:
2158 /* Don't generate a reloc if we are writing into a variant frag. */
2161 reloc_howto_type
*howto
;
2164 /* In a compound relocation, it is the final (outermost)
2165 operator that determines the relocated field. */
2166 for (i
= 1; i
< 3; i
++)
2167 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2170 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2171 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2172 bfd_get_reloc_size(howto
),
2174 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2177 /* These relocations can have an addend that won't fit in
2178 4 octets for 64bit assembly. */
2180 && ! howto
->partial_inplace
2181 && (reloc_type
[0] == BFD_RELOC_16
2182 || reloc_type
[0] == BFD_RELOC_32
2183 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2184 || reloc_type
[0] == BFD_RELOC_HI16_S
2185 || reloc_type
[0] == BFD_RELOC_LO16
2186 || reloc_type
[0] == BFD_RELOC_GPREL16
2187 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2188 || reloc_type
[0] == BFD_RELOC_GPREL32
2189 || reloc_type
[0] == BFD_RELOC_64
2190 || reloc_type
[0] == BFD_RELOC_CTOR
2191 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2192 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2193 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2194 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2195 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2196 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
))
2197 fixp
[0]->fx_no_overflow
= 1;
2199 if (reloc_needs_lo_p (*reloc_type
))
2201 struct mips_hi_fixup
*hi_fixup
;
2203 /* Reuse the last entry if it already has a matching %lo. */
2204 hi_fixup
= mips_hi_fixup_list
;
2206 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2208 hi_fixup
= ((struct mips_hi_fixup
*)
2209 xmalloc (sizeof (struct mips_hi_fixup
)));
2210 hi_fixup
->next
= mips_hi_fixup_list
;
2211 mips_hi_fixup_list
= hi_fixup
;
2213 hi_fixup
->fixp
= fixp
[0];
2214 hi_fixup
->seg
= now_seg
;
2217 /* Add fixups for the second and third relocations, if given.
2218 Note that the ABI allows the second relocation to be
2219 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2220 moment we only use RSS_UNDEF, but we could add support
2221 for the others if it ever becomes necessary. */
2222 for (i
= 1; i
< 3; i
++)
2223 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2225 address_expr
->X_op
= O_absent
;
2226 address_expr
->X_add_symbol
= 0;
2227 address_expr
->X_add_number
= 0;
2229 fixp
[i
] = fix_new_exp (frag_now
, fixp
[0]->fx_where
,
2230 fixp
[0]->fx_size
, address_expr
,
2231 FALSE
, reloc_type
[i
]);
2237 if (! mips_opts
.mips16
)
2239 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2241 dwarf2_emit_insn (4);
2244 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2246 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2247 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2249 dwarf2_emit_insn (4);
2256 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2259 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2261 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2265 /* Update the register mask information. */
2266 if (! mips_opts
.mips16
)
2268 if (pinfo
& INSN_WRITE_GPR_D
)
2269 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2270 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2271 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2272 if (pinfo
& INSN_READ_GPR_S
)
2273 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2274 if (pinfo
& INSN_WRITE_GPR_31
)
2275 mips_gprmask
|= 1 << RA
;
2276 if (pinfo
& INSN_WRITE_FPR_D
)
2277 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2278 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2279 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2280 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2281 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2282 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2283 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2284 if (pinfo
& INSN_COP
)
2286 /* We don't keep enough information to sort these cases out.
2287 The itbl support does keep this information however, although
2288 we currently don't support itbl fprmats as part of the cop
2289 instruction. May want to add this support in the future. */
2291 /* Never set the bit for $0, which is always zero. */
2292 mips_gprmask
&= ~1 << 0;
2296 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2297 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2298 & MIPS16OP_MASK_RX
);
2299 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2300 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2301 & MIPS16OP_MASK_RY
);
2302 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2303 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2304 & MIPS16OP_MASK_RZ
);
2305 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2306 mips_gprmask
|= 1 << TREG
;
2307 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2308 mips_gprmask
|= 1 << SP
;
2309 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2310 mips_gprmask
|= 1 << RA
;
2311 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2312 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2313 if (pinfo
& MIPS16_INSN_READ_Z
)
2314 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2315 & MIPS16OP_MASK_MOVE32Z
);
2316 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2317 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2318 & MIPS16OP_MASK_REGR32
);
2321 if (place
== NULL
&& ! mips_opts
.noreorder
)
2323 /* Filling the branch delay slot is more complex. We try to
2324 switch the branch with the previous instruction, which we can
2325 do if the previous instruction does not set up a condition
2326 that the branch tests and if the branch is not itself the
2327 target of any branch. */
2328 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2329 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2331 if (mips_optimize
< 2
2332 /* If we have seen .set volatile or .set nomove, don't
2334 || mips_opts
.nomove
!= 0
2335 /* If we had to emit any NOP instructions, then we
2336 already know we can not swap. */
2338 /* If we don't even know the previous insn, we can not
2340 || ! prev_insn_valid
2341 /* If the previous insn is already in a branch delay
2342 slot, then we can not swap. */
2343 || prev_insn_is_delay_slot
2344 /* If the previous previous insn was in a .set
2345 noreorder, we can't swap. Actually, the MIPS
2346 assembler will swap in this situation. However, gcc
2347 configured -with-gnu-as will generate code like
2353 in which we can not swap the bne and INSN. If gcc is
2354 not configured -with-gnu-as, it does not output the
2355 .set pseudo-ops. We don't have to check
2356 prev_insn_unreordered, because prev_insn_valid will
2357 be 0 in that case. We don't want to use
2358 prev_prev_insn_valid, because we do want to be able
2359 to swap at the start of a function. */
2360 || prev_prev_insn_unreordered
2361 /* If the branch is itself the target of a branch, we
2362 can not swap. We cheat on this; all we check for is
2363 whether there is a label on this instruction. If
2364 there are any branches to anything other than a
2365 label, users must use .set noreorder. */
2366 || insn_labels
!= NULL
2367 /* If the previous instruction is in a variant frag, we
2368 can not do the swap. This does not apply to the
2369 mips16, which uses variant frags for different
2371 || (! mips_opts
.mips16
2372 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2373 /* If the branch reads the condition codes, we don't
2374 even try to swap, because in the sequence
2379 we can not swap, and I don't feel like handling that
2381 || (! mips_opts
.mips16
2382 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2383 && (pinfo
& INSN_READ_COND_CODE
))
2384 /* We can not swap with an instruction that requires a
2385 delay slot, becase the target of the branch might
2386 interfere with that instruction. */
2387 || (! mips_opts
.mips16
2388 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2390 /* Itbl support may require additional care here. */
2391 & (INSN_LOAD_COPROC_DELAY
2392 | INSN_COPROC_MOVE_DELAY
2393 | INSN_WRITE_COND_CODE
)))
2394 || (! (hilo_interlocks
2395 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2399 || (! mips_opts
.mips16
2401 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2402 || (! mips_opts
.mips16
2403 && mips_opts
.isa
== ISA_MIPS1
2404 /* Itbl support may require additional care here. */
2405 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2406 /* We can not swap with a branch instruction. */
2408 & (INSN_UNCOND_BRANCH_DELAY
2409 | INSN_COND_BRANCH_DELAY
2410 | INSN_COND_BRANCH_LIKELY
))
2411 /* We do not swap with a trap instruction, since it
2412 complicates trap handlers to have the trap
2413 instruction be in a delay slot. */
2414 || (prev_pinfo
& INSN_TRAP
)
2415 /* If the branch reads a register that the previous
2416 instruction sets, we can not swap. */
2417 || (! mips_opts
.mips16
2418 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2419 && insn_uses_reg (ip
,
2420 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2423 || (! mips_opts
.mips16
2424 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2425 && insn_uses_reg (ip
,
2426 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2429 || (mips_opts
.mips16
2430 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2431 && insn_uses_reg (ip
,
2432 ((prev_insn
.insn_opcode
2434 & MIPS16OP_MASK_RX
),
2436 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2437 && insn_uses_reg (ip
,
2438 ((prev_insn
.insn_opcode
2440 & MIPS16OP_MASK_RY
),
2442 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2443 && insn_uses_reg (ip
,
2444 ((prev_insn
.insn_opcode
2446 & MIPS16OP_MASK_RZ
),
2448 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2449 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2450 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2451 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2452 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2453 && insn_uses_reg (ip
,
2454 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2457 /* If the branch writes a register that the previous
2458 instruction sets, we can not swap (we know that
2459 branches write only to RD or to $31). */
2460 || (! mips_opts
.mips16
2461 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2462 && (((pinfo
& INSN_WRITE_GPR_D
)
2463 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2464 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2465 || ((pinfo
& INSN_WRITE_GPR_31
)
2466 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2469 || (! mips_opts
.mips16
2470 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2471 && (((pinfo
& INSN_WRITE_GPR_D
)
2472 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2473 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2474 || ((pinfo
& INSN_WRITE_GPR_31
)
2475 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2478 || (mips_opts
.mips16
2479 && (pinfo
& MIPS16_INSN_WRITE_31
)
2480 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2481 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2482 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2484 /* If the branch writes a register that the previous
2485 instruction reads, we can not swap (we know that
2486 branches only write to RD or to $31). */
2487 || (! mips_opts
.mips16
2488 && (pinfo
& INSN_WRITE_GPR_D
)
2489 && insn_uses_reg (&prev_insn
,
2490 ((ip
->insn_opcode
>> OP_SH_RD
)
2493 || (! mips_opts
.mips16
2494 && (pinfo
& INSN_WRITE_GPR_31
)
2495 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2496 || (mips_opts
.mips16
2497 && (pinfo
& MIPS16_INSN_WRITE_31
)
2498 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2499 /* If we are generating embedded PIC code, the branch
2500 might be expanded into a sequence which uses $at, so
2501 we can't swap with an instruction which reads it. */
2502 || (mips_pic
== EMBEDDED_PIC
2503 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2504 /* If the previous previous instruction has a load
2505 delay, and sets a register that the branch reads, we
2507 || (! mips_opts
.mips16
2508 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2509 /* Itbl support may require additional care here. */
2510 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2511 || (! gpr_interlocks
2512 && (prev_prev_insn
.insn_mo
->pinfo
2513 & INSN_LOAD_MEMORY_DELAY
)))
2514 && insn_uses_reg (ip
,
2515 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2518 /* If one instruction sets a condition code and the
2519 other one uses a condition code, we can not swap. */
2520 || ((pinfo
& INSN_READ_COND_CODE
)
2521 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2522 || ((pinfo
& INSN_WRITE_COND_CODE
)
2523 && (prev_pinfo
& INSN_READ_COND_CODE
))
2524 /* If the previous instruction uses the PC, we can not
2526 || (mips_opts
.mips16
2527 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2528 /* If the previous instruction was extended, we can not
2530 || (mips_opts
.mips16
&& prev_insn_extended
)
2531 /* If the previous instruction had a fixup in mips16
2532 mode, we can not swap. This normally means that the
2533 previous instruction was a 4 byte branch anyhow. */
2534 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2535 /* If the previous instruction is a sync, sync.l, or
2536 sync.p, we can not swap. */
2537 || (prev_pinfo
& INSN_SYNC
))
2539 /* We could do even better for unconditional branches to
2540 portions of this object file; we could pick up the
2541 instruction at the destination, put it in the delay
2542 slot, and bump the destination address. */
2544 /* Update the previous insn information. */
2545 prev_prev_insn
= *ip
;
2546 prev_insn
.insn_mo
= &dummy_opcode
;
2550 /* It looks like we can actually do the swap. */
2551 if (! mips_opts
.mips16
)
2556 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2557 memcpy (temp
, prev_f
, 4);
2558 memcpy (prev_f
, f
, 4);
2559 memcpy (f
, temp
, 4);
2560 if (prev_insn_fixp
[0])
2562 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2563 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2565 if (prev_insn_fixp
[1])
2567 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2568 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2570 if (prev_insn_fixp
[2])
2572 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2573 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2575 if (prev_insn_fixp
[0] && HAVE_NEWABI
2576 && prev_insn_frag
!= frag_now
2577 && (prev_insn_fixp
[0]->fx_r_type
2578 == BFD_RELOC_MIPS_GOT_DISP
2579 || (prev_insn_fixp
[0]->fx_r_type
2580 == BFD_RELOC_MIPS_CALL16
)))
2582 /* To avoid confusion in tc_gen_reloc, we must
2583 ensure that this does not become a variant
2585 force_new_frag
= TRUE
;
2589 fixp
[0]->fx_frag
= prev_insn_frag
;
2590 fixp
[0]->fx_where
= prev_insn_where
;
2594 fixp
[1]->fx_frag
= prev_insn_frag
;
2595 fixp
[1]->fx_where
= prev_insn_where
;
2599 fixp
[2]->fx_frag
= prev_insn_frag
;
2600 fixp
[2]->fx_where
= prev_insn_where
;
2608 assert (prev_insn_fixp
[0] == NULL
);
2609 assert (prev_insn_fixp
[1] == NULL
);
2610 assert (prev_insn_fixp
[2] == NULL
);
2611 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2612 memcpy (temp
, prev_f
, 2);
2613 memcpy (prev_f
, f
, 2);
2614 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2616 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2617 memcpy (f
, temp
, 2);
2621 memcpy (f
, f
+ 2, 2);
2622 memcpy (f
+ 2, temp
, 2);
2626 fixp
[0]->fx_frag
= prev_insn_frag
;
2627 fixp
[0]->fx_where
= prev_insn_where
;
2631 fixp
[1]->fx_frag
= prev_insn_frag
;
2632 fixp
[1]->fx_where
= prev_insn_where
;
2636 fixp
[2]->fx_frag
= prev_insn_frag
;
2637 fixp
[2]->fx_where
= prev_insn_where
;
2641 /* Update the previous insn information; leave prev_insn
2643 prev_prev_insn
= *ip
;
2645 prev_insn_is_delay_slot
= 1;
2647 /* If that was an unconditional branch, forget the previous
2648 insn information. */
2649 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2651 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2652 prev_insn
.insn_mo
= &dummy_opcode
;
2655 prev_insn_fixp
[0] = NULL
;
2656 prev_insn_fixp
[1] = NULL
;
2657 prev_insn_fixp
[2] = NULL
;
2658 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2659 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2660 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2661 prev_insn_extended
= 0;
2663 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2665 /* We don't yet optimize a branch likely. What we should do
2666 is look at the target, copy the instruction found there
2667 into the delay slot, and increment the branch to jump to
2668 the next instruction. */
2670 /* Update the previous insn information. */
2671 prev_prev_insn
= *ip
;
2672 prev_insn
.insn_mo
= &dummy_opcode
;
2673 prev_insn_fixp
[0] = NULL
;
2674 prev_insn_fixp
[1] = NULL
;
2675 prev_insn_fixp
[2] = NULL
;
2676 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2677 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2678 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2679 prev_insn_extended
= 0;
2683 /* Update the previous insn information. */
2685 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2687 prev_prev_insn
= prev_insn
;
2690 /* Any time we see a branch, we always fill the delay slot
2691 immediately; since this insn is not a branch, we know it
2692 is not in a delay slot. */
2693 prev_insn_is_delay_slot
= 0;
2695 prev_insn_fixp
[0] = fixp
[0];
2696 prev_insn_fixp
[1] = fixp
[1];
2697 prev_insn_fixp
[2] = fixp
[2];
2698 prev_insn_reloc_type
[0] = reloc_type
[0];
2699 prev_insn_reloc_type
[1] = reloc_type
[1];
2700 prev_insn_reloc_type
[2] = reloc_type
[2];
2701 if (mips_opts
.mips16
)
2702 prev_insn_extended
= (ip
->use_extend
2703 || *reloc_type
> BFD_RELOC_UNUSED
);
2706 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2707 prev_insn_unreordered
= 0;
2708 prev_insn_frag
= frag_now
;
2709 prev_insn_where
= f
- frag_now
->fr_literal
;
2710 prev_insn_valid
= 1;
2712 else if (place
== NULL
)
2714 /* We need to record a bit of information even when we are not
2715 reordering, in order to determine the base address for mips16
2716 PC relative relocs. */
2717 prev_prev_insn
= prev_insn
;
2719 prev_insn_reloc_type
[0] = reloc_type
[0];
2720 prev_insn_reloc_type
[1] = reloc_type
[1];
2721 prev_insn_reloc_type
[2] = reloc_type
[2];
2722 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2723 prev_insn_unreordered
= 1;
2726 /* We just output an insn, so the next one doesn't have a label. */
2727 mips_clear_insn_labels ();
2729 /* We must ensure that the frag to which an instruction that was
2730 moved from a non-variant frag doesn't become a variant frag,
2731 otherwise tc_gen_reloc may get confused. */
2734 frag_wane (frag_now
);
2739 /* This function forgets that there was any previous instruction or
2740 label. If PRESERVE is non-zero, it remembers enough information to
2741 know whether nops are needed before a noreorder section. */
2744 mips_no_prev_insn (preserve
)
2749 prev_insn
.insn_mo
= &dummy_opcode
;
2750 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2751 prev_nop_frag
= NULL
;
2752 prev_nop_frag_holds
= 0;
2753 prev_nop_frag_required
= 0;
2754 prev_nop_frag_since
= 0;
2756 prev_insn_valid
= 0;
2757 prev_insn_is_delay_slot
= 0;
2758 prev_insn_unreordered
= 0;
2759 prev_insn_extended
= 0;
2760 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2761 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2762 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2763 prev_prev_insn_unreordered
= 0;
2764 mips_clear_insn_labels ();
2767 /* This function must be called whenever we turn on noreorder or emit
2768 something other than instructions. It inserts any NOPS which might
2769 be needed by the previous instruction, and clears the information
2770 kept for the previous instructions. The INSNS parameter is true if
2771 instructions are to follow. */
2774 mips_emit_delays (insns
)
2777 if (! mips_opts
.noreorder
)
2782 if ((! mips_opts
.mips16
2783 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2784 && (! cop_interlocks
2785 && (prev_insn
.insn_mo
->pinfo
2786 & (INSN_LOAD_COPROC_DELAY
2787 | INSN_COPROC_MOVE_DELAY
2788 | INSN_WRITE_COND_CODE
))))
2789 || (! hilo_interlocks
2790 && (prev_insn
.insn_mo
->pinfo
2793 || (! mips_opts
.mips16
2795 && (prev_insn
.insn_mo
->pinfo
2796 & INSN_LOAD_MEMORY_DELAY
))
2797 || (! mips_opts
.mips16
2798 && mips_opts
.isa
== ISA_MIPS1
2799 && (prev_insn
.insn_mo
->pinfo
2800 & INSN_COPROC_MEMORY_DELAY
)))
2802 /* Itbl support may require additional care here. */
2804 if ((! mips_opts
.mips16
2805 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2806 && (! cop_interlocks
2807 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2808 || (! hilo_interlocks
2809 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2810 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2813 if (prev_insn_unreordered
)
2816 else if ((! mips_opts
.mips16
2817 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2818 && (! cop_interlocks
2819 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2820 || (! hilo_interlocks
2821 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2822 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2824 /* Itbl support may require additional care here. */
2825 if (! prev_prev_insn_unreordered
)
2829 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
2832 const char *pn
= prev_insn
.insn_mo
->name
;
2833 if (strncmp(pn
, "macc", 4) == 0
2834 || strncmp(pn
, "dmacc", 5) == 0
2835 || strncmp(pn
, "dmult", 5) == 0)
2839 if (nops
< min_nops
)
2845 struct insn_label_list
*l
;
2849 /* Record the frag which holds the nop instructions, so
2850 that we can remove them if we don't need them. */
2851 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2852 prev_nop_frag
= frag_now
;
2853 prev_nop_frag_holds
= nops
;
2854 prev_nop_frag_required
= 0;
2855 prev_nop_frag_since
= 0;
2858 for (; nops
> 0; --nops
)
2863 /* Move on to a new frag, so that it is safe to simply
2864 decrease the size of prev_nop_frag. */
2865 frag_wane (frag_now
);
2869 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2873 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2874 symbol_set_frag (l
->label
, frag_now
);
2875 val
= (valueT
) frag_now_fix ();
2876 /* mips16 text labels are stored as odd. */
2877 if (mips_opts
.mips16
)
2879 S_SET_VALUE (l
->label
, val
);
2884 /* Mark instruction labels in mips16 mode. */
2886 mips16_mark_labels ();
2888 mips_no_prev_insn (insns
);
2891 /* Build an instruction created by a macro expansion. This is passed
2892 a pointer to the count of instructions created so far, an
2893 expression, the name of the instruction to build, an operand format
2894 string, and corresponding arguments. */
2898 macro_build (char *place
,
2906 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2915 struct mips_cl_insn insn
;
2916 bfd_reloc_code_real_type r
[3];
2920 va_start (args
, fmt
);
2926 * If the macro is about to expand into a second instruction,
2927 * print a warning if needed. We need to pass ip as a parameter
2928 * to generate a better warning message here...
2930 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2931 as_warn (_("Macro instruction expanded into multiple instructions"));
2934 * If the macro is about to expand into a second instruction,
2935 * and it is in a delay slot, print a warning.
2939 && mips_opts
.noreorder
2940 && (prev_prev_insn
.insn_mo
->pinfo
2941 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2942 | INSN_COND_BRANCH_LIKELY
)) != 0)
2943 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2946 ++*counter
; /* bump instruction counter */
2948 if (mips_opts
.mips16
)
2950 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2955 r
[0] = BFD_RELOC_UNUSED
;
2956 r
[1] = BFD_RELOC_UNUSED
;
2957 r
[2] = BFD_RELOC_UNUSED
;
2958 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2959 assert (insn
.insn_mo
);
2960 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2962 /* Search until we get a match for NAME. */
2965 /* It is assumed here that macros will never generate
2966 MDMX or MIPS-3D instructions. */
2967 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2968 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2969 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2971 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2973 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2977 assert (insn
.insn_mo
->name
);
2978 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2981 insn
.insn_opcode
= insn
.insn_mo
->match
;
2997 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3001 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3006 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3012 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3017 int tmp
= va_arg (args
, int);
3019 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3020 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3026 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3033 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3037 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3041 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3045 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3049 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3056 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3062 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3063 assert (*r
== BFD_RELOC_GPREL16
3064 || *r
== BFD_RELOC_MIPS_LITERAL
3065 || *r
== BFD_RELOC_MIPS_HIGHER
3066 || *r
== BFD_RELOC_HI16_S
3067 || *r
== BFD_RELOC_LO16
3068 || *r
== BFD_RELOC_MIPS_GOT16
3069 || *r
== BFD_RELOC_MIPS_CALL16
3070 || *r
== BFD_RELOC_MIPS_GOT_DISP
3071 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3072 || *r
== BFD_RELOC_MIPS_GOT_OFST
3073 || *r
== BFD_RELOC_MIPS_GOT_LO16
3074 || *r
== BFD_RELOC_MIPS_CALL_LO16
3075 || (ep
->X_op
== O_subtract
3076 && *r
== BFD_RELOC_PCREL_LO16
));
3080 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3082 && (ep
->X_op
== O_constant
3083 || (ep
->X_op
== O_symbol
3084 && (*r
== BFD_RELOC_MIPS_HIGHEST
3085 || *r
== BFD_RELOC_HI16_S
3086 || *r
== BFD_RELOC_HI16
3087 || *r
== BFD_RELOC_GPREL16
3088 || *r
== BFD_RELOC_MIPS_GOT_HI16
3089 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3090 || (ep
->X_op
== O_subtract
3091 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3095 assert (ep
!= NULL
);
3097 * This allows macro() to pass an immediate expression for
3098 * creating short branches without creating a symbol.
3099 * Note that the expression still might come from the assembly
3100 * input, in which case the value is not checked for range nor
3101 * is a relocation entry generated (yuck).
3103 if (ep
->X_op
== O_constant
)
3105 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3109 *r
= BFD_RELOC_16_PCREL_S2
;
3113 assert (ep
!= NULL
);
3114 *r
= BFD_RELOC_MIPS_JMP
;
3118 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3127 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3129 append_insn (place
, &insn
, ep
, r
);
3133 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3135 int *counter ATTRIBUTE_UNUSED
;
3141 struct mips_cl_insn insn
;
3142 bfd_reloc_code_real_type r
[3]
3143 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3145 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3146 assert (insn
.insn_mo
);
3147 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3149 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3150 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3153 assert (insn
.insn_mo
->name
);
3154 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3157 insn
.insn_opcode
= insn
.insn_mo
->match
;
3158 insn
.use_extend
= FALSE
;
3177 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3182 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3186 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3190 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3200 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3207 regno
= va_arg (args
, int);
3208 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3209 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3230 assert (ep
!= NULL
);
3232 if (ep
->X_op
!= O_constant
)
3233 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3236 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3237 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3240 *r
= BFD_RELOC_UNUSED
;
3246 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3253 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3255 append_insn (place
, &insn
, ep
, r
);
3259 * Generate a "jalr" instruction with a relocation hint to the called
3260 * function. This occurs in NewABI PIC code.
3263 macro_build_jalr (icnt
, ep
)
3274 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3277 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3278 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3282 * Generate a "lui" instruction.
3285 macro_build_lui (place
, counter
, ep
, regnum
)
3291 expressionS high_expr
;
3292 struct mips_cl_insn insn
;
3293 bfd_reloc_code_real_type r
[3]
3294 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3295 const char *name
= "lui";
3296 const char *fmt
= "t,u";
3298 assert (! mips_opts
.mips16
);
3304 high_expr
.X_op
= O_constant
;
3305 high_expr
.X_add_number
= ep
->X_add_number
;
3308 if (high_expr
.X_op
== O_constant
)
3310 /* we can compute the instruction now without a relocation entry */
3311 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3313 *r
= BFD_RELOC_UNUSED
;
3317 assert (ep
->X_op
== O_symbol
);
3318 /* _gp_disp is a special case, used from s_cpload. */
3319 assert (mips_pic
== NO_PIC
3321 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3322 *r
= BFD_RELOC_HI16_S
;
3326 * If the macro is about to expand into a second instruction,
3327 * print a warning if needed. We need to pass ip as a parameter
3328 * to generate a better warning message here...
3330 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3331 as_warn (_("Macro instruction expanded into multiple instructions"));
3334 ++*counter
; /* bump instruction counter */
3336 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3337 assert (insn
.insn_mo
);
3338 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3339 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3341 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3342 if (*r
== BFD_RELOC_UNUSED
)
3344 insn
.insn_opcode
|= high_expr
.X_add_number
;
3345 append_insn (place
, &insn
, NULL
, r
);
3348 append_insn (place
, &insn
, &high_expr
, r
);
3351 /* Generate a sequence of instructions to do a load or store from a constant
3352 offset off of a base register (breg) into/from a target register (treg),
3353 using AT if necessary. */
3355 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3362 assert (ep
->X_op
== O_constant
);
3364 /* Right now, this routine can only handle signed 32-bit contants. */
3365 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3366 as_warn (_("operand overflow"));
3368 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3370 /* Signed 16-bit offset will fit in the op. Easy! */
3371 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3372 (int) BFD_RELOC_LO16
, breg
);
3376 /* 32-bit offset, need multiple instructions and AT, like:
3377 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3378 addu $tempreg,$tempreg,$breg
3379 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3380 to handle the complete offset. */
3381 macro_build_lui (place
, counter
, ep
, AT
);
3384 macro_build (place
, counter
, (expressionS
*) NULL
,
3385 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
3386 ? "add" : "addu" : "daddu",
3387 "d,v,t", AT
, AT
, breg
);
3390 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3391 (int) BFD_RELOC_LO16
, AT
);
3394 as_warn (_("Macro used $at after \".set noat\""));
3399 * Generates code to set the $at register to true (one)
3400 * if reg is less than the immediate expression.
3403 set_at (counter
, reg
, unsignedp
)
3408 if (imm_expr
.X_op
== O_constant
3409 && imm_expr
.X_add_number
>= -0x8000
3410 && imm_expr
.X_add_number
< 0x8000)
3411 macro_build ((char *) NULL
, counter
, &imm_expr
,
3412 unsignedp
? "sltiu" : "slti",
3413 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3416 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3417 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3418 unsignedp
? "sltu" : "slt",
3419 "d,v,t", AT
, reg
, AT
);
3423 /* Warn if an expression is not a constant. */
3426 check_absolute_expr (ip
, ex
)
3427 struct mips_cl_insn
*ip
;
3430 if (ex
->X_op
== O_big
)
3431 as_bad (_("unsupported large constant"));
3432 else if (ex
->X_op
!= O_constant
)
3433 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3436 /* Count the leading zeroes by performing a binary chop. This is a
3437 bulky bit of source, but performance is a LOT better for the
3438 majority of values than a simple loop to count the bits:
3439 for (lcnt = 0; (lcnt < 32); lcnt++)
3440 if ((v) & (1 << (31 - lcnt)))
3442 However it is not code size friendly, and the gain will drop a bit
3443 on certain cached systems.
3445 #define COUNT_TOP_ZEROES(v) \
3446 (((v) & ~0xffff) == 0 \
3447 ? ((v) & ~0xff) == 0 \
3448 ? ((v) & ~0xf) == 0 \
3449 ? ((v) & ~0x3) == 0 \
3450 ? ((v) & ~0x1) == 0 \
3455 : ((v) & ~0x7) == 0 \
3458 : ((v) & ~0x3f) == 0 \
3459 ? ((v) & ~0x1f) == 0 \
3462 : ((v) & ~0x7f) == 0 \
3465 : ((v) & ~0xfff) == 0 \
3466 ? ((v) & ~0x3ff) == 0 \
3467 ? ((v) & ~0x1ff) == 0 \
3470 : ((v) & ~0x7ff) == 0 \
3473 : ((v) & ~0x3fff) == 0 \
3474 ? ((v) & ~0x1fff) == 0 \
3477 : ((v) & ~0x7fff) == 0 \
3480 : ((v) & ~0xffffff) == 0 \
3481 ? ((v) & ~0xfffff) == 0 \
3482 ? ((v) & ~0x3ffff) == 0 \
3483 ? ((v) & ~0x1ffff) == 0 \
3486 : ((v) & ~0x7ffff) == 0 \
3489 : ((v) & ~0x3fffff) == 0 \
3490 ? ((v) & ~0x1fffff) == 0 \
3493 : ((v) & ~0x7fffff) == 0 \
3496 : ((v) & ~0xfffffff) == 0 \
3497 ? ((v) & ~0x3ffffff) == 0 \
3498 ? ((v) & ~0x1ffffff) == 0 \
3501 : ((v) & ~0x7ffffff) == 0 \
3504 : ((v) & ~0x3fffffff) == 0 \
3505 ? ((v) & ~0x1fffffff) == 0 \
3508 : ((v) & ~0x7fffffff) == 0 \
3513 * This routine generates the least number of instructions neccessary to load
3514 * an absolute expression value into a register.
3517 load_register (counter
, reg
, ep
, dbl
)
3524 expressionS hi32
, lo32
;
3526 if (ep
->X_op
!= O_big
)
3528 assert (ep
->X_op
== O_constant
);
3529 if (ep
->X_add_number
< 0x8000
3530 && (ep
->X_add_number
>= 0
3531 || (ep
->X_add_number
>= -0x8000
3534 || sizeof (ep
->X_add_number
) > 4))))
3536 /* We can handle 16 bit signed values with an addiu to
3537 $zero. No need to ever use daddiu here, since $zero and
3538 the result are always correct in 32 bit mode. */
3539 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3540 (int) BFD_RELOC_LO16
);
3543 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3545 /* We can handle 16 bit unsigned values with an ori to
3547 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3548 (int) BFD_RELOC_LO16
);
3551 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3554 || sizeof (ep
->X_add_number
) > 4
3555 || (ep
->X_add_number
& 0x80000000) == 0))
3556 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3557 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3560 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3561 == ~ (offsetT
) 0xffffffff)))
3563 /* 32 bit values require an lui. */
3564 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3565 (int) BFD_RELOC_HI16
);
3566 if ((ep
->X_add_number
& 0xffff) != 0)
3567 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3568 (int) BFD_RELOC_LO16
);
3573 /* The value is larger than 32 bits. */
3575 if (HAVE_32BIT_GPRS
)
3577 as_bad (_("Number (0x%lx) larger than 32 bits"),
3578 (unsigned long) ep
->X_add_number
);
3579 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3580 (int) BFD_RELOC_LO16
);
3584 if (ep
->X_op
!= O_big
)
3587 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3588 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3589 hi32
.X_add_number
&= 0xffffffff;
3591 lo32
.X_add_number
&= 0xffffffff;
3595 assert (ep
->X_add_number
> 2);
3596 if (ep
->X_add_number
== 3)
3597 generic_bignum
[3] = 0;
3598 else if (ep
->X_add_number
> 4)
3599 as_bad (_("Number larger than 64 bits"));
3600 lo32
.X_op
= O_constant
;
3601 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3602 hi32
.X_op
= O_constant
;
3603 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3606 if (hi32
.X_add_number
== 0)
3611 unsigned long hi
, lo
;
3613 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3615 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3617 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3618 reg
, 0, (int) BFD_RELOC_LO16
);
3621 if (lo32
.X_add_number
& 0x80000000)
3623 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3624 (int) BFD_RELOC_HI16
);
3625 if (lo32
.X_add_number
& 0xffff)
3626 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3627 reg
, reg
, (int) BFD_RELOC_LO16
);
3632 /* Check for 16bit shifted constant. We know that hi32 is
3633 non-zero, so start the mask on the first bit of the hi32
3638 unsigned long himask
, lomask
;
3642 himask
= 0xffff >> (32 - shift
);
3643 lomask
= (0xffff << shift
) & 0xffffffff;
3647 himask
= 0xffff << (shift
- 32);
3650 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3651 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3655 tmp
.X_op
= O_constant
;
3657 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3658 | (lo32
.X_add_number
>> shift
));
3660 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3661 macro_build ((char *) NULL
, counter
, &tmp
,
3662 "ori", "t,r,i", reg
, 0,
3663 (int) BFD_RELOC_LO16
);
3664 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3665 (shift
>= 32) ? "dsll32" : "dsll",
3667 (shift
>= 32) ? shift
- 32 : shift
);
3672 while (shift
<= (64 - 16));
3674 /* Find the bit number of the lowest one bit, and store the
3675 shifted value in hi/lo. */
3676 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3677 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3681 while ((lo
& 1) == 0)
3686 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3692 while ((hi
& 1) == 0)
3701 /* Optimize if the shifted value is a (power of 2) - 1. */
3702 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3703 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3705 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3710 /* This instruction will set the register to be all
3712 tmp
.X_op
= O_constant
;
3713 tmp
.X_add_number
= (offsetT
) -1;
3714 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3715 reg
, 0, (int) BFD_RELOC_LO16
);
3719 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3720 (bit
>= 32) ? "dsll32" : "dsll",
3722 (bit
>= 32) ? bit
- 32 : bit
);
3724 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3725 (shift
>= 32) ? "dsrl32" : "dsrl",
3727 (shift
>= 32) ? shift
- 32 : shift
);
3732 /* Sign extend hi32 before calling load_register, because we can
3733 generally get better code when we load a sign extended value. */
3734 if ((hi32
.X_add_number
& 0x80000000) != 0)
3735 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3736 load_register (counter
, reg
, &hi32
, 0);
3739 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3743 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3744 "dsll32", "d,w,<", reg
, freg
, 0);
3752 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3754 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3755 (int) BFD_RELOC_HI16
);
3756 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3757 "dsrl32", "d,w,<", reg
, reg
, 0);
3763 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3764 "d,w,<", reg
, freg
, 16);
3768 mid16
.X_add_number
>>= 16;
3769 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3770 freg
, (int) BFD_RELOC_LO16
);
3771 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3772 "d,w,<", reg
, reg
, 16);
3775 if ((lo32
.X_add_number
& 0xffff) != 0)
3776 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3777 (int) BFD_RELOC_LO16
);
3780 /* Load an address into a register. */
3783 load_address (counter
, reg
, ep
, used_at
)
3791 if (ep
->X_op
!= O_constant
3792 && ep
->X_op
!= O_symbol
)
3794 as_bad (_("expression too complex"));
3795 ep
->X_op
= O_constant
;
3798 if (ep
->X_op
== O_constant
)
3800 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3804 if (mips_pic
== NO_PIC
)
3806 /* If this is a reference to a GP relative symbol, we want
3807 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3809 lui $reg,<sym> (BFD_RELOC_HI16_S)
3810 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3811 If we have an addend, we always use the latter form.
3813 With 64bit address space and a usable $at we want
3814 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3815 lui $at,<sym> (BFD_RELOC_HI16_S)
3816 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3817 daddiu $at,<sym> (BFD_RELOC_LO16)
3821 If $at is already in use, we use a path which is suboptimal
3822 on superscalar processors.
3823 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3824 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3826 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3828 daddiu $reg,<sym> (BFD_RELOC_LO16)
3830 if (HAVE_64BIT_ADDRESSES
)
3832 /* We don't do GP optimization for now because RELAX_ENCODE can't
3833 hold the data for such large chunks. */
3835 if (*used_at
== 0 && ! mips_opts
.noat
)
3837 macro_build (p
, counter
, ep
, "lui", "t,u",
3838 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3839 macro_build (p
, counter
, ep
, "lui", "t,u",
3840 AT
, (int) BFD_RELOC_HI16_S
);
3841 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3842 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3843 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3844 AT
, AT
, (int) BFD_RELOC_LO16
);
3845 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3846 "d,w,<", reg
, reg
, 0);
3847 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3848 "d,v,t", reg
, reg
, AT
);
3853 macro_build (p
, counter
, ep
, "lui", "t,u",
3854 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3855 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3856 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3857 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3858 "d,w,<", reg
, reg
, 16);
3859 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3860 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3861 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3862 "d,w,<", reg
, reg
, 16);
3863 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3864 reg
, reg
, (int) BFD_RELOC_LO16
);
3869 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3870 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3873 macro_build ((char *) NULL
, counter
, ep
,
3874 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
3875 ? "addi" : "addiu" : "daddiu", "t,r,j",
3876 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3877 p
= frag_var (rs_machine_dependent
, 8, 0,
3878 RELAX_ENCODE (4, 8, 0, 4, 0,
3879 mips_opts
.warn_about_macros
),
3880 ep
->X_add_symbol
, 0, NULL
);
3882 macro_build_lui (p
, counter
, ep
, reg
);
3885 macro_build (p
, counter
, ep
,
3886 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
3887 ? "addi" : "addiu" : "daddiu",
3888 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3891 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3895 /* If this is a reference to an external symbol, we want
3896 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3898 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3900 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3901 If there is a constant, it must be added in after.
3903 If we have NewABI, we want
3904 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3905 unless we're referencing a global symbol with a non-zero
3906 offset, in which case cst must be added separately. */
3911 if (ep
->X_add_number
)
3913 frag_now
->tc_frag_data
.tc_fr_offset
=
3914 ex
.X_add_number
= ep
->X_add_number
;
3915 ep
->X_add_number
= 0;
3916 macro_build ((char *) NULL
, counter
, ep
,
3917 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3918 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3919 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3920 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3921 ex
.X_op
= O_constant
;
3922 macro_build ((char *) NULL
, counter
, &ex
,
3923 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
3924 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3925 p
= frag_var (rs_machine_dependent
, 8, 0,
3926 RELAX_ENCODE (8, 4, 0, 0, 0,
3927 mips_opts
.warn_about_macros
),
3928 ep
->X_add_symbol
, 0, (char *) NULL
);
3929 ep
->X_add_number
= ex
.X_add_number
;
3932 macro_build (p
, counter
, ep
,
3933 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3934 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3938 /* To avoid confusion in tc_gen_reloc, we must ensure
3939 that this does not become a variant frag. */
3940 frag_wane (frag_now
);
3946 ex
.X_add_number
= ep
->X_add_number
;
3947 ep
->X_add_number
= 0;
3949 macro_build ((char *) NULL
, counter
, ep
,
3950 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3951 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3952 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3953 p
= frag_var (rs_machine_dependent
, 4, 0,
3954 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3955 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3956 macro_build (p
, counter
, ep
,
3957 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3958 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3960 if (ex
.X_add_number
!= 0)
3962 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3963 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3964 ex
.X_op
= O_constant
;
3965 macro_build ((char *) NULL
, counter
, &ex
,
3966 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3967 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3971 else if (mips_pic
== SVR4_PIC
)
3976 /* This is the large GOT case. If this is a reference to an
3977 external symbol, we want
3978 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3980 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3982 Otherwise, for a reference to a local symbol in old ABI, we want
3983 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3985 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3986 If there is a constant, it must be added in after.
3988 In the NewABI, for local symbols, with or without offsets, we want:
3989 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3990 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3996 frag_now
->tc_frag_data
.tc_fr_offset
=
3997 ex
.X_add_number
= ep
->X_add_number
;
3998 ep
->X_add_number
= 0;
3999 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
4000 (int) BFD_RELOC_MIPS_GOT_HI16
);
4001 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4002 HAVE_32BIT_ADDRESSES
? "add" : "daddu", "d,v,t", reg
,
4003 reg
, mips_gp_register
);
4004 macro_build ((char *) NULL
, counter
, ep
,
4005 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4006 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
4007 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4008 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4009 else if (ex
.X_add_number
)
4011 ex
.X_op
= O_constant
;
4012 macro_build ((char *) NULL
, counter
, &ex
,
4013 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
4014 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4017 ep
->X_add_number
= ex
.X_add_number
;
4018 p
= frag_var (rs_machine_dependent
, 8, 0,
4019 RELAX_ENCODE (ex
.X_add_number
? 16 : 12, 8, 0, 4, 0,
4020 mips_opts
.warn_about_macros
),
4021 ep
->X_add_symbol
, 0, (char *) NULL
);
4022 macro_build (p
, counter
, ep
,
4023 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
4024 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4025 macro_build (p
+ 4, counter
, ep
,
4026 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu", "t,r,j",
4027 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
4031 ex
.X_add_number
= ep
->X_add_number
;
4032 ep
->X_add_number
= 0;
4033 if (reg_needs_delay (mips_gp_register
))
4038 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
4039 (int) BFD_RELOC_MIPS_GOT_HI16
);
4040 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4041 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
4042 reg
, mips_gp_register
);
4043 macro_build ((char *) NULL
, counter
, ep
,
4044 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4045 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
4046 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4047 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
4048 mips_opts
.warn_about_macros
),
4049 ep
->X_add_symbol
, 0, NULL
);
4052 /* We need a nop before loading from $gp. This special
4053 check is required because the lui which starts the main
4054 instruction stream does not refer to $gp, and so will not
4055 insert the nop which may be required. */
4056 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
4059 macro_build (p
, counter
, ep
,
4060 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
4061 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4063 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
4065 macro_build (p
, counter
, ep
,
4066 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4067 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4069 if (ex
.X_add_number
!= 0)
4071 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4072 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4073 ex
.X_op
= O_constant
;
4074 macro_build ((char *) NULL
, counter
, &ex
,
4075 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4076 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4080 else if (mips_pic
== EMBEDDED_PIC
)
4083 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4085 macro_build ((char *) NULL
, counter
, ep
,
4086 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4087 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
4093 /* Move the contents of register SOURCE into register DEST. */
4096 move_register (counter
, dest
, source
)
4101 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4102 HAVE_32BIT_GPRS
? "addu" : "daddu",
4103 "d,v,t", dest
, source
, 0);
4108 * This routine implements the seemingly endless macro or synthesized
4109 * instructions and addressing modes in the mips assembly language. Many
4110 * of these macros are simple and are similar to each other. These could
4111 * probably be handled by some kind of table or grammer aproach instead of
4112 * this verbose method. Others are not simple macros but are more like
4113 * optimizing code generation.
4114 * One interesting optimization is when several store macros appear
4115 * consecutivly that would load AT with the upper half of the same address.
4116 * The ensuing load upper instructions are ommited. This implies some kind
4117 * of global optimization. We currently only optimize within a single macro.
4118 * For many of the load and store macros if the address is specified as a
4119 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4120 * first load register 'at' with zero and use it as the base register. The
4121 * mips assembler simply uses register $zero. Just one tiny optimization
4126 struct mips_cl_insn
*ip
;
4128 register int treg
, sreg
, dreg
, breg
;
4144 bfd_reloc_code_real_type r
;
4145 int hold_mips_optimize
;
4147 assert (! mips_opts
.mips16
);
4149 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4150 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4151 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4152 mask
= ip
->insn_mo
->mask
;
4154 expr1
.X_op
= O_constant
;
4155 expr1
.X_op_symbol
= NULL
;
4156 expr1
.X_add_symbol
= NULL
;
4157 expr1
.X_add_number
= 1;
4159 /* Umatched fixups should not be put in the same frag as a relaxable
4160 macro. For example, suppose we have:
4164 addiu $4,$4,%lo(l1) # 3
4166 If instructions 1 and 2 were put in the same frag, md_frob_file would
4167 move the fixup for #1 after the fixups for the "unrelaxed" version of
4168 #2. This would confuse tc_gen_reloc, which expects the relocations
4169 for #2 to be the last for that frag.
4171 Also, if tc_gen_reloc sees certain relocations in a variant frag,
4172 it assumes that they belong to a relaxable macro. We mustn't put
4173 other uses of such relocations into a variant frag.
4175 To avoid both problems, finish the current frag it contains a
4176 %reloc() operator. The macro then goes into a new frag. */
4177 if (prev_reloc_op_frag
== frag_now
)
4179 frag_wane (frag_now
);
4193 mips_emit_delays (TRUE
);
4194 ++mips_opts
.noreorder
;
4195 mips_any_noreorder
= 1;
4197 expr1
.X_add_number
= 8;
4198 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
4200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4203 move_register (&icnt
, dreg
, sreg
);
4204 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4205 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4207 --mips_opts
.noreorder
;
4228 if (imm_expr
.X_op
== O_constant
4229 && imm_expr
.X_add_number
>= -0x8000
4230 && imm_expr
.X_add_number
< 0x8000)
4232 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
4233 (int) BFD_RELOC_LO16
);
4236 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4237 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4257 if (imm_expr
.X_op
== O_constant
4258 && imm_expr
.X_add_number
>= 0
4259 && imm_expr
.X_add_number
< 0x10000)
4261 if (mask
!= M_NOR_I
)
4262 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4263 sreg
, (int) BFD_RELOC_LO16
);
4266 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4267 treg
, sreg
, (int) BFD_RELOC_LO16
);
4268 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4269 "d,v,t", treg
, treg
, 0);
4274 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4275 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4293 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4295 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4299 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4300 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4308 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4309 likely
? "bgezl" : "bgez", "s,p", sreg
);
4314 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4315 likely
? "blezl" : "blez", "s,p", treg
);
4318 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4320 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4321 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4327 /* check for > max integer */
4328 maxnum
= 0x7fffffff;
4329 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4336 if (imm_expr
.X_op
== O_constant
4337 && imm_expr
.X_add_number
>= maxnum
4338 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4341 /* result is always false */
4345 as_warn (_("Branch %s is always false (nop)"),
4347 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4353 as_warn (_("Branch likely %s is always false"),
4355 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4360 if (imm_expr
.X_op
!= O_constant
)
4361 as_bad (_("Unsupported large constant"));
4362 ++imm_expr
.X_add_number
;
4366 if (mask
== M_BGEL_I
)
4368 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4370 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4371 likely
? "bgezl" : "bgez", "s,p", sreg
);
4374 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4376 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4377 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4380 maxnum
= 0x7fffffff;
4381 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4388 maxnum
= - maxnum
- 1;
4389 if (imm_expr
.X_op
== O_constant
4390 && imm_expr
.X_add_number
<= maxnum
4391 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4394 /* result is always true */
4395 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4396 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4399 set_at (&icnt
, sreg
, 0);
4400 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4401 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4411 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4412 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4415 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4416 "d,v,t", AT
, sreg
, treg
);
4417 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4418 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4426 && imm_expr
.X_op
== O_constant
4427 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4429 if (imm_expr
.X_op
!= O_constant
)
4430 as_bad (_("Unsupported large constant"));
4431 ++imm_expr
.X_add_number
;
4435 if (mask
== M_BGEUL_I
)
4437 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4439 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4441 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4442 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4445 set_at (&icnt
, sreg
, 1);
4446 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4447 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4455 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4456 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4461 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4462 likely
? "bltzl" : "bltz", "s,p", treg
);
4465 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4467 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4468 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4476 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4477 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4482 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4483 "d,v,t", AT
, treg
, sreg
);
4484 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4485 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4493 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4494 likely
? "blezl" : "blez", "s,p", sreg
);
4499 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4500 likely
? "bgezl" : "bgez", "s,p", treg
);
4503 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4505 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4506 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4512 maxnum
= 0x7fffffff;
4513 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4520 if (imm_expr
.X_op
== O_constant
4521 && imm_expr
.X_add_number
>= maxnum
4522 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4524 if (imm_expr
.X_op
!= O_constant
)
4525 as_bad (_("Unsupported large constant"));
4526 ++imm_expr
.X_add_number
;
4530 if (mask
== M_BLTL_I
)
4532 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4534 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4535 likely
? "bltzl" : "bltz", "s,p", sreg
);
4538 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4541 likely
? "blezl" : "blez", "s,p", sreg
);
4544 set_at (&icnt
, sreg
, 0);
4545 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4546 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4554 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4555 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4560 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4561 "d,v,t", AT
, treg
, sreg
);
4562 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4563 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4571 && imm_expr
.X_op
== O_constant
4572 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4574 if (imm_expr
.X_op
!= O_constant
)
4575 as_bad (_("Unsupported large constant"));
4576 ++imm_expr
.X_add_number
;
4580 if (mask
== M_BLTUL_I
)
4582 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4584 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4586 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4587 likely
? "beql" : "beq",
4591 set_at (&icnt
, sreg
, 1);
4592 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4593 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4601 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4602 likely
? "bltzl" : "bltz", "s,p", sreg
);
4607 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4608 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4611 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4613 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4614 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4624 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4625 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4628 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4631 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4632 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4647 as_warn (_("Divide by zero."));
4649 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4652 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4657 mips_emit_delays (TRUE
);
4658 ++mips_opts
.noreorder
;
4659 mips_any_noreorder
= 1;
4662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4663 "s,t,q", treg
, 0, 7);
4664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4665 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4669 expr1
.X_add_number
= 8;
4670 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4672 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4673 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4676 expr1
.X_add_number
= -1;
4677 macro_build ((char *) NULL
, &icnt
, &expr1
,
4678 dbl
? "daddiu" : "addiu",
4679 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4680 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4681 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4684 expr1
.X_add_number
= 1;
4685 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4686 (int) BFD_RELOC_LO16
);
4687 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4688 "d,w,<", AT
, AT
, 31);
4692 expr1
.X_add_number
= 0x80000000;
4693 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4694 (int) BFD_RELOC_HI16
);
4698 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4699 "s,t,q", sreg
, AT
, 6);
4700 /* We want to close the noreorder block as soon as possible, so
4701 that later insns are available for delay slot filling. */
4702 --mips_opts
.noreorder
;
4706 expr1
.X_add_number
= 8;
4707 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4708 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4711 /* We want to close the noreorder block as soon as possible, so
4712 that later insns are available for delay slot filling. */
4713 --mips_opts
.noreorder
;
4715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4718 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4757 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4759 as_warn (_("Divide by zero."));
4761 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4768 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4770 if (strcmp (s2
, "mflo") == 0)
4771 move_register (&icnt
, dreg
, sreg
);
4773 move_register (&icnt
, dreg
, 0);
4776 if (imm_expr
.X_op
== O_constant
4777 && imm_expr
.X_add_number
== -1
4778 && s
[strlen (s
) - 1] != 'u')
4780 if (strcmp (s2
, "mflo") == 0)
4782 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4783 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4786 move_register (&icnt
, dreg
, 0);
4790 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4791 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4793 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4812 mips_emit_delays (TRUE
);
4813 ++mips_opts
.noreorder
;
4814 mips_any_noreorder
= 1;
4817 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4818 "s,t,q", treg
, 0, 7);
4819 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4821 /* We want to close the noreorder block as soon as possible, so
4822 that later insns are available for delay slot filling. */
4823 --mips_opts
.noreorder
;
4827 expr1
.X_add_number
= 8;
4828 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4829 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4832 /* We want to close the noreorder block as soon as possible, so
4833 that later insns are available for delay slot filling. */
4834 --mips_opts
.noreorder
;
4835 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4838 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4844 /* Load the address of a symbol into a register. If breg is not
4845 zero, we then add a base register to it. */
4847 if (dbl
&& HAVE_32BIT_GPRS
)
4848 as_warn (_("dla used to load 32-bit register"));
4850 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4851 as_warn (_("la used to load 64-bit address"));
4853 if (offset_expr
.X_op
== O_constant
4854 && offset_expr
.X_add_number
>= -0x8000
4855 && offset_expr
.X_add_number
< 0x8000)
4857 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4858 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" :
4859 HAVE_NEWABI
? "addi" : "addiu",
4860 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4875 /* When generating embedded PIC code, we permit expressions of
4878 la $treg,foo-bar($breg)
4879 where bar is an address in the current section. These are used
4880 when getting the addresses of functions. We don't permit
4881 X_add_number to be non-zero, because if the symbol is
4882 external the relaxing code needs to know that any addend is
4883 purely the offset to X_op_symbol. */
4884 if (mips_pic
== EMBEDDED_PIC
4885 && offset_expr
.X_op
== O_subtract
4886 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4887 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4888 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4890 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4893 && (offset_expr
.X_add_number
== 0
4894 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4900 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4901 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4905 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4906 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4907 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4908 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4909 "d,v,t", tempreg
, tempreg
, breg
);
4911 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4912 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4913 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4919 if (offset_expr
.X_op
!= O_symbol
4920 && offset_expr
.X_op
!= O_constant
)
4922 as_bad (_("expression too complex"));
4923 offset_expr
.X_op
= O_constant
;
4926 if (offset_expr
.X_op
== O_constant
)
4927 load_register (&icnt
, tempreg
, &offset_expr
,
4928 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4929 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4930 : HAVE_64BIT_ADDRESSES
));
4931 else if (mips_pic
== NO_PIC
)
4933 /* If this is a reference to a GP relative symbol, we want
4934 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4936 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4937 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4938 If we have a constant, we need two instructions anyhow,
4939 so we may as well always use the latter form.
4941 With 64bit address space and a usable $at we want
4942 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4943 lui $at,<sym> (BFD_RELOC_HI16_S)
4944 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4945 daddiu $at,<sym> (BFD_RELOC_LO16)
4947 daddu $tempreg,$tempreg,$at
4949 If $at is already in use, we use a path which is suboptimal
4950 on superscalar processors.
4951 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4952 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4954 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4956 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4959 if (HAVE_64BIT_ADDRESSES
)
4961 /* We don't do GP optimization for now because RELAX_ENCODE can't
4962 hold the data for such large chunks. */
4964 if (used_at
== 0 && ! mips_opts
.noat
)
4966 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4967 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4968 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4969 AT
, (int) BFD_RELOC_HI16_S
);
4970 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4971 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4972 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4973 AT
, AT
, (int) BFD_RELOC_LO16
);
4974 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4975 "d,w,<", tempreg
, tempreg
, 0);
4976 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
4977 "d,v,t", tempreg
, tempreg
, AT
);
4982 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4983 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4984 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4985 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4986 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4987 tempreg
, tempreg
, 16);
4988 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4989 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4990 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4991 tempreg
, tempreg
, 16);
4992 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4993 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4998 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4999 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5002 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5003 HAVE_NEWABI
? "addi" : "addiu",
5004 "t,r,j", tempreg
, mips_gp_register
,
5005 (int) BFD_RELOC_GPREL16
);
5006 p
= frag_var (rs_machine_dependent
, 8, 0,
5007 RELAX_ENCODE (4, 8, 0, 4, 0,
5008 mips_opts
.warn_about_macros
),
5009 offset_expr
.X_add_symbol
, 0, NULL
);
5011 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5014 macro_build (p
, &icnt
, &offset_expr
,
5015 HAVE_NEWABI
? "addi" : "addiu",
5016 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5019 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5021 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5023 /* If this is a reference to an external symbol, and there
5024 is no constant, we want
5025 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5026 or if tempreg is PIC_CALL_REG
5027 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5028 For a local symbol, we want
5029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5031 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5033 If we have a small constant, and this is a reference to
5034 an external symbol, we want
5035 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5037 addiu $tempreg,$tempreg,<constant>
5038 For a local symbol, we want the same instruction
5039 sequence, but we output a BFD_RELOC_LO16 reloc on the
5042 If we have a large constant, and this is a reference to
5043 an external symbol, we want
5044 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5045 lui $at,<hiconstant>
5046 addiu $at,$at,<loconstant>
5047 addu $tempreg,$tempreg,$at
5048 For a local symbol, we want the same instruction
5049 sequence, but we output a BFD_RELOC_LO16 reloc on the
5053 expr1
.X_add_number
= offset_expr
.X_add_number
;
5054 offset_expr
.X_add_number
= 0;
5056 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5057 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5058 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5059 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5060 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
5061 if (expr1
.X_add_number
== 0)
5070 /* We're going to put in an addu instruction using
5071 tempreg, so we may as well insert the nop right
5073 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5077 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
5078 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
5080 ? mips_opts
.warn_about_macros
5082 offset_expr
.X_add_symbol
, 0, NULL
);
5085 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5088 macro_build (p
, &icnt
, &expr1
,
5089 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5090 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5091 /* FIXME: If breg == 0, and the next instruction uses
5092 $tempreg, then if this variant case is used an extra
5093 nop will be generated. */
5095 else if (expr1
.X_add_number
>= -0x8000
5096 && expr1
.X_add_number
< 0x8000)
5098 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5100 macro_build ((char *) NULL
, &icnt
, &expr1
,
5101 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5102 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5103 frag_var (rs_machine_dependent
, 0, 0,
5104 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5105 offset_expr
.X_add_symbol
, 0, NULL
);
5111 /* If we are going to add in a base register, and the
5112 target register and the base register are the same,
5113 then we are using AT as a temporary register. Since
5114 we want to load the constant into AT, we add our
5115 current AT (from the global offset table) and the
5116 register into the register now, and pretend we were
5117 not using a base register. */
5122 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5124 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5125 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5126 "d,v,t", treg
, AT
, breg
);
5132 /* Set mips_optimize around the lui instruction to avoid
5133 inserting an unnecessary nop after the lw. */
5134 hold_mips_optimize
= mips_optimize
;
5136 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5137 mips_optimize
= hold_mips_optimize
;
5139 macro_build ((char *) NULL
, &icnt
, &expr1
,
5140 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5141 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5142 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5143 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5144 "d,v,t", tempreg
, tempreg
, AT
);
5145 frag_var (rs_machine_dependent
, 0, 0,
5146 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
5147 offset_expr
.X_add_symbol
, 0, NULL
);
5151 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5154 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5157 /* If this is a reference to an external, and there is no
5158 constant, or local symbol (*), with or without a
5160 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5161 or if tempreg is PIC_CALL_REG
5162 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5164 If we have a small constant, and this is a reference to
5165 an external symbol, we want
5166 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5167 addiu $tempreg,$tempreg,<constant>
5169 If we have a large constant, and this is a reference to
5170 an external symbol, we want
5171 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5172 lui $at,<hiconstant>
5173 addiu $at,$at,<loconstant>
5174 addu $tempreg,$tempreg,$at
5176 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5177 local symbols, even though it introduces an additional
5181 if (offset_expr
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5182 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5183 if (offset_expr
.X_add_number
)
5185 frag_now
->tc_frag_data
.tc_fr_offset
=
5186 expr1
.X_add_number
= offset_expr
.X_add_number
;
5187 offset_expr
.X_add_number
= 0;
5189 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5190 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5191 "t,o(b)", tempreg
, lw_reloc_type
,
5194 if (expr1
.X_add_number
>= -0x8000
5195 && expr1
.X_add_number
< 0x8000)
5197 macro_build ((char *) NULL
, &icnt
, &expr1
,
5198 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
5199 "t,r,j", tempreg
, tempreg
,
5200 (int) BFD_RELOC_LO16
);
5201 p
= frag_var (rs_machine_dependent
, 4, 0,
5202 RELAX_ENCODE (8, 4, 0, 0, 0, 0),
5203 offset_expr
.X_add_symbol
, 0, NULL
);
5205 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
))
5209 /* If we are going to add in a base register, and the
5210 target register and the base register are the same,
5211 then we are using AT as a temporary register. Since
5212 we want to load the constant into AT, we add our
5213 current AT (from the global offset table) and the
5214 register into the register now, and pretend we were
5215 not using a base register. */
5220 assert (tempreg
== AT
);
5221 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5222 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5223 "d,v,t", treg
, AT
, breg
);
5228 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
5229 macro_build ((char *) NULL
, &icnt
, &expr1
,
5230 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
5231 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5232 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5233 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5234 "d,v,t", dreg
, dreg
, AT
);
5236 p
= frag_var (rs_machine_dependent
, 4 + adj
, 0,
5237 RELAX_ENCODE (16 + adj
, 4 + adj
,
5239 offset_expr
.X_add_symbol
, 0, NULL
);
5244 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5246 offset_expr
.X_add_number
= expr1
.X_add_number
;
5248 macro_build (p
, &icnt
, &offset_expr
,
5249 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5250 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_DISP
,
5254 macro_build (p
+ 4, &icnt
, (expressionS
*) NULL
,
5255 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5256 "d,v,t", treg
, tempreg
, breg
);
5263 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5264 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5265 "t,o(b)", tempreg
, lw_reloc_type
,
5267 if (lw_reloc_type
!= BFD_RELOC_MIPS_GOT_DISP
)
5268 p
= frag_var (rs_machine_dependent
, 0, 0,
5269 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5270 offset_expr
.X_add_symbol
, 0, NULL
);
5275 /* To avoid confusion in tc_gen_reloc, we must ensure
5276 that this does not become a variant frag. */
5277 frag_wane (frag_now
);
5281 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5285 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5286 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5287 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5289 /* This is the large GOT case. If this is a reference to an
5290 external symbol, and there is no constant, we want
5291 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5292 addu $tempreg,$tempreg,$gp
5293 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5294 or if tempreg is PIC_CALL_REG
5295 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5296 addu $tempreg,$tempreg,$gp
5297 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5298 For a local symbol, we want
5299 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5301 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5303 If we have a small constant, and this is a reference to
5304 an external symbol, we want
5305 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5306 addu $tempreg,$tempreg,$gp
5307 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5309 addiu $tempreg,$tempreg,<constant>
5310 For a local symbol, we want
5311 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5313 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5315 If we have a large constant, and this is a reference to
5316 an external symbol, we want
5317 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5318 addu $tempreg,$tempreg,$gp
5319 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5320 lui $at,<hiconstant>
5321 addiu $at,$at,<loconstant>
5322 addu $tempreg,$tempreg,$at
5323 For a local symbol, we want
5324 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5325 lui $at,<hiconstant>
5326 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5327 addu $tempreg,$tempreg,$at
5330 expr1
.X_add_number
= offset_expr
.X_add_number
;
5331 offset_expr
.X_add_number
= 0;
5333 if (reg_needs_delay (mips_gp_register
))
5337 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5339 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5340 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5342 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5343 tempreg
, lui_reloc_type
);
5344 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5345 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5346 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5347 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5348 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5349 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5350 if (expr1
.X_add_number
== 0)
5358 /* We're going to put in an addu instruction using
5359 tempreg, so we may as well insert the nop right
5361 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5366 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5367 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
5370 ? mips_opts
.warn_about_macros
5372 offset_expr
.X_add_symbol
, 0, NULL
);
5374 else if (expr1
.X_add_number
>= -0x8000
5375 && expr1
.X_add_number
< 0x8000)
5377 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5379 macro_build ((char *) NULL
, &icnt
, &expr1
,
5380 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5381 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5383 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5384 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
5386 ? mips_opts
.warn_about_macros
5388 offset_expr
.X_add_symbol
, 0, NULL
);
5394 /* If we are going to add in a base register, and the
5395 target register and the base register are the same,
5396 then we are using AT as a temporary register. Since
5397 we want to load the constant into AT, we add our
5398 current AT (from the global offset table) and the
5399 register into the register now, and pretend we were
5400 not using a base register. */
5408 assert (tempreg
== AT
);
5409 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5411 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5412 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5413 "d,v,t", treg
, AT
, breg
);
5418 /* Set mips_optimize around the lui instruction to avoid
5419 inserting an unnecessary nop after the lw. */
5420 hold_mips_optimize
= mips_optimize
;
5422 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5423 mips_optimize
= hold_mips_optimize
;
5425 macro_build ((char *) NULL
, &icnt
, &expr1
,
5426 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5427 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5429 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5430 "d,v,t", dreg
, dreg
, AT
);
5432 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5433 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5436 ? mips_opts
.warn_about_macros
5438 offset_expr
.X_add_symbol
, 0, NULL
);
5445 /* This is needed because this instruction uses $gp, but
5446 the first instruction on the main stream does not. */
5447 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5451 macro_build (p
, &icnt
, &offset_expr
,
5452 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5457 if (expr1
.X_add_number
>= -0x8000
5458 && expr1
.X_add_number
< 0x8000)
5460 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5462 macro_build (p
, &icnt
, &expr1
,
5463 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5464 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5465 /* FIXME: If add_number is 0, and there was no base
5466 register, the external symbol case ended with a load,
5467 so if the symbol turns out to not be external, and
5468 the next instruction uses tempreg, an unnecessary nop
5469 will be inserted. */
5475 /* We must add in the base register now, as in the
5476 external symbol case. */
5477 assert (tempreg
== AT
);
5478 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5480 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5481 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5482 "d,v,t", treg
, AT
, breg
);
5485 /* We set breg to 0 because we have arranged to add
5486 it in in both cases. */
5490 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5492 macro_build (p
, &icnt
, &expr1
,
5493 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5494 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5496 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5497 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5498 "d,v,t", tempreg
, tempreg
, AT
);
5502 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5505 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5506 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5509 /* This is the large GOT case. If this is a reference to an
5510 external symbol, and there is no constant, we want
5511 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5512 add $tempreg,$tempreg,$gp
5513 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5514 or if tempreg is PIC_CALL_REG
5515 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5516 add $tempreg,$tempreg,$gp
5517 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5519 If we have a small constant, and this is a reference to
5520 an external symbol, we want
5521 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5522 add $tempreg,$tempreg,$gp
5523 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5524 addi $tempreg,$tempreg,<constant>
5526 If we have a large constant, and this is a reference to
5527 an external symbol, we want
5528 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5529 addu $tempreg,$tempreg,$gp
5530 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5531 lui $at,<hiconstant>
5532 addi $at,$at,<loconstant>
5533 add $tempreg,$tempreg,$at
5535 If we have NewABI, and we know it's a local symbol, we want
5536 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5537 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5538 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5542 frag_now
->tc_frag_data
.tc_fr_offset
=
5543 expr1
.X_add_number
= offset_expr
.X_add_number
;
5544 offset_expr
.X_add_number
= 0;
5546 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5548 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5549 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5551 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5552 tempreg
, lui_reloc_type
);
5553 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5554 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5555 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5556 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5557 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5558 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5560 if (expr1
.X_add_number
== 0)
5562 p
= frag_var (rs_machine_dependent
, 8, 0,
5563 RELAX_ENCODE (12, 8, 0, 4, 0,
5564 mips_opts
.warn_about_macros
),
5565 offset_expr
.X_add_symbol
, 0, NULL
);
5567 else if (expr1
.X_add_number
>= -0x8000
5568 && expr1
.X_add_number
< 0x8000)
5570 macro_build ((char *) NULL
, &icnt
, &expr1
,
5571 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
5572 "t,r,j", tempreg
, tempreg
,
5573 (int) BFD_RELOC_LO16
);
5574 p
= frag_var (rs_machine_dependent
, 8, 0,
5575 RELAX_ENCODE (16, 8, 0, 4, 0,
5576 mips_opts
.warn_about_macros
),
5577 offset_expr
.X_add_symbol
, 0, NULL
);
5579 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
))
5583 /* If we are going to add in a base register, and the
5584 target register and the base register are the same,
5585 then we are using AT as a temporary register. Since
5586 we want to load the constant into AT, we add our
5587 current AT (from the global offset table) and the
5588 register into the register now, and pretend we were
5589 not using a base register. */
5594 assert (tempreg
== AT
);
5595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5596 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5597 "d,v,t", treg
, AT
, breg
);
5602 /* Set mips_optimize around the lui instruction to avoid
5603 inserting an unnecessary nop after the lw. */
5604 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
5605 macro_build ((char *) NULL
, &icnt
, &expr1
,
5606 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
5607 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5608 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5609 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5610 "d,v,t", dreg
, dreg
, AT
);
5612 p
= frag_var (rs_machine_dependent
, 8 + adj
, 0,
5613 RELAX_ENCODE (24 + adj
, 8 + adj
,
5616 ? mips_opts
.warn_about_macros
5618 offset_expr
.X_add_symbol
, 0, NULL
);
5623 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5625 offset_expr
.X_add_number
= expr1
.X_add_number
;
5626 macro_build (p
, &icnt
, &offset_expr
,
5627 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5629 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5630 macro_build (p
+ 4, &icnt
, &offset_expr
,
5631 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu", "t,r,j",
5632 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
5635 macro_build (p
+ 8, &icnt
, (expressionS
*) NULL
,
5636 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5637 "d,v,t", treg
, tempreg
, breg
);
5642 else if (mips_pic
== EMBEDDED_PIC
)
5645 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5647 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5648 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5649 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5658 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5659 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" :
5660 HAVE_NEWABI
? "add" : "addu";
5662 s
= HAVE_64BIT_ADDRESSES
? "daddu" : HAVE_NEWABI
? "add" : "addu";
5664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5665 "d,v,t", treg
, tempreg
, breg
);
5674 /* The j instruction may not be used in PIC code, since it
5675 requires an absolute address. We convert it to a b
5677 if (mips_pic
== NO_PIC
)
5678 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5680 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5683 /* The jal instructions must be handled as macros because when
5684 generating PIC code they expand to multi-instruction
5685 sequences. Normally they are simple instructions. */
5690 if (mips_pic
== NO_PIC
5691 || mips_pic
== EMBEDDED_PIC
)
5692 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5694 else if (mips_pic
== SVR4_PIC
)
5696 if (sreg
!= PIC_CALL_REG
)
5697 as_warn (_("MIPS PIC call to register other than $25"));
5699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5703 if (mips_cprestore_offset
< 0)
5704 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5707 if (! mips_frame_reg_valid
)
5709 as_warn (_("No .frame pseudo-op used in PIC code"));
5710 /* Quiet this warning. */
5711 mips_frame_reg_valid
= 1;
5713 if (! mips_cprestore_valid
)
5715 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5716 /* Quiet this warning. */
5717 mips_cprestore_valid
= 1;
5719 expr1
.X_add_number
= mips_cprestore_offset
;
5720 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5721 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5722 mips_gp_register
, mips_frame_reg
);
5732 if (mips_pic
== NO_PIC
)
5733 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5734 else if (mips_pic
== SVR4_PIC
)
5738 /* If this is a reference to an external symbol, and we are
5739 using a small GOT, we want
5740 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5744 lw $gp,cprestore($sp)
5745 The cprestore value is set using the .cprestore
5746 pseudo-op. If we are using a big GOT, we want
5747 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5749 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5753 lw $gp,cprestore($sp)
5754 If the symbol is not external, we want
5755 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5757 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5760 lw $gp,cprestore($sp)
5762 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5763 sequences above, minus nops, unless the symbol is local,
5764 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5771 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5772 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5773 "t,o(b)", PIC_CALL_REG
,
5774 (int) BFD_RELOC_MIPS_CALL16
,
5776 frag_var (rs_machine_dependent
, 0, 0,
5777 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5778 offset_expr
.X_add_symbol
, 0, NULL
);
5783 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5784 "t,u", PIC_CALL_REG
,
5785 (int) BFD_RELOC_MIPS_CALL_HI16
);
5786 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5787 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5788 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5790 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5791 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5792 "t,o(b)", PIC_CALL_REG
,
5793 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5794 p
= frag_var (rs_machine_dependent
, 8, 0,
5795 RELAX_ENCODE (12, 8, 0, 4, 0, 0),
5796 offset_expr
.X_add_symbol
, 0, NULL
);
5797 macro_build (p
, &icnt
, &offset_expr
,
5798 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5799 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_GOT_PAGE
,
5801 macro_build (p
+ 4, &icnt
, &offset_expr
,
5802 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
5803 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5804 (int) BFD_RELOC_MIPS_GOT_OFST
);
5807 macro_build_jalr (icnt
, &offset_expr
);
5814 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5815 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5816 "t,o(b)", PIC_CALL_REG
,
5817 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5818 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5820 p
= frag_var (rs_machine_dependent
, 4, 0,
5821 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5822 offset_expr
.X_add_symbol
, 0, NULL
);
5828 if (reg_needs_delay (mips_gp_register
))
5832 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5833 "t,u", PIC_CALL_REG
,
5834 (int) BFD_RELOC_MIPS_CALL_HI16
);
5835 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5836 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5837 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5839 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5840 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5841 "t,o(b)", PIC_CALL_REG
,
5842 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5843 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5845 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5846 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5848 offset_expr
.X_add_symbol
, 0, NULL
);
5851 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5854 macro_build (p
, &icnt
, &offset_expr
,
5855 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5856 "t,o(b)", PIC_CALL_REG
,
5857 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5859 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5862 macro_build (p
, &icnt
, &offset_expr
,
5863 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5864 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5865 (int) BFD_RELOC_LO16
);
5866 macro_build_jalr (icnt
, &offset_expr
);
5868 if (mips_cprestore_offset
< 0)
5869 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5872 if (! mips_frame_reg_valid
)
5874 as_warn (_("No .frame pseudo-op used in PIC code"));
5875 /* Quiet this warning. */
5876 mips_frame_reg_valid
= 1;
5878 if (! mips_cprestore_valid
)
5880 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5881 /* Quiet this warning. */
5882 mips_cprestore_valid
= 1;
5884 if (mips_opts
.noreorder
)
5885 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5887 expr1
.X_add_number
= mips_cprestore_offset
;
5888 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5889 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5890 mips_gp_register
, mips_frame_reg
);
5894 else if (mips_pic
== EMBEDDED_PIC
)
5896 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5897 /* The linker may expand the call to a longer sequence which
5898 uses $at, so we must break rather than return. */
5923 /* Itbl support may require additional care here. */
5928 /* Itbl support may require additional care here. */
5933 /* Itbl support may require additional care here. */
5938 /* Itbl support may require additional care here. */
5950 if (mips_arch
== CPU_R4650
)
5952 as_bad (_("opcode not supported on this processor"));
5956 /* Itbl support may require additional care here. */
5961 /* Itbl support may require additional care here. */
5966 /* Itbl support may require additional care here. */
5986 if (breg
== treg
|| coproc
|| lr
)
6008 /* Itbl support may require additional care here. */
6013 /* Itbl support may require additional care here. */
6018 /* Itbl support may require additional care here. */
6023 /* Itbl support may require additional care here. */
6039 if (mips_arch
== CPU_R4650
)
6041 as_bad (_("opcode not supported on this processor"));
6046 /* Itbl support may require additional care here. */
6050 /* Itbl support may require additional care here. */
6055 /* Itbl support may require additional care here. */
6067 /* Itbl support may require additional care here. */
6068 if (mask
== M_LWC1_AB
6069 || mask
== M_SWC1_AB
6070 || mask
== M_LDC1_AB
6071 || mask
== M_SDC1_AB
6080 /* For embedded PIC, we allow loads where the offset is calculated
6081 by subtracting a symbol in the current segment from an unknown
6082 symbol, relative to a base register, e.g.:
6083 <op> $treg, <sym>-<localsym>($breg)
6084 This is used by the compiler for switch statements. */
6085 if (mips_pic
== EMBEDDED_PIC
6086 && offset_expr
.X_op
== O_subtract
6087 && (symbol_constant_p (offset_expr
.X_op_symbol
)
6088 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
6089 : (symbol_equated_p (offset_expr
.X_op_symbol
)
6091 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
6095 && (offset_expr
.X_add_number
== 0
6096 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
6098 /* For this case, we output the instructions:
6099 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
6100 addiu $tempreg,$tempreg,$breg
6101 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
6102 If the relocation would fit entirely in 16 bits, it would be
6104 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
6105 instead, but that seems quite difficult. */
6106 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6107 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
6108 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6109 ((bfd_arch_bits_per_address (stdoutput
) == 32
6110 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6111 ? HAVE_NEWABI
? "add" : "addu" : "daddu"),
6112 "d,v,t", tempreg
, tempreg
, breg
);
6113 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6114 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
6120 if (offset_expr
.X_op
!= O_constant
6121 && offset_expr
.X_op
!= O_symbol
)
6123 as_bad (_("expression too complex"));
6124 offset_expr
.X_op
= O_constant
;
6127 /* A constant expression in PIC code can be handled just as it
6128 is in non PIC code. */
6129 if (mips_pic
== NO_PIC
6130 || offset_expr
.X_op
== O_constant
)
6134 /* If this is a reference to a GP relative symbol, and there
6135 is no base register, we want
6136 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6137 Otherwise, if there is no base register, we want
6138 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6139 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6140 If we have a constant, we need two instructions anyhow,
6141 so we always use the latter form.
6143 If we have a base register, and this is a reference to a
6144 GP relative symbol, we want
6145 addu $tempreg,$breg,$gp
6146 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6148 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6149 addu $tempreg,$tempreg,$breg
6150 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6151 With a constant we always use the latter case.
6153 With 64bit address space and no base register and $at usable,
6155 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6156 lui $at,<sym> (BFD_RELOC_HI16_S)
6157 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6160 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6161 If we have a base register, we want
6162 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6163 lui $at,<sym> (BFD_RELOC_HI16_S)
6164 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6168 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6170 Without $at we can't generate the optimal path for superscalar
6171 processors here since this would require two temporary registers.
6172 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6173 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6175 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6177 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6178 If we have a base register, we want
6179 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6180 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6182 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6184 daddu $tempreg,$tempreg,$breg
6185 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6187 If we have 64-bit addresses, as an optimization, for
6188 addresses which are 32-bit constants (e.g. kseg0/kseg1
6189 addresses) we fall back to the 32-bit address generation
6190 mechanism since it is more efficient. Note that due to
6191 the signed offset used by memory operations, the 32-bit
6192 range is shifted down by 32768 here. This code should
6193 probably attempt to generate 64-bit constants more
6194 efficiently in general.
6196 As an extension for architectures with 64-bit registers,
6197 we don't truncate 64-bit addresses given as literal
6198 constants down to 32 bits, to support existing practice
6199 in the mips64 Linux (the kernel), that compiles source
6200 files with -mabi=64, assembling them as o32 or n32 (with
6201 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6202 the whole kernel is loaded into a memory region that is
6203 addressible with sign-extended 32-bit addresses, it is
6204 wasteful to compute the upper 32 bits of every
6205 non-literal address, that takes more space and time.
6206 Some day this should probably be implemented as an
6207 assembler option, such that the kernel doesn't have to
6208 use such ugly hacks, even though it will still have to
6209 end up converting the binary to ELF32 for a number of
6210 platforms whose boot loaders don't support ELF64
6212 if ((offset_expr
.X_op
!= O_constant
&& HAVE_64BIT_ADDRESSES
)
6213 || (offset_expr
.X_op
== O_constant
6214 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)
6215 && HAVE_64BIT_ADDRESS_CONSTANTS
))
6219 /* We don't do GP optimization for now because RELAX_ENCODE can't
6220 hold the data for such large chunks. */
6222 if (used_at
== 0 && ! mips_opts
.noat
)
6224 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6225 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
6226 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6227 AT
, (int) BFD_RELOC_HI16_S
);
6228 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6229 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
6231 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
6232 "d,v,t", AT
, AT
, breg
);
6233 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
6234 "d,w,<", tempreg
, tempreg
, 0);
6235 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
6236 "d,v,t", tempreg
, tempreg
, AT
);
6237 macro_build (p
, &icnt
, &offset_expr
, s
,
6238 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
6243 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6244 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
6245 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6246 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
6247 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
6248 "d,w,<", tempreg
, tempreg
, 16);
6249 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6250 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
6251 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
6252 "d,w,<", tempreg
, tempreg
, 16);
6254 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
6255 "d,v,t", tempreg
, tempreg
, breg
);
6256 macro_build (p
, &icnt
, &offset_expr
, s
,
6257 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
6262 else if (offset_expr
.X_op
== O_constant
6263 && !HAVE_64BIT_ADDRESS_CONSTANTS
6264 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6265 as_bad (_("load/store address overflow (max 32 bits)"));
6269 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6270 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6275 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6276 treg
, (int) BFD_RELOC_GPREL16
,
6278 p
= frag_var (rs_machine_dependent
, 8, 0,
6279 RELAX_ENCODE (4, 8, 0, 4, 0,
6280 (mips_opts
.warn_about_macros
6282 && mips_opts
.noat
))),
6283 offset_expr
.X_add_symbol
, 0, NULL
);
6286 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
6289 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6290 (int) BFD_RELOC_LO16
, tempreg
);
6294 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6295 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6300 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6301 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
6302 ? "add" : "addu" : "daddu",
6303 "d,v,t", tempreg
, breg
, mips_gp_register
);
6304 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6305 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6306 p
= frag_var (rs_machine_dependent
, 12, 0,
6307 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
6308 offset_expr
.X_add_symbol
, 0, NULL
);
6310 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
6313 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6314 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
6315 ? "add" : "addu" : "daddu",
6316 "d,v,t", tempreg
, tempreg
, breg
);
6319 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6320 (int) BFD_RELOC_LO16
, tempreg
);
6323 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6326 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6328 /* If this is a reference to an external symbol, we want
6329 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6331 <op> $treg,0($tempreg)
6333 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6335 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6336 <op> $treg,0($tempreg)
6339 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6340 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6342 If there is a base register, we add it to $tempreg before
6343 the <op>. If there is a constant, we stick it in the
6344 <op> instruction. We don't handle constants larger than
6345 16 bits, because we have no way to load the upper 16 bits
6346 (actually, we could handle them for the subset of cases
6347 in which we are not using $at). */
6348 assert (offset_expr
.X_op
== O_symbol
);
6351 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6352 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6353 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
6356 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6357 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
6358 "d,v,t", tempreg
, tempreg
, breg
);
6359 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6360 (int) BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6367 expr1
.X_add_number
= offset_expr
.X_add_number
;
6368 offset_expr
.X_add_number
= 0;
6369 if (expr1
.X_add_number
< -0x8000
6370 || expr1
.X_add_number
>= 0x8000)
6371 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6373 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6374 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
6375 (int) lw_reloc_type
, mips_gp_register
);
6376 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6377 p
= frag_var (rs_machine_dependent
, 4, 0,
6378 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6379 offset_expr
.X_add_symbol
, 0, NULL
);
6380 macro_build (p
, &icnt
, &offset_expr
,
6381 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6382 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6384 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6385 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6386 "d,v,t", tempreg
, tempreg
, breg
);
6387 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6388 (int) BFD_RELOC_LO16
, tempreg
);
6390 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6395 /* If this is a reference to an external symbol, we want
6396 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6397 addu $tempreg,$tempreg,$gp
6398 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6399 <op> $treg,0($tempreg)
6401 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6403 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6404 <op> $treg,0($tempreg)
6405 If there is a base register, we add it to $tempreg before
6406 the <op>. If there is a constant, we stick it in the
6407 <op> instruction. We don't handle constants larger than
6408 16 bits, because we have no way to load the upper 16 bits
6409 (actually, we could handle them for the subset of cases
6410 in which we are not using $at). */
6411 assert (offset_expr
.X_op
== O_symbol
);
6412 expr1
.X_add_number
= offset_expr
.X_add_number
;
6413 offset_expr
.X_add_number
= 0;
6414 if (expr1
.X_add_number
< -0x8000
6415 || expr1
.X_add_number
>= 0x8000)
6416 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6417 if (reg_needs_delay (mips_gp_register
))
6422 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6423 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6424 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6425 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6426 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
6427 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6428 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6429 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
6431 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
6432 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
6433 offset_expr
.X_add_symbol
, 0, NULL
);
6436 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6439 macro_build (p
, &icnt
, &offset_expr
,
6440 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6441 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
6444 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6446 macro_build (p
, &icnt
, &offset_expr
,
6447 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6448 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6450 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6451 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6452 "d,v,t", tempreg
, tempreg
, breg
);
6453 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6454 (int) BFD_RELOC_LO16
, tempreg
);
6456 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6459 int bregsz
= breg
!= 0 ? 4 : 0;
6461 /* If this is a reference to an external symbol, we want
6462 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6463 add $tempreg,$tempreg,$gp
6464 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6465 <op> $treg,<ofst>($tempreg)
6466 Otherwise, for local symbols, we want:
6467 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6468 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6469 assert (offset_expr
.X_op
== O_symbol
);
6470 frag_now
->tc_frag_data
.tc_fr_offset
=
6471 expr1
.X_add_number
= offset_expr
.X_add_number
;
6472 offset_expr
.X_add_number
= 0;
6473 if (expr1
.X_add_number
< -0x8000
6474 || expr1
.X_add_number
>= 0x8000)
6475 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6477 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6478 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6479 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6480 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
6481 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
6482 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6483 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6484 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
6487 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6488 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
6489 "d,v,t", tempreg
, tempreg
, breg
);
6490 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6491 (int) BFD_RELOC_LO16
, tempreg
);
6493 offset_expr
.X_add_number
= expr1
.X_add_number
;
6494 p
= frag_var (rs_machine_dependent
, 12 + bregsz
, 0,
6495 RELAX_ENCODE (16 + bregsz
, 8 + bregsz
,
6496 0, 4 + bregsz
, 0, 0),
6497 offset_expr
.X_add_symbol
, 0, NULL
);
6498 macro_build (p
, &icnt
, &offset_expr
,
6499 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6501 (int) BFD_RELOC_MIPS_GOT_PAGE
,
6504 macro_build (p
+ 4, &icnt
, (expressionS
*) NULL
,
6505 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
6506 "d,v,t", tempreg
, tempreg
, breg
);
6507 macro_build (p
+ 4 + bregsz
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6508 (int) BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6510 else if (mips_pic
== EMBEDDED_PIC
)
6512 /* If there is no base register, we want
6513 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6514 If there is a base register, we want
6515 addu $tempreg,$breg,$gp
6516 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6518 assert (offset_expr
.X_op
== O_symbol
);
6521 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6522 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
6527 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6528 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6529 "d,v,t", tempreg
, breg
, mips_gp_register
);
6530 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6531 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6544 load_register (&icnt
, treg
, &imm_expr
, 0);
6548 load_register (&icnt
, treg
, &imm_expr
, 1);
6552 if (imm_expr
.X_op
== O_constant
)
6554 load_register (&icnt
, AT
, &imm_expr
, 0);
6555 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6556 "mtc1", "t,G", AT
, treg
);
6561 assert (offset_expr
.X_op
== O_symbol
6562 && strcmp (segment_name (S_GET_SEGMENT
6563 (offset_expr
.X_add_symbol
)),
6565 && offset_expr
.X_add_number
== 0);
6566 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6567 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6572 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6573 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6574 order 32 bits of the value and the low order 32 bits are either
6575 zero or in OFFSET_EXPR. */
6576 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6578 if (HAVE_64BIT_GPRS
)
6579 load_register (&icnt
, treg
, &imm_expr
, 1);
6584 if (target_big_endian
)
6596 load_register (&icnt
, hreg
, &imm_expr
, 0);
6599 if (offset_expr
.X_op
== O_absent
)
6600 move_register (&icnt
, lreg
, 0);
6603 assert (offset_expr
.X_op
== O_constant
);
6604 load_register (&icnt
, lreg
, &offset_expr
, 0);
6611 /* We know that sym is in the .rdata section. First we get the
6612 upper 16 bits of the address. */
6613 if (mips_pic
== NO_PIC
)
6615 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6617 else if (mips_pic
== SVR4_PIC
)
6619 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6620 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6621 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6624 else if (mips_pic
== EMBEDDED_PIC
)
6626 /* For embedded PIC we pick up the entire address off $gp in
6627 a single instruction. */
6628 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6629 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
6630 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
6631 offset_expr
.X_op
= O_constant
;
6632 offset_expr
.X_add_number
= 0;
6637 /* Now we load the register(s). */
6638 if (HAVE_64BIT_GPRS
)
6639 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
6640 treg
, (int) BFD_RELOC_LO16
, AT
);
6643 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6644 treg
, (int) BFD_RELOC_LO16
, AT
);
6647 /* FIXME: How in the world do we deal with the possible
6649 offset_expr
.X_add_number
+= 4;
6650 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6651 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
6655 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6656 does not become a variant frag. */
6657 frag_wane (frag_now
);
6663 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6664 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6665 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6666 the value and the low order 32 bits are either zero or in
6668 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6670 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6671 if (HAVE_64BIT_FPRS
)
6673 assert (HAVE_64BIT_GPRS
);
6674 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6675 "dmtc1", "t,S", AT
, treg
);
6679 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6680 "mtc1", "t,G", AT
, treg
+ 1);
6681 if (offset_expr
.X_op
== O_absent
)
6682 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6683 "mtc1", "t,G", 0, treg
);
6686 assert (offset_expr
.X_op
== O_constant
);
6687 load_register (&icnt
, AT
, &offset_expr
, 0);
6688 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6689 "mtc1", "t,G", AT
, treg
);
6695 assert (offset_expr
.X_op
== O_symbol
6696 && offset_expr
.X_add_number
== 0);
6697 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6698 if (strcmp (s
, ".lit8") == 0)
6700 if (mips_opts
.isa
!= ISA_MIPS1
)
6702 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6703 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6707 breg
= mips_gp_register
;
6708 r
= BFD_RELOC_MIPS_LITERAL
;
6713 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6714 if (mips_pic
== SVR4_PIC
)
6715 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6716 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6717 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6721 /* FIXME: This won't work for a 64 bit address. */
6722 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6725 if (mips_opts
.isa
!= ISA_MIPS1
)
6727 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6728 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6730 /* To avoid confusion in tc_gen_reloc, we must ensure
6731 that this does not become a variant frag. */
6732 frag_wane (frag_now
);
6743 if (mips_arch
== CPU_R4650
)
6745 as_bad (_("opcode not supported on this processor"));
6748 /* Even on a big endian machine $fn comes before $fn+1. We have
6749 to adjust when loading from memory. */
6752 assert (mips_opts
.isa
== ISA_MIPS1
);
6753 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6754 target_big_endian
? treg
+ 1 : treg
,
6756 /* FIXME: A possible overflow which I don't know how to deal
6758 offset_expr
.X_add_number
+= 4;
6759 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6760 target_big_endian
? treg
: treg
+ 1,
6763 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6764 does not become a variant frag. */
6765 frag_wane (frag_now
);
6774 * The MIPS assembler seems to check for X_add_number not
6775 * being double aligned and generating:
6778 * addiu at,at,%lo(foo+1)
6781 * But, the resulting address is the same after relocation so why
6782 * generate the extra instruction?
6784 if (mips_arch
== CPU_R4650
)
6786 as_bad (_("opcode not supported on this processor"));
6789 /* Itbl support may require additional care here. */
6791 if (mips_opts
.isa
!= ISA_MIPS1
)
6802 if (mips_arch
== CPU_R4650
)
6804 as_bad (_("opcode not supported on this processor"));
6808 if (mips_opts
.isa
!= ISA_MIPS1
)
6816 /* Itbl support may require additional care here. */
6821 if (HAVE_64BIT_GPRS
)
6832 if (HAVE_64BIT_GPRS
)
6842 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6843 loads for the case of doing a pair of loads to simulate an 'ld'.
6844 This is not currently done by the compiler, and assembly coders
6845 writing embedded-pic code can cope. */
6847 if (offset_expr
.X_op
!= O_symbol
6848 && offset_expr
.X_op
!= O_constant
)
6850 as_bad (_("expression too complex"));
6851 offset_expr
.X_op
= O_constant
;
6854 /* Even on a big endian machine $fn comes before $fn+1. We have
6855 to adjust when loading from memory. We set coproc if we must
6856 load $fn+1 first. */
6857 /* Itbl support may require additional care here. */
6858 if (! target_big_endian
)
6861 if (mips_pic
== NO_PIC
6862 || offset_expr
.X_op
== O_constant
)
6866 /* If this is a reference to a GP relative symbol, we want
6867 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6868 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6869 If we have a base register, we use this
6871 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6872 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6873 If this is not a GP relative symbol, we want
6874 lui $at,<sym> (BFD_RELOC_HI16_S)
6875 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6876 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6877 If there is a base register, we add it to $at after the
6878 lui instruction. If there is a constant, we always use
6880 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6881 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6893 tempreg
= mips_gp_register
;
6900 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6901 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
6902 ? "add" : "addu" : "daddu",
6903 "d,v,t", AT
, breg
, mips_gp_register
);
6909 /* Itbl support may require additional care here. */
6910 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6911 coproc
? treg
+ 1 : treg
,
6912 (int) BFD_RELOC_GPREL16
, tempreg
);
6913 offset_expr
.X_add_number
+= 4;
6915 /* Set mips_optimize to 2 to avoid inserting an
6917 hold_mips_optimize
= mips_optimize
;
6919 /* Itbl support may require additional care here. */
6920 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6921 coproc
? treg
: treg
+ 1,
6922 (int) BFD_RELOC_GPREL16
, tempreg
);
6923 mips_optimize
= hold_mips_optimize
;
6925 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6926 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6927 used_at
&& mips_opts
.noat
),
6928 offset_expr
.X_add_symbol
, 0, NULL
);
6930 /* We just generated two relocs. When tc_gen_reloc
6931 handles this case, it will skip the first reloc and
6932 handle the second. The second reloc already has an
6933 extra addend of 4, which we added above. We must
6934 subtract it out, and then subtract another 4 to make
6935 the first reloc come out right. The second reloc
6936 will come out right because we are going to add 4 to
6937 offset_expr when we build its instruction below.
6939 If we have a symbol, then we don't want to include
6940 the offset, because it will wind up being included
6941 when we generate the reloc. */
6943 if (offset_expr
.X_op
== O_constant
)
6944 offset_expr
.X_add_number
-= 8;
6947 offset_expr
.X_add_number
= -4;
6948 offset_expr
.X_op
= O_constant
;
6951 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6956 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6957 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
6958 ? "add" : "addu" : "daddu",
6959 "d,v,t", AT
, breg
, AT
);
6963 /* Itbl support may require additional care here. */
6964 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6965 coproc
? treg
+ 1 : treg
,
6966 (int) BFD_RELOC_LO16
, AT
);
6969 /* FIXME: How do we handle overflow here? */
6970 offset_expr
.X_add_number
+= 4;
6971 /* Itbl support may require additional care here. */
6972 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6973 coproc
? treg
: treg
+ 1,
6974 (int) BFD_RELOC_LO16
, AT
);
6976 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6980 /* If this is a reference to an external symbol, we want
6981 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6986 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6988 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6989 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6990 If there is a base register we add it to $at before the
6991 lwc1 instructions. If there is a constant we include it
6992 in the lwc1 instructions. */
6994 expr1
.X_add_number
= offset_expr
.X_add_number
;
6995 offset_expr
.X_add_number
= 0;
6996 if (expr1
.X_add_number
< -0x8000
6997 || expr1
.X_add_number
>= 0x8000 - 4)
6998 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7003 frag_grow (24 + off
);
7004 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
7005 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
7006 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7007 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7009 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7010 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
7011 ? "add" : "addu" : "daddu",
7012 "d,v,t", AT
, breg
, AT
);
7013 /* Itbl support may require additional care here. */
7014 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
7015 coproc
? treg
+ 1 : treg
,
7016 (int) BFD_RELOC_LO16
, AT
);
7017 expr1
.X_add_number
+= 4;
7019 /* Set mips_optimize to 2 to avoid inserting an undesired
7021 hold_mips_optimize
= mips_optimize
;
7023 /* Itbl support may require additional care here. */
7024 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
7025 coproc
? treg
: treg
+ 1,
7026 (int) BFD_RELOC_LO16
, AT
);
7027 mips_optimize
= hold_mips_optimize
;
7029 (void) frag_var (rs_machine_dependent
, 0, 0,
7030 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
7031 offset_expr
.X_add_symbol
, 0, NULL
);
7033 else if (mips_pic
== SVR4_PIC
)
7038 /* If this is a reference to an external symbol, we want
7039 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7041 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7046 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7048 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7049 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7050 If there is a base register we add it to $at before the
7051 lwc1 instructions. If there is a constant we include it
7052 in the lwc1 instructions. */
7054 expr1
.X_add_number
= offset_expr
.X_add_number
;
7055 offset_expr
.X_add_number
= 0;
7056 if (expr1
.X_add_number
< -0x8000
7057 || expr1
.X_add_number
>= 0x8000 - 4)
7058 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7059 if (reg_needs_delay (mips_gp_register
))
7068 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
7069 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
7070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7071 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
7072 ? "add" : "addu" : "daddu",
7073 "d,v,t", AT
, AT
, mips_gp_register
);
7074 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
7075 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
7076 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
7077 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7079 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7080 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
7081 ? "add" : "addu" : "daddu",
7082 "d,v,t", AT
, breg
, AT
);
7083 /* Itbl support may require additional care here. */
7084 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
7085 coproc
? treg
+ 1 : treg
,
7086 (int) BFD_RELOC_LO16
, AT
);
7087 expr1
.X_add_number
+= 4;
7089 /* Set mips_optimize to 2 to avoid inserting an undesired
7091 hold_mips_optimize
= mips_optimize
;
7093 /* Itbl support may require additional care here. */
7094 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
7095 coproc
? treg
: treg
+ 1,
7096 (int) BFD_RELOC_LO16
, AT
);
7097 mips_optimize
= hold_mips_optimize
;
7098 expr1
.X_add_number
-= 4;
7100 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
7101 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
7102 8 + gpdel
+ off
, 1, 0),
7103 offset_expr
.X_add_symbol
, 0, NULL
);
7106 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
7109 macro_build (p
, &icnt
, &offset_expr
,
7110 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
7111 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
7114 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
7118 macro_build (p
, &icnt
, (expressionS
*) NULL
,
7119 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
7120 ? "add" : "addu" : "daddu",
7121 "d,v,t", AT
, breg
, AT
);
7124 /* Itbl support may require additional care here. */
7125 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
7126 coproc
? treg
+ 1 : treg
,
7127 (int) BFD_RELOC_LO16
, AT
);
7129 expr1
.X_add_number
+= 4;
7131 /* Set mips_optimize to 2 to avoid inserting an undesired
7133 hold_mips_optimize
= mips_optimize
;
7135 /* Itbl support may require additional care here. */
7136 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
7137 coproc
? treg
: treg
+ 1,
7138 (int) BFD_RELOC_LO16
, AT
);
7139 mips_optimize
= hold_mips_optimize
;
7141 else if (mips_pic
== EMBEDDED_PIC
)
7143 /* If there is no base register, we use
7144 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7145 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7146 If we have a base register, we use
7148 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7149 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7153 tempreg
= mips_gp_register
;
7158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7159 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7160 "d,v,t", AT
, breg
, mips_gp_register
);
7165 /* Itbl support may require additional care here. */
7166 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
7167 coproc
? treg
+ 1 : treg
,
7168 (int) BFD_RELOC_GPREL16
, tempreg
);
7169 offset_expr
.X_add_number
+= 4;
7170 /* Itbl support may require additional care here. */
7171 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
7172 coproc
? treg
: treg
+ 1,
7173 (int) BFD_RELOC_GPREL16
, tempreg
);
7189 assert (HAVE_32BIT_ADDRESSES
);
7190 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7191 (int) BFD_RELOC_LO16
, breg
);
7192 offset_expr
.X_add_number
+= 4;
7193 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
7194 (int) BFD_RELOC_LO16
, breg
);
7197 /* New code added to support COPZ instructions.
7198 This code builds table entries out of the macros in mip_opcodes.
7199 R4000 uses interlocks to handle coproc delays.
7200 Other chips (like the R3000) require nops to be inserted for delays.
7202 FIXME: Currently, we require that the user handle delays.
7203 In order to fill delay slots for non-interlocked chips,
7204 we must have a way to specify delays based on the coprocessor.
7205 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7206 What are the side-effects of the cop instruction?
7207 What cache support might we have and what are its effects?
7208 Both coprocessor & memory require delays. how long???
7209 What registers are read/set/modified?
7211 If an itbl is provided to interpret cop instructions,
7212 this knowledge can be encoded in the itbl spec. */
7226 /* For now we just do C (same as Cz). The parameter will be
7227 stored in insn_opcode by mips_ip. */
7228 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
7233 move_register (&icnt
, dreg
, sreg
);
7236 #ifdef LOSING_COMPILER
7238 /* Try and see if this is a new itbl instruction.
7239 This code builds table entries out of the macros in mip_opcodes.
7240 FIXME: For now we just assemble the expression and pass it's
7241 value along as a 32-bit immediate.
7242 We may want to have the assembler assemble this value,
7243 so that we gain the assembler's knowledge of delay slots,
7245 Would it be more efficient to use mask (id) here? */
7246 if (itbl_have_entries
7247 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7249 s
= ip
->insn_mo
->name
;
7251 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7252 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
7259 as_warn (_("Macro used $at after \".set noat\""));
7264 struct mips_cl_insn
*ip
;
7266 register int treg
, sreg
, dreg
, breg
;
7282 bfd_reloc_code_real_type r
;
7285 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7286 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7287 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7288 mask
= ip
->insn_mo
->mask
;
7290 expr1
.X_op
= O_constant
;
7291 expr1
.X_op_symbol
= NULL
;
7292 expr1
.X_add_symbol
= NULL
;
7293 expr1
.X_add_number
= 1;
7297 #endif /* LOSING_COMPILER */
7302 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7303 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7311 /* The MIPS assembler some times generates shifts and adds. I'm
7312 not trying to be that fancy. GCC should do this for us
7314 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7315 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7316 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7331 mips_emit_delays (TRUE
);
7332 ++mips_opts
.noreorder
;
7333 mips_any_noreorder
= 1;
7335 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7337 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7338 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7340 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7341 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7342 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
7345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
7346 "s,t,q", dreg
, AT
, 6);
7349 expr1
.X_add_number
= 8;
7350 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
7352 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
7354 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7357 --mips_opts
.noreorder
;
7358 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
7371 mips_emit_delays (TRUE
);
7372 ++mips_opts
.noreorder
;
7373 mips_any_noreorder
= 1;
7375 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7376 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7377 dbl
? "dmultu" : "multu",
7378 "s,t", sreg
, imm
? AT
: treg
);
7379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
7381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7384 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
7388 expr1
.X_add_number
= 8;
7389 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
7390 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
7392 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7395 --mips_opts
.noreorder
;
7399 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7411 macro_build ((char *) NULL
, &icnt
, NULL
, "dnegu",
7412 "d,w", tempreg
, treg
);
7413 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
7414 "d,t,s", dreg
, sreg
, tempreg
);
7419 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
7420 "d,v,t", AT
, 0, treg
);
7421 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
7422 "d,t,s", AT
, sreg
, AT
);
7423 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
7424 "d,t,s", dreg
, sreg
, treg
);
7425 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7426 "d,v,t", dreg
, dreg
, AT
);
7430 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7442 macro_build ((char *) NULL
, &icnt
, NULL
, "negu",
7443 "d,w", tempreg
, treg
);
7444 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
7445 "d,t,s", dreg
, sreg
, tempreg
);
7450 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7451 "d,v,t", AT
, 0, treg
);
7452 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7453 "d,t,s", AT
, sreg
, AT
);
7454 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7455 "d,t,s", dreg
, sreg
, treg
);
7456 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7457 "d,v,t", dreg
, dreg
, AT
);
7465 if (imm_expr
.X_op
!= O_constant
)
7466 as_bad (_("Improper rotate count"));
7467 rot
= imm_expr
.X_add_number
& 0x3f;
7468 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7470 rot
= (64 - rot
) & 0x3f;
7472 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7473 "d,w,<", dreg
, sreg
, rot
- 32);
7475 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7476 "d,w,<", dreg
, sreg
, rot
);
7481 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7482 "d,w,<", dreg
, sreg
, 0);
7485 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7486 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7489 "d,w,<", AT
, sreg
, rot
);
7490 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7491 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7492 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7493 "d,v,t", dreg
, dreg
, AT
);
7501 if (imm_expr
.X_op
!= O_constant
)
7502 as_bad (_("Improper rotate count"));
7503 rot
= imm_expr
.X_add_number
& 0x1f;
7504 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7506 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7507 "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7512 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7513 "d,w,<", dreg
, sreg
, 0);
7516 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7517 "d,w,<", AT
, sreg
, rot
);
7518 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7519 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7520 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7521 "d,v,t", dreg
, dreg
, AT
);
7526 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7528 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
7529 "d,t,s", dreg
, sreg
, treg
);
7532 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
7533 "d,v,t", AT
, 0, treg
);
7534 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
7535 "d,t,s", AT
, sreg
, AT
);
7536 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
7537 "d,t,s", dreg
, sreg
, treg
);
7538 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7539 "d,v,t", dreg
, dreg
, AT
);
7543 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7545 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
7546 "d,t,s", dreg
, sreg
, treg
);
7549 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7550 "d,v,t", AT
, 0, treg
);
7551 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7552 "d,t,s", AT
, sreg
, AT
);
7553 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7554 "d,t,s", dreg
, sreg
, treg
);
7555 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7556 "d,v,t", dreg
, dreg
, AT
);
7564 if (imm_expr
.X_op
!= O_constant
)
7565 as_bad (_("Improper rotate count"));
7566 rot
= imm_expr
.X_add_number
& 0x3f;
7567 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7570 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7571 "d,w,<", dreg
, sreg
, rot
- 32);
7573 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7574 "d,w,<", dreg
, sreg
, rot
);
7579 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7580 "d,w,<", dreg
, sreg
, 0);
7583 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7584 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7586 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7587 "d,w,<", AT
, sreg
, rot
);
7588 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7589 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7590 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7591 "d,v,t", dreg
, dreg
, AT
);
7599 if (imm_expr
.X_op
!= O_constant
)
7600 as_bad (_("Improper rotate count"));
7601 rot
= imm_expr
.X_add_number
& 0x1f;
7602 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7604 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7605 "d,w,<", dreg
, sreg
, rot
);
7610 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7611 "d,w,<", dreg
, sreg
, 0);
7614 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7615 "d,w,<", AT
, sreg
, rot
);
7616 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7617 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7618 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7619 "d,v,t", dreg
, dreg
, AT
);
7624 if (mips_arch
== CPU_R4650
)
7626 as_bad (_("opcode not supported on this processor"));
7629 assert (mips_opts
.isa
== ISA_MIPS1
);
7630 /* Even on a big endian machine $fn comes before $fn+1. We have
7631 to adjust when storing to memory. */
7632 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7633 target_big_endian
? treg
+ 1 : treg
,
7634 (int) BFD_RELOC_LO16
, breg
);
7635 offset_expr
.X_add_number
+= 4;
7636 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7637 target_big_endian
? treg
: treg
+ 1,
7638 (int) BFD_RELOC_LO16
, breg
);
7643 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7644 treg
, (int) BFD_RELOC_LO16
);
7646 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7647 sreg
, (int) BFD_RELOC_LO16
);
7650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7651 "d,v,t", dreg
, sreg
, treg
);
7652 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7653 dreg
, (int) BFD_RELOC_LO16
);
7658 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7660 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7661 sreg
, (int) BFD_RELOC_LO16
);
7666 as_warn (_("Instruction %s: result is always false"),
7668 move_register (&icnt
, dreg
, 0);
7671 if (imm_expr
.X_op
== O_constant
7672 && imm_expr
.X_add_number
>= 0
7673 && imm_expr
.X_add_number
< 0x10000)
7675 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
7676 sreg
, (int) BFD_RELOC_LO16
);
7679 else if (imm_expr
.X_op
== O_constant
7680 && imm_expr
.X_add_number
> -0x8000
7681 && imm_expr
.X_add_number
< 0)
7683 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7684 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7685 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7686 "t,r,j", dreg
, sreg
,
7687 (int) BFD_RELOC_LO16
);
7692 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7693 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7694 "d,v,t", dreg
, sreg
, AT
);
7697 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7698 (int) BFD_RELOC_LO16
);
7703 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7709 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7711 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7712 (int) BFD_RELOC_LO16
);
7715 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7717 if (imm_expr
.X_op
== O_constant
7718 && imm_expr
.X_add_number
>= -0x8000
7719 && imm_expr
.X_add_number
< 0x8000)
7721 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7722 mask
== M_SGE_I
? "slti" : "sltiu",
7723 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7728 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7729 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7730 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
7734 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7735 (int) BFD_RELOC_LO16
);
7740 case M_SGT
: /* sreg > treg <==> treg < sreg */
7746 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7750 case M_SGT_I
: /* sreg > I <==> I < sreg */
7756 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7757 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7761 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7767 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7769 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7770 (int) BFD_RELOC_LO16
);
7773 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7779 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7780 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7782 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7783 (int) BFD_RELOC_LO16
);
7787 if (imm_expr
.X_op
== O_constant
7788 && imm_expr
.X_add_number
>= -0x8000
7789 && imm_expr
.X_add_number
< 0x8000)
7791 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7792 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7795 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7796 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7801 if (imm_expr
.X_op
== O_constant
7802 && imm_expr
.X_add_number
>= -0x8000
7803 && imm_expr
.X_add_number
< 0x8000)
7805 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7806 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7809 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7810 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7811 "d,v,t", dreg
, sreg
, AT
);
7816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7817 "d,v,t", dreg
, 0, treg
);
7819 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7820 "d,v,t", dreg
, 0, sreg
);
7823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7824 "d,v,t", dreg
, sreg
, treg
);
7825 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7826 "d,v,t", dreg
, 0, dreg
);
7831 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7833 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7834 "d,v,t", dreg
, 0, sreg
);
7839 as_warn (_("Instruction %s: result is always true"),
7841 macro_build ((char *) NULL
, &icnt
, &expr1
,
7842 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7843 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7846 if (imm_expr
.X_op
== O_constant
7847 && imm_expr
.X_add_number
>= 0
7848 && imm_expr
.X_add_number
< 0x10000)
7850 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7851 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7854 else if (imm_expr
.X_op
== O_constant
7855 && imm_expr
.X_add_number
> -0x8000
7856 && imm_expr
.X_add_number
< 0)
7858 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7859 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7860 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7861 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7866 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7867 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7868 "d,v,t", dreg
, sreg
, AT
);
7871 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7872 "d,v,t", dreg
, 0, dreg
);
7880 if (imm_expr
.X_op
== O_constant
7881 && imm_expr
.X_add_number
> -0x8000
7882 && imm_expr
.X_add_number
<= 0x8000)
7884 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7885 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7886 dbl
? "daddi" : "addi",
7887 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7890 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7891 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7892 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7898 if (imm_expr
.X_op
== O_constant
7899 && imm_expr
.X_add_number
> -0x8000
7900 && imm_expr
.X_add_number
<= 0x8000)
7902 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7903 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7904 dbl
? "daddiu" : "addiu",
7905 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7908 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7909 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7910 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7931 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7932 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7938 assert (mips_opts
.isa
== ISA_MIPS1
);
7939 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7940 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7943 * Is the double cfc1 instruction a bug in the mips assembler;
7944 * or is there a reason for it?
7946 mips_emit_delays (TRUE
);
7947 ++mips_opts
.noreorder
;
7948 mips_any_noreorder
= 1;
7949 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7951 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7953 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7954 expr1
.X_add_number
= 3;
7955 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7956 (int) BFD_RELOC_LO16
);
7957 expr1
.X_add_number
= 2;
7958 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7959 (int) BFD_RELOC_LO16
);
7960 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7962 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7963 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7964 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7965 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7967 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7968 --mips_opts
.noreorder
;
7977 if (offset_expr
.X_add_number
>= 0x7fff)
7978 as_bad (_("operand overflow"));
7979 if (! target_big_endian
)
7980 ++offset_expr
.X_add_number
;
7981 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", AT
,
7982 (int) BFD_RELOC_LO16
, breg
);
7983 if (! target_big_endian
)
7984 --offset_expr
.X_add_number
;
7986 ++offset_expr
.X_add_number
;
7987 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", treg
,
7988 (int) BFD_RELOC_LO16
, breg
);
7989 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7991 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
8005 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8006 as_bad (_("operand overflow"));
8011 if (! target_big_endian
)
8012 offset_expr
.X_add_number
+= off
;
8013 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", tempreg
,
8014 (int) BFD_RELOC_LO16
, breg
);
8015 if (! target_big_endian
)
8016 offset_expr
.X_add_number
-= off
;
8018 offset_expr
.X_add_number
+= off
;
8019 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", tempreg
,
8020 (int) BFD_RELOC_LO16
, breg
);
8022 /* If necessary, move the result in tempreg the final destination. */
8023 if (treg
== tempreg
)
8025 /* Protect second load's delay slot. */
8026 if (!gpr_interlocks
)
8027 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
8028 move_register (&icnt
, treg
, tempreg
);
8042 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
8044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8045 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
8046 ? "add" : "addu" : "daddu",
8047 "d,v,t", AT
, AT
, breg
);
8048 if (! target_big_endian
)
8049 expr1
.X_add_number
= off
;
8051 expr1
.X_add_number
= 0;
8052 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
8053 (int) BFD_RELOC_LO16
, AT
);
8054 if (! target_big_endian
)
8055 expr1
.X_add_number
= 0;
8057 expr1
.X_add_number
= off
;
8058 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
8059 (int) BFD_RELOC_LO16
, AT
);
8065 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
8067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8068 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
8069 ? "add" : "addu" : "daddu",
8070 "d,v,t", AT
, AT
, breg
);
8071 if (target_big_endian
)
8072 expr1
.X_add_number
= 0;
8073 macro_build ((char *) NULL
, &icnt
, &expr1
,
8074 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
8075 (int) BFD_RELOC_LO16
, AT
);
8076 if (target_big_endian
)
8077 expr1
.X_add_number
= 1;
8079 expr1
.X_add_number
= 0;
8080 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
8081 (int) BFD_RELOC_LO16
, AT
);
8082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
8084 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
8089 if (offset_expr
.X_add_number
>= 0x7fff)
8090 as_bad (_("operand overflow"));
8091 if (target_big_endian
)
8092 ++offset_expr
.X_add_number
;
8093 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
8094 (int) BFD_RELOC_LO16
, breg
);
8095 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
8097 if (target_big_endian
)
8098 --offset_expr
.X_add_number
;
8100 ++offset_expr
.X_add_number
;
8101 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
8102 (int) BFD_RELOC_LO16
, breg
);
8115 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8116 as_bad (_("operand overflow"));
8117 if (! target_big_endian
)
8118 offset_expr
.X_add_number
+= off
;
8119 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
8120 (int) BFD_RELOC_LO16
, breg
);
8121 if (! target_big_endian
)
8122 offset_expr
.X_add_number
-= off
;
8124 offset_expr
.X_add_number
+= off
;
8125 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
8126 (int) BFD_RELOC_LO16
, breg
);
8140 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
8142 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8143 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
8144 ? "add" : "addu" : "daddu",
8145 "d,v,t", AT
, AT
, breg
);
8146 if (! target_big_endian
)
8147 expr1
.X_add_number
= off
;
8149 expr1
.X_add_number
= 0;
8150 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
8151 (int) BFD_RELOC_LO16
, AT
);
8152 if (! target_big_endian
)
8153 expr1
.X_add_number
= 0;
8155 expr1
.X_add_number
= off
;
8156 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
8157 (int) BFD_RELOC_LO16
, AT
);
8162 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
8164 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8165 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
8166 ? "add" : "addu" : "daddu",
8167 "d,v,t", AT
, AT
, breg
);
8168 if (! target_big_endian
)
8169 expr1
.X_add_number
= 0;
8170 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
8171 (int) BFD_RELOC_LO16
, AT
);
8172 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
8174 if (! target_big_endian
)
8175 expr1
.X_add_number
= 1;
8177 expr1
.X_add_number
= 0;
8178 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
8179 (int) BFD_RELOC_LO16
, AT
);
8180 if (! target_big_endian
)
8181 expr1
.X_add_number
= 0;
8183 expr1
.X_add_number
= 1;
8184 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
8185 (int) BFD_RELOC_LO16
, AT
);
8186 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
8188 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
8193 /* FIXME: Check if this is one of the itbl macros, since they
8194 are added dynamically. */
8195 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8199 as_warn (_("Macro used $at after \".set noat\""));
8202 /* Implement macros in mips16 mode. */
8206 struct mips_cl_insn
*ip
;
8209 int xreg
, yreg
, zreg
, tmp
;
8213 const char *s
, *s2
, *s3
;
8215 mask
= ip
->insn_mo
->mask
;
8217 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
8218 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
8219 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
8223 expr1
.X_op
= O_constant
;
8224 expr1
.X_op_symbol
= NULL
;
8225 expr1
.X_add_symbol
= NULL
;
8226 expr1
.X_add_number
= 1;
8245 mips_emit_delays (TRUE
);
8246 ++mips_opts
.noreorder
;
8247 mips_any_noreorder
= 1;
8248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8249 dbl
? "ddiv" : "div",
8250 "0,x,y", xreg
, yreg
);
8251 expr1
.X_add_number
= 2;
8252 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
8253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
8256 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8257 since that causes an overflow. We should do that as well,
8258 but I don't see how to do the comparisons without a temporary
8260 --mips_opts
.noreorder
;
8261 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
8280 mips_emit_delays (TRUE
);
8281 ++mips_opts
.noreorder
;
8282 mips_any_noreorder
= 1;
8283 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
8285 expr1
.X_add_number
= 2;
8286 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
8287 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
8289 --mips_opts
.noreorder
;
8290 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
8296 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8297 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
8307 if (imm_expr
.X_op
!= O_constant
)
8308 as_bad (_("Unsupported large constant"));
8309 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8310 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
8311 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8315 if (imm_expr
.X_op
!= O_constant
)
8316 as_bad (_("Unsupported large constant"));
8317 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8318 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
8323 if (imm_expr
.X_op
!= O_constant
)
8324 as_bad (_("Unsupported large constant"));
8325 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8326 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
8349 goto do_reverse_branch
;
8353 goto do_reverse_branch
;
8365 goto do_reverse_branch
;
8376 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
8378 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
8405 goto do_addone_branch_i
;
8410 goto do_addone_branch_i
;
8425 goto do_addone_branch_i
;
8432 if (imm_expr
.X_op
!= O_constant
)
8433 as_bad (_("Unsupported large constant"));
8434 ++imm_expr
.X_add_number
;
8437 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
8438 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
8442 expr1
.X_add_number
= 0;
8443 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
8445 move_register (&icnt
, xreg
, yreg
);
8446 expr1
.X_add_number
= 2;
8447 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
8448 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8449 "neg", "x,w", xreg
, xreg
);
8453 /* For consistency checking, verify that all bits are specified either
8454 by the match/mask part of the instruction definition, or by the
8457 validate_mips_insn (opc
)
8458 const struct mips_opcode
*opc
;
8460 const char *p
= opc
->args
;
8462 unsigned long used_bits
= opc
->mask
;
8464 if ((used_bits
& opc
->match
) != opc
->match
)
8466 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8467 opc
->name
, opc
->args
);
8470 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8480 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8481 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8482 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8483 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8484 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8486 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8487 c
, opc
->name
, opc
->args
);
8491 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8492 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8494 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8495 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8496 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8497 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8499 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8500 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8502 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8503 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8505 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8506 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8507 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8508 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8509 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8510 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8511 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8512 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8513 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8514 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8515 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8516 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8517 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8518 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8519 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8520 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8521 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8523 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8524 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8525 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8526 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8528 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8529 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8530 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8531 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8532 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8533 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8534 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8535 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8536 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8539 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8540 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8541 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8542 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8543 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8547 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8548 c
, opc
->name
, opc
->args
);
8552 if (used_bits
!= 0xffffffff)
8554 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8555 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8561 /* This routine assembles an instruction into its binary format. As a
8562 side effect, it sets one of the global variables imm_reloc or
8563 offset_reloc to the type of relocation to do if one of the operands
8564 is an address expression. */
8569 struct mips_cl_insn
*ip
;
8574 struct mips_opcode
*insn
;
8577 unsigned int lastregno
= 0;
8578 unsigned int lastpos
= 0;
8579 unsigned int limlo
, limhi
;
8585 /* If the instruction contains a '.', we first try to match an instruction
8586 including the '.'. Then we try again without the '.'. */
8588 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8591 /* If we stopped on whitespace, then replace the whitespace with null for
8592 the call to hash_find. Save the character we replaced just in case we
8593 have to re-parse the instruction. */
8600 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8602 /* If we didn't find the instruction in the opcode table, try again, but
8603 this time with just the instruction up to, but not including the
8607 /* Restore the character we overwrite above (if any). */
8611 /* Scan up to the first '.' or whitespace. */
8613 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8617 /* If we did not find a '.', then we can quit now. */
8620 insn_error
= "unrecognized opcode";
8624 /* Lookup the instruction in the hash table. */
8626 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8628 insn_error
= "unrecognized opcode";
8638 assert (strcmp (insn
->name
, str
) == 0);
8640 if (OPCODE_IS_MEMBER (insn
,
8642 | (file_ase_mips16
? INSN_MIPS16
: 0)
8643 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8644 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8650 if (insn
->pinfo
!= INSN_MACRO
)
8652 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8658 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8659 && strcmp (insn
->name
, insn
[1].name
) == 0)
8668 static char buf
[100];
8669 if (mips_arch_info
->is_isa
)
8671 _("opcode not supported at this ISA level (%s)"),
8672 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8675 _("opcode not supported on this processor: %s (%s)"),
8676 mips_arch_info
->name
,
8677 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8687 ip
->insn_opcode
= insn
->match
;
8689 for (args
= insn
->args
;; ++args
)
8693 s
+= strspn (s
, " \t");
8697 case '\0': /* end of args */
8710 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8714 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8718 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8722 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8728 /* Handle optional base register.
8729 Either the base register is omitted or
8730 we must have a left paren. */
8731 /* This is dependent on the next operand specifier
8732 is a base register specification. */
8733 assert (args
[1] == 'b' || args
[1] == '5'
8734 || args
[1] == '-' || args
[1] == '4');
8738 case ')': /* these must match exactly */
8745 case '+': /* Opcode extension character. */
8748 case 'A': /* ins/ext position, becomes LSB. */
8751 my_getExpression (&imm_expr
, s
);
8752 check_absolute_expr (ip
, &imm_expr
);
8753 if ((unsigned long) imm_expr
.X_add_number
< limlo
8754 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8756 as_bad (_("Improper position (%lu)"),
8757 (unsigned long) imm_expr
.X_add_number
);
8758 imm_expr
.X_add_number
= limlo
;
8760 lastpos
= imm_expr
.X_add_number
;
8761 ip
->insn_opcode
|= (imm_expr
.X_add_number
8762 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8763 imm_expr
.X_op
= O_absent
;
8767 case 'B': /* ins size, becomes MSB. */
8770 my_getExpression (&imm_expr
, s
);
8771 check_absolute_expr (ip
, &imm_expr
);
8772 /* Check for negative input so that small negative numbers
8773 will not succeed incorrectly. The checks against
8774 (pos+size) transitively check "size" itself,
8775 assuming that "pos" is reasonable. */
8776 if ((long) imm_expr
.X_add_number
< 0
8777 || ((unsigned long) imm_expr
.X_add_number
8779 || ((unsigned long) imm_expr
.X_add_number
8782 as_bad (_("Improper insert size (%lu, position %lu)"),
8783 (unsigned long) imm_expr
.X_add_number
,
8784 (unsigned long) lastpos
);
8785 imm_expr
.X_add_number
= limlo
- lastpos
;
8787 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8788 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8789 imm_expr
.X_op
= O_absent
;
8793 case 'C': /* ext size, becomes MSBD. */
8796 my_getExpression (&imm_expr
, s
);
8797 check_absolute_expr (ip
, &imm_expr
);
8798 /* Check for negative input so that small negative numbers
8799 will not succeed incorrectly. The checks against
8800 (pos+size) transitively check "size" itself,
8801 assuming that "pos" is reasonable. */
8802 if ((long) imm_expr
.X_add_number
< 0
8803 || ((unsigned long) imm_expr
.X_add_number
8805 || ((unsigned long) imm_expr
.X_add_number
8808 as_bad (_("Improper extract size (%lu, position %lu)"),
8809 (unsigned long) imm_expr
.X_add_number
,
8810 (unsigned long) lastpos
);
8811 imm_expr
.X_add_number
= limlo
- lastpos
;
8813 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8814 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8815 imm_expr
.X_op
= O_absent
;
8820 /* +D is for disassembly only; never match. */
8824 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8825 *args
, insn
->name
, insn
->args
);
8826 /* Further processing is fruitless. */
8831 case '<': /* must be at least one digit */
8833 * According to the manual, if the shift amount is greater
8834 * than 31 or less than 0, then the shift amount should be
8835 * mod 32. In reality the mips assembler issues an error.
8836 * We issue a warning and mask out all but the low 5 bits.
8838 my_getExpression (&imm_expr
, s
);
8839 check_absolute_expr (ip
, &imm_expr
);
8840 if ((unsigned long) imm_expr
.X_add_number
> 31)
8842 as_warn (_("Improper shift amount (%lu)"),
8843 (unsigned long) imm_expr
.X_add_number
);
8844 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8846 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8847 imm_expr
.X_op
= O_absent
;
8851 case '>': /* shift amount minus 32 */
8852 my_getExpression (&imm_expr
, s
);
8853 check_absolute_expr (ip
, &imm_expr
);
8854 if ((unsigned long) imm_expr
.X_add_number
< 32
8855 || (unsigned long) imm_expr
.X_add_number
> 63)
8857 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8858 imm_expr
.X_op
= O_absent
;
8862 case 'k': /* cache code */
8863 case 'h': /* prefx code */
8864 my_getExpression (&imm_expr
, s
);
8865 check_absolute_expr (ip
, &imm_expr
);
8866 if ((unsigned long) imm_expr
.X_add_number
> 31)
8868 as_warn (_("Invalid value for `%s' (%lu)"),
8870 (unsigned long) imm_expr
.X_add_number
);
8871 imm_expr
.X_add_number
&= 0x1f;
8874 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8876 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8877 imm_expr
.X_op
= O_absent
;
8881 case 'c': /* break code */
8882 my_getExpression (&imm_expr
, s
);
8883 check_absolute_expr (ip
, &imm_expr
);
8884 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8886 as_warn (_("Illegal break code (%lu)"),
8887 (unsigned long) imm_expr
.X_add_number
);
8888 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8890 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8891 imm_expr
.X_op
= O_absent
;
8895 case 'q': /* lower break code */
8896 my_getExpression (&imm_expr
, s
);
8897 check_absolute_expr (ip
, &imm_expr
);
8898 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8900 as_warn (_("Illegal lower break code (%lu)"),
8901 (unsigned long) imm_expr
.X_add_number
);
8902 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8904 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8905 imm_expr
.X_op
= O_absent
;
8909 case 'B': /* 20-bit syscall/break code. */
8910 my_getExpression (&imm_expr
, s
);
8911 check_absolute_expr (ip
, &imm_expr
);
8912 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8913 as_warn (_("Illegal 20-bit code (%lu)"),
8914 (unsigned long) imm_expr
.X_add_number
);
8915 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8916 imm_expr
.X_op
= O_absent
;
8920 case 'C': /* Coprocessor code */
8921 my_getExpression (&imm_expr
, s
);
8922 check_absolute_expr (ip
, &imm_expr
);
8923 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8925 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8926 (unsigned long) imm_expr
.X_add_number
);
8927 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8929 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8930 imm_expr
.X_op
= O_absent
;
8934 case 'J': /* 19-bit wait code. */
8935 my_getExpression (&imm_expr
, s
);
8936 check_absolute_expr (ip
, &imm_expr
);
8937 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8938 as_warn (_("Illegal 19-bit code (%lu)"),
8939 (unsigned long) imm_expr
.X_add_number
);
8940 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8941 imm_expr
.X_op
= O_absent
;
8945 case 'P': /* Performance register */
8946 my_getExpression (&imm_expr
, s
);
8947 check_absolute_expr (ip
, &imm_expr
);
8948 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8950 as_warn (_("Invalid performance register (%lu)"),
8951 (unsigned long) imm_expr
.X_add_number
);
8952 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8954 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8955 imm_expr
.X_op
= O_absent
;
8959 case 'b': /* base register */
8960 case 'd': /* destination register */
8961 case 's': /* source register */
8962 case 't': /* target register */
8963 case 'r': /* both target and source */
8964 case 'v': /* both dest and source */
8965 case 'w': /* both dest and target */
8966 case 'E': /* coprocessor target register */
8967 case 'G': /* coprocessor destination register */
8968 case 'K': /* 'rdhwr' destination register */
8969 case 'x': /* ignore register name */
8970 case 'z': /* must be zero register */
8971 case 'U': /* destination register (clo/clz). */
8986 while (ISDIGIT (*s
));
8988 as_bad (_("Invalid register number (%d)"), regno
);
8990 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8994 if (s
[1] == 'r' && s
[2] == 'a')
8999 else if (s
[1] == 'f' && s
[2] == 'p')
9004 else if (s
[1] == 's' && s
[2] == 'p')
9009 else if (s
[1] == 'g' && s
[2] == 'p')
9014 else if (s
[1] == 'a' && s
[2] == 't')
9019 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9024 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9029 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9034 else if (itbl_have_entries
)
9039 p
= s
+ 1; /* advance past '$' */
9040 n
= itbl_get_field (&p
); /* n is name */
9042 /* See if this is a register defined in an
9044 if (itbl_get_reg_val (n
, &r
))
9046 /* Get_field advances to the start of
9047 the next field, so we need to back
9048 rack to the end of the last field. */
9052 s
= strchr (s
, '\0');
9066 as_warn (_("Used $at without \".set noat\""));
9072 if (c
== 'r' || c
== 'v' || c
== 'w')
9079 /* 'z' only matches $0. */
9080 if (c
== 'z' && regno
!= 0)
9083 /* Now that we have assembled one operand, we use the args string
9084 * to figure out where it goes in the instruction. */
9091 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
9096 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
9099 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
9100 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
9105 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
9108 /* This case exists because on the r3000 trunc
9109 expands into a macro which requires a gp
9110 register. On the r6000 or r4000 it is
9111 assembled into a single instruction which
9112 ignores the register. Thus the insn version
9113 is MIPS_ISA2 and uses 'x', and the macro
9114 version is MIPS_ISA1 and uses 't'. */
9117 /* This case is for the div instruction, which
9118 acts differently if the destination argument
9119 is $0. This only matches $0, and is checked
9120 outside the switch. */
9123 /* Itbl operand; not yet implemented. FIXME ?? */
9125 /* What about all other operands like 'i', which
9126 can be specified in the opcode table? */
9136 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
9139 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
9144 case 'O': /* MDMX alignment immediate constant. */
9145 my_getExpression (&imm_expr
, s
);
9146 check_absolute_expr (ip
, &imm_expr
);
9147 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9149 as_warn ("Improper align amount (%ld), using low bits",
9150 (long) imm_expr
.X_add_number
);
9151 imm_expr
.X_add_number
&= OP_MASK_ALN
;
9153 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
9154 imm_expr
.X_op
= O_absent
;
9158 case 'Q': /* MDMX vector, element sel, or const. */
9161 /* MDMX Immediate. */
9162 my_getExpression (&imm_expr
, s
);
9163 check_absolute_expr (ip
, &imm_expr
);
9164 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9166 as_warn (_("Invalid MDMX Immediate (%ld)"),
9167 (long) imm_expr
.X_add_number
);
9168 imm_expr
.X_add_number
&= OP_MASK_FT
;
9170 imm_expr
.X_add_number
&= OP_MASK_FT
;
9171 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9172 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9174 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9175 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
9176 imm_expr
.X_op
= O_absent
;
9180 /* Not MDMX Immediate. Fall through. */
9181 case 'X': /* MDMX destination register. */
9182 case 'Y': /* MDMX source register. */
9183 case 'Z': /* MDMX target register. */
9185 case 'D': /* floating point destination register */
9186 case 'S': /* floating point source register */
9187 case 'T': /* floating point target register */
9188 case 'R': /* floating point source register */
9192 /* Accept $fN for FP and MDMX register numbers, and in
9193 addition accept $vN for MDMX register numbers. */
9194 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
9195 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
9206 while (ISDIGIT (*s
));
9209 as_bad (_("Invalid float register number (%d)"), regno
);
9211 if ((regno
& 1) != 0
9213 && ! (strcmp (str
, "mtc1") == 0
9214 || strcmp (str
, "mfc1") == 0
9215 || strcmp (str
, "lwc1") == 0
9216 || strcmp (str
, "swc1") == 0
9217 || strcmp (str
, "l.s") == 0
9218 || strcmp (str
, "s.s") == 0))
9219 as_warn (_("Float register should be even, was %d"),
9227 if (c
== 'V' || c
== 'W')
9238 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
9243 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
9246 /* This is like 'Z', but also needs to fix the MDMX
9247 vector/scalar select bits. Note that the
9248 scalar immediate case is handled above. */
9251 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9252 int max_el
= (is_qh
? 3 : 7);
9254 my_getExpression(&imm_expr
, s
);
9255 check_absolute_expr (ip
, &imm_expr
);
9257 if (imm_expr
.X_add_number
> max_el
)
9258 as_bad(_("Bad element selector %ld"),
9259 (long) imm_expr
.X_add_number
);
9260 imm_expr
.X_add_number
&= max_el
;
9261 ip
->insn_opcode
|= (imm_expr
.X_add_number
9265 as_warn(_("Expecting ']' found '%s'"), s
);
9271 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9272 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9275 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9282 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
9285 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
9295 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
9298 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
9304 my_getExpression (&imm_expr
, s
);
9305 if (imm_expr
.X_op
!= O_big
9306 && imm_expr
.X_op
!= O_constant
)
9307 insn_error
= _("absolute expression required");
9312 my_getExpression (&offset_expr
, s
);
9313 *imm_reloc
= BFD_RELOC_32
;
9326 unsigned char temp
[8];
9328 unsigned int length
;
9333 /* These only appear as the last operand in an
9334 instruction, and every instruction that accepts
9335 them in any variant accepts them in all variants.
9336 This means we don't have to worry about backing out
9337 any changes if the instruction does not match.
9339 The difference between them is the size of the
9340 floating point constant and where it goes. For 'F'
9341 and 'L' the constant is 64 bits; for 'f' and 'l' it
9342 is 32 bits. Where the constant is placed is based
9343 on how the MIPS assembler does things:
9346 f -- immediate value
9349 The .lit4 and .lit8 sections are only used if
9350 permitted by the -G argument.
9352 When generating embedded PIC code, we use the
9353 .lit8 section but not the .lit4 section (we can do
9354 .lit4 inline easily; we need to put .lit8
9355 somewhere in the data segment, and using .lit8
9356 permits the linker to eventually combine identical
9359 The code below needs to know whether the target register
9360 is 32 or 64 bits wide. It relies on the fact 'f' and
9361 'F' are used with GPR-based instructions and 'l' and
9362 'L' are used with FPR-based instructions. */
9364 f64
= *args
== 'F' || *args
== 'L';
9365 using_gprs
= *args
== 'F' || *args
== 'f';
9367 save_in
= input_line_pointer
;
9368 input_line_pointer
= s
;
9369 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9371 s
= input_line_pointer
;
9372 input_line_pointer
= save_in
;
9373 if (err
!= NULL
&& *err
!= '\0')
9375 as_bad (_("Bad floating point constant: %s"), err
);
9376 memset (temp
, '\0', sizeof temp
);
9377 length
= f64
? 8 : 4;
9380 assert (length
== (unsigned) (f64
? 8 : 4));
9384 && (! USE_GLOBAL_POINTER_OPT
9385 || mips_pic
== EMBEDDED_PIC
9386 || g_switch_value
< 4
9387 || (temp
[0] == 0 && temp
[1] == 0)
9388 || (temp
[2] == 0 && temp
[3] == 0))))
9390 imm_expr
.X_op
= O_constant
;
9391 if (! target_big_endian
)
9392 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9394 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9397 && ! mips_disable_float_construction
9398 /* Constants can only be constructed in GPRs and
9399 copied to FPRs if the GPRs are at least as wide
9400 as the FPRs. Force the constant into memory if
9401 we are using 64-bit FPRs but the GPRs are only
9404 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9405 && ((temp
[0] == 0 && temp
[1] == 0)
9406 || (temp
[2] == 0 && temp
[3] == 0))
9407 && ((temp
[4] == 0 && temp
[5] == 0)
9408 || (temp
[6] == 0 && temp
[7] == 0)))
9410 /* The value is simple enough to load with a couple of
9411 instructions. If using 32-bit registers, set
9412 imm_expr to the high order 32 bits and offset_expr to
9413 the low order 32 bits. Otherwise, set imm_expr to
9414 the entire 64 bit constant. */
9415 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9417 imm_expr
.X_op
= O_constant
;
9418 offset_expr
.X_op
= O_constant
;
9419 if (! target_big_endian
)
9421 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9422 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9426 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9427 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9429 if (offset_expr
.X_add_number
== 0)
9430 offset_expr
.X_op
= O_absent
;
9432 else if (sizeof (imm_expr
.X_add_number
) > 4)
9434 imm_expr
.X_op
= O_constant
;
9435 if (! target_big_endian
)
9436 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9438 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9442 imm_expr
.X_op
= O_big
;
9443 imm_expr
.X_add_number
= 4;
9444 if (! target_big_endian
)
9446 generic_bignum
[0] = bfd_getl16 (temp
);
9447 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9448 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9449 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9453 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9454 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9455 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9456 generic_bignum
[3] = bfd_getb16 (temp
);
9462 const char *newname
;
9465 /* Switch to the right section. */
9467 subseg
= now_subseg
;
9470 default: /* unused default case avoids warnings. */
9472 newname
= RDATA_SECTION_NAME
;
9473 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
9474 || mips_pic
== EMBEDDED_PIC
)
9478 if (mips_pic
== EMBEDDED_PIC
)
9481 newname
= RDATA_SECTION_NAME
;
9484 assert (!USE_GLOBAL_POINTER_OPT
9485 || g_switch_value
>= 4);
9489 new_seg
= subseg_new (newname
, (subsegT
) 0);
9490 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9491 bfd_set_section_flags (stdoutput
, new_seg
,
9496 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9497 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9498 && strcmp (TARGET_OS
, "elf") != 0)
9499 record_alignment (new_seg
, 4);
9501 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9503 as_bad (_("Can't use floating point insn in this section"));
9505 /* Set the argument to the current address in the
9507 offset_expr
.X_op
= O_symbol
;
9508 offset_expr
.X_add_symbol
=
9509 symbol_new ("L0\001", now_seg
,
9510 (valueT
) frag_now_fix (), frag_now
);
9511 offset_expr
.X_add_number
= 0;
9513 /* Put the floating point number into the section. */
9514 p
= frag_more ((int) length
);
9515 memcpy (p
, temp
, length
);
9517 /* Switch back to the original section. */
9518 subseg_set (seg
, subseg
);
9523 case 'i': /* 16 bit unsigned immediate */
9524 case 'j': /* 16 bit signed immediate */
9525 *imm_reloc
= BFD_RELOC_LO16
;
9526 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9529 offsetT minval
, maxval
;
9531 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9532 && strcmp (insn
->name
, insn
[1].name
) == 0);
9534 /* If the expression was written as an unsigned number,
9535 only treat it as signed if there are no more
9539 && sizeof (imm_expr
.X_add_number
) <= 4
9540 && imm_expr
.X_op
== O_constant
9541 && imm_expr
.X_add_number
< 0
9542 && imm_expr
.X_unsigned
9546 /* For compatibility with older assemblers, we accept
9547 0x8000-0xffff as signed 16-bit numbers when only
9548 signed numbers are allowed. */
9550 minval
= 0, maxval
= 0xffff;
9552 minval
= -0x8000, maxval
= 0x7fff;
9554 minval
= -0x8000, maxval
= 0xffff;
9556 if (imm_expr
.X_op
!= O_constant
9557 || imm_expr
.X_add_number
< minval
9558 || imm_expr
.X_add_number
> maxval
)
9562 if (imm_expr
.X_op
== O_constant
9563 || imm_expr
.X_op
== O_big
)
9564 as_bad (_("expression out of range"));
9570 case 'o': /* 16 bit offset */
9571 /* Check whether there is only a single bracketed expression
9572 left. If so, it must be the base register and the
9573 constant must be zero. */
9574 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9576 offset_expr
.X_op
= O_constant
;
9577 offset_expr
.X_add_number
= 0;
9581 /* If this value won't fit into a 16 bit offset, then go
9582 find a macro that will generate the 32 bit offset
9584 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9585 && (offset_expr
.X_op
!= O_constant
9586 || offset_expr
.X_add_number
>= 0x8000
9587 || offset_expr
.X_add_number
< -0x8000))
9593 case 'p': /* pc relative offset */
9594 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9595 my_getExpression (&offset_expr
, s
);
9599 case 'u': /* upper 16 bits */
9600 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9601 && imm_expr
.X_op
== O_constant
9602 && (imm_expr
.X_add_number
< 0
9603 || imm_expr
.X_add_number
>= 0x10000))
9604 as_bad (_("lui expression not in range 0..65535"));
9608 case 'a': /* 26 bit address */
9609 my_getExpression (&offset_expr
, s
);
9611 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9614 case 'N': /* 3 bit branch condition code */
9615 case 'M': /* 3 bit compare condition code */
9616 if (strncmp (s
, "$fcc", 4) != 0)
9626 while (ISDIGIT (*s
));
9628 as_bad (_("invalid condition code register $fcc%d"), regno
);
9630 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9632 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9636 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9647 while (ISDIGIT (*s
));
9650 c
= 8; /* Invalid sel value. */
9653 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9654 ip
->insn_opcode
|= c
;
9658 /* Must be at least one digit. */
9659 my_getExpression (&imm_expr
, s
);
9660 check_absolute_expr (ip
, &imm_expr
);
9662 if ((unsigned long) imm_expr
.X_add_number
9663 > (unsigned long) OP_MASK_VECBYTE
)
9665 as_bad (_("bad byte vector index (%ld)"),
9666 (long) imm_expr
.X_add_number
);
9667 imm_expr
.X_add_number
= 0;
9670 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9671 imm_expr
.X_op
= O_absent
;
9676 my_getExpression (&imm_expr
, s
);
9677 check_absolute_expr (ip
, &imm_expr
);
9679 if ((unsigned long) imm_expr
.X_add_number
9680 > (unsigned long) OP_MASK_VECALIGN
)
9682 as_bad (_("bad byte vector index (%ld)"),
9683 (long) imm_expr
.X_add_number
);
9684 imm_expr
.X_add_number
= 0;
9687 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9688 imm_expr
.X_op
= O_absent
;
9693 as_bad (_("bad char = '%c'\n"), *args
);
9698 /* Args don't match. */
9699 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9700 !strcmp (insn
->name
, insn
[1].name
))
9704 insn_error
= _("illegal operands");
9709 insn_error
= _("illegal operands");
9714 /* This routine assembles an instruction into its binary format when
9715 assembling for the mips16. As a side effect, it sets one of the
9716 global variables imm_reloc or offset_reloc to the type of
9717 relocation to do if one of the operands is an address expression.
9718 It also sets mips16_small and mips16_ext if the user explicitly
9719 requested a small or extended instruction. */
9724 struct mips_cl_insn
*ip
;
9728 struct mips_opcode
*insn
;
9731 unsigned int lastregno
= 0;
9736 mips16_small
= FALSE
;
9739 for (s
= str
; ISLOWER (*s
); ++s
)
9751 if (s
[1] == 't' && s
[2] == ' ')
9754 mips16_small
= TRUE
;
9758 else if (s
[1] == 'e' && s
[2] == ' ')
9767 insn_error
= _("unknown opcode");
9771 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9772 mips16_small
= TRUE
;
9774 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9776 insn_error
= _("unrecognized opcode");
9783 assert (strcmp (insn
->name
, str
) == 0);
9786 ip
->insn_opcode
= insn
->match
;
9787 ip
->use_extend
= FALSE
;
9788 imm_expr
.X_op
= O_absent
;
9789 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9790 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9791 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9792 offset_expr
.X_op
= O_absent
;
9793 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9794 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9795 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9796 for (args
= insn
->args
; 1; ++args
)
9803 /* In this switch statement we call break if we did not find
9804 a match, continue if we did find a match, or return if we
9813 /* Stuff the immediate value in now, if we can. */
9814 if (imm_expr
.X_op
== O_constant
9815 && *imm_reloc
> BFD_RELOC_UNUSED
9816 && insn
->pinfo
!= INSN_MACRO
)
9818 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9819 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9820 mips16_ext
, &ip
->insn_opcode
,
9821 &ip
->use_extend
, &ip
->extend
);
9822 imm_expr
.X_op
= O_absent
;
9823 *imm_reloc
= BFD_RELOC_UNUSED
;
9837 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9840 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9856 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9858 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9885 while (ISDIGIT (*s
));
9888 as_bad (_("invalid register number (%d)"), regno
);
9894 if (s
[1] == 'r' && s
[2] == 'a')
9899 else if (s
[1] == 'f' && s
[2] == 'p')
9904 else if (s
[1] == 's' && s
[2] == 'p')
9909 else if (s
[1] == 'g' && s
[2] == 'p')
9914 else if (s
[1] == 'a' && s
[2] == 't')
9919 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9924 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9929 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9942 if (c
== 'v' || c
== 'w')
9944 regno
= mips16_to_32_reg_map
[lastregno
];
9958 regno
= mips32_to_16_reg_map
[regno
];
9963 regno
= ILLEGAL_REG
;
9968 regno
= ILLEGAL_REG
;
9973 regno
= ILLEGAL_REG
;
9978 if (regno
== AT
&& ! mips_opts
.noat
)
9979 as_warn (_("used $at without \".set noat\""));
9986 if (regno
== ILLEGAL_REG
)
9993 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9997 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
10000 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
10003 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
10009 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
10012 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10013 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
10023 if (strncmp (s
, "$pc", 3) == 0)
10047 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
10049 /* This is %gprel(SYMBOL). We need to read SYMBOL,
10050 and generate the appropriate reloc. If the text
10051 inside %gprel is not a symbol name with an
10052 optional offset, then we generate a normal reloc
10053 and will probably fail later. */
10054 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
10055 if (imm_expr
.X_op
== O_symbol
)
10058 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
10060 ip
->use_extend
= TRUE
;
10067 /* Just pick up a normal expression. */
10068 my_getExpression (&imm_expr
, s
);
10071 if (imm_expr
.X_op
== O_register
)
10073 /* What we thought was an expression turned out to
10076 if (s
[0] == '(' && args
[1] == '(')
10078 /* It looks like the expression was omitted
10079 before a register indirection, which means
10080 that the expression is implicitly zero. We
10081 still set up imm_expr, so that we handle
10082 explicit extensions correctly. */
10083 imm_expr
.X_op
= O_constant
;
10084 imm_expr
.X_add_number
= 0;
10085 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10092 /* We need to relax this instruction. */
10093 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10102 /* We use offset_reloc rather than imm_reloc for the PC
10103 relative operands. This lets macros with both
10104 immediate and address operands work correctly. */
10105 my_getExpression (&offset_expr
, s
);
10107 if (offset_expr
.X_op
== O_register
)
10110 /* We need to relax this instruction. */
10111 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10115 case '6': /* break code */
10116 my_getExpression (&imm_expr
, s
);
10117 check_absolute_expr (ip
, &imm_expr
);
10118 if ((unsigned long) imm_expr
.X_add_number
> 63)
10120 as_warn (_("Invalid value for `%s' (%lu)"),
10122 (unsigned long) imm_expr
.X_add_number
);
10123 imm_expr
.X_add_number
&= 0x3f;
10125 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
10126 imm_expr
.X_op
= O_absent
;
10130 case 'a': /* 26 bit address */
10131 my_getExpression (&offset_expr
, s
);
10133 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10134 ip
->insn_opcode
<<= 16;
10137 case 'l': /* register list for entry macro */
10138 case 'L': /* register list for exit macro */
10148 int freg
, reg1
, reg2
;
10150 while (*s
== ' ' || *s
== ',')
10154 as_bad (_("can't parse register list"));
10166 while (ISDIGIT (*s
))
10188 as_bad (_("invalid register list"));
10193 while (ISDIGIT (*s
))
10200 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10202 mask
&= ~ (7 << 3);
10205 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10207 mask
&= ~ (7 << 3);
10210 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10211 mask
|= (reg2
- 3) << 3;
10212 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10213 mask
|= (reg2
- 15) << 1;
10214 else if (reg1
== RA
&& reg2
== RA
)
10218 as_bad (_("invalid register list"));
10222 /* The mask is filled in in the opcode table for the
10223 benefit of the disassembler. We remove it before
10224 applying the actual mask. */
10225 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10226 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10230 case 'e': /* extend code */
10231 my_getExpression (&imm_expr
, s
);
10232 check_absolute_expr (ip
, &imm_expr
);
10233 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10235 as_warn (_("Invalid value for `%s' (%lu)"),
10237 (unsigned long) imm_expr
.X_add_number
);
10238 imm_expr
.X_add_number
&= 0x7ff;
10240 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10241 imm_expr
.X_op
= O_absent
;
10251 /* Args don't match. */
10252 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10253 strcmp (insn
->name
, insn
[1].name
) == 0)
10260 insn_error
= _("illegal operands");
10266 /* This structure holds information we know about a mips16 immediate
10269 struct mips16_immed_operand
10271 /* The type code used in the argument string in the opcode table. */
10273 /* The number of bits in the short form of the opcode. */
10275 /* The number of bits in the extended form of the opcode. */
10277 /* The amount by which the short form is shifted when it is used;
10278 for example, the sw instruction has a shift count of 2. */
10280 /* The amount by which the short form is shifted when it is stored
10281 into the instruction code. */
10283 /* Non-zero if the short form is unsigned. */
10285 /* Non-zero if the extended form is unsigned. */
10287 /* Non-zero if the value is PC relative. */
10291 /* The mips16 immediate operand types. */
10293 static const struct mips16_immed_operand mips16_immed_operands
[] =
10295 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10296 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10297 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10298 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10299 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10300 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10301 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10302 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10303 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10304 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10305 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10306 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10307 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10308 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10309 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10310 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10311 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10312 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10313 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10314 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10315 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10318 #define MIPS16_NUM_IMMED \
10319 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10321 /* Handle a mips16 instruction with an immediate value. This or's the
10322 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10323 whether an extended value is needed; if one is needed, it sets
10324 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10325 If SMALL is true, an unextended opcode was explicitly requested.
10326 If EXT is true, an extended opcode was explicitly requested. If
10327 WARN is true, warn if EXT does not match reality. */
10330 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
10339 unsigned long *insn
;
10340 bfd_boolean
*use_extend
;
10341 unsigned short *extend
;
10343 register const struct mips16_immed_operand
*op
;
10344 int mintiny
, maxtiny
;
10345 bfd_boolean needext
;
10347 op
= mips16_immed_operands
;
10348 while (op
->type
!= type
)
10351 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10356 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10359 maxtiny
= 1 << op
->nbits
;
10364 maxtiny
= (1 << op
->nbits
) - 1;
10369 mintiny
= - (1 << (op
->nbits
- 1));
10370 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10373 /* Branch offsets have an implicit 0 in the lowest bit. */
10374 if (type
== 'p' || type
== 'q')
10377 if ((val
& ((1 << op
->shift
) - 1)) != 0
10378 || val
< (mintiny
<< op
->shift
)
10379 || val
> (maxtiny
<< op
->shift
))
10384 if (warn
&& ext
&& ! needext
)
10385 as_warn_where (file
, line
,
10386 _("extended operand requested but not required"));
10387 if (small
&& needext
)
10388 as_bad_where (file
, line
, _("invalid unextended operand value"));
10390 if (small
|| (! ext
&& ! needext
))
10394 *use_extend
= FALSE
;
10395 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10396 insnval
<<= op
->op_shift
;
10401 long minext
, maxext
;
10407 maxext
= (1 << op
->extbits
) - 1;
10411 minext
= - (1 << (op
->extbits
- 1));
10412 maxext
= (1 << (op
->extbits
- 1)) - 1;
10414 if (val
< minext
|| val
> maxext
)
10415 as_bad_where (file
, line
,
10416 _("operand value out of range for instruction"));
10418 *use_extend
= TRUE
;
10419 if (op
->extbits
== 16)
10421 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10424 else if (op
->extbits
== 15)
10426 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10431 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10435 *extend
= (unsigned short) extval
;
10440 static const struct percent_op_match
10443 bfd_reloc_code_real_type reloc
;
10446 {"%lo", BFD_RELOC_LO16
},
10448 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10449 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10450 {"%call16", BFD_RELOC_MIPS_CALL16
},
10451 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10452 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10453 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10454 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10455 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10456 {"%got", BFD_RELOC_MIPS_GOT16
},
10457 {"%gp_rel", BFD_RELOC_GPREL16
},
10458 {"%half", BFD_RELOC_16
},
10459 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10460 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10461 {"%neg", BFD_RELOC_MIPS_SUB
},
10463 {"%hi", BFD_RELOC_HI16_S
}
10467 /* Return true if *STR points to a relocation operator. When returning true,
10468 move *STR over the operator and store its relocation code in *RELOC.
10469 Leave both *STR and *RELOC alone when returning false. */
10472 parse_relocation (str
, reloc
)
10474 bfd_reloc_code_real_type
*reloc
;
10478 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
10479 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10481 *str
+= strlen (percent_op
[i
].str
);
10482 *reloc
= percent_op
[i
].reloc
;
10484 /* Check whether the output BFD supports this relocation.
10485 If not, issue an error and fall back on something safe. */
10486 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10488 as_bad ("relocation %s isn't supported by the current ABI",
10489 percent_op
[i
].str
);
10490 *reloc
= BFD_RELOC_LO16
;
10498 /* Parse string STR as a 16-bit relocatable operand. Store the
10499 expression in *EP and the relocations in the array starting
10500 at RELOC. Return the number of relocation operators used.
10502 On exit, EXPR_END points to the first character after the expression.
10503 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10506 my_getSmallExpression (ep
, reloc
, str
)
10508 bfd_reloc_code_real_type
*reloc
;
10511 bfd_reloc_code_real_type reversed_reloc
[3];
10512 size_t reloc_index
, i
;
10513 int crux_depth
, str_depth
;
10516 /* Search for the start of the main expression, recoding relocations
10517 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10518 of the main expression and with CRUX_DEPTH containing the number
10519 of open brackets at that point. */
10526 crux_depth
= str_depth
;
10528 /* Skip over whitespace and brackets, keeping count of the number
10530 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10535 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10536 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10538 my_getExpression (ep
, crux
);
10541 /* Match every open bracket. */
10542 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10546 if (crux_depth
> 0)
10547 as_bad ("unclosed '('");
10551 if (reloc_index
== 0)
10552 reloc
[0] = BFD_RELOC_LO16
;
10555 prev_reloc_op_frag
= frag_now
;
10556 for (i
= 0; i
< reloc_index
; i
++)
10557 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10560 return reloc_index
;
10564 my_getExpression (ep
, str
)
10571 save_in
= input_line_pointer
;
10572 input_line_pointer
= str
;
10574 expr_end
= input_line_pointer
;
10575 input_line_pointer
= save_in
;
10577 /* If we are in mips16 mode, and this is an expression based on `.',
10578 then we bump the value of the symbol by 1 since that is how other
10579 text symbols are handled. We don't bother to handle complex
10580 expressions, just `.' plus or minus a constant. */
10581 if (mips_opts
.mips16
10582 && ep
->X_op
== O_symbol
10583 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10584 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10585 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10586 && symbol_constant_p (ep
->X_add_symbol
)
10587 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10588 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10591 /* Turn a string in input_line_pointer into a floating point constant
10592 of type TYPE, and store the appropriate bytes in *LITP. The number
10593 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10594 returned, or NULL on OK. */
10597 md_atof (type
, litP
, sizeP
)
10603 LITTLENUM_TYPE words
[4];
10619 return _("bad call to md_atof");
10622 t
= atof_ieee (input_line_pointer
, type
, words
);
10624 input_line_pointer
= t
;
10628 if (! target_big_endian
)
10630 for (i
= prec
- 1; i
>= 0; i
--)
10632 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10638 for (i
= 0; i
< prec
; i
++)
10640 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10649 md_number_to_chars (buf
, val
, n
)
10654 if (target_big_endian
)
10655 number_to_chars_bigendian (buf
, val
, n
);
10657 number_to_chars_littleendian (buf
, val
, n
);
10661 static int support_64bit_objects(void)
10663 const char **list
, **l
;
10666 list
= bfd_target_list ();
10667 for (l
= list
; *l
!= NULL
; l
++)
10669 /* This is traditional mips */
10670 if (strcmp (*l
, "elf64-tradbigmips") == 0
10671 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10673 if (strcmp (*l
, "elf64-bigmips") == 0
10674 || strcmp (*l
, "elf64-littlemips") == 0)
10677 yes
= (*l
!= NULL
);
10681 #endif /* OBJ_ELF */
10683 const char *md_shortopts
= "nO::g::G:";
10685 struct option md_longopts
[] =
10687 /* Options which specify architecture. */
10688 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10689 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10690 {"march", required_argument
, NULL
, OPTION_MARCH
},
10691 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10692 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10693 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10694 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10695 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10696 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10697 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10698 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10699 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10700 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10701 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10702 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10703 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10704 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10705 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10706 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10707 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10708 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10709 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10711 /* Options which specify Application Specific Extensions (ASEs). */
10712 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10)
10713 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10714 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10715 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10716 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10717 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10718 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10719 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10720 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10721 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10722 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10723 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10724 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10726 /* Old-style architecture options. Don't add more of these. */
10727 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10728 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10729 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10730 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10731 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10732 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10733 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10734 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10735 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10736 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10737 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10738 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10739 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10740 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10741 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10742 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10743 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10745 /* Options which enable bug fixes. */
10746 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10747 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10748 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10749 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10750 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10751 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10752 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10753 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10754 {"mfix-vr4122-bugs", no_argument
, NULL
, OPTION_FIX_VR4122
},
10755 {"no-mfix-vr4122-bugs", no_argument
, NULL
, OPTION_NO_FIX_VR4122
},
10757 /* Miscellaneous options. */
10758 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10759 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10760 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10761 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10762 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10763 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10764 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10765 {"break", no_argument
, NULL
, OPTION_BREAK
},
10766 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10767 #define OPTION_EB (OPTION_MISC_BASE + 3)
10768 {"EB", no_argument
, NULL
, OPTION_EB
},
10769 #define OPTION_EL (OPTION_MISC_BASE + 4)
10770 {"EL", no_argument
, NULL
, OPTION_EL
},
10771 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10772 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10773 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10774 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10775 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10776 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10777 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10778 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10779 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10780 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10781 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10782 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10783 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10784 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10785 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10786 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10788 /* ELF-specific options. */
10790 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10791 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10792 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10793 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10794 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10795 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10796 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10797 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10798 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10799 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10800 #define OPTION_32 (OPTION_ELF_BASE + 4)
10801 {"32", no_argument
, NULL
, OPTION_32
},
10802 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10803 {"n32", no_argument
, NULL
, OPTION_N32
},
10804 #define OPTION_64 (OPTION_ELF_BASE + 6)
10805 {"64", no_argument
, NULL
, OPTION_64
},
10806 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10807 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10808 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10809 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10810 #endif /* OBJ_ELF */
10812 {NULL
, no_argument
, NULL
, 0}
10814 size_t md_longopts_size
= sizeof (md_longopts
);
10816 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10817 NEW_VALUE. Warn if another value was already specified. Note:
10818 we have to defer parsing the -march and -mtune arguments in order
10819 to handle 'from-abi' correctly, since the ABI might be specified
10820 in a later argument. */
10823 mips_set_option_string (string_ptr
, new_value
)
10824 const char **string_ptr
, *new_value
;
10826 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10827 as_warn (_("A different %s was already specified, is now %s"),
10828 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10831 *string_ptr
= new_value
;
10835 md_parse_option (c
, arg
)
10841 case OPTION_CONSTRUCT_FLOATS
:
10842 mips_disable_float_construction
= 0;
10845 case OPTION_NO_CONSTRUCT_FLOATS
:
10846 mips_disable_float_construction
= 1;
10858 target_big_endian
= 1;
10862 target_big_endian
= 0;
10870 if (arg
&& arg
[1] == '0')
10880 mips_debug
= atoi (arg
);
10881 /* When the MIPS assembler sees -g or -g2, it does not do
10882 optimizations which limit full symbolic debugging. We take
10883 that to be equivalent to -O0. */
10884 if (mips_debug
== 2)
10889 file_mips_isa
= ISA_MIPS1
;
10893 file_mips_isa
= ISA_MIPS2
;
10897 file_mips_isa
= ISA_MIPS3
;
10901 file_mips_isa
= ISA_MIPS4
;
10905 file_mips_isa
= ISA_MIPS5
;
10908 case OPTION_MIPS32
:
10909 file_mips_isa
= ISA_MIPS32
;
10912 case OPTION_MIPS32R2
:
10913 file_mips_isa
= ISA_MIPS32R2
;
10916 case OPTION_MIPS64
:
10917 file_mips_isa
= ISA_MIPS64
;
10921 mips_set_option_string (&mips_tune_string
, arg
);
10925 mips_set_option_string (&mips_arch_string
, arg
);
10929 mips_set_option_string (&mips_arch_string
, "4650");
10930 mips_set_option_string (&mips_tune_string
, "4650");
10933 case OPTION_NO_M4650
:
10937 mips_set_option_string (&mips_arch_string
, "4010");
10938 mips_set_option_string (&mips_tune_string
, "4010");
10941 case OPTION_NO_M4010
:
10945 mips_set_option_string (&mips_arch_string
, "4100");
10946 mips_set_option_string (&mips_tune_string
, "4100");
10949 case OPTION_NO_M4100
:
10953 mips_set_option_string (&mips_arch_string
, "3900");
10954 mips_set_option_string (&mips_tune_string
, "3900");
10957 case OPTION_NO_M3900
:
10961 mips_opts
.ase_mdmx
= 1;
10964 case OPTION_NO_MDMX
:
10965 mips_opts
.ase_mdmx
= 0;
10968 case OPTION_MIPS16
:
10969 mips_opts
.mips16
= 1;
10970 mips_no_prev_insn (FALSE
);
10973 case OPTION_NO_MIPS16
:
10974 mips_opts
.mips16
= 0;
10975 mips_no_prev_insn (FALSE
);
10978 case OPTION_MIPS3D
:
10979 mips_opts
.ase_mips3d
= 1;
10982 case OPTION_NO_MIPS3D
:
10983 mips_opts
.ase_mips3d
= 0;
10986 case OPTION_MEMBEDDED_PIC
:
10987 mips_pic
= EMBEDDED_PIC
;
10988 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10990 as_bad (_("-G may not be used with embedded PIC code"));
10993 g_switch_value
= 0x7fffffff;
10996 case OPTION_FIX_VR4122
:
10997 mips_fix_4122_bugs
= 1;
11000 case OPTION_NO_FIX_VR4122
:
11001 mips_fix_4122_bugs
= 0;
11004 case OPTION_RELAX_BRANCH
:
11005 mips_relax_branch
= 1;
11008 case OPTION_NO_RELAX_BRANCH
:
11009 mips_relax_branch
= 0;
11013 /* When generating ELF code, we permit -KPIC and -call_shared to
11014 select SVR4_PIC, and -non_shared to select no PIC. This is
11015 intended to be compatible with Irix 5. */
11016 case OPTION_CALL_SHARED
:
11017 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11019 as_bad (_("-call_shared is supported only for ELF format"));
11022 mips_pic
= SVR4_PIC
;
11023 mips_abicalls
= TRUE
;
11024 if (g_switch_seen
&& g_switch_value
!= 0)
11026 as_bad (_("-G may not be used with SVR4 PIC code"));
11029 g_switch_value
= 0;
11032 case OPTION_NON_SHARED
:
11033 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11035 as_bad (_("-non_shared is supported only for ELF format"));
11039 mips_abicalls
= FALSE
;
11042 /* The -xgot option tells the assembler to use 32 offsets when
11043 accessing the got in SVR4_PIC mode. It is for Irix
11048 #endif /* OBJ_ELF */
11051 if (! USE_GLOBAL_POINTER_OPT
)
11053 as_bad (_("-G is not supported for this configuration"));
11056 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
11058 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
11062 g_switch_value
= atoi (arg
);
11067 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11070 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11072 as_bad (_("-32 is supported for ELF format only"));
11075 mips_abi
= O32_ABI
;
11079 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11081 as_bad (_("-n32 is supported for ELF format only"));
11084 mips_abi
= N32_ABI
;
11088 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11090 as_bad (_("-64 is supported for ELF format only"));
11093 mips_abi
= N64_ABI
;
11094 if (! support_64bit_objects())
11095 as_fatal (_("No compiled in support for 64 bit object file format"));
11097 #endif /* OBJ_ELF */
11100 file_mips_gp32
= 1;
11104 file_mips_gp32
= 0;
11108 file_mips_fp32
= 1;
11112 file_mips_fp32
= 0;
11117 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11119 as_bad (_("-mabi is supported for ELF format only"));
11122 if (strcmp (arg
, "32") == 0)
11123 mips_abi
= O32_ABI
;
11124 else if (strcmp (arg
, "o64") == 0)
11125 mips_abi
= O64_ABI
;
11126 else if (strcmp (arg
, "n32") == 0)
11127 mips_abi
= N32_ABI
;
11128 else if (strcmp (arg
, "64") == 0)
11130 mips_abi
= N64_ABI
;
11131 if (! support_64bit_objects())
11132 as_fatal (_("No compiled in support for 64 bit object file "
11135 else if (strcmp (arg
, "eabi") == 0)
11136 mips_abi
= EABI_ABI
;
11139 as_fatal (_("invalid abi -mabi=%s"), arg
);
11143 #endif /* OBJ_ELF */
11145 case OPTION_M7000_HILO_FIX
:
11146 mips_7000_hilo_fix
= TRUE
;
11149 case OPTION_MNO_7000_HILO_FIX
:
11150 mips_7000_hilo_fix
= FALSE
;
11154 case OPTION_MDEBUG
:
11155 mips_flag_mdebug
= TRUE
;
11158 case OPTION_NO_MDEBUG
:
11159 mips_flag_mdebug
= FALSE
;
11161 #endif /* OBJ_ELF */
11170 /* Set up globals to generate code for the ISA or processor
11171 described by INFO. */
11174 mips_set_architecture (info
)
11175 const struct mips_cpu_info
*info
;
11179 mips_arch_info
= info
;
11180 mips_arch
= info
->cpu
;
11181 mips_opts
.isa
= info
->isa
;
11186 /* Likewise for tuning. */
11189 mips_set_tune (info
)
11190 const struct mips_cpu_info
*info
;
11194 mips_tune_info
= info
;
11195 mips_tune
= info
->cpu
;
11201 mips_after_parse_args ()
11203 /* GP relative stuff not working for PE */
11204 if (strncmp (TARGET_OS
, "pe", 2) == 0
11205 && g_switch_value
!= 0)
11208 as_bad (_("-G not supported in this configuration."));
11209 g_switch_value
= 0;
11212 if (mips_abi
== NO_ABI
)
11213 mips_abi
= MIPS_DEFAULT_ABI
;
11215 /* The following code determines the architecture and register size.
11216 Similar code was added to GCC 3.3 (see override_options() in
11217 config/mips/mips.c). The GAS and GCC code should be kept in sync
11218 as much as possible. */
11220 if (mips_arch_string
!= 0)
11221 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
11223 if (mips_tune_string
!= 0)
11224 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
11226 if (file_mips_isa
!= ISA_UNKNOWN
)
11228 /* Handle -mipsN. At this point, file_mips_isa contains the
11229 ISA level specified by -mipsN, while mips_opts.isa contains
11230 the -march selection (if any). */
11231 if (mips_arch_info
!= 0)
11233 /* -march takes precedence over -mipsN, since it is more descriptive.
11234 There's no harm in specifying both as long as the ISA levels
11236 if (file_mips_isa
!= mips_opts
.isa
)
11237 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11238 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11239 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11242 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa
));
11245 if (mips_arch_info
== 0)
11246 mips_set_architecture (mips_parse_cpu ("default CPU",
11247 MIPS_CPU_STRING_DEFAULT
));
11249 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11250 as_bad ("-march=%s is not compatible with the selected ABI",
11251 mips_arch_info
->name
);
11253 /* Optimize for mips_arch, unless -mtune selects a different processor. */
11254 if (mips_tune_info
== 0)
11255 mips_set_tune (mips_arch_info
);
11257 if (file_mips_gp32
>= 0)
11259 /* The user specified the size of the integer registers. Make sure
11260 it agrees with the ABI and ISA. */
11261 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11262 as_bad (_("-mgp64 used with a 32-bit processor"));
11263 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11264 as_bad (_("-mgp32 used with a 64-bit ABI"));
11265 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11266 as_bad (_("-mgp64 used with a 32-bit ABI"));
11270 /* Infer the integer register size from the ABI and processor.
11271 Restrict ourselves to 32-bit registers if that's all the
11272 processor has, or if the ABI cannot handle 64-bit registers. */
11273 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11274 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11277 /* ??? GAS treats single-float processors as though they had 64-bit
11278 float registers (although it complains when double-precision
11279 instructions are used). As things stand, saying they have 32-bit
11280 registers would lead to spurious "register must be even" messages.
11281 So here we assume float registers are always the same size as
11282 integer ones, unless the user says otherwise. */
11283 if (file_mips_fp32
< 0)
11284 file_mips_fp32
= file_mips_gp32
;
11286 /* End of GCC-shared inference code. */
11288 /* ??? When do we want this flag to be set? Who uses it? */
11289 if (file_mips_gp32
== 1
11290 && mips_abi
== NO_ABI
11291 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11292 mips_32bitmode
= 1;
11294 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11295 as_bad (_("trap exception not supported at ISA 1"));
11297 /* If the selected architecture includes support for ASEs, enable
11298 generation of code for them. */
11299 if (mips_opts
.mips16
== -1)
11300 mips_opts
.mips16
= (CPU_HAS_MIPS16 (mips_arch
)) ? 1 : 0;
11301 if (mips_opts
.ase_mips3d
== -1)
11302 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (mips_arch
)) ? 1 : 0;
11303 if (mips_opts
.ase_mdmx
== -1)
11304 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (mips_arch
)) ? 1 : 0;
11306 file_mips_isa
= mips_opts
.isa
;
11307 file_ase_mips16
= mips_opts
.mips16
;
11308 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11309 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11310 mips_opts
.gp32
= file_mips_gp32
;
11311 mips_opts
.fp32
= file_mips_fp32
;
11313 if (mips_flag_mdebug
< 0)
11315 #ifdef OBJ_MAYBE_ECOFF
11316 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11317 mips_flag_mdebug
= 1;
11319 #endif /* OBJ_MAYBE_ECOFF */
11320 mips_flag_mdebug
= 0;
11325 mips_init_after_args ()
11327 /* initialize opcodes */
11328 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11329 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11333 md_pcrel_from (fixP
)
11336 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11337 switch (fixP
->fx_r_type
)
11339 case BFD_RELOC_16_PCREL_S2
:
11340 case BFD_RELOC_MIPS_JMP
:
11341 /* Return the address of the delay slot. */
11348 /* This is called before the symbol table is processed. In order to
11349 work with gcc when using mips-tfile, we must keep all local labels.
11350 However, in other cases, we want to discard them. If we were
11351 called with -g, but we didn't see any debugging information, it may
11352 mean that gcc is smuggling debugging information through to
11353 mips-tfile, in which case we must generate all local labels. */
11356 mips_frob_file_before_adjust ()
11358 #ifndef NO_ECOFF_DEBUGGING
11359 if (ECOFF_DEBUGGING
11361 && ! ecoff_debugging_seen
)
11362 flag_keep_locals
= 1;
11366 /* Sort any unmatched HI16_S relocs so that they immediately precede
11367 the corresponding LO reloc. This is called before md_apply_fix3 and
11368 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
11369 explicit use of the %hi modifier. */
11374 struct mips_hi_fixup
*l
;
11376 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11378 segment_info_type
*seginfo
;
11381 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11383 /* If a GOT16 relocation turns out to be against a global symbol,
11384 there isn't supposed to be a matching LO. */
11385 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11386 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11389 /* Check quickly whether the next fixup happens to be a matching %lo. */
11390 if (fixup_has_matching_lo_p (l
->fixp
))
11393 /* Look through the fixups for this segment for a matching %lo.
11394 When we find one, move the %hi just in front of it. We do
11395 this in two passes. In the first pass, we try to find a
11396 unique %lo. In the second pass, we permit multiple %hi
11397 relocs for a single %lo (this is a GNU extension). */
11398 seginfo
= seg_info (l
->seg
);
11399 for (pass
= 0; pass
< 2; pass
++)
11404 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
11406 /* Check whether this is a %lo fixup which matches l->fixp. */
11407 if (f
->fx_r_type
== BFD_RELOC_LO16
11408 && f
->fx_addsy
== l
->fixp
->fx_addsy
11409 && f
->fx_offset
== l
->fixp
->fx_offset
11412 || !reloc_needs_lo_p (prev
->fx_r_type
)
11413 || !fixup_has_matching_lo_p (prev
)))
11417 /* Move l->fixp before f. */
11418 for (pf
= &seginfo
->fix_root
;
11420 pf
= &(*pf
)->fx_next
)
11421 assert (*pf
!= NULL
);
11423 *pf
= l
->fixp
->fx_next
;
11425 l
->fixp
->fx_next
= f
;
11427 seginfo
->fix_root
= l
->fixp
;
11429 prev
->fx_next
= l
->fixp
;
11440 #if 0 /* GCC code motion plus incomplete dead code elimination
11441 can leave a %hi without a %lo. */
11443 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
11444 _("Unmatched %%hi reloc"));
11450 /* When generating embedded PIC code we need to use a special
11451 relocation to represent the difference of two symbols in the .text
11452 section (switch tables use a difference of this sort). See
11453 include/coff/mips.h for details. This macro checks whether this
11454 fixup requires the special reloc. */
11455 #define SWITCH_TABLE(fixp) \
11456 ((fixp)->fx_r_type == BFD_RELOC_32 \
11457 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11458 && (fixp)->fx_addsy != NULL \
11459 && (fixp)->fx_subsy != NULL \
11460 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11461 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11463 /* When generating embedded PIC code we must keep all PC relative
11464 relocations, in case the linker has to relax a call. We also need
11465 to keep relocations for switch table entries.
11467 We may have combined relocations without symbols in the N32/N64 ABI.
11468 We have to prevent gas from dropping them. */
11471 mips_force_relocation (fixp
)
11474 if (generic_force_reloc (fixp
))
11478 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11479 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11480 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11481 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11484 return (mips_pic
== EMBEDDED_PIC
11486 || SWITCH_TABLE (fixp
)
11487 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
11488 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
11491 /* This hook is called before a fix is simplified. We don't really
11492 decide whether to skip a fix here. Rather, we turn global symbols
11493 used as branch targets into local symbols, such that they undergo
11494 simplification. We can only do this if the symbol is defined and
11495 it is in the same section as the branch. If this doesn't hold, we
11496 emit a better error message than just saying the relocation is not
11497 valid for the selected object format.
11499 FIXP is the fix-up we're going to try to simplify, SEG is the
11500 segment in which the fix up occurs. The return value should be
11501 non-zero to indicate the fix-up is valid for further
11502 simplifications. */
11505 mips_validate_fix (fixP
, seg
)
11509 /* There's a lot of discussion on whether it should be possible to
11510 use R_MIPS_PC16 to represent branch relocations. The outcome
11511 seems to be that it can, but gas/bfd are very broken in creating
11512 RELA relocations for this, so for now we only accept branches to
11513 symbols in the same section. Anything else is of dubious value,
11514 since there's no guarantee that at link time the symbol would be
11515 in range. Even for branches to local symbols this is arguably
11516 wrong, since it we assume the symbol is not going to be
11517 overridden, which should be possible per ELF library semantics,
11518 but then, there isn't a dynamic relocation that could be used to
11519 this effect, and the target would likely be out of range as well.
11521 Unfortunately, it seems that there is too much code out there
11522 that relies on branches to symbols that are global to be resolved
11523 as if they were local, like the IRIX tools do, so we do it as
11524 well, but with a warning so that people are reminded to fix their
11525 code. If we ever get back to using R_MIPS_PC16 for branch
11526 targets, this entire block should go away (and probably the
11527 whole function). */
11529 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
11530 && (((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11531 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11532 && mips_pic
!= EMBEDDED_PIC
)
11533 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
11536 if (! S_IS_DEFINED (fixP
->fx_addsy
))
11538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11539 _("Cannot branch to undefined symbol."));
11540 /* Avoid any further errors about this fixup. */
11543 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11545 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11546 _("Cannot branch to symbol in another section."));
11549 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11551 symbolS
*sym
= fixP
->fx_addsy
;
11553 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11554 _("Pretending global symbol used as branch target is local."));
11556 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11557 S_GET_SEGMENT (sym
),
11559 symbol_get_frag (sym
));
11560 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11561 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11562 assert (symbol_resolved_p (sym
));
11563 symbol_mark_resolved (fixP
->fx_addsy
);
11572 mips_need_elf_addend_fixup (fixP
)
11575 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
11577 if (mips_pic
== EMBEDDED_PIC
11578 && S_IS_WEAK (fixP
->fx_addsy
))
11580 if (mips_pic
!= EMBEDDED_PIC
11581 && (S_IS_WEAK (fixP
->fx_addsy
)
11582 || S_IS_EXTERNAL (fixP
->fx_addsy
))
11583 && !S_IS_COMMON (fixP
->fx_addsy
))
11585 if (((bfd_get_section_flags (stdoutput
,
11586 S_GET_SEGMENT (fixP
->fx_addsy
))
11587 & (SEC_LINK_ONCE
| SEC_MERGE
)) != 0)
11588 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
11590 sizeof (".gnu.linkonce") - 1))
11596 /* Apply a fixup to the object file. */
11599 md_apply_fix3 (fixP
, valP
, seg
)
11602 segT seg ATTRIBUTE_UNUSED
;
11606 static int previous_fx_r_type
= 0;
11607 reloc_howto_type
*howto
;
11609 /* We ignore generic BFD relocations we don't know about. */
11610 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11614 assert (fixP
->fx_size
== 4
11615 || fixP
->fx_r_type
== BFD_RELOC_16
11616 || fixP
->fx_r_type
== BFD_RELOC_64
11617 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11618 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11619 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11620 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11622 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11624 /* If we aren't adjusting this fixup to be against the section
11625 symbol, we need to adjust the value. */
11627 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11629 if (mips_need_elf_addend_fixup (fixP
)
11630 && howto
->partial_inplace
11631 && fixP
->fx_r_type
!= BFD_RELOC_GPREL16
11632 && fixP
->fx_r_type
!= BFD_RELOC_GPREL32
11633 && fixP
->fx_r_type
!= BFD_RELOC_MIPS16_GPREL
)
11635 /* In this case, the bfd_install_relocation routine will
11636 incorrectly add the symbol value back in. We just want
11637 the addend to appear in the object file.
11639 The condition above used to include
11640 "&& (! fixP->fx_pcrel || howto->pcrel_offset)".
11642 However, howto can't be trusted here, because we
11643 might change the reloc type in tc_gen_reloc. We can
11644 check howto->partial_inplace because that conversion
11645 happens to preserve howto->partial_inplace; but it
11646 does not preserve howto->pcrel_offset. I've just
11647 eliminated the check, because all MIPS PC-relative
11648 relocations are marked howto->pcrel_offset.
11650 howto->pcrel_offset was originally added for
11651 R_MIPS_PC16, which is generated for code like
11660 *valP
-= S_GET_VALUE (fixP
->fx_addsy
);
11663 /* This code was generated using trial and error and so is
11664 fragile and not trustworthy. If you change it, you should
11665 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11666 they still pass. */
11667 if (fixP
->fx_pcrel
)
11669 *valP
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11671 /* BFD's REL handling, for MIPS, is _very_ weird.
11672 This gives the right results, but it can't possibly
11673 be the way things are supposed to work. */
11674 *valP
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11679 /* We are not done if this is a composite relocation to set up gp. */
11680 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11681 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11682 || (fixP
->fx_r_type
== BFD_RELOC_64
11683 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11684 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11685 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11686 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11687 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11689 previous_fx_r_type
= fixP
->fx_r_type
;
11691 switch (fixP
->fx_r_type
)
11693 case BFD_RELOC_MIPS_JMP
:
11694 case BFD_RELOC_MIPS_SHIFT5
:
11695 case BFD_RELOC_MIPS_SHIFT6
:
11696 case BFD_RELOC_MIPS_GOT_DISP
:
11697 case BFD_RELOC_MIPS_GOT_PAGE
:
11698 case BFD_RELOC_MIPS_GOT_OFST
:
11699 case BFD_RELOC_MIPS_SUB
:
11700 case BFD_RELOC_MIPS_INSERT_A
:
11701 case BFD_RELOC_MIPS_INSERT_B
:
11702 case BFD_RELOC_MIPS_DELETE
:
11703 case BFD_RELOC_MIPS_HIGHEST
:
11704 case BFD_RELOC_MIPS_HIGHER
:
11705 case BFD_RELOC_MIPS_SCN_DISP
:
11706 case BFD_RELOC_MIPS_REL16
:
11707 case BFD_RELOC_MIPS_RELGOT
:
11708 case BFD_RELOC_MIPS_JALR
:
11709 case BFD_RELOC_HI16
:
11710 case BFD_RELOC_HI16_S
:
11711 case BFD_RELOC_GPREL16
:
11712 case BFD_RELOC_MIPS_LITERAL
:
11713 case BFD_RELOC_MIPS_CALL16
:
11714 case BFD_RELOC_MIPS_GOT16
:
11715 case BFD_RELOC_GPREL32
:
11716 case BFD_RELOC_MIPS_GOT_HI16
:
11717 case BFD_RELOC_MIPS_GOT_LO16
:
11718 case BFD_RELOC_MIPS_CALL_HI16
:
11719 case BFD_RELOC_MIPS_CALL_LO16
:
11720 case BFD_RELOC_MIPS16_GPREL
:
11721 if (fixP
->fx_pcrel
)
11722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11723 _("Invalid PC relative reloc"));
11724 /* Nothing needed to do. The value comes from the reloc entry */
11727 case BFD_RELOC_MIPS16_JMP
:
11728 /* We currently always generate a reloc against a symbol, which
11729 means that we don't want an addend even if the symbol is
11734 case BFD_RELOC_PCREL_HI16_S
:
11735 /* The addend for this is tricky if it is internal, so we just
11736 do everything here rather than in bfd_install_relocation. */
11737 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& !fixP
->fx_done
)
11740 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11742 /* For an external symbol adjust by the address to make it
11743 pcrel_offset. We use the address of the RELLO reloc
11744 which follows this one. */
11745 *valP
+= (fixP
->fx_next
->fx_frag
->fr_address
11746 + fixP
->fx_next
->fx_where
);
11748 *valP
= ((*valP
+ 0x8000) >> 16) & 0xffff;
11749 if (target_big_endian
)
11751 md_number_to_chars ((char *) buf
, *valP
, 2);
11754 case BFD_RELOC_PCREL_LO16
:
11755 /* The addend for this is tricky if it is internal, so we just
11756 do everything here rather than in bfd_install_relocation. */
11757 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& !fixP
->fx_done
)
11760 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11761 *valP
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11762 if (target_big_endian
)
11764 md_number_to_chars ((char *) buf
, *valP
, 2);
11768 /* This is handled like BFD_RELOC_32, but we output a sign
11769 extended value if we are only 32 bits. */
11771 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11773 if (8 <= sizeof (valueT
))
11774 md_number_to_chars (buf
, *valP
, 8);
11779 if ((*valP
& 0x80000000) != 0)
11783 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11785 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11791 case BFD_RELOC_RVA
:
11793 /* If we are deleting this reloc entry, we must fill in the
11794 value now. This can happen if we have a .word which is not
11795 resolved when it appears but is later defined. We also need
11796 to fill in the value if this is an embedded PIC switch table
11799 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11800 md_number_to_chars (buf
, *valP
, 4);
11804 /* If we are deleting this reloc entry, we must fill in the
11806 assert (fixP
->fx_size
== 2);
11808 md_number_to_chars (buf
, *valP
, 2);
11811 case BFD_RELOC_LO16
:
11812 /* When handling an embedded PIC switch statement, we can wind
11813 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11816 if (*valP
+ 0x8000 > 0xffff)
11817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11818 _("relocation overflow"));
11819 if (target_big_endian
)
11821 md_number_to_chars ((char *) buf
, *valP
, 2);
11825 case BFD_RELOC_16_PCREL_S2
:
11826 if ((*valP
& 0x3) != 0)
11827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11828 _("Branch to odd address (%lx)"), (long) *valP
);
11831 * We need to save the bits in the instruction since fixup_segment()
11832 * might be deleting the relocation entry (i.e., a branch within
11833 * the current segment).
11835 if (! fixP
->fx_done
)
11838 /* update old instruction data */
11839 if (target_big_endian
)
11840 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11842 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11844 if (*valP
+ 0x20000 <= 0x3ffff)
11846 insn
|= (*valP
>> 2) & 0xffff;
11847 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11849 else if (mips_pic
== NO_PIC
11851 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11852 && (fixP
->fx_frag
->fr_address
11853 < text_section
->vma
+ text_section
->_raw_size
)
11854 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11855 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11856 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11858 /* The branch offset is too large. If this is an
11859 unconditional branch, and we are not generating PIC code,
11860 we can convert it to an absolute jump instruction. */
11861 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11862 insn
= 0x0c000000; /* jal */
11864 insn
= 0x08000000; /* j */
11865 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11867 fixP
->fx_addsy
= section_symbol (text_section
);
11868 *valP
+= md_pcrel_from (fixP
);
11869 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11873 /* If we got here, we have branch-relaxation disabled,
11874 and there's nothing we can do to fix this instruction
11875 without turning it into a longer sequence. */
11876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11877 _("Branch out of range"));
11881 case BFD_RELOC_VTABLE_INHERIT
:
11884 && !S_IS_DEFINED (fixP
->fx_addsy
)
11885 && !S_IS_WEAK (fixP
->fx_addsy
))
11886 S_SET_WEAK (fixP
->fx_addsy
);
11889 case BFD_RELOC_VTABLE_ENTRY
:
11897 /* Remember value for tc_gen_reloc. */
11898 fixP
->fx_addnumber
= *valP
;
11906 const struct mips_opcode
*p
;
11907 int treg
, sreg
, dreg
, shamt
;
11912 for (i
= 0; i
< NUMOPCODES
; ++i
)
11914 p
= &mips_opcodes
[i
];
11915 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11917 printf ("%08lx %s\t", oc
, p
->name
);
11918 treg
= (oc
>> 16) & 0x1f;
11919 sreg
= (oc
>> 21) & 0x1f;
11920 dreg
= (oc
>> 11) & 0x1f;
11921 shamt
= (oc
>> 6) & 0x1f;
11923 for (args
= p
->args
;; ++args
)
11934 printf ("%c", *args
);
11938 assert (treg
== sreg
);
11939 printf ("$%d,$%d", treg
, sreg
);
11944 printf ("$%d", dreg
);
11949 printf ("$%d", treg
);
11953 printf ("0x%x", treg
);
11958 printf ("$%d", sreg
);
11962 printf ("0x%08lx", oc
& 0x1ffffff);
11969 printf ("%d", imm
);
11974 printf ("$%d", shamt
);
11985 printf (_("%08lx UNDEFINED\n"), oc
);
11996 name
= input_line_pointer
;
11997 c
= get_symbol_end ();
11998 p
= (symbolS
*) symbol_find_or_make (name
);
11999 *input_line_pointer
= c
;
12003 /* Align the current frag to a given power of two. The MIPS assembler
12004 also automatically adjusts any preceding label. */
12007 mips_align (to
, fill
, label
)
12012 mips_emit_delays (FALSE
);
12013 frag_align (to
, fill
, 0);
12014 record_alignment (now_seg
, to
);
12017 assert (S_GET_SEGMENT (label
) == now_seg
);
12018 symbol_set_frag (label
, frag_now
);
12019 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12023 /* Align to a given power of two. .align 0 turns off the automatic
12024 alignment used by the data creating pseudo-ops. */
12028 int x ATTRIBUTE_UNUSED
;
12031 register long temp_fill
;
12032 long max_alignment
= 15;
12036 o Note that the assembler pulls down any immediately preceeding label
12037 to the aligned address.
12038 o It's not documented but auto alignment is reinstated by
12039 a .align pseudo instruction.
12040 o Note also that after auto alignment is turned off the mips assembler
12041 issues an error on attempt to assemble an improperly aligned data item.
12046 temp
= get_absolute_expression ();
12047 if (temp
> max_alignment
)
12048 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12051 as_warn (_("Alignment negative: 0 assumed."));
12054 if (*input_line_pointer
== ',')
12056 ++input_line_pointer
;
12057 temp_fill
= get_absolute_expression ();
12064 mips_align (temp
, (int) temp_fill
,
12065 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
12072 demand_empty_rest_of_line ();
12076 mips_flush_pending_output ()
12078 mips_emit_delays (FALSE
);
12079 mips_clear_insn_labels ();
12088 /* When generating embedded PIC code, we only use the .text, .lit8,
12089 .sdata and .sbss sections. We change the .data and .rdata
12090 pseudo-ops to use .sdata. */
12091 if (mips_pic
== EMBEDDED_PIC
12092 && (sec
== 'd' || sec
== 'r'))
12096 /* The ELF backend needs to know that we are changing sections, so
12097 that .previous works correctly. We could do something like check
12098 for an obj_section_change_hook macro, but that might be confusing
12099 as it would not be appropriate to use it in the section changing
12100 functions in read.c, since obj-elf.c intercepts those. FIXME:
12101 This should be cleaner, somehow. */
12102 obj_elf_section_change_hook ();
12105 mips_emit_delays (FALSE
);
12115 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12116 demand_empty_rest_of_line ();
12120 if (USE_GLOBAL_POINTER_OPT
)
12122 seg
= subseg_new (RDATA_SECTION_NAME
,
12123 (subsegT
) get_absolute_expression ());
12124 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12126 bfd_set_section_flags (stdoutput
, seg
,
12132 if (strcmp (TARGET_OS
, "elf") != 0)
12133 record_alignment (seg
, 4);
12135 demand_empty_rest_of_line ();
12139 as_bad (_("No read only data section in this object file format"));
12140 demand_empty_rest_of_line ();
12146 if (USE_GLOBAL_POINTER_OPT
)
12148 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12149 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12151 bfd_set_section_flags (stdoutput
, seg
,
12152 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
12154 if (strcmp (TARGET_OS
, "elf") != 0)
12155 record_alignment (seg
, 4);
12157 demand_empty_rest_of_line ();
12162 as_bad (_("Global pointers not supported; recompile -G 0"));
12163 demand_empty_rest_of_line ();
12172 s_change_section (ignore
)
12173 int ignore ATTRIBUTE_UNUSED
;
12176 char *section_name
;
12181 int section_entry_size
;
12182 int section_alignment
;
12184 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12187 section_name
= input_line_pointer
;
12188 c
= get_symbol_end ();
12190 next_c
= *(input_line_pointer
+ 1);
12192 /* Do we have .section Name<,"flags">? */
12193 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12195 /* just after name is now '\0'. */
12196 *input_line_pointer
= c
;
12197 input_line_pointer
= section_name
;
12198 obj_elf_section (ignore
);
12201 input_line_pointer
++;
12203 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12205 section_type
= get_absolute_expression ();
12208 if (*input_line_pointer
++ == ',')
12209 section_flag
= get_absolute_expression ();
12212 if (*input_line_pointer
++ == ',')
12213 section_entry_size
= get_absolute_expression ();
12215 section_entry_size
= 0;
12216 if (*input_line_pointer
++ == ',')
12217 section_alignment
= get_absolute_expression ();
12219 section_alignment
= 0;
12221 section_name
= xstrdup (section_name
);
12223 obj_elf_change_section (section_name
, section_type
, section_flag
,
12224 section_entry_size
, 0, 0, 0);
12226 if (now_seg
->name
!= section_name
)
12227 free (section_name
);
12228 #endif /* OBJ_ELF */
12232 mips_enable_auto_align ()
12243 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12244 mips_emit_delays (FALSE
);
12245 if (log_size
> 0 && auto_align
)
12246 mips_align (log_size
, 0, label
);
12247 mips_clear_insn_labels ();
12248 cons (1 << log_size
);
12252 s_float_cons (type
)
12257 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12259 mips_emit_delays (FALSE
);
12264 mips_align (3, 0, label
);
12266 mips_align (2, 0, label
);
12269 mips_clear_insn_labels ();
12274 /* Handle .globl. We need to override it because on Irix 5 you are
12277 where foo is an undefined symbol, to mean that foo should be
12278 considered to be the address of a function. */
12282 int x ATTRIBUTE_UNUSED
;
12289 name
= input_line_pointer
;
12290 c
= get_symbol_end ();
12291 symbolP
= symbol_find_or_make (name
);
12292 *input_line_pointer
= c
;
12293 SKIP_WHITESPACE ();
12295 /* On Irix 5, every global symbol that is not explicitly labelled as
12296 being a function is apparently labelled as being an object. */
12299 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12304 secname
= input_line_pointer
;
12305 c
= get_symbol_end ();
12306 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12308 as_bad (_("%s: no such section"), secname
);
12309 *input_line_pointer
= c
;
12311 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12312 flag
= BSF_FUNCTION
;
12315 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12317 S_SET_EXTERNAL (symbolP
);
12318 demand_empty_rest_of_line ();
12323 int x ATTRIBUTE_UNUSED
;
12328 opt
= input_line_pointer
;
12329 c
= get_symbol_end ();
12333 /* FIXME: What does this mean? */
12335 else if (strncmp (opt
, "pic", 3) == 0)
12339 i
= atoi (opt
+ 3);
12344 mips_pic
= SVR4_PIC
;
12345 mips_abicalls
= TRUE
;
12348 as_bad (_(".option pic%d not supported"), i
);
12350 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
12352 if (g_switch_seen
&& g_switch_value
!= 0)
12353 as_warn (_("-G may not be used with SVR4 PIC code"));
12354 g_switch_value
= 0;
12355 bfd_set_gp_size (stdoutput
, 0);
12359 as_warn (_("Unrecognized option \"%s\""), opt
);
12361 *input_line_pointer
= c
;
12362 demand_empty_rest_of_line ();
12365 /* This structure is used to hold a stack of .set values. */
12367 struct mips_option_stack
12369 struct mips_option_stack
*next
;
12370 struct mips_set_options options
;
12373 static struct mips_option_stack
*mips_opts_stack
;
12375 /* Handle the .set pseudo-op. */
12379 int x ATTRIBUTE_UNUSED
;
12381 char *name
= input_line_pointer
, ch
;
12383 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12384 ++input_line_pointer
;
12385 ch
= *input_line_pointer
;
12386 *input_line_pointer
= '\0';
12388 if (strcmp (name
, "reorder") == 0)
12390 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
12392 /* If we still have pending nops, we can discard them. The
12393 usual nop handling will insert any that are still
12395 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12396 * (mips_opts
.mips16
? 2 : 4));
12397 prev_nop_frag
= NULL
;
12399 mips_opts
.noreorder
= 0;
12401 else if (strcmp (name
, "noreorder") == 0)
12403 mips_emit_delays (TRUE
);
12404 mips_opts
.noreorder
= 1;
12405 mips_any_noreorder
= 1;
12407 else if (strcmp (name
, "at") == 0)
12409 mips_opts
.noat
= 0;
12411 else if (strcmp (name
, "noat") == 0)
12413 mips_opts
.noat
= 1;
12415 else if (strcmp (name
, "macro") == 0)
12417 mips_opts
.warn_about_macros
= 0;
12419 else if (strcmp (name
, "nomacro") == 0)
12421 if (mips_opts
.noreorder
== 0)
12422 as_bad (_("`noreorder' must be set before `nomacro'"));
12423 mips_opts
.warn_about_macros
= 1;
12425 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12427 mips_opts
.nomove
= 0;
12429 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12431 mips_opts
.nomove
= 1;
12433 else if (strcmp (name
, "bopt") == 0)
12435 mips_opts
.nobopt
= 0;
12437 else if (strcmp (name
, "nobopt") == 0)
12439 mips_opts
.nobopt
= 1;
12441 else if (strcmp (name
, "mips16") == 0
12442 || strcmp (name
, "MIPS-16") == 0)
12443 mips_opts
.mips16
= 1;
12444 else if (strcmp (name
, "nomips16") == 0
12445 || strcmp (name
, "noMIPS-16") == 0)
12446 mips_opts
.mips16
= 0;
12447 else if (strcmp (name
, "mips3d") == 0)
12448 mips_opts
.ase_mips3d
= 1;
12449 else if (strcmp (name
, "nomips3d") == 0)
12450 mips_opts
.ase_mips3d
= 0;
12451 else if (strcmp (name
, "mdmx") == 0)
12452 mips_opts
.ase_mdmx
= 1;
12453 else if (strcmp (name
, "nomdmx") == 0)
12454 mips_opts
.ase_mdmx
= 0;
12455 else if (strncmp (name
, "mips", 4) == 0)
12459 /* Permit the user to change the ISA on the fly. Needless to
12460 say, misuse can cause serious problems. */
12461 if (strcmp (name
, "mips0") == 0)
12464 mips_opts
.isa
= file_mips_isa
;
12466 else if (strcmp (name
, "mips1") == 0)
12467 mips_opts
.isa
= ISA_MIPS1
;
12468 else if (strcmp (name
, "mips2") == 0)
12469 mips_opts
.isa
= ISA_MIPS2
;
12470 else if (strcmp (name
, "mips3") == 0)
12471 mips_opts
.isa
= ISA_MIPS3
;
12472 else if (strcmp (name
, "mips4") == 0)
12473 mips_opts
.isa
= ISA_MIPS4
;
12474 else if (strcmp (name
, "mips5") == 0)
12475 mips_opts
.isa
= ISA_MIPS5
;
12476 else if (strcmp (name
, "mips32") == 0)
12477 mips_opts
.isa
= ISA_MIPS32
;
12478 else if (strcmp (name
, "mips32r2") == 0)
12479 mips_opts
.isa
= ISA_MIPS32R2
;
12480 else if (strcmp (name
, "mips64") == 0)
12481 mips_opts
.isa
= ISA_MIPS64
;
12483 as_bad (_("unknown ISA level %s"), name
+ 4);
12485 switch (mips_opts
.isa
)
12493 mips_opts
.gp32
= 1;
12494 mips_opts
.fp32
= 1;
12500 mips_opts
.gp32
= 0;
12501 mips_opts
.fp32
= 0;
12504 as_bad (_("unknown ISA level %s"), name
+ 4);
12509 mips_opts
.gp32
= file_mips_gp32
;
12510 mips_opts
.fp32
= file_mips_fp32
;
12513 else if (strcmp (name
, "autoextend") == 0)
12514 mips_opts
.noautoextend
= 0;
12515 else if (strcmp (name
, "noautoextend") == 0)
12516 mips_opts
.noautoextend
= 1;
12517 else if (strcmp (name
, "push") == 0)
12519 struct mips_option_stack
*s
;
12521 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12522 s
->next
= mips_opts_stack
;
12523 s
->options
= mips_opts
;
12524 mips_opts_stack
= s
;
12526 else if (strcmp (name
, "pop") == 0)
12528 struct mips_option_stack
*s
;
12530 s
= mips_opts_stack
;
12532 as_bad (_(".set pop with no .set push"));
12535 /* If we're changing the reorder mode we need to handle
12536 delay slots correctly. */
12537 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12538 mips_emit_delays (TRUE
);
12539 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12541 if (prev_nop_frag
!= NULL
)
12543 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12544 * (mips_opts
.mips16
? 2 : 4));
12545 prev_nop_frag
= NULL
;
12549 mips_opts
= s
->options
;
12550 mips_opts_stack
= s
->next
;
12556 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12558 *input_line_pointer
= ch
;
12559 demand_empty_rest_of_line ();
12562 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12563 .option pic2. It means to generate SVR4 PIC calls. */
12566 s_abicalls (ignore
)
12567 int ignore ATTRIBUTE_UNUSED
;
12569 mips_pic
= SVR4_PIC
;
12570 mips_abicalls
= TRUE
;
12571 if (USE_GLOBAL_POINTER_OPT
)
12573 if (g_switch_seen
&& g_switch_value
!= 0)
12574 as_warn (_("-G may not be used with SVR4 PIC code"));
12575 g_switch_value
= 0;
12577 bfd_set_gp_size (stdoutput
, 0);
12578 demand_empty_rest_of_line ();
12581 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12582 PIC code. It sets the $gp register for the function based on the
12583 function address, which is in the register named in the argument.
12584 This uses a relocation against _gp_disp, which is handled specially
12585 by the linker. The result is:
12586 lui $gp,%hi(_gp_disp)
12587 addiu $gp,$gp,%lo(_gp_disp)
12588 addu $gp,$gp,.cpload argument
12589 The .cpload argument is normally $25 == $t9. */
12593 int ignore ATTRIBUTE_UNUSED
;
12598 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12599 .cpload is ignored. */
12600 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12606 /* .cpload should be in a .set noreorder section. */
12607 if (mips_opts
.noreorder
== 0)
12608 as_warn (_(".cpload not in noreorder section"));
12610 ex
.X_op
= O_symbol
;
12611 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12612 ex
.X_op_symbol
= NULL
;
12613 ex
.X_add_number
= 0;
12615 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12616 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12618 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
12619 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
12620 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
12622 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
12623 mips_gp_register
, mips_gp_register
, tc_get_register (0));
12625 demand_empty_rest_of_line ();
12628 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12629 .cpsetup $reg1, offset|$reg2, label
12631 If offset is given, this results in:
12632 sd $gp, offset($sp)
12633 lui $gp, %hi(%neg(%gp_rel(label)))
12634 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12635 daddu $gp, $gp, $reg1
12637 If $reg2 is given, this results in:
12638 daddu $reg2, $gp, $0
12639 lui $gp, %hi(%neg(%gp_rel(label)))
12640 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12641 daddu $gp, $gp, $reg1
12642 $reg1 is normally $25 == $t9. */
12645 int ignore ATTRIBUTE_UNUSED
;
12647 expressionS ex_off
;
12648 expressionS ex_sym
;
12653 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12654 We also need NewABI support. */
12655 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12661 reg1
= tc_get_register (0);
12662 SKIP_WHITESPACE ();
12663 if (*input_line_pointer
!= ',')
12665 as_bad (_("missing argument separator ',' for .cpsetup"));
12669 ++input_line_pointer
;
12670 SKIP_WHITESPACE ();
12671 if (*input_line_pointer
== '$')
12673 mips_cpreturn_register
= tc_get_register (0);
12674 mips_cpreturn_offset
= -1;
12678 mips_cpreturn_offset
= get_absolute_expression ();
12679 mips_cpreturn_register
= -1;
12681 SKIP_WHITESPACE ();
12682 if (*input_line_pointer
!= ',')
12684 as_bad (_("missing argument separator ',' for .cpsetup"));
12688 ++input_line_pointer
;
12689 SKIP_WHITESPACE ();
12690 expression (&ex_sym
);
12692 if (mips_cpreturn_register
== -1)
12694 ex_off
.X_op
= O_constant
;
12695 ex_off
.X_add_symbol
= NULL
;
12696 ex_off
.X_op_symbol
= NULL
;
12697 ex_off
.X_add_number
= mips_cpreturn_offset
;
12699 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
12700 mips_gp_register
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
12703 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12704 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
12706 /* Ensure there's room for the next two instructions, so that `f'
12707 doesn't end up with an address in the wrong frag. */
12710 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
12711 (int) BFD_RELOC_GPREL16
);
12712 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12713 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12714 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12715 4, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12718 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
12719 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
12720 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12721 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12722 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12723 4, NULL
, 0, 0, BFD_RELOC_LO16
);
12725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12726 HAVE_64BIT_ADDRESSES
? "daddu" : "add", "d,v,t",
12727 mips_gp_register
, mips_gp_register
, reg1
);
12729 demand_empty_rest_of_line ();
12734 int ignore ATTRIBUTE_UNUSED
;
12736 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12737 .cplocal is ignored. */
12738 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12744 mips_gp_register
= tc_get_register (0);
12745 demand_empty_rest_of_line ();
12748 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12749 offset from $sp. The offset is remembered, and after making a PIC
12750 call $gp is restored from that location. */
12753 s_cprestore (ignore
)
12754 int ignore ATTRIBUTE_UNUSED
;
12759 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12760 .cprestore is ignored. */
12761 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12767 mips_cprestore_offset
= get_absolute_expression ();
12768 mips_cprestore_valid
= 1;
12770 ex
.X_op
= O_constant
;
12771 ex
.X_add_symbol
= NULL
;
12772 ex
.X_op_symbol
= NULL
;
12773 ex
.X_add_number
= mips_cprestore_offset
;
12775 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
,
12776 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
12777 mips_gp_register
, mips_frame_reg
);
12779 demand_empty_rest_of_line ();
12782 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12783 was given in the preceeding .gpsetup, it results in:
12784 ld $gp, offset($sp)
12786 If a register $reg2 was given there, it results in:
12787 daddiu $gp, $gp, $reg2
12790 s_cpreturn (ignore
)
12791 int ignore ATTRIBUTE_UNUSED
;
12796 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12797 We also need NewABI support. */
12798 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12804 if (mips_cpreturn_register
== -1)
12806 ex
.X_op
= O_constant
;
12807 ex
.X_add_symbol
= NULL
;
12808 ex
.X_op_symbol
= NULL
;
12809 ex
.X_add_number
= mips_cpreturn_offset
;
12811 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
12812 mips_gp_register
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
12815 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12816 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
12818 demand_empty_rest_of_line ();
12821 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12822 code. It sets the offset to use in gp_rel relocations. */
12826 int ignore ATTRIBUTE_UNUSED
;
12828 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12829 We also need NewABI support. */
12830 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12836 mips_gprel_offset
= get_absolute_expression ();
12838 demand_empty_rest_of_line ();
12841 /* Handle the .gpword pseudo-op. This is used when generating PIC
12842 code. It generates a 32 bit GP relative reloc. */
12846 int ignore ATTRIBUTE_UNUSED
;
12852 /* When not generating PIC code, this is treated as .word. */
12853 if (mips_pic
!= SVR4_PIC
)
12859 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12860 mips_emit_delays (TRUE
);
12862 mips_align (2, 0, label
);
12863 mips_clear_insn_labels ();
12867 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12869 as_bad (_("Unsupported use of .gpword"));
12870 ignore_rest_of_line ();
12874 md_number_to_chars (p
, (valueT
) 0, 4);
12875 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12876 BFD_RELOC_GPREL32
);
12878 demand_empty_rest_of_line ();
12883 int ignore ATTRIBUTE_UNUSED
;
12889 /* When not generating PIC code, this is treated as .dword. */
12890 if (mips_pic
!= SVR4_PIC
)
12896 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12897 mips_emit_delays (TRUE
);
12899 mips_align (3, 0, label
);
12900 mips_clear_insn_labels ();
12904 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12906 as_bad (_("Unsupported use of .gpdword"));
12907 ignore_rest_of_line ();
12911 md_number_to_chars (p
, (valueT
) 0, 8);
12912 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12913 BFD_RELOC_GPREL32
);
12915 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12916 ex
.X_op
= O_absent
;
12917 ex
.X_add_symbol
= 0;
12918 ex
.X_add_number
= 0;
12919 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12922 demand_empty_rest_of_line ();
12925 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12926 tables in SVR4 PIC code. */
12930 int ignore ATTRIBUTE_UNUSED
;
12935 /* This is ignored when not generating SVR4 PIC code. */
12936 if (mips_pic
!= SVR4_PIC
)
12942 /* Add $gp to the register named as an argument. */
12943 reg
= tc_get_register (0);
12944 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12945 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
? "add" : "addu" : "daddu",
12946 "d,v,t", reg
, reg
, mips_gp_register
);
12948 demand_empty_rest_of_line ();
12951 /* Handle the .insn pseudo-op. This marks instruction labels in
12952 mips16 mode. This permits the linker to handle them specially,
12953 such as generating jalx instructions when needed. We also make
12954 them odd for the duration of the assembly, in order to generate the
12955 right sort of code. We will make them even in the adjust_symtab
12956 routine, while leaving them marked. This is convenient for the
12957 debugger and the disassembler. The linker knows to make them odd
12962 int ignore ATTRIBUTE_UNUSED
;
12964 mips16_mark_labels ();
12966 demand_empty_rest_of_line ();
12969 /* Handle a .stabn directive. We need these in order to mark a label
12970 as being a mips16 text label correctly. Sometimes the compiler
12971 will emit a label, followed by a .stabn, and then switch sections.
12972 If the label and .stabn are in mips16 mode, then the label is
12973 really a mips16 text label. */
12980 mips16_mark_labels ();
12985 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12989 s_mips_weakext (ignore
)
12990 int ignore ATTRIBUTE_UNUSED
;
12997 name
= input_line_pointer
;
12998 c
= get_symbol_end ();
12999 symbolP
= symbol_find_or_make (name
);
13000 S_SET_WEAK (symbolP
);
13001 *input_line_pointer
= c
;
13003 SKIP_WHITESPACE ();
13005 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13007 if (S_IS_DEFINED (symbolP
))
13009 as_bad ("ignoring attempt to redefine symbol %s",
13010 S_GET_NAME (symbolP
));
13011 ignore_rest_of_line ();
13015 if (*input_line_pointer
== ',')
13017 ++input_line_pointer
;
13018 SKIP_WHITESPACE ();
13022 if (exp
.X_op
!= O_symbol
)
13024 as_bad ("bad .weakext directive");
13025 ignore_rest_of_line ();
13028 symbol_set_value_expression (symbolP
, &exp
);
13031 demand_empty_rest_of_line ();
13034 /* Parse a register string into a number. Called from the ECOFF code
13035 to parse .frame. The argument is non-zero if this is the frame
13036 register, so that we can record it in mips_frame_reg. */
13039 tc_get_register (frame
)
13044 SKIP_WHITESPACE ();
13045 if (*input_line_pointer
++ != '$')
13047 as_warn (_("expected `$'"));
13050 else if (ISDIGIT (*input_line_pointer
))
13052 reg
= get_absolute_expression ();
13053 if (reg
< 0 || reg
>= 32)
13055 as_warn (_("Bad register number"));
13061 if (strncmp (input_line_pointer
, "ra", 2) == 0)
13064 input_line_pointer
+= 2;
13066 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
13069 input_line_pointer
+= 2;
13071 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
13074 input_line_pointer
+= 2;
13076 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
13079 input_line_pointer
+= 2;
13081 else if (strncmp (input_line_pointer
, "at", 2) == 0)
13084 input_line_pointer
+= 2;
13086 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
13089 input_line_pointer
+= 3;
13091 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
13094 input_line_pointer
+= 3;
13096 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
13099 input_line_pointer
+= 4;
13103 as_warn (_("Unrecognized register name"));
13105 while (ISALNUM(*input_line_pointer
))
13106 input_line_pointer
++;
13111 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13112 mips_frame_reg_valid
= 1;
13113 mips_cprestore_valid
= 0;
13119 md_section_align (seg
, addr
)
13123 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13126 /* We don't need to align ELF sections to the full alignment.
13127 However, Irix 5 may prefer that we align them at least to a 16
13128 byte boundary. We don't bother to align the sections if we are
13129 targeted for an embedded system. */
13130 if (strcmp (TARGET_OS
, "elf") == 0)
13136 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13139 /* Utility routine, called from above as well. If called while the
13140 input file is still being read, it's only an approximation. (For
13141 example, a symbol may later become defined which appeared to be
13142 undefined earlier.) */
13145 nopic_need_relax (sym
, before_relaxing
)
13147 int before_relaxing
;
13152 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
13154 const char *symname
;
13157 /* Find out whether this symbol can be referenced off the $gp
13158 register. It can be if it is smaller than the -G size or if
13159 it is in the .sdata or .sbss section. Certain symbols can
13160 not be referenced off the $gp, although it appears as though
13162 symname
= S_GET_NAME (sym
);
13163 if (symname
!= (const char *) NULL
13164 && (strcmp (symname
, "eprol") == 0
13165 || strcmp (symname
, "etext") == 0
13166 || strcmp (symname
, "_gp") == 0
13167 || strcmp (symname
, "edata") == 0
13168 || strcmp (symname
, "_fbss") == 0
13169 || strcmp (symname
, "_fdata") == 0
13170 || strcmp (symname
, "_ftext") == 0
13171 || strcmp (symname
, "end") == 0
13172 || strcmp (symname
, "_gp_disp") == 0))
13174 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13176 #ifndef NO_ECOFF_DEBUGGING
13177 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13178 && (symbol_get_obj (sym
)->ecoff_extern_size
13179 <= g_switch_value
))
13181 /* We must defer this decision until after the whole
13182 file has been read, since there might be a .extern
13183 after the first use of this symbol. */
13184 || (before_relaxing
13185 #ifndef NO_ECOFF_DEBUGGING
13186 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13188 && S_GET_VALUE (sym
) == 0)
13189 || (S_GET_VALUE (sym
) != 0
13190 && S_GET_VALUE (sym
) <= g_switch_value
)))
13194 const char *segname
;
13196 segname
= segment_name (S_GET_SEGMENT (sym
));
13197 assert (strcmp (segname
, ".lit8") != 0
13198 && strcmp (segname
, ".lit4") != 0);
13199 change
= (strcmp (segname
, ".sdata") != 0
13200 && strcmp (segname
, ".sbss") != 0
13201 && strncmp (segname
, ".sdata.", 7) != 0
13202 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13207 /* We are not optimizing for the $gp register. */
13212 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13215 pic_need_relax (sym
, segtype
)
13220 bfd_boolean linkonce
;
13222 /* Handle the case of a symbol equated to another symbol. */
13223 while (symbol_equated_reloc_p (sym
))
13227 /* It's possible to get a loop here in a badly written
13229 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13235 symsec
= S_GET_SEGMENT (sym
);
13237 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13239 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
13241 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
13245 /* The GNU toolchain uses an extension for ELF: a section
13246 beginning with the magic string .gnu.linkonce is a linkonce
13248 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
13249 sizeof ".gnu.linkonce" - 1) == 0)
13253 /* This must duplicate the test in adjust_reloc_syms. */
13254 return (symsec
!= &bfd_und_section
13255 && symsec
!= &bfd_abs_section
13256 && ! bfd_is_com_section (symsec
)
13259 /* A global or weak symbol is treated as external. */
13260 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13261 || (! S_IS_WEAK (sym
)
13262 && (! S_IS_EXTERNAL (sym
)
13263 || mips_pic
== EMBEDDED_PIC
)))
13269 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13270 extended opcode. SEC is the section the frag is in. */
13273 mips16_extended_frag (fragp
, sec
, stretch
)
13279 register const struct mips16_immed_operand
*op
;
13281 int mintiny
, maxtiny
;
13285 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13287 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13290 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13291 op
= mips16_immed_operands
;
13292 while (op
->type
!= type
)
13295 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13300 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13303 maxtiny
= 1 << op
->nbits
;
13308 maxtiny
= (1 << op
->nbits
) - 1;
13313 mintiny
= - (1 << (op
->nbits
- 1));
13314 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13317 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13318 val
= S_GET_VALUE (fragp
->fr_symbol
);
13319 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13325 /* We won't have the section when we are called from
13326 mips_relax_frag. However, we will always have been called
13327 from md_estimate_size_before_relax first. If this is a
13328 branch to a different section, we mark it as such. If SEC is
13329 NULL, and the frag is not marked, then it must be a branch to
13330 the same section. */
13333 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13338 /* Must have been called from md_estimate_size_before_relax. */
13341 fragp
->fr_subtype
=
13342 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13344 /* FIXME: We should support this, and let the linker
13345 catch branches and loads that are out of range. */
13346 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13347 _("unsupported PC relative reference to different section"));
13351 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13352 /* Assume non-extended on the first relaxation pass.
13353 The address we have calculated will be bogus if this is
13354 a forward branch to another frag, as the forward frag
13355 will have fr_address == 0. */
13359 /* In this case, we know for sure that the symbol fragment is in
13360 the same section. If the relax_marker of the symbol fragment
13361 differs from the relax_marker of this fragment, we have not
13362 yet adjusted the symbol fragment fr_address. We want to add
13363 in STRETCH in order to get a better estimate of the address.
13364 This particularly matters because of the shift bits. */
13366 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13370 /* Adjust stretch for any alignment frag. Note that if have
13371 been expanding the earlier code, the symbol may be
13372 defined in what appears to be an earlier frag. FIXME:
13373 This doesn't handle the fr_subtype field, which specifies
13374 a maximum number of bytes to skip when doing an
13376 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13378 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13381 stretch
= - ((- stretch
)
13382 & ~ ((1 << (int) f
->fr_offset
) - 1));
13384 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13393 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13395 /* The base address rules are complicated. The base address of
13396 a branch is the following instruction. The base address of a
13397 PC relative load or add is the instruction itself, but if it
13398 is in a delay slot (in which case it can not be extended) use
13399 the address of the instruction whose delay slot it is in. */
13400 if (type
== 'p' || type
== 'q')
13404 /* If we are currently assuming that this frag should be
13405 extended, then, the current address is two bytes
13407 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13410 /* Ignore the low bit in the target, since it will be set
13411 for a text label. */
13412 if ((val
& 1) != 0)
13415 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13417 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13420 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13422 /* Branch offsets have an implicit 0 in the lowest bit. */
13423 if (type
== 'p' || type
== 'q')
13426 /* If any of the shifted bits are set, we must use an extended
13427 opcode. If the address depends on the size of this
13428 instruction, this can lead to a loop, so we arrange to always
13429 use an extended opcode. We only check this when we are in
13430 the main relaxation loop, when SEC is NULL. */
13431 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13433 fragp
->fr_subtype
=
13434 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13438 /* If we are about to mark a frag as extended because the value
13439 is precisely maxtiny + 1, then there is a chance of an
13440 infinite loop as in the following code:
13445 In this case when the la is extended, foo is 0x3fc bytes
13446 away, so the la can be shrunk, but then foo is 0x400 away, so
13447 the la must be extended. To avoid this loop, we mark the
13448 frag as extended if it was small, and is about to become
13449 extended with a value of maxtiny + 1. */
13450 if (val
== ((maxtiny
+ 1) << op
->shift
)
13451 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13454 fragp
->fr_subtype
=
13455 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13459 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13460 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13462 if ((val
& ((1 << op
->shift
) - 1)) != 0
13463 || val
< (mintiny
<< op
->shift
)
13464 || val
> (maxtiny
<< op
->shift
))
13470 /* Compute the length of a branch sequence, and adjust the
13471 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13472 worst-case length is computed, with UPDATE being used to indicate
13473 whether an unconditional (-1), branch-likely (+1) or regular (0)
13474 branch is to be computed. */
13476 relaxed_branch_length (fragp
, sec
, update
)
13481 bfd_boolean toofar
;
13485 && S_IS_DEFINED (fragp
->fr_symbol
)
13486 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13491 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13493 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13497 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13500 /* If the symbol is not defined or it's in a different segment,
13501 assume the user knows what's going on and emit a short
13507 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13509 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13510 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13511 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13517 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13520 if (mips_pic
!= NO_PIC
)
13522 /* Additional space for PIC loading of target address. */
13524 if (mips_opts
.isa
== ISA_MIPS1
)
13525 /* Additional space for $at-stabilizing nop. */
13529 /* If branch is conditional. */
13530 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13537 /* Estimate the size of a frag before relaxing. Unless this is the
13538 mips16, we are not really relaxing here, and the final size is
13539 encoded in the subtype information. For the mips16, we have to
13540 decide whether we are using an extended opcode or not. */
13543 md_estimate_size_before_relax (fragp
, segtype
)
13549 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13552 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13554 return fragp
->fr_var
;
13557 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13558 /* We don't want to modify the EXTENDED bit here; it might get us
13559 into infinite loops. We change it only in mips_relax_frag(). */
13560 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13562 if (mips_pic
== NO_PIC
)
13563 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13564 else if (mips_pic
== SVR4_PIC
)
13565 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13571 /* Record the offset to the first reloc in the fr_opcode field.
13572 This lets md_convert_frag and tc_gen_reloc know that the code
13573 must be expanded. */
13574 fragp
->fr_opcode
= (fragp
->fr_literal
13576 - RELAX_OLD (fragp
->fr_subtype
)
13577 + RELAX_RELOC1 (fragp
->fr_subtype
));
13578 /* FIXME: This really needs as_warn_where. */
13579 if (RELAX_WARN (fragp
->fr_subtype
))
13580 as_warn (_("AT used after \".set noat\" or macro used after "
13581 "\".set nomacro\""));
13583 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
13589 /* This is called to see whether a reloc against a defined symbol
13590 should be converted into a reloc against a section. Don't adjust
13591 MIPS16 jump relocations, so we don't have to worry about the format
13592 of the offset in the .o file. Don't adjust relocations against
13593 mips16 symbols, so that the linker can find them if it needs to set
13597 mips_fix_adjustable (fixp
)
13600 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13603 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13604 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13607 if (fixp
->fx_addsy
== NULL
)
13611 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13612 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13613 && fixp
->fx_subsy
== NULL
)
13620 /* Translate internal representation of relocation info to BFD target
13624 tc_gen_reloc (section
, fixp
)
13625 asection
*section ATTRIBUTE_UNUSED
;
13628 static arelent
*retval
[4];
13630 bfd_reloc_code_real_type code
;
13632 memset (retval
, 0, sizeof(retval
));
13633 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13634 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13635 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13636 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13638 if (mips_pic
== EMBEDDED_PIC
13639 && SWITCH_TABLE (fixp
))
13641 /* For a switch table entry we use a special reloc. The addend
13642 is actually the difference between the reloc address and the
13644 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13645 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13646 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13647 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13649 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
13651 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13652 reloc
->addend
= fixp
->fx_addnumber
;
13655 /* We use a special addend for an internal RELLO reloc. */
13656 if (symbol_section_p (fixp
->fx_addsy
))
13657 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13659 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13662 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13664 assert (fixp
->fx_next
!= NULL
13665 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13667 /* The reloc is relative to the RELLO; adjust the addend
13669 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13670 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
13673 /* We use a special addend for an internal RELHI reloc. */
13674 if (symbol_section_p (fixp
->fx_addsy
))
13675 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
13676 + fixp
->fx_next
->fx_where
13677 - S_GET_VALUE (fixp
->fx_subsy
));
13679 reloc
->addend
= (fixp
->fx_addnumber
13680 + fixp
->fx_next
->fx_frag
->fr_address
13681 + fixp
->fx_next
->fx_where
);
13684 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13685 reloc
->addend
= fixp
->fx_addnumber
;
13688 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
13689 /* A gruesome hack which is a result of the gruesome gas reloc
13691 reloc
->addend
= reloc
->address
;
13693 reloc
->addend
= -reloc
->address
;
13696 /* If this is a variant frag, we may need to adjust the existing
13697 reloc and generate a new one. */
13698 if (fixp
->fx_frag
->fr_opcode
!= NULL
13699 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13701 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_DISP
13703 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
13704 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
13705 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13706 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
13707 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13708 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
13713 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
13715 /* If this is not the last reloc in this frag, then we have two
13716 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13717 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13718 the second one handle all of them. */
13719 if (fixp
->fx_next
!= NULL
13720 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
13722 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13723 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
13724 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13725 && (fixp
->fx_next
->fx_r_type
13726 == BFD_RELOC_MIPS_GOT_LO16
))
13727 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13728 && (fixp
->fx_next
->fx_r_type
13729 == BFD_RELOC_MIPS_CALL_LO16
)));
13734 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
13735 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13736 reloc
->addend
+= fixp
->fx_frag
->tc_frag_data
.tc_fr_offset
;
13737 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
13738 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13739 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13740 reloc2
->address
= (reloc
->address
13741 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
13742 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
13743 reloc2
->addend
= fixp
->fx_addnumber
- S_GET_VALUE (fixp
->fx_addsy
)
13744 + fixp
->fx_frag
->tc_frag_data
.tc_fr_offset
;
13745 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
13746 assert (reloc2
->howto
!= NULL
);
13748 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
13752 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
13754 reloc3
->address
+= 4;
13757 if (mips_pic
== NO_PIC
)
13759 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
13760 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
13762 else if (mips_pic
== SVR4_PIC
)
13764 switch (fixp
->fx_r_type
)
13768 case BFD_RELOC_MIPS_GOT16
:
13770 case BFD_RELOC_MIPS_GOT_LO16
:
13771 case BFD_RELOC_MIPS_CALL_LO16
:
13774 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
13775 reloc2
->howto
= bfd_reloc_type_lookup
13776 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
13779 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13781 case BFD_RELOC_MIPS_CALL16
:
13782 case BFD_RELOC_MIPS_GOT_OFST
:
13783 case BFD_RELOC_MIPS_GOT_DISP
:
13786 /* It may seem nonsensical to relax GOT_DISP to
13787 GOT_DISP, but we're actually turning a GOT_DISP
13788 without offset into a GOT_DISP with an offset,
13789 getting rid of the separate addition, which we can
13790 do when the symbol is found to be local. */
13791 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
13795 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13803 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13804 entry to be used in the relocation's section offset. */
13805 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13807 reloc
->address
= reloc
->addend
;
13811 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13812 fixup_segment converted a non-PC relative reloc into a PC
13813 relative reloc. In such a case, we need to convert the reloc
13815 code
= fixp
->fx_r_type
;
13816 if (fixp
->fx_pcrel
)
13821 code
= BFD_RELOC_8_PCREL
;
13824 code
= BFD_RELOC_16_PCREL
;
13827 code
= BFD_RELOC_32_PCREL
;
13830 code
= BFD_RELOC_64_PCREL
;
13832 case BFD_RELOC_8_PCREL
:
13833 case BFD_RELOC_16_PCREL
:
13834 case BFD_RELOC_32_PCREL
:
13835 case BFD_RELOC_64_PCREL
:
13836 case BFD_RELOC_16_PCREL_S2
:
13837 case BFD_RELOC_PCREL_HI16_S
:
13838 case BFD_RELOC_PCREL_LO16
:
13841 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13842 _("Cannot make %s relocation PC relative"),
13843 bfd_get_reloc_code_name (code
));
13847 /* To support a PC relative reloc when generating embedded PIC code
13848 for ECOFF, we use a Cygnus extension. We check for that here to
13849 make sure that we don't let such a reloc escape normally. */
13850 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13851 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13852 && code
== BFD_RELOC_16_PCREL_S2
13853 && mips_pic
!= EMBEDDED_PIC
)
13854 reloc
->howto
= NULL
;
13856 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13858 if (reloc
->howto
== NULL
)
13860 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13861 _("Can not represent %s relocation in this object file format"),
13862 bfd_get_reloc_code_name (code
));
13869 /* Relax a machine dependent frag. This returns the amount by which
13870 the current size of the frag should change. */
13873 mips_relax_frag (sec
, fragp
, stretch
)
13878 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13880 offsetT old_var
= fragp
->fr_var
;
13882 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13884 return fragp
->fr_var
- old_var
;
13887 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13890 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13892 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13894 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13899 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13901 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13908 /* Convert a machine dependent frag. */
13911 md_convert_frag (abfd
, asec
, fragp
)
13912 bfd
*abfd ATTRIBUTE_UNUSED
;
13919 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13922 unsigned long insn
;
13926 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13928 if (target_big_endian
)
13929 insn
= bfd_getb32 (buf
);
13931 insn
= bfd_getl32 (buf
);
13933 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13935 /* We generate a fixup instead of applying it right now
13936 because, if there are linker relaxations, we're going to
13937 need the relocations. */
13938 exp
.X_op
= O_symbol
;
13939 exp
.X_add_symbol
= fragp
->fr_symbol
;
13940 exp
.X_add_number
= fragp
->fr_offset
;
13942 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13944 BFD_RELOC_16_PCREL_S2
);
13945 fixp
->fx_file
= fragp
->fr_file
;
13946 fixp
->fx_line
= fragp
->fr_line
;
13948 md_number_to_chars ((char *)buf
, insn
, 4);
13955 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13956 _("relaxed out-of-range branch into a jump"));
13958 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13961 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13963 /* Reverse the branch. */
13964 switch ((insn
>> 28) & 0xf)
13967 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13968 have the condition reversed by tweaking a single
13969 bit, and their opcodes all have 0x4???????. */
13970 assert ((insn
& 0xf1000000) == 0x41000000);
13971 insn
^= 0x00010000;
13975 /* bltz 0x04000000 bgez 0x04010000
13976 bltzal 0x04100000 bgezal 0x04110000 */
13977 assert ((insn
& 0xfc0e0000) == 0x04000000);
13978 insn
^= 0x00010000;
13982 /* beq 0x10000000 bne 0x14000000
13983 blez 0x18000000 bgtz 0x1c000000 */
13984 insn
^= 0x04000000;
13992 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13994 /* Clear the and-link bit. */
13995 assert ((insn
& 0xfc1c0000) == 0x04100000);
13997 /* bltzal 0x04100000 bgezal 0x04110000
13998 bltzall 0x04120000 bgezall 0x04130000 */
13999 insn
&= ~0x00100000;
14002 /* Branch over the branch (if the branch was likely) or the
14003 full jump (not likely case). Compute the offset from the
14004 current instruction to branch to. */
14005 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14009 /* How many bytes in instructions we've already emitted? */
14010 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14011 /* How many bytes in instructions from here to the end? */
14012 i
= fragp
->fr_var
- i
;
14014 /* Convert to instruction count. */
14016 /* Branch counts from the next instruction. */
14019 /* Branch over the jump. */
14020 md_number_to_chars ((char *)buf
, insn
, 4);
14024 md_number_to_chars ((char*)buf
, 0, 4);
14027 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14029 /* beql $0, $0, 2f */
14031 /* Compute the PC offset from the current instruction to
14032 the end of the variable frag. */
14033 /* How many bytes in instructions we've already emitted? */
14034 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14035 /* How many bytes in instructions from here to the end? */
14036 i
= fragp
->fr_var
- i
;
14037 /* Convert to instruction count. */
14039 /* Don't decrement i, because we want to branch over the
14043 md_number_to_chars ((char *)buf
, insn
, 4);
14046 md_number_to_chars ((char *)buf
, 0, 4);
14051 if (mips_pic
== NO_PIC
)
14054 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14055 ? 0x0c000000 : 0x08000000);
14056 exp
.X_op
= O_symbol
;
14057 exp
.X_add_symbol
= fragp
->fr_symbol
;
14058 exp
.X_add_number
= fragp
->fr_offset
;
14060 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14061 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
14062 fixp
->fx_file
= fragp
->fr_file
;
14063 fixp
->fx_line
= fragp
->fr_line
;
14065 md_number_to_chars ((char*)buf
, insn
, 4);
14070 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14071 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
14072 exp
.X_op
= O_symbol
;
14073 exp
.X_add_symbol
= fragp
->fr_symbol
;
14074 exp
.X_add_number
= fragp
->fr_offset
;
14076 if (fragp
->fr_offset
)
14078 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14079 exp
.X_add_number
= 0;
14082 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14083 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
14084 fixp
->fx_file
= fragp
->fr_file
;
14085 fixp
->fx_line
= fragp
->fr_line
;
14087 md_number_to_chars ((char*)buf
, insn
, 4);
14090 if (mips_opts
.isa
== ISA_MIPS1
)
14093 md_number_to_chars ((char*)buf
, 0, 4);
14097 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14098 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14100 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14101 4, &exp
, 0, BFD_RELOC_LO16
);
14102 fixp
->fx_file
= fragp
->fr_file
;
14103 fixp
->fx_line
= fragp
->fr_line
;
14105 md_number_to_chars ((char*)buf
, insn
, 4);
14109 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14114 md_number_to_chars ((char*)buf
, insn
, 4);
14119 assert (buf
== (bfd_byte
*)fragp
->fr_literal
14120 + fragp
->fr_fix
+ fragp
->fr_var
);
14122 fragp
->fr_fix
+= fragp
->fr_var
;
14127 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14130 register const struct mips16_immed_operand
*op
;
14131 bfd_boolean small
, ext
;
14134 unsigned long insn
;
14135 bfd_boolean use_extend
;
14136 unsigned short extend
;
14138 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14139 op
= mips16_immed_operands
;
14140 while (op
->type
!= type
)
14143 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14154 resolve_symbol_value (fragp
->fr_symbol
);
14155 val
= S_GET_VALUE (fragp
->fr_symbol
);
14160 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14162 /* The rules for the base address of a PC relative reloc are
14163 complicated; see mips16_extended_frag. */
14164 if (type
== 'p' || type
== 'q')
14169 /* Ignore the low bit in the target, since it will be
14170 set for a text label. */
14171 if ((val
& 1) != 0)
14174 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14176 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14179 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14182 /* Make sure the section winds up with the alignment we have
14185 record_alignment (asec
, op
->shift
);
14189 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14190 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14191 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14192 _("extended instruction in delay slot"));
14194 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14196 if (target_big_endian
)
14197 insn
= bfd_getb16 (buf
);
14199 insn
= bfd_getl16 (buf
);
14201 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14202 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14203 small
, ext
, &insn
, &use_extend
, &extend
);
14207 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14208 fragp
->fr_fix
+= 2;
14212 md_number_to_chars ((char *) buf
, insn
, 2);
14213 fragp
->fr_fix
+= 2;
14218 if (fragp
->fr_opcode
== NULL
)
14221 old
= RELAX_OLD (fragp
->fr_subtype
);
14222 new = RELAX_NEW (fragp
->fr_subtype
);
14223 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
14226 memmove (fixptr
- old
, fixptr
, new);
14228 fragp
->fr_fix
+= new - old
;
14234 /* This function is called after the relocs have been generated.
14235 We've been storing mips16 text labels as odd. Here we convert them
14236 back to even for the convenience of the debugger. */
14239 mips_frob_file_after_relocs ()
14242 unsigned int count
, i
;
14244 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
14247 syms
= bfd_get_outsymbols (stdoutput
);
14248 count
= bfd_get_symcount (stdoutput
);
14249 for (i
= 0; i
< count
; i
++, syms
++)
14251 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
14252 && ((*syms
)->value
& 1) != 0)
14254 (*syms
)->value
&= ~1;
14255 /* If the symbol has an odd size, it was probably computed
14256 incorrectly, so adjust that as well. */
14257 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14258 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14265 /* This function is called whenever a label is defined. It is used
14266 when handling branch delays; if a branch has a label, we assume we
14267 can not move it. */
14270 mips_define_label (sym
)
14273 struct insn_label_list
*l
;
14275 if (free_insn_labels
== NULL
)
14276 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14279 l
= free_insn_labels
;
14280 free_insn_labels
= l
->next
;
14284 l
->next
= insn_labels
;
14288 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14290 /* Some special processing for a MIPS ELF file. */
14293 mips_elf_final_processing ()
14295 /* Write out the register information. */
14296 if (mips_abi
!= N64_ABI
)
14300 s
.ri_gprmask
= mips_gprmask
;
14301 s
.ri_cprmask
[0] = mips_cprmask
[0];
14302 s
.ri_cprmask
[1] = mips_cprmask
[1];
14303 s
.ri_cprmask
[2] = mips_cprmask
[2];
14304 s
.ri_cprmask
[3] = mips_cprmask
[3];
14305 /* The gp_value field is set by the MIPS ELF backend. */
14307 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14308 ((Elf32_External_RegInfo
*)
14309 mips_regmask_frag
));
14313 Elf64_Internal_RegInfo s
;
14315 s
.ri_gprmask
= mips_gprmask
;
14317 s
.ri_cprmask
[0] = mips_cprmask
[0];
14318 s
.ri_cprmask
[1] = mips_cprmask
[1];
14319 s
.ri_cprmask
[2] = mips_cprmask
[2];
14320 s
.ri_cprmask
[3] = mips_cprmask
[3];
14321 /* The gp_value field is set by the MIPS ELF backend. */
14323 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14324 ((Elf64_External_RegInfo
*)
14325 mips_regmask_frag
));
14328 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14329 sort of BFD interface for this. */
14330 if (mips_any_noreorder
)
14331 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14332 if (mips_pic
!= NO_PIC
)
14334 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14335 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14338 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14340 /* Set MIPS ELF flags for ASEs. */
14341 if (file_ase_mips16
)
14342 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14343 #if 0 /* XXX FIXME */
14344 if (file_ase_mips3d
)
14345 elf_elfheader (stdoutput
)->e_flags
|= ???;
14348 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14350 /* Set the MIPS ELF ABI flags. */
14351 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14352 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14353 else if (mips_abi
== O64_ABI
)
14354 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14355 else if (mips_abi
== EABI_ABI
)
14357 if (!file_mips_gp32
)
14358 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14360 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14362 else if (mips_abi
== N32_ABI
)
14363 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14365 /* Nothing to do for N64_ABI. */
14367 if (mips_32bitmode
)
14368 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14371 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14373 typedef struct proc
{
14375 unsigned long reg_mask
;
14376 unsigned long reg_offset
;
14377 unsigned long fpreg_mask
;
14378 unsigned long fpreg_offset
;
14379 unsigned long frame_offset
;
14380 unsigned long frame_reg
;
14381 unsigned long pc_reg
;
14384 static procS cur_proc
;
14385 static procS
*cur_proc_ptr
;
14386 static int numprocs
;
14388 /* Fill in an rs_align_code fragment. */
14391 mips_handle_align (fragp
)
14394 if (fragp
->fr_type
!= rs_align_code
)
14397 if (mips_opts
.mips16
)
14399 static const unsigned char be_nop
[] = { 0x65, 0x00 };
14400 static const unsigned char le_nop
[] = { 0x00, 0x65 };
14405 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14406 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14414 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
14418 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14429 /* check for premature end, nesting errors, etc */
14431 as_warn (_("missing .end at end of assembly"));
14440 if (*input_line_pointer
== '-')
14442 ++input_line_pointer
;
14445 if (!ISDIGIT (*input_line_pointer
))
14446 as_bad (_("expected simple number"));
14447 if (input_line_pointer
[0] == '0')
14449 if (input_line_pointer
[1] == 'x')
14451 input_line_pointer
+= 2;
14452 while (ISXDIGIT (*input_line_pointer
))
14455 val
|= hex_value (*input_line_pointer
++);
14457 return negative
? -val
: val
;
14461 ++input_line_pointer
;
14462 while (ISDIGIT (*input_line_pointer
))
14465 val
|= *input_line_pointer
++ - '0';
14467 return negative
? -val
: val
;
14470 if (!ISDIGIT (*input_line_pointer
))
14472 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14473 *input_line_pointer
, *input_line_pointer
);
14474 as_warn (_("invalid number"));
14477 while (ISDIGIT (*input_line_pointer
))
14480 val
+= *input_line_pointer
++ - '0';
14482 return negative
? -val
: val
;
14485 /* The .file directive; just like the usual .file directive, but there
14486 is an initial number which is the ECOFF file index. In the non-ECOFF
14487 case .file implies DWARF-2. */
14491 int x ATTRIBUTE_UNUSED
;
14493 static int first_file_directive
= 0;
14495 if (ECOFF_DEBUGGING
)
14504 filename
= dwarf2_directive_file (0);
14506 /* Versions of GCC up to 3.1 start files with a ".file"
14507 directive even for stabs output. Make sure that this
14508 ".file" is handled. Note that you need a version of GCC
14509 after 3.1 in order to support DWARF-2 on MIPS. */
14510 if (filename
!= NULL
&& ! first_file_directive
)
14512 (void) new_logical_line (filename
, -1);
14513 s_app_file_string (filename
);
14515 first_file_directive
= 1;
14519 /* The .loc directive, implying DWARF-2. */
14523 int x ATTRIBUTE_UNUSED
;
14525 if (!ECOFF_DEBUGGING
)
14526 dwarf2_directive_loc (0);
14529 /* The .end directive. */
14533 int x ATTRIBUTE_UNUSED
;
14537 /* Following functions need their own .frame and .cprestore directives. */
14538 mips_frame_reg_valid
= 0;
14539 mips_cprestore_valid
= 0;
14541 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14544 demand_empty_rest_of_line ();
14549 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14550 as_warn (_(".end not in text section"));
14554 as_warn (_(".end directive without a preceding .ent directive."));
14555 demand_empty_rest_of_line ();
14561 assert (S_GET_NAME (p
));
14562 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
14563 as_warn (_(".end symbol does not match .ent symbol."));
14565 if (debug_type
== DEBUG_STABS
)
14566 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14570 as_warn (_(".end directive missing or unknown symbol"));
14573 /* Generate a .pdr section. */
14574 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14576 segT saved_seg
= now_seg
;
14577 subsegT saved_subseg
= now_subseg
;
14582 dot
= frag_now_fix ();
14584 #ifdef md_flush_pending_output
14585 md_flush_pending_output ();
14589 subseg_set (pdr_seg
, 0);
14591 /* Write the symbol. */
14592 exp
.X_op
= O_symbol
;
14593 exp
.X_add_symbol
= p
;
14594 exp
.X_add_number
= 0;
14595 emit_expr (&exp
, 4);
14597 fragp
= frag_more (7 * 4);
14599 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
14600 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
14601 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
14602 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
14603 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
14604 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
14605 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
14607 subseg_set (saved_seg
, saved_subseg
);
14609 #endif /* OBJ_ELF */
14611 cur_proc_ptr
= NULL
;
14614 /* The .aent and .ent directives. */
14622 symbolP
= get_symbol ();
14623 if (*input_line_pointer
== ',')
14624 ++input_line_pointer
;
14625 SKIP_WHITESPACE ();
14626 if (ISDIGIT (*input_line_pointer
)
14627 || *input_line_pointer
== '-')
14630 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14631 as_warn (_(".ent or .aent not in text section."));
14633 if (!aent
&& cur_proc_ptr
)
14634 as_warn (_("missing .end"));
14638 /* This function needs its own .frame and .cprestore directives. */
14639 mips_frame_reg_valid
= 0;
14640 mips_cprestore_valid
= 0;
14642 cur_proc_ptr
= &cur_proc
;
14643 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14645 cur_proc_ptr
->isym
= symbolP
;
14647 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14651 if (debug_type
== DEBUG_STABS
)
14652 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14653 S_GET_NAME (symbolP
));
14656 demand_empty_rest_of_line ();
14659 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14660 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14661 s_mips_frame is used so that we can set the PDR information correctly.
14662 We can't use the ecoff routines because they make reference to the ecoff
14663 symbol table (in the mdebug section). */
14666 s_mips_frame (ignore
)
14667 int ignore ATTRIBUTE_UNUSED
;
14670 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14674 if (cur_proc_ptr
== (procS
*) NULL
)
14676 as_warn (_(".frame outside of .ent"));
14677 demand_empty_rest_of_line ();
14681 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14683 SKIP_WHITESPACE ();
14684 if (*input_line_pointer
++ != ','
14685 || get_absolute_expression_and_terminator (&val
) != ',')
14687 as_warn (_("Bad .frame directive"));
14688 --input_line_pointer
;
14689 demand_empty_rest_of_line ();
14693 cur_proc_ptr
->frame_offset
= val
;
14694 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14696 demand_empty_rest_of_line ();
14699 #endif /* OBJ_ELF */
14703 /* The .fmask and .mask directives. If the mdebug section is present
14704 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14705 embedded targets, s_mips_mask is used so that we can set the PDR
14706 information correctly. We can't use the ecoff routines because they
14707 make reference to the ecoff symbol table (in the mdebug section). */
14710 s_mips_mask (reg_type
)
14714 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14718 if (cur_proc_ptr
== (procS
*) NULL
)
14720 as_warn (_(".mask/.fmask outside of .ent"));
14721 demand_empty_rest_of_line ();
14725 if (get_absolute_expression_and_terminator (&mask
) != ',')
14727 as_warn (_("Bad .mask/.fmask directive"));
14728 --input_line_pointer
;
14729 demand_empty_rest_of_line ();
14733 off
= get_absolute_expression ();
14735 if (reg_type
== 'F')
14737 cur_proc_ptr
->fpreg_mask
= mask
;
14738 cur_proc_ptr
->fpreg_offset
= off
;
14742 cur_proc_ptr
->reg_mask
= mask
;
14743 cur_proc_ptr
->reg_offset
= off
;
14746 demand_empty_rest_of_line ();
14749 #endif /* OBJ_ELF */
14750 s_ignore (reg_type
);
14753 /* The .loc directive. */
14764 assert (now_seg
== text_section
);
14766 lineno
= get_number ();
14767 addroff
= frag_now_fix ();
14769 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14770 S_SET_TYPE (symbolP
, N_SLINE
);
14771 S_SET_OTHER (symbolP
, 0);
14772 S_SET_DESC (symbolP
, lineno
);
14773 symbolP
->sy_segment
= now_seg
;
14777 /* A table describing all the processors gas knows about. Names are
14778 matched in the order listed.
14780 To ease comparison, please keep this table in the same order as
14781 gcc's mips_cpu_info_table[]. */
14782 static const struct mips_cpu_info mips_cpu_info_table
[] =
14784 /* Entries for generic ISAs */
14785 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14786 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14787 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14788 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14789 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14790 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14791 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14792 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14795 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14796 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14797 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14800 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14803 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14804 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14805 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14806 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14807 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14808 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14809 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14810 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14811 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14812 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14813 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14814 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14817 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14818 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14819 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14820 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14821 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14822 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14823 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14824 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14825 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14826 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14827 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14828 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
14831 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
14832 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14833 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14836 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14837 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14839 /* Broadcom SB-1 CPU core */
14840 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14847 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14848 with a final "000" replaced by "k". Ignore case.
14850 Note: this function is shared between GCC and GAS. */
14853 mips_strict_matching_cpu_name_p (canonical
, given
)
14854 const char *canonical
, *given
;
14856 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14857 given
++, canonical
++;
14859 return ((*given
== 0 && *canonical
== 0)
14860 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14864 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14865 CPU name. We've traditionally allowed a lot of variation here.
14867 Note: this function is shared between GCC and GAS. */
14870 mips_matching_cpu_name_p (canonical
, given
)
14871 const char *canonical
, *given
;
14873 /* First see if the name matches exactly, or with a final "000"
14874 turned into "k". */
14875 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14878 /* If not, try comparing based on numerical designation alone.
14879 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14880 if (TOLOWER (*given
) == 'r')
14882 if (!ISDIGIT (*given
))
14885 /* Skip over some well-known prefixes in the canonical name,
14886 hoping to find a number there too. */
14887 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14889 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14891 else if (TOLOWER (canonical
[0]) == 'r')
14894 return mips_strict_matching_cpu_name_p (canonical
, given
);
14898 /* Parse an option that takes the name of a processor as its argument.
14899 OPTION is the name of the option and CPU_STRING is the argument.
14900 Return the corresponding processor enumeration if the CPU_STRING is
14901 recognized, otherwise report an error and return null.
14903 A similar function exists in GCC. */
14905 static const struct mips_cpu_info
*
14906 mips_parse_cpu (option
, cpu_string
)
14907 const char *option
, *cpu_string
;
14909 const struct mips_cpu_info
*p
;
14911 /* 'from-abi' selects the most compatible architecture for the given
14912 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14913 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14914 version. Look first at the -mgp options, if given, otherwise base
14915 the choice on MIPS_DEFAULT_64BIT.
14917 Treat NO_ABI like the EABIs. One reason to do this is that the
14918 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14919 architecture. This code picks MIPS I for 'mips' and MIPS III for
14920 'mips64', just as we did in the days before 'from-abi'. */
14921 if (strcasecmp (cpu_string
, "from-abi") == 0)
14923 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14924 return mips_cpu_info_from_isa (ISA_MIPS1
);
14926 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14927 return mips_cpu_info_from_isa (ISA_MIPS3
);
14929 if (file_mips_gp32
>= 0)
14930 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14932 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14937 /* 'default' has traditionally been a no-op. Probably not very useful. */
14938 if (strcasecmp (cpu_string
, "default") == 0)
14941 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14942 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14945 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14949 /* Return the canonical processor information for ISA (a member of the
14950 ISA_MIPS* enumeration). */
14952 static const struct mips_cpu_info
*
14953 mips_cpu_info_from_isa (isa
)
14958 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14959 if (mips_cpu_info_table
[i
].is_isa
14960 && isa
== mips_cpu_info_table
[i
].isa
)
14961 return (&mips_cpu_info_table
[i
]);
14967 show (stream
, string
, col_p
, first_p
)
14969 const char *string
;
14975 fprintf (stream
, "%24s", "");
14980 fprintf (stream
, ", ");
14984 if (*col_p
+ strlen (string
) > 72)
14986 fprintf (stream
, "\n%24s", "");
14990 fprintf (stream
, "%s", string
);
14991 *col_p
+= strlen (string
);
14997 md_show_usage (stream
)
15003 fprintf (stream
, _("\
15005 -membedded-pic generate embedded position independent code\n\
15006 -EB generate big endian output\n\
15007 -EL generate little endian output\n\
15008 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15009 -G NUM allow referencing objects up to NUM bytes\n\
15010 implicitly with the gp register [default 8]\n"));
15011 fprintf (stream
, _("\
15012 -mips1 generate MIPS ISA I instructions\n\
15013 -mips2 generate MIPS ISA II instructions\n\
15014 -mips3 generate MIPS ISA III instructions\n\
15015 -mips4 generate MIPS ISA IV instructions\n\
15016 -mips5 generate MIPS ISA V instructions\n\
15017 -mips32 generate MIPS32 ISA instructions\n\
15018 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15019 -mips64 generate MIPS64 ISA instructions\n\
15020 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15024 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15025 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15026 show (stream
, "from-abi", &column
, &first
);
15027 fputc ('\n', stream
);
15029 fprintf (stream
, _("\
15030 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15031 -no-mCPU don't generate code specific to CPU.\n\
15032 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15036 show (stream
, "3900", &column
, &first
);
15037 show (stream
, "4010", &column
, &first
);
15038 show (stream
, "4100", &column
, &first
);
15039 show (stream
, "4650", &column
, &first
);
15040 fputc ('\n', stream
);
15042 fprintf (stream
, _("\
15043 -mips16 generate mips16 instructions\n\
15044 -no-mips16 do not generate mips16 instructions\n"));
15045 fprintf (stream
, _("\
15046 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15047 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15048 -O0 remove unneeded NOPs, do not swap branches\n\
15049 -O remove unneeded NOPs and swap branches\n\
15050 -n warn about NOPs generated from macros\n\
15051 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
15052 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15053 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15055 fprintf (stream
, _("\
15056 -KPIC, -call_shared generate SVR4 position independent code\n\
15057 -non_shared do not generate position independent code\n\
15058 -xgot assume a 32 bit GOT\n\
15059 -mabi=ABI create ABI conformant object file for:\n"));
15063 show (stream
, "32", &column
, &first
);
15064 show (stream
, "o64", &column
, &first
);
15065 show (stream
, "n32", &column
, &first
);
15066 show (stream
, "64", &column
, &first
);
15067 show (stream
, "eabi", &column
, &first
);
15069 fputc ('\n', stream
);
15071 fprintf (stream
, _("\
15072 -32 create o32 ABI object file (default)\n\
15073 -n32 create n32 ABI object file\n\
15074 -64 create 64 ABI object file\n"));
15079 mips_dwarf2_format ()
15081 if (mips_abi
== N64_ABI
)
15084 return dwarf2_format_64bit_irix
;
15086 return dwarf2_format_64bit
;
15090 return dwarf2_format_32bit
;