1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2019 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The name if this is an label. */
147 /* The target label name if this is an branch. */
150 /* The frag that contains the instruction. */
153 /* The offset into FRAG of the first instruction byte. */
156 /* The relocs associated with the instruction, if any. */
159 /* True if this entry cannot be moved from its current position. */
160 unsigned int fixed_p
: 1;
162 /* True if this instruction occurred in a .set noreorder block. */
163 unsigned int noreorder_p
: 1;
165 /* True for mips16 instructions that jump to an absolute address. */
166 unsigned int mips16_absolute_jump_p
: 1;
168 /* True if this instruction is complete. */
169 unsigned int complete_p
: 1;
171 /* True if this instruction is cleared from history by unconditional
173 unsigned int cleared_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
208 <asename>', by command line options, and based on the default
211 /* Whether we are assembling for the mips16 processor. 0 if we are
212 not, 1 if we are, and -1 if the value has not been initialized.
213 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
214 -nomips16 command line options, and the default CPU. */
216 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
217 1 if we are, and -1 if the value has not been initialized. Changed
218 by `.set micromips' and `.set nomicromips', and the -mmicromips
219 and -mno-micromips command line options, and the default CPU. */
221 /* Non-zero if we should not reorder instructions. Changed by `.set
222 reorder' and `.set noreorder'. */
224 /* Non-zero if we should not permit the register designated "assembler
225 temporary" to be used in instructions. The value is the register
226 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
227 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
229 /* Non-zero if we should warn when a macro instruction expands into
230 more than one machine instruction. Changed by `.set nomacro' and
232 int warn_about_macros
;
233 /* Non-zero if we should not move instructions. Changed by `.set
234 move', `.set volatile', `.set nomove', and `.set novolatile'. */
236 /* Non-zero if we should not optimize branches by moving the target
237 of the branch into the delay slot. Actually, we don't perform
238 this optimization anyhow. Changed by `.set bopt' and `.set
241 /* Non-zero if we should not autoextend mips16 instructions.
242 Changed by `.set autoextend' and `.set noautoextend'. */
244 /* True if we should only emit 32-bit microMIPS instructions.
245 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
246 and -mno-insn32 command line options. */
248 /* Restrict general purpose registers and floating point registers
249 to 32 bit. This is initially determined when -mgp32 or -mfp32
250 is passed but can changed if the assembler code uses .set mipsN. */
253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
254 command line option, and the default CPU. */
256 /* True if ".set sym32" is in effect. */
258 /* True if floating-point operations are not allowed. Changed by .set
259 softfloat or .set hardfloat, by command line options -msoft-float or
260 -mhard-float. The default is false. */
261 bfd_boolean soft_float
;
263 /* True if only single-precision floating-point operations are allowed.
264 Changed by .set singlefloat or .set doublefloat, command-line options
265 -msingle-float or -mdouble-float. The default is false. */
266 bfd_boolean single_float
;
268 /* 1 if single-precision operations on odd-numbered registers are
272 /* The set of ASEs that should be enabled for the user specified
273 architecture. This cannot be inferred from 'arch' for all cores
274 as processors only have a unique 'arch' if they add architecture
275 specific instructions (UDI). */
279 /* Specifies whether module level options have been checked yet. */
280 static bfd_boolean file_mips_opts_checked
= FALSE
;
282 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
283 value has not been initialized. Changed by `.nan legacy' and
284 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
285 options, and the default CPU. */
286 static int mips_nan2008
= -1;
288 /* This is the struct we use to hold the module level set of options.
289 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
290 fp fields to -1 to indicate that they have not been initialized. */
292 static struct mips_set_options file_mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
295 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
296 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
297 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
298 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
302 /* This is similar to file_mips_opts, but for the current set of options. */
304 static struct mips_set_options mips_opts
=
306 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
307 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
308 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
309 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
310 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
314 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
315 static unsigned int file_ase_explicit
;
317 /* These variables are filled in with the masks of registers used.
318 The object format code reads them and puts them in the appropriate
320 unsigned long mips_gprmask
;
321 unsigned long mips_cprmask
[4];
323 /* True if any MIPS16 code was produced. */
324 static int file_ase_mips16
;
326 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
327 || mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS32R3 \
329 || mips_opts.isa == ISA_MIPS32R5 \
330 || mips_opts.isa == ISA_MIPS64 \
331 || mips_opts.isa == ISA_MIPS64R2 \
332 || mips_opts.isa == ISA_MIPS64R3 \
333 || mips_opts.isa == ISA_MIPS64R5)
335 /* True if any microMIPS code was produced. */
336 static int file_ase_micromips
;
338 /* True if we want to create R_MIPS_JALR for jalr $25. */
340 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
342 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
343 because there's no place for any addend, the only acceptable
344 expression is a bare symbol. */
345 #define MIPS_JALR_HINT_P(EXPR) \
346 (!HAVE_IN_PLACE_ADDENDS \
347 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
350 /* The argument of the -march= flag. The architecture we are assembling. */
351 static const char *mips_arch_string
;
353 /* The argument of the -mtune= flag. The architecture for which we
355 static int mips_tune
= CPU_UNKNOWN
;
356 static const char *mips_tune_string
;
358 /* True when generating 32-bit code for a 64-bit processor. */
359 static int mips_32bitmode
= 0;
361 /* True if the given ABI requires 32-bit registers. */
362 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
364 /* Likewise 64-bit registers. */
365 #define ABI_NEEDS_64BIT_REGS(ABI) \
367 || (ABI) == N64_ABI \
370 #define ISA_IS_R6(ISA) \
371 ((ISA) == ISA_MIPS32R6 \
372 || (ISA) == ISA_MIPS64R6)
374 /* Return true if ISA supports 64 bit wide gp registers. */
375 #define ISA_HAS_64BIT_REGS(ISA) \
376 ((ISA) == ISA_MIPS3 \
377 || (ISA) == ISA_MIPS4 \
378 || (ISA) == ISA_MIPS5 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2 \
381 || (ISA) == ISA_MIPS64R3 \
382 || (ISA) == ISA_MIPS64R5 \
383 || (ISA) == ISA_MIPS64R6)
385 /* Return true if ISA supports 64 bit wide float registers. */
386 #define ISA_HAS_64BIT_FPRS(ISA) \
387 ((ISA) == ISA_MIPS3 \
388 || (ISA) == ISA_MIPS4 \
389 || (ISA) == ISA_MIPS5 \
390 || (ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS32R3 \
392 || (ISA) == ISA_MIPS32R5 \
393 || (ISA) == ISA_MIPS32R6 \
394 || (ISA) == ISA_MIPS64 \
395 || (ISA) == ISA_MIPS64R2 \
396 || (ISA) == ISA_MIPS64R3 \
397 || (ISA) == ISA_MIPS64R5 \
398 || (ISA) == ISA_MIPS64R6)
400 /* Return true if ISA supports 64-bit right rotate (dror et al.)
402 #define ISA_HAS_DROR(ISA) \
403 ((ISA) == ISA_MIPS64R2 \
404 || (ISA) == ISA_MIPS64R3 \
405 || (ISA) == ISA_MIPS64R5 \
406 || (ISA) == ISA_MIPS64R6 \
407 || (mips_opts.micromips \
408 && ISA_HAS_64BIT_REGS (ISA)) \
411 /* Return true if ISA supports 32-bit right rotate (ror et al.)
413 #define ISA_HAS_ROR(ISA) \
414 ((ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS32R3 \
416 || (ISA) == ISA_MIPS32R5 \
417 || (ISA) == ISA_MIPS32R6 \
418 || (ISA) == ISA_MIPS64R2 \
419 || (ISA) == ISA_MIPS64R3 \
420 || (ISA) == ISA_MIPS64R5 \
421 || (ISA) == ISA_MIPS64R6 \
422 || (mips_opts.ase & ASE_SMARTMIPS) \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
428 (((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS32R3 \
431 || (ISA) == ISA_MIPS32R5 \
432 || (ISA) == ISA_MIPS32R6 \
433 || (ISA) == ISA_MIPS64 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6 \
438 || (CPU) == CPU_R5900) \
439 && ((CPU) != CPU_GS464 \
440 || (CPU) != CPU_GS464E \
441 || (CPU) != CPU_GS264E))
443 /* Return true if ISA supports move to/from high part of a 64-bit
444 floating-point register. */
445 #define ISA_HAS_MXHC1(ISA) \
446 ((ISA) == ISA_MIPS32R2 \
447 || (ISA) == ISA_MIPS32R3 \
448 || (ISA) == ISA_MIPS32R5 \
449 || (ISA) == ISA_MIPS32R6 \
450 || (ISA) == ISA_MIPS64R2 \
451 || (ISA) == ISA_MIPS64R3 \
452 || (ISA) == ISA_MIPS64R5 \
453 || (ISA) == ISA_MIPS64R6)
455 /* Return true if ISA supports legacy NAN. */
456 #define ISA_HAS_LEGACY_NAN(ISA) \
457 ((ISA) == ISA_MIPS1 \
458 || (ISA) == ISA_MIPS2 \
459 || (ISA) == ISA_MIPS3 \
460 || (ISA) == ISA_MIPS4 \
461 || (ISA) == ISA_MIPS5 \
462 || (ISA) == ISA_MIPS32 \
463 || (ISA) == ISA_MIPS32R2 \
464 || (ISA) == ISA_MIPS32R3 \
465 || (ISA) == ISA_MIPS32R5 \
466 || (ISA) == ISA_MIPS64 \
467 || (ISA) == ISA_MIPS64R2 \
468 || (ISA) == ISA_MIPS64R3 \
469 || (ISA) == ISA_MIPS64R5)
472 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
477 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
481 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
483 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
485 /* True if relocations are stored in-place. */
486 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
488 /* The ABI-derived address size. */
489 #define HAVE_64BIT_ADDRESSES \
490 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
491 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
493 /* The size of symbolic constants (i.e., expressions of the form
494 "SYMBOL" or "SYMBOL + OFFSET"). */
495 #define HAVE_32BIT_SYMBOLS \
496 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
497 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
499 /* Addresses are loaded in different ways, depending on the address size
500 in use. The n32 ABI Documentation also mandates the use of additions
501 with overflow checking, but existing implementations don't follow it. */
502 #define ADDRESS_ADD_INSN \
503 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
505 #define ADDRESS_ADDI_INSN \
506 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
508 #define ADDRESS_LOAD_INSN \
509 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
511 #define ADDRESS_STORE_INSN \
512 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
514 /* Return true if the given CPU supports the MIPS16 ASE. */
515 #define CPU_HAS_MIPS16(cpu) \
516 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
517 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
519 /* Return true if the given CPU supports the microMIPS ASE. */
520 #define CPU_HAS_MICROMIPS(cpu) 0
522 /* True if CPU has a dror instruction. */
523 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
525 /* True if CPU has a ror instruction. */
526 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
528 /* True if CPU is in the Octeon family. */
529 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
530 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
532 /* True if CPU has seq/sne and seqi/snei instructions. */
533 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
535 /* True, if CPU has support for ldc1 and sdc1. */
536 #define CPU_HAS_LDC1_SDC1(CPU) \
537 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
539 /* True if mflo and mfhi can be immediately followed by instructions
540 which write to the HI and LO registers.
542 According to MIPS specifications, MIPS ISAs I, II, and III need
543 (at least) two instructions between the reads of HI/LO and
544 instructions which write them, and later ISAs do not. Contradicting
545 the MIPS specifications, some MIPS IV processor user manuals (e.g.
546 the UM for the NEC Vr5000) document needing the instructions between
547 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
548 MIPS64 and later ISAs to have the interlocks, plus any specific
549 earlier-ISA CPUs for which CPU documentation declares that the
550 instructions are really interlocked. */
551 #define hilo_interlocks \
552 (mips_opts.isa == ISA_MIPS32 \
553 || mips_opts.isa == ISA_MIPS32R2 \
554 || mips_opts.isa == ISA_MIPS32R3 \
555 || mips_opts.isa == ISA_MIPS32R5 \
556 || mips_opts.isa == ISA_MIPS32R6 \
557 || mips_opts.isa == ISA_MIPS64 \
558 || mips_opts.isa == ISA_MIPS64R2 \
559 || mips_opts.isa == ISA_MIPS64R3 \
560 || mips_opts.isa == ISA_MIPS64R5 \
561 || mips_opts.isa == ISA_MIPS64R6 \
562 || mips_opts.arch == CPU_R4010 \
563 || mips_opts.arch == CPU_R5900 \
564 || mips_opts.arch == CPU_R10000 \
565 || mips_opts.arch == CPU_R12000 \
566 || mips_opts.arch == CPU_R14000 \
567 || mips_opts.arch == CPU_R16000 \
568 || mips_opts.arch == CPU_RM7000 \
569 || mips_opts.arch == CPU_VR5500 \
570 || mips_opts.micromips \
573 /* Whether the processor uses hardware interlocks to protect reads
574 from the GPRs after they are loaded from memory, and thus does not
575 require nops to be inserted. This applies to instructions marked
576 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
577 level I and microMIPS mode instructions are always interlocked. */
578 #define gpr_interlocks \
579 (mips_opts.isa != ISA_MIPS1 \
580 || mips_opts.arch == CPU_R3900 \
581 || mips_opts.arch == CPU_R5900 \
582 || mips_opts.micromips \
585 /* Whether the processor uses hardware interlocks to avoid delays
586 required by coprocessor instructions, and thus does not require
587 nops to be inserted. This applies to instructions marked
588 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
589 instructions marked INSN_WRITE_COND_CODE and ones marked
590 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
591 levels I, II, and III and microMIPS mode instructions are always
593 /* Itbl support may require additional care here. */
594 #define cop_interlocks \
595 ((mips_opts.isa != ISA_MIPS1 \
596 && mips_opts.isa != ISA_MIPS2 \
597 && mips_opts.isa != ISA_MIPS3) \
598 || mips_opts.arch == CPU_R4300 \
599 || mips_opts.micromips \
602 /* Whether the processor uses hardware interlocks to protect reads
603 from coprocessor registers after they are loaded from memory, and
604 thus does not require nops to be inserted. This applies to
605 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
606 requires at MIPS ISA level I and microMIPS mode instructions are
607 always interlocked. */
608 #define cop_mem_interlocks \
609 (mips_opts.isa != ISA_MIPS1 \
610 || mips_opts.micromips \
613 /* Is this a mfhi or mflo instruction? */
614 #define MF_HILO_INSN(PINFO) \
615 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
617 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
618 has been selected. This implies, in particular, that addresses of text
619 labels have their LSB set. */
620 #define HAVE_CODE_COMPRESSION \
621 ((mips_opts.mips16 | mips_opts.micromips) != 0)
623 /* The minimum and maximum signed values that can be stored in a GPR. */
624 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
625 #define GPR_SMIN (-GPR_SMAX - 1)
627 /* MIPS PIC level. */
629 enum mips_pic_level mips_pic
;
631 /* 1 if we should generate 32 bit offsets from the $gp register in
632 SVR4_PIC mode. Currently has no meaning in other modes. */
633 static int mips_big_got
= 0;
635 /* 1 if trap instructions should used for overflow rather than break
637 static int mips_trap
= 0;
639 /* 1 if double width floating point constants should not be constructed
640 by assembling two single width halves into two single width floating
641 point registers which just happen to alias the double width destination
642 register. On some architectures this aliasing can be disabled by a bit
643 in the status register, and the setting of this bit cannot be determined
644 automatically at assemble time. */
645 static int mips_disable_float_construction
;
647 /* Non-zero if any .set noreorder directives were used. */
649 static int mips_any_noreorder
;
651 /* Non-zero if nops should be inserted when the register referenced in
652 an mfhi/mflo instruction is read in the next two instructions. */
653 static int mips_7000_hilo_fix
;
655 /* The size of objects in the small data section. */
656 static unsigned int g_switch_value
= 8;
657 /* Whether the -G option was used. */
658 static int g_switch_seen
= 0;
663 /* If we can determine in advance that GP optimization won't be
664 possible, we can skip the relaxation stuff that tries to produce
665 GP-relative references. This makes delay slot optimization work
668 This function can only provide a guess, but it seems to work for
669 gcc output. It needs to guess right for gcc, otherwise gcc
670 will put what it thinks is a GP-relative instruction in a branch
673 I don't know if a fix is needed for the SVR4_PIC mode. I've only
674 fixed it for the non-PIC mode. KR 95/04/07 */
675 static int nopic_need_relax (symbolS
*, int);
677 /* Handle of the OPCODE hash table. */
678 static struct hash_control
*op_hash
= NULL
;
680 /* The opcode hash table we use for the mips16. */
681 static struct hash_control
*mips16_op_hash
= NULL
;
683 /* The opcode hash table we use for the microMIPS ASE. */
684 static struct hash_control
*micromips_op_hash
= NULL
;
686 /* This array holds the chars that always start a comment. If the
687 pre-processor is disabled, these aren't very useful. */
688 const char comment_chars
[] = "#";
690 /* This array holds the chars that only start a comment at the beginning of
691 a line. If the line seems to have the form '# 123 filename'
692 .line and .file directives will appear in the pre-processed output. */
693 /* Note that input_file.c hand checks for '#' at the beginning of the
694 first line of the input file. This is because the compiler outputs
695 #NO_APP at the beginning of its output. */
696 /* Also note that C style comments are always supported. */
697 const char line_comment_chars
[] = "#";
699 /* This array holds machine specific line separator characters. */
700 const char line_separator_chars
[] = ";";
702 /* Chars that can be used to separate mant from exp in floating point nums. */
703 const char EXP_CHARS
[] = "eE";
705 /* Chars that mean this number is a floating point constant.
708 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
710 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
711 changed in read.c . Ideally it shouldn't have to know about it at all,
712 but nothing is ideal around here. */
714 /* Types of printf format used for instruction-related error messages.
715 "I" means int ("%d") and "S" means string ("%s"). */
716 enum mips_insn_error_format
723 /* Information about an error that was found while assembling the current
725 struct mips_insn_error
727 /* We sometimes need to match an instruction against more than one
728 opcode table entry. Errors found during this matching are reported
729 against a particular syntactic argument rather than against the
730 instruction as a whole. We grade these messages so that errors
731 against argument N have a greater priority than an error against
732 any argument < N, since the former implies that arguments up to N
733 were acceptable and that the opcode entry was therefore a closer match.
734 If several matches report an error against the same argument,
735 we only use that error if it is the same in all cases.
737 min_argnum is the minimum argument number for which an error message
738 should be accepted. It is 0 if MSG is against the instruction as
742 /* The printf()-style message, including its format and arguments. */
743 enum mips_insn_error_format format
;
752 /* The error that should be reported for the current instruction. */
753 static struct mips_insn_error insn_error
;
755 static int auto_align
= 1;
757 /* When outputting SVR4 PIC code, the assembler needs to know the
758 offset in the stack frame from which to restore the $gp register.
759 This is set by the .cprestore pseudo-op, and saved in this
761 static offsetT mips_cprestore_offset
= -1;
763 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
764 more optimizations, it can use a register value instead of a memory-saved
765 offset and even an other register than $gp as global pointer. */
766 static offsetT mips_cpreturn_offset
= -1;
767 static int mips_cpreturn_register
= -1;
768 static int mips_gp_register
= GP
;
769 static int mips_gprel_offset
= 0;
771 /* Whether mips_cprestore_offset has been set in the current function
772 (or whether it has already been warned about, if not). */
773 static int mips_cprestore_valid
= 0;
775 /* This is the register which holds the stack frame, as set by the
776 .frame pseudo-op. This is needed to implement .cprestore. */
777 static int mips_frame_reg
= SP
;
779 /* Whether mips_frame_reg has been set in the current function
780 (or whether it has already been warned about, if not). */
781 static int mips_frame_reg_valid
= 0;
783 /* To output NOP instructions correctly, we need to keep information
784 about the previous two instructions. */
786 /* Whether we are optimizing. The default value of 2 means to remove
787 unneeded NOPs and swap branch instructions when possible. A value
788 of 1 means to not swap branches. A value of 0 means to always
790 static int mips_optimize
= 2;
792 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
793 equivalent to seeing no -g option at all. */
794 static int mips_debug
= 0;
796 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
797 #define MAX_VR4130_NOPS 4
799 /* The maximum number of NOPs needed to fill delay slots. */
800 #define MAX_DELAY_NOPS 2
802 /* The maximum number of NOPs needed for any purpose. */
805 /* The maximum range of context length of ll/sc. */
806 #define MAX_LLSC_RANGE 20
808 /* A list of previous instructions, with index 0 being the most recent.
809 We need to look back MAX_NOPS instructions when filling delay slots
810 or working around processor errata. We need to look back one
811 instruction further if we're thinking about using history[0] to
812 fill a branch delay slot. */
813 static struct mips_cl_insn history
[1 + MAX_NOPS
+ MAX_LLSC_RANGE
];
815 /* Arrays of operands for each instruction. */
816 #define MAX_OPERANDS 6
817 struct mips_operand_array
819 const struct mips_operand
*operand
[MAX_OPERANDS
];
821 static struct mips_operand_array
*mips_operands
;
822 static struct mips_operand_array
*mips16_operands
;
823 static struct mips_operand_array
*micromips_operands
;
825 /* Nop instructions used by emit_nop. */
826 static struct mips_cl_insn nop_insn
;
827 static struct mips_cl_insn mips16_nop_insn
;
828 static struct mips_cl_insn micromips_nop16_insn
;
829 static struct mips_cl_insn micromips_nop32_insn
;
831 /* Sync instructions used by insert sync. */
832 static struct mips_cl_insn sync_insn
;
834 /* The appropriate nop for the current mode. */
835 #define NOP_INSN (mips_opts.mips16 \
837 : (mips_opts.micromips \
838 ? (mips_opts.insn32 \
839 ? µmips_nop32_insn \
840 : µmips_nop16_insn) \
843 /* The size of NOP_INSN in bytes. */
844 #define NOP_INSN_SIZE ((mips_opts.mips16 \
845 || (mips_opts.micromips && !mips_opts.insn32)) \
848 /* If this is set, it points to a frag holding nop instructions which
849 were inserted before the start of a noreorder section. If those
850 nops turn out to be unnecessary, the size of the frag can be
852 static fragS
*prev_nop_frag
;
854 /* The number of nop instructions we created in prev_nop_frag. */
855 static int prev_nop_frag_holds
;
857 /* The number of nop instructions that we know we need in
859 static int prev_nop_frag_required
;
861 /* The number of instructions we've seen since prev_nop_frag. */
862 static int prev_nop_frag_since
;
864 /* Relocations against symbols are sometimes done in two parts, with a HI
865 relocation and a LO relocation. Each relocation has only 16 bits of
866 space to store an addend. This means that in order for the linker to
867 handle carries correctly, it must be able to locate both the HI and
868 the LO relocation. This means that the relocations must appear in
869 order in the relocation table.
871 In order to implement this, we keep track of each unmatched HI
872 relocation. We then sort them so that they immediately precede the
873 corresponding LO relocation. */
878 struct mips_hi_fixup
*next
;
881 /* The section this fixup is in. */
885 /* The list of unmatched HI relocs. */
887 static struct mips_hi_fixup
*mips_hi_fixup_list
;
889 /* The frag containing the last explicit relocation operator.
890 Null if explicit relocations have not been used. */
892 static fragS
*prev_reloc_op_frag
;
894 /* Map mips16 register numbers to normal MIPS register numbers. */
896 static const unsigned int mips16_to_32_reg_map
[] =
898 16, 17, 2, 3, 4, 5, 6, 7
901 /* Map microMIPS register numbers to normal MIPS register numbers. */
903 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
905 /* The microMIPS registers with type h. */
906 static const unsigned int micromips_to_32_reg_h_map1
[] =
908 5, 5, 6, 4, 4, 4, 4, 4
910 static const unsigned int micromips_to_32_reg_h_map2
[] =
912 6, 7, 7, 21, 22, 5, 6, 7
915 /* The microMIPS registers with type m. */
916 static const unsigned int micromips_to_32_reg_m_map
[] =
918 0, 17, 2, 3, 16, 18, 19, 20
921 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
923 /* Classifies the kind of instructions we're interested in when
924 implementing -mfix-vr4120. */
925 enum fix_vr4120_class
933 NUM_FIX_VR4120_CLASSES
936 /* ...likewise -mfix-loongson2f-jump. */
937 static bfd_boolean mips_fix_loongson2f_jump
;
939 /* ...likewise -mfix-loongson2f-nop. */
940 static bfd_boolean mips_fix_loongson2f_nop
;
942 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
943 static bfd_boolean mips_fix_loongson2f
;
945 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
946 there must be at least one other instruction between an instruction
947 of type X and an instruction of type Y. */
948 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
950 /* True if -mfix-vr4120 is in force. */
951 static int mips_fix_vr4120
;
953 /* ...likewise -mfix-vr4130. */
954 static int mips_fix_vr4130
;
956 /* ...likewise -mfix-24k. */
957 static int mips_fix_24k
;
959 /* ...likewise -mfix-rm7000 */
960 static int mips_fix_rm7000
;
962 /* ...likewise -mfix-cn63xxp1 */
963 static bfd_boolean mips_fix_cn63xxp1
;
965 /* ...likewise -mfix-r5900 */
966 static bfd_boolean mips_fix_r5900
;
967 static bfd_boolean mips_fix_r5900_explicit
;
969 /* ...likewise -mfix-loongson3-llsc. */
970 static bfd_boolean mips_fix_loongson3_llsc
= DEFAULT_MIPS_FIX_LOONGSON3_LLSC
;
972 /* We don't relax branches by default, since this causes us to expand
973 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
974 fail to compute the offset before expanding the macro to the most
975 efficient expansion. */
977 static int mips_relax_branch
;
979 /* TRUE if checks are suppressed for invalid branches between ISA modes.
980 Needed for broken assembly produced by some GCC versions and some
981 sloppy code out there, where branches to data labels are present. */
982 static bfd_boolean mips_ignore_branch_isa
;
984 /* The expansion of many macros depends on the type of symbol that
985 they refer to. For example, when generating position-dependent code,
986 a macro that refers to a symbol may have two different expansions,
987 one which uses GP-relative addresses and one which uses absolute
988 addresses. When generating SVR4-style PIC, a macro may have
989 different expansions for local and global symbols.
991 We handle these situations by generating both sequences and putting
992 them in variant frags. In position-dependent code, the first sequence
993 will be the GP-relative one and the second sequence will be the
994 absolute one. In SVR4 PIC, the first sequence will be for global
995 symbols and the second will be for local symbols.
997 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
998 SECOND are the lengths of the two sequences in bytes. These fields
999 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
1000 the subtype has the following flags:
1003 Set if generating PIC code.
1006 Set if it has been decided that we should use the second
1007 sequence instead of the first.
1010 Set in the first variant frag if the macro's second implementation
1011 is longer than its first. This refers to the macro as a whole,
1012 not an individual relaxation.
1015 Set in the first variant frag if the macro appeared in a .set nomacro
1016 block and if one alternative requires a warning but the other does not.
1019 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1022 RELAX_DELAY_SLOT_16BIT
1023 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1026 RELAX_DELAY_SLOT_SIZE_FIRST
1027 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1028 the macro is of the wrong size for the branch delay slot.
1030 RELAX_DELAY_SLOT_SIZE_SECOND
1031 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1032 the macro is of the wrong size for the branch delay slot.
1034 The frag's "opcode" points to the first fixup for relaxable code.
1036 Relaxable macros are generated using a sequence such as:
1038 relax_start (SYMBOL);
1039 ... generate first expansion ...
1041 ... generate second expansion ...
1044 The code and fixups for the unwanted alternative are discarded
1045 by md_convert_frag. */
1046 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1047 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1049 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1050 #define RELAX_SECOND(X) ((X) & 0xff)
1051 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1052 #define RELAX_USE_SECOND 0x20000
1053 #define RELAX_SECOND_LONGER 0x40000
1054 #define RELAX_NOMACRO 0x80000
1055 #define RELAX_DELAY_SLOT 0x100000
1056 #define RELAX_DELAY_SLOT_16BIT 0x200000
1057 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1058 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1060 /* Branch without likely bit. If label is out of range, we turn:
1062 beq reg1, reg2, label
1072 with the following opcode replacements:
1079 bltzal <-> bgezal (with jal label instead of j label)
1081 Even though keeping the delay slot instruction in the delay slot of
1082 the branch would be more efficient, it would be very tricky to do
1083 correctly, because we'd have to introduce a variable frag *after*
1084 the delay slot instruction, and expand that instead. Let's do it
1085 the easy way for now, even if the branch-not-taken case now costs
1086 one additional instruction. Out-of-range branches are not supposed
1087 to be common, anyway.
1089 Branch likely. If label is out of range, we turn:
1091 beql reg1, reg2, label
1092 delay slot (annulled if branch not taken)
1101 delay slot (executed only if branch taken)
1104 It would be possible to generate a shorter sequence by losing the
1105 likely bit, generating something like:
1110 delay slot (executed only if branch taken)
1122 bltzall -> bgezal (with jal label instead of j label)
1123 bgezall -> bltzal (ditto)
1126 but it's not clear that it would actually improve performance. */
1127 #define RELAX_BRANCH_ENCODE(at, pic, \
1128 uncond, likely, link, toofar) \
1129 ((relax_substateT) \
1132 | ((pic) ? 0x20 : 0) \
1133 | ((toofar) ? 0x40 : 0) \
1134 | ((link) ? 0x80 : 0) \
1135 | ((likely) ? 0x100 : 0) \
1136 | ((uncond) ? 0x200 : 0)))
1137 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1138 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1139 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1140 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1141 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1142 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1143 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1145 /* For mips16 code, we use an entirely different form of relaxation.
1146 mips16 supports two versions of most instructions which take
1147 immediate values: a small one which takes some small value, and a
1148 larger one which takes a 16 bit value. Since branches also follow
1149 this pattern, relaxing these values is required.
1151 We can assemble both mips16 and normal MIPS code in a single
1152 object. Therefore, we need to support this type of relaxation at
1153 the same time that we support the relaxation described above. We
1154 use the high bit of the subtype field to distinguish these cases.
1156 The information we store for this type of relaxation is the
1157 argument code found in the opcode file for this relocation, whether
1158 the user explicitly requested a small or extended form, and whether
1159 the relocation is in a jump or jal delay slot. That tells us the
1160 size of the value, and how it should be stored. We also store
1161 whether the fragment is considered to be extended or not. We also
1162 store whether this is known to be a branch to a different section,
1163 whether we have tried to relax this frag yet, and whether we have
1164 ever extended a PC relative fragment because of a shift count. */
1165 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1170 | ((e2) ? 0x100 : 0) \
1171 | ((pic) ? 0x200 : 0) \
1172 | ((sym32) ? 0x400 : 0) \
1173 | ((nomacro) ? 0x800 : 0) \
1174 | ((small) ? 0x1000 : 0) \
1175 | ((ext) ? 0x2000 : 0) \
1176 | ((dslot) ? 0x4000 : 0) \
1177 | ((jal_dslot) ? 0x8000 : 0))
1179 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1180 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1181 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1182 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1183 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1184 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1185 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1186 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1187 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1188 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1190 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1191 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1192 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1193 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1194 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1195 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1196 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1197 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1198 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1200 /* For microMIPS code, we use relaxation similar to one we use for
1201 MIPS16 code. Some instructions that take immediate values support
1202 two encodings: a small one which takes some small value, and a
1203 larger one which takes a 16 bit value. As some branches also follow
1204 this pattern, relaxing these values is required.
1206 We can assemble both microMIPS and normal MIPS code in a single
1207 object. Therefore, we need to support this type of relaxation at
1208 the same time that we support the relaxation described above. We
1209 use one of the high bits of the subtype field to distinguish these
1212 The information we store for this type of relaxation is the argument
1213 code found in the opcode file for this relocation, the register
1214 selected as the assembler temporary, whether in the 32-bit
1215 instruction mode, whether the branch is unconditional, whether it is
1216 compact, whether there is no delay-slot instruction available to fill
1217 in, whether it stores the link address implicitly in $ra, whether
1218 relaxation of out-of-range 32-bit branches to a sequence of
1219 instructions is enabled, and whether the displacement of a branch is
1220 too large to fit as an immediate argument of a 16-bit and a 32-bit
1221 branch, respectively. */
1222 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1223 uncond, compact, link, nods, \
1224 relax32, toofar16, toofar32) \
1227 | (((at) & 0x1f) << 8) \
1228 | ((insn32) ? 0x2000 : 0) \
1229 | ((pic) ? 0x4000 : 0) \
1230 | ((uncond) ? 0x8000 : 0) \
1231 | ((compact) ? 0x10000 : 0) \
1232 | ((link) ? 0x20000 : 0) \
1233 | ((nods) ? 0x40000 : 0) \
1234 | ((relax32) ? 0x80000 : 0) \
1235 | ((toofar16) ? 0x100000 : 0) \
1236 | ((toofar32) ? 0x200000 : 0))
1237 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1238 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1239 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1240 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1241 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1242 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1243 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1244 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1245 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1246 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1248 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1249 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1250 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1251 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1252 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1253 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1255 /* Sign-extend 16-bit value X. */
1256 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1258 /* Is the given value a sign-extended 32-bit value? */
1259 #define IS_SEXT_32BIT_NUM(x) \
1260 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1261 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1263 /* Is the given value a sign-extended 16-bit value? */
1264 #define IS_SEXT_16BIT_NUM(x) \
1265 (((x) &~ (offsetT) 0x7fff) == 0 \
1266 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1268 /* Is the given value a sign-extended 12-bit value? */
1269 #define IS_SEXT_12BIT_NUM(x) \
1270 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1272 /* Is the given value a sign-extended 9-bit value? */
1273 #define IS_SEXT_9BIT_NUM(x) \
1274 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1276 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1277 #define IS_ZEXT_32BIT_NUM(x) \
1278 (((x) &~ (offsetT) 0xffffffff) == 0 \
1279 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1281 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1283 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1284 (((STRUCT) >> (SHIFT)) & (MASK))
1286 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1287 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1289 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1290 : EXTRACT_BITS ((INSN).insn_opcode, \
1291 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1292 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1293 EXTRACT_BITS ((INSN).insn_opcode, \
1294 MIPS16OP_MASK_##FIELD, \
1295 MIPS16OP_SH_##FIELD)
1297 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1298 #define MIPS16_EXTEND (0xf000U << 16)
1300 /* Whether or not we are emitting a branch-likely macro. */
1301 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1303 /* Global variables used when generating relaxable macros. See the
1304 comment above RELAX_ENCODE for more details about how relaxation
1307 /* 0 if we're not emitting a relaxable macro.
1308 1 if we're emitting the first of the two relaxation alternatives.
1309 2 if we're emitting the second alternative. */
1312 /* The first relaxable fixup in the current frag. (In other words,
1313 the first fixup that refers to relaxable code.) */
1316 /* sizes[0] says how many bytes of the first alternative are stored in
1317 the current frag. Likewise sizes[1] for the second alternative. */
1318 unsigned int sizes
[2];
1320 /* The symbol on which the choice of sequence depends. */
1324 /* Global variables used to decide whether a macro needs a warning. */
1326 /* True if the macro is in a branch delay slot. */
1327 bfd_boolean delay_slot_p
;
1329 /* Set to the length in bytes required if the macro is in a delay slot
1330 that requires a specific length of instruction, otherwise zero. */
1331 unsigned int delay_slot_length
;
1333 /* For relaxable macros, sizes[0] is the length of the first alternative
1334 in bytes and sizes[1] is the length of the second alternative.
1335 For non-relaxable macros, both elements give the length of the
1337 unsigned int sizes
[2];
1339 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1340 instruction of the first alternative in bytes and first_insn_sizes[1]
1341 is the length of the first instruction of the second alternative.
1342 For non-relaxable macros, both elements give the length of the first
1343 instruction in bytes.
1345 Set to zero if we haven't yet seen the first instruction. */
1346 unsigned int first_insn_sizes
[2];
1348 /* For relaxable macros, insns[0] is the number of instructions for the
1349 first alternative and insns[1] is the number of instructions for the
1352 For non-relaxable macros, both elements give the number of
1353 instructions for the macro. */
1354 unsigned int insns
[2];
1356 /* The first variant frag for this macro. */
1358 } mips_macro_warning
;
1360 /* Prototypes for static functions. */
1362 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1364 static void append_insn
1365 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1366 bfd_boolean expansionp
);
1367 static void mips_no_prev_insn (void);
1368 static void macro_build (expressionS
*, const char *, const char *, ...);
1369 static void mips16_macro_build
1370 (expressionS
*, const char *, const char *, va_list *);
1371 static void load_register (int, expressionS
*, int);
1372 static void macro_start (void);
1373 static void macro_end (void);
1374 static void macro (struct mips_cl_insn
*ip
, char *str
);
1375 static void mips16_macro (struct mips_cl_insn
* ip
);
1376 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1377 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1378 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1379 static void mips16_immed
1380 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1381 unsigned int, unsigned long *);
1382 static size_t my_getSmallExpression
1383 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1384 static void my_getExpression (expressionS
*, char *);
1385 static void s_align (int);
1386 static void s_change_sec (int);
1387 static void s_change_section (int);
1388 static void s_cons (int);
1389 static void s_float_cons (int);
1390 static void s_mips_globl (int);
1391 static void s_option (int);
1392 static void s_mipsset (int);
1393 static void s_abicalls (int);
1394 static void s_cpload (int);
1395 static void s_cpsetup (int);
1396 static void s_cplocal (int);
1397 static void s_cprestore (int);
1398 static void s_cpreturn (int);
1399 static void s_dtprelword (int);
1400 static void s_dtpreldword (int);
1401 static void s_tprelword (int);
1402 static void s_tpreldword (int);
1403 static void s_gpvalue (int);
1404 static void s_gpword (int);
1405 static void s_gpdword (int);
1406 static void s_ehword (int);
1407 static void s_cpadd (int);
1408 static void s_insn (int);
1409 static void s_nan (int);
1410 static void s_module (int);
1411 static void s_mips_ent (int);
1412 static void s_mips_end (int);
1413 static void s_mips_frame (int);
1414 static void s_mips_mask (int reg_type
);
1415 static void s_mips_stab (int);
1416 static void s_mips_weakext (int);
1417 static void s_mips_file (int);
1418 static void s_mips_loc (int);
1419 static bfd_boolean
pic_need_relax (symbolS
*);
1420 static int relaxed_branch_length (fragS
*, asection
*, int);
1421 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1422 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1423 static void file_mips_check_options (void);
1425 /* Table and functions used to map between CPU/ISA names, and
1426 ISA levels, and CPU numbers. */
1428 struct mips_cpu_info
1430 const char *name
; /* CPU or ISA name. */
1431 int flags
; /* MIPS_CPU_* flags. */
1432 int ase
; /* Set of ASEs implemented by the CPU. */
1433 int isa
; /* ISA level. */
1434 int cpu
; /* CPU number (default CPU if ISA). */
1437 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1439 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1440 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1441 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1443 /* Command-line options. */
1444 const char *md_shortopts
= "O::g::G:";
1448 OPTION_MARCH
= OPTION_MD_BASE
,
1480 OPTION_NO_SMARTMIPS
,
1490 OPTION_NO_MICROMIPS
,
1505 OPTION_M7000_HILO_FIX
,
1506 OPTION_MNO_7000_HILO_FIX
,
1510 OPTION_NO_FIX_RM7000
,
1511 OPTION_FIX_LOONGSON3_LLSC
,
1512 OPTION_NO_FIX_LOONGSON3_LLSC
,
1513 OPTION_FIX_LOONGSON2F_JUMP
,
1514 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1515 OPTION_FIX_LOONGSON2F_NOP
,
1516 OPTION_NO_FIX_LOONGSON2F_NOP
,
1518 OPTION_NO_FIX_VR4120
,
1520 OPTION_NO_FIX_VR4130
,
1521 OPTION_FIX_CN63XXP1
,
1522 OPTION_NO_FIX_CN63XXP1
,
1524 OPTION_NO_FIX_R5900
,
1531 OPTION_CONSTRUCT_FLOATS
,
1532 OPTION_NO_CONSTRUCT_FLOATS
,
1536 OPTION_RELAX_BRANCH
,
1537 OPTION_NO_RELAX_BRANCH
,
1538 OPTION_IGNORE_BRANCH_ISA
,
1539 OPTION_NO_IGNORE_BRANCH_ISA
,
1548 OPTION_SINGLE_FLOAT
,
1549 OPTION_DOUBLE_FLOAT
,
1562 OPTION_MVXWORKS_PIC
,
1565 OPTION_NO_ODD_SPREG
,
1568 OPTION_LOONGSON_MMI
,
1569 OPTION_NO_LOONGSON_MMI
,
1570 OPTION_LOONGSON_CAM
,
1571 OPTION_NO_LOONGSON_CAM
,
1572 OPTION_LOONGSON_EXT
,
1573 OPTION_NO_LOONGSON_EXT
,
1574 OPTION_LOONGSON_EXT2
,
1575 OPTION_NO_LOONGSON_EXT2
,
1579 struct option md_longopts
[] =
1581 /* Options which specify architecture. */
1582 {"march", required_argument
, NULL
, OPTION_MARCH
},
1583 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1584 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1585 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1586 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1587 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1588 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1589 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1590 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1591 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1592 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1593 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1594 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1595 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1596 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1597 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1598 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1599 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1601 /* Options which specify Application Specific Extensions (ASEs). */
1602 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1603 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1604 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1605 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1606 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1607 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1608 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1609 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1610 {"mmt", no_argument
, NULL
, OPTION_MT
},
1611 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1612 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1613 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1614 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1615 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1616 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1617 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1618 {"meva", no_argument
, NULL
, OPTION_EVA
},
1619 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1620 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1621 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1622 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1623 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1624 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1625 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1626 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1627 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1628 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1629 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1630 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1631 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1632 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1633 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1634 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1635 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1636 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1637 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1638 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1639 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1640 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1641 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1642 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1643 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1645 /* Old-style architecture options. Don't add more of these. */
1646 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1647 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1648 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1649 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1650 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1651 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1652 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1653 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1655 /* Options which enable bug fixes. */
1656 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1657 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1658 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1659 {"mfix-loongson3-llsc", no_argument
, NULL
, OPTION_FIX_LOONGSON3_LLSC
},
1660 {"mno-fix-loongson3-llsc", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON3_LLSC
},
1661 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1662 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1663 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1664 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1665 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1666 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1667 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1668 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1669 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1670 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1671 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1672 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1673 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1674 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1675 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1676 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1678 /* Miscellaneous options. */
1679 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1680 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1681 {"break", no_argument
, NULL
, OPTION_BREAK
},
1682 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1683 {"EB", no_argument
, NULL
, OPTION_EB
},
1684 {"EL", no_argument
, NULL
, OPTION_EL
},
1685 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1686 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1687 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1688 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1689 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1690 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1691 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1692 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1693 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1694 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1695 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1696 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1697 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1698 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1699 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1700 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1701 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1702 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1703 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1704 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1705 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1706 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1707 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1709 /* Strictly speaking this next option is ELF specific,
1710 but we allow it for other ports as well in order to
1711 make testing easier. */
1712 {"32", no_argument
, NULL
, OPTION_32
},
1714 /* ELF-specific options. */
1715 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1716 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1717 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1718 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1719 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1720 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1721 {"n32", no_argument
, NULL
, OPTION_N32
},
1722 {"64", no_argument
, NULL
, OPTION_64
},
1723 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1724 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1725 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1726 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1727 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1728 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1730 {NULL
, no_argument
, NULL
, 0}
1732 size_t md_longopts_size
= sizeof (md_longopts
);
1734 /* Information about either an Application Specific Extension or an
1735 optional architecture feature that, for simplicity, we treat in the
1736 same way as an ASE. */
1739 /* The name of the ASE, used in both the command-line and .set options. */
1742 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1743 and 64-bit architectures, the flags here refer to the subset that
1744 is available on both. */
1747 /* The ASE_* flag used for instructions that are available on 64-bit
1748 architectures but that are not included in FLAGS. */
1749 unsigned int flags64
;
1751 /* The command-line options that turn the ASE on and off. */
1755 /* The minimum required architecture revisions for MIPS32, MIPS64,
1756 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1759 int micromips32_rev
;
1760 int micromips64_rev
;
1762 /* The architecture where the ASE was removed or -1 if the extension has not
1767 /* A table of all supported ASEs. */
1768 static const struct mips_ase mips_ases
[] = {
1769 { "dsp", ASE_DSP
, ASE_DSP64
,
1770 OPTION_DSP
, OPTION_NO_DSP
,
1774 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1775 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1779 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1780 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1784 { "eva", ASE_EVA
, 0,
1785 OPTION_EVA
, OPTION_NO_EVA
,
1789 { "mcu", ASE_MCU
, 0,
1790 OPTION_MCU
, OPTION_NO_MCU
,
1794 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1795 { "mdmx", ASE_MDMX
, 0,
1796 OPTION_MDMX
, OPTION_NO_MDMX
,
1800 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1801 { "mips3d", ASE_MIPS3D
, 0,
1802 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1807 OPTION_MT
, OPTION_NO_MT
,
1811 { "smartmips", ASE_SMARTMIPS
, 0,
1812 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1816 { "virt", ASE_VIRT
, ASE_VIRT64
,
1817 OPTION_VIRT
, OPTION_NO_VIRT
,
1821 { "msa", ASE_MSA
, ASE_MSA64
,
1822 OPTION_MSA
, OPTION_NO_MSA
,
1826 { "xpa", ASE_XPA
, 0,
1827 OPTION_XPA
, OPTION_NO_XPA
,
1831 { "mips16e2", ASE_MIPS16E2
, 0,
1832 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1836 { "crc", ASE_CRC
, ASE_CRC64
,
1837 OPTION_CRC
, OPTION_NO_CRC
,
1841 { "ginv", ASE_GINV
, 0,
1842 OPTION_GINV
, OPTION_NO_GINV
,
1846 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1847 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1851 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1852 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1856 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1857 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1861 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1862 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1867 /* The set of ASEs that require -mfp64. */
1868 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1870 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1871 static const unsigned int mips_ase_groups
[] = {
1872 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1873 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1878 The following pseudo-ops from the Kane and Heinrich MIPS book
1879 should be defined here, but are currently unsupported: .alias,
1880 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1882 The following pseudo-ops from the Kane and Heinrich MIPS book are
1883 specific to the type of debugging information being generated, and
1884 should be defined by the object format: .aent, .begin, .bend,
1885 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1888 The following pseudo-ops from the Kane and Heinrich MIPS book are
1889 not MIPS CPU specific, but are also not specific to the object file
1890 format. This file is probably the best place to define them, but
1891 they are not currently supported: .asm0, .endr, .lab, .struct. */
1893 static const pseudo_typeS mips_pseudo_table
[] =
1895 /* MIPS specific pseudo-ops. */
1896 {"option", s_option
, 0},
1897 {"set", s_mipsset
, 0},
1898 {"rdata", s_change_sec
, 'r'},
1899 {"sdata", s_change_sec
, 's'},
1900 {"livereg", s_ignore
, 0},
1901 {"abicalls", s_abicalls
, 0},
1902 {"cpload", s_cpload
, 0},
1903 {"cpsetup", s_cpsetup
, 0},
1904 {"cplocal", s_cplocal
, 0},
1905 {"cprestore", s_cprestore
, 0},
1906 {"cpreturn", s_cpreturn
, 0},
1907 {"dtprelword", s_dtprelword
, 0},
1908 {"dtpreldword", s_dtpreldword
, 0},
1909 {"tprelword", s_tprelword
, 0},
1910 {"tpreldword", s_tpreldword
, 0},
1911 {"gpvalue", s_gpvalue
, 0},
1912 {"gpword", s_gpword
, 0},
1913 {"gpdword", s_gpdword
, 0},
1914 {"ehword", s_ehword
, 0},
1915 {"cpadd", s_cpadd
, 0},
1916 {"insn", s_insn
, 0},
1918 {"module", s_module
, 0},
1920 /* Relatively generic pseudo-ops that happen to be used on MIPS
1922 {"asciiz", stringer
, 8 + 1},
1923 {"bss", s_change_sec
, 'b'},
1925 {"half", s_cons
, 1},
1926 {"dword", s_cons
, 3},
1927 {"weakext", s_mips_weakext
, 0},
1928 {"origin", s_org
, 0},
1929 {"repeat", s_rept
, 0},
1931 /* For MIPS this is non-standard, but we define it for consistency. */
1932 {"sbss", s_change_sec
, 'B'},
1934 /* These pseudo-ops are defined in read.c, but must be overridden
1935 here for one reason or another. */
1936 {"align", s_align
, 0},
1937 {"byte", s_cons
, 0},
1938 {"data", s_change_sec
, 'd'},
1939 {"double", s_float_cons
, 'd'},
1940 {"float", s_float_cons
, 'f'},
1941 {"globl", s_mips_globl
, 0},
1942 {"global", s_mips_globl
, 0},
1943 {"hword", s_cons
, 1},
1945 {"long", s_cons
, 2},
1946 {"octa", s_cons
, 4},
1947 {"quad", s_cons
, 3},
1948 {"section", s_change_section
, 0},
1949 {"short", s_cons
, 1},
1950 {"single", s_float_cons
, 'f'},
1951 {"stabd", s_mips_stab
, 'd'},
1952 {"stabn", s_mips_stab
, 'n'},
1953 {"stabs", s_mips_stab
, 's'},
1954 {"text", s_change_sec
, 't'},
1955 {"word", s_cons
, 2},
1957 { "extern", ecoff_directive_extern
, 0},
1962 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1964 /* These pseudo-ops should be defined by the object file format.
1965 However, a.out doesn't support them, so we have versions here. */
1966 {"aent", s_mips_ent
, 1},
1967 {"bgnb", s_ignore
, 0},
1968 {"end", s_mips_end
, 0},
1969 {"endb", s_ignore
, 0},
1970 {"ent", s_mips_ent
, 0},
1971 {"file", s_mips_file
, 0},
1972 {"fmask", s_mips_mask
, 'F'},
1973 {"frame", s_mips_frame
, 0},
1974 {"loc", s_mips_loc
, 0},
1975 {"mask", s_mips_mask
, 'R'},
1976 {"verstamp", s_ignore
, 0},
1980 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1981 purpose of the `.dc.a' internal pseudo-op. */
1984 mips_address_bytes (void)
1986 file_mips_check_options ();
1987 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1990 extern void pop_insert (const pseudo_typeS
*);
1993 mips_pop_insert (void)
1995 pop_insert (mips_pseudo_table
);
1996 if (! ECOFF_DEBUGGING
)
1997 pop_insert (mips_nonecoff_pseudo_table
);
2000 /* Symbols labelling the current insn. */
2002 struct insn_label_list
2004 struct insn_label_list
*next
;
2008 static struct insn_label_list
*free_insn_labels
;
2009 #define label_list tc_segment_info_data.labels
2011 static void mips_clear_insn_labels (void);
2012 static void mips_mark_labels (void);
2013 static void mips_compressed_mark_labels (void);
2016 mips_clear_insn_labels (void)
2018 struct insn_label_list
**pl
;
2019 segment_info_type
*si
;
2023 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
2026 si
= seg_info (now_seg
);
2027 *pl
= si
->label_list
;
2028 si
->label_list
= NULL
;
2032 /* Mark instruction labels in MIPS16/microMIPS mode. */
2035 mips_mark_labels (void)
2037 if (HAVE_CODE_COMPRESSION
)
2038 mips_compressed_mark_labels ();
2041 static char *expr_end
;
2043 /* An expression in a macro instruction. This is set by mips_ip and
2044 mips16_ip and when populated is always an O_constant. */
2046 static expressionS imm_expr
;
2048 /* The relocatable field in an instruction and the relocs associated
2049 with it. These variables are used for instructions like LUI and
2050 JAL as well as true offsets. They are also used for address
2051 operands in macros. */
2053 static expressionS offset_expr
;
2054 static bfd_reloc_code_real_type offset_reloc
[3]
2055 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2057 /* This is set to the resulting size of the instruction to be produced
2058 by mips16_ip if an explicit extension is used or by mips_ip if an
2059 explicit size is supplied. */
2061 static unsigned int forced_insn_length
;
2063 /* True if we are assembling an instruction. All dot symbols defined during
2064 this time should be treated as code labels. */
2066 static bfd_boolean mips_assembling_insn
;
2068 /* The pdr segment for per procedure frame/regmask info. Not used for
2071 static segT pdr_seg
;
2073 /* The default target format to use. */
2075 #if defined (TE_FreeBSD)
2076 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2077 #elif defined (TE_TMIPS)
2078 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2080 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2084 mips_target_format (void)
2086 switch (OUTPUT_FLAVOR
)
2088 case bfd_target_elf_flavour
:
2090 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2091 return (target_big_endian
2092 ? "elf32-bigmips-vxworks"
2093 : "elf32-littlemips-vxworks");
2095 return (target_big_endian
2096 ? (HAVE_64BIT_OBJECTS
2097 ? ELF_TARGET ("elf64-", "big")
2099 ? ELF_TARGET ("elf32-n", "big")
2100 : ELF_TARGET ("elf32-", "big")))
2101 : (HAVE_64BIT_OBJECTS
2102 ? ELF_TARGET ("elf64-", "little")
2104 ? ELF_TARGET ("elf32-n", "little")
2105 : ELF_TARGET ("elf32-", "little"))));
2112 /* Return the ISA revision that is currently in use, or 0 if we are
2113 generating code for MIPS V or below. */
2118 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2121 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2124 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2127 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2130 /* microMIPS implies revision 2 or above. */
2131 if (mips_opts
.micromips
)
2134 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2140 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2143 mips_ase_mask (unsigned int flags
)
2147 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2148 if (flags
& mips_ase_groups
[i
])
2149 flags
|= mips_ase_groups
[i
];
2153 /* Check whether the current ISA supports ASE. Issue a warning if
2157 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2161 static unsigned int warned_isa
;
2162 static unsigned int warned_fp32
;
2164 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2165 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2167 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2168 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2169 && (warned_isa
& ase
->flags
) != ase
->flags
)
2171 warned_isa
|= ase
->flags
;
2172 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2173 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2175 as_warn (_("the %d-bit %s architecture does not support the"
2176 " `%s' extension"), size
, base
, ase
->name
);
2178 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2179 ase
->name
, base
, size
, min_rev
);
2181 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2182 && (warned_isa
& ase
->flags
) != ase
->flags
)
2184 warned_isa
|= ase
->flags
;
2185 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2186 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2187 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2188 ase
->name
, base
, size
, ase
->rem_rev
);
2191 if ((ase
->flags
& FP64_ASES
)
2192 && mips_opts
.fp
!= 64
2193 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2195 warned_fp32
|= ase
->flags
;
2196 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2200 /* Check all enabled ASEs to see whether they are supported by the
2201 chosen architecture. */
2204 mips_check_isa_supports_ases (void)
2206 unsigned int i
, mask
;
2208 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2210 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2211 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2212 mips_check_isa_supports_ase (&mips_ases
[i
]);
2216 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2217 that were affected. */
2220 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2221 bfd_boolean enabled_p
)
2225 mask
= mips_ase_mask (ase
->flags
);
2228 /* Clear combination ASE flags, which need to be recalculated based on
2229 updated regular ASE settings. */
2230 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
);
2233 opts
->ase
|= ase
->flags
;
2235 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2236 instructions which are only valid when both ASEs are enabled.
2237 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2238 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2240 opts
->ase
|= ASE_XPA_VIRT
;
2241 mask
|= ASE_XPA_VIRT
;
2243 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2245 opts
->ase
|= ASE_MIPS16E2_MT
;
2246 mask
|= ASE_MIPS16E2_MT
;
2252 /* Return the ASE called NAME, or null if none. */
2254 static const struct mips_ase
*
2255 mips_lookup_ase (const char *name
)
2259 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2260 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2261 return &mips_ases
[i
];
2265 /* Return the length of a microMIPS instruction in bytes. If bits of
2266 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2267 otherwise it is a 32-bit instruction. */
2269 static inline unsigned int
2270 micromips_insn_length (const struct mips_opcode
*mo
)
2272 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2275 /* Return the length of MIPS16 instruction OPCODE. */
2277 static inline unsigned int
2278 mips16_opcode_length (unsigned long opcode
)
2280 return (opcode
>> 16) == 0 ? 2 : 4;
2283 /* Return the length of instruction INSN. */
2285 static inline unsigned int
2286 insn_length (const struct mips_cl_insn
*insn
)
2288 if (mips_opts
.micromips
)
2289 return micromips_insn_length (insn
->insn_mo
);
2290 else if (mips_opts
.mips16
)
2291 return mips16_opcode_length (insn
->insn_opcode
);
2296 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2299 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2304 insn
->insn_opcode
= mo
->match
;
2307 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2308 insn
->fixp
[i
] = NULL
;
2309 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2310 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2311 insn
->mips16_absolute_jump_p
= 0;
2312 insn
->complete_p
= 0;
2313 insn
->cleared_p
= 0;
2316 /* Get a list of all the operands in INSN. */
2318 static const struct mips_operand_array
*
2319 insn_operands (const struct mips_cl_insn
*insn
)
2321 if (insn
->insn_mo
>= &mips_opcodes
[0]
2322 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2323 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2325 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2326 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2327 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2329 if (insn
->insn_mo
>= µmips_opcodes
[0]
2330 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2331 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2336 /* Get a description of operand OPNO of INSN. */
2338 static const struct mips_operand
*
2339 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2341 const struct mips_operand_array
*operands
;
2343 operands
= insn_operands (insn
);
2344 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2346 return operands
->operand
[opno
];
2349 /* Install UVAL as the value of OPERAND in INSN. */
2352 insn_insert_operand (struct mips_cl_insn
*insn
,
2353 const struct mips_operand
*operand
, unsigned int uval
)
2355 if (mips_opts
.mips16
2356 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2357 && mips_opcode_32bit_p (insn
->insn_mo
))
2358 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2360 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2363 /* Extract the value of OPERAND from INSN. */
2365 static inline unsigned
2366 insn_extract_operand (const struct mips_cl_insn
*insn
,
2367 const struct mips_operand
*operand
)
2369 return mips_extract_operand (operand
, insn
->insn_opcode
);
2372 /* Record the current MIPS16/microMIPS mode in now_seg. */
2375 mips_record_compressed_mode (void)
2377 segment_info_type
*si
;
2379 si
= seg_info (now_seg
);
2380 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2381 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2382 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2383 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2386 /* Read a standard MIPS instruction from BUF. */
2388 static unsigned long
2389 read_insn (char *buf
)
2391 if (target_big_endian
)
2392 return bfd_getb32 ((bfd_byte
*) buf
);
2394 return bfd_getl32 ((bfd_byte
*) buf
);
2397 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2401 write_insn (char *buf
, unsigned int insn
)
2403 md_number_to_chars (buf
, insn
, 4);
2407 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2408 has length LENGTH. */
2410 static unsigned long
2411 read_compressed_insn (char *buf
, unsigned int length
)
2417 for (i
= 0; i
< length
; i
+= 2)
2420 if (target_big_endian
)
2421 insn
|= bfd_getb16 ((char *) buf
);
2423 insn
|= bfd_getl16 ((char *) buf
);
2429 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2430 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2433 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2437 for (i
= 0; i
< length
; i
+= 2)
2438 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2439 return buf
+ length
;
2442 /* Install INSN at the location specified by its "frag" and "where" fields. */
2445 install_insn (const struct mips_cl_insn
*insn
)
2447 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2448 if (HAVE_CODE_COMPRESSION
)
2449 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2451 write_insn (f
, insn
->insn_opcode
);
2452 mips_record_compressed_mode ();
2455 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2456 and install the opcode in the new location. */
2459 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2464 insn
->where
= where
;
2465 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2466 if (insn
->fixp
[i
] != NULL
)
2468 insn
->fixp
[i
]->fx_frag
= frag
;
2469 insn
->fixp
[i
]->fx_where
= where
;
2471 install_insn (insn
);
2474 /* Add INSN to the end of the output. */
2477 add_fixed_insn (struct mips_cl_insn
*insn
)
2479 char *f
= frag_more (insn_length (insn
));
2480 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2483 /* Start a variant frag and move INSN to the start of the variant part,
2484 marking it as fixed. The other arguments are as for frag_var. */
2487 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2488 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2490 frag_grow (max_chars
);
2491 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2493 frag_var (rs_machine_dependent
, max_chars
, var
,
2494 subtype
, symbol
, offset
, NULL
);
2497 /* Insert N copies of INSN into the history buffer, starting at
2498 position FIRST. Neither FIRST nor N need to be clipped. */
2501 insert_into_history (unsigned int first
, unsigned int n
,
2502 const struct mips_cl_insn
*insn
)
2504 if (mips_relax
.sequence
!= 2)
2508 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2510 history
[i
] = history
[i
- n
];
2516 /* Clear the error in insn_error. */
2519 clear_insn_error (void)
2521 memset (&insn_error
, 0, sizeof (insn_error
));
2524 /* Possibly record error message MSG for the current instruction.
2525 If the error is about a particular argument, ARGNUM is the 1-based
2526 number of that argument, otherwise it is 0. FORMAT is the format
2527 of MSG. Return true if MSG was used, false if the current message
2531 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2536 /* Give priority to errors against specific arguments, and to
2537 the first whole-instruction message. */
2543 /* Keep insn_error if it is against a later argument. */
2544 if (argnum
< insn_error
.min_argnum
)
2547 /* If both errors are against the same argument but are different,
2548 give up on reporting a specific error for this argument.
2549 See the comment about mips_insn_error for details. */
2550 if (argnum
== insn_error
.min_argnum
2552 && strcmp (insn_error
.msg
, msg
) != 0)
2555 insn_error
.min_argnum
+= 1;
2559 insn_error
.min_argnum
= argnum
;
2560 insn_error
.format
= format
;
2561 insn_error
.msg
= msg
;
2565 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2566 as for set_insn_error_format. */
2569 set_insn_error (int argnum
, const char *msg
)
2571 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2574 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2575 as for set_insn_error_format. */
2578 set_insn_error_i (int argnum
, const char *msg
, int i
)
2580 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2584 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2585 are as for set_insn_error_format. */
2588 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2590 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2592 insn_error
.u
.ss
[0] = s1
;
2593 insn_error
.u
.ss
[1] = s2
;
2597 /* Report the error in insn_error, which is against assembly code STR. */
2600 report_insn_error (const char *str
)
2602 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2604 switch (insn_error
.format
)
2611 as_bad (msg
, insn_error
.u
.i
, str
);
2615 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2619 free ((char *) msg
);
2622 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2623 the idea is to make it obvious at a glance that each errata is
2627 init_vr4120_conflicts (void)
2629 #define CONFLICT(FIRST, SECOND) \
2630 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2632 /* Errata 21 - [D]DIV[U] after [D]MACC */
2633 CONFLICT (MACC
, DIV
);
2634 CONFLICT (DMACC
, DIV
);
2636 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2637 CONFLICT (DMULT
, DMULT
);
2638 CONFLICT (DMULT
, DMACC
);
2639 CONFLICT (DMACC
, DMULT
);
2640 CONFLICT (DMACC
, DMACC
);
2642 /* Errata 24 - MT{LO,HI} after [D]MACC */
2643 CONFLICT (MACC
, MTHILO
);
2644 CONFLICT (DMACC
, MTHILO
);
2646 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2647 instruction is executed immediately after a MACC or DMACC
2648 instruction, the result of [either instruction] is incorrect." */
2649 CONFLICT (MACC
, MULT
);
2650 CONFLICT (MACC
, DMULT
);
2651 CONFLICT (DMACC
, MULT
);
2652 CONFLICT (DMACC
, DMULT
);
2654 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2655 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2656 DDIV or DDIVU instruction, the result of the MACC or
2657 DMACC instruction is incorrect.". */
2658 CONFLICT (DMULT
, MACC
);
2659 CONFLICT (DMULT
, DMACC
);
2660 CONFLICT (DIV
, MACC
);
2661 CONFLICT (DIV
, DMACC
);
2671 #define RNUM_MASK 0x00000ff
2672 #define RTYPE_MASK 0x0ffff00
2673 #define RTYPE_NUM 0x0000100
2674 #define RTYPE_FPU 0x0000200
2675 #define RTYPE_FCC 0x0000400
2676 #define RTYPE_VEC 0x0000800
2677 #define RTYPE_GP 0x0001000
2678 #define RTYPE_CP0 0x0002000
2679 #define RTYPE_PC 0x0004000
2680 #define RTYPE_ACC 0x0008000
2681 #define RTYPE_CCC 0x0010000
2682 #define RTYPE_VI 0x0020000
2683 #define RTYPE_VF 0x0040000
2684 #define RTYPE_R5900_I 0x0080000
2685 #define RTYPE_R5900_Q 0x0100000
2686 #define RTYPE_R5900_R 0x0200000
2687 #define RTYPE_R5900_ACC 0x0400000
2688 #define RTYPE_MSA 0x0800000
2689 #define RWARN 0x8000000
2691 #define GENERIC_REGISTER_NUMBERS \
2692 {"$0", RTYPE_NUM | 0}, \
2693 {"$1", RTYPE_NUM | 1}, \
2694 {"$2", RTYPE_NUM | 2}, \
2695 {"$3", RTYPE_NUM | 3}, \
2696 {"$4", RTYPE_NUM | 4}, \
2697 {"$5", RTYPE_NUM | 5}, \
2698 {"$6", RTYPE_NUM | 6}, \
2699 {"$7", RTYPE_NUM | 7}, \
2700 {"$8", RTYPE_NUM | 8}, \
2701 {"$9", RTYPE_NUM | 9}, \
2702 {"$10", RTYPE_NUM | 10}, \
2703 {"$11", RTYPE_NUM | 11}, \
2704 {"$12", RTYPE_NUM | 12}, \
2705 {"$13", RTYPE_NUM | 13}, \
2706 {"$14", RTYPE_NUM | 14}, \
2707 {"$15", RTYPE_NUM | 15}, \
2708 {"$16", RTYPE_NUM | 16}, \
2709 {"$17", RTYPE_NUM | 17}, \
2710 {"$18", RTYPE_NUM | 18}, \
2711 {"$19", RTYPE_NUM | 19}, \
2712 {"$20", RTYPE_NUM | 20}, \
2713 {"$21", RTYPE_NUM | 21}, \
2714 {"$22", RTYPE_NUM | 22}, \
2715 {"$23", RTYPE_NUM | 23}, \
2716 {"$24", RTYPE_NUM | 24}, \
2717 {"$25", RTYPE_NUM | 25}, \
2718 {"$26", RTYPE_NUM | 26}, \
2719 {"$27", RTYPE_NUM | 27}, \
2720 {"$28", RTYPE_NUM | 28}, \
2721 {"$29", RTYPE_NUM | 29}, \
2722 {"$30", RTYPE_NUM | 30}, \
2723 {"$31", RTYPE_NUM | 31}
2725 #define FPU_REGISTER_NAMES \
2726 {"$f0", RTYPE_FPU | 0}, \
2727 {"$f1", RTYPE_FPU | 1}, \
2728 {"$f2", RTYPE_FPU | 2}, \
2729 {"$f3", RTYPE_FPU | 3}, \
2730 {"$f4", RTYPE_FPU | 4}, \
2731 {"$f5", RTYPE_FPU | 5}, \
2732 {"$f6", RTYPE_FPU | 6}, \
2733 {"$f7", RTYPE_FPU | 7}, \
2734 {"$f8", RTYPE_FPU | 8}, \
2735 {"$f9", RTYPE_FPU | 9}, \
2736 {"$f10", RTYPE_FPU | 10}, \
2737 {"$f11", RTYPE_FPU | 11}, \
2738 {"$f12", RTYPE_FPU | 12}, \
2739 {"$f13", RTYPE_FPU | 13}, \
2740 {"$f14", RTYPE_FPU | 14}, \
2741 {"$f15", RTYPE_FPU | 15}, \
2742 {"$f16", RTYPE_FPU | 16}, \
2743 {"$f17", RTYPE_FPU | 17}, \
2744 {"$f18", RTYPE_FPU | 18}, \
2745 {"$f19", RTYPE_FPU | 19}, \
2746 {"$f20", RTYPE_FPU | 20}, \
2747 {"$f21", RTYPE_FPU | 21}, \
2748 {"$f22", RTYPE_FPU | 22}, \
2749 {"$f23", RTYPE_FPU | 23}, \
2750 {"$f24", RTYPE_FPU | 24}, \
2751 {"$f25", RTYPE_FPU | 25}, \
2752 {"$f26", RTYPE_FPU | 26}, \
2753 {"$f27", RTYPE_FPU | 27}, \
2754 {"$f28", RTYPE_FPU | 28}, \
2755 {"$f29", RTYPE_FPU | 29}, \
2756 {"$f30", RTYPE_FPU | 30}, \
2757 {"$f31", RTYPE_FPU | 31}
2759 #define FPU_CONDITION_CODE_NAMES \
2760 {"$fcc0", RTYPE_FCC | 0}, \
2761 {"$fcc1", RTYPE_FCC | 1}, \
2762 {"$fcc2", RTYPE_FCC | 2}, \
2763 {"$fcc3", RTYPE_FCC | 3}, \
2764 {"$fcc4", RTYPE_FCC | 4}, \
2765 {"$fcc5", RTYPE_FCC | 5}, \
2766 {"$fcc6", RTYPE_FCC | 6}, \
2767 {"$fcc7", RTYPE_FCC | 7}
2769 #define COPROC_CONDITION_CODE_NAMES \
2770 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2771 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2772 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2773 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2774 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2775 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2776 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2777 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2779 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2780 {"$a4", RTYPE_GP | 8}, \
2781 {"$a5", RTYPE_GP | 9}, \
2782 {"$a6", RTYPE_GP | 10}, \
2783 {"$a7", RTYPE_GP | 11}, \
2784 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2785 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2786 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2787 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2788 {"$t0", RTYPE_GP | 12}, \
2789 {"$t1", RTYPE_GP | 13}, \
2790 {"$t2", RTYPE_GP | 14}, \
2791 {"$t3", RTYPE_GP | 15}
2793 #define O32_SYMBOLIC_REGISTER_NAMES \
2794 {"$t0", RTYPE_GP | 8}, \
2795 {"$t1", RTYPE_GP | 9}, \
2796 {"$t2", RTYPE_GP | 10}, \
2797 {"$t3", RTYPE_GP | 11}, \
2798 {"$t4", RTYPE_GP | 12}, \
2799 {"$t5", RTYPE_GP | 13}, \
2800 {"$t6", RTYPE_GP | 14}, \
2801 {"$t7", RTYPE_GP | 15}, \
2802 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2803 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2804 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2805 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2807 /* Remaining symbolic register names. */
2808 #define SYMBOLIC_REGISTER_NAMES \
2809 {"$zero", RTYPE_GP | 0}, \
2810 {"$at", RTYPE_GP | 1}, \
2811 {"$AT", RTYPE_GP | 1}, \
2812 {"$v0", RTYPE_GP | 2}, \
2813 {"$v1", RTYPE_GP | 3}, \
2814 {"$a0", RTYPE_GP | 4}, \
2815 {"$a1", RTYPE_GP | 5}, \
2816 {"$a2", RTYPE_GP | 6}, \
2817 {"$a3", RTYPE_GP | 7}, \
2818 {"$s0", RTYPE_GP | 16}, \
2819 {"$s1", RTYPE_GP | 17}, \
2820 {"$s2", RTYPE_GP | 18}, \
2821 {"$s3", RTYPE_GP | 19}, \
2822 {"$s4", RTYPE_GP | 20}, \
2823 {"$s5", RTYPE_GP | 21}, \
2824 {"$s6", RTYPE_GP | 22}, \
2825 {"$s7", RTYPE_GP | 23}, \
2826 {"$t8", RTYPE_GP | 24}, \
2827 {"$t9", RTYPE_GP | 25}, \
2828 {"$k0", RTYPE_GP | 26}, \
2829 {"$kt0", RTYPE_GP | 26}, \
2830 {"$k1", RTYPE_GP | 27}, \
2831 {"$kt1", RTYPE_GP | 27}, \
2832 {"$gp", RTYPE_GP | 28}, \
2833 {"$sp", RTYPE_GP | 29}, \
2834 {"$s8", RTYPE_GP | 30}, \
2835 {"$fp", RTYPE_GP | 30}, \
2836 {"$ra", RTYPE_GP | 31}
2838 #define MIPS16_SPECIAL_REGISTER_NAMES \
2839 {"$pc", RTYPE_PC | 0}
2841 #define MDMX_VECTOR_REGISTER_NAMES \
2842 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2843 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2844 {"$v2", RTYPE_VEC | 2}, \
2845 {"$v3", RTYPE_VEC | 3}, \
2846 {"$v4", RTYPE_VEC | 4}, \
2847 {"$v5", RTYPE_VEC | 5}, \
2848 {"$v6", RTYPE_VEC | 6}, \
2849 {"$v7", RTYPE_VEC | 7}, \
2850 {"$v8", RTYPE_VEC | 8}, \
2851 {"$v9", RTYPE_VEC | 9}, \
2852 {"$v10", RTYPE_VEC | 10}, \
2853 {"$v11", RTYPE_VEC | 11}, \
2854 {"$v12", RTYPE_VEC | 12}, \
2855 {"$v13", RTYPE_VEC | 13}, \
2856 {"$v14", RTYPE_VEC | 14}, \
2857 {"$v15", RTYPE_VEC | 15}, \
2858 {"$v16", RTYPE_VEC | 16}, \
2859 {"$v17", RTYPE_VEC | 17}, \
2860 {"$v18", RTYPE_VEC | 18}, \
2861 {"$v19", RTYPE_VEC | 19}, \
2862 {"$v20", RTYPE_VEC | 20}, \
2863 {"$v21", RTYPE_VEC | 21}, \
2864 {"$v22", RTYPE_VEC | 22}, \
2865 {"$v23", RTYPE_VEC | 23}, \
2866 {"$v24", RTYPE_VEC | 24}, \
2867 {"$v25", RTYPE_VEC | 25}, \
2868 {"$v26", RTYPE_VEC | 26}, \
2869 {"$v27", RTYPE_VEC | 27}, \
2870 {"$v28", RTYPE_VEC | 28}, \
2871 {"$v29", RTYPE_VEC | 29}, \
2872 {"$v30", RTYPE_VEC | 30}, \
2873 {"$v31", RTYPE_VEC | 31}
2875 #define R5900_I_NAMES \
2876 {"$I", RTYPE_R5900_I | 0}
2878 #define R5900_Q_NAMES \
2879 {"$Q", RTYPE_R5900_Q | 0}
2881 #define R5900_R_NAMES \
2882 {"$R", RTYPE_R5900_R | 0}
2884 #define R5900_ACC_NAMES \
2885 {"$ACC", RTYPE_R5900_ACC | 0 }
2887 #define MIPS_DSP_ACCUMULATOR_NAMES \
2888 {"$ac0", RTYPE_ACC | 0}, \
2889 {"$ac1", RTYPE_ACC | 1}, \
2890 {"$ac2", RTYPE_ACC | 2}, \
2891 {"$ac3", RTYPE_ACC | 3}
2893 static const struct regname reg_names
[] = {
2894 GENERIC_REGISTER_NUMBERS
,
2896 FPU_CONDITION_CODE_NAMES
,
2897 COPROC_CONDITION_CODE_NAMES
,
2899 /* The $txx registers depends on the abi,
2900 these will be added later into the symbol table from
2901 one of the tables below once mips_abi is set after
2902 parsing of arguments from the command line. */
2903 SYMBOLIC_REGISTER_NAMES
,
2905 MIPS16_SPECIAL_REGISTER_NAMES
,
2906 MDMX_VECTOR_REGISTER_NAMES
,
2911 MIPS_DSP_ACCUMULATOR_NAMES
,
2915 static const struct regname reg_names_o32
[] = {
2916 O32_SYMBOLIC_REGISTER_NAMES
,
2920 static const struct regname reg_names_n32n64
[] = {
2921 N32N64_SYMBOLIC_REGISTER_NAMES
,
2925 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2926 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2927 of these register symbols, return the associated vector register,
2928 otherwise return SYMVAL itself. */
2931 mips_prefer_vec_regno (unsigned int symval
)
2933 if ((symval
& -2) == (RTYPE_GP
| 2))
2934 return RTYPE_VEC
| (symval
& 1);
2938 /* Return true if string [S, E) is a valid register name, storing its
2939 symbol value in *SYMVAL_PTR if so. */
2942 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2947 /* Terminate name. */
2951 /* Look up the name. */
2952 symbol
= symbol_find (s
);
2955 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2958 *symval_ptr
= S_GET_VALUE (symbol
);
2962 /* Return true if the string at *SPTR is a valid register name. Allow it
2963 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2966 When returning true, move *SPTR past the register, store the
2967 register's symbol value in *SYMVAL_PTR and the channel mask in
2968 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2969 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2970 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2973 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2974 unsigned int *channels_ptr
)
2978 unsigned int channels
, symval
, bit
;
2980 /* Find end of name. */
2982 if (is_name_beginner (*e
))
2984 while (is_part_of_name (*e
))
2988 if (!mips_parse_register_1 (s
, e
, &symval
))
2993 /* Eat characters from the end of the string that are valid
2994 channel suffixes. The preceding register must be $ACC or
2995 end with a digit, so there is no ambiguity. */
2998 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2999 if (m
> s
&& m
[-1] == *q
)
3006 || !mips_parse_register_1 (s
, m
, &symval
)
3007 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
3012 *symval_ptr
= symval
;
3014 *channels_ptr
= channels
;
3018 /* Check if SPTR points at a valid register specifier according to TYPES.
3019 If so, then return 1, advance S to consume the specifier and store
3020 the register's number in REGNOP, otherwise return 0. */
3023 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
3027 if (mips_parse_register (s
, ®no
, NULL
))
3029 if (types
& RTYPE_VEC
)
3030 regno
= mips_prefer_vec_regno (regno
);
3039 as_warn (_("unrecognized register name `%s'"), *s
);
3044 return regno
<= RNUM_MASK
;
3047 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3048 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3051 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3056 for (i
= 0; i
< 4; i
++)
3057 if (*s
== "xyzw"[i
])
3059 *channels
|= 1 << (3 - i
);
3065 /* Token types for parsed operand lists. */
3066 enum mips_operand_token_type
{
3067 /* A plain register, e.g. $f2. */
3070 /* A 4-bit XYZW channel mask. */
3073 /* A constant vector index, e.g. [1]. */
3076 /* A register vector index, e.g. [$2]. */
3079 /* A continuous range of registers, e.g. $s0-$s4. */
3082 /* A (possibly relocated) expression. */
3085 /* A floating-point value. */
3088 /* A single character. This can be '(', ')' or ',', but '(' only appears
3092 /* A doubled character, either "--" or "++". */
3095 /* The end of the operand list. */
3099 /* A parsed operand token. */
3100 struct mips_operand_token
3102 /* The type of token. */
3103 enum mips_operand_token_type type
;
3106 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3109 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3110 unsigned int channels
;
3112 /* The integer value of an OT_INTEGER_INDEX. */
3115 /* The two register symbol values involved in an OT_REG_RANGE. */
3117 unsigned int regno1
;
3118 unsigned int regno2
;
3121 /* The value of an OT_INTEGER. The value is represented as an
3122 expression and the relocation operators that were applied to
3123 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3124 relocation operators were used. */
3127 bfd_reloc_code_real_type relocs
[3];
3130 /* The binary data for an OT_FLOAT constant, and the number of bytes
3133 unsigned char data
[8];
3137 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3142 /* An obstack used to construct lists of mips_operand_tokens. */
3143 static struct obstack mips_operand_tokens
;
3145 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3148 mips_add_token (struct mips_operand_token
*token
,
3149 enum mips_operand_token_type type
)
3152 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3155 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3156 and OT_REG tokens for them if so, and return a pointer to the first
3157 unconsumed character. Return null otherwise. */
3160 mips_parse_base_start (char *s
)
3162 struct mips_operand_token token
;
3163 unsigned int regno
, channels
;
3164 bfd_boolean decrement_p
;
3170 SKIP_SPACE_TABS (s
);
3172 /* Only match "--" as part of a base expression. In other contexts "--X"
3173 is a double negative. */
3174 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3178 SKIP_SPACE_TABS (s
);
3181 /* Allow a channel specifier because that leads to better error messages
3182 than treating something like "$vf0x++" as an expression. */
3183 if (!mips_parse_register (&s
, ®no
, &channels
))
3187 mips_add_token (&token
, OT_CHAR
);
3192 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3195 token
.u
.regno
= regno
;
3196 mips_add_token (&token
, OT_REG
);
3200 token
.u
.channels
= channels
;
3201 mips_add_token (&token
, OT_CHANNELS
);
3204 /* For consistency, only match "++" as part of base expressions too. */
3205 SKIP_SPACE_TABS (s
);
3206 if (s
[0] == '+' && s
[1] == '+')
3210 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3216 /* Parse one or more tokens from S. Return a pointer to the first
3217 unconsumed character on success. Return null if an error was found
3218 and store the error text in insn_error. FLOAT_FORMAT is as for
3219 mips_parse_arguments. */
3222 mips_parse_argument_token (char *s
, char float_format
)
3224 char *end
, *save_in
;
3226 unsigned int regno1
, regno2
, channels
;
3227 struct mips_operand_token token
;
3229 /* First look for "($reg", since we want to treat that as an
3230 OT_CHAR and OT_REG rather than an expression. */
3231 end
= mips_parse_base_start (s
);
3235 /* Handle other characters that end up as OT_CHARs. */
3236 if (*s
== ')' || *s
== ',')
3239 mips_add_token (&token
, OT_CHAR
);
3244 /* Handle tokens that start with a register. */
3245 if (mips_parse_register (&s
, ®no1
, &channels
))
3249 /* A register and a VU0 channel suffix. */
3250 token
.u
.regno
= regno1
;
3251 mips_add_token (&token
, OT_REG
);
3253 token
.u
.channels
= channels
;
3254 mips_add_token (&token
, OT_CHANNELS
);
3258 SKIP_SPACE_TABS (s
);
3261 /* A register range. */
3263 SKIP_SPACE_TABS (s
);
3264 if (!mips_parse_register (&s
, ®no2
, NULL
))
3266 set_insn_error (0, _("invalid register range"));
3270 token
.u
.reg_range
.regno1
= regno1
;
3271 token
.u
.reg_range
.regno2
= regno2
;
3272 mips_add_token (&token
, OT_REG_RANGE
);
3276 /* Add the register itself. */
3277 token
.u
.regno
= regno1
;
3278 mips_add_token (&token
, OT_REG
);
3280 /* Check for a vector index. */
3284 SKIP_SPACE_TABS (s
);
3285 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3286 mips_add_token (&token
, OT_REG_INDEX
);
3289 expressionS element
;
3291 my_getExpression (&element
, s
);
3292 if (element
.X_op
!= O_constant
)
3294 set_insn_error (0, _("vector element must be constant"));
3298 token
.u
.index
= element
.X_add_number
;
3299 mips_add_token (&token
, OT_INTEGER_INDEX
);
3301 SKIP_SPACE_TABS (s
);
3304 set_insn_error (0, _("missing `]'"));
3314 /* First try to treat expressions as floats. */
3315 save_in
= input_line_pointer
;
3316 input_line_pointer
= s
;
3317 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3318 &token
.u
.flt
.length
);
3319 end
= input_line_pointer
;
3320 input_line_pointer
= save_in
;
3323 set_insn_error (0, err
);
3328 mips_add_token (&token
, OT_FLOAT
);
3333 /* Treat everything else as an integer expression. */
3334 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3335 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3336 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3337 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3339 mips_add_token (&token
, OT_INTEGER
);
3343 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3344 if expressions should be treated as 32-bit floating-point constants,
3345 'd' if they should be treated as 64-bit floating-point constants,
3346 or 0 if they should be treated as integer expressions (the usual case).
3348 Return a list of tokens on success, otherwise return 0. The caller
3349 must obstack_free the list after use. */
3351 static struct mips_operand_token
*
3352 mips_parse_arguments (char *s
, char float_format
)
3354 struct mips_operand_token token
;
3356 SKIP_SPACE_TABS (s
);
3359 s
= mips_parse_argument_token (s
, float_format
);
3362 obstack_free (&mips_operand_tokens
,
3363 obstack_finish (&mips_operand_tokens
));
3366 SKIP_SPACE_TABS (s
);
3368 mips_add_token (&token
, OT_END
);
3369 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3372 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3373 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3376 is_opcode_valid (const struct mips_opcode
*mo
)
3378 int isa
= mips_opts
.isa
;
3379 int ase
= mips_opts
.ase
;
3383 if (ISA_HAS_64BIT_REGS (isa
))
3384 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3385 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3386 ase
|= mips_ases
[i
].flags64
;
3388 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3391 /* Check whether the instruction or macro requires single-precision or
3392 double-precision floating-point support. Note that this information is
3393 stored differently in the opcode table for insns and macros. */
3394 if (mo
->pinfo
== INSN_MACRO
)
3396 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3397 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3401 fp_s
= mo
->pinfo
& FP_S
;
3402 fp_d
= mo
->pinfo
& FP_D
;
3405 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3408 if (fp_s
&& mips_opts
.soft_float
)
3414 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3415 selected ISA and architecture. */
3418 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3420 int isa
= mips_opts
.isa
;
3421 int ase
= mips_opts
.ase
;
3424 if (ISA_HAS_64BIT_REGS (isa
))
3425 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3426 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3427 ase
|= mips_ases
[i
].flags64
;
3429 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3432 /* Return TRUE if the size of the microMIPS opcode MO matches one
3433 explicitly requested. Always TRUE in the standard MIPS mode.
3434 Use is_size_valid_16 for MIPS16 opcodes. */
3437 is_size_valid (const struct mips_opcode
*mo
)
3439 if (!mips_opts
.micromips
)
3442 if (mips_opts
.insn32
)
3444 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3446 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3449 if (!forced_insn_length
)
3451 if (mo
->pinfo
== INSN_MACRO
)
3453 return forced_insn_length
== micromips_insn_length (mo
);
3456 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3457 explicitly requested. */
3460 is_size_valid_16 (const struct mips_opcode
*mo
)
3462 if (!forced_insn_length
)
3464 if (mo
->pinfo
== INSN_MACRO
)
3466 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3468 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3473 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3474 of the preceding instruction. Always TRUE in the standard MIPS mode.
3476 We don't accept macros in 16-bit delay slots to avoid a case where
3477 a macro expansion fails because it relies on a preceding 32-bit real
3478 instruction to have matched and does not handle the operands correctly.
3479 The only macros that may expand to 16-bit instructions are JAL that
3480 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3481 and BGT (that likewise cannot be placed in a delay slot) that decay to
3482 a NOP. In all these cases the macros precede any corresponding real
3483 instruction definitions in the opcode table, so they will match in the
3484 second pass where the size of the delay slot is ignored and therefore
3485 produce correct code. */
3488 is_delay_slot_valid (const struct mips_opcode
*mo
)
3490 if (!mips_opts
.micromips
)
3493 if (mo
->pinfo
== INSN_MACRO
)
3494 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3495 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3496 && micromips_insn_length (mo
) != 4)
3498 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3499 && micromips_insn_length (mo
) != 2)
3505 /* For consistency checking, verify that all bits of OPCODE are specified
3506 either by the match/mask part of the instruction definition, or by the
3507 operand list. Also build up a list of operands in OPERANDS.
3509 INSN_BITS says which bits of the instruction are significant.
3510 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3511 provides the mips_operand description of each operand. DECODE_OPERAND
3512 is null for MIPS16 instructions. */
3515 validate_mips_insn (const struct mips_opcode
*opcode
,
3516 unsigned long insn_bits
,
3517 const struct mips_operand
*(*decode_operand
) (const char *),
3518 struct mips_operand_array
*operands
)
3521 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3522 const struct mips_operand
*operand
;
3524 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3525 if ((mask
& opcode
->match
) != opcode
->match
)
3527 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3528 opcode
->name
, opcode
->args
);
3533 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3534 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3535 for (s
= opcode
->args
; *s
; ++s
)
3548 if (!decode_operand
)
3549 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3551 operand
= decode_operand (s
);
3552 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3554 as_bad (_("internal: unknown operand type: %s %s"),
3555 opcode
->name
, opcode
->args
);
3558 gas_assert (opno
< MAX_OPERANDS
);
3559 operands
->operand
[opno
] = operand
;
3560 if (!decode_operand
&& operand
3561 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3562 && mips_opcode_32bit_p (opcode
))
3563 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3564 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3566 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3567 if (operand
->type
== OP_MDMX_IMM_REG
)
3568 /* Bit 5 is the format selector (OB vs QH). The opcode table
3569 has separate entries for each format. */
3570 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3571 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3572 used_bits
&= ~(mask
& 0x700);
3573 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3574 operand field that cannot be fully described with LSB/SIZE. */
3575 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3576 used_bits
&= ~0x6000;
3578 /* Skip prefix characters. */
3579 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3584 doubled
= used_bits
& mask
& insn_bits
;
3587 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3588 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3592 undefined
= ~used_bits
& insn_bits
;
3593 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3595 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3596 undefined
, opcode
->name
, opcode
->args
);
3599 used_bits
&= ~insn_bits
;
3602 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3603 used_bits
, opcode
->name
, opcode
->args
);
3609 /* The MIPS16 version of validate_mips_insn. */
3612 validate_mips16_insn (const struct mips_opcode
*opcode
,
3613 struct mips_operand_array
*operands
)
3615 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3617 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3620 /* The microMIPS version of validate_mips_insn. */
3623 validate_micromips_insn (const struct mips_opcode
*opc
,
3624 struct mips_operand_array
*operands
)
3626 unsigned long insn_bits
;
3627 unsigned long major
;
3628 unsigned int length
;
3630 if (opc
->pinfo
== INSN_MACRO
)
3631 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3634 length
= micromips_insn_length (opc
);
3635 if (length
!= 2 && length
!= 4)
3637 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3638 "%s %s"), length
, opc
->name
, opc
->args
);
3641 major
= opc
->match
>> (10 + 8 * (length
- 2));
3642 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3643 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3645 as_bad (_("internal error: bad microMIPS opcode "
3646 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3650 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3651 insn_bits
= 1 << 4 * length
;
3652 insn_bits
<<= 4 * length
;
3654 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3658 /* This function is called once, at assembler startup time. It should set up
3659 all the tables, etc. that the MD part of the assembler will need. */
3664 const char *retval
= NULL
;
3668 if (mips_pic
!= NO_PIC
)
3670 if (g_switch_seen
&& g_switch_value
!= 0)
3671 as_bad (_("-G may not be used in position-independent code"));
3674 else if (mips_abicalls
)
3676 if (g_switch_seen
&& g_switch_value
!= 0)
3677 as_bad (_("-G may not be used with abicalls"));
3681 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3682 as_warn (_("could not set architecture and machine"));
3684 op_hash
= hash_new ();
3686 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3687 for (i
= 0; i
< NUMOPCODES
;)
3689 const char *name
= mips_opcodes
[i
].name
;
3691 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3694 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3695 mips_opcodes
[i
].name
, retval
);
3696 /* Probably a memory allocation problem? Give up now. */
3697 as_fatal (_("broken assembler, no assembly attempted"));
3701 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3702 decode_mips_operand
, &mips_operands
[i
]))
3705 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3707 create_insn (&nop_insn
, mips_opcodes
+ i
);
3708 if (mips_fix_loongson2f_nop
)
3709 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3710 nop_insn
.fixed_p
= 1;
3713 if (sync_insn
.insn_mo
== NULL
&& strcmp (name
, "sync") == 0)
3714 create_insn (&sync_insn
, mips_opcodes
+ i
);
3718 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3721 mips16_op_hash
= hash_new ();
3722 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3723 bfd_mips16_num_opcodes
);
3726 while (i
< bfd_mips16_num_opcodes
)
3728 const char *name
= mips16_opcodes
[i
].name
;
3730 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3732 as_fatal (_("internal: can't hash `%s': %s"),
3733 mips16_opcodes
[i
].name
, retval
);
3736 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3738 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3740 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3741 mips16_nop_insn
.fixed_p
= 1;
3745 while (i
< bfd_mips16_num_opcodes
3746 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3749 micromips_op_hash
= hash_new ();
3750 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3751 bfd_micromips_num_opcodes
);
3754 while (i
< bfd_micromips_num_opcodes
)
3756 const char *name
= micromips_opcodes
[i
].name
;
3758 retval
= hash_insert (micromips_op_hash
, name
,
3759 (void *) µmips_opcodes
[i
]);
3761 as_fatal (_("internal: can't hash `%s': %s"),
3762 micromips_opcodes
[i
].name
, retval
);
3765 struct mips_cl_insn
*micromips_nop_insn
;
3767 if (!validate_micromips_insn (µmips_opcodes
[i
],
3768 µmips_operands
[i
]))
3771 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3773 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3774 micromips_nop_insn
= µmips_nop16_insn
;
3775 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3776 micromips_nop_insn
= µmips_nop32_insn
;
3780 if (micromips_nop_insn
->insn_mo
== NULL
3781 && strcmp (name
, "nop") == 0)
3783 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3784 micromips_nop_insn
->fixed_p
= 1;
3788 while (++i
< bfd_micromips_num_opcodes
3789 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3793 as_fatal (_("broken assembler, no assembly attempted"));
3795 /* We add all the general register names to the symbol table. This
3796 helps us detect invalid uses of them. */
3797 for (i
= 0; reg_names
[i
].name
; i
++)
3798 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3799 reg_names
[i
].num
, /* & RNUM_MASK, */
3800 &zero_address_frag
));
3802 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3803 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3804 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3805 &zero_address_frag
));
3807 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3808 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3809 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3810 &zero_address_frag
));
3812 for (i
= 0; i
< 32; i
++)
3816 /* R5900 VU0 floating-point register. */
3817 sprintf (regname
, "$vf%d", i
);
3818 symbol_table_insert (symbol_new (regname
, reg_section
,
3819 RTYPE_VF
| i
, &zero_address_frag
));
3821 /* R5900 VU0 integer register. */
3822 sprintf (regname
, "$vi%d", i
);
3823 symbol_table_insert (symbol_new (regname
, reg_section
,
3824 RTYPE_VI
| i
, &zero_address_frag
));
3827 sprintf (regname
, "$w%d", i
);
3828 symbol_table_insert (symbol_new (regname
, reg_section
,
3829 RTYPE_MSA
| i
, &zero_address_frag
));
3832 obstack_init (&mips_operand_tokens
);
3834 mips_no_prev_insn ();
3837 mips_cprmask
[0] = 0;
3838 mips_cprmask
[1] = 0;
3839 mips_cprmask
[2] = 0;
3840 mips_cprmask
[3] = 0;
3842 /* set the default alignment for the text section (2**2) */
3843 record_alignment (text_section
, 2);
3845 bfd_set_gp_size (stdoutput
, g_switch_value
);
3847 /* On a native system other than VxWorks, sections must be aligned
3848 to 16 byte boundaries. When configured for an embedded ELF
3849 target, we don't bother. */
3850 if (strncmp (TARGET_OS
, "elf", 3) != 0
3851 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3853 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3854 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3855 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3858 /* Create a .reginfo section for register masks and a .mdebug
3859 section for debugging information. */
3867 subseg
= now_subseg
;
3869 /* The ABI says this section should be loaded so that the
3870 running program can access it. However, we don't load it
3871 if we are configured for an embedded target. */
3872 flags
= SEC_READONLY
| SEC_DATA
;
3873 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3874 flags
|= SEC_ALLOC
| SEC_LOAD
;
3876 if (mips_abi
!= N64_ABI
)
3878 sec
= subseg_new (".reginfo", (subsegT
) 0);
3880 bfd_set_section_flags (stdoutput
, sec
, flags
);
3881 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3883 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3887 /* The 64-bit ABI uses a .MIPS.options section rather than
3888 .reginfo section. */
3889 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3890 bfd_set_section_flags (stdoutput
, sec
, flags
);
3891 bfd_set_section_alignment (stdoutput
, sec
, 3);
3893 /* Set up the option header. */
3895 Elf_Internal_Options opthdr
;
3898 opthdr
.kind
= ODK_REGINFO
;
3899 opthdr
.size
= (sizeof (Elf_External_Options
)
3900 + sizeof (Elf64_External_RegInfo
));
3903 f
= frag_more (sizeof (Elf_External_Options
));
3904 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3905 (Elf_External_Options
*) f
);
3907 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3911 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3912 bfd_set_section_flags (stdoutput
, sec
,
3913 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3914 bfd_set_section_alignment (stdoutput
, sec
, 3);
3915 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3917 if (ECOFF_DEBUGGING
)
3919 sec
= subseg_new (".mdebug", (subsegT
) 0);
3920 (void) bfd_set_section_flags (stdoutput
, sec
,
3921 SEC_HAS_CONTENTS
| SEC_READONLY
);
3922 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3924 else if (mips_flag_pdr
)
3926 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3927 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3928 SEC_READONLY
| SEC_RELOC
3930 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3933 subseg_set (seg
, subseg
);
3936 if (mips_fix_vr4120
)
3937 init_vr4120_conflicts ();
3941 fpabi_incompatible_with (int fpabi
, const char *what
)
3943 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3944 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3948 fpabi_requires (int fpabi
, const char *what
)
3950 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3951 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3954 /* Check -mabi and register sizes against the specified FP ABI. */
3956 check_fpabi (int fpabi
)
3960 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3961 if (file_mips_opts
.soft_float
)
3962 fpabi_incompatible_with (fpabi
, "softfloat");
3963 else if (file_mips_opts
.single_float
)
3964 fpabi_incompatible_with (fpabi
, "singlefloat");
3965 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3966 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3967 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3968 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3971 case Val_GNU_MIPS_ABI_FP_XX
:
3972 if (mips_abi
!= O32_ABI
)
3973 fpabi_requires (fpabi
, "-mabi=32");
3974 else if (file_mips_opts
.soft_float
)
3975 fpabi_incompatible_with (fpabi
, "softfloat");
3976 else if (file_mips_opts
.single_float
)
3977 fpabi_incompatible_with (fpabi
, "singlefloat");
3978 else if (file_mips_opts
.fp
!= 0)
3979 fpabi_requires (fpabi
, "fp=xx");
3982 case Val_GNU_MIPS_ABI_FP_64A
:
3983 case Val_GNU_MIPS_ABI_FP_64
:
3984 if (mips_abi
!= O32_ABI
)
3985 fpabi_requires (fpabi
, "-mabi=32");
3986 else if (file_mips_opts
.soft_float
)
3987 fpabi_incompatible_with (fpabi
, "softfloat");
3988 else if (file_mips_opts
.single_float
)
3989 fpabi_incompatible_with (fpabi
, "singlefloat");
3990 else if (file_mips_opts
.fp
!= 64)
3991 fpabi_requires (fpabi
, "fp=64");
3992 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3993 fpabi_incompatible_with (fpabi
, "nooddspreg");
3994 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3995 fpabi_requires (fpabi
, "nooddspreg");
3998 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3999 if (file_mips_opts
.soft_float
)
4000 fpabi_incompatible_with (fpabi
, "softfloat");
4001 else if (!file_mips_opts
.single_float
)
4002 fpabi_requires (fpabi
, "singlefloat");
4005 case Val_GNU_MIPS_ABI_FP_SOFT
:
4006 if (!file_mips_opts
.soft_float
)
4007 fpabi_requires (fpabi
, "softfloat");
4010 case Val_GNU_MIPS_ABI_FP_OLD_64
:
4011 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4012 Tag_GNU_MIPS_ABI_FP
, fpabi
);
4015 case Val_GNU_MIPS_ABI_FP_NAN2008
:
4016 /* Silently ignore compatibility value. */
4020 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4021 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
4026 /* Perform consistency checks on the current options. */
4029 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
4031 /* Check the size of integer registers agrees with the ABI and ISA. */
4032 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
4033 as_bad (_("`gp=64' used with a 32-bit processor"));
4035 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4036 as_bad (_("`gp=32' used with a 64-bit ABI"));
4038 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4039 as_bad (_("`gp=64' used with a 32-bit ABI"));
4041 /* Check the size of the float registers agrees with the ABI and ISA. */
4045 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4046 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4047 else if (opts
->single_float
== 1)
4048 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4051 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4052 as_bad (_("`fp=64' used with a 32-bit fpu"));
4054 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4055 && !ISA_HAS_MXHC1 (opts
->isa
))
4056 as_warn (_("`fp=64' used with a 32-bit ABI"));
4060 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4061 as_warn (_("`fp=32' used with a 64-bit ABI"));
4062 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4063 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4066 as_bad (_("Unknown size of floating point registers"));
4070 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4071 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4073 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4074 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4075 else if (ISA_IS_R6 (opts
->isa
)
4076 && (opts
->micromips
== 1
4077 || opts
->mips16
== 1))
4078 as_fatal (_("`%s' cannot be used with `%s'"),
4079 opts
->micromips
? "micromips" : "mips16",
4080 mips_cpu_info_from_isa (opts
->isa
)->name
);
4082 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4083 as_fatal (_("branch relaxation is not supported in `%s'"),
4084 mips_cpu_info_from_isa (opts
->isa
)->name
);
4087 /* Perform consistency checks on the module level options exactly once.
4088 This is a deferred check that happens:
4089 at the first .set directive
4090 or, at the first pseudo op that generates code (inc .dc.a)
4091 or, at the first instruction
4095 file_mips_check_options (void)
4097 if (file_mips_opts_checked
)
4100 /* The following code determines the register size.
4101 Similar code was added to GCC 3.3 (see override_options() in
4102 config/mips/mips.c). The GAS and GCC code should be kept in sync
4103 as much as possible. */
4105 if (file_mips_opts
.gp
< 0)
4107 /* Infer the integer register size from the ABI and processor.
4108 Restrict ourselves to 32-bit registers if that's all the
4109 processor has, or if the ABI cannot handle 64-bit registers. */
4110 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4111 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4115 if (file_mips_opts
.fp
< 0)
4117 /* No user specified float register size.
4118 ??? GAS treats single-float processors as though they had 64-bit
4119 float registers (although it complains when double-precision
4120 instructions are used). As things stand, saying they have 32-bit
4121 registers would lead to spurious "register must be even" messages.
4122 So here we assume float registers are never smaller than the
4124 if (file_mips_opts
.gp
== 64)
4125 /* 64-bit integer registers implies 64-bit float registers. */
4126 file_mips_opts
.fp
= 64;
4127 else if ((file_mips_opts
.ase
& FP64_ASES
)
4128 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4129 /* Handle ASEs that require 64-bit float registers, if possible. */
4130 file_mips_opts
.fp
= 64;
4131 else if (ISA_IS_R6 (mips_opts
.isa
))
4132 /* R6 implies 64-bit float registers. */
4133 file_mips_opts
.fp
= 64;
4135 /* 32-bit float registers. */
4136 file_mips_opts
.fp
= 32;
4139 /* Disable operations on odd-numbered floating-point registers by default
4140 when using the FPXX ABI. */
4141 if (file_mips_opts
.oddspreg
< 0)
4143 if (file_mips_opts
.fp
== 0)
4144 file_mips_opts
.oddspreg
= 0;
4146 file_mips_opts
.oddspreg
= 1;
4149 /* End of GCC-shared inference code. */
4151 /* This flag is set when we have a 64-bit capable CPU but use only
4152 32-bit wide registers. Note that EABI does not use it. */
4153 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4154 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4155 || mips_abi
== O32_ABI
))
4158 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4159 as_bad (_("trap exception not supported at ISA 1"));
4161 /* If the selected architecture includes support for ASEs, enable
4162 generation of code for them. */
4163 if (file_mips_opts
.mips16
== -1)
4164 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4165 if (file_mips_opts
.micromips
== -1)
4166 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4169 if (mips_nan2008
== -1)
4170 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4171 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4172 as_fatal (_("`%s' does not support legacy NaN"),
4173 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4175 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4176 being selected implicitly. */
4177 if (file_mips_opts
.fp
!= 64)
4178 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4180 /* If the user didn't explicitly select or deselect a particular ASE,
4181 use the default setting for the CPU. */
4182 file_mips_opts
.ase
|= (file_mips_opts
.init_ase
& ~file_ase_explicit
);
4184 /* Set up the current options. These may change throughout assembly. */
4185 mips_opts
= file_mips_opts
;
4187 mips_check_isa_supports_ases ();
4188 mips_check_options (&file_mips_opts
, TRUE
);
4189 file_mips_opts_checked
= TRUE
;
4191 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4192 as_warn (_("could not set architecture and machine"));
4196 md_assemble (char *str
)
4198 struct mips_cl_insn insn
;
4199 bfd_reloc_code_real_type unused_reloc
[3]
4200 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4202 file_mips_check_options ();
4204 imm_expr
.X_op
= O_absent
;
4205 offset_expr
.X_op
= O_absent
;
4206 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4207 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4208 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4210 mips_mark_labels ();
4211 mips_assembling_insn
= TRUE
;
4212 clear_insn_error ();
4214 if (mips_opts
.mips16
)
4215 mips16_ip (str
, &insn
);
4218 mips_ip (str
, &insn
);
4219 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4220 str
, insn
.insn_opcode
));
4224 report_insn_error (str
);
4225 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4228 if (mips_opts
.mips16
)
4229 mips16_macro (&insn
);
4236 if (offset_expr
.X_op
!= O_absent
)
4237 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4239 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4242 mips_assembling_insn
= FALSE
;
4245 /* Convenience functions for abstracting away the differences between
4246 MIPS16 and non-MIPS16 relocations. */
4248 static inline bfd_boolean
4249 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4253 case BFD_RELOC_MIPS16_JMP
:
4254 case BFD_RELOC_MIPS16_GPREL
:
4255 case BFD_RELOC_MIPS16_GOT16
:
4256 case BFD_RELOC_MIPS16_CALL16
:
4257 case BFD_RELOC_MIPS16_HI16_S
:
4258 case BFD_RELOC_MIPS16_HI16
:
4259 case BFD_RELOC_MIPS16_LO16
:
4260 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4268 static inline bfd_boolean
4269 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4273 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4274 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4275 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4276 case BFD_RELOC_MICROMIPS_GPREL16
:
4277 case BFD_RELOC_MICROMIPS_JMP
:
4278 case BFD_RELOC_MICROMIPS_HI16
:
4279 case BFD_RELOC_MICROMIPS_HI16_S
:
4280 case BFD_RELOC_MICROMIPS_LO16
:
4281 case BFD_RELOC_MICROMIPS_LITERAL
:
4282 case BFD_RELOC_MICROMIPS_GOT16
:
4283 case BFD_RELOC_MICROMIPS_CALL16
:
4284 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4285 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4286 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4287 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4288 case BFD_RELOC_MICROMIPS_SUB
:
4289 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4290 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4291 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4292 case BFD_RELOC_MICROMIPS_HIGHEST
:
4293 case BFD_RELOC_MICROMIPS_HIGHER
:
4294 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4295 case BFD_RELOC_MICROMIPS_JALR
:
4303 static inline bfd_boolean
4304 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4306 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4309 static inline bfd_boolean
4310 b_reloc_p (bfd_reloc_code_real_type reloc
)
4312 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4313 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4314 || reloc
== BFD_RELOC_16_PCREL_S2
4315 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4316 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4317 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4318 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4321 static inline bfd_boolean
4322 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4324 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4325 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4328 static inline bfd_boolean
4329 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4331 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4332 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4335 static inline bfd_boolean
4336 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4338 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4339 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4342 static inline bfd_boolean
4343 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4345 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4348 static inline bfd_boolean
4349 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4351 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4352 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4355 /* Return true if RELOC is a PC-relative relocation that does not have
4356 full address range. */
4358 static inline bfd_boolean
4359 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4363 case BFD_RELOC_16_PCREL_S2
:
4364 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4365 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4366 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4367 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4368 case BFD_RELOC_MIPS_21_PCREL_S2
:
4369 case BFD_RELOC_MIPS_26_PCREL_S2
:
4370 case BFD_RELOC_MIPS_18_PCREL_S3
:
4371 case BFD_RELOC_MIPS_19_PCREL_S2
:
4374 case BFD_RELOC_32_PCREL
:
4375 case BFD_RELOC_HI16_S_PCREL
:
4376 case BFD_RELOC_LO16_PCREL
:
4377 return HAVE_64BIT_ADDRESSES
;
4384 /* Return true if the given relocation might need a matching %lo().
4385 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4386 need a matching %lo() when applied to local symbols. */
4388 static inline bfd_boolean
4389 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4391 return (HAVE_IN_PLACE_ADDENDS
4392 && (hi16_reloc_p (reloc
)
4393 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4394 all GOT16 relocations evaluate to "G". */
4395 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4398 /* Return the type of %lo() reloc needed by RELOC, given that
4399 reloc_needs_lo_p. */
4401 static inline bfd_reloc_code_real_type
4402 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4404 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4405 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4409 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4412 static inline bfd_boolean
4413 fixup_has_matching_lo_p (fixS
*fixp
)
4415 return (fixp
->fx_next
!= NULL
4416 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4417 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4418 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4421 /* Move all labels in LABELS to the current insertion point. TEXT_P
4422 says whether the labels refer to text or data. */
4425 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4427 struct insn_label_list
*l
;
4430 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4432 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4433 symbol_set_frag (l
->label
, frag_now
);
4434 val
= (valueT
) frag_now_fix ();
4435 /* MIPS16/microMIPS text labels are stored as odd. */
4436 if (text_p
&& HAVE_CODE_COMPRESSION
)
4438 S_SET_VALUE (l
->label
, val
);
4442 /* Move all labels in insn_labels to the current insertion point
4443 and treat them as text labels. */
4446 mips_move_text_labels (void)
4448 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4451 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4454 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4456 bfd_boolean linkonce
= FALSE
;
4457 segT symseg
= S_GET_SEGMENT (sym
);
4459 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4461 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4463 /* The GNU toolchain uses an extension for ELF: a section
4464 beginning with the magic string .gnu.linkonce is a
4465 linkonce section. */
4466 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4467 sizeof ".gnu.linkonce" - 1) == 0)
4473 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4474 linker to handle them specially, such as generating jalx instructions
4475 when needed. We also make them odd for the duration of the assembly,
4476 in order to generate the right sort of code. We will make them even
4477 in the adjust_symtab routine, while leaving them marked. This is
4478 convenient for the debugger and the disassembler. The linker knows
4479 to make them odd again. */
4482 mips_compressed_mark_label (symbolS
*label
)
4484 gas_assert (HAVE_CODE_COMPRESSION
);
4486 if (mips_opts
.mips16
)
4487 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4489 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4490 if ((S_GET_VALUE (label
) & 1) == 0
4491 /* Don't adjust the address if the label is global or weak, or
4492 in a link-once section, since we'll be emitting symbol reloc
4493 references to it which will be patched up by the linker, and
4494 the final value of the symbol may or may not be MIPS16/microMIPS. */
4495 && !S_IS_WEAK (label
)
4496 && !S_IS_EXTERNAL (label
)
4497 && !s_is_linkonce (label
, now_seg
))
4498 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4501 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4504 mips_compressed_mark_labels (void)
4506 struct insn_label_list
*l
;
4508 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4509 mips_compressed_mark_label (l
->label
);
4512 /* End the current frag. Make it a variant frag and record the
4516 relax_close_frag (void)
4518 mips_macro_warning
.first_frag
= frag_now
;
4519 frag_var (rs_machine_dependent
, 0, 0,
4520 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4521 mips_pic
!= NO_PIC
),
4522 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4524 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4525 mips_relax
.first_fixup
= 0;
4528 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4529 See the comment above RELAX_ENCODE for more details. */
4532 relax_start (symbolS
*symbol
)
4534 gas_assert (mips_relax
.sequence
== 0);
4535 mips_relax
.sequence
= 1;
4536 mips_relax
.symbol
= symbol
;
4539 /* Start generating the second version of a relaxable sequence.
4540 See the comment above RELAX_ENCODE for more details. */
4545 gas_assert (mips_relax
.sequence
== 1);
4546 mips_relax
.sequence
= 2;
4549 /* End the current relaxable sequence. */
4554 gas_assert (mips_relax
.sequence
== 2);
4555 relax_close_frag ();
4556 mips_relax
.sequence
= 0;
4559 /* Return true if IP is a delayed branch or jump. */
4561 static inline bfd_boolean
4562 delayed_branch_p (const struct mips_cl_insn
*ip
)
4564 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4565 | INSN_COND_BRANCH_DELAY
4566 | INSN_COND_BRANCH_LIKELY
)) != 0;
4569 /* Return true if IP is a compact branch or jump. */
4571 static inline bfd_boolean
4572 compact_branch_p (const struct mips_cl_insn
*ip
)
4574 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4575 | INSN2_COND_BRANCH
)) != 0;
4578 /* Return true if IP is an unconditional branch or jump. */
4580 static inline bfd_boolean
4581 uncond_branch_p (const struct mips_cl_insn
*ip
)
4583 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4584 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4587 /* Return true if IP is a branch-likely instruction. */
4589 static inline bfd_boolean
4590 branch_likely_p (const struct mips_cl_insn
*ip
)
4592 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4595 /* Return the type of nop that should be used to fill the delay slot
4596 of delayed branch IP. */
4598 static struct mips_cl_insn
*
4599 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4601 if (mips_opts
.micromips
4602 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4603 return µmips_nop32_insn
;
4607 /* Return a mask that has bit N set if OPCODE reads the register(s)
4611 insn_read_mask (const struct mips_opcode
*opcode
)
4613 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4616 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4620 insn_write_mask (const struct mips_opcode
*opcode
)
4622 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4625 /* Return a mask of the registers specified by operand OPERAND of INSN.
4626 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4630 operand_reg_mask (const struct mips_cl_insn
*insn
,
4631 const struct mips_operand
*operand
,
4632 unsigned int type_mask
)
4634 unsigned int uval
, vsel
;
4636 switch (operand
->type
)
4643 case OP_ADDIUSP_INT
:
4644 case OP_ENTRY_EXIT_LIST
:
4645 case OP_REPEAT_DEST_REG
:
4646 case OP_REPEAT_PREV_REG
:
4649 case OP_VU0_MATCH_SUFFIX
:
4657 case OP_OPTIONAL_REG
:
4659 const struct mips_reg_operand
*reg_op
;
4661 reg_op
= (const struct mips_reg_operand
*) operand
;
4662 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4664 uval
= insn_extract_operand (insn
, operand
);
4665 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4670 const struct mips_reg_pair_operand
*pair_op
;
4672 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4673 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4675 uval
= insn_extract_operand (insn
, operand
);
4676 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4679 case OP_CLO_CLZ_DEST
:
4680 if (!(type_mask
& (1 << OP_REG_GP
)))
4682 uval
= insn_extract_operand (insn
, operand
);
4683 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4686 if (!(type_mask
& (1 << OP_REG_GP
)))
4688 uval
= insn_extract_operand (insn
, operand
);
4689 gas_assert ((uval
& 31) == (uval
>> 5));
4690 return 1 << (uval
& 31);
4693 case OP_NON_ZERO_REG
:
4694 if (!(type_mask
& (1 << OP_REG_GP
)))
4696 uval
= insn_extract_operand (insn
, operand
);
4697 return 1 << (uval
& 31);
4699 case OP_LWM_SWM_LIST
:
4702 case OP_SAVE_RESTORE_LIST
:
4705 case OP_MDMX_IMM_REG
:
4706 if (!(type_mask
& (1 << OP_REG_VEC
)))
4708 uval
= insn_extract_operand (insn
, operand
);
4710 if ((vsel
& 0x18) == 0x18)
4712 return 1 << (uval
& 31);
4715 if (!(type_mask
& (1 << OP_REG_GP
)))
4717 return 1 << insn_extract_operand (insn
, operand
);
4722 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4723 where bit N of OPNO_MASK is set if operand N should be included.
4724 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4728 insn_reg_mask (const struct mips_cl_insn
*insn
,
4729 unsigned int type_mask
, unsigned int opno_mask
)
4731 unsigned int opno
, reg_mask
;
4735 while (opno_mask
!= 0)
4738 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4745 /* Return the mask of core registers that IP reads. */
4748 gpr_read_mask (const struct mips_cl_insn
*ip
)
4750 unsigned long pinfo
, pinfo2
;
4753 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4754 pinfo
= ip
->insn_mo
->pinfo
;
4755 pinfo2
= ip
->insn_mo
->pinfo2
;
4756 if (pinfo
& INSN_UDI
)
4758 /* UDI instructions have traditionally been assumed to read RS
4760 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4761 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4763 if (pinfo
& INSN_READ_GPR_24
)
4765 if (pinfo2
& INSN2_READ_GPR_16
)
4767 if (pinfo2
& INSN2_READ_SP
)
4769 if (pinfo2
& INSN2_READ_GPR_31
)
4771 /* Don't include register 0. */
4775 /* Return the mask of core registers that IP writes. */
4778 gpr_write_mask (const struct mips_cl_insn
*ip
)
4780 unsigned long pinfo
, pinfo2
;
4783 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4784 pinfo
= ip
->insn_mo
->pinfo
;
4785 pinfo2
= ip
->insn_mo
->pinfo2
;
4786 if (pinfo
& INSN_WRITE_GPR_24
)
4788 if (pinfo
& INSN_WRITE_GPR_31
)
4790 if (pinfo
& INSN_UDI
)
4791 /* UDI instructions have traditionally been assumed to write to RD. */
4792 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4793 if (pinfo2
& INSN2_WRITE_SP
)
4795 /* Don't include register 0. */
4799 /* Return the mask of floating-point registers that IP reads. */
4802 fpr_read_mask (const struct mips_cl_insn
*ip
)
4804 unsigned long pinfo
;
4807 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4808 | (1 << OP_REG_MSA
)),
4809 insn_read_mask (ip
->insn_mo
));
4810 pinfo
= ip
->insn_mo
->pinfo
;
4811 /* Conservatively treat all operands to an FP_D instruction are doubles.
4812 (This is overly pessimistic for things like cvt.d.s.) */
4813 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4818 /* Return the mask of floating-point registers that IP writes. */
4821 fpr_write_mask (const struct mips_cl_insn
*ip
)
4823 unsigned long pinfo
;
4826 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4827 | (1 << OP_REG_MSA
)),
4828 insn_write_mask (ip
->insn_mo
));
4829 pinfo
= ip
->insn_mo
->pinfo
;
4830 /* Conservatively treat all operands to an FP_D instruction are doubles.
4831 (This is overly pessimistic for things like cvt.s.d.) */
4832 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4837 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4838 Check whether that is allowed. */
4841 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4843 const char *s
= insn
->name
;
4844 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4846 && mips_opts
.oddspreg
;
4848 if (insn
->pinfo
== INSN_MACRO
)
4849 /* Let a macro pass, we'll catch it later when it is expanded. */
4852 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4853 otherwise it depends on oddspreg. */
4854 if ((insn
->pinfo
& FP_S
)
4855 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4856 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4857 return FPR_SIZE
== 32 || oddspreg
;
4859 /* Allow odd registers for single-precision ops and double-precision if the
4860 floating-point registers are 64-bit wide. */
4861 switch (insn
->pinfo
& (FP_S
| FP_D
))
4867 return FPR_SIZE
== 64;
4872 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4873 s
= strchr (insn
->name
, '.');
4874 if (s
!= NULL
&& opnum
== 2)
4875 s
= strchr (s
+ 1, '.');
4876 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4879 return FPR_SIZE
== 64;
4882 /* Information about an instruction argument that we're trying to match. */
4883 struct mips_arg_info
4885 /* The instruction so far. */
4886 struct mips_cl_insn
*insn
;
4888 /* The first unconsumed operand token. */
4889 struct mips_operand_token
*token
;
4891 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4894 /* The 1-based argument number, for error reporting. This does not
4895 count elided optional registers, etc.. */
4898 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4899 unsigned int last_regno
;
4901 /* If the first operand was an OP_REG, this is the register that it
4902 specified, otherwise it is ILLEGAL_REG. */
4903 unsigned int dest_regno
;
4905 /* The value of the last OP_INT operand. Only used for OP_MSB,
4906 where it gives the lsb position. */
4907 unsigned int last_op_int
;
4909 /* If true, match routines should assume that no later instruction
4910 alternative matches and should therefore be as accommodating as
4911 possible. Match routines should not report errors if something
4912 is only invalid for !LAX_MATCH. */
4913 bfd_boolean lax_match
;
4915 /* True if a reference to the current AT register was seen. */
4916 bfd_boolean seen_at
;
4919 /* Record that the argument is out of range. */
4922 match_out_of_range (struct mips_arg_info
*arg
)
4924 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4927 /* Record that the argument isn't constant but needs to be. */
4930 match_not_constant (struct mips_arg_info
*arg
)
4932 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4936 /* Try to match an OT_CHAR token for character CH. Consume the token
4937 and return true on success, otherwise return false. */
4940 match_char (struct mips_arg_info
*arg
, char ch
)
4942 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4952 /* Try to get an expression from the next tokens in ARG. Consume the
4953 tokens and return true on success, storing the expression value in
4954 VALUE and relocation types in R. */
4957 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4958 bfd_reloc_code_real_type
*r
)
4960 /* If the next token is a '(' that was parsed as being part of a base
4961 expression, assume we have an elided offset. The later match will fail
4962 if this turns out to be wrong. */
4963 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4965 value
->X_op
= O_constant
;
4966 value
->X_add_number
= 0;
4967 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4971 /* Reject register-based expressions such as "0+$2" and "(($2))".
4972 For plain registers the default error seems more appropriate. */
4973 if (arg
->token
->type
== OT_INTEGER
4974 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4976 set_insn_error (arg
->argnum
, _("register value used as expression"));
4980 if (arg
->token
->type
== OT_INTEGER
)
4982 *value
= arg
->token
->u
.integer
.value
;
4983 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4989 (arg
->argnum
, _("operand %d must be an immediate expression"),
4994 /* Try to get a constant expression from the next tokens in ARG. Consume
4995 the tokens and return true on success, storing the constant value
4999 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
5002 bfd_reloc_code_real_type r
[3];
5004 if (!match_expression (arg
, &ex
, r
))
5007 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
5008 *value
= ex
.X_add_number
;
5011 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
5012 match_out_of_range (arg
);
5014 match_not_constant (arg
);
5020 /* Return the RTYPE_* flags for a register operand of type TYPE that
5021 appears in instruction OPCODE. */
5024 convert_reg_type (const struct mips_opcode
*opcode
,
5025 enum mips_reg_operand_type type
)
5030 return RTYPE_NUM
| RTYPE_GP
;
5033 /* Allow vector register names for MDMX if the instruction is a 64-bit
5034 FPR load, store or move (including moves to and from GPRs). */
5035 if ((mips_opts
.ase
& ASE_MDMX
)
5036 && (opcode
->pinfo
& FP_D
)
5037 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5038 | INSN_COPROC_MEMORY_DELAY
5041 | INSN_STORE_MEMORY
)))
5042 return RTYPE_FPU
| RTYPE_VEC
;
5046 if (opcode
->pinfo
& (FP_D
| FP_S
))
5047 return RTYPE_CCC
| RTYPE_FCC
;
5051 if (opcode
->membership
& INSN_5400
)
5053 return RTYPE_FPU
| RTYPE_VEC
;
5059 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5060 return RTYPE_NUM
| RTYPE_CP0
;
5067 return RTYPE_NUM
| RTYPE_VI
;
5070 return RTYPE_NUM
| RTYPE_VF
;
5072 case OP_REG_R5900_I
:
5073 return RTYPE_R5900_I
;
5075 case OP_REG_R5900_Q
:
5076 return RTYPE_R5900_Q
;
5078 case OP_REG_R5900_R
:
5079 return RTYPE_R5900_R
;
5081 case OP_REG_R5900_ACC
:
5082 return RTYPE_R5900_ACC
;
5087 case OP_REG_MSA_CTRL
:
5093 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5096 check_regno (struct mips_arg_info
*arg
,
5097 enum mips_reg_operand_type type
, unsigned int regno
)
5099 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5100 arg
->seen_at
= TRUE
;
5102 if (type
== OP_REG_FP
5104 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5106 /* This was a warning prior to introducing O32 FPXX and FP64 support
5107 so maintain a warning for FP32 but raise an error for the new
5110 as_warn (_("float register should be even, was %d"), regno
);
5112 as_bad (_("float register should be even, was %d"), regno
);
5115 if (type
== OP_REG_CCC
)
5120 name
= arg
->insn
->insn_mo
->name
;
5121 length
= strlen (name
);
5122 if ((regno
& 1) != 0
5123 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5124 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5125 as_warn (_("condition code register should be even for %s, was %d"),
5128 if ((regno
& 3) != 0
5129 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5130 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5135 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5136 a register of type TYPE. Return true on success, storing the register
5137 number in *REGNO and warning about any dubious uses. */
5140 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5141 unsigned int symval
, unsigned int *regno
)
5143 if (type
== OP_REG_VEC
)
5144 symval
= mips_prefer_vec_regno (symval
);
5145 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5148 *regno
= symval
& RNUM_MASK
;
5149 check_regno (arg
, type
, *regno
);
5153 /* Try to interpret the next token in ARG as a register of type TYPE.
5154 Consume the token and return true on success, storing the register
5155 number in *REGNO. Return false on failure. */
5158 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5159 unsigned int *regno
)
5161 if (arg
->token
->type
== OT_REG
5162 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5170 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5171 Consume the token and return true on success, storing the register numbers
5172 in *REGNO1 and *REGNO2. Return false on failure. */
5175 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5176 unsigned int *regno1
, unsigned int *regno2
)
5178 if (match_reg (arg
, type
, regno1
))
5183 if (arg
->token
->type
== OT_REG_RANGE
5184 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5185 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5186 && *regno1
<= *regno2
)
5194 /* OP_INT matcher. */
5197 match_int_operand (struct mips_arg_info
*arg
,
5198 const struct mips_operand
*operand_base
)
5200 const struct mips_int_operand
*operand
;
5202 int min_val
, max_val
, factor
;
5205 operand
= (const struct mips_int_operand
*) operand_base
;
5206 factor
= 1 << operand
->shift
;
5207 min_val
= mips_int_operand_min (operand
);
5208 max_val
= mips_int_operand_max (operand
);
5210 if (operand_base
->lsb
== 0
5211 && operand_base
->size
== 16
5212 && operand
->shift
== 0
5213 && operand
->bias
== 0
5214 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5216 /* The operand can be relocated. */
5217 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5220 if (offset_expr
.X_op
== O_big
)
5222 match_out_of_range (arg
);
5226 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5227 /* Relocation operators were used. Accept the argument and
5228 leave the relocation value in offset_expr and offset_relocs
5229 for the caller to process. */
5232 if (offset_expr
.X_op
!= O_constant
)
5234 /* Accept non-constant operands if no later alternative matches,
5235 leaving it for the caller to process. */
5236 if (!arg
->lax_match
)
5238 match_not_constant (arg
);
5241 offset_reloc
[0] = BFD_RELOC_LO16
;
5245 /* Clear the global state; we're going to install the operand
5247 sval
= offset_expr
.X_add_number
;
5248 offset_expr
.X_op
= O_absent
;
5250 /* For compatibility with older assemblers, we accept
5251 0x8000-0xffff as signed 16-bit numbers when only
5252 signed numbers are allowed. */
5255 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5256 if (!arg
->lax_match
&& sval
<= max_val
)
5258 match_out_of_range (arg
);
5265 if (!match_const_int (arg
, &sval
))
5269 arg
->last_op_int
= sval
;
5271 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5273 match_out_of_range (arg
);
5277 uval
= (unsigned int) sval
>> operand
->shift
;
5278 uval
-= operand
->bias
;
5280 /* Handle -mfix-cn63xxp1. */
5282 && mips_fix_cn63xxp1
5283 && !mips_opts
.micromips
5284 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5299 /* The rest must be changed to 28. */
5304 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5308 /* OP_MAPPED_INT matcher. */
5311 match_mapped_int_operand (struct mips_arg_info
*arg
,
5312 const struct mips_operand
*operand_base
)
5314 const struct mips_mapped_int_operand
*operand
;
5315 unsigned int uval
, num_vals
;
5318 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5319 if (!match_const_int (arg
, &sval
))
5322 num_vals
= 1 << operand_base
->size
;
5323 for (uval
= 0; uval
< num_vals
; uval
++)
5324 if (operand
->int_map
[uval
] == sval
)
5326 if (uval
== num_vals
)
5328 match_out_of_range (arg
);
5332 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5336 /* OP_MSB matcher. */
5339 match_msb_operand (struct mips_arg_info
*arg
,
5340 const struct mips_operand
*operand_base
)
5342 const struct mips_msb_operand
*operand
;
5343 int min_val
, max_val
, max_high
;
5344 offsetT size
, sval
, high
;
5346 operand
= (const struct mips_msb_operand
*) operand_base
;
5347 min_val
= operand
->bias
;
5348 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5349 max_high
= operand
->opsize
;
5351 if (!match_const_int (arg
, &size
))
5354 high
= size
+ arg
->last_op_int
;
5355 sval
= operand
->add_lsb
? high
: size
;
5357 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5359 match_out_of_range (arg
);
5362 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5366 /* OP_REG matcher. */
5369 match_reg_operand (struct mips_arg_info
*arg
,
5370 const struct mips_operand
*operand_base
)
5372 const struct mips_reg_operand
*operand
;
5373 unsigned int regno
, uval
, num_vals
;
5375 operand
= (const struct mips_reg_operand
*) operand_base
;
5376 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5379 if (operand
->reg_map
)
5381 num_vals
= 1 << operand
->root
.size
;
5382 for (uval
= 0; uval
< num_vals
; uval
++)
5383 if (operand
->reg_map
[uval
] == regno
)
5385 if (num_vals
== uval
)
5391 arg
->last_regno
= regno
;
5392 if (arg
->opnum
== 1)
5393 arg
->dest_regno
= regno
;
5394 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5398 /* OP_REG_PAIR matcher. */
5401 match_reg_pair_operand (struct mips_arg_info
*arg
,
5402 const struct mips_operand
*operand_base
)
5404 const struct mips_reg_pair_operand
*operand
;
5405 unsigned int regno1
, regno2
, uval
, num_vals
;
5407 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5408 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5409 || !match_char (arg
, ',')
5410 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5413 num_vals
= 1 << operand_base
->size
;
5414 for (uval
= 0; uval
< num_vals
; uval
++)
5415 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5417 if (uval
== num_vals
)
5420 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5424 /* OP_PCREL matcher. The caller chooses the relocation type. */
5427 match_pcrel_operand (struct mips_arg_info
*arg
)
5429 bfd_reloc_code_real_type r
[3];
5431 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5434 /* OP_PERF_REG matcher. */
5437 match_perf_reg_operand (struct mips_arg_info
*arg
,
5438 const struct mips_operand
*operand
)
5442 if (!match_const_int (arg
, &sval
))
5447 || (mips_opts
.arch
== CPU_R5900
5448 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5449 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5451 set_insn_error (arg
->argnum
, _("invalid performance register"));
5455 insn_insert_operand (arg
->insn
, operand
, sval
);
5459 /* OP_ADDIUSP matcher. */
5462 match_addiusp_operand (struct mips_arg_info
*arg
,
5463 const struct mips_operand
*operand
)
5468 if (!match_const_int (arg
, &sval
))
5473 match_out_of_range (arg
);
5478 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5480 match_out_of_range (arg
);
5484 uval
= (unsigned int) sval
;
5485 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5486 insn_insert_operand (arg
->insn
, operand
, uval
);
5490 /* OP_CLO_CLZ_DEST matcher. */
5493 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5494 const struct mips_operand
*operand
)
5498 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5501 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5505 /* OP_CHECK_PREV matcher. */
5508 match_check_prev_operand (struct mips_arg_info
*arg
,
5509 const struct mips_operand
*operand_base
)
5511 const struct mips_check_prev_operand
*operand
;
5514 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5516 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5519 if (!operand
->zero_ok
&& regno
== 0)
5522 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5523 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5524 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5526 arg
->last_regno
= regno
;
5527 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5534 /* OP_SAME_RS_RT matcher. */
5537 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5538 const struct mips_operand
*operand
)
5542 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5547 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5551 arg
->last_regno
= regno
;
5553 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5557 /* OP_LWM_SWM_LIST matcher. */
5560 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5561 const struct mips_operand
*operand
)
5563 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5564 struct mips_arg_info reset
;
5567 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5571 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5576 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5579 while (match_char (arg
, ',')
5580 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5583 if (operand
->size
== 2)
5585 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5591 and any permutations of these. */
5592 if ((reglist
& 0xfff1ffff) != 0x80010000)
5595 sregs
= (reglist
>> 17) & 7;
5600 /* The list must include at least one of ra and s0-sN,
5601 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5602 which are $23 and $30 respectively.) E.g.:
5610 and any permutations of these. */
5611 if ((reglist
& 0x3f00ffff) != 0)
5614 ra
= (reglist
>> 27) & 0x10;
5615 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5618 if ((sregs
& -sregs
) != sregs
)
5621 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5625 /* OP_ENTRY_EXIT_LIST matcher. */
5628 match_entry_exit_operand (struct mips_arg_info
*arg
,
5629 const struct mips_operand
*operand
)
5632 bfd_boolean is_exit
;
5634 /* The format is the same for both ENTRY and EXIT, but the constraints
5636 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5637 mask
= (is_exit
? 7 << 3 : 0);
5640 unsigned int regno1
, regno2
;
5641 bfd_boolean is_freg
;
5643 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5645 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5650 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5653 mask
|= (5 + regno2
) << 3;
5655 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5656 mask
|= (regno2
- 3) << 3;
5657 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5658 mask
|= (regno2
- 15) << 1;
5659 else if (regno1
== RA
&& regno2
== RA
)
5664 while (match_char (arg
, ','));
5666 insn_insert_operand (arg
->insn
, operand
, mask
);
5670 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5671 the argument register mask AMASK, the number of static registers
5672 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5673 respectively, and the frame size FRAME_SIZE. */
5676 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5677 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5678 unsigned int frame_size
)
5680 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5681 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5684 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5685 argument register mask AMASK, the number of static registers saved
5686 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5687 respectively, and the frame size FRAME_SIZE. */
5690 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5691 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5692 unsigned int frame_size
)
5696 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5697 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5698 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5699 | ((frame_size
& 0xf0) << 16));
5703 /* OP_SAVE_RESTORE_LIST matcher. */
5706 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5708 unsigned int opcode
, args
, statics
, sregs
;
5709 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5710 unsigned int arg_mask
, ra
, s0
, s1
;
5713 opcode
= arg
->insn
->insn_opcode
;
5715 num_frame_sizes
= 0;
5724 unsigned int regno1
, regno2
;
5726 if (arg
->token
->type
== OT_INTEGER
)
5728 /* Handle the frame size. */
5729 if (!match_const_int (arg
, &frame_size
))
5731 num_frame_sizes
+= 1;
5735 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5738 while (regno1
<= regno2
)
5740 if (regno1
>= 4 && regno1
<= 7)
5742 if (num_frame_sizes
== 0)
5744 args
|= 1 << (regno1
- 4);
5746 /* statics $a0-$a3 */
5747 statics
|= 1 << (regno1
- 4);
5749 else if (regno1
>= 16 && regno1
<= 23)
5751 sregs
|= 1 << (regno1
- 16);
5752 else if (regno1
== 30)
5755 else if (regno1
== 31)
5756 /* Add $ra to insn. */
5766 while (match_char (arg
, ','));
5768 /* Encode args/statics combination. */
5771 else if (args
== 0xf)
5772 /* All $a0-$a3 are args. */
5773 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5774 else if (statics
== 0xf)
5775 /* All $a0-$a3 are statics. */
5776 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5779 /* Count arg registers. */
5789 /* Count static registers. */
5791 while (statics
& 0x8)
5793 statics
= (statics
<< 1) & 0xf;
5799 /* Encode args/statics. */
5800 arg_mask
= (num_args
<< 2) | num_statics
;
5803 /* Encode $s0/$s1. */
5804 if (sregs
& (1 << 0)) /* $s0 */
5806 if (sregs
& (1 << 1)) /* $s1 */
5810 /* Encode $s2-$s8. */
5820 /* Encode frame size. */
5821 if (num_frame_sizes
== 0)
5823 set_insn_error (arg
->argnum
, _("missing frame size"));
5826 if (num_frame_sizes
> 1)
5828 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5831 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5833 set_insn_error (arg
->argnum
, _("invalid frame size"));
5838 /* Finally build the instruction. */
5839 if (mips_opts
.mips16
)
5840 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5842 else if (!mips_opts
.micromips
)
5843 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5848 arg
->insn
->insn_opcode
= opcode
;
5852 /* OP_MDMX_IMM_REG matcher. */
5855 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5856 const struct mips_operand
*operand
)
5858 unsigned int regno
, uval
;
5860 const struct mips_opcode
*opcode
;
5862 /* The mips_opcode records whether this is an octobyte or quadhalf
5863 instruction. Start out with that bit in place. */
5864 opcode
= arg
->insn
->insn_mo
;
5865 uval
= mips_extract_operand (operand
, opcode
->match
);
5866 is_qh
= (uval
!= 0);
5868 if (arg
->token
->type
== OT_REG
)
5870 if ((opcode
->membership
& INSN_5400
)
5871 && strcmp (opcode
->name
, "rzu.ob") == 0)
5873 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5878 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5882 /* Check whether this is a vector register or a broadcast of
5883 a single element. */
5884 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5886 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5888 set_insn_error (arg
->argnum
, _("invalid element selector"));
5891 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5896 /* A full vector. */
5897 if ((opcode
->membership
& INSN_5400
)
5898 && (strcmp (opcode
->name
, "sll.ob") == 0
5899 || strcmp (opcode
->name
, "srl.ob") == 0))
5901 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5907 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5909 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5917 if (!match_const_int (arg
, &sval
))
5919 if (sval
< 0 || sval
> 31)
5921 match_out_of_range (arg
);
5924 uval
|= (sval
& 31);
5926 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5928 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5930 insn_insert_operand (arg
->insn
, operand
, uval
);
5934 /* OP_IMM_INDEX matcher. */
5937 match_imm_index_operand (struct mips_arg_info
*arg
,
5938 const struct mips_operand
*operand
)
5940 unsigned int max_val
;
5942 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5945 max_val
= (1 << operand
->size
) - 1;
5946 if (arg
->token
->u
.index
> max_val
)
5948 match_out_of_range (arg
);
5951 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5956 /* OP_REG_INDEX matcher. */
5959 match_reg_index_operand (struct mips_arg_info
*arg
,
5960 const struct mips_operand
*operand
)
5964 if (arg
->token
->type
!= OT_REG_INDEX
)
5967 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5970 insn_insert_operand (arg
->insn
, operand
, regno
);
5975 /* OP_PC matcher. */
5978 match_pc_operand (struct mips_arg_info
*arg
)
5980 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5988 /* OP_REG28 matcher. */
5991 match_reg28_operand (struct mips_arg_info
*arg
)
5995 if (arg
->token
->type
== OT_REG
5996 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
6005 /* OP_NON_ZERO_REG matcher. */
6008 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
6009 const struct mips_operand
*operand
)
6013 if (!match_reg (arg
, OP_REG_GP
, ®no
))
6019 arg
->last_regno
= regno
;
6020 insn_insert_operand (arg
->insn
, operand
, regno
);
6024 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6025 register that we need to match. */
6028 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6032 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6035 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6036 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6037 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6039 Return the constant in IMM and OFFSET as follows:
6041 - If the constant should be loaded via memory, set IMM to O_absent and
6042 OFFSET to the memory address.
6044 - Otherwise, if the constant should be loaded into two 32-bit registers,
6045 set IMM to the O_constant to load into the high register and OFFSET
6046 to the corresponding value for the low register.
6048 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6050 These constants only appear as the last operand in an instruction,
6051 and every instruction that accepts them in any variant accepts them
6052 in all variants. This means we don't have to worry about backing out
6053 any changes if the instruction does not match. We just match
6054 unconditionally and report an error if the constant is invalid. */
6057 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6058 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6063 const char *newname
;
6064 unsigned char *data
;
6066 /* Where the constant is placed is based on how the MIPS assembler
6069 length == 4 && using_gprs -- immediate value only
6070 length == 8 && using_gprs -- .rdata or immediate value
6071 length == 4 && !using_gprs -- .lit4 or immediate value
6072 length == 8 && !using_gprs -- .lit8 or immediate value
6074 The .lit4 and .lit8 sections are only used if permitted by the
6076 if (arg
->token
->type
!= OT_FLOAT
)
6078 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6082 gas_assert (arg
->token
->u
.flt
.length
== length
);
6083 data
= arg
->token
->u
.flt
.data
;
6086 /* Handle 32-bit constants for which an immediate value is best. */
6089 || g_switch_value
< 4
6090 || (data
[0] == 0 && data
[1] == 0)
6091 || (data
[2] == 0 && data
[3] == 0)))
6093 imm
->X_op
= O_constant
;
6094 if (!target_big_endian
)
6095 imm
->X_add_number
= bfd_getl32 (data
);
6097 imm
->X_add_number
= bfd_getb32 (data
);
6098 offset
->X_op
= O_absent
;
6102 /* Handle 64-bit constants for which an immediate value is best. */
6104 && !mips_disable_float_construction
6105 /* Constants can only be constructed in GPRs and copied to FPRs if the
6106 GPRs are at least as wide as the FPRs or MTHC1 is available.
6107 Unlike most tests for 32-bit floating-point registers this check
6108 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6109 permit 64-bit moves without MXHC1.
6110 Force the constant into memory otherwise. */
6113 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6115 && ((data
[0] == 0 && data
[1] == 0)
6116 || (data
[2] == 0 && data
[3] == 0))
6117 && ((data
[4] == 0 && data
[5] == 0)
6118 || (data
[6] == 0 && data
[7] == 0)))
6120 /* The value is simple enough to load with a couple of instructions.
6121 If using 32-bit registers, set IMM to the high order 32 bits and
6122 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6124 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6126 imm
->X_op
= O_constant
;
6127 offset
->X_op
= O_constant
;
6128 if (!target_big_endian
)
6130 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6131 offset
->X_add_number
= bfd_getl32 (data
);
6135 imm
->X_add_number
= bfd_getb32 (data
);
6136 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6138 if (offset
->X_add_number
== 0)
6139 offset
->X_op
= O_absent
;
6143 imm
->X_op
= O_constant
;
6144 if (!target_big_endian
)
6145 imm
->X_add_number
= bfd_getl64 (data
);
6147 imm
->X_add_number
= bfd_getb64 (data
);
6148 offset
->X_op
= O_absent
;
6153 /* Switch to the right section. */
6155 subseg
= now_subseg
;
6158 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6163 if (using_gprs
|| g_switch_value
< 8)
6164 newname
= RDATA_SECTION_NAME
;
6169 new_seg
= subseg_new (newname
, (subsegT
) 0);
6170 bfd_set_section_flags (stdoutput
, new_seg
,
6171 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6172 frag_align (length
== 4 ? 2 : 3, 0, 0);
6173 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6174 record_alignment (new_seg
, 4);
6176 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6178 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6180 /* Set the argument to the current address in the section. */
6181 imm
->X_op
= O_absent
;
6182 offset
->X_op
= O_symbol
;
6183 offset
->X_add_symbol
= symbol_temp_new_now ();
6184 offset
->X_add_number
= 0;
6186 /* Put the floating point number into the section. */
6187 p
= frag_more (length
);
6188 memcpy (p
, data
, length
);
6190 /* Switch back to the original section. */
6191 subseg_set (seg
, subseg
);
6195 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6199 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6200 const struct mips_operand
*operand
,
6201 bfd_boolean match_p
)
6205 /* The operand can be an XYZW mask or a single 2-bit channel index
6206 (with X being 0). */
6207 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6209 /* The suffix can be omitted when it is already part of the opcode. */
6210 if (arg
->token
->type
!= OT_CHANNELS
)
6213 uval
= arg
->token
->u
.channels
;
6214 if (operand
->size
== 2)
6216 /* Check that a single bit is set and convert it into a 2-bit index. */
6217 if ((uval
& -uval
) != uval
)
6219 uval
= 4 - ffs (uval
);
6222 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6227 insn_insert_operand (arg
->insn
, operand
, uval
);
6231 /* Try to match a token from ARG against OPERAND. Consume the token
6232 and return true on success, otherwise return false. */
6235 match_operand (struct mips_arg_info
*arg
,
6236 const struct mips_operand
*operand
)
6238 switch (operand
->type
)
6241 return match_int_operand (arg
, operand
);
6244 return match_mapped_int_operand (arg
, operand
);
6247 return match_msb_operand (arg
, operand
);
6250 case OP_OPTIONAL_REG
:
6251 return match_reg_operand (arg
, operand
);
6254 return match_reg_pair_operand (arg
, operand
);
6257 return match_pcrel_operand (arg
);
6260 return match_perf_reg_operand (arg
, operand
);
6262 case OP_ADDIUSP_INT
:
6263 return match_addiusp_operand (arg
, operand
);
6265 case OP_CLO_CLZ_DEST
:
6266 return match_clo_clz_dest_operand (arg
, operand
);
6268 case OP_LWM_SWM_LIST
:
6269 return match_lwm_swm_list_operand (arg
, operand
);
6271 case OP_ENTRY_EXIT_LIST
:
6272 return match_entry_exit_operand (arg
, operand
);
6274 case OP_SAVE_RESTORE_LIST
:
6275 return match_save_restore_list_operand (arg
);
6277 case OP_MDMX_IMM_REG
:
6278 return match_mdmx_imm_reg_operand (arg
, operand
);
6280 case OP_REPEAT_DEST_REG
:
6281 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6283 case OP_REPEAT_PREV_REG
:
6284 return match_tied_reg_operand (arg
, arg
->last_regno
);
6287 return match_pc_operand (arg
);
6290 return match_reg28_operand (arg
);
6293 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6295 case OP_VU0_MATCH_SUFFIX
:
6296 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6299 return match_imm_index_operand (arg
, operand
);
6302 return match_reg_index_operand (arg
, operand
);
6305 return match_same_rs_rt_operand (arg
, operand
);
6308 return match_check_prev_operand (arg
, operand
);
6310 case OP_NON_ZERO_REG
:
6311 return match_non_zero_reg_operand (arg
, operand
);
6316 /* ARG is the state after successfully matching an instruction.
6317 Issue any queued-up warnings. */
6320 check_completed_insn (struct mips_arg_info
*arg
)
6325 as_warn (_("used $at without \".set noat\""));
6327 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6331 /* Return true if modifying general-purpose register REG needs a delay. */
6334 reg_needs_delay (unsigned int reg
)
6336 unsigned long prev_pinfo
;
6338 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6339 if (!mips_opts
.noreorder
6340 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6341 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6342 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6348 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6349 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6350 by VR4120 errata. */
6353 classify_vr4120_insn (const char *name
)
6355 if (strncmp (name
, "macc", 4) == 0)
6356 return FIX_VR4120_MACC
;
6357 if (strncmp (name
, "dmacc", 5) == 0)
6358 return FIX_VR4120_DMACC
;
6359 if (strncmp (name
, "mult", 4) == 0)
6360 return FIX_VR4120_MULT
;
6361 if (strncmp (name
, "dmult", 5) == 0)
6362 return FIX_VR4120_DMULT
;
6363 if (strstr (name
, "div"))
6364 return FIX_VR4120_DIV
;
6365 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6366 return FIX_VR4120_MTHILO
;
6367 return NUM_FIX_VR4120_CLASSES
;
6370 #define INSN_ERET 0x42000018
6371 #define INSN_DERET 0x4200001f
6372 #define INSN_DMULT 0x1c
6373 #define INSN_DMULTU 0x1d
6375 /* Return the number of instructions that must separate INSN1 and INSN2,
6376 where INSN1 is the earlier instruction. Return the worst-case value
6377 for any INSN2 if INSN2 is null. */
6380 insns_between (const struct mips_cl_insn
*insn1
,
6381 const struct mips_cl_insn
*insn2
)
6383 unsigned long pinfo1
, pinfo2
;
6386 /* If INFO2 is null, pessimistically assume that all flags are set for
6387 the second instruction. */
6388 pinfo1
= insn1
->insn_mo
->pinfo
;
6389 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6391 /* For most targets, write-after-read dependencies on the HI and LO
6392 registers must be separated by at least two instructions. */
6393 if (!hilo_interlocks
)
6395 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6397 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6401 /* If we're working around r7000 errata, there must be two instructions
6402 between an mfhi or mflo and any instruction that uses the result. */
6403 if (mips_7000_hilo_fix
6404 && !mips_opts
.micromips
6405 && MF_HILO_INSN (pinfo1
)
6406 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6409 /* If we're working around 24K errata, one instruction is required
6410 if an ERET or DERET is followed by a branch instruction. */
6411 if (mips_fix_24k
&& !mips_opts
.micromips
)
6413 if (insn1
->insn_opcode
== INSN_ERET
6414 || insn1
->insn_opcode
== INSN_DERET
)
6417 || insn2
->insn_opcode
== INSN_ERET
6418 || insn2
->insn_opcode
== INSN_DERET
6419 || delayed_branch_p (insn2
))
6424 /* If we're working around PMC RM7000 errata, there must be three
6425 nops between a dmult and a load instruction. */
6426 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6428 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6429 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6431 if (pinfo2
& INSN_LOAD_MEMORY
)
6436 /* If working around VR4120 errata, check for combinations that need
6437 a single intervening instruction. */
6438 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6440 unsigned int class1
, class2
;
6442 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6443 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6447 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6448 if (vr4120_conflicts
[class1
] & (1 << class2
))
6453 if (!HAVE_CODE_COMPRESSION
)
6455 /* Check for GPR or coprocessor load delays. All such delays
6456 are on the RT register. */
6457 /* Itbl support may require additional care here. */
6458 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6459 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6461 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6465 /* Check for generic coprocessor hazards.
6467 This case is not handled very well. There is no special
6468 knowledge of CP0 handling, and the coprocessors other than
6469 the floating point unit are not distinguished at all. */
6470 /* Itbl support may require additional care here. FIXME!
6471 Need to modify this to include knowledge about
6472 user specified delays! */
6473 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6474 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6476 /* Handle cases where INSN1 writes to a known general coprocessor
6477 register. There must be a one instruction delay before INSN2
6478 if INSN2 reads that register, otherwise no delay is needed. */
6479 mask
= fpr_write_mask (insn1
);
6482 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6487 /* Read-after-write dependencies on the control registers
6488 require a two-instruction gap. */
6489 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6490 && (pinfo2
& INSN_READ_COND_CODE
))
6493 /* We don't know exactly what INSN1 does. If INSN2 is
6494 also a coprocessor instruction, assume there must be
6495 a one instruction gap. */
6496 if (pinfo2
& INSN_COP
)
6501 /* Check for read-after-write dependencies on the coprocessor
6502 control registers in cases where INSN1 does not need a general
6503 coprocessor delay. This means that INSN1 is a floating point
6504 comparison instruction. */
6505 /* Itbl support may require additional care here. */
6506 else if (!cop_interlocks
6507 && (pinfo1
& INSN_WRITE_COND_CODE
)
6508 && (pinfo2
& INSN_READ_COND_CODE
))
6512 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6513 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6515 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6516 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6517 || (insn2
&& delayed_branch_p (insn2
))))
6523 /* Return the number of nops that would be needed to work around the
6524 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6525 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6526 that are contained within the first IGNORE instructions of HIST. */
6529 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6530 const struct mips_cl_insn
*insn
)
6535 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6536 are not affected by the errata. */
6538 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6539 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6540 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6543 /* Search for the first MFLO or MFHI. */
6544 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6545 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6547 /* Extract the destination register. */
6548 mask
= gpr_write_mask (&hist
[i
]);
6550 /* No nops are needed if INSN reads that register. */
6551 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6554 /* ...or if any of the intervening instructions do. */
6555 for (j
= 0; j
< i
; j
++)
6556 if (gpr_read_mask (&hist
[j
]) & mask
)
6560 return MAX_VR4130_NOPS
- i
;
6565 #define BASE_REG_EQ(INSN1, INSN2) \
6566 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6567 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6569 /* Return the minimum alignment for this store instruction. */
6572 fix_24k_align_to (const struct mips_opcode
*mo
)
6574 if (strcmp (mo
->name
, "sh") == 0)
6577 if (strcmp (mo
->name
, "swc1") == 0
6578 || strcmp (mo
->name
, "swc2") == 0
6579 || strcmp (mo
->name
, "sw") == 0
6580 || strcmp (mo
->name
, "sc") == 0
6581 || strcmp (mo
->name
, "s.s") == 0)
6584 if (strcmp (mo
->name
, "sdc1") == 0
6585 || strcmp (mo
->name
, "sdc2") == 0
6586 || strcmp (mo
->name
, "s.d") == 0)
6593 struct fix_24k_store_info
6595 /* Immediate offset, if any, for this store instruction. */
6597 /* Alignment required by this store instruction. */
6599 /* True for register offsets. */
6600 int register_offset
;
6603 /* Comparison function used by qsort. */
6606 fix_24k_sort (const void *a
, const void *b
)
6608 const struct fix_24k_store_info
*pos1
= a
;
6609 const struct fix_24k_store_info
*pos2
= b
;
6611 return (pos1
->off
- pos2
->off
);
6614 /* INSN is a store instruction. Try to record the store information
6615 in STINFO. Return false if the information isn't known. */
6618 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6619 const struct mips_cl_insn
*insn
)
6621 /* The instruction must have a known offset. */
6622 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6625 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6626 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6630 /* Return the number of nops that would be needed to work around the 24k
6631 "lost data on stores during refill" errata if instruction INSN
6632 immediately followed the 2 instructions described by HIST.
6633 Ignore hazards that are contained within the first IGNORE
6634 instructions of HIST.
6636 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6637 for the data cache refills and store data. The following describes
6638 the scenario where the store data could be lost.
6640 * A data cache miss, due to either a load or a store, causing fill
6641 data to be supplied by the memory subsystem
6642 * The first three doublewords of fill data are returned and written
6644 * A sequence of four stores occurs in consecutive cycles around the
6645 final doubleword of the fill:
6649 * Zero, One or more instructions
6652 The four stores A-D must be to different doublewords of the line that
6653 is being filled. The fourth instruction in the sequence above permits
6654 the fill of the final doubleword to be transferred from the FSB into
6655 the cache. In the sequence above, the stores may be either integer
6656 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6657 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6658 different doublewords on the line. If the floating point unit is
6659 running in 1:2 mode, it is not possible to create the sequence above
6660 using only floating point store instructions.
6662 In this case, the cache line being filled is incorrectly marked
6663 invalid, thereby losing the data from any store to the line that
6664 occurs between the original miss and the completion of the five
6665 cycle sequence shown above.
6667 The workarounds are:
6669 * Run the data cache in write-through mode.
6670 * Insert a non-store instruction between
6671 Store A and Store B or Store B and Store C. */
6674 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6675 const struct mips_cl_insn
*insn
)
6677 struct fix_24k_store_info pos
[3];
6678 int align
, i
, base_offset
;
6683 /* If the previous instruction wasn't a store, there's nothing to
6685 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6688 /* If the instructions after the previous one are unknown, we have
6689 to assume the worst. */
6693 /* Check whether we are dealing with three consecutive stores. */
6694 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6695 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6698 /* If we don't know the relationship between the store addresses,
6699 assume the worst. */
6700 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6701 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6704 if (!fix_24k_record_store_info (&pos
[0], insn
)
6705 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6706 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6709 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6711 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6712 X bytes and such that the base register + X is known to be aligned
6715 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6719 align
= pos
[0].align_to
;
6720 base_offset
= pos
[0].off
;
6721 for (i
= 1; i
< 3; i
++)
6722 if (align
< pos
[i
].align_to
)
6724 align
= pos
[i
].align_to
;
6725 base_offset
= pos
[i
].off
;
6727 for (i
= 0; i
< 3; i
++)
6728 pos
[i
].off
-= base_offset
;
6731 pos
[0].off
&= ~align
+ 1;
6732 pos
[1].off
&= ~align
+ 1;
6733 pos
[2].off
&= ~align
+ 1;
6735 /* If any two stores write to the same chunk, they also write to the
6736 same doubleword. The offsets are still sorted at this point. */
6737 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6740 /* A range of at least 9 bytes is needed for the stores to be in
6741 non-overlapping doublewords. */
6742 if (pos
[2].off
- pos
[0].off
<= 8)
6745 if (pos
[2].off
- pos
[1].off
>= 24
6746 || pos
[1].off
- pos
[0].off
>= 24
6747 || pos
[2].off
- pos
[0].off
>= 32)
6753 /* Return the number of nops that would be needed if instruction INSN
6754 immediately followed the MAX_NOPS instructions given by HIST,
6755 where HIST[0] is the most recent instruction. Ignore hazards
6756 between INSN and the first IGNORE instructions in HIST.
6758 If INSN is null, return the worse-case number of nops for any
6762 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6763 const struct mips_cl_insn
*insn
)
6765 int i
, nops
, tmp_nops
;
6768 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6770 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6771 if (tmp_nops
> nops
)
6775 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6777 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6778 if (tmp_nops
> nops
)
6782 if (mips_fix_24k
&& !mips_opts
.micromips
)
6784 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6785 if (tmp_nops
> nops
)
6792 /* The variable arguments provide NUM_INSNS extra instructions that
6793 might be added to HIST. Return the largest number of nops that
6794 would be needed after the extended sequence, ignoring hazards
6795 in the first IGNORE instructions. */
6798 nops_for_sequence (int num_insns
, int ignore
,
6799 const struct mips_cl_insn
*hist
, ...)
6802 struct mips_cl_insn buffer
[MAX_NOPS
];
6803 struct mips_cl_insn
*cursor
;
6806 va_start (args
, hist
);
6807 cursor
= buffer
+ num_insns
;
6808 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6809 while (cursor
> buffer
)
6810 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6812 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6817 /* Like nops_for_insn, but if INSN is a branch, take into account the
6818 worst-case delay for the branch target. */
6821 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6822 const struct mips_cl_insn
*insn
)
6826 nops
= nops_for_insn (ignore
, hist
, insn
);
6827 if (delayed_branch_p (insn
))
6829 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6830 hist
, insn
, get_delay_slot_nop (insn
));
6831 if (tmp_nops
> nops
)
6834 else if (compact_branch_p (insn
))
6836 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6837 if (tmp_nops
> nops
)
6843 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6846 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6848 gas_assert (!HAVE_CODE_COMPRESSION
);
6849 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6850 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6853 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6854 jr target pc &= 'hffff_ffff_cfff_ffff. */
6857 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6859 gas_assert (!HAVE_CODE_COMPRESSION
);
6860 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6861 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6862 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6870 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6871 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6874 ep
.X_op
= O_constant
;
6875 ep
.X_add_number
= 0xcfff0000;
6876 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6877 ep
.X_add_number
= 0xffff;
6878 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6879 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6884 fix_loongson2f (struct mips_cl_insn
* ip
)
6886 if (mips_fix_loongson2f_nop
)
6887 fix_loongson2f_nop (ip
);
6889 if (mips_fix_loongson2f_jump
)
6890 fix_loongson2f_jump (ip
);
6893 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6896 fix_loongson3_llsc (struct mips_cl_insn
* ip
)
6898 gas_assert (!HAVE_CODE_COMPRESSION
);
6900 /* If is an local label and the insn is not sync,
6901 look forward that whether an branch between ll/sc jump to here
6902 if so, insert a sync. */
6903 if (seg_info (now_seg
)->label_list
6904 && S_IS_LOCAL (seg_info (now_seg
)->label_list
->label
)
6905 && (strcmp (ip
->insn_mo
->name
, "sync") != 0))
6907 const char *label_name
= S_GET_NAME (seg_info (now_seg
)->label_list
->label
);
6908 unsigned long lookback
= ARRAY_SIZE (history
);
6911 for (i
= 0; i
< lookback
; i
++)
6913 if (streq (history
[i
].insn_mo
->name
, "ll")
6914 || streq (history
[i
].insn_mo
->name
, "lld"))
6917 if (streq (history
[i
].insn_mo
->name
, "sc")
6918 || streq (history
[i
].insn_mo
->name
, "scd"))
6922 for (j
= i
+ 1; j
< lookback
; j
++)
6924 if (streq (history
[i
].insn_mo
->name
, "ll")
6925 || streq (history
[i
].insn_mo
->name
, "lld"))
6928 if (delayed_branch_p (&history
[j
]))
6930 if (streq (history
[j
].target
, label_name
))
6932 add_fixed_insn (&sync_insn
);
6933 insert_into_history (0, 1, &sync_insn
);
6942 /* If we find a sc, we look forward to look for an branch insn,
6943 and see whether it jump back and out of ll/sc. */
6944 else if (streq(ip
->insn_mo
->name
, "sc") || streq(ip
->insn_mo
->name
, "scd"))
6946 unsigned long lookback
= ARRAY_SIZE (history
) - 1;
6949 for (i
= 0; i
< lookback
; i
++)
6951 if (streq (history
[i
].insn_mo
->name
, "ll")
6952 || streq (history
[i
].insn_mo
->name
, "lld"))
6955 if (delayed_branch_p (&history
[i
]))
6959 for (j
= i
+ 1; j
< lookback
; j
++)
6961 if (streq (history
[j
].insn_mo
->name
, "ll")
6962 || streq (history
[i
].insn_mo
->name
, "lld"))
6966 for (; j
< lookback
; j
++)
6968 if (history
[j
].label
[0] != '\0'
6969 && streq (history
[j
].label
, history
[i
].target
)
6970 && strcmp (history
[j
+1].insn_mo
->name
, "sync") != 0)
6972 add_fixed_insn (&sync_insn
);
6973 insert_into_history (++j
, 1, &sync_insn
);
6980 /* Skip if there is a sync before ll/lld. */
6981 if ((strcmp (ip
->insn_mo
->name
, "ll") == 0
6982 || strcmp (ip
->insn_mo
->name
, "lld") == 0)
6983 && (strcmp (history
[0].insn_mo
->name
, "sync") != 0))
6985 add_fixed_insn (&sync_insn
);
6986 insert_into_history (0, 1, &sync_insn
);
6990 /* IP is a branch that has a delay slot, and we need to fill it
6991 automatically. Return true if we can do that by swapping IP
6992 with the previous instruction.
6993 ADDRESS_EXPR is an operand of the instruction to be used with
6997 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6998 bfd_reloc_code_real_type
*reloc_type
)
7000 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
7001 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
7002 unsigned int fpr_read
, prev_fpr_write
;
7004 /* -O2 and above is required for this optimization. */
7005 if (mips_optimize
< 2)
7008 /* If we have seen .set volatile or .set nomove, don't optimize. */
7009 if (mips_opts
.nomove
)
7012 /* We can't swap if the previous instruction's position is fixed. */
7013 if (history
[0].fixed_p
)
7016 /* If the previous previous insn was in a .set noreorder, we can't
7017 swap. Actually, the MIPS assembler will swap in this situation.
7018 However, gcc configured -with-gnu-as will generate code like
7026 in which we can not swap the bne and INSN. If gcc is not configured
7027 -with-gnu-as, it does not output the .set pseudo-ops. */
7028 if (history
[1].noreorder_p
)
7031 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7032 This means that the previous instruction was a 4-byte one anyhow. */
7033 if (mips_opts
.mips16
&& history
[0].fixp
[0])
7036 /* If the branch is itself the target of a branch, we can not swap.
7037 We cheat on this; all we check for is whether there is a label on
7038 this instruction. If there are any branches to anything other than
7039 a label, users must use .set noreorder. */
7040 if (seg_info (now_seg
)->label_list
)
7043 /* If the previous instruction is in a variant frag other than this
7044 branch's one, we cannot do the swap. This does not apply to
7045 MIPS16 code, which uses variant frags for different purposes. */
7046 if (!mips_opts
.mips16
7048 && history
[0].frag
->fr_type
== rs_machine_dependent
)
7051 /* We do not swap with instructions that cannot architecturally
7052 be placed in a branch delay slot, such as SYNC or ERET. We
7053 also refrain from swapping with a trap instruction, since it
7054 complicates trap handlers to have the trap instruction be in
7056 prev_pinfo
= history
[0].insn_mo
->pinfo
;
7057 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
7060 /* Check for conflicts between the branch and the instructions
7061 before the candidate delay slot. */
7062 if (nops_for_insn (0, history
+ 1, ip
) > 0)
7065 /* Check for conflicts between the swapped sequence and the
7066 target of the branch. */
7067 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
7070 /* If the branch reads a register that the previous
7071 instruction sets, we can not swap. */
7072 gpr_read
= gpr_read_mask (ip
);
7073 prev_gpr_write
= gpr_write_mask (&history
[0]);
7074 if (gpr_read
& prev_gpr_write
)
7077 fpr_read
= fpr_read_mask (ip
);
7078 prev_fpr_write
= fpr_write_mask (&history
[0]);
7079 if (fpr_read
& prev_fpr_write
)
7082 /* If the branch writes a register that the previous
7083 instruction sets, we can not swap. */
7084 gpr_write
= gpr_write_mask (ip
);
7085 if (gpr_write
& prev_gpr_write
)
7088 /* If the branch writes a register that the previous
7089 instruction reads, we can not swap. */
7090 prev_gpr_read
= gpr_read_mask (&history
[0]);
7091 if (gpr_write
& prev_gpr_read
)
7094 /* If one instruction sets a condition code and the
7095 other one uses a condition code, we can not swap. */
7096 pinfo
= ip
->insn_mo
->pinfo
;
7097 if ((pinfo
& INSN_READ_COND_CODE
)
7098 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
7100 if ((pinfo
& INSN_WRITE_COND_CODE
)
7101 && (prev_pinfo
& INSN_READ_COND_CODE
))
7104 /* If the previous instruction uses the PC, we can not swap. */
7105 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7106 if (prev_pinfo2
& INSN2_READ_PC
)
7109 /* If the previous instruction has an incorrect size for a fixed
7110 branch delay slot in microMIPS mode, we cannot swap. */
7111 pinfo2
= ip
->insn_mo
->pinfo2
;
7112 if (mips_opts
.micromips
7113 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
7114 && insn_length (history
) != 2)
7116 if (mips_opts
.micromips
7117 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
7118 && insn_length (history
) != 4)
7121 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7124 The short loop bug under certain conditions causes loops to execute
7125 only once or twice. We must ensure that the assembler never
7126 generates loops that satisfy all of the following conditions:
7128 - a loop consists of less than or equal to six instructions
7129 (including the branch delay slot);
7130 - a loop contains only one conditional branch instruction at the end
7132 - a loop does not contain any other branch or jump instructions;
7133 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7135 We need to do this because of a hardware bug in the R5900 chip. */
7137 /* Check if instruction has a parameter, ignore "j $31". */
7138 && (address_expr
!= NULL
)
7139 /* Parameter must be 16 bit. */
7140 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7141 /* Branch to same segment. */
7142 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7143 /* Branch to same code fragment. */
7144 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7145 /* Can only calculate branch offset if value is known. */
7146 && symbol_constant_p (address_expr
->X_add_symbol
)
7147 /* Check if branch is really conditional. */
7148 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7149 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7150 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7153 /* Check if loop is shorter than or equal to 6 instructions
7154 including branch and delay slot. */
7155 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7162 /* When the loop includes branches or jumps,
7163 it is not a short loop. */
7164 for (i
= 0; i
< (distance
/ 4); i
++)
7166 if ((history
[i
].cleared_p
)
7167 || delayed_branch_p (&history
[i
]))
7175 /* Insert nop after branch to fix short loop. */
7184 /* Decide how we should add IP to the instruction stream.
7185 ADDRESS_EXPR is an operand of the instruction to be used with
7188 static enum append_method
7189 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7190 bfd_reloc_code_real_type
*reloc_type
)
7192 /* The relaxed version of a macro sequence must be inherently
7194 if (mips_relax
.sequence
== 2)
7197 /* We must not dabble with instructions in a ".set noreorder" block. */
7198 if (mips_opts
.noreorder
)
7201 /* Otherwise, it's our responsibility to fill branch delay slots. */
7202 if (delayed_branch_p (ip
))
7204 if (!branch_likely_p (ip
)
7205 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7208 if (mips_opts
.mips16
7209 && ISA_SUPPORTS_MIPS16E
7210 && gpr_read_mask (ip
) != 0)
7211 return APPEND_ADD_COMPACT
;
7213 if (mips_opts
.micromips
7214 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7215 || (!forced_insn_length
7216 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7217 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7218 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7219 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7220 return APPEND_ADD_COMPACT
;
7222 return APPEND_ADD_WITH_NOP
;
7228 /* IP is an instruction whose opcode we have just changed, END points
7229 to the end of the opcode table processed. Point IP->insn_mo to the
7230 new opcode's definition. */
7233 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7235 const struct mips_opcode
*mo
;
7237 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7238 if (mo
->pinfo
!= INSN_MACRO
7239 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7247 /* IP is a MIPS16 instruction whose opcode we have just changed.
7248 Point IP->insn_mo to the new opcode's definition. */
7251 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7253 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7256 /* IP is a microMIPS instruction whose opcode we have just changed.
7257 Point IP->insn_mo to the new opcode's definition. */
7260 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7262 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7265 /* For microMIPS macros, we need to generate a local number label
7266 as the target of branches. */
7267 #define MICROMIPS_LABEL_CHAR '\037'
7268 static unsigned long micromips_target_label
;
7269 static char micromips_target_name
[32];
7272 micromips_label_name (void)
7274 char *p
= micromips_target_name
;
7275 char symbol_name_temporary
[24];
7283 l
= micromips_target_label
;
7284 #ifdef LOCAL_LABEL_PREFIX
7285 *p
++ = LOCAL_LABEL_PREFIX
;
7288 *p
++ = MICROMIPS_LABEL_CHAR
;
7291 symbol_name_temporary
[i
++] = l
% 10 + '0';
7296 *p
++ = symbol_name_temporary
[--i
];
7299 return micromips_target_name
;
7303 micromips_label_expr (expressionS
*label_expr
)
7305 label_expr
->X_op
= O_symbol
;
7306 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7307 label_expr
->X_add_number
= 0;
7311 micromips_label_inc (void)
7313 micromips_target_label
++;
7314 *micromips_target_name
= '\0';
7318 micromips_add_label (void)
7322 s
= colon (micromips_label_name ());
7323 micromips_label_inc ();
7324 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7327 /* If assembling microMIPS code, then return the microMIPS reloc
7328 corresponding to the requested one if any. Otherwise return
7329 the reloc unchanged. */
7331 static bfd_reloc_code_real_type
7332 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7334 static const bfd_reloc_code_real_type relocs
[][2] =
7336 /* Keep sorted incrementally by the left-hand key. */
7337 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7338 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7339 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7340 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7341 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7342 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7343 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7344 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7345 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7346 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7347 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7348 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7349 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7350 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7351 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7352 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7353 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7354 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7355 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7356 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7357 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7358 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7359 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7360 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7361 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7362 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7363 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7365 bfd_reloc_code_real_type r
;
7368 if (!mips_opts
.micromips
)
7370 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7376 return relocs
[i
][1];
7381 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7382 Return true on success, storing the resolved value in RESULT. */
7385 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7390 case BFD_RELOC_MIPS_HIGHEST
:
7391 case BFD_RELOC_MICROMIPS_HIGHEST
:
7392 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7395 case BFD_RELOC_MIPS_HIGHER
:
7396 case BFD_RELOC_MICROMIPS_HIGHER
:
7397 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7400 case BFD_RELOC_HI16_S
:
7401 case BFD_RELOC_HI16_S_PCREL
:
7402 case BFD_RELOC_MICROMIPS_HI16_S
:
7403 case BFD_RELOC_MIPS16_HI16_S
:
7404 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7407 case BFD_RELOC_HI16
:
7408 case BFD_RELOC_MICROMIPS_HI16
:
7409 case BFD_RELOC_MIPS16_HI16
:
7410 *result
= (operand
>> 16) & 0xffff;
7413 case BFD_RELOC_LO16
:
7414 case BFD_RELOC_LO16_PCREL
:
7415 case BFD_RELOC_MICROMIPS_LO16
:
7416 case BFD_RELOC_MIPS16_LO16
:
7417 *result
= operand
& 0xffff;
7420 case BFD_RELOC_UNUSED
:
7429 /* Output an instruction. IP is the instruction information.
7430 ADDRESS_EXPR is an operand of the instruction to be used with
7431 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7432 a macro expansion. */
7435 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7436 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7438 unsigned long prev_pinfo2
, pinfo
;
7439 bfd_boolean relaxed_branch
= FALSE
;
7440 enum append_method method
;
7441 bfd_boolean relax32
;
7444 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7445 fix_loongson2f (ip
);
7447 ip
->target
[0] = '\0';
7448 if (offset_expr
.X_op
== O_symbol
)
7449 strncpy (ip
->target
, S_GET_NAME (offset_expr
.X_add_symbol
), 15);
7450 ip
->label
[0] = '\0';
7451 if (seg_info (now_seg
)->label_list
)
7452 strncpy (ip
->label
, S_GET_NAME (seg_info (now_seg
)->label_list
->label
), 15);
7453 if (mips_fix_loongson3_llsc
&& !HAVE_CODE_COMPRESSION
)
7454 fix_loongson3_llsc (ip
);
7456 file_ase_mips16
|= mips_opts
.mips16
;
7457 file_ase_micromips
|= mips_opts
.micromips
;
7459 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7460 pinfo
= ip
->insn_mo
->pinfo
;
7462 /* Don't raise alarm about `nods' frags as they'll fill in the right
7463 kind of nop in relaxation if required. */
7464 if (mips_opts
.micromips
7466 && !(history
[0].frag
7467 && history
[0].frag
->fr_type
== rs_machine_dependent
7468 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7469 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7470 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7471 && micromips_insn_length (ip
->insn_mo
) != 2)
7472 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7473 && micromips_insn_length (ip
->insn_mo
) != 4)))
7474 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7475 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7477 if (address_expr
== NULL
)
7479 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7480 && reloc_type
[1] == BFD_RELOC_UNUSED
7481 && reloc_type
[2] == BFD_RELOC_UNUSED
7482 && address_expr
->X_op
== O_constant
)
7484 switch (*reloc_type
)
7486 case BFD_RELOC_MIPS_JMP
:
7490 /* Shift is 2, unusually, for microMIPS JALX. */
7491 shift
= (mips_opts
.micromips
7492 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7493 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7494 as_bad (_("jump to misaligned address (0x%lx)"),
7495 (unsigned long) address_expr
->X_add_number
);
7496 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7502 case BFD_RELOC_MIPS16_JMP
:
7503 if ((address_expr
->X_add_number
& 3) != 0)
7504 as_bad (_("jump to misaligned address (0x%lx)"),
7505 (unsigned long) address_expr
->X_add_number
);
7507 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7508 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7509 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7513 case BFD_RELOC_16_PCREL_S2
:
7517 shift
= mips_opts
.micromips
? 1 : 2;
7518 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7519 as_bad (_("branch to misaligned address (0x%lx)"),
7520 (unsigned long) address_expr
->X_add_number
);
7521 if (!mips_relax_branch
)
7523 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7524 & ~((1 << (shift
+ 16)) - 1))
7525 as_bad (_("branch address range overflow (0x%lx)"),
7526 (unsigned long) address_expr
->X_add_number
);
7527 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7533 case BFD_RELOC_MIPS_21_PCREL_S2
:
7538 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7539 as_bad (_("branch to misaligned address (0x%lx)"),
7540 (unsigned long) address_expr
->X_add_number
);
7541 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7542 & ~((1 << (shift
+ 21)) - 1))
7543 as_bad (_("branch address range overflow (0x%lx)"),
7544 (unsigned long) address_expr
->X_add_number
);
7545 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7550 case BFD_RELOC_MIPS_26_PCREL_S2
:
7555 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7556 as_bad (_("branch to misaligned address (0x%lx)"),
7557 (unsigned long) address_expr
->X_add_number
);
7558 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7559 & ~((1 << (shift
+ 26)) - 1))
7560 as_bad (_("branch address range overflow (0x%lx)"),
7561 (unsigned long) address_expr
->X_add_number
);
7562 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7571 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7574 ip
->insn_opcode
|= value
& 0xffff;
7582 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7584 /* There are a lot of optimizations we could do that we don't.
7585 In particular, we do not, in general, reorder instructions.
7586 If you use gcc with optimization, it will reorder
7587 instructions and generally do much more optimization then we
7588 do here; repeating all that work in the assembler would only
7589 benefit hand written assembly code, and does not seem worth
7591 int nops
= (mips_optimize
== 0
7592 ? nops_for_insn (0, history
, NULL
)
7593 : nops_for_insn_or_target (0, history
, ip
));
7597 unsigned long old_frag_offset
;
7600 old_frag
= frag_now
;
7601 old_frag_offset
= frag_now_fix ();
7603 for (i
= 0; i
< nops
; i
++)
7604 add_fixed_insn (NOP_INSN
);
7605 insert_into_history (0, nops
, NOP_INSN
);
7609 listing_prev_line ();
7610 /* We may be at the start of a variant frag. In case we
7611 are, make sure there is enough space for the frag
7612 after the frags created by listing_prev_line. The
7613 argument to frag_grow here must be at least as large
7614 as the argument to all other calls to frag_grow in
7615 this file. We don't have to worry about being in the
7616 middle of a variant frag, because the variants insert
7617 all needed nop instructions themselves. */
7621 mips_move_text_labels ();
7623 #ifndef NO_ECOFF_DEBUGGING
7624 if (ECOFF_DEBUGGING
)
7625 ecoff_fix_loc (old_frag
, old_frag_offset
);
7629 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7633 /* Work out how many nops in prev_nop_frag are needed by IP,
7634 ignoring hazards generated by the first prev_nop_frag_since
7636 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7637 gas_assert (nops
<= prev_nop_frag_holds
);
7639 /* Enforce NOPS as a minimum. */
7640 if (nops
> prev_nop_frag_required
)
7641 prev_nop_frag_required
= nops
;
7643 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7645 /* Settle for the current number of nops. Update the history
7646 accordingly (for the benefit of any future .set reorder code). */
7647 prev_nop_frag
= NULL
;
7648 insert_into_history (prev_nop_frag_since
,
7649 prev_nop_frag_holds
, NOP_INSN
);
7653 /* Allow this instruction to replace one of the nops that was
7654 tentatively added to prev_nop_frag. */
7655 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7656 prev_nop_frag_holds
--;
7657 prev_nop_frag_since
++;
7661 method
= get_append_method (ip
, address_expr
, reloc_type
);
7662 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7664 dwarf2_emit_insn (0);
7665 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7666 so "move" the instruction address accordingly.
7668 Also, it doesn't seem appropriate for the assembler to reorder .loc
7669 entries. If this instruction is a branch that we are going to swap
7670 with the previous instruction, the two instructions should be
7671 treated as a unit, and the debug information for both instructions
7672 should refer to the start of the branch sequence. Using the
7673 current position is certainly wrong when swapping a 32-bit branch
7674 and a 16-bit delay slot, since the current position would then be
7675 in the middle of a branch. */
7676 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7678 relax32
= (mips_relax_branch
7679 /* Don't try branch relaxation within .set nomacro, or within
7680 .set noat if we use $at for PIC computations. If it turns
7681 out that the branch was out-of-range, we'll get an error. */
7682 && !mips_opts
.warn_about_macros
7683 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7684 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7685 as they have no complementing branches. */
7686 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7688 if (!HAVE_CODE_COMPRESSION
7691 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7692 && delayed_branch_p (ip
))
7694 relaxed_branch
= TRUE
;
7695 add_relaxed_insn (ip
, (relaxed_branch_length
7697 uncond_branch_p (ip
) ? -1
7698 : branch_likely_p (ip
) ? 1
7701 (AT
, mips_pic
!= NO_PIC
,
7702 uncond_branch_p (ip
),
7703 branch_likely_p (ip
),
7704 pinfo
& INSN_WRITE_GPR_31
,
7706 address_expr
->X_add_symbol
,
7707 address_expr
->X_add_number
);
7708 *reloc_type
= BFD_RELOC_UNUSED
;
7710 else if (mips_opts
.micromips
7712 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7713 || *reloc_type
> BFD_RELOC_UNUSED
)
7714 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7715 /* Don't try branch relaxation when users specify
7716 16-bit/32-bit instructions. */
7717 && !forced_insn_length
)
7719 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7720 && *reloc_type
> BFD_RELOC_UNUSED
);
7721 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7722 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7723 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7724 int nods
= method
== APPEND_ADD_WITH_NOP
;
7725 int al
= pinfo
& INSN_WRITE_GPR_31
;
7726 int length32
= nods
? 8 : 4;
7728 gas_assert (address_expr
!= NULL
);
7729 gas_assert (!mips_relax
.sequence
);
7731 relaxed_branch
= TRUE
;
7733 method
= APPEND_ADD
;
7735 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7736 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7737 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7739 uncond
, compact
, al
, nods
,
7741 address_expr
->X_add_symbol
,
7742 address_expr
->X_add_number
);
7743 *reloc_type
= BFD_RELOC_UNUSED
;
7745 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7747 bfd_boolean require_unextended
;
7748 bfd_boolean require_extended
;
7752 if (forced_insn_length
!= 0)
7754 require_unextended
= forced_insn_length
== 2;
7755 require_extended
= forced_insn_length
== 4;
7759 require_unextended
= (mips_opts
.noautoextend
7760 && !mips_opcode_32bit_p (ip
->insn_mo
));
7761 require_extended
= 0;
7764 /* We need to set up a variant frag. */
7765 gas_assert (address_expr
!= NULL
);
7766 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7767 symbol created by `make_expr_symbol' may not get a necessary
7768 external relocation produced. */
7769 if (address_expr
->X_op
== O_symbol
)
7771 symbol
= address_expr
->X_add_symbol
;
7772 offset
= address_expr
->X_add_number
;
7776 symbol
= make_expr_symbol (address_expr
);
7777 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7780 add_relaxed_insn (ip
, 12, 0,
7782 (*reloc_type
- BFD_RELOC_UNUSED
,
7783 mips_opts
.ase
& ASE_MIPS16E2
,
7786 mips_opts
.warn_about_macros
,
7787 require_unextended
, require_extended
,
7788 delayed_branch_p (&history
[0]),
7789 history
[0].mips16_absolute_jump_p
),
7792 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7794 if (!delayed_branch_p (ip
))
7795 /* Make sure there is enough room to swap this instruction with
7796 a following jump instruction. */
7798 add_fixed_insn (ip
);
7802 if (mips_opts
.mips16
7803 && mips_opts
.noreorder
7804 && delayed_branch_p (&history
[0]))
7805 as_warn (_("extended instruction in delay slot"));
7807 if (mips_relax
.sequence
)
7809 /* If we've reached the end of this frag, turn it into a variant
7810 frag and record the information for the instructions we've
7812 if (frag_room () < 4)
7813 relax_close_frag ();
7814 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7817 if (mips_relax
.sequence
!= 2)
7819 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7820 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7821 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7822 mips_macro_warning
.insns
[0]++;
7824 if (mips_relax
.sequence
!= 1)
7826 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7827 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7828 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7829 mips_macro_warning
.insns
[1]++;
7832 if (mips_opts
.mips16
)
7835 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7837 add_fixed_insn (ip
);
7840 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7842 bfd_reloc_code_real_type final_type
[3];
7843 reloc_howto_type
*howto0
;
7844 reloc_howto_type
*howto
;
7847 /* Perform any necessary conversion to microMIPS relocations
7848 and find out how many relocations there actually are. */
7849 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7850 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7852 /* In a compound relocation, it is the final (outermost)
7853 operator that determines the relocated field. */
7854 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7859 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7860 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7861 bfd_get_reloc_size (howto
),
7863 howto0
&& howto0
->pc_relative
,
7865 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7866 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7868 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7869 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7870 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7872 /* These relocations can have an addend that won't fit in
7873 4 octets for 64bit assembly. */
7875 && ! howto
->partial_inplace
7876 && (reloc_type
[0] == BFD_RELOC_16
7877 || reloc_type
[0] == BFD_RELOC_32
7878 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7879 || reloc_type
[0] == BFD_RELOC_GPREL16
7880 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7881 || reloc_type
[0] == BFD_RELOC_GPREL32
7882 || reloc_type
[0] == BFD_RELOC_64
7883 || reloc_type
[0] == BFD_RELOC_CTOR
7884 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7885 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7886 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7887 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7888 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7889 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7890 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7891 || hi16_reloc_p (reloc_type
[0])
7892 || lo16_reloc_p (reloc_type
[0])))
7893 ip
->fixp
[0]->fx_no_overflow
= 1;
7895 /* These relocations can have an addend that won't fit in 2 octets. */
7896 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7897 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7898 ip
->fixp
[0]->fx_no_overflow
= 1;
7900 if (mips_relax
.sequence
)
7902 if (mips_relax
.first_fixup
== 0)
7903 mips_relax
.first_fixup
= ip
->fixp
[0];
7905 else if (reloc_needs_lo_p (*reloc_type
))
7907 struct mips_hi_fixup
*hi_fixup
;
7909 /* Reuse the last entry if it already has a matching %lo. */
7910 hi_fixup
= mips_hi_fixup_list
;
7912 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7914 hi_fixup
= XNEW (struct mips_hi_fixup
);
7915 hi_fixup
->next
= mips_hi_fixup_list
;
7916 mips_hi_fixup_list
= hi_fixup
;
7918 hi_fixup
->fixp
= ip
->fixp
[0];
7919 hi_fixup
->seg
= now_seg
;
7922 /* Add fixups for the second and third relocations, if given.
7923 Note that the ABI allows the second relocation to be
7924 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7925 moment we only use RSS_UNDEF, but we could add support
7926 for the others if it ever becomes necessary. */
7927 for (i
= 1; i
< 3; i
++)
7928 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7930 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7931 ip
->fixp
[0]->fx_size
, NULL
, 0,
7932 FALSE
, final_type
[i
]);
7934 /* Use fx_tcbit to mark compound relocs. */
7935 ip
->fixp
[0]->fx_tcbit
= 1;
7936 ip
->fixp
[i
]->fx_tcbit
= 1;
7940 /* Update the register mask information. */
7941 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7942 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7947 insert_into_history (0, 1, ip
);
7950 case APPEND_ADD_WITH_NOP
:
7952 struct mips_cl_insn
*nop
;
7954 insert_into_history (0, 1, ip
);
7955 nop
= get_delay_slot_nop (ip
);
7956 add_fixed_insn (nop
);
7957 insert_into_history (0, 1, nop
);
7958 if (mips_relax
.sequence
)
7959 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7963 case APPEND_ADD_COMPACT
:
7964 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7965 if (mips_opts
.mips16
)
7967 ip
->insn_opcode
|= 0x0080;
7968 find_altered_mips16_opcode (ip
);
7970 /* Convert microMIPS instructions. */
7971 else if (mips_opts
.micromips
)
7974 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7975 ip
->insn_opcode
|= 0x0020;
7977 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7978 ip
->insn_opcode
= 0x40e00000;
7979 /* beqz16->beqzc, bnez16->bnezc */
7980 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7982 unsigned long regno
;
7984 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7985 regno
&= MICROMIPSOP_MASK_MD
;
7986 regno
= micromips_to_32_reg_d_map
[regno
];
7987 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7988 | (regno
<< MICROMIPSOP_SH_RS
)
7989 | 0x40a00000) ^ 0x00400000;
7991 /* beqz->beqzc, bnez->bnezc */
7992 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7993 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7994 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7995 | 0x40a00000) ^ 0x00400000;
7996 /* beq $0->beqzc, bne $0->bnezc */
7997 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7998 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7999 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
8000 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
8001 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8002 | 0x40a00000) ^ 0x00400000;
8005 find_altered_micromips_opcode (ip
);
8010 insert_into_history (0, 1, ip
);
8015 struct mips_cl_insn delay
= history
[0];
8017 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
8019 /* Add the delay slot instruction to the end of the
8020 current frag and shrink the fixed part of the
8021 original frag. If the branch occupies the tail of
8022 the latter, move it backwards to cover the gap. */
8023 delay
.frag
->fr_fix
-= branch_disp
;
8024 if (delay
.frag
== ip
->frag
)
8025 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
8026 add_fixed_insn (&delay
);
8030 /* If this is not a relaxed branch and we are in the
8031 same frag, then just swap the instructions. */
8032 move_insn (ip
, delay
.frag
, delay
.where
);
8033 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
8037 insert_into_history (0, 1, &delay
);
8042 /* If we have just completed an unconditional branch, clear the history. */
8043 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
8044 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
8048 mips_no_prev_insn ();
8050 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8051 history
[i
].cleared_p
= 1;
8054 /* We need to emit a label at the end of branch-likely macros. */
8055 if (emit_branch_likely_macro
)
8057 emit_branch_likely_macro
= FALSE
;
8058 micromips_add_label ();
8061 /* We just output an insn, so the next one doesn't have a label. */
8062 mips_clear_insn_labels ();
8065 /* Forget that there was any previous instruction or label.
8066 When BRANCH is true, the branch history is also flushed. */
8069 mips_no_prev_insn (void)
8071 prev_nop_frag
= NULL
;
8072 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
8073 mips_clear_insn_labels ();
8076 /* This function must be called before we emit something other than
8077 instructions. It is like mips_no_prev_insn except that it inserts
8078 any NOPS that might be needed by previous instructions. */
8081 mips_emit_delays (void)
8083 if (! mips_opts
.noreorder
)
8085 int nops
= nops_for_insn (0, history
, NULL
);
8089 add_fixed_insn (NOP_INSN
);
8090 mips_move_text_labels ();
8093 mips_no_prev_insn ();
8096 /* Start a (possibly nested) noreorder block. */
8099 start_noreorder (void)
8101 if (mips_opts
.noreorder
== 0)
8106 /* None of the instructions before the .set noreorder can be moved. */
8107 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8108 history
[i
].fixed_p
= 1;
8110 /* Insert any nops that might be needed between the .set noreorder
8111 block and the previous instructions. We will later remove any
8112 nops that turn out not to be needed. */
8113 nops
= nops_for_insn (0, history
, NULL
);
8116 if (mips_optimize
!= 0)
8118 /* Record the frag which holds the nop instructions, so
8119 that we can remove them if we don't need them. */
8120 frag_grow (nops
* NOP_INSN_SIZE
);
8121 prev_nop_frag
= frag_now
;
8122 prev_nop_frag_holds
= nops
;
8123 prev_nop_frag_required
= 0;
8124 prev_nop_frag_since
= 0;
8127 for (; nops
> 0; --nops
)
8128 add_fixed_insn (NOP_INSN
);
8130 /* Move on to a new frag, so that it is safe to simply
8131 decrease the size of prev_nop_frag. */
8132 frag_wane (frag_now
);
8134 mips_move_text_labels ();
8136 mips_mark_labels ();
8137 mips_clear_insn_labels ();
8139 mips_opts
.noreorder
++;
8140 mips_any_noreorder
= 1;
8143 /* End a nested noreorder block. */
8146 end_noreorder (void)
8148 mips_opts
.noreorder
--;
8149 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8151 /* Commit to inserting prev_nop_frag_required nops and go back to
8152 handling nop insertion the .set reorder way. */
8153 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8155 insert_into_history (prev_nop_frag_since
,
8156 prev_nop_frag_required
, NOP_INSN
);
8157 prev_nop_frag
= NULL
;
8161 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8162 higher bits unset. */
8165 normalize_constant_expr (expressionS
*ex
)
8167 if (ex
->X_op
== O_constant
8168 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8169 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8173 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8174 all higher bits unset. */
8177 normalize_address_expr (expressionS
*ex
)
8179 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8180 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8181 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8182 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8186 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8187 Return true if the match was successful.
8189 OPCODE_EXTRA is a value that should be ORed into the opcode
8190 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8191 there are more alternatives after OPCODE and SOFT_MATCH is
8192 as for mips_arg_info. */
8195 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8196 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8197 bfd_boolean lax_match
, bfd_boolean complete_p
)
8200 struct mips_arg_info arg
;
8201 const struct mips_operand
*operand
;
8204 imm_expr
.X_op
= O_absent
;
8205 offset_expr
.X_op
= O_absent
;
8206 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8207 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8208 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8210 create_insn (insn
, opcode
);
8211 /* When no opcode suffix is specified, assume ".xyzw". */
8212 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8213 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8215 insn
->insn_opcode
|= opcode_extra
;
8216 memset (&arg
, 0, sizeof (arg
));
8220 arg
.last_regno
= ILLEGAL_REG
;
8221 arg
.dest_regno
= ILLEGAL_REG
;
8222 arg
.lax_match
= lax_match
;
8223 for (args
= opcode
->args
;; ++args
)
8225 if (arg
.token
->type
== OT_END
)
8227 /* Handle unary instructions in which only one operand is given.
8228 The source is then the same as the destination. */
8229 if (arg
.opnum
== 1 && *args
== ',')
8231 operand
= (mips_opts
.micromips
8232 ? decode_micromips_operand (args
+ 1)
8233 : decode_mips_operand (args
+ 1));
8234 if (operand
&& mips_optional_operand_p (operand
))
8242 /* Treat elided base registers as $0. */
8243 if (strcmp (args
, "(b)") == 0)
8251 /* The register suffix is optional. */
8256 /* Fail the match if there were too few operands. */
8260 /* Successful match. */
8263 clear_insn_error ();
8264 if (arg
.dest_regno
== arg
.last_regno
8265 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8269 (0, _("source and destination must be different"));
8270 else if (arg
.last_regno
== 31)
8272 (0, _("a destination register must be supplied"));
8274 else if (arg
.last_regno
== 31
8275 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8276 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8277 set_insn_error (0, _("the source register must not be $31"));
8278 check_completed_insn (&arg
);
8282 /* Fail the match if the line has too many operands. */
8286 /* Handle characters that need to match exactly. */
8287 if (*args
== '(' || *args
== ')' || *args
== ',')
8289 if (match_char (&arg
, *args
))
8296 if (arg
.token
->type
== OT_DOUBLE_CHAR
8297 && arg
.token
->u
.ch
== *args
)
8305 /* Handle special macro operands. Work out the properties of
8314 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8318 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8327 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8331 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8335 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8341 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8343 imm_expr
.X_op
= O_constant
;
8345 normalize_constant_expr (&imm_expr
);
8349 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8351 /* Assume that the offset has been elided and that what
8352 we saw was a base register. The match will fail later
8353 if that assumption turns out to be wrong. */
8354 offset_expr
.X_op
= O_constant
;
8355 offset_expr
.X_add_number
= 0;
8359 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8361 normalize_address_expr (&offset_expr
);
8366 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8372 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8378 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8384 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8390 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8394 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8398 gas_assert (mips_opts
.micromips
);
8404 if (!forced_insn_length
)
8405 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8407 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8409 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8415 operand
= (mips_opts
.micromips
8416 ? decode_micromips_operand (args
)
8417 : decode_mips_operand (args
));
8421 /* Skip prefixes. */
8422 if (*args
== '+' || *args
== 'm' || *args
== '-')
8425 if (mips_optional_operand_p (operand
)
8427 && (arg
.token
[0].type
!= OT_REG
8428 || arg
.token
[1].type
== OT_END
))
8430 /* Assume that the register has been elided and is the
8431 same as the first operand. */
8436 if (!match_operand (&arg
, operand
))
8441 /* Like match_insn, but for MIPS16. */
8444 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8445 struct mips_operand_token
*tokens
)
8448 const struct mips_operand
*operand
;
8449 const struct mips_operand
*ext_operand
;
8450 bfd_boolean pcrel
= FALSE
;
8451 int required_insn_length
;
8452 struct mips_arg_info arg
;
8455 if (forced_insn_length
)
8456 required_insn_length
= forced_insn_length
;
8457 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8458 required_insn_length
= 2;
8460 required_insn_length
= 0;
8462 create_insn (insn
, opcode
);
8463 imm_expr
.X_op
= O_absent
;
8464 offset_expr
.X_op
= O_absent
;
8465 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8466 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8467 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8470 memset (&arg
, 0, sizeof (arg
));
8474 arg
.last_regno
= ILLEGAL_REG
;
8475 arg
.dest_regno
= ILLEGAL_REG
;
8477 for (args
= opcode
->args
;; ++args
)
8481 if (arg
.token
->type
== OT_END
)
8485 /* Handle unary instructions in which only one operand is given.
8486 The source is then the same as the destination. */
8487 if (arg
.opnum
== 1 && *args
== ',')
8489 operand
= decode_mips16_operand (args
[1], FALSE
);
8490 if (operand
&& mips_optional_operand_p (operand
))
8498 /* Fail the match if there were too few operands. */
8502 /* Successful match. Stuff the immediate value in now, if
8504 clear_insn_error ();
8505 if (opcode
->pinfo
== INSN_MACRO
)
8507 gas_assert (relax_char
== 0 || relax_char
== 'p');
8508 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8511 && offset_expr
.X_op
== O_constant
8513 && calculate_reloc (*offset_reloc
,
8514 offset_expr
.X_add_number
,
8517 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8518 required_insn_length
, &insn
->insn_opcode
);
8519 offset_expr
.X_op
= O_absent
;
8520 *offset_reloc
= BFD_RELOC_UNUSED
;
8522 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8524 if (required_insn_length
== 2)
8525 set_insn_error (0, _("invalid unextended operand value"));
8526 else if (!mips_opcode_32bit_p (opcode
))
8528 forced_insn_length
= 4;
8529 insn
->insn_opcode
|= MIPS16_EXTEND
;
8532 else if (relax_char
)
8533 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8535 check_completed_insn (&arg
);
8539 /* Fail the match if the line has too many operands. */
8543 /* Handle characters that need to match exactly. */
8544 if (*args
== '(' || *args
== ')' || *args
== ',')
8546 if (match_char (&arg
, *args
))
8566 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8568 imm_expr
.X_op
= O_constant
;
8570 normalize_constant_expr (&imm_expr
);
8575 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8579 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8583 if (operand
->type
== OP_PCREL
)
8587 ext_operand
= decode_mips16_operand (c
, TRUE
);
8588 if (operand
!= ext_operand
)
8590 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8592 offset_expr
.X_op
= O_constant
;
8593 offset_expr
.X_add_number
= 0;
8598 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8601 /* '8' is used for SLTI(U) and has traditionally not
8602 been allowed to take relocation operators. */
8603 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8604 && (ext_operand
->size
!= 16 || c
== '8'))
8606 match_not_constant (&arg
);
8610 if (offset_expr
.X_op
== O_big
)
8612 match_out_of_range (&arg
);
8621 if (mips_optional_operand_p (operand
)
8623 && (arg
.token
[0].type
!= OT_REG
8624 || arg
.token
[1].type
== OT_END
))
8626 /* Assume that the register has been elided and is the
8627 same as the first operand. */
8632 if (!match_operand (&arg
, operand
))
8637 /* Record that the current instruction is invalid for the current ISA. */
8640 match_invalid_for_isa (void)
8643 (0, _("opcode not supported on this processor: %s (%s)"),
8644 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8645 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8648 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8649 Return true if a definite match or failure was found, storing any match
8650 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8651 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8652 tried and failed to match under normal conditions and now want to try a
8653 more relaxed match. */
8656 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8657 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8658 int opcode_extra
, bfd_boolean lax_match
)
8660 const struct mips_opcode
*opcode
;
8661 const struct mips_opcode
*invalid_delay_slot
;
8662 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8664 /* Search for a match, ignoring alternatives that don't satisfy the
8665 current ISA or forced_length. */
8666 invalid_delay_slot
= 0;
8667 seen_valid_for_isa
= FALSE
;
8668 seen_valid_for_size
= FALSE
;
8672 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8673 if (is_opcode_valid (opcode
))
8675 seen_valid_for_isa
= TRUE
;
8676 if (is_size_valid (opcode
))
8678 bfd_boolean delay_slot_ok
;
8680 seen_valid_for_size
= TRUE
;
8681 delay_slot_ok
= is_delay_slot_valid (opcode
);
8682 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8683 lax_match
, delay_slot_ok
))
8687 if (!invalid_delay_slot
)
8688 invalid_delay_slot
= opcode
;
8697 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8699 /* If the only matches we found had the wrong length for the delay slot,
8700 pick the first such match. We'll issue an appropriate warning later. */
8701 if (invalid_delay_slot
)
8703 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8709 /* Handle the case where we didn't try to match an instruction because
8710 all the alternatives were incompatible with the current ISA. */
8711 if (!seen_valid_for_isa
)
8713 match_invalid_for_isa ();
8717 /* Handle the case where we didn't try to match an instruction because
8718 all the alternatives were of the wrong size. */
8719 if (!seen_valid_for_size
)
8721 if (mips_opts
.insn32
)
8722 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8725 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8726 8 * forced_insn_length
);
8733 /* Like match_insns, but for MIPS16. */
8736 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8737 struct mips_operand_token
*tokens
)
8739 const struct mips_opcode
*opcode
;
8740 bfd_boolean seen_valid_for_isa
;
8741 bfd_boolean seen_valid_for_size
;
8743 /* Search for a match, ignoring alternatives that don't satisfy the
8744 current ISA. There are no separate entries for extended forms so
8745 we deal with forced_length later. */
8746 seen_valid_for_isa
= FALSE
;
8747 seen_valid_for_size
= FALSE
;
8751 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8752 if (is_opcode_valid_16 (opcode
))
8754 seen_valid_for_isa
= TRUE
;
8755 if (is_size_valid_16 (opcode
))
8757 seen_valid_for_size
= TRUE
;
8758 if (match_mips16_insn (insn
, opcode
, tokens
))
8764 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8765 && strcmp (opcode
->name
, first
->name
) == 0);
8767 /* Handle the case where we didn't try to match an instruction because
8768 all the alternatives were incompatible with the current ISA. */
8769 if (!seen_valid_for_isa
)
8771 match_invalid_for_isa ();
8775 /* Handle the case where we didn't try to match an instruction because
8776 all the alternatives were of the wrong size. */
8777 if (!seen_valid_for_size
)
8779 if (forced_insn_length
== 2)
8781 (0, _("unrecognized unextended version of MIPS16 opcode"));
8784 (0, _("unrecognized extended version of MIPS16 opcode"));
8791 /* Set up global variables for the start of a new macro. */
8796 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8797 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8798 sizeof (mips_macro_warning
.first_insn_sizes
));
8799 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8800 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8801 && delayed_branch_p (&history
[0]));
8803 && history
[0].frag
->fr_type
== rs_machine_dependent
8804 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8805 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8806 mips_macro_warning
.delay_slot_length
= 0;
8808 switch (history
[0].insn_mo
->pinfo2
8809 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8811 case INSN2_BRANCH_DELAY_32BIT
:
8812 mips_macro_warning
.delay_slot_length
= 4;
8814 case INSN2_BRANCH_DELAY_16BIT
:
8815 mips_macro_warning
.delay_slot_length
= 2;
8818 mips_macro_warning
.delay_slot_length
= 0;
8821 mips_macro_warning
.first_frag
= NULL
;
8824 /* Given that a macro is longer than one instruction or of the wrong size,
8825 return the appropriate warning for it. Return null if no warning is
8826 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8827 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8828 and RELAX_NOMACRO. */
8831 macro_warning (relax_substateT subtype
)
8833 if (subtype
& RELAX_DELAY_SLOT
)
8834 return _("macro instruction expanded into multiple instructions"
8835 " in a branch delay slot");
8836 else if (subtype
& RELAX_NOMACRO
)
8837 return _("macro instruction expanded into multiple instructions");
8838 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8839 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8840 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8841 ? _("macro instruction expanded into a wrong size instruction"
8842 " in a 16-bit branch delay slot")
8843 : _("macro instruction expanded into a wrong size instruction"
8844 " in a 32-bit branch delay slot"));
8849 /* Finish up a macro. Emit warnings as appropriate. */
8854 /* Relaxation warning flags. */
8855 relax_substateT subtype
= 0;
8857 /* Check delay slot size requirements. */
8858 if (mips_macro_warning
.delay_slot_length
== 2)
8859 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8860 if (mips_macro_warning
.delay_slot_length
!= 0)
8862 if (mips_macro_warning
.delay_slot_length
8863 != mips_macro_warning
.first_insn_sizes
[0])
8864 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8865 if (mips_macro_warning
.delay_slot_length
8866 != mips_macro_warning
.first_insn_sizes
[1])
8867 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8870 /* Check instruction count requirements. */
8871 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8873 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8874 subtype
|= RELAX_SECOND_LONGER
;
8875 if (mips_opts
.warn_about_macros
)
8876 subtype
|= RELAX_NOMACRO
;
8877 if (mips_macro_warning
.delay_slot_p
)
8878 subtype
|= RELAX_DELAY_SLOT
;
8881 /* If both alternatives fail to fill a delay slot correctly,
8882 emit the warning now. */
8883 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8884 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8889 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8890 | RELAX_DELAY_SLOT_SIZE_FIRST
8891 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8892 msg
= macro_warning (s
);
8894 as_warn ("%s", msg
);
8898 /* If both implementations are longer than 1 instruction, then emit the
8900 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8905 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8906 msg
= macro_warning (s
);
8908 as_warn ("%s", msg
);
8912 /* If any flags still set, then one implementation might need a warning
8913 and the other either will need one of a different kind or none at all.
8914 Pass any remaining flags over to relaxation. */
8915 if (mips_macro_warning
.first_frag
!= NULL
)
8916 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8919 /* Instruction operand formats used in macros that vary between
8920 standard MIPS and microMIPS code. */
8922 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8923 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8924 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8925 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8926 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8927 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8928 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8929 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8931 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8932 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8933 : cop12_fmt[mips_opts.micromips])
8934 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8935 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8936 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8937 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8938 : mem12_fmt[mips_opts.micromips])
8939 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8940 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8941 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8943 /* Read a macro's relocation codes from *ARGS and store them in *R.
8944 The first argument in *ARGS will be either the code for a single
8945 relocation or -1 followed by the three codes that make up a
8946 composite relocation. */
8949 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8953 next
= va_arg (*args
, int);
8955 r
[0] = (bfd_reloc_code_real_type
) next
;
8958 for (i
= 0; i
< 3; i
++)
8959 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8960 /* This function is only used for 16-bit relocation fields.
8961 To make the macro code simpler, treat an unrelocated value
8962 in the same way as BFD_RELOC_LO16. */
8963 if (r
[0] == BFD_RELOC_UNUSED
)
8964 r
[0] = BFD_RELOC_LO16
;
8968 /* Build an instruction created by a macro expansion. This is passed
8969 a pointer to the count of instructions created so far, an
8970 expression, the name of the instruction to build, an operand format
8971 string, and corresponding arguments. */
8974 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8976 const struct mips_opcode
*mo
= NULL
;
8977 bfd_reloc_code_real_type r
[3];
8978 const struct mips_opcode
*amo
;
8979 const struct mips_operand
*operand
;
8980 struct hash_control
*hash
;
8981 struct mips_cl_insn insn
;
8985 va_start (args
, fmt
);
8987 if (mips_opts
.mips16
)
8989 mips16_macro_build (ep
, name
, fmt
, &args
);
8994 r
[0] = BFD_RELOC_UNUSED
;
8995 r
[1] = BFD_RELOC_UNUSED
;
8996 r
[2] = BFD_RELOC_UNUSED
;
8997 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8998 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
9000 gas_assert (strcmp (name
, amo
->name
) == 0);
9004 /* Search until we get a match for NAME. It is assumed here that
9005 macros will never generate MDMX, MIPS-3D, or MT instructions.
9006 We try to match an instruction that fulfills the branch delay
9007 slot instruction length requirement (if any) of the previous
9008 instruction. While doing this we record the first instruction
9009 seen that matches all the other conditions and use it anyway
9010 if the requirement cannot be met; we will issue an appropriate
9011 warning later on. */
9012 if (strcmp (fmt
, amo
->args
) == 0
9013 && amo
->pinfo
!= INSN_MACRO
9014 && is_opcode_valid (amo
)
9015 && is_size_valid (amo
))
9017 if (is_delay_slot_valid (amo
))
9027 gas_assert (amo
->name
);
9029 while (strcmp (name
, amo
->name
) == 0);
9032 create_insn (&insn
, mo
);
9045 macro_read_relocs (&args
, r
);
9046 gas_assert (*r
== BFD_RELOC_GPREL16
9047 || *r
== BFD_RELOC_MIPS_HIGHER
9048 || *r
== BFD_RELOC_HI16_S
9049 || *r
== BFD_RELOC_LO16
9050 || *r
== BFD_RELOC_MIPS_GOT_OFST
9051 || (mips_opts
.micromips
9052 && (*r
== BFD_RELOC_16
9053 || *r
== BFD_RELOC_MIPS_GOT16
9054 || *r
== BFD_RELOC_MIPS_CALL16
9055 || *r
== BFD_RELOC_MIPS_GOT_HI16
9056 || *r
== BFD_RELOC_MIPS_GOT_LO16
9057 || *r
== BFD_RELOC_MIPS_CALL_HI16
9058 || *r
== BFD_RELOC_MIPS_CALL_LO16
9059 || *r
== BFD_RELOC_MIPS_SUB
9060 || *r
== BFD_RELOC_MIPS_GOT_PAGE
9061 || *r
== BFD_RELOC_MIPS_HIGHEST
9062 || *r
== BFD_RELOC_MIPS_GOT_DISP
9063 || *r
== BFD_RELOC_MIPS_TLS_GD
9064 || *r
== BFD_RELOC_MIPS_TLS_LDM
9065 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
9066 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
9067 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
9068 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
9069 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
9073 macro_read_relocs (&args
, r
);
9077 macro_read_relocs (&args
, r
);
9078 gas_assert (ep
!= NULL
9079 && (ep
->X_op
== O_constant
9080 || (ep
->X_op
== O_symbol
9081 && (*r
== BFD_RELOC_MIPS_HIGHEST
9082 || *r
== BFD_RELOC_HI16_S
9083 || *r
== BFD_RELOC_HI16
9084 || *r
== BFD_RELOC_GPREL16
9085 || *r
== BFD_RELOC_MIPS_GOT_HI16
9086 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
9090 gas_assert (ep
!= NULL
);
9093 * This allows macro() to pass an immediate expression for
9094 * creating short branches without creating a symbol.
9096 * We don't allow branch relaxation for these branches, as
9097 * they should only appear in ".set nomacro" anyway.
9099 if (ep
->X_op
== O_constant
)
9101 /* For microMIPS we always use relocations for branches.
9102 So we should not resolve immediate values. */
9103 gas_assert (!mips_opts
.micromips
);
9105 if ((ep
->X_add_number
& 3) != 0)
9106 as_bad (_("branch to misaligned address (0x%lx)"),
9107 (unsigned long) ep
->X_add_number
);
9108 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
9109 as_bad (_("branch address range overflow (0x%lx)"),
9110 (unsigned long) ep
->X_add_number
);
9111 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
9115 *r
= BFD_RELOC_16_PCREL_S2
;
9119 gas_assert (ep
!= NULL
);
9120 *r
= BFD_RELOC_MIPS_JMP
;
9124 operand
= (mips_opts
.micromips
9125 ? decode_micromips_operand (fmt
)
9126 : decode_mips_operand (fmt
));
9130 uval
= va_arg (args
, int);
9131 if (operand
->type
== OP_CLO_CLZ_DEST
)
9132 uval
|= (uval
<< 5);
9133 insn_insert_operand (&insn
, operand
, uval
);
9135 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9141 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9143 append_insn (&insn
, ep
, r
, TRUE
);
9147 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9150 struct mips_opcode
*mo
;
9151 struct mips_cl_insn insn
;
9152 const struct mips_operand
*operand
;
9153 bfd_reloc_code_real_type r
[3]
9154 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9156 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
9158 gas_assert (strcmp (name
, mo
->name
) == 0);
9160 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9163 gas_assert (mo
->name
);
9164 gas_assert (strcmp (name
, mo
->name
) == 0);
9167 create_insn (&insn
, mo
);
9204 gas_assert (ep
!= NULL
);
9206 if (ep
->X_op
!= O_constant
)
9207 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9208 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9210 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9212 *r
= BFD_RELOC_UNUSED
;
9218 operand
= decode_mips16_operand (c
, FALSE
);
9222 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9227 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9229 append_insn (&insn
, ep
, r
, TRUE
);
9233 * Generate a "jalr" instruction with a relocation hint to the called
9234 * function. This occurs in NewABI PIC code.
9237 macro_build_jalr (expressionS
*ep
, int cprestore
)
9239 static const bfd_reloc_code_real_type jalr_relocs
[2]
9240 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9241 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9245 if (MIPS_JALR_HINT_P (ep
))
9250 if (mips_opts
.micromips
)
9252 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9253 ? "jalr" : "jalrs");
9254 if (MIPS_JALR_HINT_P (ep
)
9256 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9257 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9259 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9262 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9263 if (MIPS_JALR_HINT_P (ep
))
9264 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9268 * Generate a "lui" instruction.
9271 macro_build_lui (expressionS
*ep
, int regnum
)
9273 gas_assert (! mips_opts
.mips16
);
9275 if (ep
->X_op
!= O_constant
)
9277 gas_assert (ep
->X_op
== O_symbol
);
9278 /* _gp_disp is a special case, used from s_cpload.
9279 __gnu_local_gp is used if mips_no_shared. */
9280 gas_assert (mips_pic
== NO_PIC
9282 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9283 || (! mips_in_shared
9284 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9285 "__gnu_local_gp") == 0));
9288 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9291 /* Generate a sequence of instructions to do a load or store from a constant
9292 offset off of a base register (breg) into/from a target register (treg),
9293 using AT if necessary. */
9295 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9296 int treg
, int breg
, int dbl
)
9298 gas_assert (ep
->X_op
== O_constant
);
9300 /* Sign-extending 32-bit constants makes their handling easier. */
9302 normalize_constant_expr (ep
);
9304 /* Right now, this routine can only handle signed 32-bit constants. */
9305 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9306 as_warn (_("operand overflow"));
9308 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9310 /* Signed 16-bit offset will fit in the op. Easy! */
9311 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9315 /* 32-bit offset, need multiple instructions and AT, like:
9316 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9317 addu $tempreg,$tempreg,$breg
9318 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9319 to handle the complete offset. */
9320 macro_build_lui (ep
, AT
);
9321 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9322 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9325 as_bad (_("macro used $at after \".set noat\""));
9330 * Generates code to set the $at register to true (one)
9331 * if reg is less than the immediate expression.
9334 set_at (int reg
, int unsignedp
)
9336 if (imm_expr
.X_add_number
>= -0x8000
9337 && imm_expr
.X_add_number
< 0x8000)
9338 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9339 AT
, reg
, BFD_RELOC_LO16
);
9342 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9343 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9347 /* Count the leading zeroes by performing a binary chop. This is a
9348 bulky bit of source, but performance is a LOT better for the
9349 majority of values than a simple loop to count the bits:
9350 for (lcnt = 0; (lcnt < 32); lcnt++)
9351 if ((v) & (1 << (31 - lcnt)))
9353 However it is not code size friendly, and the gain will drop a bit
9354 on certain cached systems.
9356 #define COUNT_TOP_ZEROES(v) \
9357 (((v) & ~0xffff) == 0 \
9358 ? ((v) & ~0xff) == 0 \
9359 ? ((v) & ~0xf) == 0 \
9360 ? ((v) & ~0x3) == 0 \
9361 ? ((v) & ~0x1) == 0 \
9366 : ((v) & ~0x7) == 0 \
9369 : ((v) & ~0x3f) == 0 \
9370 ? ((v) & ~0x1f) == 0 \
9373 : ((v) & ~0x7f) == 0 \
9376 : ((v) & ~0xfff) == 0 \
9377 ? ((v) & ~0x3ff) == 0 \
9378 ? ((v) & ~0x1ff) == 0 \
9381 : ((v) & ~0x7ff) == 0 \
9384 : ((v) & ~0x3fff) == 0 \
9385 ? ((v) & ~0x1fff) == 0 \
9388 : ((v) & ~0x7fff) == 0 \
9391 : ((v) & ~0xffffff) == 0 \
9392 ? ((v) & ~0xfffff) == 0 \
9393 ? ((v) & ~0x3ffff) == 0 \
9394 ? ((v) & ~0x1ffff) == 0 \
9397 : ((v) & ~0x7ffff) == 0 \
9400 : ((v) & ~0x3fffff) == 0 \
9401 ? ((v) & ~0x1fffff) == 0 \
9404 : ((v) & ~0x7fffff) == 0 \
9407 : ((v) & ~0xfffffff) == 0 \
9408 ? ((v) & ~0x3ffffff) == 0 \
9409 ? ((v) & ~0x1ffffff) == 0 \
9412 : ((v) & ~0x7ffffff) == 0 \
9415 : ((v) & ~0x3fffffff) == 0 \
9416 ? ((v) & ~0x1fffffff) == 0 \
9419 : ((v) & ~0x7fffffff) == 0 \
9424 * This routine generates the least number of instructions necessary to load
9425 * an absolute expression value into a register.
9428 load_register (int reg
, expressionS
*ep
, int dbl
)
9431 expressionS hi32
, lo32
;
9433 if (ep
->X_op
!= O_big
)
9435 gas_assert (ep
->X_op
== O_constant
);
9437 /* Sign-extending 32-bit constants makes their handling easier. */
9439 normalize_constant_expr (ep
);
9441 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9443 /* We can handle 16 bit signed values with an addiu to
9444 $zero. No need to ever use daddiu here, since $zero and
9445 the result are always correct in 32 bit mode. */
9446 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9449 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9451 /* We can handle 16 bit unsigned values with an ori to
9453 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9456 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9458 /* 32 bit values require an lui. */
9459 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9460 if ((ep
->X_add_number
& 0xffff) != 0)
9461 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9466 /* The value is larger than 32 bits. */
9468 if (!dbl
|| GPR_SIZE
== 32)
9472 sprintf_vma (value
, ep
->X_add_number
);
9473 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9474 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9478 if (ep
->X_op
!= O_big
)
9481 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9482 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9483 hi32
.X_add_number
&= 0xffffffff;
9485 lo32
.X_add_number
&= 0xffffffff;
9489 gas_assert (ep
->X_add_number
> 2);
9490 if (ep
->X_add_number
== 3)
9491 generic_bignum
[3] = 0;
9492 else if (ep
->X_add_number
> 4)
9493 as_bad (_("number larger than 64 bits"));
9494 lo32
.X_op
= O_constant
;
9495 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9496 hi32
.X_op
= O_constant
;
9497 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9500 if (hi32
.X_add_number
== 0)
9505 unsigned long hi
, lo
;
9507 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9509 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9511 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9514 if (lo32
.X_add_number
& 0x80000000)
9516 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9517 if (lo32
.X_add_number
& 0xffff)
9518 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9523 /* Check for 16bit shifted constant. We know that hi32 is
9524 non-zero, so start the mask on the first bit of the hi32
9529 unsigned long himask
, lomask
;
9533 himask
= 0xffff >> (32 - shift
);
9534 lomask
= (0xffff << shift
) & 0xffffffff;
9538 himask
= 0xffff << (shift
- 32);
9541 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9542 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9546 tmp
.X_op
= O_constant
;
9548 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9549 | (lo32
.X_add_number
>> shift
));
9551 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9552 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9553 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9554 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9559 while (shift
<= (64 - 16));
9561 /* Find the bit number of the lowest one bit, and store the
9562 shifted value in hi/lo. */
9563 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9564 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9568 while ((lo
& 1) == 0)
9573 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9579 while ((hi
& 1) == 0)
9588 /* Optimize if the shifted value is a (power of 2) - 1. */
9589 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9590 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9592 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9597 /* This instruction will set the register to be all
9599 tmp
.X_op
= O_constant
;
9600 tmp
.X_add_number
= (offsetT
) -1;
9601 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9605 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9606 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9608 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9609 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9614 /* Sign extend hi32 before calling load_register, because we can
9615 generally get better code when we load a sign extended value. */
9616 if ((hi32
.X_add_number
& 0x80000000) != 0)
9617 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9618 load_register (reg
, &hi32
, 0);
9621 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9625 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9633 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9635 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9636 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9642 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9646 mid16
.X_add_number
>>= 16;
9647 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9648 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9651 if ((lo32
.X_add_number
& 0xffff) != 0)
9652 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9656 load_delay_nop (void)
9658 if (!gpr_interlocks
)
9659 macro_build (NULL
, "nop", "");
9662 /* Load an address into a register. */
9665 load_address (int reg
, expressionS
*ep
, int *used_at
)
9667 if (ep
->X_op
!= O_constant
9668 && ep
->X_op
!= O_symbol
)
9670 as_bad (_("expression too complex"));
9671 ep
->X_op
= O_constant
;
9674 if (ep
->X_op
== O_constant
)
9676 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9680 if (mips_pic
== NO_PIC
)
9682 /* If this is a reference to a GP relative symbol, we want
9683 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9685 lui $reg,<sym> (BFD_RELOC_HI16_S)
9686 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9687 If we have an addend, we always use the latter form.
9689 With 64bit address space and a usable $at we want
9690 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9691 lui $at,<sym> (BFD_RELOC_HI16_S)
9692 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9693 daddiu $at,<sym> (BFD_RELOC_LO16)
9697 If $at is already in use, we use a path which is suboptimal
9698 on superscalar processors.
9699 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9700 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9702 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9704 daddiu $reg,<sym> (BFD_RELOC_LO16)
9706 For GP relative symbols in 64bit address space we can use
9707 the same sequence as in 32bit address space. */
9708 if (HAVE_64BIT_SYMBOLS
)
9710 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9711 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9713 relax_start (ep
->X_add_symbol
);
9714 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9715 mips_gp_register
, BFD_RELOC_GPREL16
);
9719 if (*used_at
== 0 && mips_opts
.at
)
9721 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9722 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9723 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9724 BFD_RELOC_MIPS_HIGHER
);
9725 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9726 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9727 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9732 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9733 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9734 BFD_RELOC_MIPS_HIGHER
);
9735 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9736 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9737 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9738 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9741 if (mips_relax
.sequence
)
9746 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9747 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9749 relax_start (ep
->X_add_symbol
);
9750 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9751 mips_gp_register
, BFD_RELOC_GPREL16
);
9754 macro_build_lui (ep
, reg
);
9755 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9756 reg
, reg
, BFD_RELOC_LO16
);
9757 if (mips_relax
.sequence
)
9761 else if (!mips_big_got
)
9765 /* If this is a reference to an external symbol, we want
9766 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9768 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9770 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9771 If there is a constant, it must be added in after.
9773 If we have NewABI, we want
9774 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9775 unless we're referencing a global symbol with a non-zero
9776 offset, in which case cst must be added separately. */
9779 if (ep
->X_add_number
)
9781 ex
.X_add_number
= ep
->X_add_number
;
9782 ep
->X_add_number
= 0;
9783 relax_start (ep
->X_add_symbol
);
9784 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9785 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9786 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9787 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9788 ex
.X_op
= O_constant
;
9789 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9790 reg
, reg
, BFD_RELOC_LO16
);
9791 ep
->X_add_number
= ex
.X_add_number
;
9794 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9795 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9796 if (mips_relax
.sequence
)
9801 ex
.X_add_number
= ep
->X_add_number
;
9802 ep
->X_add_number
= 0;
9803 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9804 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9806 relax_start (ep
->X_add_symbol
);
9808 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9812 if (ex
.X_add_number
!= 0)
9814 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9815 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9816 ex
.X_op
= O_constant
;
9817 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9818 reg
, reg
, BFD_RELOC_LO16
);
9822 else if (mips_big_got
)
9826 /* This is the large GOT case. If this is a reference to an
9827 external symbol, we want
9828 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9830 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9832 Otherwise, for a reference to a local symbol in old ABI, we want
9833 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9835 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9836 If there is a constant, it must be added in after.
9838 In the NewABI, for local symbols, with or without offsets, we want:
9839 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9840 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9844 ex
.X_add_number
= ep
->X_add_number
;
9845 ep
->X_add_number
= 0;
9846 relax_start (ep
->X_add_symbol
);
9847 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9848 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9849 reg
, reg
, mips_gp_register
);
9850 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9851 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9852 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9853 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9854 else if (ex
.X_add_number
)
9856 ex
.X_op
= O_constant
;
9857 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9861 ep
->X_add_number
= ex
.X_add_number
;
9863 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9864 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9865 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9866 BFD_RELOC_MIPS_GOT_OFST
);
9871 ex
.X_add_number
= ep
->X_add_number
;
9872 ep
->X_add_number
= 0;
9873 relax_start (ep
->X_add_symbol
);
9874 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9875 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9876 reg
, reg
, mips_gp_register
);
9877 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9878 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9880 if (reg_needs_delay (mips_gp_register
))
9882 /* We need a nop before loading from $gp. This special
9883 check is required because the lui which starts the main
9884 instruction stream does not refer to $gp, and so will not
9885 insert the nop which may be required. */
9886 macro_build (NULL
, "nop", "");
9888 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9889 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9891 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9895 if (ex
.X_add_number
!= 0)
9897 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9898 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9899 ex
.X_op
= O_constant
;
9900 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9908 if (!mips_opts
.at
&& *used_at
== 1)
9909 as_bad (_("macro used $at after \".set noat\""));
9912 /* Move the contents of register SOURCE into register DEST. */
9915 move_register (int dest
, int source
)
9917 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9918 instruction specifically requires a 32-bit one. */
9919 if (mips_opts
.micromips
9920 && !mips_opts
.insn32
9921 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9922 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9924 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9927 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9928 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9929 The two alternatives are:
9931 Global symbol Local symbol
9932 ------------- ------------
9933 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9935 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9937 load_got_offset emits the first instruction and add_got_offset
9938 emits the second for a 16-bit offset or add_got_offset_hilo emits
9939 a sequence to add a 32-bit offset using a scratch register. */
9942 load_got_offset (int dest
, expressionS
*local
)
9947 global
.X_add_number
= 0;
9949 relax_start (local
->X_add_symbol
);
9950 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9951 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9953 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9954 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9959 add_got_offset (int dest
, expressionS
*local
)
9963 global
.X_op
= O_constant
;
9964 global
.X_op_symbol
= NULL
;
9965 global
.X_add_symbol
= NULL
;
9966 global
.X_add_number
= local
->X_add_number
;
9968 relax_start (local
->X_add_symbol
);
9969 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9970 dest
, dest
, BFD_RELOC_LO16
);
9972 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9977 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9980 int hold_mips_optimize
;
9982 global
.X_op
= O_constant
;
9983 global
.X_op_symbol
= NULL
;
9984 global
.X_add_symbol
= NULL
;
9985 global
.X_add_number
= local
->X_add_number
;
9987 relax_start (local
->X_add_symbol
);
9988 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9990 /* Set mips_optimize around the lui instruction to avoid
9991 inserting an unnecessary nop after the lw. */
9992 hold_mips_optimize
= mips_optimize
;
9994 macro_build_lui (&global
, tmp
);
9995 mips_optimize
= hold_mips_optimize
;
9996 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9999 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
10002 /* Emit a sequence of instructions to emulate a branch likely operation.
10003 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10004 is its complementing branch with the original condition negated.
10005 CALL is set if the original branch specified the link operation.
10006 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10008 Code like this is produced in the noreorder mode:
10013 delay slot (executed only if branch taken)
10016 or, if CALL is set:
10021 delay slot (executed only if branch taken)
10024 In the reorder mode the delay slot would be filled with a nop anyway,
10025 so code produced is simply:
10030 This function is used when producing code for the microMIPS ASE that
10031 does not implement branch likely instructions in hardware. */
10034 macro_build_branch_likely (const char *br
, const char *brneg
,
10035 int call
, expressionS
*ep
, const char *fmt
,
10036 unsigned int sreg
, unsigned int treg
)
10038 int noreorder
= mips_opts
.noreorder
;
10041 gas_assert (mips_opts
.micromips
);
10042 start_noreorder ();
10045 micromips_label_expr (&expr1
);
10046 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
10047 macro_build (NULL
, "nop", "");
10048 macro_build (ep
, call
? "bal" : "b", "p");
10050 /* Set to true so that append_insn adds a label. */
10051 emit_branch_likely_macro
= TRUE
;
10055 macro_build (ep
, br
, fmt
, sreg
, treg
);
10056 macro_build (NULL
, "nop", "");
10061 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10062 the condition code tested. EP specifies the branch target. */
10065 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
10067 const int call
= 0;
10092 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
10095 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10096 the register tested. EP specifies the branch target. */
10099 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
10101 const char *brneg
= NULL
;
10111 br
= mips_opts
.micromips
? "bgez" : "bgezl";
10115 gas_assert (mips_opts
.micromips
);
10116 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
10124 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
10131 br
= mips_opts
.micromips
? "blez" : "blezl";
10138 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10142 gas_assert (mips_opts
.micromips
);
10143 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10150 if (mips_opts
.micromips
&& brneg
)
10151 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10153 macro_build (ep
, br
, "s,p", sreg
);
10156 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10157 TREG as the registers tested. EP specifies the branch target. */
10160 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10161 unsigned int sreg
, unsigned int treg
)
10163 const char *brneg
= NULL
;
10164 const int call
= 0;
10175 br
= mips_opts
.micromips
? "beq" : "beql";
10184 br
= mips_opts
.micromips
? "bne" : "bnel";
10190 if (mips_opts
.micromips
&& brneg
)
10191 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10193 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10196 /* Return the high part that should be loaded in order to make the low
10197 part of VALUE accessible using an offset of OFFBITS bits. */
10200 offset_high_part (offsetT value
, unsigned int offbits
)
10207 bias
= 1 << (offbits
- 1);
10208 low_mask
= bias
* 2 - 1;
10209 return (value
+ bias
) & ~low_mask
;
10212 /* Return true if the value stored in offset_expr and offset_reloc
10213 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10214 amount that the caller wants to add without inducing overflow
10215 and ALIGN is the known alignment of the value in bytes. */
10218 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10222 /* Accept any relocation operator if overflow isn't a concern. */
10223 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10226 /* These relocations are guaranteed not to overflow in correct links. */
10227 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10228 || gprel16_reloc_p (*offset_reloc
))
10231 if (offset_expr
.X_op
== O_constant
10232 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10233 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10240 * This routine implements the seemingly endless macro or synthesized
10241 * instructions and addressing modes in the mips assembly language. Many
10242 * of these macros are simple and are similar to each other. These could
10243 * probably be handled by some kind of table or grammar approach instead of
10244 * this verbose method. Others are not simple macros but are more like
10245 * optimizing code generation.
10246 * One interesting optimization is when several store macros appear
10247 * consecutively that would load AT with the upper half of the same address.
10248 * The ensuing load upper instructions are omitted. This implies some kind
10249 * of global optimization. We currently only optimize within a single macro.
10250 * For many of the load and store macros if the address is specified as a
10251 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10252 * first load register 'at' with zero and use it as the base register. The
10253 * mips assembler simply uses register $zero. Just one tiny optimization
10257 macro (struct mips_cl_insn
*ip
, char *str
)
10259 const struct mips_operand_array
*operands
;
10260 unsigned int breg
, i
;
10261 unsigned int tempreg
;
10264 expressionS label_expr
;
10279 bfd_boolean large_offset
;
10281 int hold_mips_optimize
;
10282 unsigned int align
;
10283 unsigned int op
[MAX_OPERANDS
];
10285 gas_assert (! mips_opts
.mips16
);
10287 operands
= insn_operands (ip
);
10288 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10289 if (operands
->operand
[i
])
10290 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10294 mask
= ip
->insn_mo
->mask
;
10296 label_expr
.X_op
= O_constant
;
10297 label_expr
.X_op_symbol
= NULL
;
10298 label_expr
.X_add_symbol
= NULL
;
10299 label_expr
.X_add_number
= 0;
10301 expr1
.X_op
= O_constant
;
10302 expr1
.X_op_symbol
= NULL
;
10303 expr1
.X_add_symbol
= NULL
;
10304 expr1
.X_add_number
= 1;
10311 /* Fall through. */
10319 start_noreorder ();
10321 if (mips_opts
.micromips
)
10322 micromips_label_expr (&label_expr
);
10324 label_expr
.X_add_number
= 8;
10325 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10326 if (op
[0] == op
[1])
10327 macro_build (NULL
, "nop", "");
10329 move_register (op
[0], op
[1]);
10330 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10331 if (mips_opts
.micromips
)
10332 micromips_add_label ();
10349 if (!mips_opts
.micromips
)
10351 if (imm_expr
.X_add_number
>= -0x200
10352 && imm_expr
.X_add_number
< 0x200)
10354 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10355 (int) imm_expr
.X_add_number
);
10364 if (imm_expr
.X_add_number
>= -0x8000
10365 && imm_expr
.X_add_number
< 0x8000)
10367 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10372 load_register (AT
, &imm_expr
, dbl
);
10373 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10392 if (imm_expr
.X_add_number
>= 0
10393 && imm_expr
.X_add_number
< 0x10000)
10395 if (mask
!= M_NOR_I
)
10396 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10399 macro_build (&imm_expr
, "ori", "t,r,i",
10400 op
[0], op
[1], BFD_RELOC_LO16
);
10401 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10407 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10408 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10412 switch (imm_expr
.X_add_number
)
10415 macro_build (NULL
, "nop", "");
10418 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10422 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10423 (int) imm_expr
.X_add_number
);
10426 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10427 (unsigned long) imm_expr
.X_add_number
);
10436 gas_assert (mips_opts
.micromips
);
10437 macro_build_branch_ccl (mask
, &offset_expr
,
10438 EXTRACT_OPERAND (1, BCC
, *ip
));
10445 if (imm_expr
.X_add_number
== 0)
10451 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10453 /* Fall through. */
10456 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10461 /* Fall through. */
10464 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10465 else if (op
[0] == 0)
10466 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10470 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10471 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10472 &offset_expr
, AT
, ZERO
);
10482 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10487 /* Fall through. */
10489 /* Check for > max integer. */
10490 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10493 /* Result is always false. */
10495 macro_build (NULL
, "nop", "");
10497 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10500 ++imm_expr
.X_add_number
;
10501 /* Fall through. */
10504 if (mask
== M_BGEL_I
)
10506 if (imm_expr
.X_add_number
== 0)
10508 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10509 &offset_expr
, op
[0]);
10512 if (imm_expr
.X_add_number
== 1)
10514 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10515 &offset_expr
, op
[0]);
10518 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10521 /* Result is always true. */
10522 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10523 macro_build (&offset_expr
, "b", "p");
10528 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10529 &offset_expr
, AT
, ZERO
);
10534 /* Fall through. */
10538 else if (op
[0] == 0)
10539 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10540 &offset_expr
, ZERO
, op
[1]);
10544 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10545 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10546 &offset_expr
, AT
, ZERO
);
10552 /* Fall through. */
10556 && imm_expr
.X_add_number
== -1))
10558 ++imm_expr
.X_add_number
;
10559 /* Fall through. */
10562 if (mask
== M_BGEUL_I
)
10564 if (imm_expr
.X_add_number
== 0)
10566 else if (imm_expr
.X_add_number
== 1)
10567 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10568 &offset_expr
, op
[0], ZERO
);
10573 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10574 &offset_expr
, AT
, ZERO
);
10580 /* Fall through. */
10583 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10584 else if (op
[0] == 0)
10585 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10589 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10590 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10591 &offset_expr
, AT
, ZERO
);
10597 /* Fall through. */
10600 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10601 &offset_expr
, op
[0], ZERO
);
10602 else if (op
[0] == 0)
10607 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10608 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10609 &offset_expr
, AT
, ZERO
);
10615 /* Fall through. */
10618 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10619 else if (op
[0] == 0)
10620 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10624 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10625 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10626 &offset_expr
, AT
, ZERO
);
10632 /* Fall through. */
10634 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10636 ++imm_expr
.X_add_number
;
10637 /* Fall through. */
10640 if (mask
== M_BLTL_I
)
10642 if (imm_expr
.X_add_number
== 0)
10643 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10644 else if (imm_expr
.X_add_number
== 1)
10645 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10650 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10651 &offset_expr
, AT
, ZERO
);
10657 /* Fall through. */
10660 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10661 &offset_expr
, op
[0], ZERO
);
10662 else if (op
[0] == 0)
10667 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10668 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10669 &offset_expr
, AT
, ZERO
);
10675 /* Fall through. */
10679 && imm_expr
.X_add_number
== -1))
10681 ++imm_expr
.X_add_number
;
10682 /* Fall through. */
10685 if (mask
== M_BLTUL_I
)
10687 if (imm_expr
.X_add_number
== 0)
10689 else if (imm_expr
.X_add_number
== 1)
10690 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10691 &offset_expr
, op
[0], ZERO
);
10696 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10697 &offset_expr
, AT
, ZERO
);
10703 /* Fall through. */
10706 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10707 else if (op
[0] == 0)
10708 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10712 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10713 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10714 &offset_expr
, AT
, ZERO
);
10720 /* Fall through. */
10724 else if (op
[0] == 0)
10725 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10726 &offset_expr
, ZERO
, op
[1]);
10730 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10731 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10732 &offset_expr
, AT
, ZERO
);
10738 /* Fall through. */
10744 /* Fall through. */
10750 as_warn (_("divide by zero"));
10752 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10754 macro_build (NULL
, "break", BRK_FMT
, 7);
10758 start_noreorder ();
10761 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10762 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10766 if (mips_opts
.micromips
)
10767 micromips_label_expr (&label_expr
);
10769 label_expr
.X_add_number
= 8;
10770 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10771 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10772 macro_build (NULL
, "break", BRK_FMT
, 7);
10773 if (mips_opts
.micromips
)
10774 micromips_add_label ();
10776 expr1
.X_add_number
= -1;
10778 load_register (AT
, &expr1
, dbl
);
10779 if (mips_opts
.micromips
)
10780 micromips_label_expr (&label_expr
);
10782 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10783 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10786 expr1
.X_add_number
= 1;
10787 load_register (AT
, &expr1
, dbl
);
10788 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10792 expr1
.X_add_number
= 0x80000000;
10793 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10797 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10798 /* We want to close the noreorder block as soon as possible, so
10799 that later insns are available for delay slot filling. */
10804 if (mips_opts
.micromips
)
10805 micromips_label_expr (&label_expr
);
10807 label_expr
.X_add_number
= 8;
10808 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10809 macro_build (NULL
, "nop", "");
10811 /* We want to close the noreorder block as soon as possible, so
10812 that later insns are available for delay slot filling. */
10815 macro_build (NULL
, "break", BRK_FMT
, 6);
10817 if (mips_opts
.micromips
)
10818 micromips_add_label ();
10819 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10858 if (imm_expr
.X_add_number
== 0)
10860 as_warn (_("divide by zero"));
10862 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10864 macro_build (NULL
, "break", BRK_FMT
, 7);
10867 if (imm_expr
.X_add_number
== 1)
10869 if (strcmp (s2
, "mflo") == 0)
10870 move_register (op
[0], op
[1]);
10872 move_register (op
[0], ZERO
);
10875 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10877 if (strcmp (s2
, "mflo") == 0)
10878 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10880 move_register (op
[0], ZERO
);
10885 load_register (AT
, &imm_expr
, dbl
);
10886 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10887 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10906 start_noreorder ();
10909 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10910 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10911 /* We want to close the noreorder block as soon as possible, so
10912 that later insns are available for delay slot filling. */
10917 if (mips_opts
.micromips
)
10918 micromips_label_expr (&label_expr
);
10920 label_expr
.X_add_number
= 8;
10921 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10922 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10924 /* We want to close the noreorder block as soon as possible, so
10925 that later insns are available for delay slot filling. */
10927 macro_build (NULL
, "break", BRK_FMT
, 7);
10928 if (mips_opts
.micromips
)
10929 micromips_add_label ();
10931 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10936 /* Fall through. */
10942 /* Fall through. */
10945 /* Load the address of a symbol into a register. If breg is not
10946 zero, we then add a base register to it. */
10949 if (dbl
&& GPR_SIZE
== 32)
10950 as_warn (_("dla used to load 32-bit register; recommend using la "
10953 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10954 as_warn (_("la used to load 64-bit address; recommend using dla "
10957 if (small_offset_p (0, align
, 16))
10959 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10960 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10964 if (mips_opts
.at
&& (op
[0] == breg
))
10972 if (offset_expr
.X_op
!= O_symbol
10973 && offset_expr
.X_op
!= O_constant
)
10975 as_bad (_("expression too complex"));
10976 offset_expr
.X_op
= O_constant
;
10979 if (offset_expr
.X_op
== O_constant
)
10980 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10981 else if (mips_pic
== NO_PIC
)
10983 /* If this is a reference to a GP relative symbol, we want
10984 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10986 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10987 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10988 If we have a constant, we need two instructions anyhow,
10989 so we may as well always use the latter form.
10991 With 64bit address space and a usable $at we want
10992 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10993 lui $at,<sym> (BFD_RELOC_HI16_S)
10994 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10995 daddiu $at,<sym> (BFD_RELOC_LO16)
10997 daddu $tempreg,$tempreg,$at
10999 If $at is already in use, we use a path which is suboptimal
11000 on superscalar processors.
11001 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11002 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11004 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11006 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11008 For GP relative symbols in 64bit address space we can use
11009 the same sequence as in 32bit address space. */
11010 if (HAVE_64BIT_SYMBOLS
)
11012 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11013 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11015 relax_start (offset_expr
.X_add_symbol
);
11016 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11017 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11021 if (used_at
== 0 && mips_opts
.at
)
11023 macro_build (&offset_expr
, "lui", LUI_FMT
,
11024 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11025 macro_build (&offset_expr
, "lui", LUI_FMT
,
11026 AT
, BFD_RELOC_HI16_S
);
11027 macro_build (&offset_expr
, "daddiu", "t,r,j",
11028 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11029 macro_build (&offset_expr
, "daddiu", "t,r,j",
11030 AT
, AT
, BFD_RELOC_LO16
);
11031 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11032 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11037 macro_build (&offset_expr
, "lui", LUI_FMT
,
11038 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11039 macro_build (&offset_expr
, "daddiu", "t,r,j",
11040 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11041 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11042 macro_build (&offset_expr
, "daddiu", "t,r,j",
11043 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
11044 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11045 macro_build (&offset_expr
, "daddiu", "t,r,j",
11046 tempreg
, tempreg
, BFD_RELOC_LO16
);
11049 if (mips_relax
.sequence
)
11054 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11055 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11057 relax_start (offset_expr
.X_add_symbol
);
11058 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11059 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11062 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11063 as_bad (_("offset too large"));
11064 macro_build_lui (&offset_expr
, tempreg
);
11065 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11066 tempreg
, tempreg
, BFD_RELOC_LO16
);
11067 if (mips_relax
.sequence
)
11071 else if (!mips_big_got
&& !HAVE_NEWABI
)
11073 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11075 /* If this is a reference to an external symbol, and there
11076 is no constant, we want
11077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11078 or for lca or if tempreg is PIC_CALL_REG
11079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11080 For a local symbol, we want
11081 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11083 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11085 If we have a small constant, and this is a reference to
11086 an external symbol, we want
11087 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11089 addiu $tempreg,$tempreg,<constant>
11090 For a local symbol, we want the same instruction
11091 sequence, but we output a BFD_RELOC_LO16 reloc on the
11094 If we have a large constant, and this is a reference to
11095 an external symbol, we want
11096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11097 lui $at,<hiconstant>
11098 addiu $at,$at,<loconstant>
11099 addu $tempreg,$tempreg,$at
11100 For a local symbol, we want the same instruction
11101 sequence, but we output a BFD_RELOC_LO16 reloc on the
11105 if (offset_expr
.X_add_number
== 0)
11107 if (mips_pic
== SVR4_PIC
11109 && (call
|| tempreg
== PIC_CALL_REG
))
11110 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
11112 relax_start (offset_expr
.X_add_symbol
);
11113 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11114 lw_reloc_type
, mips_gp_register
);
11117 /* We're going to put in an addu instruction using
11118 tempreg, so we may as well insert the nop right
11123 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11124 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11126 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11127 tempreg
, tempreg
, BFD_RELOC_LO16
);
11129 /* FIXME: If breg == 0, and the next instruction uses
11130 $tempreg, then if this variant case is used an extra
11131 nop will be generated. */
11133 else if (offset_expr
.X_add_number
>= -0x8000
11134 && offset_expr
.X_add_number
< 0x8000)
11136 load_got_offset (tempreg
, &offset_expr
);
11138 add_got_offset (tempreg
, &offset_expr
);
11142 expr1
.X_add_number
= offset_expr
.X_add_number
;
11143 offset_expr
.X_add_number
=
11144 SEXT_16BIT (offset_expr
.X_add_number
);
11145 load_got_offset (tempreg
, &offset_expr
);
11146 offset_expr
.X_add_number
= expr1
.X_add_number
;
11147 /* If we are going to add in a base register, and the
11148 target register and the base register are the same,
11149 then we are using AT as a temporary register. Since
11150 we want to load the constant into AT, we add our
11151 current AT (from the global offset table) and the
11152 register into the register now, and pretend we were
11153 not using a base register. */
11157 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11162 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11166 else if (!mips_big_got
&& HAVE_NEWABI
)
11168 int add_breg_early
= 0;
11170 /* If this is a reference to an external, and there is no
11171 constant, or local symbol (*), with or without a
11173 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11174 or for lca or if tempreg is PIC_CALL_REG
11175 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11177 If we have a small constant, and this is a reference to
11178 an external symbol, we want
11179 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11180 addiu $tempreg,$tempreg,<constant>
11182 If we have a large constant, and this is a reference to
11183 an external symbol, we want
11184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11185 lui $at,<hiconstant>
11186 addiu $at,$at,<loconstant>
11187 addu $tempreg,$tempreg,$at
11189 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11190 local symbols, even though it introduces an additional
11193 if (offset_expr
.X_add_number
)
11195 expr1
.X_add_number
= offset_expr
.X_add_number
;
11196 offset_expr
.X_add_number
= 0;
11198 relax_start (offset_expr
.X_add_symbol
);
11199 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11200 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11202 if (expr1
.X_add_number
>= -0x8000
11203 && expr1
.X_add_number
< 0x8000)
11205 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11206 tempreg
, tempreg
, BFD_RELOC_LO16
);
11208 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11212 /* If we are going to add in a base register, and the
11213 target register and the base register are the same,
11214 then we are using AT as a temporary register. Since
11215 we want to load the constant into AT, we add our
11216 current AT (from the global offset table) and the
11217 register into the register now, and pretend we were
11218 not using a base register. */
11223 gas_assert (tempreg
== AT
);
11224 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11227 add_breg_early
= 1;
11230 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11231 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11237 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11240 offset_expr
.X_add_number
= expr1
.X_add_number
;
11242 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11243 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11244 if (add_breg_early
)
11246 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11247 op
[0], tempreg
, breg
);
11253 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11255 relax_start (offset_expr
.X_add_symbol
);
11256 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11257 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11259 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11260 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11265 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11266 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11269 else if (mips_big_got
&& !HAVE_NEWABI
)
11272 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11273 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11274 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11276 /* This is the large GOT case. If this is a reference to an
11277 external symbol, and there is no constant, we want
11278 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11279 addu $tempreg,$tempreg,$gp
11280 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11281 or for lca or if tempreg is PIC_CALL_REG
11282 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11283 addu $tempreg,$tempreg,$gp
11284 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11285 For a local symbol, we want
11286 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11288 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11290 If we have a small constant, and this is a reference to
11291 an external symbol, we want
11292 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11293 addu $tempreg,$tempreg,$gp
11294 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11296 addiu $tempreg,$tempreg,<constant>
11297 For a local symbol, we want
11298 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11300 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11302 If we have a large constant, and this is a reference to
11303 an external symbol, we want
11304 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11305 addu $tempreg,$tempreg,$gp
11306 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11307 lui $at,<hiconstant>
11308 addiu $at,$at,<loconstant>
11309 addu $tempreg,$tempreg,$at
11310 For a local symbol, we want
11311 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11312 lui $at,<hiconstant>
11313 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11314 addu $tempreg,$tempreg,$at
11317 expr1
.X_add_number
= offset_expr
.X_add_number
;
11318 offset_expr
.X_add_number
= 0;
11319 relax_start (offset_expr
.X_add_symbol
);
11320 gpdelay
= reg_needs_delay (mips_gp_register
);
11321 if (expr1
.X_add_number
== 0 && breg
== 0
11322 && (call
|| tempreg
== PIC_CALL_REG
))
11324 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11325 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11327 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11328 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11329 tempreg
, tempreg
, mips_gp_register
);
11330 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11331 tempreg
, lw_reloc_type
, tempreg
);
11332 if (expr1
.X_add_number
== 0)
11336 /* We're going to put in an addu instruction using
11337 tempreg, so we may as well insert the nop right
11342 else if (expr1
.X_add_number
>= -0x8000
11343 && expr1
.X_add_number
< 0x8000)
11346 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11347 tempreg
, tempreg
, BFD_RELOC_LO16
);
11353 /* If we are going to add in a base register, and the
11354 target register and the base register are the same,
11355 then we are using AT as a temporary register. Since
11356 we want to load the constant into AT, we add our
11357 current AT (from the global offset table) and the
11358 register into the register now, and pretend we were
11359 not using a base register. */
11364 gas_assert (tempreg
== AT
);
11366 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11371 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11372 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11376 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11381 /* This is needed because this instruction uses $gp, but
11382 the first instruction on the main stream does not. */
11383 macro_build (NULL
, "nop", "");
11386 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11387 local_reloc_type
, mips_gp_register
);
11388 if (expr1
.X_add_number
>= -0x8000
11389 && expr1
.X_add_number
< 0x8000)
11392 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11393 tempreg
, tempreg
, BFD_RELOC_LO16
);
11394 /* FIXME: If add_number is 0, and there was no base
11395 register, the external symbol case ended with a load,
11396 so if the symbol turns out to not be external, and
11397 the next instruction uses tempreg, an unnecessary nop
11398 will be inserted. */
11404 /* We must add in the base register now, as in the
11405 external symbol case. */
11406 gas_assert (tempreg
== AT
);
11408 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11411 /* We set breg to 0 because we have arranged to add
11412 it in in both cases. */
11416 macro_build_lui (&expr1
, AT
);
11417 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11418 AT
, AT
, BFD_RELOC_LO16
);
11419 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11420 tempreg
, tempreg
, AT
);
11425 else if (mips_big_got
&& HAVE_NEWABI
)
11427 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11428 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11429 int add_breg_early
= 0;
11431 /* This is the large GOT case. If this is a reference to an
11432 external symbol, and there is no constant, we want
11433 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11434 add $tempreg,$tempreg,$gp
11435 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11436 or for lca or if tempreg is PIC_CALL_REG
11437 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11438 add $tempreg,$tempreg,$gp
11439 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11441 If we have a small constant, and this is a reference to
11442 an external symbol, we want
11443 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11444 add $tempreg,$tempreg,$gp
11445 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11446 addi $tempreg,$tempreg,<constant>
11448 If we have a large constant, and this is a reference to
11449 an external symbol, we want
11450 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11451 addu $tempreg,$tempreg,$gp
11452 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11453 lui $at,<hiconstant>
11454 addi $at,$at,<loconstant>
11455 add $tempreg,$tempreg,$at
11457 If we have NewABI, and we know it's a local symbol, we want
11458 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11459 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11460 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11462 relax_start (offset_expr
.X_add_symbol
);
11464 expr1
.X_add_number
= offset_expr
.X_add_number
;
11465 offset_expr
.X_add_number
= 0;
11467 if (expr1
.X_add_number
== 0 && breg
== 0
11468 && (call
|| tempreg
== PIC_CALL_REG
))
11470 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11471 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11473 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11474 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11475 tempreg
, tempreg
, mips_gp_register
);
11476 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11477 tempreg
, lw_reloc_type
, tempreg
);
11479 if (expr1
.X_add_number
== 0)
11481 else if (expr1
.X_add_number
>= -0x8000
11482 && expr1
.X_add_number
< 0x8000)
11484 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11485 tempreg
, tempreg
, BFD_RELOC_LO16
);
11487 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11491 /* If we are going to add in a base register, and the
11492 target register and the base register are the same,
11493 then we are using AT as a temporary register. Since
11494 we want to load the constant into AT, we add our
11495 current AT (from the global offset table) and the
11496 register into the register now, and pretend we were
11497 not using a base register. */
11502 gas_assert (tempreg
== AT
);
11503 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11506 add_breg_early
= 1;
11509 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11510 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11515 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11518 offset_expr
.X_add_number
= expr1
.X_add_number
;
11519 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11520 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11521 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11522 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11523 if (add_breg_early
)
11525 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11526 op
[0], tempreg
, breg
);
11536 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11540 gas_assert (!mips_opts
.micromips
);
11541 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11545 gas_assert (!mips_opts
.micromips
);
11546 macro_build (NULL
, "c2", "C", 0x02);
11550 gas_assert (!mips_opts
.micromips
);
11551 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11555 gas_assert (!mips_opts
.micromips
);
11556 macro_build (NULL
, "c2", "C", 3);
11560 gas_assert (!mips_opts
.micromips
);
11561 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11565 /* The j instruction may not be used in PIC code, since it
11566 requires an absolute address. We convert it to a b
11568 if (mips_pic
== NO_PIC
)
11569 macro_build (&offset_expr
, "j", "a");
11571 macro_build (&offset_expr
, "b", "p");
11574 /* The jal instructions must be handled as macros because when
11575 generating PIC code they expand to multi-instruction
11576 sequences. Normally they are simple instructions. */
11580 /* Fall through. */
11582 gas_assert (mips_opts
.micromips
);
11583 if (mips_opts
.insn32
)
11585 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11593 /* Fall through. */
11596 if (mips_pic
== NO_PIC
)
11598 s
= jals
? "jalrs" : "jalr";
11599 if (mips_opts
.micromips
11600 && !mips_opts
.insn32
11602 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11603 macro_build (NULL
, s
, "mj", op
[1]);
11605 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11609 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11610 && mips_cprestore_offset
>= 0);
11612 if (op
[1] != PIC_CALL_REG
)
11613 as_warn (_("MIPS PIC call to register other than $25"));
11615 s
= ((mips_opts
.micromips
11616 && !mips_opts
.insn32
11617 && (!mips_opts
.noreorder
|| cprestore
))
11618 ? "jalrs" : "jalr");
11619 if (mips_opts
.micromips
11620 && !mips_opts
.insn32
11622 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11623 macro_build (NULL
, s
, "mj", op
[1]);
11625 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11626 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11628 if (mips_cprestore_offset
< 0)
11629 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11632 if (!mips_frame_reg_valid
)
11634 as_warn (_("no .frame pseudo-op used in PIC code"));
11635 /* Quiet this warning. */
11636 mips_frame_reg_valid
= 1;
11638 if (!mips_cprestore_valid
)
11640 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11641 /* Quiet this warning. */
11642 mips_cprestore_valid
= 1;
11644 if (mips_opts
.noreorder
)
11645 macro_build (NULL
, "nop", "");
11646 expr1
.X_add_number
= mips_cprestore_offset
;
11647 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11650 HAVE_64BIT_ADDRESSES
);
11658 gas_assert (mips_opts
.micromips
);
11659 if (mips_opts
.insn32
)
11661 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11665 /* Fall through. */
11667 if (mips_pic
== NO_PIC
)
11668 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11669 else if (mips_pic
== SVR4_PIC
)
11671 /* If this is a reference to an external symbol, and we are
11672 using a small GOT, we want
11673 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11677 lw $gp,cprestore($sp)
11678 The cprestore value is set using the .cprestore
11679 pseudo-op. If we are using a big GOT, we want
11680 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11682 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11686 lw $gp,cprestore($sp)
11687 If the symbol is not external, we want
11688 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11690 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11693 lw $gp,cprestore($sp)
11695 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11696 sequences above, minus nops, unless the symbol is local,
11697 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11703 relax_start (offset_expr
.X_add_symbol
);
11704 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11705 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11708 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11709 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11715 relax_start (offset_expr
.X_add_symbol
);
11716 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11717 BFD_RELOC_MIPS_CALL_HI16
);
11718 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11719 PIC_CALL_REG
, mips_gp_register
);
11720 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11721 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11724 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11725 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11727 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11728 PIC_CALL_REG
, PIC_CALL_REG
,
11729 BFD_RELOC_MIPS_GOT_OFST
);
11733 macro_build_jalr (&offset_expr
, 0);
11737 relax_start (offset_expr
.X_add_symbol
);
11740 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11741 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11750 gpdelay
= reg_needs_delay (mips_gp_register
);
11751 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11752 BFD_RELOC_MIPS_CALL_HI16
);
11753 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11754 PIC_CALL_REG
, mips_gp_register
);
11755 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11756 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11761 macro_build (NULL
, "nop", "");
11763 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11764 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11767 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11768 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11770 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11772 if (mips_cprestore_offset
< 0)
11773 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11776 if (!mips_frame_reg_valid
)
11778 as_warn (_("no .frame pseudo-op used in PIC code"));
11779 /* Quiet this warning. */
11780 mips_frame_reg_valid
= 1;
11782 if (!mips_cprestore_valid
)
11784 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11785 /* Quiet this warning. */
11786 mips_cprestore_valid
= 1;
11788 if (mips_opts
.noreorder
)
11789 macro_build (NULL
, "nop", "");
11790 expr1
.X_add_number
= mips_cprestore_offset
;
11791 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11794 HAVE_64BIT_ADDRESSES
);
11798 else if (mips_pic
== VXWORKS_PIC
)
11799 as_bad (_("non-PIC jump used in PIC library"));
11906 gas_assert (!mips_opts
.micromips
);
11909 /* Itbl support may require additional care here. */
11915 /* Itbl support may require additional care here. */
11921 offbits
= (mips_opts
.micromips
? 12
11922 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11924 /* Itbl support may require additional care here. */
11928 gas_assert (!mips_opts
.micromips
);
11931 /* Itbl support may require additional care here. */
11937 offbits
= (mips_opts
.micromips
? 12 : 16);
11942 offbits
= (mips_opts
.micromips
? 12 : 16);
11947 /* Itbl support may require additional care here. */
11953 offbits
= (mips_opts
.micromips
? 12
11954 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11956 /* Itbl support may require additional care here. */
11962 /* Itbl support may require additional care here. */
11968 /* Itbl support may require additional care here. */
11974 offbits
= (mips_opts
.micromips
? 12 : 16);
11979 offbits
= (mips_opts
.micromips
? 12 : 16);
11984 offbits
= (mips_opts
.micromips
? 12
11985 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11991 offbits
= (mips_opts
.micromips
? 12
11992 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11998 offbits
= (mips_opts
.micromips
? 12 : 16);
12001 gas_assert (mips_opts
.micromips
);
12008 gas_assert (mips_opts
.micromips
);
12015 gas_assert (mips_opts
.micromips
);
12021 gas_assert (mips_opts
.micromips
);
12028 /* We don't want to use $0 as tempreg. */
12029 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
12032 tempreg
= op
[0] + lp
;
12048 gas_assert (!mips_opts
.micromips
);
12051 /* Itbl support may require additional care here. */
12057 /* Itbl support may require additional care here. */
12063 offbits
= (mips_opts
.micromips
? 12
12064 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12066 /* Itbl support may require additional care here. */
12070 gas_assert (!mips_opts
.micromips
);
12073 /* Itbl support may require additional care here. */
12079 offbits
= (mips_opts
.micromips
? 12 : 16);
12084 offbits
= (mips_opts
.micromips
? 12 : 16);
12089 offbits
= (mips_opts
.micromips
? 12
12090 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12096 offbits
= (mips_opts
.micromips
? 12
12097 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12102 fmt
= (mips_opts
.micromips
? "k,~(b)"
12103 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12105 offbits
= (mips_opts
.micromips
? 12
12106 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12116 fmt
= (mips_opts
.micromips
? "k,~(b)"
12117 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12119 offbits
= (mips_opts
.micromips
? 12
12120 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12132 /* Itbl support may require additional care here. */
12137 offbits
= (mips_opts
.micromips
? 12
12138 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12140 /* Itbl support may require additional care here. */
12146 /* Itbl support may require additional care here. */
12150 gas_assert (!mips_opts
.micromips
);
12153 /* Itbl support may require additional care here. */
12159 offbits
= (mips_opts
.micromips
? 12 : 16);
12164 offbits
= (mips_opts
.micromips
? 12 : 16);
12167 gas_assert (mips_opts
.micromips
);
12173 gas_assert (mips_opts
.micromips
);
12179 gas_assert (mips_opts
.micromips
);
12185 gas_assert (mips_opts
.micromips
);
12194 if (small_offset_p (0, align
, 16))
12196 /* The first case exists for M_LD_AB and M_SD_AB, which are
12197 macros for o32 but which should act like normal instructions
12200 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12201 offset_reloc
[1], offset_reloc
[2], breg
);
12202 else if (small_offset_p (0, align
, offbits
))
12205 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12207 macro_build (NULL
, s
, fmt
, op
[0],
12208 (int) offset_expr
.X_add_number
, breg
);
12214 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12215 tempreg
, breg
, -1, offset_reloc
[0],
12216 offset_reloc
[1], offset_reloc
[2]);
12218 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12220 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12228 if (offset_expr
.X_op
!= O_constant
12229 && offset_expr
.X_op
!= O_symbol
)
12231 as_bad (_("expression too complex"));
12232 offset_expr
.X_op
= O_constant
;
12235 if (HAVE_32BIT_ADDRESSES
12236 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12240 sprintf_vma (value
, offset_expr
.X_add_number
);
12241 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12244 /* A constant expression in PIC code can be handled just as it
12245 is in non PIC code. */
12246 if (offset_expr
.X_op
== O_constant
)
12248 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12249 offbits
== 0 ? 16 : offbits
);
12250 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12252 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12254 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12255 tempreg
, tempreg
, breg
);
12258 if (offset_expr
.X_add_number
!= 0)
12259 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12260 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12261 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12263 else if (offbits
== 16)
12264 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12266 macro_build (NULL
, s
, fmt
, op
[0],
12267 (int) offset_expr
.X_add_number
, tempreg
);
12269 else if (offbits
!= 16)
12271 /* The offset field is too narrow to be used for a low-part
12272 relocation, so load the whole address into the auxiliary
12274 load_address (tempreg
, &offset_expr
, &used_at
);
12276 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12277 tempreg
, tempreg
, breg
);
12279 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12281 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12283 else if (mips_pic
== NO_PIC
)
12285 /* If this is a reference to a GP relative symbol, and there
12286 is no base register, we want
12287 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12288 Otherwise, if there is no base register, we want
12289 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12290 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12291 If we have a constant, we need two instructions anyhow,
12292 so we always use the latter form.
12294 If we have a base register, and this is a reference to a
12295 GP relative symbol, we want
12296 addu $tempreg,$breg,$gp
12297 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12299 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12300 addu $tempreg,$tempreg,$breg
12301 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12302 With a constant we always use the latter case.
12304 With 64bit address space and no base register and $at usable,
12306 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12307 lui $at,<sym> (BFD_RELOC_HI16_S)
12308 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12311 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12312 If we have a base register, we want
12313 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12314 lui $at,<sym> (BFD_RELOC_HI16_S)
12315 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12319 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12321 Without $at we can't generate the optimal path for superscalar
12322 processors here since this would require two temporary registers.
12323 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12324 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12326 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12328 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12329 If we have a base register, we want
12330 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12331 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12333 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12335 daddu $tempreg,$tempreg,$breg
12336 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12338 For GP relative symbols in 64bit address space we can use
12339 the same sequence as in 32bit address space. */
12340 if (HAVE_64BIT_SYMBOLS
)
12342 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12343 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12345 relax_start (offset_expr
.X_add_symbol
);
12348 macro_build (&offset_expr
, s
, fmt
, op
[0],
12349 BFD_RELOC_GPREL16
, mips_gp_register
);
12353 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12354 tempreg
, breg
, mips_gp_register
);
12355 macro_build (&offset_expr
, s
, fmt
, op
[0],
12356 BFD_RELOC_GPREL16
, tempreg
);
12361 if (used_at
== 0 && mips_opts
.at
)
12363 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12364 BFD_RELOC_MIPS_HIGHEST
);
12365 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12367 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12368 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12370 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12371 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12372 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12373 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12379 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12380 BFD_RELOC_MIPS_HIGHEST
);
12381 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12382 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12383 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12384 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12385 tempreg
, BFD_RELOC_HI16_S
);
12386 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12388 macro_build (NULL
, "daddu", "d,v,t",
12389 tempreg
, tempreg
, breg
);
12390 macro_build (&offset_expr
, s
, fmt
, op
[0],
12391 BFD_RELOC_LO16
, tempreg
);
12394 if (mips_relax
.sequence
)
12401 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12402 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12404 relax_start (offset_expr
.X_add_symbol
);
12405 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12409 macro_build_lui (&offset_expr
, tempreg
);
12410 macro_build (&offset_expr
, s
, fmt
, op
[0],
12411 BFD_RELOC_LO16
, tempreg
);
12412 if (mips_relax
.sequence
)
12417 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12418 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12420 relax_start (offset_expr
.X_add_symbol
);
12421 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12422 tempreg
, breg
, mips_gp_register
);
12423 macro_build (&offset_expr
, s
, fmt
, op
[0],
12424 BFD_RELOC_GPREL16
, tempreg
);
12427 macro_build_lui (&offset_expr
, tempreg
);
12428 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12429 tempreg
, tempreg
, breg
);
12430 macro_build (&offset_expr
, s
, fmt
, op
[0],
12431 BFD_RELOC_LO16
, tempreg
);
12432 if (mips_relax
.sequence
)
12436 else if (!mips_big_got
)
12438 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12440 /* If this is a reference to an external symbol, we want
12441 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12443 <op> op[0],0($tempreg)
12445 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12447 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12448 <op> op[0],0($tempreg)
12450 For NewABI, we want
12451 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12452 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12454 If there is a base register, we add it to $tempreg before
12455 the <op>. If there is a constant, we stick it in the
12456 <op> instruction. We don't handle constants larger than
12457 16 bits, because we have no way to load the upper 16 bits
12458 (actually, we could handle them for the subset of cases
12459 in which we are not using $at). */
12460 gas_assert (offset_expr
.X_op
== O_symbol
);
12463 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12464 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12466 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12467 tempreg
, tempreg
, breg
);
12468 macro_build (&offset_expr
, s
, fmt
, op
[0],
12469 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12472 expr1
.X_add_number
= offset_expr
.X_add_number
;
12473 offset_expr
.X_add_number
= 0;
12474 if (expr1
.X_add_number
< -0x8000
12475 || expr1
.X_add_number
>= 0x8000)
12476 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12477 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12478 lw_reloc_type
, mips_gp_register
);
12480 relax_start (offset_expr
.X_add_symbol
);
12482 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12483 tempreg
, BFD_RELOC_LO16
);
12486 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12487 tempreg
, tempreg
, breg
);
12488 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12490 else if (mips_big_got
&& !HAVE_NEWABI
)
12494 /* If this is a reference to an external symbol, we want
12495 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12496 addu $tempreg,$tempreg,$gp
12497 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12498 <op> op[0],0($tempreg)
12500 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12502 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12503 <op> op[0],0($tempreg)
12504 If there is a base register, we add it to $tempreg before
12505 the <op>. If there is a constant, we stick it in the
12506 <op> instruction. We don't handle constants larger than
12507 16 bits, because we have no way to load the upper 16 bits
12508 (actually, we could handle them for the subset of cases
12509 in which we are not using $at). */
12510 gas_assert (offset_expr
.X_op
== O_symbol
);
12511 expr1
.X_add_number
= offset_expr
.X_add_number
;
12512 offset_expr
.X_add_number
= 0;
12513 if (expr1
.X_add_number
< -0x8000
12514 || expr1
.X_add_number
>= 0x8000)
12515 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12516 gpdelay
= reg_needs_delay (mips_gp_register
);
12517 relax_start (offset_expr
.X_add_symbol
);
12518 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12519 BFD_RELOC_MIPS_GOT_HI16
);
12520 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12522 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12523 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12526 macro_build (NULL
, "nop", "");
12527 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12528 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12530 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12531 tempreg
, BFD_RELOC_LO16
);
12535 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12536 tempreg
, tempreg
, breg
);
12537 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12539 else if (mips_big_got
&& HAVE_NEWABI
)
12541 /* If this is a reference to an external symbol, we want
12542 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12543 add $tempreg,$tempreg,$gp
12544 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12545 <op> op[0],<ofst>($tempreg)
12546 Otherwise, for local symbols, we want:
12547 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12548 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12549 gas_assert (offset_expr
.X_op
== O_symbol
);
12550 expr1
.X_add_number
= offset_expr
.X_add_number
;
12551 offset_expr
.X_add_number
= 0;
12552 if (expr1
.X_add_number
< -0x8000
12553 || expr1
.X_add_number
>= 0x8000)
12554 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12555 relax_start (offset_expr
.X_add_symbol
);
12556 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12557 BFD_RELOC_MIPS_GOT_HI16
);
12558 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12560 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12561 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12563 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12564 tempreg
, tempreg
, breg
);
12565 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12568 offset_expr
.X_add_number
= expr1
.X_add_number
;
12569 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12570 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12572 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12573 tempreg
, tempreg
, breg
);
12574 macro_build (&offset_expr
, s
, fmt
, op
[0],
12575 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12584 gas_assert (mips_opts
.micromips
);
12585 gas_assert (mips_opts
.insn32
);
12586 start_noreorder ();
12587 macro_build (NULL
, "jr", "s", RA
);
12588 expr1
.X_add_number
= op
[0] << 2;
12589 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12594 gas_assert (mips_opts
.micromips
);
12595 gas_assert (mips_opts
.insn32
);
12596 macro_build (NULL
, "jr", "s", op
[0]);
12597 if (mips_opts
.noreorder
)
12598 macro_build (NULL
, "nop", "");
12603 load_register (op
[0], &imm_expr
, 0);
12607 load_register (op
[0], &imm_expr
, 1);
12611 if (imm_expr
.X_op
== O_constant
)
12614 load_register (AT
, &imm_expr
, 0);
12615 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12620 gas_assert (imm_expr
.X_op
== O_absent
12621 && offset_expr
.X_op
== O_symbol
12622 && strcmp (segment_name (S_GET_SEGMENT
12623 (offset_expr
.X_add_symbol
)),
12625 && offset_expr
.X_add_number
== 0);
12626 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12627 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12632 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12633 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12634 order 32 bits of the value and the low order 32 bits are either
12635 zero or in OFFSET_EXPR. */
12636 if (imm_expr
.X_op
== O_constant
)
12638 if (GPR_SIZE
== 64)
12639 load_register (op
[0], &imm_expr
, 1);
12644 if (target_big_endian
)
12656 load_register (hreg
, &imm_expr
, 0);
12659 if (offset_expr
.X_op
== O_absent
)
12660 move_register (lreg
, 0);
12663 gas_assert (offset_expr
.X_op
== O_constant
);
12664 load_register (lreg
, &offset_expr
, 0);
12670 gas_assert (imm_expr
.X_op
== O_absent
);
12672 /* We know that sym is in the .rdata section. First we get the
12673 upper 16 bits of the address. */
12674 if (mips_pic
== NO_PIC
)
12676 macro_build_lui (&offset_expr
, AT
);
12681 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12682 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12686 /* Now we load the register(s). */
12687 if (GPR_SIZE
== 64)
12690 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12691 BFD_RELOC_LO16
, AT
);
12696 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12697 BFD_RELOC_LO16
, AT
);
12700 /* FIXME: How in the world do we deal with the possible
12702 offset_expr
.X_add_number
+= 4;
12703 macro_build (&offset_expr
, "lw", "t,o(b)",
12704 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12710 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12711 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12712 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12713 the value and the low order 32 bits are either zero or in
12715 if (imm_expr
.X_op
== O_constant
)
12718 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12719 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12720 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12723 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12724 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12725 else if (FPR_SIZE
!= 32)
12726 as_bad (_("Unable to generate `%s' compliant code "
12728 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12730 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12731 if (offset_expr
.X_op
== O_absent
)
12732 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12735 gas_assert (offset_expr
.X_op
== O_constant
);
12736 load_register (AT
, &offset_expr
, 0);
12737 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12743 gas_assert (imm_expr
.X_op
== O_absent
12744 && offset_expr
.X_op
== O_symbol
12745 && offset_expr
.X_add_number
== 0);
12746 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12747 if (strcmp (s
, ".lit8") == 0)
12749 op
[2] = mips_gp_register
;
12750 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12751 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12752 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12756 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12758 if (mips_pic
!= NO_PIC
)
12759 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12760 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12763 /* FIXME: This won't work for a 64 bit address. */
12764 macro_build_lui (&offset_expr
, AT
);
12768 offset_reloc
[0] = BFD_RELOC_LO16
;
12769 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12770 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12773 /* Fall through. */
12776 /* The MIPS assembler seems to check for X_add_number not
12777 being double aligned and generating:
12780 addiu at,at,%lo(foo+1)
12783 But, the resulting address is the same after relocation so why
12784 generate the extra instruction? */
12785 /* Itbl support may require additional care here. */
12788 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12797 gas_assert (!mips_opts
.micromips
);
12798 /* Itbl support may require additional care here. */
12801 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12821 if (GPR_SIZE
== 64)
12831 if (GPR_SIZE
== 64)
12839 /* Even on a big endian machine $fn comes before $fn+1. We have
12840 to adjust when loading from memory. We set coproc if we must
12841 load $fn+1 first. */
12842 /* Itbl support may require additional care here. */
12843 if (!target_big_endian
)
12847 if (small_offset_p (0, align
, 16))
12850 if (!small_offset_p (4, align
, 16))
12852 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12853 -1, offset_reloc
[0], offset_reloc
[1],
12855 expr1
.X_add_number
= 0;
12859 offset_reloc
[0] = BFD_RELOC_LO16
;
12860 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12861 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12863 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12865 ep
->X_add_number
+= 4;
12866 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12867 offset_reloc
[1], offset_reloc
[2], breg
);
12868 ep
->X_add_number
-= 4;
12869 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12870 offset_reloc
[1], offset_reloc
[2], breg
);
12874 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12875 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12877 ep
->X_add_number
+= 4;
12878 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12879 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12885 if (offset_expr
.X_op
!= O_symbol
12886 && offset_expr
.X_op
!= O_constant
)
12888 as_bad (_("expression too complex"));
12889 offset_expr
.X_op
= O_constant
;
12892 if (HAVE_32BIT_ADDRESSES
12893 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12897 sprintf_vma (value
, offset_expr
.X_add_number
);
12898 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12901 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12903 /* If this is a reference to a GP relative symbol, we want
12904 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12905 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12906 If we have a base register, we use this
12908 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12909 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12910 If this is not a GP relative symbol, we want
12911 lui $at,<sym> (BFD_RELOC_HI16_S)
12912 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12913 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12914 If there is a base register, we add it to $at after the
12915 lui instruction. If there is a constant, we always use
12917 if (offset_expr
.X_op
== O_symbol
12918 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12919 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12921 relax_start (offset_expr
.X_add_symbol
);
12924 tempreg
= mips_gp_register
;
12928 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12929 AT
, breg
, mips_gp_register
);
12934 /* Itbl support may require additional care here. */
12935 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12936 BFD_RELOC_GPREL16
, tempreg
);
12937 offset_expr
.X_add_number
+= 4;
12939 /* Set mips_optimize to 2 to avoid inserting an
12941 hold_mips_optimize
= mips_optimize
;
12943 /* Itbl support may require additional care here. */
12944 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12945 BFD_RELOC_GPREL16
, tempreg
);
12946 mips_optimize
= hold_mips_optimize
;
12950 offset_expr
.X_add_number
-= 4;
12953 if (offset_high_part (offset_expr
.X_add_number
, 16)
12954 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12956 load_address (AT
, &offset_expr
, &used_at
);
12957 offset_expr
.X_op
= O_constant
;
12958 offset_expr
.X_add_number
= 0;
12961 macro_build_lui (&offset_expr
, AT
);
12963 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12964 /* Itbl support may require additional care here. */
12965 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12966 BFD_RELOC_LO16
, AT
);
12967 /* FIXME: How do we handle overflow here? */
12968 offset_expr
.X_add_number
+= 4;
12969 /* Itbl support may require additional care here. */
12970 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12971 BFD_RELOC_LO16
, AT
);
12972 if (mips_relax
.sequence
)
12975 else if (!mips_big_got
)
12977 /* If this is a reference to an external symbol, we want
12978 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12981 <op> op[0]+1,4($at)
12983 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12985 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12986 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12987 If there is a base register we add it to $at before the
12988 lwc1 instructions. If there is a constant we include it
12989 in the lwc1 instructions. */
12991 expr1
.X_add_number
= offset_expr
.X_add_number
;
12992 if (expr1
.X_add_number
< -0x8000
12993 || expr1
.X_add_number
>= 0x8000 - 4)
12994 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12995 load_got_offset (AT
, &offset_expr
);
12998 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13000 /* Set mips_optimize to 2 to avoid inserting an undesired
13002 hold_mips_optimize
= mips_optimize
;
13005 /* Itbl support may require additional care here. */
13006 relax_start (offset_expr
.X_add_symbol
);
13007 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13008 BFD_RELOC_LO16
, AT
);
13009 expr1
.X_add_number
+= 4;
13010 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13011 BFD_RELOC_LO16
, AT
);
13013 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13014 BFD_RELOC_LO16
, AT
);
13015 offset_expr
.X_add_number
+= 4;
13016 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13017 BFD_RELOC_LO16
, AT
);
13020 mips_optimize
= hold_mips_optimize
;
13022 else if (mips_big_got
)
13026 /* If this is a reference to an external symbol, we want
13027 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13029 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13032 <op> op[0]+1,4($at)
13034 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13036 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13037 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13038 If there is a base register we add it to $at before the
13039 lwc1 instructions. If there is a constant we include it
13040 in the lwc1 instructions. */
13042 expr1
.X_add_number
= offset_expr
.X_add_number
;
13043 offset_expr
.X_add_number
= 0;
13044 if (expr1
.X_add_number
< -0x8000
13045 || expr1
.X_add_number
>= 0x8000 - 4)
13046 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13047 gpdelay
= reg_needs_delay (mips_gp_register
);
13048 relax_start (offset_expr
.X_add_symbol
);
13049 macro_build (&offset_expr
, "lui", LUI_FMT
,
13050 AT
, BFD_RELOC_MIPS_GOT_HI16
);
13051 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13052 AT
, AT
, mips_gp_register
);
13053 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
13054 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
13057 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13058 /* Itbl support may require additional care here. */
13059 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13060 BFD_RELOC_LO16
, AT
);
13061 expr1
.X_add_number
+= 4;
13063 /* Set mips_optimize to 2 to avoid inserting an undesired
13065 hold_mips_optimize
= mips_optimize
;
13067 /* Itbl support may require additional care here. */
13068 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13069 BFD_RELOC_LO16
, AT
);
13070 mips_optimize
= hold_mips_optimize
;
13071 expr1
.X_add_number
-= 4;
13074 offset_expr
.X_add_number
= expr1
.X_add_number
;
13076 macro_build (NULL
, "nop", "");
13077 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
13078 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
13081 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13082 /* Itbl support may require additional care here. */
13083 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13084 BFD_RELOC_LO16
, AT
);
13085 offset_expr
.X_add_number
+= 4;
13087 /* Set mips_optimize to 2 to avoid inserting an undesired
13089 hold_mips_optimize
= mips_optimize
;
13091 /* Itbl support may require additional care here. */
13092 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13093 BFD_RELOC_LO16
, AT
);
13094 mips_optimize
= hold_mips_optimize
;
13108 gas_assert (!mips_opts
.micromips
);
13113 /* New code added to support COPZ instructions.
13114 This code builds table entries out of the macros in mip_opcodes.
13115 R4000 uses interlocks to handle coproc delays.
13116 Other chips (like the R3000) require nops to be inserted for delays.
13118 FIXME: Currently, we require that the user handle delays.
13119 In order to fill delay slots for non-interlocked chips,
13120 we must have a way to specify delays based on the coprocessor.
13121 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13122 What are the side-effects of the cop instruction?
13123 What cache support might we have and what are its effects?
13124 Both coprocessor & memory require delays. how long???
13125 What registers are read/set/modified?
13127 If an itbl is provided to interpret cop instructions,
13128 this knowledge can be encoded in the itbl spec. */
13142 gas_assert (!mips_opts
.micromips
);
13143 /* For now we just do C (same as Cz). The parameter will be
13144 stored in insn_opcode by mips_ip. */
13145 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13149 move_register (op
[0], op
[1]);
13153 gas_assert (mips_opts
.micromips
);
13154 gas_assert (mips_opts
.insn32
);
13155 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13156 micromips_to_32_reg_m_map
[op
[1]]);
13157 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13158 micromips_to_32_reg_n_map
[op
[2]]);
13163 /* Fall through. */
13165 if (mips_opts
.arch
== CPU_R5900
)
13166 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13170 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13171 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13177 /* Fall through. */
13179 /* The MIPS assembler some times generates shifts and adds. I'm
13180 not trying to be that fancy. GCC should do this for us
13183 load_register (AT
, &imm_expr
, dbl
);
13184 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13185 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13190 /* Fall through. */
13197 /* Fall through. */
13200 start_noreorder ();
13203 load_register (AT
, &imm_expr
, dbl
);
13204 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13205 op
[1], imm
? AT
: op
[2]);
13206 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13207 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13208 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13210 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13213 if (mips_opts
.micromips
)
13214 micromips_label_expr (&label_expr
);
13216 label_expr
.X_add_number
= 8;
13217 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13218 macro_build (NULL
, "nop", "");
13219 macro_build (NULL
, "break", BRK_FMT
, 6);
13220 if (mips_opts
.micromips
)
13221 micromips_add_label ();
13224 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13229 /* Fall through. */
13236 /* Fall through. */
13239 start_noreorder ();
13242 load_register (AT
, &imm_expr
, dbl
);
13243 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13244 op
[1], imm
? AT
: op
[2]);
13245 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13246 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13248 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13251 if (mips_opts
.micromips
)
13252 micromips_label_expr (&label_expr
);
13254 label_expr
.X_add_number
= 8;
13255 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13256 macro_build (NULL
, "nop", "");
13257 macro_build (NULL
, "break", BRK_FMT
, 6);
13258 if (mips_opts
.micromips
)
13259 micromips_add_label ();
13265 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13267 if (op
[0] == op
[1])
13274 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13275 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13279 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13280 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13281 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13282 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13286 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13288 if (op
[0] == op
[1])
13295 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13296 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13300 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13301 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13302 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13303 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13312 rot
= imm_expr
.X_add_number
& 0x3f;
13313 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13315 rot
= (64 - rot
) & 0x3f;
13317 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13319 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13324 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13327 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13328 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13331 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13332 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13333 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13341 rot
= imm_expr
.X_add_number
& 0x1f;
13342 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13344 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13345 (32 - rot
) & 0x1f);
13350 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13354 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13355 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13356 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13361 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13363 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13367 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13368 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13369 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13370 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13374 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13376 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13380 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13381 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13382 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13383 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13392 rot
= imm_expr
.X_add_number
& 0x3f;
13393 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13396 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13398 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13403 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13406 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13407 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13410 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13411 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13412 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13420 rot
= imm_expr
.X_add_number
& 0x1f;
13421 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13423 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13428 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13432 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13433 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13434 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13440 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13441 else if (op
[2] == 0)
13442 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13445 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13446 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13451 if (imm_expr
.X_add_number
== 0)
13453 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13458 as_warn (_("instruction %s: result is always false"),
13459 ip
->insn_mo
->name
);
13460 move_register (op
[0], 0);
13463 if (CPU_HAS_SEQ (mips_opts
.arch
)
13464 && -512 <= imm_expr
.X_add_number
13465 && imm_expr
.X_add_number
< 512)
13467 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13468 (int) imm_expr
.X_add_number
);
13471 if (imm_expr
.X_add_number
>= 0
13472 && imm_expr
.X_add_number
< 0x10000)
13473 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13474 else if (imm_expr
.X_add_number
> -0x8000
13475 && imm_expr
.X_add_number
< 0)
13477 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13478 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13479 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13481 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13484 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13485 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13490 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13491 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13494 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13497 case M_SGE
: /* X >= Y <==> not (X < Y) */
13503 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13504 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13507 case M_SGE_I
: /* X >= I <==> not (X < I). */
13509 if (imm_expr
.X_add_number
>= -0x8000
13510 && imm_expr
.X_add_number
< 0x8000)
13511 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13512 op
[0], op
[1], BFD_RELOC_LO16
);
13515 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13516 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13520 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13523 case M_SGT
: /* X > Y <==> Y < X. */
13529 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13532 case M_SGT_I
: /* X > I <==> I < X. */
13539 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13540 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13543 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X). */
13549 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13550 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13553 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13560 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13561 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13562 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13566 if (imm_expr
.X_add_number
>= -0x8000
13567 && imm_expr
.X_add_number
< 0x8000)
13569 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13574 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13575 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13579 if (imm_expr
.X_add_number
>= -0x8000
13580 && imm_expr
.X_add_number
< 0x8000)
13582 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13587 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13588 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13593 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13594 else if (op
[2] == 0)
13595 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13598 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13599 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13604 if (imm_expr
.X_add_number
== 0)
13606 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13611 as_warn (_("instruction %s: result is always true"),
13612 ip
->insn_mo
->name
);
13613 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13614 op
[0], 0, BFD_RELOC_LO16
);
13617 if (CPU_HAS_SEQ (mips_opts
.arch
)
13618 && -512 <= imm_expr
.X_add_number
13619 && imm_expr
.X_add_number
< 512)
13621 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13622 (int) imm_expr
.X_add_number
);
13625 if (imm_expr
.X_add_number
>= 0
13626 && imm_expr
.X_add_number
< 0x10000)
13628 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13631 else if (imm_expr
.X_add_number
> -0x8000
13632 && imm_expr
.X_add_number
< 0)
13634 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13635 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13636 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13638 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13641 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13642 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13647 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13648 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13651 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13666 if (!mips_opts
.micromips
)
13668 if (imm_expr
.X_add_number
> -0x200
13669 && imm_expr
.X_add_number
<= 0x200)
13671 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13672 (int) -imm_expr
.X_add_number
);
13681 if (imm_expr
.X_add_number
> -0x8000
13682 && imm_expr
.X_add_number
<= 0x8000)
13684 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13685 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13690 load_register (AT
, &imm_expr
, dbl
);
13691 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13713 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13714 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13719 gas_assert (!mips_opts
.micromips
);
13720 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13724 * Is the double cfc1 instruction a bug in the mips assembler;
13725 * or is there a reason for it?
13727 start_noreorder ();
13728 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13729 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13730 macro_build (NULL
, "nop", "");
13731 expr1
.X_add_number
= 3;
13732 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13733 expr1
.X_add_number
= 2;
13734 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13735 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13736 macro_build (NULL
, "nop", "");
13737 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13739 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13740 macro_build (NULL
, "nop", "");
13757 offbits
= (mips_opts
.micromips
? 12 : 16);
13763 offbits
= (mips_opts
.micromips
? 12 : 16);
13775 offbits
= (mips_opts
.micromips
? 12 : 16);
13782 offbits
= (mips_opts
.micromips
? 12 : 16);
13788 large_offset
= !small_offset_p (off
, align
, offbits
);
13790 expr1
.X_add_number
= 0;
13795 if (small_offset_p (0, align
, 16))
13796 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13797 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13800 load_address (tempreg
, ep
, &used_at
);
13802 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13803 tempreg
, tempreg
, breg
);
13805 offset_reloc
[0] = BFD_RELOC_LO16
;
13806 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13807 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13812 else if (!ust
&& op
[0] == breg
)
13823 if (!target_big_endian
)
13824 ep
->X_add_number
+= off
;
13826 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13828 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13829 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13831 if (!target_big_endian
)
13832 ep
->X_add_number
-= off
;
13834 ep
->X_add_number
+= off
;
13836 macro_build (NULL
, s2
, "t,~(b)",
13837 tempreg
, (int) ep
->X_add_number
, breg
);
13839 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13840 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13842 /* If necessary, move the result in tempreg to the final destination. */
13843 if (!ust
&& op
[0] != tempreg
)
13845 /* Protect second load's delay slot. */
13847 move_register (op
[0], tempreg
);
13853 if (target_big_endian
== ust
)
13854 ep
->X_add_number
+= off
;
13855 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13856 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13857 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13859 /* For halfword transfers we need a temporary register to shuffle
13860 bytes. Unfortunately for M_USH_A we have none available before
13861 the next store as AT holds the base address. We deal with this
13862 case by clobbering TREG and then restoring it as with ULH. */
13863 tempreg
= ust
== large_offset
? op
[0] : AT
;
13865 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13867 if (target_big_endian
== ust
)
13868 ep
->X_add_number
-= off
;
13870 ep
->X_add_number
+= off
;
13871 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13872 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13874 /* For M_USH_A re-retrieve the LSB. */
13875 if (ust
&& large_offset
)
13877 if (target_big_endian
)
13878 ep
->X_add_number
+= off
;
13880 ep
->X_add_number
-= off
;
13881 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13882 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13884 /* For ULH and M_USH_A OR the LSB in. */
13885 if (!ust
|| large_offset
)
13887 tempreg
= !large_offset
? AT
: op
[0];
13888 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13889 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13894 /* FIXME: Check if this is one of the itbl macros, since they
13895 are added dynamically. */
13896 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13899 if (!mips_opts
.at
&& used_at
)
13900 as_bad (_("macro used $at after \".set noat\""));
13903 /* Implement macros in mips16 mode. */
13906 mips16_macro (struct mips_cl_insn
*ip
)
13908 const struct mips_operand_array
*operands
;
13913 const char *s
, *s2
, *s3
;
13914 unsigned int op
[MAX_OPERANDS
];
13917 mask
= ip
->insn_mo
->mask
;
13919 operands
= insn_operands (ip
);
13920 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13921 if (operands
->operand
[i
])
13922 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13926 expr1
.X_op
= O_constant
;
13927 expr1
.X_op_symbol
= NULL
;
13928 expr1
.X_add_symbol
= NULL
;
13929 expr1
.X_add_number
= 1;
13940 /* Fall through. */
13946 /* Fall through. */
13950 start_noreorder ();
13951 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13952 expr1
.X_add_number
= 2;
13953 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13954 macro_build (NULL
, "break", "6", 7);
13956 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13957 since that causes an overflow. We should do that as well,
13958 but I don't see how to do the comparisons without a temporary
13961 macro_build (NULL
, s
, "x", op
[0]);
13980 start_noreorder ();
13981 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13982 expr1
.X_add_number
= 2;
13983 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13984 macro_build (NULL
, "break", "6", 7);
13986 macro_build (NULL
, s2
, "x", op
[0]);
13991 /* Fall through. */
13993 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13994 macro_build (NULL
, "mflo", "x", op
[0]);
14002 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14003 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
14007 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14008 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
14012 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14013 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
14035 goto do_reverse_branch
;
14039 goto do_reverse_branch
;
14051 goto do_reverse_branch
;
14062 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
14063 macro_build (&offset_expr
, s2
, "p");
14090 goto do_addone_branch_i
;
14095 goto do_addone_branch_i
;
14110 goto do_addone_branch_i
;
14116 do_addone_branch_i
:
14117 ++imm_expr
.X_add_number
;
14120 macro_build (&imm_expr
, s
, s3
, op
[0]);
14121 macro_build (&offset_expr
, s2
, "p");
14125 expr1
.X_add_number
= 0;
14126 macro_build (&expr1
, "slti", "x,8", op
[1]);
14127 if (op
[0] != op
[1])
14128 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
14129 expr1
.X_add_number
= 2;
14130 macro_build (&expr1
, "bteqz", "p");
14131 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14136 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14137 opcode bits in *OPCODE_EXTRA. */
14139 static struct mips_opcode
*
14140 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
14141 ssize_t length
, unsigned int *opcode_extra
)
14143 char *name
, *dot
, *p
;
14144 unsigned int mask
, suffix
;
14146 struct mips_opcode
*insn
;
14148 /* Make a copy of the instruction so that we can fiddle with it. */
14149 name
= xstrndup (start
, length
);
14151 /* Look up the instruction as-is. */
14152 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14156 dot
= strchr (name
, '.');
14159 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14160 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14161 if (*p
== 0 && mask
!= 0)
14164 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14166 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14168 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14174 if (mips_opts
.micromips
)
14176 /* See if there's an instruction size override suffix,
14177 either `16' or `32', at the end of the mnemonic proper,
14178 that defines the operation, i.e. before the first `.'
14179 character if any. Strip it and retry. */
14180 opend
= dot
!= NULL
? dot
- name
: length
;
14181 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14183 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14189 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14190 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14193 forced_insn_length
= suffix
;
14205 /* Assemble an instruction into its binary format. If the instruction
14206 is a macro, set imm_expr and offset_expr to the values associated
14207 with "I" and "A" operands respectively. Otherwise store the value
14208 of the relocatable field (if any) in offset_expr. In both cases
14209 set offset_reloc to the relocation operators applied to offset_expr. */
14212 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14214 const struct mips_opcode
*first
, *past
;
14215 struct hash_control
*hash
;
14218 struct mips_operand_token
*tokens
;
14219 unsigned int opcode_extra
;
14221 if (mips_opts
.micromips
)
14223 hash
= micromips_op_hash
;
14224 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14229 past
= &mips_opcodes
[NUMOPCODES
];
14231 forced_insn_length
= 0;
14234 /* We first try to match an instruction up to a space or to the end. */
14235 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14238 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14241 set_insn_error (0, _("unrecognized opcode"));
14245 if (strcmp (first
->name
, "li.s") == 0)
14247 else if (strcmp (first
->name
, "li.d") == 0)
14251 tokens
= mips_parse_arguments (str
+ end
, format
);
14255 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14256 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14257 set_insn_error (0, _("invalid operands"));
14259 obstack_free (&mips_operand_tokens
, tokens
);
14262 /* As for mips_ip, but used when assembling MIPS16 code.
14263 Also set forced_insn_length to the resulting instruction size in
14264 bytes if the user explicitly requested a small or extended instruction. */
14267 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14270 struct mips_opcode
*first
;
14271 struct mips_operand_token
*tokens
;
14274 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14296 else if (*s
== 'e')
14303 else if (*s
++ == ' ')
14305 set_insn_error (0, _("unrecognized opcode"));
14308 forced_insn_length
= l
;
14311 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14316 set_insn_error (0, _("unrecognized opcode"));
14320 tokens
= mips_parse_arguments (s
, 0);
14324 if (!match_mips16_insns (insn
, first
, tokens
))
14325 set_insn_error (0, _("invalid operands"));
14327 obstack_free (&mips_operand_tokens
, tokens
);
14330 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14331 NBITS is the number of significant bits in VAL. */
14333 static unsigned long
14334 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14339 val
&= (1U << nbits
) - 1;
14340 if (nbits
== 16 || nbits
== 9)
14342 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14345 else if (nbits
== 15)
14347 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14350 else if (nbits
== 6)
14352 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14355 return (extval
<< 16) | val
;
14358 /* Like decode_mips16_operand, but require the operand to be defined and
14359 require it to be an integer. */
14361 static const struct mips_int_operand
*
14362 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14364 const struct mips_operand
*operand
;
14366 operand
= decode_mips16_operand (type
, extended_p
);
14367 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14369 return (const struct mips_int_operand
*) operand
;
14372 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14375 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14376 bfd_reloc_code_real_type reloc
, offsetT sval
)
14378 int min_val
, max_val
;
14380 min_val
= mips_int_operand_min (operand
);
14381 max_val
= mips_int_operand_max (operand
);
14382 if (reloc
!= BFD_RELOC_UNUSED
)
14385 sval
= SEXT_16BIT (sval
);
14390 return (sval
>= min_val
14392 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14395 /* Install immediate value VAL into MIPS16 instruction *INSN,
14396 extending it if necessary. The instruction in *INSN may
14397 already be extended.
14399 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14400 if none. In the former case, VAL is a 16-bit number with no
14401 defined signedness.
14403 TYPE is the type of the immediate field. USER_INSN_LENGTH
14404 is the length that the user requested, or 0 if none. */
14407 mips16_immed (const char *file
, unsigned int line
, int type
,
14408 bfd_reloc_code_real_type reloc
, offsetT val
,
14409 unsigned int user_insn_length
, unsigned long *insn
)
14411 const struct mips_int_operand
*operand
;
14412 unsigned int uval
, length
;
14414 operand
= mips16_immed_operand (type
, FALSE
);
14415 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14417 /* We need an extended instruction. */
14418 if (user_insn_length
== 2)
14419 as_bad_where (file
, line
, _("invalid unextended operand value"));
14421 *insn
|= MIPS16_EXTEND
;
14423 else if (user_insn_length
== 4)
14425 /* The operand doesn't force an unextended instruction to be extended.
14426 Warn if the user wanted an extended instruction anyway. */
14427 *insn
|= MIPS16_EXTEND
;
14428 as_warn_where (file
, line
,
14429 _("extended operand requested but not required"));
14432 length
= mips16_opcode_length (*insn
);
14435 operand
= mips16_immed_operand (type
, TRUE
);
14436 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14437 as_bad_where (file
, line
,
14438 _("operand value out of range for instruction"));
14440 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14441 if (length
== 2 || operand
->root
.lsb
!= 0)
14442 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14444 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14447 struct percent_op_match
14450 bfd_reloc_code_real_type reloc
;
14453 static const struct percent_op_match mips_percent_op
[] =
14455 {"%lo", BFD_RELOC_LO16
},
14456 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14457 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14458 {"%call16", BFD_RELOC_MIPS_CALL16
},
14459 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14460 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14461 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14462 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14463 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14464 {"%got", BFD_RELOC_MIPS_GOT16
},
14465 {"%gp_rel", BFD_RELOC_GPREL16
},
14466 {"%gprel", BFD_RELOC_GPREL16
},
14467 {"%half", BFD_RELOC_16
},
14468 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14469 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14470 {"%neg", BFD_RELOC_MIPS_SUB
},
14471 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14472 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14473 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14474 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14475 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14476 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14477 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14478 {"%hi", BFD_RELOC_HI16_S
},
14479 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14480 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14483 static const struct percent_op_match mips16_percent_op
[] =
14485 {"%lo", BFD_RELOC_MIPS16_LO16
},
14486 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14487 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14488 {"%got", BFD_RELOC_MIPS16_GOT16
},
14489 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14490 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14491 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14492 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14493 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14494 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14495 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14496 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14497 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14501 /* Return true if *STR points to a relocation operator. When returning true,
14502 move *STR over the operator and store its relocation code in *RELOC.
14503 Leave both *STR and *RELOC alone when returning false. */
14506 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14508 const struct percent_op_match
*percent_op
;
14511 if (mips_opts
.mips16
)
14513 percent_op
= mips16_percent_op
;
14514 limit
= ARRAY_SIZE (mips16_percent_op
);
14518 percent_op
= mips_percent_op
;
14519 limit
= ARRAY_SIZE (mips_percent_op
);
14522 for (i
= 0; i
< limit
; i
++)
14523 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14525 int len
= strlen (percent_op
[i
].str
);
14527 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14530 *str
+= strlen (percent_op
[i
].str
);
14531 *reloc
= percent_op
[i
].reloc
;
14533 /* Check whether the output BFD supports this relocation.
14534 If not, issue an error and fall back on something safe. */
14535 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14537 as_bad (_("relocation %s isn't supported by the current ABI"),
14538 percent_op
[i
].str
);
14539 *reloc
= BFD_RELOC_UNUSED
;
14547 /* Parse string STR as a 16-bit relocatable operand. Store the
14548 expression in *EP and the relocations in the array starting
14549 at RELOC. Return the number of relocation operators used.
14551 On exit, EXPR_END points to the first character after the expression. */
14554 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14557 bfd_reloc_code_real_type reversed_reloc
[3];
14558 size_t reloc_index
, i
;
14559 int crux_depth
, str_depth
;
14562 /* Search for the start of the main expression, recoding relocations
14563 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14564 of the main expression and with CRUX_DEPTH containing the number
14565 of open brackets at that point. */
14572 crux_depth
= str_depth
;
14574 /* Skip over whitespace and brackets, keeping count of the number
14576 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14581 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14582 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14584 my_getExpression (ep
, crux
);
14587 /* Match every open bracket. */
14588 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14592 if (crux_depth
> 0)
14593 as_bad (_("unclosed '('"));
14597 if (reloc_index
!= 0)
14599 prev_reloc_op_frag
= frag_now
;
14600 for (i
= 0; i
< reloc_index
; i
++)
14601 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14604 return reloc_index
;
14608 my_getExpression (expressionS
*ep
, char *str
)
14612 save_in
= input_line_pointer
;
14613 input_line_pointer
= str
;
14615 expr_end
= input_line_pointer
;
14616 input_line_pointer
= save_in
;
14620 md_atof (int type
, char *litP
, int *sizeP
)
14622 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14626 md_number_to_chars (char *buf
, valueT val
, int n
)
14628 if (target_big_endian
)
14629 number_to_chars_bigendian (buf
, val
, n
);
14631 number_to_chars_littleendian (buf
, val
, n
);
14634 static int support_64bit_objects(void)
14636 const char **list
, **l
;
14639 list
= bfd_target_list ();
14640 for (l
= list
; *l
!= NULL
; l
++)
14641 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14642 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14644 yes
= (*l
!= NULL
);
14649 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14650 NEW_VALUE. Warn if another value was already specified. Note:
14651 we have to defer parsing the -march and -mtune arguments in order
14652 to handle 'from-abi' correctly, since the ABI might be specified
14653 in a later argument. */
14656 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14658 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14659 as_warn (_("a different %s was already specified, is now %s"),
14660 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14663 *string_ptr
= new_value
;
14667 md_parse_option (int c
, const char *arg
)
14671 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14672 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14674 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14675 c
== mips_ases
[i
].option_on
);
14681 case OPTION_CONSTRUCT_FLOATS
:
14682 mips_disable_float_construction
= 0;
14685 case OPTION_NO_CONSTRUCT_FLOATS
:
14686 mips_disable_float_construction
= 1;
14698 target_big_endian
= 1;
14702 target_big_endian
= 0;
14708 else if (arg
[0] == '0')
14710 else if (arg
[0] == '1')
14720 mips_debug
= atoi (arg
);
14724 file_mips_opts
.isa
= ISA_MIPS1
;
14728 file_mips_opts
.isa
= ISA_MIPS2
;
14732 file_mips_opts
.isa
= ISA_MIPS3
;
14736 file_mips_opts
.isa
= ISA_MIPS4
;
14740 file_mips_opts
.isa
= ISA_MIPS5
;
14743 case OPTION_MIPS32
:
14744 file_mips_opts
.isa
= ISA_MIPS32
;
14747 case OPTION_MIPS32R2
:
14748 file_mips_opts
.isa
= ISA_MIPS32R2
;
14751 case OPTION_MIPS32R3
:
14752 file_mips_opts
.isa
= ISA_MIPS32R3
;
14755 case OPTION_MIPS32R5
:
14756 file_mips_opts
.isa
= ISA_MIPS32R5
;
14759 case OPTION_MIPS32R6
:
14760 file_mips_opts
.isa
= ISA_MIPS32R6
;
14763 case OPTION_MIPS64R2
:
14764 file_mips_opts
.isa
= ISA_MIPS64R2
;
14767 case OPTION_MIPS64R3
:
14768 file_mips_opts
.isa
= ISA_MIPS64R3
;
14771 case OPTION_MIPS64R5
:
14772 file_mips_opts
.isa
= ISA_MIPS64R5
;
14775 case OPTION_MIPS64R6
:
14776 file_mips_opts
.isa
= ISA_MIPS64R6
;
14779 case OPTION_MIPS64
:
14780 file_mips_opts
.isa
= ISA_MIPS64
;
14784 mips_set_option_string (&mips_tune_string
, arg
);
14788 mips_set_option_string (&mips_arch_string
, arg
);
14792 mips_set_option_string (&mips_arch_string
, "4650");
14793 mips_set_option_string (&mips_tune_string
, "4650");
14796 case OPTION_NO_M4650
:
14800 mips_set_option_string (&mips_arch_string
, "4010");
14801 mips_set_option_string (&mips_tune_string
, "4010");
14804 case OPTION_NO_M4010
:
14808 mips_set_option_string (&mips_arch_string
, "4100");
14809 mips_set_option_string (&mips_tune_string
, "4100");
14812 case OPTION_NO_M4100
:
14816 mips_set_option_string (&mips_arch_string
, "3900");
14817 mips_set_option_string (&mips_tune_string
, "3900");
14820 case OPTION_NO_M3900
:
14823 case OPTION_MICROMIPS
:
14824 if (file_mips_opts
.mips16
== 1)
14826 as_bad (_("-mmicromips cannot be used with -mips16"));
14829 file_mips_opts
.micromips
= 1;
14830 mips_no_prev_insn ();
14833 case OPTION_NO_MICROMIPS
:
14834 file_mips_opts
.micromips
= 0;
14835 mips_no_prev_insn ();
14838 case OPTION_MIPS16
:
14839 if (file_mips_opts
.micromips
== 1)
14841 as_bad (_("-mips16 cannot be used with -micromips"));
14844 file_mips_opts
.mips16
= 1;
14845 mips_no_prev_insn ();
14848 case OPTION_NO_MIPS16
:
14849 file_mips_opts
.mips16
= 0;
14850 mips_no_prev_insn ();
14853 case OPTION_FIX_24K
:
14857 case OPTION_NO_FIX_24K
:
14861 case OPTION_FIX_RM7000
:
14862 mips_fix_rm7000
= 1;
14865 case OPTION_NO_FIX_RM7000
:
14866 mips_fix_rm7000
= 0;
14869 case OPTION_FIX_LOONGSON3_LLSC
:
14870 mips_fix_loongson3_llsc
= TRUE
;
14873 case OPTION_NO_FIX_LOONGSON3_LLSC
:
14874 mips_fix_loongson3_llsc
= FALSE
;
14877 case OPTION_FIX_LOONGSON2F_JUMP
:
14878 mips_fix_loongson2f_jump
= TRUE
;
14881 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14882 mips_fix_loongson2f_jump
= FALSE
;
14885 case OPTION_FIX_LOONGSON2F_NOP
:
14886 mips_fix_loongson2f_nop
= TRUE
;
14889 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14890 mips_fix_loongson2f_nop
= FALSE
;
14893 case OPTION_FIX_VR4120
:
14894 mips_fix_vr4120
= 1;
14897 case OPTION_NO_FIX_VR4120
:
14898 mips_fix_vr4120
= 0;
14901 case OPTION_FIX_VR4130
:
14902 mips_fix_vr4130
= 1;
14905 case OPTION_NO_FIX_VR4130
:
14906 mips_fix_vr4130
= 0;
14909 case OPTION_FIX_CN63XXP1
:
14910 mips_fix_cn63xxp1
= TRUE
;
14913 case OPTION_NO_FIX_CN63XXP1
:
14914 mips_fix_cn63xxp1
= FALSE
;
14917 case OPTION_FIX_R5900
:
14918 mips_fix_r5900
= TRUE
;
14919 mips_fix_r5900_explicit
= TRUE
;
14922 case OPTION_NO_FIX_R5900
:
14923 mips_fix_r5900
= FALSE
;
14924 mips_fix_r5900_explicit
= TRUE
;
14927 case OPTION_RELAX_BRANCH
:
14928 mips_relax_branch
= 1;
14931 case OPTION_NO_RELAX_BRANCH
:
14932 mips_relax_branch
= 0;
14935 case OPTION_IGNORE_BRANCH_ISA
:
14936 mips_ignore_branch_isa
= TRUE
;
14939 case OPTION_NO_IGNORE_BRANCH_ISA
:
14940 mips_ignore_branch_isa
= FALSE
;
14943 case OPTION_INSN32
:
14944 file_mips_opts
.insn32
= TRUE
;
14947 case OPTION_NO_INSN32
:
14948 file_mips_opts
.insn32
= FALSE
;
14951 case OPTION_MSHARED
:
14952 mips_in_shared
= TRUE
;
14955 case OPTION_MNO_SHARED
:
14956 mips_in_shared
= FALSE
;
14959 case OPTION_MSYM32
:
14960 file_mips_opts
.sym32
= TRUE
;
14963 case OPTION_MNO_SYM32
:
14964 file_mips_opts
.sym32
= FALSE
;
14967 /* When generating ELF code, we permit -KPIC and -call_shared to
14968 select SVR4_PIC, and -non_shared to select no PIC. This is
14969 intended to be compatible with Irix 5. */
14970 case OPTION_CALL_SHARED
:
14971 mips_pic
= SVR4_PIC
;
14972 mips_abicalls
= TRUE
;
14975 case OPTION_CALL_NONPIC
:
14977 mips_abicalls
= TRUE
;
14980 case OPTION_NON_SHARED
:
14982 mips_abicalls
= FALSE
;
14985 /* The -xgot option tells the assembler to use 32 bit offsets
14986 when accessing the got in SVR4_PIC mode. It is for Irix
14993 g_switch_value
= atoi (arg
);
14997 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15000 mips_abi
= O32_ABI
;
15004 mips_abi
= N32_ABI
;
15008 mips_abi
= N64_ABI
;
15009 if (!support_64bit_objects())
15010 as_fatal (_("no compiled in support for 64 bit object file format"));
15014 file_mips_opts
.gp
= 32;
15018 file_mips_opts
.gp
= 64;
15022 file_mips_opts
.fp
= 32;
15026 file_mips_opts
.fp
= 0;
15030 file_mips_opts
.fp
= 64;
15033 case OPTION_ODD_SPREG
:
15034 file_mips_opts
.oddspreg
= 1;
15037 case OPTION_NO_ODD_SPREG
:
15038 file_mips_opts
.oddspreg
= 0;
15041 case OPTION_SINGLE_FLOAT
:
15042 file_mips_opts
.single_float
= 1;
15045 case OPTION_DOUBLE_FLOAT
:
15046 file_mips_opts
.single_float
= 0;
15049 case OPTION_SOFT_FLOAT
:
15050 file_mips_opts
.soft_float
= 1;
15053 case OPTION_HARD_FLOAT
:
15054 file_mips_opts
.soft_float
= 0;
15058 if (strcmp (arg
, "32") == 0)
15059 mips_abi
= O32_ABI
;
15060 else if (strcmp (arg
, "o64") == 0)
15061 mips_abi
= O64_ABI
;
15062 else if (strcmp (arg
, "n32") == 0)
15063 mips_abi
= N32_ABI
;
15064 else if (strcmp (arg
, "64") == 0)
15066 mips_abi
= N64_ABI
;
15067 if (! support_64bit_objects())
15068 as_fatal (_("no compiled in support for 64 bit object file "
15071 else if (strcmp (arg
, "eabi") == 0)
15072 mips_abi
= EABI_ABI
;
15075 as_fatal (_("invalid abi -mabi=%s"), arg
);
15080 case OPTION_M7000_HILO_FIX
:
15081 mips_7000_hilo_fix
= TRUE
;
15084 case OPTION_MNO_7000_HILO_FIX
:
15085 mips_7000_hilo_fix
= FALSE
;
15088 case OPTION_MDEBUG
:
15089 mips_flag_mdebug
= TRUE
;
15092 case OPTION_NO_MDEBUG
:
15093 mips_flag_mdebug
= FALSE
;
15097 mips_flag_pdr
= TRUE
;
15100 case OPTION_NO_PDR
:
15101 mips_flag_pdr
= FALSE
;
15104 case OPTION_MVXWORKS_PIC
:
15105 mips_pic
= VXWORKS_PIC
;
15109 if (strcmp (arg
, "2008") == 0)
15111 else if (strcmp (arg
, "legacy") == 0)
15115 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
15124 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15129 /* Set up globals to tune for the ISA or processor described by INFO. */
15132 mips_set_tune (const struct mips_cpu_info
*info
)
15135 mips_tune
= info
->cpu
;
15140 mips_after_parse_args (void)
15142 const struct mips_cpu_info
*arch_info
= 0;
15143 const struct mips_cpu_info
*tune_info
= 0;
15145 /* GP relative stuff not working for PE. */
15146 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15148 if (g_switch_seen
&& g_switch_value
!= 0)
15149 as_bad (_("-G not supported in this configuration"));
15150 g_switch_value
= 0;
15153 if (mips_abi
== NO_ABI
)
15154 mips_abi
= MIPS_DEFAULT_ABI
;
15156 /* The following code determines the architecture.
15157 Similar code was added to GCC 3.3 (see override_options() in
15158 config/mips/mips.c). The GAS and GCC code should be kept in sync
15159 as much as possible. */
15161 if (mips_arch_string
!= 0)
15162 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15164 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15166 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15167 ISA level specified by -mipsN, while arch_info->isa contains
15168 the -march selection (if any). */
15169 if (arch_info
!= 0)
15171 /* -march takes precedence over -mipsN, since it is more descriptive.
15172 There's no harm in specifying both as long as the ISA levels
15174 if (file_mips_opts
.isa
!= arch_info
->isa
)
15175 as_bad (_("-%s conflicts with the other architecture options,"
15176 " which imply -%s"),
15177 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15178 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15181 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15184 if (arch_info
== 0)
15186 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15187 gas_assert (arch_info
);
15190 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15191 as_bad (_("-march=%s is not compatible with the selected ABI"),
15194 file_mips_opts
.arch
= arch_info
->cpu
;
15195 file_mips_opts
.isa
= arch_info
->isa
;
15196 file_mips_opts
.init_ase
= arch_info
->ase
;
15198 /* Set up initial mips_opts state. */
15199 mips_opts
= file_mips_opts
;
15201 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15202 if (!mips_fix_r5900_explicit
)
15203 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15205 /* The register size inference code is now placed in
15206 file_mips_check_options. */
15208 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15210 if (mips_tune_string
!= 0)
15211 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15213 if (tune_info
== 0)
15214 mips_set_tune (arch_info
);
15216 mips_set_tune (tune_info
);
15218 if (mips_flag_mdebug
< 0)
15219 mips_flag_mdebug
= 0;
15223 mips_init_after_args (void)
15225 /* Initialize opcodes. */
15226 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15227 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15231 md_pcrel_from (fixS
*fixP
)
15233 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15235 switch (fixP
->fx_r_type
)
15237 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15238 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15239 /* Return the address of the delay slot. */
15242 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15243 case BFD_RELOC_MICROMIPS_JMP
:
15244 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15245 case BFD_RELOC_16_PCREL_S2
:
15246 case BFD_RELOC_MIPS_21_PCREL_S2
:
15247 case BFD_RELOC_MIPS_26_PCREL_S2
:
15248 case BFD_RELOC_MIPS_JMP
:
15249 /* Return the address of the delay slot. */
15252 case BFD_RELOC_MIPS_18_PCREL_S3
:
15253 /* Return the aligned address of the doubleword containing
15254 the instruction. */
15262 /* This is called before the symbol table is processed. In order to
15263 work with gcc when using mips-tfile, we must keep all local labels.
15264 However, in other cases, we want to discard them. If we were
15265 called with -g, but we didn't see any debugging information, it may
15266 mean that gcc is smuggling debugging information through to
15267 mips-tfile, in which case we must generate all local labels. */
15270 mips_frob_file_before_adjust (void)
15272 #ifndef NO_ECOFF_DEBUGGING
15273 if (ECOFF_DEBUGGING
15275 && ! ecoff_debugging_seen
)
15276 flag_keep_locals
= 1;
15280 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15281 the corresponding LO16 reloc. This is called before md_apply_fix and
15282 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15283 relocation operators.
15285 For our purposes, a %lo() expression matches a %got() or %hi()
15288 (a) it refers to the same symbol; and
15289 (b) the offset applied in the %lo() expression is no lower than
15290 the offset applied in the %got() or %hi().
15292 (b) allows us to cope with code like:
15295 lh $4,%lo(foo+2)($4)
15297 ...which is legal on RELA targets, and has a well-defined behaviour
15298 if the user knows that adding 2 to "foo" will not induce a carry to
15301 When several %lo()s match a particular %got() or %hi(), we use the
15302 following rules to distinguish them:
15304 (1) %lo()s with smaller offsets are a better match than %lo()s with
15307 (2) %lo()s with no matching %got() or %hi() are better than those
15308 that already have a matching %got() or %hi().
15310 (3) later %lo()s are better than earlier %lo()s.
15312 These rules are applied in order.
15314 (1) means, among other things, that %lo()s with identical offsets are
15315 chosen if they exist.
15317 (2) means that we won't associate several high-part relocations with
15318 the same low-part relocation unless there's no alternative. Having
15319 several high parts for the same low part is a GNU extension; this rule
15320 allows careful users to avoid it.
15322 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15323 with the last high-part relocation being at the front of the list.
15324 It therefore makes sense to choose the last matching low-part
15325 relocation, all other things being equal. It's also easier
15326 to code that way. */
15329 mips_frob_file (void)
15331 struct mips_hi_fixup
*l
;
15332 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15334 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15336 segment_info_type
*seginfo
;
15337 bfd_boolean matched_lo_p
;
15338 fixS
**hi_pos
, **lo_pos
, **pos
;
15340 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15342 /* If a GOT16 relocation turns out to be against a global symbol,
15343 there isn't supposed to be a matching LO. Ignore %gots against
15344 constants; we'll report an error for those later. */
15345 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15346 && !(l
->fixp
->fx_addsy
15347 && pic_need_relax (l
->fixp
->fx_addsy
)))
15350 /* Check quickly whether the next fixup happens to be a matching %lo. */
15351 if (fixup_has_matching_lo_p (l
->fixp
))
15354 seginfo
= seg_info (l
->seg
);
15356 /* Set HI_POS to the position of this relocation in the chain.
15357 Set LO_POS to the position of the chosen low-part relocation.
15358 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15359 relocation that matches an immediately-preceding high-part
15363 matched_lo_p
= FALSE
;
15364 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15366 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15368 if (*pos
== l
->fixp
)
15371 if ((*pos
)->fx_r_type
== looking_for_rtype
15372 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15373 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15375 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15377 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15380 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15381 && fixup_has_matching_lo_p (*pos
));
15384 /* If we found a match, remove the high-part relocation from its
15385 current position and insert it before the low-part relocation.
15386 Make the offsets match so that fixup_has_matching_lo_p()
15389 We don't warn about unmatched high-part relocations since some
15390 versions of gcc have been known to emit dead "lui ...%hi(...)"
15392 if (lo_pos
!= NULL
)
15394 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15395 if (l
->fixp
->fx_next
!= *lo_pos
)
15397 *hi_pos
= l
->fixp
->fx_next
;
15398 l
->fixp
->fx_next
= *lo_pos
;
15406 mips_force_relocation (fixS
*fixp
)
15408 if (generic_force_reloc (fixp
))
15411 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15412 so that the linker relaxation can update targets. */
15413 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15414 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15415 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15418 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15419 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15420 microMIPS symbols so that we can do cross-mode branch diagnostics
15421 and BAL to JALX conversion by the linker. */
15422 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15423 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15424 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15426 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15429 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15430 if (ISA_IS_R6 (file_mips_opts
.isa
)
15431 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15432 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15433 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15434 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15435 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15436 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15437 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15443 /* Implement TC_FORCE_RELOCATION_ABS. */
15446 mips_force_relocation_abs (fixS
*fixp
)
15448 if (generic_force_reloc (fixp
))
15451 /* These relocations do not have enough bits in the in-place addend
15452 to hold an arbitrary absolute section's offset. */
15453 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15459 /* Read the instruction associated with RELOC from BUF. */
15461 static unsigned int
15462 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15464 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15465 return read_compressed_insn (buf
, 4);
15467 return read_insn (buf
);
15470 /* Write instruction INSN to BUF, given that it has been relocated
15474 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15475 unsigned long insn
)
15477 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15478 write_compressed_insn (buf
, insn
, 4);
15480 write_insn (buf
, insn
);
15483 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15484 to a symbol in another ISA mode, which cannot be converted to JALX. */
15487 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15489 unsigned long opcode
;
15493 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15496 other
= S_GET_OTHER (fixP
->fx_addsy
);
15497 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15498 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15499 switch (fixP
->fx_r_type
)
15501 case BFD_RELOC_MIPS_JMP
:
15502 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15503 case BFD_RELOC_MICROMIPS_JMP
:
15504 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15510 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15511 jump to a symbol in the same ISA mode. */
15514 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15516 unsigned long opcode
;
15520 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15523 other
= S_GET_OTHER (fixP
->fx_addsy
);
15524 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15525 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15526 switch (fixP
->fx_r_type
)
15528 case BFD_RELOC_MIPS_JMP
:
15529 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15530 case BFD_RELOC_MIPS16_JMP
:
15531 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15532 case BFD_RELOC_MICROMIPS_JMP
:
15533 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15539 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15540 to a symbol whose value plus addend is not aligned according to the
15541 ultimate (after linker relaxation) jump instruction's immediate field
15542 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15543 regular MIPS code, to (1 << 2). */
15546 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15548 bfd_boolean micro_to_mips_p
;
15552 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15555 other
= S_GET_OTHER (fixP
->fx_addsy
);
15556 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15557 val
+= fixP
->fx_offset
;
15558 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15559 && !ELF_ST_IS_MICROMIPS (other
));
15560 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15561 != ELF_ST_IS_COMPRESSED (other
));
15564 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15565 to a symbol whose annotation indicates another ISA mode. For absolute
15566 symbols check the ISA bit instead.
15568 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15569 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15570 MIPS symbols and associated with BAL instructions as these instructions
15571 may be converted to JALX by the linker. */
15574 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15576 bfd_boolean absolute_p
;
15577 unsigned long opcode
;
15583 if (mips_ignore_branch_isa
)
15586 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15589 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15590 absolute_p
= bfd_is_abs_section (symsec
);
15592 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15593 other
= S_GET_OTHER (fixP
->fx_addsy
);
15595 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15596 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15597 switch (fixP
->fx_r_type
)
15599 case BFD_RELOC_16_PCREL_S2
:
15600 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15601 && opcode
!= 0x0411);
15602 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15603 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15604 && opcode
!= 0x4060);
15605 case BFD_RELOC_MIPS_21_PCREL_S2
:
15606 case BFD_RELOC_MIPS_26_PCREL_S2
:
15607 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15608 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15609 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15610 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15611 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15612 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15618 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15619 branch instruction pointed to by FIXP is not aligned according to the
15620 branch instruction's immediate field requirement. We need the addend
15621 to preserve the ISA bit and also the sum must not have bit 2 set. We
15622 must explicitly OR in the ISA bit from symbol annotation as the bit
15623 won't be set in the symbol's value then. */
15626 fix_bad_misaligned_branch_p (fixS
*fixP
)
15628 bfd_boolean absolute_p
;
15635 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15638 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15639 absolute_p
= bfd_is_abs_section (symsec
);
15641 val
= S_GET_VALUE (fixP
->fx_addsy
);
15642 other
= S_GET_OTHER (fixP
->fx_addsy
);
15643 off
= fixP
->fx_offset
;
15645 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15646 val
|= ELF_ST_IS_COMPRESSED (other
);
15648 return (val
& 0x3) != isa_bit
;
15651 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15652 and its calculated value VAL. */
15655 fix_validate_branch (fixS
*fixP
, valueT val
)
15657 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15659 _("branch to misaligned address (0x%lx)"),
15660 (long) (val
+ md_pcrel_from (fixP
)));
15661 else if (fix_bad_cross_mode_branch_p (fixP
))
15662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15663 _("branch to a symbol in another ISA mode"));
15664 else if (fix_bad_misaligned_branch_p (fixP
))
15665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15666 _("branch to misaligned address (0x%lx)"),
15667 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15668 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15670 _("cannot encode misaligned addend "
15671 "in the relocatable field (0x%lx)"),
15672 (long) fixP
->fx_offset
);
15675 /* Apply a fixup to the object file. */
15678 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15681 unsigned long insn
;
15682 reloc_howto_type
*howto
;
15684 if (fixP
->fx_pcrel
)
15685 switch (fixP
->fx_r_type
)
15687 case BFD_RELOC_16_PCREL_S2
:
15688 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15689 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15690 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15691 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15692 case BFD_RELOC_32_PCREL
:
15693 case BFD_RELOC_MIPS_21_PCREL_S2
:
15694 case BFD_RELOC_MIPS_26_PCREL_S2
:
15695 case BFD_RELOC_MIPS_18_PCREL_S3
:
15696 case BFD_RELOC_MIPS_19_PCREL_S2
:
15697 case BFD_RELOC_HI16_S_PCREL
:
15698 case BFD_RELOC_LO16_PCREL
:
15702 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15707 _("PC-relative reference to a different section"));
15711 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15712 that have no MIPS ELF equivalent. */
15713 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15715 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15720 gas_assert (fixP
->fx_size
== 2
15721 || fixP
->fx_size
== 4
15722 || fixP
->fx_r_type
== BFD_RELOC_8
15723 || fixP
->fx_r_type
== BFD_RELOC_16
15724 || fixP
->fx_r_type
== BFD_RELOC_64
15725 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15726 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15727 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15728 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15729 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15730 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15731 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15733 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15735 /* Don't treat parts of a composite relocation as done. There are two
15738 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15739 should nevertheless be emitted if the first part is.
15741 (2) In normal usage, composite relocations are never assembly-time
15742 constants. The easiest way of dealing with the pathological
15743 exceptions is to generate a relocation against STN_UNDEF and
15744 leave everything up to the linker. */
15745 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15748 switch (fixP
->fx_r_type
)
15750 case BFD_RELOC_MIPS_TLS_GD
:
15751 case BFD_RELOC_MIPS_TLS_LDM
:
15752 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15753 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15754 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15755 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15756 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15757 case BFD_RELOC_MIPS_TLS_TPREL32
:
15758 case BFD_RELOC_MIPS_TLS_TPREL64
:
15759 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15760 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15761 case BFD_RELOC_MICROMIPS_TLS_GD
:
15762 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15763 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15764 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15765 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15766 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15767 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15768 case BFD_RELOC_MIPS16_TLS_GD
:
15769 case BFD_RELOC_MIPS16_TLS_LDM
:
15770 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15771 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15772 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15773 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15774 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15775 if (fixP
->fx_addsy
)
15776 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15779 _("TLS relocation against a constant"));
15782 case BFD_RELOC_MIPS_JMP
:
15783 case BFD_RELOC_MIPS16_JMP
:
15784 case BFD_RELOC_MICROMIPS_JMP
:
15788 gas_assert (!fixP
->fx_done
);
15790 /* Shift is 2, unusually, for microMIPS JALX. */
15791 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15792 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15797 if (fix_bad_cross_mode_jump_p (fixP
))
15798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15799 _("jump to a symbol in another ISA mode"));
15800 else if (fix_bad_same_mode_jalx_p (fixP
))
15801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15802 _("JALX to a symbol in the same ISA mode"));
15803 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15805 _("jump to misaligned address (0x%lx)"),
15806 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15807 + fixP
->fx_offset
));
15808 else if (HAVE_IN_PLACE_ADDENDS
15809 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15811 _("cannot encode misaligned addend "
15812 "in the relocatable field (0x%lx)"),
15813 (long) fixP
->fx_offset
);
15815 /* Fall through. */
15817 case BFD_RELOC_MIPS_SHIFT5
:
15818 case BFD_RELOC_MIPS_SHIFT6
:
15819 case BFD_RELOC_MIPS_GOT_DISP
:
15820 case BFD_RELOC_MIPS_GOT_PAGE
:
15821 case BFD_RELOC_MIPS_GOT_OFST
:
15822 case BFD_RELOC_MIPS_SUB
:
15823 case BFD_RELOC_MIPS_INSERT_A
:
15824 case BFD_RELOC_MIPS_INSERT_B
:
15825 case BFD_RELOC_MIPS_DELETE
:
15826 case BFD_RELOC_MIPS_HIGHEST
:
15827 case BFD_RELOC_MIPS_HIGHER
:
15828 case BFD_RELOC_MIPS_SCN_DISP
:
15829 case BFD_RELOC_MIPS_REL16
:
15830 case BFD_RELOC_MIPS_RELGOT
:
15831 case BFD_RELOC_MIPS_JALR
:
15832 case BFD_RELOC_HI16
:
15833 case BFD_RELOC_HI16_S
:
15834 case BFD_RELOC_LO16
:
15835 case BFD_RELOC_GPREL16
:
15836 case BFD_RELOC_MIPS_LITERAL
:
15837 case BFD_RELOC_MIPS_CALL16
:
15838 case BFD_RELOC_MIPS_GOT16
:
15839 case BFD_RELOC_GPREL32
:
15840 case BFD_RELOC_MIPS_GOT_HI16
:
15841 case BFD_RELOC_MIPS_GOT_LO16
:
15842 case BFD_RELOC_MIPS_CALL_HI16
:
15843 case BFD_RELOC_MIPS_CALL_LO16
:
15844 case BFD_RELOC_HI16_S_PCREL
:
15845 case BFD_RELOC_LO16_PCREL
:
15846 case BFD_RELOC_MIPS16_GPREL
:
15847 case BFD_RELOC_MIPS16_GOT16
:
15848 case BFD_RELOC_MIPS16_CALL16
:
15849 case BFD_RELOC_MIPS16_HI16
:
15850 case BFD_RELOC_MIPS16_HI16_S
:
15851 case BFD_RELOC_MIPS16_LO16
:
15852 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15853 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15854 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15855 case BFD_RELOC_MICROMIPS_SUB
:
15856 case BFD_RELOC_MICROMIPS_HIGHEST
:
15857 case BFD_RELOC_MICROMIPS_HIGHER
:
15858 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15859 case BFD_RELOC_MICROMIPS_JALR
:
15860 case BFD_RELOC_MICROMIPS_HI16
:
15861 case BFD_RELOC_MICROMIPS_HI16_S
:
15862 case BFD_RELOC_MICROMIPS_LO16
:
15863 case BFD_RELOC_MICROMIPS_GPREL16
:
15864 case BFD_RELOC_MICROMIPS_LITERAL
:
15865 case BFD_RELOC_MICROMIPS_CALL16
:
15866 case BFD_RELOC_MICROMIPS_GOT16
:
15867 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15868 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15869 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15870 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15871 case BFD_RELOC_MIPS_EH
:
15876 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15878 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15879 if (mips16_reloc_p (fixP
->fx_r_type
))
15880 insn
|= mips16_immed_extend (value
, 16);
15882 insn
|= (value
& 0xffff);
15883 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15887 _("unsupported constant in relocation"));
15892 /* This is handled like BFD_RELOC_32, but we output a sign
15893 extended value if we are only 32 bits. */
15896 if (8 <= sizeof (valueT
))
15897 md_number_to_chars (buf
, *valP
, 8);
15902 if ((*valP
& 0x80000000) != 0)
15906 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15907 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15912 case BFD_RELOC_RVA
:
15914 case BFD_RELOC_32_PCREL
:
15917 /* If we are deleting this reloc entry, we must fill in the
15918 value now. This can happen if we have a .word which is not
15919 resolved when it appears but is later defined. */
15921 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15924 case BFD_RELOC_MIPS_21_PCREL_S2
:
15925 fix_validate_branch (fixP
, *valP
);
15926 if (!fixP
->fx_done
)
15929 if (*valP
+ 0x400000 <= 0x7fffff)
15931 insn
= read_insn (buf
);
15932 insn
|= (*valP
>> 2) & 0x1fffff;
15933 write_insn (buf
, insn
);
15936 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15937 _("branch out of range"));
15940 case BFD_RELOC_MIPS_26_PCREL_S2
:
15941 fix_validate_branch (fixP
, *valP
);
15942 if (!fixP
->fx_done
)
15945 if (*valP
+ 0x8000000 <= 0xfffffff)
15947 insn
= read_insn (buf
);
15948 insn
|= (*valP
>> 2) & 0x3ffffff;
15949 write_insn (buf
, insn
);
15952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15953 _("branch out of range"));
15956 case BFD_RELOC_MIPS_18_PCREL_S3
:
15957 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15959 _("PC-relative access using misaligned symbol (%lx)"),
15960 (long) S_GET_VALUE (fixP
->fx_addsy
));
15961 if ((fixP
->fx_offset
& 0x7) != 0)
15962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15963 _("PC-relative access using misaligned offset (%lx)"),
15964 (long) fixP
->fx_offset
);
15965 if (!fixP
->fx_done
)
15968 if (*valP
+ 0x100000 <= 0x1fffff)
15970 insn
= read_insn (buf
);
15971 insn
|= (*valP
>> 3) & 0x3ffff;
15972 write_insn (buf
, insn
);
15975 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15976 _("PC-relative access out of range"));
15979 case BFD_RELOC_MIPS_19_PCREL_S2
:
15980 if ((*valP
& 0x3) != 0)
15981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15982 _("PC-relative access to misaligned address (%lx)"),
15984 if (!fixP
->fx_done
)
15987 if (*valP
+ 0x100000 <= 0x1fffff)
15989 insn
= read_insn (buf
);
15990 insn
|= (*valP
>> 2) & 0x7ffff;
15991 write_insn (buf
, insn
);
15994 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15995 _("PC-relative access out of range"));
15998 case BFD_RELOC_16_PCREL_S2
:
15999 fix_validate_branch (fixP
, *valP
);
16001 /* We need to save the bits in the instruction since fixup_segment()
16002 might be deleting the relocation entry (i.e., a branch within
16003 the current segment). */
16004 if (! fixP
->fx_done
)
16007 /* Update old instruction data. */
16008 insn
= read_insn (buf
);
16010 if (*valP
+ 0x20000 <= 0x3ffff)
16012 insn
|= (*valP
>> 2) & 0xffff;
16013 write_insn (buf
, insn
);
16015 else if (fixP
->fx_tcbit2
16017 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16018 && (fixP
->fx_frag
->fr_address
16019 < text_section
->vma
+ bfd_get_section_size (text_section
))
16020 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16021 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16022 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16024 /* The branch offset is too large. If this is an
16025 unconditional branch, and we are not generating PIC code,
16026 we can convert it to an absolute jump instruction. */
16027 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16028 insn
= 0x0c000000; /* jal */
16030 insn
= 0x08000000; /* j */
16031 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16033 fixP
->fx_addsy
= section_symbol (text_section
);
16034 *valP
+= md_pcrel_from (fixP
);
16035 write_insn (buf
, insn
);
16039 /* If we got here, we have branch-relaxation disabled,
16040 and there's nothing we can do to fix this instruction
16041 without turning it into a longer sequence. */
16042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16043 _("branch out of range"));
16047 case BFD_RELOC_MIPS16_16_PCREL_S1
:
16048 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16049 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16050 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16051 gas_assert (!fixP
->fx_done
);
16052 if (fix_bad_cross_mode_branch_p (fixP
))
16053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16054 _("branch to a symbol in another ISA mode"));
16055 else if (fixP
->fx_addsy
16056 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
16057 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
16058 && (fixP
->fx_offset
& 0x1) != 0)
16059 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16060 _("branch to misaligned address (0x%lx)"),
16061 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
16062 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
16063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16064 _("cannot encode misaligned addend "
16065 "in the relocatable field (0x%lx)"),
16066 (long) fixP
->fx_offset
);
16069 case BFD_RELOC_VTABLE_INHERIT
:
16072 && !S_IS_DEFINED (fixP
->fx_addsy
)
16073 && !S_IS_WEAK (fixP
->fx_addsy
))
16074 S_SET_WEAK (fixP
->fx_addsy
);
16077 case BFD_RELOC_NONE
:
16078 case BFD_RELOC_VTABLE_ENTRY
:
16086 /* Remember value for tc_gen_reloc. */
16087 fixP
->fx_addnumber
= *valP
;
16097 c
= get_symbol_name (&name
);
16098 p
= (symbolS
*) symbol_find_or_make (name
);
16099 (void) restore_line_pointer (c
);
16103 /* Align the current frag to a given power of two. If a particular
16104 fill byte should be used, FILL points to an integer that contains
16105 that byte, otherwise FILL is null.
16107 This function used to have the comment:
16109 The MIPS assembler also automatically adjusts any preceding label.
16111 The implementation therefore applied the adjustment to a maximum of
16112 one label. However, other label adjustments are applied to batches
16113 of labels, and adjusting just one caused problems when new labels
16114 were added for the sake of debugging or unwind information.
16115 We therefore adjust all preceding labels (given as LABELS) instead. */
16118 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16120 mips_emit_delays ();
16121 mips_record_compressed_mode ();
16122 if (fill
== NULL
&& subseg_text_p (now_seg
))
16123 frag_align_code (to
, 0);
16125 frag_align (to
, fill
? *fill
: 0, 0);
16126 record_alignment (now_seg
, to
);
16127 mips_move_labels (labels
, FALSE
);
16130 /* Align to a given power of two. .align 0 turns off the automatic
16131 alignment used by the data creating pseudo-ops. */
16134 s_align (int x ATTRIBUTE_UNUSED
)
16136 int temp
, fill_value
, *fill_ptr
;
16137 long max_alignment
= 28;
16139 /* o Note that the assembler pulls down any immediately preceding label
16140 to the aligned address.
16141 o It's not documented but auto alignment is reinstated by
16142 a .align pseudo instruction.
16143 o Note also that after auto alignment is turned off the mips assembler
16144 issues an error on attempt to assemble an improperly aligned data item.
16147 temp
= get_absolute_expression ();
16148 if (temp
> max_alignment
)
16149 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16152 as_warn (_("alignment negative, 0 assumed"));
16155 if (*input_line_pointer
== ',')
16157 ++input_line_pointer
;
16158 fill_value
= get_absolute_expression ();
16159 fill_ptr
= &fill_value
;
16165 segment_info_type
*si
= seg_info (now_seg
);
16166 struct insn_label_list
*l
= si
->label_list
;
16167 /* Auto alignment should be switched on by next section change. */
16169 mips_align (temp
, fill_ptr
, l
);
16176 demand_empty_rest_of_line ();
16180 s_change_sec (int sec
)
16184 /* The ELF backend needs to know that we are changing sections, so
16185 that .previous works correctly. We could do something like check
16186 for an obj_section_change_hook macro, but that might be confusing
16187 as it would not be appropriate to use it in the section changing
16188 functions in read.c, since obj-elf.c intercepts those. FIXME:
16189 This should be cleaner, somehow. */
16190 obj_elf_section_change_hook ();
16192 mips_emit_delays ();
16203 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16204 demand_empty_rest_of_line ();
16208 seg
= subseg_new (RDATA_SECTION_NAME
,
16209 (subsegT
) get_absolute_expression ());
16210 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16211 | SEC_READONLY
| SEC_RELOC
16213 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16214 record_alignment (seg
, 4);
16215 demand_empty_rest_of_line ();
16219 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16220 bfd_set_section_flags (stdoutput
, seg
,
16221 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16222 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16223 record_alignment (seg
, 4);
16224 demand_empty_rest_of_line ();
16228 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16229 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16230 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16231 record_alignment (seg
, 4);
16232 demand_empty_rest_of_line ();
16240 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16243 char *section_name
;
16248 int section_entry_size
;
16249 int section_alignment
;
16251 saved_ilp
= input_line_pointer
;
16252 endc
= get_symbol_name (§ion_name
);
16253 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16255 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16257 /* Do we have .section Name<,"flags">? */
16258 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16260 /* Just after name is now '\0'. */
16261 (void) restore_line_pointer (endc
);
16262 input_line_pointer
= saved_ilp
;
16263 obj_elf_section (ignore
);
16267 section_name
= xstrdup (section_name
);
16268 c
= restore_line_pointer (endc
);
16270 input_line_pointer
++;
16272 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16274 section_type
= get_absolute_expression ();
16278 if (*input_line_pointer
++ == ',')
16279 section_flag
= get_absolute_expression ();
16283 if (*input_line_pointer
++ == ',')
16284 section_entry_size
= get_absolute_expression ();
16286 section_entry_size
= 0;
16288 if (*input_line_pointer
++ == ',')
16289 section_alignment
= get_absolute_expression ();
16291 section_alignment
= 0;
16293 /* FIXME: really ignore? */
16294 (void) section_alignment
;
16296 /* When using the generic form of .section (as implemented by obj-elf.c),
16297 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16298 traditionally had to fall back on the more common @progbits instead.
16300 There's nothing really harmful in this, since bfd will correct
16301 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16302 means that, for backwards compatibility, the special_section entries
16303 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16305 Even so, we shouldn't force users of the MIPS .section syntax to
16306 incorrectly label the sections as SHT_PROGBITS. The best compromise
16307 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16308 generic type-checking code. */
16309 if (section_type
== SHT_MIPS_DWARF
)
16310 section_type
= SHT_PROGBITS
;
16312 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
16313 section_entry_size
, 0, 0, 0);
16315 if (now_seg
->name
!= section_name
)
16316 free (section_name
);
16320 mips_enable_auto_align (void)
16326 s_cons (int log_size
)
16328 segment_info_type
*si
= seg_info (now_seg
);
16329 struct insn_label_list
*l
= si
->label_list
;
16331 mips_emit_delays ();
16332 if (log_size
> 0 && auto_align
)
16333 mips_align (log_size
, 0, l
);
16334 cons (1 << log_size
);
16335 mips_clear_insn_labels ();
16339 s_float_cons (int type
)
16341 segment_info_type
*si
= seg_info (now_seg
);
16342 struct insn_label_list
*l
= si
->label_list
;
16344 mips_emit_delays ();
16349 mips_align (3, 0, l
);
16351 mips_align (2, 0, l
);
16355 mips_clear_insn_labels ();
16358 /* Handle .globl. We need to override it because on Irix 5 you are
16361 where foo is an undefined symbol, to mean that foo should be
16362 considered to be the address of a function. */
16365 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16374 c
= get_symbol_name (&name
);
16375 symbolP
= symbol_find_or_make (name
);
16376 S_SET_EXTERNAL (symbolP
);
16378 *input_line_pointer
= c
;
16379 SKIP_WHITESPACE_AFTER_NAME ();
16381 /* On Irix 5, every global symbol that is not explicitly labelled as
16382 being a function is apparently labelled as being an object. */
16385 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16386 && (*input_line_pointer
!= ','))
16391 c
= get_symbol_name (&secname
);
16392 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16394 as_bad (_("%s: no such section"), secname
);
16395 (void) restore_line_pointer (c
);
16397 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16398 flag
= BSF_FUNCTION
;
16401 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16403 c
= *input_line_pointer
;
16406 input_line_pointer
++;
16407 SKIP_WHITESPACE ();
16408 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16414 demand_empty_rest_of_line ();
16418 s_option (int x ATTRIBUTE_UNUSED
)
16423 c
= get_symbol_name (&opt
);
16427 /* FIXME: What does this mean? */
16429 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16433 i
= atoi (opt
+ 3);
16434 if (i
!= 0 && i
!= 2)
16435 as_bad (_(".option pic%d not supported"), i
);
16436 else if (mips_pic
== VXWORKS_PIC
)
16437 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16442 mips_pic
= SVR4_PIC
;
16443 mips_abicalls
= TRUE
;
16446 if (mips_pic
== SVR4_PIC
)
16448 if (g_switch_seen
&& g_switch_value
!= 0)
16449 as_warn (_("-G may not be used with SVR4 PIC code"));
16450 g_switch_value
= 0;
16451 bfd_set_gp_size (stdoutput
, 0);
16455 as_warn (_("unrecognized option \"%s\""), opt
);
16457 (void) restore_line_pointer (c
);
16458 demand_empty_rest_of_line ();
16461 /* This structure is used to hold a stack of .set values. */
16463 struct mips_option_stack
16465 struct mips_option_stack
*next
;
16466 struct mips_set_options options
;
16469 static struct mips_option_stack
*mips_opts_stack
;
16471 /* Return status for .set/.module option handling. */
16473 enum code_option_type
16475 /* Unrecognized option. */
16476 OPTION_TYPE_BAD
= -1,
16478 /* Ordinary option. */
16479 OPTION_TYPE_NORMAL
,
16481 /* ISA changing option. */
16485 /* Handle common .set/.module options. Return status indicating option
16488 static enum code_option_type
16489 parse_code_option (char * name
)
16491 bfd_boolean isa_set
= FALSE
;
16492 const struct mips_ase
*ase
;
16494 if (strncmp (name
, "at=", 3) == 0)
16496 char *s
= name
+ 3;
16498 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16499 as_bad (_("unrecognized register name `%s'"), s
);
16501 else if (strcmp (name
, "at") == 0)
16502 mips_opts
.at
= ATREG
;
16503 else if (strcmp (name
, "noat") == 0)
16504 mips_opts
.at
= ZERO
;
16505 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16506 mips_opts
.nomove
= 0;
16507 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16508 mips_opts
.nomove
= 1;
16509 else if (strcmp (name
, "bopt") == 0)
16510 mips_opts
.nobopt
= 0;
16511 else if (strcmp (name
, "nobopt") == 0)
16512 mips_opts
.nobopt
= 1;
16513 else if (strcmp (name
, "gp=32") == 0)
16515 else if (strcmp (name
, "gp=64") == 0)
16517 else if (strcmp (name
, "fp=32") == 0)
16519 else if (strcmp (name
, "fp=xx") == 0)
16521 else if (strcmp (name
, "fp=64") == 0)
16523 else if (strcmp (name
, "softfloat") == 0)
16524 mips_opts
.soft_float
= 1;
16525 else if (strcmp (name
, "hardfloat") == 0)
16526 mips_opts
.soft_float
= 0;
16527 else if (strcmp (name
, "singlefloat") == 0)
16528 mips_opts
.single_float
= 1;
16529 else if (strcmp (name
, "doublefloat") == 0)
16530 mips_opts
.single_float
= 0;
16531 else if (strcmp (name
, "nooddspreg") == 0)
16532 mips_opts
.oddspreg
= 0;
16533 else if (strcmp (name
, "oddspreg") == 0)
16534 mips_opts
.oddspreg
= 1;
16535 else if (strcmp (name
, "mips16") == 0
16536 || strcmp (name
, "MIPS-16") == 0)
16537 mips_opts
.mips16
= 1;
16538 else if (strcmp (name
, "nomips16") == 0
16539 || strcmp (name
, "noMIPS-16") == 0)
16540 mips_opts
.mips16
= 0;
16541 else if (strcmp (name
, "micromips") == 0)
16542 mips_opts
.micromips
= 1;
16543 else if (strcmp (name
, "nomicromips") == 0)
16544 mips_opts
.micromips
= 0;
16545 else if (name
[0] == 'n'
16547 && (ase
= mips_lookup_ase (name
+ 2)))
16548 mips_set_ase (ase
, &mips_opts
, FALSE
);
16549 else if ((ase
= mips_lookup_ase (name
)))
16550 mips_set_ase (ase
, &mips_opts
, TRUE
);
16551 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16553 /* Permit the user to change the ISA and architecture on the fly.
16554 Needless to say, misuse can cause serious problems. */
16555 if (strncmp (name
, "arch=", 5) == 0)
16557 const struct mips_cpu_info
*p
;
16559 p
= mips_parse_cpu ("internal use", name
+ 5);
16561 as_bad (_("unknown architecture %s"), name
+ 5);
16564 mips_opts
.arch
= p
->cpu
;
16565 mips_opts
.isa
= p
->isa
;
16567 mips_opts
.init_ase
= p
->ase
;
16570 else if (strncmp (name
, "mips", 4) == 0)
16572 const struct mips_cpu_info
*p
;
16574 p
= mips_parse_cpu ("internal use", name
);
16576 as_bad (_("unknown ISA level %s"), name
+ 4);
16579 mips_opts
.arch
= p
->cpu
;
16580 mips_opts
.isa
= p
->isa
;
16582 mips_opts
.init_ase
= p
->ase
;
16586 as_bad (_("unknown ISA or architecture %s"), name
);
16588 else if (strcmp (name
, "autoextend") == 0)
16589 mips_opts
.noautoextend
= 0;
16590 else if (strcmp (name
, "noautoextend") == 0)
16591 mips_opts
.noautoextend
= 1;
16592 else if (strcmp (name
, "insn32") == 0)
16593 mips_opts
.insn32
= TRUE
;
16594 else if (strcmp (name
, "noinsn32") == 0)
16595 mips_opts
.insn32
= FALSE
;
16596 else if (strcmp (name
, "sym32") == 0)
16597 mips_opts
.sym32
= TRUE
;
16598 else if (strcmp (name
, "nosym32") == 0)
16599 mips_opts
.sym32
= FALSE
;
16601 return OPTION_TYPE_BAD
;
16603 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16606 /* Handle the .set pseudo-op. */
16609 s_mipsset (int x ATTRIBUTE_UNUSED
)
16611 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16612 char *name
= input_line_pointer
, ch
;
16614 file_mips_check_options ();
16616 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16617 ++input_line_pointer
;
16618 ch
= *input_line_pointer
;
16619 *input_line_pointer
= '\0';
16621 if (strchr (name
, ','))
16623 /* Generic ".set" directive; use the generic handler. */
16624 *input_line_pointer
= ch
;
16625 input_line_pointer
= name
;
16630 if (strcmp (name
, "reorder") == 0)
16632 if (mips_opts
.noreorder
)
16635 else if (strcmp (name
, "noreorder") == 0)
16637 if (!mips_opts
.noreorder
)
16638 start_noreorder ();
16640 else if (strcmp (name
, "macro") == 0)
16641 mips_opts
.warn_about_macros
= 0;
16642 else if (strcmp (name
, "nomacro") == 0)
16644 if (mips_opts
.noreorder
== 0)
16645 as_bad (_("`noreorder' must be set before `nomacro'"));
16646 mips_opts
.warn_about_macros
= 1;
16648 else if (strcmp (name
, "gp=default") == 0)
16649 mips_opts
.gp
= file_mips_opts
.gp
;
16650 else if (strcmp (name
, "fp=default") == 0)
16651 mips_opts
.fp
= file_mips_opts
.fp
;
16652 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16654 mips_opts
.isa
= file_mips_opts
.isa
;
16655 mips_opts
.arch
= file_mips_opts
.arch
;
16656 mips_opts
.init_ase
= file_mips_opts
.init_ase
;
16657 mips_opts
.gp
= file_mips_opts
.gp
;
16658 mips_opts
.fp
= file_mips_opts
.fp
;
16660 else if (strcmp (name
, "push") == 0)
16662 struct mips_option_stack
*s
;
16664 s
= XNEW (struct mips_option_stack
);
16665 s
->next
= mips_opts_stack
;
16666 s
->options
= mips_opts
;
16667 mips_opts_stack
= s
;
16669 else if (strcmp (name
, "pop") == 0)
16671 struct mips_option_stack
*s
;
16673 s
= mips_opts_stack
;
16675 as_bad (_(".set pop with no .set push"));
16678 /* If we're changing the reorder mode we need to handle
16679 delay slots correctly. */
16680 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16681 start_noreorder ();
16682 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16685 mips_opts
= s
->options
;
16686 mips_opts_stack
= s
->next
;
16692 type
= parse_code_option (name
);
16693 if (type
== OPTION_TYPE_BAD
)
16694 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16697 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16698 registers based on what is supported by the arch/cpu. */
16699 if (type
== OPTION_TYPE_ISA
)
16701 switch (mips_opts
.isa
)
16706 /* MIPS I cannot support FPXX. */
16708 /* fall-through. */
16715 if (mips_opts
.fp
!= 0)
16731 if (mips_opts
.fp
!= 0)
16733 if (mips_opts
.arch
== CPU_R5900
)
16740 as_bad (_("unknown ISA level %s"), name
+ 4);
16745 mips_check_options (&mips_opts
, FALSE
);
16747 mips_check_isa_supports_ases ();
16748 *input_line_pointer
= ch
;
16749 demand_empty_rest_of_line ();
16752 /* Handle the .module pseudo-op. */
16755 s_module (int ignore ATTRIBUTE_UNUSED
)
16757 char *name
= input_line_pointer
, ch
;
16759 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16760 ++input_line_pointer
;
16761 ch
= *input_line_pointer
;
16762 *input_line_pointer
= '\0';
16764 if (!file_mips_opts_checked
)
16766 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16767 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16769 /* Update module level settings from mips_opts. */
16770 file_mips_opts
= mips_opts
;
16773 as_bad (_(".module is not permitted after generating code"));
16775 *input_line_pointer
= ch
;
16776 demand_empty_rest_of_line ();
16779 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16780 .option pic2. It means to generate SVR4 PIC calls. */
16783 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16785 mips_pic
= SVR4_PIC
;
16786 mips_abicalls
= TRUE
;
16788 if (g_switch_seen
&& g_switch_value
!= 0)
16789 as_warn (_("-G may not be used with SVR4 PIC code"));
16790 g_switch_value
= 0;
16792 bfd_set_gp_size (stdoutput
, 0);
16793 demand_empty_rest_of_line ();
16796 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16797 PIC code. It sets the $gp register for the function based on the
16798 function address, which is in the register named in the argument.
16799 This uses a relocation against _gp_disp, which is handled specially
16800 by the linker. The result is:
16801 lui $gp,%hi(_gp_disp)
16802 addiu $gp,$gp,%lo(_gp_disp)
16803 addu $gp,$gp,.cpload argument
16804 The .cpload argument is normally $25 == $t9.
16806 The -mno-shared option changes this to:
16807 lui $gp,%hi(__gnu_local_gp)
16808 addiu $gp,$gp,%lo(__gnu_local_gp)
16809 and the argument is ignored. This saves an instruction, but the
16810 resulting code is not position independent; it uses an absolute
16811 address for __gnu_local_gp. Thus code assembled with -mno-shared
16812 can go into an ordinary executable, but not into a shared library. */
16815 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16821 file_mips_check_options ();
16823 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16824 .cpload is ignored. */
16825 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16831 if (mips_opts
.mips16
)
16833 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16834 ignore_rest_of_line ();
16838 /* .cpload should be in a .set noreorder section. */
16839 if (mips_opts
.noreorder
== 0)
16840 as_warn (_(".cpload not in noreorder section"));
16842 reg
= tc_get_register (0);
16844 /* If we need to produce a 64-bit address, we are better off using
16845 the default instruction sequence. */
16846 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16848 ex
.X_op
= O_symbol
;
16849 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16851 ex
.X_op_symbol
= NULL
;
16852 ex
.X_add_number
= 0;
16854 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16855 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16857 mips_mark_labels ();
16858 mips_assembling_insn
= TRUE
;
16861 macro_build_lui (&ex
, mips_gp_register
);
16862 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16863 mips_gp_register
, BFD_RELOC_LO16
);
16865 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16866 mips_gp_register
, reg
);
16869 mips_assembling_insn
= FALSE
;
16870 demand_empty_rest_of_line ();
16873 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16874 .cpsetup $reg1, offset|$reg2, label
16876 If offset is given, this results in:
16877 sd $gp, offset($sp)
16878 lui $gp, %hi(%neg(%gp_rel(label)))
16879 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16880 daddu $gp, $gp, $reg1
16882 If $reg2 is given, this results in:
16884 lui $gp, %hi(%neg(%gp_rel(label)))
16885 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16886 daddu $gp, $gp, $reg1
16887 $reg1 is normally $25 == $t9.
16889 The -mno-shared option replaces the last three instructions with
16891 addiu $gp,$gp,%lo(_gp) */
16894 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16896 expressionS ex_off
;
16897 expressionS ex_sym
;
16900 file_mips_check_options ();
16902 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16903 We also need NewABI support. */
16904 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16910 if (mips_opts
.mips16
)
16912 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16913 ignore_rest_of_line ();
16917 reg1
= tc_get_register (0);
16918 SKIP_WHITESPACE ();
16919 if (*input_line_pointer
!= ',')
16921 as_bad (_("missing argument separator ',' for .cpsetup"));
16925 ++input_line_pointer
;
16926 SKIP_WHITESPACE ();
16927 if (*input_line_pointer
== '$')
16929 mips_cpreturn_register
= tc_get_register (0);
16930 mips_cpreturn_offset
= -1;
16934 mips_cpreturn_offset
= get_absolute_expression ();
16935 mips_cpreturn_register
= -1;
16937 SKIP_WHITESPACE ();
16938 if (*input_line_pointer
!= ',')
16940 as_bad (_("missing argument separator ',' for .cpsetup"));
16944 ++input_line_pointer
;
16945 SKIP_WHITESPACE ();
16946 expression (&ex_sym
);
16948 mips_mark_labels ();
16949 mips_assembling_insn
= TRUE
;
16952 if (mips_cpreturn_register
== -1)
16954 ex_off
.X_op
= O_constant
;
16955 ex_off
.X_add_symbol
= NULL
;
16956 ex_off
.X_op_symbol
= NULL
;
16957 ex_off
.X_add_number
= mips_cpreturn_offset
;
16959 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16960 BFD_RELOC_LO16
, SP
);
16963 move_register (mips_cpreturn_register
, mips_gp_register
);
16965 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16967 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16968 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16971 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16972 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16973 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16975 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16976 mips_gp_register
, reg1
);
16982 ex
.X_op
= O_symbol
;
16983 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16984 ex
.X_op_symbol
= NULL
;
16985 ex
.X_add_number
= 0;
16987 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16988 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16990 macro_build_lui (&ex
, mips_gp_register
);
16991 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16992 mips_gp_register
, BFD_RELOC_LO16
);
16997 mips_assembling_insn
= FALSE
;
16998 demand_empty_rest_of_line ();
17002 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17004 file_mips_check_options ();
17006 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17007 .cplocal is ignored. */
17008 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17014 if (mips_opts
.mips16
)
17016 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17017 ignore_rest_of_line ();
17021 mips_gp_register
= tc_get_register (0);
17022 demand_empty_rest_of_line ();
17025 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17026 offset from $sp. The offset is remembered, and after making a PIC
17027 call $gp is restored from that location. */
17030 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17034 file_mips_check_options ();
17036 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17037 .cprestore is ignored. */
17038 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17044 if (mips_opts
.mips16
)
17046 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17047 ignore_rest_of_line ();
17051 mips_cprestore_offset
= get_absolute_expression ();
17052 mips_cprestore_valid
= 1;
17054 ex
.X_op
= O_constant
;
17055 ex
.X_add_symbol
= NULL
;
17056 ex
.X_op_symbol
= NULL
;
17057 ex
.X_add_number
= mips_cprestore_offset
;
17059 mips_mark_labels ();
17060 mips_assembling_insn
= TRUE
;
17063 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17064 SP
, HAVE_64BIT_ADDRESSES
);
17067 mips_assembling_insn
= FALSE
;
17068 demand_empty_rest_of_line ();
17071 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17072 was given in the preceding .cpsetup, it results in:
17073 ld $gp, offset($sp)
17075 If a register $reg2 was given there, it results in:
17076 or $gp, $reg2, $0 */
17079 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17083 file_mips_check_options ();
17085 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17086 We also need NewABI support. */
17087 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17093 if (mips_opts
.mips16
)
17095 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17096 ignore_rest_of_line ();
17100 mips_mark_labels ();
17101 mips_assembling_insn
= TRUE
;
17104 if (mips_cpreturn_register
== -1)
17106 ex
.X_op
= O_constant
;
17107 ex
.X_add_symbol
= NULL
;
17108 ex
.X_op_symbol
= NULL
;
17109 ex
.X_add_number
= mips_cpreturn_offset
;
17111 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17114 move_register (mips_gp_register
, mips_cpreturn_register
);
17118 mips_assembling_insn
= FALSE
;
17119 demand_empty_rest_of_line ();
17122 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17123 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17124 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17125 debug information or MIPS16 TLS. */
17128 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17129 bfd_reloc_code_real_type rtype
)
17136 if (ex
.X_op
!= O_symbol
)
17138 as_bad (_("unsupported use of %s"), dirstr
);
17139 ignore_rest_of_line ();
17142 p
= frag_more (bytes
);
17143 md_number_to_chars (p
, 0, bytes
);
17144 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17145 demand_empty_rest_of_line ();
17146 mips_clear_insn_labels ();
17149 /* Handle .dtprelword. */
17152 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17154 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17157 /* Handle .dtpreldword. */
17160 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17162 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17165 /* Handle .tprelword. */
17168 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17170 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17173 /* Handle .tpreldword. */
17176 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17178 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17181 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17182 code. It sets the offset to use in gp_rel relocations. */
17185 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17187 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17188 We also need NewABI support. */
17189 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17195 mips_gprel_offset
= get_absolute_expression ();
17197 demand_empty_rest_of_line ();
17200 /* Handle the .gpword pseudo-op. This is used when generating PIC
17201 code. It generates a 32 bit GP relative reloc. */
17204 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17206 segment_info_type
*si
;
17207 struct insn_label_list
*l
;
17211 /* When not generating PIC code, this is treated as .word. */
17212 if (mips_pic
!= SVR4_PIC
)
17218 si
= seg_info (now_seg
);
17219 l
= si
->label_list
;
17220 mips_emit_delays ();
17222 mips_align (2, 0, l
);
17225 mips_clear_insn_labels ();
17227 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17229 as_bad (_("unsupported use of .gpword"));
17230 ignore_rest_of_line ();
17234 md_number_to_chars (p
, 0, 4);
17235 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17236 BFD_RELOC_GPREL32
);
17238 demand_empty_rest_of_line ();
17242 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17244 segment_info_type
*si
;
17245 struct insn_label_list
*l
;
17249 /* When not generating PIC code, this is treated as .dword. */
17250 if (mips_pic
!= SVR4_PIC
)
17256 si
= seg_info (now_seg
);
17257 l
= si
->label_list
;
17258 mips_emit_delays ();
17260 mips_align (3, 0, l
);
17263 mips_clear_insn_labels ();
17265 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17267 as_bad (_("unsupported use of .gpdword"));
17268 ignore_rest_of_line ();
17272 md_number_to_chars (p
, 0, 8);
17273 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17274 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17276 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17277 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17278 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17280 demand_empty_rest_of_line ();
17283 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17284 tables. It generates a R_MIPS_EH reloc. */
17287 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17292 mips_emit_delays ();
17295 mips_clear_insn_labels ();
17297 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17299 as_bad (_("unsupported use of .ehword"));
17300 ignore_rest_of_line ();
17304 md_number_to_chars (p
, 0, 4);
17305 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17306 BFD_RELOC_32_PCREL
);
17308 demand_empty_rest_of_line ();
17311 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17312 tables in SVR4 PIC code. */
17315 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17319 file_mips_check_options ();
17321 /* This is ignored when not generating SVR4 PIC code. */
17322 if (mips_pic
!= SVR4_PIC
)
17328 mips_mark_labels ();
17329 mips_assembling_insn
= TRUE
;
17331 /* Add $gp to the register named as an argument. */
17333 reg
= tc_get_register (0);
17334 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17337 mips_assembling_insn
= FALSE
;
17338 demand_empty_rest_of_line ();
17341 /* Handle the .insn pseudo-op. This marks instruction labels in
17342 mips16/micromips mode. This permits the linker to handle them specially,
17343 such as generating jalx instructions when needed. We also make
17344 them odd for the duration of the assembly, in order to generate the
17345 right sort of code. We will make them even in the adjust_symtab
17346 routine, while leaving them marked. This is convenient for the
17347 debugger and the disassembler. The linker knows to make them odd
17351 s_insn (int ignore ATTRIBUTE_UNUSED
)
17353 file_mips_check_options ();
17354 file_ase_mips16
|= mips_opts
.mips16
;
17355 file_ase_micromips
|= mips_opts
.micromips
;
17357 mips_mark_labels ();
17359 demand_empty_rest_of_line ();
17362 /* Handle the .nan pseudo-op. */
17365 s_nan (int ignore ATTRIBUTE_UNUSED
)
17367 static const char str_legacy
[] = "legacy";
17368 static const char str_2008
[] = "2008";
17371 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17373 if (i
== sizeof (str_2008
) - 1
17374 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17376 else if (i
== sizeof (str_legacy
) - 1
17377 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17379 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17382 as_bad (_("`%s' does not support legacy NaN"),
17383 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17386 as_bad (_("bad .nan directive"));
17388 input_line_pointer
+= i
;
17389 demand_empty_rest_of_line ();
17392 /* Handle a .stab[snd] directive. Ideally these directives would be
17393 implemented in a transparent way, so that removing them would not
17394 have any effect on the generated instructions. However, s_stab
17395 internally changes the section, so in practice we need to decide
17396 now whether the preceding label marks compressed code. We do not
17397 support changing the compression mode of a label after a .stab*
17398 directive, such as in:
17404 so the current mode wins. */
17407 s_mips_stab (int type
)
17409 file_mips_check_options ();
17410 mips_mark_labels ();
17414 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17417 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17424 c
= get_symbol_name (&name
);
17425 symbolP
= symbol_find_or_make (name
);
17426 S_SET_WEAK (symbolP
);
17427 *input_line_pointer
= c
;
17429 SKIP_WHITESPACE_AFTER_NAME ();
17431 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17433 if (S_IS_DEFINED (symbolP
))
17435 as_bad (_("ignoring attempt to redefine symbol %s"),
17436 S_GET_NAME (symbolP
));
17437 ignore_rest_of_line ();
17441 if (*input_line_pointer
== ',')
17443 ++input_line_pointer
;
17444 SKIP_WHITESPACE ();
17448 if (exp
.X_op
!= O_symbol
)
17450 as_bad (_("bad .weakext directive"));
17451 ignore_rest_of_line ();
17454 symbol_set_value_expression (symbolP
, &exp
);
17457 demand_empty_rest_of_line ();
17460 /* Parse a register string into a number. Called from the ECOFF code
17461 to parse .frame. The argument is non-zero if this is the frame
17462 register, so that we can record it in mips_frame_reg. */
17465 tc_get_register (int frame
)
17469 SKIP_WHITESPACE ();
17470 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17474 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17475 mips_frame_reg_valid
= 1;
17476 mips_cprestore_valid
= 0;
17482 md_section_align (asection
*seg
, valueT addr
)
17484 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17486 /* We don't need to align ELF sections to the full alignment.
17487 However, Irix 5 may prefer that we align them at least to a 16
17488 byte boundary. We don't bother to align the sections if we
17489 are targeted for an embedded system. */
17490 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17495 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17498 /* Utility routine, called from above as well. If called while the
17499 input file is still being read, it's only an approximation. (For
17500 example, a symbol may later become defined which appeared to be
17501 undefined earlier.) */
17504 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17509 if (g_switch_value
> 0)
17511 const char *symname
;
17514 /* Find out whether this symbol can be referenced off the $gp
17515 register. It can be if it is smaller than the -G size or if
17516 it is in the .sdata or .sbss section. Certain symbols can
17517 not be referenced off the $gp, although it appears as though
17519 symname
= S_GET_NAME (sym
);
17520 if (symname
!= (const char *) NULL
17521 && (strcmp (symname
, "eprol") == 0
17522 || strcmp (symname
, "etext") == 0
17523 || strcmp (symname
, "_gp") == 0
17524 || strcmp (symname
, "edata") == 0
17525 || strcmp (symname
, "_fbss") == 0
17526 || strcmp (symname
, "_fdata") == 0
17527 || strcmp (symname
, "_ftext") == 0
17528 || strcmp (symname
, "end") == 0
17529 || strcmp (symname
, "_gp_disp") == 0))
17531 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17533 #ifndef NO_ECOFF_DEBUGGING
17534 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17535 && (symbol_get_obj (sym
)->ecoff_extern_size
17536 <= g_switch_value
))
17538 /* We must defer this decision until after the whole
17539 file has been read, since there might be a .extern
17540 after the first use of this symbol. */
17541 || (before_relaxing
17542 #ifndef NO_ECOFF_DEBUGGING
17543 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17545 && S_GET_VALUE (sym
) == 0)
17546 || (S_GET_VALUE (sym
) != 0
17547 && S_GET_VALUE (sym
) <= g_switch_value
)))
17551 const char *segname
;
17553 segname
= segment_name (S_GET_SEGMENT (sym
));
17554 gas_assert (strcmp (segname
, ".lit8") != 0
17555 && strcmp (segname
, ".lit4") != 0);
17556 change
= (strcmp (segname
, ".sdata") != 0
17557 && strcmp (segname
, ".sbss") != 0
17558 && strncmp (segname
, ".sdata.", 7) != 0
17559 && strncmp (segname
, ".sbss.", 6) != 0
17560 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17561 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17566 /* We are not optimizing for the $gp register. */
17571 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17574 pic_need_relax (symbolS
*sym
)
17578 /* Handle the case of a symbol equated to another symbol. */
17579 while (symbol_equated_reloc_p (sym
))
17583 /* It's possible to get a loop here in a badly written program. */
17584 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17590 if (symbol_section_p (sym
))
17593 symsec
= S_GET_SEGMENT (sym
);
17595 /* This must duplicate the test in adjust_reloc_syms. */
17596 return (!bfd_is_und_section (symsec
)
17597 && !bfd_is_abs_section (symsec
)
17598 && !bfd_is_com_section (symsec
)
17599 /* A global or weak symbol is treated as external. */
17600 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17603 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17604 convert a section-relative value VAL to the equivalent PC-relative
17608 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17609 offsetT val
, long stretch
)
17614 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17616 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17618 /* If the relax_marker of the symbol fragment differs from the
17619 relax_marker of this fragment, we have not yet adjusted the
17620 symbol fragment fr_address. We want to add in STRETCH in
17621 order to get a better estimate of the address. This
17622 particularly matters because of the shift bits. */
17623 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17627 /* Adjust stretch for any alignment frag. Note that if have
17628 been expanding the earlier code, the symbol may be
17629 defined in what appears to be an earlier frag. FIXME:
17630 This doesn't handle the fr_subtype field, which specifies
17631 a maximum number of bytes to skip when doing an
17633 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17635 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17638 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17640 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17649 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17651 /* The base address rules are complicated. The base address of
17652 a branch is the following instruction. The base address of a
17653 PC relative load or add is the instruction itself, but if it
17654 is in a delay slot (in which case it can not be extended) use
17655 the address of the instruction whose delay slot it is in. */
17656 if (pcrel_op
->include_isa_bit
)
17660 /* If we are currently assuming that this frag should be
17661 extended, then the current address is two bytes higher. */
17662 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17665 /* Ignore the low bit in the target, since it will be set
17666 for a text label. */
17669 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17671 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17674 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17679 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17680 extended opcode. SEC is the section the frag is in. */
17683 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17685 const struct mips_int_operand
*operand
;
17690 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17692 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17695 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17696 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17697 operand
= mips16_immed_operand (type
, FALSE
);
17698 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17699 || (operand
->root
.type
== OP_PCREL
17701 : !bfd_is_abs_section (symsec
)))
17704 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17706 if (operand
->root
.type
== OP_PCREL
)
17708 const struct mips_pcrel_operand
*pcrel_op
;
17711 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17714 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17715 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17717 /* If any of the shifted bits are set, we must use an extended
17718 opcode. If the address depends on the size of this
17719 instruction, this can lead to a loop, so we arrange to always
17720 use an extended opcode. */
17721 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17723 fragp
->fr_subtype
=
17724 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17728 /* If we are about to mark a frag as extended because the value
17729 is precisely the next value above maxtiny, then there is a
17730 chance of an infinite loop as in the following code:
17735 In this case when the la is extended, foo is 0x3fc bytes
17736 away, so the la can be shrunk, but then foo is 0x400 away, so
17737 the la must be extended. To avoid this loop, we mark the
17738 frag as extended if it was small, and is about to become
17739 extended with the next value above maxtiny. */
17740 maxtiny
= mips_int_operand_max (operand
);
17741 if (val
== maxtiny
+ (1 << operand
->shift
)
17742 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17744 fragp
->fr_subtype
=
17745 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17750 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17753 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17754 macro expansion. SEC is the section the frag is in. We only
17755 support PC-relative instructions (LA, DLA, LW, LD) here, in
17756 non-PIC code using 32-bit addressing. */
17759 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17761 const struct mips_pcrel_operand
*pcrel_op
;
17762 const struct mips_int_operand
*operand
;
17767 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17769 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17771 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17774 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17780 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17781 if (bfd_is_abs_section (symsec
))
17783 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17785 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17788 operand
= mips16_immed_operand (type
, TRUE
);
17789 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17790 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17791 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17793 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17800 /* Compute the length of a branch sequence, and adjust the
17801 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17802 worst-case length is computed, with UPDATE being used to indicate
17803 whether an unconditional (-1), branch-likely (+1) or regular (0)
17804 branch is to be computed. */
17806 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17808 bfd_boolean toofar
;
17812 && S_IS_DEFINED (fragp
->fr_symbol
)
17813 && !S_IS_WEAK (fragp
->fr_symbol
)
17814 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17819 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17821 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17825 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17828 /* If the symbol is not defined or it's in a different segment,
17829 we emit the long sequence. */
17832 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17834 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17835 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17836 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17837 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17838 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17844 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17847 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17849 /* Additional space for PIC loading of target address. */
17851 if (mips_opts
.isa
== ISA_MIPS1
)
17852 /* Additional space for $at-stabilizing nop. */
17856 /* If branch is conditional. */
17857 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17864 /* Get a FRAG's branch instruction delay slot size, either from the
17865 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17866 or SHORT_INSN_SIZE otherwise. */
17869 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17871 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17874 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17876 return short_insn_size
;
17879 /* Compute the length of a branch sequence, and adjust the
17880 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17881 worst-case length is computed, with UPDATE being used to indicate
17882 whether an unconditional (-1), or regular (0) branch is to be
17886 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17888 bfd_boolean insn32
= TRUE
;
17889 bfd_boolean nods
= TRUE
;
17890 bfd_boolean pic
= TRUE
;
17891 bfd_boolean al
= TRUE
;
17892 int short_insn_size
;
17893 bfd_boolean toofar
;
17898 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17899 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17900 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17901 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17903 short_insn_size
= insn32
? 4 : 2;
17906 && S_IS_DEFINED (fragp
->fr_symbol
)
17907 && !S_IS_WEAK (fragp
->fr_symbol
)
17908 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17913 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17914 /* Ignore the low bit in the target, since it will be set
17915 for a text label. */
17916 if ((val
& 1) != 0)
17919 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17923 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17926 /* If the symbol is not defined or it's in a different segment,
17927 we emit the long sequence. */
17930 if (fragp
&& update
17931 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17932 fragp
->fr_subtype
= (toofar
17933 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17934 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17939 bfd_boolean compact_known
= fragp
!= NULL
;
17940 bfd_boolean compact
= FALSE
;
17941 bfd_boolean uncond
;
17945 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17946 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17949 uncond
= update
< 0;
17951 /* If label is out of range, we turn branch <br>:
17953 <br> label # 4 bytes
17960 # compact && (!PIC || insn32)
17963 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17964 length
+= short_insn_size
;
17966 /* If assembling PIC code, we further turn:
17972 lw/ld at, %got(label)(gp) # 4 bytes
17973 d/addiu at, %lo(label) # 4 bytes
17974 jr/c at # 2/4 bytes
17977 length
+= 4 + short_insn_size
;
17979 /* Add an extra nop if the jump has no compact form and we need
17980 to fill the delay slot. */
17981 if ((!pic
|| al
) && nods
)
17983 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17984 : short_insn_size
);
17986 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17988 <brneg> 0f # 4 bytes
17989 nop # 2/4 bytes if !compact
17992 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17996 /* Add an extra nop to fill the delay slot. */
17997 gas_assert (fragp
);
17998 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
18004 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18005 bit accordingly. */
18008 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18010 bfd_boolean toofar
;
18013 && S_IS_DEFINED (fragp
->fr_symbol
)
18014 && !S_IS_WEAK (fragp
->fr_symbol
)
18015 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18021 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18022 /* Ignore the low bit in the target, since it will be set
18023 for a text label. */
18024 if ((val
& 1) != 0)
18027 /* Assume this is a 2-byte branch. */
18028 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18030 /* We try to avoid the infinite loop by not adding 2 more bytes for
18035 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18037 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18038 else if (type
== 'E')
18039 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18044 /* If the symbol is not defined or it's in a different segment,
18045 we emit a normal 32-bit branch. */
18048 if (fragp
&& update
18049 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18051 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18052 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18060 /* Estimate the size of a frag before relaxing. Unless this is the
18061 mips16, we are not really relaxing here, and the final size is
18062 encoded in the subtype information. For the mips16, we have to
18063 decide whether we are using an extended opcode or not. */
18066 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18070 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18073 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
18075 return fragp
->fr_var
;
18078 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18080 /* We don't want to modify the EXTENDED bit here; it might get us
18081 into infinite loops. We change it only in mips_relax_frag(). */
18082 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18083 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
18085 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
18088 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18092 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18093 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
18094 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18095 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
18096 fragp
->fr_var
= length
;
18101 if (mips_pic
== VXWORKS_PIC
)
18102 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18104 else if (RELAX_PIC (fragp
->fr_subtype
))
18105 change
= pic_need_relax (fragp
->fr_symbol
);
18107 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18111 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18112 return -RELAX_FIRST (fragp
->fr_subtype
);
18115 return -RELAX_SECOND (fragp
->fr_subtype
);
18118 /* This is called to see whether a reloc against a defined symbol
18119 should be converted into a reloc against a section. */
18122 mips_fix_adjustable (fixS
*fixp
)
18124 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18125 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18128 if (fixp
->fx_addsy
== NULL
)
18131 /* Allow relocs used for EH tables. */
18132 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
18135 /* If symbol SYM is in a mergeable section, relocations of the form
18136 SYM + 0 can usually be made section-relative. The mergeable data
18137 is then identified by the section offset rather than by the symbol.
18139 However, if we're generating REL LO16 relocations, the offset is split
18140 between the LO16 and partnering high part relocation. The linker will
18141 need to recalculate the complete offset in order to correctly identify
18144 The linker has traditionally not looked for the partnering high part
18145 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18146 placed anywhere. Rather than break backwards compatibility by changing
18147 this, it seems better not to force the issue, and instead keep the
18148 original symbol. This will work with either linker behavior. */
18149 if ((lo16_reloc_p (fixp
->fx_r_type
)
18150 || reloc_needs_lo_p (fixp
->fx_r_type
))
18151 && HAVE_IN_PLACE_ADDENDS
18152 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18155 /* There is no place to store an in-place offset for JALR relocations. */
18156 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18159 /* Likewise an in-range offset of limited PC-relative relocations may
18160 overflow the in-place relocatable field if recalculated against the
18161 start address of the symbol's containing section.
18163 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18164 section relative to allow linker relaxations to be performed later on. */
18165 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18166 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18169 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18170 to a floating-point stub. The same is true for non-R_MIPS16_26
18171 relocations against MIPS16 functions; in this case, the stub becomes
18172 the function's canonical address.
18174 Floating-point stubs are stored in unique .mips16.call.* or
18175 .mips16.fn.* sections. If a stub T for function F is in section S,
18176 the first relocation in section S must be against F; this is how the
18177 linker determines the target function. All relocations that might
18178 resolve to T must also be against F. We therefore have the following
18179 restrictions, which are given in an intentionally-redundant way:
18181 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18184 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18185 if that stub might be used.
18187 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18190 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18191 that stub might be used.
18193 There is a further restriction:
18195 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18196 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18197 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18198 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18199 against MIPS16 or microMIPS symbols because we need to keep the
18200 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18201 detection and JAL or BAL to JALX instruction conversion in the
18204 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18205 against a MIPS16 symbol. We deal with (5) by additionally leaving
18206 alone any jump and branch relocations against a microMIPS symbol.
18208 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18209 relocation against some symbol R, no relocation against R may be
18210 reduced. (Note that this deals with (2) as well as (1) because
18211 relocations against global symbols will never be reduced on ELF
18212 targets.) This approach is a little simpler than trying to detect
18213 stub sections, and gives the "all or nothing" per-symbol consistency
18214 that we have for MIPS16 symbols. */
18215 if (fixp
->fx_subsy
== NULL
18216 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18217 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18218 && (jmp_reloc_p (fixp
->fx_r_type
)
18219 || b_reloc_p (fixp
->fx_r_type
)))
18220 || *symbol_get_tc (fixp
->fx_addsy
)))
18226 /* Translate internal representation of relocation info to BFD target
18230 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18232 static arelent
*retval
[4];
18234 bfd_reloc_code_real_type code
;
18236 memset (retval
, 0, sizeof(retval
));
18237 reloc
= retval
[0] = XCNEW (arelent
);
18238 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18239 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18240 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18242 if (fixp
->fx_pcrel
)
18244 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18245 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18246 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18247 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18248 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18249 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18250 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18251 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18252 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18253 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18254 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18255 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18257 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18258 Relocations want only the symbol offset. */
18259 switch (fixp
->fx_r_type
)
18261 case BFD_RELOC_MIPS_18_PCREL_S3
:
18262 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18265 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18269 else if (HAVE_IN_PLACE_ADDENDS
18270 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18271 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18272 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18274 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18275 addend accordingly. */
18276 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18279 reloc
->addend
= fixp
->fx_addnumber
;
18281 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18282 entry to be used in the relocation's section offset. */
18283 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18285 reloc
->address
= reloc
->addend
;
18289 code
= fixp
->fx_r_type
;
18291 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18292 if (reloc
->howto
== NULL
)
18294 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18295 _("cannot represent %s relocation in this object file"
18297 bfd_get_reloc_code_name (code
));
18304 /* Relax a machine dependent frag. This returns the amount by which
18305 the current size of the frag should change. */
18308 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18310 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18312 offsetT old_var
= fragp
->fr_var
;
18314 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18316 return fragp
->fr_var
- old_var
;
18319 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18321 offsetT old_var
= fragp
->fr_var
;
18322 offsetT new_var
= 4;
18324 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18325 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18326 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18327 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18328 fragp
->fr_var
= new_var
;
18330 return new_var
- old_var
;
18333 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18336 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18338 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18340 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18341 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18343 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18345 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18351 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18353 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18355 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18356 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18357 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18359 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18361 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18369 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18371 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18373 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18374 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18375 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18379 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18380 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18387 /* Convert a machine dependent frag. */
18390 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18392 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18395 unsigned long insn
;
18398 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18399 insn
= read_insn (buf
);
18401 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18403 /* We generate a fixup instead of applying it right now
18404 because, if there are linker relaxations, we're going to
18405 need the relocations. */
18406 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18407 fragp
->fr_symbol
, fragp
->fr_offset
,
18408 TRUE
, BFD_RELOC_16_PCREL_S2
);
18409 fixp
->fx_file
= fragp
->fr_file
;
18410 fixp
->fx_line
= fragp
->fr_line
;
18412 buf
= write_insn (buf
, insn
);
18418 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18419 _("relaxed out-of-range branch into a jump"));
18421 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18424 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18426 /* Reverse the branch. */
18427 switch ((insn
>> 28) & 0xf)
18430 if ((insn
& 0xff000000) == 0x47000000
18431 || (insn
& 0xff600000) == 0x45600000)
18433 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18434 reversed by tweaking bit 23. */
18435 insn
^= 0x00800000;
18439 /* bc[0-3][tf]l? instructions can have the condition
18440 reversed by tweaking a single TF bit, and their
18441 opcodes all have 0x4???????. */
18442 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18443 insn
^= 0x00010000;
18448 /* bltz 0x04000000 bgez 0x04010000
18449 bltzal 0x04100000 bgezal 0x04110000 */
18450 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18451 insn
^= 0x00010000;
18455 /* beq 0x10000000 bne 0x14000000
18456 blez 0x18000000 bgtz 0x1c000000 */
18457 insn
^= 0x04000000;
18465 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18467 /* Clear the and-link bit. */
18468 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18470 /* bltzal 0x04100000 bgezal 0x04110000
18471 bltzall 0x04120000 bgezall 0x04130000 */
18472 insn
&= ~0x00100000;
18475 /* Branch over the branch (if the branch was likely) or the
18476 full jump (not likely case). Compute the offset from the
18477 current instruction to branch to. */
18478 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18482 /* How many bytes in instructions we've already emitted? */
18483 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18484 /* How many bytes in instructions from here to the end? */
18485 i
= fragp
->fr_var
- i
;
18487 /* Convert to instruction count. */
18489 /* Branch counts from the next instruction. */
18492 /* Branch over the jump. */
18493 buf
= write_insn (buf
, insn
);
18496 buf
= write_insn (buf
, 0);
18498 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18500 /* beql $0, $0, 2f */
18502 /* Compute the PC offset from the current instruction to
18503 the end of the variable frag. */
18504 /* How many bytes in instructions we've already emitted? */
18505 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18506 /* How many bytes in instructions from here to the end? */
18507 i
= fragp
->fr_var
- i
;
18508 /* Convert to instruction count. */
18510 /* Don't decrement i, because we want to branch over the
18514 buf
= write_insn (buf
, insn
);
18515 buf
= write_insn (buf
, 0);
18519 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18522 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18523 ? 0x0c000000 : 0x08000000);
18525 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18526 fragp
->fr_symbol
, fragp
->fr_offset
,
18527 FALSE
, BFD_RELOC_MIPS_JMP
);
18528 fixp
->fx_file
= fragp
->fr_file
;
18529 fixp
->fx_line
= fragp
->fr_line
;
18531 buf
= write_insn (buf
, insn
);
18535 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18537 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18538 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18539 insn
|= at
<< OP_SH_RT
;
18541 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18542 fragp
->fr_symbol
, fragp
->fr_offset
,
18543 FALSE
, BFD_RELOC_MIPS_GOT16
);
18544 fixp
->fx_file
= fragp
->fr_file
;
18545 fixp
->fx_line
= fragp
->fr_line
;
18547 buf
= write_insn (buf
, insn
);
18549 if (mips_opts
.isa
== ISA_MIPS1
)
18551 buf
= write_insn (buf
, 0);
18553 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18554 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18555 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18557 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18558 fragp
->fr_symbol
, fragp
->fr_offset
,
18559 FALSE
, BFD_RELOC_LO16
);
18560 fixp
->fx_file
= fragp
->fr_file
;
18561 fixp
->fx_line
= fragp
->fr_line
;
18563 buf
= write_insn (buf
, insn
);
18566 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18570 insn
|= at
<< OP_SH_RS
;
18572 buf
= write_insn (buf
, insn
);
18576 fragp
->fr_fix
+= fragp
->fr_var
;
18577 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18581 /* Relax microMIPS branches. */
18582 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18584 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18585 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18586 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18587 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18588 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18589 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18590 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18591 bfd_boolean short_ds
;
18592 unsigned long insn
;
18595 fragp
->fr_fix
+= fragp
->fr_var
;
18597 /* Handle 16-bit branches that fit or are forced to fit. */
18598 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18600 /* We generate a fixup instead of applying it right now,
18601 because if there is linker relaxation, we're going to
18602 need the relocations. */
18606 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18607 fragp
->fr_symbol
, fragp
->fr_offset
,
18608 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18611 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18612 fragp
->fr_symbol
, fragp
->fr_offset
,
18613 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18619 fixp
->fx_file
= fragp
->fr_file
;
18620 fixp
->fx_line
= fragp
->fr_line
;
18622 /* These relocations can have an addend that won't fit in
18624 fixp
->fx_no_overflow
= 1;
18629 /* Handle 32-bit branches that fit or are forced to fit. */
18630 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18631 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18633 /* We generate a fixup instead of applying it right now,
18634 because if there is linker relaxation, we're going to
18635 need the relocations. */
18636 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18637 fragp
->fr_symbol
, fragp
->fr_offset
,
18638 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18639 fixp
->fx_file
= fragp
->fr_file
;
18640 fixp
->fx_line
= fragp
->fr_line
;
18644 insn
= read_compressed_insn (buf
, 4);
18649 /* Check the short-delay-slot bit. */
18650 if (!al
|| (insn
& 0x02000000) != 0)
18651 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18653 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18656 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18661 /* Relax 16-bit branches to 32-bit branches. */
18664 insn
= read_compressed_insn (buf
, 2);
18666 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18667 insn
= 0x94000000; /* beq */
18668 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18670 unsigned long regno
;
18672 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18673 regno
= micromips_to_32_reg_d_map
[regno
];
18674 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18675 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18680 /* Nothing else to do, just write it out. */
18681 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18682 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18684 buf
= write_compressed_insn (buf
, insn
, 4);
18686 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18687 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18692 insn
= read_compressed_insn (buf
, 4);
18694 /* Relax 32-bit branches to a sequence of instructions. */
18695 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18696 _("relaxed out-of-range branch into a jump"));
18698 /* Set the short-delay-slot bit. */
18699 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18701 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18705 /* Reverse the branch. */
18706 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18707 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18708 insn
^= 0x20000000;
18709 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18710 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18711 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18712 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18713 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18714 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18715 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18716 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18717 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18718 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18719 insn
^= 0x00400000;
18720 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18721 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18722 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18723 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18724 insn
^= 0x00200000;
18725 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18727 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18729 insn
^= 0x00800000;
18735 /* Clear the and-link and short-delay-slot bits. */
18736 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18738 /* bltzal 0x40200000 bgezal 0x40600000 */
18739 /* bltzals 0x42200000 bgezals 0x42600000 */
18740 insn
&= ~0x02200000;
18743 /* Make a label at the end for use with the branch. */
18744 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18745 micromips_label_inc ();
18746 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18749 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18750 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18751 fixp
->fx_file
= fragp
->fr_file
;
18752 fixp
->fx_line
= fragp
->fr_line
;
18754 /* Branch over the jump. */
18755 buf
= write_compressed_insn (buf
, insn
, 4);
18761 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18763 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18769 unsigned long jal
= (short_ds
|| nods
18770 ? 0x74000000 : 0xf4000000); /* jal/s */
18772 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18773 insn
= al
? jal
: 0xd4000000;
18775 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18776 fragp
->fr_symbol
, fragp
->fr_offset
,
18777 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18778 fixp
->fx_file
= fragp
->fr_file
;
18779 fixp
->fx_line
= fragp
->fr_line
;
18781 buf
= write_compressed_insn (buf
, insn
, 4);
18783 if (compact
|| nods
)
18787 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18789 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18794 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18796 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18797 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18798 insn
|= at
<< MICROMIPSOP_SH_RT
;
18800 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18801 fragp
->fr_symbol
, fragp
->fr_offset
,
18802 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18803 fixp
->fx_file
= fragp
->fr_file
;
18804 fixp
->fx_line
= fragp
->fr_line
;
18806 buf
= write_compressed_insn (buf
, insn
, 4);
18808 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18809 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18810 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18812 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18813 fragp
->fr_symbol
, fragp
->fr_offset
,
18814 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18815 fixp
->fx_file
= fragp
->fr_file
;
18816 fixp
->fx_line
= fragp
->fr_line
;
18818 buf
= write_compressed_insn (buf
, insn
, 4);
18823 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18824 insn
|= at
<< MICROMIPSOP_SH_RS
;
18826 buf
= write_compressed_insn (buf
, insn
, 4);
18828 if (compact
|| nods
)
18830 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18834 /* jr/jrc/jalr/jalrs $at */
18835 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18836 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18838 insn
= al
? jalr
: jr
;
18839 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18841 buf
= write_compressed_insn (buf
, insn
, 2);
18846 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18848 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18853 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18857 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18860 const struct mips_int_operand
*operand
;
18863 unsigned int user_length
;
18864 bfd_boolean need_reloc
;
18865 unsigned long insn
;
18870 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18871 operand
= mips16_immed_operand (type
, FALSE
);
18873 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18874 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18875 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18877 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18878 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18879 || (operand
->root
.type
== OP_PCREL
&& !mac
18881 : !bfd_is_abs_section (symsec
)));
18883 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18885 const struct mips_pcrel_operand
*pcrel_op
;
18887 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18889 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18891 if (!mips_ignore_branch_isa
18892 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18893 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18894 _("branch to a symbol in another ISA mode"));
18895 else if ((fragp
->fr_offset
& 0x1) != 0)
18896 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18897 _("branch to misaligned address (0x%lx)"),
18901 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18903 /* Make sure the section winds up with the alignment we have
18905 if (operand
->shift
> 0)
18906 record_alignment (asec
, operand
->shift
);
18909 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18910 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18913 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18914 _("macro instruction expanded into multiple "
18915 "instructions in a branch delay slot"));
18917 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18918 _("extended instruction in a branch delay slot"));
18920 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18921 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18922 _("macro instruction expanded into multiple "
18925 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18927 insn
= read_compressed_insn (buf
, 2);
18929 insn
|= MIPS16_EXTEND
;
18931 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18933 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18945 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18946 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18948 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
18954 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18956 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18957 fragp
->fr_symbol
, fragp
->fr_offset
,
18958 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18959 fixp
->fx_file
= fragp
->fr_file
;
18960 fixp
->fx_line
= fragp
->fr_line
;
18962 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
18963 fragp
->fr_symbol
, fragp
->fr_offset
,
18964 FALSE
, BFD_RELOC_MIPS16_LO16
);
18965 fixp
->fx_file
= fragp
->fr_file
;
18966 fixp
->fx_line
= fragp
->fr_line
;
18971 switch (insn
& 0xf800)
18973 case 0x0800: /* ADDIU */
18974 reg
= (insn
>> 8) & 0x7;
18975 op
= 0xf0004800 | (reg
<< 8);
18977 case 0xb000: /* LW */
18978 reg
= (insn
>> 8) & 0x7;
18979 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18981 case 0xf800: /* I64 */
18982 reg
= (insn
>> 5) & 0x7;
18983 switch (insn
& 0x0700)
18985 case 0x0400: /* LD */
18986 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18988 case 0x0600: /* DADDIU */
18989 op
= 0xf000fd00 | (reg
<< 5);
18999 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
19000 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
19001 buf
= write_compressed_insn (buf
, new, 4);
19004 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
19005 buf
= write_compressed_insn (buf
, new, 4);
19007 op
|= mips16_immed_extend (val
, 16);
19008 buf
= write_compressed_insn (buf
, op
, 4);
19010 fragp
->fr_fix
+= e2
? 8 : 12;
19014 unsigned int length
= ext
? 4 : 2;
19018 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
19025 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
19030 if (mac
|| reloc
== BFD_RELOC_NONE
)
19031 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19032 _("unsupported relocation"));
19035 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19036 fragp
->fr_symbol
, fragp
->fr_offset
,
19038 fixp
->fx_file
= fragp
->fr_file
;
19039 fixp
->fx_line
= fragp
->fr_line
;
19042 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19043 _("invalid unextended operand value"));
19046 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
19047 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
19049 gas_assert (mips16_opcode_length (insn
) == length
);
19050 write_compressed_insn (buf
, insn
, length
);
19051 fragp
->fr_fix
+= length
;
19056 relax_substateT subtype
= fragp
->fr_subtype
;
19057 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
19058 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
19059 unsigned int first
, second
;
19062 first
= RELAX_FIRST (subtype
);
19063 second
= RELAX_SECOND (subtype
);
19064 fixp
= (fixS
*) fragp
->fr_opcode
;
19066 /* If the delay slot chosen does not match the size of the instruction,
19067 then emit a warning. */
19068 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
19069 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
19074 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
19075 | RELAX_DELAY_SLOT_SIZE_FIRST
19076 | RELAX_DELAY_SLOT_SIZE_SECOND
);
19077 msg
= macro_warning (s
);
19079 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19083 /* Possibly emit a warning if we've chosen the longer option. */
19084 if (use_second
== second_longer
)
19090 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
19091 msg
= macro_warning (s
);
19093 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19097 /* Go through all the fixups for the first sequence. Disable them
19098 (by marking them as done) if we're going to use the second
19099 sequence instead. */
19101 && fixp
->fx_frag
== fragp
19102 && fixp
->fx_where
+ second
< fragp
->fr_fix
)
19104 if (subtype
& RELAX_USE_SECOND
)
19106 fixp
= fixp
->fx_next
;
19109 /* Go through the fixups for the second sequence. Disable them if
19110 we're going to use the first sequence, otherwise adjust their
19111 addresses to account for the relaxation. */
19112 while (fixp
&& fixp
->fx_frag
== fragp
)
19114 if (subtype
& RELAX_USE_SECOND
)
19115 fixp
->fx_where
-= first
;
19118 fixp
= fixp
->fx_next
;
19121 /* Now modify the frag contents. */
19122 if (subtype
& RELAX_USE_SECOND
)
19126 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
19127 memmove (start
, start
+ first
, second
);
19128 fragp
->fr_fix
-= first
;
19131 fragp
->fr_fix
-= second
;
19135 /* This function is called after the relocs have been generated.
19136 We've been storing mips16 text labels as odd. Here we convert them
19137 back to even for the convenience of the debugger. */
19140 mips_frob_file_after_relocs (void)
19143 unsigned int count
, i
;
19145 syms
= bfd_get_outsymbols (stdoutput
);
19146 count
= bfd_get_symcount (stdoutput
);
19147 for (i
= 0; i
< count
; i
++, syms
++)
19148 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19149 && ((*syms
)->value
& 1) != 0)
19151 (*syms
)->value
&= ~1;
19152 /* If the symbol has an odd size, it was probably computed
19153 incorrectly, so adjust that as well. */
19154 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19155 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19159 /* This function is called whenever a label is defined, including fake
19160 labels instantiated off the dot special symbol. It is used when
19161 handling branch delays; if a branch has a label, we assume we cannot
19162 move it. This also bumps the value of the symbol by 1 in compressed
19166 mips_record_label (symbolS
*sym
)
19168 segment_info_type
*si
= seg_info (now_seg
);
19169 struct insn_label_list
*l
;
19171 if (free_insn_labels
== NULL
)
19172 l
= XNEW (struct insn_label_list
);
19175 l
= free_insn_labels
;
19176 free_insn_labels
= l
->next
;
19180 l
->next
= si
->label_list
;
19181 si
->label_list
= l
;
19184 /* This function is called as tc_frob_label() whenever a label is defined
19185 and adds a DWARF-2 record we only want for true labels. */
19188 mips_define_label (symbolS
*sym
)
19190 mips_record_label (sym
);
19191 dwarf2_emit_label (sym
);
19194 /* This function is called by tc_new_dot_label whenever a new dot symbol
19198 mips_add_dot_label (symbolS
*sym
)
19200 mips_record_label (sym
);
19201 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19202 mips_compressed_mark_label (sym
);
19205 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19206 static unsigned int
19207 mips_convert_ase_flags (int ase
)
19209 unsigned int ext_ases
= 0;
19212 ext_ases
|= AFL_ASE_DSP
;
19213 if (ase
& ASE_DSPR2
)
19214 ext_ases
|= AFL_ASE_DSPR2
;
19215 if (ase
& ASE_DSPR3
)
19216 ext_ases
|= AFL_ASE_DSPR3
;
19218 ext_ases
|= AFL_ASE_EVA
;
19220 ext_ases
|= AFL_ASE_MCU
;
19221 if (ase
& ASE_MDMX
)
19222 ext_ases
|= AFL_ASE_MDMX
;
19223 if (ase
& ASE_MIPS3D
)
19224 ext_ases
|= AFL_ASE_MIPS3D
;
19226 ext_ases
|= AFL_ASE_MT
;
19227 if (ase
& ASE_SMARTMIPS
)
19228 ext_ases
|= AFL_ASE_SMARTMIPS
;
19229 if (ase
& ASE_VIRT
)
19230 ext_ases
|= AFL_ASE_VIRT
;
19232 ext_ases
|= AFL_ASE_MSA
;
19234 ext_ases
|= AFL_ASE_XPA
;
19235 if (ase
& ASE_MIPS16E2
)
19236 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19238 ext_ases
|= AFL_ASE_CRC
;
19239 if (ase
& ASE_GINV
)
19240 ext_ases
|= AFL_ASE_GINV
;
19241 if (ase
& ASE_LOONGSON_MMI
)
19242 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19243 if (ase
& ASE_LOONGSON_CAM
)
19244 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19245 if (ase
& ASE_LOONGSON_EXT
)
19246 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19247 if (ase
& ASE_LOONGSON_EXT2
)
19248 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19252 /* Some special processing for a MIPS ELF file. */
19255 mips_elf_final_processing (void)
19258 Elf_Internal_ABIFlags_v0 flags
;
19262 switch (file_mips_opts
.isa
)
19265 flags
.isa_level
= 1;
19268 flags
.isa_level
= 2;
19271 flags
.isa_level
= 3;
19274 flags
.isa_level
= 4;
19277 flags
.isa_level
= 5;
19280 flags
.isa_level
= 32;
19284 flags
.isa_level
= 32;
19288 flags
.isa_level
= 32;
19292 flags
.isa_level
= 32;
19296 flags
.isa_level
= 32;
19300 flags
.isa_level
= 64;
19304 flags
.isa_level
= 64;
19308 flags
.isa_level
= 64;
19312 flags
.isa_level
= 64;
19316 flags
.isa_level
= 64;
19321 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19322 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19323 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19324 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19326 flags
.cpr2_size
= AFL_REG_NONE
;
19327 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19328 Tag_GNU_MIPS_ABI_FP
);
19329 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19330 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19331 if (file_ase_mips16
)
19332 flags
.ases
|= AFL_ASE_MIPS16
;
19333 if (file_ase_micromips
)
19334 flags
.ases
|= AFL_ASE_MICROMIPS
;
19336 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19337 || file_mips_opts
.fp
== 64)
19338 && file_mips_opts
.oddspreg
)
19339 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19342 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19343 ((Elf_External_ABIFlags_v0
*)
19346 /* Write out the register information. */
19347 if (mips_abi
!= N64_ABI
)
19351 s
.ri_gprmask
= mips_gprmask
;
19352 s
.ri_cprmask
[0] = mips_cprmask
[0];
19353 s
.ri_cprmask
[1] = mips_cprmask
[1];
19354 s
.ri_cprmask
[2] = mips_cprmask
[2];
19355 s
.ri_cprmask
[3] = mips_cprmask
[3];
19356 /* The gp_value field is set by the MIPS ELF backend. */
19358 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19359 ((Elf32_External_RegInfo
*)
19360 mips_regmask_frag
));
19364 Elf64_Internal_RegInfo s
;
19366 s
.ri_gprmask
= mips_gprmask
;
19368 s
.ri_cprmask
[0] = mips_cprmask
[0];
19369 s
.ri_cprmask
[1] = mips_cprmask
[1];
19370 s
.ri_cprmask
[2] = mips_cprmask
[2];
19371 s
.ri_cprmask
[3] = mips_cprmask
[3];
19372 /* The gp_value field is set by the MIPS ELF backend. */
19374 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19375 ((Elf64_External_RegInfo
*)
19376 mips_regmask_frag
));
19379 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19380 sort of BFD interface for this. */
19381 if (mips_any_noreorder
)
19382 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19383 if (mips_pic
!= NO_PIC
)
19385 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19386 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19389 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19391 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19392 defined at present; this might need to change in future. */
19393 if (file_ase_mips16
)
19394 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19395 if (file_ase_micromips
)
19396 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19397 if (file_mips_opts
.ase
& ASE_MDMX
)
19398 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19400 /* Set the MIPS ELF ABI flags. */
19401 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19402 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19403 else if (mips_abi
== O64_ABI
)
19404 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19405 else if (mips_abi
== EABI_ABI
)
19407 if (file_mips_opts
.gp
== 64)
19408 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19410 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19413 /* Nothing to do for N32_ABI or N64_ABI. */
19415 if (mips_32bitmode
)
19416 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19418 if (mips_nan2008
== 1)
19419 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19421 /* 32 bit code with 64 bit FP registers. */
19422 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19423 Tag_GNU_MIPS_ABI_FP
);
19424 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19425 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19428 typedef struct proc
{
19430 symbolS
*func_end_sym
;
19431 unsigned long reg_mask
;
19432 unsigned long reg_offset
;
19433 unsigned long fpreg_mask
;
19434 unsigned long fpreg_offset
;
19435 unsigned long frame_offset
;
19436 unsigned long frame_reg
;
19437 unsigned long pc_reg
;
19440 static procS cur_proc
;
19441 static procS
*cur_proc_ptr
;
19442 static int numprocs
;
19444 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19445 as "2", and a normal nop as "0". */
19447 #define NOP_OPCODE_MIPS 0
19448 #define NOP_OPCODE_MIPS16 1
19449 #define NOP_OPCODE_MICROMIPS 2
19452 mips_nop_opcode (void)
19454 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19455 return NOP_OPCODE_MICROMIPS
;
19456 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19457 return NOP_OPCODE_MIPS16
;
19459 return NOP_OPCODE_MIPS
;
19462 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19463 32-bit microMIPS NOPs here (if applicable). */
19466 mips_handle_align (fragS
*fragp
)
19470 int bytes
, size
, excess
;
19473 if (fragp
->fr_type
!= rs_align_code
)
19476 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19478 switch (nop_opcode
)
19480 case NOP_OPCODE_MICROMIPS
:
19481 opcode
= micromips_nop32_insn
.insn_opcode
;
19484 case NOP_OPCODE_MIPS16
:
19485 opcode
= mips16_nop_insn
.insn_opcode
;
19488 case NOP_OPCODE_MIPS
:
19490 opcode
= nop_insn
.insn_opcode
;
19495 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19496 excess
= bytes
% size
;
19498 /* Handle the leading part if we're not inserting a whole number of
19499 instructions, and make it the end of the fixed part of the frag.
19500 Try to fit in a short microMIPS NOP if applicable and possible,
19501 and use zeroes otherwise. */
19502 gas_assert (excess
< 4);
19503 fragp
->fr_fix
+= excess
;
19508 /* Fall through. */
19510 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19512 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19516 /* Fall through. */
19519 /* Fall through. */
19524 md_number_to_chars (p
, opcode
, size
);
19525 fragp
->fr_var
= size
;
19534 if (*input_line_pointer
== '-')
19536 ++input_line_pointer
;
19539 if (!ISDIGIT (*input_line_pointer
))
19540 as_bad (_("expected simple number"));
19541 if (input_line_pointer
[0] == '0')
19543 if (input_line_pointer
[1] == 'x')
19545 input_line_pointer
+= 2;
19546 while (ISXDIGIT (*input_line_pointer
))
19549 val
|= hex_value (*input_line_pointer
++);
19551 return negative
? -val
: val
;
19555 ++input_line_pointer
;
19556 while (ISDIGIT (*input_line_pointer
))
19559 val
|= *input_line_pointer
++ - '0';
19561 return negative
? -val
: val
;
19564 if (!ISDIGIT (*input_line_pointer
))
19566 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19567 *input_line_pointer
, *input_line_pointer
);
19568 as_warn (_("invalid number"));
19571 while (ISDIGIT (*input_line_pointer
))
19574 val
+= *input_line_pointer
++ - '0';
19576 return negative
? -val
: val
;
19579 /* The .file directive; just like the usual .file directive, but there
19580 is an initial number which is the ECOFF file index. In the non-ECOFF
19581 case .file implies DWARF-2. */
19584 s_mips_file (int x ATTRIBUTE_UNUSED
)
19586 static int first_file_directive
= 0;
19588 if (ECOFF_DEBUGGING
)
19597 filename
= dwarf2_directive_filename ();
19599 /* Versions of GCC up to 3.1 start files with a ".file"
19600 directive even for stabs output. Make sure that this
19601 ".file" is handled. Note that you need a version of GCC
19602 after 3.1 in order to support DWARF-2 on MIPS. */
19603 if (filename
!= NULL
&& ! first_file_directive
)
19605 (void) new_logical_line (filename
, -1);
19606 s_app_file_string (filename
, 0);
19608 first_file_directive
= 1;
19612 /* The .loc directive, implying DWARF-2. */
19615 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19617 if (!ECOFF_DEBUGGING
)
19618 dwarf2_directive_loc (0);
19621 /* The .end directive. */
19624 s_mips_end (int x ATTRIBUTE_UNUSED
)
19628 /* Following functions need their own .frame and .cprestore directives. */
19629 mips_frame_reg_valid
= 0;
19630 mips_cprestore_valid
= 0;
19632 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19635 demand_empty_rest_of_line ();
19640 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19641 as_warn (_(".end not in text section"));
19645 as_warn (_(".end directive without a preceding .ent directive"));
19646 demand_empty_rest_of_line ();
19652 gas_assert (S_GET_NAME (p
));
19653 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19654 as_warn (_(".end symbol does not match .ent symbol"));
19656 if (debug_type
== DEBUG_STABS
)
19657 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19661 as_warn (_(".end directive missing or unknown symbol"));
19663 /* Create an expression to calculate the size of the function. */
19664 if (p
&& cur_proc_ptr
)
19666 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19667 expressionS
*exp
= XNEW (expressionS
);
19670 exp
->X_op
= O_subtract
;
19671 exp
->X_add_symbol
= symbol_temp_new_now ();
19672 exp
->X_op_symbol
= p
;
19673 exp
->X_add_number
= 0;
19675 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19678 #ifdef md_flush_pending_output
19679 md_flush_pending_output ();
19682 /* Generate a .pdr section. */
19683 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19685 segT saved_seg
= now_seg
;
19686 subsegT saved_subseg
= now_subseg
;
19690 gas_assert (pdr_seg
);
19691 subseg_set (pdr_seg
, 0);
19693 /* Write the symbol. */
19694 exp
.X_op
= O_symbol
;
19695 exp
.X_add_symbol
= p
;
19696 exp
.X_add_number
= 0;
19697 emit_expr (&exp
, 4);
19699 fragp
= frag_more (7 * 4);
19701 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19702 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19703 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19704 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19705 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19706 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19707 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19709 subseg_set (saved_seg
, saved_subseg
);
19712 cur_proc_ptr
= NULL
;
19715 /* The .aent and .ent directives. */
19718 s_mips_ent (int aent
)
19722 symbolP
= get_symbol ();
19723 if (*input_line_pointer
== ',')
19724 ++input_line_pointer
;
19725 SKIP_WHITESPACE ();
19726 if (ISDIGIT (*input_line_pointer
)
19727 || *input_line_pointer
== '-')
19730 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19731 as_warn (_(".ent or .aent not in text section"));
19733 if (!aent
&& cur_proc_ptr
)
19734 as_warn (_("missing .end"));
19738 /* This function needs its own .frame and .cprestore directives. */
19739 mips_frame_reg_valid
= 0;
19740 mips_cprestore_valid
= 0;
19742 cur_proc_ptr
= &cur_proc
;
19743 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19745 cur_proc_ptr
->func_sym
= symbolP
;
19749 if (debug_type
== DEBUG_STABS
)
19750 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19751 S_GET_NAME (symbolP
));
19754 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19756 demand_empty_rest_of_line ();
19759 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19760 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19761 s_mips_frame is used so that we can set the PDR information correctly.
19762 We can't use the ecoff routines because they make reference to the ecoff
19763 symbol table (in the mdebug section). */
19766 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19768 if (ECOFF_DEBUGGING
)
19774 if (cur_proc_ptr
== (procS
*) NULL
)
19776 as_warn (_(".frame outside of .ent"));
19777 demand_empty_rest_of_line ();
19781 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19783 SKIP_WHITESPACE ();
19784 if (*input_line_pointer
++ != ','
19785 || get_absolute_expression_and_terminator (&val
) != ',')
19787 as_warn (_("bad .frame directive"));
19788 --input_line_pointer
;
19789 demand_empty_rest_of_line ();
19793 cur_proc_ptr
->frame_offset
= val
;
19794 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19796 demand_empty_rest_of_line ();
19800 /* The .fmask and .mask directives. If the mdebug section is present
19801 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19802 embedded targets, s_mips_mask is used so that we can set the PDR
19803 information correctly. We can't use the ecoff routines because they
19804 make reference to the ecoff symbol table (in the mdebug section). */
19807 s_mips_mask (int reg_type
)
19809 if (ECOFF_DEBUGGING
)
19810 s_ignore (reg_type
);
19815 if (cur_proc_ptr
== (procS
*) NULL
)
19817 as_warn (_(".mask/.fmask outside of .ent"));
19818 demand_empty_rest_of_line ();
19822 if (get_absolute_expression_and_terminator (&mask
) != ',')
19824 as_warn (_("bad .mask/.fmask directive"));
19825 --input_line_pointer
;
19826 demand_empty_rest_of_line ();
19830 off
= get_absolute_expression ();
19832 if (reg_type
== 'F')
19834 cur_proc_ptr
->fpreg_mask
= mask
;
19835 cur_proc_ptr
->fpreg_offset
= off
;
19839 cur_proc_ptr
->reg_mask
= mask
;
19840 cur_proc_ptr
->reg_offset
= off
;
19843 demand_empty_rest_of_line ();
19847 /* A table describing all the processors gas knows about. Names are
19848 matched in the order listed.
19850 To ease comparison, please keep this table in the same order as
19851 gcc's mips_cpu_info_table[]. */
19852 static const struct mips_cpu_info mips_cpu_info_table
[] =
19854 /* Entries for generic ISAs. */
19855 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19856 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19857 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19858 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19859 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19860 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19861 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19862 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19863 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19864 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19865 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19866 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19867 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19868 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19869 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19872 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19873 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19874 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19877 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19880 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19881 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19882 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19883 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19884 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19885 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19886 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19887 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19888 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19889 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19890 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19891 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19892 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19893 /* ST Microelectronics Loongson 2E and 2F cores. */
19894 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19895 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
19898 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19899 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19900 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19901 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19902 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19903 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19904 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19905 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19906 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19907 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19908 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19909 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19910 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19911 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19912 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19915 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19916 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19917 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19918 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19920 /* MIPS 32 Release 2 */
19921 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19922 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19923 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19924 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19925 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19926 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19927 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19928 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19929 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19930 ISA_MIPS32R2
, CPU_MIPS32R2
},
19931 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19932 ISA_MIPS32R2
, CPU_MIPS32R2
},
19933 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19934 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19935 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19936 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19937 /* Deprecated forms of the above. */
19938 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19939 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19940 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19941 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19942 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19943 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19944 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19945 /* Deprecated forms of the above. */
19946 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19947 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19948 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19949 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19950 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19951 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19952 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19953 /* Deprecated forms of the above. */
19954 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19955 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19956 /* 34Kn is a 34kc without DSP. */
19957 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19958 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19959 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19960 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19961 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19962 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19963 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19964 /* Deprecated forms of the above. */
19965 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19966 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19967 /* 1004K cores are multiprocessor versions of the 34K. */
19968 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19969 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19970 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19971 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19972 /* interaptiv is the new name for 1004kf. */
19973 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19974 { "interaptiv-mr2", 0,
19975 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
19976 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
19977 /* M5100 family. */
19978 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19979 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19980 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19981 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19984 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19985 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19986 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19987 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19989 /* Broadcom SB-1 CPU core. */
19990 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19991 /* Broadcom SB-1A CPU core. */
19992 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19994 /* MIPS 64 Release 2. */
19995 /* Loongson CPU core. */
19996 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
19997 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
19998 ISA_MIPS64R2
, CPU_GS464
},
19999 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20000 ISA_MIPS64R2
, CPU_GS464
},
20001 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20002 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
20003 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20004 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
20006 /* Cavium Networks Octeon CPU core. */
20007 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
20008 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
20009 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
20010 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
20013 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
20016 XLP is mostly like XLR, with the prominent exception that it is
20017 MIPS64R2 rather than MIPS64. */
20018 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
20020 /* MIPS 64 Release 6. */
20021 { "i6400", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20022 { "i6500", 0, ASE_VIRT
| ASE_MSA
| ASE_CRC
| ASE_GINV
,
20023 ISA_MIPS64R6
, CPU_MIPS64R6
},
20024 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20027 { NULL
, 0, 0, 0, 0 }
20031 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20032 with a final "000" replaced by "k". Ignore case.
20034 Note: this function is shared between GCC and GAS. */
20037 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
20039 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
20040 given
++, canonical
++;
20042 return ((*given
== 0 && *canonical
== 0)
20043 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
20047 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20048 CPU name. We've traditionally allowed a lot of variation here.
20050 Note: this function is shared between GCC and GAS. */
20053 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
20055 /* First see if the name matches exactly, or with a final "000"
20056 turned into "k". */
20057 if (mips_strict_matching_cpu_name_p (canonical
, given
))
20060 /* If not, try comparing based on numerical designation alone.
20061 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20062 if (TOLOWER (*given
) == 'r')
20064 if (!ISDIGIT (*given
))
20067 /* Skip over some well-known prefixes in the canonical name,
20068 hoping to find a number there too. */
20069 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
20071 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
20073 else if (TOLOWER (canonical
[0]) == 'r')
20076 return mips_strict_matching_cpu_name_p (canonical
, given
);
20080 /* Parse an option that takes the name of a processor as its argument.
20081 OPTION is the name of the option and CPU_STRING is the argument.
20082 Return the corresponding processor enumeration if the CPU_STRING is
20083 recognized, otherwise report an error and return null.
20085 A similar function exists in GCC. */
20087 static const struct mips_cpu_info
*
20088 mips_parse_cpu (const char *option
, const char *cpu_string
)
20090 const struct mips_cpu_info
*p
;
20092 /* 'from-abi' selects the most compatible architecture for the given
20093 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20094 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20095 version. Look first at the -mgp options, if given, otherwise base
20096 the choice on MIPS_DEFAULT_64BIT.
20098 Treat NO_ABI like the EABIs. One reason to do this is that the
20099 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20100 architecture. This code picks MIPS I for 'mips' and MIPS III for
20101 'mips64', just as we did in the days before 'from-abi'. */
20102 if (strcasecmp (cpu_string
, "from-abi") == 0)
20104 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
20105 return mips_cpu_info_from_isa (ISA_MIPS1
);
20107 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
20108 return mips_cpu_info_from_isa (ISA_MIPS3
);
20110 if (file_mips_opts
.gp
>= 0)
20111 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
20112 ? ISA_MIPS1
: ISA_MIPS3
);
20114 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20119 /* 'default' has traditionally been a no-op. Probably not very useful. */
20120 if (strcasecmp (cpu_string
, "default") == 0)
20123 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
20124 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
20127 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
20131 /* Return the canonical processor information for ISA (a member of the
20132 ISA_MIPS* enumeration). */
20134 static const struct mips_cpu_info
*
20135 mips_cpu_info_from_isa (int isa
)
20139 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20140 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
20141 && isa
== mips_cpu_info_table
[i
].isa
)
20142 return (&mips_cpu_info_table
[i
]);
20147 static const struct mips_cpu_info
*
20148 mips_cpu_info_from_arch (int arch
)
20152 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20153 if (arch
== mips_cpu_info_table
[i
].cpu
)
20154 return (&mips_cpu_info_table
[i
]);
20160 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20164 fprintf (stream
, "%24s", "");
20169 fprintf (stream
, ", ");
20173 if (*col_p
+ strlen (string
) > 72)
20175 fprintf (stream
, "\n%24s", "");
20179 fprintf (stream
, "%s", string
);
20180 *col_p
+= strlen (string
);
20186 md_show_usage (FILE *stream
)
20191 fprintf (stream
, _("\
20193 -EB generate big endian output\n\
20194 -EL generate little endian output\n\
20195 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20196 -G NUM allow referencing objects up to NUM bytes\n\
20197 implicitly with the gp register [default 8]\n"));
20198 fprintf (stream
, _("\
20199 -mips1 generate MIPS ISA I instructions\n\
20200 -mips2 generate MIPS ISA II instructions\n\
20201 -mips3 generate MIPS ISA III instructions\n\
20202 -mips4 generate MIPS ISA IV instructions\n\
20203 -mips5 generate MIPS ISA V instructions\n\
20204 -mips32 generate MIPS32 ISA instructions\n\
20205 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20206 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20207 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20208 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20209 -mips64 generate MIPS64 ISA instructions\n\
20210 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20211 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20212 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20213 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20214 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20218 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20219 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20220 show (stream
, "from-abi", &column
, &first
);
20221 fputc ('\n', stream
);
20223 fprintf (stream
, _("\
20224 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20225 -no-mCPU don't generate code specific to CPU.\n\
20226 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20230 show (stream
, "3900", &column
, &first
);
20231 show (stream
, "4010", &column
, &first
);
20232 show (stream
, "4100", &column
, &first
);
20233 show (stream
, "4650", &column
, &first
);
20234 fputc ('\n', stream
);
20236 fprintf (stream
, _("\
20237 -mips16 generate mips16 instructions\n\
20238 -no-mips16 do not generate mips16 instructions\n"));
20239 fprintf (stream
, _("\
20240 -mmips16e2 generate MIPS16e2 instructions\n\
20241 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20242 fprintf (stream
, _("\
20243 -mmicromips generate microMIPS instructions\n\
20244 -mno-micromips do not generate microMIPS instructions\n"));
20245 fprintf (stream
, _("\
20246 -msmartmips generate smartmips instructions\n\
20247 -mno-smartmips do not generate smartmips instructions\n"));
20248 fprintf (stream
, _("\
20249 -mdsp generate DSP instructions\n\
20250 -mno-dsp do not generate DSP instructions\n"));
20251 fprintf (stream
, _("\
20252 -mdspr2 generate DSP R2 instructions\n\
20253 -mno-dspr2 do not generate DSP R2 instructions\n"));
20254 fprintf (stream
, _("\
20255 -mdspr3 generate DSP R3 instructions\n\
20256 -mno-dspr3 do not generate DSP R3 instructions\n"));
20257 fprintf (stream
, _("\
20258 -mmt generate MT instructions\n\
20259 -mno-mt do not generate MT instructions\n"));
20260 fprintf (stream
, _("\
20261 -mmcu generate MCU instructions\n\
20262 -mno-mcu do not generate MCU instructions\n"));
20263 fprintf (stream
, _("\
20264 -mmsa generate MSA instructions\n\
20265 -mno-msa do not generate MSA instructions\n"));
20266 fprintf (stream
, _("\
20267 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20268 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20269 fprintf (stream
, _("\
20270 -mvirt generate Virtualization instructions\n\
20271 -mno-virt do not generate Virtualization instructions\n"));
20272 fprintf (stream
, _("\
20273 -mcrc generate CRC instructions\n\
20274 -mno-crc do not generate CRC instructions\n"));
20275 fprintf (stream
, _("\
20276 -mginv generate Global INValidate (GINV) instructions\n\
20277 -mno-ginv do not generate Global INValidate instructions\n"));
20278 fprintf (stream
, _("\
20279 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20280 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20281 fprintf (stream
, _("\
20282 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20283 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20284 fprintf (stream
, _("\
20285 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20286 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20287 fprintf (stream
, _("\
20288 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20289 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20290 fprintf (stream
, _("\
20291 -minsn32 only generate 32-bit microMIPS instructions\n\
20292 -mno-insn32 generate all microMIPS instructions\n"));
20293 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20294 fprintf (stream
, _("\
20295 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20296 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20298 fprintf (stream
, _("\
20299 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20300 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20302 fprintf (stream
, _("\
20303 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20304 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20305 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20306 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20307 -mfix-vr4120 work around certain VR4120 errata\n\
20308 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20309 -mfix-24k insert a nop after ERET and DERET instructions\n\
20310 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20311 -mfix-r5900 work around R5900 short loop errata\n\
20312 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20313 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20314 -msym32 assume all symbols have 32-bit values\n\
20315 -O0 do not remove unneeded NOPs, do not swap branches\n\
20316 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20317 -O2 remove unneeded NOPs and swap branches\n\
20318 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20319 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20320 fprintf (stream
, _("\
20321 -mhard-float allow floating-point instructions\n\
20322 -msoft-float do not allow floating-point instructions\n\
20323 -msingle-float only allow 32-bit floating-point operations\n\
20324 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20325 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20326 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20327 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20328 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20329 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20333 show (stream
, "legacy", &column
, &first
);
20334 show (stream
, "2008", &column
, &first
);
20336 fputc ('\n', stream
);
20338 fprintf (stream
, _("\
20339 -KPIC, -call_shared generate SVR4 position independent code\n\
20340 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20341 -mvxworks-pic generate VxWorks position independent code\n\
20342 -non_shared do not generate code that can operate with DSOs\n\
20343 -xgot assume a 32 bit GOT\n\
20344 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20345 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20346 position dependent (non shared) code\n\
20347 -mabi=ABI create ABI conformant object file for:\n"));
20351 show (stream
, "32", &column
, &first
);
20352 show (stream
, "o64", &column
, &first
);
20353 show (stream
, "n32", &column
, &first
);
20354 show (stream
, "64", &column
, &first
);
20355 show (stream
, "eabi", &column
, &first
);
20357 fputc ('\n', stream
);
20359 fprintf (stream
, _("\
20360 -32 create o32 ABI object file%s\n"),
20361 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20362 fprintf (stream
, _("\
20363 -n32 create n32 ABI object file%s\n"),
20364 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20365 fprintf (stream
, _("\
20366 -64 create 64 ABI object file%s\n"),
20367 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20372 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20374 if (HAVE_64BIT_SYMBOLS
)
20375 return dwarf2_format_64bit_irix
;
20377 return dwarf2_format_32bit
;
20382 mips_dwarf2_addr_size (void)
20384 if (HAVE_64BIT_OBJECTS
)
20390 /* Standard calling conventions leave the CFA at SP on entry. */
20392 mips_cfi_frame_initial_instructions (void)
20394 cfi_add_CFA_def_cfa_register (SP
);
20398 tc_mips_regname_to_dw2regnum (char *regname
)
20400 unsigned int regnum
= -1;
20403 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20409 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20410 Given a symbolic attribute NAME, return the proper integer value.
20411 Returns -1 if the attribute is not known. */
20414 mips_convert_symbolic_attribute (const char *name
)
20416 static const struct
20421 attribute_table
[] =
20423 #define T(tag) {#tag, tag}
20424 T (Tag_GNU_MIPS_ABI_FP
),
20425 T (Tag_GNU_MIPS_ABI_MSA
),
20433 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20434 if (streq (name
, attribute_table
[i
].name
))
20435 return attribute_table
[i
].tag
;
20443 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20445 mips_emit_delays ();
20447 as_warn (_("missing .end at end of assembly"));
20449 /* Just in case no code was emitted, do the consistency check. */
20450 file_mips_check_options ();
20452 /* Set a floating-point ABI if the user did not. */
20453 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20455 /* Perform consistency checks on the floating-point ABI. */
20456 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20457 Tag_GNU_MIPS_ABI_FP
);
20458 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20459 check_fpabi (fpabi
);
20463 /* Soft-float gets precedence over single-float, the two options should
20464 not be used together so this should not matter. */
20465 if (file_mips_opts
.soft_float
== 1)
20466 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20467 /* Single-float gets precedence over all double_float cases. */
20468 else if (file_mips_opts
.single_float
== 1)
20469 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20472 switch (file_mips_opts
.fp
)
20475 if (file_mips_opts
.gp
== 32)
20476 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20479 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20482 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20483 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20484 else if (file_mips_opts
.gp
== 32)
20485 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20487 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20492 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20493 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20497 /* Returns the relocation type required for a particular CFI encoding. */
20499 bfd_reloc_code_real_type
20500 mips_cfi_reloc_for_encoding (int encoding
)
20502 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20503 return BFD_RELOC_32_PCREL
;
20504 else return BFD_RELOC_NONE
;