1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian
;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode
*insn_mo
;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend
;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode
;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p
: 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p
: 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p
: 1;
161 /* The ABI to use. */
172 /* MIPS ABI we are using for this output file. */
173 static enum mips_abi_level mips_abi
= NO_ABI
;
175 /* Whether or not we have code that can call pic code. */
176 int mips_abicalls
= FALSE
;
178 /* Whether or not we have code which can be put into a shared
180 static bfd_boolean mips_in_shared
= TRUE
;
182 /* This is the set of options which may be modified by the .set
183 pseudo-op. We use a struct so that .set push and .set pop are more
186 struct mips_set_options
188 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
189 if it has not been initialized. Changed by `.set mipsN', and the
190 -mipsN command line option, and the default CPU. */
192 /* Enabled Application Specific Extensions (ASEs). These are set to -1
193 if they have not been initialized. Changed by `.set <asename>', by
194 command line options, and based on the default architecture. */
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Non-zero if we should not reorder instructions. Changed by `.set
207 reorder' and `.set noreorder'. */
209 /* Non-zero if we should not permit the register designated "assembler
210 temporary" to be used in instructions. The value is the register
211 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
212 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
214 /* Non-zero if we should warn when a macro instruction expands into
215 more than one machine instruction. Changed by `.set nomacro' and
217 int warn_about_macros
;
218 /* Non-zero if we should not move instructions. Changed by `.set
219 move', `.set volatile', `.set nomove', and `.set novolatile'. */
221 /* Non-zero if we should not optimize branches by moving the target
222 of the branch into the delay slot. Actually, we don't perform
223 this optimization anyhow. Changed by `.set bopt' and `.set
226 /* Non-zero if we should not autoextend mips16 instructions.
227 Changed by `.set autoextend' and `.set noautoextend'. */
229 /* Restrict general purpose registers and floating point registers
230 to 32 bit. This is initially determined when -mgp32 or -mfp32
231 is passed but can changed if the assembler code uses .set mipsN. */
234 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
235 command line option, and the default CPU. */
237 /* True if ".set sym32" is in effect. */
239 /* True if floating-point operations are not allowed. Changed by .set
240 softfloat or .set hardfloat, by command line options -msoft-float or
241 -mhard-float. The default is false. */
242 bfd_boolean soft_float
;
244 /* True if only single-precision floating-point operations are allowed.
245 Changed by .set singlefloat or .set doublefloat, command-line options
246 -msingle-float or -mdouble-float. The default is false. */
247 bfd_boolean single_float
;
250 /* This is the struct we use to hold the current set of options. Note
251 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
252 -1 to indicate that they have not been initialized. */
254 /* True if -mgp32 was passed. */
255 static int file_mips_gp32
= -1;
257 /* True if -mfp32 was passed. */
258 static int file_mips_fp32
= -1;
260 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
261 static int file_mips_soft_float
= 0;
263 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
264 static int file_mips_single_float
= 0;
266 static struct mips_set_options mips_opts
=
268 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
269 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
270 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
271 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
272 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
273 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
276 /* These variables are filled in with the masks of registers used.
277 The object format code reads them and puts them in the appropriate
279 unsigned long mips_gprmask
;
280 unsigned long mips_cprmask
[4];
282 /* MIPS ISA we are using for this output file. */
283 static int file_mips_isa
= ISA_UNKNOWN
;
285 /* True if any MIPS16 code was produced. */
286 static int file_ase_mips16
;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if we want to create R_MIPS_JALR for jalr $25. */
295 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
297 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
298 because there's no place for any addend, the only acceptable
299 expression is a bare symbol. */
300 #define MIPS_JALR_HINT_P(EXPR) \
301 (!HAVE_IN_PLACE_ADDENDS \
302 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
305 /* True if -mips3d was passed or implied by arguments passed on the
306 command line (e.g., by -march). */
307 static int file_ase_mips3d
;
309 /* True if -mdmx was passed or implied by arguments passed on the
310 command line (e.g., by -march). */
311 static int file_ase_mdmx
;
313 /* True if -msmartmips was passed or implied by arguments passed on the
314 command line (e.g., by -march). */
315 static int file_ase_smartmips
;
317 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
318 || mips_opts.isa == ISA_MIPS32R2)
320 /* True if -mdsp was passed or implied by arguments passed on the
321 command line (e.g., by -march). */
322 static int file_ase_dsp
;
324 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
325 || mips_opts.isa == ISA_MIPS64R2)
327 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
329 /* True if -mdspr2 was passed or implied by arguments passed on the
330 command line (e.g., by -march). */
331 static int file_ase_dspr2
;
333 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
334 || mips_opts.isa == ISA_MIPS64R2)
336 /* True if -mmt was passed or implied by arguments passed on the
337 command line (e.g., by -march). */
338 static int file_ase_mt
;
340 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
341 || mips_opts.isa == ISA_MIPS64R2)
343 /* The argument of the -march= flag. The architecture we are assembling. */
344 static int file_mips_arch
= CPU_UNKNOWN
;
345 static const char *mips_arch_string
;
347 /* The argument of the -mtune= flag. The architecture for which we
349 static int mips_tune
= CPU_UNKNOWN
;
350 static const char *mips_tune_string
;
352 /* True when generating 32-bit code for a 64-bit processor. */
353 static int mips_32bitmode
= 0;
355 /* True if the given ABI requires 32-bit registers. */
356 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
358 /* Likewise 64-bit registers. */
359 #define ABI_NEEDS_64BIT_REGS(ABI) \
361 || (ABI) == N64_ABI \
364 /* Return true if ISA supports 64 bit wide gp registers. */
365 #define ISA_HAS_64BIT_REGS(ISA) \
366 ((ISA) == ISA_MIPS3 \
367 || (ISA) == ISA_MIPS4 \
368 || (ISA) == ISA_MIPS5 \
369 || (ISA) == ISA_MIPS64 \
370 || (ISA) == ISA_MIPS64R2)
372 /* Return true if ISA supports 64 bit wide float registers. */
373 #define ISA_HAS_64BIT_FPRS(ISA) \
374 ((ISA) == ISA_MIPS3 \
375 || (ISA) == ISA_MIPS4 \
376 || (ISA) == ISA_MIPS5 \
377 || (ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64 \
379 || (ISA) == ISA_MIPS64R2)
381 /* Return true if ISA supports 64-bit right rotate (dror et al.)
383 #define ISA_HAS_DROR(ISA) \
384 ((ISA) == ISA_MIPS64R2)
386 /* Return true if ISA supports 32-bit right rotate (ror et al.)
388 #define ISA_HAS_ROR(ISA) \
389 ((ISA) == ISA_MIPS32R2 \
390 || (ISA) == ISA_MIPS64R2 \
391 || mips_opts.ase_smartmips)
393 /* Return true if ISA supports single-precision floats in odd registers. */
394 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
395 ((ISA) == ISA_MIPS32 \
396 || (ISA) == ISA_MIPS32R2 \
397 || (ISA) == ISA_MIPS64 \
398 || (ISA) == ISA_MIPS64R2)
400 /* Return true if ISA supports move to/from high part of a 64-bit
401 floating-point register. */
402 #define ISA_HAS_MXHC1(ISA) \
403 ((ISA) == ISA_MIPS32R2 \
404 || (ISA) == ISA_MIPS64R2)
406 #define HAVE_32BIT_GPRS \
407 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
409 #define HAVE_32BIT_FPRS \
410 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
412 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
413 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
415 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
417 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
419 /* True if relocations are stored in-place. */
420 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
422 /* The ABI-derived address size. */
423 #define HAVE_64BIT_ADDRESSES \
424 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
425 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
427 /* The size of symbolic constants (i.e., expressions of the form
428 "SYMBOL" or "SYMBOL + OFFSET"). */
429 #define HAVE_32BIT_SYMBOLS \
430 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
431 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
433 /* Addresses are loaded in different ways, depending on the address size
434 in use. The n32 ABI Documentation also mandates the use of additions
435 with overflow checking, but existing implementations don't follow it. */
436 #define ADDRESS_ADD_INSN \
437 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
439 #define ADDRESS_ADDI_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
442 #define ADDRESS_LOAD_INSN \
443 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
445 #define ADDRESS_STORE_INSN \
446 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
448 /* Return true if the given CPU supports the MIPS16 ASE. */
449 #define CPU_HAS_MIPS16(cpu) \
450 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
451 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
453 /* True if CPU has a dror instruction. */
454 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
456 /* True if CPU has a ror instruction. */
457 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
459 /* True if CPU has seq/sne and seqi/snei instructions. */
460 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
462 /* True if CPU does not implement the all the coprocessor insns. For these
463 CPUs only those COP insns are accepted that are explicitly marked to be
464 available on the CPU. ISA membership for COP insns is ignored. */
465 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
467 /* True if mflo and mfhi can be immediately followed by instructions
468 which write to the HI and LO registers.
470 According to MIPS specifications, MIPS ISAs I, II, and III need
471 (at least) two instructions between the reads of HI/LO and
472 instructions which write them, and later ISAs do not. Contradicting
473 the MIPS specifications, some MIPS IV processor user manuals (e.g.
474 the UM for the NEC Vr5000) document needing the instructions between
475 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
476 MIPS64 and later ISAs to have the interlocks, plus any specific
477 earlier-ISA CPUs for which CPU documentation declares that the
478 instructions are really interlocked. */
479 #define hilo_interlocks \
480 (mips_opts.isa == ISA_MIPS32 \
481 || mips_opts.isa == ISA_MIPS32R2 \
482 || mips_opts.isa == ISA_MIPS64 \
483 || mips_opts.isa == ISA_MIPS64R2 \
484 || mips_opts.arch == CPU_R4010 \
485 || mips_opts.arch == CPU_R10000 \
486 || mips_opts.arch == CPU_R12000 \
487 || mips_opts.arch == CPU_R14000 \
488 || mips_opts.arch == CPU_R16000 \
489 || mips_opts.arch == CPU_RM7000 \
490 || mips_opts.arch == CPU_VR5500 \
493 /* Whether the processor uses hardware interlocks to protect reads
494 from the GPRs after they are loaded from memory, and thus does not
495 require nops to be inserted. This applies to instructions marked
496 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
498 #define gpr_interlocks \
499 (mips_opts.isa != ISA_MIPS1 \
500 || mips_opts.arch == CPU_R3900)
502 /* Whether the processor uses hardware interlocks to avoid delays
503 required by coprocessor instructions, and thus does not require
504 nops to be inserted. This applies to instructions marked
505 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
506 between instructions marked INSN_WRITE_COND_CODE and ones marked
507 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
508 levels I, II, and III. */
509 /* Itbl support may require additional care here. */
510 #define cop_interlocks \
511 ((mips_opts.isa != ISA_MIPS1 \
512 && mips_opts.isa != ISA_MIPS2 \
513 && mips_opts.isa != ISA_MIPS3) \
514 || mips_opts.arch == CPU_R4300 \
517 /* Whether the processor uses hardware interlocks to protect reads
518 from coprocessor registers after they are loaded from memory, and
519 thus does not require nops to be inserted. This applies to
520 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
521 requires at MIPS ISA level I. */
522 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
524 /* Is this a mfhi or mflo instruction? */
525 #define MF_HILO_INSN(PINFO) \
526 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
528 /* Returns true for a (non floating-point) coprocessor instruction. Reading
529 or writing the condition code is only possible on the coprocessors and
530 these insns are not marked with INSN_COP. Thus for these insns use the
531 condition-code flags. */
532 #define COP_INSN(PINFO) \
533 (PINFO != INSN_MACRO \
534 && ((PINFO) & (FP_S | FP_D)) == 0 \
535 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
537 /* MIPS PIC level. */
539 enum mips_pic_level mips_pic
;
541 /* 1 if we should generate 32 bit offsets from the $gp register in
542 SVR4_PIC mode. Currently has no meaning in other modes. */
543 static int mips_big_got
= 0;
545 /* 1 if trap instructions should used for overflow rather than break
547 static int mips_trap
= 0;
549 /* 1 if double width floating point constants should not be constructed
550 by assembling two single width halves into two single width floating
551 point registers which just happen to alias the double width destination
552 register. On some architectures this aliasing can be disabled by a bit
553 in the status register, and the setting of this bit cannot be determined
554 automatically at assemble time. */
555 static int mips_disable_float_construction
;
557 /* Non-zero if any .set noreorder directives were used. */
559 static int mips_any_noreorder
;
561 /* Non-zero if nops should be inserted when the register referenced in
562 an mfhi/mflo instruction is read in the next two instructions. */
563 static int mips_7000_hilo_fix
;
565 /* The size of objects in the small data section. */
566 static unsigned int g_switch_value
= 8;
567 /* Whether the -G option was used. */
568 static int g_switch_seen
= 0;
573 /* If we can determine in advance that GP optimization won't be
574 possible, we can skip the relaxation stuff that tries to produce
575 GP-relative references. This makes delay slot optimization work
578 This function can only provide a guess, but it seems to work for
579 gcc output. It needs to guess right for gcc, otherwise gcc
580 will put what it thinks is a GP-relative instruction in a branch
583 I don't know if a fix is needed for the SVR4_PIC mode. I've only
584 fixed it for the non-PIC mode. KR 95/04/07 */
585 static int nopic_need_relax (symbolS
*, int);
587 /* handle of the OPCODE hash table */
588 static struct hash_control
*op_hash
= NULL
;
590 /* The opcode hash table we use for the mips16. */
591 static struct hash_control
*mips16_op_hash
= NULL
;
593 /* This array holds the chars that always start a comment. If the
594 pre-processor is disabled, these aren't very useful */
595 const char comment_chars
[] = "#";
597 /* This array holds the chars that only start a comment at the beginning of
598 a line. If the line seems to have the form '# 123 filename'
599 .line and .file directives will appear in the pre-processed output */
600 /* Note that input_file.c hand checks for '#' at the beginning of the
601 first line of the input file. This is because the compiler outputs
602 #NO_APP at the beginning of its output. */
603 /* Also note that C style comments are always supported. */
604 const char line_comment_chars
[] = "#";
606 /* This array holds machine specific line separator characters. */
607 const char line_separator_chars
[] = ";";
609 /* Chars that can be used to separate mant from exp in floating point nums */
610 const char EXP_CHARS
[] = "eE";
612 /* Chars that mean this number is a floating point constant */
615 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
617 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
618 changed in read.c . Ideally it shouldn't have to know about it at all,
619 but nothing is ideal around here.
622 static char *insn_error
;
624 static int auto_align
= 1;
626 /* When outputting SVR4 PIC code, the assembler needs to know the
627 offset in the stack frame from which to restore the $gp register.
628 This is set by the .cprestore pseudo-op, and saved in this
630 static offsetT mips_cprestore_offset
= -1;
632 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
633 more optimizations, it can use a register value instead of a memory-saved
634 offset and even an other register than $gp as global pointer. */
635 static offsetT mips_cpreturn_offset
= -1;
636 static int mips_cpreturn_register
= -1;
637 static int mips_gp_register
= GP
;
638 static int mips_gprel_offset
= 0;
640 /* Whether mips_cprestore_offset has been set in the current function
641 (or whether it has already been warned about, if not). */
642 static int mips_cprestore_valid
= 0;
644 /* This is the register which holds the stack frame, as set by the
645 .frame pseudo-op. This is needed to implement .cprestore. */
646 static int mips_frame_reg
= SP
;
648 /* Whether mips_frame_reg has been set in the current function
649 (or whether it has already been warned about, if not). */
650 static int mips_frame_reg_valid
= 0;
652 /* To output NOP instructions correctly, we need to keep information
653 about the previous two instructions. */
655 /* Whether we are optimizing. The default value of 2 means to remove
656 unneeded NOPs and swap branch instructions when possible. A value
657 of 1 means to not swap branches. A value of 0 means to always
659 static int mips_optimize
= 2;
661 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
662 equivalent to seeing no -g option at all. */
663 static int mips_debug
= 0;
665 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
666 #define MAX_VR4130_NOPS 4
668 /* The maximum number of NOPs needed to fill delay slots. */
669 #define MAX_DELAY_NOPS 2
671 /* The maximum number of NOPs needed for any purpose. */
674 /* A list of previous instructions, with index 0 being the most recent.
675 We need to look back MAX_NOPS instructions when filling delay slots
676 or working around processor errata. We need to look back one
677 instruction further if we're thinking about using history[0] to
678 fill a branch delay slot. */
679 static struct mips_cl_insn history
[1 + MAX_NOPS
];
681 /* Nop instructions used by emit_nop. */
682 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
684 /* The appropriate nop for the current mode. */
685 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
687 /* If this is set, it points to a frag holding nop instructions which
688 were inserted before the start of a noreorder section. If those
689 nops turn out to be unnecessary, the size of the frag can be
691 static fragS
*prev_nop_frag
;
693 /* The number of nop instructions we created in prev_nop_frag. */
694 static int prev_nop_frag_holds
;
696 /* The number of nop instructions that we know we need in
698 static int prev_nop_frag_required
;
700 /* The number of instructions we've seen since prev_nop_frag. */
701 static int prev_nop_frag_since
;
703 /* For ECOFF and ELF, relocations against symbols are done in two
704 parts, with a HI relocation and a LO relocation. Each relocation
705 has only 16 bits of space to store an addend. This means that in
706 order for the linker to handle carries correctly, it must be able
707 to locate both the HI and the LO relocation. This means that the
708 relocations must appear in order in the relocation table.
710 In order to implement this, we keep track of each unmatched HI
711 relocation. We then sort them so that they immediately precede the
712 corresponding LO relocation. */
717 struct mips_hi_fixup
*next
;
720 /* The section this fixup is in. */
724 /* The list of unmatched HI relocs. */
726 static struct mips_hi_fixup
*mips_hi_fixup_list
;
728 /* The frag containing the last explicit relocation operator.
729 Null if explicit relocations have not been used. */
731 static fragS
*prev_reloc_op_frag
;
733 /* Map normal MIPS register numbers to mips16 register numbers. */
735 #define X ILLEGAL_REG
736 static const int mips32_to_16_reg_map
[] =
738 X
, X
, 2, 3, 4, 5, 6, 7,
739 X
, X
, X
, X
, X
, X
, X
, X
,
740 0, 1, X
, X
, X
, X
, X
, X
,
741 X
, X
, X
, X
, X
, X
, X
, X
745 /* Map mips16 register numbers to normal MIPS register numbers. */
747 static const unsigned int mips16_to_32_reg_map
[] =
749 16, 17, 2, 3, 4, 5, 6, 7
752 /* Classifies the kind of instructions we're interested in when
753 implementing -mfix-vr4120. */
754 enum fix_vr4120_class
762 NUM_FIX_VR4120_CLASSES
765 /* ...likewise -mfix-loongson2f-jump. */
766 static bfd_boolean mips_fix_loongson2f_jump
;
768 /* ...likewise -mfix-loongson2f-nop. */
769 static bfd_boolean mips_fix_loongson2f_nop
;
771 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
772 static bfd_boolean mips_fix_loongson2f
;
774 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
775 there must be at least one other instruction between an instruction
776 of type X and an instruction of type Y. */
777 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
779 /* True if -mfix-vr4120 is in force. */
780 static int mips_fix_vr4120
;
782 /* ...likewise -mfix-vr4130. */
783 static int mips_fix_vr4130
;
785 /* ...likewise -mfix-24k. */
786 static int mips_fix_24k
;
788 /* ...likewise -mfix-cn63xxp1 */
789 static bfd_boolean mips_fix_cn63xxp1
;
791 /* We don't relax branches by default, since this causes us to expand
792 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
793 fail to compute the offset before expanding the macro to the most
794 efficient expansion. */
796 static int mips_relax_branch
;
798 /* The expansion of many macros depends on the type of symbol that
799 they refer to. For example, when generating position-dependent code,
800 a macro that refers to a symbol may have two different expansions,
801 one which uses GP-relative addresses and one which uses absolute
802 addresses. When generating SVR4-style PIC, a macro may have
803 different expansions for local and global symbols.
805 We handle these situations by generating both sequences and putting
806 them in variant frags. In position-dependent code, the first sequence
807 will be the GP-relative one and the second sequence will be the
808 absolute one. In SVR4 PIC, the first sequence will be for global
809 symbols and the second will be for local symbols.
811 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
812 SECOND are the lengths of the two sequences in bytes. These fields
813 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
814 the subtype has the following flags:
817 Set if it has been decided that we should use the second
818 sequence instead of the first.
821 Set in the first variant frag if the macro's second implementation
822 is longer than its first. This refers to the macro as a whole,
823 not an individual relaxation.
826 Set in the first variant frag if the macro appeared in a .set nomacro
827 block and if one alternative requires a warning but the other does not.
830 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
833 The frag's "opcode" points to the first fixup for relaxable code.
835 Relaxable macros are generated using a sequence such as:
837 relax_start (SYMBOL);
838 ... generate first expansion ...
840 ... generate second expansion ...
843 The code and fixups for the unwanted alternative are discarded
844 by md_convert_frag. */
845 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
847 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
848 #define RELAX_SECOND(X) ((X) & 0xff)
849 #define RELAX_USE_SECOND 0x10000
850 #define RELAX_SECOND_LONGER 0x20000
851 #define RELAX_NOMACRO 0x40000
852 #define RELAX_DELAY_SLOT 0x80000
854 /* Branch without likely bit. If label is out of range, we turn:
856 beq reg1, reg2, label
866 with the following opcode replacements:
873 bltzal <-> bgezal (with jal label instead of j label)
875 Even though keeping the delay slot instruction in the delay slot of
876 the branch would be more efficient, it would be very tricky to do
877 correctly, because we'd have to introduce a variable frag *after*
878 the delay slot instruction, and expand that instead. Let's do it
879 the easy way for now, even if the branch-not-taken case now costs
880 one additional instruction. Out-of-range branches are not supposed
881 to be common, anyway.
883 Branch likely. If label is out of range, we turn:
885 beql reg1, reg2, label
886 delay slot (annulled if branch not taken)
895 delay slot (executed only if branch taken)
898 It would be possible to generate a shorter sequence by losing the
899 likely bit, generating something like:
904 delay slot (executed only if branch taken)
916 bltzall -> bgezal (with jal label instead of j label)
917 bgezall -> bltzal (ditto)
920 but it's not clear that it would actually improve performance. */
921 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
925 | ((toofar) ? 0x20 : 0) \
926 | ((link) ? 0x40 : 0) \
927 | ((likely) ? 0x80 : 0) \
928 | ((uncond) ? 0x100 : 0)))
929 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
930 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
931 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
932 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
933 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
934 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
936 /* For mips16 code, we use an entirely different form of relaxation.
937 mips16 supports two versions of most instructions which take
938 immediate values: a small one which takes some small value, and a
939 larger one which takes a 16 bit value. Since branches also follow
940 this pattern, relaxing these values is required.
942 We can assemble both mips16 and normal MIPS code in a single
943 object. Therefore, we need to support this type of relaxation at
944 the same time that we support the relaxation described above. We
945 use the high bit of the subtype field to distinguish these cases.
947 The information we store for this type of relaxation is the
948 argument code found in the opcode file for this relocation, whether
949 the user explicitly requested a small or extended form, and whether
950 the relocation is in a jump or jal delay slot. That tells us the
951 size of the value, and how it should be stored. We also store
952 whether the fragment is considered to be extended or not. We also
953 store whether this is known to be a branch to a different section,
954 whether we have tried to relax this frag yet, and whether we have
955 ever extended a PC relative fragment because of a shift count. */
956 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
959 | ((small) ? 0x100 : 0) \
960 | ((ext) ? 0x200 : 0) \
961 | ((dslot) ? 0x400 : 0) \
962 | ((jal_dslot) ? 0x800 : 0))
963 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
964 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
965 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
966 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
967 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
968 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
969 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
970 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
971 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
972 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
973 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
974 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
976 /* Is the given value a sign-extended 32-bit value? */
977 #define IS_SEXT_32BIT_NUM(x) \
978 (((x) &~ (offsetT) 0x7fffffff) == 0 \
979 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
981 /* Is the given value a sign-extended 16-bit value? */
982 #define IS_SEXT_16BIT_NUM(x) \
983 (((x) &~ (offsetT) 0x7fff) == 0 \
984 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
986 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
987 #define IS_ZEXT_32BIT_NUM(x) \
988 (((x) &~ (offsetT) 0xffffffff) == 0 \
989 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
991 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
992 VALUE << SHIFT. VALUE is evaluated exactly once. */
993 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
994 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
995 | (((VALUE) & (MASK)) << (SHIFT)))
997 /* Extract bits MASK << SHIFT from STRUCT and shift them right
999 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1000 (((STRUCT) >> (SHIFT)) & (MASK))
1002 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1003 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1005 include/opcode/mips.h specifies operand fields using the macros
1006 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1007 with "MIPS16OP" instead of "OP". */
1008 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1009 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1010 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1011 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1012 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1014 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1015 #define EXTRACT_OPERAND(FIELD, INSN) \
1016 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1017 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1018 EXTRACT_BITS ((INSN).insn_opcode, \
1019 MIPS16OP_MASK_##FIELD, \
1020 MIPS16OP_SH_##FIELD)
1022 /* Global variables used when generating relaxable macros. See the
1023 comment above RELAX_ENCODE for more details about how relaxation
1026 /* 0 if we're not emitting a relaxable macro.
1027 1 if we're emitting the first of the two relaxation alternatives.
1028 2 if we're emitting the second alternative. */
1031 /* The first relaxable fixup in the current frag. (In other words,
1032 the first fixup that refers to relaxable code.) */
1035 /* sizes[0] says how many bytes of the first alternative are stored in
1036 the current frag. Likewise sizes[1] for the second alternative. */
1037 unsigned int sizes
[2];
1039 /* The symbol on which the choice of sequence depends. */
1043 /* Global variables used to decide whether a macro needs a warning. */
1045 /* True if the macro is in a branch delay slot. */
1046 bfd_boolean delay_slot_p
;
1048 /* For relaxable macros, sizes[0] is the length of the first alternative
1049 in bytes and sizes[1] is the length of the second alternative.
1050 For non-relaxable macros, both elements give the length of the
1052 unsigned int sizes
[2];
1054 /* The first variant frag for this macro. */
1056 } mips_macro_warning
;
1058 /* Prototypes for static functions. */
1060 #define internalError() \
1061 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1063 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1065 static void append_insn
1066 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*);
1067 static void mips_no_prev_insn (void);
1068 static void macro_build (expressionS
*, const char *, const char *, ...);
1069 static void mips16_macro_build
1070 (expressionS
*, const char *, const char *, va_list *);
1071 static void load_register (int, expressionS
*, int);
1072 static void macro_start (void);
1073 static void macro_end (void);
1074 static void macro (struct mips_cl_insn
* ip
);
1075 static void mips16_macro (struct mips_cl_insn
* ip
);
1076 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1077 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1078 static void mips16_immed
1079 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1080 unsigned long *, bfd_boolean
*, unsigned short *);
1081 static size_t my_getSmallExpression
1082 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1083 static void my_getExpression (expressionS
*, char *);
1084 static void s_align (int);
1085 static void s_change_sec (int);
1086 static void s_change_section (int);
1087 static void s_cons (int);
1088 static void s_float_cons (int);
1089 static void s_mips_globl (int);
1090 static void s_option (int);
1091 static void s_mipsset (int);
1092 static void s_abicalls (int);
1093 static void s_cpload (int);
1094 static void s_cpsetup (int);
1095 static void s_cplocal (int);
1096 static void s_cprestore (int);
1097 static void s_cpreturn (int);
1098 static void s_dtprelword (int);
1099 static void s_dtpreldword (int);
1100 static void s_gpvalue (int);
1101 static void s_gpword (int);
1102 static void s_gpdword (int);
1103 static void s_cpadd (int);
1104 static void s_insn (int);
1105 static void md_obj_begin (void);
1106 static void md_obj_end (void);
1107 static void s_mips_ent (int);
1108 static void s_mips_end (int);
1109 static void s_mips_frame (int);
1110 static void s_mips_mask (int reg_type
);
1111 static void s_mips_stab (int);
1112 static void s_mips_weakext (int);
1113 static void s_mips_file (int);
1114 static void s_mips_loc (int);
1115 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1116 static int relaxed_branch_length (fragS
*, asection
*, int);
1117 static int validate_mips_insn (const struct mips_opcode
*);
1119 /* Table and functions used to map between CPU/ISA names, and
1120 ISA levels, and CPU numbers. */
1122 struct mips_cpu_info
1124 const char *name
; /* CPU or ISA name. */
1125 int flags
; /* ASEs available, or ISA flag. */
1126 int isa
; /* ISA level. */
1127 int cpu
; /* CPU number (default CPU if ISA). */
1130 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1131 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1132 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1133 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1134 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1135 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1136 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1138 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1139 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1140 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1144 The following pseudo-ops from the Kane and Heinrich MIPS book
1145 should be defined here, but are currently unsupported: .alias,
1146 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1148 The following pseudo-ops from the Kane and Heinrich MIPS book are
1149 specific to the type of debugging information being generated, and
1150 should be defined by the object format: .aent, .begin, .bend,
1151 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1154 The following pseudo-ops from the Kane and Heinrich MIPS book are
1155 not MIPS CPU specific, but are also not specific to the object file
1156 format. This file is probably the best place to define them, but
1157 they are not currently supported: .asm0, .endr, .lab, .struct. */
1159 static const pseudo_typeS mips_pseudo_table
[] =
1161 /* MIPS specific pseudo-ops. */
1162 {"option", s_option
, 0},
1163 {"set", s_mipsset
, 0},
1164 {"rdata", s_change_sec
, 'r'},
1165 {"sdata", s_change_sec
, 's'},
1166 {"livereg", s_ignore
, 0},
1167 {"abicalls", s_abicalls
, 0},
1168 {"cpload", s_cpload
, 0},
1169 {"cpsetup", s_cpsetup
, 0},
1170 {"cplocal", s_cplocal
, 0},
1171 {"cprestore", s_cprestore
, 0},
1172 {"cpreturn", s_cpreturn
, 0},
1173 {"dtprelword", s_dtprelword
, 0},
1174 {"dtpreldword", s_dtpreldword
, 0},
1175 {"gpvalue", s_gpvalue
, 0},
1176 {"gpword", s_gpword
, 0},
1177 {"gpdword", s_gpdword
, 0},
1178 {"cpadd", s_cpadd
, 0},
1179 {"insn", s_insn
, 0},
1181 /* Relatively generic pseudo-ops that happen to be used on MIPS
1183 {"asciiz", stringer
, 8 + 1},
1184 {"bss", s_change_sec
, 'b'},
1186 {"half", s_cons
, 1},
1187 {"dword", s_cons
, 3},
1188 {"weakext", s_mips_weakext
, 0},
1189 {"origin", s_org
, 0},
1190 {"repeat", s_rept
, 0},
1192 /* For MIPS this is non-standard, but we define it for consistency. */
1193 {"sbss", s_change_sec
, 'B'},
1195 /* These pseudo-ops are defined in read.c, but must be overridden
1196 here for one reason or another. */
1197 {"align", s_align
, 0},
1198 {"byte", s_cons
, 0},
1199 {"data", s_change_sec
, 'd'},
1200 {"double", s_float_cons
, 'd'},
1201 {"float", s_float_cons
, 'f'},
1202 {"globl", s_mips_globl
, 0},
1203 {"global", s_mips_globl
, 0},
1204 {"hword", s_cons
, 1},
1206 {"long", s_cons
, 2},
1207 {"octa", s_cons
, 4},
1208 {"quad", s_cons
, 3},
1209 {"section", s_change_section
, 0},
1210 {"short", s_cons
, 1},
1211 {"single", s_float_cons
, 'f'},
1212 {"stabn", s_mips_stab
, 'n'},
1213 {"text", s_change_sec
, 't'},
1214 {"word", s_cons
, 2},
1216 { "extern", ecoff_directive_extern
, 0},
1221 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1223 /* These pseudo-ops should be defined by the object file format.
1224 However, a.out doesn't support them, so we have versions here. */
1225 {"aent", s_mips_ent
, 1},
1226 {"bgnb", s_ignore
, 0},
1227 {"end", s_mips_end
, 0},
1228 {"endb", s_ignore
, 0},
1229 {"ent", s_mips_ent
, 0},
1230 {"file", s_mips_file
, 0},
1231 {"fmask", s_mips_mask
, 'F'},
1232 {"frame", s_mips_frame
, 0},
1233 {"loc", s_mips_loc
, 0},
1234 {"mask", s_mips_mask
, 'R'},
1235 {"verstamp", s_ignore
, 0},
1239 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1240 purpose of the `.dc.a' internal pseudo-op. */
1243 mips_address_bytes (void)
1245 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1248 extern void pop_insert (const pseudo_typeS
*);
1251 mips_pop_insert (void)
1253 pop_insert (mips_pseudo_table
);
1254 if (! ECOFF_DEBUGGING
)
1255 pop_insert (mips_nonecoff_pseudo_table
);
1258 /* Symbols labelling the current insn. */
1260 struct insn_label_list
1262 struct insn_label_list
*next
;
1266 static struct insn_label_list
*free_insn_labels
;
1267 #define label_list tc_segment_info_data.labels
1269 static void mips_clear_insn_labels (void);
1272 mips_clear_insn_labels (void)
1274 register struct insn_label_list
**pl
;
1275 segment_info_type
*si
;
1279 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1282 si
= seg_info (now_seg
);
1283 *pl
= si
->label_list
;
1284 si
->label_list
= NULL
;
1289 static char *expr_end
;
1291 /* Expressions which appear in instructions. These are set by
1294 static expressionS imm_expr
;
1295 static expressionS imm2_expr
;
1296 static expressionS offset_expr
;
1298 /* Relocs associated with imm_expr and offset_expr. */
1300 static bfd_reloc_code_real_type imm_reloc
[3]
1301 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1302 static bfd_reloc_code_real_type offset_reloc
[3]
1303 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1305 /* These are set by mips16_ip if an explicit extension is used. */
1307 static bfd_boolean mips16_small
, mips16_ext
;
1310 /* The pdr segment for per procedure frame/regmask info. Not used for
1313 static segT pdr_seg
;
1316 /* The default target format to use. */
1318 #if defined (TE_FreeBSD)
1319 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1320 #elif defined (TE_TMIPS)
1321 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1323 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1327 mips_target_format (void)
1329 switch (OUTPUT_FLAVOR
)
1331 case bfd_target_ecoff_flavour
:
1332 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1333 case bfd_target_coff_flavour
:
1335 case bfd_target_elf_flavour
:
1337 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1338 return (target_big_endian
1339 ? "elf32-bigmips-vxworks"
1340 : "elf32-littlemips-vxworks");
1342 return (target_big_endian
1343 ? (HAVE_64BIT_OBJECTS
1344 ? ELF_TARGET ("elf64-", "big")
1346 ? ELF_TARGET ("elf32-n", "big")
1347 : ELF_TARGET ("elf32-", "big")))
1348 : (HAVE_64BIT_OBJECTS
1349 ? ELF_TARGET ("elf64-", "little")
1351 ? ELF_TARGET ("elf32-n", "little")
1352 : ELF_TARGET ("elf32-", "little"))));
1359 /* Return the length of instruction INSN. */
1361 static inline unsigned int
1362 insn_length (const struct mips_cl_insn
*insn
)
1364 if (!mips_opts
.mips16
)
1366 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1369 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1372 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1377 insn
->use_extend
= FALSE
;
1379 insn
->insn_opcode
= mo
->match
;
1382 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1383 insn
->fixp
[i
] = NULL
;
1384 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1385 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1386 insn
->mips16_absolute_jump_p
= 0;
1389 /* Record the current MIPS16 mode in now_seg. */
1392 mips_record_mips16_mode (void)
1394 segment_info_type
*si
;
1396 si
= seg_info (now_seg
);
1397 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1398 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1401 /* Install INSN at the location specified by its "frag" and "where" fields. */
1404 install_insn (const struct mips_cl_insn
*insn
)
1406 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1407 if (!mips_opts
.mips16
)
1408 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1409 else if (insn
->mips16_absolute_jump_p
)
1411 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1412 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1416 if (insn
->use_extend
)
1418 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1421 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1423 mips_record_mips16_mode ();
1426 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1427 and install the opcode in the new location. */
1430 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1435 insn
->where
= where
;
1436 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1437 if (insn
->fixp
[i
] != NULL
)
1439 insn
->fixp
[i
]->fx_frag
= frag
;
1440 insn
->fixp
[i
]->fx_where
= where
;
1442 install_insn (insn
);
1445 /* Add INSN to the end of the output. */
1448 add_fixed_insn (struct mips_cl_insn
*insn
)
1450 char *f
= frag_more (insn_length (insn
));
1451 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1454 /* Start a variant frag and move INSN to the start of the variant part,
1455 marking it as fixed. The other arguments are as for frag_var. */
1458 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1459 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1461 frag_grow (max_chars
);
1462 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1464 frag_var (rs_machine_dependent
, max_chars
, var
,
1465 subtype
, symbol
, offset
, NULL
);
1468 /* Insert N copies of INSN into the history buffer, starting at
1469 position FIRST. Neither FIRST nor N need to be clipped. */
1472 insert_into_history (unsigned int first
, unsigned int n
,
1473 const struct mips_cl_insn
*insn
)
1475 if (mips_relax
.sequence
!= 2)
1479 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1481 history
[i
] = history
[i
- n
];
1487 /* Emit a nop instruction, recording it in the history buffer. */
1492 add_fixed_insn (NOP_INSN
);
1493 insert_into_history (0, 1, NOP_INSN
);
1496 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1497 the idea is to make it obvious at a glance that each errata is
1501 init_vr4120_conflicts (void)
1503 #define CONFLICT(FIRST, SECOND) \
1504 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1506 /* Errata 21 - [D]DIV[U] after [D]MACC */
1507 CONFLICT (MACC
, DIV
);
1508 CONFLICT (DMACC
, DIV
);
1510 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1511 CONFLICT (DMULT
, DMULT
);
1512 CONFLICT (DMULT
, DMACC
);
1513 CONFLICT (DMACC
, DMULT
);
1514 CONFLICT (DMACC
, DMACC
);
1516 /* Errata 24 - MT{LO,HI} after [D]MACC */
1517 CONFLICT (MACC
, MTHILO
);
1518 CONFLICT (DMACC
, MTHILO
);
1520 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1521 instruction is executed immediately after a MACC or DMACC
1522 instruction, the result of [either instruction] is incorrect." */
1523 CONFLICT (MACC
, MULT
);
1524 CONFLICT (MACC
, DMULT
);
1525 CONFLICT (DMACC
, MULT
);
1526 CONFLICT (DMACC
, DMULT
);
1528 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1529 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1530 DDIV or DDIVU instruction, the result of the MACC or
1531 DMACC instruction is incorrect.". */
1532 CONFLICT (DMULT
, MACC
);
1533 CONFLICT (DMULT
, DMACC
);
1534 CONFLICT (DIV
, MACC
);
1535 CONFLICT (DIV
, DMACC
);
1545 #define RTYPE_MASK 0x1ff00
1546 #define RTYPE_NUM 0x00100
1547 #define RTYPE_FPU 0x00200
1548 #define RTYPE_FCC 0x00400
1549 #define RTYPE_VEC 0x00800
1550 #define RTYPE_GP 0x01000
1551 #define RTYPE_CP0 0x02000
1552 #define RTYPE_PC 0x04000
1553 #define RTYPE_ACC 0x08000
1554 #define RTYPE_CCC 0x10000
1555 #define RNUM_MASK 0x000ff
1556 #define RWARN 0x80000
1558 #define GENERIC_REGISTER_NUMBERS \
1559 {"$0", RTYPE_NUM | 0}, \
1560 {"$1", RTYPE_NUM | 1}, \
1561 {"$2", RTYPE_NUM | 2}, \
1562 {"$3", RTYPE_NUM | 3}, \
1563 {"$4", RTYPE_NUM | 4}, \
1564 {"$5", RTYPE_NUM | 5}, \
1565 {"$6", RTYPE_NUM | 6}, \
1566 {"$7", RTYPE_NUM | 7}, \
1567 {"$8", RTYPE_NUM | 8}, \
1568 {"$9", RTYPE_NUM | 9}, \
1569 {"$10", RTYPE_NUM | 10}, \
1570 {"$11", RTYPE_NUM | 11}, \
1571 {"$12", RTYPE_NUM | 12}, \
1572 {"$13", RTYPE_NUM | 13}, \
1573 {"$14", RTYPE_NUM | 14}, \
1574 {"$15", RTYPE_NUM | 15}, \
1575 {"$16", RTYPE_NUM | 16}, \
1576 {"$17", RTYPE_NUM | 17}, \
1577 {"$18", RTYPE_NUM | 18}, \
1578 {"$19", RTYPE_NUM | 19}, \
1579 {"$20", RTYPE_NUM | 20}, \
1580 {"$21", RTYPE_NUM | 21}, \
1581 {"$22", RTYPE_NUM | 22}, \
1582 {"$23", RTYPE_NUM | 23}, \
1583 {"$24", RTYPE_NUM | 24}, \
1584 {"$25", RTYPE_NUM | 25}, \
1585 {"$26", RTYPE_NUM | 26}, \
1586 {"$27", RTYPE_NUM | 27}, \
1587 {"$28", RTYPE_NUM | 28}, \
1588 {"$29", RTYPE_NUM | 29}, \
1589 {"$30", RTYPE_NUM | 30}, \
1590 {"$31", RTYPE_NUM | 31}
1592 #define FPU_REGISTER_NAMES \
1593 {"$f0", RTYPE_FPU | 0}, \
1594 {"$f1", RTYPE_FPU | 1}, \
1595 {"$f2", RTYPE_FPU | 2}, \
1596 {"$f3", RTYPE_FPU | 3}, \
1597 {"$f4", RTYPE_FPU | 4}, \
1598 {"$f5", RTYPE_FPU | 5}, \
1599 {"$f6", RTYPE_FPU | 6}, \
1600 {"$f7", RTYPE_FPU | 7}, \
1601 {"$f8", RTYPE_FPU | 8}, \
1602 {"$f9", RTYPE_FPU | 9}, \
1603 {"$f10", RTYPE_FPU | 10}, \
1604 {"$f11", RTYPE_FPU | 11}, \
1605 {"$f12", RTYPE_FPU | 12}, \
1606 {"$f13", RTYPE_FPU | 13}, \
1607 {"$f14", RTYPE_FPU | 14}, \
1608 {"$f15", RTYPE_FPU | 15}, \
1609 {"$f16", RTYPE_FPU | 16}, \
1610 {"$f17", RTYPE_FPU | 17}, \
1611 {"$f18", RTYPE_FPU | 18}, \
1612 {"$f19", RTYPE_FPU | 19}, \
1613 {"$f20", RTYPE_FPU | 20}, \
1614 {"$f21", RTYPE_FPU | 21}, \
1615 {"$f22", RTYPE_FPU | 22}, \
1616 {"$f23", RTYPE_FPU | 23}, \
1617 {"$f24", RTYPE_FPU | 24}, \
1618 {"$f25", RTYPE_FPU | 25}, \
1619 {"$f26", RTYPE_FPU | 26}, \
1620 {"$f27", RTYPE_FPU | 27}, \
1621 {"$f28", RTYPE_FPU | 28}, \
1622 {"$f29", RTYPE_FPU | 29}, \
1623 {"$f30", RTYPE_FPU | 30}, \
1624 {"$f31", RTYPE_FPU | 31}
1626 #define FPU_CONDITION_CODE_NAMES \
1627 {"$fcc0", RTYPE_FCC | 0}, \
1628 {"$fcc1", RTYPE_FCC | 1}, \
1629 {"$fcc2", RTYPE_FCC | 2}, \
1630 {"$fcc3", RTYPE_FCC | 3}, \
1631 {"$fcc4", RTYPE_FCC | 4}, \
1632 {"$fcc5", RTYPE_FCC | 5}, \
1633 {"$fcc6", RTYPE_FCC | 6}, \
1634 {"$fcc7", RTYPE_FCC | 7}
1636 #define COPROC_CONDITION_CODE_NAMES \
1637 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1638 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1639 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1640 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1641 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1642 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1643 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1644 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1646 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1647 {"$a4", RTYPE_GP | 8}, \
1648 {"$a5", RTYPE_GP | 9}, \
1649 {"$a6", RTYPE_GP | 10}, \
1650 {"$a7", RTYPE_GP | 11}, \
1651 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1652 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1653 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1654 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1655 {"$t0", RTYPE_GP | 12}, \
1656 {"$t1", RTYPE_GP | 13}, \
1657 {"$t2", RTYPE_GP | 14}, \
1658 {"$t3", RTYPE_GP | 15}
1660 #define O32_SYMBOLIC_REGISTER_NAMES \
1661 {"$t0", RTYPE_GP | 8}, \
1662 {"$t1", RTYPE_GP | 9}, \
1663 {"$t2", RTYPE_GP | 10}, \
1664 {"$t3", RTYPE_GP | 11}, \
1665 {"$t4", RTYPE_GP | 12}, \
1666 {"$t5", RTYPE_GP | 13}, \
1667 {"$t6", RTYPE_GP | 14}, \
1668 {"$t7", RTYPE_GP | 15}, \
1669 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1670 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1671 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1672 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1674 /* Remaining symbolic register names */
1675 #define SYMBOLIC_REGISTER_NAMES \
1676 {"$zero", RTYPE_GP | 0}, \
1677 {"$at", RTYPE_GP | 1}, \
1678 {"$AT", RTYPE_GP | 1}, \
1679 {"$v0", RTYPE_GP | 2}, \
1680 {"$v1", RTYPE_GP | 3}, \
1681 {"$a0", RTYPE_GP | 4}, \
1682 {"$a1", RTYPE_GP | 5}, \
1683 {"$a2", RTYPE_GP | 6}, \
1684 {"$a3", RTYPE_GP | 7}, \
1685 {"$s0", RTYPE_GP | 16}, \
1686 {"$s1", RTYPE_GP | 17}, \
1687 {"$s2", RTYPE_GP | 18}, \
1688 {"$s3", RTYPE_GP | 19}, \
1689 {"$s4", RTYPE_GP | 20}, \
1690 {"$s5", RTYPE_GP | 21}, \
1691 {"$s6", RTYPE_GP | 22}, \
1692 {"$s7", RTYPE_GP | 23}, \
1693 {"$t8", RTYPE_GP | 24}, \
1694 {"$t9", RTYPE_GP | 25}, \
1695 {"$k0", RTYPE_GP | 26}, \
1696 {"$kt0", RTYPE_GP | 26}, \
1697 {"$k1", RTYPE_GP | 27}, \
1698 {"$kt1", RTYPE_GP | 27}, \
1699 {"$gp", RTYPE_GP | 28}, \
1700 {"$sp", RTYPE_GP | 29}, \
1701 {"$s8", RTYPE_GP | 30}, \
1702 {"$fp", RTYPE_GP | 30}, \
1703 {"$ra", RTYPE_GP | 31}
1705 #define MIPS16_SPECIAL_REGISTER_NAMES \
1706 {"$pc", RTYPE_PC | 0}
1708 #define MDMX_VECTOR_REGISTER_NAMES \
1709 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1710 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1711 {"$v2", RTYPE_VEC | 2}, \
1712 {"$v3", RTYPE_VEC | 3}, \
1713 {"$v4", RTYPE_VEC | 4}, \
1714 {"$v5", RTYPE_VEC | 5}, \
1715 {"$v6", RTYPE_VEC | 6}, \
1716 {"$v7", RTYPE_VEC | 7}, \
1717 {"$v8", RTYPE_VEC | 8}, \
1718 {"$v9", RTYPE_VEC | 9}, \
1719 {"$v10", RTYPE_VEC | 10}, \
1720 {"$v11", RTYPE_VEC | 11}, \
1721 {"$v12", RTYPE_VEC | 12}, \
1722 {"$v13", RTYPE_VEC | 13}, \
1723 {"$v14", RTYPE_VEC | 14}, \
1724 {"$v15", RTYPE_VEC | 15}, \
1725 {"$v16", RTYPE_VEC | 16}, \
1726 {"$v17", RTYPE_VEC | 17}, \
1727 {"$v18", RTYPE_VEC | 18}, \
1728 {"$v19", RTYPE_VEC | 19}, \
1729 {"$v20", RTYPE_VEC | 20}, \
1730 {"$v21", RTYPE_VEC | 21}, \
1731 {"$v22", RTYPE_VEC | 22}, \
1732 {"$v23", RTYPE_VEC | 23}, \
1733 {"$v24", RTYPE_VEC | 24}, \
1734 {"$v25", RTYPE_VEC | 25}, \
1735 {"$v26", RTYPE_VEC | 26}, \
1736 {"$v27", RTYPE_VEC | 27}, \
1737 {"$v28", RTYPE_VEC | 28}, \
1738 {"$v29", RTYPE_VEC | 29}, \
1739 {"$v30", RTYPE_VEC | 30}, \
1740 {"$v31", RTYPE_VEC | 31}
1742 #define MIPS_DSP_ACCUMULATOR_NAMES \
1743 {"$ac0", RTYPE_ACC | 0}, \
1744 {"$ac1", RTYPE_ACC | 1}, \
1745 {"$ac2", RTYPE_ACC | 2}, \
1746 {"$ac3", RTYPE_ACC | 3}
1748 static const struct regname reg_names
[] = {
1749 GENERIC_REGISTER_NUMBERS
,
1751 FPU_CONDITION_CODE_NAMES
,
1752 COPROC_CONDITION_CODE_NAMES
,
1754 /* The $txx registers depends on the abi,
1755 these will be added later into the symbol table from
1756 one of the tables below once mips_abi is set after
1757 parsing of arguments from the command line. */
1758 SYMBOLIC_REGISTER_NAMES
,
1760 MIPS16_SPECIAL_REGISTER_NAMES
,
1761 MDMX_VECTOR_REGISTER_NAMES
,
1762 MIPS_DSP_ACCUMULATOR_NAMES
,
1766 static const struct regname reg_names_o32
[] = {
1767 O32_SYMBOLIC_REGISTER_NAMES
,
1771 static const struct regname reg_names_n32n64
[] = {
1772 N32N64_SYMBOLIC_REGISTER_NAMES
,
1777 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1784 /* Find end of name. */
1786 if (is_name_beginner (*e
))
1788 while (is_part_of_name (*e
))
1791 /* Terminate name. */
1795 /* Look for a register symbol. */
1796 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1798 int r
= S_GET_VALUE (symbolP
);
1800 reg
= r
& RNUM_MASK
;
1801 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1802 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1803 reg
= (r
& RNUM_MASK
) - 2;
1805 /* Else see if this is a register defined in an itbl entry. */
1806 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1813 if (itbl_get_reg_val (n
, &r
))
1814 reg
= r
& RNUM_MASK
;
1817 /* Advance to next token if a register was recognised. */
1820 else if (types
& RWARN
)
1821 as_warn (_("Unrecognized register name `%s'"), *s
);
1829 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1830 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1833 is_opcode_valid (const struct mips_opcode
*mo
)
1835 int isa
= mips_opts
.isa
;
1838 if (mips_opts
.ase_mdmx
)
1840 if (mips_opts
.ase_dsp
)
1842 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1844 if (mips_opts
.ase_dspr2
)
1846 if (mips_opts
.ase_mt
)
1848 if (mips_opts
.ase_mips3d
)
1850 if (mips_opts
.ase_smartmips
)
1851 isa
|= INSN_SMARTMIPS
;
1853 /* Don't accept instructions based on the ISA if the CPU does not implement
1854 all the coprocessor insns. */
1855 if (NO_ISA_COP (mips_opts
.arch
)
1856 && COP_INSN (mo
->pinfo
))
1859 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1862 /* Check whether the instruction or macro requires single-precision or
1863 double-precision floating-point support. Note that this information is
1864 stored differently in the opcode table for insns and macros. */
1865 if (mo
->pinfo
== INSN_MACRO
)
1867 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1868 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1872 fp_s
= mo
->pinfo
& FP_S
;
1873 fp_d
= mo
->pinfo
& FP_D
;
1876 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1879 if (fp_s
&& mips_opts
.soft_float
)
1885 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1886 selected ISA and architecture. */
1889 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1891 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1894 /* This function is called once, at assembler startup time. It should set up
1895 all the tables, etc. that the MD part of the assembler will need. */
1900 const char *retval
= NULL
;
1904 if (mips_pic
!= NO_PIC
)
1906 if (g_switch_seen
&& g_switch_value
!= 0)
1907 as_bad (_("-G may not be used in position-independent code"));
1911 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1912 as_warn (_("Could not set architecture and machine"));
1914 op_hash
= hash_new ();
1916 for (i
= 0; i
< NUMOPCODES
;)
1918 const char *name
= mips_opcodes
[i
].name
;
1920 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1923 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1924 mips_opcodes
[i
].name
, retval
);
1925 /* Probably a memory allocation problem? Give up now. */
1926 as_fatal (_("Broken assembler. No assembly attempted."));
1930 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1932 if (!validate_mips_insn (&mips_opcodes
[i
]))
1934 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1936 create_insn (&nop_insn
, mips_opcodes
+ i
);
1937 if (mips_fix_loongson2f_nop
)
1938 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
1939 nop_insn
.fixed_p
= 1;
1944 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1947 mips16_op_hash
= hash_new ();
1950 while (i
< bfd_mips16_num_opcodes
)
1952 const char *name
= mips16_opcodes
[i
].name
;
1954 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1956 as_fatal (_("internal: can't hash `%s': %s"),
1957 mips16_opcodes
[i
].name
, retval
);
1960 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1961 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1962 != mips16_opcodes
[i
].match
))
1964 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1965 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1968 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1970 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1971 mips16_nop_insn
.fixed_p
= 1;
1975 while (i
< bfd_mips16_num_opcodes
1976 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1980 as_fatal (_("Broken assembler. No assembly attempted."));
1982 /* We add all the general register names to the symbol table. This
1983 helps us detect invalid uses of them. */
1984 for (i
= 0; reg_names
[i
].name
; i
++)
1985 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1986 reg_names
[i
].num
, /* & RNUM_MASK, */
1987 &zero_address_frag
));
1989 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1990 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1991 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
1992 &zero_address_frag
));
1994 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1995 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1996 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
1997 &zero_address_frag
));
1999 mips_no_prev_insn ();
2002 mips_cprmask
[0] = 0;
2003 mips_cprmask
[1] = 0;
2004 mips_cprmask
[2] = 0;
2005 mips_cprmask
[3] = 0;
2007 /* set the default alignment for the text section (2**2) */
2008 record_alignment (text_section
, 2);
2010 bfd_set_gp_size (stdoutput
, g_switch_value
);
2015 /* On a native system other than VxWorks, sections must be aligned
2016 to 16 byte boundaries. When configured for an embedded ELF
2017 target, we don't bother. */
2018 if (strncmp (TARGET_OS
, "elf", 3) != 0
2019 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2021 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2022 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2023 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2026 /* Create a .reginfo section for register masks and a .mdebug
2027 section for debugging information. */
2035 subseg
= now_subseg
;
2037 /* The ABI says this section should be loaded so that the
2038 running program can access it. However, we don't load it
2039 if we are configured for an embedded target */
2040 flags
= SEC_READONLY
| SEC_DATA
;
2041 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2042 flags
|= SEC_ALLOC
| SEC_LOAD
;
2044 if (mips_abi
!= N64_ABI
)
2046 sec
= subseg_new (".reginfo", (subsegT
) 0);
2048 bfd_set_section_flags (stdoutput
, sec
, flags
);
2049 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2051 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2055 /* The 64-bit ABI uses a .MIPS.options section rather than
2056 .reginfo section. */
2057 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2058 bfd_set_section_flags (stdoutput
, sec
, flags
);
2059 bfd_set_section_alignment (stdoutput
, sec
, 3);
2061 /* Set up the option header. */
2063 Elf_Internal_Options opthdr
;
2066 opthdr
.kind
= ODK_REGINFO
;
2067 opthdr
.size
= (sizeof (Elf_External_Options
)
2068 + sizeof (Elf64_External_RegInfo
));
2071 f
= frag_more (sizeof (Elf_External_Options
));
2072 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2073 (Elf_External_Options
*) f
);
2075 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2079 if (ECOFF_DEBUGGING
)
2081 sec
= subseg_new (".mdebug", (subsegT
) 0);
2082 (void) bfd_set_section_flags (stdoutput
, sec
,
2083 SEC_HAS_CONTENTS
| SEC_READONLY
);
2084 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2086 else if (mips_flag_pdr
)
2088 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2089 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2090 SEC_READONLY
| SEC_RELOC
2092 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2095 subseg_set (seg
, subseg
);
2098 #endif /* OBJ_ELF */
2100 if (! ECOFF_DEBUGGING
)
2103 if (mips_fix_vr4120
)
2104 init_vr4120_conflicts ();
2110 if (! ECOFF_DEBUGGING
)
2115 md_assemble (char *str
)
2117 struct mips_cl_insn insn
;
2118 bfd_reloc_code_real_type unused_reloc
[3]
2119 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2121 imm_expr
.X_op
= O_absent
;
2122 imm2_expr
.X_op
= O_absent
;
2123 offset_expr
.X_op
= O_absent
;
2124 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2125 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2126 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2127 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2128 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2129 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2131 if (mips_opts
.mips16
)
2132 mips16_ip (str
, &insn
);
2135 mips_ip (str
, &insn
);
2136 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2137 str
, insn
.insn_opcode
));
2142 as_bad ("%s `%s'", insn_error
, str
);
2146 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2149 if (mips_opts
.mips16
)
2150 mips16_macro (&insn
);
2157 if (imm_expr
.X_op
!= O_absent
)
2158 append_insn (&insn
, &imm_expr
, imm_reloc
);
2159 else if (offset_expr
.X_op
!= O_absent
)
2160 append_insn (&insn
, &offset_expr
, offset_reloc
);
2162 append_insn (&insn
, NULL
, unused_reloc
);
2166 /* Convenience functions for abstracting away the differences between
2167 MIPS16 and non-MIPS16 relocations. */
2169 static inline bfd_boolean
2170 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2174 case BFD_RELOC_MIPS16_JMP
:
2175 case BFD_RELOC_MIPS16_GPREL
:
2176 case BFD_RELOC_MIPS16_GOT16
:
2177 case BFD_RELOC_MIPS16_CALL16
:
2178 case BFD_RELOC_MIPS16_HI16_S
:
2179 case BFD_RELOC_MIPS16_HI16
:
2180 case BFD_RELOC_MIPS16_LO16
:
2188 static inline bfd_boolean
2189 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2191 return reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
;
2194 static inline bfd_boolean
2195 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2197 return reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
;
2200 static inline bfd_boolean
2201 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2203 return reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
;
2206 /* Return true if the given relocation might need a matching %lo().
2207 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2208 need a matching %lo() when applied to local symbols. */
2210 static inline bfd_boolean
2211 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2213 return (HAVE_IN_PLACE_ADDENDS
2214 && (hi16_reloc_p (reloc
)
2215 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2216 all GOT16 relocations evaluate to "G". */
2217 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2220 /* Return the type of %lo() reloc needed by RELOC, given that
2221 reloc_needs_lo_p. */
2223 static inline bfd_reloc_code_real_type
2224 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2226 return mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
: BFD_RELOC_LO16
;
2229 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2232 static inline bfd_boolean
2233 fixup_has_matching_lo_p (fixS
*fixp
)
2235 return (fixp
->fx_next
!= NULL
2236 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2237 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2238 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2241 /* See whether instruction IP reads register REG. CLASS is the type
2245 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2246 enum mips_regclass regclass
)
2248 if (regclass
== MIPS16_REG
)
2250 gas_assert (mips_opts
.mips16
);
2251 reg
= mips16_to_32_reg_map
[reg
];
2252 regclass
= MIPS_GR_REG
;
2255 /* Don't report on general register ZERO, since it never changes. */
2256 if (regclass
== MIPS_GR_REG
&& reg
== ZERO
)
2259 if (regclass
== MIPS_FP_REG
)
2261 gas_assert (! mips_opts
.mips16
);
2262 /* If we are called with either $f0 or $f1, we must check $f0.
2263 This is not optimal, because it will introduce an unnecessary
2264 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2265 need to distinguish reading both $f0 and $f1 or just one of
2266 them. Note that we don't have to check the other way,
2267 because there is no instruction that sets both $f0 and $f1
2268 and requires a delay. */
2269 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2270 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2271 == (reg
&~ (unsigned) 1)))
2273 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2274 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2275 == (reg
&~ (unsigned) 1)))
2277 if ((ip
->insn_mo
->pinfo2
& INSN2_READ_FPR_Z
)
2278 && ((EXTRACT_OPERAND (FZ
, *ip
) & ~(unsigned) 1)
2279 == (reg
&~ (unsigned) 1)))
2282 else if (! mips_opts
.mips16
)
2284 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2285 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2287 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2288 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2290 if ((ip
->insn_mo
->pinfo2
& INSN2_READ_GPR_D
)
2291 && EXTRACT_OPERAND (RD
, *ip
) == reg
)
2293 if ((ip
->insn_mo
->pinfo2
& INSN2_READ_GPR_Z
)
2294 && EXTRACT_OPERAND (RZ
, *ip
) == reg
)
2299 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2300 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2302 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2303 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2305 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2306 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2309 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2311 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2313 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2315 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2316 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2323 /* This function returns true if modifying a register requires a
2327 reg_needs_delay (unsigned int reg
)
2329 unsigned long prev_pinfo
;
2331 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2332 if (! mips_opts
.noreorder
2333 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2334 && ! gpr_interlocks
)
2335 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2336 && ! cop_interlocks
)))
2338 /* A load from a coprocessor or from memory. All load delays
2339 delay the use of general register rt for one instruction. */
2340 /* Itbl support may require additional care here. */
2341 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2342 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2349 /* Move all labels in insn_labels to the current insertion point. */
2352 mips_move_labels (void)
2354 segment_info_type
*si
= seg_info (now_seg
);
2355 struct insn_label_list
*l
;
2358 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2360 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2361 symbol_set_frag (l
->label
, frag_now
);
2362 val
= (valueT
) frag_now_fix ();
2363 /* mips16 text labels are stored as odd. */
2364 if (mips_opts
.mips16
)
2366 S_SET_VALUE (l
->label
, val
);
2371 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2373 bfd_boolean linkonce
= FALSE
;
2374 segT symseg
= S_GET_SEGMENT (sym
);
2376 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2378 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2381 /* The GNU toolchain uses an extension for ELF: a section
2382 beginning with the magic string .gnu.linkonce is a
2383 linkonce section. */
2384 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2385 sizeof ".gnu.linkonce" - 1) == 0)
2392 /* Mark instruction labels in mips16 mode. This permits the linker to
2393 handle them specially, such as generating jalx instructions when
2394 needed. We also make them odd for the duration of the assembly, in
2395 order to generate the right sort of code. We will make them even
2396 in the adjust_symtab routine, while leaving them marked. This is
2397 convenient for the debugger and the disassembler. The linker knows
2398 to make them odd again. */
2401 mips16_mark_labels (void)
2403 segment_info_type
*si
= seg_info (now_seg
);
2404 struct insn_label_list
*l
;
2406 if (!mips_opts
.mips16
)
2409 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2411 symbolS
*label
= l
->label
;
2413 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2415 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2417 if ((S_GET_VALUE (label
) & 1) == 0
2418 /* Don't adjust the address if the label is global or weak, or
2419 in a link-once section, since we'll be emitting symbol reloc
2420 references to it which will be patched up by the linker, and
2421 the final value of the symbol may or may not be MIPS16. */
2422 && ! S_IS_WEAK (label
)
2423 && ! S_IS_EXTERNAL (label
)
2424 && ! s_is_linkonce (label
, now_seg
))
2425 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2429 /* End the current frag. Make it a variant frag and record the
2433 relax_close_frag (void)
2435 mips_macro_warning
.first_frag
= frag_now
;
2436 frag_var (rs_machine_dependent
, 0, 0,
2437 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2438 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2440 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2441 mips_relax
.first_fixup
= 0;
2444 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2445 See the comment above RELAX_ENCODE for more details. */
2448 relax_start (symbolS
*symbol
)
2450 gas_assert (mips_relax
.sequence
== 0);
2451 mips_relax
.sequence
= 1;
2452 mips_relax
.symbol
= symbol
;
2455 /* Start generating the second version of a relaxable sequence.
2456 See the comment above RELAX_ENCODE for more details. */
2461 gas_assert (mips_relax
.sequence
== 1);
2462 mips_relax
.sequence
= 2;
2465 /* End the current relaxable sequence. */
2470 gas_assert (mips_relax
.sequence
== 2);
2471 relax_close_frag ();
2472 mips_relax
.sequence
= 0;
2475 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2476 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2477 by VR4120 errata. */
2480 classify_vr4120_insn (const char *name
)
2482 if (strncmp (name
, "macc", 4) == 0)
2483 return FIX_VR4120_MACC
;
2484 if (strncmp (name
, "dmacc", 5) == 0)
2485 return FIX_VR4120_DMACC
;
2486 if (strncmp (name
, "mult", 4) == 0)
2487 return FIX_VR4120_MULT
;
2488 if (strncmp (name
, "dmult", 5) == 0)
2489 return FIX_VR4120_DMULT
;
2490 if (strstr (name
, "div"))
2491 return FIX_VR4120_DIV
;
2492 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2493 return FIX_VR4120_MTHILO
;
2494 return NUM_FIX_VR4120_CLASSES
;
2497 #define INSN_ERET 0x42000018
2498 #define INSN_DERET 0x4200001f
2500 /* Return the number of instructions that must separate INSN1 and INSN2,
2501 where INSN1 is the earlier instruction. Return the worst-case value
2502 for any INSN2 if INSN2 is null. */
2505 insns_between (const struct mips_cl_insn
*insn1
,
2506 const struct mips_cl_insn
*insn2
)
2508 unsigned long pinfo1
, pinfo2
;
2510 /* This function needs to know which pinfo flags are set for INSN2
2511 and which registers INSN2 uses. The former is stored in PINFO2 and
2512 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2513 will have every flag set and INSN2_USES_REG will always return true. */
2514 pinfo1
= insn1
->insn_mo
->pinfo
;
2515 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2517 #define INSN2_USES_REG(REG, CLASS) \
2518 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2520 /* For most targets, write-after-read dependencies on the HI and LO
2521 registers must be separated by at least two instructions. */
2522 if (!hilo_interlocks
)
2524 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2526 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2530 /* If we're working around r7000 errata, there must be two instructions
2531 between an mfhi or mflo and any instruction that uses the result. */
2532 if (mips_7000_hilo_fix
2533 && MF_HILO_INSN (pinfo1
)
2534 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2537 /* If we're working around 24K errata, one instruction is required
2538 if an ERET or DERET is followed by a branch instruction. */
2541 if (insn1
->insn_opcode
== INSN_ERET
2542 || insn1
->insn_opcode
== INSN_DERET
)
2545 || insn2
->insn_opcode
== INSN_ERET
2546 || insn2
->insn_opcode
== INSN_DERET
2547 || (insn2
->insn_mo
->pinfo
2548 & (INSN_UNCOND_BRANCH_DELAY
2549 | INSN_COND_BRANCH_DELAY
2550 | INSN_COND_BRANCH_LIKELY
)) != 0)
2555 /* If working around VR4120 errata, check for combinations that need
2556 a single intervening instruction. */
2557 if (mips_fix_vr4120
)
2559 unsigned int class1
, class2
;
2561 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2562 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2566 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2567 if (vr4120_conflicts
[class1
] & (1 << class2
))
2572 if (!mips_opts
.mips16
)
2574 /* Check for GPR or coprocessor load delays. All such delays
2575 are on the RT register. */
2576 /* Itbl support may require additional care here. */
2577 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2578 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2580 know (pinfo1
& INSN_WRITE_GPR_T
);
2581 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2585 /* Check for generic coprocessor hazards.
2587 This case is not handled very well. There is no special
2588 knowledge of CP0 handling, and the coprocessors other than
2589 the floating point unit are not distinguished at all. */
2590 /* Itbl support may require additional care here. FIXME!
2591 Need to modify this to include knowledge about
2592 user specified delays! */
2593 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2594 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2596 /* Handle cases where INSN1 writes to a known general coprocessor
2597 register. There must be a one instruction delay before INSN2
2598 if INSN2 reads that register, otherwise no delay is needed. */
2599 if (pinfo1
& INSN_WRITE_FPR_T
)
2601 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2604 else if (pinfo1
& INSN_WRITE_FPR_S
)
2606 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2611 /* Read-after-write dependencies on the control registers
2612 require a two-instruction gap. */
2613 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2614 && (pinfo2
& INSN_READ_COND_CODE
))
2617 /* We don't know exactly what INSN1 does. If INSN2 is
2618 also a coprocessor instruction, assume there must be
2619 a one instruction gap. */
2620 if (pinfo2
& INSN_COP
)
2625 /* Check for read-after-write dependencies on the coprocessor
2626 control registers in cases where INSN1 does not need a general
2627 coprocessor delay. This means that INSN1 is a floating point
2628 comparison instruction. */
2629 /* Itbl support may require additional care here. */
2630 else if (!cop_interlocks
2631 && (pinfo1
& INSN_WRITE_COND_CODE
)
2632 && (pinfo2
& INSN_READ_COND_CODE
))
2636 #undef INSN2_USES_REG
2641 /* Return the number of nops that would be needed to work around the
2642 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2643 the MAX_VR4130_NOPS instructions described by HIST. */
2646 nops_for_vr4130 (const struct mips_cl_insn
*hist
,
2647 const struct mips_cl_insn
*insn
)
2651 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2652 are not affected by the errata. */
2654 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2655 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2656 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2659 /* Search for the first MFLO or MFHI. */
2660 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2661 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
2663 /* Extract the destination register. */
2664 if (mips_opts
.mips16
)
2665 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, hist
[i
])];
2667 reg
= EXTRACT_OPERAND (RD
, hist
[i
]);
2669 /* No nops are needed if INSN reads that register. */
2670 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2673 /* ...or if any of the intervening instructions do. */
2674 for (j
= 0; j
< i
; j
++)
2675 if (insn_uses_reg (&hist
[j
], reg
, MIPS_GR_REG
))
2678 return MAX_VR4130_NOPS
- i
;
2683 /* Return the number of nops that would be needed if instruction INSN
2684 immediately followed the MAX_NOPS instructions given by HIST,
2685 where HIST[0] is the most recent instruction. If INSN is null,
2686 return the worse-case number of nops for any instruction. */
2689 nops_for_insn (const struct mips_cl_insn
*hist
,
2690 const struct mips_cl_insn
*insn
)
2692 int i
, nops
, tmp_nops
;
2695 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2697 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
2698 if (tmp_nops
> nops
)
2702 if (mips_fix_vr4130
)
2704 tmp_nops
= nops_for_vr4130 (hist
, insn
);
2705 if (tmp_nops
> nops
)
2712 /* The variable arguments provide NUM_INSNS extra instructions that
2713 might be added to HIST. Return the largest number of nops that
2714 would be needed after the extended sequence. */
2717 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*hist
, ...)
2720 struct mips_cl_insn buffer
[MAX_NOPS
];
2721 struct mips_cl_insn
*cursor
;
2724 va_start (args
, hist
);
2725 cursor
= buffer
+ num_insns
;
2726 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2727 while (cursor
> buffer
)
2728 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2730 nops
= nops_for_insn (buffer
, NULL
);
2735 /* Like nops_for_insn, but if INSN is a branch, take into account the
2736 worst-case delay for the branch target. */
2739 nops_for_insn_or_target (const struct mips_cl_insn
*hist
,
2740 const struct mips_cl_insn
*insn
)
2744 nops
= nops_for_insn (hist
, insn
);
2745 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2746 | INSN_COND_BRANCH_DELAY
2747 | INSN_COND_BRANCH_LIKELY
))
2749 tmp_nops
= nops_for_sequence (2, hist
, insn
, NOP_INSN
);
2750 if (tmp_nops
> nops
)
2753 else if (mips_opts
.mips16
2754 && (insn
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2755 | MIPS16_INSN_COND_BRANCH
)))
2757 tmp_nops
= nops_for_sequence (1, hist
, insn
);
2758 if (tmp_nops
> nops
)
2764 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2767 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
2769 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
2770 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
2773 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2774 jr target pc &= 'hffff_ffff_cfff_ffff. */
2777 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
2779 if (strcmp (ip
->insn_mo
->name
, "j") == 0
2780 || strcmp (ip
->insn_mo
->name
, "jr") == 0
2781 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
2789 sreg
= EXTRACT_OPERAND (RS
, *ip
);
2790 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
2793 ep
.X_op
= O_constant
;
2794 ep
.X_add_number
= 0xcfff0000;
2795 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
2796 ep
.X_add_number
= 0xffff;
2797 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
2798 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
2803 fix_loongson2f (struct mips_cl_insn
* ip
)
2805 if (mips_fix_loongson2f_nop
)
2806 fix_loongson2f_nop (ip
);
2808 if (mips_fix_loongson2f_jump
)
2809 fix_loongson2f_jump (ip
);
2812 /* Output an instruction. IP is the instruction information.
2813 ADDRESS_EXPR is an operand of the instruction to be used with
2817 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2818 bfd_reloc_code_real_type
*reloc_type
)
2820 unsigned long prev_pinfo
, pinfo
;
2821 unsigned long prev_pinfo2
, pinfo2
;
2822 relax_stateT prev_insn_frag_type
= 0;
2823 bfd_boolean relaxed_branch
= FALSE
;
2824 segment_info_type
*si
= seg_info (now_seg
);
2826 if (mips_fix_loongson2f
)
2827 fix_loongson2f (ip
);
2829 /* Mark instruction labels in mips16 mode. */
2830 mips16_mark_labels ();
2832 file_ase_mips16
|= mips_opts
.mips16
;
2834 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2835 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
2836 pinfo
= ip
->insn_mo
->pinfo
;
2837 pinfo2
= ip
->insn_mo
->pinfo2
;
2839 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2841 /* There are a lot of optimizations we could do that we don't.
2842 In particular, we do not, in general, reorder instructions.
2843 If you use gcc with optimization, it will reorder
2844 instructions and generally do much more optimization then we
2845 do here; repeating all that work in the assembler would only
2846 benefit hand written assembly code, and does not seem worth
2848 int nops
= (mips_optimize
== 0
2849 ? nops_for_insn (history
, NULL
)
2850 : nops_for_insn_or_target (history
, ip
));
2854 unsigned long old_frag_offset
;
2857 old_frag
= frag_now
;
2858 old_frag_offset
= frag_now_fix ();
2860 for (i
= 0; i
< nops
; i
++)
2865 listing_prev_line ();
2866 /* We may be at the start of a variant frag. In case we
2867 are, make sure there is enough space for the frag
2868 after the frags created by listing_prev_line. The
2869 argument to frag_grow here must be at least as large
2870 as the argument to all other calls to frag_grow in
2871 this file. We don't have to worry about being in the
2872 middle of a variant frag, because the variants insert
2873 all needed nop instructions themselves. */
2877 mips_move_labels ();
2879 #ifndef NO_ECOFF_DEBUGGING
2880 if (ECOFF_DEBUGGING
)
2881 ecoff_fix_loc (old_frag
, old_frag_offset
);
2885 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2887 /* Work out how many nops in prev_nop_frag are needed by IP. */
2888 int nops
= nops_for_insn_or_target (history
, ip
);
2889 gas_assert (nops
<= prev_nop_frag_holds
);
2891 /* Enforce NOPS as a minimum. */
2892 if (nops
> prev_nop_frag_required
)
2893 prev_nop_frag_required
= nops
;
2895 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2897 /* Settle for the current number of nops. Update the history
2898 accordingly (for the benefit of any future .set reorder code). */
2899 prev_nop_frag
= NULL
;
2900 insert_into_history (prev_nop_frag_since
,
2901 prev_nop_frag_holds
, NOP_INSN
);
2905 /* Allow this instruction to replace one of the nops that was
2906 tentatively added to prev_nop_frag. */
2907 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2908 prev_nop_frag_holds
--;
2909 prev_nop_frag_since
++;
2914 /* The value passed to dwarf2_emit_insn is the distance between
2915 the beginning of the current instruction and the address that
2916 should be recorded in the debug tables. For MIPS16 debug info
2917 we want to use ISA-encoded addresses, so we pass -1 for an
2918 address higher by one than the current. */
2919 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2922 /* Record the frag type before frag_var. */
2923 if (history
[0].frag
)
2924 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2927 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2928 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2929 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2930 && mips_relax_branch
2931 /* Don't try branch relaxation within .set nomacro, or within
2932 .set noat if we use $at for PIC computations. If it turns
2933 out that the branch was out-of-range, we'll get an error. */
2934 && !mips_opts
.warn_about_macros
2935 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
2936 && !mips_opts
.mips16
)
2938 relaxed_branch
= TRUE
;
2939 add_relaxed_insn (ip
, (relaxed_branch_length
2941 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2942 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2946 pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2947 pinfo
& INSN_COND_BRANCH_LIKELY
,
2948 pinfo
& INSN_WRITE_GPR_31
,
2950 address_expr
->X_add_symbol
,
2951 address_expr
->X_add_number
);
2952 *reloc_type
= BFD_RELOC_UNUSED
;
2954 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2956 /* We need to set up a variant frag. */
2957 gas_assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2958 add_relaxed_insn (ip
, 4, 0,
2960 (*reloc_type
- BFD_RELOC_UNUSED
,
2961 mips16_small
, mips16_ext
,
2962 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2963 history
[0].mips16_absolute_jump_p
),
2964 make_expr_symbol (address_expr
), 0);
2966 else if (mips_opts
.mips16
2968 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2970 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2971 /* Make sure there is enough room to swap this instruction with
2972 a following jump instruction. */
2974 add_fixed_insn (ip
);
2978 if (mips_opts
.mips16
2979 && mips_opts
.noreorder
2980 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2981 as_warn (_("extended instruction in delay slot"));
2983 if (mips_relax
.sequence
)
2985 /* If we've reached the end of this frag, turn it into a variant
2986 frag and record the information for the instructions we've
2988 if (frag_room () < 4)
2989 relax_close_frag ();
2990 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2993 if (mips_relax
.sequence
!= 2)
2994 mips_macro_warning
.sizes
[0] += 4;
2995 if (mips_relax
.sequence
!= 1)
2996 mips_macro_warning
.sizes
[1] += 4;
2998 if (mips_opts
.mips16
)
3001 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
3003 add_fixed_insn (ip
);
3006 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
3008 if (address_expr
->X_op
== O_constant
)
3012 switch (*reloc_type
)
3015 ip
->insn_opcode
|= address_expr
->X_add_number
;
3018 case BFD_RELOC_MIPS_HIGHEST
:
3019 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
3020 ip
->insn_opcode
|= tmp
& 0xffff;
3023 case BFD_RELOC_MIPS_HIGHER
:
3024 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
3025 ip
->insn_opcode
|= tmp
& 0xffff;
3028 case BFD_RELOC_HI16_S
:
3029 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
3030 ip
->insn_opcode
|= tmp
& 0xffff;
3033 case BFD_RELOC_HI16
:
3034 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
3037 case BFD_RELOC_UNUSED
:
3038 case BFD_RELOC_LO16
:
3039 case BFD_RELOC_MIPS_GOT_DISP
:
3040 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
3043 case BFD_RELOC_MIPS_JMP
:
3044 if ((address_expr
->X_add_number
& 3) != 0)
3045 as_bad (_("jump to misaligned address (0x%lx)"),
3046 (unsigned long) address_expr
->X_add_number
);
3047 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
3050 case BFD_RELOC_MIPS16_JMP
:
3051 if ((address_expr
->X_add_number
& 3) != 0)
3052 as_bad (_("jump to misaligned address (0x%lx)"),
3053 (unsigned long) address_expr
->X_add_number
);
3055 (((address_expr
->X_add_number
& 0x7c0000) << 3)
3056 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
3057 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
3060 case BFD_RELOC_16_PCREL_S2
:
3061 if ((address_expr
->X_add_number
& 3) != 0)
3062 as_bad (_("branch to misaligned address (0x%lx)"),
3063 (unsigned long) address_expr
->X_add_number
);
3064 if (mips_relax_branch
)
3066 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
3067 as_bad (_("branch address range overflow (0x%lx)"),
3068 (unsigned long) address_expr
->X_add_number
);
3069 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
3076 else if (*reloc_type
< BFD_RELOC_UNUSED
)
3079 reloc_howto_type
*howto
;
3082 /* In a compound relocation, it is the final (outermost)
3083 operator that determines the relocated field. */
3084 for (i
= 1; i
< 3; i
++)
3085 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
3088 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
3091 /* To reproduce this failure try assembling gas/testsuites/
3092 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3094 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type
[i
- 1]);
3095 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
3098 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
3099 bfd_get_reloc_size (howto
),
3101 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
3104 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3105 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
3106 && ip
->fixp
[0]->fx_addsy
)
3107 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
3109 /* These relocations can have an addend that won't fit in
3110 4 octets for 64bit assembly. */
3112 && ! howto
->partial_inplace
3113 && (reloc_type
[0] == BFD_RELOC_16
3114 || reloc_type
[0] == BFD_RELOC_32
3115 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
3116 || reloc_type
[0] == BFD_RELOC_GPREL16
3117 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
3118 || reloc_type
[0] == BFD_RELOC_GPREL32
3119 || reloc_type
[0] == BFD_RELOC_64
3120 || reloc_type
[0] == BFD_RELOC_CTOR
3121 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
3122 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
3123 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
3124 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
3125 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
3126 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
3127 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
3128 || hi16_reloc_p (reloc_type
[0])
3129 || lo16_reloc_p (reloc_type
[0])))
3130 ip
->fixp
[0]->fx_no_overflow
= 1;
3132 if (mips_relax
.sequence
)
3134 if (mips_relax
.first_fixup
== 0)
3135 mips_relax
.first_fixup
= ip
->fixp
[0];
3137 else if (reloc_needs_lo_p (*reloc_type
))
3139 struct mips_hi_fixup
*hi_fixup
;
3141 /* Reuse the last entry if it already has a matching %lo. */
3142 hi_fixup
= mips_hi_fixup_list
;
3144 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
3146 hi_fixup
= ((struct mips_hi_fixup
*)
3147 xmalloc (sizeof (struct mips_hi_fixup
)));
3148 hi_fixup
->next
= mips_hi_fixup_list
;
3149 mips_hi_fixup_list
= hi_fixup
;
3151 hi_fixup
->fixp
= ip
->fixp
[0];
3152 hi_fixup
->seg
= now_seg
;
3155 /* Add fixups for the second and third relocations, if given.
3156 Note that the ABI allows the second relocation to be
3157 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3158 moment we only use RSS_UNDEF, but we could add support
3159 for the others if it ever becomes necessary. */
3160 for (i
= 1; i
< 3; i
++)
3161 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
3163 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
3164 ip
->fixp
[0]->fx_size
, NULL
, 0,
3165 FALSE
, reloc_type
[i
]);
3167 /* Use fx_tcbit to mark compound relocs. */
3168 ip
->fixp
[0]->fx_tcbit
= 1;
3169 ip
->fixp
[i
]->fx_tcbit
= 1;
3175 /* Update the register mask information. */
3176 if (! mips_opts
.mips16
)
3178 if ((pinfo
& INSN_WRITE_GPR_D
) || (pinfo2
& INSN2_READ_GPR_D
))
3179 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
3180 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
3181 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
3182 if (pinfo
& INSN_READ_GPR_S
)
3183 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
3184 if (pinfo
& INSN_WRITE_GPR_31
)
3185 mips_gprmask
|= 1 << RA
;
3186 if (pinfo2
& (INSN2_WRITE_GPR_Z
| INSN2_READ_GPR_Z
))
3187 mips_gprmask
|= 1 << EXTRACT_OPERAND (RZ
, *ip
);
3188 if (pinfo
& INSN_WRITE_FPR_D
)
3189 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
3190 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
3191 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
3192 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
3193 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
3194 if ((pinfo
& INSN_READ_FPR_R
) != 0)
3195 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
3196 if (pinfo2
& (INSN2_WRITE_FPR_Z
| INSN2_READ_FPR_Z
))
3197 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FZ
, *ip
);
3198 if (pinfo
& INSN_COP
)
3200 /* We don't keep enough information to sort these cases out.
3201 The itbl support does keep this information however, although
3202 we currently don't support itbl fprmats as part of the cop
3203 instruction. May want to add this support in the future. */
3205 /* Never set the bit for $0, which is always zero. */
3206 mips_gprmask
&= ~1 << 0;
3210 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
3211 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
3212 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
3213 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
3214 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3215 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
3216 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
3217 mips_gprmask
|= 1 << TREG
;
3218 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
3219 mips_gprmask
|= 1 << SP
;
3220 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
3221 mips_gprmask
|= 1 << RA
;
3222 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3223 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3224 if (pinfo
& MIPS16_INSN_READ_Z
)
3225 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
3226 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3227 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3230 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3232 /* Filling the branch delay slot is more complex. We try to
3233 switch the branch with the previous instruction, which we can
3234 do if the previous instruction does not set up a condition
3235 that the branch tests and if the branch is not itself the
3236 target of any branch. */
3237 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3238 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3240 if (mips_optimize
< 2
3241 /* If we have seen .set volatile or .set nomove, don't
3243 || mips_opts
.nomove
!= 0
3244 /* We can't swap if the previous instruction's position
3246 || history
[0].fixed_p
3247 /* If the previous previous insn was in a .set
3248 noreorder, we can't swap. Actually, the MIPS
3249 assembler will swap in this situation. However, gcc
3250 configured -with-gnu-as will generate code like
3256 in which we can not swap the bne and INSN. If gcc is
3257 not configured -with-gnu-as, it does not output the
3259 || history
[1].noreorder_p
3260 /* If the branch is itself the target of a branch, we
3261 can not swap. We cheat on this; all we check for is
3262 whether there is a label on this instruction. If
3263 there are any branches to anything other than a
3264 label, users must use .set noreorder. */
3265 || si
->label_list
!= NULL
3266 /* If the previous instruction is in a variant frag
3267 other than this branch's one, we cannot do the swap.
3268 This does not apply to the mips16, which uses variant
3269 frags for different purposes. */
3270 || (! mips_opts
.mips16
3271 && prev_insn_frag_type
== rs_machine_dependent
)
3272 /* Check for conflicts between the branch and the instructions
3273 before the candidate delay slot. */
3274 || nops_for_insn (history
+ 1, ip
) > 0
3275 /* Check for conflicts between the swapped sequence and the
3276 target of the branch. */
3277 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
3278 /* We do not swap with a trap instruction, since it
3279 complicates trap handlers to have the trap
3280 instruction be in a delay slot. */
3281 || (prev_pinfo
& INSN_TRAP
)
3282 /* If the branch reads a register that the previous
3283 instruction sets, we can not swap. */
3284 || (! mips_opts
.mips16
3285 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3286 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
3288 || (! mips_opts
.mips16
3289 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3290 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3292 || (! mips_opts
.mips16
3293 && (prev_pinfo2
& INSN2_WRITE_GPR_Z
)
3294 && insn_uses_reg (ip
, EXTRACT_OPERAND (RZ
, history
[0]),
3296 || (mips_opts
.mips16
3297 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3299 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3301 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3303 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3305 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3307 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3309 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3310 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3311 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3312 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3313 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3314 && insn_uses_reg (ip
,
3315 MIPS16OP_EXTRACT_REG32R
3316 (history
[0].insn_opcode
),
3318 /* If the branch writes a register that the previous
3319 instruction sets, we can not swap (we know that
3320 branches write only to RD or to $31). */
3321 || (! mips_opts
.mips16
3322 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3323 && (((pinfo
& INSN_WRITE_GPR_D
)
3324 && (EXTRACT_OPERAND (RT
, history
[0])
3325 == EXTRACT_OPERAND (RD
, *ip
)))
3326 || ((pinfo
& INSN_WRITE_GPR_31
)
3327 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3328 || (! mips_opts
.mips16
3329 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3330 && (((pinfo
& INSN_WRITE_GPR_D
)
3331 && (EXTRACT_OPERAND (RD
, history
[0])
3332 == EXTRACT_OPERAND (RD
, *ip
)))
3333 || ((pinfo
& INSN_WRITE_GPR_31
)
3334 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3335 || (mips_opts
.mips16
3336 && (pinfo
& MIPS16_INSN_WRITE_31
)
3337 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3338 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3339 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3341 /* If the branch writes a register that the previous
3342 instruction reads, we can not swap (we know that
3343 branches only write to RD or to $31). */
3344 || (! mips_opts
.mips16
3345 && (pinfo
& INSN_WRITE_GPR_D
)
3346 && insn_uses_reg (&history
[0],
3347 EXTRACT_OPERAND (RD
, *ip
),
3349 || (! mips_opts
.mips16
3350 && (pinfo
& INSN_WRITE_GPR_31
)
3351 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3352 || (mips_opts
.mips16
3353 && (pinfo
& MIPS16_INSN_WRITE_31
)
3354 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3355 /* If one instruction sets a condition code and the
3356 other one uses a condition code, we can not swap. */
3357 || ((pinfo
& INSN_READ_COND_CODE
)
3358 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3359 || ((pinfo
& INSN_WRITE_COND_CODE
)
3360 && (prev_pinfo
& INSN_READ_COND_CODE
))
3361 /* If the previous instruction uses the PC, we can not
3363 || (mips_opts
.mips16
3364 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3365 /* If the previous instruction had a fixup in mips16
3366 mode, we can not swap. This normally means that the
3367 previous instruction was a 4 byte branch anyhow. */
3368 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3369 /* If the previous instruction is a sync, sync.l, or
3370 sync.p, we can not swap. */
3371 || (prev_pinfo
& INSN_SYNC
)
3372 /* If the previous instruction is an ERET or
3373 DERET, avoid the swap. */
3374 || (history
[0].insn_opcode
== INSN_ERET
)
3375 || (history
[0].insn_opcode
== INSN_DERET
))
3377 if (mips_opts
.mips16
3378 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3379 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3380 && ISA_SUPPORTS_MIPS16E
)
3382 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3383 ip
->insn_opcode
|= 0x0080;
3385 insert_into_history (0, 1, ip
);
3389 /* We could do even better for unconditional branches to
3390 portions of this object file; we could pick up the
3391 instruction at the destination, put it in the delay
3392 slot, and bump the destination address. */
3393 insert_into_history (0, 1, ip
);
3397 if (mips_relax
.sequence
)
3398 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3402 /* It looks like we can actually do the swap. */
3403 struct mips_cl_insn delay
= history
[0];
3404 if (mips_opts
.mips16
)
3406 know (delay
.frag
== ip
->frag
);
3407 move_insn (ip
, delay
.frag
, delay
.where
);
3408 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3410 else if (relaxed_branch
)
3412 /* Add the delay slot instruction to the end of the
3413 current frag and shrink the fixed part of the
3414 original frag. If the branch occupies the tail of
3415 the latter, move it backwards to cover the gap. */
3416 delay
.frag
->fr_fix
-= 4;
3417 if (delay
.frag
== ip
->frag
)
3418 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3419 add_fixed_insn (&delay
);
3423 move_insn (&delay
, ip
->frag
, ip
->where
);
3424 move_insn (ip
, history
[0].frag
, history
[0].where
);
3428 insert_into_history (0, 1, &delay
);
3431 /* If that was an unconditional branch, forget the previous
3432 insn information. */
3433 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3435 mips_no_prev_insn ();
3438 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3440 /* We don't yet optimize a branch likely. What we should do
3441 is look at the target, copy the instruction found there
3442 into the delay slot, and increment the branch to jump to
3443 the next instruction. */
3444 insert_into_history (0, 1, ip
);
3448 insert_into_history (0, 1, ip
);
3451 insert_into_history (0, 1, ip
);
3453 /* We just output an insn, so the next one doesn't have a label. */
3454 mips_clear_insn_labels ();
3457 /* Forget that there was any previous instruction or label. */
3460 mips_no_prev_insn (void)
3462 prev_nop_frag
= NULL
;
3463 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3464 mips_clear_insn_labels ();
3467 /* This function must be called before we emit something other than
3468 instructions. It is like mips_no_prev_insn except that it inserts
3469 any NOPS that might be needed by previous instructions. */
3472 mips_emit_delays (void)
3474 if (! mips_opts
.noreorder
)
3476 int nops
= nops_for_insn (history
, NULL
);
3480 add_fixed_insn (NOP_INSN
);
3481 mips_move_labels ();
3484 mips_no_prev_insn ();
3487 /* Start a (possibly nested) noreorder block. */
3490 start_noreorder (void)
3492 if (mips_opts
.noreorder
== 0)
3497 /* None of the instructions before the .set noreorder can be moved. */
3498 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3499 history
[i
].fixed_p
= 1;
3501 /* Insert any nops that might be needed between the .set noreorder
3502 block and the previous instructions. We will later remove any
3503 nops that turn out not to be needed. */
3504 nops
= nops_for_insn (history
, NULL
);
3507 if (mips_optimize
!= 0)
3509 /* Record the frag which holds the nop instructions, so
3510 that we can remove them if we don't need them. */
3511 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3512 prev_nop_frag
= frag_now
;
3513 prev_nop_frag_holds
= nops
;
3514 prev_nop_frag_required
= 0;
3515 prev_nop_frag_since
= 0;
3518 for (; nops
> 0; --nops
)
3519 add_fixed_insn (NOP_INSN
);
3521 /* Move on to a new frag, so that it is safe to simply
3522 decrease the size of prev_nop_frag. */
3523 frag_wane (frag_now
);
3525 mips_move_labels ();
3527 mips16_mark_labels ();
3528 mips_clear_insn_labels ();
3530 mips_opts
.noreorder
++;
3531 mips_any_noreorder
= 1;
3534 /* End a nested noreorder block. */
3537 end_noreorder (void)
3540 mips_opts
.noreorder
--;
3541 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3543 /* Commit to inserting prev_nop_frag_required nops and go back to
3544 handling nop insertion the .set reorder way. */
3545 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3546 * (mips_opts
.mips16
? 2 : 4));
3547 insert_into_history (prev_nop_frag_since
,
3548 prev_nop_frag_required
, NOP_INSN
);
3549 prev_nop_frag
= NULL
;
3553 /* Set up global variables for the start of a new macro. */
3558 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3559 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3560 && (history
[0].insn_mo
->pinfo
3561 & (INSN_UNCOND_BRANCH_DELAY
3562 | INSN_COND_BRANCH_DELAY
3563 | INSN_COND_BRANCH_LIKELY
)) != 0);
3566 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3567 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3568 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3571 macro_warning (relax_substateT subtype
)
3573 if (subtype
& RELAX_DELAY_SLOT
)
3574 return _("Macro instruction expanded into multiple instructions"
3575 " in a branch delay slot");
3576 else if (subtype
& RELAX_NOMACRO
)
3577 return _("Macro instruction expanded into multiple instructions");
3582 /* Finish up a macro. Emit warnings as appropriate. */
3587 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3589 relax_substateT subtype
;
3591 /* Set up the relaxation warning flags. */
3593 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3594 subtype
|= RELAX_SECOND_LONGER
;
3595 if (mips_opts
.warn_about_macros
)
3596 subtype
|= RELAX_NOMACRO
;
3597 if (mips_macro_warning
.delay_slot_p
)
3598 subtype
|= RELAX_DELAY_SLOT
;
3600 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3602 /* Either the macro has a single implementation or both
3603 implementations are longer than 4 bytes. Emit the
3605 const char *msg
= macro_warning (subtype
);
3607 as_warn ("%s", msg
);
3611 /* One implementation might need a warning but the other
3612 definitely doesn't. */
3613 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3618 /* Read a macro's relocation codes from *ARGS and store them in *R.
3619 The first argument in *ARGS will be either the code for a single
3620 relocation or -1 followed by the three codes that make up a
3621 composite relocation. */
3624 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3628 next
= va_arg (*args
, int);
3630 r
[0] = (bfd_reloc_code_real_type
) next
;
3632 for (i
= 0; i
< 3; i
++)
3633 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3636 /* Build an instruction created by a macro expansion. This is passed
3637 a pointer to the count of instructions created so far, an
3638 expression, the name of the instruction to build, an operand format
3639 string, and corresponding arguments. */
3642 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3644 const struct mips_opcode
*mo
;
3645 struct mips_cl_insn insn
;
3646 bfd_reloc_code_real_type r
[3];
3649 va_start (args
, fmt
);
3651 if (mips_opts
.mips16
)
3653 mips16_macro_build (ep
, name
, fmt
, &args
);
3658 r
[0] = BFD_RELOC_UNUSED
;
3659 r
[1] = BFD_RELOC_UNUSED
;
3660 r
[2] = BFD_RELOC_UNUSED
;
3661 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3663 gas_assert (strcmp (name
, mo
->name
) == 0);
3667 /* Search until we get a match for NAME. It is assumed here that
3668 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3669 if (strcmp (fmt
, mo
->args
) == 0
3670 && mo
->pinfo
!= INSN_MACRO
3671 && is_opcode_valid (mo
))
3675 gas_assert (mo
->name
);
3676 gas_assert (strcmp (name
, mo
->name
) == 0);
3679 create_insn (&insn
, mo
);
3697 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3702 /* Note that in the macro case, these arguments are already
3703 in MSB form. (When handling the instruction in the
3704 non-macro case, these arguments are sizes from which
3705 MSB values must be calculated.) */
3706 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3712 /* Note that in the macro case, these arguments are already
3713 in MSBD form. (When handling the instruction in the
3714 non-macro case, these arguments are sizes from which
3715 MSBD values must be calculated.) */
3716 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3720 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3729 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3735 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3739 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3744 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3750 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3755 int tmp
= va_arg (args
, int);
3757 INSERT_OPERAND (RT
, insn
, tmp
);
3758 INSERT_OPERAND (RD
, insn
, tmp
);
3764 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3771 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3775 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3779 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3783 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3787 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3794 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3799 macro_read_relocs (&args
, r
);
3800 gas_assert (*r
== BFD_RELOC_GPREL16
3801 || *r
== BFD_RELOC_MIPS_HIGHER
3802 || *r
== BFD_RELOC_HI16_S
3803 || *r
== BFD_RELOC_LO16
3804 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
3808 macro_read_relocs (&args
, r
);
3812 macro_read_relocs (&args
, r
);
3813 gas_assert (ep
!= NULL
3814 && (ep
->X_op
== O_constant
3815 || (ep
->X_op
== O_symbol
3816 && (*r
== BFD_RELOC_MIPS_HIGHEST
3817 || *r
== BFD_RELOC_HI16_S
3818 || *r
== BFD_RELOC_HI16
3819 || *r
== BFD_RELOC_GPREL16
3820 || *r
== BFD_RELOC_MIPS_GOT_HI16
3821 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3825 gas_assert (ep
!= NULL
);
3828 * This allows macro() to pass an immediate expression for
3829 * creating short branches without creating a symbol.
3831 * We don't allow branch relaxation for these branches, as
3832 * they should only appear in ".set nomacro" anyway.
3834 if (ep
->X_op
== O_constant
)
3836 if ((ep
->X_add_number
& 3) != 0)
3837 as_bad (_("branch to misaligned address (0x%lx)"),
3838 (unsigned long) ep
->X_add_number
);
3839 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3840 as_bad (_("branch address range overflow (0x%lx)"),
3841 (unsigned long) ep
->X_add_number
);
3842 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3846 *r
= BFD_RELOC_16_PCREL_S2
;
3850 gas_assert (ep
!= NULL
);
3851 *r
= BFD_RELOC_MIPS_JMP
;
3855 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3859 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3868 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3870 append_insn (&insn
, ep
, r
);
3874 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3877 struct mips_opcode
*mo
;
3878 struct mips_cl_insn insn
;
3879 bfd_reloc_code_real_type r
[3]
3880 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3882 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3884 gas_assert (strcmp (name
, mo
->name
) == 0);
3886 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3889 gas_assert (mo
->name
);
3890 gas_assert (strcmp (name
, mo
->name
) == 0);
3893 create_insn (&insn
, mo
);
3911 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
3916 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
3920 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
3924 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
3934 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
3941 regno
= va_arg (*args
, int);
3942 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3943 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3964 gas_assert (ep
!= NULL
);
3966 if (ep
->X_op
!= O_constant
)
3967 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3970 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3971 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3974 *r
= BFD_RELOC_UNUSED
;
3980 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
3987 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3989 append_insn (&insn
, ep
, r
);
3993 * Sign-extend 32-bit mode constants that have bit 31 set and all
3994 * higher bits unset.
3997 normalize_constant_expr (expressionS
*ex
)
3999 if (ex
->X_op
== O_constant
4000 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
4001 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
4006 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4007 * all higher bits unset.
4010 normalize_address_expr (expressionS
*ex
)
4012 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
4013 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
4014 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
4015 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
4020 * Generate a "jalr" instruction with a relocation hint to the called
4021 * function. This occurs in NewABI PIC code.
4024 macro_build_jalr (expressionS
*ep
)
4028 if (MIPS_JALR_HINT_P (ep
))
4033 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
4034 if (MIPS_JALR_HINT_P (ep
))
4035 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
4036 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
4040 * Generate a "lui" instruction.
4043 macro_build_lui (expressionS
*ep
, int regnum
)
4045 expressionS high_expr
;
4046 const struct mips_opcode
*mo
;
4047 struct mips_cl_insn insn
;
4048 bfd_reloc_code_real_type r
[3]
4049 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4050 const char *name
= "lui";
4051 const char *fmt
= "t,u";
4053 gas_assert (! mips_opts
.mips16
);
4057 if (high_expr
.X_op
== O_constant
)
4059 /* We can compute the instruction now without a relocation entry. */
4060 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
4062 *r
= BFD_RELOC_UNUSED
;
4066 gas_assert (ep
->X_op
== O_symbol
);
4067 /* _gp_disp is a special case, used from s_cpload.
4068 __gnu_local_gp is used if mips_no_shared. */
4069 gas_assert (mips_pic
== NO_PIC
4071 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
4072 || (! mips_in_shared
4073 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
4074 "__gnu_local_gp") == 0));
4075 *r
= BFD_RELOC_HI16_S
;
4078 mo
= hash_find (op_hash
, name
);
4079 gas_assert (strcmp (name
, mo
->name
) == 0);
4080 gas_assert (strcmp (fmt
, mo
->args
) == 0);
4081 create_insn (&insn
, mo
);
4083 insn
.insn_opcode
= insn
.insn_mo
->match
;
4084 INSERT_OPERAND (RT
, insn
, regnum
);
4085 if (*r
== BFD_RELOC_UNUSED
)
4087 insn
.insn_opcode
|= high_expr
.X_add_number
;
4088 append_insn (&insn
, NULL
, r
);
4091 append_insn (&insn
, &high_expr
, r
);
4094 /* Generate a sequence of instructions to do a load or store from a constant
4095 offset off of a base register (breg) into/from a target register (treg),
4096 using AT if necessary. */
4098 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
4099 int treg
, int breg
, int dbl
)
4101 gas_assert (ep
->X_op
== O_constant
);
4103 /* Sign-extending 32-bit constants makes their handling easier. */
4105 normalize_constant_expr (ep
);
4107 /* Right now, this routine can only handle signed 32-bit constants. */
4108 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
4109 as_warn (_("operand overflow"));
4111 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
4113 /* Signed 16-bit offset will fit in the op. Easy! */
4114 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
4118 /* 32-bit offset, need multiple instructions and AT, like:
4119 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4120 addu $tempreg,$tempreg,$breg
4121 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4122 to handle the complete offset. */
4123 macro_build_lui (ep
, AT
);
4124 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
4125 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
4128 as_bad (_("Macro used $at after \".set noat\""));
4133 * Generates code to set the $at register to true (one)
4134 * if reg is less than the immediate expression.
4137 set_at (int reg
, int unsignedp
)
4139 if (imm_expr
.X_op
== O_constant
4140 && imm_expr
.X_add_number
>= -0x8000
4141 && imm_expr
.X_add_number
< 0x8000)
4142 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
4143 AT
, reg
, BFD_RELOC_LO16
);
4146 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4147 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
4151 /* Warn if an expression is not a constant. */
4154 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
4156 if (ex
->X_op
== O_big
)
4157 as_bad (_("unsupported large constant"));
4158 else if (ex
->X_op
!= O_constant
)
4159 as_bad (_("Instruction %s requires absolute expression"),
4162 if (HAVE_32BIT_GPRS
)
4163 normalize_constant_expr (ex
);
4166 /* Count the leading zeroes by performing a binary chop. This is a
4167 bulky bit of source, but performance is a LOT better for the
4168 majority of values than a simple loop to count the bits:
4169 for (lcnt = 0; (lcnt < 32); lcnt++)
4170 if ((v) & (1 << (31 - lcnt)))
4172 However it is not code size friendly, and the gain will drop a bit
4173 on certain cached systems.
4175 #define COUNT_TOP_ZEROES(v) \
4176 (((v) & ~0xffff) == 0 \
4177 ? ((v) & ~0xff) == 0 \
4178 ? ((v) & ~0xf) == 0 \
4179 ? ((v) & ~0x3) == 0 \
4180 ? ((v) & ~0x1) == 0 \
4185 : ((v) & ~0x7) == 0 \
4188 : ((v) & ~0x3f) == 0 \
4189 ? ((v) & ~0x1f) == 0 \
4192 : ((v) & ~0x7f) == 0 \
4195 : ((v) & ~0xfff) == 0 \
4196 ? ((v) & ~0x3ff) == 0 \
4197 ? ((v) & ~0x1ff) == 0 \
4200 : ((v) & ~0x7ff) == 0 \
4203 : ((v) & ~0x3fff) == 0 \
4204 ? ((v) & ~0x1fff) == 0 \
4207 : ((v) & ~0x7fff) == 0 \
4210 : ((v) & ~0xffffff) == 0 \
4211 ? ((v) & ~0xfffff) == 0 \
4212 ? ((v) & ~0x3ffff) == 0 \
4213 ? ((v) & ~0x1ffff) == 0 \
4216 : ((v) & ~0x7ffff) == 0 \
4219 : ((v) & ~0x3fffff) == 0 \
4220 ? ((v) & ~0x1fffff) == 0 \
4223 : ((v) & ~0x7fffff) == 0 \
4226 : ((v) & ~0xfffffff) == 0 \
4227 ? ((v) & ~0x3ffffff) == 0 \
4228 ? ((v) & ~0x1ffffff) == 0 \
4231 : ((v) & ~0x7ffffff) == 0 \
4234 : ((v) & ~0x3fffffff) == 0 \
4235 ? ((v) & ~0x1fffffff) == 0 \
4238 : ((v) & ~0x7fffffff) == 0 \
4243 * This routine generates the least number of instructions necessary to load
4244 * an absolute expression value into a register.
4247 load_register (int reg
, expressionS
*ep
, int dbl
)
4250 expressionS hi32
, lo32
;
4252 if (ep
->X_op
!= O_big
)
4254 gas_assert (ep
->X_op
== O_constant
);
4256 /* Sign-extending 32-bit constants makes their handling easier. */
4258 normalize_constant_expr (ep
);
4260 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4262 /* We can handle 16 bit signed values with an addiu to
4263 $zero. No need to ever use daddiu here, since $zero and
4264 the result are always correct in 32 bit mode. */
4265 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4268 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4270 /* We can handle 16 bit unsigned values with an ori to
4272 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4275 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4277 /* 32 bit values require an lui. */
4278 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4279 if ((ep
->X_add_number
& 0xffff) != 0)
4280 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4285 /* The value is larger than 32 bits. */
4287 if (!dbl
|| HAVE_32BIT_GPRS
)
4291 sprintf_vma (value
, ep
->X_add_number
);
4292 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4293 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4297 if (ep
->X_op
!= O_big
)
4300 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4301 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4302 hi32
.X_add_number
&= 0xffffffff;
4304 lo32
.X_add_number
&= 0xffffffff;
4308 gas_assert (ep
->X_add_number
> 2);
4309 if (ep
->X_add_number
== 3)
4310 generic_bignum
[3] = 0;
4311 else if (ep
->X_add_number
> 4)
4312 as_bad (_("Number larger than 64 bits"));
4313 lo32
.X_op
= O_constant
;
4314 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4315 hi32
.X_op
= O_constant
;
4316 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4319 if (hi32
.X_add_number
== 0)
4324 unsigned long hi
, lo
;
4326 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4328 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4330 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4333 if (lo32
.X_add_number
& 0x80000000)
4335 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4336 if (lo32
.X_add_number
& 0xffff)
4337 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4342 /* Check for 16bit shifted constant. We know that hi32 is
4343 non-zero, so start the mask on the first bit of the hi32
4348 unsigned long himask
, lomask
;
4352 himask
= 0xffff >> (32 - shift
);
4353 lomask
= (0xffff << shift
) & 0xffffffff;
4357 himask
= 0xffff << (shift
- 32);
4360 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4361 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4365 tmp
.X_op
= O_constant
;
4367 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4368 | (lo32
.X_add_number
>> shift
));
4370 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4371 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4372 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4373 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4378 while (shift
<= (64 - 16));
4380 /* Find the bit number of the lowest one bit, and store the
4381 shifted value in hi/lo. */
4382 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4383 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4387 while ((lo
& 1) == 0)
4392 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4398 while ((hi
& 1) == 0)
4407 /* Optimize if the shifted value is a (power of 2) - 1. */
4408 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4409 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4411 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4416 /* This instruction will set the register to be all
4418 tmp
.X_op
= O_constant
;
4419 tmp
.X_add_number
= (offsetT
) -1;
4420 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4424 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4425 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4427 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4428 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4433 /* Sign extend hi32 before calling load_register, because we can
4434 generally get better code when we load a sign extended value. */
4435 if ((hi32
.X_add_number
& 0x80000000) != 0)
4436 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4437 load_register (reg
, &hi32
, 0);
4440 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4444 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4452 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4454 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4455 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4461 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4465 mid16
.X_add_number
>>= 16;
4466 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4467 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4470 if ((lo32
.X_add_number
& 0xffff) != 0)
4471 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4475 load_delay_nop (void)
4477 if (!gpr_interlocks
)
4478 macro_build (NULL
, "nop", "");
4481 /* Load an address into a register. */
4484 load_address (int reg
, expressionS
*ep
, int *used_at
)
4486 if (ep
->X_op
!= O_constant
4487 && ep
->X_op
!= O_symbol
)
4489 as_bad (_("expression too complex"));
4490 ep
->X_op
= O_constant
;
4493 if (ep
->X_op
== O_constant
)
4495 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4499 if (mips_pic
== NO_PIC
)
4501 /* If this is a reference to a GP relative symbol, we want
4502 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4504 lui $reg,<sym> (BFD_RELOC_HI16_S)
4505 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4506 If we have an addend, we always use the latter form.
4508 With 64bit address space and a usable $at we want
4509 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4510 lui $at,<sym> (BFD_RELOC_HI16_S)
4511 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4512 daddiu $at,<sym> (BFD_RELOC_LO16)
4516 If $at is already in use, we use a path which is suboptimal
4517 on superscalar processors.
4518 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4519 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4521 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4523 daddiu $reg,<sym> (BFD_RELOC_LO16)
4525 For GP relative symbols in 64bit address space we can use
4526 the same sequence as in 32bit address space. */
4527 if (HAVE_64BIT_SYMBOLS
)
4529 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4530 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4532 relax_start (ep
->X_add_symbol
);
4533 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4534 mips_gp_register
, BFD_RELOC_GPREL16
);
4538 if (*used_at
== 0 && mips_opts
.at
)
4540 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4541 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4542 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4543 BFD_RELOC_MIPS_HIGHER
);
4544 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4545 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4546 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4551 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4552 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4553 BFD_RELOC_MIPS_HIGHER
);
4554 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4555 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4556 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4557 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4560 if (mips_relax
.sequence
)
4565 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4566 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4568 relax_start (ep
->X_add_symbol
);
4569 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4570 mips_gp_register
, BFD_RELOC_GPREL16
);
4573 macro_build_lui (ep
, reg
);
4574 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4575 reg
, reg
, BFD_RELOC_LO16
);
4576 if (mips_relax
.sequence
)
4580 else if (!mips_big_got
)
4584 /* If this is a reference to an external symbol, we want
4585 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4587 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4589 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4590 If there is a constant, it must be added in after.
4592 If we have NewABI, we want
4593 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4594 unless we're referencing a global symbol with a non-zero
4595 offset, in which case cst must be added separately. */
4598 if (ep
->X_add_number
)
4600 ex
.X_add_number
= ep
->X_add_number
;
4601 ep
->X_add_number
= 0;
4602 relax_start (ep
->X_add_symbol
);
4603 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4604 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4605 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4606 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4607 ex
.X_op
= O_constant
;
4608 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4609 reg
, reg
, BFD_RELOC_LO16
);
4610 ep
->X_add_number
= ex
.X_add_number
;
4613 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4614 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4615 if (mips_relax
.sequence
)
4620 ex
.X_add_number
= ep
->X_add_number
;
4621 ep
->X_add_number
= 0;
4622 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4623 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4625 relax_start (ep
->X_add_symbol
);
4627 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4631 if (ex
.X_add_number
!= 0)
4633 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4634 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4635 ex
.X_op
= O_constant
;
4636 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4637 reg
, reg
, BFD_RELOC_LO16
);
4641 else if (mips_big_got
)
4645 /* This is the large GOT case. If this is a reference to an
4646 external symbol, we want
4647 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4649 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4651 Otherwise, for a reference to a local symbol in old ABI, we want
4652 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4654 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4655 If there is a constant, it must be added in after.
4657 In the NewABI, for local symbols, with or without offsets, we want:
4658 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4659 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4663 ex
.X_add_number
= ep
->X_add_number
;
4664 ep
->X_add_number
= 0;
4665 relax_start (ep
->X_add_symbol
);
4666 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4668 reg
, reg
, mips_gp_register
);
4669 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4670 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4671 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4672 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4673 else if (ex
.X_add_number
)
4675 ex
.X_op
= O_constant
;
4676 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4680 ep
->X_add_number
= ex
.X_add_number
;
4682 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4683 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4684 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4685 BFD_RELOC_MIPS_GOT_OFST
);
4690 ex
.X_add_number
= ep
->X_add_number
;
4691 ep
->X_add_number
= 0;
4692 relax_start (ep
->X_add_symbol
);
4693 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4694 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4695 reg
, reg
, mips_gp_register
);
4696 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4697 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4699 if (reg_needs_delay (mips_gp_register
))
4701 /* We need a nop before loading from $gp. This special
4702 check is required because the lui which starts the main
4703 instruction stream does not refer to $gp, and so will not
4704 insert the nop which may be required. */
4705 macro_build (NULL
, "nop", "");
4707 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4708 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4710 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4714 if (ex
.X_add_number
!= 0)
4716 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4717 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4718 ex
.X_op
= O_constant
;
4719 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4727 if (!mips_opts
.at
&& *used_at
== 1)
4728 as_bad (_("Macro used $at after \".set noat\""));
4731 /* Move the contents of register SOURCE into register DEST. */
4734 move_register (int dest
, int source
)
4736 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4740 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4741 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4742 The two alternatives are:
4744 Global symbol Local sybmol
4745 ------------- ------------
4746 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4748 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4750 load_got_offset emits the first instruction and add_got_offset
4751 emits the second for a 16-bit offset or add_got_offset_hilo emits
4752 a sequence to add a 32-bit offset using a scratch register. */
4755 load_got_offset (int dest
, expressionS
*local
)
4760 global
.X_add_number
= 0;
4762 relax_start (local
->X_add_symbol
);
4763 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4764 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4766 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4767 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4772 add_got_offset (int dest
, expressionS
*local
)
4776 global
.X_op
= O_constant
;
4777 global
.X_op_symbol
= NULL
;
4778 global
.X_add_symbol
= NULL
;
4779 global
.X_add_number
= local
->X_add_number
;
4781 relax_start (local
->X_add_symbol
);
4782 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4783 dest
, dest
, BFD_RELOC_LO16
);
4785 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4790 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4793 int hold_mips_optimize
;
4795 global
.X_op
= O_constant
;
4796 global
.X_op_symbol
= NULL
;
4797 global
.X_add_symbol
= NULL
;
4798 global
.X_add_number
= local
->X_add_number
;
4800 relax_start (local
->X_add_symbol
);
4801 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4803 /* Set mips_optimize around the lui instruction to avoid
4804 inserting an unnecessary nop after the lw. */
4805 hold_mips_optimize
= mips_optimize
;
4807 macro_build_lui (&global
, tmp
);
4808 mips_optimize
= hold_mips_optimize
;
4809 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4812 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4817 * This routine implements the seemingly endless macro or synthesized
4818 * instructions and addressing modes in the mips assembly language. Many
4819 * of these macros are simple and are similar to each other. These could
4820 * probably be handled by some kind of table or grammar approach instead of
4821 * this verbose method. Others are not simple macros but are more like
4822 * optimizing code generation.
4823 * One interesting optimization is when several store macros appear
4824 * consecutively that would load AT with the upper half of the same address.
4825 * The ensuing load upper instructions are ommited. This implies some kind
4826 * of global optimization. We currently only optimize within a single macro.
4827 * For many of the load and store macros if the address is specified as a
4828 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4829 * first load register 'at' with zero and use it as the base register. The
4830 * mips assembler simply uses register $zero. Just one tiny optimization
4834 macro (struct mips_cl_insn
*ip
)
4836 unsigned int treg
, sreg
, dreg
, breg
;
4837 unsigned int tempreg
;
4852 bfd_reloc_code_real_type r
;
4853 int hold_mips_optimize
;
4855 gas_assert (! mips_opts
.mips16
);
4857 treg
= EXTRACT_OPERAND (RT
, *ip
);
4858 dreg
= EXTRACT_OPERAND (RD
, *ip
);
4859 sreg
= breg
= EXTRACT_OPERAND (RS
, *ip
);
4860 mask
= ip
->insn_mo
->mask
;
4862 expr1
.X_op
= O_constant
;
4863 expr1
.X_op_symbol
= NULL
;
4864 expr1
.X_add_symbol
= NULL
;
4865 expr1
.X_add_number
= 1;
4879 expr1
.X_add_number
= 8;
4880 macro_build (&expr1
, "bgez", "s,p", sreg
);
4882 macro_build (NULL
, "nop", "");
4884 move_register (dreg
, sreg
);
4885 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4908 if (imm_expr
.X_op
== O_constant
4909 && imm_expr
.X_add_number
>= -0x8000
4910 && imm_expr
.X_add_number
< 0x8000)
4912 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4916 load_register (AT
, &imm_expr
, dbl
);
4917 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4936 if (imm_expr
.X_op
== O_constant
4937 && imm_expr
.X_add_number
>= 0
4938 && imm_expr
.X_add_number
< 0x10000)
4940 if (mask
!= M_NOR_I
)
4941 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4944 macro_build (&imm_expr
, "ori", "t,r,i",
4945 treg
, sreg
, BFD_RELOC_LO16
);
4946 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4952 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4953 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4957 switch (imm_expr
.X_add_number
)
4960 macro_build (NULL
, "nop", "");
4963 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4966 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4967 (int) imm_expr
.X_add_number
);
4986 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4988 macro_build (&offset_expr
, s
, "s,t,p", sreg
, ZERO
);
4992 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4993 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
5001 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
5006 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
5010 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5011 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5017 /* Check for > max integer. */
5018 maxnum
= 0x7fffffff;
5019 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5026 if (imm_expr
.X_op
== O_constant
5027 && imm_expr
.X_add_number
>= maxnum
5028 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5031 /* Result is always false. */
5033 macro_build (NULL
, "nop", "");
5035 macro_build (&offset_expr
, "bnel", "s,t,p", ZERO
, ZERO
);
5038 if (imm_expr
.X_op
!= O_constant
)
5039 as_bad (_("Unsupported large constant"));
5040 ++imm_expr
.X_add_number
;
5044 if (mask
== M_BGEL_I
)
5046 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5048 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
5051 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5053 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5056 maxnum
= 0x7fffffff;
5057 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5064 maxnum
= - maxnum
- 1;
5065 if (imm_expr
.X_op
== O_constant
5066 && imm_expr
.X_add_number
<= maxnum
5067 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5070 /* result is always true */
5071 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
5072 macro_build (&offset_expr
, "b", "p");
5077 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5087 macro_build (&offset_expr
, likely
? "beql" : "beq",
5088 "s,t,p", ZERO
, treg
);
5092 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5093 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5101 && imm_expr
.X_op
== O_constant
5102 && imm_expr
.X_add_number
== -1))
5104 if (imm_expr
.X_op
!= O_constant
)
5105 as_bad (_("Unsupported large constant"));
5106 ++imm_expr
.X_add_number
;
5110 if (mask
== M_BGEUL_I
)
5112 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5114 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5116 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5117 "s,t,p", sreg
, ZERO
);
5122 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5130 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5135 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
5139 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5140 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5148 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5149 "s,t,p", sreg
, ZERO
);
5155 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5156 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5164 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5169 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
5173 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5174 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5180 maxnum
= 0x7fffffff;
5181 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5188 if (imm_expr
.X_op
== O_constant
5189 && imm_expr
.X_add_number
>= maxnum
5190 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5192 if (imm_expr
.X_op
!= O_constant
)
5193 as_bad (_("Unsupported large constant"));
5194 ++imm_expr
.X_add_number
;
5198 if (mask
== M_BLTL_I
)
5200 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5202 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5205 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5207 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5212 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5220 macro_build (&offset_expr
, likely
? "beql" : "beq",
5221 "s,t,p", sreg
, ZERO
);
5227 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5228 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5236 && imm_expr
.X_op
== O_constant
5237 && imm_expr
.X_add_number
== -1))
5239 if (imm_expr
.X_op
!= O_constant
)
5240 as_bad (_("Unsupported large constant"));
5241 ++imm_expr
.X_add_number
;
5245 if (mask
== M_BLTUL_I
)
5247 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5249 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5251 macro_build (&offset_expr
, likely
? "beql" : "beq",
5252 "s,t,p", sreg
, ZERO
);
5257 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5265 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5270 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5274 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5275 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5285 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5286 "s,t,p", ZERO
, treg
);
5290 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5291 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5296 /* Use unsigned arithmetic. */
5300 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5302 as_bad (_("Unsupported large constant"));
5307 pos
= imm_expr
.X_add_number
;
5308 size
= imm2_expr
.X_add_number
;
5313 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
5316 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
5318 as_bad (_("Improper extract size (%lu, position %lu)"),
5319 (unsigned long) size
, (unsigned long) pos
);
5323 if (size
<= 32 && pos
< 32)
5328 else if (size
<= 32)
5338 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5345 /* Use unsigned arithmetic. */
5349 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5351 as_bad (_("Unsupported large constant"));
5356 pos
= imm_expr
.X_add_number
;
5357 size
= imm2_expr
.X_add_number
;
5362 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
5365 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
5367 as_bad (_("Improper insert size (%lu, position %lu)"),
5368 (unsigned long) size
, (unsigned long) pos
);
5372 if (pos
< 32 && (pos
+ size
- 1) < 32)
5387 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5388 (int) (pos
+ size
- 1));
5404 as_warn (_("Divide by zero."));
5406 macro_build (NULL
, "teq", "s,t,q", ZERO
, ZERO
, 7);
5408 macro_build (NULL
, "break", "c", 7);
5415 macro_build (NULL
, "teq", "s,t,q", treg
, ZERO
, 7);
5416 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5420 expr1
.X_add_number
= 8;
5421 macro_build (&expr1
, "bne", "s,t,p", treg
, ZERO
);
5422 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5423 macro_build (NULL
, "break", "c", 7);
5425 expr1
.X_add_number
= -1;
5427 load_register (AT
, &expr1
, dbl
);
5428 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5429 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5432 expr1
.X_add_number
= 1;
5433 load_register (AT
, &expr1
, dbl
);
5434 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5438 expr1
.X_add_number
= 0x80000000;
5439 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5443 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5444 /* We want to close the noreorder block as soon as possible, so
5445 that later insns are available for delay slot filling. */
5450 expr1
.X_add_number
= 8;
5451 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5452 macro_build (NULL
, "nop", "");
5454 /* We want to close the noreorder block as soon as possible, so
5455 that later insns are available for delay slot filling. */
5458 macro_build (NULL
, "break", "c", 6);
5460 macro_build (NULL
, s
, "d", dreg
);
5499 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5501 as_warn (_("Divide by zero."));
5503 macro_build (NULL
, "teq", "s,t,q", ZERO
, ZERO
, 7);
5505 macro_build (NULL
, "break", "c", 7);
5508 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5510 if (strcmp (s2
, "mflo") == 0)
5511 move_register (dreg
, sreg
);
5513 move_register (dreg
, ZERO
);
5516 if (imm_expr
.X_op
== O_constant
5517 && imm_expr
.X_add_number
== -1
5518 && s
[strlen (s
) - 1] != 'u')
5520 if (strcmp (s2
, "mflo") == 0)
5522 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5525 move_register (dreg
, ZERO
);
5530 load_register (AT
, &imm_expr
, dbl
);
5531 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5532 macro_build (NULL
, s2
, "d", dreg
);
5554 macro_build (NULL
, "teq", "s,t,q", treg
, ZERO
, 7);
5555 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5556 /* We want to close the noreorder block as soon as possible, so
5557 that later insns are available for delay slot filling. */
5562 expr1
.X_add_number
= 8;
5563 macro_build (&expr1
, "bne", "s,t,p", treg
, ZERO
);
5564 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5566 /* We want to close the noreorder block as soon as possible, so
5567 that later insns are available for delay slot filling. */
5569 macro_build (NULL
, "break", "c", 7);
5571 macro_build (NULL
, s2
, "d", dreg
);
5583 /* Load the address of a symbol into a register. If breg is not
5584 zero, we then add a base register to it. */
5586 if (dbl
&& HAVE_32BIT_GPRS
)
5587 as_warn (_("dla used to load 32-bit register"));
5589 if (!dbl
&& HAVE_64BIT_OBJECTS
)
5590 as_warn (_("la used to load 64-bit address"));
5592 if (offset_expr
.X_op
== O_constant
5593 && offset_expr
.X_add_number
>= -0x8000
5594 && offset_expr
.X_add_number
< 0x8000)
5596 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5597 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5601 if (mips_opts
.at
&& (treg
== breg
))
5611 if (offset_expr
.X_op
!= O_symbol
5612 && offset_expr
.X_op
!= O_constant
)
5614 as_bad (_("Expression too complex"));
5615 offset_expr
.X_op
= O_constant
;
5618 if (offset_expr
.X_op
== O_constant
)
5619 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5620 else if (mips_pic
== NO_PIC
)
5622 /* If this is a reference to a GP relative symbol, we want
5623 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5625 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5626 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5627 If we have a constant, we need two instructions anyhow,
5628 so we may as well always use the latter form.
5630 With 64bit address space and a usable $at we want
5631 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5632 lui $at,<sym> (BFD_RELOC_HI16_S)
5633 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5634 daddiu $at,<sym> (BFD_RELOC_LO16)
5636 daddu $tempreg,$tempreg,$at
5638 If $at is already in use, we use a path which is suboptimal
5639 on superscalar processors.
5640 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5641 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5643 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5645 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5647 For GP relative symbols in 64bit address space we can use
5648 the same sequence as in 32bit address space. */
5649 if (HAVE_64BIT_SYMBOLS
)
5651 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5652 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5654 relax_start (offset_expr
.X_add_symbol
);
5655 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5656 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5660 if (used_at
== 0 && mips_opts
.at
)
5662 macro_build (&offset_expr
, "lui", "t,u",
5663 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5664 macro_build (&offset_expr
, "lui", "t,u",
5665 AT
, BFD_RELOC_HI16_S
);
5666 macro_build (&offset_expr
, "daddiu", "t,r,j",
5667 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5668 macro_build (&offset_expr
, "daddiu", "t,r,j",
5669 AT
, AT
, BFD_RELOC_LO16
);
5670 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5671 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5676 macro_build (&offset_expr
, "lui", "t,u",
5677 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5678 macro_build (&offset_expr
, "daddiu", "t,r,j",
5679 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5680 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5681 macro_build (&offset_expr
, "daddiu", "t,r,j",
5682 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5683 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5684 macro_build (&offset_expr
, "daddiu", "t,r,j",
5685 tempreg
, tempreg
, BFD_RELOC_LO16
);
5688 if (mips_relax
.sequence
)
5693 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5694 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5696 relax_start (offset_expr
.X_add_symbol
);
5697 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5698 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5701 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5702 as_bad (_("Offset too large"));
5703 macro_build_lui (&offset_expr
, tempreg
);
5704 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5705 tempreg
, tempreg
, BFD_RELOC_LO16
);
5706 if (mips_relax
.sequence
)
5710 else if (!mips_big_got
&& !HAVE_NEWABI
)
5712 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5714 /* If this is a reference to an external symbol, and there
5715 is no constant, we want
5716 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5717 or for lca or if tempreg is PIC_CALL_REG
5718 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5719 For a local symbol, we want
5720 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5722 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5724 If we have a small constant, and this is a reference to
5725 an external symbol, we want
5726 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5728 addiu $tempreg,$tempreg,<constant>
5729 For a local symbol, we want the same instruction
5730 sequence, but we output a BFD_RELOC_LO16 reloc on the
5733 If we have a large constant, and this is a reference to
5734 an external symbol, we want
5735 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5736 lui $at,<hiconstant>
5737 addiu $at,$at,<loconstant>
5738 addu $tempreg,$tempreg,$at
5739 For a local symbol, we want the same instruction
5740 sequence, but we output a BFD_RELOC_LO16 reloc on the
5744 if (offset_expr
.X_add_number
== 0)
5746 if (mips_pic
== SVR4_PIC
5748 && (call
|| tempreg
== PIC_CALL_REG
))
5749 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5751 relax_start (offset_expr
.X_add_symbol
);
5752 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5753 lw_reloc_type
, mips_gp_register
);
5756 /* We're going to put in an addu instruction using
5757 tempreg, so we may as well insert the nop right
5762 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5763 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5765 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5766 tempreg
, tempreg
, BFD_RELOC_LO16
);
5768 /* FIXME: If breg == 0, and the next instruction uses
5769 $tempreg, then if this variant case is used an extra
5770 nop will be generated. */
5772 else if (offset_expr
.X_add_number
>= -0x8000
5773 && offset_expr
.X_add_number
< 0x8000)
5775 load_got_offset (tempreg
, &offset_expr
);
5777 add_got_offset (tempreg
, &offset_expr
);
5781 expr1
.X_add_number
= offset_expr
.X_add_number
;
5782 offset_expr
.X_add_number
=
5783 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5784 load_got_offset (tempreg
, &offset_expr
);
5785 offset_expr
.X_add_number
= expr1
.X_add_number
;
5786 /* If we are going to add in a base register, and the
5787 target register and the base register are the same,
5788 then we are using AT as a temporary register. Since
5789 we want to load the constant into AT, we add our
5790 current AT (from the global offset table) and the
5791 register into the register now, and pretend we were
5792 not using a base register. */
5796 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5801 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5805 else if (!mips_big_got
&& HAVE_NEWABI
)
5807 int add_breg_early
= 0;
5809 /* If this is a reference to an external, and there is no
5810 constant, or local symbol (*), with or without a
5812 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5813 or for lca or if tempreg is PIC_CALL_REG
5814 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5816 If we have a small constant, and this is a reference to
5817 an external symbol, we want
5818 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5819 addiu $tempreg,$tempreg,<constant>
5821 If we have a large constant, and this is a reference to
5822 an external symbol, we want
5823 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5824 lui $at,<hiconstant>
5825 addiu $at,$at,<loconstant>
5826 addu $tempreg,$tempreg,$at
5828 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5829 local symbols, even though it introduces an additional
5832 if (offset_expr
.X_add_number
)
5834 expr1
.X_add_number
= offset_expr
.X_add_number
;
5835 offset_expr
.X_add_number
= 0;
5837 relax_start (offset_expr
.X_add_symbol
);
5838 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5839 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5841 if (expr1
.X_add_number
>= -0x8000
5842 && expr1
.X_add_number
< 0x8000)
5844 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5845 tempreg
, tempreg
, BFD_RELOC_LO16
);
5847 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5849 /* If we are going to add in a base register, and the
5850 target register and the base register are the same,
5851 then we are using AT as a temporary register. Since
5852 we want to load the constant into AT, we add our
5853 current AT (from the global offset table) and the
5854 register into the register now, and pretend we were
5855 not using a base register. */
5860 gas_assert (tempreg
== AT
);
5861 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5867 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5868 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5874 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5877 offset_expr
.X_add_number
= expr1
.X_add_number
;
5879 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5880 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5883 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5884 treg
, tempreg
, breg
);
5890 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5892 relax_start (offset_expr
.X_add_symbol
);
5893 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5894 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5896 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5897 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5902 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5903 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5906 else if (mips_big_got
&& !HAVE_NEWABI
)
5909 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5910 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5911 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5913 /* This is the large GOT case. If this is a reference to an
5914 external symbol, and there is no constant, we want
5915 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5916 addu $tempreg,$tempreg,$gp
5917 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5918 or for lca or if tempreg is PIC_CALL_REG
5919 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5920 addu $tempreg,$tempreg,$gp
5921 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5922 For a local symbol, we want
5923 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5925 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5927 If we have a small constant, and this is a reference to
5928 an external symbol, we want
5929 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5930 addu $tempreg,$tempreg,$gp
5931 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5933 addiu $tempreg,$tempreg,<constant>
5934 For a local symbol, we want
5935 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5937 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5939 If we have a large constant, and this is a reference to
5940 an external symbol, we want
5941 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5942 addu $tempreg,$tempreg,$gp
5943 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5944 lui $at,<hiconstant>
5945 addiu $at,$at,<loconstant>
5946 addu $tempreg,$tempreg,$at
5947 For a local symbol, we want
5948 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5949 lui $at,<hiconstant>
5950 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5951 addu $tempreg,$tempreg,$at
5954 expr1
.X_add_number
= offset_expr
.X_add_number
;
5955 offset_expr
.X_add_number
= 0;
5956 relax_start (offset_expr
.X_add_symbol
);
5957 gpdelay
= reg_needs_delay (mips_gp_register
);
5958 if (expr1
.X_add_number
== 0 && breg
== 0
5959 && (call
|| tempreg
== PIC_CALL_REG
))
5961 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5962 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5964 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5965 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5966 tempreg
, tempreg
, mips_gp_register
);
5967 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5968 tempreg
, lw_reloc_type
, tempreg
);
5969 if (expr1
.X_add_number
== 0)
5973 /* We're going to put in an addu instruction using
5974 tempreg, so we may as well insert the nop right
5979 else if (expr1
.X_add_number
>= -0x8000
5980 && expr1
.X_add_number
< 0x8000)
5983 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5984 tempreg
, tempreg
, BFD_RELOC_LO16
);
5988 /* If we are going to add in a base register, and the
5989 target register and the base register are the same,
5990 then we are using AT as a temporary register. Since
5991 we want to load the constant into AT, we add our
5992 current AT (from the global offset table) and the
5993 register into the register now, and pretend we were
5994 not using a base register. */
5999 gas_assert (tempreg
== AT
);
6001 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6006 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6007 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6011 offset_expr
.X_add_number
=
6012 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
6017 /* This is needed because this instruction uses $gp, but
6018 the first instruction on the main stream does not. */
6019 macro_build (NULL
, "nop", "");
6022 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6023 local_reloc_type
, mips_gp_register
);
6024 if (expr1
.X_add_number
>= -0x8000
6025 && expr1
.X_add_number
< 0x8000)
6028 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6029 tempreg
, tempreg
, BFD_RELOC_LO16
);
6030 /* FIXME: If add_number is 0, and there was no base
6031 register, the external symbol case ended with a load,
6032 so if the symbol turns out to not be external, and
6033 the next instruction uses tempreg, an unnecessary nop
6034 will be inserted. */
6040 /* We must add in the base register now, as in the
6041 external symbol case. */
6042 gas_assert (tempreg
== AT
);
6044 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6047 /* We set breg to 0 because we have arranged to add
6048 it in in both cases. */
6052 macro_build_lui (&expr1
, AT
);
6053 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6054 AT
, AT
, BFD_RELOC_LO16
);
6055 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6056 tempreg
, tempreg
, AT
);
6061 else if (mips_big_got
&& HAVE_NEWABI
)
6063 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
6064 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
6065 int add_breg_early
= 0;
6067 /* This is the large GOT case. If this is a reference to an
6068 external symbol, and there is no constant, we want
6069 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6070 add $tempreg,$tempreg,$gp
6071 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6072 or for lca or if tempreg is PIC_CALL_REG
6073 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6074 add $tempreg,$tempreg,$gp
6075 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6077 If we have a small constant, and this is a reference to
6078 an external symbol, we want
6079 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6080 add $tempreg,$tempreg,$gp
6081 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6082 addi $tempreg,$tempreg,<constant>
6084 If we have a large constant, and this is a reference to
6085 an external symbol, we want
6086 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6087 addu $tempreg,$tempreg,$gp
6088 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6089 lui $at,<hiconstant>
6090 addi $at,$at,<loconstant>
6091 add $tempreg,$tempreg,$at
6093 If we have NewABI, and we know it's a local symbol, we want
6094 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6095 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6096 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6098 relax_start (offset_expr
.X_add_symbol
);
6100 expr1
.X_add_number
= offset_expr
.X_add_number
;
6101 offset_expr
.X_add_number
= 0;
6103 if (expr1
.X_add_number
== 0 && breg
== 0
6104 && (call
|| tempreg
== PIC_CALL_REG
))
6106 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
6107 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
6109 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
6110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6111 tempreg
, tempreg
, mips_gp_register
);
6112 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6113 tempreg
, lw_reloc_type
, tempreg
);
6115 if (expr1
.X_add_number
== 0)
6117 else if (expr1
.X_add_number
>= -0x8000
6118 && expr1
.X_add_number
< 0x8000)
6120 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
6121 tempreg
, tempreg
, BFD_RELOC_LO16
);
6123 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
6125 /* If we are going to add in a base register, and the
6126 target register and the base register are the same,
6127 then we are using AT as a temporary register. Since
6128 we want to load the constant into AT, we add our
6129 current AT (from the global offset table) and the
6130 register into the register now, and pretend we were
6131 not using a base register. */
6136 gas_assert (tempreg
== AT
);
6137 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6143 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6144 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6149 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6152 offset_expr
.X_add_number
= expr1
.X_add_number
;
6153 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6154 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6155 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6156 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
6159 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6160 treg
, tempreg
, breg
);
6170 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
6175 unsigned long temp
= (treg
<< 16) | (0x01);
6176 macro_build (NULL
, "c2", "C", temp
);
6182 unsigned long temp
= (0x02);
6183 macro_build (NULL
, "c2", "C", temp
);
6189 unsigned long temp
= (treg
<< 16) | (0x02);
6190 macro_build (NULL
, "c2", "C", temp
);
6195 macro_build (NULL
, "c2", "C", 3);
6200 unsigned long temp
= (treg
<< 16) | 0x03;
6201 macro_build (NULL
, "c2", "C", temp
);
6206 /* The j instruction may not be used in PIC code, since it
6207 requires an absolute address. We convert it to a b
6209 if (mips_pic
== NO_PIC
)
6210 macro_build (&offset_expr
, "j", "a");
6212 macro_build (&offset_expr
, "b", "p");
6215 /* The jal instructions must be handled as macros because when
6216 generating PIC code they expand to multi-instruction
6217 sequences. Normally they are simple instructions. */
6222 if (mips_pic
== NO_PIC
)
6223 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6226 if (sreg
!= PIC_CALL_REG
)
6227 as_warn (_("MIPS PIC call to register other than $25"));
6229 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6230 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
6232 if (mips_cprestore_offset
< 0)
6233 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6236 if (!mips_frame_reg_valid
)
6238 as_warn (_("No .frame pseudo-op used in PIC code"));
6239 /* Quiet this warning. */
6240 mips_frame_reg_valid
= 1;
6242 if (!mips_cprestore_valid
)
6244 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6245 /* Quiet this warning. */
6246 mips_cprestore_valid
= 1;
6248 if (mips_opts
.noreorder
)
6249 macro_build (NULL
, "nop", "");
6250 expr1
.X_add_number
= mips_cprestore_offset
;
6251 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6254 HAVE_64BIT_ADDRESSES
);
6262 if (mips_pic
== NO_PIC
)
6263 macro_build (&offset_expr
, "jal", "a");
6264 else if (mips_pic
== SVR4_PIC
)
6266 /* If this is a reference to an external symbol, and we are
6267 using a small GOT, we want
6268 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6272 lw $gp,cprestore($sp)
6273 The cprestore value is set using the .cprestore
6274 pseudo-op. If we are using a big GOT, we want
6275 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6277 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6281 lw $gp,cprestore($sp)
6282 If the symbol is not external, we want
6283 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6285 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6288 lw $gp,cprestore($sp)
6290 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6291 sequences above, minus nops, unless the symbol is local,
6292 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6298 relax_start (offset_expr
.X_add_symbol
);
6299 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6300 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6303 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6304 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6310 relax_start (offset_expr
.X_add_symbol
);
6311 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6312 BFD_RELOC_MIPS_CALL_HI16
);
6313 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6314 PIC_CALL_REG
, mips_gp_register
);
6315 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6316 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6319 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6320 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6322 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6323 PIC_CALL_REG
, PIC_CALL_REG
,
6324 BFD_RELOC_MIPS_GOT_OFST
);
6328 macro_build_jalr (&offset_expr
);
6332 relax_start (offset_expr
.X_add_symbol
);
6335 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6336 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6345 gpdelay
= reg_needs_delay (mips_gp_register
);
6346 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6347 BFD_RELOC_MIPS_CALL_HI16
);
6348 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6349 PIC_CALL_REG
, mips_gp_register
);
6350 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6351 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6356 macro_build (NULL
, "nop", "");
6358 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6359 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6362 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6363 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6365 macro_build_jalr (&offset_expr
);
6367 if (mips_cprestore_offset
< 0)
6368 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6371 if (!mips_frame_reg_valid
)
6373 as_warn (_("No .frame pseudo-op used in PIC code"));
6374 /* Quiet this warning. */
6375 mips_frame_reg_valid
= 1;
6377 if (!mips_cprestore_valid
)
6379 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6380 /* Quiet this warning. */
6381 mips_cprestore_valid
= 1;
6383 if (mips_opts
.noreorder
)
6384 macro_build (NULL
, "nop", "");
6385 expr1
.X_add_number
= mips_cprestore_offset
;
6386 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6389 HAVE_64BIT_ADDRESSES
);
6393 else if (mips_pic
== VXWORKS_PIC
)
6394 as_bad (_("Non-PIC jump used in PIC library"));
6417 /* Itbl support may require additional care here. */
6422 /* Itbl support may require additional care here. */
6427 /* Itbl support may require additional care here. */
6432 /* Itbl support may require additional care here. */
6445 /* Itbl support may require additional care here. */
6450 /* Itbl support may require additional care here. */
6455 /* Itbl support may require additional care here. */
6475 if (breg
== treg
|| coproc
|| lr
)
6496 /* Itbl support may require additional care here. */
6501 /* Itbl support may require additional care here. */
6506 /* Itbl support may require additional care here. */
6511 /* Itbl support may require additional care here. */
6532 /* Itbl support may require additional care here. */
6536 /* Itbl support may require additional care here. */
6541 /* Itbl support may require additional care here. */
6554 && NO_ISA_COP (mips_opts
.arch
)
6555 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
6557 as_bad (_("Opcode not supported on this processor: %s"),
6558 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
6562 /* Itbl support may require additional care here. */
6563 if (mask
== M_LWC1_AB
6564 || mask
== M_SWC1_AB
6565 || mask
== M_LDC1_AB
6566 || mask
== M_SDC1_AB
6570 else if (mask
== M_CACHE_AB
)
6577 if (offset_expr
.X_op
!= O_constant
6578 && offset_expr
.X_op
!= O_symbol
)
6580 as_bad (_("Expression too complex"));
6581 offset_expr
.X_op
= O_constant
;
6584 if (HAVE_32BIT_ADDRESSES
6585 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6589 sprintf_vma (value
, offset_expr
.X_add_number
);
6590 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6593 /* A constant expression in PIC code can be handled just as it
6594 is in non PIC code. */
6595 if (offset_expr
.X_op
== O_constant
)
6597 expr1
.X_add_number
= offset_expr
.X_add_number
;
6598 normalize_address_expr (&expr1
);
6599 if (!IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
6601 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
6602 & ~(bfd_vma
) 0xffff);
6603 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6605 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6606 tempreg
, tempreg
, breg
);
6609 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
6611 else if (mips_pic
== NO_PIC
)
6613 /* If this is a reference to a GP relative symbol, and there
6614 is no base register, we want
6615 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6616 Otherwise, if there is no base register, we want
6617 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6618 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6619 If we have a constant, we need two instructions anyhow,
6620 so we always use the latter form.
6622 If we have a base register, and this is a reference to a
6623 GP relative symbol, we want
6624 addu $tempreg,$breg,$gp
6625 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6627 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6628 addu $tempreg,$tempreg,$breg
6629 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6630 With a constant we always use the latter case.
6632 With 64bit address space and no base register and $at usable,
6634 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6635 lui $at,<sym> (BFD_RELOC_HI16_S)
6636 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6639 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6640 If we have a base register, we want
6641 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6642 lui $at,<sym> (BFD_RELOC_HI16_S)
6643 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6647 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6649 Without $at we can't generate the optimal path for superscalar
6650 processors here since this would require two temporary registers.
6651 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6652 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6654 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6656 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6657 If we have a base register, we want
6658 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6659 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6661 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6663 daddu $tempreg,$tempreg,$breg
6664 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6666 For GP relative symbols in 64bit address space we can use
6667 the same sequence as in 32bit address space. */
6668 if (HAVE_64BIT_SYMBOLS
)
6670 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6671 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6673 relax_start (offset_expr
.X_add_symbol
);
6676 macro_build (&offset_expr
, s
, fmt
, treg
,
6677 BFD_RELOC_GPREL16
, mips_gp_register
);
6681 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6682 tempreg
, breg
, mips_gp_register
);
6683 macro_build (&offset_expr
, s
, fmt
, treg
,
6684 BFD_RELOC_GPREL16
, tempreg
);
6689 if (used_at
== 0 && mips_opts
.at
)
6691 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6692 BFD_RELOC_MIPS_HIGHEST
);
6693 macro_build (&offset_expr
, "lui", "t,u", AT
,
6695 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6696 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6698 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6699 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6700 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6701 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6707 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6708 BFD_RELOC_MIPS_HIGHEST
);
6709 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6710 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6711 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6712 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6713 tempreg
, BFD_RELOC_HI16_S
);
6714 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6716 macro_build (NULL
, "daddu", "d,v,t",
6717 tempreg
, tempreg
, breg
);
6718 macro_build (&offset_expr
, s
, fmt
, treg
,
6719 BFD_RELOC_LO16
, tempreg
);
6722 if (mips_relax
.sequence
)
6729 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6730 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6732 relax_start (offset_expr
.X_add_symbol
);
6733 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6737 macro_build_lui (&offset_expr
, tempreg
);
6738 macro_build (&offset_expr
, s
, fmt
, treg
,
6739 BFD_RELOC_LO16
, tempreg
);
6740 if (mips_relax
.sequence
)
6745 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6746 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6748 relax_start (offset_expr
.X_add_symbol
);
6749 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6750 tempreg
, breg
, mips_gp_register
);
6751 macro_build (&offset_expr
, s
, fmt
, treg
,
6752 BFD_RELOC_GPREL16
, tempreg
);
6755 macro_build_lui (&offset_expr
, tempreg
);
6756 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6757 tempreg
, tempreg
, breg
);
6758 macro_build (&offset_expr
, s
, fmt
, treg
,
6759 BFD_RELOC_LO16
, tempreg
);
6760 if (mips_relax
.sequence
)
6764 else if (!mips_big_got
)
6766 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6768 /* If this is a reference to an external symbol, we want
6769 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6771 <op> $treg,0($tempreg)
6773 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6775 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6776 <op> $treg,0($tempreg)
6779 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6780 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6782 If there is a base register, we add it to $tempreg before
6783 the <op>. If there is a constant, we stick it in the
6784 <op> instruction. We don't handle constants larger than
6785 16 bits, because we have no way to load the upper 16 bits
6786 (actually, we could handle them for the subset of cases
6787 in which we are not using $at). */
6788 gas_assert (offset_expr
.X_op
== O_symbol
);
6791 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6792 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6794 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6795 tempreg
, tempreg
, breg
);
6796 macro_build (&offset_expr
, s
, fmt
, treg
,
6797 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6800 expr1
.X_add_number
= offset_expr
.X_add_number
;
6801 offset_expr
.X_add_number
= 0;
6802 if (expr1
.X_add_number
< -0x8000
6803 || expr1
.X_add_number
>= 0x8000)
6804 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6805 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6806 lw_reloc_type
, mips_gp_register
);
6808 relax_start (offset_expr
.X_add_symbol
);
6810 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6811 tempreg
, BFD_RELOC_LO16
);
6814 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6815 tempreg
, tempreg
, breg
);
6816 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6818 else if (mips_big_got
&& !HAVE_NEWABI
)
6822 /* If this is a reference to an external symbol, we want
6823 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6824 addu $tempreg,$tempreg,$gp
6825 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6826 <op> $treg,0($tempreg)
6828 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6830 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6831 <op> $treg,0($tempreg)
6832 If there is a base register, we add it to $tempreg before
6833 the <op>. If there is a constant, we stick it in the
6834 <op> instruction. We don't handle constants larger than
6835 16 bits, because we have no way to load the upper 16 bits
6836 (actually, we could handle them for the subset of cases
6837 in which we are not using $at). */
6838 gas_assert (offset_expr
.X_op
== O_symbol
);
6839 expr1
.X_add_number
= offset_expr
.X_add_number
;
6840 offset_expr
.X_add_number
= 0;
6841 if (expr1
.X_add_number
< -0x8000
6842 || expr1
.X_add_number
>= 0x8000)
6843 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6844 gpdelay
= reg_needs_delay (mips_gp_register
);
6845 relax_start (offset_expr
.X_add_symbol
);
6846 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6847 BFD_RELOC_MIPS_GOT_HI16
);
6848 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6850 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6851 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6854 macro_build (NULL
, "nop", "");
6855 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6856 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6858 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6859 tempreg
, BFD_RELOC_LO16
);
6863 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6864 tempreg
, tempreg
, breg
);
6865 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6867 else if (mips_big_got
&& HAVE_NEWABI
)
6869 /* If this is a reference to an external symbol, we want
6870 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6871 add $tempreg,$tempreg,$gp
6872 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6873 <op> $treg,<ofst>($tempreg)
6874 Otherwise, for local symbols, we want:
6875 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6876 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6877 gas_assert (offset_expr
.X_op
== O_symbol
);
6878 expr1
.X_add_number
= offset_expr
.X_add_number
;
6879 offset_expr
.X_add_number
= 0;
6880 if (expr1
.X_add_number
< -0x8000
6881 || expr1
.X_add_number
>= 0x8000)
6882 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6883 relax_start (offset_expr
.X_add_symbol
);
6884 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6885 BFD_RELOC_MIPS_GOT_HI16
);
6886 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6888 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6889 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6891 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6892 tempreg
, tempreg
, breg
);
6893 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6896 offset_expr
.X_add_number
= expr1
.X_add_number
;
6897 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6898 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6900 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6901 tempreg
, tempreg
, breg
);
6902 macro_build (&offset_expr
, s
, fmt
, treg
,
6903 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6913 load_register (treg
, &imm_expr
, 0);
6917 load_register (treg
, &imm_expr
, 1);
6921 if (imm_expr
.X_op
== O_constant
)
6924 load_register (AT
, &imm_expr
, 0);
6925 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6930 gas_assert (offset_expr
.X_op
== O_symbol
6931 && strcmp (segment_name (S_GET_SEGMENT
6932 (offset_expr
.X_add_symbol
)),
6934 && offset_expr
.X_add_number
== 0);
6935 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6936 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6941 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6942 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6943 order 32 bits of the value and the low order 32 bits are either
6944 zero or in OFFSET_EXPR. */
6945 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6947 if (HAVE_64BIT_GPRS
)
6948 load_register (treg
, &imm_expr
, 1);
6953 if (target_big_endian
)
6965 load_register (hreg
, &imm_expr
, 0);
6968 if (offset_expr
.X_op
== O_absent
)
6969 move_register (lreg
, 0);
6972 gas_assert (offset_expr
.X_op
== O_constant
);
6973 load_register (lreg
, &offset_expr
, 0);
6980 /* We know that sym is in the .rdata section. First we get the
6981 upper 16 bits of the address. */
6982 if (mips_pic
== NO_PIC
)
6984 macro_build_lui (&offset_expr
, AT
);
6989 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6990 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6994 /* Now we load the register(s). */
6995 if (HAVE_64BIT_GPRS
)
6998 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7003 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7006 /* FIXME: How in the world do we deal with the possible
7008 offset_expr
.X_add_number
+= 4;
7009 macro_build (&offset_expr
, "lw", "t,o(b)",
7010 treg
+ 1, BFD_RELOC_LO16
, AT
);
7016 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7017 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7018 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7019 the value and the low order 32 bits are either zero or in
7021 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
7024 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
7025 if (HAVE_64BIT_FPRS
)
7027 gas_assert (HAVE_64BIT_GPRS
);
7028 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
7032 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
7033 if (offset_expr
.X_op
== O_absent
)
7034 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
7037 gas_assert (offset_expr
.X_op
== O_constant
);
7038 load_register (AT
, &offset_expr
, 0);
7039 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
7045 gas_assert (offset_expr
.X_op
== O_symbol
7046 && offset_expr
.X_add_number
== 0);
7047 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
7048 if (strcmp (s
, ".lit8") == 0)
7050 if (mips_opts
.isa
!= ISA_MIPS1
)
7052 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
7053 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
7056 breg
= mips_gp_register
;
7057 r
= BFD_RELOC_MIPS_LITERAL
;
7062 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
7064 if (mips_pic
!= NO_PIC
)
7065 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7066 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7069 /* FIXME: This won't work for a 64 bit address. */
7070 macro_build_lui (&offset_expr
, AT
);
7073 if (mips_opts
.isa
!= ISA_MIPS1
)
7075 macro_build (&offset_expr
, "ldc1", "T,o(b)",
7076 treg
, BFD_RELOC_LO16
, AT
);
7085 /* Even on a big endian machine $fn comes before $fn+1. We have
7086 to adjust when loading from memory. */
7089 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7090 macro_build (&offset_expr
, "lwc1", "T,o(b)",
7091 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
7092 /* FIXME: A possible overflow which I don't know how to deal
7094 offset_expr
.X_add_number
+= 4;
7095 macro_build (&offset_expr
, "lwc1", "T,o(b)",
7096 target_big_endian
? treg
: treg
+ 1, r
, breg
);
7100 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7101 /* Even on a big endian machine $fn comes before $fn+1. We have
7102 to adjust when storing to memory. */
7103 macro_build (&offset_expr
, "swc1", "T,o(b)",
7104 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7105 offset_expr
.X_add_number
+= 4;
7106 macro_build (&offset_expr
, "swc1", "T,o(b)",
7107 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7112 * The MIPS assembler seems to check for X_add_number not
7113 * being double aligned and generating:
7116 * addiu at,at,%lo(foo+1)
7119 * But, the resulting address is the same after relocation so why
7120 * generate the extra instruction?
7122 /* Itbl support may require additional care here. */
7124 if (mips_opts
.isa
!= ISA_MIPS1
)
7135 if (mips_opts
.isa
!= ISA_MIPS1
)
7143 /* Itbl support may require additional care here. */
7148 if (HAVE_64BIT_GPRS
)
7159 if (HAVE_64BIT_GPRS
)
7169 if (offset_expr
.X_op
!= O_symbol
7170 && offset_expr
.X_op
!= O_constant
)
7172 as_bad (_("Expression too complex"));
7173 offset_expr
.X_op
= O_constant
;
7176 if (HAVE_32BIT_ADDRESSES
7177 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7181 sprintf_vma (value
, offset_expr
.X_add_number
);
7182 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7185 /* Even on a big endian machine $fn comes before $fn+1. We have
7186 to adjust when loading from memory. We set coproc if we must
7187 load $fn+1 first. */
7188 /* Itbl support may require additional care here. */
7189 if (!target_big_endian
)
7192 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
7194 /* If this is a reference to a GP relative symbol, we want
7195 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7196 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7197 If we have a base register, we use this
7199 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7200 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7201 If this is not a GP relative symbol, we want
7202 lui $at,<sym> (BFD_RELOC_HI16_S)
7203 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7204 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7205 If there is a base register, we add it to $at after the
7206 lui instruction. If there is a constant, we always use
7208 if (offset_expr
.X_op
== O_symbol
7209 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7210 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7212 relax_start (offset_expr
.X_add_symbol
);
7215 tempreg
= mips_gp_register
;
7219 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7220 AT
, breg
, mips_gp_register
);
7225 /* Itbl support may require additional care here. */
7226 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7227 BFD_RELOC_GPREL16
, tempreg
);
7228 offset_expr
.X_add_number
+= 4;
7230 /* Set mips_optimize to 2 to avoid inserting an
7232 hold_mips_optimize
= mips_optimize
;
7234 /* Itbl support may require additional care here. */
7235 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7236 BFD_RELOC_GPREL16
, tempreg
);
7237 mips_optimize
= hold_mips_optimize
;
7241 offset_expr
.X_add_number
-= 4;
7244 macro_build_lui (&offset_expr
, AT
);
7246 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7247 /* Itbl support may require additional care here. */
7248 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7249 BFD_RELOC_LO16
, AT
);
7250 /* FIXME: How do we handle overflow here? */
7251 offset_expr
.X_add_number
+= 4;
7252 /* Itbl support may require additional care here. */
7253 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7254 BFD_RELOC_LO16
, AT
);
7255 if (mips_relax
.sequence
)
7258 else if (!mips_big_got
)
7260 /* If this is a reference to an external symbol, we want
7261 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7266 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7268 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7269 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7270 If there is a base register we add it to $at before the
7271 lwc1 instructions. If there is a constant we include it
7272 in the lwc1 instructions. */
7274 expr1
.X_add_number
= offset_expr
.X_add_number
;
7275 if (expr1
.X_add_number
< -0x8000
7276 || expr1
.X_add_number
>= 0x8000 - 4)
7277 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7278 load_got_offset (AT
, &offset_expr
);
7281 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7283 /* Set mips_optimize to 2 to avoid inserting an undesired
7285 hold_mips_optimize
= mips_optimize
;
7288 /* Itbl support may require additional care here. */
7289 relax_start (offset_expr
.X_add_symbol
);
7290 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7291 BFD_RELOC_LO16
, AT
);
7292 expr1
.X_add_number
+= 4;
7293 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7294 BFD_RELOC_LO16
, AT
);
7296 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7297 BFD_RELOC_LO16
, AT
);
7298 offset_expr
.X_add_number
+= 4;
7299 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7300 BFD_RELOC_LO16
, AT
);
7303 mips_optimize
= hold_mips_optimize
;
7305 else if (mips_big_got
)
7309 /* If this is a reference to an external symbol, we want
7310 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7312 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7317 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7319 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7320 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7321 If there is a base register we add it to $at before the
7322 lwc1 instructions. If there is a constant we include it
7323 in the lwc1 instructions. */
7325 expr1
.X_add_number
= offset_expr
.X_add_number
;
7326 offset_expr
.X_add_number
= 0;
7327 if (expr1
.X_add_number
< -0x8000
7328 || expr1
.X_add_number
>= 0x8000 - 4)
7329 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7330 gpdelay
= reg_needs_delay (mips_gp_register
);
7331 relax_start (offset_expr
.X_add_symbol
);
7332 macro_build (&offset_expr
, "lui", "t,u",
7333 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7334 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7335 AT
, AT
, mips_gp_register
);
7336 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7337 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7340 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7341 /* Itbl support may require additional care here. */
7342 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7343 BFD_RELOC_LO16
, AT
);
7344 expr1
.X_add_number
+= 4;
7346 /* Set mips_optimize to 2 to avoid inserting an undesired
7348 hold_mips_optimize
= mips_optimize
;
7350 /* Itbl support may require additional care here. */
7351 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7352 BFD_RELOC_LO16
, AT
);
7353 mips_optimize
= hold_mips_optimize
;
7354 expr1
.X_add_number
-= 4;
7357 offset_expr
.X_add_number
= expr1
.X_add_number
;
7359 macro_build (NULL
, "nop", "");
7360 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7361 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7364 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7365 /* Itbl support may require additional care here. */
7366 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7367 BFD_RELOC_LO16
, AT
);
7368 offset_expr
.X_add_number
+= 4;
7370 /* Set mips_optimize to 2 to avoid inserting an undesired
7372 hold_mips_optimize
= mips_optimize
;
7374 /* Itbl support may require additional care here. */
7375 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7376 BFD_RELOC_LO16
, AT
);
7377 mips_optimize
= hold_mips_optimize
;
7386 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
7389 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
7391 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
7392 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
7394 if (!HAVE_64BIT_GPRS
)
7396 offset_expr
.X_add_number
+= 4;
7397 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
7398 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
7403 /* New code added to support COPZ instructions.
7404 This code builds table entries out of the macros in mip_opcodes.
7405 R4000 uses interlocks to handle coproc delays.
7406 Other chips (like the R3000) require nops to be inserted for delays.
7408 FIXME: Currently, we require that the user handle delays.
7409 In order to fill delay slots for non-interlocked chips,
7410 we must have a way to specify delays based on the coprocessor.
7411 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7412 What are the side-effects of the cop instruction?
7413 What cache support might we have and what are its effects?
7414 Both coprocessor & memory require delays. how long???
7415 What registers are read/set/modified?
7417 If an itbl is provided to interpret cop instructions,
7418 this knowledge can be encoded in the itbl spec. */
7432 if (NO_ISA_COP (mips_opts
.arch
)
7433 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
7435 as_bad (_("opcode not supported on this processor: %s"),
7436 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
7440 /* For now we just do C (same as Cz). The parameter will be
7441 stored in insn_opcode by mips_ip. */
7442 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7446 move_register (dreg
, sreg
);
7452 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7453 macro_build (NULL
, "mflo", "d", dreg
);
7459 /* The MIPS assembler some times generates shifts and adds. I'm
7460 not trying to be that fancy. GCC should do this for us
7463 load_register (AT
, &imm_expr
, dbl
);
7464 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7465 macro_build (NULL
, "mflo", "d", dreg
);
7481 load_register (AT
, &imm_expr
, dbl
);
7482 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7483 macro_build (NULL
, "mflo", "d", dreg
);
7484 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7485 macro_build (NULL
, "mfhi", "d", AT
);
7487 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7490 expr1
.X_add_number
= 8;
7491 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7492 macro_build (NULL
, "nop", "");
7493 macro_build (NULL
, "break", "c", 6);
7496 macro_build (NULL
, "mflo", "d", dreg
);
7512 load_register (AT
, &imm_expr
, dbl
);
7513 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7514 sreg
, imm
? AT
: treg
);
7515 macro_build (NULL
, "mfhi", "d", AT
);
7516 macro_build (NULL
, "mflo", "d", dreg
);
7518 macro_build (NULL
, "tne", "s,t,q", AT
, ZERO
, 6);
7521 expr1
.X_add_number
= 8;
7522 macro_build (&expr1
, "beq", "s,t,p", AT
, ZERO
);
7523 macro_build (NULL
, "nop", "");
7524 macro_build (NULL
, "break", "c", 6);
7530 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7541 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7542 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7546 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
7547 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7548 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7549 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7553 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7564 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7565 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7569 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
7570 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7571 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7572 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7581 if (imm_expr
.X_op
!= O_constant
)
7582 as_bad (_("Improper rotate count"));
7583 rot
= imm_expr
.X_add_number
& 0x3f;
7584 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7586 rot
= (64 - rot
) & 0x3f;
7588 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7590 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7595 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7598 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7599 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7602 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7603 macro_build (NULL
, rr
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7604 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7612 if (imm_expr
.X_op
!= O_constant
)
7613 as_bad (_("Improper rotate count"));
7614 rot
= imm_expr
.X_add_number
& 0x1f;
7615 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7617 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7622 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7626 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7627 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7628 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7633 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7635 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7639 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
7640 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7641 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7642 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7646 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7648 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7652 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
7653 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7654 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7655 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7664 if (imm_expr
.X_op
!= O_constant
)
7665 as_bad (_("Improper rotate count"));
7666 rot
= imm_expr
.X_add_number
& 0x3f;
7667 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7670 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7672 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7677 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7680 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7681 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7684 macro_build (NULL
, rr
, "d,w,<", AT
, sreg
, rot
);
7685 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7686 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7694 if (imm_expr
.X_op
!= O_constant
)
7695 as_bad (_("Improper rotate count"));
7696 rot
= imm_expr
.X_add_number
& 0x1f;
7697 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7699 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7704 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7708 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7709 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7710 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7716 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7718 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7721 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7722 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7727 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7729 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7734 as_warn (_("Instruction %s: result is always false"),
7736 move_register (dreg
, 0);
7739 if (CPU_HAS_SEQ (mips_opts
.arch
)
7740 && -512 <= imm_expr
.X_add_number
7741 && imm_expr
.X_add_number
< 512)
7743 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7744 (int) imm_expr
.X_add_number
);
7747 if (imm_expr
.X_op
== O_constant
7748 && imm_expr
.X_add_number
>= 0
7749 && imm_expr
.X_add_number
< 0x10000)
7751 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7753 else if (imm_expr
.X_op
== O_constant
7754 && imm_expr
.X_add_number
> -0x8000
7755 && imm_expr
.X_add_number
< 0)
7757 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7758 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7759 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7761 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7764 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7765 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7770 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7771 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7774 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7777 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7783 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7784 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7787 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7789 if (imm_expr
.X_op
== O_constant
7790 && imm_expr
.X_add_number
>= -0x8000
7791 && imm_expr
.X_add_number
< 0x8000)
7793 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7794 dreg
, sreg
, BFD_RELOC_LO16
);
7798 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7799 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7803 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7806 case M_SGT
: /* sreg > treg <==> treg < sreg */
7812 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7815 case M_SGT_I
: /* sreg > I <==> I < sreg */
7822 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7823 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7826 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7832 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7833 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7836 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7843 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7844 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7845 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7849 if (imm_expr
.X_op
== O_constant
7850 && imm_expr
.X_add_number
>= -0x8000
7851 && imm_expr
.X_add_number
< 0x8000)
7853 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7857 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7858 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7862 if (imm_expr
.X_op
== O_constant
7863 && imm_expr
.X_add_number
>= -0x8000
7864 && imm_expr
.X_add_number
< 0x8000)
7866 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7871 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7872 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7877 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7879 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7882 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7883 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7888 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7890 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7895 as_warn (_("Instruction %s: result is always true"),
7897 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7898 dreg
, 0, BFD_RELOC_LO16
);
7901 if (CPU_HAS_SEQ (mips_opts
.arch
)
7902 && -512 <= imm_expr
.X_add_number
7903 && imm_expr
.X_add_number
< 512)
7905 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
7906 (int) imm_expr
.X_add_number
);
7909 if (imm_expr
.X_op
== O_constant
7910 && imm_expr
.X_add_number
>= 0
7911 && imm_expr
.X_add_number
< 0x10000)
7913 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7915 else if (imm_expr
.X_op
== O_constant
7916 && imm_expr
.X_add_number
> -0x8000
7917 && imm_expr
.X_add_number
< 0)
7919 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7920 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7921 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7923 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7926 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7927 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
7932 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7933 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7936 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7942 if (imm_expr
.X_op
== O_constant
7943 && imm_expr
.X_add_number
> -0x8000
7944 && imm_expr
.X_add_number
<= 0x8000)
7946 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7947 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7948 dreg
, sreg
, BFD_RELOC_LO16
);
7952 load_register (AT
, &imm_expr
, dbl
);
7953 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7959 if (imm_expr
.X_op
== O_constant
7960 && imm_expr
.X_add_number
> -0x8000
7961 && imm_expr
.X_add_number
<= 0x8000)
7963 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7964 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7965 dreg
, sreg
, BFD_RELOC_LO16
);
7969 load_register (AT
, &imm_expr
, dbl
);
7970 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7992 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7993 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7998 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8000 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
8001 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
8004 * Is the double cfc1 instruction a bug in the mips assembler;
8005 * or is there a reason for it?
8008 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
8009 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
8010 macro_build (NULL
, "nop", "");
8011 expr1
.X_add_number
= 3;
8012 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
8013 expr1
.X_add_number
= 2;
8014 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
8015 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
8016 macro_build (NULL
, "nop", "");
8017 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
8019 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
8020 macro_build (NULL
, "nop", "");
8031 if (offset_expr
.X_add_number
>= 0x7fff)
8032 as_bad (_("Operand overflow"));
8033 if (!target_big_endian
)
8034 ++offset_expr
.X_add_number
;
8035 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8036 if (!target_big_endian
)
8037 --offset_expr
.X_add_number
;
8039 ++offset_expr
.X_add_number
;
8040 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8041 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
8042 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8055 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8056 as_bad (_("Operand overflow"));
8064 if (!target_big_endian
)
8065 offset_expr
.X_add_number
+= off
;
8066 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8067 if (!target_big_endian
)
8068 offset_expr
.X_add_number
-= off
;
8070 offset_expr
.X_add_number
+= off
;
8071 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8073 /* If necessary, move the result in tempreg to the final destination. */
8074 if (treg
== tempreg
)
8076 /* Protect second load's delay slot. */
8078 move_register (treg
, tempreg
);
8092 load_address (AT
, &offset_expr
, &used_at
);
8094 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8095 if (!target_big_endian
)
8096 expr1
.X_add_number
= off
;
8098 expr1
.X_add_number
= 0;
8099 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8100 if (!target_big_endian
)
8101 expr1
.X_add_number
= 0;
8103 expr1
.X_add_number
= off
;
8104 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8110 load_address (AT
, &offset_expr
, &used_at
);
8112 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8113 if (target_big_endian
)
8114 expr1
.X_add_number
= 0;
8115 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
8116 treg
, BFD_RELOC_LO16
, AT
);
8117 if (target_big_endian
)
8118 expr1
.X_add_number
= 1;
8120 expr1
.X_add_number
= 0;
8121 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8122 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8123 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8128 if (offset_expr
.X_add_number
>= 0x7fff)
8129 as_bad (_("Operand overflow"));
8130 if (target_big_endian
)
8131 ++offset_expr
.X_add_number
;
8132 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8133 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
8134 if (target_big_endian
)
8135 --offset_expr
.X_add_number
;
8137 ++offset_expr
.X_add_number
;
8138 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8151 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8152 as_bad (_("Operand overflow"));
8153 if (!target_big_endian
)
8154 offset_expr
.X_add_number
+= off
;
8155 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8156 if (!target_big_endian
)
8157 offset_expr
.X_add_number
-= off
;
8159 offset_expr
.X_add_number
+= off
;
8160 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8174 load_address (AT
, &offset_expr
, &used_at
);
8176 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8177 if (!target_big_endian
)
8178 expr1
.X_add_number
= off
;
8180 expr1
.X_add_number
= 0;
8181 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8182 if (!target_big_endian
)
8183 expr1
.X_add_number
= 0;
8185 expr1
.X_add_number
= off
;
8186 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8191 load_address (AT
, &offset_expr
, &used_at
);
8193 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8194 if (!target_big_endian
)
8195 expr1
.X_add_number
= 0;
8196 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8197 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8198 if (!target_big_endian
)
8199 expr1
.X_add_number
= 1;
8201 expr1
.X_add_number
= 0;
8202 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8203 if (!target_big_endian
)
8204 expr1
.X_add_number
= 0;
8206 expr1
.X_add_number
= 1;
8207 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8208 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8209 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8213 /* FIXME: Check if this is one of the itbl macros, since they
8214 are added dynamically. */
8215 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8218 if (!mips_opts
.at
&& used_at
)
8219 as_bad (_("Macro used $at after \".set noat\""));
8222 /* Implement macros in mips16 mode. */
8225 mips16_macro (struct mips_cl_insn
*ip
)
8228 int xreg
, yreg
, zreg
, tmp
;
8231 const char *s
, *s2
, *s3
;
8233 mask
= ip
->insn_mo
->mask
;
8235 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8236 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8237 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8239 expr1
.X_op
= O_constant
;
8240 expr1
.X_op_symbol
= NULL
;
8241 expr1
.X_add_symbol
= NULL
;
8242 expr1
.X_add_number
= 1;
8262 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8263 expr1
.X_add_number
= 2;
8264 macro_build (&expr1
, "bnez", "x,p", yreg
);
8265 macro_build (NULL
, "break", "6", 7);
8267 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8268 since that causes an overflow. We should do that as well,
8269 but I don't see how to do the comparisons without a temporary
8272 macro_build (NULL
, s
, "x", zreg
);
8292 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8293 expr1
.X_add_number
= 2;
8294 macro_build (&expr1
, "bnez", "x,p", yreg
);
8295 macro_build (NULL
, "break", "6", 7);
8297 macro_build (NULL
, s2
, "x", zreg
);
8303 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8304 macro_build (NULL
, "mflo", "x", zreg
);
8312 if (imm_expr
.X_op
!= O_constant
)
8313 as_bad (_("Unsupported large constant"));
8314 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8315 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8319 if (imm_expr
.X_op
!= O_constant
)
8320 as_bad (_("Unsupported large constant"));
8321 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8322 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8326 if (imm_expr
.X_op
!= O_constant
)
8327 as_bad (_("Unsupported large constant"));
8328 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8329 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8351 goto do_reverse_branch
;
8355 goto do_reverse_branch
;
8367 goto do_reverse_branch
;
8378 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8379 macro_build (&offset_expr
, s2
, "p");
8406 goto do_addone_branch_i
;
8411 goto do_addone_branch_i
;
8426 goto do_addone_branch_i
;
8433 if (imm_expr
.X_op
!= O_constant
)
8434 as_bad (_("Unsupported large constant"));
8435 ++imm_expr
.X_add_number
;
8438 macro_build (&imm_expr
, s
, s3
, xreg
);
8439 macro_build (&offset_expr
, s2
, "p");
8443 expr1
.X_add_number
= 0;
8444 macro_build (&expr1
, "slti", "x,8", yreg
);
8446 move_register (xreg
, yreg
);
8447 expr1
.X_add_number
= 2;
8448 macro_build (&expr1
, "bteqz", "p");
8449 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8453 /* For consistency checking, verify that all bits are specified either
8454 by the match/mask part of the instruction definition, or by the
8457 validate_mips_insn (const struct mips_opcode
*opc
)
8459 const char *p
= opc
->args
;
8461 unsigned long used_bits
= opc
->mask
;
8463 if ((used_bits
& opc
->match
) != opc
->match
)
8465 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8466 opc
->name
, opc
->args
);
8469 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8479 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8480 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8481 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8482 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8483 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8484 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8485 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8486 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8487 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8488 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8489 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8490 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8491 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8493 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8494 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8495 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8496 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8497 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8498 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8499 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8500 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8501 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8502 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8503 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
8504 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
8505 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
8506 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
8507 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
8510 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8511 c
, opc
->name
, opc
->args
);
8515 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8516 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8518 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8519 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8520 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8521 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8523 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8524 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8526 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8527 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8529 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8530 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8531 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8532 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8533 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8534 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8535 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8536 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8537 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8538 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8539 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8540 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8541 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8542 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8543 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8544 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8545 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8547 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8548 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8549 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8550 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8552 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8553 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8554 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8555 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8556 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8557 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8558 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8559 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8560 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8563 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8564 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8565 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8566 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8567 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8570 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8571 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8572 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8573 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8574 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8575 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8576 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8577 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8578 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8579 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8580 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8581 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8582 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8583 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8584 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8585 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8586 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8587 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8589 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8590 c
, opc
->name
, opc
->args
);
8594 if (used_bits
!= 0xffffffff)
8596 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8597 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8603 /* UDI immediates. */
8611 static const struct mips_immed mips_immed
[] = {
8612 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8613 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8614 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8615 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8619 /* Check whether an odd floating-point register is allowed. */
8621 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8623 const char *s
= insn
->name
;
8625 if (insn
->pinfo
== INSN_MACRO
)
8626 /* Let a macro pass, we'll catch it later when it is expanded. */
8629 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8631 /* Allow odd registers for single-precision ops. */
8632 switch (insn
->pinfo
& (FP_S
| FP_D
))
8636 return 1; /* both single precision - ok */
8638 return 0; /* both double precision - fail */
8643 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8644 s
= strchr (insn
->name
, '.');
8646 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8647 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8650 /* Single-precision coprocessor loads and moves are OK too. */
8651 if ((insn
->pinfo
& FP_S
)
8652 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8653 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8659 /* This routine assembles an instruction into its binary format. As a
8660 side effect, it sets one of the global variables imm_reloc or
8661 offset_reloc to the type of relocation to do if one of the operands
8662 is an address expression. */
8665 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8670 struct mips_opcode
*insn
;
8673 unsigned int lastregno
;
8674 unsigned int lastpos
= 0;
8675 unsigned int limlo
, limhi
;
8678 offsetT min_range
, max_range
;
8684 /* If the instruction contains a '.', we first try to match an instruction
8685 including the '.'. Then we try again without the '.'. */
8687 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8690 /* If we stopped on whitespace, then replace the whitespace with null for
8691 the call to hash_find. Save the character we replaced just in case we
8692 have to re-parse the instruction. */
8699 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8701 /* If we didn't find the instruction in the opcode table, try again, but
8702 this time with just the instruction up to, but not including the
8706 /* Restore the character we overwrite above (if any). */
8710 /* Scan up to the first '.' or whitespace. */
8712 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8716 /* If we did not find a '.', then we can quit now. */
8719 insn_error
= _("Unrecognized opcode");
8723 /* Lookup the instruction in the hash table. */
8725 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8727 insn_error
= _("Unrecognized opcode");
8737 gas_assert (strcmp (insn
->name
, str
) == 0);
8739 ok
= is_opcode_valid (insn
);
8742 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8743 && strcmp (insn
->name
, insn
[1].name
) == 0)
8752 static char buf
[100];
8754 _("opcode not supported on this processor: %s (%s)"),
8755 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8756 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8765 create_insn (ip
, insn
);
8768 lastregno
= 0xffffffff;
8769 for (args
= insn
->args
;; ++args
)
8773 s
+= strspn (s
, " \t");
8777 case '\0': /* end of args */
8782 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
8783 my_getExpression (&imm_expr
, s
);
8784 check_absolute_expr (ip
, &imm_expr
);
8785 if ((unsigned long) imm_expr
.X_add_number
!= 1
8786 && (unsigned long) imm_expr
.X_add_number
!= 3)
8788 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8789 (unsigned long) imm_expr
.X_add_number
);
8791 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8792 imm_expr
.X_op
= O_absent
;
8796 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
8797 my_getExpression (&imm_expr
, s
);
8798 check_absolute_expr (ip
, &imm_expr
);
8799 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8801 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8802 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8804 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8805 imm_expr
.X_op
= O_absent
;
8809 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
8810 my_getExpression (&imm_expr
, s
);
8811 check_absolute_expr (ip
, &imm_expr
);
8812 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8814 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8815 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8817 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8818 imm_expr
.X_op
= O_absent
;
8822 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
8823 my_getExpression (&imm_expr
, s
);
8824 check_absolute_expr (ip
, &imm_expr
);
8825 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8827 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8828 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8830 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8831 imm_expr
.X_op
= O_absent
;
8835 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
8836 my_getExpression (&imm_expr
, s
);
8837 check_absolute_expr (ip
, &imm_expr
);
8838 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8840 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8841 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8843 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8844 imm_expr
.X_op
= O_absent
;
8848 case '7': /* Four DSP accumulators in bits 11,12. */
8849 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8850 s
[3] >= '0' && s
[3] <= '3')
8854 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8858 as_bad (_("Invalid dsp acc register"));
8861 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
8862 my_getExpression (&imm_expr
, s
);
8863 check_absolute_expr (ip
, &imm_expr
);
8864 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8866 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8868 (unsigned long) imm_expr
.X_add_number
);
8870 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8871 imm_expr
.X_op
= O_absent
;
8875 case '9': /* Four DSP accumulators in bits 21,22. */
8876 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8877 s
[3] >= '0' && s
[3] <= '3')
8881 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8885 as_bad (_("Invalid dsp acc register"));
8888 case '0': /* DSP 6-bit signed immediate in bit 20. */
8889 my_getExpression (&imm_expr
, s
);
8890 check_absolute_expr (ip
, &imm_expr
);
8891 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8892 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8893 if (imm_expr
.X_add_number
< min_range
||
8894 imm_expr
.X_add_number
> max_range
)
8896 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8897 (long) min_range
, (long) max_range
,
8898 (long) imm_expr
.X_add_number
);
8900 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8901 imm_expr
.X_op
= O_absent
;
8905 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
8906 my_getExpression (&imm_expr
, s
);
8907 check_absolute_expr (ip
, &imm_expr
);
8908 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8910 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8912 (unsigned long) imm_expr
.X_add_number
);
8914 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8915 imm_expr
.X_op
= O_absent
;
8919 case ':': /* DSP 7-bit signed immediate in bit 19. */
8920 my_getExpression (&imm_expr
, s
);
8921 check_absolute_expr (ip
, &imm_expr
);
8922 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8923 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8924 if (imm_expr
.X_add_number
< min_range
||
8925 imm_expr
.X_add_number
> max_range
)
8927 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8928 (long) min_range
, (long) max_range
,
8929 (long) imm_expr
.X_add_number
);
8931 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8932 imm_expr
.X_op
= O_absent
;
8936 case '@': /* DSP 10-bit signed immediate in bit 16. */
8937 my_getExpression (&imm_expr
, s
);
8938 check_absolute_expr (ip
, &imm_expr
);
8939 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8940 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8941 if (imm_expr
.X_add_number
< min_range
||
8942 imm_expr
.X_add_number
> max_range
)
8944 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8945 (long) min_range
, (long) max_range
,
8946 (long) imm_expr
.X_add_number
);
8948 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8949 imm_expr
.X_op
= O_absent
;
8953 case '!': /* MT usermode flag bit. */
8954 my_getExpression (&imm_expr
, s
);
8955 check_absolute_expr (ip
, &imm_expr
);
8956 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8957 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8958 (unsigned long) imm_expr
.X_add_number
);
8959 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8960 imm_expr
.X_op
= O_absent
;
8964 case '$': /* MT load high flag bit. */
8965 my_getExpression (&imm_expr
, s
);
8966 check_absolute_expr (ip
, &imm_expr
);
8967 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8968 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8969 (unsigned long) imm_expr
.X_add_number
);
8970 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8971 imm_expr
.X_op
= O_absent
;
8975 case '*': /* Four DSP accumulators in bits 18,19. */
8976 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8977 s
[3] >= '0' && s
[3] <= '3')
8981 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8985 as_bad (_("Invalid dsp/smartmips acc register"));
8988 case '&': /* Four DSP accumulators in bits 13,14. */
8989 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8990 s
[3] >= '0' && s
[3] <= '3')
8994 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8998 as_bad (_("Invalid dsp/smartmips acc register"));
9010 INSERT_OPERAND (RS
, *ip
, lastregno
);
9014 INSERT_OPERAND (RT
, *ip
, lastregno
);
9018 INSERT_OPERAND (FT
, *ip
, lastregno
);
9022 INSERT_OPERAND (FS
, *ip
, lastregno
);
9028 /* Handle optional base register.
9029 Either the base register is omitted or
9030 we must have a left paren. */
9031 /* This is dependent on the next operand specifier
9032 is a base register specification. */
9033 gas_assert (args
[1] == 'b');
9037 case ')': /* These must match exactly. */
9044 case '+': /* Opcode extension character. */
9047 case '1': /* UDI immediates. */
9052 const struct mips_immed
*imm
= mips_immed
;
9054 while (imm
->type
&& imm
->type
!= *args
)
9058 my_getExpression (&imm_expr
, s
);
9059 check_absolute_expr (ip
, &imm_expr
);
9060 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
9062 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9063 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
9064 (unsigned long) imm_expr
.X_add_number
,
9065 (unsigned long) imm_expr
.X_add_number
);
9066 imm_expr
.X_add_number
&= imm
->mask
;
9068 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
9070 imm_expr
.X_op
= O_absent
;
9075 case 'A': /* ins/ext position, becomes LSB. */
9084 my_getExpression (&imm_expr
, s
);
9085 check_absolute_expr (ip
, &imm_expr
);
9086 if ((unsigned long) imm_expr
.X_add_number
< limlo
9087 || (unsigned long) imm_expr
.X_add_number
> limhi
)
9089 as_bad (_("Improper position (%lu)"),
9090 (unsigned long) imm_expr
.X_add_number
);
9091 imm_expr
.X_add_number
= limlo
;
9093 lastpos
= imm_expr
.X_add_number
;
9094 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9095 imm_expr
.X_op
= O_absent
;
9099 case 'B': /* ins size, becomes MSB. */
9108 my_getExpression (&imm_expr
, s
);
9109 check_absolute_expr (ip
, &imm_expr
);
9110 /* Check for negative input so that small negative numbers
9111 will not succeed incorrectly. The checks against
9112 (pos+size) transitively check "size" itself,
9113 assuming that "pos" is reasonable. */
9114 if ((long) imm_expr
.X_add_number
< 0
9115 || ((unsigned long) imm_expr
.X_add_number
9117 || ((unsigned long) imm_expr
.X_add_number
9120 as_bad (_("Improper insert size (%lu, position %lu)"),
9121 (unsigned long) imm_expr
.X_add_number
,
9122 (unsigned long) lastpos
);
9123 imm_expr
.X_add_number
= limlo
- lastpos
;
9125 INSERT_OPERAND (INSMSB
, *ip
,
9126 lastpos
+ imm_expr
.X_add_number
- 1);
9127 imm_expr
.X_op
= O_absent
;
9131 case 'C': /* ext size, becomes MSBD. */
9144 my_getExpression (&imm_expr
, s
);
9145 check_absolute_expr (ip
, &imm_expr
);
9146 /* Check for negative input so that small negative numbers
9147 will not succeed incorrectly. The checks against
9148 (pos+size) transitively check "size" itself,
9149 assuming that "pos" is reasonable. */
9150 if ((long) imm_expr
.X_add_number
< 0
9151 || ((unsigned long) imm_expr
.X_add_number
9153 || ((unsigned long) imm_expr
.X_add_number
9156 as_bad (_("Improper extract size (%lu, position %lu)"),
9157 (unsigned long) imm_expr
.X_add_number
,
9158 (unsigned long) lastpos
);
9159 imm_expr
.X_add_number
= limlo
- lastpos
;
9161 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
9162 imm_expr
.X_op
= O_absent
;
9167 /* +D is for disassembly only; never match. */
9171 /* "+I" is like "I", except that imm2_expr is used. */
9172 my_getExpression (&imm2_expr
, s
);
9173 if (imm2_expr
.X_op
!= O_big
9174 && imm2_expr
.X_op
!= O_constant
)
9175 insn_error
= _("absolute expression required");
9176 if (HAVE_32BIT_GPRS
)
9177 normalize_constant_expr (&imm2_expr
);
9181 case 'T': /* Coprocessor register. */
9182 /* +T is for disassembly only; never match. */
9185 case 't': /* Coprocessor register number. */
9186 if (s
[0] == '$' && ISDIGIT (s
[1]))
9196 while (ISDIGIT (*s
));
9198 as_bad (_("Invalid register number (%d)"), regno
);
9201 INSERT_OPERAND (RT
, *ip
, regno
);
9206 as_bad (_("Invalid coprocessor 0 register number"));
9210 /* bbit[01] and bbit[01]32 bit index. Give error if index
9211 is not in the valid range. */
9212 my_getExpression (&imm_expr
, s
);
9213 check_absolute_expr (ip
, &imm_expr
);
9214 if ((unsigned) imm_expr
.X_add_number
> 31)
9216 as_bad (_("Improper bit index (%lu)"),
9217 (unsigned long) imm_expr
.X_add_number
);
9218 imm_expr
.X_add_number
= 0;
9220 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9221 imm_expr
.X_op
= O_absent
;
9226 /* bbit[01] bit index when bbit is used but we generate
9227 bbit[01]32 because the index is over 32. Move to the
9228 next candidate if index is not in the valid range. */
9229 my_getExpression (&imm_expr
, s
);
9230 check_absolute_expr (ip
, &imm_expr
);
9231 if ((unsigned) imm_expr
.X_add_number
< 32
9232 || (unsigned) imm_expr
.X_add_number
> 63)
9234 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9235 imm_expr
.X_op
= O_absent
;
9240 /* cins, cins32, exts and exts32 position field. Give error
9241 if it's not in the valid range. */
9242 my_getExpression (&imm_expr
, s
);
9243 check_absolute_expr (ip
, &imm_expr
);
9244 if ((unsigned) imm_expr
.X_add_number
> 31)
9246 as_bad (_("Improper position (%lu)"),
9247 (unsigned long) imm_expr
.X_add_number
);
9248 imm_expr
.X_add_number
= 0;
9250 /* Make the pos explicit to simplify +S. */
9251 lastpos
= imm_expr
.X_add_number
+ 32;
9252 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9253 imm_expr
.X_op
= O_absent
;
9258 /* cins, cins32, exts and exts32 position field. Move to
9259 the next candidate if it's not in the valid range. */
9260 my_getExpression (&imm_expr
, s
);
9261 check_absolute_expr (ip
, &imm_expr
);
9262 if ((unsigned) imm_expr
.X_add_number
< 32
9263 || (unsigned) imm_expr
.X_add_number
> 63)
9265 lastpos
= imm_expr
.X_add_number
;
9266 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9267 imm_expr
.X_op
= O_absent
;
9272 /* cins and exts length-minus-one field. */
9273 my_getExpression (&imm_expr
, s
);
9274 check_absolute_expr (ip
, &imm_expr
);
9275 if ((unsigned long) imm_expr
.X_add_number
> 31)
9277 as_bad (_("Improper size (%lu)"),
9278 (unsigned long) imm_expr
.X_add_number
);
9279 imm_expr
.X_add_number
= 0;
9281 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9282 imm_expr
.X_op
= O_absent
;
9287 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9288 length-minus-one field. */
9289 my_getExpression (&imm_expr
, s
);
9290 check_absolute_expr (ip
, &imm_expr
);
9291 if ((long) imm_expr
.X_add_number
< 0
9292 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9294 as_bad (_("Improper size (%lu)"),
9295 (unsigned long) imm_expr
.X_add_number
);
9296 imm_expr
.X_add_number
= 0;
9298 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9299 imm_expr
.X_op
= O_absent
;
9304 /* seqi/snei immediate field. */
9305 my_getExpression (&imm_expr
, s
);
9306 check_absolute_expr (ip
, &imm_expr
);
9307 if ((long) imm_expr
.X_add_number
< -512
9308 || (long) imm_expr
.X_add_number
>= 512)
9310 as_bad (_("Improper immediate (%ld)"),
9311 (long) imm_expr
.X_add_number
);
9312 imm_expr
.X_add_number
= 0;
9314 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9315 imm_expr
.X_op
= O_absent
;
9319 case 'a': /* 8-bit signed offset in bit 6 */
9320 my_getExpression (&imm_expr
, s
);
9321 check_absolute_expr (ip
, &imm_expr
);
9322 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
9323 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
9324 if (imm_expr
.X_add_number
< min_range
9325 || imm_expr
.X_add_number
> max_range
)
9327 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9328 (long) min_range
, (long) max_range
,
9329 (long) imm_expr
.X_add_number
);
9331 INSERT_OPERAND (OFFSET_A
, *ip
, imm_expr
.X_add_number
);
9332 imm_expr
.X_op
= O_absent
;
9336 case 'b': /* 8-bit signed offset in bit 3 */
9337 my_getExpression (&imm_expr
, s
);
9338 check_absolute_expr (ip
, &imm_expr
);
9339 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
9340 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
9341 if (imm_expr
.X_add_number
< min_range
9342 || imm_expr
.X_add_number
> max_range
)
9344 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9345 (long) min_range
, (long) max_range
,
9346 (long) imm_expr
.X_add_number
);
9348 INSERT_OPERAND (OFFSET_B
, *ip
, imm_expr
.X_add_number
);
9349 imm_expr
.X_op
= O_absent
;
9353 case 'c': /* 9-bit signed offset in bit 6 */
9354 my_getExpression (&imm_expr
, s
);
9355 check_absolute_expr (ip
, &imm_expr
);
9356 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
9357 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
9358 /* We check the offset range before adjusted. */
9361 if (imm_expr
.X_add_number
< min_range
9362 || imm_expr
.X_add_number
> max_range
)
9364 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9365 (long) min_range
, (long) max_range
,
9366 (long) imm_expr
.X_add_number
);
9368 if (imm_expr
.X_add_number
& 0xf)
9370 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9371 (long) imm_expr
.X_add_number
);
9373 /* Right shift 4 bits to adjust the offset operand. */
9374 INSERT_OPERAND (OFFSET_C
, *ip
, imm_expr
.X_add_number
>> 4);
9375 imm_expr
.X_op
= O_absent
;
9380 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
9382 if (regno
== AT
&& mips_opts
.at
)
9384 if (mips_opts
.at
== ATREG
)
9385 as_warn (_("used $at without \".set noat\""));
9387 as_warn (_("used $%u with \".set at=$%u\""),
9388 regno
, mips_opts
.at
);
9390 INSERT_OPERAND (RZ
, *ip
, regno
);
9394 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
9396 INSERT_OPERAND (FZ
, *ip
, regno
);
9400 as_bad (_("Internal error: bad mips opcode "
9401 "(unknown extension operand type `+%c'): %s %s"),
9402 *args
, insn
->name
, insn
->args
);
9403 /* Further processing is fruitless. */
9408 case '<': /* must be at least one digit */
9410 * According to the manual, if the shift amount is greater
9411 * than 31 or less than 0, then the shift amount should be
9412 * mod 32. In reality the mips assembler issues an error.
9413 * We issue a warning and mask out all but the low 5 bits.
9415 my_getExpression (&imm_expr
, s
);
9416 check_absolute_expr (ip
, &imm_expr
);
9417 if ((unsigned long) imm_expr
.X_add_number
> 31)
9418 as_warn (_("Improper shift amount (%lu)"),
9419 (unsigned long) imm_expr
.X_add_number
);
9420 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9421 imm_expr
.X_op
= O_absent
;
9425 case '>': /* shift amount minus 32 */
9426 my_getExpression (&imm_expr
, s
);
9427 check_absolute_expr (ip
, &imm_expr
);
9428 if ((unsigned long) imm_expr
.X_add_number
< 32
9429 || (unsigned long) imm_expr
.X_add_number
> 63)
9431 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9432 imm_expr
.X_op
= O_absent
;
9436 case 'k': /* CACHE code. */
9437 case 'h': /* PREFX code. */
9438 case '1': /* SYNC type. */
9439 my_getExpression (&imm_expr
, s
);
9440 check_absolute_expr (ip
, &imm_expr
);
9441 if ((unsigned long) imm_expr
.X_add_number
> 31)
9442 as_warn (_("Invalid value for `%s' (%lu)"),
9444 (unsigned long) imm_expr
.X_add_number
);
9447 if (mips_fix_cn63xxp1
&& strcmp ("pref", insn
->name
) == 0)
9448 switch (imm_expr
.X_add_number
)
9457 case 31: /* These are ok. */
9460 default: /* The rest must be changed to 28. */
9461 imm_expr
.X_add_number
= 28;
9464 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9466 else if (*args
== 'h')
9467 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9469 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9470 imm_expr
.X_op
= O_absent
;
9474 case 'c': /* BREAK code. */
9475 my_getExpression (&imm_expr
, s
);
9476 check_absolute_expr (ip
, &imm_expr
);
9477 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9478 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9480 (unsigned long) imm_expr
.X_add_number
);
9481 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9482 imm_expr
.X_op
= O_absent
;
9486 case 'q': /* Lower BREAK code. */
9487 my_getExpression (&imm_expr
, s
);
9488 check_absolute_expr (ip
, &imm_expr
);
9489 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9490 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9492 (unsigned long) imm_expr
.X_add_number
);
9493 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9494 imm_expr
.X_op
= O_absent
;
9498 case 'B': /* 20-bit SYSCALL/BREAK code. */
9499 my_getExpression (&imm_expr
, s
);
9500 check_absolute_expr (ip
, &imm_expr
);
9501 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9502 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9504 (unsigned long) imm_expr
.X_add_number
);
9505 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9506 imm_expr
.X_op
= O_absent
;
9510 case 'C': /* Coprocessor code. */
9511 my_getExpression (&imm_expr
, s
);
9512 check_absolute_expr (ip
, &imm_expr
);
9513 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9515 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9516 (unsigned long) imm_expr
.X_add_number
);
9517 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9519 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9520 imm_expr
.X_op
= O_absent
;
9524 case 'J': /* 19-bit WAIT code. */
9525 my_getExpression (&imm_expr
, s
);
9526 check_absolute_expr (ip
, &imm_expr
);
9527 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9529 as_warn (_("Illegal 19-bit code (%lu)"),
9530 (unsigned long) imm_expr
.X_add_number
);
9531 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9533 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9534 imm_expr
.X_op
= O_absent
;
9538 case 'P': /* Performance register. */
9539 my_getExpression (&imm_expr
, s
);
9540 check_absolute_expr (ip
, &imm_expr
);
9541 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9542 as_warn (_("Invalid performance register (%lu)"),
9543 (unsigned long) imm_expr
.X_add_number
);
9544 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9545 imm_expr
.X_op
= O_absent
;
9549 case 'G': /* Coprocessor destination register. */
9550 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9551 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9553 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9554 INSERT_OPERAND (RD
, *ip
, regno
);
9563 case 'b': /* Base register. */
9564 case 'd': /* Destination register. */
9565 case 's': /* Source register. */
9566 case 't': /* Target register. */
9567 case 'r': /* Both target and source. */
9568 case 'v': /* Both dest and source. */
9569 case 'w': /* Both dest and target. */
9570 case 'E': /* Coprocessor target register. */
9571 case 'K': /* RDHWR destination register. */
9572 case 'x': /* Ignore register name. */
9573 case 'z': /* Must be zero register. */
9574 case 'U': /* Destination register (CLO/CLZ). */
9575 case 'g': /* Coprocessor destination register. */
9577 if (*args
== 'E' || *args
== 'K')
9578 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9581 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9582 if (regno
== AT
&& mips_opts
.at
)
9584 if (mips_opts
.at
== ATREG
)
9585 as_warn (_("Used $at without \".set noat\""));
9587 as_warn (_("Used $%u with \".set at=$%u\""),
9588 regno
, mips_opts
.at
);
9598 if (c
== 'r' || c
== 'v' || c
== 'w')
9605 /* 'z' only matches $0. */
9606 if (c
== 'z' && regno
!= 0)
9609 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
9611 if (regno
== lastregno
)
9614 = _("Source and destination must be different");
9617 if (regno
== 31 && lastregno
== 0xffffffff)
9620 = _("A destination register must be supplied");
9624 /* Now that we have assembled one operand, we use the args
9625 string to figure out where it goes in the instruction. */
9632 INSERT_OPERAND (RS
, *ip
, regno
);
9637 INSERT_OPERAND (RD
, *ip
, regno
);
9640 INSERT_OPERAND (RD
, *ip
, regno
);
9641 INSERT_OPERAND (RT
, *ip
, regno
);
9646 INSERT_OPERAND (RT
, *ip
, regno
);
9649 /* This case exists because on the r3000 trunc
9650 expands into a macro which requires a gp
9651 register. On the r6000 or r4000 it is
9652 assembled into a single instruction which
9653 ignores the register. Thus the insn version
9654 is MIPS_ISA2 and uses 'x', and the macro
9655 version is MIPS_ISA1 and uses 't'. */
9658 /* This case is for the div instruction, which
9659 acts differently if the destination argument
9660 is $0. This only matches $0, and is checked
9661 outside the switch. */
9671 INSERT_OPERAND (RS
, *ip
, lastregno
);
9674 INSERT_OPERAND (RT
, *ip
, lastregno
);
9679 case 'O': /* MDMX alignment immediate constant. */
9680 my_getExpression (&imm_expr
, s
);
9681 check_absolute_expr (ip
, &imm_expr
);
9682 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9683 as_warn (_("Improper align amount (%ld), using low bits"),
9684 (long) imm_expr
.X_add_number
);
9685 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9686 imm_expr
.X_op
= O_absent
;
9690 case 'Q': /* MDMX vector, element sel, or const. */
9693 /* MDMX Immediate. */
9694 my_getExpression (&imm_expr
, s
);
9695 check_absolute_expr (ip
, &imm_expr
);
9696 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9697 as_warn (_("Invalid MDMX Immediate (%ld)"),
9698 (long) imm_expr
.X_add_number
);
9699 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9700 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9701 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9703 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9704 imm_expr
.X_op
= O_absent
;
9708 /* Not MDMX Immediate. Fall through. */
9709 case 'X': /* MDMX destination register. */
9710 case 'Y': /* MDMX source register. */
9711 case 'Z': /* MDMX target register. */
9713 case 'D': /* Floating point destination register. */
9714 case 'S': /* Floating point source register. */
9715 case 'T': /* Floating point target register. */
9716 case 'R': /* Floating point source register. */
9721 || (mips_opts
.ase_mdmx
9722 && (ip
->insn_mo
->pinfo
& FP_D
)
9723 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9724 | INSN_COPROC_MEMORY_DELAY
9725 | INSN_LOAD_COPROC_DELAY
9726 | INSN_LOAD_MEMORY_DELAY
9727 | INSN_STORE_MEMORY
))))
9730 if (reg_lookup (&s
, rtype
, ®no
))
9732 if ((regno
& 1) != 0
9734 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9735 as_warn (_("Float register should be even, was %d"),
9743 if (c
== 'V' || c
== 'W')
9754 INSERT_OPERAND (FD
, *ip
, regno
);
9759 INSERT_OPERAND (FS
, *ip
, regno
);
9762 /* This is like 'Z', but also needs to fix the MDMX
9763 vector/scalar select bits. Note that the
9764 scalar immediate case is handled above. */
9767 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9768 int max_el
= (is_qh
? 3 : 7);
9770 my_getExpression(&imm_expr
, s
);
9771 check_absolute_expr (ip
, &imm_expr
);
9773 if (imm_expr
.X_add_number
> max_el
)
9774 as_bad (_("Bad element selector %ld"),
9775 (long) imm_expr
.X_add_number
);
9776 imm_expr
.X_add_number
&= max_el
;
9777 ip
->insn_opcode
|= (imm_expr
.X_add_number
9780 imm_expr
.X_op
= O_absent
;
9782 as_warn (_("Expecting ']' found '%s'"), s
);
9788 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9789 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9792 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9799 INSERT_OPERAND (FT
, *ip
, regno
);
9802 INSERT_OPERAND (FR
, *ip
, regno
);
9812 INSERT_OPERAND (FS
, *ip
, lastregno
);
9815 INSERT_OPERAND (FT
, *ip
, lastregno
);
9821 my_getExpression (&imm_expr
, s
);
9822 if (imm_expr
.X_op
!= O_big
9823 && imm_expr
.X_op
!= O_constant
)
9824 insn_error
= _("absolute expression required");
9825 if (HAVE_32BIT_GPRS
)
9826 normalize_constant_expr (&imm_expr
);
9831 my_getExpression (&offset_expr
, s
);
9832 normalize_address_expr (&offset_expr
);
9833 *imm_reloc
= BFD_RELOC_32
;
9846 unsigned char temp
[8];
9848 unsigned int length
;
9853 /* These only appear as the last operand in an
9854 instruction, and every instruction that accepts
9855 them in any variant accepts them in all variants.
9856 This means we don't have to worry about backing out
9857 any changes if the instruction does not match.
9859 The difference between them is the size of the
9860 floating point constant and where it goes. For 'F'
9861 and 'L' the constant is 64 bits; for 'f' and 'l' it
9862 is 32 bits. Where the constant is placed is based
9863 on how the MIPS assembler does things:
9866 f -- immediate value
9869 The .lit4 and .lit8 sections are only used if
9870 permitted by the -G argument.
9872 The code below needs to know whether the target register
9873 is 32 or 64 bits wide. It relies on the fact 'f' and
9874 'F' are used with GPR-based instructions and 'l' and
9875 'L' are used with FPR-based instructions. */
9877 f64
= *args
== 'F' || *args
== 'L';
9878 using_gprs
= *args
== 'F' || *args
== 'f';
9880 save_in
= input_line_pointer
;
9881 input_line_pointer
= s
;
9882 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9884 s
= input_line_pointer
;
9885 input_line_pointer
= save_in
;
9886 if (err
!= NULL
&& *err
!= '\0')
9888 as_bad (_("Bad floating point constant: %s"), err
);
9889 memset (temp
, '\0', sizeof temp
);
9890 length
= f64
? 8 : 4;
9893 gas_assert (length
== (unsigned) (f64
? 8 : 4));
9897 && (g_switch_value
< 4
9898 || (temp
[0] == 0 && temp
[1] == 0)
9899 || (temp
[2] == 0 && temp
[3] == 0))))
9901 imm_expr
.X_op
= O_constant
;
9902 if (!target_big_endian
)
9903 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9905 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9908 && !mips_disable_float_construction
9909 /* Constants can only be constructed in GPRs and
9910 copied to FPRs if the GPRs are at least as wide
9911 as the FPRs. Force the constant into memory if
9912 we are using 64-bit FPRs but the GPRs are only
9915 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9916 && ((temp
[0] == 0 && temp
[1] == 0)
9917 || (temp
[2] == 0 && temp
[3] == 0))
9918 && ((temp
[4] == 0 && temp
[5] == 0)
9919 || (temp
[6] == 0 && temp
[7] == 0)))
9921 /* The value is simple enough to load with a couple of
9922 instructions. If using 32-bit registers, set
9923 imm_expr to the high order 32 bits and offset_expr to
9924 the low order 32 bits. Otherwise, set imm_expr to
9925 the entire 64 bit constant. */
9926 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9928 imm_expr
.X_op
= O_constant
;
9929 offset_expr
.X_op
= O_constant
;
9930 if (!target_big_endian
)
9932 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9933 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9937 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9938 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9940 if (offset_expr
.X_add_number
== 0)
9941 offset_expr
.X_op
= O_absent
;
9943 else if (sizeof (imm_expr
.X_add_number
) > 4)
9945 imm_expr
.X_op
= O_constant
;
9946 if (!target_big_endian
)
9947 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9949 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9953 imm_expr
.X_op
= O_big
;
9954 imm_expr
.X_add_number
= 4;
9955 if (!target_big_endian
)
9957 generic_bignum
[0] = bfd_getl16 (temp
);
9958 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9959 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9960 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9964 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9965 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9966 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9967 generic_bignum
[3] = bfd_getb16 (temp
);
9973 const char *newname
;
9976 /* Switch to the right section. */
9978 subseg
= now_subseg
;
9981 default: /* unused default case avoids warnings. */
9983 newname
= RDATA_SECTION_NAME
;
9984 if (g_switch_value
>= 8)
9988 newname
= RDATA_SECTION_NAME
;
9991 gas_assert (g_switch_value
>= 4);
9995 new_seg
= subseg_new (newname
, (subsegT
) 0);
9997 bfd_set_section_flags (stdoutput
, new_seg
,
10002 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
10003 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
10004 record_alignment (new_seg
, 4);
10006 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
10007 if (seg
== now_seg
)
10008 as_bad (_("Can't use floating point insn in this section"));
10010 /* Set the argument to the current address in the
10012 offset_expr
.X_op
= O_symbol
;
10013 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
10014 offset_expr
.X_add_number
= 0;
10016 /* Put the floating point number into the section. */
10017 p
= frag_more ((int) length
);
10018 memcpy (p
, temp
, length
);
10020 /* Switch back to the original section. */
10021 subseg_set (seg
, subseg
);
10026 case 'i': /* 16-bit unsigned immediate. */
10027 case 'j': /* 16-bit signed immediate. */
10028 *imm_reloc
= BFD_RELOC_LO16
;
10029 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
10032 offsetT minval
, maxval
;
10034 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
10035 && strcmp (insn
->name
, insn
[1].name
) == 0);
10037 /* If the expression was written as an unsigned number,
10038 only treat it as signed if there are no more
10042 && sizeof (imm_expr
.X_add_number
) <= 4
10043 && imm_expr
.X_op
== O_constant
10044 && imm_expr
.X_add_number
< 0
10045 && imm_expr
.X_unsigned
10046 && HAVE_64BIT_GPRS
)
10049 /* For compatibility with older assemblers, we accept
10050 0x8000-0xffff as signed 16-bit numbers when only
10051 signed numbers are allowed. */
10053 minval
= 0, maxval
= 0xffff;
10055 minval
= -0x8000, maxval
= 0x7fff;
10057 minval
= -0x8000, maxval
= 0xffff;
10059 if (imm_expr
.X_op
!= O_constant
10060 || imm_expr
.X_add_number
< minval
10061 || imm_expr
.X_add_number
> maxval
)
10065 if (imm_expr
.X_op
== O_constant
10066 || imm_expr
.X_op
== O_big
)
10067 as_bad (_("Expression out of range"));
10073 case 'o': /* 16-bit offset. */
10074 offset_reloc
[0] = BFD_RELOC_LO16
;
10075 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10076 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10078 /* Check whether there is only a single bracketed expression
10079 left. If so, it must be the base register and the
10080 constant must be zero. */
10081 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
10083 offset_expr
.X_op
= O_constant
;
10084 offset_expr
.X_add_number
= 0;
10088 /* If this value won't fit into a 16 bit offset, then go
10089 find a macro that will generate the 32 bit offset
10091 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
10092 && (offset_expr
.X_op
!= O_constant
10093 || offset_expr
.X_add_number
>= 0x8000
10094 || offset_expr
.X_add_number
< -0x8000))
10100 case 'p': /* PC-relative offset. */
10101 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
10102 my_getExpression (&offset_expr
, s
);
10106 case 'u': /* Upper 16 bits. */
10107 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
10108 && imm_expr
.X_op
== O_constant
10109 && (imm_expr
.X_add_number
< 0
10110 || imm_expr
.X_add_number
>= 0x10000))
10111 as_bad (_("lui expression (%lu) not in range 0..65535"),
10112 (unsigned long) imm_expr
.X_add_number
);
10116 case 'a': /* 26-bit address. */
10117 my_getExpression (&offset_expr
, s
);
10119 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
10122 case 'N': /* 3-bit branch condition code. */
10123 case 'M': /* 3-bit compare condition code. */
10125 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
10126 rtype
|= RTYPE_FCC
;
10127 if (!reg_lookup (&s
, rtype
, ®no
))
10129 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
10130 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
10131 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
10132 && (regno
& 1) != 0)
10133 as_warn (_("Condition code register should be even for %s, "
10136 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
10137 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
10138 && (regno
& 3) != 0)
10139 as_warn (_("Condition code register should be 0 or 4 for %s, "
10143 INSERT_OPERAND (BCC
, *ip
, regno
);
10145 INSERT_OPERAND (CCC
, *ip
, regno
);
10149 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
10160 while (ISDIGIT (*s
));
10163 c
= 8; /* Invalid sel value. */
10166 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10167 ip
->insn_opcode
|= c
;
10171 /* Must be at least one digit. */
10172 my_getExpression (&imm_expr
, s
);
10173 check_absolute_expr (ip
, &imm_expr
);
10175 if ((unsigned long) imm_expr
.X_add_number
10176 > (unsigned long) OP_MASK_VECBYTE
)
10178 as_bad (_("bad byte vector index (%ld)"),
10179 (long) imm_expr
.X_add_number
);
10180 imm_expr
.X_add_number
= 0;
10183 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
10184 imm_expr
.X_op
= O_absent
;
10189 my_getExpression (&imm_expr
, s
);
10190 check_absolute_expr (ip
, &imm_expr
);
10192 if ((unsigned long) imm_expr
.X_add_number
10193 > (unsigned long) OP_MASK_VECALIGN
)
10195 as_bad (_("bad byte vector index (%ld)"),
10196 (long) imm_expr
.X_add_number
);
10197 imm_expr
.X_add_number
= 0;
10200 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
10201 imm_expr
.X_op
= O_absent
;
10206 as_bad (_("Bad char = '%c'\n"), *args
);
10211 /* Args don't match. */
10212 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
10213 !strcmp (insn
->name
, insn
[1].name
))
10217 insn_error
= _("Illegal operands");
10221 *(--argsStart
) = save_c
;
10222 insn_error
= _("Illegal operands");
10227 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10229 /* This routine assembles an instruction into its binary format when
10230 assembling for the mips16. As a side effect, it sets one of the
10231 global variables imm_reloc or offset_reloc to the type of
10232 relocation to do if one of the operands is an address expression.
10233 It also sets mips16_small and mips16_ext if the user explicitly
10234 requested a small or extended instruction. */
10237 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
10241 struct mips_opcode
*insn
;
10243 unsigned int regno
;
10244 unsigned int lastregno
= 0;
10250 mips16_small
= FALSE
;
10251 mips16_ext
= FALSE
;
10253 for (s
= str
; ISLOWER (*s
); ++s
)
10265 if (s
[1] == 't' && s
[2] == ' ')
10268 mips16_small
= TRUE
;
10272 else if (s
[1] == 'e' && s
[2] == ' ')
10279 /* Fall through. */
10281 insn_error
= _("unknown opcode");
10285 if (mips_opts
.noautoextend
&& ! mips16_ext
)
10286 mips16_small
= TRUE
;
10288 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
10290 insn_error
= _("unrecognized opcode");
10299 gas_assert (strcmp (insn
->name
, str
) == 0);
10301 ok
= is_opcode_valid_16 (insn
);
10304 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10305 && strcmp (insn
->name
, insn
[1].name
) == 0)
10314 static char buf
[100];
10316 _("opcode not supported on this processor: %s (%s)"),
10317 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10318 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10325 create_insn (ip
, insn
);
10326 imm_expr
.X_op
= O_absent
;
10327 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10328 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10329 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10330 imm2_expr
.X_op
= O_absent
;
10331 offset_expr
.X_op
= O_absent
;
10332 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10333 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10334 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10335 for (args
= insn
->args
; 1; ++args
)
10342 /* In this switch statement we call break if we did not find
10343 a match, continue if we did find a match, or return if we
10352 /* Stuff the immediate value in now, if we can. */
10353 if (imm_expr
.X_op
== O_constant
10354 && *imm_reloc
> BFD_RELOC_UNUSED
10355 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
10356 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
10357 && insn
->pinfo
!= INSN_MACRO
)
10361 switch (*offset_reloc
)
10363 case BFD_RELOC_MIPS16_HI16_S
:
10364 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10367 case BFD_RELOC_MIPS16_HI16
:
10368 tmp
= imm_expr
.X_add_number
>> 16;
10371 case BFD_RELOC_MIPS16_LO16
:
10372 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10376 case BFD_RELOC_UNUSED
:
10377 tmp
= imm_expr
.X_add_number
;
10383 *offset_reloc
= BFD_RELOC_UNUSED
;
10385 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10386 tmp
, TRUE
, mips16_small
,
10387 mips16_ext
, &ip
->insn_opcode
,
10388 &ip
->use_extend
, &ip
->extend
);
10389 imm_expr
.X_op
= O_absent
;
10390 *imm_reloc
= BFD_RELOC_UNUSED
;
10404 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10407 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10423 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10425 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10429 /* Fall through. */
10440 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10442 if (c
== 'v' || c
== 'w')
10445 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10447 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10458 if (c
== 'v' || c
== 'w')
10460 regno
= mips16_to_32_reg_map
[lastregno
];
10474 regno
= mips32_to_16_reg_map
[regno
];
10479 regno
= ILLEGAL_REG
;
10484 regno
= ILLEGAL_REG
;
10489 regno
= ILLEGAL_REG
;
10494 if (regno
== AT
&& mips_opts
.at
)
10496 if (mips_opts
.at
== ATREG
)
10497 as_warn (_("used $at without \".set noat\""));
10499 as_warn (_("used $%u with \".set at=$%u\""),
10500 regno
, mips_opts
.at
);
10508 if (regno
== ILLEGAL_REG
)
10515 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10519 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10522 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10525 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10531 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10534 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10535 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10545 if (strncmp (s
, "$pc", 3) == 0)
10562 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10565 if (imm_expr
.X_op
!= O_constant
)
10568 ip
->use_extend
= TRUE
;
10573 /* We need to relax this instruction. */
10574 *offset_reloc
= *imm_reloc
;
10575 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10580 *imm_reloc
= BFD_RELOC_UNUSED
;
10581 /* Fall through. */
10588 my_getExpression (&imm_expr
, s
);
10589 if (imm_expr
.X_op
== O_register
)
10591 /* What we thought was an expression turned out to
10594 if (s
[0] == '(' && args
[1] == '(')
10596 /* It looks like the expression was omitted
10597 before a register indirection, which means
10598 that the expression is implicitly zero. We
10599 still set up imm_expr, so that we handle
10600 explicit extensions correctly. */
10601 imm_expr
.X_op
= O_constant
;
10602 imm_expr
.X_add_number
= 0;
10603 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10610 /* We need to relax this instruction. */
10611 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10620 /* We use offset_reloc rather than imm_reloc for the PC
10621 relative operands. This lets macros with both
10622 immediate and address operands work correctly. */
10623 my_getExpression (&offset_expr
, s
);
10625 if (offset_expr
.X_op
== O_register
)
10628 /* We need to relax this instruction. */
10629 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10633 case '6': /* break code */
10634 my_getExpression (&imm_expr
, s
);
10635 check_absolute_expr (ip
, &imm_expr
);
10636 if ((unsigned long) imm_expr
.X_add_number
> 63)
10637 as_warn (_("Invalid value for `%s' (%lu)"),
10639 (unsigned long) imm_expr
.X_add_number
);
10640 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10641 imm_expr
.X_op
= O_absent
;
10645 case 'a': /* 26 bit address */
10646 my_getExpression (&offset_expr
, s
);
10648 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10649 ip
->insn_opcode
<<= 16;
10652 case 'l': /* register list for entry macro */
10653 case 'L': /* register list for exit macro */
10663 unsigned int freg
, reg1
, reg2
;
10665 while (*s
== ' ' || *s
== ',')
10667 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10669 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10673 as_bad (_("can't parse register list"));
10683 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10684 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10686 as_bad (_("invalid register list"));
10690 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10692 mask
&= ~ (7 << 3);
10695 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10697 mask
&= ~ (7 << 3);
10700 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10701 mask
|= (reg2
- 3) << 3;
10702 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10703 mask
|= (reg2
- 15) << 1;
10704 else if (reg1
== RA
&& reg2
== RA
)
10708 as_bad (_("invalid register list"));
10712 /* The mask is filled in in the opcode table for the
10713 benefit of the disassembler. We remove it before
10714 applying the actual mask. */
10715 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10716 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10720 case 'm': /* Register list for save insn. */
10721 case 'M': /* Register list for restore insn. */
10724 int framesz
= 0, seen_framesz
= 0;
10725 int nargs
= 0, statics
= 0, sregs
= 0;
10729 unsigned int reg1
, reg2
;
10731 SKIP_SPACE_TABS (s
);
10734 SKIP_SPACE_TABS (s
);
10736 my_getExpression (&imm_expr
, s
);
10737 if (imm_expr
.X_op
== O_constant
)
10739 /* Handle the frame size. */
10742 as_bad (_("more than one frame size in list"));
10746 framesz
= imm_expr
.X_add_number
;
10747 imm_expr
.X_op
= O_absent
;
10752 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10754 as_bad (_("can't parse register list"));
10766 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10769 as_bad (_("can't parse register list"));
10774 while (reg1
<= reg2
)
10776 if (reg1
>= 4 && reg1
<= 7)
10780 nargs
|= 1 << (reg1
- 4);
10782 /* statics $a0-$a3 */
10783 statics
|= 1 << (reg1
- 4);
10785 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10788 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10790 else if (reg1
== 31)
10792 /* Add $ra to insn. */
10797 as_bad (_("unexpected register in list"));
10805 /* Encode args/statics combination. */
10806 if (nargs
& statics
)
10807 as_bad (_("arg/static registers overlap"));
10808 else if (nargs
== 0xf)
10809 /* All $a0-$a3 are args. */
10810 opcode
|= MIPS16_ALL_ARGS
<< 16;
10811 else if (statics
== 0xf)
10812 /* All $a0-$a3 are statics. */
10813 opcode
|= MIPS16_ALL_STATICS
<< 16;
10816 int narg
= 0, nstat
= 0;
10818 /* Count arg registers. */
10819 while (nargs
& 0x1)
10825 as_bad (_("invalid arg register list"));
10827 /* Count static registers. */
10828 while (statics
& 0x8)
10830 statics
= (statics
<< 1) & 0xf;
10834 as_bad (_("invalid static register list"));
10836 /* Encode args/statics. */
10837 opcode
|= ((narg
<< 2) | nstat
) << 16;
10840 /* Encode $s0/$s1. */
10841 if (sregs
& (1 << 0)) /* $s0 */
10843 if (sregs
& (1 << 1)) /* $s1 */
10849 /* Count regs $s2-$s8. */
10857 as_bad (_("invalid static register list"));
10858 /* Encode $s2-$s8. */
10859 opcode
|= nsreg
<< 24;
10862 /* Encode frame size. */
10864 as_bad (_("missing frame size"));
10865 else if ((framesz
& 7) != 0 || framesz
< 0
10866 || framesz
> 0xff * 8)
10867 as_bad (_("invalid frame size"));
10868 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10871 opcode
|= (((framesz
& 0xf0) << 16)
10872 | (framesz
& 0x0f));
10875 /* Finally build the instruction. */
10876 if ((opcode
>> 16) != 0 || framesz
== 0)
10878 ip
->use_extend
= TRUE
;
10879 ip
->extend
= opcode
>> 16;
10881 ip
->insn_opcode
|= opcode
& 0x7f;
10885 case 'e': /* extend code */
10886 my_getExpression (&imm_expr
, s
);
10887 check_absolute_expr (ip
, &imm_expr
);
10888 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10890 as_warn (_("Invalid value for `%s' (%lu)"),
10892 (unsigned long) imm_expr
.X_add_number
);
10893 imm_expr
.X_add_number
&= 0x7ff;
10895 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10896 imm_expr
.X_op
= O_absent
;
10906 /* Args don't match. */
10907 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10908 strcmp (insn
->name
, insn
[1].name
) == 0)
10915 insn_error
= _("illegal operands");
10921 /* This structure holds information we know about a mips16 immediate
10924 struct mips16_immed_operand
10926 /* The type code used in the argument string in the opcode table. */
10928 /* The number of bits in the short form of the opcode. */
10930 /* The number of bits in the extended form of the opcode. */
10932 /* The amount by which the short form is shifted when it is used;
10933 for example, the sw instruction has a shift count of 2. */
10935 /* The amount by which the short form is shifted when it is stored
10936 into the instruction code. */
10938 /* Non-zero if the short form is unsigned. */
10940 /* Non-zero if the extended form is unsigned. */
10942 /* Non-zero if the value is PC relative. */
10946 /* The mips16 immediate operand types. */
10948 static const struct mips16_immed_operand mips16_immed_operands
[] =
10950 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10951 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10952 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10953 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10954 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10955 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10956 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10957 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10958 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10959 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10960 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10961 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10962 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10963 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10964 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10965 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10966 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10967 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10968 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10969 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10970 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10973 #define MIPS16_NUM_IMMED \
10974 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10976 /* Handle a mips16 instruction with an immediate value. This or's the
10977 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10978 whether an extended value is needed; if one is needed, it sets
10979 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10980 If SMALL is true, an unextended opcode was explicitly requested.
10981 If EXT is true, an extended opcode was explicitly requested. If
10982 WARN is true, warn if EXT does not match reality. */
10985 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10986 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10987 unsigned long *insn
, bfd_boolean
*use_extend
,
10988 unsigned short *extend
)
10990 const struct mips16_immed_operand
*op
;
10991 int mintiny
, maxtiny
;
10992 bfd_boolean needext
;
10994 op
= mips16_immed_operands
;
10995 while (op
->type
!= type
)
10998 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11003 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11006 maxtiny
= 1 << op
->nbits
;
11011 maxtiny
= (1 << op
->nbits
) - 1;
11016 mintiny
= - (1 << (op
->nbits
- 1));
11017 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11020 /* Branch offsets have an implicit 0 in the lowest bit. */
11021 if (type
== 'p' || type
== 'q')
11024 if ((val
& ((1 << op
->shift
) - 1)) != 0
11025 || val
< (mintiny
<< op
->shift
)
11026 || val
> (maxtiny
<< op
->shift
))
11031 if (warn
&& ext
&& ! needext
)
11032 as_warn_where (file
, line
,
11033 _("extended operand requested but not required"));
11034 if (small
&& needext
)
11035 as_bad_where (file
, line
, _("invalid unextended operand value"));
11037 if (small
|| (! ext
&& ! needext
))
11041 *use_extend
= FALSE
;
11042 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
11043 insnval
<<= op
->op_shift
;
11048 long minext
, maxext
;
11054 maxext
= (1 << op
->extbits
) - 1;
11058 minext
= - (1 << (op
->extbits
- 1));
11059 maxext
= (1 << (op
->extbits
- 1)) - 1;
11061 if (val
< minext
|| val
> maxext
)
11062 as_bad_where (file
, line
,
11063 _("operand value out of range for instruction"));
11065 *use_extend
= TRUE
;
11066 if (op
->extbits
== 16)
11068 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
11071 else if (op
->extbits
== 15)
11073 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
11078 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
11082 *extend
= (unsigned short) extval
;
11087 struct percent_op_match
11090 bfd_reloc_code_real_type reloc
;
11093 static const struct percent_op_match mips_percent_op
[] =
11095 {"%lo", BFD_RELOC_LO16
},
11097 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
11098 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
11099 {"%call16", BFD_RELOC_MIPS_CALL16
},
11100 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
11101 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
11102 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
11103 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
11104 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
11105 {"%got", BFD_RELOC_MIPS_GOT16
},
11106 {"%gp_rel", BFD_RELOC_GPREL16
},
11107 {"%half", BFD_RELOC_16
},
11108 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
11109 {"%higher", BFD_RELOC_MIPS_HIGHER
},
11110 {"%neg", BFD_RELOC_MIPS_SUB
},
11111 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
11112 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
11113 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
11114 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
11115 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
11116 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
11117 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
11119 {"%hi", BFD_RELOC_HI16_S
}
11122 static const struct percent_op_match mips16_percent_op
[] =
11124 {"%lo", BFD_RELOC_MIPS16_LO16
},
11125 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
11126 {"%got", BFD_RELOC_MIPS16_GOT16
},
11127 {"%call16", BFD_RELOC_MIPS16_CALL16
},
11128 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
11132 /* Return true if *STR points to a relocation operator. When returning true,
11133 move *STR over the operator and store its relocation code in *RELOC.
11134 Leave both *STR and *RELOC alone when returning false. */
11137 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
11139 const struct percent_op_match
*percent_op
;
11142 if (mips_opts
.mips16
)
11144 percent_op
= mips16_percent_op
;
11145 limit
= ARRAY_SIZE (mips16_percent_op
);
11149 percent_op
= mips_percent_op
;
11150 limit
= ARRAY_SIZE (mips_percent_op
);
11153 for (i
= 0; i
< limit
; i
++)
11154 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
11156 int len
= strlen (percent_op
[i
].str
);
11158 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
11161 *str
+= strlen (percent_op
[i
].str
);
11162 *reloc
= percent_op
[i
].reloc
;
11164 /* Check whether the output BFD supports this relocation.
11165 If not, issue an error and fall back on something safe. */
11166 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
11168 as_bad (_("relocation %s isn't supported by the current ABI"),
11169 percent_op
[i
].str
);
11170 *reloc
= BFD_RELOC_UNUSED
;
11178 /* Parse string STR as a 16-bit relocatable operand. Store the
11179 expression in *EP and the relocations in the array starting
11180 at RELOC. Return the number of relocation operators used.
11182 On exit, EXPR_END points to the first character after the expression. */
11185 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
11188 bfd_reloc_code_real_type reversed_reloc
[3];
11189 size_t reloc_index
, i
;
11190 int crux_depth
, str_depth
;
11193 /* Search for the start of the main expression, recoding relocations
11194 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11195 of the main expression and with CRUX_DEPTH containing the number
11196 of open brackets at that point. */
11203 crux_depth
= str_depth
;
11205 /* Skip over whitespace and brackets, keeping count of the number
11207 while (*str
== ' ' || *str
== '\t' || *str
== '(')
11212 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
11213 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
11215 my_getExpression (ep
, crux
);
11218 /* Match every open bracket. */
11219 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
11223 if (crux_depth
> 0)
11224 as_bad (_("unclosed '('"));
11228 if (reloc_index
!= 0)
11230 prev_reloc_op_frag
= frag_now
;
11231 for (i
= 0; i
< reloc_index
; i
++)
11232 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
11235 return reloc_index
;
11239 my_getExpression (expressionS
*ep
, char *str
)
11243 save_in
= input_line_pointer
;
11244 input_line_pointer
= str
;
11246 expr_end
= input_line_pointer
;
11247 input_line_pointer
= save_in
;
11251 md_atof (int type
, char *litP
, int *sizeP
)
11253 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
11257 md_number_to_chars (char *buf
, valueT val
, int n
)
11259 if (target_big_endian
)
11260 number_to_chars_bigendian (buf
, val
, n
);
11262 number_to_chars_littleendian (buf
, val
, n
);
11266 static int support_64bit_objects(void)
11268 const char **list
, **l
;
11271 list
= bfd_target_list ();
11272 for (l
= list
; *l
!= NULL
; l
++)
11273 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
11274 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
11276 yes
= (*l
!= NULL
);
11280 #endif /* OBJ_ELF */
11282 const char *md_shortopts
= "O::g::G:";
11286 OPTION_MARCH
= OPTION_MD_BASE
,
11308 OPTION_NO_SMARTMIPS
,
11311 OPTION_COMPAT_ARCH_BASE
,
11320 OPTION_M7000_HILO_FIX
,
11321 OPTION_MNO_7000_HILO_FIX
,
11324 OPTION_FIX_LOONGSON2F_JUMP
,
11325 OPTION_NO_FIX_LOONGSON2F_JUMP
,
11326 OPTION_FIX_LOONGSON2F_NOP
,
11327 OPTION_NO_FIX_LOONGSON2F_NOP
,
11329 OPTION_NO_FIX_VR4120
,
11331 OPTION_NO_FIX_VR4130
,
11332 OPTION_FIX_CN63XXP1
,
11333 OPTION_NO_FIX_CN63XXP1
,
11340 OPTION_CONSTRUCT_FLOATS
,
11341 OPTION_NO_CONSTRUCT_FLOATS
,
11344 OPTION_RELAX_BRANCH
,
11345 OPTION_NO_RELAX_BRANCH
,
11352 OPTION_SINGLE_FLOAT
,
11353 OPTION_DOUBLE_FLOAT
,
11356 OPTION_CALL_SHARED
,
11357 OPTION_CALL_NONPIC
,
11367 OPTION_MVXWORKS_PIC
,
11368 #endif /* OBJ_ELF */
11372 struct option md_longopts
[] =
11374 /* Options which specify architecture. */
11375 {"march", required_argument
, NULL
, OPTION_MARCH
},
11376 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11377 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11378 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11379 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11380 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11381 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11382 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11383 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11384 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11385 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11386 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11388 /* Options which specify Application Specific Extensions (ASEs). */
11389 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11390 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11391 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11392 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11393 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11394 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11395 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11396 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11397 {"mmt", no_argument
, NULL
, OPTION_MT
},
11398 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11399 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11400 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11401 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11402 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11404 /* Old-style architecture options. Don't add more of these. */
11405 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11406 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11407 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11408 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11409 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11410 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11411 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11412 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11414 /* Options which enable bug fixes. */
11415 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11416 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11417 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11418 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
11419 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
11420 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
11421 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
11422 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11423 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11424 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11425 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11426 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
11427 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
11428 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
11429 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
11431 /* Miscellaneous options. */
11432 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11433 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11434 {"break", no_argument
, NULL
, OPTION_BREAK
},
11435 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11436 {"EB", no_argument
, NULL
, OPTION_EB
},
11437 {"EL", no_argument
, NULL
, OPTION_EL
},
11438 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11439 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11440 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11441 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11442 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11443 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11444 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11445 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11446 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11447 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11448 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11449 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11450 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11451 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11452 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11453 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11455 /* Strictly speaking this next option is ELF specific,
11456 but we allow it for other ports as well in order to
11457 make testing easier. */
11458 {"32", no_argument
, NULL
, OPTION_32
},
11460 /* ELF-specific options. */
11462 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11463 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11464 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
11465 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11466 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11467 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11468 {"n32", no_argument
, NULL
, OPTION_N32
},
11469 {"64", no_argument
, NULL
, OPTION_64
},
11470 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11471 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11472 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11473 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11474 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11475 #endif /* OBJ_ELF */
11477 {NULL
, no_argument
, NULL
, 0}
11479 size_t md_longopts_size
= sizeof (md_longopts
);
11481 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11482 NEW_VALUE. Warn if another value was already specified. Note:
11483 we have to defer parsing the -march and -mtune arguments in order
11484 to handle 'from-abi' correctly, since the ABI might be specified
11485 in a later argument. */
11488 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11490 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11491 as_warn (_("A different %s was already specified, is now %s"),
11492 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11495 *string_ptr
= new_value
;
11499 md_parse_option (int c
, char *arg
)
11503 case OPTION_CONSTRUCT_FLOATS
:
11504 mips_disable_float_construction
= 0;
11507 case OPTION_NO_CONSTRUCT_FLOATS
:
11508 mips_disable_float_construction
= 1;
11520 target_big_endian
= 1;
11524 target_big_endian
= 0;
11530 else if (arg
[0] == '0')
11532 else if (arg
[0] == '1')
11542 mips_debug
= atoi (arg
);
11546 file_mips_isa
= ISA_MIPS1
;
11550 file_mips_isa
= ISA_MIPS2
;
11554 file_mips_isa
= ISA_MIPS3
;
11558 file_mips_isa
= ISA_MIPS4
;
11562 file_mips_isa
= ISA_MIPS5
;
11565 case OPTION_MIPS32
:
11566 file_mips_isa
= ISA_MIPS32
;
11569 case OPTION_MIPS32R2
:
11570 file_mips_isa
= ISA_MIPS32R2
;
11573 case OPTION_MIPS64R2
:
11574 file_mips_isa
= ISA_MIPS64R2
;
11577 case OPTION_MIPS64
:
11578 file_mips_isa
= ISA_MIPS64
;
11582 mips_set_option_string (&mips_tune_string
, arg
);
11586 mips_set_option_string (&mips_arch_string
, arg
);
11590 mips_set_option_string (&mips_arch_string
, "4650");
11591 mips_set_option_string (&mips_tune_string
, "4650");
11594 case OPTION_NO_M4650
:
11598 mips_set_option_string (&mips_arch_string
, "4010");
11599 mips_set_option_string (&mips_tune_string
, "4010");
11602 case OPTION_NO_M4010
:
11606 mips_set_option_string (&mips_arch_string
, "4100");
11607 mips_set_option_string (&mips_tune_string
, "4100");
11610 case OPTION_NO_M4100
:
11614 mips_set_option_string (&mips_arch_string
, "3900");
11615 mips_set_option_string (&mips_tune_string
, "3900");
11618 case OPTION_NO_M3900
:
11622 mips_opts
.ase_mdmx
= 1;
11625 case OPTION_NO_MDMX
:
11626 mips_opts
.ase_mdmx
= 0;
11630 mips_opts
.ase_dsp
= 1;
11631 mips_opts
.ase_dspr2
= 0;
11634 case OPTION_NO_DSP
:
11635 mips_opts
.ase_dsp
= 0;
11636 mips_opts
.ase_dspr2
= 0;
11640 mips_opts
.ase_dspr2
= 1;
11641 mips_opts
.ase_dsp
= 1;
11644 case OPTION_NO_DSPR2
:
11645 mips_opts
.ase_dspr2
= 0;
11646 mips_opts
.ase_dsp
= 0;
11650 mips_opts
.ase_mt
= 1;
11654 mips_opts
.ase_mt
= 0;
11657 case OPTION_MIPS16
:
11658 mips_opts
.mips16
= 1;
11659 mips_no_prev_insn ();
11662 case OPTION_NO_MIPS16
:
11663 mips_opts
.mips16
= 0;
11664 mips_no_prev_insn ();
11667 case OPTION_MIPS3D
:
11668 mips_opts
.ase_mips3d
= 1;
11671 case OPTION_NO_MIPS3D
:
11672 mips_opts
.ase_mips3d
= 0;
11675 case OPTION_SMARTMIPS
:
11676 mips_opts
.ase_smartmips
= 1;
11679 case OPTION_NO_SMARTMIPS
:
11680 mips_opts
.ase_smartmips
= 0;
11683 case OPTION_FIX_24K
:
11687 case OPTION_NO_FIX_24K
:
11691 case OPTION_FIX_LOONGSON2F_JUMP
:
11692 mips_fix_loongson2f_jump
= TRUE
;
11695 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
11696 mips_fix_loongson2f_jump
= FALSE
;
11699 case OPTION_FIX_LOONGSON2F_NOP
:
11700 mips_fix_loongson2f_nop
= TRUE
;
11703 case OPTION_NO_FIX_LOONGSON2F_NOP
:
11704 mips_fix_loongson2f_nop
= FALSE
;
11707 case OPTION_FIX_VR4120
:
11708 mips_fix_vr4120
= 1;
11711 case OPTION_NO_FIX_VR4120
:
11712 mips_fix_vr4120
= 0;
11715 case OPTION_FIX_VR4130
:
11716 mips_fix_vr4130
= 1;
11719 case OPTION_NO_FIX_VR4130
:
11720 mips_fix_vr4130
= 0;
11723 case OPTION_FIX_CN63XXP1
:
11724 mips_fix_cn63xxp1
= TRUE
;
11727 case OPTION_NO_FIX_CN63XXP1
:
11728 mips_fix_cn63xxp1
= FALSE
;
11731 case OPTION_RELAX_BRANCH
:
11732 mips_relax_branch
= 1;
11735 case OPTION_NO_RELAX_BRANCH
:
11736 mips_relax_branch
= 0;
11739 case OPTION_MSHARED
:
11740 mips_in_shared
= TRUE
;
11743 case OPTION_MNO_SHARED
:
11744 mips_in_shared
= FALSE
;
11747 case OPTION_MSYM32
:
11748 mips_opts
.sym32
= TRUE
;
11751 case OPTION_MNO_SYM32
:
11752 mips_opts
.sym32
= FALSE
;
11756 /* When generating ELF code, we permit -KPIC and -call_shared to
11757 select SVR4_PIC, and -non_shared to select no PIC. This is
11758 intended to be compatible with Irix 5. */
11759 case OPTION_CALL_SHARED
:
11762 as_bad (_("-call_shared is supported only for ELF format"));
11765 mips_pic
= SVR4_PIC
;
11766 mips_abicalls
= TRUE
;
11769 case OPTION_CALL_NONPIC
:
11772 as_bad (_("-call_nonpic is supported only for ELF format"));
11776 mips_abicalls
= TRUE
;
11779 case OPTION_NON_SHARED
:
11782 as_bad (_("-non_shared is supported only for ELF format"));
11786 mips_abicalls
= FALSE
;
11789 /* The -xgot option tells the assembler to use 32 bit offsets
11790 when accessing the got in SVR4_PIC mode. It is for Irix
11795 #endif /* OBJ_ELF */
11798 g_switch_value
= atoi (arg
);
11802 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11806 mips_abi
= O32_ABI
;
11807 /* We silently ignore -32 for non-ELF targets. This greatly
11808 simplifies the construction of the MIPS GAS test cases. */
11815 as_bad (_("-n32 is supported for ELF format only"));
11818 mips_abi
= N32_ABI
;
11824 as_bad (_("-64 is supported for ELF format only"));
11827 mips_abi
= N64_ABI
;
11828 if (!support_64bit_objects())
11829 as_fatal (_("No compiled in support for 64 bit object file format"));
11831 #endif /* OBJ_ELF */
11834 file_mips_gp32
= 1;
11838 file_mips_gp32
= 0;
11842 file_mips_fp32
= 1;
11846 file_mips_fp32
= 0;
11849 case OPTION_SINGLE_FLOAT
:
11850 file_mips_single_float
= 1;
11853 case OPTION_DOUBLE_FLOAT
:
11854 file_mips_single_float
= 0;
11857 case OPTION_SOFT_FLOAT
:
11858 file_mips_soft_float
= 1;
11861 case OPTION_HARD_FLOAT
:
11862 file_mips_soft_float
= 0;
11869 as_bad (_("-mabi is supported for ELF format only"));
11872 if (strcmp (arg
, "32") == 0)
11873 mips_abi
= O32_ABI
;
11874 else if (strcmp (arg
, "o64") == 0)
11875 mips_abi
= O64_ABI
;
11876 else if (strcmp (arg
, "n32") == 0)
11877 mips_abi
= N32_ABI
;
11878 else if (strcmp (arg
, "64") == 0)
11880 mips_abi
= N64_ABI
;
11881 if (! support_64bit_objects())
11882 as_fatal (_("No compiled in support for 64 bit object file "
11885 else if (strcmp (arg
, "eabi") == 0)
11886 mips_abi
= EABI_ABI
;
11889 as_fatal (_("invalid abi -mabi=%s"), arg
);
11893 #endif /* OBJ_ELF */
11895 case OPTION_M7000_HILO_FIX
:
11896 mips_7000_hilo_fix
= TRUE
;
11899 case OPTION_MNO_7000_HILO_FIX
:
11900 mips_7000_hilo_fix
= FALSE
;
11904 case OPTION_MDEBUG
:
11905 mips_flag_mdebug
= TRUE
;
11908 case OPTION_NO_MDEBUG
:
11909 mips_flag_mdebug
= FALSE
;
11913 mips_flag_pdr
= TRUE
;
11916 case OPTION_NO_PDR
:
11917 mips_flag_pdr
= FALSE
;
11920 case OPTION_MVXWORKS_PIC
:
11921 mips_pic
= VXWORKS_PIC
;
11923 #endif /* OBJ_ELF */
11929 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
11934 /* Set up globals to generate code for the ISA or processor
11935 described by INFO. */
11938 mips_set_architecture (const struct mips_cpu_info
*info
)
11942 file_mips_arch
= info
->cpu
;
11943 mips_opts
.arch
= info
->cpu
;
11944 mips_opts
.isa
= info
->isa
;
11949 /* Likewise for tuning. */
11952 mips_set_tune (const struct mips_cpu_info
*info
)
11955 mips_tune
= info
->cpu
;
11960 mips_after_parse_args (void)
11962 const struct mips_cpu_info
*arch_info
= 0;
11963 const struct mips_cpu_info
*tune_info
= 0;
11965 /* GP relative stuff not working for PE */
11966 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11968 if (g_switch_seen
&& g_switch_value
!= 0)
11969 as_bad (_("-G not supported in this configuration."));
11970 g_switch_value
= 0;
11973 if (mips_abi
== NO_ABI
)
11974 mips_abi
= MIPS_DEFAULT_ABI
;
11976 /* The following code determines the architecture and register size.
11977 Similar code was added to GCC 3.3 (see override_options() in
11978 config/mips/mips.c). The GAS and GCC code should be kept in sync
11979 as much as possible. */
11981 if (mips_arch_string
!= 0)
11982 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11984 if (file_mips_isa
!= ISA_UNKNOWN
)
11986 /* Handle -mipsN. At this point, file_mips_isa contains the
11987 ISA level specified by -mipsN, while arch_info->isa contains
11988 the -march selection (if any). */
11989 if (arch_info
!= 0)
11991 /* -march takes precedence over -mipsN, since it is more descriptive.
11992 There's no harm in specifying both as long as the ISA levels
11994 if (file_mips_isa
!= arch_info
->isa
)
11995 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11996 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11997 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
12000 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
12003 if (arch_info
== 0)
12004 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
12006 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
12007 as_bad (_("-march=%s is not compatible with the selected ABI"),
12010 mips_set_architecture (arch_info
);
12012 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12013 if (mips_tune_string
!= 0)
12014 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
12016 if (tune_info
== 0)
12017 mips_set_tune (arch_info
);
12019 mips_set_tune (tune_info
);
12021 if (file_mips_gp32
>= 0)
12023 /* The user specified the size of the integer registers. Make sure
12024 it agrees with the ABI and ISA. */
12025 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12026 as_bad (_("-mgp64 used with a 32-bit processor"));
12027 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
12028 as_bad (_("-mgp32 used with a 64-bit ABI"));
12029 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
12030 as_bad (_("-mgp64 used with a 32-bit ABI"));
12034 /* Infer the integer register size from the ABI and processor.
12035 Restrict ourselves to 32-bit registers if that's all the
12036 processor has, or if the ABI cannot handle 64-bit registers. */
12037 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
12038 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
12041 switch (file_mips_fp32
)
12045 /* No user specified float register size.
12046 ??? GAS treats single-float processors as though they had 64-bit
12047 float registers (although it complains when double-precision
12048 instructions are used). As things stand, saying they have 32-bit
12049 registers would lead to spurious "register must be even" messages.
12050 So here we assume float registers are never smaller than the
12052 if (file_mips_gp32
== 0)
12053 /* 64-bit integer registers implies 64-bit float registers. */
12054 file_mips_fp32
= 0;
12055 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
12056 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12057 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12058 file_mips_fp32
= 0;
12060 /* 32-bit float registers. */
12061 file_mips_fp32
= 1;
12064 /* The user specified the size of the float registers. Check if it
12065 agrees with the ABI and ISA. */
12067 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12068 as_bad (_("-mfp64 used with a 32-bit fpu"));
12069 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
12070 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
12071 as_warn (_("-mfp64 used with a 32-bit ABI"));
12074 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
12075 as_warn (_("-mfp32 used with a 64-bit ABI"));
12079 /* End of GCC-shared inference code. */
12081 /* This flag is set when we have a 64-bit capable CPU but use only
12082 32-bit wide registers. Note that EABI does not use it. */
12083 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
12084 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
12085 || mips_abi
== O32_ABI
))
12086 mips_32bitmode
= 1;
12088 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
12089 as_bad (_("trap exception not supported at ISA 1"));
12091 /* If the selected architecture includes support for ASEs, enable
12092 generation of code for them. */
12093 if (mips_opts
.mips16
== -1)
12094 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
12095 if (mips_opts
.ase_mips3d
== -1)
12096 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
12097 && file_mips_fp32
== 0) ? 1 : 0;
12098 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
12099 as_bad (_("-mfp32 used with -mips3d"));
12101 if (mips_opts
.ase_mdmx
== -1)
12102 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
12103 && file_mips_fp32
== 0) ? 1 : 0;
12104 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
12105 as_bad (_("-mfp32 used with -mdmx"));
12107 if (mips_opts
.ase_smartmips
== -1)
12108 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
12109 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
12110 as_warn (_("%s ISA does not support SmartMIPS"),
12111 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12113 if (mips_opts
.ase_dsp
== -1)
12114 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
12115 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
12116 as_warn (_("%s ISA does not support DSP ASE"),
12117 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12119 if (mips_opts
.ase_dspr2
== -1)
12121 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
12122 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
12124 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
12125 as_warn (_("%s ISA does not support DSP R2 ASE"),
12126 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12128 if (mips_opts
.ase_mt
== -1)
12129 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
12130 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
12131 as_warn (_("%s ISA does not support MT ASE"),
12132 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12134 file_mips_isa
= mips_opts
.isa
;
12135 file_ase_mips3d
= mips_opts
.ase_mips3d
;
12136 file_ase_mdmx
= mips_opts
.ase_mdmx
;
12137 file_ase_smartmips
= mips_opts
.ase_smartmips
;
12138 file_ase_dsp
= mips_opts
.ase_dsp
;
12139 file_ase_dspr2
= mips_opts
.ase_dspr2
;
12140 file_ase_mt
= mips_opts
.ase_mt
;
12141 mips_opts
.gp32
= file_mips_gp32
;
12142 mips_opts
.fp32
= file_mips_fp32
;
12143 mips_opts
.soft_float
= file_mips_soft_float
;
12144 mips_opts
.single_float
= file_mips_single_float
;
12146 if (mips_flag_mdebug
< 0)
12148 #ifdef OBJ_MAYBE_ECOFF
12149 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
12150 mips_flag_mdebug
= 1;
12152 #endif /* OBJ_MAYBE_ECOFF */
12153 mips_flag_mdebug
= 0;
12158 mips_init_after_args (void)
12160 /* initialize opcodes */
12161 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
12162 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
12166 md_pcrel_from (fixS
*fixP
)
12168 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12169 switch (fixP
->fx_r_type
)
12171 case BFD_RELOC_16_PCREL_S2
:
12172 case BFD_RELOC_MIPS_JMP
:
12173 /* Return the address of the delay slot. */
12176 /* We have no relocation type for PC relative MIPS16 instructions. */
12177 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
12178 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12179 _("PC relative MIPS16 instruction references a different section"));
12184 /* This is called before the symbol table is processed. In order to
12185 work with gcc when using mips-tfile, we must keep all local labels.
12186 However, in other cases, we want to discard them. If we were
12187 called with -g, but we didn't see any debugging information, it may
12188 mean that gcc is smuggling debugging information through to
12189 mips-tfile, in which case we must generate all local labels. */
12192 mips_frob_file_before_adjust (void)
12194 #ifndef NO_ECOFF_DEBUGGING
12195 if (ECOFF_DEBUGGING
12197 && ! ecoff_debugging_seen
)
12198 flag_keep_locals
= 1;
12202 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12203 the corresponding LO16 reloc. This is called before md_apply_fix and
12204 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12205 relocation operators.
12207 For our purposes, a %lo() expression matches a %got() or %hi()
12210 (a) it refers to the same symbol; and
12211 (b) the offset applied in the %lo() expression is no lower than
12212 the offset applied in the %got() or %hi().
12214 (b) allows us to cope with code like:
12217 lh $4,%lo(foo+2)($4)
12219 ...which is legal on RELA targets, and has a well-defined behaviour
12220 if the user knows that adding 2 to "foo" will not induce a carry to
12223 When several %lo()s match a particular %got() or %hi(), we use the
12224 following rules to distinguish them:
12226 (1) %lo()s with smaller offsets are a better match than %lo()s with
12229 (2) %lo()s with no matching %got() or %hi() are better than those
12230 that already have a matching %got() or %hi().
12232 (3) later %lo()s are better than earlier %lo()s.
12234 These rules are applied in order.
12236 (1) means, among other things, that %lo()s with identical offsets are
12237 chosen if they exist.
12239 (2) means that we won't associate several high-part relocations with
12240 the same low-part relocation unless there's no alternative. Having
12241 several high parts for the same low part is a GNU extension; this rule
12242 allows careful users to avoid it.
12244 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12245 with the last high-part relocation being at the front of the list.
12246 It therefore makes sense to choose the last matching low-part
12247 relocation, all other things being equal. It's also easier
12248 to code that way. */
12251 mips_frob_file (void)
12253 struct mips_hi_fixup
*l
;
12254 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
12256 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
12258 segment_info_type
*seginfo
;
12259 bfd_boolean matched_lo_p
;
12260 fixS
**hi_pos
, **lo_pos
, **pos
;
12262 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
12264 /* If a GOT16 relocation turns out to be against a global symbol,
12265 there isn't supposed to be a matching LO. */
12266 if (got16_reloc_p (l
->fixp
->fx_r_type
)
12267 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
12270 /* Check quickly whether the next fixup happens to be a matching %lo. */
12271 if (fixup_has_matching_lo_p (l
->fixp
))
12274 seginfo
= seg_info (l
->seg
);
12276 /* Set HI_POS to the position of this relocation in the chain.
12277 Set LO_POS to the position of the chosen low-part relocation.
12278 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12279 relocation that matches an immediately-preceding high-part
12283 matched_lo_p
= FALSE
;
12284 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
12286 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
12288 if (*pos
== l
->fixp
)
12291 if ((*pos
)->fx_r_type
== looking_for_rtype
12292 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
12293 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
12295 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
12297 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
12300 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
12301 && fixup_has_matching_lo_p (*pos
));
12304 /* If we found a match, remove the high-part relocation from its
12305 current position and insert it before the low-part relocation.
12306 Make the offsets match so that fixup_has_matching_lo_p()
12309 We don't warn about unmatched high-part relocations since some
12310 versions of gcc have been known to emit dead "lui ...%hi(...)"
12312 if (lo_pos
!= NULL
)
12314 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
12315 if (l
->fixp
->fx_next
!= *lo_pos
)
12317 *hi_pos
= l
->fixp
->fx_next
;
12318 l
->fixp
->fx_next
= *lo_pos
;
12325 /* We may have combined relocations without symbols in the N32/N64 ABI.
12326 We have to prevent gas from dropping them. */
12329 mips_force_relocation (fixS
*fixp
)
12331 if (generic_force_reloc (fixp
))
12335 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
12336 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
12337 || hi16_reloc_p (fixp
->fx_r_type
)
12338 || lo16_reloc_p (fixp
->fx_r_type
)))
12344 /* Apply a fixup to the object file. */
12347 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12351 reloc_howto_type
*howto
;
12353 /* We ignore generic BFD relocations we don't know about. */
12354 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12358 gas_assert (fixP
->fx_size
== 4
12359 || fixP
->fx_r_type
== BFD_RELOC_16
12360 || fixP
->fx_r_type
== BFD_RELOC_64
12361 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12362 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12363 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12364 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12365 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12367 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12369 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12371 /* Don't treat parts of a composite relocation as done. There are two
12374 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12375 should nevertheless be emitted if the first part is.
12377 (2) In normal usage, composite relocations are never assembly-time
12378 constants. The easiest way of dealing with the pathological
12379 exceptions is to generate a relocation against STN_UNDEF and
12380 leave everything up to the linker. */
12381 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12384 switch (fixP
->fx_r_type
)
12386 case BFD_RELOC_MIPS_TLS_GD
:
12387 case BFD_RELOC_MIPS_TLS_LDM
:
12388 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12389 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12390 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12391 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12392 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12393 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12394 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12395 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12398 case BFD_RELOC_MIPS_JMP
:
12399 case BFD_RELOC_MIPS_SHIFT5
:
12400 case BFD_RELOC_MIPS_SHIFT6
:
12401 case BFD_RELOC_MIPS_GOT_DISP
:
12402 case BFD_RELOC_MIPS_GOT_PAGE
:
12403 case BFD_RELOC_MIPS_GOT_OFST
:
12404 case BFD_RELOC_MIPS_SUB
:
12405 case BFD_RELOC_MIPS_INSERT_A
:
12406 case BFD_RELOC_MIPS_INSERT_B
:
12407 case BFD_RELOC_MIPS_DELETE
:
12408 case BFD_RELOC_MIPS_HIGHEST
:
12409 case BFD_RELOC_MIPS_HIGHER
:
12410 case BFD_RELOC_MIPS_SCN_DISP
:
12411 case BFD_RELOC_MIPS_REL16
:
12412 case BFD_RELOC_MIPS_RELGOT
:
12413 case BFD_RELOC_MIPS_JALR
:
12414 case BFD_RELOC_HI16
:
12415 case BFD_RELOC_HI16_S
:
12416 case BFD_RELOC_GPREL16
:
12417 case BFD_RELOC_MIPS_LITERAL
:
12418 case BFD_RELOC_MIPS_CALL16
:
12419 case BFD_RELOC_MIPS_GOT16
:
12420 case BFD_RELOC_GPREL32
:
12421 case BFD_RELOC_MIPS_GOT_HI16
:
12422 case BFD_RELOC_MIPS_GOT_LO16
:
12423 case BFD_RELOC_MIPS_CALL_HI16
:
12424 case BFD_RELOC_MIPS_CALL_LO16
:
12425 case BFD_RELOC_MIPS16_GPREL
:
12426 case BFD_RELOC_MIPS16_GOT16
:
12427 case BFD_RELOC_MIPS16_CALL16
:
12428 case BFD_RELOC_MIPS16_HI16
:
12429 case BFD_RELOC_MIPS16_HI16_S
:
12430 case BFD_RELOC_MIPS16_JMP
:
12431 /* Nothing needed to do. The value comes from the reloc entry. */
12435 /* This is handled like BFD_RELOC_32, but we output a sign
12436 extended value if we are only 32 bits. */
12439 if (8 <= sizeof (valueT
))
12440 md_number_to_chars ((char *) buf
, *valP
, 8);
12445 if ((*valP
& 0x80000000) != 0)
12449 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12451 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12457 case BFD_RELOC_RVA
:
12460 /* If we are deleting this reloc entry, we must fill in the
12461 value now. This can happen if we have a .word which is not
12462 resolved when it appears but is later defined. */
12464 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12467 case BFD_RELOC_LO16
:
12468 case BFD_RELOC_MIPS16_LO16
:
12469 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12470 may be safe to remove, but if so it's not obvious. */
12471 /* When handling an embedded PIC switch statement, we can wind
12472 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12475 if (*valP
+ 0x8000 > 0xffff)
12476 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12477 _("relocation overflow"));
12478 if (target_big_endian
)
12480 md_number_to_chars ((char *) buf
, *valP
, 2);
12484 case BFD_RELOC_16_PCREL_S2
:
12485 if ((*valP
& 0x3) != 0)
12486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12487 _("Branch to misaligned address (%lx)"), (long) *valP
);
12489 /* We need to save the bits in the instruction since fixup_segment()
12490 might be deleting the relocation entry (i.e., a branch within
12491 the current segment). */
12492 if (! fixP
->fx_done
)
12495 /* Update old instruction data. */
12496 if (target_big_endian
)
12497 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12499 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12501 if (*valP
+ 0x20000 <= 0x3ffff)
12503 insn
|= (*valP
>> 2) & 0xffff;
12504 md_number_to_chars ((char *) buf
, insn
, 4);
12506 else if (mips_pic
== NO_PIC
12508 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12509 && (fixP
->fx_frag
->fr_address
12510 < text_section
->vma
+ bfd_get_section_size (text_section
))
12511 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12512 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12513 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12515 /* The branch offset is too large. If this is an
12516 unconditional branch, and we are not generating PIC code,
12517 we can convert it to an absolute jump instruction. */
12518 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12519 insn
= 0x0c000000; /* jal */
12521 insn
= 0x08000000; /* j */
12522 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12524 fixP
->fx_addsy
= section_symbol (text_section
);
12525 *valP
+= md_pcrel_from (fixP
);
12526 md_number_to_chars ((char *) buf
, insn
, 4);
12530 /* If we got here, we have branch-relaxation disabled,
12531 and there's nothing we can do to fix this instruction
12532 without turning it into a longer sequence. */
12533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12534 _("Branch out of range"));
12538 case BFD_RELOC_VTABLE_INHERIT
:
12541 && !S_IS_DEFINED (fixP
->fx_addsy
)
12542 && !S_IS_WEAK (fixP
->fx_addsy
))
12543 S_SET_WEAK (fixP
->fx_addsy
);
12546 case BFD_RELOC_VTABLE_ENTRY
:
12554 /* Remember value for tc_gen_reloc. */
12555 fixP
->fx_addnumber
= *valP
;
12565 name
= input_line_pointer
;
12566 c
= get_symbol_end ();
12567 p
= (symbolS
*) symbol_find_or_make (name
);
12568 *input_line_pointer
= c
;
12572 /* Align the current frag to a given power of two. If a particular
12573 fill byte should be used, FILL points to an integer that contains
12574 that byte, otherwise FILL is null.
12576 The MIPS assembler also automatically adjusts any preceding
12580 mips_align (int to
, int *fill
, symbolS
*label
)
12582 mips_emit_delays ();
12583 mips_record_mips16_mode ();
12584 if (fill
== NULL
&& subseg_text_p (now_seg
))
12585 frag_align_code (to
, 0);
12587 frag_align (to
, fill
? *fill
: 0, 0);
12588 record_alignment (now_seg
, to
);
12591 gas_assert (S_GET_SEGMENT (label
) == now_seg
);
12592 symbol_set_frag (label
, frag_now
);
12593 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12597 /* Align to a given power of two. .align 0 turns off the automatic
12598 alignment used by the data creating pseudo-ops. */
12601 s_align (int x ATTRIBUTE_UNUSED
)
12603 int temp
, fill_value
, *fill_ptr
;
12604 long max_alignment
= 28;
12606 /* o Note that the assembler pulls down any immediately preceding label
12607 to the aligned address.
12608 o It's not documented but auto alignment is reinstated by
12609 a .align pseudo instruction.
12610 o Note also that after auto alignment is turned off the mips assembler
12611 issues an error on attempt to assemble an improperly aligned data item.
12614 temp
= get_absolute_expression ();
12615 if (temp
> max_alignment
)
12616 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12619 as_warn (_("Alignment negative: 0 assumed."));
12622 if (*input_line_pointer
== ',')
12624 ++input_line_pointer
;
12625 fill_value
= get_absolute_expression ();
12626 fill_ptr
= &fill_value
;
12632 segment_info_type
*si
= seg_info (now_seg
);
12633 struct insn_label_list
*l
= si
->label_list
;
12634 /* Auto alignment should be switched on by next section change. */
12636 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12643 demand_empty_rest_of_line ();
12647 s_change_sec (int sec
)
12652 /* The ELF backend needs to know that we are changing sections, so
12653 that .previous works correctly. We could do something like check
12654 for an obj_section_change_hook macro, but that might be confusing
12655 as it would not be appropriate to use it in the section changing
12656 functions in read.c, since obj-elf.c intercepts those. FIXME:
12657 This should be cleaner, somehow. */
12659 obj_elf_section_change_hook ();
12662 mips_emit_delays ();
12673 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12674 demand_empty_rest_of_line ();
12678 seg
= subseg_new (RDATA_SECTION_NAME
,
12679 (subsegT
) get_absolute_expression ());
12682 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12683 | SEC_READONLY
| SEC_RELOC
12685 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12686 record_alignment (seg
, 4);
12688 demand_empty_rest_of_line ();
12692 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12695 bfd_set_section_flags (stdoutput
, seg
,
12696 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12697 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12698 record_alignment (seg
, 4);
12700 demand_empty_rest_of_line ();
12704 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
12707 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
12708 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12709 record_alignment (seg
, 4);
12711 demand_empty_rest_of_line ();
12719 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12722 char *section_name
;
12727 int section_entry_size
;
12728 int section_alignment
;
12733 section_name
= input_line_pointer
;
12734 c
= get_symbol_end ();
12736 next_c
= *(input_line_pointer
+ 1);
12738 /* Do we have .section Name<,"flags">? */
12739 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12741 /* just after name is now '\0'. */
12742 *input_line_pointer
= c
;
12743 input_line_pointer
= section_name
;
12744 obj_elf_section (ignore
);
12747 input_line_pointer
++;
12749 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12751 section_type
= get_absolute_expression ();
12754 if (*input_line_pointer
++ == ',')
12755 section_flag
= get_absolute_expression ();
12758 if (*input_line_pointer
++ == ',')
12759 section_entry_size
= get_absolute_expression ();
12761 section_entry_size
= 0;
12762 if (*input_line_pointer
++ == ',')
12763 section_alignment
= get_absolute_expression ();
12765 section_alignment
= 0;
12766 /* FIXME: really ignore? */
12767 (void) section_alignment
;
12769 section_name
= xstrdup (section_name
);
12771 /* When using the generic form of .section (as implemented by obj-elf.c),
12772 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12773 traditionally had to fall back on the more common @progbits instead.
12775 There's nothing really harmful in this, since bfd will correct
12776 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12777 means that, for backwards compatibility, the special_section entries
12778 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12780 Even so, we shouldn't force users of the MIPS .section syntax to
12781 incorrectly label the sections as SHT_PROGBITS. The best compromise
12782 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12783 generic type-checking code. */
12784 if (section_type
== SHT_MIPS_DWARF
)
12785 section_type
= SHT_PROGBITS
;
12787 obj_elf_change_section (section_name
, section_type
, section_flag
,
12788 section_entry_size
, 0, 0, 0);
12790 if (now_seg
->name
!= section_name
)
12791 free (section_name
);
12792 #endif /* OBJ_ELF */
12796 mips_enable_auto_align (void)
12802 s_cons (int log_size
)
12804 segment_info_type
*si
= seg_info (now_seg
);
12805 struct insn_label_list
*l
= si
->label_list
;
12808 label
= l
!= NULL
? l
->label
: NULL
;
12809 mips_emit_delays ();
12810 if (log_size
> 0 && auto_align
)
12811 mips_align (log_size
, 0, label
);
12812 cons (1 << log_size
);
12813 mips_clear_insn_labels ();
12817 s_float_cons (int type
)
12819 segment_info_type
*si
= seg_info (now_seg
);
12820 struct insn_label_list
*l
= si
->label_list
;
12823 label
= l
!= NULL
? l
->label
: NULL
;
12825 mips_emit_delays ();
12830 mips_align (3, 0, label
);
12832 mips_align (2, 0, label
);
12836 mips_clear_insn_labels ();
12839 /* Handle .globl. We need to override it because on Irix 5 you are
12842 where foo is an undefined symbol, to mean that foo should be
12843 considered to be the address of a function. */
12846 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12855 name
= input_line_pointer
;
12856 c
= get_symbol_end ();
12857 symbolP
= symbol_find_or_make (name
);
12858 S_SET_EXTERNAL (symbolP
);
12860 *input_line_pointer
= c
;
12861 SKIP_WHITESPACE ();
12863 /* On Irix 5, every global symbol that is not explicitly labelled as
12864 being a function is apparently labelled as being an object. */
12867 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12868 && (*input_line_pointer
!= ','))
12873 secname
= input_line_pointer
;
12874 c
= get_symbol_end ();
12875 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12877 as_bad (_("%s: no such section"), secname
);
12878 *input_line_pointer
= c
;
12880 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12881 flag
= BSF_FUNCTION
;
12884 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12886 c
= *input_line_pointer
;
12889 input_line_pointer
++;
12890 SKIP_WHITESPACE ();
12891 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12897 demand_empty_rest_of_line ();
12901 s_option (int x ATTRIBUTE_UNUSED
)
12906 opt
= input_line_pointer
;
12907 c
= get_symbol_end ();
12911 /* FIXME: What does this mean? */
12913 else if (strncmp (opt
, "pic", 3) == 0)
12917 i
= atoi (opt
+ 3);
12922 mips_pic
= SVR4_PIC
;
12923 mips_abicalls
= TRUE
;
12926 as_bad (_(".option pic%d not supported"), i
);
12928 if (mips_pic
== SVR4_PIC
)
12930 if (g_switch_seen
&& g_switch_value
!= 0)
12931 as_warn (_("-G may not be used with SVR4 PIC code"));
12932 g_switch_value
= 0;
12933 bfd_set_gp_size (stdoutput
, 0);
12937 as_warn (_("Unrecognized option \"%s\""), opt
);
12939 *input_line_pointer
= c
;
12940 demand_empty_rest_of_line ();
12943 /* This structure is used to hold a stack of .set values. */
12945 struct mips_option_stack
12947 struct mips_option_stack
*next
;
12948 struct mips_set_options options
;
12951 static struct mips_option_stack
*mips_opts_stack
;
12953 /* Handle the .set pseudo-op. */
12956 s_mipsset (int x ATTRIBUTE_UNUSED
)
12958 char *name
= input_line_pointer
, ch
;
12960 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12961 ++input_line_pointer
;
12962 ch
= *input_line_pointer
;
12963 *input_line_pointer
= '\0';
12965 if (strcmp (name
, "reorder") == 0)
12967 if (mips_opts
.noreorder
)
12970 else if (strcmp (name
, "noreorder") == 0)
12972 if (!mips_opts
.noreorder
)
12973 start_noreorder ();
12975 else if (strncmp (name
, "at=", 3) == 0)
12977 char *s
= name
+ 3;
12979 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
12980 as_bad (_("Unrecognized register name `%s'"), s
);
12982 else if (strcmp (name
, "at") == 0)
12984 mips_opts
.at
= ATREG
;
12986 else if (strcmp (name
, "noat") == 0)
12988 mips_opts
.at
= ZERO
;
12990 else if (strcmp (name
, "macro") == 0)
12992 mips_opts
.warn_about_macros
= 0;
12994 else if (strcmp (name
, "nomacro") == 0)
12996 if (mips_opts
.noreorder
== 0)
12997 as_bad (_("`noreorder' must be set before `nomacro'"));
12998 mips_opts
.warn_about_macros
= 1;
13000 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
13002 mips_opts
.nomove
= 0;
13004 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
13006 mips_opts
.nomove
= 1;
13008 else if (strcmp (name
, "bopt") == 0)
13010 mips_opts
.nobopt
= 0;
13012 else if (strcmp (name
, "nobopt") == 0)
13014 mips_opts
.nobopt
= 1;
13016 else if (strcmp (name
, "gp=default") == 0)
13017 mips_opts
.gp32
= file_mips_gp32
;
13018 else if (strcmp (name
, "gp=32") == 0)
13019 mips_opts
.gp32
= 1;
13020 else if (strcmp (name
, "gp=64") == 0)
13022 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13023 as_warn (_("%s isa does not support 64-bit registers"),
13024 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13025 mips_opts
.gp32
= 0;
13027 else if (strcmp (name
, "fp=default") == 0)
13028 mips_opts
.fp32
= file_mips_fp32
;
13029 else if (strcmp (name
, "fp=32") == 0)
13030 mips_opts
.fp32
= 1;
13031 else if (strcmp (name
, "fp=64") == 0)
13033 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13034 as_warn (_("%s isa does not support 64-bit floating point registers"),
13035 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13036 mips_opts
.fp32
= 0;
13038 else if (strcmp (name
, "softfloat") == 0)
13039 mips_opts
.soft_float
= 1;
13040 else if (strcmp (name
, "hardfloat") == 0)
13041 mips_opts
.soft_float
= 0;
13042 else if (strcmp (name
, "singlefloat") == 0)
13043 mips_opts
.single_float
= 1;
13044 else if (strcmp (name
, "doublefloat") == 0)
13045 mips_opts
.single_float
= 0;
13046 else if (strcmp (name
, "mips16") == 0
13047 || strcmp (name
, "MIPS-16") == 0)
13048 mips_opts
.mips16
= 1;
13049 else if (strcmp (name
, "nomips16") == 0
13050 || strcmp (name
, "noMIPS-16") == 0)
13051 mips_opts
.mips16
= 0;
13052 else if (strcmp (name
, "smartmips") == 0)
13054 if (!ISA_SUPPORTS_SMARTMIPS
)
13055 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13056 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13057 mips_opts
.ase_smartmips
= 1;
13059 else if (strcmp (name
, "nosmartmips") == 0)
13060 mips_opts
.ase_smartmips
= 0;
13061 else if (strcmp (name
, "mips3d") == 0)
13062 mips_opts
.ase_mips3d
= 1;
13063 else if (strcmp (name
, "nomips3d") == 0)
13064 mips_opts
.ase_mips3d
= 0;
13065 else if (strcmp (name
, "mdmx") == 0)
13066 mips_opts
.ase_mdmx
= 1;
13067 else if (strcmp (name
, "nomdmx") == 0)
13068 mips_opts
.ase_mdmx
= 0;
13069 else if (strcmp (name
, "dsp") == 0)
13071 if (!ISA_SUPPORTS_DSP_ASE
)
13072 as_warn (_("%s ISA does not support DSP ASE"),
13073 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13074 mips_opts
.ase_dsp
= 1;
13075 mips_opts
.ase_dspr2
= 0;
13077 else if (strcmp (name
, "nodsp") == 0)
13079 mips_opts
.ase_dsp
= 0;
13080 mips_opts
.ase_dspr2
= 0;
13082 else if (strcmp (name
, "dspr2") == 0)
13084 if (!ISA_SUPPORTS_DSPR2_ASE
)
13085 as_warn (_("%s ISA does not support DSP R2 ASE"),
13086 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13087 mips_opts
.ase_dspr2
= 1;
13088 mips_opts
.ase_dsp
= 1;
13090 else if (strcmp (name
, "nodspr2") == 0)
13092 mips_opts
.ase_dspr2
= 0;
13093 mips_opts
.ase_dsp
= 0;
13095 else if (strcmp (name
, "mt") == 0)
13097 if (!ISA_SUPPORTS_MT_ASE
)
13098 as_warn (_("%s ISA does not support MT ASE"),
13099 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13100 mips_opts
.ase_mt
= 1;
13102 else if (strcmp (name
, "nomt") == 0)
13103 mips_opts
.ase_mt
= 0;
13104 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
13108 /* Permit the user to change the ISA and architecture on the fly.
13109 Needless to say, misuse can cause serious problems. */
13110 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
13113 mips_opts
.isa
= file_mips_isa
;
13114 mips_opts
.arch
= file_mips_arch
;
13116 else if (strncmp (name
, "arch=", 5) == 0)
13118 const struct mips_cpu_info
*p
;
13120 p
= mips_parse_cpu("internal use", name
+ 5);
13122 as_bad (_("unknown architecture %s"), name
+ 5);
13125 mips_opts
.arch
= p
->cpu
;
13126 mips_opts
.isa
= p
->isa
;
13129 else if (strncmp (name
, "mips", 4) == 0)
13131 const struct mips_cpu_info
*p
;
13133 p
= mips_parse_cpu("internal use", name
);
13135 as_bad (_("unknown ISA level %s"), name
+ 4);
13138 mips_opts
.arch
= p
->cpu
;
13139 mips_opts
.isa
= p
->isa
;
13143 as_bad (_("unknown ISA or architecture %s"), name
);
13145 switch (mips_opts
.isa
)
13153 mips_opts
.gp32
= 1;
13154 mips_opts
.fp32
= 1;
13161 mips_opts
.gp32
= 0;
13162 mips_opts
.fp32
= 0;
13165 as_bad (_("unknown ISA level %s"), name
+ 4);
13170 mips_opts
.gp32
= file_mips_gp32
;
13171 mips_opts
.fp32
= file_mips_fp32
;
13174 else if (strcmp (name
, "autoextend") == 0)
13175 mips_opts
.noautoextend
= 0;
13176 else if (strcmp (name
, "noautoextend") == 0)
13177 mips_opts
.noautoextend
= 1;
13178 else if (strcmp (name
, "push") == 0)
13180 struct mips_option_stack
*s
;
13182 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
13183 s
->next
= mips_opts_stack
;
13184 s
->options
= mips_opts
;
13185 mips_opts_stack
= s
;
13187 else if (strcmp (name
, "pop") == 0)
13189 struct mips_option_stack
*s
;
13191 s
= mips_opts_stack
;
13193 as_bad (_(".set pop with no .set push"));
13196 /* If we're changing the reorder mode we need to handle
13197 delay slots correctly. */
13198 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
13199 start_noreorder ();
13200 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
13203 mips_opts
= s
->options
;
13204 mips_opts_stack
= s
->next
;
13208 else if (strcmp (name
, "sym32") == 0)
13209 mips_opts
.sym32
= TRUE
;
13210 else if (strcmp (name
, "nosym32") == 0)
13211 mips_opts
.sym32
= FALSE
;
13212 else if (strchr (name
, ','))
13214 /* Generic ".set" directive; use the generic handler. */
13215 *input_line_pointer
= ch
;
13216 input_line_pointer
= name
;
13222 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
13224 *input_line_pointer
= ch
;
13225 demand_empty_rest_of_line ();
13228 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13229 .option pic2. It means to generate SVR4 PIC calls. */
13232 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
13234 mips_pic
= SVR4_PIC
;
13235 mips_abicalls
= TRUE
;
13237 if (g_switch_seen
&& g_switch_value
!= 0)
13238 as_warn (_("-G may not be used with SVR4 PIC code"));
13239 g_switch_value
= 0;
13241 bfd_set_gp_size (stdoutput
, 0);
13242 demand_empty_rest_of_line ();
13245 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13246 PIC code. It sets the $gp register for the function based on the
13247 function address, which is in the register named in the argument.
13248 This uses a relocation against _gp_disp, which is handled specially
13249 by the linker. The result is:
13250 lui $gp,%hi(_gp_disp)
13251 addiu $gp,$gp,%lo(_gp_disp)
13252 addu $gp,$gp,.cpload argument
13253 The .cpload argument is normally $25 == $t9.
13255 The -mno-shared option changes this to:
13256 lui $gp,%hi(__gnu_local_gp)
13257 addiu $gp,$gp,%lo(__gnu_local_gp)
13258 and the argument is ignored. This saves an instruction, but the
13259 resulting code is not position independent; it uses an absolute
13260 address for __gnu_local_gp. Thus code assembled with -mno-shared
13261 can go into an ordinary executable, but not into a shared library. */
13264 s_cpload (int ignore ATTRIBUTE_UNUSED
)
13270 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13271 .cpload is ignored. */
13272 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13278 /* .cpload should be in a .set noreorder section. */
13279 if (mips_opts
.noreorder
== 0)
13280 as_warn (_(".cpload not in noreorder section"));
13282 reg
= tc_get_register (0);
13284 /* If we need to produce a 64-bit address, we are better off using
13285 the default instruction sequence. */
13286 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
13288 ex
.X_op
= O_symbol
;
13289 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
13291 ex
.X_op_symbol
= NULL
;
13292 ex
.X_add_number
= 0;
13294 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13295 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13298 macro_build_lui (&ex
, mips_gp_register
);
13299 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13300 mips_gp_register
, BFD_RELOC_LO16
);
13302 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
13303 mips_gp_register
, reg
);
13306 demand_empty_rest_of_line ();
13309 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13310 .cpsetup $reg1, offset|$reg2, label
13312 If offset is given, this results in:
13313 sd $gp, offset($sp)
13314 lui $gp, %hi(%neg(%gp_rel(label)))
13315 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13316 daddu $gp, $gp, $reg1
13318 If $reg2 is given, this results in:
13319 daddu $reg2, $gp, $0
13320 lui $gp, %hi(%neg(%gp_rel(label)))
13321 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13322 daddu $gp, $gp, $reg1
13323 $reg1 is normally $25 == $t9.
13325 The -mno-shared option replaces the last three instructions with
13327 addiu $gp,$gp,%lo(_gp) */
13330 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
13332 expressionS ex_off
;
13333 expressionS ex_sym
;
13336 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13337 We also need NewABI support. */
13338 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13344 reg1
= tc_get_register (0);
13345 SKIP_WHITESPACE ();
13346 if (*input_line_pointer
!= ',')
13348 as_bad (_("missing argument separator ',' for .cpsetup"));
13352 ++input_line_pointer
;
13353 SKIP_WHITESPACE ();
13354 if (*input_line_pointer
== '$')
13356 mips_cpreturn_register
= tc_get_register (0);
13357 mips_cpreturn_offset
= -1;
13361 mips_cpreturn_offset
= get_absolute_expression ();
13362 mips_cpreturn_register
= -1;
13364 SKIP_WHITESPACE ();
13365 if (*input_line_pointer
!= ',')
13367 as_bad (_("missing argument separator ',' for .cpsetup"));
13371 ++input_line_pointer
;
13372 SKIP_WHITESPACE ();
13373 expression (&ex_sym
);
13376 if (mips_cpreturn_register
== -1)
13378 ex_off
.X_op
= O_constant
;
13379 ex_off
.X_add_symbol
= NULL
;
13380 ex_off
.X_op_symbol
= NULL
;
13381 ex_off
.X_add_number
= mips_cpreturn_offset
;
13383 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13384 BFD_RELOC_LO16
, SP
);
13387 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13388 mips_gp_register
, 0);
13390 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13392 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13393 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13396 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13397 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13398 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13400 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13401 mips_gp_register
, reg1
);
13407 ex
.X_op
= O_symbol
;
13408 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13409 ex
.X_op_symbol
= NULL
;
13410 ex
.X_add_number
= 0;
13412 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13413 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13415 macro_build_lui (&ex
, mips_gp_register
);
13416 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13417 mips_gp_register
, BFD_RELOC_LO16
);
13422 demand_empty_rest_of_line ();
13426 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13428 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13429 .cplocal is ignored. */
13430 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13436 mips_gp_register
= tc_get_register (0);
13437 demand_empty_rest_of_line ();
13440 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13441 offset from $sp. The offset is remembered, and after making a PIC
13442 call $gp is restored from that location. */
13445 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13449 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13450 .cprestore is ignored. */
13451 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13457 mips_cprestore_offset
= get_absolute_expression ();
13458 mips_cprestore_valid
= 1;
13460 ex
.X_op
= O_constant
;
13461 ex
.X_add_symbol
= NULL
;
13462 ex
.X_op_symbol
= NULL
;
13463 ex
.X_add_number
= mips_cprestore_offset
;
13466 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13467 SP
, HAVE_64BIT_ADDRESSES
);
13470 demand_empty_rest_of_line ();
13473 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13474 was given in the preceding .cpsetup, it results in:
13475 ld $gp, offset($sp)
13477 If a register $reg2 was given there, it results in:
13478 daddu $gp, $reg2, $0 */
13481 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13485 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13486 We also need NewABI support. */
13487 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13494 if (mips_cpreturn_register
== -1)
13496 ex
.X_op
= O_constant
;
13497 ex
.X_add_symbol
= NULL
;
13498 ex
.X_op_symbol
= NULL
;
13499 ex
.X_add_number
= mips_cpreturn_offset
;
13501 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13504 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13505 mips_cpreturn_register
, 0);
13508 demand_empty_rest_of_line ();
13511 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13512 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13513 use in DWARF debug information. */
13516 s_dtprel_internal (size_t bytes
)
13523 if (ex
.X_op
!= O_symbol
)
13525 as_bad (_("Unsupported use of %s"), (bytes
== 8
13528 ignore_rest_of_line ();
13531 p
= frag_more (bytes
);
13532 md_number_to_chars (p
, 0, bytes
);
13533 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13535 ? BFD_RELOC_MIPS_TLS_DTPREL64
13536 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13538 demand_empty_rest_of_line ();
13541 /* Handle .dtprelword. */
13544 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13546 s_dtprel_internal (4);
13549 /* Handle .dtpreldword. */
13552 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13554 s_dtprel_internal (8);
13557 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13558 code. It sets the offset to use in gp_rel relocations. */
13561 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13563 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13564 We also need NewABI support. */
13565 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13571 mips_gprel_offset
= get_absolute_expression ();
13573 demand_empty_rest_of_line ();
13576 /* Handle the .gpword pseudo-op. This is used when generating PIC
13577 code. It generates a 32 bit GP relative reloc. */
13580 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13582 segment_info_type
*si
;
13583 struct insn_label_list
*l
;
13588 /* When not generating PIC code, this is treated as .word. */
13589 if (mips_pic
!= SVR4_PIC
)
13595 si
= seg_info (now_seg
);
13596 l
= si
->label_list
;
13597 label
= l
!= NULL
? l
->label
: NULL
;
13598 mips_emit_delays ();
13600 mips_align (2, 0, label
);
13603 mips_clear_insn_labels ();
13605 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13607 as_bad (_("Unsupported use of .gpword"));
13608 ignore_rest_of_line ();
13612 md_number_to_chars (p
, 0, 4);
13613 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13614 BFD_RELOC_GPREL32
);
13616 demand_empty_rest_of_line ();
13620 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13622 segment_info_type
*si
;
13623 struct insn_label_list
*l
;
13628 /* When not generating PIC code, this is treated as .dword. */
13629 if (mips_pic
!= SVR4_PIC
)
13635 si
= seg_info (now_seg
);
13636 l
= si
->label_list
;
13637 label
= l
!= NULL
? l
->label
: NULL
;
13638 mips_emit_delays ();
13640 mips_align (3, 0, label
);
13643 mips_clear_insn_labels ();
13645 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13647 as_bad (_("Unsupported use of .gpdword"));
13648 ignore_rest_of_line ();
13652 md_number_to_chars (p
, 0, 8);
13653 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13654 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13656 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13657 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13658 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13660 demand_empty_rest_of_line ();
13663 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13664 tables in SVR4 PIC code. */
13667 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13671 /* This is ignored when not generating SVR4 PIC code. */
13672 if (mips_pic
!= SVR4_PIC
)
13678 /* Add $gp to the register named as an argument. */
13680 reg
= tc_get_register (0);
13681 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13684 demand_empty_rest_of_line ();
13687 /* Handle the .insn pseudo-op. This marks instruction labels in
13688 mips16 mode. This permits the linker to handle them specially,
13689 such as generating jalx instructions when needed. We also make
13690 them odd for the duration of the assembly, in order to generate the
13691 right sort of code. We will make them even in the adjust_symtab
13692 routine, while leaving them marked. This is convenient for the
13693 debugger and the disassembler. The linker knows to make them odd
13697 s_insn (int ignore ATTRIBUTE_UNUSED
)
13699 mips16_mark_labels ();
13701 demand_empty_rest_of_line ();
13704 /* Handle a .stabn directive. We need these in order to mark a label
13705 as being a mips16 text label correctly. Sometimes the compiler
13706 will emit a label, followed by a .stabn, and then switch sections.
13707 If the label and .stabn are in mips16 mode, then the label is
13708 really a mips16 text label. */
13711 s_mips_stab (int type
)
13714 mips16_mark_labels ();
13719 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13722 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13729 name
= input_line_pointer
;
13730 c
= get_symbol_end ();
13731 symbolP
= symbol_find_or_make (name
);
13732 S_SET_WEAK (symbolP
);
13733 *input_line_pointer
= c
;
13735 SKIP_WHITESPACE ();
13737 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13739 if (S_IS_DEFINED (symbolP
))
13741 as_bad (_("ignoring attempt to redefine symbol %s"),
13742 S_GET_NAME (symbolP
));
13743 ignore_rest_of_line ();
13747 if (*input_line_pointer
== ',')
13749 ++input_line_pointer
;
13750 SKIP_WHITESPACE ();
13754 if (exp
.X_op
!= O_symbol
)
13756 as_bad (_("bad .weakext directive"));
13757 ignore_rest_of_line ();
13760 symbol_set_value_expression (symbolP
, &exp
);
13763 demand_empty_rest_of_line ();
13766 /* Parse a register string into a number. Called from the ECOFF code
13767 to parse .frame. The argument is non-zero if this is the frame
13768 register, so that we can record it in mips_frame_reg. */
13771 tc_get_register (int frame
)
13775 SKIP_WHITESPACE ();
13776 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13780 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13781 mips_frame_reg_valid
= 1;
13782 mips_cprestore_valid
= 0;
13788 md_section_align (asection
*seg
, valueT addr
)
13790 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13794 /* We don't need to align ELF sections to the full alignment.
13795 However, Irix 5 may prefer that we align them at least to a 16
13796 byte boundary. We don't bother to align the sections if we
13797 are targeted for an embedded system. */
13798 if (strncmp (TARGET_OS
, "elf", 3) == 0)
13804 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13807 /* Utility routine, called from above as well. If called while the
13808 input file is still being read, it's only an approximation. (For
13809 example, a symbol may later become defined which appeared to be
13810 undefined earlier.) */
13813 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13818 if (g_switch_value
> 0)
13820 const char *symname
;
13823 /* Find out whether this symbol can be referenced off the $gp
13824 register. It can be if it is smaller than the -G size or if
13825 it is in the .sdata or .sbss section. Certain symbols can
13826 not be referenced off the $gp, although it appears as though
13828 symname
= S_GET_NAME (sym
);
13829 if (symname
!= (const char *) NULL
13830 && (strcmp (symname
, "eprol") == 0
13831 || strcmp (symname
, "etext") == 0
13832 || strcmp (symname
, "_gp") == 0
13833 || strcmp (symname
, "edata") == 0
13834 || strcmp (symname
, "_fbss") == 0
13835 || strcmp (symname
, "_fdata") == 0
13836 || strcmp (symname
, "_ftext") == 0
13837 || strcmp (symname
, "end") == 0
13838 || strcmp (symname
, "_gp_disp") == 0))
13840 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13842 #ifndef NO_ECOFF_DEBUGGING
13843 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13844 && (symbol_get_obj (sym
)->ecoff_extern_size
13845 <= g_switch_value
))
13847 /* We must defer this decision until after the whole
13848 file has been read, since there might be a .extern
13849 after the first use of this symbol. */
13850 || (before_relaxing
13851 #ifndef NO_ECOFF_DEBUGGING
13852 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13854 && S_GET_VALUE (sym
) == 0)
13855 || (S_GET_VALUE (sym
) != 0
13856 && S_GET_VALUE (sym
) <= g_switch_value
)))
13860 const char *segname
;
13862 segname
= segment_name (S_GET_SEGMENT (sym
));
13863 gas_assert (strcmp (segname
, ".lit8") != 0
13864 && strcmp (segname
, ".lit4") != 0);
13865 change
= (strcmp (segname
, ".sdata") != 0
13866 && strcmp (segname
, ".sbss") != 0
13867 && strncmp (segname
, ".sdata.", 7) != 0
13868 && strncmp (segname
, ".sbss.", 6) != 0
13869 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13870 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13875 /* We are not optimizing for the $gp register. */
13880 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13883 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13887 /* Handle the case of a symbol equated to another symbol. */
13888 while (symbol_equated_reloc_p (sym
))
13892 /* It's possible to get a loop here in a badly written program. */
13893 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13899 if (symbol_section_p (sym
))
13902 symsec
= S_GET_SEGMENT (sym
);
13904 /* This must duplicate the test in adjust_reloc_syms. */
13905 return (symsec
!= &bfd_und_section
13906 && symsec
!= &bfd_abs_section
13907 && !bfd_is_com_section (symsec
)
13908 && !s_is_linkonce (sym
, segtype
)
13910 /* A global or weak symbol is treated as external. */
13911 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13917 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13918 extended opcode. SEC is the section the frag is in. */
13921 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13924 const struct mips16_immed_operand
*op
;
13926 int mintiny
, maxtiny
;
13930 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13932 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13935 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13936 op
= mips16_immed_operands
;
13937 while (op
->type
!= type
)
13940 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13945 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13948 maxtiny
= 1 << op
->nbits
;
13953 maxtiny
= (1 << op
->nbits
) - 1;
13958 mintiny
= - (1 << (op
->nbits
- 1));
13959 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13962 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13963 val
= S_GET_VALUE (fragp
->fr_symbol
);
13964 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13970 /* We won't have the section when we are called from
13971 mips_relax_frag. However, we will always have been called
13972 from md_estimate_size_before_relax first. If this is a
13973 branch to a different section, we mark it as such. If SEC is
13974 NULL, and the frag is not marked, then it must be a branch to
13975 the same section. */
13978 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13983 /* Must have been called from md_estimate_size_before_relax. */
13986 fragp
->fr_subtype
=
13987 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13989 /* FIXME: We should support this, and let the linker
13990 catch branches and loads that are out of range. */
13991 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13992 _("unsupported PC relative reference to different section"));
13996 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13997 /* Assume non-extended on the first relaxation pass.
13998 The address we have calculated will be bogus if this is
13999 a forward branch to another frag, as the forward frag
14000 will have fr_address == 0. */
14004 /* In this case, we know for sure that the symbol fragment is in
14005 the same section. If the relax_marker of the symbol fragment
14006 differs from the relax_marker of this fragment, we have not
14007 yet adjusted the symbol fragment fr_address. We want to add
14008 in STRETCH in order to get a better estimate of the address.
14009 This particularly matters because of the shift bits. */
14011 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
14015 /* Adjust stretch for any alignment frag. Note that if have
14016 been expanding the earlier code, the symbol may be
14017 defined in what appears to be an earlier frag. FIXME:
14018 This doesn't handle the fr_subtype field, which specifies
14019 a maximum number of bytes to skip when doing an
14021 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
14023 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
14026 stretch
= - ((- stretch
)
14027 & ~ ((1 << (int) f
->fr_offset
) - 1));
14029 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
14038 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14040 /* The base address rules are complicated. The base address of
14041 a branch is the following instruction. The base address of a
14042 PC relative load or add is the instruction itself, but if it
14043 is in a delay slot (in which case it can not be extended) use
14044 the address of the instruction whose delay slot it is in. */
14045 if (type
== 'p' || type
== 'q')
14049 /* If we are currently assuming that this frag should be
14050 extended, then, the current address is two bytes
14052 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14055 /* Ignore the low bit in the target, since it will be set
14056 for a text label. */
14057 if ((val
& 1) != 0)
14060 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14062 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14065 val
-= addr
& ~ ((1 << op
->shift
) - 1);
14067 /* Branch offsets have an implicit 0 in the lowest bit. */
14068 if (type
== 'p' || type
== 'q')
14071 /* If any of the shifted bits are set, we must use an extended
14072 opcode. If the address depends on the size of this
14073 instruction, this can lead to a loop, so we arrange to always
14074 use an extended opcode. We only check this when we are in
14075 the main relaxation loop, when SEC is NULL. */
14076 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
14078 fragp
->fr_subtype
=
14079 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14083 /* If we are about to mark a frag as extended because the value
14084 is precisely maxtiny + 1, then there is a chance of an
14085 infinite loop as in the following code:
14090 In this case when the la is extended, foo is 0x3fc bytes
14091 away, so the la can be shrunk, but then foo is 0x400 away, so
14092 the la must be extended. To avoid this loop, we mark the
14093 frag as extended if it was small, and is about to become
14094 extended with a value of maxtiny + 1. */
14095 if (val
== ((maxtiny
+ 1) << op
->shift
)
14096 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
14099 fragp
->fr_subtype
=
14100 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14104 else if (symsec
!= absolute_section
&& sec
!= NULL
)
14105 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
14107 if ((val
& ((1 << op
->shift
) - 1)) != 0
14108 || val
< (mintiny
<< op
->shift
)
14109 || val
> (maxtiny
<< op
->shift
))
14115 /* Compute the length of a branch sequence, and adjust the
14116 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14117 worst-case length is computed, with UPDATE being used to indicate
14118 whether an unconditional (-1), branch-likely (+1) or regular (0)
14119 branch is to be computed. */
14121 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
14123 bfd_boolean toofar
;
14127 && S_IS_DEFINED (fragp
->fr_symbol
)
14128 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
14133 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
14135 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
14139 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
14142 /* If the symbol is not defined or it's in a different segment,
14143 assume the user knows what's going on and emit a short
14149 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14151 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
14152 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
14153 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
14154 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
14160 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
14163 if (mips_pic
!= NO_PIC
)
14165 /* Additional space for PIC loading of target address. */
14167 if (mips_opts
.isa
== ISA_MIPS1
)
14168 /* Additional space for $at-stabilizing nop. */
14172 /* If branch is conditional. */
14173 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
14180 /* Estimate the size of a frag before relaxing. Unless this is the
14181 mips16, we are not really relaxing here, and the final size is
14182 encoded in the subtype information. For the mips16, we have to
14183 decide whether we are using an extended opcode or not. */
14186 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
14190 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14193 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
14195 return fragp
->fr_var
;
14198 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14199 /* We don't want to modify the EXTENDED bit here; it might get us
14200 into infinite loops. We change it only in mips_relax_frag(). */
14201 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
14203 if (mips_pic
== NO_PIC
)
14204 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
14205 else if (mips_pic
== SVR4_PIC
)
14206 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
14207 else if (mips_pic
== VXWORKS_PIC
)
14208 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14215 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
14216 return -RELAX_FIRST (fragp
->fr_subtype
);
14219 return -RELAX_SECOND (fragp
->fr_subtype
);
14222 /* This is called to see whether a reloc against a defined symbol
14223 should be converted into a reloc against a section. */
14226 mips_fix_adjustable (fixS
*fixp
)
14228 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14229 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14232 if (fixp
->fx_addsy
== NULL
)
14235 /* If symbol SYM is in a mergeable section, relocations of the form
14236 SYM + 0 can usually be made section-relative. The mergeable data
14237 is then identified by the section offset rather than by the symbol.
14239 However, if we're generating REL LO16 relocations, the offset is split
14240 between the LO16 and parterning high part relocation. The linker will
14241 need to recalculate the complete offset in order to correctly identify
14244 The linker has traditionally not looked for the parterning high part
14245 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14246 placed anywhere. Rather than break backwards compatibility by changing
14247 this, it seems better not to force the issue, and instead keep the
14248 original symbol. This will work with either linker behavior. */
14249 if ((lo16_reloc_p (fixp
->fx_r_type
)
14250 || reloc_needs_lo_p (fixp
->fx_r_type
))
14251 && HAVE_IN_PLACE_ADDENDS
14252 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
14255 /* There is no place to store an in-place offset for JALR relocations.
14256 Likewise an in-range offset of PC-relative relocations may overflow
14257 the in-place relocatable field if recalculated against the start
14258 address of the symbol's containing section. */
14259 if (HAVE_IN_PLACE_ADDENDS
14260 && (fixp
->fx_pcrel
|| fixp
->fx_r_type
== BFD_RELOC_MIPS_JALR
))
14264 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14265 to a floating-point stub. The same is true for non-R_MIPS16_26
14266 relocations against MIPS16 functions; in this case, the stub becomes
14267 the function's canonical address.
14269 Floating-point stubs are stored in unique .mips16.call.* or
14270 .mips16.fn.* sections. If a stub T for function F is in section S,
14271 the first relocation in section S must be against F; this is how the
14272 linker determines the target function. All relocations that might
14273 resolve to T must also be against F. We therefore have the following
14274 restrictions, which are given in an intentionally-redundant way:
14276 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14279 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14280 if that stub might be used.
14282 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14285 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14286 that stub might be used.
14288 There is a further restriction:
14290 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14291 on targets with in-place addends; the relocation field cannot
14292 encode the low bit.
14294 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14295 against a MIPS16 symbol.
14297 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14298 relocation against some symbol R, no relocation against R may be
14299 reduced. (Note that this deals with (2) as well as (1) because
14300 relocations against global symbols will never be reduced on ELF
14301 targets.) This approach is a little simpler than trying to detect
14302 stub sections, and gives the "all or nothing" per-symbol consistency
14303 that we have for MIPS16 symbols. */
14305 && fixp
->fx_subsy
== NULL
14306 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
14307 || *symbol_get_tc (fixp
->fx_addsy
)))
14314 /* Translate internal representation of relocation info to BFD target
14318 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14320 static arelent
*retval
[4];
14322 bfd_reloc_code_real_type code
;
14324 memset (retval
, 0, sizeof(retval
));
14325 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
14326 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
14327 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14328 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14330 if (fixp
->fx_pcrel
)
14332 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
14334 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14335 Relocations want only the symbol offset. */
14336 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
14339 /* A gruesome hack which is a result of the gruesome gas
14340 reloc handling. What's worse, for COFF (as opposed to
14341 ECOFF), we might need yet another copy of reloc->address.
14342 See bfd_install_relocation. */
14343 reloc
->addend
+= reloc
->address
;
14347 reloc
->addend
= fixp
->fx_addnumber
;
14349 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14350 entry to be used in the relocation's section offset. */
14351 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14353 reloc
->address
= reloc
->addend
;
14357 code
= fixp
->fx_r_type
;
14359 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14360 if (reloc
->howto
== NULL
)
14362 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14363 _("Can not represent %s relocation in this object file format"),
14364 bfd_get_reloc_code_name (code
));
14371 /* Relax a machine dependent frag. This returns the amount by which
14372 the current size of the frag should change. */
14375 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14377 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14379 offsetT old_var
= fragp
->fr_var
;
14381 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14383 return fragp
->fr_var
- old_var
;
14386 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14389 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14391 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14393 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14398 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14400 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14407 /* Convert a machine dependent frag. */
14410 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14412 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14415 unsigned long insn
;
14419 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14421 if (target_big_endian
)
14422 insn
= bfd_getb32 (buf
);
14424 insn
= bfd_getl32 (buf
);
14426 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14428 /* We generate a fixup instead of applying it right now
14429 because, if there are linker relaxations, we're going to
14430 need the relocations. */
14431 exp
.X_op
= O_symbol
;
14432 exp
.X_add_symbol
= fragp
->fr_symbol
;
14433 exp
.X_add_number
= fragp
->fr_offset
;
14435 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14436 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14437 fixp
->fx_file
= fragp
->fr_file
;
14438 fixp
->fx_line
= fragp
->fr_line
;
14440 md_number_to_chars ((char *) buf
, insn
, 4);
14447 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14448 _("Relaxed out-of-range branch into a jump"));
14450 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14453 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14455 /* Reverse the branch. */
14456 switch ((insn
>> 28) & 0xf)
14459 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14460 have the condition reversed by tweaking a single
14461 bit, and their opcodes all have 0x4???????. */
14462 gas_assert ((insn
& 0xf1000000) == 0x41000000);
14463 insn
^= 0x00010000;
14467 /* bltz 0x04000000 bgez 0x04010000
14468 bltzal 0x04100000 bgezal 0x04110000 */
14469 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
14470 insn
^= 0x00010000;
14474 /* beq 0x10000000 bne 0x14000000
14475 blez 0x18000000 bgtz 0x1c000000 */
14476 insn
^= 0x04000000;
14484 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14486 /* Clear the and-link bit. */
14487 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
14489 /* bltzal 0x04100000 bgezal 0x04110000
14490 bltzall 0x04120000 bgezall 0x04130000 */
14491 insn
&= ~0x00100000;
14494 /* Branch over the branch (if the branch was likely) or the
14495 full jump (not likely case). Compute the offset from the
14496 current instruction to branch to. */
14497 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14501 /* How many bytes in instructions we've already emitted? */
14502 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14503 /* How many bytes in instructions from here to the end? */
14504 i
= fragp
->fr_var
- i
;
14506 /* Convert to instruction count. */
14508 /* Branch counts from the next instruction. */
14511 /* Branch over the jump. */
14512 md_number_to_chars ((char *) buf
, insn
, 4);
14516 md_number_to_chars ((char *) buf
, 0, 4);
14519 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14521 /* beql $0, $0, 2f */
14523 /* Compute the PC offset from the current instruction to
14524 the end of the variable frag. */
14525 /* How many bytes in instructions we've already emitted? */
14526 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14527 /* How many bytes in instructions from here to the end? */
14528 i
= fragp
->fr_var
- i
;
14529 /* Convert to instruction count. */
14531 /* Don't decrement i, because we want to branch over the
14535 md_number_to_chars ((char *) buf
, insn
, 4);
14538 md_number_to_chars ((char *) buf
, 0, 4);
14543 if (mips_pic
== NO_PIC
)
14546 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14547 ? 0x0c000000 : 0x08000000);
14548 exp
.X_op
= O_symbol
;
14549 exp
.X_add_symbol
= fragp
->fr_symbol
;
14550 exp
.X_add_number
= fragp
->fr_offset
;
14552 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14553 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14554 fixp
->fx_file
= fragp
->fr_file
;
14555 fixp
->fx_line
= fragp
->fr_line
;
14557 md_number_to_chars ((char *) buf
, insn
, 4);
14562 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
14564 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14565 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
14566 insn
|= at
<< OP_SH_RT
;
14567 exp
.X_op
= O_symbol
;
14568 exp
.X_add_symbol
= fragp
->fr_symbol
;
14569 exp
.X_add_number
= fragp
->fr_offset
;
14571 if (fragp
->fr_offset
)
14573 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14574 exp
.X_add_number
= 0;
14577 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14578 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14579 fixp
->fx_file
= fragp
->fr_file
;
14580 fixp
->fx_line
= fragp
->fr_line
;
14582 md_number_to_chars ((char *) buf
, insn
, 4);
14585 if (mips_opts
.isa
== ISA_MIPS1
)
14588 md_number_to_chars ((char *) buf
, 0, 4);
14592 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14593 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
14594 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
14596 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14597 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14598 fixp
->fx_file
= fragp
->fr_file
;
14599 fixp
->fx_line
= fragp
->fr_line
;
14601 md_number_to_chars ((char *) buf
, insn
, 4);
14605 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14609 insn
|= at
<< OP_SH_RS
;
14611 md_number_to_chars ((char *) buf
, insn
, 4);
14616 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
14617 + fragp
->fr_fix
+ fragp
->fr_var
);
14619 fragp
->fr_fix
+= fragp
->fr_var
;
14624 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14627 const struct mips16_immed_operand
*op
;
14628 bfd_boolean small
, ext
;
14631 unsigned long insn
;
14632 bfd_boolean use_extend
;
14633 unsigned short extend
;
14635 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14636 op
= mips16_immed_operands
;
14637 while (op
->type
!= type
)
14640 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14651 val
= resolve_symbol_value (fragp
->fr_symbol
);
14656 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14658 /* The rules for the base address of a PC relative reloc are
14659 complicated; see mips16_extended_frag. */
14660 if (type
== 'p' || type
== 'q')
14665 /* Ignore the low bit in the target, since it will be
14666 set for a text label. */
14667 if ((val
& 1) != 0)
14670 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14672 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14675 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14678 /* Make sure the section winds up with the alignment we have
14681 record_alignment (asec
, op
->shift
);
14685 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14686 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14687 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14688 _("extended instruction in delay slot"));
14690 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14692 if (target_big_endian
)
14693 insn
= bfd_getb16 (buf
);
14695 insn
= bfd_getl16 (buf
);
14697 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14698 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14699 small
, ext
, &insn
, &use_extend
, &extend
);
14703 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14704 fragp
->fr_fix
+= 2;
14708 md_number_to_chars ((char *) buf
, insn
, 2);
14709 fragp
->fr_fix
+= 2;
14717 first
= RELAX_FIRST (fragp
->fr_subtype
);
14718 second
= RELAX_SECOND (fragp
->fr_subtype
);
14719 fixp
= (fixS
*) fragp
->fr_opcode
;
14721 /* Possibly emit a warning if we've chosen the longer option. */
14722 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14723 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14725 const char *msg
= macro_warning (fragp
->fr_subtype
);
14727 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
14730 /* Go through all the fixups for the first sequence. Disable them
14731 (by marking them as done) if we're going to use the second
14732 sequence instead. */
14734 && fixp
->fx_frag
== fragp
14735 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14737 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14739 fixp
= fixp
->fx_next
;
14742 /* Go through the fixups for the second sequence. Disable them if
14743 we're going to use the first sequence, otherwise adjust their
14744 addresses to account for the relaxation. */
14745 while (fixp
&& fixp
->fx_frag
== fragp
)
14747 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14748 fixp
->fx_where
-= first
;
14751 fixp
= fixp
->fx_next
;
14754 /* Now modify the frag contents. */
14755 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14759 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14760 memmove (start
, start
+ first
, second
);
14761 fragp
->fr_fix
-= first
;
14764 fragp
->fr_fix
-= second
;
14770 /* This function is called after the relocs have been generated.
14771 We've been storing mips16 text labels as odd. Here we convert them
14772 back to even for the convenience of the debugger. */
14775 mips_frob_file_after_relocs (void)
14778 unsigned int count
, i
;
14783 syms
= bfd_get_outsymbols (stdoutput
);
14784 count
= bfd_get_symcount (stdoutput
);
14785 for (i
= 0; i
< count
; i
++, syms
++)
14787 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
14788 && ((*syms
)->value
& 1) != 0)
14790 (*syms
)->value
&= ~1;
14791 /* If the symbol has an odd size, it was probably computed
14792 incorrectly, so adjust that as well. */
14793 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14794 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14801 /* This function is called whenever a label is defined, including fake
14802 labels instantiated off the dot special symbol. It is used when
14803 handling branch delays; if a branch has a label, we assume we cannot
14804 move it. This also bumps the value of the symbol by 1 in compressed
14808 mips_record_label (symbolS
*sym
)
14810 segment_info_type
*si
= seg_info (now_seg
);
14811 struct insn_label_list
*l
;
14813 if (free_insn_labels
== NULL
)
14814 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14817 l
= free_insn_labels
;
14818 free_insn_labels
= l
->next
;
14822 l
->next
= si
->label_list
;
14823 si
->label_list
= l
;
14826 /* This function is called as tc_frob_label() whenever a label is defined
14827 and adds a DWARF-2 record we only want for true labels. */
14830 mips_define_label (symbolS
*sym
)
14832 mips_record_label (sym
);
14834 dwarf2_emit_label (sym
);
14838 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14840 /* Some special processing for a MIPS ELF file. */
14843 mips_elf_final_processing (void)
14845 /* Write out the register information. */
14846 if (mips_abi
!= N64_ABI
)
14850 s
.ri_gprmask
= mips_gprmask
;
14851 s
.ri_cprmask
[0] = mips_cprmask
[0];
14852 s
.ri_cprmask
[1] = mips_cprmask
[1];
14853 s
.ri_cprmask
[2] = mips_cprmask
[2];
14854 s
.ri_cprmask
[3] = mips_cprmask
[3];
14855 /* The gp_value field is set by the MIPS ELF backend. */
14857 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14858 ((Elf32_External_RegInfo
*)
14859 mips_regmask_frag
));
14863 Elf64_Internal_RegInfo s
;
14865 s
.ri_gprmask
= mips_gprmask
;
14867 s
.ri_cprmask
[0] = mips_cprmask
[0];
14868 s
.ri_cprmask
[1] = mips_cprmask
[1];
14869 s
.ri_cprmask
[2] = mips_cprmask
[2];
14870 s
.ri_cprmask
[3] = mips_cprmask
[3];
14871 /* The gp_value field is set by the MIPS ELF backend. */
14873 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14874 ((Elf64_External_RegInfo
*)
14875 mips_regmask_frag
));
14878 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14879 sort of BFD interface for this. */
14880 if (mips_any_noreorder
)
14881 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14882 if (mips_pic
!= NO_PIC
)
14884 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14885 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14888 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14890 /* Set MIPS ELF flags for ASEs. */
14891 /* We may need to define a new flag for DSP ASE, and set this flag when
14892 file_ase_dsp is true. */
14893 /* Same for DSP R2. */
14894 /* We may need to define a new flag for MT ASE, and set this flag when
14895 file_ase_mt is true. */
14896 if (file_ase_mips16
)
14897 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14898 #if 0 /* XXX FIXME */
14899 if (file_ase_mips3d
)
14900 elf_elfheader (stdoutput
)->e_flags
|= ???;
14903 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14905 /* Set the MIPS ELF ABI flags. */
14906 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14907 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14908 else if (mips_abi
== O64_ABI
)
14909 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14910 else if (mips_abi
== EABI_ABI
)
14912 if (!file_mips_gp32
)
14913 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14915 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14917 else if (mips_abi
== N32_ABI
)
14918 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14920 /* Nothing to do for N64_ABI. */
14922 if (mips_32bitmode
)
14923 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14925 #if 0 /* XXX FIXME */
14926 /* 32 bit code with 64 bit FP registers. */
14927 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14928 elf_elfheader (stdoutput
)->e_flags
|= ???;
14932 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14934 typedef struct proc
{
14936 symbolS
*func_end_sym
;
14937 unsigned long reg_mask
;
14938 unsigned long reg_offset
;
14939 unsigned long fpreg_mask
;
14940 unsigned long fpreg_offset
;
14941 unsigned long frame_offset
;
14942 unsigned long frame_reg
;
14943 unsigned long pc_reg
;
14946 static procS cur_proc
;
14947 static procS
*cur_proc_ptr
;
14948 static int numprocs
;
14950 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14954 mips_nop_opcode (void)
14956 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
14959 /* Fill in an rs_align_code fragment. This only needs to do something
14960 for MIPS16 code, where 0 is not a nop. */
14963 mips_handle_align (fragS
*fragp
)
14966 int bytes
, size
, excess
;
14969 if (fragp
->fr_type
!= rs_align_code
)
14972 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14975 opcode
= mips16_nop_insn
.insn_opcode
;
14980 opcode
= nop_insn
.insn_opcode
;
14984 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14985 excess
= bytes
% size
;
14988 /* If we're not inserting a whole number of instructions,
14989 pad the end of the fixed part of the frag with zeros. */
14990 memset (p
, 0, excess
);
14992 fragp
->fr_fix
+= excess
;
14995 md_number_to_chars (p
, opcode
, size
);
14996 fragp
->fr_var
= size
;
15000 md_obj_begin (void)
15007 /* Check for premature end, nesting errors, etc. */
15009 as_warn (_("missing .end at end of assembly"));
15018 if (*input_line_pointer
== '-')
15020 ++input_line_pointer
;
15023 if (!ISDIGIT (*input_line_pointer
))
15024 as_bad (_("expected simple number"));
15025 if (input_line_pointer
[0] == '0')
15027 if (input_line_pointer
[1] == 'x')
15029 input_line_pointer
+= 2;
15030 while (ISXDIGIT (*input_line_pointer
))
15033 val
|= hex_value (*input_line_pointer
++);
15035 return negative
? -val
: val
;
15039 ++input_line_pointer
;
15040 while (ISDIGIT (*input_line_pointer
))
15043 val
|= *input_line_pointer
++ - '0';
15045 return negative
? -val
: val
;
15048 if (!ISDIGIT (*input_line_pointer
))
15050 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15051 *input_line_pointer
, *input_line_pointer
);
15052 as_warn (_("invalid number"));
15055 while (ISDIGIT (*input_line_pointer
))
15058 val
+= *input_line_pointer
++ - '0';
15060 return negative
? -val
: val
;
15063 /* The .file directive; just like the usual .file directive, but there
15064 is an initial number which is the ECOFF file index. In the non-ECOFF
15065 case .file implies DWARF-2. */
15068 s_mips_file (int x ATTRIBUTE_UNUSED
)
15070 static int first_file_directive
= 0;
15072 if (ECOFF_DEBUGGING
)
15081 filename
= dwarf2_directive_file (0);
15083 /* Versions of GCC up to 3.1 start files with a ".file"
15084 directive even for stabs output. Make sure that this
15085 ".file" is handled. Note that you need a version of GCC
15086 after 3.1 in order to support DWARF-2 on MIPS. */
15087 if (filename
!= NULL
&& ! first_file_directive
)
15089 (void) new_logical_line (filename
, -1);
15090 s_app_file_string (filename
, 0);
15092 first_file_directive
= 1;
15096 /* The .loc directive, implying DWARF-2. */
15099 s_mips_loc (int x ATTRIBUTE_UNUSED
)
15101 if (!ECOFF_DEBUGGING
)
15102 dwarf2_directive_loc (0);
15105 /* The .end directive. */
15108 s_mips_end (int x ATTRIBUTE_UNUSED
)
15112 /* Following functions need their own .frame and .cprestore directives. */
15113 mips_frame_reg_valid
= 0;
15114 mips_cprestore_valid
= 0;
15116 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15119 demand_empty_rest_of_line ();
15124 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
15125 as_warn (_(".end not in text section"));
15129 as_warn (_(".end directive without a preceding .ent directive."));
15130 demand_empty_rest_of_line ();
15136 gas_assert (S_GET_NAME (p
));
15137 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
15138 as_warn (_(".end symbol does not match .ent symbol."));
15140 if (debug_type
== DEBUG_STABS
)
15141 stabs_generate_asm_endfunc (S_GET_NAME (p
),
15145 as_warn (_(".end directive missing or unknown symbol"));
15148 /* Create an expression to calculate the size of the function. */
15149 if (p
&& cur_proc_ptr
)
15151 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
15152 expressionS
*exp
= xmalloc (sizeof (expressionS
));
15155 exp
->X_op
= O_subtract
;
15156 exp
->X_add_symbol
= symbol_temp_new_now ();
15157 exp
->X_op_symbol
= p
;
15158 exp
->X_add_number
= 0;
15160 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
15163 /* Generate a .pdr section. */
15164 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
15166 segT saved_seg
= now_seg
;
15167 subsegT saved_subseg
= now_subseg
;
15171 #ifdef md_flush_pending_output
15172 md_flush_pending_output ();
15175 gas_assert (pdr_seg
);
15176 subseg_set (pdr_seg
, 0);
15178 /* Write the symbol. */
15179 exp
.X_op
= O_symbol
;
15180 exp
.X_add_symbol
= p
;
15181 exp
.X_add_number
= 0;
15182 emit_expr (&exp
, 4);
15184 fragp
= frag_more (7 * 4);
15186 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
15187 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
15188 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
15189 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
15190 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
15191 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
15192 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
15194 subseg_set (saved_seg
, saved_subseg
);
15196 #endif /* OBJ_ELF */
15198 cur_proc_ptr
= NULL
;
15201 /* The .aent and .ent directives. */
15204 s_mips_ent (int aent
)
15208 symbolP
= get_symbol ();
15209 if (*input_line_pointer
== ',')
15210 ++input_line_pointer
;
15211 SKIP_WHITESPACE ();
15212 if (ISDIGIT (*input_line_pointer
)
15213 || *input_line_pointer
== '-')
15216 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
15217 as_warn (_(".ent or .aent not in text section."));
15219 if (!aent
&& cur_proc_ptr
)
15220 as_warn (_("missing .end"));
15224 /* This function needs its own .frame and .cprestore directives. */
15225 mips_frame_reg_valid
= 0;
15226 mips_cprestore_valid
= 0;
15228 cur_proc_ptr
= &cur_proc
;
15229 memset (cur_proc_ptr
, '\0', sizeof (procS
));
15231 cur_proc_ptr
->func_sym
= symbolP
;
15235 if (debug_type
== DEBUG_STABS
)
15236 stabs_generate_asm_func (S_GET_NAME (symbolP
),
15237 S_GET_NAME (symbolP
));
15240 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
15242 demand_empty_rest_of_line ();
15245 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15246 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15247 s_mips_frame is used so that we can set the PDR information correctly.
15248 We can't use the ecoff routines because they make reference to the ecoff
15249 symbol table (in the mdebug section). */
15252 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
15255 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15259 if (cur_proc_ptr
== (procS
*) NULL
)
15261 as_warn (_(".frame outside of .ent"));
15262 demand_empty_rest_of_line ();
15266 cur_proc_ptr
->frame_reg
= tc_get_register (1);
15268 SKIP_WHITESPACE ();
15269 if (*input_line_pointer
++ != ','
15270 || get_absolute_expression_and_terminator (&val
) != ',')
15272 as_warn (_("Bad .frame directive"));
15273 --input_line_pointer
;
15274 demand_empty_rest_of_line ();
15278 cur_proc_ptr
->frame_offset
= val
;
15279 cur_proc_ptr
->pc_reg
= tc_get_register (0);
15281 demand_empty_rest_of_line ();
15284 #endif /* OBJ_ELF */
15288 /* The .fmask and .mask directives. If the mdebug section is present
15289 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15290 embedded targets, s_mips_mask is used so that we can set the PDR
15291 information correctly. We can't use the ecoff routines because they
15292 make reference to the ecoff symbol table (in the mdebug section). */
15295 s_mips_mask (int reg_type
)
15298 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15302 if (cur_proc_ptr
== (procS
*) NULL
)
15304 as_warn (_(".mask/.fmask outside of .ent"));
15305 demand_empty_rest_of_line ();
15309 if (get_absolute_expression_and_terminator (&mask
) != ',')
15311 as_warn (_("Bad .mask/.fmask directive"));
15312 --input_line_pointer
;
15313 demand_empty_rest_of_line ();
15317 off
= get_absolute_expression ();
15319 if (reg_type
== 'F')
15321 cur_proc_ptr
->fpreg_mask
= mask
;
15322 cur_proc_ptr
->fpreg_offset
= off
;
15326 cur_proc_ptr
->reg_mask
= mask
;
15327 cur_proc_ptr
->reg_offset
= off
;
15330 demand_empty_rest_of_line ();
15333 #endif /* OBJ_ELF */
15334 s_ignore (reg_type
);
15337 /* A table describing all the processors gas knows about. Names are
15338 matched in the order listed.
15340 To ease comparison, please keep this table in the same order as
15341 gcc's mips_cpu_info_table[]. */
15342 static const struct mips_cpu_info mips_cpu_info_table
[] =
15344 /* Entries for generic ISAs */
15345 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
15346 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
15347 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
15348 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
15349 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
15350 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
15351 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15352 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
15353 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
15356 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
15357 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
15358 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
15361 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
15364 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
15365 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
15366 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
15367 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
15368 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
15369 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
15370 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
15371 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
15372 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
15373 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
15374 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
15375 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
15376 /* ST Microelectronics Loongson 2E and 2F cores */
15377 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
15378 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
15381 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
15382 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
15383 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
15384 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
15385 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
15386 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
15387 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
15388 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
15389 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
15390 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15391 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15392 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15393 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15394 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15395 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15398 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15399 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15400 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15401 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15403 /* MIPS 32 Release 2 */
15404 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15405 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15406 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15407 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15408 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15409 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15410 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15411 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15412 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15413 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15414 /* Deprecated forms of the above. */
15415 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15416 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15417 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15418 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15419 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15420 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15421 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15422 /* Deprecated forms of the above. */
15423 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15424 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15425 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15426 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15427 ISA_MIPS32R2
, CPU_MIPS32R2
},
15428 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15429 ISA_MIPS32R2
, CPU_MIPS32R2
},
15430 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15431 ISA_MIPS32R2
, CPU_MIPS32R2
},
15432 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15433 ISA_MIPS32R2
, CPU_MIPS32R2
},
15434 /* Deprecated forms of the above. */
15435 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15436 ISA_MIPS32R2
, CPU_MIPS32R2
},
15437 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15438 ISA_MIPS32R2
, CPU_MIPS32R2
},
15439 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15440 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15441 ISA_MIPS32R2
, CPU_MIPS32R2
},
15442 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15443 ISA_MIPS32R2
, CPU_MIPS32R2
},
15444 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15445 ISA_MIPS32R2
, CPU_MIPS32R2
},
15446 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15447 ISA_MIPS32R2
, CPU_MIPS32R2
},
15448 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15449 ISA_MIPS32R2
, CPU_MIPS32R2
},
15450 /* Deprecated forms of the above. */
15451 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15452 ISA_MIPS32R2
, CPU_MIPS32R2
},
15453 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15454 ISA_MIPS32R2
, CPU_MIPS32R2
},
15455 /* 1004K cores are multiprocessor versions of the 34K. */
15456 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15457 ISA_MIPS32R2
, CPU_MIPS32R2
},
15458 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15459 ISA_MIPS32R2
, CPU_MIPS32R2
},
15460 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15461 ISA_MIPS32R2
, CPU_MIPS32R2
},
15462 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15463 ISA_MIPS32R2
, CPU_MIPS32R2
},
15466 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15467 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15468 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15469 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15471 /* Broadcom SB-1 CPU core */
15472 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15473 ISA_MIPS64
, CPU_SB1
},
15474 /* Broadcom SB-1A CPU core */
15475 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15476 ISA_MIPS64
, CPU_SB1
},
15478 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
15480 /* MIPS 64 Release 2 */
15482 /* Cavium Networks Octeon CPU core */
15483 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15486 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
15493 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15494 with a final "000" replaced by "k". Ignore case.
15496 Note: this function is shared between GCC and GAS. */
15499 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15501 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15502 given
++, canonical
++;
15504 return ((*given
== 0 && *canonical
== 0)
15505 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15509 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15510 CPU name. We've traditionally allowed a lot of variation here.
15512 Note: this function is shared between GCC and GAS. */
15515 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15517 /* First see if the name matches exactly, or with a final "000"
15518 turned into "k". */
15519 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15522 /* If not, try comparing based on numerical designation alone.
15523 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15524 if (TOLOWER (*given
) == 'r')
15526 if (!ISDIGIT (*given
))
15529 /* Skip over some well-known prefixes in the canonical name,
15530 hoping to find a number there too. */
15531 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15533 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15535 else if (TOLOWER (canonical
[0]) == 'r')
15538 return mips_strict_matching_cpu_name_p (canonical
, given
);
15542 /* Parse an option that takes the name of a processor as its argument.
15543 OPTION is the name of the option and CPU_STRING is the argument.
15544 Return the corresponding processor enumeration if the CPU_STRING is
15545 recognized, otherwise report an error and return null.
15547 A similar function exists in GCC. */
15549 static const struct mips_cpu_info
*
15550 mips_parse_cpu (const char *option
, const char *cpu_string
)
15552 const struct mips_cpu_info
*p
;
15554 /* 'from-abi' selects the most compatible architecture for the given
15555 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15556 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15557 version. Look first at the -mgp options, if given, otherwise base
15558 the choice on MIPS_DEFAULT_64BIT.
15560 Treat NO_ABI like the EABIs. One reason to do this is that the
15561 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15562 architecture. This code picks MIPS I for 'mips' and MIPS III for
15563 'mips64', just as we did in the days before 'from-abi'. */
15564 if (strcasecmp (cpu_string
, "from-abi") == 0)
15566 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15567 return mips_cpu_info_from_isa (ISA_MIPS1
);
15569 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15570 return mips_cpu_info_from_isa (ISA_MIPS3
);
15572 if (file_mips_gp32
>= 0)
15573 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15575 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15580 /* 'default' has traditionally been a no-op. Probably not very useful. */
15581 if (strcasecmp (cpu_string
, "default") == 0)
15584 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15585 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15588 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
15592 /* Return the canonical processor information for ISA (a member of the
15593 ISA_MIPS* enumeration). */
15595 static const struct mips_cpu_info
*
15596 mips_cpu_info_from_isa (int isa
)
15600 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15601 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15602 && isa
== mips_cpu_info_table
[i
].isa
)
15603 return (&mips_cpu_info_table
[i
]);
15608 static const struct mips_cpu_info
*
15609 mips_cpu_info_from_arch (int arch
)
15613 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15614 if (arch
== mips_cpu_info_table
[i
].cpu
)
15615 return (&mips_cpu_info_table
[i
]);
15621 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15625 fprintf (stream
, "%24s", "");
15630 fprintf (stream
, ", ");
15634 if (*col_p
+ strlen (string
) > 72)
15636 fprintf (stream
, "\n%24s", "");
15640 fprintf (stream
, "%s", string
);
15641 *col_p
+= strlen (string
);
15647 md_show_usage (FILE *stream
)
15652 fprintf (stream
, _("\
15654 -EB generate big endian output\n\
15655 -EL generate little endian output\n\
15656 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15657 -G NUM allow referencing objects up to NUM bytes\n\
15658 implicitly with the gp register [default 8]\n"));
15659 fprintf (stream
, _("\
15660 -mips1 generate MIPS ISA I instructions\n\
15661 -mips2 generate MIPS ISA II instructions\n\
15662 -mips3 generate MIPS ISA III instructions\n\
15663 -mips4 generate MIPS ISA IV instructions\n\
15664 -mips5 generate MIPS ISA V instructions\n\
15665 -mips32 generate MIPS32 ISA instructions\n\
15666 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15667 -mips64 generate MIPS64 ISA instructions\n\
15668 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15669 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15673 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15674 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15675 show (stream
, "from-abi", &column
, &first
);
15676 fputc ('\n', stream
);
15678 fprintf (stream
, _("\
15679 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15680 -no-mCPU don't generate code specific to CPU.\n\
15681 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15685 show (stream
, "3900", &column
, &first
);
15686 show (stream
, "4010", &column
, &first
);
15687 show (stream
, "4100", &column
, &first
);
15688 show (stream
, "4650", &column
, &first
);
15689 fputc ('\n', stream
);
15691 fprintf (stream
, _("\
15692 -mips16 generate mips16 instructions\n\
15693 -no-mips16 do not generate mips16 instructions\n"));
15694 fprintf (stream
, _("\
15695 -msmartmips generate smartmips instructions\n\
15696 -mno-smartmips do not generate smartmips instructions\n"));
15697 fprintf (stream
, _("\
15698 -mdsp generate DSP instructions\n\
15699 -mno-dsp do not generate DSP instructions\n"));
15700 fprintf (stream
, _("\
15701 -mdspr2 generate DSP R2 instructions\n\
15702 -mno-dspr2 do not generate DSP R2 instructions\n"));
15703 fprintf (stream
, _("\
15704 -mmt generate MT instructions\n\
15705 -mno-mt do not generate MT instructions\n"));
15706 fprintf (stream
, _("\
15707 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15708 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15709 -mfix-vr4120 work around certain VR4120 errata\n\
15710 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15711 -mfix-24k insert a nop after ERET and DERET instructions\n\
15712 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15713 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15714 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15715 -msym32 assume all symbols have 32-bit values\n\
15716 -O0 remove unneeded NOPs, do not swap branches\n\
15717 -O remove unneeded NOPs and swap branches\n\
15718 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15719 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15720 fprintf (stream
, _("\
15721 -mhard-float allow floating-point instructions\n\
15722 -msoft-float do not allow floating-point instructions\n\
15723 -msingle-float only allow 32-bit floating-point operations\n\
15724 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15725 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15728 fprintf (stream
, _("\
15729 -KPIC, -call_shared generate SVR4 position independent code\n\
15730 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15731 -mvxworks-pic generate VxWorks position independent code\n\
15732 -non_shared do not generate code that can operate with DSOs\n\
15733 -xgot assume a 32 bit GOT\n\
15734 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15735 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15736 position dependent (non shared) code\n\
15737 -mabi=ABI create ABI conformant object file for:\n"));
15741 show (stream
, "32", &column
, &first
);
15742 show (stream
, "o64", &column
, &first
);
15743 show (stream
, "n32", &column
, &first
);
15744 show (stream
, "64", &column
, &first
);
15745 show (stream
, "eabi", &column
, &first
);
15747 fputc ('\n', stream
);
15749 fprintf (stream
, _("\
15750 -32 create o32 ABI object file (default)\n\
15751 -n32 create n32 ABI object file\n\
15752 -64 create 64 ABI object file\n"));
15758 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
15760 if (HAVE_64BIT_SYMBOLS
)
15761 return dwarf2_format_64bit_irix
;
15763 return dwarf2_format_32bit
;
15768 mips_dwarf2_addr_size (void)
15770 if (HAVE_64BIT_OBJECTS
)
15776 /* Standard calling conventions leave the CFA at SP on entry. */
15778 mips_cfi_frame_initial_instructions (void)
15780 cfi_add_CFA_def_cfa_register (SP
);
15784 tc_mips_regname_to_dw2regnum (char *regname
)
15786 unsigned int regnum
= -1;
15789 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))