1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa
;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1138 | ((e2) ? 0x100 : 0) \
1139 | ((pic) ? 0x200 : 0) \
1140 | ((sym32) ? 0x400 : 0) \
1141 | ((nomacro) ? 0x800 : 0) \
1142 | ((small) ? 0x1000 : 0) \
1143 | ((ext) ? 0x2000 : 0) \
1144 | ((dslot) ? 0x4000 : 0) \
1145 | ((jal_dslot) ? 0x8000 : 0))
1147 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1148 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1149 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1150 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1151 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1152 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1153 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1154 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1155 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1158 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1159 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1160 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1161 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1162 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1163 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1164 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1165 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1166 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1168 /* For microMIPS code, we use relaxation similar to one we use for
1169 MIPS16 code. Some instructions that take immediate values support
1170 two encodings: a small one which takes some small value, and a
1171 larger one which takes a 16 bit value. As some branches also follow
1172 this pattern, relaxing these values is required.
1174 We can assemble both microMIPS and normal MIPS code in a single
1175 object. Therefore, we need to support this type of relaxation at
1176 the same time that we support the relaxation described above. We
1177 use one of the high bits of the subtype field to distinguish these
1180 The information we store for this type of relaxation is the argument
1181 code found in the opcode file for this relocation, the register
1182 selected as the assembler temporary, whether in the 32-bit
1183 instruction mode, whether the branch is unconditional, whether it is
1184 compact, whether there is no delay-slot instruction available to fill
1185 in, whether it stores the link address implicitly in $ra, whether
1186 relaxation of out-of-range 32-bit branches to a sequence of
1187 instructions is enabled, and whether the displacement of a branch is
1188 too large to fit as an immediate argument of a 16-bit and a 32-bit
1189 branch, respectively. */
1190 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1191 uncond, compact, link, nods, \
1192 relax32, toofar16, toofar32) \
1195 | (((at) & 0x1f) << 8) \
1196 | ((insn32) ? 0x2000 : 0) \
1197 | ((pic) ? 0x4000 : 0) \
1198 | ((uncond) ? 0x8000 : 0) \
1199 | ((compact) ? 0x10000 : 0) \
1200 | ((link) ? 0x20000 : 0) \
1201 | ((nods) ? 0x40000 : 0) \
1202 | ((relax32) ? 0x80000 : 0) \
1203 | ((toofar16) ? 0x100000 : 0) \
1204 | ((toofar32) ? 0x200000 : 0))
1205 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1206 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1207 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1208 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1209 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1210 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1211 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1212 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1213 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1214 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1216 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1217 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1218 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1219 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1220 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1221 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1223 /* Sign-extend 16-bit value X. */
1224 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1226 /* Is the given value a sign-extended 32-bit value? */
1227 #define IS_SEXT_32BIT_NUM(x) \
1228 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1229 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1231 /* Is the given value a sign-extended 16-bit value? */
1232 #define IS_SEXT_16BIT_NUM(x) \
1233 (((x) &~ (offsetT) 0x7fff) == 0 \
1234 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1236 /* Is the given value a sign-extended 12-bit value? */
1237 #define IS_SEXT_12BIT_NUM(x) \
1238 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1240 /* Is the given value a sign-extended 9-bit value? */
1241 #define IS_SEXT_9BIT_NUM(x) \
1242 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1244 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1245 #define IS_ZEXT_32BIT_NUM(x) \
1246 (((x) &~ (offsetT) 0xffffffff) == 0 \
1247 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1249 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1251 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1252 (((STRUCT) >> (SHIFT)) & (MASK))
1254 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1255 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1257 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1258 : EXTRACT_BITS ((INSN).insn_opcode, \
1259 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1260 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1261 EXTRACT_BITS ((INSN).insn_opcode, \
1262 MIPS16OP_MASK_##FIELD, \
1263 MIPS16OP_SH_##FIELD)
1265 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1266 #define MIPS16_EXTEND (0xf000U << 16)
1268 /* Whether or not we are emitting a branch-likely macro. */
1269 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1271 /* Global variables used when generating relaxable macros. See the
1272 comment above RELAX_ENCODE for more details about how relaxation
1275 /* 0 if we're not emitting a relaxable macro.
1276 1 if we're emitting the first of the two relaxation alternatives.
1277 2 if we're emitting the second alternative. */
1280 /* The first relaxable fixup in the current frag. (In other words,
1281 the first fixup that refers to relaxable code.) */
1284 /* sizes[0] says how many bytes of the first alternative are stored in
1285 the current frag. Likewise sizes[1] for the second alternative. */
1286 unsigned int sizes
[2];
1288 /* The symbol on which the choice of sequence depends. */
1292 /* Global variables used to decide whether a macro needs a warning. */
1294 /* True if the macro is in a branch delay slot. */
1295 bfd_boolean delay_slot_p
;
1297 /* Set to the length in bytes required if the macro is in a delay slot
1298 that requires a specific length of instruction, otherwise zero. */
1299 unsigned int delay_slot_length
;
1301 /* For relaxable macros, sizes[0] is the length of the first alternative
1302 in bytes and sizes[1] is the length of the second alternative.
1303 For non-relaxable macros, both elements give the length of the
1305 unsigned int sizes
[2];
1307 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1308 instruction of the first alternative in bytes and first_insn_sizes[1]
1309 is the length of the first instruction of the second alternative.
1310 For non-relaxable macros, both elements give the length of the first
1311 instruction in bytes.
1313 Set to zero if we haven't yet seen the first instruction. */
1314 unsigned int first_insn_sizes
[2];
1316 /* For relaxable macros, insns[0] is the number of instructions for the
1317 first alternative and insns[1] is the number of instructions for the
1320 For non-relaxable macros, both elements give the number of
1321 instructions for the macro. */
1322 unsigned int insns
[2];
1324 /* The first variant frag for this macro. */
1326 } mips_macro_warning
;
1328 /* Prototypes for static functions. */
1330 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1332 static void append_insn
1333 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1334 bfd_boolean expansionp
);
1335 static void mips_no_prev_insn (void);
1336 static void macro_build (expressionS
*, const char *, const char *, ...);
1337 static void mips16_macro_build
1338 (expressionS
*, const char *, const char *, va_list *);
1339 static void load_register (int, expressionS
*, int);
1340 static void macro_start (void);
1341 static void macro_end (void);
1342 static void macro (struct mips_cl_insn
*ip
, char *str
);
1343 static void mips16_macro (struct mips_cl_insn
* ip
);
1344 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1345 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1346 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1347 static void mips16_immed
1348 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1349 unsigned int, unsigned long *);
1350 static size_t my_getSmallExpression
1351 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1352 static void my_getExpression (expressionS
*, char *);
1353 static void s_align (int);
1354 static void s_change_sec (int);
1355 static void s_change_section (int);
1356 static void s_cons (int);
1357 static void s_float_cons (int);
1358 static void s_mips_globl (int);
1359 static void s_option (int);
1360 static void s_mipsset (int);
1361 static void s_abicalls (int);
1362 static void s_cpload (int);
1363 static void s_cpsetup (int);
1364 static void s_cplocal (int);
1365 static void s_cprestore (int);
1366 static void s_cpreturn (int);
1367 static void s_dtprelword (int);
1368 static void s_dtpreldword (int);
1369 static void s_tprelword (int);
1370 static void s_tpreldword (int);
1371 static void s_gpvalue (int);
1372 static void s_gpword (int);
1373 static void s_gpdword (int);
1374 static void s_ehword (int);
1375 static void s_cpadd (int);
1376 static void s_insn (int);
1377 static void s_nan (int);
1378 static void s_module (int);
1379 static void s_mips_ent (int);
1380 static void s_mips_end (int);
1381 static void s_mips_frame (int);
1382 static void s_mips_mask (int reg_type
);
1383 static void s_mips_stab (int);
1384 static void s_mips_weakext (int);
1385 static void s_mips_file (int);
1386 static void s_mips_loc (int);
1387 static bfd_boolean
pic_need_relax (symbolS
*);
1388 static int relaxed_branch_length (fragS
*, asection
*, int);
1389 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1390 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1391 static void file_mips_check_options (void);
1393 /* Table and functions used to map between CPU/ISA names, and
1394 ISA levels, and CPU numbers. */
1396 struct mips_cpu_info
1398 const char *name
; /* CPU or ISA name. */
1399 int flags
; /* MIPS_CPU_* flags. */
1400 int ase
; /* Set of ASEs implemented by the CPU. */
1401 int isa
; /* ISA level. */
1402 int cpu
; /* CPU number (default CPU if ISA). */
1405 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1407 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1408 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1409 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1411 /* Command-line options. */
1412 const char *md_shortopts
= "O::g::G:";
1416 OPTION_MARCH
= OPTION_MD_BASE
,
1448 OPTION_NO_SMARTMIPS
,
1458 OPTION_NO_MICROMIPS
,
1473 OPTION_M7000_HILO_FIX
,
1474 OPTION_MNO_7000_HILO_FIX
,
1478 OPTION_NO_FIX_RM7000
,
1479 OPTION_FIX_LOONGSON2F_JUMP
,
1480 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1481 OPTION_FIX_LOONGSON2F_NOP
,
1482 OPTION_NO_FIX_LOONGSON2F_NOP
,
1484 OPTION_NO_FIX_VR4120
,
1486 OPTION_NO_FIX_VR4130
,
1487 OPTION_FIX_CN63XXP1
,
1488 OPTION_NO_FIX_CN63XXP1
,
1495 OPTION_CONSTRUCT_FLOATS
,
1496 OPTION_NO_CONSTRUCT_FLOATS
,
1500 OPTION_RELAX_BRANCH
,
1501 OPTION_NO_RELAX_BRANCH
,
1502 OPTION_IGNORE_BRANCH_ISA
,
1503 OPTION_NO_IGNORE_BRANCH_ISA
,
1512 OPTION_SINGLE_FLOAT
,
1513 OPTION_DOUBLE_FLOAT
,
1526 OPTION_MVXWORKS_PIC
,
1529 OPTION_NO_ODD_SPREG
,
1532 OPTION_LOONGSON_MMI
,
1533 OPTION_NO_LOONGSON_MMI
,
1537 struct option md_longopts
[] =
1539 /* Options which specify architecture. */
1540 {"march", required_argument
, NULL
, OPTION_MARCH
},
1541 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1542 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1543 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1544 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1545 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1546 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1547 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1548 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1549 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1550 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1551 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1552 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1553 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1554 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1555 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1556 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1557 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1559 /* Options which specify Application Specific Extensions (ASEs). */
1560 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1561 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1562 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1563 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1564 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1565 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1566 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1567 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1568 {"mmt", no_argument
, NULL
, OPTION_MT
},
1569 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1570 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1571 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1572 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1573 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1574 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1575 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1576 {"meva", no_argument
, NULL
, OPTION_EVA
},
1577 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1578 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1579 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1580 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1581 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1582 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1583 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1584 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1585 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1586 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1587 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1588 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1589 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1590 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1591 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1592 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1593 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1594 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1595 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1597 /* Old-style architecture options. Don't add more of these. */
1598 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1599 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1600 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1601 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1602 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1603 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1604 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1605 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1607 /* Options which enable bug fixes. */
1608 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1609 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1610 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1611 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1612 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1613 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1614 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1615 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1616 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1617 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1618 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1619 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1620 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1621 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1622 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1623 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1624 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1626 /* Miscellaneous options. */
1627 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1628 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1629 {"break", no_argument
, NULL
, OPTION_BREAK
},
1630 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1631 {"EB", no_argument
, NULL
, OPTION_EB
},
1632 {"EL", no_argument
, NULL
, OPTION_EL
},
1633 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1634 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1635 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1636 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1637 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1638 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1639 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1640 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1641 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1642 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1643 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1644 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1645 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1646 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1647 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1648 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1649 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1650 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1651 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1652 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1653 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1654 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1655 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1657 /* Strictly speaking this next option is ELF specific,
1658 but we allow it for other ports as well in order to
1659 make testing easier. */
1660 {"32", no_argument
, NULL
, OPTION_32
},
1662 /* ELF-specific options. */
1663 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1664 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1665 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1666 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1667 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1668 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1669 {"n32", no_argument
, NULL
, OPTION_N32
},
1670 {"64", no_argument
, NULL
, OPTION_64
},
1671 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1672 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1673 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1674 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1675 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1676 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1678 {NULL
, no_argument
, NULL
, 0}
1680 size_t md_longopts_size
= sizeof (md_longopts
);
1682 /* Information about either an Application Specific Extension or an
1683 optional architecture feature that, for simplicity, we treat in the
1684 same way as an ASE. */
1687 /* The name of the ASE, used in both the command-line and .set options. */
1690 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1691 and 64-bit architectures, the flags here refer to the subset that
1692 is available on both. */
1695 /* The ASE_* flag used for instructions that are available on 64-bit
1696 architectures but that are not included in FLAGS. */
1697 unsigned int flags64
;
1699 /* The command-line options that turn the ASE on and off. */
1703 /* The minimum required architecture revisions for MIPS32, MIPS64,
1704 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1707 int micromips32_rev
;
1708 int micromips64_rev
;
1710 /* The architecture where the ASE was removed or -1 if the extension has not
1715 /* A table of all supported ASEs. */
1716 static const struct mips_ase mips_ases
[] = {
1717 { "dsp", ASE_DSP
, ASE_DSP64
,
1718 OPTION_DSP
, OPTION_NO_DSP
,
1722 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1723 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1727 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1728 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1732 { "eva", ASE_EVA
, 0,
1733 OPTION_EVA
, OPTION_NO_EVA
,
1737 { "mcu", ASE_MCU
, 0,
1738 OPTION_MCU
, OPTION_NO_MCU
,
1742 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1743 { "mdmx", ASE_MDMX
, 0,
1744 OPTION_MDMX
, OPTION_NO_MDMX
,
1748 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1749 { "mips3d", ASE_MIPS3D
, 0,
1750 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1755 OPTION_MT
, OPTION_NO_MT
,
1759 { "smartmips", ASE_SMARTMIPS
, 0,
1760 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1764 { "virt", ASE_VIRT
, ASE_VIRT64
,
1765 OPTION_VIRT
, OPTION_NO_VIRT
,
1769 { "msa", ASE_MSA
, ASE_MSA64
,
1770 OPTION_MSA
, OPTION_NO_MSA
,
1774 { "xpa", ASE_XPA
, 0,
1775 OPTION_XPA
, OPTION_NO_XPA
,
1779 { "mips16e2", ASE_MIPS16E2
, 0,
1780 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1784 { "crc", ASE_CRC
, ASE_CRC64
,
1785 OPTION_CRC
, OPTION_NO_CRC
,
1789 { "ginv", ASE_GINV
, 0,
1790 OPTION_GINV
, OPTION_NO_GINV
,
1794 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1795 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1800 /* The set of ASEs that require -mfp64. */
1801 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1803 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1804 static const unsigned int mips_ase_groups
[] = {
1805 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
1810 The following pseudo-ops from the Kane and Heinrich MIPS book
1811 should be defined here, but are currently unsupported: .alias,
1812 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1814 The following pseudo-ops from the Kane and Heinrich MIPS book are
1815 specific to the type of debugging information being generated, and
1816 should be defined by the object format: .aent, .begin, .bend,
1817 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1820 The following pseudo-ops from the Kane and Heinrich MIPS book are
1821 not MIPS CPU specific, but are also not specific to the object file
1822 format. This file is probably the best place to define them, but
1823 they are not currently supported: .asm0, .endr, .lab, .struct. */
1825 static const pseudo_typeS mips_pseudo_table
[] =
1827 /* MIPS specific pseudo-ops. */
1828 {"option", s_option
, 0},
1829 {"set", s_mipsset
, 0},
1830 {"rdata", s_change_sec
, 'r'},
1831 {"sdata", s_change_sec
, 's'},
1832 {"livereg", s_ignore
, 0},
1833 {"abicalls", s_abicalls
, 0},
1834 {"cpload", s_cpload
, 0},
1835 {"cpsetup", s_cpsetup
, 0},
1836 {"cplocal", s_cplocal
, 0},
1837 {"cprestore", s_cprestore
, 0},
1838 {"cpreturn", s_cpreturn
, 0},
1839 {"dtprelword", s_dtprelword
, 0},
1840 {"dtpreldword", s_dtpreldword
, 0},
1841 {"tprelword", s_tprelword
, 0},
1842 {"tpreldword", s_tpreldword
, 0},
1843 {"gpvalue", s_gpvalue
, 0},
1844 {"gpword", s_gpword
, 0},
1845 {"gpdword", s_gpdword
, 0},
1846 {"ehword", s_ehword
, 0},
1847 {"cpadd", s_cpadd
, 0},
1848 {"insn", s_insn
, 0},
1850 {"module", s_module
, 0},
1852 /* Relatively generic pseudo-ops that happen to be used on MIPS
1854 {"asciiz", stringer
, 8 + 1},
1855 {"bss", s_change_sec
, 'b'},
1857 {"half", s_cons
, 1},
1858 {"dword", s_cons
, 3},
1859 {"weakext", s_mips_weakext
, 0},
1860 {"origin", s_org
, 0},
1861 {"repeat", s_rept
, 0},
1863 /* For MIPS this is non-standard, but we define it for consistency. */
1864 {"sbss", s_change_sec
, 'B'},
1866 /* These pseudo-ops are defined in read.c, but must be overridden
1867 here for one reason or another. */
1868 {"align", s_align
, 0},
1869 {"byte", s_cons
, 0},
1870 {"data", s_change_sec
, 'd'},
1871 {"double", s_float_cons
, 'd'},
1872 {"float", s_float_cons
, 'f'},
1873 {"globl", s_mips_globl
, 0},
1874 {"global", s_mips_globl
, 0},
1875 {"hword", s_cons
, 1},
1877 {"long", s_cons
, 2},
1878 {"octa", s_cons
, 4},
1879 {"quad", s_cons
, 3},
1880 {"section", s_change_section
, 0},
1881 {"short", s_cons
, 1},
1882 {"single", s_float_cons
, 'f'},
1883 {"stabd", s_mips_stab
, 'd'},
1884 {"stabn", s_mips_stab
, 'n'},
1885 {"stabs", s_mips_stab
, 's'},
1886 {"text", s_change_sec
, 't'},
1887 {"word", s_cons
, 2},
1889 { "extern", ecoff_directive_extern
, 0},
1894 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1896 /* These pseudo-ops should be defined by the object file format.
1897 However, a.out doesn't support them, so we have versions here. */
1898 {"aent", s_mips_ent
, 1},
1899 {"bgnb", s_ignore
, 0},
1900 {"end", s_mips_end
, 0},
1901 {"endb", s_ignore
, 0},
1902 {"ent", s_mips_ent
, 0},
1903 {"file", s_mips_file
, 0},
1904 {"fmask", s_mips_mask
, 'F'},
1905 {"frame", s_mips_frame
, 0},
1906 {"loc", s_mips_loc
, 0},
1907 {"mask", s_mips_mask
, 'R'},
1908 {"verstamp", s_ignore
, 0},
1912 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1913 purpose of the `.dc.a' internal pseudo-op. */
1916 mips_address_bytes (void)
1918 file_mips_check_options ();
1919 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1922 extern void pop_insert (const pseudo_typeS
*);
1925 mips_pop_insert (void)
1927 pop_insert (mips_pseudo_table
);
1928 if (! ECOFF_DEBUGGING
)
1929 pop_insert (mips_nonecoff_pseudo_table
);
1932 /* Symbols labelling the current insn. */
1934 struct insn_label_list
1936 struct insn_label_list
*next
;
1940 static struct insn_label_list
*free_insn_labels
;
1941 #define label_list tc_segment_info_data.labels
1943 static void mips_clear_insn_labels (void);
1944 static void mips_mark_labels (void);
1945 static void mips_compressed_mark_labels (void);
1948 mips_clear_insn_labels (void)
1950 struct insn_label_list
**pl
;
1951 segment_info_type
*si
;
1955 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1958 si
= seg_info (now_seg
);
1959 *pl
= si
->label_list
;
1960 si
->label_list
= NULL
;
1964 /* Mark instruction labels in MIPS16/microMIPS mode. */
1967 mips_mark_labels (void)
1969 if (HAVE_CODE_COMPRESSION
)
1970 mips_compressed_mark_labels ();
1973 static char *expr_end
;
1975 /* An expression in a macro instruction. This is set by mips_ip and
1976 mips16_ip and when populated is always an O_constant. */
1978 static expressionS imm_expr
;
1980 /* The relocatable field in an instruction and the relocs associated
1981 with it. These variables are used for instructions like LUI and
1982 JAL as well as true offsets. They are also used for address
1983 operands in macros. */
1985 static expressionS offset_expr
;
1986 static bfd_reloc_code_real_type offset_reloc
[3]
1987 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1989 /* This is set to the resulting size of the instruction to be produced
1990 by mips16_ip if an explicit extension is used or by mips_ip if an
1991 explicit size is supplied. */
1993 static unsigned int forced_insn_length
;
1995 /* True if we are assembling an instruction. All dot symbols defined during
1996 this time should be treated as code labels. */
1998 static bfd_boolean mips_assembling_insn
;
2000 /* The pdr segment for per procedure frame/regmask info. Not used for
2003 static segT pdr_seg
;
2005 /* The default target format to use. */
2007 #if defined (TE_FreeBSD)
2008 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2009 #elif defined (TE_TMIPS)
2010 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2012 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2016 mips_target_format (void)
2018 switch (OUTPUT_FLAVOR
)
2020 case bfd_target_elf_flavour
:
2022 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2023 return (target_big_endian
2024 ? "elf32-bigmips-vxworks"
2025 : "elf32-littlemips-vxworks");
2027 return (target_big_endian
2028 ? (HAVE_64BIT_OBJECTS
2029 ? ELF_TARGET ("elf64-", "big")
2031 ? ELF_TARGET ("elf32-n", "big")
2032 : ELF_TARGET ("elf32-", "big")))
2033 : (HAVE_64BIT_OBJECTS
2034 ? ELF_TARGET ("elf64-", "little")
2036 ? ELF_TARGET ("elf32-n", "little")
2037 : ELF_TARGET ("elf32-", "little"))));
2044 /* Return the ISA revision that is currently in use, or 0 if we are
2045 generating code for MIPS V or below. */
2050 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2053 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2056 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2059 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2062 /* microMIPS implies revision 2 or above. */
2063 if (mips_opts
.micromips
)
2066 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2072 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2075 mips_ase_mask (unsigned int flags
)
2079 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2080 if (flags
& mips_ase_groups
[i
])
2081 flags
|= mips_ase_groups
[i
];
2085 /* Check whether the current ISA supports ASE. Issue a warning if
2089 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2093 static unsigned int warned_isa
;
2094 static unsigned int warned_fp32
;
2096 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2097 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2099 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2100 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2101 && (warned_isa
& ase
->flags
) != ase
->flags
)
2103 warned_isa
|= ase
->flags
;
2104 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2105 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2107 as_warn (_("the %d-bit %s architecture does not support the"
2108 " `%s' extension"), size
, base
, ase
->name
);
2110 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2111 ase
->name
, base
, size
, min_rev
);
2113 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2114 && (warned_isa
& ase
->flags
) != ase
->flags
)
2116 warned_isa
|= ase
->flags
;
2117 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2118 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2119 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2120 ase
->name
, base
, size
, ase
->rem_rev
);
2123 if ((ase
->flags
& FP64_ASES
)
2124 && mips_opts
.fp
!= 64
2125 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2127 warned_fp32
|= ase
->flags
;
2128 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2132 /* Check all enabled ASEs to see whether they are supported by the
2133 chosen architecture. */
2136 mips_check_isa_supports_ases (void)
2138 unsigned int i
, mask
;
2140 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2142 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2143 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2144 mips_check_isa_supports_ase (&mips_ases
[i
]);
2148 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2149 that were affected. */
2152 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2153 bfd_boolean enabled_p
)
2157 mask
= mips_ase_mask (ase
->flags
);
2160 /* Clear combination ASE flags, which need to be recalculated based on
2161 updated regular ASE settings. */
2162 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
);
2165 opts
->ase
|= ase
->flags
;
2167 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2168 instructions which are only valid when both ASEs are enabled.
2169 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2170 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2172 opts
->ase
|= ASE_XPA_VIRT
;
2173 mask
|= ASE_XPA_VIRT
;
2175 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2177 opts
->ase
|= ASE_MIPS16E2_MT
;
2178 mask
|= ASE_MIPS16E2_MT
;
2184 /* Return the ASE called NAME, or null if none. */
2186 static const struct mips_ase
*
2187 mips_lookup_ase (const char *name
)
2191 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2192 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2193 return &mips_ases
[i
];
2197 /* Return the length of a microMIPS instruction in bytes. If bits of
2198 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2199 otherwise it is a 32-bit instruction. */
2201 static inline unsigned int
2202 micromips_insn_length (const struct mips_opcode
*mo
)
2204 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2207 /* Return the length of MIPS16 instruction OPCODE. */
2209 static inline unsigned int
2210 mips16_opcode_length (unsigned long opcode
)
2212 return (opcode
>> 16) == 0 ? 2 : 4;
2215 /* Return the length of instruction INSN. */
2217 static inline unsigned int
2218 insn_length (const struct mips_cl_insn
*insn
)
2220 if (mips_opts
.micromips
)
2221 return micromips_insn_length (insn
->insn_mo
);
2222 else if (mips_opts
.mips16
)
2223 return mips16_opcode_length (insn
->insn_opcode
);
2228 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2231 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2236 insn
->insn_opcode
= mo
->match
;
2239 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2240 insn
->fixp
[i
] = NULL
;
2241 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2242 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2243 insn
->mips16_absolute_jump_p
= 0;
2244 insn
->complete_p
= 0;
2245 insn
->cleared_p
= 0;
2248 /* Get a list of all the operands in INSN. */
2250 static const struct mips_operand_array
*
2251 insn_operands (const struct mips_cl_insn
*insn
)
2253 if (insn
->insn_mo
>= &mips_opcodes
[0]
2254 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2255 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2257 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2258 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2259 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2261 if (insn
->insn_mo
>= µmips_opcodes
[0]
2262 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2263 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2268 /* Get a description of operand OPNO of INSN. */
2270 static const struct mips_operand
*
2271 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2273 const struct mips_operand_array
*operands
;
2275 operands
= insn_operands (insn
);
2276 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2278 return operands
->operand
[opno
];
2281 /* Install UVAL as the value of OPERAND in INSN. */
2284 insn_insert_operand (struct mips_cl_insn
*insn
,
2285 const struct mips_operand
*operand
, unsigned int uval
)
2287 if (mips_opts
.mips16
2288 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2289 && mips_opcode_32bit_p (insn
->insn_mo
))
2290 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2292 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2295 /* Extract the value of OPERAND from INSN. */
2297 static inline unsigned
2298 insn_extract_operand (const struct mips_cl_insn
*insn
,
2299 const struct mips_operand
*operand
)
2301 return mips_extract_operand (operand
, insn
->insn_opcode
);
2304 /* Record the current MIPS16/microMIPS mode in now_seg. */
2307 mips_record_compressed_mode (void)
2309 segment_info_type
*si
;
2311 si
= seg_info (now_seg
);
2312 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2313 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2314 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2315 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2318 /* Read a standard MIPS instruction from BUF. */
2320 static unsigned long
2321 read_insn (char *buf
)
2323 if (target_big_endian
)
2324 return bfd_getb32 ((bfd_byte
*) buf
);
2326 return bfd_getl32 ((bfd_byte
*) buf
);
2329 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2333 write_insn (char *buf
, unsigned int insn
)
2335 md_number_to_chars (buf
, insn
, 4);
2339 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2340 has length LENGTH. */
2342 static unsigned long
2343 read_compressed_insn (char *buf
, unsigned int length
)
2349 for (i
= 0; i
< length
; i
+= 2)
2352 if (target_big_endian
)
2353 insn
|= bfd_getb16 ((char *) buf
);
2355 insn
|= bfd_getl16 ((char *) buf
);
2361 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2362 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2365 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2369 for (i
= 0; i
< length
; i
+= 2)
2370 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2371 return buf
+ length
;
2374 /* Install INSN at the location specified by its "frag" and "where" fields. */
2377 install_insn (const struct mips_cl_insn
*insn
)
2379 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2380 if (HAVE_CODE_COMPRESSION
)
2381 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2383 write_insn (f
, insn
->insn_opcode
);
2384 mips_record_compressed_mode ();
2387 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2388 and install the opcode in the new location. */
2391 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2396 insn
->where
= where
;
2397 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2398 if (insn
->fixp
[i
] != NULL
)
2400 insn
->fixp
[i
]->fx_frag
= frag
;
2401 insn
->fixp
[i
]->fx_where
= where
;
2403 install_insn (insn
);
2406 /* Add INSN to the end of the output. */
2409 add_fixed_insn (struct mips_cl_insn
*insn
)
2411 char *f
= frag_more (insn_length (insn
));
2412 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2415 /* Start a variant frag and move INSN to the start of the variant part,
2416 marking it as fixed. The other arguments are as for frag_var. */
2419 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2420 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2422 frag_grow (max_chars
);
2423 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2425 frag_var (rs_machine_dependent
, max_chars
, var
,
2426 subtype
, symbol
, offset
, NULL
);
2429 /* Insert N copies of INSN into the history buffer, starting at
2430 position FIRST. Neither FIRST nor N need to be clipped. */
2433 insert_into_history (unsigned int first
, unsigned int n
,
2434 const struct mips_cl_insn
*insn
)
2436 if (mips_relax
.sequence
!= 2)
2440 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2442 history
[i
] = history
[i
- n
];
2448 /* Clear the error in insn_error. */
2451 clear_insn_error (void)
2453 memset (&insn_error
, 0, sizeof (insn_error
));
2456 /* Possibly record error message MSG for the current instruction.
2457 If the error is about a particular argument, ARGNUM is the 1-based
2458 number of that argument, otherwise it is 0. FORMAT is the format
2459 of MSG. Return true if MSG was used, false if the current message
2463 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2468 /* Give priority to errors against specific arguments, and to
2469 the first whole-instruction message. */
2475 /* Keep insn_error if it is against a later argument. */
2476 if (argnum
< insn_error
.min_argnum
)
2479 /* If both errors are against the same argument but are different,
2480 give up on reporting a specific error for this argument.
2481 See the comment about mips_insn_error for details. */
2482 if (argnum
== insn_error
.min_argnum
2484 && strcmp (insn_error
.msg
, msg
) != 0)
2487 insn_error
.min_argnum
+= 1;
2491 insn_error
.min_argnum
= argnum
;
2492 insn_error
.format
= format
;
2493 insn_error
.msg
= msg
;
2497 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2498 as for set_insn_error_format. */
2501 set_insn_error (int argnum
, const char *msg
)
2503 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2506 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2507 as for set_insn_error_format. */
2510 set_insn_error_i (int argnum
, const char *msg
, int i
)
2512 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2516 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2517 are as for set_insn_error_format. */
2520 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2522 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2524 insn_error
.u
.ss
[0] = s1
;
2525 insn_error
.u
.ss
[1] = s2
;
2529 /* Report the error in insn_error, which is against assembly code STR. */
2532 report_insn_error (const char *str
)
2534 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2536 switch (insn_error
.format
)
2543 as_bad (msg
, insn_error
.u
.i
, str
);
2547 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2551 free ((char *) msg
);
2554 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2555 the idea is to make it obvious at a glance that each errata is
2559 init_vr4120_conflicts (void)
2561 #define CONFLICT(FIRST, SECOND) \
2562 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2564 /* Errata 21 - [D]DIV[U] after [D]MACC */
2565 CONFLICT (MACC
, DIV
);
2566 CONFLICT (DMACC
, DIV
);
2568 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2569 CONFLICT (DMULT
, DMULT
);
2570 CONFLICT (DMULT
, DMACC
);
2571 CONFLICT (DMACC
, DMULT
);
2572 CONFLICT (DMACC
, DMACC
);
2574 /* Errata 24 - MT{LO,HI} after [D]MACC */
2575 CONFLICT (MACC
, MTHILO
);
2576 CONFLICT (DMACC
, MTHILO
);
2578 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2579 instruction is executed immediately after a MACC or DMACC
2580 instruction, the result of [either instruction] is incorrect." */
2581 CONFLICT (MACC
, MULT
);
2582 CONFLICT (MACC
, DMULT
);
2583 CONFLICT (DMACC
, MULT
);
2584 CONFLICT (DMACC
, DMULT
);
2586 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2587 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2588 DDIV or DDIVU instruction, the result of the MACC or
2589 DMACC instruction is incorrect.". */
2590 CONFLICT (DMULT
, MACC
);
2591 CONFLICT (DMULT
, DMACC
);
2592 CONFLICT (DIV
, MACC
);
2593 CONFLICT (DIV
, DMACC
);
2603 #define RNUM_MASK 0x00000ff
2604 #define RTYPE_MASK 0x0ffff00
2605 #define RTYPE_NUM 0x0000100
2606 #define RTYPE_FPU 0x0000200
2607 #define RTYPE_FCC 0x0000400
2608 #define RTYPE_VEC 0x0000800
2609 #define RTYPE_GP 0x0001000
2610 #define RTYPE_CP0 0x0002000
2611 #define RTYPE_PC 0x0004000
2612 #define RTYPE_ACC 0x0008000
2613 #define RTYPE_CCC 0x0010000
2614 #define RTYPE_VI 0x0020000
2615 #define RTYPE_VF 0x0040000
2616 #define RTYPE_R5900_I 0x0080000
2617 #define RTYPE_R5900_Q 0x0100000
2618 #define RTYPE_R5900_R 0x0200000
2619 #define RTYPE_R5900_ACC 0x0400000
2620 #define RTYPE_MSA 0x0800000
2621 #define RWARN 0x8000000
2623 #define GENERIC_REGISTER_NUMBERS \
2624 {"$0", RTYPE_NUM | 0}, \
2625 {"$1", RTYPE_NUM | 1}, \
2626 {"$2", RTYPE_NUM | 2}, \
2627 {"$3", RTYPE_NUM | 3}, \
2628 {"$4", RTYPE_NUM | 4}, \
2629 {"$5", RTYPE_NUM | 5}, \
2630 {"$6", RTYPE_NUM | 6}, \
2631 {"$7", RTYPE_NUM | 7}, \
2632 {"$8", RTYPE_NUM | 8}, \
2633 {"$9", RTYPE_NUM | 9}, \
2634 {"$10", RTYPE_NUM | 10}, \
2635 {"$11", RTYPE_NUM | 11}, \
2636 {"$12", RTYPE_NUM | 12}, \
2637 {"$13", RTYPE_NUM | 13}, \
2638 {"$14", RTYPE_NUM | 14}, \
2639 {"$15", RTYPE_NUM | 15}, \
2640 {"$16", RTYPE_NUM | 16}, \
2641 {"$17", RTYPE_NUM | 17}, \
2642 {"$18", RTYPE_NUM | 18}, \
2643 {"$19", RTYPE_NUM | 19}, \
2644 {"$20", RTYPE_NUM | 20}, \
2645 {"$21", RTYPE_NUM | 21}, \
2646 {"$22", RTYPE_NUM | 22}, \
2647 {"$23", RTYPE_NUM | 23}, \
2648 {"$24", RTYPE_NUM | 24}, \
2649 {"$25", RTYPE_NUM | 25}, \
2650 {"$26", RTYPE_NUM | 26}, \
2651 {"$27", RTYPE_NUM | 27}, \
2652 {"$28", RTYPE_NUM | 28}, \
2653 {"$29", RTYPE_NUM | 29}, \
2654 {"$30", RTYPE_NUM | 30}, \
2655 {"$31", RTYPE_NUM | 31}
2657 #define FPU_REGISTER_NAMES \
2658 {"$f0", RTYPE_FPU | 0}, \
2659 {"$f1", RTYPE_FPU | 1}, \
2660 {"$f2", RTYPE_FPU | 2}, \
2661 {"$f3", RTYPE_FPU | 3}, \
2662 {"$f4", RTYPE_FPU | 4}, \
2663 {"$f5", RTYPE_FPU | 5}, \
2664 {"$f6", RTYPE_FPU | 6}, \
2665 {"$f7", RTYPE_FPU | 7}, \
2666 {"$f8", RTYPE_FPU | 8}, \
2667 {"$f9", RTYPE_FPU | 9}, \
2668 {"$f10", RTYPE_FPU | 10}, \
2669 {"$f11", RTYPE_FPU | 11}, \
2670 {"$f12", RTYPE_FPU | 12}, \
2671 {"$f13", RTYPE_FPU | 13}, \
2672 {"$f14", RTYPE_FPU | 14}, \
2673 {"$f15", RTYPE_FPU | 15}, \
2674 {"$f16", RTYPE_FPU | 16}, \
2675 {"$f17", RTYPE_FPU | 17}, \
2676 {"$f18", RTYPE_FPU | 18}, \
2677 {"$f19", RTYPE_FPU | 19}, \
2678 {"$f20", RTYPE_FPU | 20}, \
2679 {"$f21", RTYPE_FPU | 21}, \
2680 {"$f22", RTYPE_FPU | 22}, \
2681 {"$f23", RTYPE_FPU | 23}, \
2682 {"$f24", RTYPE_FPU | 24}, \
2683 {"$f25", RTYPE_FPU | 25}, \
2684 {"$f26", RTYPE_FPU | 26}, \
2685 {"$f27", RTYPE_FPU | 27}, \
2686 {"$f28", RTYPE_FPU | 28}, \
2687 {"$f29", RTYPE_FPU | 29}, \
2688 {"$f30", RTYPE_FPU | 30}, \
2689 {"$f31", RTYPE_FPU | 31}
2691 #define FPU_CONDITION_CODE_NAMES \
2692 {"$fcc0", RTYPE_FCC | 0}, \
2693 {"$fcc1", RTYPE_FCC | 1}, \
2694 {"$fcc2", RTYPE_FCC | 2}, \
2695 {"$fcc3", RTYPE_FCC | 3}, \
2696 {"$fcc4", RTYPE_FCC | 4}, \
2697 {"$fcc5", RTYPE_FCC | 5}, \
2698 {"$fcc6", RTYPE_FCC | 6}, \
2699 {"$fcc7", RTYPE_FCC | 7}
2701 #define COPROC_CONDITION_CODE_NAMES \
2702 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2703 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2704 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2705 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2706 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2707 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2708 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2709 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2711 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2712 {"$a4", RTYPE_GP | 8}, \
2713 {"$a5", RTYPE_GP | 9}, \
2714 {"$a6", RTYPE_GP | 10}, \
2715 {"$a7", RTYPE_GP | 11}, \
2716 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2717 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2718 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2719 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2720 {"$t0", RTYPE_GP | 12}, \
2721 {"$t1", RTYPE_GP | 13}, \
2722 {"$t2", RTYPE_GP | 14}, \
2723 {"$t3", RTYPE_GP | 15}
2725 #define O32_SYMBOLIC_REGISTER_NAMES \
2726 {"$t0", RTYPE_GP | 8}, \
2727 {"$t1", RTYPE_GP | 9}, \
2728 {"$t2", RTYPE_GP | 10}, \
2729 {"$t3", RTYPE_GP | 11}, \
2730 {"$t4", RTYPE_GP | 12}, \
2731 {"$t5", RTYPE_GP | 13}, \
2732 {"$t6", RTYPE_GP | 14}, \
2733 {"$t7", RTYPE_GP | 15}, \
2734 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2735 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2736 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2737 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2739 /* Remaining symbolic register names */
2740 #define SYMBOLIC_REGISTER_NAMES \
2741 {"$zero", RTYPE_GP | 0}, \
2742 {"$at", RTYPE_GP | 1}, \
2743 {"$AT", RTYPE_GP | 1}, \
2744 {"$v0", RTYPE_GP | 2}, \
2745 {"$v1", RTYPE_GP | 3}, \
2746 {"$a0", RTYPE_GP | 4}, \
2747 {"$a1", RTYPE_GP | 5}, \
2748 {"$a2", RTYPE_GP | 6}, \
2749 {"$a3", RTYPE_GP | 7}, \
2750 {"$s0", RTYPE_GP | 16}, \
2751 {"$s1", RTYPE_GP | 17}, \
2752 {"$s2", RTYPE_GP | 18}, \
2753 {"$s3", RTYPE_GP | 19}, \
2754 {"$s4", RTYPE_GP | 20}, \
2755 {"$s5", RTYPE_GP | 21}, \
2756 {"$s6", RTYPE_GP | 22}, \
2757 {"$s7", RTYPE_GP | 23}, \
2758 {"$t8", RTYPE_GP | 24}, \
2759 {"$t9", RTYPE_GP | 25}, \
2760 {"$k0", RTYPE_GP | 26}, \
2761 {"$kt0", RTYPE_GP | 26}, \
2762 {"$k1", RTYPE_GP | 27}, \
2763 {"$kt1", RTYPE_GP | 27}, \
2764 {"$gp", RTYPE_GP | 28}, \
2765 {"$sp", RTYPE_GP | 29}, \
2766 {"$s8", RTYPE_GP | 30}, \
2767 {"$fp", RTYPE_GP | 30}, \
2768 {"$ra", RTYPE_GP | 31}
2770 #define MIPS16_SPECIAL_REGISTER_NAMES \
2771 {"$pc", RTYPE_PC | 0}
2773 #define MDMX_VECTOR_REGISTER_NAMES \
2774 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2775 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2776 {"$v2", RTYPE_VEC | 2}, \
2777 {"$v3", RTYPE_VEC | 3}, \
2778 {"$v4", RTYPE_VEC | 4}, \
2779 {"$v5", RTYPE_VEC | 5}, \
2780 {"$v6", RTYPE_VEC | 6}, \
2781 {"$v7", RTYPE_VEC | 7}, \
2782 {"$v8", RTYPE_VEC | 8}, \
2783 {"$v9", RTYPE_VEC | 9}, \
2784 {"$v10", RTYPE_VEC | 10}, \
2785 {"$v11", RTYPE_VEC | 11}, \
2786 {"$v12", RTYPE_VEC | 12}, \
2787 {"$v13", RTYPE_VEC | 13}, \
2788 {"$v14", RTYPE_VEC | 14}, \
2789 {"$v15", RTYPE_VEC | 15}, \
2790 {"$v16", RTYPE_VEC | 16}, \
2791 {"$v17", RTYPE_VEC | 17}, \
2792 {"$v18", RTYPE_VEC | 18}, \
2793 {"$v19", RTYPE_VEC | 19}, \
2794 {"$v20", RTYPE_VEC | 20}, \
2795 {"$v21", RTYPE_VEC | 21}, \
2796 {"$v22", RTYPE_VEC | 22}, \
2797 {"$v23", RTYPE_VEC | 23}, \
2798 {"$v24", RTYPE_VEC | 24}, \
2799 {"$v25", RTYPE_VEC | 25}, \
2800 {"$v26", RTYPE_VEC | 26}, \
2801 {"$v27", RTYPE_VEC | 27}, \
2802 {"$v28", RTYPE_VEC | 28}, \
2803 {"$v29", RTYPE_VEC | 29}, \
2804 {"$v30", RTYPE_VEC | 30}, \
2805 {"$v31", RTYPE_VEC | 31}
2807 #define R5900_I_NAMES \
2808 {"$I", RTYPE_R5900_I | 0}
2810 #define R5900_Q_NAMES \
2811 {"$Q", RTYPE_R5900_Q | 0}
2813 #define R5900_R_NAMES \
2814 {"$R", RTYPE_R5900_R | 0}
2816 #define R5900_ACC_NAMES \
2817 {"$ACC", RTYPE_R5900_ACC | 0 }
2819 #define MIPS_DSP_ACCUMULATOR_NAMES \
2820 {"$ac0", RTYPE_ACC | 0}, \
2821 {"$ac1", RTYPE_ACC | 1}, \
2822 {"$ac2", RTYPE_ACC | 2}, \
2823 {"$ac3", RTYPE_ACC | 3}
2825 static const struct regname reg_names
[] = {
2826 GENERIC_REGISTER_NUMBERS
,
2828 FPU_CONDITION_CODE_NAMES
,
2829 COPROC_CONDITION_CODE_NAMES
,
2831 /* The $txx registers depends on the abi,
2832 these will be added later into the symbol table from
2833 one of the tables below once mips_abi is set after
2834 parsing of arguments from the command line. */
2835 SYMBOLIC_REGISTER_NAMES
,
2837 MIPS16_SPECIAL_REGISTER_NAMES
,
2838 MDMX_VECTOR_REGISTER_NAMES
,
2843 MIPS_DSP_ACCUMULATOR_NAMES
,
2847 static const struct regname reg_names_o32
[] = {
2848 O32_SYMBOLIC_REGISTER_NAMES
,
2852 static const struct regname reg_names_n32n64
[] = {
2853 N32N64_SYMBOLIC_REGISTER_NAMES
,
2857 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2858 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2859 of these register symbols, return the associated vector register,
2860 otherwise return SYMVAL itself. */
2863 mips_prefer_vec_regno (unsigned int symval
)
2865 if ((symval
& -2) == (RTYPE_GP
| 2))
2866 return RTYPE_VEC
| (symval
& 1);
2870 /* Return true if string [S, E) is a valid register name, storing its
2871 symbol value in *SYMVAL_PTR if so. */
2874 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2879 /* Terminate name. */
2883 /* Look up the name. */
2884 symbol
= symbol_find (s
);
2887 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2890 *symval_ptr
= S_GET_VALUE (symbol
);
2894 /* Return true if the string at *SPTR is a valid register name. Allow it
2895 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2898 When returning true, move *SPTR past the register, store the
2899 register's symbol value in *SYMVAL_PTR and the channel mask in
2900 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2901 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2902 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2905 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2906 unsigned int *channels_ptr
)
2910 unsigned int channels
, symval
, bit
;
2912 /* Find end of name. */
2914 if (is_name_beginner (*e
))
2916 while (is_part_of_name (*e
))
2920 if (!mips_parse_register_1 (s
, e
, &symval
))
2925 /* Eat characters from the end of the string that are valid
2926 channel suffixes. The preceding register must be $ACC or
2927 end with a digit, so there is no ambiguity. */
2930 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2931 if (m
> s
&& m
[-1] == *q
)
2938 || !mips_parse_register_1 (s
, m
, &symval
)
2939 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2944 *symval_ptr
= symval
;
2946 *channels_ptr
= channels
;
2950 /* Check if SPTR points at a valid register specifier according to TYPES.
2951 If so, then return 1, advance S to consume the specifier and store
2952 the register's number in REGNOP, otherwise return 0. */
2955 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2959 if (mips_parse_register (s
, ®no
, NULL
))
2961 if (types
& RTYPE_VEC
)
2962 regno
= mips_prefer_vec_regno (regno
);
2971 as_warn (_("unrecognized register name `%s'"), *s
);
2976 return regno
<= RNUM_MASK
;
2979 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2980 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2983 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2988 for (i
= 0; i
< 4; i
++)
2989 if (*s
== "xyzw"[i
])
2991 *channels
|= 1 << (3 - i
);
2997 /* Token types for parsed operand lists. */
2998 enum mips_operand_token_type
{
2999 /* A plain register, e.g. $f2. */
3002 /* A 4-bit XYZW channel mask. */
3005 /* A constant vector index, e.g. [1]. */
3008 /* A register vector index, e.g. [$2]. */
3011 /* A continuous range of registers, e.g. $s0-$s4. */
3014 /* A (possibly relocated) expression. */
3017 /* A floating-point value. */
3020 /* A single character. This can be '(', ')' or ',', but '(' only appears
3024 /* A doubled character, either "--" or "++". */
3027 /* The end of the operand list. */
3031 /* A parsed operand token. */
3032 struct mips_operand_token
3034 /* The type of token. */
3035 enum mips_operand_token_type type
;
3038 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3041 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3042 unsigned int channels
;
3044 /* The integer value of an OT_INTEGER_INDEX. */
3047 /* The two register symbol values involved in an OT_REG_RANGE. */
3049 unsigned int regno1
;
3050 unsigned int regno2
;
3053 /* The value of an OT_INTEGER. The value is represented as an
3054 expression and the relocation operators that were applied to
3055 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3056 relocation operators were used. */
3059 bfd_reloc_code_real_type relocs
[3];
3062 /* The binary data for an OT_FLOAT constant, and the number of bytes
3065 unsigned char data
[8];
3069 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3074 /* An obstack used to construct lists of mips_operand_tokens. */
3075 static struct obstack mips_operand_tokens
;
3077 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3080 mips_add_token (struct mips_operand_token
*token
,
3081 enum mips_operand_token_type type
)
3084 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3087 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3088 and OT_REG tokens for them if so, and return a pointer to the first
3089 unconsumed character. Return null otherwise. */
3092 mips_parse_base_start (char *s
)
3094 struct mips_operand_token token
;
3095 unsigned int regno
, channels
;
3096 bfd_boolean decrement_p
;
3102 SKIP_SPACE_TABS (s
);
3104 /* Only match "--" as part of a base expression. In other contexts "--X"
3105 is a double negative. */
3106 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3110 SKIP_SPACE_TABS (s
);
3113 /* Allow a channel specifier because that leads to better error messages
3114 than treating something like "$vf0x++" as an expression. */
3115 if (!mips_parse_register (&s
, ®no
, &channels
))
3119 mips_add_token (&token
, OT_CHAR
);
3124 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3127 token
.u
.regno
= regno
;
3128 mips_add_token (&token
, OT_REG
);
3132 token
.u
.channels
= channels
;
3133 mips_add_token (&token
, OT_CHANNELS
);
3136 /* For consistency, only match "++" as part of base expressions too. */
3137 SKIP_SPACE_TABS (s
);
3138 if (s
[0] == '+' && s
[1] == '+')
3142 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3148 /* Parse one or more tokens from S. Return a pointer to the first
3149 unconsumed character on success. Return null if an error was found
3150 and store the error text in insn_error. FLOAT_FORMAT is as for
3151 mips_parse_arguments. */
3154 mips_parse_argument_token (char *s
, char float_format
)
3156 char *end
, *save_in
;
3158 unsigned int regno1
, regno2
, channels
;
3159 struct mips_operand_token token
;
3161 /* First look for "($reg", since we want to treat that as an
3162 OT_CHAR and OT_REG rather than an expression. */
3163 end
= mips_parse_base_start (s
);
3167 /* Handle other characters that end up as OT_CHARs. */
3168 if (*s
== ')' || *s
== ',')
3171 mips_add_token (&token
, OT_CHAR
);
3176 /* Handle tokens that start with a register. */
3177 if (mips_parse_register (&s
, ®no1
, &channels
))
3181 /* A register and a VU0 channel suffix. */
3182 token
.u
.regno
= regno1
;
3183 mips_add_token (&token
, OT_REG
);
3185 token
.u
.channels
= channels
;
3186 mips_add_token (&token
, OT_CHANNELS
);
3190 SKIP_SPACE_TABS (s
);
3193 /* A register range. */
3195 SKIP_SPACE_TABS (s
);
3196 if (!mips_parse_register (&s
, ®no2
, NULL
))
3198 set_insn_error (0, _("invalid register range"));
3202 token
.u
.reg_range
.regno1
= regno1
;
3203 token
.u
.reg_range
.regno2
= regno2
;
3204 mips_add_token (&token
, OT_REG_RANGE
);
3208 /* Add the register itself. */
3209 token
.u
.regno
= regno1
;
3210 mips_add_token (&token
, OT_REG
);
3212 /* Check for a vector index. */
3216 SKIP_SPACE_TABS (s
);
3217 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3218 mips_add_token (&token
, OT_REG_INDEX
);
3221 expressionS element
;
3223 my_getExpression (&element
, s
);
3224 if (element
.X_op
!= O_constant
)
3226 set_insn_error (0, _("vector element must be constant"));
3230 token
.u
.index
= element
.X_add_number
;
3231 mips_add_token (&token
, OT_INTEGER_INDEX
);
3233 SKIP_SPACE_TABS (s
);
3236 set_insn_error (0, _("missing `]'"));
3246 /* First try to treat expressions as floats. */
3247 save_in
= input_line_pointer
;
3248 input_line_pointer
= s
;
3249 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3250 &token
.u
.flt
.length
);
3251 end
= input_line_pointer
;
3252 input_line_pointer
= save_in
;
3255 set_insn_error (0, err
);
3260 mips_add_token (&token
, OT_FLOAT
);
3265 /* Treat everything else as an integer expression. */
3266 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3267 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3268 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3269 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3271 mips_add_token (&token
, OT_INTEGER
);
3275 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3276 if expressions should be treated as 32-bit floating-point constants,
3277 'd' if they should be treated as 64-bit floating-point constants,
3278 or 0 if they should be treated as integer expressions (the usual case).
3280 Return a list of tokens on success, otherwise return 0. The caller
3281 must obstack_free the list after use. */
3283 static struct mips_operand_token
*
3284 mips_parse_arguments (char *s
, char float_format
)
3286 struct mips_operand_token token
;
3288 SKIP_SPACE_TABS (s
);
3291 s
= mips_parse_argument_token (s
, float_format
);
3294 obstack_free (&mips_operand_tokens
,
3295 obstack_finish (&mips_operand_tokens
));
3298 SKIP_SPACE_TABS (s
);
3300 mips_add_token (&token
, OT_END
);
3301 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3304 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3305 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3308 is_opcode_valid (const struct mips_opcode
*mo
)
3310 int isa
= mips_opts
.isa
;
3311 int ase
= mips_opts
.ase
;
3315 if (ISA_HAS_64BIT_REGS (isa
))
3316 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3317 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3318 ase
|= mips_ases
[i
].flags64
;
3320 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3323 /* Check whether the instruction or macro requires single-precision or
3324 double-precision floating-point support. Note that this information is
3325 stored differently in the opcode table for insns and macros. */
3326 if (mo
->pinfo
== INSN_MACRO
)
3328 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3329 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3333 fp_s
= mo
->pinfo
& FP_S
;
3334 fp_d
= mo
->pinfo
& FP_D
;
3337 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3340 if (fp_s
&& mips_opts
.soft_float
)
3346 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3347 selected ISA and architecture. */
3350 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3352 int isa
= mips_opts
.isa
;
3353 int ase
= mips_opts
.ase
;
3356 if (ISA_HAS_64BIT_REGS (isa
))
3357 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3358 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3359 ase
|= mips_ases
[i
].flags64
;
3361 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3364 /* Return TRUE if the size of the microMIPS opcode MO matches one
3365 explicitly requested. Always TRUE in the standard MIPS mode.
3366 Use is_size_valid_16 for MIPS16 opcodes. */
3369 is_size_valid (const struct mips_opcode
*mo
)
3371 if (!mips_opts
.micromips
)
3374 if (mips_opts
.insn32
)
3376 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3378 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3381 if (!forced_insn_length
)
3383 if (mo
->pinfo
== INSN_MACRO
)
3385 return forced_insn_length
== micromips_insn_length (mo
);
3388 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3389 explicitly requested. */
3392 is_size_valid_16 (const struct mips_opcode
*mo
)
3394 if (!forced_insn_length
)
3396 if (mo
->pinfo
== INSN_MACRO
)
3398 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3400 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3405 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3406 of the preceding instruction. Always TRUE in the standard MIPS mode.
3408 We don't accept macros in 16-bit delay slots to avoid a case where
3409 a macro expansion fails because it relies on a preceding 32-bit real
3410 instruction to have matched and does not handle the operands correctly.
3411 The only macros that may expand to 16-bit instructions are JAL that
3412 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3413 and BGT (that likewise cannot be placed in a delay slot) that decay to
3414 a NOP. In all these cases the macros precede any corresponding real
3415 instruction definitions in the opcode table, so they will match in the
3416 second pass where the size of the delay slot is ignored and therefore
3417 produce correct code. */
3420 is_delay_slot_valid (const struct mips_opcode
*mo
)
3422 if (!mips_opts
.micromips
)
3425 if (mo
->pinfo
== INSN_MACRO
)
3426 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3427 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3428 && micromips_insn_length (mo
) != 4)
3430 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3431 && micromips_insn_length (mo
) != 2)
3437 /* For consistency checking, verify that all bits of OPCODE are specified
3438 either by the match/mask part of the instruction definition, or by the
3439 operand list. Also build up a list of operands in OPERANDS.
3441 INSN_BITS says which bits of the instruction are significant.
3442 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3443 provides the mips_operand description of each operand. DECODE_OPERAND
3444 is null for MIPS16 instructions. */
3447 validate_mips_insn (const struct mips_opcode
*opcode
,
3448 unsigned long insn_bits
,
3449 const struct mips_operand
*(*decode_operand
) (const char *),
3450 struct mips_operand_array
*operands
)
3453 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3454 const struct mips_operand
*operand
;
3456 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3457 if ((mask
& opcode
->match
) != opcode
->match
)
3459 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3460 opcode
->name
, opcode
->args
);
3465 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3466 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3467 for (s
= opcode
->args
; *s
; ++s
)
3480 if (!decode_operand
)
3481 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3483 operand
= decode_operand (s
);
3484 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3486 as_bad (_("internal: unknown operand type: %s %s"),
3487 opcode
->name
, opcode
->args
);
3490 gas_assert (opno
< MAX_OPERANDS
);
3491 operands
->operand
[opno
] = operand
;
3492 if (!decode_operand
&& operand
3493 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3494 && mips_opcode_32bit_p (opcode
))
3495 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3496 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3498 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3499 if (operand
->type
== OP_MDMX_IMM_REG
)
3500 /* Bit 5 is the format selector (OB vs QH). The opcode table
3501 has separate entries for each format. */
3502 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3503 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3504 used_bits
&= ~(mask
& 0x700);
3505 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3506 operand field that cannot be fully described with LSB/SIZE. */
3507 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3508 used_bits
&= ~0x6000;
3510 /* Skip prefix characters. */
3511 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3516 doubled
= used_bits
& mask
& insn_bits
;
3519 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3520 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3524 undefined
= ~used_bits
& insn_bits
;
3525 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3527 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3528 undefined
, opcode
->name
, opcode
->args
);
3531 used_bits
&= ~insn_bits
;
3534 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3535 used_bits
, opcode
->name
, opcode
->args
);
3541 /* The MIPS16 version of validate_mips_insn. */
3544 validate_mips16_insn (const struct mips_opcode
*opcode
,
3545 struct mips_operand_array
*operands
)
3547 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3549 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3552 /* The microMIPS version of validate_mips_insn. */
3555 validate_micromips_insn (const struct mips_opcode
*opc
,
3556 struct mips_operand_array
*operands
)
3558 unsigned long insn_bits
;
3559 unsigned long major
;
3560 unsigned int length
;
3562 if (opc
->pinfo
== INSN_MACRO
)
3563 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3566 length
= micromips_insn_length (opc
);
3567 if (length
!= 2 && length
!= 4)
3569 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3570 "%s %s"), length
, opc
->name
, opc
->args
);
3573 major
= opc
->match
>> (10 + 8 * (length
- 2));
3574 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3575 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3577 as_bad (_("internal error: bad microMIPS opcode "
3578 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3582 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3583 insn_bits
= 1 << 4 * length
;
3584 insn_bits
<<= 4 * length
;
3586 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3590 /* This function is called once, at assembler startup time. It should set up
3591 all the tables, etc. that the MD part of the assembler will need. */
3596 const char *retval
= NULL
;
3600 if (mips_pic
!= NO_PIC
)
3602 if (g_switch_seen
&& g_switch_value
!= 0)
3603 as_bad (_("-G may not be used in position-independent code"));
3606 else if (mips_abicalls
)
3608 if (g_switch_seen
&& g_switch_value
!= 0)
3609 as_bad (_("-G may not be used with abicalls"));
3613 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3614 as_warn (_("could not set architecture and machine"));
3616 op_hash
= hash_new ();
3618 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3619 for (i
= 0; i
< NUMOPCODES
;)
3621 const char *name
= mips_opcodes
[i
].name
;
3623 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3626 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3627 mips_opcodes
[i
].name
, retval
);
3628 /* Probably a memory allocation problem? Give up now. */
3629 as_fatal (_("broken assembler, no assembly attempted"));
3633 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3634 decode_mips_operand
, &mips_operands
[i
]))
3636 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3638 create_insn (&nop_insn
, mips_opcodes
+ i
);
3639 if (mips_fix_loongson2f_nop
)
3640 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3641 nop_insn
.fixed_p
= 1;
3645 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3648 mips16_op_hash
= hash_new ();
3649 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3650 bfd_mips16_num_opcodes
);
3653 while (i
< bfd_mips16_num_opcodes
)
3655 const char *name
= mips16_opcodes
[i
].name
;
3657 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3659 as_fatal (_("internal: can't hash `%s': %s"),
3660 mips16_opcodes
[i
].name
, retval
);
3663 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3665 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3667 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3668 mips16_nop_insn
.fixed_p
= 1;
3672 while (i
< bfd_mips16_num_opcodes
3673 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3676 micromips_op_hash
= hash_new ();
3677 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3678 bfd_micromips_num_opcodes
);
3681 while (i
< bfd_micromips_num_opcodes
)
3683 const char *name
= micromips_opcodes
[i
].name
;
3685 retval
= hash_insert (micromips_op_hash
, name
,
3686 (void *) µmips_opcodes
[i
]);
3688 as_fatal (_("internal: can't hash `%s': %s"),
3689 micromips_opcodes
[i
].name
, retval
);
3692 struct mips_cl_insn
*micromips_nop_insn
;
3694 if (!validate_micromips_insn (µmips_opcodes
[i
],
3695 µmips_operands
[i
]))
3698 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3700 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3701 micromips_nop_insn
= µmips_nop16_insn
;
3702 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3703 micromips_nop_insn
= µmips_nop32_insn
;
3707 if (micromips_nop_insn
->insn_mo
== NULL
3708 && strcmp (name
, "nop") == 0)
3710 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3711 micromips_nop_insn
->fixed_p
= 1;
3715 while (++i
< bfd_micromips_num_opcodes
3716 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3720 as_fatal (_("broken assembler, no assembly attempted"));
3722 /* We add all the general register names to the symbol table. This
3723 helps us detect invalid uses of them. */
3724 for (i
= 0; reg_names
[i
].name
; i
++)
3725 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3726 reg_names
[i
].num
, /* & RNUM_MASK, */
3727 &zero_address_frag
));
3729 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3730 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3731 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3732 &zero_address_frag
));
3734 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3735 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3736 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3737 &zero_address_frag
));
3739 for (i
= 0; i
< 32; i
++)
3743 /* R5900 VU0 floating-point register. */
3744 sprintf (regname
, "$vf%d", i
);
3745 symbol_table_insert (symbol_new (regname
, reg_section
,
3746 RTYPE_VF
| i
, &zero_address_frag
));
3748 /* R5900 VU0 integer register. */
3749 sprintf (regname
, "$vi%d", i
);
3750 symbol_table_insert (symbol_new (regname
, reg_section
,
3751 RTYPE_VI
| i
, &zero_address_frag
));
3754 sprintf (regname
, "$w%d", i
);
3755 symbol_table_insert (symbol_new (regname
, reg_section
,
3756 RTYPE_MSA
| i
, &zero_address_frag
));
3759 obstack_init (&mips_operand_tokens
);
3761 mips_no_prev_insn ();
3764 mips_cprmask
[0] = 0;
3765 mips_cprmask
[1] = 0;
3766 mips_cprmask
[2] = 0;
3767 mips_cprmask
[3] = 0;
3769 /* set the default alignment for the text section (2**2) */
3770 record_alignment (text_section
, 2);
3772 bfd_set_gp_size (stdoutput
, g_switch_value
);
3774 /* On a native system other than VxWorks, sections must be aligned
3775 to 16 byte boundaries. When configured for an embedded ELF
3776 target, we don't bother. */
3777 if (strncmp (TARGET_OS
, "elf", 3) != 0
3778 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3780 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3781 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3782 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3785 /* Create a .reginfo section for register masks and a .mdebug
3786 section for debugging information. */
3794 subseg
= now_subseg
;
3796 /* The ABI says this section should be loaded so that the
3797 running program can access it. However, we don't load it
3798 if we are configured for an embedded target */
3799 flags
= SEC_READONLY
| SEC_DATA
;
3800 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3801 flags
|= SEC_ALLOC
| SEC_LOAD
;
3803 if (mips_abi
!= N64_ABI
)
3805 sec
= subseg_new (".reginfo", (subsegT
) 0);
3807 bfd_set_section_flags (stdoutput
, sec
, flags
);
3808 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3810 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3814 /* The 64-bit ABI uses a .MIPS.options section rather than
3815 .reginfo section. */
3816 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3817 bfd_set_section_flags (stdoutput
, sec
, flags
);
3818 bfd_set_section_alignment (stdoutput
, sec
, 3);
3820 /* Set up the option header. */
3822 Elf_Internal_Options opthdr
;
3825 opthdr
.kind
= ODK_REGINFO
;
3826 opthdr
.size
= (sizeof (Elf_External_Options
)
3827 + sizeof (Elf64_External_RegInfo
));
3830 f
= frag_more (sizeof (Elf_External_Options
));
3831 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3832 (Elf_External_Options
*) f
);
3834 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3838 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3839 bfd_set_section_flags (stdoutput
, sec
,
3840 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3841 bfd_set_section_alignment (stdoutput
, sec
, 3);
3842 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3844 if (ECOFF_DEBUGGING
)
3846 sec
= subseg_new (".mdebug", (subsegT
) 0);
3847 (void) bfd_set_section_flags (stdoutput
, sec
,
3848 SEC_HAS_CONTENTS
| SEC_READONLY
);
3849 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3851 else if (mips_flag_pdr
)
3853 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3854 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3855 SEC_READONLY
| SEC_RELOC
3857 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3860 subseg_set (seg
, subseg
);
3863 if (mips_fix_vr4120
)
3864 init_vr4120_conflicts ();
3868 fpabi_incompatible_with (int fpabi
, const char *what
)
3870 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3871 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3875 fpabi_requires (int fpabi
, const char *what
)
3877 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3878 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3881 /* Check -mabi and register sizes against the specified FP ABI. */
3883 check_fpabi (int fpabi
)
3887 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3888 if (file_mips_opts
.soft_float
)
3889 fpabi_incompatible_with (fpabi
, "softfloat");
3890 else if (file_mips_opts
.single_float
)
3891 fpabi_incompatible_with (fpabi
, "singlefloat");
3892 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3893 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3894 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3895 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3898 case Val_GNU_MIPS_ABI_FP_XX
:
3899 if (mips_abi
!= O32_ABI
)
3900 fpabi_requires (fpabi
, "-mabi=32");
3901 else if (file_mips_opts
.soft_float
)
3902 fpabi_incompatible_with (fpabi
, "softfloat");
3903 else if (file_mips_opts
.single_float
)
3904 fpabi_incompatible_with (fpabi
, "singlefloat");
3905 else if (file_mips_opts
.fp
!= 0)
3906 fpabi_requires (fpabi
, "fp=xx");
3909 case Val_GNU_MIPS_ABI_FP_64A
:
3910 case Val_GNU_MIPS_ABI_FP_64
:
3911 if (mips_abi
!= O32_ABI
)
3912 fpabi_requires (fpabi
, "-mabi=32");
3913 else if (file_mips_opts
.soft_float
)
3914 fpabi_incompatible_with (fpabi
, "softfloat");
3915 else if (file_mips_opts
.single_float
)
3916 fpabi_incompatible_with (fpabi
, "singlefloat");
3917 else if (file_mips_opts
.fp
!= 64)
3918 fpabi_requires (fpabi
, "fp=64");
3919 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3920 fpabi_incompatible_with (fpabi
, "nooddspreg");
3921 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3922 fpabi_requires (fpabi
, "nooddspreg");
3925 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3926 if (file_mips_opts
.soft_float
)
3927 fpabi_incompatible_with (fpabi
, "softfloat");
3928 else if (!file_mips_opts
.single_float
)
3929 fpabi_requires (fpabi
, "singlefloat");
3932 case Val_GNU_MIPS_ABI_FP_SOFT
:
3933 if (!file_mips_opts
.soft_float
)
3934 fpabi_requires (fpabi
, "softfloat");
3937 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3938 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3939 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3942 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3943 /* Silently ignore compatibility value. */
3947 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3948 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3953 /* Perform consistency checks on the current options. */
3956 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3958 /* Check the size of integer registers agrees with the ABI and ISA. */
3959 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3960 as_bad (_("`gp=64' used with a 32-bit processor"));
3962 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3963 as_bad (_("`gp=32' used with a 64-bit ABI"));
3965 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3966 as_bad (_("`gp=64' used with a 32-bit ABI"));
3968 /* Check the size of the float registers agrees with the ABI and ISA. */
3972 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3973 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3974 else if (opts
->single_float
== 1)
3975 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3978 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3979 as_bad (_("`fp=64' used with a 32-bit fpu"));
3981 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3982 && !ISA_HAS_MXHC1 (opts
->isa
))
3983 as_warn (_("`fp=64' used with a 32-bit ABI"));
3987 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3988 as_warn (_("`fp=32' used with a 64-bit ABI"));
3989 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
3990 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3993 as_bad (_("Unknown size of floating point registers"));
3997 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3998 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4000 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4001 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4002 else if (ISA_IS_R6 (opts
->isa
)
4003 && (opts
->micromips
== 1
4004 || opts
->mips16
== 1))
4005 as_fatal (_("`%s' cannot be used with `%s'"),
4006 opts
->micromips
? "micromips" : "mips16",
4007 mips_cpu_info_from_isa (opts
->isa
)->name
);
4009 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4010 as_fatal (_("branch relaxation is not supported in `%s'"),
4011 mips_cpu_info_from_isa (opts
->isa
)->name
);
4014 /* Perform consistency checks on the module level options exactly once.
4015 This is a deferred check that happens:
4016 at the first .set directive
4017 or, at the first pseudo op that generates code (inc .dc.a)
4018 or, at the first instruction
4022 file_mips_check_options (void)
4024 const struct mips_cpu_info
*arch_info
= 0;
4026 if (file_mips_opts_checked
)
4029 /* The following code determines the register size.
4030 Similar code was added to GCC 3.3 (see override_options() in
4031 config/mips/mips.c). The GAS and GCC code should be kept in sync
4032 as much as possible. */
4034 if (file_mips_opts
.gp
< 0)
4036 /* Infer the integer register size from the ABI and processor.
4037 Restrict ourselves to 32-bit registers if that's all the
4038 processor has, or if the ABI cannot handle 64-bit registers. */
4039 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4040 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4044 if (file_mips_opts
.fp
< 0)
4046 /* No user specified float register size.
4047 ??? GAS treats single-float processors as though they had 64-bit
4048 float registers (although it complains when double-precision
4049 instructions are used). As things stand, saying they have 32-bit
4050 registers would lead to spurious "register must be even" messages.
4051 So here we assume float registers are never smaller than the
4053 if (file_mips_opts
.gp
== 64)
4054 /* 64-bit integer registers implies 64-bit float registers. */
4055 file_mips_opts
.fp
= 64;
4056 else if ((file_mips_opts
.ase
& FP64_ASES
)
4057 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4058 /* Handle ASEs that require 64-bit float registers, if possible. */
4059 file_mips_opts
.fp
= 64;
4060 else if (ISA_IS_R6 (mips_opts
.isa
))
4061 /* R6 implies 64-bit float registers. */
4062 file_mips_opts
.fp
= 64;
4064 /* 32-bit float registers. */
4065 file_mips_opts
.fp
= 32;
4068 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
4070 /* Disable operations on odd-numbered floating-point registers by default
4071 when using the FPXX ABI. */
4072 if (file_mips_opts
.oddspreg
< 0)
4074 if (file_mips_opts
.fp
== 0)
4075 file_mips_opts
.oddspreg
= 0;
4077 file_mips_opts
.oddspreg
= 1;
4080 /* End of GCC-shared inference code. */
4082 /* This flag is set when we have a 64-bit capable CPU but use only
4083 32-bit wide registers. Note that EABI does not use it. */
4084 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4085 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4086 || mips_abi
== O32_ABI
))
4089 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4090 as_bad (_("trap exception not supported at ISA 1"));
4092 /* If the selected architecture includes support for ASEs, enable
4093 generation of code for them. */
4094 if (file_mips_opts
.mips16
== -1)
4095 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4096 if (file_mips_opts
.micromips
== -1)
4097 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4100 if (mips_nan2008
== -1)
4101 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4102 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4103 as_fatal (_("`%s' does not support legacy NaN"),
4104 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4106 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4107 being selected implicitly. */
4108 if (file_mips_opts
.fp
!= 64)
4109 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4111 /* If the user didn't explicitly select or deselect a particular ASE,
4112 use the default setting for the CPU. */
4113 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4115 /* Set up the current options. These may change throughout assembly. */
4116 mips_opts
= file_mips_opts
;
4118 mips_check_isa_supports_ases ();
4119 mips_check_options (&file_mips_opts
, TRUE
);
4120 file_mips_opts_checked
= TRUE
;
4122 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4123 as_warn (_("could not set architecture and machine"));
4127 md_assemble (char *str
)
4129 struct mips_cl_insn insn
;
4130 bfd_reloc_code_real_type unused_reloc
[3]
4131 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4133 file_mips_check_options ();
4135 imm_expr
.X_op
= O_absent
;
4136 offset_expr
.X_op
= O_absent
;
4137 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4138 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4139 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4141 mips_mark_labels ();
4142 mips_assembling_insn
= TRUE
;
4143 clear_insn_error ();
4145 if (mips_opts
.mips16
)
4146 mips16_ip (str
, &insn
);
4149 mips_ip (str
, &insn
);
4150 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4151 str
, insn
.insn_opcode
));
4155 report_insn_error (str
);
4156 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4159 if (mips_opts
.mips16
)
4160 mips16_macro (&insn
);
4167 if (offset_expr
.X_op
!= O_absent
)
4168 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4170 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4173 mips_assembling_insn
= FALSE
;
4176 /* Convenience functions for abstracting away the differences between
4177 MIPS16 and non-MIPS16 relocations. */
4179 static inline bfd_boolean
4180 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4184 case BFD_RELOC_MIPS16_JMP
:
4185 case BFD_RELOC_MIPS16_GPREL
:
4186 case BFD_RELOC_MIPS16_GOT16
:
4187 case BFD_RELOC_MIPS16_CALL16
:
4188 case BFD_RELOC_MIPS16_HI16_S
:
4189 case BFD_RELOC_MIPS16_HI16
:
4190 case BFD_RELOC_MIPS16_LO16
:
4191 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4199 static inline bfd_boolean
4200 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4204 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4205 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4206 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4207 case BFD_RELOC_MICROMIPS_GPREL16
:
4208 case BFD_RELOC_MICROMIPS_JMP
:
4209 case BFD_RELOC_MICROMIPS_HI16
:
4210 case BFD_RELOC_MICROMIPS_HI16_S
:
4211 case BFD_RELOC_MICROMIPS_LO16
:
4212 case BFD_RELOC_MICROMIPS_LITERAL
:
4213 case BFD_RELOC_MICROMIPS_GOT16
:
4214 case BFD_RELOC_MICROMIPS_CALL16
:
4215 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4216 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4217 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4218 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4219 case BFD_RELOC_MICROMIPS_SUB
:
4220 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4221 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4222 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4223 case BFD_RELOC_MICROMIPS_HIGHEST
:
4224 case BFD_RELOC_MICROMIPS_HIGHER
:
4225 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4226 case BFD_RELOC_MICROMIPS_JALR
:
4234 static inline bfd_boolean
4235 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4237 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4240 static inline bfd_boolean
4241 b_reloc_p (bfd_reloc_code_real_type reloc
)
4243 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4244 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4245 || reloc
== BFD_RELOC_16_PCREL_S2
4246 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4247 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4248 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4249 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4252 static inline bfd_boolean
4253 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4255 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4256 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4259 static inline bfd_boolean
4260 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4262 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4263 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4266 static inline bfd_boolean
4267 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4269 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4270 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4273 static inline bfd_boolean
4274 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4276 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4279 static inline bfd_boolean
4280 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4282 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4283 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4286 /* Return true if RELOC is a PC-relative relocation that does not have
4287 full address range. */
4289 static inline bfd_boolean
4290 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4294 case BFD_RELOC_16_PCREL_S2
:
4295 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4296 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4297 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4298 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4299 case BFD_RELOC_MIPS_21_PCREL_S2
:
4300 case BFD_RELOC_MIPS_26_PCREL_S2
:
4301 case BFD_RELOC_MIPS_18_PCREL_S3
:
4302 case BFD_RELOC_MIPS_19_PCREL_S2
:
4305 case BFD_RELOC_32_PCREL
:
4306 case BFD_RELOC_HI16_S_PCREL
:
4307 case BFD_RELOC_LO16_PCREL
:
4308 return HAVE_64BIT_ADDRESSES
;
4315 /* Return true if the given relocation might need a matching %lo().
4316 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4317 need a matching %lo() when applied to local symbols. */
4319 static inline bfd_boolean
4320 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4322 return (HAVE_IN_PLACE_ADDENDS
4323 && (hi16_reloc_p (reloc
)
4324 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4325 all GOT16 relocations evaluate to "G". */
4326 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4329 /* Return the type of %lo() reloc needed by RELOC, given that
4330 reloc_needs_lo_p. */
4332 static inline bfd_reloc_code_real_type
4333 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4335 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4336 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4340 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4343 static inline bfd_boolean
4344 fixup_has_matching_lo_p (fixS
*fixp
)
4346 return (fixp
->fx_next
!= NULL
4347 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4348 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4349 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4352 /* Move all labels in LABELS to the current insertion point. TEXT_P
4353 says whether the labels refer to text or data. */
4356 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4358 struct insn_label_list
*l
;
4361 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4363 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4364 symbol_set_frag (l
->label
, frag_now
);
4365 val
= (valueT
) frag_now_fix ();
4366 /* MIPS16/microMIPS text labels are stored as odd. */
4367 if (text_p
&& HAVE_CODE_COMPRESSION
)
4369 S_SET_VALUE (l
->label
, val
);
4373 /* Move all labels in insn_labels to the current insertion point
4374 and treat them as text labels. */
4377 mips_move_text_labels (void)
4379 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4382 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4385 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4387 bfd_boolean linkonce
= FALSE
;
4388 segT symseg
= S_GET_SEGMENT (sym
);
4390 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4392 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4394 /* The GNU toolchain uses an extension for ELF: a section
4395 beginning with the magic string .gnu.linkonce is a
4396 linkonce section. */
4397 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4398 sizeof ".gnu.linkonce" - 1) == 0)
4404 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4405 linker to handle them specially, such as generating jalx instructions
4406 when needed. We also make them odd for the duration of the assembly,
4407 in order to generate the right sort of code. We will make them even
4408 in the adjust_symtab routine, while leaving them marked. This is
4409 convenient for the debugger and the disassembler. The linker knows
4410 to make them odd again. */
4413 mips_compressed_mark_label (symbolS
*label
)
4415 gas_assert (HAVE_CODE_COMPRESSION
);
4417 if (mips_opts
.mips16
)
4418 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4420 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4421 if ((S_GET_VALUE (label
) & 1) == 0
4422 /* Don't adjust the address if the label is global or weak, or
4423 in a link-once section, since we'll be emitting symbol reloc
4424 references to it which will be patched up by the linker, and
4425 the final value of the symbol may or may not be MIPS16/microMIPS. */
4426 && !S_IS_WEAK (label
)
4427 && !S_IS_EXTERNAL (label
)
4428 && !s_is_linkonce (label
, now_seg
))
4429 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4432 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4435 mips_compressed_mark_labels (void)
4437 struct insn_label_list
*l
;
4439 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4440 mips_compressed_mark_label (l
->label
);
4443 /* End the current frag. Make it a variant frag and record the
4447 relax_close_frag (void)
4449 mips_macro_warning
.first_frag
= frag_now
;
4450 frag_var (rs_machine_dependent
, 0, 0,
4451 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4452 mips_pic
!= NO_PIC
),
4453 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4455 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4456 mips_relax
.first_fixup
= 0;
4459 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4460 See the comment above RELAX_ENCODE for more details. */
4463 relax_start (symbolS
*symbol
)
4465 gas_assert (mips_relax
.sequence
== 0);
4466 mips_relax
.sequence
= 1;
4467 mips_relax
.symbol
= symbol
;
4470 /* Start generating the second version of a relaxable sequence.
4471 See the comment above RELAX_ENCODE for more details. */
4476 gas_assert (mips_relax
.sequence
== 1);
4477 mips_relax
.sequence
= 2;
4480 /* End the current relaxable sequence. */
4485 gas_assert (mips_relax
.sequence
== 2);
4486 relax_close_frag ();
4487 mips_relax
.sequence
= 0;
4490 /* Return true if IP is a delayed branch or jump. */
4492 static inline bfd_boolean
4493 delayed_branch_p (const struct mips_cl_insn
*ip
)
4495 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4496 | INSN_COND_BRANCH_DELAY
4497 | INSN_COND_BRANCH_LIKELY
)) != 0;
4500 /* Return true if IP is a compact branch or jump. */
4502 static inline bfd_boolean
4503 compact_branch_p (const struct mips_cl_insn
*ip
)
4505 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4506 | INSN2_COND_BRANCH
)) != 0;
4509 /* Return true if IP is an unconditional branch or jump. */
4511 static inline bfd_boolean
4512 uncond_branch_p (const struct mips_cl_insn
*ip
)
4514 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4515 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4518 /* Return true if IP is a branch-likely instruction. */
4520 static inline bfd_boolean
4521 branch_likely_p (const struct mips_cl_insn
*ip
)
4523 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4526 /* Return the type of nop that should be used to fill the delay slot
4527 of delayed branch IP. */
4529 static struct mips_cl_insn
*
4530 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4532 if (mips_opts
.micromips
4533 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4534 return µmips_nop32_insn
;
4538 /* Return a mask that has bit N set if OPCODE reads the register(s)
4542 insn_read_mask (const struct mips_opcode
*opcode
)
4544 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4547 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4551 insn_write_mask (const struct mips_opcode
*opcode
)
4553 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4556 /* Return a mask of the registers specified by operand OPERAND of INSN.
4557 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4561 operand_reg_mask (const struct mips_cl_insn
*insn
,
4562 const struct mips_operand
*operand
,
4563 unsigned int type_mask
)
4565 unsigned int uval
, vsel
;
4567 switch (operand
->type
)
4574 case OP_ADDIUSP_INT
:
4575 case OP_ENTRY_EXIT_LIST
:
4576 case OP_REPEAT_DEST_REG
:
4577 case OP_REPEAT_PREV_REG
:
4580 case OP_VU0_MATCH_SUFFIX
:
4588 case OP_OPTIONAL_REG
:
4590 const struct mips_reg_operand
*reg_op
;
4592 reg_op
= (const struct mips_reg_operand
*) operand
;
4593 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4595 uval
= insn_extract_operand (insn
, operand
);
4596 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4601 const struct mips_reg_pair_operand
*pair_op
;
4603 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4604 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4606 uval
= insn_extract_operand (insn
, operand
);
4607 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4610 case OP_CLO_CLZ_DEST
:
4611 if (!(type_mask
& (1 << OP_REG_GP
)))
4613 uval
= insn_extract_operand (insn
, operand
);
4614 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4617 if (!(type_mask
& (1 << OP_REG_GP
)))
4619 uval
= insn_extract_operand (insn
, operand
);
4620 gas_assert ((uval
& 31) == (uval
>> 5));
4621 return 1 << (uval
& 31);
4624 case OP_NON_ZERO_REG
:
4625 if (!(type_mask
& (1 << OP_REG_GP
)))
4627 uval
= insn_extract_operand (insn
, operand
);
4628 return 1 << (uval
& 31);
4630 case OP_LWM_SWM_LIST
:
4633 case OP_SAVE_RESTORE_LIST
:
4636 case OP_MDMX_IMM_REG
:
4637 if (!(type_mask
& (1 << OP_REG_VEC
)))
4639 uval
= insn_extract_operand (insn
, operand
);
4641 if ((vsel
& 0x18) == 0x18)
4643 return 1 << (uval
& 31);
4646 if (!(type_mask
& (1 << OP_REG_GP
)))
4648 return 1 << insn_extract_operand (insn
, operand
);
4653 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4654 where bit N of OPNO_MASK is set if operand N should be included.
4655 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4659 insn_reg_mask (const struct mips_cl_insn
*insn
,
4660 unsigned int type_mask
, unsigned int opno_mask
)
4662 unsigned int opno
, reg_mask
;
4666 while (opno_mask
!= 0)
4669 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4676 /* Return the mask of core registers that IP reads. */
4679 gpr_read_mask (const struct mips_cl_insn
*ip
)
4681 unsigned long pinfo
, pinfo2
;
4684 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4685 pinfo
= ip
->insn_mo
->pinfo
;
4686 pinfo2
= ip
->insn_mo
->pinfo2
;
4687 if (pinfo
& INSN_UDI
)
4689 /* UDI instructions have traditionally been assumed to read RS
4691 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4692 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4694 if (pinfo
& INSN_READ_GPR_24
)
4696 if (pinfo2
& INSN2_READ_GPR_16
)
4698 if (pinfo2
& INSN2_READ_SP
)
4700 if (pinfo2
& INSN2_READ_GPR_31
)
4702 /* Don't include register 0. */
4706 /* Return the mask of core registers that IP writes. */
4709 gpr_write_mask (const struct mips_cl_insn
*ip
)
4711 unsigned long pinfo
, pinfo2
;
4714 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4715 pinfo
= ip
->insn_mo
->pinfo
;
4716 pinfo2
= ip
->insn_mo
->pinfo2
;
4717 if (pinfo
& INSN_WRITE_GPR_24
)
4719 if (pinfo
& INSN_WRITE_GPR_31
)
4721 if (pinfo
& INSN_UDI
)
4722 /* UDI instructions have traditionally been assumed to write to RD. */
4723 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4724 if (pinfo2
& INSN2_WRITE_SP
)
4726 /* Don't include register 0. */
4730 /* Return the mask of floating-point registers that IP reads. */
4733 fpr_read_mask (const struct mips_cl_insn
*ip
)
4735 unsigned long pinfo
;
4738 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4739 | (1 << OP_REG_MSA
)),
4740 insn_read_mask (ip
->insn_mo
));
4741 pinfo
= ip
->insn_mo
->pinfo
;
4742 /* Conservatively treat all operands to an FP_D instruction are doubles.
4743 (This is overly pessimistic for things like cvt.d.s.) */
4744 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4749 /* Return the mask of floating-point registers that IP writes. */
4752 fpr_write_mask (const struct mips_cl_insn
*ip
)
4754 unsigned long pinfo
;
4757 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4758 | (1 << OP_REG_MSA
)),
4759 insn_write_mask (ip
->insn_mo
));
4760 pinfo
= ip
->insn_mo
->pinfo
;
4761 /* Conservatively treat all operands to an FP_D instruction are doubles.
4762 (This is overly pessimistic for things like cvt.s.d.) */
4763 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4768 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4769 Check whether that is allowed. */
4772 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4774 const char *s
= insn
->name
;
4775 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4777 && mips_opts
.oddspreg
;
4779 if (insn
->pinfo
== INSN_MACRO
)
4780 /* Let a macro pass, we'll catch it later when it is expanded. */
4783 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4784 otherwise it depends on oddspreg. */
4785 if ((insn
->pinfo
& FP_S
)
4786 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4787 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4788 return FPR_SIZE
== 32 || oddspreg
;
4790 /* Allow odd registers for single-precision ops and double-precision if the
4791 floating-point registers are 64-bit wide. */
4792 switch (insn
->pinfo
& (FP_S
| FP_D
))
4798 return FPR_SIZE
== 64;
4803 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4804 s
= strchr (insn
->name
, '.');
4805 if (s
!= NULL
&& opnum
== 2)
4806 s
= strchr (s
+ 1, '.');
4807 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4810 return FPR_SIZE
== 64;
4813 /* Information about an instruction argument that we're trying to match. */
4814 struct mips_arg_info
4816 /* The instruction so far. */
4817 struct mips_cl_insn
*insn
;
4819 /* The first unconsumed operand token. */
4820 struct mips_operand_token
*token
;
4822 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4825 /* The 1-based argument number, for error reporting. This does not
4826 count elided optional registers, etc.. */
4829 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4830 unsigned int last_regno
;
4832 /* If the first operand was an OP_REG, this is the register that it
4833 specified, otherwise it is ILLEGAL_REG. */
4834 unsigned int dest_regno
;
4836 /* The value of the last OP_INT operand. Only used for OP_MSB,
4837 where it gives the lsb position. */
4838 unsigned int last_op_int
;
4840 /* If true, match routines should assume that no later instruction
4841 alternative matches and should therefore be as accommodating as
4842 possible. Match routines should not report errors if something
4843 is only invalid for !LAX_MATCH. */
4844 bfd_boolean lax_match
;
4846 /* True if a reference to the current AT register was seen. */
4847 bfd_boolean seen_at
;
4850 /* Record that the argument is out of range. */
4853 match_out_of_range (struct mips_arg_info
*arg
)
4855 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4858 /* Record that the argument isn't constant but needs to be. */
4861 match_not_constant (struct mips_arg_info
*arg
)
4863 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4867 /* Try to match an OT_CHAR token for character CH. Consume the token
4868 and return true on success, otherwise return false. */
4871 match_char (struct mips_arg_info
*arg
, char ch
)
4873 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4883 /* Try to get an expression from the next tokens in ARG. Consume the
4884 tokens and return true on success, storing the expression value in
4885 VALUE and relocation types in R. */
4888 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4889 bfd_reloc_code_real_type
*r
)
4891 /* If the next token is a '(' that was parsed as being part of a base
4892 expression, assume we have an elided offset. The later match will fail
4893 if this turns out to be wrong. */
4894 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4896 value
->X_op
= O_constant
;
4897 value
->X_add_number
= 0;
4898 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4902 /* Reject register-based expressions such as "0+$2" and "(($2))".
4903 For plain registers the default error seems more appropriate. */
4904 if (arg
->token
->type
== OT_INTEGER
4905 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4907 set_insn_error (arg
->argnum
, _("register value used as expression"));
4911 if (arg
->token
->type
== OT_INTEGER
)
4913 *value
= arg
->token
->u
.integer
.value
;
4914 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4920 (arg
->argnum
, _("operand %d must be an immediate expression"),
4925 /* Try to get a constant expression from the next tokens in ARG. Consume
4926 the tokens and return true on success, storing the constant value
4930 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4933 bfd_reloc_code_real_type r
[3];
4935 if (!match_expression (arg
, &ex
, r
))
4938 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4939 *value
= ex
.X_add_number
;
4942 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
4943 match_out_of_range (arg
);
4945 match_not_constant (arg
);
4951 /* Return the RTYPE_* flags for a register operand of type TYPE that
4952 appears in instruction OPCODE. */
4955 convert_reg_type (const struct mips_opcode
*opcode
,
4956 enum mips_reg_operand_type type
)
4961 return RTYPE_NUM
| RTYPE_GP
;
4964 /* Allow vector register names for MDMX if the instruction is a 64-bit
4965 FPR load, store or move (including moves to and from GPRs). */
4966 if ((mips_opts
.ase
& ASE_MDMX
)
4967 && (opcode
->pinfo
& FP_D
)
4968 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4969 | INSN_COPROC_MEMORY_DELAY
4972 | INSN_STORE_MEMORY
)))
4973 return RTYPE_FPU
| RTYPE_VEC
;
4977 if (opcode
->pinfo
& (FP_D
| FP_S
))
4978 return RTYPE_CCC
| RTYPE_FCC
;
4982 if (opcode
->membership
& INSN_5400
)
4984 return RTYPE_FPU
| RTYPE_VEC
;
4990 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4991 return RTYPE_NUM
| RTYPE_CP0
;
4998 return RTYPE_NUM
| RTYPE_VI
;
5001 return RTYPE_NUM
| RTYPE_VF
;
5003 case OP_REG_R5900_I
:
5004 return RTYPE_R5900_I
;
5006 case OP_REG_R5900_Q
:
5007 return RTYPE_R5900_Q
;
5009 case OP_REG_R5900_R
:
5010 return RTYPE_R5900_R
;
5012 case OP_REG_R5900_ACC
:
5013 return RTYPE_R5900_ACC
;
5018 case OP_REG_MSA_CTRL
:
5024 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5027 check_regno (struct mips_arg_info
*arg
,
5028 enum mips_reg_operand_type type
, unsigned int regno
)
5030 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5031 arg
->seen_at
= TRUE
;
5033 if (type
== OP_REG_FP
5035 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5037 /* This was a warning prior to introducing O32 FPXX and FP64 support
5038 so maintain a warning for FP32 but raise an error for the new
5041 as_warn (_("float register should be even, was %d"), regno
);
5043 as_bad (_("float register should be even, was %d"), regno
);
5046 if (type
== OP_REG_CCC
)
5051 name
= arg
->insn
->insn_mo
->name
;
5052 length
= strlen (name
);
5053 if ((regno
& 1) != 0
5054 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5055 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5056 as_warn (_("condition code register should be even for %s, was %d"),
5059 if ((regno
& 3) != 0
5060 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5061 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5066 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5067 a register of type TYPE. Return true on success, storing the register
5068 number in *REGNO and warning about any dubious uses. */
5071 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5072 unsigned int symval
, unsigned int *regno
)
5074 if (type
== OP_REG_VEC
)
5075 symval
= mips_prefer_vec_regno (symval
);
5076 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5079 *regno
= symval
& RNUM_MASK
;
5080 check_regno (arg
, type
, *regno
);
5084 /* Try to interpret the next token in ARG as a register of type TYPE.
5085 Consume the token and return true on success, storing the register
5086 number in *REGNO. Return false on failure. */
5089 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5090 unsigned int *regno
)
5092 if (arg
->token
->type
== OT_REG
5093 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5101 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5102 Consume the token and return true on success, storing the register numbers
5103 in *REGNO1 and *REGNO2. Return false on failure. */
5106 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5107 unsigned int *regno1
, unsigned int *regno2
)
5109 if (match_reg (arg
, type
, regno1
))
5114 if (arg
->token
->type
== OT_REG_RANGE
5115 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5116 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5117 && *regno1
<= *regno2
)
5125 /* OP_INT matcher. */
5128 match_int_operand (struct mips_arg_info
*arg
,
5129 const struct mips_operand
*operand_base
)
5131 const struct mips_int_operand
*operand
;
5133 int min_val
, max_val
, factor
;
5136 operand
= (const struct mips_int_operand
*) operand_base
;
5137 factor
= 1 << operand
->shift
;
5138 min_val
= mips_int_operand_min (operand
);
5139 max_val
= mips_int_operand_max (operand
);
5141 if (operand_base
->lsb
== 0
5142 && operand_base
->size
== 16
5143 && operand
->shift
== 0
5144 && operand
->bias
== 0
5145 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5147 /* The operand can be relocated. */
5148 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5151 if (offset_expr
.X_op
== O_big
)
5153 match_out_of_range (arg
);
5157 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5158 /* Relocation operators were used. Accept the argument and
5159 leave the relocation value in offset_expr and offset_relocs
5160 for the caller to process. */
5163 if (offset_expr
.X_op
!= O_constant
)
5165 /* Accept non-constant operands if no later alternative matches,
5166 leaving it for the caller to process. */
5167 if (!arg
->lax_match
)
5169 match_not_constant (arg
);
5172 offset_reloc
[0] = BFD_RELOC_LO16
;
5176 /* Clear the global state; we're going to install the operand
5178 sval
= offset_expr
.X_add_number
;
5179 offset_expr
.X_op
= O_absent
;
5181 /* For compatibility with older assemblers, we accept
5182 0x8000-0xffff as signed 16-bit numbers when only
5183 signed numbers are allowed. */
5186 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5187 if (!arg
->lax_match
&& sval
<= max_val
)
5189 match_out_of_range (arg
);
5196 if (!match_const_int (arg
, &sval
))
5200 arg
->last_op_int
= sval
;
5202 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5204 match_out_of_range (arg
);
5208 uval
= (unsigned int) sval
>> operand
->shift
;
5209 uval
-= operand
->bias
;
5211 /* Handle -mfix-cn63xxp1. */
5213 && mips_fix_cn63xxp1
5214 && !mips_opts
.micromips
5215 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5230 /* The rest must be changed to 28. */
5235 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5239 /* OP_MAPPED_INT matcher. */
5242 match_mapped_int_operand (struct mips_arg_info
*arg
,
5243 const struct mips_operand
*operand_base
)
5245 const struct mips_mapped_int_operand
*operand
;
5246 unsigned int uval
, num_vals
;
5249 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5250 if (!match_const_int (arg
, &sval
))
5253 num_vals
= 1 << operand_base
->size
;
5254 for (uval
= 0; uval
< num_vals
; uval
++)
5255 if (operand
->int_map
[uval
] == sval
)
5257 if (uval
== num_vals
)
5259 match_out_of_range (arg
);
5263 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5267 /* OP_MSB matcher. */
5270 match_msb_operand (struct mips_arg_info
*arg
,
5271 const struct mips_operand
*operand_base
)
5273 const struct mips_msb_operand
*operand
;
5274 int min_val
, max_val
, max_high
;
5275 offsetT size
, sval
, high
;
5277 operand
= (const struct mips_msb_operand
*) operand_base
;
5278 min_val
= operand
->bias
;
5279 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5280 max_high
= operand
->opsize
;
5282 if (!match_const_int (arg
, &size
))
5285 high
= size
+ arg
->last_op_int
;
5286 sval
= operand
->add_lsb
? high
: size
;
5288 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5290 match_out_of_range (arg
);
5293 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5297 /* OP_REG matcher. */
5300 match_reg_operand (struct mips_arg_info
*arg
,
5301 const struct mips_operand
*operand_base
)
5303 const struct mips_reg_operand
*operand
;
5304 unsigned int regno
, uval
, num_vals
;
5306 operand
= (const struct mips_reg_operand
*) operand_base
;
5307 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5310 if (operand
->reg_map
)
5312 num_vals
= 1 << operand
->root
.size
;
5313 for (uval
= 0; uval
< num_vals
; uval
++)
5314 if (operand
->reg_map
[uval
] == regno
)
5316 if (num_vals
== uval
)
5322 arg
->last_regno
= regno
;
5323 if (arg
->opnum
== 1)
5324 arg
->dest_regno
= regno
;
5325 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5329 /* OP_REG_PAIR matcher. */
5332 match_reg_pair_operand (struct mips_arg_info
*arg
,
5333 const struct mips_operand
*operand_base
)
5335 const struct mips_reg_pair_operand
*operand
;
5336 unsigned int regno1
, regno2
, uval
, num_vals
;
5338 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5339 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5340 || !match_char (arg
, ',')
5341 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5344 num_vals
= 1 << operand_base
->size
;
5345 for (uval
= 0; uval
< num_vals
; uval
++)
5346 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5348 if (uval
== num_vals
)
5351 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5355 /* OP_PCREL matcher. The caller chooses the relocation type. */
5358 match_pcrel_operand (struct mips_arg_info
*arg
)
5360 bfd_reloc_code_real_type r
[3];
5362 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5365 /* OP_PERF_REG matcher. */
5368 match_perf_reg_operand (struct mips_arg_info
*arg
,
5369 const struct mips_operand
*operand
)
5373 if (!match_const_int (arg
, &sval
))
5378 || (mips_opts
.arch
== CPU_R5900
5379 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5380 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5382 set_insn_error (arg
->argnum
, _("invalid performance register"));
5386 insn_insert_operand (arg
->insn
, operand
, sval
);
5390 /* OP_ADDIUSP matcher. */
5393 match_addiusp_operand (struct mips_arg_info
*arg
,
5394 const struct mips_operand
*operand
)
5399 if (!match_const_int (arg
, &sval
))
5404 match_out_of_range (arg
);
5409 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5411 match_out_of_range (arg
);
5415 uval
= (unsigned int) sval
;
5416 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5417 insn_insert_operand (arg
->insn
, operand
, uval
);
5421 /* OP_CLO_CLZ_DEST matcher. */
5424 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5425 const struct mips_operand
*operand
)
5429 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5432 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5436 /* OP_CHECK_PREV matcher. */
5439 match_check_prev_operand (struct mips_arg_info
*arg
,
5440 const struct mips_operand
*operand_base
)
5442 const struct mips_check_prev_operand
*operand
;
5445 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5447 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5450 if (!operand
->zero_ok
&& regno
== 0)
5453 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5454 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5455 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5457 arg
->last_regno
= regno
;
5458 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5465 /* OP_SAME_RS_RT matcher. */
5468 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5469 const struct mips_operand
*operand
)
5473 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5478 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5482 arg
->last_regno
= regno
;
5484 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5488 /* OP_LWM_SWM_LIST matcher. */
5491 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5492 const struct mips_operand
*operand
)
5494 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5495 struct mips_arg_info reset
;
5498 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5502 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5507 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5510 while (match_char (arg
, ',')
5511 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5514 if (operand
->size
== 2)
5516 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5522 and any permutations of these. */
5523 if ((reglist
& 0xfff1ffff) != 0x80010000)
5526 sregs
= (reglist
>> 17) & 7;
5531 /* The list must include at least one of ra and s0-sN,
5532 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5533 which are $23 and $30 respectively.) E.g.:
5541 and any permutations of these. */
5542 if ((reglist
& 0x3f00ffff) != 0)
5545 ra
= (reglist
>> 27) & 0x10;
5546 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5549 if ((sregs
& -sregs
) != sregs
)
5552 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5556 /* OP_ENTRY_EXIT_LIST matcher. */
5559 match_entry_exit_operand (struct mips_arg_info
*arg
,
5560 const struct mips_operand
*operand
)
5563 bfd_boolean is_exit
;
5565 /* The format is the same for both ENTRY and EXIT, but the constraints
5567 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5568 mask
= (is_exit
? 7 << 3 : 0);
5571 unsigned int regno1
, regno2
;
5572 bfd_boolean is_freg
;
5574 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5576 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5581 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5584 mask
|= (5 + regno2
) << 3;
5586 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5587 mask
|= (regno2
- 3) << 3;
5588 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5589 mask
|= (regno2
- 15) << 1;
5590 else if (regno1
== RA
&& regno2
== RA
)
5595 while (match_char (arg
, ','));
5597 insn_insert_operand (arg
->insn
, operand
, mask
);
5601 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5602 the argument register mask AMASK, the number of static registers
5603 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5604 respectively, and the frame size FRAME_SIZE. */
5607 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5608 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5609 unsigned int frame_size
)
5611 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5612 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5615 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5616 argument register mask AMASK, the number of static registers saved
5617 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5618 respectively, and the frame size FRAME_SIZE. */
5621 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5622 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5623 unsigned int frame_size
)
5627 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5628 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5629 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5630 | ((frame_size
& 0xf0) << 16));
5634 /* OP_SAVE_RESTORE_LIST matcher. */
5637 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5639 unsigned int opcode
, args
, statics
, sregs
;
5640 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5641 unsigned int arg_mask
, ra
, s0
, s1
;
5644 opcode
= arg
->insn
->insn_opcode
;
5646 num_frame_sizes
= 0;
5655 unsigned int regno1
, regno2
;
5657 if (arg
->token
->type
== OT_INTEGER
)
5659 /* Handle the frame size. */
5660 if (!match_const_int (arg
, &frame_size
))
5662 num_frame_sizes
+= 1;
5666 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5669 while (regno1
<= regno2
)
5671 if (regno1
>= 4 && regno1
<= 7)
5673 if (num_frame_sizes
== 0)
5675 args
|= 1 << (regno1
- 4);
5677 /* statics $a0-$a3 */
5678 statics
|= 1 << (regno1
- 4);
5680 else if (regno1
>= 16 && regno1
<= 23)
5682 sregs
|= 1 << (regno1
- 16);
5683 else if (regno1
== 30)
5686 else if (regno1
== 31)
5687 /* Add $ra to insn. */
5697 while (match_char (arg
, ','));
5699 /* Encode args/statics combination. */
5702 else if (args
== 0xf)
5703 /* All $a0-$a3 are args. */
5704 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5705 else if (statics
== 0xf)
5706 /* All $a0-$a3 are statics. */
5707 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5710 /* Count arg registers. */
5720 /* Count static registers. */
5722 while (statics
& 0x8)
5724 statics
= (statics
<< 1) & 0xf;
5730 /* Encode args/statics. */
5731 arg_mask
= (num_args
<< 2) | num_statics
;
5734 /* Encode $s0/$s1. */
5735 if (sregs
& (1 << 0)) /* $s0 */
5737 if (sregs
& (1 << 1)) /* $s1 */
5741 /* Encode $s2-$s8. */
5751 /* Encode frame size. */
5752 if (num_frame_sizes
== 0)
5754 set_insn_error (arg
->argnum
, _("missing frame size"));
5757 if (num_frame_sizes
> 1)
5759 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5762 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5764 set_insn_error (arg
->argnum
, _("invalid frame size"));
5769 /* Finally build the instruction. */
5770 if (mips_opts
.mips16
)
5771 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5773 else if (!mips_opts
.micromips
)
5774 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5779 arg
->insn
->insn_opcode
= opcode
;
5783 /* OP_MDMX_IMM_REG matcher. */
5786 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5787 const struct mips_operand
*operand
)
5789 unsigned int regno
, uval
;
5791 const struct mips_opcode
*opcode
;
5793 /* The mips_opcode records whether this is an octobyte or quadhalf
5794 instruction. Start out with that bit in place. */
5795 opcode
= arg
->insn
->insn_mo
;
5796 uval
= mips_extract_operand (operand
, opcode
->match
);
5797 is_qh
= (uval
!= 0);
5799 if (arg
->token
->type
== OT_REG
)
5801 if ((opcode
->membership
& INSN_5400
)
5802 && strcmp (opcode
->name
, "rzu.ob") == 0)
5804 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5809 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5813 /* Check whether this is a vector register or a broadcast of
5814 a single element. */
5815 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5817 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5819 set_insn_error (arg
->argnum
, _("invalid element selector"));
5822 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5827 /* A full vector. */
5828 if ((opcode
->membership
& INSN_5400
)
5829 && (strcmp (opcode
->name
, "sll.ob") == 0
5830 || strcmp (opcode
->name
, "srl.ob") == 0))
5832 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5838 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5840 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5848 if (!match_const_int (arg
, &sval
))
5850 if (sval
< 0 || sval
> 31)
5852 match_out_of_range (arg
);
5855 uval
|= (sval
& 31);
5857 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5859 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5861 insn_insert_operand (arg
->insn
, operand
, uval
);
5865 /* OP_IMM_INDEX matcher. */
5868 match_imm_index_operand (struct mips_arg_info
*arg
,
5869 const struct mips_operand
*operand
)
5871 unsigned int max_val
;
5873 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5876 max_val
= (1 << operand
->size
) - 1;
5877 if (arg
->token
->u
.index
> max_val
)
5879 match_out_of_range (arg
);
5882 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5887 /* OP_REG_INDEX matcher. */
5890 match_reg_index_operand (struct mips_arg_info
*arg
,
5891 const struct mips_operand
*operand
)
5895 if (arg
->token
->type
!= OT_REG_INDEX
)
5898 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5901 insn_insert_operand (arg
->insn
, operand
, regno
);
5906 /* OP_PC matcher. */
5909 match_pc_operand (struct mips_arg_info
*arg
)
5911 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5919 /* OP_REG28 matcher. */
5922 match_reg28_operand (struct mips_arg_info
*arg
)
5926 if (arg
->token
->type
== OT_REG
5927 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
5936 /* OP_NON_ZERO_REG matcher. */
5939 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5940 const struct mips_operand
*operand
)
5944 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5950 arg
->last_regno
= regno
;
5951 insn_insert_operand (arg
->insn
, operand
, regno
);
5955 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5956 register that we need to match. */
5959 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5963 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5966 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
5967 LENGTH is the length of the value in bytes (4 for float, 8 for double)
5968 and USING_GPRS says whether the destination is a GPR rather than an FPR.
5970 Return the constant in IMM and OFFSET as follows:
5972 - If the constant should be loaded via memory, set IMM to O_absent and
5973 OFFSET to the memory address.
5975 - Otherwise, if the constant should be loaded into two 32-bit registers,
5976 set IMM to the O_constant to load into the high register and OFFSET
5977 to the corresponding value for the low register.
5979 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5981 These constants only appear as the last operand in an instruction,
5982 and every instruction that accepts them in any variant accepts them
5983 in all variants. This means we don't have to worry about backing out
5984 any changes if the instruction does not match. We just match
5985 unconditionally and report an error if the constant is invalid. */
5988 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5989 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5994 const char *newname
;
5995 unsigned char *data
;
5997 /* Where the constant is placed is based on how the MIPS assembler
6000 length == 4 && using_gprs -- immediate value only
6001 length == 8 && using_gprs -- .rdata or immediate value
6002 length == 4 && !using_gprs -- .lit4 or immediate value
6003 length == 8 && !using_gprs -- .lit8 or immediate value
6005 The .lit4 and .lit8 sections are only used if permitted by the
6007 if (arg
->token
->type
!= OT_FLOAT
)
6009 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6013 gas_assert (arg
->token
->u
.flt
.length
== length
);
6014 data
= arg
->token
->u
.flt
.data
;
6017 /* Handle 32-bit constants for which an immediate value is best. */
6020 || g_switch_value
< 4
6021 || (data
[0] == 0 && data
[1] == 0)
6022 || (data
[2] == 0 && data
[3] == 0)))
6024 imm
->X_op
= O_constant
;
6025 if (!target_big_endian
)
6026 imm
->X_add_number
= bfd_getl32 (data
);
6028 imm
->X_add_number
= bfd_getb32 (data
);
6029 offset
->X_op
= O_absent
;
6033 /* Handle 64-bit constants for which an immediate value is best. */
6035 && !mips_disable_float_construction
6036 /* Constants can only be constructed in GPRs and copied to FPRs if the
6037 GPRs are at least as wide as the FPRs or MTHC1 is available.
6038 Unlike most tests for 32-bit floating-point registers this check
6039 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6040 permit 64-bit moves without MXHC1.
6041 Force the constant into memory otherwise. */
6044 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6046 && ((data
[0] == 0 && data
[1] == 0)
6047 || (data
[2] == 0 && data
[3] == 0))
6048 && ((data
[4] == 0 && data
[5] == 0)
6049 || (data
[6] == 0 && data
[7] == 0)))
6051 /* The value is simple enough to load with a couple of instructions.
6052 If using 32-bit registers, set IMM to the high order 32 bits and
6053 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6055 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6057 imm
->X_op
= O_constant
;
6058 offset
->X_op
= O_constant
;
6059 if (!target_big_endian
)
6061 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6062 offset
->X_add_number
= bfd_getl32 (data
);
6066 imm
->X_add_number
= bfd_getb32 (data
);
6067 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6069 if (offset
->X_add_number
== 0)
6070 offset
->X_op
= O_absent
;
6074 imm
->X_op
= O_constant
;
6075 if (!target_big_endian
)
6076 imm
->X_add_number
= bfd_getl64 (data
);
6078 imm
->X_add_number
= bfd_getb64 (data
);
6079 offset
->X_op
= O_absent
;
6084 /* Switch to the right section. */
6086 subseg
= now_subseg
;
6089 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6094 if (using_gprs
|| g_switch_value
< 8)
6095 newname
= RDATA_SECTION_NAME
;
6100 new_seg
= subseg_new (newname
, (subsegT
) 0);
6101 bfd_set_section_flags (stdoutput
, new_seg
,
6102 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6103 frag_align (length
== 4 ? 2 : 3, 0, 0);
6104 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6105 record_alignment (new_seg
, 4);
6107 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6109 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6111 /* Set the argument to the current address in the section. */
6112 imm
->X_op
= O_absent
;
6113 offset
->X_op
= O_symbol
;
6114 offset
->X_add_symbol
= symbol_temp_new_now ();
6115 offset
->X_add_number
= 0;
6117 /* Put the floating point number into the section. */
6118 p
= frag_more (length
);
6119 memcpy (p
, data
, length
);
6121 /* Switch back to the original section. */
6122 subseg_set (seg
, subseg
);
6126 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6130 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6131 const struct mips_operand
*operand
,
6132 bfd_boolean match_p
)
6136 /* The operand can be an XYZW mask or a single 2-bit channel index
6137 (with X being 0). */
6138 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6140 /* The suffix can be omitted when it is already part of the opcode. */
6141 if (arg
->token
->type
!= OT_CHANNELS
)
6144 uval
= arg
->token
->u
.channels
;
6145 if (operand
->size
== 2)
6147 /* Check that a single bit is set and convert it into a 2-bit index. */
6148 if ((uval
& -uval
) != uval
)
6150 uval
= 4 - ffs (uval
);
6153 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6158 insn_insert_operand (arg
->insn
, operand
, uval
);
6162 /* Try to match a token from ARG against OPERAND. Consume the token
6163 and return true on success, otherwise return false. */
6166 match_operand (struct mips_arg_info
*arg
,
6167 const struct mips_operand
*operand
)
6169 switch (operand
->type
)
6172 return match_int_operand (arg
, operand
);
6175 return match_mapped_int_operand (arg
, operand
);
6178 return match_msb_operand (arg
, operand
);
6181 case OP_OPTIONAL_REG
:
6182 return match_reg_operand (arg
, operand
);
6185 return match_reg_pair_operand (arg
, operand
);
6188 return match_pcrel_operand (arg
);
6191 return match_perf_reg_operand (arg
, operand
);
6193 case OP_ADDIUSP_INT
:
6194 return match_addiusp_operand (arg
, operand
);
6196 case OP_CLO_CLZ_DEST
:
6197 return match_clo_clz_dest_operand (arg
, operand
);
6199 case OP_LWM_SWM_LIST
:
6200 return match_lwm_swm_list_operand (arg
, operand
);
6202 case OP_ENTRY_EXIT_LIST
:
6203 return match_entry_exit_operand (arg
, operand
);
6205 case OP_SAVE_RESTORE_LIST
:
6206 return match_save_restore_list_operand (arg
);
6208 case OP_MDMX_IMM_REG
:
6209 return match_mdmx_imm_reg_operand (arg
, operand
);
6211 case OP_REPEAT_DEST_REG
:
6212 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6214 case OP_REPEAT_PREV_REG
:
6215 return match_tied_reg_operand (arg
, arg
->last_regno
);
6218 return match_pc_operand (arg
);
6221 return match_reg28_operand (arg
);
6224 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6226 case OP_VU0_MATCH_SUFFIX
:
6227 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6230 return match_imm_index_operand (arg
, operand
);
6233 return match_reg_index_operand (arg
, operand
);
6236 return match_same_rs_rt_operand (arg
, operand
);
6239 return match_check_prev_operand (arg
, operand
);
6241 case OP_NON_ZERO_REG
:
6242 return match_non_zero_reg_operand (arg
, operand
);
6247 /* ARG is the state after successfully matching an instruction.
6248 Issue any queued-up warnings. */
6251 check_completed_insn (struct mips_arg_info
*arg
)
6256 as_warn (_("used $at without \".set noat\""));
6258 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6262 /* Return true if modifying general-purpose register REG needs a delay. */
6265 reg_needs_delay (unsigned int reg
)
6267 unsigned long prev_pinfo
;
6269 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6270 if (!mips_opts
.noreorder
6271 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6272 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6273 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6279 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6280 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6281 by VR4120 errata. */
6284 classify_vr4120_insn (const char *name
)
6286 if (strncmp (name
, "macc", 4) == 0)
6287 return FIX_VR4120_MACC
;
6288 if (strncmp (name
, "dmacc", 5) == 0)
6289 return FIX_VR4120_DMACC
;
6290 if (strncmp (name
, "mult", 4) == 0)
6291 return FIX_VR4120_MULT
;
6292 if (strncmp (name
, "dmult", 5) == 0)
6293 return FIX_VR4120_DMULT
;
6294 if (strstr (name
, "div"))
6295 return FIX_VR4120_DIV
;
6296 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6297 return FIX_VR4120_MTHILO
;
6298 return NUM_FIX_VR4120_CLASSES
;
6301 #define INSN_ERET 0x42000018
6302 #define INSN_DERET 0x4200001f
6303 #define INSN_DMULT 0x1c
6304 #define INSN_DMULTU 0x1d
6306 /* Return the number of instructions that must separate INSN1 and INSN2,
6307 where INSN1 is the earlier instruction. Return the worst-case value
6308 for any INSN2 if INSN2 is null. */
6311 insns_between (const struct mips_cl_insn
*insn1
,
6312 const struct mips_cl_insn
*insn2
)
6314 unsigned long pinfo1
, pinfo2
;
6317 /* If INFO2 is null, pessimistically assume that all flags are set for
6318 the second instruction. */
6319 pinfo1
= insn1
->insn_mo
->pinfo
;
6320 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6322 /* For most targets, write-after-read dependencies on the HI and LO
6323 registers must be separated by at least two instructions. */
6324 if (!hilo_interlocks
)
6326 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6328 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6332 /* If we're working around r7000 errata, there must be two instructions
6333 between an mfhi or mflo and any instruction that uses the result. */
6334 if (mips_7000_hilo_fix
6335 && !mips_opts
.micromips
6336 && MF_HILO_INSN (pinfo1
)
6337 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6340 /* If we're working around 24K errata, one instruction is required
6341 if an ERET or DERET is followed by a branch instruction. */
6342 if (mips_fix_24k
&& !mips_opts
.micromips
)
6344 if (insn1
->insn_opcode
== INSN_ERET
6345 || insn1
->insn_opcode
== INSN_DERET
)
6348 || insn2
->insn_opcode
== INSN_ERET
6349 || insn2
->insn_opcode
== INSN_DERET
6350 || delayed_branch_p (insn2
))
6355 /* If we're working around PMC RM7000 errata, there must be three
6356 nops between a dmult and a load instruction. */
6357 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6359 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6360 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6362 if (pinfo2
& INSN_LOAD_MEMORY
)
6367 /* If working around VR4120 errata, check for combinations that need
6368 a single intervening instruction. */
6369 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6371 unsigned int class1
, class2
;
6373 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6374 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6378 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6379 if (vr4120_conflicts
[class1
] & (1 << class2
))
6384 if (!HAVE_CODE_COMPRESSION
)
6386 /* Check for GPR or coprocessor load delays. All such delays
6387 are on the RT register. */
6388 /* Itbl support may require additional care here. */
6389 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6390 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6392 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6396 /* Check for generic coprocessor hazards.
6398 This case is not handled very well. There is no special
6399 knowledge of CP0 handling, and the coprocessors other than
6400 the floating point unit are not distinguished at all. */
6401 /* Itbl support may require additional care here. FIXME!
6402 Need to modify this to include knowledge about
6403 user specified delays! */
6404 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6405 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6407 /* Handle cases where INSN1 writes to a known general coprocessor
6408 register. There must be a one instruction delay before INSN2
6409 if INSN2 reads that register, otherwise no delay is needed. */
6410 mask
= fpr_write_mask (insn1
);
6413 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6418 /* Read-after-write dependencies on the control registers
6419 require a two-instruction gap. */
6420 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6421 && (pinfo2
& INSN_READ_COND_CODE
))
6424 /* We don't know exactly what INSN1 does. If INSN2 is
6425 also a coprocessor instruction, assume there must be
6426 a one instruction gap. */
6427 if (pinfo2
& INSN_COP
)
6432 /* Check for read-after-write dependencies on the coprocessor
6433 control registers in cases where INSN1 does not need a general
6434 coprocessor delay. This means that INSN1 is a floating point
6435 comparison instruction. */
6436 /* Itbl support may require additional care here. */
6437 else if (!cop_interlocks
6438 && (pinfo1
& INSN_WRITE_COND_CODE
)
6439 && (pinfo2
& INSN_READ_COND_CODE
))
6443 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6444 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6446 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6447 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6448 || (insn2
&& delayed_branch_p (insn2
))))
6454 /* Return the number of nops that would be needed to work around the
6455 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6456 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6457 that are contained within the first IGNORE instructions of HIST. */
6460 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6461 const struct mips_cl_insn
*insn
)
6466 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6467 are not affected by the errata. */
6469 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6470 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6471 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6474 /* Search for the first MFLO or MFHI. */
6475 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6476 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6478 /* Extract the destination register. */
6479 mask
= gpr_write_mask (&hist
[i
]);
6481 /* No nops are needed if INSN reads that register. */
6482 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6485 /* ...or if any of the intervening instructions do. */
6486 for (j
= 0; j
< i
; j
++)
6487 if (gpr_read_mask (&hist
[j
]) & mask
)
6491 return MAX_VR4130_NOPS
- i
;
6496 #define BASE_REG_EQ(INSN1, INSN2) \
6497 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6498 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6500 /* Return the minimum alignment for this store instruction. */
6503 fix_24k_align_to (const struct mips_opcode
*mo
)
6505 if (strcmp (mo
->name
, "sh") == 0)
6508 if (strcmp (mo
->name
, "swc1") == 0
6509 || strcmp (mo
->name
, "swc2") == 0
6510 || strcmp (mo
->name
, "sw") == 0
6511 || strcmp (mo
->name
, "sc") == 0
6512 || strcmp (mo
->name
, "s.s") == 0)
6515 if (strcmp (mo
->name
, "sdc1") == 0
6516 || strcmp (mo
->name
, "sdc2") == 0
6517 || strcmp (mo
->name
, "s.d") == 0)
6524 struct fix_24k_store_info
6526 /* Immediate offset, if any, for this store instruction. */
6528 /* Alignment required by this store instruction. */
6530 /* True for register offsets. */
6531 int register_offset
;
6534 /* Comparison function used by qsort. */
6537 fix_24k_sort (const void *a
, const void *b
)
6539 const struct fix_24k_store_info
*pos1
= a
;
6540 const struct fix_24k_store_info
*pos2
= b
;
6542 return (pos1
->off
- pos2
->off
);
6545 /* INSN is a store instruction. Try to record the store information
6546 in STINFO. Return false if the information isn't known. */
6549 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6550 const struct mips_cl_insn
*insn
)
6552 /* The instruction must have a known offset. */
6553 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6556 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6557 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6561 /* Return the number of nops that would be needed to work around the 24k
6562 "lost data on stores during refill" errata if instruction INSN
6563 immediately followed the 2 instructions described by HIST.
6564 Ignore hazards that are contained within the first IGNORE
6565 instructions of HIST.
6567 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6568 for the data cache refills and store data. The following describes
6569 the scenario where the store data could be lost.
6571 * A data cache miss, due to either a load or a store, causing fill
6572 data to be supplied by the memory subsystem
6573 * The first three doublewords of fill data are returned and written
6575 * A sequence of four stores occurs in consecutive cycles around the
6576 final doubleword of the fill:
6580 * Zero, One or more instructions
6583 The four stores A-D must be to different doublewords of the line that
6584 is being filled. The fourth instruction in the sequence above permits
6585 the fill of the final doubleword to be transferred from the FSB into
6586 the cache. In the sequence above, the stores may be either integer
6587 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6588 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6589 different doublewords on the line. If the floating point unit is
6590 running in 1:2 mode, it is not possible to create the sequence above
6591 using only floating point store instructions.
6593 In this case, the cache line being filled is incorrectly marked
6594 invalid, thereby losing the data from any store to the line that
6595 occurs between the original miss and the completion of the five
6596 cycle sequence shown above.
6598 The workarounds are:
6600 * Run the data cache in write-through mode.
6601 * Insert a non-store instruction between
6602 Store A and Store B or Store B and Store C. */
6605 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6606 const struct mips_cl_insn
*insn
)
6608 struct fix_24k_store_info pos
[3];
6609 int align
, i
, base_offset
;
6614 /* If the previous instruction wasn't a store, there's nothing to
6616 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6619 /* If the instructions after the previous one are unknown, we have
6620 to assume the worst. */
6624 /* Check whether we are dealing with three consecutive stores. */
6625 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6626 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6629 /* If we don't know the relationship between the store addresses,
6630 assume the worst. */
6631 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6632 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6635 if (!fix_24k_record_store_info (&pos
[0], insn
)
6636 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6637 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6640 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6642 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6643 X bytes and such that the base register + X is known to be aligned
6646 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6650 align
= pos
[0].align_to
;
6651 base_offset
= pos
[0].off
;
6652 for (i
= 1; i
< 3; i
++)
6653 if (align
< pos
[i
].align_to
)
6655 align
= pos
[i
].align_to
;
6656 base_offset
= pos
[i
].off
;
6658 for (i
= 0; i
< 3; i
++)
6659 pos
[i
].off
-= base_offset
;
6662 pos
[0].off
&= ~align
+ 1;
6663 pos
[1].off
&= ~align
+ 1;
6664 pos
[2].off
&= ~align
+ 1;
6666 /* If any two stores write to the same chunk, they also write to the
6667 same doubleword. The offsets are still sorted at this point. */
6668 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6671 /* A range of at least 9 bytes is needed for the stores to be in
6672 non-overlapping doublewords. */
6673 if (pos
[2].off
- pos
[0].off
<= 8)
6676 if (pos
[2].off
- pos
[1].off
>= 24
6677 || pos
[1].off
- pos
[0].off
>= 24
6678 || pos
[2].off
- pos
[0].off
>= 32)
6684 /* Return the number of nops that would be needed if instruction INSN
6685 immediately followed the MAX_NOPS instructions given by HIST,
6686 where HIST[0] is the most recent instruction. Ignore hazards
6687 between INSN and the first IGNORE instructions in HIST.
6689 If INSN is null, return the worse-case number of nops for any
6693 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6694 const struct mips_cl_insn
*insn
)
6696 int i
, nops
, tmp_nops
;
6699 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6701 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6702 if (tmp_nops
> nops
)
6706 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6708 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6709 if (tmp_nops
> nops
)
6713 if (mips_fix_24k
&& !mips_opts
.micromips
)
6715 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6716 if (tmp_nops
> nops
)
6723 /* The variable arguments provide NUM_INSNS extra instructions that
6724 might be added to HIST. Return the largest number of nops that
6725 would be needed after the extended sequence, ignoring hazards
6726 in the first IGNORE instructions. */
6729 nops_for_sequence (int num_insns
, int ignore
,
6730 const struct mips_cl_insn
*hist
, ...)
6733 struct mips_cl_insn buffer
[MAX_NOPS
];
6734 struct mips_cl_insn
*cursor
;
6737 va_start (args
, hist
);
6738 cursor
= buffer
+ num_insns
;
6739 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6740 while (cursor
> buffer
)
6741 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6743 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6748 /* Like nops_for_insn, but if INSN is a branch, take into account the
6749 worst-case delay for the branch target. */
6752 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6753 const struct mips_cl_insn
*insn
)
6757 nops
= nops_for_insn (ignore
, hist
, insn
);
6758 if (delayed_branch_p (insn
))
6760 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6761 hist
, insn
, get_delay_slot_nop (insn
));
6762 if (tmp_nops
> nops
)
6765 else if (compact_branch_p (insn
))
6767 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6768 if (tmp_nops
> nops
)
6774 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6777 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6779 gas_assert (!HAVE_CODE_COMPRESSION
);
6780 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6781 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6784 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6785 jr target pc &= 'hffff_ffff_cfff_ffff. */
6788 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6790 gas_assert (!HAVE_CODE_COMPRESSION
);
6791 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6792 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6793 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6801 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6802 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6805 ep
.X_op
= O_constant
;
6806 ep
.X_add_number
= 0xcfff0000;
6807 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6808 ep
.X_add_number
= 0xffff;
6809 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6810 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6815 fix_loongson2f (struct mips_cl_insn
* ip
)
6817 if (mips_fix_loongson2f_nop
)
6818 fix_loongson2f_nop (ip
);
6820 if (mips_fix_loongson2f_jump
)
6821 fix_loongson2f_jump (ip
);
6824 /* IP is a branch that has a delay slot, and we need to fill it
6825 automatically. Return true if we can do that by swapping IP
6826 with the previous instruction.
6827 ADDRESS_EXPR is an operand of the instruction to be used with
6831 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6832 bfd_reloc_code_real_type
*reloc_type
)
6834 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6835 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6836 unsigned int fpr_read
, prev_fpr_write
;
6838 /* -O2 and above is required for this optimization. */
6839 if (mips_optimize
< 2)
6842 /* If we have seen .set volatile or .set nomove, don't optimize. */
6843 if (mips_opts
.nomove
)
6846 /* We can't swap if the previous instruction's position is fixed. */
6847 if (history
[0].fixed_p
)
6850 /* If the previous previous insn was in a .set noreorder, we can't
6851 swap. Actually, the MIPS assembler will swap in this situation.
6852 However, gcc configured -with-gnu-as will generate code like
6860 in which we can not swap the bne and INSN. If gcc is not configured
6861 -with-gnu-as, it does not output the .set pseudo-ops. */
6862 if (history
[1].noreorder_p
)
6865 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6866 This means that the previous instruction was a 4-byte one anyhow. */
6867 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6870 /* If the branch is itself the target of a branch, we can not swap.
6871 We cheat on this; all we check for is whether there is a label on
6872 this instruction. If there are any branches to anything other than
6873 a label, users must use .set noreorder. */
6874 if (seg_info (now_seg
)->label_list
)
6877 /* If the previous instruction is in a variant frag other than this
6878 branch's one, we cannot do the swap. This does not apply to
6879 MIPS16 code, which uses variant frags for different purposes. */
6880 if (!mips_opts
.mips16
6882 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6885 /* We do not swap with instructions that cannot architecturally
6886 be placed in a branch delay slot, such as SYNC or ERET. We
6887 also refrain from swapping with a trap instruction, since it
6888 complicates trap handlers to have the trap instruction be in
6890 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6891 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6894 /* Check for conflicts between the branch and the instructions
6895 before the candidate delay slot. */
6896 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6899 /* Check for conflicts between the swapped sequence and the
6900 target of the branch. */
6901 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6904 /* If the branch reads a register that the previous
6905 instruction sets, we can not swap. */
6906 gpr_read
= gpr_read_mask (ip
);
6907 prev_gpr_write
= gpr_write_mask (&history
[0]);
6908 if (gpr_read
& prev_gpr_write
)
6911 fpr_read
= fpr_read_mask (ip
);
6912 prev_fpr_write
= fpr_write_mask (&history
[0]);
6913 if (fpr_read
& prev_fpr_write
)
6916 /* If the branch writes a register that the previous
6917 instruction sets, we can not swap. */
6918 gpr_write
= gpr_write_mask (ip
);
6919 if (gpr_write
& prev_gpr_write
)
6922 /* If the branch writes a register that the previous
6923 instruction reads, we can not swap. */
6924 prev_gpr_read
= gpr_read_mask (&history
[0]);
6925 if (gpr_write
& prev_gpr_read
)
6928 /* If one instruction sets a condition code and the
6929 other one uses a condition code, we can not swap. */
6930 pinfo
= ip
->insn_mo
->pinfo
;
6931 if ((pinfo
& INSN_READ_COND_CODE
)
6932 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6934 if ((pinfo
& INSN_WRITE_COND_CODE
)
6935 && (prev_pinfo
& INSN_READ_COND_CODE
))
6938 /* If the previous instruction uses the PC, we can not swap. */
6939 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6940 if (prev_pinfo2
& INSN2_READ_PC
)
6943 /* If the previous instruction has an incorrect size for a fixed
6944 branch delay slot in microMIPS mode, we cannot swap. */
6945 pinfo2
= ip
->insn_mo
->pinfo2
;
6946 if (mips_opts
.micromips
6947 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6948 && insn_length (history
) != 2)
6950 if (mips_opts
.micromips
6951 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6952 && insn_length (history
) != 4)
6955 /* On R5900 short loops need to be fixed by inserting a nop in
6956 the branch delay slots.
6957 A short loop can be terminated too early. */
6958 if (mips_opts
.arch
== CPU_R5900
6959 /* Check if instruction has a parameter, ignore "j $31". */
6960 && (address_expr
!= NULL
)
6961 /* Parameter must be 16 bit. */
6962 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6963 /* Branch to same segment. */
6964 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
6965 /* Branch to same code fragment. */
6966 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
6967 /* Can only calculate branch offset if value is known. */
6968 && symbol_constant_p (address_expr
->X_add_symbol
)
6969 /* Check if branch is really conditional. */
6970 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6971 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6972 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6975 /* Check if loop is shorter than 6 instructions including
6976 branch and delay slot. */
6977 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
6984 /* When the loop includes branches or jumps,
6985 it is not a short loop. */
6986 for (i
= 0; i
< (distance
/ 4); i
++)
6988 if ((history
[i
].cleared_p
)
6989 || delayed_branch_p (&history
[i
]))
6997 /* Insert nop after branch to fix short loop. */
7006 /* Decide how we should add IP to the instruction stream.
7007 ADDRESS_EXPR is an operand of the instruction to be used with
7010 static enum append_method
7011 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7012 bfd_reloc_code_real_type
*reloc_type
)
7014 /* The relaxed version of a macro sequence must be inherently
7016 if (mips_relax
.sequence
== 2)
7019 /* We must not dabble with instructions in a ".set noreorder" block. */
7020 if (mips_opts
.noreorder
)
7023 /* Otherwise, it's our responsibility to fill branch delay slots. */
7024 if (delayed_branch_p (ip
))
7026 if (!branch_likely_p (ip
)
7027 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7030 if (mips_opts
.mips16
7031 && ISA_SUPPORTS_MIPS16E
7032 && gpr_read_mask (ip
) != 0)
7033 return APPEND_ADD_COMPACT
;
7035 if (mips_opts
.micromips
7036 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7037 || (!forced_insn_length
7038 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7039 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7040 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7041 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7042 return APPEND_ADD_COMPACT
;
7044 return APPEND_ADD_WITH_NOP
;
7050 /* IP is an instruction whose opcode we have just changed, END points
7051 to the end of the opcode table processed. Point IP->insn_mo to the
7052 new opcode's definition. */
7055 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7057 const struct mips_opcode
*mo
;
7059 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7060 if (mo
->pinfo
!= INSN_MACRO
7061 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7069 /* IP is a MIPS16 instruction whose opcode we have just changed.
7070 Point IP->insn_mo to the new opcode's definition. */
7073 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7075 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7078 /* IP is a microMIPS instruction whose opcode we have just changed.
7079 Point IP->insn_mo to the new opcode's definition. */
7082 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7084 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7087 /* For microMIPS macros, we need to generate a local number label
7088 as the target of branches. */
7089 #define MICROMIPS_LABEL_CHAR '\037'
7090 static unsigned long micromips_target_label
;
7091 static char micromips_target_name
[32];
7094 micromips_label_name (void)
7096 char *p
= micromips_target_name
;
7097 char symbol_name_temporary
[24];
7105 l
= micromips_target_label
;
7106 #ifdef LOCAL_LABEL_PREFIX
7107 *p
++ = LOCAL_LABEL_PREFIX
;
7110 *p
++ = MICROMIPS_LABEL_CHAR
;
7113 symbol_name_temporary
[i
++] = l
% 10 + '0';
7118 *p
++ = symbol_name_temporary
[--i
];
7121 return micromips_target_name
;
7125 micromips_label_expr (expressionS
*label_expr
)
7127 label_expr
->X_op
= O_symbol
;
7128 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7129 label_expr
->X_add_number
= 0;
7133 micromips_label_inc (void)
7135 micromips_target_label
++;
7136 *micromips_target_name
= '\0';
7140 micromips_add_label (void)
7144 s
= colon (micromips_label_name ());
7145 micromips_label_inc ();
7146 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7149 /* If assembling microMIPS code, then return the microMIPS reloc
7150 corresponding to the requested one if any. Otherwise return
7151 the reloc unchanged. */
7153 static bfd_reloc_code_real_type
7154 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7156 static const bfd_reloc_code_real_type relocs
[][2] =
7158 /* Keep sorted incrementally by the left-hand key. */
7159 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7160 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7161 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7162 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7163 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7164 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7165 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7166 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7167 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7168 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7169 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7170 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7171 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7172 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7173 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7174 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7175 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7176 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7177 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7178 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7179 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7180 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7181 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7182 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7183 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7184 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7185 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7187 bfd_reloc_code_real_type r
;
7190 if (!mips_opts
.micromips
)
7192 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7198 return relocs
[i
][1];
7203 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7204 Return true on success, storing the resolved value in RESULT. */
7207 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7212 case BFD_RELOC_MIPS_HIGHEST
:
7213 case BFD_RELOC_MICROMIPS_HIGHEST
:
7214 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7217 case BFD_RELOC_MIPS_HIGHER
:
7218 case BFD_RELOC_MICROMIPS_HIGHER
:
7219 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7222 case BFD_RELOC_HI16_S
:
7223 case BFD_RELOC_HI16_S_PCREL
:
7224 case BFD_RELOC_MICROMIPS_HI16_S
:
7225 case BFD_RELOC_MIPS16_HI16_S
:
7226 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7229 case BFD_RELOC_HI16
:
7230 case BFD_RELOC_MICROMIPS_HI16
:
7231 case BFD_RELOC_MIPS16_HI16
:
7232 *result
= (operand
>> 16) & 0xffff;
7235 case BFD_RELOC_LO16
:
7236 case BFD_RELOC_LO16_PCREL
:
7237 case BFD_RELOC_MICROMIPS_LO16
:
7238 case BFD_RELOC_MIPS16_LO16
:
7239 *result
= operand
& 0xffff;
7242 case BFD_RELOC_UNUSED
:
7251 /* Output an instruction. IP is the instruction information.
7252 ADDRESS_EXPR is an operand of the instruction to be used with
7253 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7254 a macro expansion. */
7257 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7258 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7260 unsigned long prev_pinfo2
, pinfo
;
7261 bfd_boolean relaxed_branch
= FALSE
;
7262 enum append_method method
;
7263 bfd_boolean relax32
;
7266 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7267 fix_loongson2f (ip
);
7269 file_ase_mips16
|= mips_opts
.mips16
;
7270 file_ase_micromips
|= mips_opts
.micromips
;
7272 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7273 pinfo
= ip
->insn_mo
->pinfo
;
7275 /* Don't raise alarm about `nods' frags as they'll fill in the right
7276 kind of nop in relaxation if required. */
7277 if (mips_opts
.micromips
7279 && !(history
[0].frag
7280 && history
[0].frag
->fr_type
== rs_machine_dependent
7281 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7282 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7283 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7284 && micromips_insn_length (ip
->insn_mo
) != 2)
7285 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7286 && micromips_insn_length (ip
->insn_mo
) != 4)))
7287 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7288 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7290 if (address_expr
== NULL
)
7292 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7293 && reloc_type
[1] == BFD_RELOC_UNUSED
7294 && reloc_type
[2] == BFD_RELOC_UNUSED
7295 && address_expr
->X_op
== O_constant
)
7297 switch (*reloc_type
)
7299 case BFD_RELOC_MIPS_JMP
:
7303 /* Shift is 2, unusually, for microMIPS JALX. */
7304 shift
= (mips_opts
.micromips
7305 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7306 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7307 as_bad (_("jump to misaligned address (0x%lx)"),
7308 (unsigned long) address_expr
->X_add_number
);
7309 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7315 case BFD_RELOC_MIPS16_JMP
:
7316 if ((address_expr
->X_add_number
& 3) != 0)
7317 as_bad (_("jump to misaligned address (0x%lx)"),
7318 (unsigned long) address_expr
->X_add_number
);
7320 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7321 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7322 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7326 case BFD_RELOC_16_PCREL_S2
:
7330 shift
= mips_opts
.micromips
? 1 : 2;
7331 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7332 as_bad (_("branch to misaligned address (0x%lx)"),
7333 (unsigned long) address_expr
->X_add_number
);
7334 if (!mips_relax_branch
)
7336 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7337 & ~((1 << (shift
+ 16)) - 1))
7338 as_bad (_("branch address range overflow (0x%lx)"),
7339 (unsigned long) address_expr
->X_add_number
);
7340 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7346 case BFD_RELOC_MIPS_21_PCREL_S2
:
7351 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7352 as_bad (_("branch to misaligned address (0x%lx)"),
7353 (unsigned long) address_expr
->X_add_number
);
7354 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7355 & ~((1 << (shift
+ 21)) - 1))
7356 as_bad (_("branch address range overflow (0x%lx)"),
7357 (unsigned long) address_expr
->X_add_number
);
7358 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7363 case BFD_RELOC_MIPS_26_PCREL_S2
:
7368 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7369 as_bad (_("branch to misaligned address (0x%lx)"),
7370 (unsigned long) address_expr
->X_add_number
);
7371 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7372 & ~((1 << (shift
+ 26)) - 1))
7373 as_bad (_("branch address range overflow (0x%lx)"),
7374 (unsigned long) address_expr
->X_add_number
);
7375 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7384 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7387 ip
->insn_opcode
|= value
& 0xffff;
7395 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7397 /* There are a lot of optimizations we could do that we don't.
7398 In particular, we do not, in general, reorder instructions.
7399 If you use gcc with optimization, it will reorder
7400 instructions and generally do much more optimization then we
7401 do here; repeating all that work in the assembler would only
7402 benefit hand written assembly code, and does not seem worth
7404 int nops
= (mips_optimize
== 0
7405 ? nops_for_insn (0, history
, NULL
)
7406 : nops_for_insn_or_target (0, history
, ip
));
7410 unsigned long old_frag_offset
;
7413 old_frag
= frag_now
;
7414 old_frag_offset
= frag_now_fix ();
7416 for (i
= 0; i
< nops
; i
++)
7417 add_fixed_insn (NOP_INSN
);
7418 insert_into_history (0, nops
, NOP_INSN
);
7422 listing_prev_line ();
7423 /* We may be at the start of a variant frag. In case we
7424 are, make sure there is enough space for the frag
7425 after the frags created by listing_prev_line. The
7426 argument to frag_grow here must be at least as large
7427 as the argument to all other calls to frag_grow in
7428 this file. We don't have to worry about being in the
7429 middle of a variant frag, because the variants insert
7430 all needed nop instructions themselves. */
7434 mips_move_text_labels ();
7436 #ifndef NO_ECOFF_DEBUGGING
7437 if (ECOFF_DEBUGGING
)
7438 ecoff_fix_loc (old_frag
, old_frag_offset
);
7442 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7446 /* Work out how many nops in prev_nop_frag are needed by IP,
7447 ignoring hazards generated by the first prev_nop_frag_since
7449 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7450 gas_assert (nops
<= prev_nop_frag_holds
);
7452 /* Enforce NOPS as a minimum. */
7453 if (nops
> prev_nop_frag_required
)
7454 prev_nop_frag_required
= nops
;
7456 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7458 /* Settle for the current number of nops. Update the history
7459 accordingly (for the benefit of any future .set reorder code). */
7460 prev_nop_frag
= NULL
;
7461 insert_into_history (prev_nop_frag_since
,
7462 prev_nop_frag_holds
, NOP_INSN
);
7466 /* Allow this instruction to replace one of the nops that was
7467 tentatively added to prev_nop_frag. */
7468 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7469 prev_nop_frag_holds
--;
7470 prev_nop_frag_since
++;
7474 method
= get_append_method (ip
, address_expr
, reloc_type
);
7475 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7477 dwarf2_emit_insn (0);
7478 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7479 so "move" the instruction address accordingly.
7481 Also, it doesn't seem appropriate for the assembler to reorder .loc
7482 entries. If this instruction is a branch that we are going to swap
7483 with the previous instruction, the two instructions should be
7484 treated as a unit, and the debug information for both instructions
7485 should refer to the start of the branch sequence. Using the
7486 current position is certainly wrong when swapping a 32-bit branch
7487 and a 16-bit delay slot, since the current position would then be
7488 in the middle of a branch. */
7489 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7491 relax32
= (mips_relax_branch
7492 /* Don't try branch relaxation within .set nomacro, or within
7493 .set noat if we use $at for PIC computations. If it turns
7494 out that the branch was out-of-range, we'll get an error. */
7495 && !mips_opts
.warn_about_macros
7496 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7497 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7498 as they have no complementing branches. */
7499 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7501 if (!HAVE_CODE_COMPRESSION
7504 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7505 && delayed_branch_p (ip
))
7507 relaxed_branch
= TRUE
;
7508 add_relaxed_insn (ip
, (relaxed_branch_length
7510 uncond_branch_p (ip
) ? -1
7511 : branch_likely_p (ip
) ? 1
7514 (AT
, mips_pic
!= NO_PIC
,
7515 uncond_branch_p (ip
),
7516 branch_likely_p (ip
),
7517 pinfo
& INSN_WRITE_GPR_31
,
7519 address_expr
->X_add_symbol
,
7520 address_expr
->X_add_number
);
7521 *reloc_type
= BFD_RELOC_UNUSED
;
7523 else if (mips_opts
.micromips
7525 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7526 || *reloc_type
> BFD_RELOC_UNUSED
)
7527 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7528 /* Don't try branch relaxation when users specify
7529 16-bit/32-bit instructions. */
7530 && !forced_insn_length
)
7532 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7533 && *reloc_type
> BFD_RELOC_UNUSED
);
7534 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7535 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7536 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7537 int nods
= method
== APPEND_ADD_WITH_NOP
;
7538 int al
= pinfo
& INSN_WRITE_GPR_31
;
7539 int length32
= nods
? 8 : 4;
7541 gas_assert (address_expr
!= NULL
);
7542 gas_assert (!mips_relax
.sequence
);
7544 relaxed_branch
= TRUE
;
7546 method
= APPEND_ADD
;
7548 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7549 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7550 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7552 uncond
, compact
, al
, nods
,
7554 address_expr
->X_add_symbol
,
7555 address_expr
->X_add_number
);
7556 *reloc_type
= BFD_RELOC_UNUSED
;
7558 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7560 bfd_boolean require_unextended
;
7561 bfd_boolean require_extended
;
7565 if (forced_insn_length
!= 0)
7567 require_unextended
= forced_insn_length
== 2;
7568 require_extended
= forced_insn_length
== 4;
7572 require_unextended
= (mips_opts
.noautoextend
7573 && !mips_opcode_32bit_p (ip
->insn_mo
));
7574 require_extended
= 0;
7577 /* We need to set up a variant frag. */
7578 gas_assert (address_expr
!= NULL
);
7579 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7580 symbol created by `make_expr_symbol' may not get a necessary
7581 external relocation produced. */
7582 if (address_expr
->X_op
== O_symbol
)
7584 symbol
= address_expr
->X_add_symbol
;
7585 offset
= address_expr
->X_add_number
;
7589 symbol
= make_expr_symbol (address_expr
);
7590 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7593 add_relaxed_insn (ip
, 12, 0,
7595 (*reloc_type
- BFD_RELOC_UNUSED
,
7596 mips_opts
.ase
& ASE_MIPS16E2
,
7599 mips_opts
.warn_about_macros
,
7600 require_unextended
, require_extended
,
7601 delayed_branch_p (&history
[0]),
7602 history
[0].mips16_absolute_jump_p
),
7605 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7607 if (!delayed_branch_p (ip
))
7608 /* Make sure there is enough room to swap this instruction with
7609 a following jump instruction. */
7611 add_fixed_insn (ip
);
7615 if (mips_opts
.mips16
7616 && mips_opts
.noreorder
7617 && delayed_branch_p (&history
[0]))
7618 as_warn (_("extended instruction in delay slot"));
7620 if (mips_relax
.sequence
)
7622 /* If we've reached the end of this frag, turn it into a variant
7623 frag and record the information for the instructions we've
7625 if (frag_room () < 4)
7626 relax_close_frag ();
7627 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7630 if (mips_relax
.sequence
!= 2)
7632 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7633 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7634 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7635 mips_macro_warning
.insns
[0]++;
7637 if (mips_relax
.sequence
!= 1)
7639 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7640 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7641 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7642 mips_macro_warning
.insns
[1]++;
7645 if (mips_opts
.mips16
)
7648 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7650 add_fixed_insn (ip
);
7653 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7655 bfd_reloc_code_real_type final_type
[3];
7656 reloc_howto_type
*howto0
;
7657 reloc_howto_type
*howto
;
7660 /* Perform any necessary conversion to microMIPS relocations
7661 and find out how many relocations there actually are. */
7662 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7663 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7665 /* In a compound relocation, it is the final (outermost)
7666 operator that determines the relocated field. */
7667 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7672 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7673 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7674 bfd_get_reloc_size (howto
),
7676 howto0
&& howto0
->pc_relative
,
7678 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7679 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7681 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7682 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7683 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7685 /* These relocations can have an addend that won't fit in
7686 4 octets for 64bit assembly. */
7688 && ! howto
->partial_inplace
7689 && (reloc_type
[0] == BFD_RELOC_16
7690 || reloc_type
[0] == BFD_RELOC_32
7691 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7692 || reloc_type
[0] == BFD_RELOC_GPREL16
7693 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7694 || reloc_type
[0] == BFD_RELOC_GPREL32
7695 || reloc_type
[0] == BFD_RELOC_64
7696 || reloc_type
[0] == BFD_RELOC_CTOR
7697 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7698 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7699 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7700 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7701 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7702 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7703 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7704 || hi16_reloc_p (reloc_type
[0])
7705 || lo16_reloc_p (reloc_type
[0])))
7706 ip
->fixp
[0]->fx_no_overflow
= 1;
7708 /* These relocations can have an addend that won't fit in 2 octets. */
7709 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7710 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7711 ip
->fixp
[0]->fx_no_overflow
= 1;
7713 if (mips_relax
.sequence
)
7715 if (mips_relax
.first_fixup
== 0)
7716 mips_relax
.first_fixup
= ip
->fixp
[0];
7718 else if (reloc_needs_lo_p (*reloc_type
))
7720 struct mips_hi_fixup
*hi_fixup
;
7722 /* Reuse the last entry if it already has a matching %lo. */
7723 hi_fixup
= mips_hi_fixup_list
;
7725 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7727 hi_fixup
= XNEW (struct mips_hi_fixup
);
7728 hi_fixup
->next
= mips_hi_fixup_list
;
7729 mips_hi_fixup_list
= hi_fixup
;
7731 hi_fixup
->fixp
= ip
->fixp
[0];
7732 hi_fixup
->seg
= now_seg
;
7735 /* Add fixups for the second and third relocations, if given.
7736 Note that the ABI allows the second relocation to be
7737 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7738 moment we only use RSS_UNDEF, but we could add support
7739 for the others if it ever becomes necessary. */
7740 for (i
= 1; i
< 3; i
++)
7741 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7743 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7744 ip
->fixp
[0]->fx_size
, NULL
, 0,
7745 FALSE
, final_type
[i
]);
7747 /* Use fx_tcbit to mark compound relocs. */
7748 ip
->fixp
[0]->fx_tcbit
= 1;
7749 ip
->fixp
[i
]->fx_tcbit
= 1;
7753 /* Update the register mask information. */
7754 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7755 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7760 insert_into_history (0, 1, ip
);
7763 case APPEND_ADD_WITH_NOP
:
7765 struct mips_cl_insn
*nop
;
7767 insert_into_history (0, 1, ip
);
7768 nop
= get_delay_slot_nop (ip
);
7769 add_fixed_insn (nop
);
7770 insert_into_history (0, 1, nop
);
7771 if (mips_relax
.sequence
)
7772 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7776 case APPEND_ADD_COMPACT
:
7777 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7778 if (mips_opts
.mips16
)
7780 ip
->insn_opcode
|= 0x0080;
7781 find_altered_mips16_opcode (ip
);
7783 /* Convert microMIPS instructions. */
7784 else if (mips_opts
.micromips
)
7787 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7788 ip
->insn_opcode
|= 0x0020;
7790 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7791 ip
->insn_opcode
= 0x40e00000;
7792 /* beqz16->beqzc, bnez16->bnezc */
7793 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7795 unsigned long regno
;
7797 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7798 regno
&= MICROMIPSOP_MASK_MD
;
7799 regno
= micromips_to_32_reg_d_map
[regno
];
7800 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7801 | (regno
<< MICROMIPSOP_SH_RS
)
7802 | 0x40a00000) ^ 0x00400000;
7804 /* beqz->beqzc, bnez->bnezc */
7805 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7806 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7807 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7808 | 0x40a00000) ^ 0x00400000;
7809 /* beq $0->beqzc, bne $0->bnezc */
7810 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7811 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7812 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7813 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7814 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7815 | 0x40a00000) ^ 0x00400000;
7818 find_altered_micromips_opcode (ip
);
7823 insert_into_history (0, 1, ip
);
7828 struct mips_cl_insn delay
= history
[0];
7830 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7832 /* Add the delay slot instruction to the end of the
7833 current frag and shrink the fixed part of the
7834 original frag. If the branch occupies the tail of
7835 the latter, move it backwards to cover the gap. */
7836 delay
.frag
->fr_fix
-= branch_disp
;
7837 if (delay
.frag
== ip
->frag
)
7838 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7839 add_fixed_insn (&delay
);
7843 /* If this is not a relaxed branch and we are in the
7844 same frag, then just swap the instructions. */
7845 move_insn (ip
, delay
.frag
, delay
.where
);
7846 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7850 insert_into_history (0, 1, &delay
);
7855 /* If we have just completed an unconditional branch, clear the history. */
7856 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7857 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7861 mips_no_prev_insn ();
7863 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7864 history
[i
].cleared_p
= 1;
7867 /* We need to emit a label at the end of branch-likely macros. */
7868 if (emit_branch_likely_macro
)
7870 emit_branch_likely_macro
= FALSE
;
7871 micromips_add_label ();
7874 /* We just output an insn, so the next one doesn't have a label. */
7875 mips_clear_insn_labels ();
7878 /* Forget that there was any previous instruction or label.
7879 When BRANCH is true, the branch history is also flushed. */
7882 mips_no_prev_insn (void)
7884 prev_nop_frag
= NULL
;
7885 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7886 mips_clear_insn_labels ();
7889 /* This function must be called before we emit something other than
7890 instructions. It is like mips_no_prev_insn except that it inserts
7891 any NOPS that might be needed by previous instructions. */
7894 mips_emit_delays (void)
7896 if (! mips_opts
.noreorder
)
7898 int nops
= nops_for_insn (0, history
, NULL
);
7902 add_fixed_insn (NOP_INSN
);
7903 mips_move_text_labels ();
7906 mips_no_prev_insn ();
7909 /* Start a (possibly nested) noreorder block. */
7912 start_noreorder (void)
7914 if (mips_opts
.noreorder
== 0)
7919 /* None of the instructions before the .set noreorder can be moved. */
7920 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7921 history
[i
].fixed_p
= 1;
7923 /* Insert any nops that might be needed between the .set noreorder
7924 block and the previous instructions. We will later remove any
7925 nops that turn out not to be needed. */
7926 nops
= nops_for_insn (0, history
, NULL
);
7929 if (mips_optimize
!= 0)
7931 /* Record the frag which holds the nop instructions, so
7932 that we can remove them if we don't need them. */
7933 frag_grow (nops
* NOP_INSN_SIZE
);
7934 prev_nop_frag
= frag_now
;
7935 prev_nop_frag_holds
= nops
;
7936 prev_nop_frag_required
= 0;
7937 prev_nop_frag_since
= 0;
7940 for (; nops
> 0; --nops
)
7941 add_fixed_insn (NOP_INSN
);
7943 /* Move on to a new frag, so that it is safe to simply
7944 decrease the size of prev_nop_frag. */
7945 frag_wane (frag_now
);
7947 mips_move_text_labels ();
7949 mips_mark_labels ();
7950 mips_clear_insn_labels ();
7952 mips_opts
.noreorder
++;
7953 mips_any_noreorder
= 1;
7956 /* End a nested noreorder block. */
7959 end_noreorder (void)
7961 mips_opts
.noreorder
--;
7962 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7964 /* Commit to inserting prev_nop_frag_required nops and go back to
7965 handling nop insertion the .set reorder way. */
7966 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7968 insert_into_history (prev_nop_frag_since
,
7969 prev_nop_frag_required
, NOP_INSN
);
7970 prev_nop_frag
= NULL
;
7974 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7975 higher bits unset. */
7978 normalize_constant_expr (expressionS
*ex
)
7980 if (ex
->X_op
== O_constant
7981 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7982 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7986 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7987 all higher bits unset. */
7990 normalize_address_expr (expressionS
*ex
)
7992 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7993 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7994 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7995 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7999 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8000 Return true if the match was successful.
8002 OPCODE_EXTRA is a value that should be ORed into the opcode
8003 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8004 there are more alternatives after OPCODE and SOFT_MATCH is
8005 as for mips_arg_info. */
8008 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8009 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8010 bfd_boolean lax_match
, bfd_boolean complete_p
)
8013 struct mips_arg_info arg
;
8014 const struct mips_operand
*operand
;
8017 imm_expr
.X_op
= O_absent
;
8018 offset_expr
.X_op
= O_absent
;
8019 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8020 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8021 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8023 create_insn (insn
, opcode
);
8024 /* When no opcode suffix is specified, assume ".xyzw". */
8025 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8026 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8028 insn
->insn_opcode
|= opcode_extra
;
8029 memset (&arg
, 0, sizeof (arg
));
8033 arg
.last_regno
= ILLEGAL_REG
;
8034 arg
.dest_regno
= ILLEGAL_REG
;
8035 arg
.lax_match
= lax_match
;
8036 for (args
= opcode
->args
;; ++args
)
8038 if (arg
.token
->type
== OT_END
)
8040 /* Handle unary instructions in which only one operand is given.
8041 The source is then the same as the destination. */
8042 if (arg
.opnum
== 1 && *args
== ',')
8044 operand
= (mips_opts
.micromips
8045 ? decode_micromips_operand (args
+ 1)
8046 : decode_mips_operand (args
+ 1));
8047 if (operand
&& mips_optional_operand_p (operand
))
8055 /* Treat elided base registers as $0. */
8056 if (strcmp (args
, "(b)") == 0)
8064 /* The register suffix is optional. */
8069 /* Fail the match if there were too few operands. */
8073 /* Successful match. */
8076 clear_insn_error ();
8077 if (arg
.dest_regno
== arg
.last_regno
8078 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8082 (0, _("source and destination must be different"));
8083 else if (arg
.last_regno
== 31)
8085 (0, _("a destination register must be supplied"));
8087 else if (arg
.last_regno
== 31
8088 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8089 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8090 set_insn_error (0, _("the source register must not be $31"));
8091 check_completed_insn (&arg
);
8095 /* Fail the match if the line has too many operands. */
8099 /* Handle characters that need to match exactly. */
8100 if (*args
== '(' || *args
== ')' || *args
== ',')
8102 if (match_char (&arg
, *args
))
8109 if (arg
.token
->type
== OT_DOUBLE_CHAR
8110 && arg
.token
->u
.ch
== *args
)
8118 /* Handle special macro operands. Work out the properties of
8127 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8131 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8140 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8144 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8148 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8154 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8156 imm_expr
.X_op
= O_constant
;
8158 normalize_constant_expr (&imm_expr
);
8162 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8164 /* Assume that the offset has been elided and that what
8165 we saw was a base register. The match will fail later
8166 if that assumption turns out to be wrong. */
8167 offset_expr
.X_op
= O_constant
;
8168 offset_expr
.X_add_number
= 0;
8172 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8174 normalize_address_expr (&offset_expr
);
8179 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8185 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8191 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8197 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8203 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8207 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8211 gas_assert (mips_opts
.micromips
);
8217 if (!forced_insn_length
)
8218 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8220 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8222 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8228 operand
= (mips_opts
.micromips
8229 ? decode_micromips_operand (args
)
8230 : decode_mips_operand (args
));
8234 /* Skip prefixes. */
8235 if (*args
== '+' || *args
== 'm' || *args
== '-')
8238 if (mips_optional_operand_p (operand
)
8240 && (arg
.token
[0].type
!= OT_REG
8241 || arg
.token
[1].type
== OT_END
))
8243 /* Assume that the register has been elided and is the
8244 same as the first operand. */
8249 if (!match_operand (&arg
, operand
))
8254 /* Like match_insn, but for MIPS16. */
8257 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8258 struct mips_operand_token
*tokens
)
8261 const struct mips_operand
*operand
;
8262 const struct mips_operand
*ext_operand
;
8263 bfd_boolean pcrel
= FALSE
;
8264 int required_insn_length
;
8265 struct mips_arg_info arg
;
8268 if (forced_insn_length
)
8269 required_insn_length
= forced_insn_length
;
8270 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8271 required_insn_length
= 2;
8273 required_insn_length
= 0;
8275 create_insn (insn
, opcode
);
8276 imm_expr
.X_op
= O_absent
;
8277 offset_expr
.X_op
= O_absent
;
8278 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8279 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8280 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8283 memset (&arg
, 0, sizeof (arg
));
8287 arg
.last_regno
= ILLEGAL_REG
;
8288 arg
.dest_regno
= ILLEGAL_REG
;
8290 for (args
= opcode
->args
;; ++args
)
8294 if (arg
.token
->type
== OT_END
)
8298 /* Handle unary instructions in which only one operand is given.
8299 The source is then the same as the destination. */
8300 if (arg
.opnum
== 1 && *args
== ',')
8302 operand
= decode_mips16_operand (args
[1], FALSE
);
8303 if (operand
&& mips_optional_operand_p (operand
))
8311 /* Fail the match if there were too few operands. */
8315 /* Successful match. Stuff the immediate value in now, if
8317 clear_insn_error ();
8318 if (opcode
->pinfo
== INSN_MACRO
)
8320 gas_assert (relax_char
== 0 || relax_char
== 'p');
8321 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8324 && offset_expr
.X_op
== O_constant
8326 && calculate_reloc (*offset_reloc
,
8327 offset_expr
.X_add_number
,
8330 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8331 required_insn_length
, &insn
->insn_opcode
);
8332 offset_expr
.X_op
= O_absent
;
8333 *offset_reloc
= BFD_RELOC_UNUSED
;
8335 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8337 if (required_insn_length
== 2)
8338 set_insn_error (0, _("invalid unextended operand value"));
8339 else if (!mips_opcode_32bit_p (opcode
))
8341 forced_insn_length
= 4;
8342 insn
->insn_opcode
|= MIPS16_EXTEND
;
8345 else if (relax_char
)
8346 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8348 check_completed_insn (&arg
);
8352 /* Fail the match if the line has too many operands. */
8356 /* Handle characters that need to match exactly. */
8357 if (*args
== '(' || *args
== ')' || *args
== ',')
8359 if (match_char (&arg
, *args
))
8379 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8381 imm_expr
.X_op
= O_constant
;
8383 normalize_constant_expr (&imm_expr
);
8388 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8392 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8396 if (operand
->type
== OP_PCREL
)
8400 ext_operand
= decode_mips16_operand (c
, TRUE
);
8401 if (operand
!= ext_operand
)
8403 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8405 offset_expr
.X_op
= O_constant
;
8406 offset_expr
.X_add_number
= 0;
8411 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8414 /* '8' is used for SLTI(U) and has traditionally not
8415 been allowed to take relocation operators. */
8416 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8417 && (ext_operand
->size
!= 16 || c
== '8'))
8419 match_not_constant (&arg
);
8423 if (offset_expr
.X_op
== O_big
)
8425 match_out_of_range (&arg
);
8434 if (mips_optional_operand_p (operand
)
8436 && (arg
.token
[0].type
!= OT_REG
8437 || arg
.token
[1].type
== OT_END
))
8439 /* Assume that the register has been elided and is the
8440 same as the first operand. */
8445 if (!match_operand (&arg
, operand
))
8450 /* Record that the current instruction is invalid for the current ISA. */
8453 match_invalid_for_isa (void)
8456 (0, _("opcode not supported on this processor: %s (%s)"),
8457 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8458 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8461 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8462 Return true if a definite match or failure was found, storing any match
8463 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8464 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8465 tried and failed to match under normal conditions and now want to try a
8466 more relaxed match. */
8469 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8470 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8471 int opcode_extra
, bfd_boolean lax_match
)
8473 const struct mips_opcode
*opcode
;
8474 const struct mips_opcode
*invalid_delay_slot
;
8475 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8477 /* Search for a match, ignoring alternatives that don't satisfy the
8478 current ISA or forced_length. */
8479 invalid_delay_slot
= 0;
8480 seen_valid_for_isa
= FALSE
;
8481 seen_valid_for_size
= FALSE
;
8485 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8486 if (is_opcode_valid (opcode
))
8488 seen_valid_for_isa
= TRUE
;
8489 if (is_size_valid (opcode
))
8491 bfd_boolean delay_slot_ok
;
8493 seen_valid_for_size
= TRUE
;
8494 delay_slot_ok
= is_delay_slot_valid (opcode
);
8495 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8496 lax_match
, delay_slot_ok
))
8500 if (!invalid_delay_slot
)
8501 invalid_delay_slot
= opcode
;
8510 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8512 /* If the only matches we found had the wrong length for the delay slot,
8513 pick the first such match. We'll issue an appropriate warning later. */
8514 if (invalid_delay_slot
)
8516 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8522 /* Handle the case where we didn't try to match an instruction because
8523 all the alternatives were incompatible with the current ISA. */
8524 if (!seen_valid_for_isa
)
8526 match_invalid_for_isa ();
8530 /* Handle the case where we didn't try to match an instruction because
8531 all the alternatives were of the wrong size. */
8532 if (!seen_valid_for_size
)
8534 if (mips_opts
.insn32
)
8535 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8538 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8539 8 * forced_insn_length
);
8546 /* Like match_insns, but for MIPS16. */
8549 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8550 struct mips_operand_token
*tokens
)
8552 const struct mips_opcode
*opcode
;
8553 bfd_boolean seen_valid_for_isa
;
8554 bfd_boolean seen_valid_for_size
;
8556 /* Search for a match, ignoring alternatives that don't satisfy the
8557 current ISA. There are no separate entries for extended forms so
8558 we deal with forced_length later. */
8559 seen_valid_for_isa
= FALSE
;
8560 seen_valid_for_size
= FALSE
;
8564 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8565 if (is_opcode_valid_16 (opcode
))
8567 seen_valid_for_isa
= TRUE
;
8568 if (is_size_valid_16 (opcode
))
8570 seen_valid_for_size
= TRUE
;
8571 if (match_mips16_insn (insn
, opcode
, tokens
))
8577 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8578 && strcmp (opcode
->name
, first
->name
) == 0);
8580 /* Handle the case where we didn't try to match an instruction because
8581 all the alternatives were incompatible with the current ISA. */
8582 if (!seen_valid_for_isa
)
8584 match_invalid_for_isa ();
8588 /* Handle the case where we didn't try to match an instruction because
8589 all the alternatives were of the wrong size. */
8590 if (!seen_valid_for_size
)
8592 if (forced_insn_length
== 2)
8594 (0, _("unrecognized unextended version of MIPS16 opcode"));
8597 (0, _("unrecognized extended version of MIPS16 opcode"));
8604 /* Set up global variables for the start of a new macro. */
8609 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8610 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8611 sizeof (mips_macro_warning
.first_insn_sizes
));
8612 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8613 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8614 && delayed_branch_p (&history
[0]));
8616 && history
[0].frag
->fr_type
== rs_machine_dependent
8617 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8618 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8619 mips_macro_warning
.delay_slot_length
= 0;
8621 switch (history
[0].insn_mo
->pinfo2
8622 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8624 case INSN2_BRANCH_DELAY_32BIT
:
8625 mips_macro_warning
.delay_slot_length
= 4;
8627 case INSN2_BRANCH_DELAY_16BIT
:
8628 mips_macro_warning
.delay_slot_length
= 2;
8631 mips_macro_warning
.delay_slot_length
= 0;
8634 mips_macro_warning
.first_frag
= NULL
;
8637 /* Given that a macro is longer than one instruction or of the wrong size,
8638 return the appropriate warning for it. Return null if no warning is
8639 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8640 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8641 and RELAX_NOMACRO. */
8644 macro_warning (relax_substateT subtype
)
8646 if (subtype
& RELAX_DELAY_SLOT
)
8647 return _("macro instruction expanded into multiple instructions"
8648 " in a branch delay slot");
8649 else if (subtype
& RELAX_NOMACRO
)
8650 return _("macro instruction expanded into multiple instructions");
8651 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8652 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8653 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8654 ? _("macro instruction expanded into a wrong size instruction"
8655 " in a 16-bit branch delay slot")
8656 : _("macro instruction expanded into a wrong size instruction"
8657 " in a 32-bit branch delay slot"));
8662 /* Finish up a macro. Emit warnings as appropriate. */
8667 /* Relaxation warning flags. */
8668 relax_substateT subtype
= 0;
8670 /* Check delay slot size requirements. */
8671 if (mips_macro_warning
.delay_slot_length
== 2)
8672 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8673 if (mips_macro_warning
.delay_slot_length
!= 0)
8675 if (mips_macro_warning
.delay_slot_length
8676 != mips_macro_warning
.first_insn_sizes
[0])
8677 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8678 if (mips_macro_warning
.delay_slot_length
8679 != mips_macro_warning
.first_insn_sizes
[1])
8680 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8683 /* Check instruction count requirements. */
8684 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8686 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8687 subtype
|= RELAX_SECOND_LONGER
;
8688 if (mips_opts
.warn_about_macros
)
8689 subtype
|= RELAX_NOMACRO
;
8690 if (mips_macro_warning
.delay_slot_p
)
8691 subtype
|= RELAX_DELAY_SLOT
;
8694 /* If both alternatives fail to fill a delay slot correctly,
8695 emit the warning now. */
8696 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8697 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8702 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8703 | RELAX_DELAY_SLOT_SIZE_FIRST
8704 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8705 msg
= macro_warning (s
);
8707 as_warn ("%s", msg
);
8711 /* If both implementations are longer than 1 instruction, then emit the
8713 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8718 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8719 msg
= macro_warning (s
);
8721 as_warn ("%s", msg
);
8725 /* If any flags still set, then one implementation might need a warning
8726 and the other either will need one of a different kind or none at all.
8727 Pass any remaining flags over to relaxation. */
8728 if (mips_macro_warning
.first_frag
!= NULL
)
8729 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8732 /* Instruction operand formats used in macros that vary between
8733 standard MIPS and microMIPS code. */
8735 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8736 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8737 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8738 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8739 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8740 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8741 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8742 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8744 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8745 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8746 : cop12_fmt[mips_opts.micromips])
8747 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8748 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8749 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8750 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8751 : mem12_fmt[mips_opts.micromips])
8752 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8753 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8754 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8756 /* Read a macro's relocation codes from *ARGS and store them in *R.
8757 The first argument in *ARGS will be either the code for a single
8758 relocation or -1 followed by the three codes that make up a
8759 composite relocation. */
8762 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8766 next
= va_arg (*args
, int);
8768 r
[0] = (bfd_reloc_code_real_type
) next
;
8771 for (i
= 0; i
< 3; i
++)
8772 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8773 /* This function is only used for 16-bit relocation fields.
8774 To make the macro code simpler, treat an unrelocated value
8775 in the same way as BFD_RELOC_LO16. */
8776 if (r
[0] == BFD_RELOC_UNUSED
)
8777 r
[0] = BFD_RELOC_LO16
;
8781 /* Build an instruction created by a macro expansion. This is passed
8782 a pointer to the count of instructions created so far, an
8783 expression, the name of the instruction to build, an operand format
8784 string, and corresponding arguments. */
8787 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8789 const struct mips_opcode
*mo
= NULL
;
8790 bfd_reloc_code_real_type r
[3];
8791 const struct mips_opcode
*amo
;
8792 const struct mips_operand
*operand
;
8793 struct hash_control
*hash
;
8794 struct mips_cl_insn insn
;
8798 va_start (args
, fmt
);
8800 if (mips_opts
.mips16
)
8802 mips16_macro_build (ep
, name
, fmt
, &args
);
8807 r
[0] = BFD_RELOC_UNUSED
;
8808 r
[1] = BFD_RELOC_UNUSED
;
8809 r
[2] = BFD_RELOC_UNUSED
;
8810 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8811 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8813 gas_assert (strcmp (name
, amo
->name
) == 0);
8817 /* Search until we get a match for NAME. It is assumed here that
8818 macros will never generate MDMX, MIPS-3D, or MT instructions.
8819 We try to match an instruction that fulfills the branch delay
8820 slot instruction length requirement (if any) of the previous
8821 instruction. While doing this we record the first instruction
8822 seen that matches all the other conditions and use it anyway
8823 if the requirement cannot be met; we will issue an appropriate
8824 warning later on. */
8825 if (strcmp (fmt
, amo
->args
) == 0
8826 && amo
->pinfo
!= INSN_MACRO
8827 && is_opcode_valid (amo
)
8828 && is_size_valid (amo
))
8830 if (is_delay_slot_valid (amo
))
8840 gas_assert (amo
->name
);
8842 while (strcmp (name
, amo
->name
) == 0);
8845 create_insn (&insn
, mo
);
8858 macro_read_relocs (&args
, r
);
8859 gas_assert (*r
== BFD_RELOC_GPREL16
8860 || *r
== BFD_RELOC_MIPS_HIGHER
8861 || *r
== BFD_RELOC_HI16_S
8862 || *r
== BFD_RELOC_LO16
8863 || *r
== BFD_RELOC_MIPS_GOT_OFST
8864 || (mips_opts
.micromips
8865 && (*r
== BFD_RELOC_16
8866 || *r
== BFD_RELOC_MIPS_GOT16
8867 || *r
== BFD_RELOC_MIPS_CALL16
8868 || *r
== BFD_RELOC_MIPS_GOT_HI16
8869 || *r
== BFD_RELOC_MIPS_GOT_LO16
8870 || *r
== BFD_RELOC_MIPS_CALL_HI16
8871 || *r
== BFD_RELOC_MIPS_CALL_LO16
8872 || *r
== BFD_RELOC_MIPS_SUB
8873 || *r
== BFD_RELOC_MIPS_GOT_PAGE
8874 || *r
== BFD_RELOC_MIPS_HIGHEST
8875 || *r
== BFD_RELOC_MIPS_GOT_DISP
8876 || *r
== BFD_RELOC_MIPS_TLS_GD
8877 || *r
== BFD_RELOC_MIPS_TLS_LDM
8878 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
8879 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
8880 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
8881 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
8882 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
8886 macro_read_relocs (&args
, r
);
8890 macro_read_relocs (&args
, r
);
8891 gas_assert (ep
!= NULL
8892 && (ep
->X_op
== O_constant
8893 || (ep
->X_op
== O_symbol
8894 && (*r
== BFD_RELOC_MIPS_HIGHEST
8895 || *r
== BFD_RELOC_HI16_S
8896 || *r
== BFD_RELOC_HI16
8897 || *r
== BFD_RELOC_GPREL16
8898 || *r
== BFD_RELOC_MIPS_GOT_HI16
8899 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8903 gas_assert (ep
!= NULL
);
8906 * This allows macro() to pass an immediate expression for
8907 * creating short branches without creating a symbol.
8909 * We don't allow branch relaxation for these branches, as
8910 * they should only appear in ".set nomacro" anyway.
8912 if (ep
->X_op
== O_constant
)
8914 /* For microMIPS we always use relocations for branches.
8915 So we should not resolve immediate values. */
8916 gas_assert (!mips_opts
.micromips
);
8918 if ((ep
->X_add_number
& 3) != 0)
8919 as_bad (_("branch to misaligned address (0x%lx)"),
8920 (unsigned long) ep
->X_add_number
);
8921 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8922 as_bad (_("branch address range overflow (0x%lx)"),
8923 (unsigned long) ep
->X_add_number
);
8924 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8928 *r
= BFD_RELOC_16_PCREL_S2
;
8932 gas_assert (ep
!= NULL
);
8933 *r
= BFD_RELOC_MIPS_JMP
;
8937 operand
= (mips_opts
.micromips
8938 ? decode_micromips_operand (fmt
)
8939 : decode_mips_operand (fmt
));
8943 uval
= va_arg (args
, int);
8944 if (operand
->type
== OP_CLO_CLZ_DEST
)
8945 uval
|= (uval
<< 5);
8946 insn_insert_operand (&insn
, operand
, uval
);
8948 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8954 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8956 append_insn (&insn
, ep
, r
, TRUE
);
8960 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8963 struct mips_opcode
*mo
;
8964 struct mips_cl_insn insn
;
8965 const struct mips_operand
*operand
;
8966 bfd_reloc_code_real_type r
[3]
8967 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8969 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8971 gas_assert (strcmp (name
, mo
->name
) == 0);
8973 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8976 gas_assert (mo
->name
);
8977 gas_assert (strcmp (name
, mo
->name
) == 0);
8980 create_insn (&insn
, mo
);
9017 gas_assert (ep
!= NULL
);
9019 if (ep
->X_op
!= O_constant
)
9020 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9021 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9023 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9025 *r
= BFD_RELOC_UNUSED
;
9031 operand
= decode_mips16_operand (c
, FALSE
);
9035 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9040 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9042 append_insn (&insn
, ep
, r
, TRUE
);
9046 * Generate a "jalr" instruction with a relocation hint to the called
9047 * function. This occurs in NewABI PIC code.
9050 macro_build_jalr (expressionS
*ep
, int cprestore
)
9052 static const bfd_reloc_code_real_type jalr_relocs
[2]
9053 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9054 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9058 if (MIPS_JALR_HINT_P (ep
))
9063 if (mips_opts
.micromips
)
9065 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9066 ? "jalr" : "jalrs");
9067 if (MIPS_JALR_HINT_P (ep
)
9069 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9070 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9072 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9075 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9076 if (MIPS_JALR_HINT_P (ep
))
9077 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9081 * Generate a "lui" instruction.
9084 macro_build_lui (expressionS
*ep
, int regnum
)
9086 gas_assert (! mips_opts
.mips16
);
9088 if (ep
->X_op
!= O_constant
)
9090 gas_assert (ep
->X_op
== O_symbol
);
9091 /* _gp_disp is a special case, used from s_cpload.
9092 __gnu_local_gp is used if mips_no_shared. */
9093 gas_assert (mips_pic
== NO_PIC
9095 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9096 || (! mips_in_shared
9097 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9098 "__gnu_local_gp") == 0));
9101 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9104 /* Generate a sequence of instructions to do a load or store from a constant
9105 offset off of a base register (breg) into/from a target register (treg),
9106 using AT if necessary. */
9108 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9109 int treg
, int breg
, int dbl
)
9111 gas_assert (ep
->X_op
== O_constant
);
9113 /* Sign-extending 32-bit constants makes their handling easier. */
9115 normalize_constant_expr (ep
);
9117 /* Right now, this routine can only handle signed 32-bit constants. */
9118 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9119 as_warn (_("operand overflow"));
9121 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9123 /* Signed 16-bit offset will fit in the op. Easy! */
9124 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9128 /* 32-bit offset, need multiple instructions and AT, like:
9129 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9130 addu $tempreg,$tempreg,$breg
9131 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9132 to handle the complete offset. */
9133 macro_build_lui (ep
, AT
);
9134 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9135 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9138 as_bad (_("macro used $at after \".set noat\""));
9143 * Generates code to set the $at register to true (one)
9144 * if reg is less than the immediate expression.
9147 set_at (int reg
, int unsignedp
)
9149 if (imm_expr
.X_add_number
>= -0x8000
9150 && imm_expr
.X_add_number
< 0x8000)
9151 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9152 AT
, reg
, BFD_RELOC_LO16
);
9155 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9156 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9160 /* Count the leading zeroes by performing a binary chop. This is a
9161 bulky bit of source, but performance is a LOT better for the
9162 majority of values than a simple loop to count the bits:
9163 for (lcnt = 0; (lcnt < 32); lcnt++)
9164 if ((v) & (1 << (31 - lcnt)))
9166 However it is not code size friendly, and the gain will drop a bit
9167 on certain cached systems.
9169 #define COUNT_TOP_ZEROES(v) \
9170 (((v) & ~0xffff) == 0 \
9171 ? ((v) & ~0xff) == 0 \
9172 ? ((v) & ~0xf) == 0 \
9173 ? ((v) & ~0x3) == 0 \
9174 ? ((v) & ~0x1) == 0 \
9179 : ((v) & ~0x7) == 0 \
9182 : ((v) & ~0x3f) == 0 \
9183 ? ((v) & ~0x1f) == 0 \
9186 : ((v) & ~0x7f) == 0 \
9189 : ((v) & ~0xfff) == 0 \
9190 ? ((v) & ~0x3ff) == 0 \
9191 ? ((v) & ~0x1ff) == 0 \
9194 : ((v) & ~0x7ff) == 0 \
9197 : ((v) & ~0x3fff) == 0 \
9198 ? ((v) & ~0x1fff) == 0 \
9201 : ((v) & ~0x7fff) == 0 \
9204 : ((v) & ~0xffffff) == 0 \
9205 ? ((v) & ~0xfffff) == 0 \
9206 ? ((v) & ~0x3ffff) == 0 \
9207 ? ((v) & ~0x1ffff) == 0 \
9210 : ((v) & ~0x7ffff) == 0 \
9213 : ((v) & ~0x3fffff) == 0 \
9214 ? ((v) & ~0x1fffff) == 0 \
9217 : ((v) & ~0x7fffff) == 0 \
9220 : ((v) & ~0xfffffff) == 0 \
9221 ? ((v) & ~0x3ffffff) == 0 \
9222 ? ((v) & ~0x1ffffff) == 0 \
9225 : ((v) & ~0x7ffffff) == 0 \
9228 : ((v) & ~0x3fffffff) == 0 \
9229 ? ((v) & ~0x1fffffff) == 0 \
9232 : ((v) & ~0x7fffffff) == 0 \
9237 * This routine generates the least number of instructions necessary to load
9238 * an absolute expression value into a register.
9241 load_register (int reg
, expressionS
*ep
, int dbl
)
9244 expressionS hi32
, lo32
;
9246 if (ep
->X_op
!= O_big
)
9248 gas_assert (ep
->X_op
== O_constant
);
9250 /* Sign-extending 32-bit constants makes their handling easier. */
9252 normalize_constant_expr (ep
);
9254 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9256 /* We can handle 16 bit signed values with an addiu to
9257 $zero. No need to ever use daddiu here, since $zero and
9258 the result are always correct in 32 bit mode. */
9259 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9262 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9264 /* We can handle 16 bit unsigned values with an ori to
9266 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9269 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9271 /* 32 bit values require an lui. */
9272 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9273 if ((ep
->X_add_number
& 0xffff) != 0)
9274 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9279 /* The value is larger than 32 bits. */
9281 if (!dbl
|| GPR_SIZE
== 32)
9285 sprintf_vma (value
, ep
->X_add_number
);
9286 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9287 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9291 if (ep
->X_op
!= O_big
)
9294 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9295 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9296 hi32
.X_add_number
&= 0xffffffff;
9298 lo32
.X_add_number
&= 0xffffffff;
9302 gas_assert (ep
->X_add_number
> 2);
9303 if (ep
->X_add_number
== 3)
9304 generic_bignum
[3] = 0;
9305 else if (ep
->X_add_number
> 4)
9306 as_bad (_("number larger than 64 bits"));
9307 lo32
.X_op
= O_constant
;
9308 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9309 hi32
.X_op
= O_constant
;
9310 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9313 if (hi32
.X_add_number
== 0)
9318 unsigned long hi
, lo
;
9320 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9322 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9324 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9327 if (lo32
.X_add_number
& 0x80000000)
9329 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9330 if (lo32
.X_add_number
& 0xffff)
9331 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9336 /* Check for 16bit shifted constant. We know that hi32 is
9337 non-zero, so start the mask on the first bit of the hi32
9342 unsigned long himask
, lomask
;
9346 himask
= 0xffff >> (32 - shift
);
9347 lomask
= (0xffff << shift
) & 0xffffffff;
9351 himask
= 0xffff << (shift
- 32);
9354 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9355 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9359 tmp
.X_op
= O_constant
;
9361 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9362 | (lo32
.X_add_number
>> shift
));
9364 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9365 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9366 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9367 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9372 while (shift
<= (64 - 16));
9374 /* Find the bit number of the lowest one bit, and store the
9375 shifted value in hi/lo. */
9376 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9377 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9381 while ((lo
& 1) == 0)
9386 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9392 while ((hi
& 1) == 0)
9401 /* Optimize if the shifted value is a (power of 2) - 1. */
9402 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9403 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9405 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9410 /* This instruction will set the register to be all
9412 tmp
.X_op
= O_constant
;
9413 tmp
.X_add_number
= (offsetT
) -1;
9414 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9418 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9419 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9421 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9422 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9427 /* Sign extend hi32 before calling load_register, because we can
9428 generally get better code when we load a sign extended value. */
9429 if ((hi32
.X_add_number
& 0x80000000) != 0)
9430 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9431 load_register (reg
, &hi32
, 0);
9434 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9438 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9446 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9448 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9449 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9455 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9459 mid16
.X_add_number
>>= 16;
9460 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9461 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9464 if ((lo32
.X_add_number
& 0xffff) != 0)
9465 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9469 load_delay_nop (void)
9471 if (!gpr_interlocks
)
9472 macro_build (NULL
, "nop", "");
9475 /* Load an address into a register. */
9478 load_address (int reg
, expressionS
*ep
, int *used_at
)
9480 if (ep
->X_op
!= O_constant
9481 && ep
->X_op
!= O_symbol
)
9483 as_bad (_("expression too complex"));
9484 ep
->X_op
= O_constant
;
9487 if (ep
->X_op
== O_constant
)
9489 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9493 if (mips_pic
== NO_PIC
)
9495 /* If this is a reference to a GP relative symbol, we want
9496 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9498 lui $reg,<sym> (BFD_RELOC_HI16_S)
9499 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9500 If we have an addend, we always use the latter form.
9502 With 64bit address space and a usable $at we want
9503 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9504 lui $at,<sym> (BFD_RELOC_HI16_S)
9505 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9506 daddiu $at,<sym> (BFD_RELOC_LO16)
9510 If $at is already in use, we use a path which is suboptimal
9511 on superscalar processors.
9512 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9513 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9515 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9517 daddiu $reg,<sym> (BFD_RELOC_LO16)
9519 For GP relative symbols in 64bit address space we can use
9520 the same sequence as in 32bit address space. */
9521 if (HAVE_64BIT_SYMBOLS
)
9523 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9524 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9526 relax_start (ep
->X_add_symbol
);
9527 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9528 mips_gp_register
, BFD_RELOC_GPREL16
);
9532 if (*used_at
== 0 && mips_opts
.at
)
9534 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9535 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9536 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9537 BFD_RELOC_MIPS_HIGHER
);
9538 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9539 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9540 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9545 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9546 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9547 BFD_RELOC_MIPS_HIGHER
);
9548 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9549 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9550 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9551 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9554 if (mips_relax
.sequence
)
9559 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9560 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9562 relax_start (ep
->X_add_symbol
);
9563 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9564 mips_gp_register
, BFD_RELOC_GPREL16
);
9567 macro_build_lui (ep
, reg
);
9568 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9569 reg
, reg
, BFD_RELOC_LO16
);
9570 if (mips_relax
.sequence
)
9574 else if (!mips_big_got
)
9578 /* If this is a reference to an external symbol, we want
9579 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9581 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9583 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9584 If there is a constant, it must be added in after.
9586 If we have NewABI, we want
9587 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9588 unless we're referencing a global symbol with a non-zero
9589 offset, in which case cst must be added separately. */
9592 if (ep
->X_add_number
)
9594 ex
.X_add_number
= ep
->X_add_number
;
9595 ep
->X_add_number
= 0;
9596 relax_start (ep
->X_add_symbol
);
9597 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9598 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9599 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9600 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9601 ex
.X_op
= O_constant
;
9602 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9603 reg
, reg
, BFD_RELOC_LO16
);
9604 ep
->X_add_number
= ex
.X_add_number
;
9607 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9608 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9609 if (mips_relax
.sequence
)
9614 ex
.X_add_number
= ep
->X_add_number
;
9615 ep
->X_add_number
= 0;
9616 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9617 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9619 relax_start (ep
->X_add_symbol
);
9621 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9625 if (ex
.X_add_number
!= 0)
9627 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9628 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9629 ex
.X_op
= O_constant
;
9630 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9631 reg
, reg
, BFD_RELOC_LO16
);
9635 else if (mips_big_got
)
9639 /* This is the large GOT case. If this is a reference to an
9640 external symbol, we want
9641 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9643 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9645 Otherwise, for a reference to a local symbol in old ABI, we want
9646 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9648 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9649 If there is a constant, it must be added in after.
9651 In the NewABI, for local symbols, with or without offsets, we want:
9652 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9653 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9657 ex
.X_add_number
= ep
->X_add_number
;
9658 ep
->X_add_number
= 0;
9659 relax_start (ep
->X_add_symbol
);
9660 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9661 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9662 reg
, reg
, mips_gp_register
);
9663 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9664 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9665 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9666 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9667 else if (ex
.X_add_number
)
9669 ex
.X_op
= O_constant
;
9670 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9674 ep
->X_add_number
= ex
.X_add_number
;
9676 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9677 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9678 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9679 BFD_RELOC_MIPS_GOT_OFST
);
9684 ex
.X_add_number
= ep
->X_add_number
;
9685 ep
->X_add_number
= 0;
9686 relax_start (ep
->X_add_symbol
);
9687 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9688 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9689 reg
, reg
, mips_gp_register
);
9690 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9691 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9693 if (reg_needs_delay (mips_gp_register
))
9695 /* We need a nop before loading from $gp. This special
9696 check is required because the lui which starts the main
9697 instruction stream does not refer to $gp, and so will not
9698 insert the nop which may be required. */
9699 macro_build (NULL
, "nop", "");
9701 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9702 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9704 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9708 if (ex
.X_add_number
!= 0)
9710 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9711 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9712 ex
.X_op
= O_constant
;
9713 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9721 if (!mips_opts
.at
&& *used_at
== 1)
9722 as_bad (_("macro used $at after \".set noat\""));
9725 /* Move the contents of register SOURCE into register DEST. */
9728 move_register (int dest
, int source
)
9730 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9731 instruction specifically requires a 32-bit one. */
9732 if (mips_opts
.micromips
9733 && !mips_opts
.insn32
9734 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9735 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9737 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9740 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9741 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9742 The two alternatives are:
9744 Global symbol Local symbol
9745 ------------- ------------
9746 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9748 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9750 load_got_offset emits the first instruction and add_got_offset
9751 emits the second for a 16-bit offset or add_got_offset_hilo emits
9752 a sequence to add a 32-bit offset using a scratch register. */
9755 load_got_offset (int dest
, expressionS
*local
)
9760 global
.X_add_number
= 0;
9762 relax_start (local
->X_add_symbol
);
9763 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9764 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9766 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9767 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9772 add_got_offset (int dest
, expressionS
*local
)
9776 global
.X_op
= O_constant
;
9777 global
.X_op_symbol
= NULL
;
9778 global
.X_add_symbol
= NULL
;
9779 global
.X_add_number
= local
->X_add_number
;
9781 relax_start (local
->X_add_symbol
);
9782 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9783 dest
, dest
, BFD_RELOC_LO16
);
9785 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9790 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9793 int hold_mips_optimize
;
9795 global
.X_op
= O_constant
;
9796 global
.X_op_symbol
= NULL
;
9797 global
.X_add_symbol
= NULL
;
9798 global
.X_add_number
= local
->X_add_number
;
9800 relax_start (local
->X_add_symbol
);
9801 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9803 /* Set mips_optimize around the lui instruction to avoid
9804 inserting an unnecessary nop after the lw. */
9805 hold_mips_optimize
= mips_optimize
;
9807 macro_build_lui (&global
, tmp
);
9808 mips_optimize
= hold_mips_optimize
;
9809 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9812 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9815 /* Emit a sequence of instructions to emulate a branch likely operation.
9816 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9817 is its complementing branch with the original condition negated.
9818 CALL is set if the original branch specified the link operation.
9819 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9821 Code like this is produced in the noreorder mode:
9826 delay slot (executed only if branch taken)
9834 delay slot (executed only if branch taken)
9837 In the reorder mode the delay slot would be filled with a nop anyway,
9838 so code produced is simply:
9843 This function is used when producing code for the microMIPS ASE that
9844 does not implement branch likely instructions in hardware. */
9847 macro_build_branch_likely (const char *br
, const char *brneg
,
9848 int call
, expressionS
*ep
, const char *fmt
,
9849 unsigned int sreg
, unsigned int treg
)
9851 int noreorder
= mips_opts
.noreorder
;
9854 gas_assert (mips_opts
.micromips
);
9858 micromips_label_expr (&expr1
);
9859 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9860 macro_build (NULL
, "nop", "");
9861 macro_build (ep
, call
? "bal" : "b", "p");
9863 /* Set to true so that append_insn adds a label. */
9864 emit_branch_likely_macro
= TRUE
;
9868 macro_build (ep
, br
, fmt
, sreg
, treg
);
9869 macro_build (NULL
, "nop", "");
9874 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9875 the condition code tested. EP specifies the branch target. */
9878 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9905 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9908 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9909 the register tested. EP specifies the branch target. */
9912 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9914 const char *brneg
= NULL
;
9924 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9928 gas_assert (mips_opts
.micromips
);
9929 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9937 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9944 br
= mips_opts
.micromips
? "blez" : "blezl";
9951 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9955 gas_assert (mips_opts
.micromips
);
9956 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9963 if (mips_opts
.micromips
&& brneg
)
9964 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9966 macro_build (ep
, br
, "s,p", sreg
);
9969 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9970 TREG as the registers tested. EP specifies the branch target. */
9973 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9974 unsigned int sreg
, unsigned int treg
)
9976 const char *brneg
= NULL
;
9988 br
= mips_opts
.micromips
? "beq" : "beql";
9997 br
= mips_opts
.micromips
? "bne" : "bnel";
10003 if (mips_opts
.micromips
&& brneg
)
10004 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10006 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10009 /* Return the high part that should be loaded in order to make the low
10010 part of VALUE accessible using an offset of OFFBITS bits. */
10013 offset_high_part (offsetT value
, unsigned int offbits
)
10020 bias
= 1 << (offbits
- 1);
10021 low_mask
= bias
* 2 - 1;
10022 return (value
+ bias
) & ~low_mask
;
10025 /* Return true if the value stored in offset_expr and offset_reloc
10026 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10027 amount that the caller wants to add without inducing overflow
10028 and ALIGN is the known alignment of the value in bytes. */
10031 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10035 /* Accept any relocation operator if overflow isn't a concern. */
10036 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10039 /* These relocations are guaranteed not to overflow in correct links. */
10040 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10041 || gprel16_reloc_p (*offset_reloc
))
10044 if (offset_expr
.X_op
== O_constant
10045 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10046 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10053 * This routine implements the seemingly endless macro or synthesized
10054 * instructions and addressing modes in the mips assembly language. Many
10055 * of these macros are simple and are similar to each other. These could
10056 * probably be handled by some kind of table or grammar approach instead of
10057 * this verbose method. Others are not simple macros but are more like
10058 * optimizing code generation.
10059 * One interesting optimization is when several store macros appear
10060 * consecutively that would load AT with the upper half of the same address.
10061 * The ensuing load upper instructions are omitted. This implies some kind
10062 * of global optimization. We currently only optimize within a single macro.
10063 * For many of the load and store macros if the address is specified as a
10064 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10065 * first load register 'at' with zero and use it as the base register. The
10066 * mips assembler simply uses register $zero. Just one tiny optimization
10070 macro (struct mips_cl_insn
*ip
, char *str
)
10072 const struct mips_operand_array
*operands
;
10073 unsigned int breg
, i
;
10074 unsigned int tempreg
;
10077 expressionS label_expr
;
10092 bfd_boolean large_offset
;
10094 int hold_mips_optimize
;
10095 unsigned int align
;
10096 unsigned int op
[MAX_OPERANDS
];
10098 gas_assert (! mips_opts
.mips16
);
10100 operands
= insn_operands (ip
);
10101 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10102 if (operands
->operand
[i
])
10103 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10107 mask
= ip
->insn_mo
->mask
;
10109 label_expr
.X_op
= O_constant
;
10110 label_expr
.X_op_symbol
= NULL
;
10111 label_expr
.X_add_symbol
= NULL
;
10112 label_expr
.X_add_number
= 0;
10114 expr1
.X_op
= O_constant
;
10115 expr1
.X_op_symbol
= NULL
;
10116 expr1
.X_add_symbol
= NULL
;
10117 expr1
.X_add_number
= 1;
10124 /* Fall through. */
10132 start_noreorder ();
10134 if (mips_opts
.micromips
)
10135 micromips_label_expr (&label_expr
);
10137 label_expr
.X_add_number
= 8;
10138 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10139 if (op
[0] == op
[1])
10140 macro_build (NULL
, "nop", "");
10142 move_register (op
[0], op
[1]);
10143 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10144 if (mips_opts
.micromips
)
10145 micromips_add_label ();
10162 if (!mips_opts
.micromips
)
10164 if (imm_expr
.X_add_number
>= -0x200
10165 && imm_expr
.X_add_number
< 0x200)
10167 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10168 (int) imm_expr
.X_add_number
);
10177 if (imm_expr
.X_add_number
>= -0x8000
10178 && imm_expr
.X_add_number
< 0x8000)
10180 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10185 load_register (AT
, &imm_expr
, dbl
);
10186 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10205 if (imm_expr
.X_add_number
>= 0
10206 && imm_expr
.X_add_number
< 0x10000)
10208 if (mask
!= M_NOR_I
)
10209 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10212 macro_build (&imm_expr
, "ori", "t,r,i",
10213 op
[0], op
[1], BFD_RELOC_LO16
);
10214 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10220 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10221 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10225 switch (imm_expr
.X_add_number
)
10228 macro_build (NULL
, "nop", "");
10231 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10235 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10236 (int) imm_expr
.X_add_number
);
10239 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10240 (unsigned long) imm_expr
.X_add_number
);
10249 gas_assert (mips_opts
.micromips
);
10250 macro_build_branch_ccl (mask
, &offset_expr
,
10251 EXTRACT_OPERAND (1, BCC
, *ip
));
10258 if (imm_expr
.X_add_number
== 0)
10264 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10266 /* Fall through. */
10269 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10274 /* Fall through. */
10277 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10278 else if (op
[0] == 0)
10279 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10283 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10284 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10285 &offset_expr
, AT
, ZERO
);
10295 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10300 /* Fall through. */
10302 /* Check for > max integer. */
10303 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10306 /* Result is always false. */
10308 macro_build (NULL
, "nop", "");
10310 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10313 ++imm_expr
.X_add_number
;
10317 if (mask
== M_BGEL_I
)
10319 if (imm_expr
.X_add_number
== 0)
10321 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10322 &offset_expr
, op
[0]);
10325 if (imm_expr
.X_add_number
== 1)
10327 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10328 &offset_expr
, op
[0]);
10331 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10334 /* result is always true */
10335 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10336 macro_build (&offset_expr
, "b", "p");
10341 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10342 &offset_expr
, AT
, ZERO
);
10347 /* Fall through. */
10351 else if (op
[0] == 0)
10352 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10353 &offset_expr
, ZERO
, op
[1]);
10357 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10358 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10359 &offset_expr
, AT
, ZERO
);
10365 /* Fall through. */
10369 && imm_expr
.X_add_number
== -1))
10371 ++imm_expr
.X_add_number
;
10375 if (mask
== M_BGEUL_I
)
10377 if (imm_expr
.X_add_number
== 0)
10379 else if (imm_expr
.X_add_number
== 1)
10380 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10381 &offset_expr
, op
[0], ZERO
);
10386 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10387 &offset_expr
, AT
, ZERO
);
10393 /* Fall through. */
10396 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10397 else if (op
[0] == 0)
10398 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10402 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10403 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10404 &offset_expr
, AT
, ZERO
);
10410 /* Fall through. */
10413 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10414 &offset_expr
, op
[0], ZERO
);
10415 else if (op
[0] == 0)
10420 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10421 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10422 &offset_expr
, AT
, ZERO
);
10428 /* Fall through. */
10431 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10432 else if (op
[0] == 0)
10433 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10437 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10438 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10439 &offset_expr
, AT
, ZERO
);
10445 /* Fall through. */
10447 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10449 ++imm_expr
.X_add_number
;
10453 if (mask
== M_BLTL_I
)
10455 if (imm_expr
.X_add_number
== 0)
10456 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10457 else if (imm_expr
.X_add_number
== 1)
10458 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10463 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10464 &offset_expr
, AT
, ZERO
);
10470 /* Fall through. */
10473 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10474 &offset_expr
, op
[0], ZERO
);
10475 else if (op
[0] == 0)
10480 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10481 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10482 &offset_expr
, AT
, ZERO
);
10488 /* Fall through. */
10492 && imm_expr
.X_add_number
== -1))
10494 ++imm_expr
.X_add_number
;
10498 if (mask
== M_BLTUL_I
)
10500 if (imm_expr
.X_add_number
== 0)
10502 else if (imm_expr
.X_add_number
== 1)
10503 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10504 &offset_expr
, op
[0], ZERO
);
10509 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10510 &offset_expr
, AT
, ZERO
);
10516 /* Fall through. */
10519 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10520 else if (op
[0] == 0)
10521 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10525 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10526 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10527 &offset_expr
, AT
, ZERO
);
10533 /* Fall through. */
10537 else if (op
[0] == 0)
10538 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10539 &offset_expr
, ZERO
, op
[1]);
10543 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10544 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10545 &offset_expr
, AT
, ZERO
);
10551 /* Fall through. */
10557 /* Fall through. */
10563 as_warn (_("divide by zero"));
10565 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10567 macro_build (NULL
, "break", BRK_FMT
, 7);
10571 start_noreorder ();
10574 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10575 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10579 if (mips_opts
.micromips
)
10580 micromips_label_expr (&label_expr
);
10582 label_expr
.X_add_number
= 8;
10583 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10584 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10585 macro_build (NULL
, "break", BRK_FMT
, 7);
10586 if (mips_opts
.micromips
)
10587 micromips_add_label ();
10589 expr1
.X_add_number
= -1;
10591 load_register (AT
, &expr1
, dbl
);
10592 if (mips_opts
.micromips
)
10593 micromips_label_expr (&label_expr
);
10595 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10596 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10599 expr1
.X_add_number
= 1;
10600 load_register (AT
, &expr1
, dbl
);
10601 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10605 expr1
.X_add_number
= 0x80000000;
10606 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10610 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10611 /* We want to close the noreorder block as soon as possible, so
10612 that later insns are available for delay slot filling. */
10617 if (mips_opts
.micromips
)
10618 micromips_label_expr (&label_expr
);
10620 label_expr
.X_add_number
= 8;
10621 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10622 macro_build (NULL
, "nop", "");
10624 /* We want to close the noreorder block as soon as possible, so
10625 that later insns are available for delay slot filling. */
10628 macro_build (NULL
, "break", BRK_FMT
, 6);
10630 if (mips_opts
.micromips
)
10631 micromips_add_label ();
10632 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10671 if (imm_expr
.X_add_number
== 0)
10673 as_warn (_("divide by zero"));
10675 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10677 macro_build (NULL
, "break", BRK_FMT
, 7);
10680 if (imm_expr
.X_add_number
== 1)
10682 if (strcmp (s2
, "mflo") == 0)
10683 move_register (op
[0], op
[1]);
10685 move_register (op
[0], ZERO
);
10688 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10690 if (strcmp (s2
, "mflo") == 0)
10691 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10693 move_register (op
[0], ZERO
);
10698 load_register (AT
, &imm_expr
, dbl
);
10699 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10700 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10719 start_noreorder ();
10722 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10723 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10724 /* We want to close the noreorder block as soon as possible, so
10725 that later insns are available for delay slot filling. */
10730 if (mips_opts
.micromips
)
10731 micromips_label_expr (&label_expr
);
10733 label_expr
.X_add_number
= 8;
10734 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10735 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10737 /* We want to close the noreorder block as soon as possible, so
10738 that later insns are available for delay slot filling. */
10740 macro_build (NULL
, "break", BRK_FMT
, 7);
10741 if (mips_opts
.micromips
)
10742 micromips_add_label ();
10744 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10749 /* Fall through. */
10755 /* Fall through. */
10758 /* Load the address of a symbol into a register. If breg is not
10759 zero, we then add a base register to it. */
10762 if (dbl
&& GPR_SIZE
== 32)
10763 as_warn (_("dla used to load 32-bit register; recommend using la "
10766 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10767 as_warn (_("la used to load 64-bit address; recommend using dla "
10770 if (small_offset_p (0, align
, 16))
10772 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10773 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10777 if (mips_opts
.at
&& (op
[0] == breg
))
10785 if (offset_expr
.X_op
!= O_symbol
10786 && offset_expr
.X_op
!= O_constant
)
10788 as_bad (_("expression too complex"));
10789 offset_expr
.X_op
= O_constant
;
10792 if (offset_expr
.X_op
== O_constant
)
10793 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10794 else if (mips_pic
== NO_PIC
)
10796 /* If this is a reference to a GP relative symbol, we want
10797 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10799 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10800 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10801 If we have a constant, we need two instructions anyhow,
10802 so we may as well always use the latter form.
10804 With 64bit address space and a usable $at we want
10805 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10806 lui $at,<sym> (BFD_RELOC_HI16_S)
10807 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10808 daddiu $at,<sym> (BFD_RELOC_LO16)
10810 daddu $tempreg,$tempreg,$at
10812 If $at is already in use, we use a path which is suboptimal
10813 on superscalar processors.
10814 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10815 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10817 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10819 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10821 For GP relative symbols in 64bit address space we can use
10822 the same sequence as in 32bit address space. */
10823 if (HAVE_64BIT_SYMBOLS
)
10825 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10826 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10828 relax_start (offset_expr
.X_add_symbol
);
10829 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10830 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10834 if (used_at
== 0 && mips_opts
.at
)
10836 macro_build (&offset_expr
, "lui", LUI_FMT
,
10837 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10838 macro_build (&offset_expr
, "lui", LUI_FMT
,
10839 AT
, BFD_RELOC_HI16_S
);
10840 macro_build (&offset_expr
, "daddiu", "t,r,j",
10841 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10842 macro_build (&offset_expr
, "daddiu", "t,r,j",
10843 AT
, AT
, BFD_RELOC_LO16
);
10844 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10845 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10850 macro_build (&offset_expr
, "lui", LUI_FMT
,
10851 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10852 macro_build (&offset_expr
, "daddiu", "t,r,j",
10853 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10854 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10855 macro_build (&offset_expr
, "daddiu", "t,r,j",
10856 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10857 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10858 macro_build (&offset_expr
, "daddiu", "t,r,j",
10859 tempreg
, tempreg
, BFD_RELOC_LO16
);
10862 if (mips_relax
.sequence
)
10867 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10868 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10870 relax_start (offset_expr
.X_add_symbol
);
10871 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10872 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10875 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10876 as_bad (_("offset too large"));
10877 macro_build_lui (&offset_expr
, tempreg
);
10878 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10879 tempreg
, tempreg
, BFD_RELOC_LO16
);
10880 if (mips_relax
.sequence
)
10884 else if (!mips_big_got
&& !HAVE_NEWABI
)
10886 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10888 /* If this is a reference to an external symbol, and there
10889 is no constant, we want
10890 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10891 or for lca or if tempreg is PIC_CALL_REG
10892 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10893 For a local symbol, we want
10894 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10896 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10898 If we have a small constant, and this is a reference to
10899 an external symbol, we want
10900 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10902 addiu $tempreg,$tempreg,<constant>
10903 For a local symbol, we want the same instruction
10904 sequence, but we output a BFD_RELOC_LO16 reloc on the
10907 If we have a large constant, and this is a reference to
10908 an external symbol, we want
10909 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10910 lui $at,<hiconstant>
10911 addiu $at,$at,<loconstant>
10912 addu $tempreg,$tempreg,$at
10913 For a local symbol, we want the same instruction
10914 sequence, but we output a BFD_RELOC_LO16 reloc on the
10918 if (offset_expr
.X_add_number
== 0)
10920 if (mips_pic
== SVR4_PIC
10922 && (call
|| tempreg
== PIC_CALL_REG
))
10923 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10925 relax_start (offset_expr
.X_add_symbol
);
10926 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10927 lw_reloc_type
, mips_gp_register
);
10930 /* We're going to put in an addu instruction using
10931 tempreg, so we may as well insert the nop right
10936 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10937 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10939 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10940 tempreg
, tempreg
, BFD_RELOC_LO16
);
10942 /* FIXME: If breg == 0, and the next instruction uses
10943 $tempreg, then if this variant case is used an extra
10944 nop will be generated. */
10946 else if (offset_expr
.X_add_number
>= -0x8000
10947 && offset_expr
.X_add_number
< 0x8000)
10949 load_got_offset (tempreg
, &offset_expr
);
10951 add_got_offset (tempreg
, &offset_expr
);
10955 expr1
.X_add_number
= offset_expr
.X_add_number
;
10956 offset_expr
.X_add_number
=
10957 SEXT_16BIT (offset_expr
.X_add_number
);
10958 load_got_offset (tempreg
, &offset_expr
);
10959 offset_expr
.X_add_number
= expr1
.X_add_number
;
10960 /* If we are going to add in a base register, and the
10961 target register and the base register are the same,
10962 then we are using AT as a temporary register. Since
10963 we want to load the constant into AT, we add our
10964 current AT (from the global offset table) and the
10965 register into the register now, and pretend we were
10966 not using a base register. */
10970 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10975 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10979 else if (!mips_big_got
&& HAVE_NEWABI
)
10981 int add_breg_early
= 0;
10983 /* If this is a reference to an external, and there is no
10984 constant, or local symbol (*), with or without a
10986 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10987 or for lca or if tempreg is PIC_CALL_REG
10988 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10990 If we have a small constant, and this is a reference to
10991 an external symbol, we want
10992 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10993 addiu $tempreg,$tempreg,<constant>
10995 If we have a large constant, and this is a reference to
10996 an external symbol, we want
10997 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10998 lui $at,<hiconstant>
10999 addiu $at,$at,<loconstant>
11000 addu $tempreg,$tempreg,$at
11002 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11003 local symbols, even though it introduces an additional
11006 if (offset_expr
.X_add_number
)
11008 expr1
.X_add_number
= offset_expr
.X_add_number
;
11009 offset_expr
.X_add_number
= 0;
11011 relax_start (offset_expr
.X_add_symbol
);
11012 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11013 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11015 if (expr1
.X_add_number
>= -0x8000
11016 && expr1
.X_add_number
< 0x8000)
11018 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11019 tempreg
, tempreg
, BFD_RELOC_LO16
);
11021 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11025 /* If we are going to add in a base register, and the
11026 target register and the base register are the same,
11027 then we are using AT as a temporary register. Since
11028 we want to load the constant into AT, we add our
11029 current AT (from the global offset table) and the
11030 register into the register now, and pretend we were
11031 not using a base register. */
11036 gas_assert (tempreg
== AT
);
11037 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11040 add_breg_early
= 1;
11043 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11044 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11050 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11053 offset_expr
.X_add_number
= expr1
.X_add_number
;
11055 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11056 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11057 if (add_breg_early
)
11059 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11060 op
[0], tempreg
, breg
);
11066 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11068 relax_start (offset_expr
.X_add_symbol
);
11069 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11070 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11072 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11073 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11078 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11079 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11082 else if (mips_big_got
&& !HAVE_NEWABI
)
11085 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11086 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11087 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11089 /* This is the large GOT case. If this is a reference to an
11090 external symbol, and there is no constant, we want
11091 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11092 addu $tempreg,$tempreg,$gp
11093 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11094 or for lca or if tempreg is PIC_CALL_REG
11095 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11096 addu $tempreg,$tempreg,$gp
11097 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11098 For a local symbol, we want
11099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11101 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11103 If we have a small constant, and this is a reference to
11104 an external symbol, we want
11105 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11106 addu $tempreg,$tempreg,$gp
11107 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11109 addiu $tempreg,$tempreg,<constant>
11110 For a local symbol, we want
11111 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11113 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11115 If we have a large constant, and this is a reference to
11116 an external symbol, we want
11117 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11118 addu $tempreg,$tempreg,$gp
11119 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11120 lui $at,<hiconstant>
11121 addiu $at,$at,<loconstant>
11122 addu $tempreg,$tempreg,$at
11123 For a local symbol, we want
11124 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11125 lui $at,<hiconstant>
11126 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11127 addu $tempreg,$tempreg,$at
11130 expr1
.X_add_number
= offset_expr
.X_add_number
;
11131 offset_expr
.X_add_number
= 0;
11132 relax_start (offset_expr
.X_add_symbol
);
11133 gpdelay
= reg_needs_delay (mips_gp_register
);
11134 if (expr1
.X_add_number
== 0 && breg
== 0
11135 && (call
|| tempreg
== PIC_CALL_REG
))
11137 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11138 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11140 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11141 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11142 tempreg
, tempreg
, mips_gp_register
);
11143 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11144 tempreg
, lw_reloc_type
, tempreg
);
11145 if (expr1
.X_add_number
== 0)
11149 /* We're going to put in an addu instruction using
11150 tempreg, so we may as well insert the nop right
11155 else if (expr1
.X_add_number
>= -0x8000
11156 && expr1
.X_add_number
< 0x8000)
11159 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11160 tempreg
, tempreg
, BFD_RELOC_LO16
);
11166 /* If we are going to add in a base register, and the
11167 target register and the base register are the same,
11168 then we are using AT as a temporary register. Since
11169 we want to load the constant into AT, we add our
11170 current AT (from the global offset table) and the
11171 register into the register now, and pretend we were
11172 not using a base register. */
11177 gas_assert (tempreg
== AT
);
11179 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11184 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11185 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11189 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11194 /* This is needed because this instruction uses $gp, but
11195 the first instruction on the main stream does not. */
11196 macro_build (NULL
, "nop", "");
11199 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11200 local_reloc_type
, mips_gp_register
);
11201 if (expr1
.X_add_number
>= -0x8000
11202 && expr1
.X_add_number
< 0x8000)
11205 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11206 tempreg
, tempreg
, BFD_RELOC_LO16
);
11207 /* FIXME: If add_number is 0, and there was no base
11208 register, the external symbol case ended with a load,
11209 so if the symbol turns out to not be external, and
11210 the next instruction uses tempreg, an unnecessary nop
11211 will be inserted. */
11217 /* We must add in the base register now, as in the
11218 external symbol case. */
11219 gas_assert (tempreg
== AT
);
11221 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11224 /* We set breg to 0 because we have arranged to add
11225 it in in both cases. */
11229 macro_build_lui (&expr1
, AT
);
11230 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11231 AT
, AT
, BFD_RELOC_LO16
);
11232 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11233 tempreg
, tempreg
, AT
);
11238 else if (mips_big_got
&& HAVE_NEWABI
)
11240 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11241 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11242 int add_breg_early
= 0;
11244 /* This is the large GOT case. If this is a reference to an
11245 external symbol, and there is no constant, we want
11246 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11247 add $tempreg,$tempreg,$gp
11248 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11249 or for lca or if tempreg is PIC_CALL_REG
11250 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11251 add $tempreg,$tempreg,$gp
11252 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11254 If we have a small constant, and this is a reference to
11255 an external symbol, we want
11256 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11257 add $tempreg,$tempreg,$gp
11258 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11259 addi $tempreg,$tempreg,<constant>
11261 If we have a large constant, and this is a reference to
11262 an external symbol, we want
11263 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11264 addu $tempreg,$tempreg,$gp
11265 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11266 lui $at,<hiconstant>
11267 addi $at,$at,<loconstant>
11268 add $tempreg,$tempreg,$at
11270 If we have NewABI, and we know it's a local symbol, we want
11271 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11272 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11273 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11275 relax_start (offset_expr
.X_add_symbol
);
11277 expr1
.X_add_number
= offset_expr
.X_add_number
;
11278 offset_expr
.X_add_number
= 0;
11280 if (expr1
.X_add_number
== 0 && breg
== 0
11281 && (call
|| tempreg
== PIC_CALL_REG
))
11283 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11284 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11286 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11287 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11288 tempreg
, tempreg
, mips_gp_register
);
11289 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11290 tempreg
, lw_reloc_type
, tempreg
);
11292 if (expr1
.X_add_number
== 0)
11294 else if (expr1
.X_add_number
>= -0x8000
11295 && expr1
.X_add_number
< 0x8000)
11297 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11298 tempreg
, tempreg
, BFD_RELOC_LO16
);
11300 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11304 /* If we are going to add in a base register, and the
11305 target register and the base register are the same,
11306 then we are using AT as a temporary register. Since
11307 we want to load the constant into AT, we add our
11308 current AT (from the global offset table) and the
11309 register into the register now, and pretend we were
11310 not using a base register. */
11315 gas_assert (tempreg
== AT
);
11316 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11319 add_breg_early
= 1;
11322 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11323 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11328 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11331 offset_expr
.X_add_number
= expr1
.X_add_number
;
11332 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11333 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11334 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11335 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11336 if (add_breg_early
)
11338 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11339 op
[0], tempreg
, breg
);
11349 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11353 gas_assert (!mips_opts
.micromips
);
11354 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11358 gas_assert (!mips_opts
.micromips
);
11359 macro_build (NULL
, "c2", "C", 0x02);
11363 gas_assert (!mips_opts
.micromips
);
11364 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11368 gas_assert (!mips_opts
.micromips
);
11369 macro_build (NULL
, "c2", "C", 3);
11373 gas_assert (!mips_opts
.micromips
);
11374 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11378 /* The j instruction may not be used in PIC code, since it
11379 requires an absolute address. We convert it to a b
11381 if (mips_pic
== NO_PIC
)
11382 macro_build (&offset_expr
, "j", "a");
11384 macro_build (&offset_expr
, "b", "p");
11387 /* The jal instructions must be handled as macros because when
11388 generating PIC code they expand to multi-instruction
11389 sequences. Normally they are simple instructions. */
11393 /* Fall through. */
11395 gas_assert (mips_opts
.micromips
);
11396 if (mips_opts
.insn32
)
11398 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11406 /* Fall through. */
11409 if (mips_pic
== NO_PIC
)
11411 s
= jals
? "jalrs" : "jalr";
11412 if (mips_opts
.micromips
11413 && !mips_opts
.insn32
11415 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11416 macro_build (NULL
, s
, "mj", op
[1]);
11418 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11422 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11423 && mips_cprestore_offset
>= 0);
11425 if (op
[1] != PIC_CALL_REG
)
11426 as_warn (_("MIPS PIC call to register other than $25"));
11428 s
= ((mips_opts
.micromips
11429 && !mips_opts
.insn32
11430 && (!mips_opts
.noreorder
|| cprestore
))
11431 ? "jalrs" : "jalr");
11432 if (mips_opts
.micromips
11433 && !mips_opts
.insn32
11435 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11436 macro_build (NULL
, s
, "mj", op
[1]);
11438 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11439 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11441 if (mips_cprestore_offset
< 0)
11442 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11445 if (!mips_frame_reg_valid
)
11447 as_warn (_("no .frame pseudo-op used in PIC code"));
11448 /* Quiet this warning. */
11449 mips_frame_reg_valid
= 1;
11451 if (!mips_cprestore_valid
)
11453 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11454 /* Quiet this warning. */
11455 mips_cprestore_valid
= 1;
11457 if (mips_opts
.noreorder
)
11458 macro_build (NULL
, "nop", "");
11459 expr1
.X_add_number
= mips_cprestore_offset
;
11460 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11463 HAVE_64BIT_ADDRESSES
);
11471 gas_assert (mips_opts
.micromips
);
11472 if (mips_opts
.insn32
)
11474 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11478 /* Fall through. */
11480 if (mips_pic
== NO_PIC
)
11481 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11482 else if (mips_pic
== SVR4_PIC
)
11484 /* If this is a reference to an external symbol, and we are
11485 using a small GOT, we want
11486 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11490 lw $gp,cprestore($sp)
11491 The cprestore value is set using the .cprestore
11492 pseudo-op. If we are using a big GOT, we want
11493 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11495 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11499 lw $gp,cprestore($sp)
11500 If the symbol is not external, we want
11501 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11503 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11506 lw $gp,cprestore($sp)
11508 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11509 sequences above, minus nops, unless the symbol is local,
11510 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11516 relax_start (offset_expr
.X_add_symbol
);
11517 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11518 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11521 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11522 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11528 relax_start (offset_expr
.X_add_symbol
);
11529 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11530 BFD_RELOC_MIPS_CALL_HI16
);
11531 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11532 PIC_CALL_REG
, mips_gp_register
);
11533 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11534 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11537 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11538 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11540 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11541 PIC_CALL_REG
, PIC_CALL_REG
,
11542 BFD_RELOC_MIPS_GOT_OFST
);
11546 macro_build_jalr (&offset_expr
, 0);
11550 relax_start (offset_expr
.X_add_symbol
);
11553 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11554 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11563 gpdelay
= reg_needs_delay (mips_gp_register
);
11564 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11565 BFD_RELOC_MIPS_CALL_HI16
);
11566 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11567 PIC_CALL_REG
, mips_gp_register
);
11568 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11569 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11574 macro_build (NULL
, "nop", "");
11576 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11577 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11580 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11581 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11583 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11585 if (mips_cprestore_offset
< 0)
11586 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11589 if (!mips_frame_reg_valid
)
11591 as_warn (_("no .frame pseudo-op used in PIC code"));
11592 /* Quiet this warning. */
11593 mips_frame_reg_valid
= 1;
11595 if (!mips_cprestore_valid
)
11597 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11598 /* Quiet this warning. */
11599 mips_cprestore_valid
= 1;
11601 if (mips_opts
.noreorder
)
11602 macro_build (NULL
, "nop", "");
11603 expr1
.X_add_number
= mips_cprestore_offset
;
11604 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11607 HAVE_64BIT_ADDRESSES
);
11611 else if (mips_pic
== VXWORKS_PIC
)
11612 as_bad (_("non-PIC jump used in PIC library"));
11719 gas_assert (!mips_opts
.micromips
);
11722 /* Itbl support may require additional care here. */
11728 /* Itbl support may require additional care here. */
11734 offbits
= (mips_opts
.micromips
? 12
11735 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11737 /* Itbl support may require additional care here. */
11741 gas_assert (!mips_opts
.micromips
);
11744 /* Itbl support may require additional care here. */
11750 offbits
= (mips_opts
.micromips
? 12 : 16);
11755 offbits
= (mips_opts
.micromips
? 12 : 16);
11760 /* Itbl support may require additional care here. */
11766 offbits
= (mips_opts
.micromips
? 12
11767 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11769 /* Itbl support may require additional care here. */
11775 /* Itbl support may require additional care here. */
11781 /* Itbl support may require additional care here. */
11787 offbits
= (mips_opts
.micromips
? 12 : 16);
11792 offbits
= (mips_opts
.micromips
? 12 : 16);
11797 offbits
= (mips_opts
.micromips
? 12
11798 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11804 offbits
= (mips_opts
.micromips
? 12
11805 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11811 offbits
= (mips_opts
.micromips
? 12 : 16);
11814 gas_assert (mips_opts
.micromips
);
11821 gas_assert (mips_opts
.micromips
);
11828 gas_assert (mips_opts
.micromips
);
11834 gas_assert (mips_opts
.micromips
);
11841 /* We don't want to use $0 as tempreg. */
11842 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11845 tempreg
= op
[0] + lp
;
11861 gas_assert (!mips_opts
.micromips
);
11864 /* Itbl support may require additional care here. */
11870 /* Itbl support may require additional care here. */
11876 offbits
= (mips_opts
.micromips
? 12
11877 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11879 /* Itbl support may require additional care here. */
11883 gas_assert (!mips_opts
.micromips
);
11886 /* Itbl support may require additional care here. */
11892 offbits
= (mips_opts
.micromips
? 12 : 16);
11897 offbits
= (mips_opts
.micromips
? 12 : 16);
11902 offbits
= (mips_opts
.micromips
? 12
11903 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11909 offbits
= (mips_opts
.micromips
? 12
11910 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11915 fmt
= (mips_opts
.micromips
? "k,~(b)"
11916 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11918 offbits
= (mips_opts
.micromips
? 12
11919 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11929 fmt
= (mips_opts
.micromips
? "k,~(b)"
11930 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11932 offbits
= (mips_opts
.micromips
? 12
11933 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11945 /* Itbl support may require additional care here. */
11950 offbits
= (mips_opts
.micromips
? 12
11951 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11953 /* Itbl support may require additional care here. */
11959 /* Itbl support may require additional care here. */
11963 gas_assert (!mips_opts
.micromips
);
11966 /* Itbl support may require additional care here. */
11972 offbits
= (mips_opts
.micromips
? 12 : 16);
11977 offbits
= (mips_opts
.micromips
? 12 : 16);
11980 gas_assert (mips_opts
.micromips
);
11986 gas_assert (mips_opts
.micromips
);
11992 gas_assert (mips_opts
.micromips
);
11998 gas_assert (mips_opts
.micromips
);
12007 if (small_offset_p (0, align
, 16))
12009 /* The first case exists for M_LD_AB and M_SD_AB, which are
12010 macros for o32 but which should act like normal instructions
12013 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12014 offset_reloc
[1], offset_reloc
[2], breg
);
12015 else if (small_offset_p (0, align
, offbits
))
12018 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12020 macro_build (NULL
, s
, fmt
, op
[0],
12021 (int) offset_expr
.X_add_number
, breg
);
12027 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12028 tempreg
, breg
, -1, offset_reloc
[0],
12029 offset_reloc
[1], offset_reloc
[2]);
12031 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12033 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12041 if (offset_expr
.X_op
!= O_constant
12042 && offset_expr
.X_op
!= O_symbol
)
12044 as_bad (_("expression too complex"));
12045 offset_expr
.X_op
= O_constant
;
12048 if (HAVE_32BIT_ADDRESSES
12049 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12053 sprintf_vma (value
, offset_expr
.X_add_number
);
12054 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12057 /* A constant expression in PIC code can be handled just as it
12058 is in non PIC code. */
12059 if (offset_expr
.X_op
== O_constant
)
12061 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12062 offbits
== 0 ? 16 : offbits
);
12063 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12065 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12067 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12068 tempreg
, tempreg
, breg
);
12071 if (offset_expr
.X_add_number
!= 0)
12072 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12073 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12074 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12076 else if (offbits
== 16)
12077 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12079 macro_build (NULL
, s
, fmt
, op
[0],
12080 (int) offset_expr
.X_add_number
, tempreg
);
12082 else if (offbits
!= 16)
12084 /* The offset field is too narrow to be used for a low-part
12085 relocation, so load the whole address into the auxiliary
12087 load_address (tempreg
, &offset_expr
, &used_at
);
12089 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12090 tempreg
, tempreg
, breg
);
12092 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12094 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12096 else if (mips_pic
== NO_PIC
)
12098 /* If this is a reference to a GP relative symbol, and there
12099 is no base register, we want
12100 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12101 Otherwise, if there is no base register, we want
12102 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12103 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12104 If we have a constant, we need two instructions anyhow,
12105 so we always use the latter form.
12107 If we have a base register, and this is a reference to a
12108 GP relative symbol, we want
12109 addu $tempreg,$breg,$gp
12110 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12112 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12113 addu $tempreg,$tempreg,$breg
12114 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12115 With a constant we always use the latter case.
12117 With 64bit address space and no base register and $at usable,
12119 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12120 lui $at,<sym> (BFD_RELOC_HI16_S)
12121 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12124 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12125 If we have a base register, we want
12126 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12127 lui $at,<sym> (BFD_RELOC_HI16_S)
12128 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12132 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12134 Without $at we can't generate the optimal path for superscalar
12135 processors here since this would require two temporary registers.
12136 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12137 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12139 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12141 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12142 If we have a base register, we want
12143 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12144 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12146 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12148 daddu $tempreg,$tempreg,$breg
12149 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12151 For GP relative symbols in 64bit address space we can use
12152 the same sequence as in 32bit address space. */
12153 if (HAVE_64BIT_SYMBOLS
)
12155 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12156 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12158 relax_start (offset_expr
.X_add_symbol
);
12161 macro_build (&offset_expr
, s
, fmt
, op
[0],
12162 BFD_RELOC_GPREL16
, mips_gp_register
);
12166 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12167 tempreg
, breg
, mips_gp_register
);
12168 macro_build (&offset_expr
, s
, fmt
, op
[0],
12169 BFD_RELOC_GPREL16
, tempreg
);
12174 if (used_at
== 0 && mips_opts
.at
)
12176 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12177 BFD_RELOC_MIPS_HIGHEST
);
12178 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12180 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12181 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12183 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12184 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12185 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12186 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12192 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12193 BFD_RELOC_MIPS_HIGHEST
);
12194 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12195 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12196 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12197 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12198 tempreg
, BFD_RELOC_HI16_S
);
12199 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12201 macro_build (NULL
, "daddu", "d,v,t",
12202 tempreg
, tempreg
, breg
);
12203 macro_build (&offset_expr
, s
, fmt
, op
[0],
12204 BFD_RELOC_LO16
, tempreg
);
12207 if (mips_relax
.sequence
)
12214 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12215 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12217 relax_start (offset_expr
.X_add_symbol
);
12218 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12222 macro_build_lui (&offset_expr
, tempreg
);
12223 macro_build (&offset_expr
, s
, fmt
, op
[0],
12224 BFD_RELOC_LO16
, tempreg
);
12225 if (mips_relax
.sequence
)
12230 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12231 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12233 relax_start (offset_expr
.X_add_symbol
);
12234 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12235 tempreg
, breg
, mips_gp_register
);
12236 macro_build (&offset_expr
, s
, fmt
, op
[0],
12237 BFD_RELOC_GPREL16
, tempreg
);
12240 macro_build_lui (&offset_expr
, tempreg
);
12241 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12242 tempreg
, tempreg
, breg
);
12243 macro_build (&offset_expr
, s
, fmt
, op
[0],
12244 BFD_RELOC_LO16
, tempreg
);
12245 if (mips_relax
.sequence
)
12249 else if (!mips_big_got
)
12251 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12253 /* If this is a reference to an external symbol, we want
12254 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12256 <op> op[0],0($tempreg)
12258 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12260 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12261 <op> op[0],0($tempreg)
12263 For NewABI, we want
12264 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12265 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12267 If there is a base register, we add it to $tempreg before
12268 the <op>. If there is a constant, we stick it in the
12269 <op> instruction. We don't handle constants larger than
12270 16 bits, because we have no way to load the upper 16 bits
12271 (actually, we could handle them for the subset of cases
12272 in which we are not using $at). */
12273 gas_assert (offset_expr
.X_op
== O_symbol
);
12276 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12277 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12279 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12280 tempreg
, tempreg
, breg
);
12281 macro_build (&offset_expr
, s
, fmt
, op
[0],
12282 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12285 expr1
.X_add_number
= offset_expr
.X_add_number
;
12286 offset_expr
.X_add_number
= 0;
12287 if (expr1
.X_add_number
< -0x8000
12288 || expr1
.X_add_number
>= 0x8000)
12289 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12290 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12291 lw_reloc_type
, mips_gp_register
);
12293 relax_start (offset_expr
.X_add_symbol
);
12295 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12296 tempreg
, BFD_RELOC_LO16
);
12299 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12300 tempreg
, tempreg
, breg
);
12301 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12303 else if (mips_big_got
&& !HAVE_NEWABI
)
12307 /* If this is a reference to an external symbol, we want
12308 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12309 addu $tempreg,$tempreg,$gp
12310 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12311 <op> op[0],0($tempreg)
12313 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12315 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12316 <op> op[0],0($tempreg)
12317 If there is a base register, we add it to $tempreg before
12318 the <op>. If there is a constant, we stick it in the
12319 <op> instruction. We don't handle constants larger than
12320 16 bits, because we have no way to load the upper 16 bits
12321 (actually, we could handle them for the subset of cases
12322 in which we are not using $at). */
12323 gas_assert (offset_expr
.X_op
== O_symbol
);
12324 expr1
.X_add_number
= offset_expr
.X_add_number
;
12325 offset_expr
.X_add_number
= 0;
12326 if (expr1
.X_add_number
< -0x8000
12327 || expr1
.X_add_number
>= 0x8000)
12328 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12329 gpdelay
= reg_needs_delay (mips_gp_register
);
12330 relax_start (offset_expr
.X_add_symbol
);
12331 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12332 BFD_RELOC_MIPS_GOT_HI16
);
12333 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12335 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12336 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12339 macro_build (NULL
, "nop", "");
12340 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12341 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12343 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12344 tempreg
, BFD_RELOC_LO16
);
12348 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12349 tempreg
, tempreg
, breg
);
12350 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12352 else if (mips_big_got
&& HAVE_NEWABI
)
12354 /* If this is a reference to an external symbol, we want
12355 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12356 add $tempreg,$tempreg,$gp
12357 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12358 <op> op[0],<ofst>($tempreg)
12359 Otherwise, for local symbols, we want:
12360 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12361 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12362 gas_assert (offset_expr
.X_op
== O_symbol
);
12363 expr1
.X_add_number
= offset_expr
.X_add_number
;
12364 offset_expr
.X_add_number
= 0;
12365 if (expr1
.X_add_number
< -0x8000
12366 || expr1
.X_add_number
>= 0x8000)
12367 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12368 relax_start (offset_expr
.X_add_symbol
);
12369 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12370 BFD_RELOC_MIPS_GOT_HI16
);
12371 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12373 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12374 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12376 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12377 tempreg
, tempreg
, breg
);
12378 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12381 offset_expr
.X_add_number
= expr1
.X_add_number
;
12382 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12383 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12385 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12386 tempreg
, tempreg
, breg
);
12387 macro_build (&offset_expr
, s
, fmt
, op
[0],
12388 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12397 gas_assert (mips_opts
.micromips
);
12398 gas_assert (mips_opts
.insn32
);
12399 start_noreorder ();
12400 macro_build (NULL
, "jr", "s", RA
);
12401 expr1
.X_add_number
= op
[0] << 2;
12402 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12407 gas_assert (mips_opts
.micromips
);
12408 gas_assert (mips_opts
.insn32
);
12409 macro_build (NULL
, "jr", "s", op
[0]);
12410 if (mips_opts
.noreorder
)
12411 macro_build (NULL
, "nop", "");
12416 load_register (op
[0], &imm_expr
, 0);
12420 load_register (op
[0], &imm_expr
, 1);
12424 if (imm_expr
.X_op
== O_constant
)
12427 load_register (AT
, &imm_expr
, 0);
12428 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12433 gas_assert (imm_expr
.X_op
== O_absent
12434 && offset_expr
.X_op
== O_symbol
12435 && strcmp (segment_name (S_GET_SEGMENT
12436 (offset_expr
.X_add_symbol
)),
12438 && offset_expr
.X_add_number
== 0);
12439 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12440 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12445 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12446 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12447 order 32 bits of the value and the low order 32 bits are either
12448 zero or in OFFSET_EXPR. */
12449 if (imm_expr
.X_op
== O_constant
)
12451 if (GPR_SIZE
== 64)
12452 load_register (op
[0], &imm_expr
, 1);
12457 if (target_big_endian
)
12469 load_register (hreg
, &imm_expr
, 0);
12472 if (offset_expr
.X_op
== O_absent
)
12473 move_register (lreg
, 0);
12476 gas_assert (offset_expr
.X_op
== O_constant
);
12477 load_register (lreg
, &offset_expr
, 0);
12483 gas_assert (imm_expr
.X_op
== O_absent
);
12485 /* We know that sym is in the .rdata section. First we get the
12486 upper 16 bits of the address. */
12487 if (mips_pic
== NO_PIC
)
12489 macro_build_lui (&offset_expr
, AT
);
12494 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12495 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12499 /* Now we load the register(s). */
12500 if (GPR_SIZE
== 64)
12503 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12504 BFD_RELOC_LO16
, AT
);
12509 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12510 BFD_RELOC_LO16
, AT
);
12513 /* FIXME: How in the world do we deal with the possible
12515 offset_expr
.X_add_number
+= 4;
12516 macro_build (&offset_expr
, "lw", "t,o(b)",
12517 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12523 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12524 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12525 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12526 the value and the low order 32 bits are either zero or in
12528 if (imm_expr
.X_op
== O_constant
)
12531 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12532 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12533 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12536 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12537 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12538 else if (FPR_SIZE
!= 32)
12539 as_bad (_("Unable to generate `%s' compliant code "
12541 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12543 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12544 if (offset_expr
.X_op
== O_absent
)
12545 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12548 gas_assert (offset_expr
.X_op
== O_constant
);
12549 load_register (AT
, &offset_expr
, 0);
12550 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12556 gas_assert (imm_expr
.X_op
== O_absent
12557 && offset_expr
.X_op
== O_symbol
12558 && offset_expr
.X_add_number
== 0);
12559 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12560 if (strcmp (s
, ".lit8") == 0)
12562 op
[2] = mips_gp_register
;
12563 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12564 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12565 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12569 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12571 if (mips_pic
!= NO_PIC
)
12572 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12573 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12576 /* FIXME: This won't work for a 64 bit address. */
12577 macro_build_lui (&offset_expr
, AT
);
12581 offset_reloc
[0] = BFD_RELOC_LO16
;
12582 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12583 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12590 * The MIPS assembler seems to check for X_add_number not
12591 * being double aligned and generating:
12592 * lui at,%hi(foo+1)
12594 * addiu at,at,%lo(foo+1)
12597 * But, the resulting address is the same after relocation so why
12598 * generate the extra instruction?
12600 /* Itbl support may require additional care here. */
12603 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12612 gas_assert (!mips_opts
.micromips
);
12613 /* Itbl support may require additional care here. */
12616 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12636 if (GPR_SIZE
== 64)
12646 if (GPR_SIZE
== 64)
12654 /* Even on a big endian machine $fn comes before $fn+1. We have
12655 to adjust when loading from memory. We set coproc if we must
12656 load $fn+1 first. */
12657 /* Itbl support may require additional care here. */
12658 if (!target_big_endian
)
12662 if (small_offset_p (0, align
, 16))
12665 if (!small_offset_p (4, align
, 16))
12667 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12668 -1, offset_reloc
[0], offset_reloc
[1],
12670 expr1
.X_add_number
= 0;
12674 offset_reloc
[0] = BFD_RELOC_LO16
;
12675 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12676 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12678 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12680 ep
->X_add_number
+= 4;
12681 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12682 offset_reloc
[1], offset_reloc
[2], breg
);
12683 ep
->X_add_number
-= 4;
12684 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12685 offset_reloc
[1], offset_reloc
[2], breg
);
12689 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12690 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12692 ep
->X_add_number
+= 4;
12693 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12694 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12700 if (offset_expr
.X_op
!= O_symbol
12701 && offset_expr
.X_op
!= O_constant
)
12703 as_bad (_("expression too complex"));
12704 offset_expr
.X_op
= O_constant
;
12707 if (HAVE_32BIT_ADDRESSES
12708 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12712 sprintf_vma (value
, offset_expr
.X_add_number
);
12713 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12716 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12718 /* If this is a reference to a GP relative symbol, we want
12719 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12720 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12721 If we have a base register, we use this
12723 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12724 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12725 If this is not a GP relative symbol, we want
12726 lui $at,<sym> (BFD_RELOC_HI16_S)
12727 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12728 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12729 If there is a base register, we add it to $at after the
12730 lui instruction. If there is a constant, we always use
12732 if (offset_expr
.X_op
== O_symbol
12733 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12734 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12736 relax_start (offset_expr
.X_add_symbol
);
12739 tempreg
= mips_gp_register
;
12743 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12744 AT
, breg
, mips_gp_register
);
12749 /* Itbl support may require additional care here. */
12750 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12751 BFD_RELOC_GPREL16
, tempreg
);
12752 offset_expr
.X_add_number
+= 4;
12754 /* Set mips_optimize to 2 to avoid inserting an
12756 hold_mips_optimize
= mips_optimize
;
12758 /* Itbl support may require additional care here. */
12759 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12760 BFD_RELOC_GPREL16
, tempreg
);
12761 mips_optimize
= hold_mips_optimize
;
12765 offset_expr
.X_add_number
-= 4;
12768 if (offset_high_part (offset_expr
.X_add_number
, 16)
12769 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12771 load_address (AT
, &offset_expr
, &used_at
);
12772 offset_expr
.X_op
= O_constant
;
12773 offset_expr
.X_add_number
= 0;
12776 macro_build_lui (&offset_expr
, AT
);
12778 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12779 /* Itbl support may require additional care here. */
12780 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12781 BFD_RELOC_LO16
, AT
);
12782 /* FIXME: How do we handle overflow here? */
12783 offset_expr
.X_add_number
+= 4;
12784 /* Itbl support may require additional care here. */
12785 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12786 BFD_RELOC_LO16
, AT
);
12787 if (mips_relax
.sequence
)
12790 else if (!mips_big_got
)
12792 /* If this is a reference to an external symbol, we want
12793 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12796 <op> op[0]+1,4($at)
12798 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12800 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12801 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12802 If there is a base register we add it to $at before the
12803 lwc1 instructions. If there is a constant we include it
12804 in the lwc1 instructions. */
12806 expr1
.X_add_number
= offset_expr
.X_add_number
;
12807 if (expr1
.X_add_number
< -0x8000
12808 || expr1
.X_add_number
>= 0x8000 - 4)
12809 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12810 load_got_offset (AT
, &offset_expr
);
12813 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12815 /* Set mips_optimize to 2 to avoid inserting an undesired
12817 hold_mips_optimize
= mips_optimize
;
12820 /* Itbl support may require additional care here. */
12821 relax_start (offset_expr
.X_add_symbol
);
12822 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12823 BFD_RELOC_LO16
, AT
);
12824 expr1
.X_add_number
+= 4;
12825 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12826 BFD_RELOC_LO16
, AT
);
12828 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12829 BFD_RELOC_LO16
, AT
);
12830 offset_expr
.X_add_number
+= 4;
12831 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12832 BFD_RELOC_LO16
, AT
);
12835 mips_optimize
= hold_mips_optimize
;
12837 else if (mips_big_got
)
12841 /* If this is a reference to an external symbol, we want
12842 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12844 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12847 <op> op[0]+1,4($at)
12849 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12851 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12852 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12853 If there is a base register we add it to $at before the
12854 lwc1 instructions. If there is a constant we include it
12855 in the lwc1 instructions. */
12857 expr1
.X_add_number
= offset_expr
.X_add_number
;
12858 offset_expr
.X_add_number
= 0;
12859 if (expr1
.X_add_number
< -0x8000
12860 || expr1
.X_add_number
>= 0x8000 - 4)
12861 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12862 gpdelay
= reg_needs_delay (mips_gp_register
);
12863 relax_start (offset_expr
.X_add_symbol
);
12864 macro_build (&offset_expr
, "lui", LUI_FMT
,
12865 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12866 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12867 AT
, AT
, mips_gp_register
);
12868 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12869 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12872 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12873 /* Itbl support may require additional care here. */
12874 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12875 BFD_RELOC_LO16
, AT
);
12876 expr1
.X_add_number
+= 4;
12878 /* Set mips_optimize to 2 to avoid inserting an undesired
12880 hold_mips_optimize
= mips_optimize
;
12882 /* Itbl support may require additional care here. */
12883 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12884 BFD_RELOC_LO16
, AT
);
12885 mips_optimize
= hold_mips_optimize
;
12886 expr1
.X_add_number
-= 4;
12889 offset_expr
.X_add_number
= expr1
.X_add_number
;
12891 macro_build (NULL
, "nop", "");
12892 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12893 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12896 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12897 /* Itbl support may require additional care here. */
12898 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12899 BFD_RELOC_LO16
, AT
);
12900 offset_expr
.X_add_number
+= 4;
12902 /* Set mips_optimize to 2 to avoid inserting an undesired
12904 hold_mips_optimize
= mips_optimize
;
12906 /* Itbl support may require additional care here. */
12907 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12908 BFD_RELOC_LO16
, AT
);
12909 mips_optimize
= hold_mips_optimize
;
12923 gas_assert (!mips_opts
.micromips
);
12928 /* New code added to support COPZ instructions.
12929 This code builds table entries out of the macros in mip_opcodes.
12930 R4000 uses interlocks to handle coproc delays.
12931 Other chips (like the R3000) require nops to be inserted for delays.
12933 FIXME: Currently, we require that the user handle delays.
12934 In order to fill delay slots for non-interlocked chips,
12935 we must have a way to specify delays based on the coprocessor.
12936 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12937 What are the side-effects of the cop instruction?
12938 What cache support might we have and what are its effects?
12939 Both coprocessor & memory require delays. how long???
12940 What registers are read/set/modified?
12942 If an itbl is provided to interpret cop instructions,
12943 this knowledge can be encoded in the itbl spec. */
12957 gas_assert (!mips_opts
.micromips
);
12958 /* For now we just do C (same as Cz). The parameter will be
12959 stored in insn_opcode by mips_ip. */
12960 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12964 move_register (op
[0], op
[1]);
12968 gas_assert (mips_opts
.micromips
);
12969 gas_assert (mips_opts
.insn32
);
12970 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12971 micromips_to_32_reg_m_map
[op
[1]]);
12972 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12973 micromips_to_32_reg_n_map
[op
[2]]);
12978 /* Fall through. */
12980 if (mips_opts
.arch
== CPU_R5900
)
12981 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12985 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12986 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12992 /* Fall through. */
12994 /* The MIPS assembler some times generates shifts and adds. I'm
12995 not trying to be that fancy. GCC should do this for us
12998 load_register (AT
, &imm_expr
, dbl
);
12999 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13000 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13005 /* Fall through. */
13012 /* Fall through. */
13015 start_noreorder ();
13018 load_register (AT
, &imm_expr
, dbl
);
13019 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13020 op
[1], imm
? AT
: op
[2]);
13021 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13022 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13023 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13025 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13028 if (mips_opts
.micromips
)
13029 micromips_label_expr (&label_expr
);
13031 label_expr
.X_add_number
= 8;
13032 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13033 macro_build (NULL
, "nop", "");
13034 macro_build (NULL
, "break", BRK_FMT
, 6);
13035 if (mips_opts
.micromips
)
13036 micromips_add_label ();
13039 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13044 /* Fall through. */
13051 /* Fall through. */
13054 start_noreorder ();
13057 load_register (AT
, &imm_expr
, dbl
);
13058 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13059 op
[1], imm
? AT
: op
[2]);
13060 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13061 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13063 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13066 if (mips_opts
.micromips
)
13067 micromips_label_expr (&label_expr
);
13069 label_expr
.X_add_number
= 8;
13070 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13071 macro_build (NULL
, "nop", "");
13072 macro_build (NULL
, "break", BRK_FMT
, 6);
13073 if (mips_opts
.micromips
)
13074 micromips_add_label ();
13080 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13082 if (op
[0] == op
[1])
13089 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13090 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13094 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13095 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13096 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13097 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13101 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13103 if (op
[0] == op
[1])
13110 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13111 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13115 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13116 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13117 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13118 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13127 rot
= imm_expr
.X_add_number
& 0x3f;
13128 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13130 rot
= (64 - rot
) & 0x3f;
13132 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13134 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13139 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13142 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13143 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13146 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13147 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13148 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13156 rot
= imm_expr
.X_add_number
& 0x1f;
13157 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13159 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13160 (32 - rot
) & 0x1f);
13165 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13169 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13170 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13171 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13176 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13178 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13182 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13183 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13184 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13185 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13189 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13191 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13195 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13196 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13197 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13198 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13207 rot
= imm_expr
.X_add_number
& 0x3f;
13208 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13211 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13213 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13218 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13221 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13222 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13225 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13226 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13227 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13235 rot
= imm_expr
.X_add_number
& 0x1f;
13236 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13238 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13243 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13247 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13248 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13249 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13255 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13256 else if (op
[2] == 0)
13257 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13260 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13261 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13266 if (imm_expr
.X_add_number
== 0)
13268 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13273 as_warn (_("instruction %s: result is always false"),
13274 ip
->insn_mo
->name
);
13275 move_register (op
[0], 0);
13278 if (CPU_HAS_SEQ (mips_opts
.arch
)
13279 && -512 <= imm_expr
.X_add_number
13280 && imm_expr
.X_add_number
< 512)
13282 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13283 (int) imm_expr
.X_add_number
);
13286 if (imm_expr
.X_add_number
>= 0
13287 && imm_expr
.X_add_number
< 0x10000)
13288 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13289 else if (imm_expr
.X_add_number
> -0x8000
13290 && imm_expr
.X_add_number
< 0)
13292 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13293 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13294 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13296 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13299 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13300 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13305 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13306 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13309 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13312 case M_SGE
: /* X >= Y <==> not (X < Y) */
13318 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13319 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13322 case M_SGE_I
: /* X >= I <==> not (X < I) */
13324 if (imm_expr
.X_add_number
>= -0x8000
13325 && imm_expr
.X_add_number
< 0x8000)
13326 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13327 op
[0], op
[1], BFD_RELOC_LO16
);
13330 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13331 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13335 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13338 case M_SGT
: /* X > Y <==> Y < X */
13344 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13347 case M_SGT_I
: /* X > I <==> I < X */
13354 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13355 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13358 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13364 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13365 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13368 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13375 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13376 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13377 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13381 if (imm_expr
.X_add_number
>= -0x8000
13382 && imm_expr
.X_add_number
< 0x8000)
13384 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13389 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13390 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13394 if (imm_expr
.X_add_number
>= -0x8000
13395 && imm_expr
.X_add_number
< 0x8000)
13397 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13402 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13403 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13408 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13409 else if (op
[2] == 0)
13410 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13413 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13414 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13419 if (imm_expr
.X_add_number
== 0)
13421 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13426 as_warn (_("instruction %s: result is always true"),
13427 ip
->insn_mo
->name
);
13428 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13429 op
[0], 0, BFD_RELOC_LO16
);
13432 if (CPU_HAS_SEQ (mips_opts
.arch
)
13433 && -512 <= imm_expr
.X_add_number
13434 && imm_expr
.X_add_number
< 512)
13436 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13437 (int) imm_expr
.X_add_number
);
13440 if (imm_expr
.X_add_number
>= 0
13441 && imm_expr
.X_add_number
< 0x10000)
13443 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13446 else if (imm_expr
.X_add_number
> -0x8000
13447 && imm_expr
.X_add_number
< 0)
13449 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13450 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13451 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13453 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13456 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13457 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13462 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13463 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13466 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13481 if (!mips_opts
.micromips
)
13483 if (imm_expr
.X_add_number
> -0x200
13484 && imm_expr
.X_add_number
<= 0x200)
13486 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13487 (int) -imm_expr
.X_add_number
);
13496 if (imm_expr
.X_add_number
> -0x8000
13497 && imm_expr
.X_add_number
<= 0x8000)
13499 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13500 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13505 load_register (AT
, &imm_expr
, dbl
);
13506 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13528 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13529 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13534 gas_assert (!mips_opts
.micromips
);
13535 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13539 * Is the double cfc1 instruction a bug in the mips assembler;
13540 * or is there a reason for it?
13542 start_noreorder ();
13543 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13544 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13545 macro_build (NULL
, "nop", "");
13546 expr1
.X_add_number
= 3;
13547 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13548 expr1
.X_add_number
= 2;
13549 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13550 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13551 macro_build (NULL
, "nop", "");
13552 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13554 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13555 macro_build (NULL
, "nop", "");
13572 offbits
= (mips_opts
.micromips
? 12 : 16);
13578 offbits
= (mips_opts
.micromips
? 12 : 16);
13590 offbits
= (mips_opts
.micromips
? 12 : 16);
13597 offbits
= (mips_opts
.micromips
? 12 : 16);
13603 large_offset
= !small_offset_p (off
, align
, offbits
);
13605 expr1
.X_add_number
= 0;
13610 if (small_offset_p (0, align
, 16))
13611 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13612 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13615 load_address (tempreg
, ep
, &used_at
);
13617 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13618 tempreg
, tempreg
, breg
);
13620 offset_reloc
[0] = BFD_RELOC_LO16
;
13621 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13622 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13627 else if (!ust
&& op
[0] == breg
)
13638 if (!target_big_endian
)
13639 ep
->X_add_number
+= off
;
13641 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13643 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13644 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13646 if (!target_big_endian
)
13647 ep
->X_add_number
-= off
;
13649 ep
->X_add_number
+= off
;
13651 macro_build (NULL
, s2
, "t,~(b)",
13652 tempreg
, (int) ep
->X_add_number
, breg
);
13654 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13655 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13657 /* If necessary, move the result in tempreg to the final destination. */
13658 if (!ust
&& op
[0] != tempreg
)
13660 /* Protect second load's delay slot. */
13662 move_register (op
[0], tempreg
);
13668 if (target_big_endian
== ust
)
13669 ep
->X_add_number
+= off
;
13670 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13671 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13672 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13674 /* For halfword transfers we need a temporary register to shuffle
13675 bytes. Unfortunately for M_USH_A we have none available before
13676 the next store as AT holds the base address. We deal with this
13677 case by clobbering TREG and then restoring it as with ULH. */
13678 tempreg
= ust
== large_offset
? op
[0] : AT
;
13680 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13682 if (target_big_endian
== ust
)
13683 ep
->X_add_number
-= off
;
13685 ep
->X_add_number
+= off
;
13686 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13687 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13689 /* For M_USH_A re-retrieve the LSB. */
13690 if (ust
&& large_offset
)
13692 if (target_big_endian
)
13693 ep
->X_add_number
+= off
;
13695 ep
->X_add_number
-= off
;
13696 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13697 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13699 /* For ULH and M_USH_A OR the LSB in. */
13700 if (!ust
|| large_offset
)
13702 tempreg
= !large_offset
? AT
: op
[0];
13703 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13704 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13709 /* FIXME: Check if this is one of the itbl macros, since they
13710 are added dynamically. */
13711 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13714 if (!mips_opts
.at
&& used_at
)
13715 as_bad (_("macro used $at after \".set noat\""));
13718 /* Implement macros in mips16 mode. */
13721 mips16_macro (struct mips_cl_insn
*ip
)
13723 const struct mips_operand_array
*operands
;
13728 const char *s
, *s2
, *s3
;
13729 unsigned int op
[MAX_OPERANDS
];
13732 mask
= ip
->insn_mo
->mask
;
13734 operands
= insn_operands (ip
);
13735 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13736 if (operands
->operand
[i
])
13737 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13741 expr1
.X_op
= O_constant
;
13742 expr1
.X_op_symbol
= NULL
;
13743 expr1
.X_add_symbol
= NULL
;
13744 expr1
.X_add_number
= 1;
13755 /* Fall through. */
13761 /* Fall through. */
13765 start_noreorder ();
13766 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13767 expr1
.X_add_number
= 2;
13768 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13769 macro_build (NULL
, "break", "6", 7);
13771 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13772 since that causes an overflow. We should do that as well,
13773 but I don't see how to do the comparisons without a temporary
13776 macro_build (NULL
, s
, "x", op
[0]);
13795 start_noreorder ();
13796 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13797 expr1
.X_add_number
= 2;
13798 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13799 macro_build (NULL
, "break", "6", 7);
13801 macro_build (NULL
, s2
, "x", op
[0]);
13806 /* Fall through. */
13808 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13809 macro_build (NULL
, "mflo", "x", op
[0]);
13817 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13818 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13822 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13823 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13827 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13828 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13850 goto do_reverse_branch
;
13854 goto do_reverse_branch
;
13866 goto do_reverse_branch
;
13877 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13878 macro_build (&offset_expr
, s2
, "p");
13905 goto do_addone_branch_i
;
13910 goto do_addone_branch_i
;
13925 goto do_addone_branch_i
;
13931 do_addone_branch_i
:
13932 ++imm_expr
.X_add_number
;
13935 macro_build (&imm_expr
, s
, s3
, op
[0]);
13936 macro_build (&offset_expr
, s2
, "p");
13940 expr1
.X_add_number
= 0;
13941 macro_build (&expr1
, "slti", "x,8", op
[1]);
13942 if (op
[0] != op
[1])
13943 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13944 expr1
.X_add_number
= 2;
13945 macro_build (&expr1
, "bteqz", "p");
13946 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13951 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13952 opcode bits in *OPCODE_EXTRA. */
13954 static struct mips_opcode
*
13955 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13956 ssize_t length
, unsigned int *opcode_extra
)
13958 char *name
, *dot
, *p
;
13959 unsigned int mask
, suffix
;
13961 struct mips_opcode
*insn
;
13963 /* Make a copy of the instruction so that we can fiddle with it. */
13964 name
= xstrndup (start
, length
);
13966 /* Look up the instruction as-is. */
13967 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13971 dot
= strchr (name
, '.');
13974 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13975 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13976 if (*p
== 0 && mask
!= 0)
13979 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13981 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13983 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13989 if (mips_opts
.micromips
)
13991 /* See if there's an instruction size override suffix,
13992 either `16' or `32', at the end of the mnemonic proper,
13993 that defines the operation, i.e. before the first `.'
13994 character if any. Strip it and retry. */
13995 opend
= dot
!= NULL
? dot
- name
: length
;
13996 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13998 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14004 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14005 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14008 forced_insn_length
= suffix
;
14020 /* Assemble an instruction into its binary format. If the instruction
14021 is a macro, set imm_expr and offset_expr to the values associated
14022 with "I" and "A" operands respectively. Otherwise store the value
14023 of the relocatable field (if any) in offset_expr. In both cases
14024 set offset_reloc to the relocation operators applied to offset_expr. */
14027 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14029 const struct mips_opcode
*first
, *past
;
14030 struct hash_control
*hash
;
14033 struct mips_operand_token
*tokens
;
14034 unsigned int opcode_extra
;
14036 if (mips_opts
.micromips
)
14038 hash
= micromips_op_hash
;
14039 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14044 past
= &mips_opcodes
[NUMOPCODES
];
14046 forced_insn_length
= 0;
14049 /* We first try to match an instruction up to a space or to the end. */
14050 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14053 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14056 set_insn_error (0, _("unrecognized opcode"));
14060 if (strcmp (first
->name
, "li.s") == 0)
14062 else if (strcmp (first
->name
, "li.d") == 0)
14066 tokens
= mips_parse_arguments (str
+ end
, format
);
14070 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14071 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14072 set_insn_error (0, _("invalid operands"));
14074 obstack_free (&mips_operand_tokens
, tokens
);
14077 /* As for mips_ip, but used when assembling MIPS16 code.
14078 Also set forced_insn_length to the resulting instruction size in
14079 bytes if the user explicitly requested a small or extended instruction. */
14082 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14085 struct mips_opcode
*first
;
14086 struct mips_operand_token
*tokens
;
14089 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14111 else if (*s
== 'e')
14118 else if (*s
++ == ' ')
14120 set_insn_error (0, _("unrecognized opcode"));
14123 forced_insn_length
= l
;
14126 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14131 set_insn_error (0, _("unrecognized opcode"));
14135 tokens
= mips_parse_arguments (s
, 0);
14139 if (!match_mips16_insns (insn
, first
, tokens
))
14140 set_insn_error (0, _("invalid operands"));
14142 obstack_free (&mips_operand_tokens
, tokens
);
14145 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14146 NBITS is the number of significant bits in VAL. */
14148 static unsigned long
14149 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14154 val
&= (1U << nbits
) - 1;
14155 if (nbits
== 16 || nbits
== 9)
14157 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14160 else if (nbits
== 15)
14162 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14165 else if (nbits
== 6)
14167 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14170 return (extval
<< 16) | val
;
14173 /* Like decode_mips16_operand, but require the operand to be defined and
14174 require it to be an integer. */
14176 static const struct mips_int_operand
*
14177 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14179 const struct mips_operand
*operand
;
14181 operand
= decode_mips16_operand (type
, extended_p
);
14182 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14184 return (const struct mips_int_operand
*) operand
;
14187 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14190 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14191 bfd_reloc_code_real_type reloc
, offsetT sval
)
14193 int min_val
, max_val
;
14195 min_val
= mips_int_operand_min (operand
);
14196 max_val
= mips_int_operand_max (operand
);
14197 if (reloc
!= BFD_RELOC_UNUSED
)
14200 sval
= SEXT_16BIT (sval
);
14205 return (sval
>= min_val
14207 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14210 /* Install immediate value VAL into MIPS16 instruction *INSN,
14211 extending it if necessary. The instruction in *INSN may
14212 already be extended.
14214 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14215 if none. In the former case, VAL is a 16-bit number with no
14216 defined signedness.
14218 TYPE is the type of the immediate field. USER_INSN_LENGTH
14219 is the length that the user requested, or 0 if none. */
14222 mips16_immed (const char *file
, unsigned int line
, int type
,
14223 bfd_reloc_code_real_type reloc
, offsetT val
,
14224 unsigned int user_insn_length
, unsigned long *insn
)
14226 const struct mips_int_operand
*operand
;
14227 unsigned int uval
, length
;
14229 operand
= mips16_immed_operand (type
, FALSE
);
14230 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14232 /* We need an extended instruction. */
14233 if (user_insn_length
== 2)
14234 as_bad_where (file
, line
, _("invalid unextended operand value"));
14236 *insn
|= MIPS16_EXTEND
;
14238 else if (user_insn_length
== 4)
14240 /* The operand doesn't force an unextended instruction to be extended.
14241 Warn if the user wanted an extended instruction anyway. */
14242 *insn
|= MIPS16_EXTEND
;
14243 as_warn_where (file
, line
,
14244 _("extended operand requested but not required"));
14247 length
= mips16_opcode_length (*insn
);
14250 operand
= mips16_immed_operand (type
, TRUE
);
14251 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14252 as_bad_where (file
, line
,
14253 _("operand value out of range for instruction"));
14255 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14256 if (length
== 2 || operand
->root
.lsb
!= 0)
14257 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14259 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14262 struct percent_op_match
14265 bfd_reloc_code_real_type reloc
;
14268 static const struct percent_op_match mips_percent_op
[] =
14270 {"%lo", BFD_RELOC_LO16
},
14271 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14272 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14273 {"%call16", BFD_RELOC_MIPS_CALL16
},
14274 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14275 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14276 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14277 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14278 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14279 {"%got", BFD_RELOC_MIPS_GOT16
},
14280 {"%gp_rel", BFD_RELOC_GPREL16
},
14281 {"%gprel", BFD_RELOC_GPREL16
},
14282 {"%half", BFD_RELOC_16
},
14283 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14284 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14285 {"%neg", BFD_RELOC_MIPS_SUB
},
14286 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14287 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14288 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14289 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14290 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14291 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14292 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14293 {"%hi", BFD_RELOC_HI16_S
},
14294 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14295 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14298 static const struct percent_op_match mips16_percent_op
[] =
14300 {"%lo", BFD_RELOC_MIPS16_LO16
},
14301 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14302 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14303 {"%got", BFD_RELOC_MIPS16_GOT16
},
14304 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14305 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14306 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14307 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14308 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14309 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14310 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14311 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14312 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14316 /* Return true if *STR points to a relocation operator. When returning true,
14317 move *STR over the operator and store its relocation code in *RELOC.
14318 Leave both *STR and *RELOC alone when returning false. */
14321 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14323 const struct percent_op_match
*percent_op
;
14326 if (mips_opts
.mips16
)
14328 percent_op
= mips16_percent_op
;
14329 limit
= ARRAY_SIZE (mips16_percent_op
);
14333 percent_op
= mips_percent_op
;
14334 limit
= ARRAY_SIZE (mips_percent_op
);
14337 for (i
= 0; i
< limit
; i
++)
14338 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14340 int len
= strlen (percent_op
[i
].str
);
14342 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14345 *str
+= strlen (percent_op
[i
].str
);
14346 *reloc
= percent_op
[i
].reloc
;
14348 /* Check whether the output BFD supports this relocation.
14349 If not, issue an error and fall back on something safe. */
14350 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14352 as_bad (_("relocation %s isn't supported by the current ABI"),
14353 percent_op
[i
].str
);
14354 *reloc
= BFD_RELOC_UNUSED
;
14362 /* Parse string STR as a 16-bit relocatable operand. Store the
14363 expression in *EP and the relocations in the array starting
14364 at RELOC. Return the number of relocation operators used.
14366 On exit, EXPR_END points to the first character after the expression. */
14369 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14372 bfd_reloc_code_real_type reversed_reloc
[3];
14373 size_t reloc_index
, i
;
14374 int crux_depth
, str_depth
;
14377 /* Search for the start of the main expression, recoding relocations
14378 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14379 of the main expression and with CRUX_DEPTH containing the number
14380 of open brackets at that point. */
14387 crux_depth
= str_depth
;
14389 /* Skip over whitespace and brackets, keeping count of the number
14391 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14396 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14397 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14399 my_getExpression (ep
, crux
);
14402 /* Match every open bracket. */
14403 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14407 if (crux_depth
> 0)
14408 as_bad (_("unclosed '('"));
14412 if (reloc_index
!= 0)
14414 prev_reloc_op_frag
= frag_now
;
14415 for (i
= 0; i
< reloc_index
; i
++)
14416 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14419 return reloc_index
;
14423 my_getExpression (expressionS
*ep
, char *str
)
14427 save_in
= input_line_pointer
;
14428 input_line_pointer
= str
;
14430 expr_end
= input_line_pointer
;
14431 input_line_pointer
= save_in
;
14435 md_atof (int type
, char *litP
, int *sizeP
)
14437 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14441 md_number_to_chars (char *buf
, valueT val
, int n
)
14443 if (target_big_endian
)
14444 number_to_chars_bigendian (buf
, val
, n
);
14446 number_to_chars_littleendian (buf
, val
, n
);
14449 static int support_64bit_objects(void)
14451 const char **list
, **l
;
14454 list
= bfd_target_list ();
14455 for (l
= list
; *l
!= NULL
; l
++)
14456 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14457 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14459 yes
= (*l
!= NULL
);
14464 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14465 NEW_VALUE. Warn if another value was already specified. Note:
14466 we have to defer parsing the -march and -mtune arguments in order
14467 to handle 'from-abi' correctly, since the ABI might be specified
14468 in a later argument. */
14471 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14473 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14474 as_warn (_("a different %s was already specified, is now %s"),
14475 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14478 *string_ptr
= new_value
;
14482 md_parse_option (int c
, const char *arg
)
14486 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14487 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14489 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14490 c
== mips_ases
[i
].option_on
);
14496 case OPTION_CONSTRUCT_FLOATS
:
14497 mips_disable_float_construction
= 0;
14500 case OPTION_NO_CONSTRUCT_FLOATS
:
14501 mips_disable_float_construction
= 1;
14513 target_big_endian
= 1;
14517 target_big_endian
= 0;
14523 else if (arg
[0] == '0')
14525 else if (arg
[0] == '1')
14535 mips_debug
= atoi (arg
);
14539 file_mips_opts
.isa
= ISA_MIPS1
;
14543 file_mips_opts
.isa
= ISA_MIPS2
;
14547 file_mips_opts
.isa
= ISA_MIPS3
;
14551 file_mips_opts
.isa
= ISA_MIPS4
;
14555 file_mips_opts
.isa
= ISA_MIPS5
;
14558 case OPTION_MIPS32
:
14559 file_mips_opts
.isa
= ISA_MIPS32
;
14562 case OPTION_MIPS32R2
:
14563 file_mips_opts
.isa
= ISA_MIPS32R2
;
14566 case OPTION_MIPS32R3
:
14567 file_mips_opts
.isa
= ISA_MIPS32R3
;
14570 case OPTION_MIPS32R5
:
14571 file_mips_opts
.isa
= ISA_MIPS32R5
;
14574 case OPTION_MIPS32R6
:
14575 file_mips_opts
.isa
= ISA_MIPS32R6
;
14578 case OPTION_MIPS64R2
:
14579 file_mips_opts
.isa
= ISA_MIPS64R2
;
14582 case OPTION_MIPS64R3
:
14583 file_mips_opts
.isa
= ISA_MIPS64R3
;
14586 case OPTION_MIPS64R5
:
14587 file_mips_opts
.isa
= ISA_MIPS64R5
;
14590 case OPTION_MIPS64R6
:
14591 file_mips_opts
.isa
= ISA_MIPS64R6
;
14594 case OPTION_MIPS64
:
14595 file_mips_opts
.isa
= ISA_MIPS64
;
14599 mips_set_option_string (&mips_tune_string
, arg
);
14603 mips_set_option_string (&mips_arch_string
, arg
);
14607 mips_set_option_string (&mips_arch_string
, "4650");
14608 mips_set_option_string (&mips_tune_string
, "4650");
14611 case OPTION_NO_M4650
:
14615 mips_set_option_string (&mips_arch_string
, "4010");
14616 mips_set_option_string (&mips_tune_string
, "4010");
14619 case OPTION_NO_M4010
:
14623 mips_set_option_string (&mips_arch_string
, "4100");
14624 mips_set_option_string (&mips_tune_string
, "4100");
14627 case OPTION_NO_M4100
:
14631 mips_set_option_string (&mips_arch_string
, "3900");
14632 mips_set_option_string (&mips_tune_string
, "3900");
14635 case OPTION_NO_M3900
:
14638 case OPTION_MICROMIPS
:
14639 if (file_mips_opts
.mips16
== 1)
14641 as_bad (_("-mmicromips cannot be used with -mips16"));
14644 file_mips_opts
.micromips
= 1;
14645 mips_no_prev_insn ();
14648 case OPTION_NO_MICROMIPS
:
14649 file_mips_opts
.micromips
= 0;
14650 mips_no_prev_insn ();
14653 case OPTION_MIPS16
:
14654 if (file_mips_opts
.micromips
== 1)
14656 as_bad (_("-mips16 cannot be used with -micromips"));
14659 file_mips_opts
.mips16
= 1;
14660 mips_no_prev_insn ();
14663 case OPTION_NO_MIPS16
:
14664 file_mips_opts
.mips16
= 0;
14665 mips_no_prev_insn ();
14668 case OPTION_FIX_24K
:
14672 case OPTION_NO_FIX_24K
:
14676 case OPTION_FIX_RM7000
:
14677 mips_fix_rm7000
= 1;
14680 case OPTION_NO_FIX_RM7000
:
14681 mips_fix_rm7000
= 0;
14684 case OPTION_FIX_LOONGSON2F_JUMP
:
14685 mips_fix_loongson2f_jump
= TRUE
;
14688 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14689 mips_fix_loongson2f_jump
= FALSE
;
14692 case OPTION_FIX_LOONGSON2F_NOP
:
14693 mips_fix_loongson2f_nop
= TRUE
;
14696 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14697 mips_fix_loongson2f_nop
= FALSE
;
14700 case OPTION_FIX_VR4120
:
14701 mips_fix_vr4120
= 1;
14704 case OPTION_NO_FIX_VR4120
:
14705 mips_fix_vr4120
= 0;
14708 case OPTION_FIX_VR4130
:
14709 mips_fix_vr4130
= 1;
14712 case OPTION_NO_FIX_VR4130
:
14713 mips_fix_vr4130
= 0;
14716 case OPTION_FIX_CN63XXP1
:
14717 mips_fix_cn63xxp1
= TRUE
;
14720 case OPTION_NO_FIX_CN63XXP1
:
14721 mips_fix_cn63xxp1
= FALSE
;
14724 case OPTION_RELAX_BRANCH
:
14725 mips_relax_branch
= 1;
14728 case OPTION_NO_RELAX_BRANCH
:
14729 mips_relax_branch
= 0;
14732 case OPTION_IGNORE_BRANCH_ISA
:
14733 mips_ignore_branch_isa
= TRUE
;
14736 case OPTION_NO_IGNORE_BRANCH_ISA
:
14737 mips_ignore_branch_isa
= FALSE
;
14740 case OPTION_INSN32
:
14741 file_mips_opts
.insn32
= TRUE
;
14744 case OPTION_NO_INSN32
:
14745 file_mips_opts
.insn32
= FALSE
;
14748 case OPTION_MSHARED
:
14749 mips_in_shared
= TRUE
;
14752 case OPTION_MNO_SHARED
:
14753 mips_in_shared
= FALSE
;
14756 case OPTION_MSYM32
:
14757 file_mips_opts
.sym32
= TRUE
;
14760 case OPTION_MNO_SYM32
:
14761 file_mips_opts
.sym32
= FALSE
;
14764 /* When generating ELF code, we permit -KPIC and -call_shared to
14765 select SVR4_PIC, and -non_shared to select no PIC. This is
14766 intended to be compatible with Irix 5. */
14767 case OPTION_CALL_SHARED
:
14768 mips_pic
= SVR4_PIC
;
14769 mips_abicalls
= TRUE
;
14772 case OPTION_CALL_NONPIC
:
14774 mips_abicalls
= TRUE
;
14777 case OPTION_NON_SHARED
:
14779 mips_abicalls
= FALSE
;
14782 /* The -xgot option tells the assembler to use 32 bit offsets
14783 when accessing the got in SVR4_PIC mode. It is for Irix
14790 g_switch_value
= atoi (arg
);
14794 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14797 mips_abi
= O32_ABI
;
14801 mips_abi
= N32_ABI
;
14805 mips_abi
= N64_ABI
;
14806 if (!support_64bit_objects())
14807 as_fatal (_("no compiled in support for 64 bit object file format"));
14811 file_mips_opts
.gp
= 32;
14815 file_mips_opts
.gp
= 64;
14819 file_mips_opts
.fp
= 32;
14823 file_mips_opts
.fp
= 0;
14827 file_mips_opts
.fp
= 64;
14830 case OPTION_ODD_SPREG
:
14831 file_mips_opts
.oddspreg
= 1;
14834 case OPTION_NO_ODD_SPREG
:
14835 file_mips_opts
.oddspreg
= 0;
14838 case OPTION_SINGLE_FLOAT
:
14839 file_mips_opts
.single_float
= 1;
14842 case OPTION_DOUBLE_FLOAT
:
14843 file_mips_opts
.single_float
= 0;
14846 case OPTION_SOFT_FLOAT
:
14847 file_mips_opts
.soft_float
= 1;
14850 case OPTION_HARD_FLOAT
:
14851 file_mips_opts
.soft_float
= 0;
14855 if (strcmp (arg
, "32") == 0)
14856 mips_abi
= O32_ABI
;
14857 else if (strcmp (arg
, "o64") == 0)
14858 mips_abi
= O64_ABI
;
14859 else if (strcmp (arg
, "n32") == 0)
14860 mips_abi
= N32_ABI
;
14861 else if (strcmp (arg
, "64") == 0)
14863 mips_abi
= N64_ABI
;
14864 if (! support_64bit_objects())
14865 as_fatal (_("no compiled in support for 64 bit object file "
14868 else if (strcmp (arg
, "eabi") == 0)
14869 mips_abi
= EABI_ABI
;
14872 as_fatal (_("invalid abi -mabi=%s"), arg
);
14877 case OPTION_M7000_HILO_FIX
:
14878 mips_7000_hilo_fix
= TRUE
;
14881 case OPTION_MNO_7000_HILO_FIX
:
14882 mips_7000_hilo_fix
= FALSE
;
14885 case OPTION_MDEBUG
:
14886 mips_flag_mdebug
= TRUE
;
14889 case OPTION_NO_MDEBUG
:
14890 mips_flag_mdebug
= FALSE
;
14894 mips_flag_pdr
= TRUE
;
14897 case OPTION_NO_PDR
:
14898 mips_flag_pdr
= FALSE
;
14901 case OPTION_MVXWORKS_PIC
:
14902 mips_pic
= VXWORKS_PIC
;
14906 if (strcmp (arg
, "2008") == 0)
14908 else if (strcmp (arg
, "legacy") == 0)
14912 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14921 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14926 /* Set up globals to tune for the ISA or processor described by INFO. */
14929 mips_set_tune (const struct mips_cpu_info
*info
)
14932 mips_tune
= info
->cpu
;
14937 mips_after_parse_args (void)
14939 const struct mips_cpu_info
*arch_info
= 0;
14940 const struct mips_cpu_info
*tune_info
= 0;
14942 /* GP relative stuff not working for PE */
14943 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14945 if (g_switch_seen
&& g_switch_value
!= 0)
14946 as_bad (_("-G not supported in this configuration"));
14947 g_switch_value
= 0;
14950 if (mips_abi
== NO_ABI
)
14951 mips_abi
= MIPS_DEFAULT_ABI
;
14953 /* The following code determines the architecture.
14954 Similar code was added to GCC 3.3 (see override_options() in
14955 config/mips/mips.c). The GAS and GCC code should be kept in sync
14956 as much as possible. */
14958 if (mips_arch_string
!= 0)
14959 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14961 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14963 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14964 ISA level specified by -mipsN, while arch_info->isa contains
14965 the -march selection (if any). */
14966 if (arch_info
!= 0)
14968 /* -march takes precedence over -mipsN, since it is more descriptive.
14969 There's no harm in specifying both as long as the ISA levels
14971 if (file_mips_opts
.isa
!= arch_info
->isa
)
14972 as_bad (_("-%s conflicts with the other architecture options,"
14973 " which imply -%s"),
14974 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14975 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14978 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14981 if (arch_info
== 0)
14983 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14984 gas_assert (arch_info
);
14987 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14988 as_bad (_("-march=%s is not compatible with the selected ABI"),
14991 file_mips_opts
.arch
= arch_info
->cpu
;
14992 file_mips_opts
.isa
= arch_info
->isa
;
14994 /* Set up initial mips_opts state. */
14995 mips_opts
= file_mips_opts
;
14997 /* The register size inference code is now placed in
14998 file_mips_check_options. */
15000 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15002 if (mips_tune_string
!= 0)
15003 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15005 if (tune_info
== 0)
15006 mips_set_tune (arch_info
);
15008 mips_set_tune (tune_info
);
15010 if (mips_flag_mdebug
< 0)
15011 mips_flag_mdebug
= 0;
15015 mips_init_after_args (void)
15017 /* initialize opcodes */
15018 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15019 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15023 md_pcrel_from (fixS
*fixP
)
15025 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15026 switch (fixP
->fx_r_type
)
15028 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15029 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15030 /* Return the address of the delay slot. */
15033 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15034 case BFD_RELOC_MICROMIPS_JMP
:
15035 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15036 case BFD_RELOC_16_PCREL_S2
:
15037 case BFD_RELOC_MIPS_21_PCREL_S2
:
15038 case BFD_RELOC_MIPS_26_PCREL_S2
:
15039 case BFD_RELOC_MIPS_JMP
:
15040 /* Return the address of the delay slot. */
15043 case BFD_RELOC_MIPS_18_PCREL_S3
:
15044 /* Return the aligned address of the doubleword containing
15045 the instruction. */
15053 /* This is called before the symbol table is processed. In order to
15054 work with gcc when using mips-tfile, we must keep all local labels.
15055 However, in other cases, we want to discard them. If we were
15056 called with -g, but we didn't see any debugging information, it may
15057 mean that gcc is smuggling debugging information through to
15058 mips-tfile, in which case we must generate all local labels. */
15061 mips_frob_file_before_adjust (void)
15063 #ifndef NO_ECOFF_DEBUGGING
15064 if (ECOFF_DEBUGGING
15066 && ! ecoff_debugging_seen
)
15067 flag_keep_locals
= 1;
15071 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15072 the corresponding LO16 reloc. This is called before md_apply_fix and
15073 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15074 relocation operators.
15076 For our purposes, a %lo() expression matches a %got() or %hi()
15079 (a) it refers to the same symbol; and
15080 (b) the offset applied in the %lo() expression is no lower than
15081 the offset applied in the %got() or %hi().
15083 (b) allows us to cope with code like:
15086 lh $4,%lo(foo+2)($4)
15088 ...which is legal on RELA targets, and has a well-defined behaviour
15089 if the user knows that adding 2 to "foo" will not induce a carry to
15092 When several %lo()s match a particular %got() or %hi(), we use the
15093 following rules to distinguish them:
15095 (1) %lo()s with smaller offsets are a better match than %lo()s with
15098 (2) %lo()s with no matching %got() or %hi() are better than those
15099 that already have a matching %got() or %hi().
15101 (3) later %lo()s are better than earlier %lo()s.
15103 These rules are applied in order.
15105 (1) means, among other things, that %lo()s with identical offsets are
15106 chosen if they exist.
15108 (2) means that we won't associate several high-part relocations with
15109 the same low-part relocation unless there's no alternative. Having
15110 several high parts for the same low part is a GNU extension; this rule
15111 allows careful users to avoid it.
15113 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15114 with the last high-part relocation being at the front of the list.
15115 It therefore makes sense to choose the last matching low-part
15116 relocation, all other things being equal. It's also easier
15117 to code that way. */
15120 mips_frob_file (void)
15122 struct mips_hi_fixup
*l
;
15123 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15125 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15127 segment_info_type
*seginfo
;
15128 bfd_boolean matched_lo_p
;
15129 fixS
**hi_pos
, **lo_pos
, **pos
;
15131 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15133 /* If a GOT16 relocation turns out to be against a global symbol,
15134 there isn't supposed to be a matching LO. Ignore %gots against
15135 constants; we'll report an error for those later. */
15136 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15137 && !(l
->fixp
->fx_addsy
15138 && pic_need_relax (l
->fixp
->fx_addsy
)))
15141 /* Check quickly whether the next fixup happens to be a matching %lo. */
15142 if (fixup_has_matching_lo_p (l
->fixp
))
15145 seginfo
= seg_info (l
->seg
);
15147 /* Set HI_POS to the position of this relocation in the chain.
15148 Set LO_POS to the position of the chosen low-part relocation.
15149 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15150 relocation that matches an immediately-preceding high-part
15154 matched_lo_p
= FALSE
;
15155 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15157 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15159 if (*pos
== l
->fixp
)
15162 if ((*pos
)->fx_r_type
== looking_for_rtype
15163 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15164 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15166 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15168 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15171 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15172 && fixup_has_matching_lo_p (*pos
));
15175 /* If we found a match, remove the high-part relocation from its
15176 current position and insert it before the low-part relocation.
15177 Make the offsets match so that fixup_has_matching_lo_p()
15180 We don't warn about unmatched high-part relocations since some
15181 versions of gcc have been known to emit dead "lui ...%hi(...)"
15183 if (lo_pos
!= NULL
)
15185 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15186 if (l
->fixp
->fx_next
!= *lo_pos
)
15188 *hi_pos
= l
->fixp
->fx_next
;
15189 l
->fixp
->fx_next
= *lo_pos
;
15197 mips_force_relocation (fixS
*fixp
)
15199 if (generic_force_reloc (fixp
))
15202 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15203 so that the linker relaxation can update targets. */
15204 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15205 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15206 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15209 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15210 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15211 microMIPS symbols so that we can do cross-mode branch diagnostics
15212 and BAL to JALX conversion by the linker. */
15213 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15214 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15215 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15217 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15220 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15221 if (ISA_IS_R6 (file_mips_opts
.isa
)
15222 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15223 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15224 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15225 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15226 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15227 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15228 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15234 /* Implement TC_FORCE_RELOCATION_ABS. */
15237 mips_force_relocation_abs (fixS
*fixp
)
15239 if (generic_force_reloc (fixp
))
15242 /* These relocations do not have enough bits in the in-place addend
15243 to hold an arbitrary absolute section's offset. */
15244 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15250 /* Read the instruction associated with RELOC from BUF. */
15252 static unsigned int
15253 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15255 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15256 return read_compressed_insn (buf
, 4);
15258 return read_insn (buf
);
15261 /* Write instruction INSN to BUF, given that it has been relocated
15265 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15266 unsigned long insn
)
15268 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15269 write_compressed_insn (buf
, insn
, 4);
15271 write_insn (buf
, insn
);
15274 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15275 to a symbol in another ISA mode, which cannot be converted to JALX. */
15278 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15280 unsigned long opcode
;
15284 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15287 other
= S_GET_OTHER (fixP
->fx_addsy
);
15288 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15289 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15290 switch (fixP
->fx_r_type
)
15292 case BFD_RELOC_MIPS_JMP
:
15293 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15294 case BFD_RELOC_MICROMIPS_JMP
:
15295 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15301 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15302 jump to a symbol in the same ISA mode. */
15305 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15307 unsigned long opcode
;
15311 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15314 other
= S_GET_OTHER (fixP
->fx_addsy
);
15315 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15316 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15317 switch (fixP
->fx_r_type
)
15319 case BFD_RELOC_MIPS_JMP
:
15320 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15321 case BFD_RELOC_MIPS16_JMP
:
15322 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15323 case BFD_RELOC_MICROMIPS_JMP
:
15324 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15330 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15331 to a symbol whose value plus addend is not aligned according to the
15332 ultimate (after linker relaxation) jump instruction's immediate field
15333 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15334 regular MIPS code, to (1 << 2). */
15337 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15339 bfd_boolean micro_to_mips_p
;
15343 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15346 other
= S_GET_OTHER (fixP
->fx_addsy
);
15347 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15348 val
+= fixP
->fx_offset
;
15349 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15350 && !ELF_ST_IS_MICROMIPS (other
));
15351 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15352 != ELF_ST_IS_COMPRESSED (other
));
15355 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15356 to a symbol whose annotation indicates another ISA mode. For absolute
15357 symbols check the ISA bit instead.
15359 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15360 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15361 MIPS symbols and associated with BAL instructions as these instructions
15362 may be converted to JALX by the linker. */
15365 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15367 bfd_boolean absolute_p
;
15368 unsigned long opcode
;
15374 if (mips_ignore_branch_isa
)
15377 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15380 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15381 absolute_p
= bfd_is_abs_section (symsec
);
15383 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15384 other
= S_GET_OTHER (fixP
->fx_addsy
);
15386 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15387 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15388 switch (fixP
->fx_r_type
)
15390 case BFD_RELOC_16_PCREL_S2
:
15391 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15392 && opcode
!= 0x0411);
15393 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15394 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15395 && opcode
!= 0x4060);
15396 case BFD_RELOC_MIPS_21_PCREL_S2
:
15397 case BFD_RELOC_MIPS_26_PCREL_S2
:
15398 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15399 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15400 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15401 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15402 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15403 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15409 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15410 branch instruction pointed to by FIXP is not aligned according to the
15411 branch instruction's immediate field requirement. We need the addend
15412 to preserve the ISA bit and also the sum must not have bit 2 set. We
15413 must explicitly OR in the ISA bit from symbol annotation as the bit
15414 won't be set in the symbol's value then. */
15417 fix_bad_misaligned_branch_p (fixS
*fixP
)
15419 bfd_boolean absolute_p
;
15426 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15429 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15430 absolute_p
= bfd_is_abs_section (symsec
);
15432 val
= S_GET_VALUE (fixP
->fx_addsy
);
15433 other
= S_GET_OTHER (fixP
->fx_addsy
);
15434 off
= fixP
->fx_offset
;
15436 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15437 val
|= ELF_ST_IS_COMPRESSED (other
);
15439 return (val
& 0x3) != isa_bit
;
15442 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15443 and its calculated value VAL. */
15446 fix_validate_branch (fixS
*fixP
, valueT val
)
15448 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15450 _("branch to misaligned address (0x%lx)"),
15451 (long) (val
+ md_pcrel_from (fixP
)));
15452 else if (fix_bad_cross_mode_branch_p (fixP
))
15453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15454 _("branch to a symbol in another ISA mode"));
15455 else if (fix_bad_misaligned_branch_p (fixP
))
15456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15457 _("branch to misaligned address (0x%lx)"),
15458 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15459 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15461 _("cannot encode misaligned addend "
15462 "in the relocatable field (0x%lx)"),
15463 (long) fixP
->fx_offset
);
15466 /* Apply a fixup to the object file. */
15469 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15472 unsigned long insn
;
15473 reloc_howto_type
*howto
;
15475 if (fixP
->fx_pcrel
)
15476 switch (fixP
->fx_r_type
)
15478 case BFD_RELOC_16_PCREL_S2
:
15479 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15480 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15481 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15482 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15483 case BFD_RELOC_32_PCREL
:
15484 case BFD_RELOC_MIPS_21_PCREL_S2
:
15485 case BFD_RELOC_MIPS_26_PCREL_S2
:
15486 case BFD_RELOC_MIPS_18_PCREL_S3
:
15487 case BFD_RELOC_MIPS_19_PCREL_S2
:
15488 case BFD_RELOC_HI16_S_PCREL
:
15489 case BFD_RELOC_LO16_PCREL
:
15493 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15497 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15498 _("PC-relative reference to a different section"));
15502 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15503 that have no MIPS ELF equivalent. */
15504 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15506 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15511 gas_assert (fixP
->fx_size
== 2
15512 || fixP
->fx_size
== 4
15513 || fixP
->fx_r_type
== BFD_RELOC_8
15514 || fixP
->fx_r_type
== BFD_RELOC_16
15515 || fixP
->fx_r_type
== BFD_RELOC_64
15516 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15517 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15518 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15519 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15520 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15521 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15522 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15524 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15526 /* Don't treat parts of a composite relocation as done. There are two
15529 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15530 should nevertheless be emitted if the first part is.
15532 (2) In normal usage, composite relocations are never assembly-time
15533 constants. The easiest way of dealing with the pathological
15534 exceptions is to generate a relocation against STN_UNDEF and
15535 leave everything up to the linker. */
15536 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15539 switch (fixP
->fx_r_type
)
15541 case BFD_RELOC_MIPS_TLS_GD
:
15542 case BFD_RELOC_MIPS_TLS_LDM
:
15543 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15544 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15545 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15546 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15547 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15548 case BFD_RELOC_MIPS_TLS_TPREL32
:
15549 case BFD_RELOC_MIPS_TLS_TPREL64
:
15550 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15551 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15552 case BFD_RELOC_MICROMIPS_TLS_GD
:
15553 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15554 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15555 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15556 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15557 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15558 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15559 case BFD_RELOC_MIPS16_TLS_GD
:
15560 case BFD_RELOC_MIPS16_TLS_LDM
:
15561 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15562 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15563 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15564 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15565 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15566 if (fixP
->fx_addsy
)
15567 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15570 _("TLS relocation against a constant"));
15573 case BFD_RELOC_MIPS_JMP
:
15574 case BFD_RELOC_MIPS16_JMP
:
15575 case BFD_RELOC_MICROMIPS_JMP
:
15579 gas_assert (!fixP
->fx_done
);
15581 /* Shift is 2, unusually, for microMIPS JALX. */
15582 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15583 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15588 if (fix_bad_cross_mode_jump_p (fixP
))
15589 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15590 _("jump to a symbol in another ISA mode"));
15591 else if (fix_bad_same_mode_jalx_p (fixP
))
15592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15593 _("JALX to a symbol in the same ISA mode"));
15594 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15595 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15596 _("jump to misaligned address (0x%lx)"),
15597 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15598 + fixP
->fx_offset
));
15599 else if (HAVE_IN_PLACE_ADDENDS
15600 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15602 _("cannot encode misaligned addend "
15603 "in the relocatable field (0x%lx)"),
15604 (long) fixP
->fx_offset
);
15606 /* Fall through. */
15608 case BFD_RELOC_MIPS_SHIFT5
:
15609 case BFD_RELOC_MIPS_SHIFT6
:
15610 case BFD_RELOC_MIPS_GOT_DISP
:
15611 case BFD_RELOC_MIPS_GOT_PAGE
:
15612 case BFD_RELOC_MIPS_GOT_OFST
:
15613 case BFD_RELOC_MIPS_SUB
:
15614 case BFD_RELOC_MIPS_INSERT_A
:
15615 case BFD_RELOC_MIPS_INSERT_B
:
15616 case BFD_RELOC_MIPS_DELETE
:
15617 case BFD_RELOC_MIPS_HIGHEST
:
15618 case BFD_RELOC_MIPS_HIGHER
:
15619 case BFD_RELOC_MIPS_SCN_DISP
:
15620 case BFD_RELOC_MIPS_REL16
:
15621 case BFD_RELOC_MIPS_RELGOT
:
15622 case BFD_RELOC_MIPS_JALR
:
15623 case BFD_RELOC_HI16
:
15624 case BFD_RELOC_HI16_S
:
15625 case BFD_RELOC_LO16
:
15626 case BFD_RELOC_GPREL16
:
15627 case BFD_RELOC_MIPS_LITERAL
:
15628 case BFD_RELOC_MIPS_CALL16
:
15629 case BFD_RELOC_MIPS_GOT16
:
15630 case BFD_RELOC_GPREL32
:
15631 case BFD_RELOC_MIPS_GOT_HI16
:
15632 case BFD_RELOC_MIPS_GOT_LO16
:
15633 case BFD_RELOC_MIPS_CALL_HI16
:
15634 case BFD_RELOC_MIPS_CALL_LO16
:
15635 case BFD_RELOC_HI16_S_PCREL
:
15636 case BFD_RELOC_LO16_PCREL
:
15637 case BFD_RELOC_MIPS16_GPREL
:
15638 case BFD_RELOC_MIPS16_GOT16
:
15639 case BFD_RELOC_MIPS16_CALL16
:
15640 case BFD_RELOC_MIPS16_HI16
:
15641 case BFD_RELOC_MIPS16_HI16_S
:
15642 case BFD_RELOC_MIPS16_LO16
:
15643 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15644 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15645 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15646 case BFD_RELOC_MICROMIPS_SUB
:
15647 case BFD_RELOC_MICROMIPS_HIGHEST
:
15648 case BFD_RELOC_MICROMIPS_HIGHER
:
15649 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15650 case BFD_RELOC_MICROMIPS_JALR
:
15651 case BFD_RELOC_MICROMIPS_HI16
:
15652 case BFD_RELOC_MICROMIPS_HI16_S
:
15653 case BFD_RELOC_MICROMIPS_LO16
:
15654 case BFD_RELOC_MICROMIPS_GPREL16
:
15655 case BFD_RELOC_MICROMIPS_LITERAL
:
15656 case BFD_RELOC_MICROMIPS_CALL16
:
15657 case BFD_RELOC_MICROMIPS_GOT16
:
15658 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15659 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15660 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15661 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15662 case BFD_RELOC_MIPS_EH
:
15667 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15669 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15670 if (mips16_reloc_p (fixP
->fx_r_type
))
15671 insn
|= mips16_immed_extend (value
, 16);
15673 insn
|= (value
& 0xffff);
15674 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15677 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15678 _("unsupported constant in relocation"));
15683 /* This is handled like BFD_RELOC_32, but we output a sign
15684 extended value if we are only 32 bits. */
15687 if (8 <= sizeof (valueT
))
15688 md_number_to_chars (buf
, *valP
, 8);
15693 if ((*valP
& 0x80000000) != 0)
15697 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15698 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15703 case BFD_RELOC_RVA
:
15705 case BFD_RELOC_32_PCREL
:
15708 /* If we are deleting this reloc entry, we must fill in the
15709 value now. This can happen if we have a .word which is not
15710 resolved when it appears but is later defined. */
15712 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15715 case BFD_RELOC_MIPS_21_PCREL_S2
:
15716 fix_validate_branch (fixP
, *valP
);
15717 if (!fixP
->fx_done
)
15720 if (*valP
+ 0x400000 <= 0x7fffff)
15722 insn
= read_insn (buf
);
15723 insn
|= (*valP
>> 2) & 0x1fffff;
15724 write_insn (buf
, insn
);
15727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15728 _("branch out of range"));
15731 case BFD_RELOC_MIPS_26_PCREL_S2
:
15732 fix_validate_branch (fixP
, *valP
);
15733 if (!fixP
->fx_done
)
15736 if (*valP
+ 0x8000000 <= 0xfffffff)
15738 insn
= read_insn (buf
);
15739 insn
|= (*valP
>> 2) & 0x3ffffff;
15740 write_insn (buf
, insn
);
15743 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15744 _("branch out of range"));
15747 case BFD_RELOC_MIPS_18_PCREL_S3
:
15748 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15750 _("PC-relative access using misaligned symbol (%lx)"),
15751 (long) S_GET_VALUE (fixP
->fx_addsy
));
15752 if ((fixP
->fx_offset
& 0x7) != 0)
15753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15754 _("PC-relative access using misaligned offset (%lx)"),
15755 (long) fixP
->fx_offset
);
15756 if (!fixP
->fx_done
)
15759 if (*valP
+ 0x100000 <= 0x1fffff)
15761 insn
= read_insn (buf
);
15762 insn
|= (*valP
>> 3) & 0x3ffff;
15763 write_insn (buf
, insn
);
15766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15767 _("PC-relative access out of range"));
15770 case BFD_RELOC_MIPS_19_PCREL_S2
:
15771 if ((*valP
& 0x3) != 0)
15772 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15773 _("PC-relative access to misaligned address (%lx)"),
15775 if (!fixP
->fx_done
)
15778 if (*valP
+ 0x100000 <= 0x1fffff)
15780 insn
= read_insn (buf
);
15781 insn
|= (*valP
>> 2) & 0x7ffff;
15782 write_insn (buf
, insn
);
15785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15786 _("PC-relative access out of range"));
15789 case BFD_RELOC_16_PCREL_S2
:
15790 fix_validate_branch (fixP
, *valP
);
15792 /* We need to save the bits in the instruction since fixup_segment()
15793 might be deleting the relocation entry (i.e., a branch within
15794 the current segment). */
15795 if (! fixP
->fx_done
)
15798 /* Update old instruction data. */
15799 insn
= read_insn (buf
);
15801 if (*valP
+ 0x20000 <= 0x3ffff)
15803 insn
|= (*valP
>> 2) & 0xffff;
15804 write_insn (buf
, insn
);
15806 else if (fixP
->fx_tcbit2
15808 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15809 && (fixP
->fx_frag
->fr_address
15810 < text_section
->vma
+ bfd_get_section_size (text_section
))
15811 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15812 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15813 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15815 /* The branch offset is too large. If this is an
15816 unconditional branch, and we are not generating PIC code,
15817 we can convert it to an absolute jump instruction. */
15818 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15819 insn
= 0x0c000000; /* jal */
15821 insn
= 0x08000000; /* j */
15822 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15824 fixP
->fx_addsy
= section_symbol (text_section
);
15825 *valP
+= md_pcrel_from (fixP
);
15826 write_insn (buf
, insn
);
15830 /* If we got here, we have branch-relaxation disabled,
15831 and there's nothing we can do to fix this instruction
15832 without turning it into a longer sequence. */
15833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15834 _("branch out of range"));
15838 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15839 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15840 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15841 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15842 gas_assert (!fixP
->fx_done
);
15843 if (fix_bad_cross_mode_branch_p (fixP
))
15844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15845 _("branch to a symbol in another ISA mode"));
15846 else if (fixP
->fx_addsy
15847 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15848 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15849 && (fixP
->fx_offset
& 0x1) != 0)
15850 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15851 _("branch to misaligned address (0x%lx)"),
15852 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15853 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15855 _("cannot encode misaligned addend "
15856 "in the relocatable field (0x%lx)"),
15857 (long) fixP
->fx_offset
);
15860 case BFD_RELOC_VTABLE_INHERIT
:
15863 && !S_IS_DEFINED (fixP
->fx_addsy
)
15864 && !S_IS_WEAK (fixP
->fx_addsy
))
15865 S_SET_WEAK (fixP
->fx_addsy
);
15868 case BFD_RELOC_NONE
:
15869 case BFD_RELOC_VTABLE_ENTRY
:
15877 /* Remember value for tc_gen_reloc. */
15878 fixP
->fx_addnumber
= *valP
;
15888 c
= get_symbol_name (&name
);
15889 p
= (symbolS
*) symbol_find_or_make (name
);
15890 (void) restore_line_pointer (c
);
15894 /* Align the current frag to a given power of two. If a particular
15895 fill byte should be used, FILL points to an integer that contains
15896 that byte, otherwise FILL is null.
15898 This function used to have the comment:
15900 The MIPS assembler also automatically adjusts any preceding label.
15902 The implementation therefore applied the adjustment to a maximum of
15903 one label. However, other label adjustments are applied to batches
15904 of labels, and adjusting just one caused problems when new labels
15905 were added for the sake of debugging or unwind information.
15906 We therefore adjust all preceding labels (given as LABELS) instead. */
15909 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15911 mips_emit_delays ();
15912 mips_record_compressed_mode ();
15913 if (fill
== NULL
&& subseg_text_p (now_seg
))
15914 frag_align_code (to
, 0);
15916 frag_align (to
, fill
? *fill
: 0, 0);
15917 record_alignment (now_seg
, to
);
15918 mips_move_labels (labels
, FALSE
);
15921 /* Align to a given power of two. .align 0 turns off the automatic
15922 alignment used by the data creating pseudo-ops. */
15925 s_align (int x ATTRIBUTE_UNUSED
)
15927 int temp
, fill_value
, *fill_ptr
;
15928 long max_alignment
= 28;
15930 /* o Note that the assembler pulls down any immediately preceding label
15931 to the aligned address.
15932 o It's not documented but auto alignment is reinstated by
15933 a .align pseudo instruction.
15934 o Note also that after auto alignment is turned off the mips assembler
15935 issues an error on attempt to assemble an improperly aligned data item.
15938 temp
= get_absolute_expression ();
15939 if (temp
> max_alignment
)
15940 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15943 as_warn (_("alignment negative, 0 assumed"));
15946 if (*input_line_pointer
== ',')
15948 ++input_line_pointer
;
15949 fill_value
= get_absolute_expression ();
15950 fill_ptr
= &fill_value
;
15956 segment_info_type
*si
= seg_info (now_seg
);
15957 struct insn_label_list
*l
= si
->label_list
;
15958 /* Auto alignment should be switched on by next section change. */
15960 mips_align (temp
, fill_ptr
, l
);
15967 demand_empty_rest_of_line ();
15971 s_change_sec (int sec
)
15975 /* The ELF backend needs to know that we are changing sections, so
15976 that .previous works correctly. We could do something like check
15977 for an obj_section_change_hook macro, but that might be confusing
15978 as it would not be appropriate to use it in the section changing
15979 functions in read.c, since obj-elf.c intercepts those. FIXME:
15980 This should be cleaner, somehow. */
15981 obj_elf_section_change_hook ();
15983 mips_emit_delays ();
15994 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15995 demand_empty_rest_of_line ();
15999 seg
= subseg_new (RDATA_SECTION_NAME
,
16000 (subsegT
) get_absolute_expression ());
16001 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16002 | SEC_READONLY
| SEC_RELOC
16004 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16005 record_alignment (seg
, 4);
16006 demand_empty_rest_of_line ();
16010 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16011 bfd_set_section_flags (stdoutput
, seg
,
16012 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16013 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16014 record_alignment (seg
, 4);
16015 demand_empty_rest_of_line ();
16019 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16020 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16021 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16022 record_alignment (seg
, 4);
16023 demand_empty_rest_of_line ();
16031 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16034 char *section_name
;
16039 int section_entry_size
;
16040 int section_alignment
;
16042 saved_ilp
= input_line_pointer
;
16043 endc
= get_symbol_name (§ion_name
);
16044 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16046 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16048 /* Do we have .section Name<,"flags">? */
16049 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16051 /* Just after name is now '\0'. */
16052 (void) restore_line_pointer (endc
);
16053 input_line_pointer
= saved_ilp
;
16054 obj_elf_section (ignore
);
16058 section_name
= xstrdup (section_name
);
16059 c
= restore_line_pointer (endc
);
16061 input_line_pointer
++;
16063 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16065 section_type
= get_absolute_expression ();
16069 if (*input_line_pointer
++ == ',')
16070 section_flag
= get_absolute_expression ();
16074 if (*input_line_pointer
++ == ',')
16075 section_entry_size
= get_absolute_expression ();
16077 section_entry_size
= 0;
16079 if (*input_line_pointer
++ == ',')
16080 section_alignment
= get_absolute_expression ();
16082 section_alignment
= 0;
16084 /* FIXME: really ignore? */
16085 (void) section_alignment
;
16087 /* When using the generic form of .section (as implemented by obj-elf.c),
16088 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16089 traditionally had to fall back on the more common @progbits instead.
16091 There's nothing really harmful in this, since bfd will correct
16092 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16093 means that, for backwards compatibility, the special_section entries
16094 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16096 Even so, we shouldn't force users of the MIPS .section syntax to
16097 incorrectly label the sections as SHT_PROGBITS. The best compromise
16098 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16099 generic type-checking code. */
16100 if (section_type
== SHT_MIPS_DWARF
)
16101 section_type
= SHT_PROGBITS
;
16103 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
16104 section_entry_size
, 0, 0, 0);
16106 if (now_seg
->name
!= section_name
)
16107 free (section_name
);
16111 mips_enable_auto_align (void)
16117 s_cons (int log_size
)
16119 segment_info_type
*si
= seg_info (now_seg
);
16120 struct insn_label_list
*l
= si
->label_list
;
16122 mips_emit_delays ();
16123 if (log_size
> 0 && auto_align
)
16124 mips_align (log_size
, 0, l
);
16125 cons (1 << log_size
);
16126 mips_clear_insn_labels ();
16130 s_float_cons (int type
)
16132 segment_info_type
*si
= seg_info (now_seg
);
16133 struct insn_label_list
*l
= si
->label_list
;
16135 mips_emit_delays ();
16140 mips_align (3, 0, l
);
16142 mips_align (2, 0, l
);
16146 mips_clear_insn_labels ();
16149 /* Handle .globl. We need to override it because on Irix 5 you are
16152 where foo is an undefined symbol, to mean that foo should be
16153 considered to be the address of a function. */
16156 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16165 c
= get_symbol_name (&name
);
16166 symbolP
= symbol_find_or_make (name
);
16167 S_SET_EXTERNAL (symbolP
);
16169 *input_line_pointer
= c
;
16170 SKIP_WHITESPACE_AFTER_NAME ();
16172 /* On Irix 5, every global symbol that is not explicitly labelled as
16173 being a function is apparently labelled as being an object. */
16176 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16177 && (*input_line_pointer
!= ','))
16182 c
= get_symbol_name (&secname
);
16183 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16185 as_bad (_("%s: no such section"), secname
);
16186 (void) restore_line_pointer (c
);
16188 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16189 flag
= BSF_FUNCTION
;
16192 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16194 c
= *input_line_pointer
;
16197 input_line_pointer
++;
16198 SKIP_WHITESPACE ();
16199 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16205 demand_empty_rest_of_line ();
16209 s_option (int x ATTRIBUTE_UNUSED
)
16214 c
= get_symbol_name (&opt
);
16218 /* FIXME: What does this mean? */
16220 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16224 i
= atoi (opt
+ 3);
16225 if (i
!= 0 && i
!= 2)
16226 as_bad (_(".option pic%d not supported"), i
);
16227 else if (mips_pic
== VXWORKS_PIC
)
16228 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16233 mips_pic
= SVR4_PIC
;
16234 mips_abicalls
= TRUE
;
16237 if (mips_pic
== SVR4_PIC
)
16239 if (g_switch_seen
&& g_switch_value
!= 0)
16240 as_warn (_("-G may not be used with SVR4 PIC code"));
16241 g_switch_value
= 0;
16242 bfd_set_gp_size (stdoutput
, 0);
16246 as_warn (_("unrecognized option \"%s\""), opt
);
16248 (void) restore_line_pointer (c
);
16249 demand_empty_rest_of_line ();
16252 /* This structure is used to hold a stack of .set values. */
16254 struct mips_option_stack
16256 struct mips_option_stack
*next
;
16257 struct mips_set_options options
;
16260 static struct mips_option_stack
*mips_opts_stack
;
16262 /* Return status for .set/.module option handling. */
16264 enum code_option_type
16266 /* Unrecognized option. */
16267 OPTION_TYPE_BAD
= -1,
16269 /* Ordinary option. */
16270 OPTION_TYPE_NORMAL
,
16272 /* ISA changing option. */
16276 /* Handle common .set/.module options. Return status indicating option
16279 static enum code_option_type
16280 parse_code_option (char * name
)
16282 bfd_boolean isa_set
= FALSE
;
16283 const struct mips_ase
*ase
;
16285 if (strncmp (name
, "at=", 3) == 0)
16287 char *s
= name
+ 3;
16289 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16290 as_bad (_("unrecognized register name `%s'"), s
);
16292 else if (strcmp (name
, "at") == 0)
16293 mips_opts
.at
= ATREG
;
16294 else if (strcmp (name
, "noat") == 0)
16295 mips_opts
.at
= ZERO
;
16296 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16297 mips_opts
.nomove
= 0;
16298 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16299 mips_opts
.nomove
= 1;
16300 else if (strcmp (name
, "bopt") == 0)
16301 mips_opts
.nobopt
= 0;
16302 else if (strcmp (name
, "nobopt") == 0)
16303 mips_opts
.nobopt
= 1;
16304 else if (strcmp (name
, "gp=32") == 0)
16306 else if (strcmp (name
, "gp=64") == 0)
16308 else if (strcmp (name
, "fp=32") == 0)
16310 else if (strcmp (name
, "fp=xx") == 0)
16312 else if (strcmp (name
, "fp=64") == 0)
16314 else if (strcmp (name
, "softfloat") == 0)
16315 mips_opts
.soft_float
= 1;
16316 else if (strcmp (name
, "hardfloat") == 0)
16317 mips_opts
.soft_float
= 0;
16318 else if (strcmp (name
, "singlefloat") == 0)
16319 mips_opts
.single_float
= 1;
16320 else if (strcmp (name
, "doublefloat") == 0)
16321 mips_opts
.single_float
= 0;
16322 else if (strcmp (name
, "nooddspreg") == 0)
16323 mips_opts
.oddspreg
= 0;
16324 else if (strcmp (name
, "oddspreg") == 0)
16325 mips_opts
.oddspreg
= 1;
16326 else if (strcmp (name
, "mips16") == 0
16327 || strcmp (name
, "MIPS-16") == 0)
16328 mips_opts
.mips16
= 1;
16329 else if (strcmp (name
, "nomips16") == 0
16330 || strcmp (name
, "noMIPS-16") == 0)
16331 mips_opts
.mips16
= 0;
16332 else if (strcmp (name
, "micromips") == 0)
16333 mips_opts
.micromips
= 1;
16334 else if (strcmp (name
, "nomicromips") == 0)
16335 mips_opts
.micromips
= 0;
16336 else if (name
[0] == 'n'
16338 && (ase
= mips_lookup_ase (name
+ 2)))
16339 mips_set_ase (ase
, &mips_opts
, FALSE
);
16340 else if ((ase
= mips_lookup_ase (name
)))
16341 mips_set_ase (ase
, &mips_opts
, TRUE
);
16342 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16344 /* Permit the user to change the ISA and architecture on the fly.
16345 Needless to say, misuse can cause serious problems. */
16346 if (strncmp (name
, "arch=", 5) == 0)
16348 const struct mips_cpu_info
*p
;
16350 p
= mips_parse_cpu ("internal use", name
+ 5);
16352 as_bad (_("unknown architecture %s"), name
+ 5);
16355 mips_opts
.arch
= p
->cpu
;
16356 mips_opts
.isa
= p
->isa
;
16360 else if (strncmp (name
, "mips", 4) == 0)
16362 const struct mips_cpu_info
*p
;
16364 p
= mips_parse_cpu ("internal use", name
);
16366 as_bad (_("unknown ISA level %s"), name
+ 4);
16369 mips_opts
.arch
= p
->cpu
;
16370 mips_opts
.isa
= p
->isa
;
16375 as_bad (_("unknown ISA or architecture %s"), name
);
16377 else if (strcmp (name
, "autoextend") == 0)
16378 mips_opts
.noautoextend
= 0;
16379 else if (strcmp (name
, "noautoextend") == 0)
16380 mips_opts
.noautoextend
= 1;
16381 else if (strcmp (name
, "insn32") == 0)
16382 mips_opts
.insn32
= TRUE
;
16383 else if (strcmp (name
, "noinsn32") == 0)
16384 mips_opts
.insn32
= FALSE
;
16385 else if (strcmp (name
, "sym32") == 0)
16386 mips_opts
.sym32
= TRUE
;
16387 else if (strcmp (name
, "nosym32") == 0)
16388 mips_opts
.sym32
= FALSE
;
16390 return OPTION_TYPE_BAD
;
16392 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16395 /* Handle the .set pseudo-op. */
16398 s_mipsset (int x ATTRIBUTE_UNUSED
)
16400 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16401 char *name
= input_line_pointer
, ch
;
16403 file_mips_check_options ();
16405 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16406 ++input_line_pointer
;
16407 ch
= *input_line_pointer
;
16408 *input_line_pointer
= '\0';
16410 if (strchr (name
, ','))
16412 /* Generic ".set" directive; use the generic handler. */
16413 *input_line_pointer
= ch
;
16414 input_line_pointer
= name
;
16419 if (strcmp (name
, "reorder") == 0)
16421 if (mips_opts
.noreorder
)
16424 else if (strcmp (name
, "noreorder") == 0)
16426 if (!mips_opts
.noreorder
)
16427 start_noreorder ();
16429 else if (strcmp (name
, "macro") == 0)
16430 mips_opts
.warn_about_macros
= 0;
16431 else if (strcmp (name
, "nomacro") == 0)
16433 if (mips_opts
.noreorder
== 0)
16434 as_bad (_("`noreorder' must be set before `nomacro'"));
16435 mips_opts
.warn_about_macros
= 1;
16437 else if (strcmp (name
, "gp=default") == 0)
16438 mips_opts
.gp
= file_mips_opts
.gp
;
16439 else if (strcmp (name
, "fp=default") == 0)
16440 mips_opts
.fp
= file_mips_opts
.fp
;
16441 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16443 mips_opts
.isa
= file_mips_opts
.isa
;
16444 mips_opts
.arch
= file_mips_opts
.arch
;
16445 mips_opts
.gp
= file_mips_opts
.gp
;
16446 mips_opts
.fp
= file_mips_opts
.fp
;
16448 else if (strcmp (name
, "push") == 0)
16450 struct mips_option_stack
*s
;
16452 s
= XNEW (struct mips_option_stack
);
16453 s
->next
= mips_opts_stack
;
16454 s
->options
= mips_opts
;
16455 mips_opts_stack
= s
;
16457 else if (strcmp (name
, "pop") == 0)
16459 struct mips_option_stack
*s
;
16461 s
= mips_opts_stack
;
16463 as_bad (_(".set pop with no .set push"));
16466 /* If we're changing the reorder mode we need to handle
16467 delay slots correctly. */
16468 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16469 start_noreorder ();
16470 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16473 mips_opts
= s
->options
;
16474 mips_opts_stack
= s
->next
;
16480 type
= parse_code_option (name
);
16481 if (type
== OPTION_TYPE_BAD
)
16482 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16485 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16486 registers based on what is supported by the arch/cpu. */
16487 if (type
== OPTION_TYPE_ISA
)
16489 switch (mips_opts
.isa
)
16494 /* MIPS I cannot support FPXX. */
16496 /* fall-through. */
16503 if (mips_opts
.fp
!= 0)
16519 if (mips_opts
.fp
!= 0)
16521 if (mips_opts
.arch
== CPU_R5900
)
16528 as_bad (_("unknown ISA level %s"), name
+ 4);
16533 mips_check_options (&mips_opts
, FALSE
);
16535 mips_check_isa_supports_ases ();
16536 *input_line_pointer
= ch
;
16537 demand_empty_rest_of_line ();
16540 /* Handle the .module pseudo-op. */
16543 s_module (int ignore ATTRIBUTE_UNUSED
)
16545 char *name
= input_line_pointer
, ch
;
16547 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16548 ++input_line_pointer
;
16549 ch
= *input_line_pointer
;
16550 *input_line_pointer
= '\0';
16552 if (!file_mips_opts_checked
)
16554 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16555 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16557 /* Update module level settings from mips_opts. */
16558 file_mips_opts
= mips_opts
;
16561 as_bad (_(".module is not permitted after generating code"));
16563 *input_line_pointer
= ch
;
16564 demand_empty_rest_of_line ();
16567 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16568 .option pic2. It means to generate SVR4 PIC calls. */
16571 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16573 mips_pic
= SVR4_PIC
;
16574 mips_abicalls
= TRUE
;
16576 if (g_switch_seen
&& g_switch_value
!= 0)
16577 as_warn (_("-G may not be used with SVR4 PIC code"));
16578 g_switch_value
= 0;
16580 bfd_set_gp_size (stdoutput
, 0);
16581 demand_empty_rest_of_line ();
16584 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16585 PIC code. It sets the $gp register for the function based on the
16586 function address, which is in the register named in the argument.
16587 This uses a relocation against _gp_disp, which is handled specially
16588 by the linker. The result is:
16589 lui $gp,%hi(_gp_disp)
16590 addiu $gp,$gp,%lo(_gp_disp)
16591 addu $gp,$gp,.cpload argument
16592 The .cpload argument is normally $25 == $t9.
16594 The -mno-shared option changes this to:
16595 lui $gp,%hi(__gnu_local_gp)
16596 addiu $gp,$gp,%lo(__gnu_local_gp)
16597 and the argument is ignored. This saves an instruction, but the
16598 resulting code is not position independent; it uses an absolute
16599 address for __gnu_local_gp. Thus code assembled with -mno-shared
16600 can go into an ordinary executable, but not into a shared library. */
16603 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16609 file_mips_check_options ();
16611 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16612 .cpload is ignored. */
16613 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16619 if (mips_opts
.mips16
)
16621 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16622 ignore_rest_of_line ();
16626 /* .cpload should be in a .set noreorder section. */
16627 if (mips_opts
.noreorder
== 0)
16628 as_warn (_(".cpload not in noreorder section"));
16630 reg
= tc_get_register (0);
16632 /* If we need to produce a 64-bit address, we are better off using
16633 the default instruction sequence. */
16634 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16636 ex
.X_op
= O_symbol
;
16637 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16639 ex
.X_op_symbol
= NULL
;
16640 ex
.X_add_number
= 0;
16642 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16643 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16645 mips_mark_labels ();
16646 mips_assembling_insn
= TRUE
;
16649 macro_build_lui (&ex
, mips_gp_register
);
16650 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16651 mips_gp_register
, BFD_RELOC_LO16
);
16653 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16654 mips_gp_register
, reg
);
16657 mips_assembling_insn
= FALSE
;
16658 demand_empty_rest_of_line ();
16661 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16662 .cpsetup $reg1, offset|$reg2, label
16664 If offset is given, this results in:
16665 sd $gp, offset($sp)
16666 lui $gp, %hi(%neg(%gp_rel(label)))
16667 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16668 daddu $gp, $gp, $reg1
16670 If $reg2 is given, this results in:
16672 lui $gp, %hi(%neg(%gp_rel(label)))
16673 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16674 daddu $gp, $gp, $reg1
16675 $reg1 is normally $25 == $t9.
16677 The -mno-shared option replaces the last three instructions with
16679 addiu $gp,$gp,%lo(_gp) */
16682 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16684 expressionS ex_off
;
16685 expressionS ex_sym
;
16688 file_mips_check_options ();
16690 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16691 We also need NewABI support. */
16692 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16698 if (mips_opts
.mips16
)
16700 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16701 ignore_rest_of_line ();
16705 reg1
= tc_get_register (0);
16706 SKIP_WHITESPACE ();
16707 if (*input_line_pointer
!= ',')
16709 as_bad (_("missing argument separator ',' for .cpsetup"));
16713 ++input_line_pointer
;
16714 SKIP_WHITESPACE ();
16715 if (*input_line_pointer
== '$')
16717 mips_cpreturn_register
= tc_get_register (0);
16718 mips_cpreturn_offset
= -1;
16722 mips_cpreturn_offset
= get_absolute_expression ();
16723 mips_cpreturn_register
= -1;
16725 SKIP_WHITESPACE ();
16726 if (*input_line_pointer
!= ',')
16728 as_bad (_("missing argument separator ',' for .cpsetup"));
16732 ++input_line_pointer
;
16733 SKIP_WHITESPACE ();
16734 expression (&ex_sym
);
16736 mips_mark_labels ();
16737 mips_assembling_insn
= TRUE
;
16740 if (mips_cpreturn_register
== -1)
16742 ex_off
.X_op
= O_constant
;
16743 ex_off
.X_add_symbol
= NULL
;
16744 ex_off
.X_op_symbol
= NULL
;
16745 ex_off
.X_add_number
= mips_cpreturn_offset
;
16747 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16748 BFD_RELOC_LO16
, SP
);
16751 move_register (mips_cpreturn_register
, mips_gp_register
);
16753 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16755 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16756 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16759 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16760 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16761 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16763 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16764 mips_gp_register
, reg1
);
16770 ex
.X_op
= O_symbol
;
16771 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16772 ex
.X_op_symbol
= NULL
;
16773 ex
.X_add_number
= 0;
16775 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16776 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16778 macro_build_lui (&ex
, mips_gp_register
);
16779 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16780 mips_gp_register
, BFD_RELOC_LO16
);
16785 mips_assembling_insn
= FALSE
;
16786 demand_empty_rest_of_line ();
16790 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16792 file_mips_check_options ();
16794 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16795 .cplocal is ignored. */
16796 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16802 if (mips_opts
.mips16
)
16804 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16805 ignore_rest_of_line ();
16809 mips_gp_register
= tc_get_register (0);
16810 demand_empty_rest_of_line ();
16813 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16814 offset from $sp. The offset is remembered, and after making a PIC
16815 call $gp is restored from that location. */
16818 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16822 file_mips_check_options ();
16824 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16825 .cprestore is ignored. */
16826 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16832 if (mips_opts
.mips16
)
16834 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16835 ignore_rest_of_line ();
16839 mips_cprestore_offset
= get_absolute_expression ();
16840 mips_cprestore_valid
= 1;
16842 ex
.X_op
= O_constant
;
16843 ex
.X_add_symbol
= NULL
;
16844 ex
.X_op_symbol
= NULL
;
16845 ex
.X_add_number
= mips_cprestore_offset
;
16847 mips_mark_labels ();
16848 mips_assembling_insn
= TRUE
;
16851 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16852 SP
, HAVE_64BIT_ADDRESSES
);
16855 mips_assembling_insn
= FALSE
;
16856 demand_empty_rest_of_line ();
16859 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16860 was given in the preceding .cpsetup, it results in:
16861 ld $gp, offset($sp)
16863 If a register $reg2 was given there, it results in:
16864 or $gp, $reg2, $0 */
16867 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16871 file_mips_check_options ();
16873 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16874 We also need NewABI support. */
16875 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16881 if (mips_opts
.mips16
)
16883 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16884 ignore_rest_of_line ();
16888 mips_mark_labels ();
16889 mips_assembling_insn
= TRUE
;
16892 if (mips_cpreturn_register
== -1)
16894 ex
.X_op
= O_constant
;
16895 ex
.X_add_symbol
= NULL
;
16896 ex
.X_op_symbol
= NULL
;
16897 ex
.X_add_number
= mips_cpreturn_offset
;
16899 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16902 move_register (mips_gp_register
, mips_cpreturn_register
);
16906 mips_assembling_insn
= FALSE
;
16907 demand_empty_rest_of_line ();
16910 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16911 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16912 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16913 debug information or MIPS16 TLS. */
16916 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16917 bfd_reloc_code_real_type rtype
)
16924 if (ex
.X_op
!= O_symbol
)
16926 as_bad (_("unsupported use of %s"), dirstr
);
16927 ignore_rest_of_line ();
16930 p
= frag_more (bytes
);
16931 md_number_to_chars (p
, 0, bytes
);
16932 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16933 demand_empty_rest_of_line ();
16934 mips_clear_insn_labels ();
16937 /* Handle .dtprelword. */
16940 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16942 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16945 /* Handle .dtpreldword. */
16948 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16950 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16953 /* Handle .tprelword. */
16956 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16958 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16961 /* Handle .tpreldword. */
16964 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16966 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16969 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16970 code. It sets the offset to use in gp_rel relocations. */
16973 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16975 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16976 We also need NewABI support. */
16977 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16983 mips_gprel_offset
= get_absolute_expression ();
16985 demand_empty_rest_of_line ();
16988 /* Handle the .gpword pseudo-op. This is used when generating PIC
16989 code. It generates a 32 bit GP relative reloc. */
16992 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16994 segment_info_type
*si
;
16995 struct insn_label_list
*l
;
16999 /* When not generating PIC code, this is treated as .word. */
17000 if (mips_pic
!= SVR4_PIC
)
17006 si
= seg_info (now_seg
);
17007 l
= si
->label_list
;
17008 mips_emit_delays ();
17010 mips_align (2, 0, l
);
17013 mips_clear_insn_labels ();
17015 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17017 as_bad (_("unsupported use of .gpword"));
17018 ignore_rest_of_line ();
17022 md_number_to_chars (p
, 0, 4);
17023 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17024 BFD_RELOC_GPREL32
);
17026 demand_empty_rest_of_line ();
17030 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17032 segment_info_type
*si
;
17033 struct insn_label_list
*l
;
17037 /* When not generating PIC code, this is treated as .dword. */
17038 if (mips_pic
!= SVR4_PIC
)
17044 si
= seg_info (now_seg
);
17045 l
= si
->label_list
;
17046 mips_emit_delays ();
17048 mips_align (3, 0, l
);
17051 mips_clear_insn_labels ();
17053 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17055 as_bad (_("unsupported use of .gpdword"));
17056 ignore_rest_of_line ();
17060 md_number_to_chars (p
, 0, 8);
17061 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17062 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17064 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17065 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17066 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17068 demand_empty_rest_of_line ();
17071 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17072 tables. It generates a R_MIPS_EH reloc. */
17075 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17080 mips_emit_delays ();
17083 mips_clear_insn_labels ();
17085 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17087 as_bad (_("unsupported use of .ehword"));
17088 ignore_rest_of_line ();
17092 md_number_to_chars (p
, 0, 4);
17093 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17094 BFD_RELOC_32_PCREL
);
17096 demand_empty_rest_of_line ();
17099 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17100 tables in SVR4 PIC code. */
17103 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17107 file_mips_check_options ();
17109 /* This is ignored when not generating SVR4 PIC code. */
17110 if (mips_pic
!= SVR4_PIC
)
17116 mips_mark_labels ();
17117 mips_assembling_insn
= TRUE
;
17119 /* Add $gp to the register named as an argument. */
17121 reg
= tc_get_register (0);
17122 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17125 mips_assembling_insn
= FALSE
;
17126 demand_empty_rest_of_line ();
17129 /* Handle the .insn pseudo-op. This marks instruction labels in
17130 mips16/micromips mode. This permits the linker to handle them specially,
17131 such as generating jalx instructions when needed. We also make
17132 them odd for the duration of the assembly, in order to generate the
17133 right sort of code. We will make them even in the adjust_symtab
17134 routine, while leaving them marked. This is convenient for the
17135 debugger and the disassembler. The linker knows to make them odd
17139 s_insn (int ignore ATTRIBUTE_UNUSED
)
17141 file_mips_check_options ();
17142 file_ase_mips16
|= mips_opts
.mips16
;
17143 file_ase_micromips
|= mips_opts
.micromips
;
17145 mips_mark_labels ();
17147 demand_empty_rest_of_line ();
17150 /* Handle the .nan pseudo-op. */
17153 s_nan (int ignore ATTRIBUTE_UNUSED
)
17155 static const char str_legacy
[] = "legacy";
17156 static const char str_2008
[] = "2008";
17159 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17161 if (i
== sizeof (str_2008
) - 1
17162 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17164 else if (i
== sizeof (str_legacy
) - 1
17165 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17167 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17170 as_bad (_("`%s' does not support legacy NaN"),
17171 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17174 as_bad (_("bad .nan directive"));
17176 input_line_pointer
+= i
;
17177 demand_empty_rest_of_line ();
17180 /* Handle a .stab[snd] directive. Ideally these directives would be
17181 implemented in a transparent way, so that removing them would not
17182 have any effect on the generated instructions. However, s_stab
17183 internally changes the section, so in practice we need to decide
17184 now whether the preceding label marks compressed code. We do not
17185 support changing the compression mode of a label after a .stab*
17186 directive, such as in:
17192 so the current mode wins. */
17195 s_mips_stab (int type
)
17197 file_mips_check_options ();
17198 mips_mark_labels ();
17202 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17205 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17212 c
= get_symbol_name (&name
);
17213 symbolP
= symbol_find_or_make (name
);
17214 S_SET_WEAK (symbolP
);
17215 *input_line_pointer
= c
;
17217 SKIP_WHITESPACE_AFTER_NAME ();
17219 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17221 if (S_IS_DEFINED (symbolP
))
17223 as_bad (_("ignoring attempt to redefine symbol %s"),
17224 S_GET_NAME (symbolP
));
17225 ignore_rest_of_line ();
17229 if (*input_line_pointer
== ',')
17231 ++input_line_pointer
;
17232 SKIP_WHITESPACE ();
17236 if (exp
.X_op
!= O_symbol
)
17238 as_bad (_("bad .weakext directive"));
17239 ignore_rest_of_line ();
17242 symbol_set_value_expression (symbolP
, &exp
);
17245 demand_empty_rest_of_line ();
17248 /* Parse a register string into a number. Called from the ECOFF code
17249 to parse .frame. The argument is non-zero if this is the frame
17250 register, so that we can record it in mips_frame_reg. */
17253 tc_get_register (int frame
)
17257 SKIP_WHITESPACE ();
17258 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17262 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17263 mips_frame_reg_valid
= 1;
17264 mips_cprestore_valid
= 0;
17270 md_section_align (asection
*seg
, valueT addr
)
17272 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17274 /* We don't need to align ELF sections to the full alignment.
17275 However, Irix 5 may prefer that we align them at least to a 16
17276 byte boundary. We don't bother to align the sections if we
17277 are targeted for an embedded system. */
17278 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17283 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17286 /* Utility routine, called from above as well. If called while the
17287 input file is still being read, it's only an approximation. (For
17288 example, a symbol may later become defined which appeared to be
17289 undefined earlier.) */
17292 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17297 if (g_switch_value
> 0)
17299 const char *symname
;
17302 /* Find out whether this symbol can be referenced off the $gp
17303 register. It can be if it is smaller than the -G size or if
17304 it is in the .sdata or .sbss section. Certain symbols can
17305 not be referenced off the $gp, although it appears as though
17307 symname
= S_GET_NAME (sym
);
17308 if (symname
!= (const char *) NULL
17309 && (strcmp (symname
, "eprol") == 0
17310 || strcmp (symname
, "etext") == 0
17311 || strcmp (symname
, "_gp") == 0
17312 || strcmp (symname
, "edata") == 0
17313 || strcmp (symname
, "_fbss") == 0
17314 || strcmp (symname
, "_fdata") == 0
17315 || strcmp (symname
, "_ftext") == 0
17316 || strcmp (symname
, "end") == 0
17317 || strcmp (symname
, "_gp_disp") == 0))
17319 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17321 #ifndef NO_ECOFF_DEBUGGING
17322 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17323 && (symbol_get_obj (sym
)->ecoff_extern_size
17324 <= g_switch_value
))
17326 /* We must defer this decision until after the whole
17327 file has been read, since there might be a .extern
17328 after the first use of this symbol. */
17329 || (before_relaxing
17330 #ifndef NO_ECOFF_DEBUGGING
17331 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17333 && S_GET_VALUE (sym
) == 0)
17334 || (S_GET_VALUE (sym
) != 0
17335 && S_GET_VALUE (sym
) <= g_switch_value
)))
17339 const char *segname
;
17341 segname
= segment_name (S_GET_SEGMENT (sym
));
17342 gas_assert (strcmp (segname
, ".lit8") != 0
17343 && strcmp (segname
, ".lit4") != 0);
17344 change
= (strcmp (segname
, ".sdata") != 0
17345 && strcmp (segname
, ".sbss") != 0
17346 && strncmp (segname
, ".sdata.", 7) != 0
17347 && strncmp (segname
, ".sbss.", 6) != 0
17348 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17349 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17354 /* We are not optimizing for the $gp register. */
17359 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17362 pic_need_relax (symbolS
*sym
)
17366 /* Handle the case of a symbol equated to another symbol. */
17367 while (symbol_equated_reloc_p (sym
))
17371 /* It's possible to get a loop here in a badly written program. */
17372 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17378 if (symbol_section_p (sym
))
17381 symsec
= S_GET_SEGMENT (sym
);
17383 /* This must duplicate the test in adjust_reloc_syms. */
17384 return (!bfd_is_und_section (symsec
)
17385 && !bfd_is_abs_section (symsec
)
17386 && !bfd_is_com_section (symsec
)
17387 /* A global or weak symbol is treated as external. */
17388 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17391 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17392 convert a section-relative value VAL to the equivalent PC-relative
17396 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17397 offsetT val
, long stretch
)
17402 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17404 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17406 /* If the relax_marker of the symbol fragment differs from the
17407 relax_marker of this fragment, we have not yet adjusted the
17408 symbol fragment fr_address. We want to add in STRETCH in
17409 order to get a better estimate of the address. This
17410 particularly matters because of the shift bits. */
17411 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17415 /* Adjust stretch for any alignment frag. Note that if have
17416 been expanding the earlier code, the symbol may be
17417 defined in what appears to be an earlier frag. FIXME:
17418 This doesn't handle the fr_subtype field, which specifies
17419 a maximum number of bytes to skip when doing an
17421 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17423 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17426 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17428 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17437 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17439 /* The base address rules are complicated. The base address of
17440 a branch is the following instruction. The base address of a
17441 PC relative load or add is the instruction itself, but if it
17442 is in a delay slot (in which case it can not be extended) use
17443 the address of the instruction whose delay slot it is in. */
17444 if (pcrel_op
->include_isa_bit
)
17448 /* If we are currently assuming that this frag should be
17449 extended, then the current address is two bytes higher. */
17450 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17453 /* Ignore the low bit in the target, since it will be set
17454 for a text label. */
17457 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17459 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17462 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17467 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17468 extended opcode. SEC is the section the frag is in. */
17471 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17473 const struct mips_int_operand
*operand
;
17478 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17480 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17483 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17484 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17485 operand
= mips16_immed_operand (type
, FALSE
);
17486 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17487 || (operand
->root
.type
== OP_PCREL
17489 : !bfd_is_abs_section (symsec
)))
17492 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17494 if (operand
->root
.type
== OP_PCREL
)
17496 const struct mips_pcrel_operand
*pcrel_op
;
17499 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17502 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17503 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17505 /* If any of the shifted bits are set, we must use an extended
17506 opcode. If the address depends on the size of this
17507 instruction, this can lead to a loop, so we arrange to always
17508 use an extended opcode. */
17509 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17511 fragp
->fr_subtype
=
17512 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17516 /* If we are about to mark a frag as extended because the value
17517 is precisely the next value above maxtiny, then there is a
17518 chance of an infinite loop as in the following code:
17523 In this case when the la is extended, foo is 0x3fc bytes
17524 away, so the la can be shrunk, but then foo is 0x400 away, so
17525 the la must be extended. To avoid this loop, we mark the
17526 frag as extended if it was small, and is about to become
17527 extended with the next value above maxtiny. */
17528 maxtiny
= mips_int_operand_max (operand
);
17529 if (val
== maxtiny
+ (1 << operand
->shift
)
17530 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17532 fragp
->fr_subtype
=
17533 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17538 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17541 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17542 macro expansion. SEC is the section the frag is in. We only
17543 support PC-relative instructions (LA, DLA, LW, LD) here, in
17544 non-PIC code using 32-bit addressing. */
17547 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17549 const struct mips_pcrel_operand
*pcrel_op
;
17550 const struct mips_int_operand
*operand
;
17555 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17557 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17559 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17562 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17568 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17569 if (bfd_is_abs_section (symsec
))
17571 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17573 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17576 operand
= mips16_immed_operand (type
, TRUE
);
17577 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17578 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17579 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17581 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17588 /* Compute the length of a branch sequence, and adjust the
17589 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17590 worst-case length is computed, with UPDATE being used to indicate
17591 whether an unconditional (-1), branch-likely (+1) or regular (0)
17592 branch is to be computed. */
17594 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17596 bfd_boolean toofar
;
17600 && S_IS_DEFINED (fragp
->fr_symbol
)
17601 && !S_IS_WEAK (fragp
->fr_symbol
)
17602 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17607 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17609 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17613 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17616 /* If the symbol is not defined or it's in a different segment,
17617 we emit the long sequence. */
17620 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17622 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17623 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17624 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17625 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17626 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17632 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17635 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17637 /* Additional space for PIC loading of target address. */
17639 if (mips_opts
.isa
== ISA_MIPS1
)
17640 /* Additional space for $at-stabilizing nop. */
17644 /* If branch is conditional. */
17645 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17652 /* Get a FRAG's branch instruction delay slot size, either from the
17653 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17654 or SHORT_INSN_SIZE otherwise. */
17657 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17659 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17662 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17664 return short_insn_size
;
17667 /* Compute the length of a branch sequence, and adjust the
17668 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17669 worst-case length is computed, with UPDATE being used to indicate
17670 whether an unconditional (-1), or regular (0) branch is to be
17674 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17676 bfd_boolean insn32
= TRUE
;
17677 bfd_boolean nods
= TRUE
;
17678 bfd_boolean pic
= TRUE
;
17679 bfd_boolean al
= TRUE
;
17680 int short_insn_size
;
17681 bfd_boolean toofar
;
17686 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17687 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17688 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17689 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17691 short_insn_size
= insn32
? 4 : 2;
17694 && S_IS_DEFINED (fragp
->fr_symbol
)
17695 && !S_IS_WEAK (fragp
->fr_symbol
)
17696 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17701 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17702 /* Ignore the low bit in the target, since it will be set
17703 for a text label. */
17704 if ((val
& 1) != 0)
17707 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17711 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17714 /* If the symbol is not defined or it's in a different segment,
17715 we emit the long sequence. */
17718 if (fragp
&& update
17719 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17720 fragp
->fr_subtype
= (toofar
17721 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17722 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17727 bfd_boolean compact_known
= fragp
!= NULL
;
17728 bfd_boolean compact
= FALSE
;
17729 bfd_boolean uncond
;
17733 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17734 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17737 uncond
= update
< 0;
17739 /* If label is out of range, we turn branch <br>:
17741 <br> label # 4 bytes
17748 # compact && (!PIC || insn32)
17751 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17752 length
+= short_insn_size
;
17754 /* If assembling PIC code, we further turn:
17760 lw/ld at, %got(label)(gp) # 4 bytes
17761 d/addiu at, %lo(label) # 4 bytes
17762 jr/c at # 2/4 bytes
17765 length
+= 4 + short_insn_size
;
17767 /* Add an extra nop if the jump has no compact form and we need
17768 to fill the delay slot. */
17769 if ((!pic
|| al
) && nods
)
17771 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17772 : short_insn_size
);
17774 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17776 <brneg> 0f # 4 bytes
17777 nop # 2/4 bytes if !compact
17780 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17784 /* Add an extra nop to fill the delay slot. */
17785 gas_assert (fragp
);
17786 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17792 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17793 bit accordingly. */
17796 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17798 bfd_boolean toofar
;
17801 && S_IS_DEFINED (fragp
->fr_symbol
)
17802 && !S_IS_WEAK (fragp
->fr_symbol
)
17803 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17809 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17810 /* Ignore the low bit in the target, since it will be set
17811 for a text label. */
17812 if ((val
& 1) != 0)
17815 /* Assume this is a 2-byte branch. */
17816 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17818 /* We try to avoid the infinite loop by not adding 2 more bytes for
17823 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17825 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17826 else if (type
== 'E')
17827 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17832 /* If the symbol is not defined or it's in a different segment,
17833 we emit a normal 32-bit branch. */
17836 if (fragp
&& update
17837 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17839 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17840 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17848 /* Estimate the size of a frag before relaxing. Unless this is the
17849 mips16, we are not really relaxing here, and the final size is
17850 encoded in the subtype information. For the mips16, we have to
17851 decide whether we are using an extended opcode or not. */
17854 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17858 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17861 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17863 return fragp
->fr_var
;
17866 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17868 /* We don't want to modify the EXTENDED bit here; it might get us
17869 into infinite loops. We change it only in mips_relax_frag(). */
17870 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17871 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
17873 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
17876 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17880 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17881 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17882 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17883 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17884 fragp
->fr_var
= length
;
17889 if (mips_pic
== VXWORKS_PIC
)
17890 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17892 else if (RELAX_PIC (fragp
->fr_subtype
))
17893 change
= pic_need_relax (fragp
->fr_symbol
);
17895 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17899 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17900 return -RELAX_FIRST (fragp
->fr_subtype
);
17903 return -RELAX_SECOND (fragp
->fr_subtype
);
17906 /* This is called to see whether a reloc against a defined symbol
17907 should be converted into a reloc against a section. */
17910 mips_fix_adjustable (fixS
*fixp
)
17912 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17913 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17916 if (fixp
->fx_addsy
== NULL
)
17919 /* Allow relocs used for EH tables. */
17920 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17923 /* If symbol SYM is in a mergeable section, relocations of the form
17924 SYM + 0 can usually be made section-relative. The mergeable data
17925 is then identified by the section offset rather than by the symbol.
17927 However, if we're generating REL LO16 relocations, the offset is split
17928 between the LO16 and partnering high part relocation. The linker will
17929 need to recalculate the complete offset in order to correctly identify
17932 The linker has traditionally not looked for the partnering high part
17933 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17934 placed anywhere. Rather than break backwards compatibility by changing
17935 this, it seems better not to force the issue, and instead keep the
17936 original symbol. This will work with either linker behavior. */
17937 if ((lo16_reloc_p (fixp
->fx_r_type
)
17938 || reloc_needs_lo_p (fixp
->fx_r_type
))
17939 && HAVE_IN_PLACE_ADDENDS
17940 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17943 /* There is no place to store an in-place offset for JALR relocations. */
17944 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17947 /* Likewise an in-range offset of limited PC-relative relocations may
17948 overflow the in-place relocatable field if recalculated against the
17949 start address of the symbol's containing section.
17951 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17952 section relative to allow linker relaxations to be performed later on. */
17953 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17954 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17957 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17958 to a floating-point stub. The same is true for non-R_MIPS16_26
17959 relocations against MIPS16 functions; in this case, the stub becomes
17960 the function's canonical address.
17962 Floating-point stubs are stored in unique .mips16.call.* or
17963 .mips16.fn.* sections. If a stub T for function F is in section S,
17964 the first relocation in section S must be against F; this is how the
17965 linker determines the target function. All relocations that might
17966 resolve to T must also be against F. We therefore have the following
17967 restrictions, which are given in an intentionally-redundant way:
17969 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17972 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17973 if that stub might be used.
17975 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17978 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17979 that stub might be used.
17981 There is a further restriction:
17983 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17984 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17985 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17986 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17987 against MIPS16 or microMIPS symbols because we need to keep the
17988 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17989 detection and JAL or BAL to JALX instruction conversion in the
17992 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17993 against a MIPS16 symbol. We deal with (5) by additionally leaving
17994 alone any jump and branch relocations against a microMIPS symbol.
17996 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17997 relocation against some symbol R, no relocation against R may be
17998 reduced. (Note that this deals with (2) as well as (1) because
17999 relocations against global symbols will never be reduced on ELF
18000 targets.) This approach is a little simpler than trying to detect
18001 stub sections, and gives the "all or nothing" per-symbol consistency
18002 that we have for MIPS16 symbols. */
18003 if (fixp
->fx_subsy
== NULL
18004 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18005 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18006 && (jmp_reloc_p (fixp
->fx_r_type
)
18007 || b_reloc_p (fixp
->fx_r_type
)))
18008 || *symbol_get_tc (fixp
->fx_addsy
)))
18014 /* Translate internal representation of relocation info to BFD target
18018 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18020 static arelent
*retval
[4];
18022 bfd_reloc_code_real_type code
;
18024 memset (retval
, 0, sizeof(retval
));
18025 reloc
= retval
[0] = XCNEW (arelent
);
18026 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18027 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18028 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18030 if (fixp
->fx_pcrel
)
18032 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18033 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18034 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18035 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18036 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18037 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18038 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18039 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18040 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18041 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18042 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18043 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18045 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18046 Relocations want only the symbol offset. */
18047 switch (fixp
->fx_r_type
)
18049 case BFD_RELOC_MIPS_18_PCREL_S3
:
18050 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18053 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18057 else if (HAVE_IN_PLACE_ADDENDS
18058 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18059 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18060 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18062 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18063 addend accordingly. */
18064 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18067 reloc
->addend
= fixp
->fx_addnumber
;
18069 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18070 entry to be used in the relocation's section offset. */
18071 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18073 reloc
->address
= reloc
->addend
;
18077 code
= fixp
->fx_r_type
;
18079 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18080 if (reloc
->howto
== NULL
)
18082 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18083 _("cannot represent %s relocation in this object file"
18085 bfd_get_reloc_code_name (code
));
18092 /* Relax a machine dependent frag. This returns the amount by which
18093 the current size of the frag should change. */
18096 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18098 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18100 offsetT old_var
= fragp
->fr_var
;
18102 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18104 return fragp
->fr_var
- old_var
;
18107 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18109 offsetT old_var
= fragp
->fr_var
;
18110 offsetT new_var
= 4;
18112 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18113 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18114 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18115 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18116 fragp
->fr_var
= new_var
;
18118 return new_var
- old_var
;
18121 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18124 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18126 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18128 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18129 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18131 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18133 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18139 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18141 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18143 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18144 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18145 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18147 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18149 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18157 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18159 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18161 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18162 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18163 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18167 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18168 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18175 /* Convert a machine dependent frag. */
18178 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18180 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18183 unsigned long insn
;
18186 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18187 insn
= read_insn (buf
);
18189 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18191 /* We generate a fixup instead of applying it right now
18192 because, if there are linker relaxations, we're going to
18193 need the relocations. */
18194 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18195 fragp
->fr_symbol
, fragp
->fr_offset
,
18196 TRUE
, BFD_RELOC_16_PCREL_S2
);
18197 fixp
->fx_file
= fragp
->fr_file
;
18198 fixp
->fx_line
= fragp
->fr_line
;
18200 buf
= write_insn (buf
, insn
);
18206 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18207 _("relaxed out-of-range branch into a jump"));
18209 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18212 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18214 /* Reverse the branch. */
18215 switch ((insn
>> 28) & 0xf)
18218 if ((insn
& 0xff000000) == 0x47000000
18219 || (insn
& 0xff600000) == 0x45600000)
18221 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18222 reversed by tweaking bit 23. */
18223 insn
^= 0x00800000;
18227 /* bc[0-3][tf]l? instructions can have the condition
18228 reversed by tweaking a single TF bit, and their
18229 opcodes all have 0x4???????. */
18230 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18231 insn
^= 0x00010000;
18236 /* bltz 0x04000000 bgez 0x04010000
18237 bltzal 0x04100000 bgezal 0x04110000 */
18238 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18239 insn
^= 0x00010000;
18243 /* beq 0x10000000 bne 0x14000000
18244 blez 0x18000000 bgtz 0x1c000000 */
18245 insn
^= 0x04000000;
18253 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18255 /* Clear the and-link bit. */
18256 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18258 /* bltzal 0x04100000 bgezal 0x04110000
18259 bltzall 0x04120000 bgezall 0x04130000 */
18260 insn
&= ~0x00100000;
18263 /* Branch over the branch (if the branch was likely) or the
18264 full jump (not likely case). Compute the offset from the
18265 current instruction to branch to. */
18266 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18270 /* How many bytes in instructions we've already emitted? */
18271 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18272 /* How many bytes in instructions from here to the end? */
18273 i
= fragp
->fr_var
- i
;
18275 /* Convert to instruction count. */
18277 /* Branch counts from the next instruction. */
18280 /* Branch over the jump. */
18281 buf
= write_insn (buf
, insn
);
18284 buf
= write_insn (buf
, 0);
18286 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18288 /* beql $0, $0, 2f */
18290 /* Compute the PC offset from the current instruction to
18291 the end of the variable frag. */
18292 /* How many bytes in instructions we've already emitted? */
18293 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18294 /* How many bytes in instructions from here to the end? */
18295 i
= fragp
->fr_var
- i
;
18296 /* Convert to instruction count. */
18298 /* Don't decrement i, because we want to branch over the
18302 buf
= write_insn (buf
, insn
);
18303 buf
= write_insn (buf
, 0);
18307 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18310 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18311 ? 0x0c000000 : 0x08000000);
18313 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18314 fragp
->fr_symbol
, fragp
->fr_offset
,
18315 FALSE
, BFD_RELOC_MIPS_JMP
);
18316 fixp
->fx_file
= fragp
->fr_file
;
18317 fixp
->fx_line
= fragp
->fr_line
;
18319 buf
= write_insn (buf
, insn
);
18323 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18325 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18326 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18327 insn
|= at
<< OP_SH_RT
;
18329 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18330 fragp
->fr_symbol
, fragp
->fr_offset
,
18331 FALSE
, BFD_RELOC_MIPS_GOT16
);
18332 fixp
->fx_file
= fragp
->fr_file
;
18333 fixp
->fx_line
= fragp
->fr_line
;
18335 buf
= write_insn (buf
, insn
);
18337 if (mips_opts
.isa
== ISA_MIPS1
)
18339 buf
= write_insn (buf
, 0);
18341 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18342 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18343 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18345 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18346 fragp
->fr_symbol
, fragp
->fr_offset
,
18347 FALSE
, BFD_RELOC_LO16
);
18348 fixp
->fx_file
= fragp
->fr_file
;
18349 fixp
->fx_line
= fragp
->fr_line
;
18351 buf
= write_insn (buf
, insn
);
18354 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18358 insn
|= at
<< OP_SH_RS
;
18360 buf
= write_insn (buf
, insn
);
18364 fragp
->fr_fix
+= fragp
->fr_var
;
18365 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18369 /* Relax microMIPS branches. */
18370 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18372 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18373 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18374 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18375 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18376 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18377 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18378 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18379 bfd_boolean short_ds
;
18380 unsigned long insn
;
18383 fragp
->fr_fix
+= fragp
->fr_var
;
18385 /* Handle 16-bit branches that fit or are forced to fit. */
18386 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18388 /* We generate a fixup instead of applying it right now,
18389 because if there is linker relaxation, we're going to
18390 need the relocations. */
18394 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18395 fragp
->fr_symbol
, fragp
->fr_offset
,
18396 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18399 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18400 fragp
->fr_symbol
, fragp
->fr_offset
,
18401 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18407 fixp
->fx_file
= fragp
->fr_file
;
18408 fixp
->fx_line
= fragp
->fr_line
;
18410 /* These relocations can have an addend that won't fit in
18412 fixp
->fx_no_overflow
= 1;
18417 /* Handle 32-bit branches that fit or are forced to fit. */
18418 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18419 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18421 /* We generate a fixup instead of applying it right now,
18422 because if there is linker relaxation, we're going to
18423 need the relocations. */
18424 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18425 fragp
->fr_symbol
, fragp
->fr_offset
,
18426 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18427 fixp
->fx_file
= fragp
->fr_file
;
18428 fixp
->fx_line
= fragp
->fr_line
;
18432 insn
= read_compressed_insn (buf
, 4);
18437 /* Check the short-delay-slot bit. */
18438 if (!al
|| (insn
& 0x02000000) != 0)
18439 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18441 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18444 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18449 /* Relax 16-bit branches to 32-bit branches. */
18452 insn
= read_compressed_insn (buf
, 2);
18454 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18455 insn
= 0x94000000; /* beq */
18456 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18458 unsigned long regno
;
18460 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18461 regno
= micromips_to_32_reg_d_map
[regno
];
18462 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18463 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18468 /* Nothing else to do, just write it out. */
18469 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18470 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18472 buf
= write_compressed_insn (buf
, insn
, 4);
18474 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18475 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18480 insn
= read_compressed_insn (buf
, 4);
18482 /* Relax 32-bit branches to a sequence of instructions. */
18483 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18484 _("relaxed out-of-range branch into a jump"));
18486 /* Set the short-delay-slot bit. */
18487 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18489 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18493 /* Reverse the branch. */
18494 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18495 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18496 insn
^= 0x20000000;
18497 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18498 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18499 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18500 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18501 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18502 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18503 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18504 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18505 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18506 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18507 insn
^= 0x00400000;
18508 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18509 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18510 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18511 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18512 insn
^= 0x00200000;
18513 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18515 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18517 insn
^= 0x00800000;
18523 /* Clear the and-link and short-delay-slot bits. */
18524 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18526 /* bltzal 0x40200000 bgezal 0x40600000 */
18527 /* bltzals 0x42200000 bgezals 0x42600000 */
18528 insn
&= ~0x02200000;
18531 /* Make a label at the end for use with the branch. */
18532 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18533 micromips_label_inc ();
18534 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18537 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18538 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18539 fixp
->fx_file
= fragp
->fr_file
;
18540 fixp
->fx_line
= fragp
->fr_line
;
18542 /* Branch over the jump. */
18543 buf
= write_compressed_insn (buf
, insn
, 4);
18549 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18551 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18557 unsigned long jal
= (short_ds
|| nods
18558 ? 0x74000000 : 0xf4000000); /* jal/s */
18560 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18561 insn
= al
? jal
: 0xd4000000;
18563 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18564 fragp
->fr_symbol
, fragp
->fr_offset
,
18565 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18566 fixp
->fx_file
= fragp
->fr_file
;
18567 fixp
->fx_line
= fragp
->fr_line
;
18569 buf
= write_compressed_insn (buf
, insn
, 4);
18571 if (compact
|| nods
)
18575 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18577 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18582 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18584 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18585 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18586 insn
|= at
<< MICROMIPSOP_SH_RT
;
18588 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18589 fragp
->fr_symbol
, fragp
->fr_offset
,
18590 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18591 fixp
->fx_file
= fragp
->fr_file
;
18592 fixp
->fx_line
= fragp
->fr_line
;
18594 buf
= write_compressed_insn (buf
, insn
, 4);
18596 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18597 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18598 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18600 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18601 fragp
->fr_symbol
, fragp
->fr_offset
,
18602 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18603 fixp
->fx_file
= fragp
->fr_file
;
18604 fixp
->fx_line
= fragp
->fr_line
;
18606 buf
= write_compressed_insn (buf
, insn
, 4);
18611 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18612 insn
|= at
<< MICROMIPSOP_SH_RS
;
18614 buf
= write_compressed_insn (buf
, insn
, 4);
18616 if (compact
|| nods
)
18618 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18622 /* jr/jrc/jalr/jalrs $at */
18623 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18624 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18626 insn
= al
? jalr
: jr
;
18627 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18629 buf
= write_compressed_insn (buf
, insn
, 2);
18634 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18636 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18641 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18645 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18648 const struct mips_int_operand
*operand
;
18651 unsigned int user_length
;
18652 bfd_boolean need_reloc
;
18653 unsigned long insn
;
18658 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18659 operand
= mips16_immed_operand (type
, FALSE
);
18661 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18662 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18663 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18665 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18666 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18667 || (operand
->root
.type
== OP_PCREL
&& !mac
18669 : !bfd_is_abs_section (symsec
)));
18671 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18673 const struct mips_pcrel_operand
*pcrel_op
;
18675 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18677 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18679 if (!mips_ignore_branch_isa
18680 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18681 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18682 _("branch to a symbol in another ISA mode"));
18683 else if ((fragp
->fr_offset
& 0x1) != 0)
18684 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18685 _("branch to misaligned address (0x%lx)"),
18689 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18691 /* Make sure the section winds up with the alignment we have
18693 if (operand
->shift
> 0)
18694 record_alignment (asec
, operand
->shift
);
18697 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18698 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18701 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18702 _("macro instruction expanded into multiple "
18703 "instructions in a branch delay slot"));
18705 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18706 _("extended instruction in a branch delay slot"));
18708 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18709 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18710 _("macro instruction expanded into multiple "
18713 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18715 insn
= read_compressed_insn (buf
, 2);
18717 insn
|= MIPS16_EXTEND
;
18719 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18721 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18733 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18734 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18736 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
18742 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18744 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18745 fragp
->fr_symbol
, fragp
->fr_offset
,
18746 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18747 fixp
->fx_file
= fragp
->fr_file
;
18748 fixp
->fx_line
= fragp
->fr_line
;
18750 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
18751 fragp
->fr_symbol
, fragp
->fr_offset
,
18752 FALSE
, BFD_RELOC_MIPS16_LO16
);
18753 fixp
->fx_file
= fragp
->fr_file
;
18754 fixp
->fx_line
= fragp
->fr_line
;
18759 switch (insn
& 0xf800)
18761 case 0x0800: /* ADDIU */
18762 reg
= (insn
>> 8) & 0x7;
18763 op
= 0xf0004800 | (reg
<< 8);
18765 case 0xb000: /* LW */
18766 reg
= (insn
>> 8) & 0x7;
18767 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18769 case 0xf800: /* I64 */
18770 reg
= (insn
>> 5) & 0x7;
18771 switch (insn
& 0x0700)
18773 case 0x0400: /* LD */
18774 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18776 case 0x0600: /* DADDIU */
18777 op
= 0xf000fd00 | (reg
<< 5);
18787 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
18788 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18789 buf
= write_compressed_insn (buf
, new, 4);
18792 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18793 buf
= write_compressed_insn (buf
, new, 4);
18795 op
|= mips16_immed_extend (val
, 16);
18796 buf
= write_compressed_insn (buf
, op
, 4);
18798 fragp
->fr_fix
+= e2
? 8 : 12;
18802 unsigned int length
= ext
? 4 : 2;
18806 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18813 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18818 if (mac
|| reloc
== BFD_RELOC_NONE
)
18819 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18820 _("unsupported relocation"));
18823 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18824 fragp
->fr_symbol
, fragp
->fr_offset
,
18826 fixp
->fx_file
= fragp
->fr_file
;
18827 fixp
->fx_line
= fragp
->fr_line
;
18830 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18831 _("invalid unextended operand value"));
18834 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18835 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18837 gas_assert (mips16_opcode_length (insn
) == length
);
18838 write_compressed_insn (buf
, insn
, length
);
18839 fragp
->fr_fix
+= length
;
18844 relax_substateT subtype
= fragp
->fr_subtype
;
18845 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18846 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18850 first
= RELAX_FIRST (subtype
);
18851 second
= RELAX_SECOND (subtype
);
18852 fixp
= (fixS
*) fragp
->fr_opcode
;
18854 /* If the delay slot chosen does not match the size of the instruction,
18855 then emit a warning. */
18856 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18857 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18862 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18863 | RELAX_DELAY_SLOT_SIZE_FIRST
18864 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18865 msg
= macro_warning (s
);
18867 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18871 /* Possibly emit a warning if we've chosen the longer option. */
18872 if (use_second
== second_longer
)
18878 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18879 msg
= macro_warning (s
);
18881 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18885 /* Go through all the fixups for the first sequence. Disable them
18886 (by marking them as done) if we're going to use the second
18887 sequence instead. */
18889 && fixp
->fx_frag
== fragp
18890 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18892 if (subtype
& RELAX_USE_SECOND
)
18894 fixp
= fixp
->fx_next
;
18897 /* Go through the fixups for the second sequence. Disable them if
18898 we're going to use the first sequence, otherwise adjust their
18899 addresses to account for the relaxation. */
18900 while (fixp
&& fixp
->fx_frag
== fragp
)
18902 if (subtype
& RELAX_USE_SECOND
)
18903 fixp
->fx_where
-= first
;
18906 fixp
= fixp
->fx_next
;
18909 /* Now modify the frag contents. */
18910 if (subtype
& RELAX_USE_SECOND
)
18914 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18915 memmove (start
, start
+ first
, second
);
18916 fragp
->fr_fix
-= first
;
18919 fragp
->fr_fix
-= second
;
18923 /* This function is called after the relocs have been generated.
18924 We've been storing mips16 text labels as odd. Here we convert them
18925 back to even for the convenience of the debugger. */
18928 mips_frob_file_after_relocs (void)
18931 unsigned int count
, i
;
18933 syms
= bfd_get_outsymbols (stdoutput
);
18934 count
= bfd_get_symcount (stdoutput
);
18935 for (i
= 0; i
< count
; i
++, syms
++)
18936 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18937 && ((*syms
)->value
& 1) != 0)
18939 (*syms
)->value
&= ~1;
18940 /* If the symbol has an odd size, it was probably computed
18941 incorrectly, so adjust that as well. */
18942 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18943 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18947 /* This function is called whenever a label is defined, including fake
18948 labels instantiated off the dot special symbol. It is used when
18949 handling branch delays; if a branch has a label, we assume we cannot
18950 move it. This also bumps the value of the symbol by 1 in compressed
18954 mips_record_label (symbolS
*sym
)
18956 segment_info_type
*si
= seg_info (now_seg
);
18957 struct insn_label_list
*l
;
18959 if (free_insn_labels
== NULL
)
18960 l
= XNEW (struct insn_label_list
);
18963 l
= free_insn_labels
;
18964 free_insn_labels
= l
->next
;
18968 l
->next
= si
->label_list
;
18969 si
->label_list
= l
;
18972 /* This function is called as tc_frob_label() whenever a label is defined
18973 and adds a DWARF-2 record we only want for true labels. */
18976 mips_define_label (symbolS
*sym
)
18978 mips_record_label (sym
);
18979 dwarf2_emit_label (sym
);
18982 /* This function is called by tc_new_dot_label whenever a new dot symbol
18986 mips_add_dot_label (symbolS
*sym
)
18988 mips_record_label (sym
);
18989 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18990 mips_compressed_mark_label (sym
);
18993 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18994 static unsigned int
18995 mips_convert_ase_flags (int ase
)
18997 unsigned int ext_ases
= 0;
19000 ext_ases
|= AFL_ASE_DSP
;
19001 if (ase
& ASE_DSPR2
)
19002 ext_ases
|= AFL_ASE_DSPR2
;
19003 if (ase
& ASE_DSPR3
)
19004 ext_ases
|= AFL_ASE_DSPR3
;
19006 ext_ases
|= AFL_ASE_EVA
;
19008 ext_ases
|= AFL_ASE_MCU
;
19009 if (ase
& ASE_MDMX
)
19010 ext_ases
|= AFL_ASE_MDMX
;
19011 if (ase
& ASE_MIPS3D
)
19012 ext_ases
|= AFL_ASE_MIPS3D
;
19014 ext_ases
|= AFL_ASE_MT
;
19015 if (ase
& ASE_SMARTMIPS
)
19016 ext_ases
|= AFL_ASE_SMARTMIPS
;
19017 if (ase
& ASE_VIRT
)
19018 ext_ases
|= AFL_ASE_VIRT
;
19020 ext_ases
|= AFL_ASE_MSA
;
19022 ext_ases
|= AFL_ASE_XPA
;
19023 if (ase
& ASE_MIPS16E2
)
19024 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19026 ext_ases
|= AFL_ASE_CRC
;
19027 if (ase
& ASE_GINV
)
19028 ext_ases
|= AFL_ASE_GINV
;
19029 if (ase
& ASE_LOONGSON_MMI
)
19030 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19034 /* Some special processing for a MIPS ELF file. */
19037 mips_elf_final_processing (void)
19040 Elf_Internal_ABIFlags_v0 flags
;
19044 switch (file_mips_opts
.isa
)
19047 flags
.isa_level
= 1;
19050 flags
.isa_level
= 2;
19053 flags
.isa_level
= 3;
19056 flags
.isa_level
= 4;
19059 flags
.isa_level
= 5;
19062 flags
.isa_level
= 32;
19066 flags
.isa_level
= 32;
19070 flags
.isa_level
= 32;
19074 flags
.isa_level
= 32;
19078 flags
.isa_level
= 32;
19082 flags
.isa_level
= 64;
19086 flags
.isa_level
= 64;
19090 flags
.isa_level
= 64;
19094 flags
.isa_level
= 64;
19098 flags
.isa_level
= 64;
19103 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19104 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19105 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19106 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19108 flags
.cpr2_size
= AFL_REG_NONE
;
19109 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19110 Tag_GNU_MIPS_ABI_FP
);
19111 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19112 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19113 if (file_ase_mips16
)
19114 flags
.ases
|= AFL_ASE_MIPS16
;
19115 if (file_ase_micromips
)
19116 flags
.ases
|= AFL_ASE_MICROMIPS
;
19118 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19119 || file_mips_opts
.fp
== 64)
19120 && file_mips_opts
.oddspreg
)
19121 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19124 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19125 ((Elf_External_ABIFlags_v0
*)
19128 /* Write out the register information. */
19129 if (mips_abi
!= N64_ABI
)
19133 s
.ri_gprmask
= mips_gprmask
;
19134 s
.ri_cprmask
[0] = mips_cprmask
[0];
19135 s
.ri_cprmask
[1] = mips_cprmask
[1];
19136 s
.ri_cprmask
[2] = mips_cprmask
[2];
19137 s
.ri_cprmask
[3] = mips_cprmask
[3];
19138 /* The gp_value field is set by the MIPS ELF backend. */
19140 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19141 ((Elf32_External_RegInfo
*)
19142 mips_regmask_frag
));
19146 Elf64_Internal_RegInfo s
;
19148 s
.ri_gprmask
= mips_gprmask
;
19150 s
.ri_cprmask
[0] = mips_cprmask
[0];
19151 s
.ri_cprmask
[1] = mips_cprmask
[1];
19152 s
.ri_cprmask
[2] = mips_cprmask
[2];
19153 s
.ri_cprmask
[3] = mips_cprmask
[3];
19154 /* The gp_value field is set by the MIPS ELF backend. */
19156 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19157 ((Elf64_External_RegInfo
*)
19158 mips_regmask_frag
));
19161 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19162 sort of BFD interface for this. */
19163 if (mips_any_noreorder
)
19164 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19165 if (mips_pic
!= NO_PIC
)
19167 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19168 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19171 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19173 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19174 defined at present; this might need to change in future. */
19175 if (file_ase_mips16
)
19176 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19177 if (file_ase_micromips
)
19178 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19179 if (file_mips_opts
.ase
& ASE_MDMX
)
19180 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19182 /* Set the MIPS ELF ABI flags. */
19183 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19184 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19185 else if (mips_abi
== O64_ABI
)
19186 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19187 else if (mips_abi
== EABI_ABI
)
19189 if (file_mips_opts
.gp
== 64)
19190 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19192 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19195 /* Nothing to do for N32_ABI or N64_ABI. */
19197 if (mips_32bitmode
)
19198 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19200 if (mips_nan2008
== 1)
19201 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19203 /* 32 bit code with 64 bit FP registers. */
19204 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19205 Tag_GNU_MIPS_ABI_FP
);
19206 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19207 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19210 typedef struct proc
{
19212 symbolS
*func_end_sym
;
19213 unsigned long reg_mask
;
19214 unsigned long reg_offset
;
19215 unsigned long fpreg_mask
;
19216 unsigned long fpreg_offset
;
19217 unsigned long frame_offset
;
19218 unsigned long frame_reg
;
19219 unsigned long pc_reg
;
19222 static procS cur_proc
;
19223 static procS
*cur_proc_ptr
;
19224 static int numprocs
;
19226 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19227 as "2", and a normal nop as "0". */
19229 #define NOP_OPCODE_MIPS 0
19230 #define NOP_OPCODE_MIPS16 1
19231 #define NOP_OPCODE_MICROMIPS 2
19234 mips_nop_opcode (void)
19236 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19237 return NOP_OPCODE_MICROMIPS
;
19238 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19239 return NOP_OPCODE_MIPS16
;
19241 return NOP_OPCODE_MIPS
;
19244 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19245 32-bit microMIPS NOPs here (if applicable). */
19248 mips_handle_align (fragS
*fragp
)
19252 int bytes
, size
, excess
;
19255 if (fragp
->fr_type
!= rs_align_code
)
19258 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19260 switch (nop_opcode
)
19262 case NOP_OPCODE_MICROMIPS
:
19263 opcode
= micromips_nop32_insn
.insn_opcode
;
19266 case NOP_OPCODE_MIPS16
:
19267 opcode
= mips16_nop_insn
.insn_opcode
;
19270 case NOP_OPCODE_MIPS
:
19272 opcode
= nop_insn
.insn_opcode
;
19277 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19278 excess
= bytes
% size
;
19280 /* Handle the leading part if we're not inserting a whole number of
19281 instructions, and make it the end of the fixed part of the frag.
19282 Try to fit in a short microMIPS NOP if applicable and possible,
19283 and use zeroes otherwise. */
19284 gas_assert (excess
< 4);
19285 fragp
->fr_fix
+= excess
;
19290 /* Fall through. */
19292 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19294 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19298 /* Fall through. */
19301 /* Fall through. */
19306 md_number_to_chars (p
, opcode
, size
);
19307 fragp
->fr_var
= size
;
19316 if (*input_line_pointer
== '-')
19318 ++input_line_pointer
;
19321 if (!ISDIGIT (*input_line_pointer
))
19322 as_bad (_("expected simple number"));
19323 if (input_line_pointer
[0] == '0')
19325 if (input_line_pointer
[1] == 'x')
19327 input_line_pointer
+= 2;
19328 while (ISXDIGIT (*input_line_pointer
))
19331 val
|= hex_value (*input_line_pointer
++);
19333 return negative
? -val
: val
;
19337 ++input_line_pointer
;
19338 while (ISDIGIT (*input_line_pointer
))
19341 val
|= *input_line_pointer
++ - '0';
19343 return negative
? -val
: val
;
19346 if (!ISDIGIT (*input_line_pointer
))
19348 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19349 *input_line_pointer
, *input_line_pointer
);
19350 as_warn (_("invalid number"));
19353 while (ISDIGIT (*input_line_pointer
))
19356 val
+= *input_line_pointer
++ - '0';
19358 return negative
? -val
: val
;
19361 /* The .file directive; just like the usual .file directive, but there
19362 is an initial number which is the ECOFF file index. In the non-ECOFF
19363 case .file implies DWARF-2. */
19366 s_mips_file (int x ATTRIBUTE_UNUSED
)
19368 static int first_file_directive
= 0;
19370 if (ECOFF_DEBUGGING
)
19379 filename
= dwarf2_directive_filename ();
19381 /* Versions of GCC up to 3.1 start files with a ".file"
19382 directive even for stabs output. Make sure that this
19383 ".file" is handled. Note that you need a version of GCC
19384 after 3.1 in order to support DWARF-2 on MIPS. */
19385 if (filename
!= NULL
&& ! first_file_directive
)
19387 (void) new_logical_line (filename
, -1);
19388 s_app_file_string (filename
, 0);
19390 first_file_directive
= 1;
19394 /* The .loc directive, implying DWARF-2. */
19397 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19399 if (!ECOFF_DEBUGGING
)
19400 dwarf2_directive_loc (0);
19403 /* The .end directive. */
19406 s_mips_end (int x ATTRIBUTE_UNUSED
)
19410 /* Following functions need their own .frame and .cprestore directives. */
19411 mips_frame_reg_valid
= 0;
19412 mips_cprestore_valid
= 0;
19414 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19417 demand_empty_rest_of_line ();
19422 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19423 as_warn (_(".end not in text section"));
19427 as_warn (_(".end directive without a preceding .ent directive"));
19428 demand_empty_rest_of_line ();
19434 gas_assert (S_GET_NAME (p
));
19435 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19436 as_warn (_(".end symbol does not match .ent symbol"));
19438 if (debug_type
== DEBUG_STABS
)
19439 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19443 as_warn (_(".end directive missing or unknown symbol"));
19445 /* Create an expression to calculate the size of the function. */
19446 if (p
&& cur_proc_ptr
)
19448 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19449 expressionS
*exp
= XNEW (expressionS
);
19452 exp
->X_op
= O_subtract
;
19453 exp
->X_add_symbol
= symbol_temp_new_now ();
19454 exp
->X_op_symbol
= p
;
19455 exp
->X_add_number
= 0;
19457 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19460 #ifdef md_flush_pending_output
19461 md_flush_pending_output ();
19464 /* Generate a .pdr section. */
19465 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19467 segT saved_seg
= now_seg
;
19468 subsegT saved_subseg
= now_subseg
;
19472 gas_assert (pdr_seg
);
19473 subseg_set (pdr_seg
, 0);
19475 /* Write the symbol. */
19476 exp
.X_op
= O_symbol
;
19477 exp
.X_add_symbol
= p
;
19478 exp
.X_add_number
= 0;
19479 emit_expr (&exp
, 4);
19481 fragp
= frag_more (7 * 4);
19483 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19484 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19485 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19486 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19487 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19488 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19489 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19491 subseg_set (saved_seg
, saved_subseg
);
19494 cur_proc_ptr
= NULL
;
19497 /* The .aent and .ent directives. */
19500 s_mips_ent (int aent
)
19504 symbolP
= get_symbol ();
19505 if (*input_line_pointer
== ',')
19506 ++input_line_pointer
;
19507 SKIP_WHITESPACE ();
19508 if (ISDIGIT (*input_line_pointer
)
19509 || *input_line_pointer
== '-')
19512 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19513 as_warn (_(".ent or .aent not in text section"));
19515 if (!aent
&& cur_proc_ptr
)
19516 as_warn (_("missing .end"));
19520 /* This function needs its own .frame and .cprestore directives. */
19521 mips_frame_reg_valid
= 0;
19522 mips_cprestore_valid
= 0;
19524 cur_proc_ptr
= &cur_proc
;
19525 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19527 cur_proc_ptr
->func_sym
= symbolP
;
19531 if (debug_type
== DEBUG_STABS
)
19532 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19533 S_GET_NAME (symbolP
));
19536 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19538 demand_empty_rest_of_line ();
19541 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19542 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19543 s_mips_frame is used so that we can set the PDR information correctly.
19544 We can't use the ecoff routines because they make reference to the ecoff
19545 symbol table (in the mdebug section). */
19548 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19550 if (ECOFF_DEBUGGING
)
19556 if (cur_proc_ptr
== (procS
*) NULL
)
19558 as_warn (_(".frame outside of .ent"));
19559 demand_empty_rest_of_line ();
19563 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19565 SKIP_WHITESPACE ();
19566 if (*input_line_pointer
++ != ','
19567 || get_absolute_expression_and_terminator (&val
) != ',')
19569 as_warn (_("bad .frame directive"));
19570 --input_line_pointer
;
19571 demand_empty_rest_of_line ();
19575 cur_proc_ptr
->frame_offset
= val
;
19576 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19578 demand_empty_rest_of_line ();
19582 /* The .fmask and .mask directives. If the mdebug section is present
19583 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19584 embedded targets, s_mips_mask is used so that we can set the PDR
19585 information correctly. We can't use the ecoff routines because they
19586 make reference to the ecoff symbol table (in the mdebug section). */
19589 s_mips_mask (int reg_type
)
19591 if (ECOFF_DEBUGGING
)
19592 s_ignore (reg_type
);
19597 if (cur_proc_ptr
== (procS
*) NULL
)
19599 as_warn (_(".mask/.fmask outside of .ent"));
19600 demand_empty_rest_of_line ();
19604 if (get_absolute_expression_and_terminator (&mask
) != ',')
19606 as_warn (_("bad .mask/.fmask directive"));
19607 --input_line_pointer
;
19608 demand_empty_rest_of_line ();
19612 off
= get_absolute_expression ();
19614 if (reg_type
== 'F')
19616 cur_proc_ptr
->fpreg_mask
= mask
;
19617 cur_proc_ptr
->fpreg_offset
= off
;
19621 cur_proc_ptr
->reg_mask
= mask
;
19622 cur_proc_ptr
->reg_offset
= off
;
19625 demand_empty_rest_of_line ();
19629 /* A table describing all the processors gas knows about. Names are
19630 matched in the order listed.
19632 To ease comparison, please keep this table in the same order as
19633 gcc's mips_cpu_info_table[]. */
19634 static const struct mips_cpu_info mips_cpu_info_table
[] =
19636 /* Entries for generic ISAs */
19637 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19638 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19639 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19640 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19641 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19642 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19643 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19644 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19645 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19646 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19647 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19648 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19649 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19650 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19651 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19654 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19655 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19656 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19659 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19662 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19663 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19664 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19665 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19666 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19667 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19668 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19669 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19670 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19671 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19672 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19673 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19674 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19675 /* ST Microelectronics Loongson 2E and 2F cores */
19676 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19677 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
19680 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19681 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19682 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19683 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19684 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19685 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19686 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19687 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19688 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19689 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19690 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19691 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19692 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19693 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19694 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19697 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19698 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19699 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19700 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19702 /* MIPS 32 Release 2 */
19703 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19704 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19705 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19706 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19707 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19708 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19709 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19710 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19711 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19712 ISA_MIPS32R2
, CPU_MIPS32R2
},
19713 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19714 ISA_MIPS32R2
, CPU_MIPS32R2
},
19715 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19716 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19717 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19718 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19719 /* Deprecated forms of the above. */
19720 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19721 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19722 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19723 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19724 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19725 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19726 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19727 /* Deprecated forms of the above. */
19728 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19729 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19730 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19731 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19732 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19733 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19734 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19735 /* Deprecated forms of the above. */
19736 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19737 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19738 /* 34Kn is a 34kc without DSP. */
19739 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19740 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19741 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19742 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19743 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19744 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19745 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19746 /* Deprecated forms of the above. */
19747 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19748 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19749 /* 1004K cores are multiprocessor versions of the 34K. */
19750 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19751 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19752 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19753 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19754 /* interaptiv is the new name for 1004kf */
19755 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19756 { "interaptiv-mr2", 0,
19757 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
19758 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
19760 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19761 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19762 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19763 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19766 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19767 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19768 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19769 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19771 /* Broadcom SB-1 CPU core */
19772 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19773 /* Broadcom SB-1A CPU core */
19774 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19776 { "loongson3a", 0, ASE_LOONGSON_MMI
, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
19778 /* MIPS 64 Release 2 */
19780 /* Cavium Networks Octeon CPU core */
19781 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19782 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19783 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19784 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19787 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19790 XLP is mostly like XLR, with the prominent exception that it is
19791 MIPS64R2 rather than MIPS64. */
19792 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19794 /* MIPS 64 Release 6 */
19795 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19796 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19799 { NULL
, 0, 0, 0, 0 }
19803 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19804 with a final "000" replaced by "k". Ignore case.
19806 Note: this function is shared between GCC and GAS. */
19809 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19811 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19812 given
++, canonical
++;
19814 return ((*given
== 0 && *canonical
== 0)
19815 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19819 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19820 CPU name. We've traditionally allowed a lot of variation here.
19822 Note: this function is shared between GCC and GAS. */
19825 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19827 /* First see if the name matches exactly, or with a final "000"
19828 turned into "k". */
19829 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19832 /* If not, try comparing based on numerical designation alone.
19833 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19834 if (TOLOWER (*given
) == 'r')
19836 if (!ISDIGIT (*given
))
19839 /* Skip over some well-known prefixes in the canonical name,
19840 hoping to find a number there too. */
19841 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19843 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19845 else if (TOLOWER (canonical
[0]) == 'r')
19848 return mips_strict_matching_cpu_name_p (canonical
, given
);
19852 /* Parse an option that takes the name of a processor as its argument.
19853 OPTION is the name of the option and CPU_STRING is the argument.
19854 Return the corresponding processor enumeration if the CPU_STRING is
19855 recognized, otherwise report an error and return null.
19857 A similar function exists in GCC. */
19859 static const struct mips_cpu_info
*
19860 mips_parse_cpu (const char *option
, const char *cpu_string
)
19862 const struct mips_cpu_info
*p
;
19864 /* 'from-abi' selects the most compatible architecture for the given
19865 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19866 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19867 version. Look first at the -mgp options, if given, otherwise base
19868 the choice on MIPS_DEFAULT_64BIT.
19870 Treat NO_ABI like the EABIs. One reason to do this is that the
19871 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19872 architecture. This code picks MIPS I for 'mips' and MIPS III for
19873 'mips64', just as we did in the days before 'from-abi'. */
19874 if (strcasecmp (cpu_string
, "from-abi") == 0)
19876 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19877 return mips_cpu_info_from_isa (ISA_MIPS1
);
19879 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19880 return mips_cpu_info_from_isa (ISA_MIPS3
);
19882 if (file_mips_opts
.gp
>= 0)
19883 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19884 ? ISA_MIPS1
: ISA_MIPS3
);
19886 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19891 /* 'default' has traditionally been a no-op. Probably not very useful. */
19892 if (strcasecmp (cpu_string
, "default") == 0)
19895 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19896 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19899 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19903 /* Return the canonical processor information for ISA (a member of the
19904 ISA_MIPS* enumeration). */
19906 static const struct mips_cpu_info
*
19907 mips_cpu_info_from_isa (int isa
)
19911 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19912 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19913 && isa
== mips_cpu_info_table
[i
].isa
)
19914 return (&mips_cpu_info_table
[i
]);
19919 static const struct mips_cpu_info
*
19920 mips_cpu_info_from_arch (int arch
)
19924 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19925 if (arch
== mips_cpu_info_table
[i
].cpu
)
19926 return (&mips_cpu_info_table
[i
]);
19932 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19936 fprintf (stream
, "%24s", "");
19941 fprintf (stream
, ", ");
19945 if (*col_p
+ strlen (string
) > 72)
19947 fprintf (stream
, "\n%24s", "");
19951 fprintf (stream
, "%s", string
);
19952 *col_p
+= strlen (string
);
19958 md_show_usage (FILE *stream
)
19963 fprintf (stream
, _("\
19965 -EB generate big endian output\n\
19966 -EL generate little endian output\n\
19967 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19968 -G NUM allow referencing objects up to NUM bytes\n\
19969 implicitly with the gp register [default 8]\n"));
19970 fprintf (stream
, _("\
19971 -mips1 generate MIPS ISA I instructions\n\
19972 -mips2 generate MIPS ISA II instructions\n\
19973 -mips3 generate MIPS ISA III instructions\n\
19974 -mips4 generate MIPS ISA IV instructions\n\
19975 -mips5 generate MIPS ISA V instructions\n\
19976 -mips32 generate MIPS32 ISA instructions\n\
19977 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19978 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19979 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19980 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19981 -mips64 generate MIPS64 ISA instructions\n\
19982 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19983 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19984 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19985 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19986 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19990 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19991 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19992 show (stream
, "from-abi", &column
, &first
);
19993 fputc ('\n', stream
);
19995 fprintf (stream
, _("\
19996 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19997 -no-mCPU don't generate code specific to CPU.\n\
19998 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20002 show (stream
, "3900", &column
, &first
);
20003 show (stream
, "4010", &column
, &first
);
20004 show (stream
, "4100", &column
, &first
);
20005 show (stream
, "4650", &column
, &first
);
20006 fputc ('\n', stream
);
20008 fprintf (stream
, _("\
20009 -mips16 generate mips16 instructions\n\
20010 -no-mips16 do not generate mips16 instructions\n"));
20011 fprintf (stream
, _("\
20012 -mmips16e2 generate MIPS16e2 instructions\n\
20013 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20014 fprintf (stream
, _("\
20015 -mmicromips generate microMIPS instructions\n\
20016 -mno-micromips do not generate microMIPS instructions\n"));
20017 fprintf (stream
, _("\
20018 -msmartmips generate smartmips instructions\n\
20019 -mno-smartmips do not generate smartmips instructions\n"));
20020 fprintf (stream
, _("\
20021 -mdsp generate DSP instructions\n\
20022 -mno-dsp do not generate DSP instructions\n"));
20023 fprintf (stream
, _("\
20024 -mdspr2 generate DSP R2 instructions\n\
20025 -mno-dspr2 do not generate DSP R2 instructions\n"));
20026 fprintf (stream
, _("\
20027 -mdspr3 generate DSP R3 instructions\n\
20028 -mno-dspr3 do not generate DSP R3 instructions\n"));
20029 fprintf (stream
, _("\
20030 -mmt generate MT instructions\n\
20031 -mno-mt do not generate MT instructions\n"));
20032 fprintf (stream
, _("\
20033 -mmcu generate MCU instructions\n\
20034 -mno-mcu do not generate MCU instructions\n"));
20035 fprintf (stream
, _("\
20036 -mmsa generate MSA instructions\n\
20037 -mno-msa do not generate MSA instructions\n"));
20038 fprintf (stream
, _("\
20039 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20040 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20041 fprintf (stream
, _("\
20042 -mvirt generate Virtualization instructions\n\
20043 -mno-virt do not generate Virtualization instructions\n"));
20044 fprintf (stream
, _("\
20045 -mcrc generate CRC instructions\n\
20046 -mno-crc do not generate CRC instructions\n"));
20047 fprintf (stream
, _("\
20048 -mginv generate Global INValidate (GINV) instructions\n\
20049 -mno-ginv do not generate Global INValidate instructions\n"));
20050 fprintf (stream
, _("\
20051 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20052 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20053 fprintf (stream
, _("\
20054 -minsn32 only generate 32-bit microMIPS instructions\n\
20055 -mno-insn32 generate all microMIPS instructions\n"));
20056 fprintf (stream
, _("\
20057 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20058 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20059 -mfix-vr4120 work around certain VR4120 errata\n\
20060 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20061 -mfix-24k insert a nop after ERET and DERET instructions\n\
20062 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20063 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20064 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20065 -msym32 assume all symbols have 32-bit values\n\
20066 -O0 do not remove unneeded NOPs, do not swap branches\n\
20067 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20068 -O2 remove unneeded NOPs and swap branches\n\
20069 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20070 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20071 fprintf (stream
, _("\
20072 -mhard-float allow floating-point instructions\n\
20073 -msoft-float do not allow floating-point instructions\n\
20074 -msingle-float only allow 32-bit floating-point operations\n\
20075 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20076 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20077 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20078 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20079 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20080 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20084 show (stream
, "legacy", &column
, &first
);
20085 show (stream
, "2008", &column
, &first
);
20087 fputc ('\n', stream
);
20089 fprintf (stream
, _("\
20090 -KPIC, -call_shared generate SVR4 position independent code\n\
20091 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20092 -mvxworks-pic generate VxWorks position independent code\n\
20093 -non_shared do not generate code that can operate with DSOs\n\
20094 -xgot assume a 32 bit GOT\n\
20095 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20096 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20097 position dependent (non shared) code\n\
20098 -mabi=ABI create ABI conformant object file for:\n"));
20102 show (stream
, "32", &column
, &first
);
20103 show (stream
, "o64", &column
, &first
);
20104 show (stream
, "n32", &column
, &first
);
20105 show (stream
, "64", &column
, &first
);
20106 show (stream
, "eabi", &column
, &first
);
20108 fputc ('\n', stream
);
20110 fprintf (stream
, _("\
20111 -32 create o32 ABI object file%s\n"),
20112 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20113 fprintf (stream
, _("\
20114 -n32 create n32 ABI object file%s\n"),
20115 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20116 fprintf (stream
, _("\
20117 -64 create 64 ABI object file%s\n"),
20118 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20123 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20125 if (HAVE_64BIT_SYMBOLS
)
20126 return dwarf2_format_64bit_irix
;
20128 return dwarf2_format_32bit
;
20133 mips_dwarf2_addr_size (void)
20135 if (HAVE_64BIT_OBJECTS
)
20141 /* Standard calling conventions leave the CFA at SP on entry. */
20143 mips_cfi_frame_initial_instructions (void)
20145 cfi_add_CFA_def_cfa_register (SP
);
20149 tc_mips_regname_to_dw2regnum (char *regname
)
20151 unsigned int regnum
= -1;
20154 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20160 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20161 Given a symbolic attribute NAME, return the proper integer value.
20162 Returns -1 if the attribute is not known. */
20165 mips_convert_symbolic_attribute (const char *name
)
20167 static const struct
20172 attribute_table
[] =
20174 #define T(tag) {#tag, tag}
20175 T (Tag_GNU_MIPS_ABI_FP
),
20176 T (Tag_GNU_MIPS_ABI_MSA
),
20184 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20185 if (streq (name
, attribute_table
[i
].name
))
20186 return attribute_table
[i
].tag
;
20194 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20196 mips_emit_delays ();
20198 as_warn (_("missing .end at end of assembly"));
20200 /* Just in case no code was emitted, do the consistency check. */
20201 file_mips_check_options ();
20203 /* Set a floating-point ABI if the user did not. */
20204 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20206 /* Perform consistency checks on the floating-point ABI. */
20207 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20208 Tag_GNU_MIPS_ABI_FP
);
20209 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20210 check_fpabi (fpabi
);
20214 /* Soft-float gets precedence over single-float, the two options should
20215 not be used together so this should not matter. */
20216 if (file_mips_opts
.soft_float
== 1)
20217 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20218 /* Single-float gets precedence over all double_float cases. */
20219 else if (file_mips_opts
.single_float
== 1)
20220 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20223 switch (file_mips_opts
.fp
)
20226 if (file_mips_opts
.gp
== 32)
20227 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20230 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20233 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20234 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20235 else if (file_mips_opts
.gp
== 32)
20236 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20238 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20243 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20244 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20248 /* Returns the relocation type required for a particular CFI encoding. */
20250 bfd_reloc_code_real_type
20251 mips_cfi_reloc_for_encoding (int encoding
)
20253 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20254 return BFD_RELOC_32_PCREL
;
20255 else return BFD_RELOC_NONE
;